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ESP32 Technical Reference Manual Espressif Systems July 5, 2017 About This Manual The ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailed and complete information on how to use the ESP32 memory and peripherals. For pin definition, electrical characteristics and package information, please see the ESP32 Datasheet. Related Resources Additional documentation and other resources about ESP32 can be accessed here: ESP32 Resources. Release Notes Date Version Release notes 2016.08 V1.0 Initial release. 2016.09 V1.1 Added Chapter I2C Controller. Added Chapter PID/MPU/MMU; 2016.11 V1.2 Updated Section IO_MUX and GPIO Matrix Register Summary; Updated Section LED_PWM Register Summary. Added Chapter eFuse Controller; 2016.12 V1.3 Added Chapter RSA Accelerator; Added Chapter Random Number Generator; Updated Section I2C Controller Interrupt and Section I2C Controller Registers. 2017.01 V1.4 2017.03 V1.5 2017.03 V1.6 Added Chapter SPI; Added Chapter UART Controllers. Added Chapter I2S. Added Chapter SD/MMC Host Controller; Added register IO_MUX_PIN_CTRL in Chapter IO_MUX and GPIO Matrix. Added Chapter On-Chip Sensors and Analog Signal Processing; Added Section Audio PLL; 2017.05 V1.7 Updated Section eFuse Controller Register Summary; Updated Sections I2S PDM and LCD MODE; Updated Section Communication Format Supported by GP-SPI Slave. Added register I2S_STATE_REG in Chapter I2S; 2017.06 V1.8 Updated Chapter IO_MUX and GPIO Matrix; Added Chapter ULP Co-processor. 2017.06 V1.9 2017.07 V2.0 Updated Chapter IO_MUX and GPIO Matrix; Added Chapter MCPWM. Added Chapter SDIO Slave. Documentation Change Notification Espressif provides email notifications to keep customers updated on changes to technical documentation. Please subscribe here. Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including liability for infringement of any proprietary rights, relating to the use of information in this document, is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Copyright © 2017 Espressif Inc. All rights reserved. Contents 1 System and Memory 19 1.1 Introduction 19 1.2 Features 19 1.3 Functional Description 21 1.3.1 Address Mapping 21 1.3.2 Embedded Memory 21 1.3.2.1 Internal ROM 0 22 1.3.2.2 Internal ROM 1 22 1.3.2.3 Internal SRAM 0 23 1.3.2.4 Internal SRAM 1 23 1.3.2.5 Internal SRAM 2 24 1.3.2.6 DMA 24 1.3.2.7 RTC FAST Memory 24 1.3.2.8 RTC SLOW Memory 24 1.3.3 External Memory 24 1.3.4 Peripherals 25 1.3.4.1 Asymmetric PID Controller Peripheral 26 1.3.4.2 Non-Contiguous Peripheral Memory Ranges 26 1.3.4.3 Memory Speed 27 2 Interrupt Matrix 28 2.1 Introduction 28 2.2 Features 28 2.3 Functional Description 28 2.3.1 Peripheral Interrupt Source 28 2.3.2 CPU Interrupt 32 2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 32 2.3.4 CPU NMI Interrupt Mask 33 2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 33 3 Reset and Clock 34 3.1 34 3.2 System Reset 3.1.1 Introduction 34 3.1.2 Reset Source 34 System Clock 35 3.2.1 Introduction 35 3.2.2 Clock Source 36 3.2.3 CPU Clock 36 3.2.4 Peripheral Clock 37 3.2.4.1 APB_CLK Source 37 3.2.4.2 REF_TICK Source 38 3.2.4.3 LEDC_SCLK Source 38 3.2.4.4 APLL_SCLK Source 38 3.2.4.5 PLL_D2_CLK Source 38 3.2.4.6 Clock Source Considerations 39 3.2.5 Wi-Fi BT Clock 39 3.2.6 RTC Clock 39 3.2.7 Audio PLL 39 4 IO_MUX and GPIO Matrix 41 4.1 Introduction 41 4.2 Peripheral Input via GPIO Matrix 42 4.3 4.4 4.5 4.2.1 Summary 42 4.2.2 Functional Description 42 4.2.3 Simple GPIO Input 43 Peripheral Output via GPIO Matrix 43 4.3.1 Summary 43 4.3.2 Functional Description 44 4.3.3 Simple GPIO Output 45 Direct I/O via IO_MUX 45 4.4.1 Summary 45 4.4.2 Functional Description 45 RTC IO_MUX for Low Power and Analog I/O 45 4.5.1 Summary 45 4.5.2 Functional Description 46 4.6 Light-sleep Mode Pin Functions 46 4.7 Pad Hold Feature 46 4.8 I/O Pad Power Supply 46 4.8.1 4.9 VDD_SDIO Power Domain Peripheral Signal List 47 47 4.10 IO_MUX Pad List 52 4.11 RTC_MUX Pin List 53 4.12 Register Summary 54 4.13 Registers 58 5 SPI 79 5.1 Overview 79 5.2 SPI Features 79 5.3 GP-SPI 80 5.3.1 GP-SPI Master Mode 80 5.3.2 GP-SPI Slave Mode 81 5.3.2.1 Communication Format Supported by GP-SPI Slave 81 5.3.2.2 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode 81 5.3.3 5.4 5.5 GP-SPI Clock Control 82 82 5.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) 83 5.4.2 GP-SPI Timing 83 Parallel QSPI 5.5.1 5.6 GP-SPI Data Buffer Communication Format of Parallel QSPI GP-SPI Interrupt Hardware 5.6.1 SPI Interrupts 84 85 85 85 5.6.2 DMA Interrupts 86 5.7 Register Summary 86 5.8 Registers 89 6 SDIO Slave 111 6.1 Overview 111 6.2 Features 111 6.3 Functional Description 111 6.3.1 SDIO Slave Block Diagram 111 6.3.2 Sending and Receiving Data on SDIO Bus 112 6.3.3 Register Access 112 6.3.4 DMA 113 6.3.5 Packet-Sending/-Receiving Procedure 114 6.3.5.1 Sending Packets to SDIO Host 114 6.3.5.2 Receiving Packets from SDIO Host 115 6.3.6 SDIO Bus Timing 116 6.3.7 Interrupt 117 6.3.7.1 Host Interrupt 117 6.3.7.2 Slave Interrupt 117 6.4 Register Summary 118 6.5 SLC Registers 120 6.6 SLC Host Registers 128 6.7 HINF Registers 141 7 SD/MMC Host Controller 142 7.1 Overview 142 7.2 Features 142 7.3 SD/MMC External Interface Signals 142 7.4 Functional Description 143 7.4.1 SD/MMC Host Controller Architecture 143 7.4.1.1 BIU 144 7.4.1.2 CIU 144 7.4.2 Command Path 144 7.4.3 Data Path 145 7.4.3.1 Data Transmit Operation 145 7.4.3.2 Data Receive Operation 146 7.5 Software Restrictions for Proper CIU Operation 146 7.6 RAM for Receiving and Sending Data 147 7.6.1 Transmit RAM Module 147 7.6.2 Receive RAM Module 148 7.7 Descriptor Chain 148 7.8 The Structure of a Linked List 148 Initialization 150 7.9 7.9.1 DMAC Initialization 150 7.9.2 DMAC Transmission Initialization 151 7.9.3 DMAC Reception Initialization 151 7.10 Interrupt 152 7.11 Register Summary 152 7.12 Registers 154 8 I2C Controller 174 8.1 Overview 174 8.2 Features 174 8.3 Functional Description 174 8.3.1 Introduction 174 8.3.2 Architecture 175 8.3.3 I2C Bus Timing 176 8.3.4 I2C cmd Structure 176 8.3.5 I2C Master Writes to Slave 177 8.3.6 I2C Master Reads from Slave 179 8.3.7 Interrupts 181 8.4 Register Summary 182 8.5 Registers 184 9 I2S 195 9.1 Overview 195 9.2 Features 196 9.3 The Clock of I2S Module 197 9.4 I2S Mode 197 9.4.1 9.5 9.6 Supported Audio Standards 198 9.4.1.1 Philips Standard 198 9.4.1.2 MSB Alignment Standard 198 9.4.1.3 PCM Standard 199 9.4.2 Module Reset 199 9.4.3 FIFO Operation 199 9.4.4 Sending Data 199 9.4.5 Receiving Data 201 9.4.6 I2S Master/Slave Mode 202 9.4.7 I2S PDM 203 LCD Mode 205 9.5.1 LCD Master Transmitting Mode 205 9.5.2 Camera Slave Receiving Mode 206 9.5.3 ADC/DAC mode 207 I2S Interrupts 208 9.6.1 FIFO Interrupts 208 9.6.2 DMA Interrupts 208 9.7 Register Summary 208 9.8 Registers 210 10 UART Controllers 227 10.1 Overview 227 10.2 UART Features 227 10.3 Functional Description 227 10.3.1 Introduction 227 10.3.2 UART Architecture 228 10.3.3 UART RAM 229 10.3.4 Baud Rate Detection 229 10.3.5 UART Data Frame 229 10.3.6 Flow Control 230 10.3.6.1 Hardware Flow Control 231 10.3.6.2 Software Flow Control 231 10.3.7 UART DMA 232 10.3.8 UART Interrupts 232 10.3.9 UCHI Interrupts 233 10.4 Register Summary 233 10.5 Registers 236 11 LED_PWM 262 11.1 Introduction 262 11.2 Functional Description 262 11.2.1 Architecture 262 11.2.2 Timers 263 11.2.3 Channels 263 11.2.4 Interrupts 264 11.3 Register Summary 264 11.4 Registers 267 12 Remote Controller Peripheral 277 12.1 Introduction 277 12.2 Functional Description 277 12.2.1 RMT Architecture 277 12.2.2 RMT RAM 278 12.2.3 Clock 278 12.2.4 Transmitter 278 12.2.5 Receiver 279 12.2.6 Interrupts 279 12.3 Register Summary 279 12.4 Registers 281 13 MCPWM 286 13.1 Introduction 286 13.2 Features 286 13.3 Submodules 288 13.3.1 Overview 288 13.3.1.1 Prescaler Submodule 288 13.3.1.2 Timer Submodule 288 13.3.1.3 Operator Submodule 289 13.3.1.4 Fault Detection Submodule 291 13.3.1.5 Capture Submodule 291 13.3.2 PWM Timer Submodule 13.3.2.1 Configurations of the PWM Timer Submodule 291 291 13.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 292 13.3.2.3 PWM Timer Shadow Register 296 13.3.2.4 PWM Timer Synchronization and Phase Locking 296 13.3.3 PWM Operator Submodule 296 13.3.3.1 PWM Generator Submodule 297 13.3.3.2 Dead Time Generator Submodule 307 13.3.3.3 PWM Carrier Submodule 311 13.3.3.4 Fault Handler Submodule 313 13.3.4 Capture Submodule 315 13.3.4.1 Introduction 315 13.3.4.2 Capture Timer 315 13.3.4.3 Capture Channel 315 13.4 Register Summary 316 13.5 Registers 318 14 PULSE_CNT 361 14.1 Introduction 361 14.2 Functional Description 361 14.2.1 Architecture 361 14.2.2 Counter Channel Inputs 361 14.2.3 Watchpoints 362 14.2.4 Examples 363 14.2.5 Interrupts 363 14.3 Register Summary 363 14.4 Registers 365 15 64-bit Timers 369 15.1 Introduction 369 15.2 Functional Description 369 15.2.1 16-bit Prescaler 369 15.2.2 64-bit Time-base Counter 369 15.2.3 Alarm Generation 370 15.2.4 MWDT 370 15.2.5 Interrupts 370 15.3 Register Summary 370 15.4 Registers 372 16 Watchdog Timers 379 16.1 Introduction 379 16.2 Features 379 16.3 Functional Description 379 16.3.1 Clock 379 16.3.1.1 Operating Procedure 380 16.3.1.2 Write Protection 380 16.3.1.3 Flash Boot Protection 380 16.3.1.4 Registers 381 17 eFuse Controller 382 17.1 Introduction 382 17.2 Features 382 17.3 Functional Description 382 17.3.1 Structure 382 17.3.1.1 System Parameter efuse_wr_disable 383 17.3.1.2 System Parameter efuse_rd_disable 384 17.3.1.3 System Parameter coding_scheme 384 17.3.2 Programming of System Parameters 385 17.3.3 Software Reading of System Parameters 388 17.3.4 The Use of System Parameters by Hardware Modules 389 17.3.5 Interrupts 389 17.4 Register Summary 389 17.5 Registers 392 18 AES Accelerator 402 18.1 Introduction 402 18.2 Features 402 18.3 Functional Description 402 18.3.1 AES Algorithm Operations 402 18.3.2 Key, Plaintext and Ciphertext 402 18.3.3 Endianness 403 18.3.4 Encryption and Decryption Operations 405 18.3.5 Speed 405 18.4 Register Summary 405 18.5 Registers 407 19 SHA Accelerator 409 19.1 Introduction 409 19.2 Features 409 19.3 Functional Description 409 19.3.1 Padding and Parsing the Message 409 19.3.2 Message Digest 409 19.3.3 Hash Operation 410 19.3.4 Speed 410 19.4 Register Summary 410 19.5 Registers 412 20 RSA Accelerator 417 20.1 Introduction 417 20.2 Features 417 20.3 Functional Description 417 20.3.1 Initialization 417 20.3.2 Large Number Modular Exponentiation 417 20.3.3 Large Number Modular Multiplication 419 20.3.4 Large Number Multiplication 419 20.4 Register Summary 420 20.5 Registers 421 21 Random Number Generator 423 21.1 Introduction 423 21.2 Feature 423 21.3 Functional Description 423 21.4 Register Summary 423 21.5 Register 423 22 PID/MPU/MMU 424 22.1 Introduction 424 22.2 Features 424 22.3 Functional Description 424 22.3.1 PID Controller 424 22.3.2 MPU/MMU 425 22.3.2.1 Embedded Memory 425 22.3.2.2 External Memory 431 22.3.2.3 Peripheral 437 23 On-Chip Sensors and Analog Signal Processing 439 23.1 Introduction 439 23.2 Capacitive Touch Sensor 439 23.2.1 Introduction 439 23.2.2 Features 439 23.2.3 Available GPIOs 440 23.2.4 Functional Description 440 23.2.5 Touch FSM 441 23.3 SAR ADC 442 23.3.1 Introduction 442 23.3.2 Features 443 23.3.3 Outline of Function 443 23.3.4 RTC SAR ADC Controllers 445 23.3.5 DIG SAR ADC Controllers 446 23.4 Low-Noise Amplifier 448 23.4.1 Introduction 448 23.4.2 Features 448 23.4.3 Overview of Function 448 23.5 Hall Sensor 449 23.5.1 Introduction 449 23.5.2 Features 450 23.5.3 Functional Description 450 23.6 Temperature Sensor 450 23.6.1 Introduction 450 23.6.2 Features 451 23.6.3 Functional Description 451 23.7 DAC 23.7.1 Introduction 451 451 23.7.2 Features 451 23.7.3 Structure 452 23.7.4 Cosine Waveform Generator 452 23.7.5 DMA support 453 23.8 Register Summary 453 23.8.1 Sensors 453 23.8.2 Advanced Peripheral Bus 454 23.8.3 RTC I/O 454 23.9 Registers 455 23.9.1 Sensors 455 23.9.2 Advanced Peripheral Bus 466 23.9.3 RTC I/O 469 24 ULP Co-processor 470 24.1 Introduction 470 24.2 Features 470 24.3 Functional Description 471 24.4 Instruction Set 471 24.4.1 ALU - Perform Arithmetic/Logic Operations 472 24.4.1.1 Operations among Registers 472 24.4.1.2 Operations with Immediate Value 473 24.4.1.3 Operations with Stage Count Register 473 24.4.2 ST – Store Data in Memory 474 24.4.3 LD – Load Data from Memory 474 24.4.4 JUMP – Jump to an Absolute Address 475 24.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) 475 24.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register) 476 24.4.7 HALT – End the Program 476 24.4.8 WAKE – Wake up the Chip 477 24.4.9 Sleep – Set the ULP Timer’s Wake-up Period 477 24.4.10 WAIT – Wait for a Number of Cycles 477 24.4.11 TSENS – Take Measurements with the Temperature Sensor 477 24.4.12 ADC – Take Measurement with ADC 478 24.4.13 I2C_RD/I2C_WR – Read/Write I2C 479 24.4.14 REG_RD – Read from Peripheral Register 479 24.4.15 REG_WR – Write to Peripheral Register 480 24.5 ULP Program Execution 480 24.6 RTC_I2C Controller 482 24.6.1 Configuring RTC_I2C 482 24.6.2 Using RTC_I2C 482 24.6.2.1 I2C_RD - Read a Single Byte 483 24.6.2.2 I2C_WR - Write a Single Byte 483 24.6.2.3 Detecting Error Conditions 484 24.6.2.4 Connecting I2C Signals 484 24.7 Register Summary 484 24.7.1 SENS_ULP Address Space 484 24.7.2 RTC_I2C Address Space 484 24.8 Registers 486 24.8.1 SENS_ULP Address Space 486 24.8.2 RTC_I2C Address Space 488 List of Tables 1 Address Mapping 21 2 Embedded Memory Address Mapping 21 3 Module with DMA 24 4 External Memory Address Mapping 25 5 Peripheral Address Mapping 25 6 PRO_CPU, APP_CPU Interrupt Configuration 30 7 CPU Interrupts 32 8 PRO_CPU and APP_CPU Reset Reason Values 34 9 CPU_CLK Source 36 10 CPU_CLK Derivation 37 11 Peripheral Clock Usage 37 12 APB_CLK Derivation 38 13 REF_TICK Derivation 38 14 LEDC_SCLK Derivation 38 15 IO_MUX Light-sleep Pin Function Registers 46 16 GPIO Matrix Peripheral Signals 47 17 IO_MUX Pad Summary 52 18 RTC_MUX Pin Summary 53 22 SPI Signal and Pin Signal Function Mapping 79 23 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master 83 24 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave 83 29 SD/MMC Signal Description 143 30 DES0 149 31 DES1 150 32 DES2 150 33 DES3 150 36 I2S Signal Bus Description 196 37 Register Configuration 200 38 Send Channel Mode 200 39 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration 202 40 The Register Configuration to Which the Four Modes Correspond 202 41 Upsampling Rate Configuration 203 42 Down-sampling Configuration 205 48 Configuration Parameters of the Operator Submodule 290 49 Timing Events Used in PWM Generator 298 50 Timing Events Priority When PWM Timer Increments 298 51 Timing Events Priority when PWM Timer Decrements 299 52 Dead Time Generator Switches Control Registers 308 53 Typical Dead Time Generator Operating Modes 309 58 System Parameter 382 59 BLOCK1/2/3 Encoding 384 60 Program Register 385 61 Timing Configuration 387 62 Software Read Register 388 64 Operation Mode 402 65 AES Text Endianness 403 66 AES-128 Key Endianness 404 67 AES-192 Key Endianness 404 68 AES-256 Key Endianness 404 73 MPU and MMU Structure for Internal Memory 425 74 MPU for RTC FAST Memory 426 75 MPU for RTC SLOW Memory 426 76 Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2 427 77 Page Boundaries for SRAM0 MMU 428 78 Page Boundaries for SRAM2 MMU 428 79 DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG 429 80 MPU for DMA 430 81 Virtual Address for External Memory 432 82 MMU Entry Numbers for PRO_CPU 432 83 MMU Entry Numbers for APP_CPU 432 84 MMU Entry Numbers for PRO_CPU (Special Mode) 433 85 MMU Entry Numbers for APP_CPU (Special Mode) 433 86 Virtual Address Mode for External SRAM 434 87 Virtual Address for External SRAM ( Normal Mode ) 435 88 Virtual Address for External SRAM ( Low-High Mode ) 435 89 Virtual Address for External SRAM ( Even-Odd Mode ) 435 90 MMU Entry Numbers for External RAM 436 91 MPU for Peripheral 437 92 DPORT_AHBLITE_MPU_TABLE_X_REG 438 93 ESP32 Capacitive Sensing Touch Pads 440 94 Inputs of SAR ADC module 444 95 ESP32 SAR ADC Controllers 445 96 Fields of the Pattern Table Register 447 97 Fields of Type I DMA Data Format 448 98 Fields of Type II DMA Data Format 448 101 ALU Operations among Registers 472 102 ALU Operations with Immediate Value 473 103 ALU Operations with Stage Count Register 474 104 Input Signals Measured using the ADC Instruction 478 List of Figures 1 System Structure 20 2 System Address Mapping 20 3 Interrupt Matrix Structure 28 4 System Reset 34 5 System Clock 35 6 IO_MUX, RTC IO_MUX and GPIO Matrix Overview 41 7 Peripheral Input via IO_MUX, GPIO Matrix 42 8 Output via GPIO Matrix 44 9 ESP32 I/O Pad Power Sources 47 10 SPI Architecture 79 11 SPI Master and Slave Full-duplex Communication 80 12 SPI Data Buffer 82 13 Parallel QSPI 84 14 Communication Format of Parallel QSPI 85 15 SDIO Slave Block Diagram 111 16 SDIO Bus Packet Transmission 112 17 CMD53 Content 112 18 SDIO Slave DMA Linked-List Structure 113 19 SDIO Slave’s Linked List 113 20 Packet Sending Procedure (Initiated by Slave) 114 21 Packet Receiving Procedure (Initiated by Host) 115 22 Loading Receiving Buffer 116 23 Sampling Timing Diagram 116 24 Output Timing Diagram 117 25 SD/MMC Controller Topology 142 26 SD/MMC Controller External Interface Signals 143 27 SDIO Host Block Diagram 143 28 Command Path State Machine 145 29 Data Transmit State Machine 145 30 Data Receive State Machine 146 31 Descriptor Chain 148 32 The Structure of a Linked List 148 33 I2C Master Architecture 175 34 I2C Slave Architecture 175 35 I2C Sequence Chart 176 36 Structure of The I2C Command Register 176 37 I2C Master Writes to Slave with 7-bit Address 177 38 I2C Master Writes to Slave with 10-bit Address 178 39 I2C Master Writes to addrM in RAM of Slave with 7-bit Address 178 40 I2C Master Writes to Slave with 7-bit Address in Two Segments 179 41 I2C Master Reads from Slave with 7-bit Address 179 42 I2C Master Reads from Slave with 10-bit Address 180 43 I2C Master Reads N Bytes of Data from addrM in Slave with 7-bit Address 180 44 I2C Master Reads from Slave with 7-bit Address in Two Segments 181 45 I2S System Block Diagram 195 46 I2S Clock 197 47 Philips Standard 198 48 MSB Alignment Standard 198 49 PCM Standard 199 50 Tx FIFO Data Mode 200 51 The First Stage of Receiving Data 201 52 Modes of Writing Received Data into FIFO 202 53 PDM Transmitting Module 203 54 PDM Sends Signal 204 55 PDM Receives Signal 204 56 PDM Receive Module 204 57 LCD Master Transmitting Mode 205 58 LCD Master Transmitting Data Frame, Form 1 205 59 LCD Master Transmitting Data Frame, Form 2 206 60 Camera Slave Receiving Mode 206 61 ADC Interface of I2S0 207 62 DAC Interface of I2S 207 63 Data Input by I2S DAC Interface 207 64 UART Basic Structure 228 65 UART shared RAM 229 66 UART Data Frame Structure 230 67 AT_CMD Character Format 230 68 Hardware Flow Control 231 69 LED_PWM Architecture 262 70 LED_PWM High-speed Channel Diagram 262 71 LED PWM Output Signal Diagram 263 72 Output Signal Diagram of Gradient Duty Cycle 264 73 RMT Architecture 277 74 Data Structure 278 75 MCPWM Module Overview 286 76 Prescaler Submodule 288 77 Timer Submodule 288 78 Operator Submodule 289 79 Fault Detection Submodule 291 80 Capture Submodule 291 81 Count-Up Mode Waveform 292 82 Count-Down Mode Waveforms 293 83 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 293 84 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 293 85 UTEP and UTEZ Generation in Count-Up Mode 294 86 DTEP and DTEZ Generation in Count-Down Mode 295 87 DTEP and UTEZ Generation in Count-Up-Down Mode 295 88 Submodules Inside the PWM Operator 297 89 Symmetrical Waveform in Count-Up-Down Mode 300 90 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and PWMxB 91 — Active High 301 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 302 92 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High 93 303 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Complementary 304 94 Example of an NCI Software-Force Event on PWMxA 305 95 Example of a CNTU Software-Force Event on PWMxB 306 96 Options for Setting up the Dead Time Generator Submodule 308 97 Active High Complementary (AHC) Dead Time Waveforms 309 98 Active Low Complementary (ALC) Dead Time Waveforms 310 99 Active High (AH) Dead Time Waveforms 310 100 Active Low (AL) Dead Time Waveforms 310 101 Example of Waveforms Showing PWM Carrier Action 312 102 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule 313 103 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 313 104 PULSE_CNT Architecture 361 105 PULSE_CNT Upcounting Diagram 363 106 PULSE_CNT Downcounting Diagram 363 107 MMU Access Example 427 108 Touch Sensor 439 109 Touch Sensor Structure 440 110 Touch Sensor Operating Flow 441 111 Touch FSM Structure 442 112 SAR ADC Depiction 443 113 SAR ADC Outline of Function 444 114 RTC SAR ADC Outline of Function 446 115 Diagram of DIG SAR ADC Controllers 447 116 Structure of Low-Noise Amplifier 448 117 Low-Noise Amplifier – Sequence of Operation 449 118 Hall Sensor 450 119 Temperature Sensor 451 120 Diagram of DAC function 452 121 Cosine Waveform (CW) Generator 453 122 ULP Co-processor Diagram 470 123 The ULP Co-processor Instruction Format 471 124 Instruction Type — ALU for Operations among Registers 472 125 Instruction Type — ALU for Operations with Immediate Value 473 126 Instruction Type — ALU for Operations with Stage Count Register 473 127 Instruction Type — ST 474 128 Instruction Type — LD 474 129 Instruction Type — JUMP 475 130 Instruction Type — JUMPR 475 131 Instruction Type — JUMP 476 132 Instruction Type — HALT 476 133 Instruction Type — WAKE 477 134 Instruction Type — SLEEP 477 135 Instruction Type — WAIT 477 136 Instruction Type — TSENS 477 137 Instruction Type — ADC 478 138 Instruction Type — I2C 479 139 Instruction Type — REG_RD 479 140 Instruction Type — REG_WR 480 141 Control of ULP Program Execution 481 142 Sample of a ULP Operation Sequence 482 143 I2C Read Operation 483 144 I2C Write Operation 484 1. SYSTEM AND MEMORY 1. System and Memory 1.1 Introduction The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs. With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they use the same addresses to access the same memory. Multiple peripherals in the system can access embedded memory via DMA. The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however, for most purposes the two CPUs are interchangeable. 1.2 Features • Address Space – Symmetric address mapping – 4 GB (32-bit) address space for both data bus and instruction bus – 1296 KB embedded memory address space – 19704 KB external memory address space – 512 KB peripheral address space – Some embedded and external memory regions can be accessed by either data bus or instruction bus – 328 KB DMA address space • Embedded Memory – 448 KB Internal ROM – 520 KB Internal SRAM – 8 KB RTC FAST Memory – 8 KB RTC SLOW Memory • External Memory Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the embedded memory can be used as transparent cache for this external memory. – Supports up to 16 MB off-Chip SPI Flash. – Supports up to 8 MB off-Chip SPI SRAM. • Peripherals – 41 peripherals • DMA – 13 modules are capable of DMA operation Espressif Systems 19 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY The block diagram in Figure 1 illustrates the system structure, and the block diagram in Figure 2 illustrates the address map structure. Figure 1: System Structure Figure 2: System Address Mapping Espressif Systems 20 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY 1.3 Functional Description 1.3.1 Address Mapping Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are symmetric between the two CPUs. Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~ 0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are shared by the data and instruction bus. The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access the least significant, second least significant, second most significant, and the most significant bytes of the 32-bit word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or non-aligned byte, half-word and word read-and-write operations. The CPU can read and write data through the instruction bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception. Each CPU can directly access embedded memory through both the data bus and the instruction bus, external memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1 illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus. Some embedded memories and some external memories can be accessed via the data bus or the instruction bus. In these cases, the same memory is available to either of the CPUs at two address ranges. Table 1: Address Mapping Bus Type Boundary Address Size Target Low Address High Address 0x0000_0000 0x3F3F_FFFF Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory 0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Memory Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Memory Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory 0x40C0_0000 0x4FFF_FFFF 244 MB Reserved 0x5000_0000 0x5000_1FFF 8 KB Embedded Memory 0x5000_2000 0xFFFF_FFFF Data Instruction Reserved Reserved 1.3.2 Embedded Memory The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST memory (8 KB) and RTC SLOW memory (8 KB). The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The 520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM. Table 2 lists all embedded memories and their address ranges on the data and instruction buses. Table 2: Embedded Memory Address Mapping Espressif Systems 21 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY Bus Type Boundary Address Size Target Comment 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only 0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved - 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 - 0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved - Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA Size Target Comment Data Data Bus Type Low Address High Address 0x3FF8_0000 Boundary Address Low Address High Address Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 - 0x4006_0000 0x4006_FFFF 64 KB Reserved - Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 - Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 - Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 - Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only Size Target Comment 8 KB RTC SLOW Memory - Bus Type Data Instruction Boundary Address Low Address High Address 0x5000_0000 0x5000_1FFF 1.3.2.1 Internal ROM 0 The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range 0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus. The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order to access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF. While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU, respectively. 1.3.2.2 Internal ROM 1 The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~ 0x3FF9_FFFF of the data bus. Espressif Systems 22 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY 1.3.2.3 Internal SRAM 0 The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses 0x4007_0000 ~ 0x4007_7FFF of the instruction bus. The remaining 128 KB can always be read and written by either CPU at addresses 0x4007_8000 ~ 0x4007_FFFF of instruction bus. 1.3.2.4 Internal SRAM 1 The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses 0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the instruction bus. The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the data bus. That is to say, address 0x3FFE_0000 and 0x400B_FFFC access the same word 0x3FFE_0004 and 0x400B_FFF8 access the same word 0x3FFE_0008 and 0x400B_FFF4 access the same word …… 0x3FFF_FFF4 and 0x400A_0008 access the same word 0x3FFF_FFF8 and 0x400A_0004 access the same word 0x3FFF_FFFC and 0x400A_0000 access the same word The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is not reversed between address spaces. For example, address 0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8. …… 0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000. Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more information. Espressif Systems 23 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY 1.3.2.5 Internal SRAM 2 The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000 ~ 0x3FFD_FFFF on the data bus. 1.3.2.6 DMA DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2. This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2. In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals. Table 3: Module with DMA UART0 UART1 UART2 SPI1 SPI2 SPI3 I2S0 I2S1 SDIO Slave SDMMC EMAC BT WIFI 1.3.2.7 RTC FAST Memory RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of 0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on the instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the APP_CPU. The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses 0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not provide access to RTC FAST Memory or any other memory location. 1.3.2.8 RTC SLOW Memory RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of 0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus. 1.3.3 External Memory The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 4 provides a list of external memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an external physical memory address (in the external memory’s address space), according to the MMU settings. Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM. Espressif Systems 24 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY Table 4: External Memory Address Mapping Bus Type Boundary Address Size Target Comment 0x3F7F_FFFF 4 MB External Flash Read 0x3FBF_FFFF 4 MB External SRAM Read and Write Size Target Comment 11512 KB External Flash Read Low Address High Address Data 0x3F40_0000 Data 0x3F80_0000 Bus Type Instruction Boundary Address Low Address High Address 0x400C_2000 0x40BF_FFFF 1.3.4 Peripherals The ESP32 has 41 peripherals. Table 5 specifically describes the peripherals and their respective address ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single exception; this being the PID Controller. Table 5: Peripheral Address Mapping Bus Type Boundary Address Size Target 0x3FF0_0FFF 4 KB DPort Register 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot 0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table 0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller 0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0 0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1 Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0 Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO 0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX 0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1 0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0 Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1 0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0 Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0 Low Address High Address Data 0x3FF0_0000 Data Data Data Data Espressif Systems 25 Comment Per-CPU peripheral One of three parts ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY Bus Type Boundary Address Size Target Comment 0x3FF5_5FFF 4 KB SDIO Slave One of three parts 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM Data 0x3FF5_A000 0x3FF5_AFFF 4 KB Efuse Controller Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption 0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved Data 0x3FF5_E000 0x3FF5_EFFF 4 KB PWM0 Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0 Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1 0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2 Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3 Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1 Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC 0x3FF6_B000 0x3FF6_BFFF 4 KB Reserved Data 0x3FF6_C000 0x3FF6_CFFF 4 KB PWM1 Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1 Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2 Data 0x3FF6_F000 0x3FF6_FFFF 4 KB PWM2 Data 0x3FF7_0000 0x3FF7_0FFF 4 KB PWM3 0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG 0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved Low Address High Address Data 0x3FF5_5000 Data Data One of three parts 1.3.4.1 Asymmetric PID Controller Peripheral There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart. Each CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller. 1.3.4.2 Non-Contiguous Peripheral Memory Ranges The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~ 3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similarly to other peripherals, access to this peripheral is identical for both CPUs. Espressif Systems 26 ESP32 Technical Reference Manual V2.0 1. SYSTEM AND MEMORY 1.3.4.3 Memory Speed The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory. Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access the SRAM at full speed, provided they access addresses in different memory banks. Espressif Systems 27 ESP32 Technical Reference Manual V2.0 2. INTERRUPT MATRIX 2. Interrupt Matrix 2.1 Introduction The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two CPUs’ peripheral interrupts. This configuration is made to be highly flexible in order to meet many different needs. 2.2 Features • Accepts 71 peripheral interrupt sources as input. • Generates 26 peripheral interrupt sources per CPU as output (52 total). • CPU NMI Interrupt Mask. • Queries current interrupt status of peripheral interrupt sources. The structure of the Interrupt Matrix is shown in Figure 3. Figure 3: Interrupt Matrix Structure 2.3 Functional Description 2.3.1 Peripheral Interrupt Source ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 6. 67 of 71 ESP32 peripheral interrupt sources can be allocated to either CPU. The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and Espressif Systems 28 ESP32 Technical Reference Manual V2.0 2. INTERRUPT MATRIX GPIO_INTERRUPT_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt sources. Espressif Systems 29 ESP32 Technical Reference Manual V2.0 PRO_CPU Configuration Register APP_CPU Peripheral Interrupt Source Peripheral Interrupt Status Register Bit Name No. Name No. Peripheral Interrupt Status Register Name Bit Configuration Register PRO_MAC_INTR_MAP_REG 0 0 MAC_INTR 0 0 APP_MAC_INTR_MAP_REG PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 APP_MAC_NMI_MAP_REG PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 APP_BB_INT_MAP_REG PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 APP_BT_MAC_INT_MAP_REG PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 APP_BT_BB_INT_MAP_REG PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 APP_RWBLE_IRQ_MAP_REG 8 RWBT_NMI 8 APP_RWBT_NMI_MAP_REG PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 APP_RWBLE_NMI_MAP_REG PRO_SLC0_INTR_MAP_REG PRO_RWBT_NMI_MAP_REG 10 8 10 SLC0_INTR 10 8 10 APP_SLC0_INTR_MAP_REG PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 APP_SLC1_INTR_MAP_REG PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 APP_UHCI0_INTR_MAP_REG 13 UHCI1_INTR 13 14 TG_T0_LEVEL_INT 14 PRO_UHCI1_INTR_MAP_REG 13 PRO_TG_T0_LEVEL_INT_MAP_REG 14 PRO_INTR_STATUS_REG_0 APP_INTR_STATUS_REG_0 13 APP_UHCI1_INTR_MAP_REG 14 APP_TG_T0_LEVEL_INT_MAP_REG 30 PRO_TG_T1_LEVEL_INT_MAP_REG 15 15 TG_T1_LEVEL_INT 15 15 APP_TG_T1_LEVEL_INT_MAP_REG PRO_TG_WDT_LEVEL_INT_MAP_REG 16 16 TG_WDT_LEVEL_INT 16 16 APP_TG_WDT_LEVEL_INT_MAP_REG PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 APP_TG_LACT_LEVEL_INT_MAP_REG PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 APP_TG1_T0_LEVEL_INT_MAP_REG PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 APP_TG1_T1_LEVEL_INT_MAP_REG PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 APP_TG1_WDT_LEVEL_INT_MAP_REG TG1_LACT_LEVEL_INT ESP32 Technical Reference Manual V2.0 PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 21 21 APP_TG1_LACT_LEVEL_INT_MAP_REG PRO_GPIO_INTERRUPT_PRO_MAP_REG 22 22 GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP 22 22 APP_GPIO_INTERRUPT_APP_MAP_REG PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG 23 23 GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI 23 23 APP_GPIO_INTERRUPT_APP_NMI_MAP_REG PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 APP_CPU_INTR_FROM_CPU_0_MAP_REG PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 APP_CPU_INTR_FROM_CPU_1_MAP_REG PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 APP_CPU_INTR_FROM_CPU_2_MAP_REG PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 APP_CPU_INTR_FROM_CPU_3_MAP_REG PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 APP_SPI_INTR_0_MAP_REG PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 APP_SPI_INTR_1_MAP_REG PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 APP_SPI_INTR_2_MAP_REG PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 APP_SPI_INTR_3_MAP_REG PRO_I2S0_INT_MAP_REG 0 32 I2S0_INT 32 0 APP_I2S0_INT_MAP_REG PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 APP_I2S1_INT_MAP_REG PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 APP_UART_INTR_MAP_REG PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 APP_UART1_INTR_MAP_REG PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 APP_UART2_INTR_MAP_REG PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 APP_SDIO_HOST_INTERRUPT_MAP_REG PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 APP_EMAC_INT_MAP_REG PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 APP_PWM0_INTR_MAP_REG PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 APP_PWM1_INTR_MAP_REG PRO_PWM2_INTR_MAP_REG 9 41 PWM2_INTR 41 9 APP_PWM2_INTR_MAP_REG PRO_PWM3_INTR_MAP_REG 10 42 PWM3_INTR 42 10 APP_PWM3_INTR_MAP_REG PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 APP_LEDC_INT_MAP_REG PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 APP_EFUSE_INT_MAP_REG PRO_INTR_STATUS_REG_1 APP_INTR_STATUS_REG_1 PRO_CAN_INT_MAP_REG 13 45 CAN_INT 45 13 APP_CAN_INT_MAP_REG PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 APP_RTC_CORE_INTR_MAP_REG PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 APP_PCNT_INTR_MAP_REG PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 APP_I2C_EXT0_INTR_MAP_REG APP_RMT_INTR_MAP_REG PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 APP_I2C_EXT1_INTR_MAP_REG PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 APP_RSA_INTR_MAP_REG PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 APP_SPI1_DMA_INT_MAP_REG 2. INTERRUPT MATRIX Espressif Systems Table 6: PRO_CPU, APP_CPU Interrupt Configuration Configuration Register APP_CPU Peripheral Interrupt Source Status Register Bit Name No. Name No. Peripheral Interrupt Status Register Name Bit Configuration Register PRO_SPI2_DMA_INT_MAP_REG 21 53 SPI2_DMA_INT 53 21 APP_SPI2_DMA_INT_MAP_REG PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 APP_SPI3_DMA_INT_MAP_REG PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 APP_WDG_INT_MAP_REG PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 APP_TIMER_INT1_MAP_REG 57 TIMER_INT2 57 58 TG_T0_EDGE_INT 58 PRO_TIMER_INT2_MAP_REG 25 PRO_TG_T0_EDGE_INT_MAP_REG 26 PRO_INTR_STATUS_REG_1 APP_INTR_STATUS_REG_1 25 APP_TIMER_INT2_MAP_REG 26 APP_TG_T0_EDGE_INT_MAP_REG PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 APP_TG_T1_EDGE_INT_MAP_REG PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 APP_TG_WDT_EDGE_INT_MAP_REG PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 APP_TG_LACT_EDGE_INT_MAP_REG PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 APP_TG1_T0_EDGE_INT_MAP_REG PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 APP_TG1_T1_EDGE_INT_MAP_REG PRO_TG1_WDT_EDGE_INT_MAP_REG 0 64 TG1_WDT_EDGE_INT 64 0 APP_TG1_WDT_EDGE_INT_MAP_REG PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 APP_TG1_LACT_EDGE_INT_MAP_REG PRO_MMU_IA_INT_MAP_REG 2 66 MMU_IA_INT 66 2 APP_MMU_IA_INT_MAP_REG PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 APP_MPU_IA_INT_MAP_REG PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 APP_CACHE_IA_INT_MAP_REG PRO_INTR_STATUS_REG_2 APP_INTR_STATUS_REG_2 2. INTERRUPT MATRIX Espressif Systems PRO_CPU Peripheral Interrupt 31 ESP32 Technical Reference Manual V2.0 2. INTERRUPT MATRIX 2.3.2 CPU Interrupt Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All interrupts in a CPU are listed in Table 7. Table 7: CPU Interrupts No. Category Type Priority Level 0 Peripheral Level-Triggered 1 1 Peripheral Level-Triggered 1 2 Peripheral Level-Triggered 1 3 Peripheral Level-Triggered 1 4 Peripheral Level-Triggered 1 5 Peripheral Level-Triggered 1 6 Internal Timer.0 1 7 Internal Software 1 8 Peripheral Level-Triggered 1 9 Peripheral Level-Triggered 1 10 Peripheral Edge-Triggered 1 11 Internal Profiling 3 12 Peripheral Level-Triggered 1 13 Peripheral Level-Triggered 1 14 Peripheral NMI NMI 15 Internal Timer.1 3 16 Internal Timer.2 5 17 Peripheral Level-Triggered 1 18 Peripheral Level-Triggered 1 19 Peripheral Level-Triggered 2 20 Peripheral Level-Triggered 2 21 Peripheral Level-Triggered 2 22 Peripheral Edge-Triggered 3 23 Peripheral Level-Triggered 3 24 Peripheral Level-Triggered 4 25 Peripheral Level-Triggered 4 26 Peripheral Level-Triggered 5 27 Peripheral Level-Triggered 3 28 Peripheral Edge-Triggered 4 29 Internal Software 3 30 Peripheral Edge-Triggered 4 31 Peripheral Level-Triggered 5 2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU In this section: • Source_X stands for any particular peripheral interrupt source. • PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration Espressif Systems 32 ESP32 Technical Reference Manual V2.0 2. INTERRUPT MATRIX register of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the peripheral interrupt source Source_X. In Table 6 the registers listed under “PRO_CPU (APP_CPU) Peripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources listed in “Peripheral Interrupt Source - Name”. • Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5, 8 ~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31. • Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15, 16, 29. Using this terminology, the possible operations of the Interrupt Matrix controller can be described as follows: • Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU) Set PRO_X_MAP_REG�or APP_X_MAP_REG�to Num_P. Num_P can be any CPU peripheral interrupt number. CPU interrupts can be shared between multiple peripherals (see below). • Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU) Set PRO_X_MAP_REG�or APP_X _MAP_REG�for peripheral interrupt source to any Num_I. The specific choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as Num_I is connected to either CPU. • Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral interrupts will trigger CPU Interrupt_P. 2.3.4 CPU NMI Interrupt Mask The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU’s ( or APP_CPU’s ) NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the peripheral PID Controller, respectively. 2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source The current interrupt status of a peripheral interrupt source can be read via the bit value in PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n), as shown in the mapping in Table 6. Espressif Systems 33 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK 3. Reset and Clock 3.1 System Reset 3.1.1 Introduction The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the RAM. Figure 4 shows the subsystems included in each reset level. Figure 4: System Reset • CPU reset: Only resets the registers of one or both of the CPU cores. • Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC is not reset. • System reset: Resets all the registers on the chip, including those of the RTC. 3.1.2 Reset Source While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able to reset only one of the two cores. The reset reason for each core can be looked up individually: the PRO_CPU reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the APP_CPU in APP_CNTL_RESET_CAUSE_PROCPU. Table 8 shows the possible reset reason values that can be read from these registers. Table 8: PRO_CPU and APP_CPU Reset Reason Values PRO APP Source Reset Type Note 0x01 0x01 Chip Power On Reset System Reset - 0x10 0x10 RWDT System Reset System Reset See WDT Chapter. 0x0F 0x0F Brown Out Reset System Reset See Power Management Chapter. 0x03 0x03 Software System Reset Core Reset Configure RTC_CNTL_SW_SYS_RST register. 0x05 0x05 Deep Sleep Reset Core Reset See Power Management Chapter. 0x07 0x07 MWDT0 Global Reset Core Reset See WDT Chapter. Espressif Systems 34 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK PRO APP APP Source Reset Type Note 0x08 0x08 MWDT1 Global Reset Core Reset See WDT Chapter. 0x09 0x09 RWDT Core Reset Core Reset See WDT Chapter. 0x0B - MWDT0 CPU Reset CPU Reset See WDT Chapter. 0x0C - Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register. - 0x0B MWDT1 CPU Reset CPU Reset See WDT Chapter. - 0x0C Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register. CPU Reset See WDT Chapter. 0x0D 0x0D RWDT CPU Reset Indicates - 0xE PRO CPU Reset CPU Reset that the PRO CPU has indepen- dently reset the APP CPU by configuring the DPORT_APPCPU_RESETTING register. 3.2 System Clock 3.2.1 Introduction The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can be configured to meet different requirements. Figure 5 shows the system clock structure. Figure 5: System Clock Espressif Systems 35 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK 3.2.2 Clock Source The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source. Specifically, the clock sources available are: • High Speed Clocks – PLL_CLK is an internal PLL clock with a frequency of 320 MHz. – XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz. • Low Power Clocks – XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz. – RTC8M_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable. – RTC8M_D256_CLK is divided from RTC8M_CLK 256. Its frequency is (RTC8M_CLK / 256). With the default RTC8M_CLK frequency of 8 MHz, this clock runs at 31.250 KHz. – RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is adjustable. • Audio Clock – APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz. 3.2.3 CPU Clock As Figure 5 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 160 MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce power consumption. The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK, RTC8M_CLK and XTL_CLK can be set as the CPU_CLK source; see Table 9 and 10. Table 9: CPU_CLK Source RTC_CNTL_SOC_CLK_SEL Value Clock Source 0 XTL_CLK 1 PLL_CLK 2 RTC8M_CLK 3 APLL_CLK Espressif Systems 36 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK Table 10: CPU_CLK Derivation Clock Source SEL* 0 / XTL_CLK - 1 / PLL_CLK 0 1 / PLL_CLK 1 2 / RTC8M_CLK - 3 / APLL_CLK 0 CPU Clock CPU_CLK = XTL_CLK / (APB_CTRL_PRE_DIV_CNT+1) APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0. CPU_CLK = PLL_CLK / 4 CPU_CLK frequency is 80 MHz CPU_CLK = PLL_CLK / 2 CPU_CLK frequency is 160 MHz CPU_CLK = RTC8M_CLK / (APB_CTRL_PRE_DIV_CNT+1) APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0. CPU_CLK = APLL_CLK / 4 3 / APLL_CLK 1 CPU_CLK = APLL_CLK / 2 *SEL: DPORT_CPUPERIOD _SEL value 3.2.4 Peripheral Clock Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK and PLL_D2_CLK. Table 11 shows which clocks can be used by which peripherals. Table 11: Peripheral Clock Usage Peripherals APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_D2_CLK EMAC Y N N Y N TIMG Y N N N N I2S Y N N Y Y UART Y Y N N N RMT Y Y N N N LED PWM Y Y Y N N PWM Y N N N N I2C Y N N N N SPI Y N N N N PCNT Y N N N N Efuse Controller Y N N N N SDIO Slave Y N N N N SDMMC Y N N N N 3.2.4.1 APB_CLK Source The APB_CLK is derived from CPU_CLK as detailed in Table 12. The division factor depends on the CPU_CLK source. Espressif Systems 37 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK Table 12: APB_CLK Derivation CPU_CLK Source APB_CLK PLL_CLK PLL_CLK / 4 APLL_CLK CPU_CLK / 2 XTAL_CLK CPU_CLK RTC8M_CLK CPU_CLK 3.2.4.2 REF_TICK Source REF_TICK is derived from APB_CLK via a divider. The divider value used depends on the APB_CLK source, which in turn depends on the CPU_CLK source. By configuring correct divider values for each APB_CLK source, the user can ensure that the REF_TICK frequency does not change when CPU_CLK changes source, causing the APB_CLK frequency to change. Clock divider registers are shown in Table 13. Table 13: REF_TICK Derivation CPU_CLK & APB_CLK Source Clock Divider Register PLL_CLK APB_CTRL_PLL_TICK_NUM XTAL_CLK APB_CTRL_XTAL_TICK_NUM APLL_CLK APB_CTRL_APLL_TICK_NUM RTC8M_CLK APB_CTRL_CK8M_TICK_NUM 3.2.4.3 LEDC_SCLK Source The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 14. Table 14: LEDC_SCLK Derivation LEDC_APB_CLK_SEL Value LEDC_SCLK Source 1 RTC8M_CLK 0 APB_CLK 3.2.4.4 APLL_SCLK Source The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration registers. 3.2.4.5 PLL_D2_CLK Source PLL_D2_CLK is half the PLL_CLK frequency. Espressif Systems 38 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK 3.2.4.6 Clock Source Considerations Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the peripherals will need to update their clock configuration to operate at the same frequency after the change. Peripherals accessing REF_TICK can continue operating normally when switching clock sources, without changing clock source. Please see Table 11 for details. The LED PWM module can use RTC8M_CLK as a clock source when APB_CLK is disabled. In other words, when the system is in low-power consumption mode (see power manager module), normal peripherals will be halted (APB_CLK is turned off), but the LED PWM can work normally via RTC8M_CLK. 3.2.5 Wi-Fi BT Clock Wi-Fi and BT can only operate if APB_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK requires Wi-Fi and BT to both have entered low-power consumption mode first. For LOW_POWER_CLK, one of RTC_CLK, SLOW_CLK, RTC8M_CLK or XTL_CLK can be selected as the low-power consumption mode clock source for Wi-Fi and BT. 3.2.6 RTC Clock The clock sources of SLOW_CLK and FAST_CLK are low-frequency clocks. The RTC module can operate when most other clocks are stopped. SLOW_CLK is used to clock the Power Management module. It can be sourced from RTC_CLK, XTL32K_CLK or RTC8M_D256_CLK FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from RTC8M_CLK. 3.2.7 Audio PLL The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter, and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may carry jitter and, therefore, they do not support a high-precision clock frequency setting. Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an audio PLL intended for I2S peripherals. More details on how to clock the I2S module, using an APLL clock, can be found in Chapter I2S. The Audio PLL formula is as follows: fout = fxtal (sdm2 + sdm1 + sdm0 + 4) 28 216 2(odir + 2) The parameters of this formula are defined below: • fxtal : the frequency of the crystal oscillator, usually 40 MHz; • sdm0: the value is 0 ~ 255; • sdm1: the value is 0 ~ 255; • sdm2: the value is 0 ~ 63; • odir: the value is 0 ~ 31; Espressif Systems 39 ESP32 Technical Reference Manual V2.0 3. RESET AND CLOCK The operating frequency range of the numerator is 350 MHz ~ 500 MHz: 350M Hz < fxtal (sdm2 + sdm1 sdm0 + 16 + 4) < 500M Hz 28 2 Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in ECO and Workarounds for Bugs in ESP32 for further details. Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA_FORCE_PD, respectively. Disabling it takes priority over enabling it. When RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system, i.e., when the system enters sleep mode, PLL will be disabled automatically; when the system wakes up, PLL will be enabled automatically. Espressif Systems 40 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 4. IO_MUX and GPIO Matrix 4.1 Introduction The ESP32 chip features 34 physical GPIO pads. Some GPIO pads can neither be used nor have the corresponding pins on the chip package. Each pad can be used as a general-purpose I/O, or be connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for routing signals from the peripherals to GPIO pads. Together these systems provide highly configurable I/O. This chapter describes the signal selection and connection between the digital pads (FUNC_SEL, IE, OE, WPU, WDU, etc.), 162 peripheral input and 176 output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE, etc.), fast peripheral input/output signals (control signals: IE, OE, etc.), and RTC IO_MUX. Figure 6: IO_MUX, RTC IO_MUX and GPIO Matrix Overview 1. The IO_MUX contains one register per GPIO pad. Each pad can be configured to perform a ”GPIO” function (when connected to the GPIO Matrix) or a direct function (bypassing the GPIO Matrix). Some high-speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency digital performance. In this case, the IO_MUX is used to connect these pads directly to the peripheral.) See Section 4.10 for a list of IO_MUX functions for each I/O pad. 2. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pads. • For input to the chip: Each of the 162 internal peripheral inputs can select any GPIO pad as the input source. • For output from the chip: The output signal of each of the 34 GPIO pads can be from one of the 176 peripheral output signals. Espressif Systems 41 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX See Section 4.9 for a list of GPIO Matrix peripheral signals. 3. RTC IO_MUX is used to connect GPIO pads to their low-power and analog functions. Only a subset of GPIO pads have these optional ”RTC” functions. See Section 4.11 for a list of RTC IO_MUX functions. 4.2 Peripheral Input via GPIO Matrix 4.2.1 Summary To receive a peripheral input signal via the GPIO Matrix, the GPIO Matrix is configured to source the peripheral signal’s input index (0-18, 23-36, 39-58, 61-90, 95-124, 140-155, 164-181, 190-195, 198-206) from one of the 34 GPIOs (0-19, 21-23, 25-27, 32-39). The input signal is read from the GPIO pad through the IO_MUX. The IO_MUX must be configured to set the chosen pad to ”GPIO” function. This causes the GPIO pad input signal to be routed into the GPIO Matrix, which in turn routes it to the selected peripheral input. 4.2.2 Functional Description Figure 7 shows the logic for input selection via GPIO Matrix. In IO MUX In GPIO matrix GPIO_FUNCy_IN_SEL GPIOx_MCU_SEL 0 1 2 3 Peripheral Signal Y X 39 GPIO0_in GPIO1_in GPIO2_in GPIO_SIGxx_IN_SEL GPIO3_in 0 (FUNC) GPIO X in GPIOX_in 0 1 (GPIO) 1 (FUNC) 2 (GPIO) I/O Pad X GPIO39_in GPIOx_FUN_IE = 1 (0x30) 48 (0x38) 56 Constant 0 input Constant 1 input Figure 7: Peripheral Input via IO_MUX, GPIO Matrix To read GPIO pad X into peripheral signal Y, follow the steps below: 1. Configure the GPIO_FUNCy_IN_SEL_CFG register for peripheral signal Y in the GPIO Matrix: • Set the GPIO_FUNCx_IN_SEL field to the number of the GPIO pad X to read from. 2. Configure the GPIO_FUNCx_OUT_SEL_CFG and GPIO_ENABLE_DATA[x] for GPIO pad X in the GPIO Matrix: • For input-only signals, the pad output can be disabled by setting the GPIO_FUNCx_OEN_SEL bits to 1 and GPIO_ENABLE_DATA[x] to 0. For input/output dual mode signal, there is no need to disable output. Espressif Systems 42 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 3. Configure the IO_MUX register for GPIO pad X: • Set the function field to GPIO. • Enable the input by setting the xx_FUN_IE bit. • Set xx_FUN_WPU and xx_FUN_WPD fields, as required, to enable internal pull-up/pull-down resistors. Notes: • One input pad can be connected to multiple input_signals. • The input signal can be inverted with GPIO_FUNCx_IN_INV_SEL. • It is possible to have a peripheral read a constantly low or constantly high input value without connecting this input to a pad. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO number: – When GPIO_FUNCx_IN_SEL is 0x30, input_signal_x is always 0. – When GPIO_FUNCx_IN_SEL is 0x38, input_signal_x is always 1. 4.2.3 Simple GPIO Input The GPIO_IN_REG/GPIO_IN1_REG register holds the input values of each GPIO pad. The input value of any GPIO pin can be read at any time without configuring the GPIO Matrix for a particular peripheral signal. However, it is necessary to configure the xx_FUN_IE register for pad X, as shown in Section 4.2.2. 4.3 Peripheral Output via GPIO Matrix 4.3.1 Summary To output a signal from a peripheral via the GPIO Matrix, the GPIO Matrix is configured to route the peripheral output signal (0-18, 23-37, 61-121, 140-125, 224-228) to one of the 34 GPIOs (0-19, 21-23, 25-27, 32-39). The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO_MUX, which is configured to set the chosen pad to ”GPIO” function. This causes the output GPIO signal to be connected to the pad. Note: The peripheral output signals 224 to 228 can be configured to be routed in from one GPIO and output directly from another GPIO. Espressif Systems 43 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Figure 8: Output via GPIO Matrix 4.3.2 Functional Description One of the 176 output signals can be selected to go through the GPIO matrix into the IO_MUX and then to a pad. Figure 8 illustrates the configuration. To output peripheral signal Y to particular GPIO pad X, follow these steps: 1. Configure the GPIO_FUNCx_OUT_SEL_CFG register and GPIO_ENABLE_DATA[x] of GPIO X in the GPIO Matrix: • Set GPIO_FUNCx_OUT_SEL to the index of required peripheral output signal Y. • Set the GPIO_FUNCx_OEN_SEL bits and GPIO_ENABLE_DATA[x] to enable output mode, or clear GPIO_FUNCx_OEN_SEL to zero so that the output enable signal will be decided by the internal logic function. 2. Alternatively, to enable open drain mode set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register. 3. Configure the I/O mux register for GPIO pad X: • Set the function field to GPIO. • Set the xx_FUN_DRV field to the required value for output strength. The higher the value is, the stronger the output becomes. Pull up/down the pad by configuring xx_FUNC_WPU and xx_FUNC_WPD registers in open drain mode. Notes: • The output signal from a single peripheral can be sent to multiple pads simultaneously. • Only the 34 GPIOs can be used as outputs. • The output signal can be inverted by setting the GPIO_FUNCx_OUT_INV_SEL bit. Espressif Systems 44 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 4.3.3 Simple GPIO Output The GPIO Matrix can also be used for simple GPIO output – setting a bit in the GPIO_OUT_DATA register will write to the corresponding GPIO pad. To configure a pad as simple GPIO output, the GPIO Matrix GPIO_FUNCx_OUT_SEL register is configured with a special peripheral index value (0x100). 4.4 Direct I/O via IO_MUX 4.4.1 Summary Some high speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency digital performance. In this case, the IO_MUX is used to connect these pads directly to the peripheral. Selecting this option is less flexible than using the GPIO Matrix, as the IO_MUX register for each GPIO pad can only select from a limited number of functions. However, better high-frequency digital performance will be maintained. 4.4.2 Functional Description Two registers must be configured in order to bypass the GPIO Matrix for peripheral I/O: 1. IO_MUX for the GPIO pad must be set to the required pad function. (Please refer to section 4.10 for a list of pad functions.) 2. For inputs, the SIG_IN_SEL register must be set to route the input directly to the peripheral. 4.5 RTC IO_MUX for Low Power and Analog I/O 4.5.1 Summary 18 GPIO pads have low power capabilities (RTC domain) and analog functions which are handled by the RTC subsystem of ESP32. The IO_MUX and GPIO Matrix are not used for these functions; rather, the RTC_MUX is used to redirect the I/O to the RTC subsystem. When configured as RTC GPIOs, the output pads can still retain the output level value when the chip is in Deep-sleep mode, and the input pads can wake up the chip from Deep-sleep. Section 4.11 has a list of RTC_MUX pins and their functions. Espressif Systems 45 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 4.5.2 Functional Description Each pad with analog and RTC functions is controlled by the RTC_IO_TOUCH_PADx_TO_GPIO bit in the RTC_GPIO_PINx register. By default this bit is set to 1, routing all I/O via the IO_MUX subsystem as described in earlier subsections. If the RTC_IO_TOUCH_PADx_TO_GPIO bit is cleared, then I/O to and from that pad is routed to the RTC subsystem. In this mode, the RTC_GPIO_PINx register is used for digital I/O and the analog features of the pad are also available. See Section 4.11 for a list of RTC pin functions. See 4.11 for a table mapping GPIO pads to their RTC equivalent pins and analog functions. Note that the RTC_IO_PINx registers use the RTC GPIO pin numbering, not the GPIO pad numbering. 4.6 Light-sleep Mode Pin Functions Pins can have different functions when the ESP32 is in Light-sleep mode. If the GPIOxx_SLP_SEL bit in the IO_MUX register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in Light-sleep mode: Table 15: IO_MUX Light-sleep Pin Function Registers Normal Execution Light-sleep Mode OR GPIOxx_SLP_SEL = 0 AND GPIOxx_SLP_SEL = 1 Output Drive Strength GPIOxx_FUNC_DRV GPIOxx_MCU_DRV Pullup Resistor GPIOxx_FUNC_WPU GPIOxx_MCU_WPU Pulldown Resistor GPIOxx_FUNC_WPD GPIOxx_MCU_WPD Output Enable (From GPIO Matrix _OEN field) GPIOxx_MCU_OE IO_MUX Function If GPIOxx_SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep modes. 4.7 Pad Hold Feature Each IO pad (including the RTC pads) has an individual hold function controlled by a RTC register. When the pad is set to hold, the state is latched at that moment and will not change no matter how the internal signals change or how the IO_MUX configuration or GPIO configuration is modified. Users can use the hold function for the pads to retain the pad state through a core reset and system reset triggered by watchdog time-out or Deep-sleep events. 4.8 I/O Pad Power Supply IO pad power supply is shown in Figure 9. • Pads marked blue are RTC pads that have their individual analog function and can also act as normal digital IO pads. For details, please see Section 4.11. • Pads marked pink and green have digital functions only. • Pads marked green can be powered externally or internally via VDD_SDIO (see below). Espressif Systems 46 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Figure 9: ESP32 I/O Pad Power Sources 4.8.1 VDD_SDIO Power Domain VDD_SDIO can source or sink current, allowing this power domain to be powered externally or internally. To power VDD_SDIO externally, apply the same power supply of VDD3P3_RTC to the VDD_SDIO pad. Without an external power supply, the internal regulator will supply VDD_SDIO. The VDD_SDIO voltage can be configured to be either 1.8V or the same as VDD3P3_RTC), depending on the state of the MTDI pad at reset – a high level configures 1.8V and a low level configures the voltage to be the same as VDD3P3_RTC. Setting the efuse bit determines the default voltage of the VDD_SDIO. In addition, software can change the voltage of the VDD_SDIO by configuring register bits. 4.9 Peripheral Signal List Table 16 contains a list of Peripheral Input/Output signals used by the GPIO Matrix: Table 16: GPIO Matrix Peripheral Signals Signal Input Signal Output Signal Direct I/O in IO_MUX 0 SPICLK_in SPICLK_out YES 1 SPIQ_in SPIQ_out YES 2 SPID_in SPID_out YES 3 SPIHD_in SPIHD_out YES 4 SPIWP_in SPIWP_out YES 5 SPICS0_in SPICS0_out YES 6 SPICS1_in SPICS1_out 7 SPICS2_in SPICS2_out 8 HSPICLK_in HSPICLK_out YES 9 HSPIQ_in HSPIQ_out YES Espressif Systems 47 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Signal Input Signal Output Signal Direct I/O in IO_MUX 10 HSPID_in HSPID_out YES 11 HSPICS0_in HSPICS0_out YES 12 HSPIHD_in HSPIHD_out YES 13 HSPIWP_in HSPIWP_out YES 14 U0RXD_in U0TXD_out YES 15 U0CTS_in U0RTS_out YES 16 U0DSR_in U0DTR_out 17 U1RXD_in U1TXD_out YES 18 U1CTS_in U1RTS_out YES 23 I2S0O_BCK_in I2S0O_BCK_out 24 I2S1O_BCK_in I2S1O_BCK_out 25 I2S0O_WS_in I2S0O_WS_out 26 I2S1O_WS_in I2S1O_WS_out 27 I2S0I_BCK_in I2S0I_BCK_out 28 I2S0I_WS_in I2S0I_WS_out 29 I2CEXT0_SCL_in I2CEXT0_SCL_out 30 I2CEXT0_SDA_in I2CEXT0_SDA_out 31 pwm0_sync0_in sdio_tohost_int_out 32 pwm0_sync1_in pwm0_out0a 33 pwm0_sync2_in pwm0_out0b 34 pwm0_f0_in pwm0_out1a 35 pwm0_f1_in pwm0_out1b 36 pwm0_f2_in pwm0_out2a 37 pwm0_out2b 39 pcnt_sig_ch0_in0 40 pcnt_sig_ch1_in0 41 pcnt_ctrl_ch0_in0 42 pcnt_ctrl_ch1_in0 43 pcnt_sig_ch0_in1 44 pcnt_sig_ch1_in1 45 pcnt_ctrl_ch0_in1 46 pcnt_ctrl_ch1_in1 47 pcnt_sig_ch0_in2 48 pcnt_sig_ch1_in2 49 pcnt_ctrl_ch0_in2 50 pcnt_ctrl_ch1_in2 51 pcnt_sig_ch0_in3 52 pcnt_sig_ch1_in3 53 pcnt_ctrl_ch0_in3 54 pcnt_ctrl_ch1_in3 55 pcnt_sig_ch0_in4 56 pcnt_sig_ch1_in4 57 pcnt_ctrl_ch0_in4 58 pcnt_ctrl_ch1_in4 Espressif Systems 48 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Signal Input Signal Output Signal 61 HSPICS1_in HSPICS1_out 62 HSPICS2_in HSPICS2_out 63 VSPICLK_in VSPICLK_out_mux YES 64 VSPIQ_in VSPIQ_out YES 65 VSPID_in VSPID_out YES 66 VSPIHD_in VSPIHD_out YES 67 VSPIWP_in VSPIWP_out YES 68 VSPICS0_in VSPICS0_out YES 69 VSPICS1_in VSPICS1_out 70 VSPICS2_in VSPICS2_out 71 pcnt_sig_ch0_in5 ledc_hs_sig_out0 72 pcnt_sig_ch1_in5 ledc_hs_sig_out1 73 pcnt_ctrl_ch0_in5 ledc_hs_sig_out2 74 pcnt_ctrl_ch1_in5 ledc_hs_sig_out3 75 pcnt_sig_ch0_in6 ledc_hs_sig_out4 76 pcnt_sig_ch1_in6 ledc_hs_sig_out5 77 pcnt_ctrl_ch0_in6 ledc_hs_sig_out6 78 pcnt_ctrl_ch1_in6 ledc_hs_sig_out7 79 pcnt_sig_ch0_in7 ledc_ls_sig_out0 80 pcnt_sig_ch1_in7 ledc_ls_sig_out1 81 pcnt_ctrl_ch0_in7 ledc_ls_sig_out2 82 pcnt_ctrl_ch1_in7 ledc_ls_sig_out3 83 rmt_sig_in0 ledc_ls_sig_out4 84 rmt_sig_in1 ledc_ls_sig_out5 85 rmt_sig_in2 ledc_ls_sig_out6 86 rmt_sig_in3 ledc_ls_sig_out7 87 rmt_sig_in4 rmt_sig_out0 88 rmt_sig_in5 rmt_sig_out1 89 rmt_sig_in6 rmt_sig_out2 90 rmt_sig_in7 rmt_sig_out3 91 rmt_sig_out4 92 rmt_sig_out5 93 rmt_sig_out6 94 rmt_sig_out7 Direct I/O in IO_MUX 95 I2CEXT1_SCL_in I2CEXT1_SCL_out 96 I2CEXT1_SDA_in I2CEXT1_SDA_out 97 host_card_detect_n_1 host_ccmd_od_pullup_en_n 98 host_card_detect_n_2 host_rst_n_1 99 host_card_write_prt_1 host_rst_n_2 100 host_card_write_prt_2 gpio_sd0_out 101 host_card_int_n_1 gpio_sd1_out 102 host_card_int_n_2 gpio_sd2_out 103 pwm1_sync0_in gpio_sd3_out 104 pwm1_sync1_in gpio_sd4_out Espressif Systems 49 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Signal Input Signal Output Signal 105 pwm1_sync2_in gpio_sd5_out 106 pwm1_f0_in gpio_sd6_out 107 pwm1_f1_in gpio_sd7_out 108 pwm1_f2_in pwm1_out0a 109 pwm0_cap0_in pwm1_out0b 110 pwm0_cap1_in pwm1_out1a 111 pwm0_cap2_in pwm1_out1b 112 pwm1_cap0_in pwm1_out2a 113 pwm1_cap1_in pwm1_out2b 114 pwm1_cap2_in pwm2_out1h 115 pwm2_flta pwm2_out1l 116 pwm2_fltb pwm2_out2h 117 pwm2_cap1_in pwm2_out2l 118 pwm2_cap2_in pwm2_out3h 119 pwm2_cap3_in pwm2_out3l 120 pwm3_flta pwm2_out4h 121 pwm3_fltb pwm2_out4l 122 pwm3_cap1_in 123 pwm3_cap2_in 124 pwm3_cap3_in 140 I2S0I_DATA_in0 I2S0O_DATA_out0 141 I2S0I_DATA_in1 I2S0O_DATA_out1 142 I2S0I_DATA_in2 I2S0O_DATA_out2 143 I2S0I_DATA_in3 I2S0O_DATA_out3 144 I2S0I_DATA_in4 I2S0O_DATA_out4 145 I2S0I_DATA_in5 I2S0O_DATA_out5 146 I2S0I_DATA_in6 I2S0O_DATA_out6 147 I2S0I_DATA_in7 I2S0O_DATA_out7 148 I2S0I_DATA_in8 I2S0O_DATA_out8 149 I2S0I_DATA_in9 I2S0O_DATA_out9 150 I2S0I_DATA_in10 I2S0O_DATA_out10 151 I2S0I_DATA_in11 I2S0O_DATA_out11 152 I2S0I_DATA_in12 I2S0O_DATA_out12 153 I2S0I_DATA_in13 I2S0O_DATA_out13 154 I2S0I_DATA_in14 I2S0O_DATA_out14 155 I2S0I_DATA_in15 I2S0O_DATA_out15 156 I2S0O_DATA_out16 157 I2S0O_DATA_out17 158 I2S0O_DATA_out18 159 I2S0O_DATA_out19 160 I2S0O_DATA_out20 161 I2S0O_DATA_out21 162 I2S0O_DATA_out22 163 I2S0O_DATA_out23 Espressif Systems 50 Direct I/O in IO_MUX ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Signal Input Signal Output Signal 164 I2S1I_BCK_in I2S1I_BCK_out 165 I2S1I_WS_in I2S1I_WS_out 166 I2S1I_DATA_in0 I2S1O_DATA_out0 167 I2S1I_DATA_in1 I2S1O_DATA_out1 168 I2S1I_DATA_in2 I2S1O_DATA_out2 169 I2S1I_DATA_in3 I2S1O_DATA_out3 170 I2S1I_DATA_in4 I2S1O_DATA_out4 171 I2S1I_DATA_in5 I2S1O_DATA_out5 172 I2S1I_DATA_in6 I2S1O_DATA_out6 173 I2S1I_DATA_in7 I2S1O_DATA_out7 174 I2S1I_DATA_in8 I2S1O_DATA_out8 175 I2S1I_DATA_in9 I2S1O_DATA_out9 176 I2S1I_DATA_in10 I2S1O_DATA_out10 177 I2S1I_DATA_in11 I2S1O_DATA_out11 178 I2S1I_DATA_in12 I2S1O_DATA_out12 179 I2S1I_DATA_in13 I2S1O_DATA_out13 180 I2S1I_DATA_in14 I2S1O_DATA_out14 181 I2S1I_DATA_in15 I2S1O_DATA_out15 182 I2S1O_DATA_out16 183 I2S1O_DATA_out17 184 I2S1O_DATA_out18 185 I2S1O_DATA_out19 186 I2S1O_DATA_out20 187 I2S1O_DATA_out21 188 I2S1O_DATA_out22 189 I2S1O_DATA_out23 190 I2S0I_H_SYNC pwm3_out1h 191 I2S0I_V_SYNC pwm3_out1l 192 I2S0I_H_ENABLE pwm3_out2h 193 I2S1I_H_SYNC pwm3_out2l 194 I2S1I_V_SYNC pwm3_out3h 195 I2S1I_H_ENABLE pwm3_out3l 196 pwm3_out4h 197 pwm3_out4l Direct I/O in IO_MUX 198 U2RXD_in U2TXD_out YES 199 U2CTS_in U2RTS_out YES 200 emac_mdc_i emac_mdc_o 201 emac_mdi_i emac_mdo_o 202 emac_crs_i emac_crs_o 203 emac_col_i emac_col_o 204 pcmfsync_in bt_audio0_irq 205 pcmclk_in bt_audio1_irq 206 pcmdin bt_audio2_irq 207 Espressif Systems ble_audio0_irq 51 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Signal Input Signal Output Signal 208 ble_audio1_irq 209 ble_audio2_irq 210 pcmfsync_out 211 pcmclk_out 212 pcmdout 213 ble_audio_sync0_p 214 ble_audio_sync1_p 215 ble_audio_sync2_p 224 sig_in_func224 225 sig_in_func225 226 sig_in_func226 227 sig_in_func227 228 sig_in_func228 Direct I/O in IO_MUX Direct I/O in IO_MUX ”YES” means that this signal is also available directly via IO_MUX. To apply the GPIO Matrix to these signals, their corresponding SIG_IN_SEL register must be cleared. 4.10 IO_MUX Pad List Table 17 shows the IO_MUX functions for each I/O pad: Table 17: IO_MUX Pad Summary GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes 0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R 1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 - 2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R 3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 - 4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R 5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 - 6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 - 7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 - 8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 - 9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 - 10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 - 11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 - 12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R 13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 1 R 14 MTMS MTMS HSPICLK GPIO14 HS2_CLK SD_CLK EMAC_TXD2 1 R 15 MTDO MTDO HSPICS0 GPIO15 HS2_CMD SD_CMD EMAC_RXD3 3 R 16 GPIO16 GPIO16 - GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT 1 - 17 GPIO17 GPIO17 - GPIO17 HS1_DATA5 U2TXD EMAC_CLK_180 1 - 18 GPIO18 GPIO18 VSPICLK GPIO18 HS1_DATA7 - - 1 - 19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS - EMAC_TXD0 1 - 21 GPIO21 GPIO21 VSPIHD GPIO21 - - EMAC_TX_EN 1 - 22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS - EMAC_TXD1 1 - 23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE - - 1 - 25 GPIO25 GPIO25 - GPIO25 - - EMAC_RXD0 0 R 26 GPIO26 GPIO26 - GPIO26 - - EMAC_RXD1 0 R 27 GPIO27 GPIO27 - GPIO27 - - EMAC_RX_DV 1 R 32 32K_XP GPIO32 - GPIO32 - - - 0 R 33 32K_XN GPIO33 - GPIO33 - - - 0 R Espressif Systems 52 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes 34 VDET_1 GPIO34 - GPIO34 - - - 0 R, I 35 VDET_2 GPIO35 - GPIO35 - - - 0 R, I 36 SENSOR_VP GPIO36 - GPIO36 - - - 0 R, I 37 SENSOR_CAPP GPIO37 - GPIO37 - - - 0 R, I 38 SENSOR_CAPN GPIO38 - GPIO38 - - - 0 R, I 39 SENSOR_VN - GPIO39 - - - 0 R, I GPIO39 Reset Configurations ”Reset” column shows each pad’s default configurations after reset: • 0 - IE=0 (input disabled). • 1 - IE=1 (input enabled). • 2 - IE=1, WPD=1 (input enabled, pulldown resistor). • 3 - IE=1, WPU=1 (input enabled, pullup resistor). Notes • R - Pad has RTC/analog functions via RTC_MUX. • I - Pad can only be configured as input GPIO. Please refer to the ESP32 Pin Lists in ESP32 Datasheet for more details. 4.11 RTC_MUX Pin List Table 18 shows the RTC pins and how they correspond to GPIO pads: Table 18: RTC_MUX Pin Summary RTC GPIO Num GPIO Num Pad Name 0 36 1 Analog Function 1 2 3 SENSOR_VP ADC_H ADC1_CH0 - 37 SENSOR_CAPP ADC_H ADC1_CH1 - 2 38 SENSOR_CAPN ADC_H ADC1_CH2 - 3 39 SENSOR_VN ADC_H ADC1_CH3 - 4 34 VDET_1 - ADC1_CH6 - 5 35 VDET_2 - ADC1_CH7 - 6 25 GPIO25 DAC_1 ADC2_CH8 - 7 26 GPIO26 DAC_2 ADC2_CH9 - 8 33 32K_XN XTAL_32K_N ADC1_CH5 TOUCH8 9 32 32K_XP XTAL_32K_P ADC1_CH4 TOUCH9 10 4 GPIO4 - ADC2_CH0 TOUCH0 11 0 GPIO0 - ADC2_CH1 TOUCH1 12 2 GPIO2 - ADC2_CH2 TOUCH2 13 15 MTDO - ADC2_CH3 TOUCH3 14 13 MTCK - ADC2_CH4 TOUCH4 15 12 MTDI - ADC2_CH5 TOUCH5 16 14 MTMS - ADC2_CH6 TOUCH6 Espressif Systems 53 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX RTC GPIO Num GPIO Num Pad Name 17 27 GPIO27 4.12 Analog Function 1 2 3 - ADC2_CH7 TOUCH7 Register Summary Name Description Address Access GPIO_OUT_REG GPIO 0-31 output register_REG 0x3FF44004 R/W GPIO_OUT_W1TS_REG GPIO 0-31 output register_W1TS_REG 0x3FF44008 WO GPIO_OUT_W1TC_REG GPIO 0-31 output register_W1TC_REG 0x3FF4400C WO GPIO_OUT1_REG GPIO 32-39 output register_REG 0x3FF44010 R/W GPIO_OUT1_W1TS_REG GPIO 32-39 output bit set register_REG 0x3FF44014 WO GPIO_OUT1_W1TC_REG GPIO 32-39 output bit clear register_REG 0x3FF44018 WO GPIO_ENABLE_REG GPIO 0-31 output enable register_REG 0x3FF44020 R/W GPIO_ENABLE_W1TS_REG GPIO 0-31 output enable register_W1TS_REG 0x3FF44024 WO GPIO_ENABLE_W1TC_REG GPIO 0-31 output enable register_W1TC_REG 0x3FF44028 WO GPIO_ENABLE1_REG GPIO 32-39 output enable register_REG 0x3FF4402C R/W GPIO_ENABLE1_W1TS_REG GPIO 32-39 output enable bit set register_REG 0x3FF44030 WO GPIO_ENABLE1_W1TC_REG GPIO 32-39 output enable bit clear register_REG 0x3FF44034 WO GPIO_STRAP_REG Bootstrap pin value register_REG 0x3FF44038 RO GPIO_IN_REG GPIO 0-31 input register_REG 0x3FF4403C RO GPIO_IN1_REG GPIO 32-39 input register_REG 0x3FF44040 RO GPIO_STATUS_REG GPIO 0-31 interrupt status register_REG 0x3FF44044 R/W GPIO_STATUS_W1TS_REG GPIO 0-31 interrupt status register_W1TS_REG 0x3FF44048 WO GPIO_STATUS_W1TC_REG GPIO 0-31 interrupt status register_W1TC_REG 0x3FF4404C WO GPIO_STATUS1_REG GPIO 32-39 interrupt status register1_REG 0x3FF44050 R/W GPIO_STATUS1_W1TS_REG GPIO 32-39 interrupt status bit set register_REG 0x3FF44054 WO GPIO_STATUS1_W1TC_REG GPIO 32-39 interrupt status bit clear register_REG 0x3FF44058 WO GPIO_ACPU_INT_REG GPIO 0-31 APP_CPU interrupt status_REG 0x3FF44060 RO 0x3FF44064 RO 0x3FF44068 RO 0x3FF4406C RO 0x3FF44074 RO 0x3FF44078 RO 0x3FF4407C RO 0x3FF44080 RO GPIO_ACPU_NMI_INT_REG GPIO_PCPU_INT_REG GPIO_PCPU_NMI_INT_REG GPIO_ACPU_INT1_REG GPIO_ACPU_NMI_INT1_REG GPIO_PCPU_INT1_REG GPIO_PCPU_NMI_INT1_REG GPIO 0-31 APP_CPU non-maskable interrupt status_REG GPIO 0-31 PRO_CPU interrupt status_REG GPIO 0-31 PRO_CPU non-maskable interrupt status_REG GPIO 32-39 APP_CPU interrupt status_REG GPIO 32-39 APP_CPU non-maskable interrupt status_REG GPIO 32-39 PRO_CPU interrupt status_REG GPIO 32-39 PRO_CPU non-maskable interrupt status_REG GPIO_PIN0_REG Configuration for GPIO pin 0_REG 0x3FF44088 R/W GPIO_PIN1_REG Configuration for GPIO pin 1_REG 0x3FF4408C R/W GPIO_PIN2_REG Configuration for GPIO pin 2_REG 0x3FF44090 R/W ... ... Espressif Systems 54 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Name Description Address Access GPIO_PIN38_REG Configuration for GPIO pin 38_REG 0x3FF44120 R/W GPIO_PIN39_REG Configuration for GPIO pin 39_REG 0x3FF44124 R/W GPIO_FUNC0_IN_SEL_CFG_REG Peripheral function 0 input selection register_REG 0x3FF44130 R/W GPIO_FUNC1_IN_SEL_CFG_REG Peripheral function 1 input selection register_REG 0x3FF44134 R/W ... ... 0x3FF44528 R/W 0x3FF4452C R/W GPIO_FUNC254_IN_SEL_CFG_REG GPIO_FUNC255_IN_SEL_CFG_REG Peripheral function 254 input selection register_REG Peripheral function 255 input selection register_REG GPIO_FUNC0_OUT_SEL_CFG_REG Peripheral output selection for GPIO 0_REG 0x3FF44530 R/W GPIO_FUNC1_OUT_SEL_CFG_REG Peripheral output selection for GPIO 1_REG 0x3FF44534 R/W ... ... GPIO_FUNC38_OUT_SEL_CFG_REG Peripheral output selection for GPIO 38_REG 0x3FF445C8 R/W GPIO_FUNC39_OUT_SEL_CFG_REG Peripheral output selection for GPIO 39_REG 0x3FF445CC R/W Name Description Address Access IO_MUX_PIN_CTRL Clock output configuration register 0x3FF49000 R/W IO_MUX_GPIO36_REG Configuration register for pad GPIO36 0x3FF49004 R/W IO_MUX_GPIO37_REG Configuration register for pad GPIO37 0x3FF49008 R/W IO_MUX_GPIO38_REG Configuration register for pad GPIO38 0x3FF4900C R/W IO_MUX_GPIO39_REG Configuration register for pad GPIO39 0x3FF49010 R/W IO_MUX_GPIO34_REG Configuration register for pad GPIO34 0x3FF49014 R/W IO_MUX_GPIO35_REG Configuration register for pad GPIO35 0x3FF49018 R/W IO_MUX_GPIO32_REG Configuration register for pad GPIO32 0x3FF4901C R/W IO_MUX_GPIO33_REG Configuration register for pad GPIO33 0x3FF49020 R/W IO_MUX_GPIO25_REG Configuration register for pad GPIO25 0x3FF49024 R/W IO_MUX_GPIO26_REG Configuration register for pad GPIO26 0x3FF49028 R/W IO_MUX_GPIO27_REG Configuration register for pad GPIO27 0x3FF4902C R/W IO_MUX_MTMS_REG Configuration register for pad MTMS 0x3FF49030 R/W IO_MUX_MTDI_REG Configuration register for pad MTDI 0x3FF49034 R/W IO_MUX_MTCK_REG Configuration register for pad MTCK 0x3FF49038 R/W IO_MUX_MTDO_REG Configuration register for pad MTDO 0x3FF4903C R/W IO_MUX_GPIO2_REG Configuration register for pad GPIO2 0x3FF49040 R/W IO_MUX_GPIO0_REG Configuration register for pad GPIO0 0x3FF49044 R/W IO_MUX_GPIO4_REG Configuration register for pad GPIO4 0x3FF49048 R/W IO_MUX_GPIO16_REG Configuration register for pad GPIO16 0x3FF4904C R/W IO_MUX_GPIO17_REG Configuration register for pad GPIO17 0x3FF49050 R/W IO_MUX_SD_DATA2_REG Configuration register for pad SD_DATA2 0x3FF49054 R/W IO_MUX_SD_DATA3_REG Configuration register for pad SD_DATA3 0x3FF49058 R/W IO_MUX_SD_CMD_REG Configuration register for pad SD_CMD 0x3FF4905C R/W IO_MUX_SD_CLK_REG Configuration register for pad SD_CLK 0x3FF49060 R/W IO_MUX_SD_DATA0_REG Configuration register for pad SD_DATA0 0x3FF49064 R/W IO_MUX_SD_DATA1_REG Configuration register for pad SD_DATA1 0x3FF49068 R/W IO_MUX_GPIO5_REG Configuration register for pad GPIO5 0x3FF4906C R/W Espressif Systems 55 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Name Description Address Access IO_MUX_GPIO18_REG Configuration register for pad GPIO18 0x3FF49070 R/W IO_MUX_GPIO19_REG Configuration register for pad GPIO19 0x3FF49074 R/W IO_MUX_GPIO20_REG Configuration register for pad GPIO20 0x3FF49078 R/W IO_MUX_GPIO21_REG Configuration register for pad GPIO21 0x3FF4907C R/W IO_MUX_GPIO22_REG Configuration register for pad GPIO22 0x3FF49080 R/W IO_MUX_U0RXD_REG Configuration register for pad U0RXD 0x3FF49084 R/W IO_MUX_U0TXD_REG Configuration register for pad U0TXD 0x3FF49088 R/W IO_MUX_GPIO23_REG Configuration register for pad GPIO23 0x3FF4908C R/W IO_MUX_GPIO24_REG Configuration register for pad GPIO24 0x3FF49090 R/W Name Description Address Access RTCIO_RTC_GPIO_OUT_REG RTC GPIO output register_REG 0x3FF48000 R/W RTCIO_RTC_GPIO_OUT_W1TS_REG RTC GPIO output bit set register_REG 0x3FF48004 WO RTCIO_RTC_GPIO_OUT_W1TC_REG RTC GPIO output bit clear register_REG 0x3FF48008 WO RTCIO_RTC_GPIO_ENABLE_REG RTC GPIO output enable register_REG 0x3FF4800C R/W RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTC GPIO output enable bit setregister_REG 0x3FF48010 WO RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTC GPIO output enable bit clear register_REG 0x3FF48014 WO RTCIO_RTC_GPIO_STATUS_REG RTC GPIO interrupt status register_REG 0x3FF48018 WO RTCIO_RTC_GPIO_STATUS_W1TS_REG RTC GPIO interrupt status bit set register_REG 0x3FF4801C WO 0x3FF48020 WO GPIO configuration / data registers RTCIO_RTC_GPIO_STATUS_W1TC_REG RTC GPIO interrupt status bit clear register_REG RTCIO_RTC_GPIO_IN_REG RTC GPIO input register_REG 0x3FF48024 RO RTCIO_RTC_GPIO_PIN0_REG RTC configuration for pin 0_REG 0x3FF48028 R/W RTCIO_RTC_GPIO_PIN1_REG RTC configuration for pin 1_REG 0x3FF4802C R/W RTCIO_RTC_GPIO_PIN2_REG RTC configuration for pin 2_REG 0x3FF48030 R/W RTCIO_RTC_GPIO_PIN3_REG RTC configuration for pin 3_REG 0x3FF48034 R/W RTCIO_RTC_GPIO_PIN4_REG RTC configuration for pin 4_REG 0x3FF48038 R/W RTCIO_RTC_GPIO_PIN5_REG RTC configuration for pin 5_REG 0x3FF4803C R/W RTCIO_RTC_GPIO_PIN6_REG RTC configuration for pin 6_REG 0x3FF48040 R/W RTCIO_RTC_GPIO_PIN7_REG RTC configuration for pin 7_REG 0x3FF48044 R/W RTCIO_RTC_GPIO_PIN8_REG RTC configuration for pin 8_REG 0x3FF48048 R/W RTCIO_RTC_GPIO_PIN9_REG RTC configuration for pin 9_REG 0x3FF4804C R/W RTCIO_RTC_GPIO_PIN10_REG RTC configuration for pin 10_REG 0x3FF48050 R/W RTCIO_RTC_GPIO_PIN11_REG RTC configuration for pin 11_REG 0x3FF48054 R/W RTCIO_RTC_GPIO_PIN12_REG RTC configuration for pin 12_REG 0x3FF48058 R/W RTCIO_RTC_GPIO_PIN13_REG RTC configuration for pin 13_REG 0x3FF4805C R/W RTCIO_RTC_GPIO_PIN14_REG RTC configuration for pin 14_REG 0x3FF48060 R/W RTCIO_RTC_GPIO_PIN15_REG RTC configuration for pin 15_REG 0x3FF48064 R/W RTCIO_RTC_GPIO_PIN16_REG RTC configuration for pin 16_REG 0x3FF48068 R/W RTCIO_RTC_GPIO_PIN17_REG RTC configuration for pin 17_REG 0x3FF4806C R/W RTCIO_DIG_PAD_HOLD_REG RTC GPIO hold register_REG 0x3FF48074 R/W 0x3FF48078 R/W GPIO RTC function configuration registers RTCIO_HALL_SENS_REG Espressif Systems Hall sensor configuration_REG 56 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Name Description Address Access RTCIO_SENSOR_PADS_REG Sensor pads configuration register_REG 0x3FF4807C R/W RTCIO_ADC_PAD_REG ADC configuration register_REG 0x3FF48080 R/W RTCIO_PAD_DAC1_REG DAC1 configuration register_REG 0x3FF48084 R/W RTCIO_PAD_DAC2_REG DAC2 configuration register_REG 0x3FF48088 R/W RTCIO_XTAL_32K_PAD_REG 32KHz crystal pads configuration register_REG 0x3FF4808C R/W RTCIO_TOUCH_CFG_REG Touch sensor configuration register_REG 0x3FF48090 R/W RTCIO_TOUCH_PAD0_REG Touch pad configuration register_REG 0x3FF48094 R/W ... ... RTCIO_TOUCH_PAD9_REG Touch pad configuration register_REG 0x3FF480B8 R/W RTCIO_EXT_WAKEUP0_REG External wake up configuration register_REG 0x3FF480BC R/W RTCIO_XTL_EXT_CTR_REG Crystal power down enable GPIO source_REG 0x3FF480C0 R/W RTCIO_SAR_I2C_IO_REG RTC I2C pad selection_REG 0x3FF480C4 R/W Espressif Systems 57 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 4.13 Registers Register 4.1: GPIO_OUT_REG (0x0004) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_OUT_REG GPIO0-31 output value. (R/W) Register 4.2: GPIO_OUT_W1TS_REG (0x0008) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT_REG will be set. (WO) Register 4.3: GPIO_OUT_W1TC_REG (0x000c) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO) G (re PI O se rv _O ed ) UT _D AT A Register 4.4: GPIO_OUT1_REG (0x0010) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 x 0 x x x x x x x Reset GPIO_OUT_DATA GPIO32-39 output value. (R/W) Espressif Systems 58 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX G PI (re s er ve O _O d) UT _ DA TA Register 4.5: GPIO_OUT1_W1TS_REG (0x0014) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x Reset GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO) G (re s PI O _O er ve d ) UT _D AT A Register 4.6: GPIO_OUT1_W1TC_REG (0x0018) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x Reset GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO) Register 4.7: GPIO_ENABLE_REG (0x0020) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_ENABLE_REG GPIO0-31 output enable. (R/W) Register 4.8: GPIO_ENABLE_W1TS_REG (0x0024) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE will be set. (WO) Register 4.9: GPIO_ENABLE_W1TC_REG (0x0028) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO) Espressif Systems 59 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX G (re PI se rv O _E ed ) NA BL E_ DA TA Register 4.10: GPIO_ENABLE1_REG (0x002c) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x x x Reset GPIO_ENABLE_DATA GPIO32-39 output enable. (R/W) G PI (re se O _E rv ed ) NA BL E_ DA TA Register 4.11: GPIO_ENABLE1_W1TS_REG (0x0030) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x Reset GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE1 will be set. (WO) G PI (re se O _E rv ed ) NA BL E_ DA TA Register 4.12: GPIO_ENABLE1_W1TC_REG (0x0034) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x Reset GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO) G (re PI O _S se rv ed ) TR AP PI N G Register 4.13: GPIO_STRAP_REG (0x0038) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 x 0 x x x x x x x x x x x x x x x Reset GPIO_STRAPPING GPIO strapping results: Bit5-bit0 of boot_sel_chip[5:0] correspond to MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5, respectively. Espressif Systems 60 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Register 4.14: GPIO_IN_REG (0x003c) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_IN_REG GPIO0-31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level. (RO) G (re PI O se r _I ve d) N_ DA TA _N EX T Register 4.15: GPIO_IN1_REG (0x0040) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x Reset GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pad input value. (RO) Register 4.16: GPIO_STATUS_REG (0x0044) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_STATUS_REG GPIO0-31 interrupt status register. Each bit can be either of the two interrupt sources for the two CPUs. The enable bits in GPIO_STATUS_INTERRUPT, corresponding to the 0-4 bits in GPIO_PINn_REG should be set to 1. (R/W) Register 4.17: GPIO_STATUS_W1TS_REG (0x0048) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_STATUS_W1TS_REG GPIO0-31 interrupt status set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set. (WO) Register 4.18: GPIO_STATUS_W1TC_REG (0x004c) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_STATUS_W1TC_REG GPIO0-31 interrupt status clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. (WO) Espressif Systems 61 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX G (re PI se O _S rv ed ) TA TU S_ IN TE RR UP T Register 4.19: GPIO_STATUS1_REG (0x0050) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x x x Reset GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status. (R/W) G (re PI se O rv e _S d) TA TU S_ IN TE RR UP T Register 4.20: GPIO_STATUS1_W1TS_REG (0x0054) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x Reset GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be set. (WO) G (re se PI O _S rv ed ) TA TU S_ IN TE RR UP T Register 4.21: GPIO_STATUS1_W1TC_REG (0x0058) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 x x x x x x x x Reset GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared. (WO) Register 4.22: GPIO_ACPU_INT_REG (0x0060) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO) Espressif Systems 62 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX Register 4.23: GPIO_ACPU_NMI_INT_REG (0x0064) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO) Register 4.24: GPIO_PCPU_INT_REG (0x0068) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset x x x x x x x Reset GPIO_PCPU_INT_REG GPIO0-31 PRO CPU interrupt status. (RO) Register 4.25: GPIO_PCPU_NMI_INT_REG (0x006c) 31 x 0 x x x x x x x x x x x x x x x x x x x x x x x x GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO) G (re PI O se r ve _A d) PP CP U_ IN T Register 4.26: GPIO_ACPU_INT1_REG (0x0074) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 x 0 x x x x x x x x x Reset GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO) G (re PI O se rv ed ) _A PP CP U _N M I_ IN T Register 4.27: GPIO_ACPU_NMI_INT1_REG (0x0078) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 x 0 x x x x x Reset GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO) Espressif Systems 63 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX G (re PI se r ve O _P d) RO CP U_ I NT Register 4.28: GPIO_PCPU_INT1_REG (0x007c) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 x 0 x x x x x x x x x Reset GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO) G PI (re s O _P er ve d ) RO CP U_ NM I_ IN T Register 4.29: GPIO_PCPU_NMI_INT1_REG (0x0080) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 x 0 x x x x x Reset GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO) Espressif Systems 64 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 31 0 18 0 0 0 0 0 0 0 0 0 0 0 0 17 0 x x x x 11 10 9 x 0 0 x x 7 x 6 x 0 0 0 R PI G PI O G G 12 O _P IN (re n_ se P rv ed AD _D ) RI VE IN n_ W AK _P EU IN P_ n_ EN IN T_ AB TY LE (re PE se rv ed ) ) _P ed O rv 13 PI se (re G (re s PI O er ve _P d) IN n_ I NT _E NA Register 4.30: GPIO_PINn_REG (n: 0-39) (0x88+0x4*n) 3 2 3 2 0 x 0 0 Reset GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W) bit0: APP CPU interrupt enable; bit1: APP CPU non-maskable interrupt enable; bit3: PRO CPU interrupt enable; bit4: PRO CPU non-maskable interrupt enable. GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep. (R/W) GPIO_PINn_INT_TYPE Interrupt type selection: (R/W) 0: GPIO interrupt disable; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O _ PI SIG O m _F _ UN IN Cm _SE _I L N_ IN G V_ PI O SE _F L UN Cm _I N_ SE L G G (re PI se rv ed ) Register 4.31: GPIO_FUNCm_IN_SEL_CFG_REG (m: 0-255) (0x130+0x4*m) 8 7 6 5 0 x x x 0 x x x x x Reset GPIO_SIGm_IN_SEL Bypass the GPIO Matrix. 0: route through GPIO Matrix, 1: connect signal directly to peripheral configured in the IO_MUX. (R/W) GPIO_FUNCm_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W) GPIO_FUNCm_IN_SEL Selection control for peripheral input m. A value of 0-39 selects which of the 40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30 for a constantly low input. (R/W) Espressif Systems 65 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX G (re se rv ed ) PI O G _F PI U O N G _F C n PI U _ O N O _F Cn EN UN _O _ Cn EN INV _O _S _S UT EL EL _I NV _S EL G PI O _F UN Cn _O UT _S EL Register 4.32: GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-39) (0x530+0x4*n) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 11 10 9 8 0 0 x x x x x x x x x x x x Reset GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable signal. (R/W) GPIO_FUNCn_OEN_SEL 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG; 0: use output enable signal from peripheral. (R/W) GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W) GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. connects peripheral output s to GPIO output n. A value of s (0<=s<256) A value of 256 selects bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG as the output value and output enable. (R/W) 0x0 11 8 6 0x0 LK 1 PI N_ CT PI N_ N_ PI 12 RL RL CT RL CT ve d) se r (re 31 _C _C L _C LK 3 K2 Register 4.33: IO_MUX_PIN_CTRL (0x3FF49000) 3 0x0 3 0 0x0 Reset For the configuration of I2S0 peripheral clock output: When PIN_CTRL[3:0] = 0x0, select and output module clock on the CLK_OUT1 in the IO_MUX Pad Summary; When PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0, select and output module clock on the CLK_OUT2 in the IO_MUX Pad Summary; When PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0; select and output module clock on the CLK_OUT3 in the IO_MUX Pad Summary. For the configuration of I2S1 peripheral clock output: When PIN_CTRL[3:0] = 0xF, select and output module clock on CLK_OUT1-3. (R/W) Espressif Systems 66 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 31 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 _x _F U 12 IO IO IO (re se r _x _M ve d) CU _S EL NC _x _ _ IO FU DR V _x N IO _FU C_I _x N E _F C_ UN W IO C PU _x _M _W PD C IO _x U_D R IO _M _x CU V IO _M _IE _x CU IO _M _W _x CU P IO _SL _W U _x P P _M _S D CU EL _O E Register 4.34: IO_MUX_x_REG (x: GPIO0-GPIO39) (0x10+4*x) 11 0x0 10 0x2 9 8 7 0 0 0 6 5 0x0 4 3 2 1 0 0 0 0 0 0 Reset IO_x_MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 1, 1 selects Function 2, etc. (R/W) IO_x_FUNC_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. (R/W) IO_x_FUNC_IE Input enable of the pad. 1: input enabled; 0: input disabled. (R/W) IO_x_FUNC_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. (R/W) IO_x_FUNC_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. (R/W) IO_x_MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. (R/W) IO_x_MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. (R/W) IO_x_MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. (R/W) IO_x_MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. (R/W) IO_x_SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. (R/W) IO_x_MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W) (re RT CI se r O ve d ) _R T C_ G PI O _O UT _D AT A Register 4.35: RTCIO_RTC_GPIO_OUT_REG (0x0000) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 output register. Bit14 is GPIO[0], bit15 is GPIO[1], etc. (R/W) Espressif Systems 67 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX (re RT CI O se rv _R ed ) TC _G PI O _O UT _D AT A_ W 1T S Register 4.36: RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0001) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 output set register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be set. (WO) RT (re se CI O rv ed _R ) TC _G PI O _O UT _D AT A_ W 1T C Register 4.37: RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0002) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO) RT CI O (re se rv _R ed ) TC _G PI O _E N AB LE Register 4.38: RTCIO_RTC_GPIO_ENABLE_REG (0x0003) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1 means this GPIO pad is output. (R/W) Espressif Systems 68 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX (re RT CI O se rv _R ed ) TC _G PI O _E NA BL E_ W 1T S Register 4.39: RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0004) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO) RT CI O _R (re se rv ed ) TC _G PI O _E NA BL E_ W 1T C Register 4.40: RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0005) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO) (re RT CI O se rv _R ed ) TC _G PI O _S TA TU S_ IN T Register 4.41: RTCIO_RTC_GPIO_STATUS_REG (0x0006) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status. Bit14 is GPIO[0], bit15 is GPIO[1], etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT- CIO_RTC_GPIO_PINn_REG. 1: corresponding interrupt; 0: no interrupt. (R/W) Espressif Systems 69 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX RT CI O _R (re se rv ed ) TC _G PI O _S TA TU S _I NT _W 1T S Register 4.42: RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x0007) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 interrupt set register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be set. (WO) RT CI O _R (re se rv ed ) TC _G PI O _S TA TU S_ IN T_ W 1T C Register 4.43: RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0008) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared. (WO) RT CI (re se rv O _R ed ) TC _G PI O _I N_ NE XT Register 4.44: RTCIO_RTC_GPIO_IN_REG (0x0009) 31 x 14 x x x x x x x x x x x x x x x x 27 x 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each bit represents a pad input value, 1 for high level, and 0 for low level. (RO) Espressif Systems 70 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 0 x x 7 x ed ) x 0 0 0 RT ER _D RI V n_ PA D IN CI O (re se rv 6 _R (re se TC_ rv ed GP IO ) _P O _P PI TC _G _R CI O RT RT (re s er CI O ve _R d) TC _G PI O _P IN n_ W AK EU IN P_ n_ EN IN T_ AB TY LE PE Register 4.45: RTCIO_RTC_GPIO_PINn_REG (n: 0-17) (0xA+1*n) 3 2 3 2 0 x 0 0 Reset RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up the ESP32 from Light-sleep. (R/W) RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO interrupt type selection. (R/W) 0: GPIO interrupt disable; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. RTCIO_RTC_GPIO_PINn_PAD_DRIVER Pad driver selection. 0: normal output; 1: open drain. (R/W) Register 4.46: RTCIO_DIG_PAD_HOLD_REG (0x001d) 31 0 0 Reset RTCIO_DIG_PAD_HOLD_REG Select which digital pads are on hold. While 0 allows normal operation, 1 puts the pad on hold. (R/W) 31 30 59 0 0 0 (re RT se r ve d ) C RT IO_ CI HA O LL _H _ AL XP L_ D_ PH HA AS LL E Register 4.47: RTCIO_HALL_SENS_REG (0x001e) 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_HALL_XPD_HALL Power on hall sensor and connect to VP and VN. (R/W) RTCIO_HALL_PHASE Reverse the polarity of the hall sensor. (R/W) Espressif Systems 71 ESP32 Technical Reference Manual V2.0 RT C RT IO_ CI SE RT O_ NS C SE O RT IO_ NS R_S C SE O E RT IO_ NS R_S NSE C SE O E 1 RT IO_ NS R_S NSE _HO C SE O E 2 L RT IO_ NS R_S NSE _HO D C SE O E 3 L RT IO_ NS R_S NSE _HO D CI SE OR EN 4_ LD O N _ S H _S SO S E O RT EN R EN 1_ LD CI S _S SE MU O _S OR EN 2_M X_ RT EN _S SE U SE C SO EN 3_M X_ L RT IO_ SE U SE S C E R_ 4 X L RT IO_ NS SEN _M _S CI SE OR SE UX EL O N _ 1_ _SE _S SO S FU RT L EN R EN N_ CI SO _S SE O S E 1 _S E R N _ RT EN _S SE SLP L EN 1_ _ CI S O RT O_ SE SL SE C SE R_ 1 P_ L RT IO_ NS SEN _FU IE N CI SE OR SE O N _ 2_ _IE _S SO S F RT EN R EN UN CI SO _S SE _S O E 2 _S EL R N _ RT EN _S SE SL EN 2_ P_ CI S O R T O_ S S SE CI SE R_S E2_ LP_ L O N FU IE E RT _ S N CI SE OR NSE O N _ 3_ _IE _S SO S FU RT EN R EN N_ CI SO _S SE O SE E 3 _S N R _ L RT EN _S SE SL P E C SO NS 3_S _S RT IO_ E3 LP EL C SE R_ _ RT IO_ NS SEN _FU IE N_ CI SE OR SE O N _ IE 4_ _S SO S FU EN R EN N SO _S SE _ (re R_ ENS 4_S SEL se SE E LP rv ed NS 4_S _S ) E4 LP EL _F _IE UN _I E 4. IO_MUX AND GPIO MATRIX Register 4.48: RTCIO_SENSOR_PADS_REG (0x001f) 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 Espressif Systems 23 22 0 21 20 19 0 0 0 18 17 0 16 15 14 0 0 0 72 13 12 0 11 10 9 0 0 0 8 7 0 6 5 4 7 0 0 0 0 4 0 0 0 Reset RTCIO_SENSOR_SENSEn_HOLD Set to 1 to hold the output value on sensen; 0 is for normal operation. (R/W) RTCIO_SENSOR_SENSEn_MUX_SEL 1: route sensen to the RTC block; 0: route sensen to the digital IO_MUX. (R/W) RTCIO_SENSOR_SENSEn_FUN_SEL Select the RTC IO_MUX function for this pad. 0: select Function 0; 1: select Function 1. (R/W) RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pad: set to 1 to put the pad in sleep mode. (R/W) RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 31 30 29 28 0 0 0 0 27 26 0 25 24 23 0 0 0 22 21 0 20 19 18 35 0 0 0 0 (re RT se rv ed ) C RT IO_ CI AD RT O_ C_ C AD AD RT IO_ C_ C1 CI AD AD _H O C C O _A _A 2 L RT DC D _H D CI _ C1 OL O _A ADC _M D RT DC 2_ UX C M _S RT IO_ _AD U E C1 X_ L CI AD O C _F SEL RT _ _ UN CI AD AD O C C _S _A _A 1 EL RT DC D _S L C CI _A 1_ P_ O _A D S S RT DC C1 LP_ EL _ CI _ AD FUN IE RT O_ C2 _I CI AD _F E RT O_ C_ UN CI AD AD O C C _S _A _A 2 EL DC D _S L C _A 2_ P_ DC SL SE 2_ P_ L FU IE N_ IE Register 4.49: RTCIO_ADC_PAD_REG (0x0020) 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_ADC_ADCn_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation. (R/W) RTCIO_ADC_ADCn_MUX_SEL 0: route pad to the digital IO_MUX; (R/W) 1: route pad to the RTC block. RTCIO_ADC_ADCn_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select Function 1. (R/W) RTCIO_ADC_ADCn_SLP_SEL Signal selection of pad’s sleep mode. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1 enabled; 0 disabled. (R/W) RTCIO_ADC_ADCn_FUN_IE Input enable of the pad. 1 enabled; 0 disabled. (R/W) Espressif Systems 73 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX RT CI O _P RT AD CI _P RT O_ DA CI PA C1 RT O_ D_ _D CI PA PD O D_ AC RV _P P 1 AD DA _H _P C O DA 1_R LD C1 DE _R UE RT CI O _P AD _P DA C1 _D AC RT CI R T O_ CI PA O D_ _P P RT AD DA CI _P C O D 1_ _P RT AD AC XPD CI _P 1_M _D R T O_ DA U A P C A C1 X_ C RT IO_ D_ _F SEL CI PA PD UN D O A RT _ _ C _S CI PA PD 1_ EL RT O_ D_ AC SL CI PA PD 1_ P_ O D_ AC SL SE _P P 1 P L AD DA _S _I _P C LP E DA 1_F _O C1 UN E _D _I AC E _X PD (re _F se O rv RC ed E ) Register 4.50: RTCIO_PAD_DAC1_REG (0x0021) 31 30 2 29 28 27 0 0 0 26 19 0 18 17 0 0 16 15 0 14 13 12 11 10 19 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 Reset RTCIO_PAD_PDAC1_DRV Select the drive strength of the pad. (R/W) RTCIO_PAD_PDAC1_HOLD Set to 1 to hold the output value on the pad; set to 0 for normal operation. (R/W) RTCIO_PAD_PDAC1_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W) RTCIO_PAD_PDAC1_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W) RTCIO_PAD_PDAC1_DAC PAD DAC1 output value. (R/W) RTCIO_PAD_PDAC1_XPD_DAC Power on DAC1. Usually, PDAC1 needs to be tristated if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) RTCIO_PAD_PDAC1_MUX_SEL 0: route pad to the digital IO_MUX; (R/W) 1: route to the RTC block. RTCIO_PAD_PDAC1_FUN_SEL the functional selection signal of the pad. (R/W) RTCIO_PAD_PDAC1_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_PAD_PDAC1_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC1_SLP_OE Output enable of the pad. 1: enabled ; 0: disabled. (R/W) RTCIO_PAD_PDAC1_FUN_IE Input enable of the pad. 1: enabled it; 0: disabled. (R/W) RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) Espressif Systems 74 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX RT CI O _P RT AD CI _P RT O_ DA CI PA C2 RT O_ D_ _D CI PA PD O D_ AC RV _P P 2 AD DA _H _P C O DA 2_R LD C2 DE _R UE RT CI O _P AD _P DA C2 _D AC RT CI R T O_ CI PA O D_ _P P RT AD DA CI _P C O D 2_ _P RT AD AC XPD CI _P 2_M _D R T O_ DA U A P C A C2 X_ C RT IO_ D_ _F SEL CI PA PD UN D O A RT _ _ C _S CI PA PD 2_ EL RT O_ D_ AC SL CI PA PD 2_ P_ O D_ AC SL SE _P P 2 P L AD DA _S _I _P C LP E DA 2_F _O C2 UN E _D _I AC E _X PD (re _F se O rv RC ed E ) Register 4.51: RTCIO_PAD_DAC2_REG (0x0022) 31 30 2 29 28 27 0 0 0 26 19 0 18 17 0 0 16 15 0 14 13 12 11 10 19 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 Reset RTCIO_PAD_PDAC2_DRV Select the drive strength of the pad. (R/W) RTCIO_PAD_PDAC2_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation. (R/W) RTCIO_PAD_PDAC2_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W) RTCIO_PAD_PDAC2_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W) RTCIO_PAD_PDAC2_DAC PAD DAC2 output value. (R/W) RTCIO_PAD_PDAC2_XPD_DAC Power on DAC2. PDAC2 needs to be tristated if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) RTCIO_PAD_PDAC2_MUX_SEL 0: route pad to the digital IO_MUX; (R/W) 1: route to the RTC block. RTCIO_PAD_PDAC2_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select Function 1. (R/W) RTCIO_PAD_PDAC2_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_PAD_PDAC2_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC2_SLP_OE Output enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC2_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) Espressif Systems 75 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX CI O RT 31 30 2 RT _X TA CI L_ RT O_ X3 2N CI XT RT O_ AL _D _ X RV CI T X3 O AL 2 _X _ N RT _ X TA 3 H CI L_ 2N OL O X3 _R D _X 2N DE RT TA CI _R L_ O U RT _ X3 2P E CI XT _D RT O_ AL RV CI XT _X3 O AL 2 _X _ P_ RT X TA 3 H CI L_ 2P OL O X3 _R D _X 2P DE RT TA _R CI L_ O UE RT _ DA CI XT C_ RT O_ AL X CI XT _XP TAL O AL D _3 _X _ _ 2K RT TA X3 XT CI L_ 2N AL O _ X3 _M 3 _X 2P U 2K RT TA _M X_ CI L_ O RT _ X3 U SE X 2N X_S L CI T RT O_ AL _F E UN L CI XT _X3 A O R T _ L 2N _S EL CI XT _X3 _S O AL 2 L _X _ N P_ RT TA X3 _S SE CI L_ 2N LP L O X3 _S _IE _X 2N LP RT TA C _F _O L_ U E RT IO_ X3 2P N_I CI XT E A O _F RT _ L UN CI XT _X3 _S RT O_ AL 2P E CI XT _X3 _S O AL 2 LP L _X _ P_ _ RT X TA 3 S SE CI L_ 2P LP L O X3 _S _IE _X 2P LP TA _F _O RT L_ CI DR UN E O _I ES _X E (re _X TA se TA L _D rv L_ ed BI 32 ) AS K _X TA L_ 32 K Register 4.52: RTCIO_XTAL_32K_PAD_REG (0x0023) 29 28 27 0 0 0 26 25 2 24 23 22 21 20 19 18 17 0 0 0 0 1 0 0 0 16 15 0 14 13 12 11 0 0 0 0 10 9 0 8 7 6 5 4 3 2 1 1 0 0 0 0 1 0 0 0 0 Reset RTCIO_XTAL_X32N_DRV Select the drive strength of the pad. (R/W) RTCIO_XTAL_X32N_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation. (R/W) RTCIO_XTAL_X32N_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W) RTCIO_XTAL_X32N_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W) RTCIO_XTAL_X32P_DRV Select the drive strength of the pad. (R/W) RTCIO_XTAL_X32P_HOLD Set to 1 to hold the output value on the pad, 0 is for normal operation. (R/W) RTCIO_XTAL_X32P_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W) RTCIO_XTAL_X32P_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W) RTCIO_XTAL_DAC_XTAL_32K 32K XTAL bias current DAC value. (R/W) RTCIO_XTAL_XPD_XTAL_32K Power up 32 KHz crystal oscillator. (R/W) RTCIO_XTAL_X32N_MUX_SEL 0: route X32N pad to the digital IO_MUX; 1: route to RTC block. (R/W) RTCIO_XTAL_X32P_MUX_SEL 0: route X32P pad to the digital IO_MUX; 1: route to RTC block. (R/W) RTCIO_XTAL_X32N_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1. (R/W) RTCIO_XTAL_X32N_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_XTAL_X32N_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_X32N_SLP_OE Output enable of the pad. 1: enabled; 0; disabled. (R/W) RTCIO_XTAL_X32N_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_X32P_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1. (R/W) RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_XTAL_X32P_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_X32P_SLP_OE Output enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_X32P_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_XTAL_DRES_XTAL_32K 32K XTAL resistor bias control. (R/W) RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL self-bias reference control. (R/W) Espressif Systems 76 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX 31 30 29 0 1 1 0 28 27 26 0 1 25 24 23 1 0 (re se rv ed ) RT CI O _T RT O UC CI O H_ _T X O UC PD RT H_ _BI CI O DR AS _T EF O UC RT H H_ CI O D _T RE O FL UC RT H_ CI O DR _T AN O UC G E H_ DC UR Register 4.53: RTCIO_TOUCH_CFG_REG (0x0024) 45 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_TOUCH_XPD_BIAS Touch sensor bias power on bit. 1: power on; 0: disabled. (R/W) RTCIO_TOUCH_DREFH Touch sensor saw wave top voltage. (R/W) RTCIO_TOUCH_DREFL Touch sensor saw wave bottom voltage. (R/W) RTCIO_TOUCH_DRANGE Touch sensor saw wave voltage range. (R/W) RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is available. (R/W) 31 0 26 0 0 0 0 0 25 23 0x4 22 21 20 19 37 0 0 0 0 0 d) rv e se (re (re RT CI O se rv ed ) _T O UC RT H_ CI PA R T O_ Dn CI TO O _D R T _ UC T AC C O H RT IO_ UC _PA CI TO H_ Dn O U P _ _T C A ST O H_ Dn AR UC P _T T H_ ADn IE_ PA _X OP Dn PD T _T O _G PI O Register 4.54: RTCIO_TOUCH_PADn_REG (n: 0-9) (0x25+1*n) 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_TOUCH_PADn_DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 100. (R/W) RTCIO_TOUCH_PADn_START Start touch sensor. (R/W) RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option. 0: tie low; 1: tie high. (R/W) RTCIO_TOUCH_PADn_XPD Touch sensor power on. (R/W) RTCIO_TOUCH_PADn_TO_GPIO Connect the RTC pad input to digital pad input; 0 is available. (R/W) Espressif Systems 77 ESP32 Technical Reference Manual V2.0 4. IO_MUX AND GPIO MATRIX (re s er RT CI O ve d) _E XT _W AK EU P0 _S EL Register 4.55: RTCIO_EXT_WAKEUP0_REG (0x002f) 31 27 0 53 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is in deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W) (re RT se CI O rv e _X d) TL _E XT _C TR _S EL Register 4.56: RTCIO_XTL_EXT_CTR_REG (0x0030) 31 27 0 53 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTCIO_XTL_EXT_CTR_SEL Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0; 1: select GPIO2, etc. The input value on this pin XOR RTCIO_RTC_EXT_XTAL_CONF_REG[30] is the crystal power down enable signal. (R/W) 31 30 0 29 ed ) se rv (re RT RT CI O _S AR _I 2C CI O _S _S DA AR _S _I EL 2C _S CL _S EL Register 4.57: RTCIO_SAR_I2C_IO_REG (0x0031) 28 0 55 0 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCIO_SAR_I2C_SDA_SEL Selects a different pad as the RTC I2C SDA signal. 0 0 0 0 Reset 0: use pad TOUCH_PAD[1]; 1: use pad TOUCH_PAD[3]. (R/W) RTCIO_SAR_I2C_SCL_SEL Selects a different pad as the RTC I2C SCL signal. 0: use pad TOUCH_PAD[0]; 1: use pad TOUCH_PAD[2]. (R/W) Espressif Systems 78 ESP32 Technical Reference Manual V2.0 5. SPI 5. SPI 5.1 Overview Figure 10: SPI Architecture As Figure 10 shows, ESP32 integrates four SPI controllers which can be used to communicate with external devices that use the SPI protocol. Controller SPI0 is used as a buffer for accessing external memory. Controller SPI1 can be used as a master. Controllers SPI2 and SPI3 can be configured as either a master or a slave. When used as a master, each SPI controller can drive multiple CS signals (CS0 ~ CS2) to activate multiple slaves. Controllers SPI1 ~ SPI3 share two DMA channels. The SPI signal buses consist of D, Q, CS0-CS2, CLK, WP, and HD signals, as Table 22 shows. Controllers SPI0 and SPI1 share one signal bus through an arbiter; the signals of the shared bus start with ”SPI”. Controllers SPI2 and SPI3 use signal buses starting with ”HSPI” and ”VSPI” respectively. The I/O lines included in the above-mentioned signal buses can be mapped to pins via either the IO_MUX module or the GPIO matrix. (Please refer to Chapter IO_MUX for details.) The SPI controller supports four-line half-duplex and full-duplex communication (MOSI, MISO, CS, and CLK lines) and three-line-bit half-duplex-only communication (DATA, CS, and CLK lines) in GP-SPI mode. In QSPI mode, a SPI controller accesses the flash or SRAM by using signal buses D, Q, CS0 ~ CS2, CLK, WP, and HD as a four-bit parallel SPI bus. The mapping between the GP-SPI signal bus and the QSPI signal bus is shown in Table 22. Table 22: SPI Signal and Pin Signal Function Mapping Four-line GP-SPI Three-line GP-SPI QSPI Full-duplex Half-duplex Signal bus signal bus bus MOSI DATA MISO signal Pin function signals SPI signal HSPI signal VSPI signal bus bus bus D SPID HSPID VSPID - Q SPIQ HSPIQ VSPIQ CS CS CS SPICS0 HSPICS0 VSPICS0 CLK CLK CLK SPICLK HSPICLK VSPICLK - - WP SPIWP HSPIWP VSPIWP - - HD SPIHD HSPIHD VSPIHD 5.2 SPI Features General Purpose SPI (GP-SPI) Espressif Systems 79 ESP32 Technical Reference Manual V2.0 5. SPI • Programmable data transaction length, in multiples of 1 byte • Four-line full-duplex communication and three-line half-duplex communication support • Master mode and slave mode • Programmable CPOL and CPHA • Programmable clock Parallel QSPI • Communication format support for specific slave devices such as flash • Programmable communication format • Six variations of flash-read operations available • Automatic shift between flash and SRAM access • Automatic wait states for flash access SPI DMA Support • Support for sending and receiving data using linked lists SPI Interrupt Hardware • SPI interrupts • SPI DMA interrupts 5.3 GP-SPI The SPI1 ~ SPI3 controllers can communicate with other slaves as a standard SPI master. Every SPI master can be connected to three slaves at most by default. In non-DMA mode, the maximum length of data received/sent in one burst is 64 bytes. The data length is in multiples of 1 byte. 5.3.1 GP-SPI Master Mode The SPI master mode supports four-line full-duplex communication and three-line half-duplex communication. The connections needed for four-line full-duplex communications are outlined in Figure 11. Figure 11: SPI Master and Slave Full-duplex Communication For four-line full-duplex communication, the length of received and sent data needs to be set by configuring the SPI_MISO_DLEN_REG, SPI_MOSI_DLEN_REG registers for master mode as well as Espressif Systems 80 ESP32 Technical Reference Manual V2.0 5. SPI SPI_SLV_RDBUF_DLEN_REG, SPI_SLV_WRBUF_DLEN_REG registers for slave mode. The SPI_DOUTDIN bit and SPI_USR_MOSI bit in register SPI_USER_REG should also be configured. The SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize data transfer. If ESP32 SPI is configured as a slave using three-line half-duplex communication, the master-slave communication should meet a certain communication format. Please refer to 5.3.2.1 for details. For example, if ESP32 SPI acts as a slave, the communication format should be: command + address + received/sent data. The address length of the master should be the same as that of the slave; the value of the address should be 0. The byte order in which ESP32 SPI reads and writes is controlled by the SPI_RD_BYTE_ORDER bit and the SPI_WR_BYTE_ORDER bit in register SPI_USER_REG. The bit order is controlled by the SPI_RD_BIT_ORDER bit and the SPI_WR_BIT_ORDER bit in register SPI_CTRL_REG. 5.3.2 GP-SPI Slave Mode ESP32 SPI2 ~ SPI3 can communicate with other host devices as a slave device. ESP32 SPI should use particular protocols when acting as a slave. Data received or sent at one time can be no more than 64 bytes when not using DMA. During a valid read/write process, the appropriate CS signal must be maintained at a low level. If the CS signal is pulled up during transmission, the internal state of the slave will be reset. 5.3.2.1 Communication Format Supported by GP-SPI Slave The communication format of ESP32 SPI is: command + address + read/write data. When using half-duplex communication, the slave read and write operations use fixed hardware commands from which the address part can not be removed. The command is specified as follows: 1. command: length: 3 ~ 16 bits; Master Out Slave In (MOSI). 2. address: length: 1 ~ 32 bits; Master Out Slave In (MOSI). 3. data read/write: length�0 ~ 512 bits (64 bytes); Master Out Slave In (MOSI) or Master In Slave Out (MISO). When ESP32 SPI is used as a slave in full-duplex communication, data transaction can be directly initiated without the master sending command and address. However, please note that the CS should be pulled low at least one SPI clock period before a read/write process is initiated, and should be pulled high at least one SPI clock period after the read/write process is completed. 5.3.2.2 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode The minimum length of a command received by the slave should be three bits. The lowest three bits correspond to fixed hardware read and write operations as follows: 1. 0x1 (received by slave): Writes data sent by the master into the slave status register via MOSI. 2. 0x2 (received by slave): Writes data sent by the master into the slave data buffer. 3. 0x3 (sent by slave): Sends data in the slave buffer to master via MISO. 4. 0x4 (sent by slave): Sends data in the slave status register to master via MISO. 5. 0x6 (received and then sent by slave): Writes master data on MOSI into data buffer and then sends the date in the slave data buffer to MISO. Espressif Systems 81 ESP32 Technical Reference Manual V2.0 5. SPI The master can write the slave status register SPI_SLV_WR_STATUS_REG, and decide whether to read data from register SPI_SLV_WR_STATUS_REG or register SPI_RD_STATUS_REG via the SPI_SLV_STATUS_READBACK bit in the register SPI_SLAVE1_REG. The SPI master can maintain communication with the slave by reading and writing slave status register, thus realizing relatively complex communication with ease. 5.3.3 GP-SPI Data Buffer Figure 12: SPI Data Buffer ESP32 SPI has 16 x 32 bits of data buffer to buffer data-send and data-receive operations. As is shown in Figure 12, received data is written from the low byte of SPI_W0_REG by default and the writing ends with SPI_W15_REG. If the data length is over 64 bytes, the extra part will be written from SPI_W0_REG. Data buffer blocks SPI_W0_REG ~ SPI_W7_REG and SPI_W8_REG ~ SPI_W15_REG data correspond to the lower part and the higher part respectively. They can be used separately, and are controlled by the SPI_USR_MOSI_HIGHPART bit and the SPI_USR_MISO_HIGHPART bit in register SPI_USER_REG. For example, if SPI is configured as a master, when SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data; when SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data. If SPI acts as a slave, when SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data; when SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data. 5.4 GP-SPI Clock Control The maximum output clock frequency of ESP32 GP-SPI master is fapb /2, and the maximum input clock frequency of the ESP32 GP-SPI slave is fapb /8. The master can derive other clock frequencies via frequency division. fspi = fapb (SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1) SPI_CLKCNT_N and SPI_CLKDIV_PRE are two bits of register SPI_CLOCK_REG (Please refer to 5.8 Register Description for details). When the SPI_CLK_EQU_SYSCLK bit in the register SPI_CLOCK_REG is set to 1, and the other bits are set to 0, SPI output clock frequency is fapb . For other clock frequencies, SPI_CLK_EQU_SYSCLK needs to be 0. Espressif Systems 82 ESP32 Technical Reference Manual V2.0 5. SPI 5.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) The clock polarity and clock phase of ESP32 SPI are controlled by the SPI_CK_IDLE_EDGE bit in register SPI_PIN_REG, the SPI_CK_OUT_EDGE bit and the SPI_CK_I_EDGE bit in register SPI_USER_REG, the SPI_MISO_DELAY_MODE[1:0] bit, the SPI_MISO_DELAY_NUM[2:0] bit, the SPI_MOSI_DELAY_MODE[1:0] bit, and the SPI_MOSI_DELAY_MUM[2:0] bit in register SPI_CTRL2_REG. Table 23 and Table 24 show the clock polarity and phase as well as the corresponding register values for ESP32 SPI master and slave, respectively. Table 23: Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master Registers mode0 mode1 mode2 mode3 SPI_CK_IDLE_EDGE 0 0 1 1 SPI_CK_OUT_EDGE 0 1 1 0 SPI_MISO_DELAY_MODE 2(0) 1(0) 1(0) 2(0) SPI_MISO_DELAY_NUM 0 0 0 0 SPI_MOSI_DELAY_MODE 0 0 0 0 SPI_MOSI_DELAY_NUM 0 0 0 0 Table 24: Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave Registers mode0 mode1 mode2 mode3 SPI_CK_IDLE_EDGE 0 0 1 1 SPI_CK_I_EDGE 0 1 1 0 SPI_MISO_DELAY_MODE 0 0 0 0 SPI_MISO_DELAY_NUM 0 0 0 0 SPI_MOSI_DELAY_MODE 2 1 1 2 SPI_MOSI_DELAY_NUM 0 0 0 0 1. mode0 means CPOL=0, CPHA=0. When SPI is idle, the clock output is logic low; data change on the falling edge of the SPI clock and are sampled on the rising edge; 2. mode1 means CPOL=0, CPHA=1. When SPI is idle, the clock output is logic low; data change on the rising edge of the SPI clock and are sampled on the falling edge; 3. mode2 means when CPOL=1, CPHA=0. When SPI is idle, the clock output is logic high; data change on the rising edge of the SPI clock and are sampled on the falling edge; 4. mode3 means when CPOL=1, CPHA=1. When SPI is idle, the clock output is logic high; data change on the falling edge of the SPI clock and are sampled on the rising edge. 5.4.2 GP-SPI Timing The data signals of ESP32 GP-SPI can be mapped to physical pins via IO_MUX or via IO_MUX and GPIO matrix. When signals pass through the matrix, they will be delayed by two clkapb clock cycles. When GP-SPI is used as master and the data signals are not received by the SPI controller via GPIO matrix, if GP-SPI output clock frequency is not higher than clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 when configuring the clock polarity. If GP-SPI output clock frequency is not higher than clkapb /4, register Espressif Systems 83 ESP32 Technical Reference Manual V2.0 5. SPI SPI_MISO_DELAY_MODE can be set to the corresponding value in Table 23 when configuring the clock polarity. When GP-SPI is used in master mode and the data signals enter the SPI controller via the GPIO matrix: 1. If GP-SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 and the dummy state should be enabled (SPI_USR_DUMMY = 1) for one clkspi clock cycle (SPI_USR_DUMMY_CYCLELEN = 0) when configuring the clock polarity; 2. If GP-SPI output clock frequency is clkapb /4, register SPI_MISO_DELAY_MODE should be set to 0 when configuring the clock polarity; 3. If GP-SPI output clock frequency is not higher than clkapb /8, register SPI_MISO_DELAY_MODE can be set to the corresponding value in Table 23 when configuring the clock polarity. When GP-SPI is used in slave mode, the maximum slave input clock frequency is fapb /8. In addition, the clock signal and the data signals should be routed to the SPI controller via the same path, i.e., neither the clock signal nor the data signals enter the SPI controller via the GPIO matrix, or both the clock signal and the data signals enter the SPI controller via the GPIO matrix. This is important in ensuring that the signals are not delayed by different time periods before they reach the SPI hardware. 5.5 Parallel QSPI ESP32 SPI controllers support SPI bus memory devices (such as flash and SRAM). The hardware connection between the SPI pins and the memories is shown by Figure 13. Figure 13: Parallel QSPI SPI1, SPI2 and SPI3 controllers can also be configured as QSPI master to connect to external memory. The maximum output clock frequency of the SPI memory interface is fapb , with the same clock configuration as that of the GP-SPI master. ESP32 QSPI supports flash-read operation in one-line mode, two-line mode, and four-line mode. Espressif Systems 84 ESP32 Technical Reference Manual V2.0 5. SPI 5.5.1 Communication Format of Parallel QSPI To support communication with special slave devices, ESP32 QSPI implements a specifically designed communication protocol. The communication format of ESP32 QSPI master is command + address + read/write data, as shown in Figure 14, with details as follows: 1. Command: length: 1 ~ 16 bits; Master Out Slave In. 2. Address: length: 0 ~ 64 bits; Master Out Slave In. 3. Data read/write: length: 0 ~ 512 bits (64 bytes); Master Out Slave In or Master In Slave Out. Figure 14: Communication Format of Parallel QSPI When ESP32 SPI is configured as a master and communicates with slaves that use the SPI protocol, options such as command, address, data, etc., can be adjusted as required by the specific application. When ESP32 SPI reads special devices such as Flash and SRAM, a dummy state with a programmable length can be inserted between the address phase and the data phase. 5.6 GP-SPI Interrupt Hardware ESP32 SPI generates two types of interrupts. One is the SPI interrupt and the other is the SPI DMA interrupt. ESP32 SPI reckons the completion of send and/or receive operations as the completion of one operation from the controller and generates one interrupt. When ESP32 SPI is configured to slave mode, the slave will generate read/write status registers and read/write buffer data interrupts according to different operations. 5.6.1 SPI Interrupts The SPI_*_INTEN bits in the SPI_SLAVE_REG register can be set to enable SPI interrupts. When an SPI interrupt happens, the interrupt flag in the corresponding SPI_*_DONE register will get set. This flag is writable, and an interrupt can be cleared by setting the bit to zero. • SPI_TRANS_DONE_INT: Triggered when a SPI operation is done. • SPI_SLV_WR_STA_INT: Triggered when a SPI slave status write is done. • SPI_SLV_RD_STA_INT: Triggered when a SPI slave status read is done. • SPI_SLV_WR_BUF_INT: Triggered when a SPI slave buffer write is done. • SPI_SLV_RD_BUD_INT: Triggered when s SPI slave buffer read is done. Espressif Systems 85 ESP32 Technical Reference Manual V2.0 5. SPI 5.6.2 DMA Interrupts • SPI_OUT_TOTAL_EOF_INT: Triggered when all linked lists are sent. • SPI_OUT_EOF_INT: Triggered when one linked list is sent. • SPI_OUT_DONE_INT: Triggered when the last linked list item has zero length. • SPI_IN_SUC_EOF_INT: Triggered when all linked lists are received. • SPI_IN_ERR_EOF_INT: Triggered when there is an error receiving linked lists. • SPI_IN_DONE_INT: Triggered when the last received linked list had a length of 0. • SPI_INLINK_DSCR_ERROR_INT: Triggered when the received linked list is invalid. • SPI_OUTLINK_DSCR_ERROR_INT: Triggered when the linked list to be sent is invalid. • SPI_INLINK_DSCR_EMPTY_INT: Triggered when no valid linked list is available. 5.7 Register Summary Name Description SPI0 SPI1 SPI2 SPI3 Acc Control and configuration registers Bit SPI_CTRL_REG order and QIO/DIO/QOUT/DOUT 3FF43008 3FF42008 3FF64008 3FF64008 R/W mode settings SPI_CTRL1_REG CS delay configuration 3FF4300C 3FF4200C 3FF6400C 3FF6400C R/W SPI_CTRL2_REG Timing configuration 3FF43014 3FF42014 3FF64014 3FF64014 R/W SPI_CLOCK_REG Clock configuration 3FF43018 3FF42018 3FF64018 3FF64018 R/W SPI_PIN_REG Polarity and CS configuration 3FF43034 3FF42034 3FF64034 3FF64034 R/W Slave mode configuration registers Slave mode configSPI_SLAVE_REG uration and interrupt 3FF43038 3FF42038 3FF64038 3FF64038 R/W status SPI_SLAVE1_REG SPI_SLAVE2_REG SPI_SLAVE3_REG SPI_SLV_WR_STATUS_REG SPI_SLV_WRBUF_DLEN_REG SPI_SLV_RDBUF_DLEN_REG SPI_SLV_RD_BIT_REG Espressif Systems Slave data bit lengths Dummy cycle length configuration Read/write sta- tus/buffer register Slave status/higher master address Write-buffer opera- tion length Read-buffer opera- tion length Read data operation length 86 3FF4303C 3FF4203C 3FF6403C 3FF6403C R/W 3FF43040 3FF42040 3FF64040 3FF64040 R/W 3FF43044 3FF42044 3FF64044 3FF64044 R/W 3FF43030 3FF42030 3FF64030 3FF64030 R/W 3FF43048 3FF42048 3FF64048 3FF64048 R/W 3FF4304C 3FF4204C 3FF6404C 3FF6404C R/W 3FF43064 3FF42064 3FF64064 3FF64064 R/W ESP32 Technical Reference Manual V2.0 5. SPI User-defined command mode registers SPI_CMD_REG SPI_ADDR_REG SPI_USER_REG SPI_USER1_REG Start user-defined command Address data SPI_USER2_REG 3FF43004 3FF42004 3FF64004 3FF64004 R/W User defined command configuration Address and dummy cycle configuration Command 3FF43000 3FF42000 3FF64000 3FF64000 R/W 3FF4301C 3FF4201C 3FF6401C 3FF6401C R/W 3FF43020 3FF42020 3FF64020 3FF64020 R/W length and value configura- 3FF43024 3FF42024 3FF64024 3FF64024 R/W tion SPI_MOSI_DLEN_REG MOSI length 3FF43028 3FF42028 3FF64028 3FF64028 R/W SPI_W0_REG SPI data register 0 3FF43080 3FF42080 3FF64080 3FF64080 R/W SPI_W1_REG SPI data register 1 3FF43084 3FF42084 3FF64084 3FF64084 R/W SPI_W2_REG SPI data register 2 3FF43088 3FF42088 3FF64088 3FF64088 R/W SPI_W3_REG SPI data register 3 3FF4308C 3FF4208C 3FF6408C 3FF6408C R/W SPI_W4_REG SPI data register 4 3FF43090 3FF42090 3FF64090 3FF64090 R/W SPI_W5_REG SPI data register 5 3FF43094 3FF42094 3FF64094 3FF64094 R/W SPI_W6_REG SPI data register 6 3FF43098 3FF42098 3FF64098 3FF64098 R/W SPI_W7_REG SPI data register 7 3FF4309C 3FF4209C 3FF6409C 3FF6409C R/W SPI_W8_REG SPI data register 8 3FF430A0 3FF420A0 3FF640A0 3FF640A0 R/W SPI_W9_REG SPI data register 9 3FF430A4 3FF420A4 3FF640A4 3FF640A4 R/W SPI_W10_REG SPI data register 10 3FF430A8 3FF420A8 3FF640A8 3FF640A8 R/W SPI_W11_REG SPI data register 11 3FF430AC 3FF420AC 3FF640AC 3FF640AC R/W SPI_W12_REG SPI data register 12 3FF430B0 3FF420B0 3FF640B0 3FF640B0 R/W SPI_W13_REG SPI data register 13 3FF430B4 3FF420B4 3FF640B4 3FF640B4 R/W SPI_W14_REG SPI data register 14 3FF430B8 3FF420B8 3FF640B8 3FF640B8 R/W SPI_W15_REG SPI data register 15 3FF430BC 3FF420BC 3FF640BC 3FF640BC R/W SPI_TX_CRC_REG CRC32 of 256 bits of data (SPI1 only) 3FF430C0 3FF420C0 3FF640C0 3FF640C0 R/W Status registers SPI_RD_STATUS_REG Slave status and fast read mode 3FF43010 3FF42010 3FF64010 3FF64010 R/W DMA configuration registers SPI_DMA_CONF_REG SPI_DMA_OUT_LINK_REG SPI_DMA_IN_LINK_REG SPI_DMA_STATUS_REG DMA configuration register DMA outlink address and configuration DMA inlink address and configuration DMA status Descriptor SPI_IN_ERR_EOF_DES_ADDR_REG where 3FF43100 3FF42100 3FF64100 3FF64100 R/W 3FF43104 3FF42104 3FF64104 3FF64104 R/W 3FF43108 3FF42108 3FF64108 3FF64108 R/W 3FF4310C 3FF4210C 3FF6410C 3FF6410C RO address an error 3FF43120 3FF42120 3FF64120 3FF64120 RO occurs Espressif Systems 87 ESP32 Technical Reference Manual V2.0 5. SPI SPI_IN_SUC_EOF_DES_ADDR_REG SPI_INLINK_DSCR_REG SPI_INLINK_DSCR_BF0_REG SPI_INLINK_DSCR_BF1_REG Descriptor address where EOF occurs Current descriptor pointer Next descriptor data pointer Current descriptor data pointer 3FF43124 3FF42124 3FF64124 3FF64124 RO 3FF43128 3FF42128 3FF64128 3FF64128 RO 3FF4312C 3FF4212C 3FF6412C 3FF6412C RO 3FF43130 3FF42130 3FF64130 3FF64130 RO Relative buffer adSPI_OUT_EOF_BFR_DES_ADDR_REG dress where EOF 3FF43134 3FF42134 3FF64134 3FF64134 RO occurs SPI_OUT_EOF_DES_ADDR_REG SPI_OUTLINK_DSCR_REG SPI_OUTLINK_DSCR_BF0_REG SPI_OUTLINK_DSCR_BF1_REG SPI_DMA_RSTATUS_REG SPI_DMA_TSTATUS_REG Descriptor address where EOF occurs Current descriptor pointer Next descriptor data pointer Current descriptor data pointer DMA memory read status DMA memory write status 3FF43138 3FF42138 3FF64138 3FF64138 RO 3FF4313C 3FF4213C 3FF6413C 3FF6413C RO 3FF43140 3FF42140 3FF64140 3FF64140 RO 3FF43144 3FF42144 3FF64144 3FF64144 RO 3FF43148 3FF42148 3FF64148 3FF64148 RO 3FF4314C 3FF4214C 3FF6414C 3FF6414C RO DMA interrupt registers SPI_DMA_INT_RAW_REG SPI_DMA_INT_ST_REG Raw interrupt status Masked interrupt status 3FF43114 3FF42114 3FF64114 3FF64114 RO 3FF43118 3FF42118 3FF64118 3FF64118 RO SPI_DMA_INT_ENA_REG Interrupt enable bits 3FF43110 3FF42110 3FF64110 3FF64110 R/W SPI_DMA_INT_CLR_REG Interrupt clear bits 3FF4311C 3FF4211C 3FF6411C 3FF6411C R/W Espressif Systems 88 ESP32 Technical Reference Manual V2.0 5. SPI 5.8 Registers 0 0 0 0 0 0 0 0 0 0 0 ed ) (re SP I_ U er (re s 31 0 se rv SR ve d) Register 5.1: SPI_CMD_REG (0x0) 19 18 35 0 0 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_USR This bit is used to enable user-defined commands. An operation will be triggered when this bit is set. The bit will be cleared once the operation is done. (R/W) Register 5.2: SPI_ADDR_REG (0x4) 31 0 0x000000000 Reset SPI_ADDR_REG Address to slave or from master. If the address length is bigger than 32 bits, SPI_SLV_WR_STATUS_REG contains the lower 32 bits while this register contains the higher address bits. (R/W) Espressif Systems 89 ESP32 Technical Reference Manual V2.0 5. SPI 31 0 0 0 27 26 25 24 23 22 21 20 19 0 0 0 0 0 0 1 0 0 0 0 0 se rv ed ) I_ SP FR I_ EA FA D_ ST D RD UA _M L O DE 0 15 14 13 25 0 0 1 0 (re SP (re SP se rv ed ) I_ SP WR I_ _B SP RD IT_ I_ _B O SP FR IT_ RD I_ EA OR ER (re FR D_ DE se EA QIO R SP rve D_ I_ d) DIO SP WP I_ FR EA D_ Q UA (re D se rv ed ) Register 5.3: SPI_CTRL_REG (0x8) 13 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_WR_BIT_ORDER This bit determines the bit order for command, address and MOSI data writes. 1: sends LSB first; 0: sends MSB first. (R/W) SPI_RD_BIT_ORDER This bit determines the bit order for MOSI data reads. 1: receives LSB first; 0: receives MSB first. (R/W) SPI_FREAD_QIO This bit determines whether to use four data lines for address writes and MOSI data reads or not. 1: enable; 0: disable. (R/W) SPI_FREAD_DIO This bit determines whether to use two data lines for address writes and MOSI data reads or not. 1: enable; 0: disable. (R/W) SPI_WP This bit determines the write-protection signal output when SPI is idle. 1: output high; 0: output low. (R/W) SPI_FREAD_QUAD This bit determines whether to use four data lines for MOSI data reads or not. 1: enable; 0: disable. (R/W) SPI_FREAD_DUAL This bit determines whether to use two data lines for MOSI data reads or not. 1: enable; 0: disable. (R/W) SPI_FASTRD_MODE This bit is used to enable spi_fread_qio, spi_fread_dio, spi_fread_qout, and spi_fread_dout. 1: enable�0: disable. (R/W) 31 (re SP I_ se rv CS ed ) _H O LD _D EL AY Register 5.4: SPI_CTRL1_REG (0xC) 28 0x05 55 0 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_CS_HOLD_DELAY The number of SPI clock cycles by which the SPI CS signal is delayed. (R/W) Espressif Systems 90 ESP32 Technical Reference Manual V2.0 5. SPI SP SP I_ S TA TU I_ ST AT U S S_ EX T Register 5.5: SPI_RD_STATUS_REG (0x10) 31 24 0x000 23 16 0x000 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_STATUS_EXT In slave mode, this is the status for the master to read. (R/W) SPI_STATUS In slave mode, this is the status for the master to read. (R/W) Espressif Systems 91 ESP32 Technical Reference Manual V2.0 5. SPI 0x00 27 26 0x0 23 22 0x0 21 0x0 20 0x0 17 16 DE 0x0 12 0x00 7 4 0x01 TU SP SP I_ 8 0x00 I_ SE HO ed rv re se 11 P_ LD _T I M TI M E _H IG UT O I_ CK _ SP 15 E H_ M O DE M AY _ _D EL AY _N U IS O M I_ SP 18 O M DE O _D EL IS O SP SP I_ M I_ M O SI I_ M O SP 25 LA Y_ M LA Y_ _D E AY _M EL _D CS I_ SP 28 SI _D E DE O AY _N UM EL _D CS I_ SP 31 NU M Register 5.6: SPI_CTRL2_REG (0x14) 3 0 0x01 Reset SPI_CS_DELAY_NUM The spi_cs signal is delayed by the number of system clock cycles configured here. (R/W) SPI_CS_DELAY_MODE This register field determines the way the spi_cs signal is delayed by spi_clk. (R/W) 0: none. 1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, spi_cs is delayed by half a cycle, otherwise it is delayed by one cycle. 2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, spi_cs is delayed by one cycle, otherwise it is delayed by half a cycle. 3: the spi_cs signal is delayed by one cycle. SPI_MOSI_DELAY_NUM The MOSI signals are delayed by the number of system clock cycles configured here. (R/W) SPI_MOSI_DELAY_MODE This register field determines the way the MOSI signals are delayed by spi_clk. (R/W) 0: none. 1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by half a cycle, otherwise they are delayed by one cycle. 2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by one cycle, otherwise they are delayed by half a cycle. 3: the MOSI signals are delayed one cycle. SPI_MISO_DELAY_NUM The MISO signals are delayed by the number of system clock cycles specified here. (R/W) SPI_MISO_DELAY_MODE This register field determines the way MISO signals are delayed by spi_clk. (R/W) 0: none. 1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by half a cycle, otherwise they are delayed by one cycle. 2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by one cycle, otherwise they are delayed by half a cycle. 3: the MISO signals are delayed by one cycle. SPI_HOLD_TIME The number of spi_clk cycles by which CS pin signals are delayed. These bits are used in conjunction with the SPI_CS_HOLD bit. (R/W) SPI_SETUP_TIME The number of spi_clk cycles for which spi_cs is made active before the SPI data transaction starts. This register field is used when SPI_CS_SETUP is set. (R/W) Espressif Systems 92 ESP32 Technical Reference Manual V2.0 5. SPI 30 1 0 0 0 0 0 0 0 0 0 0 0 0 17 I_ CL KC NT _L _H SP SP I_ C SP I_ SP 18 0 I_ CL KC NT LK CN T_ V_ CL KD I EQ LK _ I_ C SP 31 N PR E U_ SY SC LK Register 5.7: SPI_CLOCK_REG (0x18) 12 11 6 0x03 0x01 5 0 0x03 Reset SPI_CLK_EQU_SYSCLK In master mode, when this bit is set to 1, spi_clk is equal to system clock; when set to 0, spi_clk is divided from system clock. (R/W) SPI_CLKDIV_PRE In master mode, the value of this register field is the pre-divider value for spi_clk, minus one. (R/W) SPI_CLKCNT_N In master mode, this is the divider for spi_clk minus one. The spi_clk frequency is system_clock/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). (R/W) SPI_CLKCNT_H For a 50% duty cycle, set this to floor((SPI_CLKCNT_N+1)/2-1). (R/W) SPI_CLKCNT_L In master mode, this must be equal to SPI_CLKCNT_N. In slave mode this must be 0. (R/W) Espressif Systems 93 ESP32 Technical Reference Manual V2.0 SP SP I_ SP SIO I_ SP FW I_ RI SP FW TE_ I_ RI Q SP FW TE_ IO I_ RI D SP FW TE_ IO I_ RIT QU SP WR E_ A I_ _B DU D RD Y A _B TE L (re Y T _O se E_ RD rv ed O ER SP RD ) I_ ER SP CK I_ _O SP CK UT I_ _I_ _E SP CS ED DG I_ _S GE E CS ET _H UP O (re LD se rv ed ) SP I_ DO UT DI N I_ SP US I_ R_ SP US CO I_ R_ M SP US AD MA I_ R_ DR ND SP US DU I_ R_ M SP US MIS MY I_ R_ O SP US MO I_ R_ S SP US DU I I_ R_ MM US M R_ OS Y_ID M I_H L IS IG E O _H HP IG AR HP T (re AR se T rv ed ) Register 5.8: SPI_USER_REG (0x1C) 31 30 29 28 27 26 25 24 23 1 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 Reset SPI_USR_COMMAND This bit enables the command phase of an operation. (R/W) SPI_USR_ADDR This bit enables the address phase of an operation. (R/W) SPI_USR_DUMMY This bit enables the dummy phase of an operation. (R/W) SPI_USR_MISO This bit enables the read-data phase of an operation. (R/W) SPI_USR_MOSI This bit enables the write-data phase of an operation. (R/W) SPI_USR_DUMMY_IDLE The spi_clk signal is disabled in the dummy phase when the bit is set. (R/W) SPI_USR_MOSI_HIGHPART If set, data written to the device is only read from SPI_W8-SPI_W15 of the SPI buffer. (R/W) SPI_USR_MISO_HIGHPART If set, data read from the device is only written to SPI_W8-SPI_W15 of the SPI buffer. (R/W) SPI_SIO Set this bit to enable three-line half-duplex communication where MOSI and MISO signals share the same pin. (R/W) SPI_FWRITE_QIO This bit enables the use of four data lines for address and MISO data writes. 1: enable; 0: disable. (R/W) SPI_FWRITE_DIO This bit enables the use of two data lines for address and MISO data writes. 1: enable; 0: disable. (R/W) SPI_FWRITE_QUAD This bit enables the use of four data lines for MISO data writes. 1: enable; 0: disable. (R/W) SPI_FWRITE_DUAL This bit determines whether to use two data lines for MISO data writes or not. 1: enable; 0: disable. (R/W) SPI_WR_BYTE_ORDER This bit determines the byte-endianness for writing command, address, and MOSI data. 1: big-endian; 0: litte-endian. (R/W) SPI_RD_BYTE_ORDER This bit determines the byte-endianness for reading MISO data. 1: big-endian; 0: little_endian. (R/W) SPI_CK_OUT_EDGE This bit, combined with SPI_MOSI_DELAY_MODE, sets the MOSI signal delay mode. (R/W) SPI_CK_I_EDGE In slave mode, the bit is the same as SPI_CK_OUT_EDGE in master mode. It is combined with SPI_MISO_DELAY_MODE. (R/W) SPI_CS_SETUP Setting this bit enables a delay between spi_cs being active and starting data transfer, as specified in SPI_SETUP_TIME. This bit only is valid in half-duplex mode, that is, when SPI_DOUTDIN is not set. (R/W) SPI_CS_HOLD Setting this bit enables a delay between the end of a transmission and spi_cs being made inactive, as specified in SPI_HOLD_TIME. (R/W) SPI_DOUTDIN Set the bit to enable full-duplex communication, meaning that MOSI data is sent out at the same time MISO data is received. 1: enable; 0: disable. (R/W) Espressif Systems 94 ESP32 Technical Reference Manual V2.0 5. SPI 31 26 23 I_ SP SP (re s I_ er US ve US R d) R_ AD _D UM DR M _B I Y_ TL EN CY CL E LE N Register 5.9: SPI_USER1_REG (0x20) 25 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 7 Reset SPI_USR_ADDR_BITLEN The bit length of the address phase minus one. (RO) SPI_USR_DUMMY_CYCLELEN The number of spi_clk cycles for the dummy phase, minus one. (R/W) 31 R_ US I_ SP (re SP se r I_ US ve d) R_ CO CO M M M AN M AN D_ D_ BI VA L TL E UE N Register 5.10: SPI_USER2_REG (0x24) 28 7 27 0 16 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_USR_COMMAND_BITLEN The bit length of the command phase minus one. (R/W) SPI_USR_COMMAND_VALUE The value of the command. (R/W) SP (re se I_ US rv e d) R_ M O SI _ DB IT LE N Register 5.11: SPI_MOSI_DLEN_REG (0x28) 31 0 24 0 0 0 0 0 0 23 0 0 0x0000000 Reset SPI_USR_MOSI_DBITLEN The bit length of the data to be written to the device minus one. (R/W) Espressif Systems 95 ESP32 Technical Reference Manual V2.0 5. SPI SP (re s er ve d) I_ US R_ M IS O _D BI T LE N Register 5.12: SPI_MISO_DLEN_REG (0x2C) 31 0 24 0 0 0 0 0 0 23 0 0 0x0000000 Reset SPI_USR_MISO_DBITLEN The bit length of the data to be read from the device, minus one. (R/W) Register 5.13: SPI_SLV_WR_STATUS_REG (0x30) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_SLV_WR_STATUS_REG In the slave mode this register is the status register for the master to write into. In the master mode, if the address length is bigger than 32 bits, this register contains the lower 32 bits. (R/W) Espressif Systems 96 ESP32 Technical Reference Manual V2.0 5. SPI 30 29 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 11 0 0 0 9 I_ M AS TE SP R_ I_ CS CK _P _D (re O IS se L rv ed SP ) I_ SP CS I_ 2_ SP CS DIS I_ 1_D CS I 0_ S DI S ed ) 10 SP M I_ SP 14 0 (re se rv AS ) ed rv se (re (re 31 TE R_ CK _S E L se SP rve I_ d) SP CS I_ _K CK EE _I P_ DL A E_ CT ED IVE G E Register 5.14: SPI_PIN_REG (0x34) 8 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1 1 0 Reset SPI_CS_KEEP_ACTIVE When set, the spi_cs will be kept active even when not in a data transaction. (R/W) SPI_CK_IDLE_EDGE The idle state of the spi_clk line. (R/W) 1: the spi_clk line is high when idle; 0: the spi_clk line is low when idle. SPI_MASTER_CK_SEL This register field contains one bit per spi_cs line. When a bit is set in master mode, the corresponding spi_cs line is made active and the spi_cs pin outputs spi_clk. (R/W) SPI_MASTER_CS_POL This register filed selects the polarity of the spi_cs line. It contains one bit per spi_cs line. Possible values of the bits: (R/W) 0: spi_cs is active-low; 1: spi_cs is active-high. SPI_CK_DIS When set, output of the spi_clk signal is disabled. (R/W) SPI_CS2_DIS This bit enables the SPI CS2 pin. 1: disables CS2; 0: spi_cs2 is active during the data transaction. (R/W) SPI_CS1_DIS This bit enables the SPI CS1 pin. 1: disables CS1; 0: spi_cs1 is active during the data transaction (R/W) SPI_CS0_DIS This bit enables the SPI CS0 pin. 1: disables CS0; 0: spi_cs0 is active during the data transaction. (R/W) Espressif Systems 97 ESP32 Technical Reference Manual V2.0 31 30 29 28 27 26 0 0 0 0 0 0 23 0 0 22 0 0 20 0 19 0 0 17 0 16 0 0 12 0 0 0 SP SP I_ CS _I _M I_ O T SP R DE I_ AN SP SLV S_ I_ _ IN SP SLV WR TEN I_ _ _S SP SLV RD_ TA_ I_ _ S IN SP SLV WR TA_ TE I_ _R _B INT N SP TR D_ UF EN I_ AN B _IN SP SLV S_ UF_ TE I_ _W DO IN N SP SLV R NE TE N I_ _R _S SP SLV D_ TA_ I_ _W ST DO SL R A V_ _ _D NE RD BU ON _B F_D E UF O _D NE O NE SP I_ SP SY I_ NC SP SL _R I_ AV ES SP SLV E_M ET I_ _ O SP SLV WR DE I_ _W _R SL R D V_ _ _B CM RD UF D_ _ST _EN SP DE A_ I_ TR FI EN NE AN S_ CN T SP I_ SL V_ LA ST _S SP TA I_ TE SL V_ LA ST _C O M M (re AN se D rv ed ) Register 5.15: SPI_SLAVE_REG (0x38) 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_SYNC_RESET This bit is used to enable software reset. When set, it resets the latched values of the SPI clock line, cs line and data lines. (R/W) SPI_SLAVE_MODE This bit is used to set the mode of the SPI device. (R/W) 1: slave mode; 0: master mode. SPI_SLV_WR_RD_BUF_EN Setting this bit enables the write and read buffer commands in slave mode. (R/W) SPI_SLV_WR_RD_STA_EN Setting this bit enables the write and read status commands in slave mode. (R/W) SPI_SLV_CMD_DEFINE This bit is used to enable custom slave mode commands. (R/W) 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 0x1: write-status; 0x2: write-buffer, 0x3: read-buffer; and 0x4: read-status. SPI_TRANS_CNT The counter for operations in both the master mode and the slave mode. (RO) SPI_SLV_LAST_STATE In slave mode, this contains the state of the SPI state machine. (RO) SPI_SLV_LAST_COMMAND In slave mode, this contains the value of the received command. (RO) SPI_CS_I_MODE In the slave mode, this selects the mode to synchronize the input SPI cs signal and eliminate SPI cs jitter. (R/W) 0: configured through registers (SPI_CS_DELAY_NUM and SPI_CS_DELAY_MODE); 1: using double synchronization method and configured through registers (SPI_CS_DELAY_NUM and SPI_CS_DELAY_MODE); 2: using double synchronization method. SPI_TRANS_INTEN The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt. (R/W) SPI_SLV_WR_STA_INTEN The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt. (R/W) SPI_SLV_RD_STA_INTEN The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt. (R/W) SPI_SLV_WR_BUF_INTEN The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt. (R/W) SPI_SLV_RD_BUF_INTEN The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt. (R/W) SPI_TRANS_DONE The raw interrupt status bit for the SPI_TRANS_DONE_INT interrupt. (R/W) SPI_SLV_WR_STA_DONE The raw interrupt status bit for the SPI_SLV_WR_STA_INT interrupt. (R/W) SPI_SLV_RD_STA_DONE The raw interrupt status bit for the SPI_SLV_RD_STA_INT interrupt. (R/W) SPI_SLV_WR_BUF_DONE The raw interrupt status bit for the SPI_SLV_WR_BUF_INT interrupt. (R/W) SPI_SLV_RD_BUF_DONE The raw interrupt status bit for the SPI_SLV_RD_BUF_INT interrupt. (R/W) Espressif Systems 98 ESP32 Technical Reference Manual V2.0 5. SPI 31 0 0 0 0 27 26 25 24 0 0 1 0 16 0 0 0 0 0 0 0 15 0 DR _B I_ IT LE SP SLV N I_ _W S SP LV R S I_ _ T SP SLV RDS A_D I_ _W TA U SL R _ M V_ B DU MY RD UF M _E BU _D MY N F_ U M _E DU M N M Y_E M N Y_ EN AD 9 SP SP 10 0x00 R_ I_ SL V_ W SL V_ RD I_ SP SP SP I_ I_ SL V_ ST AT U _A DD R_ BI T LE N S_ BI TL S SP LV EN _ I_ S SL T V_ AT ST US AT _F US AS _R T_ EA EN DB AC (re K se rv ed ) Register 5.16: SPI_SLAVE1_REG (0x3C) 4 0x00 3 2 1 0 0 0 0 0 Reset SPI_SLV_STATUS_BITLEN In slave mode, this sets the length of the status field. (R/W) SPI_SLV_STATUS_FAST_EN In slave mode, this enables fast reads of the status. (R/W) SPI_SLV_STATUS_READBACK In slave mode, this selects the active status register. (R/W) 1: reads register of SPI_SLV_WR_STATUS; 0: reads register of SPI_RD_STATUS. SPI_SLV_RD_ADDR_BITLEN In slave mode, this contains the address length in bits for a read-buffer operation, minus one. (R/W) SPI_SLV_WR_ADDR_BITLEN In slave mode, this contains the address length in bits for a write-buffer operation, minus one. (R/W) SPI_SLV_WRSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for write-status operations. (R/W) SPI_SLV_RDSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for read-status operations. (R/W) SPI_SLV_WRBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for write-buffer operations. (R/W) SPI_SLV_RDBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for read-buffer operations. (R/W) Espressif Systems 99 ESP32 Technical Reference Manual V2.0 5. SPI 31 0 24 0 0 0 0 0 0 23 16 0 LE N LE N CY CL E CY CL E Y_ Y_ M M DU M M DU ST A_ TA _ RD RS SL V_ W LV _ SP I_ I_ S SP SP SP I_ S I_ S LV _ LV _ W RB RD BU UF F_ D _D UM UM M M Y_ CY CL EL Y_ CY CL EL EN EN Register 5.17: SPI_SLAVE2_REG (0x40) 15 8 0x000 7 0 0x000 0x000 Reset SPI_SLV_WRBUF_DUMMY_CYCLELEN In slave mode, this contains number of spi_clk cycles for the dummy phase for write-buffer operations, minus one. (R/W) SPI_SLV_RDBUF_DUMMY_CYCLELEN In slave mode, this contains the number of spi_clk cycles for the dummy phase for read-buffer operations, minus one (R/W) SPI_SLV_WRSTA_DUMMY_CYCLELEN In slave mode, this contains the number of spi_clk cycles for the dummy phase for write-status operations, minus one. (R/W) SPI_SLV_RDSTA_DUMMY_CYCLELEN In slave mode, this contains the number of spi_clk cycles for the dummy phase for read-status operations, minus one. (R/W) 31 0 24 0 0 0 0 0 0 23 0 0 16 0 0 0 0 UE UE D_ VA L VA L D_ F_ CM M BU UF _C RD W RB SL V_ SL V_ I_ I_ 0 0 SP SP SP SP I_ I_ SL V_ SL V_ W RD RS ST A_ TA _ CM CM D_ D_ VA L VA L UE UE Register 5.18: SPI_SLAVE3_REG (0x44) 15 0 0 8 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 Reset SPI_SLV_WRSTA_CMD_VALUE In slave mode, this contains the value of the write-status command. (R/W) SPI_SLV_RDSTA_CMD_VALUE In slave mode, this contains the value of the read-status command. (R/W) SPI_SLV_WRBUF_CMD_VALUE In slave mode, this contains the value of the write-buffer command. (R/W) SPI_SLV_RDBUF_CMD_VALUE In slave mode, this contains the value of the read-buffer command. (R/W) Espressif Systems 100 ESP32 Technical Reference Manual V2.0 5. SPI SP (re s er I_ S ve LV _ d) W RB U F_ DB IT LE N Register 5.19: SPI_SLV_WRBUF_DLEN_REG (0x48) 31 0 24 0 0 0 0 0 0 23 0 0 0x0000000 Reset SPI_SLV_WRBUF_DBITLEN This equals to the bit length of data written into the slave buffer, minus one. (R/W) SP I_ (re se rv ed SL V_ ) RD BU F_ DB IT LE N Register 5.20: SPI_SLV_RDBUF_DLEN_REG (0x4C) 31 0 24 0 0 0 0 0 0 23 0 0 0x0000000 Reset SPI_SLV_RDBUF_DBITLEN This equals to the bit length of data read from the slave buffer, minus one. (R/W) SP I_ (re se rv ed SL V_ ) RD AT A_ BI T Register 5.21: SPI_SLV_RD_BIT_REG (0x64) 31 0 24 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_SLV_RDATA_BIT This equals to the bit length of data the master reads from the slave, minus one. (R/W) Register 5.22: SPI_Wn_REG (n: 0-15) (0x80+4*n) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_Wn_REG Data buffer. (R/W) Espressif Systems 101 ESP32 Technical Reference Manual V2.0 5. SPI Register 5.23: SPI_TX_CRC_REG (0xC0) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_TX_CRC_REG For SPI1, this contains the CRC32 value of 256 bits of data. (R/W) SP (re se I_ S rv T ed ) Register 5.24: SPI_EXT2_REG (0xF8) 31 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 Reset SPI_ST The current state of the SPI state machine: (RO) 0: idle state 1: preparation state 2: send command state 3: send data state 4: read data state 5: write data state 6: wait state 7: done state Espressif Systems 102 ESP32 Technical Reference Manual V2.0 5. SPI (re se r ve d) SP I_ SP DM I_ A_ SP DM CO I_ A_ N (re DM TX TIN se A_ _S UE SP rve RX TO I_ d) _S P TO SP OU P I_ T_ I SP ND DA T I_ S A SP OU CR _B I_ TD _BU UR O S UT C RS ST_ _E R_ T_ EN (re O BU EN F_ R se M ST rv O _ ed DE EN ) SP I_ SP AH I_ BM SP AH _R I_ BM S SP OU _F T I_ T_ IFO IN R _R ST _R (re ST se ST rv ed ) Register 5.25: SPI_DMA_CONF_REG (0x100) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 1 0 0 6 5 4 3 2 3 2 0 0 0 0 0 0 0 Reset SPI_DMA_CONTINUE This bit enables SPI DMA continuous data Tx/Rx mode. (R/W) SPI_DMA_TX_STOP When in continuous Tx/Rx mode, setting this bit stops sending data. (R/W) SPI_DMA_RX_STOP When in continuous Tx/Rx mode, setting this bit stops receiving data. (R/W) SPI_OUT_DATA_BURST_EN SPI DMA reads data from memory in burst mode. (R/W) SPI_INDSCR_BURST_EN SPI DMA reads descriptor in burst mode when writing data to the memory. (R/W) SPI_OUTDSCR_BURST_EN SPI DMA reads descriptor in burst mode when reading data from the memory. (R/W) SPI_OUT_EOF_MODE DMA out-EOF-flag generation mode. (R/W) 1: out-EOF-flag is generated when DMA has popped all data from the FIFO; 0: out-EOF-flag is generated when DMA has pushed all data to the FIFO. SPI_AHBM_RST reset SPI DMA AHB master. (R/W) SPI_AHBM_FIFO_RST This bit is used to reset SPI DMA AHB master FIFO pointer. (R/W) SPI_OUT_RST The bit is used to reset DMA out-FSM and out-data FIFO pointer. (R/W) SPI_IN_RST The bit is used to reset DMA in-DSM and in-data FIFO pointer. (R/W) 31 30 29 28 27 0 0 0 0 0 DR NK _A D LI UT ed ) SP I _O se rv (re (re se SP rve I_ d) SP OU I_ TL SP OU INK I_ TL _R O IN E UT K S LI _S TA NK TA RT _S RT TO P Register 5.26: SPI_DMA_OUT_LINK_REG (0x104) 20 0 0 0 0 0 0 19 0 0 0x000000 Reset SPI_OUTLINK_RESTART Set the bit to add new outlink descriptors. (R/W) SPI_OUTLINK_START Set the bit to start to use outlink descriptor. (R/W) SPI_OUTLINK_STOP Set the bit to stop to use outlink descriptor. (R/W) SPI_OUTLINK_ADDR The address of the first outlink descriptor. (R/W) Espressif Systems 103 ESP32 Technical Reference Manual V2.0 5. SPI 31 30 29 28 27 0 0 0 0 0 0 0 DD R _R ET TO 0 NK _A K_ AU SP SP I_ I_ IN LI IN LI N ) ed rv (re se (re se SP rve I_ d) SP INL I_ IN SP INL K_R I_ INK ES IN _ T LI S A NK TA RT _S RT TO P Register 5.27: SPI_DMA_IN_LINK_REG (0x108) 0 0 21 20 0 0 19 0 0x000000 Reset SPI_INLINK_RESTART Set the bit to add new inlink descriptors. (R/W) SPI_INLINK_START Set the bit to start to use inlink descriptor. (R/W) SPI_INLINK_STOP Set the bit to stop to use inlink descriptor. (R/W) SPI_INLINK_AUTO_RET when the bit is set, inlink descriptor jumps to the next descriptor when a packet is invalid. (R/W) SPI_INLINK_ADDR The address of the first inlink descriptor. (R/W) (re se rv e d) SP I_ SP DM I_ A_ DM T X A_ _E RX N _E N Register 5.28: SPI_DMA_STATUS_REG (0x10C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset SPI_DMA_TX_EN SPI DMA write-data status bit. (RO) SPI_DMA_RX_EN SPI DMA read-data status bit. (RO) Espressif Systems 104 ESP32 Technical Reference Manual V2.0 5. SPI (re s er ve d) SP I_ SP OU I_ T_ SP OU TO I_ T_ TA SP OU EO L_E I_ T_ F_ O SP IN_ DO INT F_I I_ SU NE _E NT SP IN_ C_ _IN NA _E NA I_ ER EO T SP IN_ R_ F_ _EN I_ DO EO IN A SP INL NE F_ T_E I_ IN _ IN N SP OU K_D INT T_E A I_ TL S _EN NA IN IN CR A LI K NK _D _E _D SC RR SC R_ OR R_ ER _IN EM RO T_ PT R_ EN Y_ IN A I N T_ T_ E N EN A A Register 5.29: SPI_DMA_INT_ENA_REG (0x110) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_TOTAL_EOF_INT interrupt. (R/W) SPI_OUT_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_EOF_INT interrupt. (R/W) SPI_OUT_DONE_INT_ENA The interrupt enable bit for the SPI_OUT_DONE_INT interrupt. (R/W) SPI_IN_SUC_EOF_INT_ENA The interrupt enable bit for the SPI_IN_SUC_EOF_INT interrupt. (R/W) SPI_IN_ERR_EOF_INT_ENA The interrupt enable bit for the SPI_IN_ERR_EOF_INT interrupt. (R/W) SPI_IN_DONE_INT_ENA The interrupt enable bit for the SPI_IN_DONE_INT interrupt. (R/W) SPI_INLINK_DSCR_ERROR_INT_ENA The interrupt enable bit for the for the for the SPI_INLINK_DSCR_ERROR_INT interrupt. (R/W) SPI_OUTLINK_DSCR_ERROR_INT_ENA The interrupt enable bit SPI_OUTLINK_DSCR_ERROR_INT interrupt. (R/W) SPI_INLINK_DSCR_EMPTY_INT_ENA The interrupt enable bit SPI_INLINK_DSCR_EMPTY_INT interrupt. (R/W) Espressif Systems 105 ESP32 Technical Reference Manual V2.0 5. SPI (re s er ve d) SP I_ SP OU I_ T_ SP OU TO I_ T_ TA SP OU EO L_E I_ T_ F_ O SP IN_ DO INT F_I I_ SU NE _R NT SP IN_ C_ _IN AW _R AW I_ ER EO T SP IN_ R_ F_ _RA I_ DO EO IN W SP INL NE F_ T_R I_ IN _ IN A SP OU K_D INT T_R W I_ TL S _R AW IN IN CR AW LI K NK _D _E _D SC RR SC R_ OR R_ ER _IN EM RO T_ PT R_ RA Y_ IN W IN T_ T_ R A RA W W Register 5.30: SPI_DMA_INT_RAW_REG (0x114) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_TOTAL_EOF_INT interrupt. (RO) SPI_OUT_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO) SPI_OUT_DONE_INT_RAW The raw interrupt status bit for the SPI_OUT_DONE_INT interrupt. (RO) SPI_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt. (RO) SPI_IN_ERR_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt. (RO) SPI_IN_DONE_INT_RAW The raw interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO) SPI_INLINK_DSCR_ERROR_INT_RAW The raw interrupt status bit for the for the for the SPI_INLINK_DSCR_ERROR_INT interrupt. (RO) SPI_OUTLINK_DSCR_ERROR_INT_RAW The raw interrupt status bit SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO) SPI_INLINK_DSCR_EMPTY_INT_RAW The raw interrupt status bit SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO) Espressif Systems 106 ESP32 Technical Reference Manual V2.0 5. SPI (re s er ve d) SP I_ SP OU I_ T_ SP OU TO I_ T_ TA SP OU EO L_E I_ T_ F_ O SP IN_ DO INT F_I I_ SU NE _S NT SP IN_ C_ _IN T _S T I_ ER EO T SP IN_ R_ F_ _ST I_ DO EO IN SP INL NE F_ T_S I_ IN _ IN T SP OU K_D INT T_S I_ TL S _ST T IN IN CR LI K NK _D _E _D SC RR SC R_ OR R_ ER _IN EM RO T_ PT R_ ST Y_ IN IN T_ T_ S T ST Register 5.31: SPI_DMA_INT_ST_REG (0x118) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_TOTAL_EOF_INT interrupt. (RO) SPI_OUT_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO) SPI_OUT_DONE_INT_ST The masked interrupt status bit for the SPI_OUT_DONE_INT interrupt. (RO) SPI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt. (RO) SPI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt. (RO) SPI_IN_DONE_INT_ST The masked interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO) SPI_INLINK_DSCR_ERROR_INT_ST The masked interrupt status bit for the for the for the SPI_INLINK_DSCR_ERROR_INT interrupt. (RO) SPI_OUTLINK_DSCR_ERROR_INT_ST The masked interrupt status bit SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO) SPI_INLINK_DSCR_EMPTY_INT_ST The masked interrupt status bit SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO) Espressif Systems 107 ESP32 Technical Reference Manual V2.0 5. SPI SP (re s er ve d) I_ SP OU I_ T_ SP OU TO I_ T_ TA SP OU EO L_E I_ T_ F_ O SP IN_ DO INT F_I I_ SU NE _C NT SP IN_ C_ _IN LR _C LR I_ ER EO T SP IN_ R_ F_ _CL I_ DO EO IN R SP INL NE F_ T_C I_ IN _ IN L SP OU K_D INT T_C R I_ TL S _C LR IN IN CR LR LI K NK _D _E _D SC RR SC R_ OR R_ ER _IN EM RO T_ PT R_ CL Y_ IN R IN T_ T_ C L CL R R Register 5.32: SPI_DMA_INT_CLR_REG (0x11C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUT_TOTAL_EOF_INT_CLR Set this bit to clear the SPI_OUT_TOTAL_EOF_INT interrupt. (R/W) SPI_OUT_EOF_INT_CLR Set this bit to clear the SPI_OUT_EOF_INT interrupt. (R/W) SPI_OUT_DONE_INT_CLR Set this bit to clear the SPI_OUT_DONE_INT interrupt. (R/W) SPI_IN_SUC_EOF_INT_CLR Set this bit to clear the SPI_IN_SUC_EOF_INT interrupt. (R/W) SPI_IN_ERR_EOF_INT_CLR Set this bit to clear the SPI_IN_ERR_EOF_INT interrupt. (R/W) SPI_IN_DONE_INT_CLR Set this bit to clear the SPI_IN_DONE_INT interrupt. (R/W) SPI_INLINK_DSCR_ERROR_INT_CLR Set this bit to clear the SPI_INLINK_DSCR_ERROR_INT interrupt. (R/W) SPI_OUTLINK_DSCR_ERROR_INT_CLR Set this bit to clear the SPI_OUTLINK_DSCR_ERROR_INT interrupt. (R/W) SPI_INLINK_DSCR_EMPTY_INT_CLR Set this bit to clear the SPI_INLINK_DSCR_EMPTY_INT interrupt. (R/W) Register 5.33: SPI_IN_ERR_EOF_DES_ADDR_REG (0x120) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_IN_ERR_EOF_DES_ADDR_REG The inlink descriptor address when SPI DMA encountered an error in receiving data. (RO) Register 5.34: SPI_IN_SUC_EOF_DES_ADDR_REG (0x124) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_IN_SUC_EOF_DES_ADDR_REG The last inlink descriptor address when SPI DMA encountered EOF. (RO) Espressif Systems 108 ESP32 Technical Reference Manual V2.0 5. SPI Register 5.35: SPI_INLINK_DSCR_REG (0x128) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 Reset 0 0 0 0 0 0 Reset 0 0 0 0 0 Reset SPI_INLINK_DSCR_REG The address of the current inlink descriptor. (RO) Register 5.36: SPI_INLINK_DSCR_BF0_REG (0x12C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_INLINK_DSCR_BF0_REG The address of the next inlink descriptor. (RO) Register 5.37: SPI_INLINK_DSCR_BF1_REG (0x130) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_INLINK_DSCR_BF1_REG The address of the next inlink data buffer. (RO) Register 5.38: SPI_OUT_EOF_BFR_DES_ADDR_REG (0x134) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_OUT_EOF_BFR_DES_ADDR_REG The buffer address corresponding to the outlink descriptor that produces EOF. (RO) Register 5.39: SPI_OUT_EOF_DES_ADDR_REG (0x138) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUT_EOF_DES_ADDR_REG The last outlink descriptor address when SPI DMA encountered EOF. (RO) Register 5.40: SPI_OUTLINK_DSCR_REG (0x13C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUTLINK_DSCR_REG The address of the current outlink descriptor. (RO) Espressif Systems 109 ESP32 Technical Reference Manual V2.0 5. SPI Register 5.41: SPI_OUTLINK_DSCR_BF0_REG (0x140) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SPI_OUTLINK_DSCR_BF0_REG The address of the next outlink descriptor. (RO) Register 5.42: SPI_OUTLINK_DSCR_BF1_REG (0x144) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 Reset SPI_OUTLINK_DSCR_BF1_REG The address of the next outlink data buffer. (RO) 30 29 0 0 0 d) _D E rv e TX se (re TX 31 S_ AD DR _F TX IFO _F _E IF M O P _F TY UL L ES S Register 5.43: SPI_DMA_RSTATUS_REG (0x148) 20 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_FIFO_EMPTY The SPI DMA Tx FIFO is empty. (RO) TX_FIFO_FULL The SPI DMA Tx FIFO is full. (RO) TX_DES_ADDRESS The LSB of the SPI DMA outlink descriptor address. (RO) 31 30 29 0 0 0 (re RX _D se r ve d ) ES _A DD RE RX _ RX FIFO _F _E IF M O P _F TY UL L SS Register 5.44: SPI_DMA_TSTATUS_REG (0x14C) 20 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RX_FIFO_EMPTY The SPI DMA Rx FIFO is empty. (RO) RX_FIFO_FULL The SPI DMA Rx FIFO is full. (RO) RX_DES_ADDRESS The LSB of the SPI DMA inlink descriptor address. (RO) Espressif Systems 110 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 6. SDIO Slave 6.1 Overview The ESP32 features hardware support for the industry-standard Secure Digital (SD) device interface that conforms to the SD Input/Output (SDIO) Specification Version 2.0. This allows a host controller to access the ESP32 via an SDIO bus protocol, enabling high-speed data transfer. The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via Direct Memory Access (DMA), thus reducing processing overhead while maintaining high performance. 6.2 Features • Meets SDIO V2.0 specification • Supports SDIO SPI, 1-bit, and 4-bit transfer modes • Full host clock range of 0 ~ 50 MHz • Configurable sample and drive clock edge • Integrated, SDIO-accessible registers for information interaction • Supports SDIO interrupt mechanism • Automatic data padding • Block size of up to 512 bytes • Interrupt vector between Host and Slave for bidirectional interrupt 6.3 Functional Description 6.3.1 SDIO Slave Block Diagram The functional block diagram of the SDIO slave module is shown in Figure 15. Figure 15: SDIO Slave Block Diagram The Host System represents any SDIO specification V2.0-compatible host device. The Host System interacts with the ESP32 (configured as the SDIO slave) via the standard SDIO bus implementation. The SDIO Device Interface block enables effective communication with the external Host by directly providing SDIO interface registers and enabling DMA operation for high-speed data transfer over the Advanced High-performance Bus (AHB) without engaging the CPU. Espressif Systems 111 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 6.3.2 Sending and Receiving Data on SDIO Bus Data is transmitted between Host and Slave through the SDIO bus I/O Function1. After the Host enables the I/O Function1 in the Slave, according to the SDIO protocol, data transmission will begin. ESP32 segregates data into packets sent to/from the Host. To achieve high bus utilization and data transfer rates, we recommend the single block transmission mode. For detailed information on this mode, please refer to the SDIO V2.0 protocol specification. When Host and Slave exchange data as blocks on the SDIO bus, the Slave automatically pads data-when sending data out-and automatically strips padding data from the incoming data block. Whether the Slave pads or discards the data depends on the data address on the SDIO bus. When the data address is equal to, or greater than, 0x1F800, the Slave will start padding or discarding data. Therefore, the starting data address should be 0x1F800 - Packet_length, where Packet_length is measured in bytes. Data flow on the SDIO bus is shown in Figure 16. Figure 16: SDIO Bus Packet Transmission The standard IO_RW_EXTENDED (CMD53) command is used to initiate a packet transfer of an arbitrary length. The content of the CMD53 command used in data transmission is as illustrated in Figure 17 below. For detailed information on CMD53, please refer to the SDIO protocol specifications. S D Command Index 11010b R/W Flag Function Number 001b Block Mode 1b OP Code 1b Register Address 0x1F800-Packet_length CRC7 E 1 1 6 1 3 1 1 17 7 1 Figure 17: CMD53 Content 6.3.3 Register Access For effective interaction between Host and Slave, the Host can access certain registers in the Slave via the SDIO bus I/O Function1. These registers are in continuous address fields from SLC0HOST_TOKEN_RDATA to SLCHOST_INF_ST. The Host device can access these registers by simply setting the register addresses of CMD52 or CMD53 to the low 10 bits of the corresponding register address. The Host can access several consecutive registers at one go with CMD53, thus achieving a higher effective transfer rate. There are 54 bytes of field between SLCHOST_CONF_W0_REG and SLCHOST_CONF_W15_REG. Host and Slave can access and change these fields, thus facilitating the information interaction between Host and Slave. Espressif Systems 112 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 6.3.4 DMA The SDIO Slave module uses dedicated DMA to access data residing in the RAM. As shown in Figure 15, the RAM is accessed over the AHB. DMA accesses RAM through a linked-list descriptor. Every linked list is composed of three words, as shown in Figure 18. Figure 18: SDIO Slave DMA Linked-List Structure • Owner: The allowed operator of the buffer that corresponds to the current linked list. 0: CPU is the allowed operator; 1: DMA is the allowed operator. • Eof: End-of-file marker, indicating that this linked-list element is the last element of the data packet. • Length: The number of valid bytes in the buffer, i.e., the number of bytes that should be accessed from the buffer for reading/writing. • Size: The maximum number of available buffers. • Buffer Address Pointer: The address of the data buffer as seen by the CPU (according to the RAM address space). • Next Descriptor Address: The address of the next linked-list element in the CPU RAM address space. If the current linked list is the last one, the Eof bit should be 1, and the last descriptor address should be 0. The Slave’s linked-list chain is shown in Figure 19: Figure 19: SDIO Slave’s Linked List Espressif Systems 113 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 6.3.5 Packet-Sending/-Receiving Procedure The SDIO Host and Slave devices need to follow specific data transfer procedures to successfully exchange data over the SDIO interface. 6.3.5.1 Sending Packets to SDIO Host The transmission of packets from Slave to Host is initiated by the Slave. The Host will be notified with an interrupt (for detailed information on interrupts, please refer to SDIO protocol). After the Host reads the relevant information from the Slave, it will initiate an SDIO bus transaction accordingly. The whole procedure is illustrated in Figure 20. Figure 20: Packet Sending Procedure (Initiated by Slave) When the Host is interrupted, it reads relevant information from the Slave by visiting registers SLC0HOST_INT and SLCHOST_PKT_LEN. Espressif Systems 114 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE • SLC0HOST_INT: Interrupt status register. If the value of SLC0_RX_NEW_PACKET_INT_ST is 1, this indicates that the Slave has a packet to send. • SLCHOST_PKT_LEN: Packet length accumulator register. The current value minus the value of last time equals the packet length sent this time. In order to start DMA, the CPU needs to write the low 20 bits of the address of the first linked-list element to the SLC0_RXLINK_ADDR bit of SLC0RX_LINK, then set the SLC0_RXLINK_START bit of SLC0RX_LINK. The DMA will automatically complete the data transfer. Upon completion of the operation, DMA will interrupt the CPU so that the buffer space can be freed or reused. 6.3.5.2 Receiving Packets from SDIO Host Transmission of packets from Host to Slave is initiated by the Host. The Slave receives data via DMA and stores it in RAM. After transmission is completed, the CPU will be interrupted to process the data. The whole procedure is demonstrated in Figure 21. Figure 21: Packet Receiving Procedure (Initiated by Host) The Host obtains the number of available receiving buffers from the Slave by accessing register SLC0HOST_TOKEN_RDATA. The Slave CPU should update this value after the receiving DMA linked list is prepared. HOSTREG_SLC0_TOKEN1 in SLC0HOST_TOKEN_RDATA stores the accumulated number of available buffers. The Host can figure out the available buffer space, using HOSTREG_SLC0_TOKEN1 minus the number of buffers already used. Espressif Systems 115 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE If the buffers are not enough, the Host needs to constantly poll the register until there are enough buffers available. To ensure sufficient receiving buffers, the Slave CPU must constantly load buffers on the receiving linked list. The process is shown in Figure 22. Figure 22: Loading Receiving Buffer The CPU first needs to append new buffer segments at the end of the linked list that is being used by DMA and is available for receiving data. The CPU then needs to notify the DMA that the linked list has been modified. This can be done by setting bit SLC0_TXLINK_RESTART of the SLC0TX_LINK register. Please note that when the CPU initiates DMA to receive packets for the first time, SLC0_TXLINK_RESTART should be set to 1. Lastly, the CPU refreshes any available buffer information by writing to the SLC0TOKEN1 register. 6.3.6 SDIO Bus Timing The SDIO bus operates at a very high speed and the PCB trace length usually affects signal integrity by introducing latency. To ensure that the timing characteristics conform to the desired bus timing, the SDIO Slave module supports configuration of input sampling clock edge and output driving clock edge. When the incoming data changes near the rising edge of the clock, the Slave will perform sampling on the falling edge of the clock, or vice versa, as Figure 23 shows. Figure 23: Sampling Timing Diagram Sampling edges are configured via the FRC_POS_SAMP and FRC_NEG_SAMP bitfields in the SLCHOST_CONF register. Each field is five bits wide, with bits corresponding to the CMD line and four DATA lines (0-3). Setting a bit in FRC_POS_SAMP causes the corresponding line to be sampled for input at the rising clock edge, whereas setting a bit in FRC_NEG_SAMP causes the corresponding line to be sampled for input at the falling clock edge. Espressif Systems 116 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE The Slave can also select the edge at which data output lines are driven to accommodate for any latency caused by the physical signal path, as shown in Figure 24. Figure 24: Output Timing Diagram Driving edges are configured via the FRC_SDIO20 and FRC_SDIO11 bitfields in the SLCHOST_CONF register. Each field is five bits wide, with bits corresponding to the CMD line and four DATA lines (0-3). Setting a bit in FRC_SDIO20 causes the corresponding line to output at the rising clock edge, whereas setting a bit in FRC_SDIO11 causes the corresponding line to output at the falling clock edge. 6.3.7 Interrupt Host and Slave can interrupt each other via the interrupt vector. Both Host and Slave have eight interrupt vectors. The interrupt is enabled by configuring the interrupt vector register (setting the enable bit to 1). The interrupt vector registers can clear themselves automatically, which means one interrupt at a time and no other configuration is required. 6.3.7.1 Host Interrupt • SLC0HOST_SLC0_RX_NEW_PACKET_INT Slave has a packet to send. • SLC0HOST_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt. • SLC0HOST_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt. • SLC0HOST_SLC0_TOHOST_BITn_INT (n: 0 ~ 7) Slave interrupts Host. 6.3.7.2 Slave Interrupt • SLC0INT_SLC0_RX_DSCR_ERR_INT Slave sending descriptor error. • SLC0INT_SLC0_TX_DSCR_ERR_INT Slave receiving descriptor error. • SLC0INT_SLC0_RX_EOF_INT Slave sending operation is finished. • SLC0INT_SLC0_RX_DONE_INT A single buffer is sent by Slave. • SLC0INT_SLC0_TX_SUC_EOF_INT Slave receiving operation is finished. • SLC0INT_SLC0_TX_DONE_INT A single buffer is finished during receiving operation. • SLC0INT_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt. • SLC0INT_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt. • SLC0INT_SLC0_TX_START_INT Slave receiving interrupt initialization. • SLC0INT_SLC0_RX_START_INT Slave sending interrupt initialization. Espressif Systems 117 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE • SLC0INT_SLC_FRHOST_BITn_INT (n: 0 ~ 7) Host interrupts Slave. 6.4 Register Summary Name Description Address Access SDIO DMA (SLC) configuration registers SLCCONF0_REG SLCCONF0_SLC configuration 0x3FF58000 R/W SLC0INT_RAW_REG Raw interrupt status 0x3FF58004 RO SLC0INT_ST_REG Interrupt status 0x3FF58008 RO SLC0INT_ENA_REG Interrupt enable 0x3FF5800C R/W SLC0INT_CLR_REG Interrupt clear 0x3FF58010 WO SLC0RX_LINK_REG Transmitting linked list configuration 0x3FF5803C R/W SLC0TX_LINK_REG Receiving linked list configuration 0x3FF58040 R/W SLCINTVEC_TOHOST_REG Interrupt sector for Slave to interrupt Host 0x3FF5804C WO SLC0TOKEN1_REG Number of receiving buffer 0x3FF58054 WO SLCCONF1_REG Control register 0x3FF58060 R/W SLC_RX_DSCR_CONF_REG DMA transmission configuration 0x3FF58098 R/W SLC0_LEN_CONF_REG Length control of the transmitting packets 0x3FF580E4 R/W SLC0_LENGTH_REG Length of the transmitting packets 0x3FF580E8 R/W Name Description Address Access SLC0HOST_INT_RAW_REG Raw interrupt 0x3FF55000 RO SLC0HOST_INT_ST_REG Masked interrupt status 0x3FF55058 RO SLCHOST_PKT_LEN_REG Length of the transmitting packets 0x3FF55060 RO SLCHOST_CONF_W0_REG Host and Slave communication register0 0x3FF5506C R/W SLCHOST_CONF_W1_REG Host and Slave communication register1 0x3FF55070 R/W SLCHOST_CONF_W2_REG Host and Slave communication register2 0x3FF55074 R/W SLCHOST_CONF_W3_REG Host and Slave communication register3 0x3FF55078 R/W SLCHOST_CONF_W4_REG Host and Slave communication register4 0x3FF5507C R/W SLCHOST_CONF_W6_REG Host and Slave communication register6 0x3FF55088 R/W SLCHOST_CONF_W7_REG Interrupt vector for Host to interrupt Slave 0x3FF5508C WO SLCHOST_CONF_W8_REG Host and Slave communication register8 0x3FF5509C R/W SLCHOST_CONF_W9_REG Host and Slave communication register9 0x3FF550A0 R/W SLCHOST_CONF_W10_REG Host and Slave communication register10 0x3FF550A4 R/W SLCHOST_CONF_W11_REG Host and Slave communication register11 0x3FF550A8 R/W SLCHOST_CONF_W12_REG Host and Slave communication register12 0x3FF550AC R/W SLCHOST_CONF_W13_REG Host and Slave communication register13 0x3FF550B0 R/W SLCHOST_CONF_W14_REG Host and Slave communication register14 0x3FF550B4 R/W SLCHOST_CONF_W15_REG Host and Slave communication register15 0x3FF550B8 R/W SLC0HOST_INT_CLR_REG Interrupt clear 0x3FF550D4 WO SLC0HOST_FUNC1_INT_ENA_REG Interrupt enable 0x3FF550DC R/W SLCHOST_CONF_REG Edge configuration 0x3FF551F0 R/W SDIO SLC Host registers Espressif Systems 118 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE Name Description Address Access SDIO specification configuration 0x3FF4B004 R/W SDIO HINF registers HINF_CFG_DATA1_REG Espressif Systems 119 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 6.5 SLC Registers The first block of SDIO control registers starts at 0x3FF5_8000. 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ed ) rv se (re SL (re s er CC O ve d) NF 0 _S LC 0_ TO KE N_ A UT O _C LR SL C SL CO C NF SL CO 0_ CC NF SL O 0_S C0_ N (re L R se F0_ C0 X_ SL _R AU rv ed C0 X_ TO SL ) _T LO _W CC X_ O R SL O LO P_ BA CC NF O TES CK P_ T O 0_S NF L TE 0_ C0 ST SL _R C0 X_ _T RS X_ T RS T Register 6.1: SLCCONF0_REG (0x0) 15 14 13 0 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 Reset SLCCONF0_SLC0_TOKEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W) SLCCONF0_SLC0_RX_AUTO_WRBACK Allows changing the owner bit of the transmitting buffer’s linked list when transmitting data. (R/W) SLCCONF0_SLC0_RX_LOOP_TEST Loop around when the slave buffer finishes sending packets. When set to 1, hardware will not change the owner bit in the linked list. (R/W) SLCCONF0_SLC0_TX_LOOP_TEST Loop around when the slave buffer finishes receiving packets. When set to 1, hardware will not change the owner bit in the linked list. (R/W) SLCCONF0_SLC0_RX_RST Set this bit to reset the transmitting FSM. (R/W) SLCCONF0_SLC0_TX_RST Set this bit to reset the receiving FSM. (R/W) Espressif Systems 120 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 SL C SL 0IN C0 T_ (re IN SL se T_ C0 SL rve SL _R C d) C0 X_D _T S SL 0IN X_ C C0 T_ DS R_ S SL IN L CR ER C0 T_ C0 _E R_I SL IN SL _R RR NT C0 T_ C0 X_E _I _R IN SL _R OF NT A T_ C0 X_ _ (re _R W I D SL _T O NT se AW C0 X_ N _R rv ed _T SU E_I AW SL ) N C X_ _ T C DO EO _R SL 0IN NE F_ AW T C0 _ _I INT SL IN SL NT _ C0 T_ C0 _R RA _ S SL IN L TX AW W C T C _ 0 _O SL 0IN SL _R VF C T_ C0 X_ _I SL 0IN SL _TX UD NT_ C T_ C0 _S F_ R SL 0IN SL _R TA INT AW C T_ C_ X_ RT _R SL 0IN SL FRH STA _IN AW C T_ C_ O R T SL 0IN SL FRH ST T_IN _RA C T_ C_ O _B T W SL 0IN SL FRH ST IT7 _RA C T_ C_ O _B _IN W SL 0IN SL FRH ST IT6 T_ C T_ C_ O _B _IN RA SL 0IN SL FRH ST IT5 T_ W C0 T_ C_ O _B _IN RA IN SL FRH ST IT4 T_ W T_ C_ O _B _I R SL FR S IT NT AW C_ HO T_B 3_ _R FR S IT INT AW HO T_B 2_ _R ST IT1 INT AW _ B _I _R IT NT AW 0_ _R IN A T_ W RA W (re (re s se er ve rv ed ) d) Register 6.2: SLC0INT_RAW_REG (0x4) 27 0x00 26 0 0 0 0 0 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave sending descriptor error (RO) SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave receiving descriptor error. (RO) SLC0INT_SLC0_RX_EOF_INT_RAW The interrupt mark bit when Slave sending operation is finished. (RO) SLC0INT_SLC0_RX_DONE_INT_RAW The raw interrupt bit to mark single buffer as sent by Slave. (RO) SLC0INT_SLC0_TX_SUC_EOF_INT_RAW The raw interrupt bit to mark Slave receiving operation as finished. (RO) SLC0INT_SLC0_TX_DONE_INT_RAW The raw interrupt bit to mark a single buffer as finished during Slave receiving operation. (RO) SLC0INT_SLC0_TX_OVF_INT_RAW The raw interrupt bit to mark Slave receiving buffer overflow. (RO) SLC0INT_SLC0_RX_UDF_INT_RAW The raw interrupt bit for Slave sending buffer underflow. (RO) SLC0INT_SLC0_TX_START_INT_RAW The raw interrupt bit for registering Slave receiving initialization interrupt. (RO) SLC0INT_SLC0_RX_START_INT_RAW The raw interrupt bit to mark Slave sending initialization interrupt. (RO) SLC0INT_SLC_FRHOST_BIT7_INT_RAW The interrupt mark bit 7 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT6_INT_RAW The interrupt mark bit 6 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT5_INT_RAW The interrupt mark bit 5 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT4_INT_RAW The interrupt mark bit 4 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT3_INT_RAW The interrupt mark bit 3 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT2_INT_RAW The interrupt mark bit 2 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT1_INT_RAW The interrupt mark bit 1 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT0_INT_RAW The interrupt mark bit 0 for Host to interrupt Slave. (RO) Espressif Systems 121 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 SL C SL 0IN C0 T_ (re IN SL se T_ C0 SL rve SL _R C d) C0 X_D _T S SL 0IN X_ C C0 T_ DS R_ S SL IN L CR ER C0 T_ C0 _E R_I SL IN SL _R RR NT C0 T_ C0 X_E _I _S IN SL _R OF NT T T_ C0 X_ _ (re _S I D SL _T O NT se T C0 X_ N _S rv E ed _T SU _I T SL ) N C X_ _ T C DO EO _S SL 0IN NE F_ T T C0 _ _I INT SL IN SL NT _ C0 T_ C0 _S S T _ S SL IN L TX T C T C _ 0 _O SL 0IN SL _R VF C T_ C0 X_ _I SL 0IN SL _TX UD NT_ C T_ C0 _S F_ S SL 0IN SL _R TA INT T C T_ C_ X_ RT _S SL 0IN SL FRH STA _IN T C T_ C_ O R T SL 0IN SL FRH ST T_IN _ST C T_ C_ O _B T SL 0IN SL FRH ST IT7 _ST C T_ C_ O _B _IN SL 0IN SL FRH ST IT6 T_ C T_ C_ O _B _IN ST SL 0IN SL FRH ST IT5 T_ C0 T_ C_ O _B _IN ST IN SL FRH ST IT4 T_ T_ C_ O _B _I S SL FR S IT NT T C_ HO T_B 3_ _S FR S IT INT T HO T_B 2_ _S ST IT1 INT T _B _I _S IT NT T 0_ _S IN T T_ ST (re s (re se er ve rv ed d) ) Register 6.3: SLC0INT_ST_REG (0x8) 27 0x00 26 0 0 0 0 0 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SLC0INT_SLC0_RX_DSCR_ERR_INT_ST The interrupt status bit for Slave sending descriptor error. (RO) SLC0INT_SLC0_TX_DSCR_ERR_INT_ST The interrupt status bit for Slave receiving descriptor error. (RO) SLC0INT_SLC0_RX_EOF_INT_ST The interrupt status bit for finished Slave sending operation. (RO) SLC0INT_SLC0_RX_DONE_INT_ST The interrupt status bit for finished Slave sending operation. (RO) SLC0INT_SLC0_TX_SUC_EOF_INT_ST The interrupt status bit for marking Slave receiving operation as finished. (RO) SLC0INT_SLC0_TX_DONE_INT_ST The interrupt status bit for marking a single buffer as finished during the receiving operation. (RO) SLC0INT_SLC0_TX_OVF_INT_ST The interrupt status bit for Slave receiving overflow interrupt. (RO) SLC0INT_SLC0_RX_UDF_INT_ST The interrupt status bit for Slave sending buffer underflow. (RO) SLC0INT_SLC0_TX_START_INT_ST The interrupt status bit for Slave receiving interrupt initialization. (RO) SLC0INT_SLC0_RX_START_INT_ST The interrupt status bit for Slave sending interrupt initialization. (RO) SLC0INT_SLC_FRHOST_BIT7_INT_ST The interrupt status bit 7 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT6_INT_ST The interrupt status bit 6 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT5_INT_ST The interrupt status bit 5 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT4_INT_ST The interrupt status bit 4 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT3_INT_ST The interrupt status bit 3 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT2_INT_ST The interrupt status bit 2 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT1_INT_ST The interrupt status bit 1 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT0_INT_ST The interrupt status bit 0 for Host to interrupt Slave. (RO) Espressif Systems 122 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 SL C SL 0IN C0 T_ (re IN SL se T_ C0 SL rve SL _R C d) C0 X_D _T S SL 0IN X_ C C0 T_ DS R_ S SL IN L CR ER C0 T_ C0 _E R_I SL IN SL _R RR NT C0 T_ C0 X_E _I _E IN SL _R OF NT N T_ C0 X_ _ (re _E A I D SL _T O NT se NA C0 X_ N _E rv ed SU E_ N _ SL TX C IN A ) C _ D _E T_ O O EN SL 0IN NE F_ A T C0 _ _I INT S SL IN L NT _ C0 T_ C0 _E E N _ S SL IN L TX NA A C T C _ 0 _O SL 0IN SL _R VF C T_ C0 X_ _I SL 0IN SL _TX UD NT_ C T_ C0 _S F_ E SL 0IN SL _R TA INT NA C T_ C_ X_ RT _E SL 0IN SL FRH STA _IN NA C T_ C_ O R T SL 0IN SL FRH ST T_IN _EN C T_ C_ O _B T A SL 0IN SL FRH ST IT7 _EN C T_ C_ O _B _IN A SL 0IN SL FRH ST IT6 T_ C T_ C_ O _B _IN EN SL 0IN SL FRH ST IT5 T_ A C0 T_ C_ O _B _IN EN IN SL FRH ST IT4 T_ A T_ C_ O _B _I EN SL FR S IT NT A C_ HO T_B 3_ _E FR S IT INT NA HO T_B 2_ _E ST IT1 INT NA _B _I _E IT NT NA 0_ _E IN N T_ A EN A (re (re s se er rv ve ed ) d) Register 6.4: SLC0INT_ENA_REG (0xC) 27 0x00 26 0 0 0 0 0 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SLC0INT_SLC0_RX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave sending linked list descriptor error. (R/W) SLC0INT_SLC0_TX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave receiving linked list descriptor error. (R/W) SLC0INT_SLC0_RX_EOF_INT_ENA The interrupt enable bit for Slave sending operation completion. (R/W) SLC0INT_SLC0_RX_DONE_INT_ENA The interrupt enable bit for single buffer’s sent interrupt, in Slave sending mode. (R/W) SLC0INT_SLC0_TX_SUC_EOF_INT_ENA The interrupt enable bit for Slave receiving operation completion. (R/W) SLC0INT_SLC0_TX_DONE_INT_ENA The interrupt enable bit for single buffer’s full event, in Slave receiving mode. (R/W) SLC0INT_SLC0_TX_OVF_INT_ENA The interrupt enable bit for Slave receiving buffer overflow. (R/W) SLC0INT_SLC0_RX_UDF_INT_ENA The interrupt enable bit for Slave sending buffer underflow. (R/W) SLC0INT_SLC0_TX_START_INT_ENA The interrupt enable bit for Slave receiving operation initialization. (R/W) SLC0INT_SLC0_RX_START_INT_ENA The interrupt enable bit for Slave sending operation initialization. (R/W) SLC0INT_SLC_FRHOST_BIT7_INT_ENA The interrupt enable bit 7 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT6_INT_ENA The interrupt enable bit 6 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT5_INT_ENA The interrupt enable bit 5 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT4_INT_ENA The interrupt enable bit 4 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT3_INT_ENA The interrupt enable bit 3 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT2_INT_ENA The interrupt enable bit 2 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT1_INT_ENA The interrupt enable bit 1 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT0_INT_ENA The interrupt enable bit 0 for Host to interrupt Slave. (R/W) Espressif Systems 123 ESP32 Technical Reference Manual V2.0 31 27 0x00 SL C SL 0IN C0 T_ (re IN SL se T_ C0 SL rve SL _R C d) C0 X_D _T S SL 0IN X_ C C0 T_ DS R_ S SL IN L CR ER C0 T_ C0 _E R_I SL IN SL _R RR NT C0 T_ C0 X_E _I _C IN SL _R OF NT LR T_ C0 X_ _ (re _C I D SL _T O NT se LR C0 X_ N _C rv E ed _T SU _I LR SL ) N C X_ _ T C DO EO _C SL 0IN NE F_ LR T C0 _ _I INT SL IN SL NT _ C0 T_ C0 _C CL _ S SL IN L TX LR R C T C _ 0 _O SL 0IN SL _R VF C T_ C0 X_ _I SL 0IN SL _TX UD NT_ C T_ C0 _S F_ C SL 0IN SL _R TA INT LR C T_ C_ X_ RT _C SL 0IN SL FRH STA _IN LR C T_ C_ O R T SL 0IN SL FRH ST T_IN _CL C T_ C_ O _B T R SL 0IN SL FRH ST IT7 _CL C T_ C_ O _B _IN R SL 0IN SL FRH ST IT6 T_ C T_ C_ O _B _IN C SL 0IN SL FRH ST IT5 T_ LR C0 T_ C_ O _B _IN CL IN SL FRH ST IT4 T_ R T_ C_ O _B _I C SL FR S IT NT LR C_ HO T_B 3_ _C FR S IT INT LR HO T_B 2_ _C ST IT1 INT LR _B _I _C IT NT LR 0_ _C IN L T_ R CL R (re (re se se rv ed rv ed ) ) Register 6.5: SLC0INT_CLR_REG (0x10) 26 0 0 0 0 0 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave sending linked list descriptor error. (WO) SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave receiving linked list descriptor error. (WO) SLC0INT_SLC0_RX_EOF_INT_CLR Interrupt clear bit for Slave sending operation completion. (WO) SLC0INT_SLC0_RX_DONE_INT_CLR Interrupt clear bit for single buffer’s sent interrupt, in Slave sending mode. (WO) SLC0INT_SLC0_TX_SUC_EOF_INT_CLR Interrupt clear bit for Slave receiving operation completion. (WO) SLC0INT_SLC0_TX_DONE_INT_CLR Interrupt clear bit for single buffer’s full event, in Slave receiving mode. (WO) SLC0INT_SLC0_TX_OVF_INT_CLR Set this bit to clear the Slave receiving overflow interrupt. (WO) SLC0INT_SLC0_RX_UDF_INT_CLR Set this bit to clear the Slave sending underflow interrupt. (WO) SLC0INT_SLC0_TX_START_INT_CLR Set this bit to clear the interrupt for Slave receiving operation initialization. (WO) SLC0INT_SLC0_RX_START_INT_CLR Set this bit to clear the interrupt for Slave sending operation initialization. (WO) SLC0INT_SLC_FRHOST_BIT7_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT7_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT6_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT6_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT5_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT5_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT4_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT4_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT3_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT3_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT2_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT2_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT1_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT1_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT0_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT0_INT interrupt. (WO) 6. SDIO SLAVE 31 30 29 28 27 0 0 0 0 0 SL C0 R X_ S LC 0_ RX LI NK _A DD R (re se SL rve C d) SL 0RX C _ SL 0RX SLC C0 _S 0_ RX LC RX _S 0_ LIN LC RX K 0_ LIN _R RX K ES LI _S TA NK TA RT _S RT (re TO se P rv ed ) Register 6.6: SLC0RX_LINK_REG (0x3C) 20 0 0 0 0 0 0 19 0 0 0x000000 Reset SLC0RX_SLC0_RXLINK_RESTART Set this bit to restart and continue the linked list operation for sending packets. (R/W) SLC0RX_SLC0_RXLINK_START Set this bit to start the linked list operation for sending packets. Sending will start from the address indicated by SLC0_RXLINK_ADDR. (R/W) SLC0RX_SLC0_RXLINK_STOP Set this bit to stop the linked list operation. (R/W) SLC0RX_SLC0_RXLINK_ADDR The lowest 20 bits in the initial address of Slave’s sending linked list. (R/W) (re SL C0 TX _S LC 0 _T XL I NK _A DD R se SL rve C d) SL 0TX C _S SL 0TX LC C0 _S 0_ TX LC TX _S 0_ LIN LC TX K_ 0_ LIN RE TX K S LI _S TA NK TA RT _S RT (re TO se P rv ed ) Register 6.7: SLC0TX_LINK_REG (0x40) 31 30 29 28 27 0 0 0 0 0 20 0 0 0 0 0 0 19 0 0 0x000000 Reset SLC0TX_SLC0_TXLINK_RESTART Set this bit to restart and continue the linked list operation for receiving packets. (R/W) SLC0TX_SLC0_TXLINK_START Set this bit to start the linked list operation for receiving packets. Receiving will start from the address indicated by SLC0_TXLINK_ADDR. (R/W) SLC0TX_SLC0_TXLINK_STOP Set this bit to stop the linked list operation for receiving packets. (R/W) SLC0TX_SLC0_TXLINK_ADDR The lowest 20 bits in the initial address of Slave’s receiving linked list. (R/W) Espressif Systems 125 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 0x000 23 0 16 0 0 0 0 EC _S CI NT V ed ) SL se rv (re (re (re se se rv rv ed ed ) ) LC 0_ TO HO ST _I NT V EC Register 6.8: SLCINTVEC_TOHOST_REG (0x4C) 0 0 15 8 0 7 0 0x000 0x000 Reset SLCINTVEC_SLC0_TOHOST_INTVEC The interrupt vector for Slave to interrupt Host. (WO) 27 0x00 O _T TO C0 0_ 15 14 13 12 0 0 0 0 SL C0 TO KE N1 _S L (re se SL rve C0 d) T (re OK EN se 1_ rv ed SL ) C 16 0x0000 KE N1 KE N1 KE _T O LC 0 KE N1 _S 28 SL C0 TO (re se rv ed ) 31 N1 _I NC _W DA TA _M O RE Register 6.9: SLC0TOKEN1_REG (0x54) 11 0 0x0000 Reset SLC0TOKEN1_SLC0_TOKEN1 The accumulated number of buffers for receiving packets. (RO) SLC0TOKEN1_SLC0_TOKEN1_INC_MORE Set this bit to add the value of SLC0TOKEN1_SLC0_TOKEN1_WDATA to that of SLC0TOKEN1_SLC0_TOKEN1. (WO) SLC0TOKEN1_SLC0_TOKEN1_WDATA The number of available receiving buffers. (WO) Espressif Systems 126 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE ed ) d) 23 0x000 (re (re s se er rv ve d) ve er (re s 31 22 0 16 0 0 0 SL C SL CO C NF SL CO 1_ CC NF SL O 1_S C0_ NF L R 1_ C0 X_ SL _T ST C0 X_ ITC _L ST H EN ITC _E _A H N UT _EN O _C LR Register 6.10: SLCCONF1_REG (0x60) 0 0 15 0 0 0 0 0 0 0 0 0 7 6 5 4 0 1 1 1 Reset SLCCONF1_SLC0_RX_STITCH_EN Please initialize to 0. Do not modify it. (R/W) SLCCONF1_SLC0_TX_STITCH_EN Please initialize to 0. Do not modify it. (R/W) SLCCONF1_SLC0_LEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W) (re se r ve SL C_ SL d) C0 _T O KE N_ NO _R EP LA CE Register 6.11: SLC_RX_DSCR_CONF_REG (0x98) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset SLC_SLC0_TOKEN_NO_REPLACE Please initialize to 1. Do not modify it. (R/W) 31 29 0x0 0 0 0 0 0 _L EN _W DA TA E se N_I NC rv ed _M ) O SL C0 _L C0 28 (re SL (re se r (re se rv ve d ) ed ) RE Register 6.12: SLC0_LEN_CONF_REG (0xE4) 23 22 21 20 0 0 0 0 19 0 0x000000 Reset SLC0_LEN_INC_MORE Set this bit to add the value of SLC0_LEN to that of SLC0_LEN_WDATA. (WO) SLC0_LEN_WDATA The packet length sent. (WO) Espressif Systems 127 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE (re SL se rv ed C0 _L E ) N Register 6.13: SLC0_LENGTH_REG (0xE8) 31 20 19 0 0x0000 0x000000 Reset SLC0_LEN Indicates the packet length sent by the Slave. (RO) 6.6 SLC Host Registers The second block of SDIO control registers starts at 0x3FF5_5000. Espressif Systems 128 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 26 0x00 25 24 23 22 0 0 0 0 0 ) ed rv (re se ve d) C0 HO ST SL (re s (re s er er ve d) _S LC 0_ R X_ NE W SL C SL 0HO C S SL 0HO T_S C S L SL 0HO T_S C0_ C0 S LC TO SL HO T_S 0_ H C S L T OS SL 0HO T_S C0_ OH T_ C S L T OS BIT SL 0HO T_S C0_ OH T_ 7_ C S L T OS BIT IN SL 0HO T_S C0_ OH T_ 6_ T_R C0 S LC TO OS BIT INT AW HO T_S 0_ H T_ 5_ _R ST LC TO OST BIT INT AW _S 0_ HO _B 4_I _R LC TO S IT NT AW 0_ HO T_B 3_I _R TO S IT NT AW HO T_B 2_ _R ST IT1 INT AW _B _I _R IT NT AW 0_ _R IN A T_ W _P AC SL KE C0 T_ SL HO IN T_ C0 S RA HO T_S W ST LC _S 0_ LC TX 0_ _O RX VF _U _IN DF T_ (re se _I RA NT W rv ed _R ) AW Register 6.14: SLC0HOST_INT_RAW_REG (0x50) 0 0 18 17 16 15 0 0 0 0 0 0 0 SLC0HOST_SLC0_RX_NEW_PACKET_INT_RAW The 0 raw 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Reset interrupt status bit for the SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO) SLC0HOST_SLC0_TX_OVF_INT_RAW The raw interrupt status bit for the interrupt status bit for the SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO) SLC0HOST_SLC0_RX_UDF_INT_RAW The raw SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT7_INT_RAW The raw interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT6_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT5_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT4_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW The raw SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO) Espressif Systems 129 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 26 0x00 25 24 23 22 0 0 0 0 0 d) ve er 0 SL (re s (re (re s se rv ed ) er ve d) SL C0 HO ST _S LC 0_ R X_ NE W _P AC SL C SL 0HO C S SL 0HO T_S C S L SL 0HO T_S C0_ C0 S LC TO SL HO T_S 0_ H C S L T OS SL 0HO T_S C0_ OH T_ C S L T OS BIT SL 0HO T_S C0_ OH T_ 7_ C S L T OS BIT IN SL 0HO T_S C0_ OH T_ 6_ T_S C0 S LC TO OS BIT INT T HO T_S 0_ H T_ 5_ _S ST LC TO OST BIT INT T _S 0_ HO _B 4_I _S LC TO S IT NT T 0_ HO T_B 3_I _S TO S IT NT T HO T_B 2_ _S ST IT1 INT T _B _I _S IT NT T 0_ _S IN T T_ KE C0 T_ SL HO IN T_ C0 S ST HO T_S ST LC _S 0 _ LC TX 0_ _O RX VF _U _IN DF T_ (re se _I ST NT rv ed _S ) T Register 6.15: SLC0HOST_INT_ST_REG (0x58) 0 18 17 16 15 0 0 0 0 0 0 SLC0HOST_SLC0_RX_NEW_PACKET_INT_ST The 0 0 0 masked 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Reset interrupt status bit for the SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO) SLC0HOST_SLC0_TX_OVF_INT_ST The masked interrupt status bit for the interrupt status bit for the SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO) SLC0HOST_SLC0_RX_UDF_INT_ST The masked SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT7_INT_ST The masked interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the interrupt status bit for the SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT6_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT5_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT4_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT3_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT2_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT1_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT0_INT_ST The masked SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO) Espressif Systems 130 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE SL SL CH CH O O ST ST _H O _H O ST ST RE G RE G _S _S LC 0 LC 0_ LE _L EN N _C H EC K Register 6.16: SLCHOST_PKT_LEN_REG (0x60) 31 20 19 0 0x000 0x000 SLCHOST_HOSTREG_SLC0_LEN_CHECK Its value is Reset HOSTREG_SLC0_LEN[9:0] plus HOSTREG_SLC0_LEN[19:10]. (RO) SLCHOST_HOSTREG_SLC0_LEN The accumulated value of the data length sent by the Slave. The value gets updated only when the Host reads it. 23 0x000 0 _C O O 16 15 0x000 SL CH SL CH O O ST ST _C _C O ST O SL CH 24 NF NF 2 NF 3 NF O ST _C O CH SL 31 1 Register 6.17: SLCHOST_CONF_W0_REG (0x6C) 8 0x000 7 0 0x000 Reset SLCHOST_CONF3 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF2 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 131 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 23 16 0x000 4 _C O NF NF 5 ST _C O CH O ST SL SL CH O SL CH SL CH O O ST ST _C O _C O NF 6 NF 7 Register 6.18: SLCHOST_CONF_W1_REG (0x70) 15 0x000 8 7 0x000 0 0x000 Reset SLCHOST_CONF7 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF6 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF5 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF4 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) 31 24 23 0x000 8 9 NF NF _C O O _C ST ST O O 16 15 0x000 SL CH SL CH SL SL CH CH O O ST _C O ST _C O NF NF 11 10 Register 6.19: SLCHOST_CONF_W2_REG (0x74) 8 0x000 7 0 0x000 Reset SLCHOST_CONF11 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF10 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 132 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE SL CH SL CH O ST _C O O ST _C O NF 1 4 NF 15 Register 6.20: SLCHOST_CONF_W3_REG (0x78) 31 24 23 0x000 16 0x000 Reset SLCHOST_CONF15 The information interaction register between Host and Slave. Both Host and Slave can be read from and written to this. (R/W) SLCHOST_CONF14 The information interaction register between Host and Slave. Both Host and Slave can be read from and written to this. (R/W) SL CH SL CH O O ST ST _C _C O O NF NF 19 18 Register 6.21: SLCHOST_CONF_W4_REG (0x7C) 31 24 23 0x000 16 0x000 Reset SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 133 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 23 0x000 4 NF 2 5 _C O NF 2 ST _C O CH O ST 16 SL SL CH O SL SL CH CH O ST _C O O ST _C O NF 27 NF 26 Register 6.22: SLCHOST_CONF_W6_REG (0x88) 15 8 0x000 7 0x000 0 0x000 Reset SLCHOST_CONF27 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF26 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF25 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF24 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) 31 0 24 0 0 0 0 0 0 23 0 16 0x000 rv ed ) ST O (re se CH SL (re SL se r CH O ve d) ST _C _C O O NF NF 31 29 Register 6.23: SLCHOST_CONF_W7_REG (0x8C) 15 0 8 0 0 0 0 0 0 0 7 0 0x000 Reset SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared automatically. (WO) SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared automatically. (WO) Espressif Systems 134 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 23 16 0x000 2 NF 3 3 _C O NF 3 ST _C O CH O ST SL SL CH O SL SL CH CH O ST _C O O ST _C O NF 35 NF 34 Register 6.24: SLCHOST_CONF_W8_REG (0x9C) 15 0x000 8 7 0x000 0 0x000 Reset SLCHOST_CONF35 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF34 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) 23 0x000 36 _C O O 16 15 0x000 SL SL CH CH O O ST ST _C ST _C O O CH SL 24 NF NF 38 NF 39 NF O _C ST O CH SL 31 37 Register 6.25: SLCHOST_CONF_W9_REG (0xA0) 8 0x000 7 0 0x000 Reset SLCHOST_CONF39 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF38 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF37 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF36 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 135 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 23 0x000 0 NF 4 1 _C O NF 4 ST _C O CH O ST 16 SL SL CH O SL SL CH CH O ST _C O O ST _C O NF 43 NF 42 Register 6.26: SLCHOST_CONF_W10_REG (0xA4) 15 0x000 8 7 0x000 0 0x000 Reset SLCHOST_CONF43 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF42 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) 23 0x000 44 _C O O 16 15 0x000 SL SL CH CH O O ST ST _C ST _C O O CH SL 24 NF NF 46 NF 47 NF O _C ST O CH SL 31 45 Register 6.27: SLCHOST_CONF_W11_REG (0xA8) 8 0x000 7 0 0x000 Reset SLCHOST_CONF47 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF46 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF45 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF44 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 136 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 23 0x000 8 NF 4 9 _C O NF 4 ST _C O CH O ST 16 SL SL CH O SL SL CH CH O ST _C O O ST _C O NF 51 NF 50 Register 6.28: SLCHOST_CONF_W12_REG (0xAC) 15 0x000 8 7 0x000 0 0x000 Reset SLCHOST_CONF51 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF50 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) 23 0x000 52 _C O O 16 15 0x000 SL SL CH CH O O ST ST _C ST _C O O CH SL 24 NF NF 54 NF 55 NF O _C ST O CH SL 31 53 Register 6.29: SLCHOST_CONF_W13_REG (0xB0) 8 0x000 7 0 0x000 Reset SLCHOST_CONF55 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF54 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF53 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF52 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 137 ESP32 Technical Reference Manual V2.0 6. SDIO SLAVE 31 24 23 0x000 6 NF 5 7 _C O NF 5 ST _C O CH O ST 16 SL SL CH O SL SL CH CH O ST _C O O ST _C O NF 59 NF 58 Register 6.30: SLCHOST_CONF_W14_REG (0xB4) 15 0x000 8 7 0x000 0 0x000 Reset SLCHOST_CONF59 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF58 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) 23 0x000 60 _C O O 16 15 0x000 SL SL CH CH O O ST ST _C ST _C O O CH SL 24 NF NF 62 NF 63 NF O _C ST O CH SL 31 61 Register 6.31: SLCHOST_CONF_W15_REG (0xB8) 8 0x000 7 0 0x000 Reset SLCHOST_CONF63 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF62 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems 138 ESP32 Technical Reference Manual V2.0 31 26 0x00 d) ve ve d) C0 HO ST _S 25 24 23 22 0 0 0 0 0 er (re s SL (re (re s se er rv ed ) LC 0_ RX _N E W _P AC SL C SL 0HO C S SL 0HO T_S C S L SL 0HO T_S C0_ C 0 S LC TO SL HO T_S 0_ H C S L T OS SL 0HO T_S C0_ OH T_ C S L T OS BIT SL 0HO T_S C0_ OH T_ 7_ C S L T OS BIT IN SL 0HO T_S C0_ OH T_ 6_ T_C C0 S LC TO OS BIT INT LR HO T_S 0_ H T_ 5_ _C ST LC TO OST BIT INT LR _S 0_ HO _B 4_I _C LC TO S IT NT LR 0_ HO T_B 3_I _C TO S IT NT LR HO T_B 2_ _C ST IT1 INT LR _B _I _C IT NT LR 0_ _C IN L T_ R SL KE C0 T_ SL HO IN T_ C0 S CL HO T_S R ST LC _S 0 _ LC TX 0_ _O RX VF _U _IN DF T_ (re se _I CL NT R rv ed _C ) LR Register 6.32: SLC0HOST_INT_CLR_REG (0xD4) 0 0 18 17 16 15 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Reset SLC0HOST_SLC0_RX_NEW_PACKET_INT_CLR Set this bit to clear the SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (WO) SLC0HOST_SLC0_TX_OVF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TX_OVF_INT interrupt. (WO) SLC0HOST_SLC0_RX_UDF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_RX_UDF_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT7_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT6_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT5_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT4_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (WO) 31 26 0x00 25 24 23 22 0 0 0 0 0 d) ve er 0 SL (re s (re s (re s er ve d) er ve d) SL C0 HO ST _F N1 _S LC 0_ RX _N E SL C SL 0HO C0 S SL HO T_F C S N SL 0HO T_F 1_S C 0 S N LC SL HO T_F 1_S 0_ C S N L TO SL 0HO T_F 1_S C0_ HO C S N L TO S SL 0HO T_F 1_S C0_ HO T_B C S N L TO S IT SL 0HO T_F 1_S C0_ HO T_B 7_ C0 S N LC TO S IT INT HO T_F 1_S 0_ HO T_B 6_ _E I ST N1 LC TO ST IT5 NT NA _F _S 0_ HO _B _I _EN N1 LC TO S IT NT A _S 0_ HO T_B 4_I _E LC TO S IT NT NA 0_ HO T_B 3_I _E TO S IT NT NA HO T_B 2_ _E ST IT1 INT NA _B _I _E IT NT NA 0 _ W _P C0 AC SL HO KE C0 S T_ IN HO T_F T_ ST N1 EN _F _S A N1 LC _ S 0_ T LC X 0_ _O RX VF (re se _U _IN rv DF T_ ed _I EN ) NT A _E NA Register 6.33: SLC0HOST_FUNC1_INT_ENA_REG (0xDC) 0 18 17 16 15 0 0 0 0 0 0 SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA The 0 0 0 interrupt 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Reset enable bit for the SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TX_OVF_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_TX_OVF_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_RX_UDF_INT_ENA The interrupt enable bit for the SLC0HOST_FN1_SLC0_RX_UDF_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA The interrupt enable bit for the interrupt enable bit for the interrupt enable bit for the interrupt enable bit for the interrupt enable bit for the interrupt enable bit for the interrupt enable bit for the interrupt enable bit for the SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA The SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT interrupt. (R/W) 6. SDIO SLAVE 31 28 0 0 0 27 20 0 0 0 0 0 0 0 0 15 0 0 0 14 10 0 0 0 0 0 11 20 DI O IO _F RC _S _F RC _ ST ST SL CH O SL CH O ST CH O SL 19 0 0 SD NE G _F RC _ ST _F RC _P O O SL CH (re s (re s er er ve ve d) d) S_ _S SA M AM P P Register 6.34: SLCHOST_CONF_REG (0x1F0) 9 5 0 0 0 0 0 4 0 0 0 0 0 0 0 Reset SLCHOST_FRC_POS_SAMP Set this bit to sample the corresponding signal at the rising clock edge. (R/W) SLCHOST_FRC_NEG_SAMP Set this bit to sample the corresponding signal at the falling clock edge. (R/W) SLCHOST_FRC_SDIO20 Set this bit to output the corresponding signal at the rising clock edge. (R/W) SLCHOST_FRC_SDIO11 Set this bit to output the corresponding signal at the falling clock edge. (R/W) 6.7 HINF Registers The third block of SDIO control registers starts at 0x3FF4_B000. 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HINF_HIGHSPEED_ENABLE Please initialize to 1. Do not modify it. (R/W) HINF_SDIO_IOREADY1 Please initialize to 1. Do not modify it. (R/W) 0 0 0 0 NF IG _S HS DI PE O E _I D O _E RE N AD AB Y1 LE HI HI (re se NF _H rv e d) Register 6.35: HINF_CFG_DATA1_REG (0x4) 3 2 1 0 0 0 Reset 7. SD/MMC HOST CONTROLLER 7. SD/MMC Host Controller 7.1 Overview The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral Bus (APB) and an external memory device. The memory card interface allows the ESP32 to be connected to SDIO memory cards, MMC cards and devices with a CE-ATA interface. It supports two external cards (Card0 and Card1). 7.2 Features This module has the following features: • Two external cards • Supports SD Memory Card standard: versions 3.0 and 3.01 • Supports MMC: versions 4.41, 4.5, and 4.51 • Supports CE-ATA: version 1.1 • Supports 1-bit, 4-bit, and 8-bit (Card0 only) modes The SD/MMC controller topology is shown in Figure 25. The controller supports two peripherals which cannot be functional at the same time. Figure 25: SD/MMC Controller Topology 7.3 SD/MMC External Interface Signals The primary external interface signals, which enable the SD/MMC controller to communicate with an external device, are clock (clk), command (cmd) and data signals. Additional signals include the card interrupt, card detect, and write-protect signals. The direction of each signal is shown in Figure 26. The direction and description of each pin are listed in Table 29. Espressif Systems 142 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Figure 26: SD/MMC Controller External Interface Signals Table 29: SD/MMC Signal Description Pin Direction Description cclk_out Output Clock signals for slave device ccmd Duplex Duplex command/response lines cdata Duplex Duplex data read/write lines card_detect_n Input Card detection input line card_write_prt Input Card write protection status input 7.4 Functional Description 7.4.1 SD/MMC Host Controller Architecture The SD/MMC host controller consists of two main functional blocks, as shown in Figure 27: • Bus Interface Unit (BIU): It provides APB interfaces for registers, data read and write operation by FIFO and DMA. • Card Interface Unit (CIU): It handles external memory card interface protocols. It also provides clock control. Figure 27: SDIO Host Block Diagram Espressif Systems 143 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 7.4.1.1 BIU The BIU provides the access to registers and FIFO data through the Host Interface Unit (HIU). Additionally, it provides FIFO access to independent data through a DMA interface. The host interface can be configured as an APB interface. Figure 27 illustrates the internal components of the BIU. The BIU provides the following functions: • Host interface • DMA interface • Interrupt control • Register access • FIFO access • Power/pull-up control and card detection 7.4.1.2 CIU The CIU module implements the card-specific protocols. Within the CIU, the command path control unit and data path control unit prompt the controller to interface with the command and data ports, respectively, of the SD/MMC/CE-ATA cards. The CIU also provides clock control. Figure 27 illustrates the internal structure of the CIU, which consists of the following primary functional blocks: • Command path • Data path • SDIO interrupt control • Clock control • Mux/demux unit 7.4.2 Command Path The command path performs the following functions: • Configures clock parameters • Configures card command parameters • Sends commands to card bus (ccmd_out line) • Receives responses from card bus (ccmd_in line) • Sends responses to BIU • Drives the P-bit on the command line The command path State Machine is shown in Figure 28. Espressif Systems 144 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Figure 28: Command Path State Machine 7.4.3 Data Path The data path block pops FIFO data and transmits them on cdata_out during a write-data transfer, or it receives data on cdata_in and pushes them into FIFO during a read-data transfer. The data path loads new data parameters, i.e., expected data, read/write data transfer, stream/block transfer, block size, byte count, card type, timeout registers, etc., whenever a data transfer command is not in progress. If the data_expected bit is set in the Command register, the new command is a data-transfer command and the data path starts one of the following operations: • Transmitting data if the read/write bit = 1 • Receiving data if read/write bit = 0 7.4.3.1 Data Transmit Operation The data transmit state machine is illustrated in Figure 29. The module starts data transmission two clock cycles after a response for the data-write command is received. This occurs even if the command path detects a response error or a cyclic redundancy check (CRC) error in a response. If no response is received from the card until the response timeout, no data are transmitted. Depending on the value of the transfer_mode bit in the Command register, the data-transmit state machine adds data to the card’s data bus in a stream or in block(s). The data transmit state machine is shown in Figure 29. Figure 29: Data Transmit State Machine Espressif Systems 145 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 7.4.3.2 Data Receive Operation The data-receive state machine is illustrated in Figure 30. The module receives data two clock cycles after the end bit of a data-read command, even if the command path detects a response error or a CRC error. If no response is received from the card and a response timeout occurs, the BIU does not receive a signal about the completion of the data transfer. If the command sent by the CIU is an illegal operation for the card, it would prevent the card from starting a read-data transfer, and the BIU will not receive a signal about the completion of the data transfer. If no data are received by the data timeout, the data path signals a data timeout to the BIU, which marks an end to the data transfer. Based on the value of the transfer_mode bit in the Command register, the data-receive state machine gets data from the card’s data bus in a stream or block(s). The data receive state machine is shown in Figure 30. Figure 30: Data Receive State Machine 7.5 Software Restrictions for Proper CIU Operation • Only one card at a time can be selected to execute a command or data transfer. For example, when data are being transferred to or from a card, a new command must not be issued to another card. A new command, however, can be issued to the same card, allowing it to read the device status or stop the transfer. • Only one command at a time can be issued for data transfers. • During an open-ended card-write operation, if the card clock is stopped due to FIFO being empty, the software must fill FIFO with data first, and then start the card clock. Only then can it issue a stop/abort command to the card. • During an SDIO/COMBO card transfer, if the card function is suspended and the software wants to resume the suspended transfer, it must first reset FIFO, and then issue the resume command as if it were a new data-transfer command. • When issuing card reset commands (CMD0, CMD15 or CMD52_reset), while a card data transfer is in progress, the software must set the stop_abort_cmd bit in the Command register, so that the CIU can stop the data transfer after issuing the card reset command. • When the data’s end bit error is set in the RINTSTS register, the CIU does not guarantee SDIO interrupts. In such a case, the software ignores SDIO interrupts and issues a stop/abort command to the card, so that the card stops sending read-data. Espressif Systems 146 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER • If the card clock is stopped due to FIFO being full during a card read, the software will read at least two FIFO locations to restart the card clock. • Only one CE-ATA device at a time can be selected for a command or data transfer. For example, when data are transferred from a CE-ATA device, a new command should not be sent to another CE-ATA device. • If a CE-ATA device’s interrupts are enabled (nIEN=0), a new RW_BLK command should not be sent to the same device if the execution of a RW_BLK command is already in progress (the RW_BLK command used in this databook is the RW_MULTIPLE_BLOCK MMC command defined by the CE-ATA specifications). Only the CCSD can be sent while waiting for the CCS. • If, however, a CE-ATA device’s interrupts are disabled (nIEN=1), a new command can be issued to the same device, allowing it to read status information. • Open-ended transfers are not supported in CE-ATA devices. • The send_auto_stop signal is not supported (software should not set the send_auto_stop bit) in CE-ATA transfers. After configuring the command start bit to 1, the values of the following registers cannot be changed before a command has been issued: • CMD - command • CMDARG - command argument • BYTCNT - byte count • BLKSIZ - block size • CLKDIV - clock divider • CKLENA - clock enable • CLKSRC - clock source • TMOUT - timeout • CTYPE - card type 7.6 RAM for Receiving and Sending Data The submodule RAM is a buffer area for sending and receiving data. It can be divided into two units: the one is for sending data, and the other is for receiving data. The process of sending and receiving data can also be achieved by the CPU and DMA for reading and writing. The latter method is described in detail in Section 7.8. 7.6.1 Transmit RAM Module There are two ways to enable a write operation: DMA and CPU read/write. If SDIO-sending is enabled, data can be written to the transferred RAM module by APB interface or DMA. Data will be written from register EMAC_FIFO to the CPU, directly, by an APB interface. Espressif Systems 147 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 7.6.2 Receive RAM Module There are two ways to enable a read operation: DMA and CPU read/write. When a subunit of the data path receives data, the subdata will be written onto the receive-RAM. Then, these subdata can be read either with the APB or the DMA method at the reading end. Register EMAC_FIFO can be read by the APB directly. 7.7 Descriptor Chain Each linked list module consists of two parts: the linked list itself and a data buffer. In other words, each module points to a unique data buffer and the linked list that follows the module. Figure 31 shows the descriptor chain. Figure 31: Descriptor Chain 7.8 The Structure of a Linked List Each linked list consists of four words. As is shown below, Figure 32 demonstrates the linked list’s structure, and Table 30, Table 31, Table 32, Table 33 provide the descriptions of linked lists. Figure 32: The Structure of a Linked List Espressif Systems 148 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER The DES0 element contains control and status information. Table 30: DES0 Bits Name Description When set, this bit indicates that the descriptor is 31 OWN owned by the DMAC. When reset, it indicates that the descriptor is owned by the Host. The DMAC clears this bit when it completes the data transfer. These error bits indicate the status of the transition to or from the card. The following bits are also present in RINTSTS, which indicates their digital logic OR gate. • EBE: End Bit Error 30 CES (Card Error Summary) • RTO: Response Time out • RCRC: Response CRC • SBE: Start Bit Error • DRTO: Data Read Timeout • DCRC: Data CRC for Receive • RE: Response Error 29:6 Reserved Reserved When set, this bit indicates that the descriptor list has 5 ER (End of Ring) reached its final descriptor. The DMAC then returns to the base address of the list, creating a Descriptor Ring. 4 CH (Second Address Chained) When set, this bit indicates that the second address in the descriptor is the Next Descriptor address. When this bit is set, BS2 (DES1[25:13]) should be all zeros. When set, this bit indicates that this descriptor con- 3 FD (First Descriptor) tains the first buffer of the data. If the size of the first buffer is 0, the Next Descriptor contains the beginning of the data. This bit is associated with the last block of a DMA transfer. When set, the bit indicates that the buffers pointed by this descriptor are the last buffers of the 2 LD (Last Descriptor) data. After this descriptor is completed, the remaining byte count is 0. In other words, after the descriptor with the LD bit set is completed, the remaining byte count should be 0. 1 0 DIC (Disable Interrupt on Completion) Reserved When set, this bit will prevent the setting of the TI/RI bit of the DMAC Status Register (IDSTS) for the data that ends in the buffer pointed by this descriptor. Reserved The DES1 element contains the buffer size. Espressif Systems 149 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Table 31: DES1 Bits Name Description 31:26 Reserved Reserved 25:13 Reserved Reserved Indicates the data buffer byte size, which must be a 12:0 multiple of four. In the case where the buffer size is not BS1 (Buffer 1 Size) a multiple of four, the resulting behavior is undefined. This field should not be zero. The DES2 element contains the address pointer to the data buffer. Table 32: DES2 Bits Name Description 31:0 Buffer Address Pointer 1 These bits indicate the physical address of the data buffer. The DES3 element contains the address pointer to the next descriptor if the present descriptor is not the last one in a chained descriptor structure. Table 33: DES3 Bits Name Description If the Second Address Chained (DES0[4]) bit is set, then this address contains the pointer to the physical 31:0 Next Descriptor Address memory where the Next Descriptor is present. If this is not the last descriptor, then the Next Descriptor address pointer must be DES3[1:0] = 0. 7.9 Initialization 7.9.1 DMAC Initialization The DMAC initialization should proceed as follows: • Write to the DMAC Bus Mode Register (BMOD_REG) will set the Host bus’s access parameters. • Write to the DMAC Interrupt Enable Register (IDINTEN) will mask any unnecessary interrupt causes. • The software driver creates either the transmit or the receive descriptor list. Then, it writes to the DMAC Descriptor List Base Address Register (DBADDR), providing the DMAC with the starting address of the list. • The DMAC engine attempts to acquire descriptors from descriptor lists. Espressif Systems 150 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 7.9.2 DMAC Transmission Initialization The DMAC transmission occurs as follows: 1. The Host sets up the elements (DES0-DES3) for transmission, and sets the OWN bit (DES0[31]). The Host also prepares the data buffer. 2. The Host programs the write-data command in the CMD register in BIU. 3. The Host also programs the required transmit threshold (TX_WMARK field in FIFOTH register). 4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that the host owns the descriptor. In this case, the DMAC enters a suspend-state and asserts the Descriptor Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any value to PLDMND_REG. 5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can be done. 6. Subsequently, the DMAC engine waits for a DMA interface request (dw_dma_req) from BIU. This request will be generated, based on the programmed transmit-threshold value. For the last bytes of data which cannot be accessed using a burst, single transfers are performed on the AHB Master Interface. 7. The DMAC fetches the transmit data from the data buffer in the Host memory and transfers them to FIFO for transmission to card. 8. When data span across multiple descriptors, the DMAC fetches the next descriptor and extends its operation using the following descriptor. The last descriptor bit indicates whether the data span multiple descriptors or not. 9. When data transmission is complete, the status information is updated in the IDSTS register by setting the Transmit Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing a write transaction to DES0. 7.9.3 DMAC Reception Initialization The DMAC reception occurs as follows: 1. The Host sets up the element (DES0-DES3) for reception, and sets the OWN bit (DES0[31]). 2. The Host programs the read-data command in the CMD register in BIU. 3. Then, the Host programs the required level of the receive-threshold (RX_WMARK field in FIFOTH register). 4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that the host owns the descriptor. In this case, the DMA enters a suspend-state and asserts the Descriptor Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any value to PLDMND_REG. 5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can be done. 6. The DMAC engine then waits for a DMA interface request (dw_dma_req) from BIU. This request will be generated, based on the programmed receive-threshold value. For the last bytes of the data which cannot be accessed using a burst, single transfers are performed on the AHB. 7. The DMAC fetches the data from FIFO and transfers them to the Host memory. Espressif Systems 151 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 8. When data span across multiple descriptors, the DMAC will fetch the next descriptor and extend its operation using the following descriptor. The last descriptor bit indicates whether the data span multiple descriptors or not. 9. When data reception is complete, the status information is updated in the IDSTS register by setting Receive-Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing a write-transaction to DES0. 7.10 Interrupt Interrupts can be generated as a result of various events. The IDSTS register contains all the bits that might cause an interrupt. The IDINTEN register contains an enable bit for each of the events that can cause an interrupt. There are two groups of summary interrupts, ”Normal” ones (bit8 NIS) and ”Abnormal” ones (bit9 AIS), as outlined in the IDSTS register. Interrupts are cleared by writing 1 to the position of the corresponding bit. When all the enabled interrupts within a group are cleared, the corresponding summary bit is also cleared. When both summary bits are cleared, the interrupt signal dmac_intr_o is de-asserted (stops signalling). Interrupts are not queued up, and if a new interrupt-event occurs before the driver has responded to it, no additional interrupts are generated. For example, the Receive Interrupt IDSTS[1] indicates that one or more data were transferred to the Host buffer. An interrupt is generated only once for concurrent events. The driver must scan the IDSTS register for the interrupt cause. 7.11 Register Summary Name Description Address Access CTRL_REG Control register 0x0000 R/W CLKDIV_REG Clock divider configuration register 0x0008 R/W CLKSRC_REG Clock source selection register 0x000C R/W CLKENA_REG Clock enable register 0x0010 R/W TMOUT_REG Data and response timeout configuration register 0x0014 R/W CTYPE_REG Card bus width configuration register 0x0018 R/W BLKSIZ_REG Card data block size configuration register 0x001C R/W BYTCNT_REG Data transfer length configuration register 0x0020 R/W INTMASK_REG SDIO interrupt mask register 0x0024 R/W CMDARG_REG Command argument data register 0x0028 R/W CMD_REG Command and boot configuration register 0x002C R/W RESP0_REG Response data register 0x0030 RO RESP1_REG Long response data register 0x0034 RO RESP2_REG Long response data register 0x0038 RO RESP3_REG Long response data register 0x003C RO MINTSTS_REG Masked interrupt status register 0x0040 RO RINTSTS_REG Raw interrupt status register 0x0044 R/W STATUS_REG SD/MMC status register 0x0048 RO Espressif Systems 152 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Name Description Address Access FIFOTH_REG FIFO configuration register 0x004C R/W CDETECT_REG Card detect register 0x0050 RO WRTPRT_REG Card write protection (WP) status register 0x0054 RO TCBCNT_REG Transferred byte count register 0x005C RO TBBCNT_REG Transferred byte count register 0x0060 RO DEBNCE_REG Debounce filter time configuration register 0x0064 R/W USRID_REG User ID (scratchpad) register 0x0068 R/W RST_N_REG Card reset register 0x0078 R/W BMOD_REG Burst mode transfer configuration register 0x0080 R/W PLDMND_REG Poll demand configuration register 0x0084 WO DBADDR_REG Descriptor base address register 0x0088 R/W IDSTS_REG IDMAC status register 0x008C R/W IDINTEN_REG IDMAC interrupt enable register 0x0090 R/W DSCADDR_REG Host descriptor address pointer 0x0094 RO BUFADDR_REG Host buffer address pointer register 0x0098 RO Espressif Systems 153 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 7.12 Registers SD/MMC controller registers can be accessed by the APB bus of the CPU. 31 25 0x00 24 CE A SE TA_ ND DE SE _A VI N U CE AB D_C TO _IN O C _S TE SE RT SD TO RR P_ U N _R CC PT RE D_I EA D R SD _ST AD Q _ AT (re _W _R DA US se A ES TA r I P IN ve T O T_ d) NS (re EN E A se B DM rve LE A d) FI _R FO E S CO _R ET NT ESE RO T LL ER _R ES ET ed ) rv (re se (re s (re se er rv ve ed ) d) Register 7.1: CTRL_REG (0x0000) 131 1 120 0x00 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset CEATA_DEVICE_INTERRUPT_STATUS Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device’s interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device’s interrupt, then software should set this bit. (R/W) SEND_AUTO_STOP_CCSD Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in RINTSTS is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the send_auto_stop_ccsd bit. (R/W) SEND_CCSD When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the send_ccsd bit. It also sets the Command Done (CD) bit in the RINTSTS register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. (R/W) ABORT_READ_DATA After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. (R/W) SEND_IRQ_RESPONSE Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. (R/W) Espressif Systems 154 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 31 25 0x00 24 1 CE A SE TA_ ND DE SE _A VI N U CE AB D_C TO _IN O C _S TE SE RT SD TO RR P_ U N _R CC PT RE D_I EA D R SD _ST AD Q _ AT DM _W _R DA T US A_ AI ES A P IN E T O T_ NA NS (re EN BL E A E se B DM rve LE A d) FI _R FO E S CO _R ET NT ESE RO T LL ER _R ES ET d) ve er (re s (re (re se se rv ed rv ed ) ) Register 7.2: CTRL_REG (continued) (0x0000) 131 120 0x00 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset READ_WAIT For sending read-wait to SDIO cards. (R/W) INT_ENABLE Global interrupt enable/disable bit. 0: Disable; 1: Enable. (R/W) DMA_RESET To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. (R/W) FIFO_RESET To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. (R/W) CONTROLLER_RESET To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two cclk_in clock cycles. (R/W) Espressif Systems 155 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 24 23 0x000 ER 0 R1 16 15 0x000 ID CL K_ DI V CL K_ DI VI DE VI D K_ DI CL 31 CL K_ DI VI DE R2 ER 3 Register 7.3: CLKDIV_REG (0x0008) 8 0x000 7 0 0x000 Reset CLK_DIVIDER3 Clock divider-3 value. Clock division factor is 2*n, where n=0 bypasses the divider (division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented because only one clock divider is supported. (R/W) CLK_DIVIDER2 Clock divider-2 value. Clock division factor is 2*n, where n=0 bypasses the divider (division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented because only one clock divider is supported. (R/W) CLK_DIVIDER1 Clock divider-1 value. Clock division factor is 2*n, where n=0 bypasses the divider (division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented because only one clock divider is supported. (R/W) CLK_DIVIDER0 Clock divider-0 value. Clock division factor is 2*n, where n=0 bypasses the divider (division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented because only one clock divider is supported. (R/W) (re CL se KS rv e RC d) _R EG Register 7.4: CLKSRC_REG (0x000C) 31 4 0x000000 3 0 0x0 Reset CLKSRC_REG Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3. In MMC-Ver3.3-only controller, only one clock divider is supported. The cclk_out is always from clock divider 0, and this register is not implemented. (R/W) Espressif Systems 156 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER (re se rv CC LK _E ed ) NA BE L Register 7.5: CLKENA_REG (0x0010) 31 2 0x00000 1 0 0x00000 Reset CCLK_ENABEL Clock-enable control for two SD card clocks and one MMC card clock is supported. 0: Clock disabled; 1: Clock enabled. In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. (R/W) RE SP O DA TA _T I M NS E_ EO UT TI M EO UT Register 7.6: TMOUT_REG (0x0014) 31 8 0x0FFFFFF 7 0 0x040 Reset DATA_TIMEOUT Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. (R/W) RESPONSE_TIMEOUT Response timeout value. Value is specified in terms of number of card output clocks, i.e., cclk_out. (R/W) Espressif Systems 157 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 31 18 0x00000 17 16 CA RD _W ed ) (re se rv CA (re se r ve d) RD _W ID TH 8 ID TH 4 Register 7.7: CTYPE_REG (0x0018) 15 0x00000 2 0x00000 1 0 0x00000 Reset CARD_WIDTH8 One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit[17:16] correspond to card[1:0] respectively. (R/W) CARD_WIDTH4 One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit[1:0] correspond to card[1:0] respectively. Only NUM_CARDS*2 number of bits are implemented. (R/W) (re BL O se rv CK ed ) _S I ZE Register 7.8: BLKSIZ_REG (0x001C) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0x00200 Reset BLOCK_SIZE Block size. (R/W) Register 7.9: BYTCNT_REG (0x0020) 31 0 0x000000200 Reset BYTCNT_REG Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. (R/W) Espressif Systems 158 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER K AS M IN T_ (re SD se IO rv ed ) _I NT _M AS K Register 7.10: INTMASK_REG (0x0024) 31 18 0x00000 17 16 15 0x00000 0 0x00000 Reset SDIO_INT_MASK SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, these bits are always 0. (R/W) INT_MASK These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. (R/W) Bit 15 (EBE): End-bit error, read/write (no CRC) Bit 14 (ACD): Auto command done Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt Bit 12 (HLE): Hardware locked write error Bit 11 (FRUN): FIFO underrun/overrun error Bit 10 (HTO): Data starvation-by-host timeout/Volt_switch_int Bit 9 (DRTO): Data read timeout Bit 8 (RTO): Response timeout Bit 7 (DCRC): Data CRC error Bit 6 (RCRC): Response CRC error Bit 5 (RXDR): Receive FIFO data request Bit 4 (TXDR): Transmit FIFO data request Bit 3 (DTO): Data transfer over Bit 2 (CD): Command done Bit 1 (RE): Response error Bit 0 (CD): Card detect Register 7.11: CMDARG_REG (0x0028) 31 0 0x000000000 Reset CMDARG_REG Value indicates command argument to be passed to the card. (R/W) Espressif Systems 159 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER ST A (re RT_ se C US rve MD E d) (re _HO se L (re rve E se d) (re rve se d) (re rve se d) (re rve se d) CC rve S d) RE _EX A P UP D_C EC DA EA TED TE TA _C _D LO EV CK IC CA _R E RD EG _N IS TE UM RS BE _O R SE NL Y N ST D_I O NIT W P_A IA AI B LIZ SE T_P OR AT N RV T_ IO TR D_A DA CM N A U TA D RE NS TO _C A FE _S OM DA D/W R_M TO P T R O P LET CH A_E ITE DE E E XP RE CK EC S _R TE RE PO ES D SP NS PO O E_ NS NS LE E E_ NG _C EX TH RC PE CT CM D_ IN DE X Register 7.12: CMD_REG (0x002C) 31 30 29 28 27 26 25 24 23 22 21 0 0 1 0 0 0 0 0 0 0 0 20 16 0x00 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 5 0 0x00 Reset START_CMD Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. (R/W) USE_HOLE Use Hold Register. (R/W) 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register. CCS_EXPECTED Expected Command Completion Signal (CCS) configuration. (R/W) 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device. 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. READ_CEATA_DEVICE Read access flag. (R/W) 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. (R/W) Espressif Systems 160 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER ST A (re RT_ se C US rve MD E d) (re _HO se L (re rve E se d) (re rve se d) (re rve se d) (re rve se d) CC rve S d) RE _EX A P UP D_C EC DA EA TED TE TA _C _D LO EV CK IC CA _R E RD EG _N IS TE UM RS BE _O R SE NL Y N ST D_I O NIT W P_A IA AI B LIZ SE T_P OR AT N RV T_ IO TR D_A DA CM N A U TA D RE NS TO _C A FE _S OM DA D/W R_M TO P T R O P LET CH A_E ITE DE E E XP RE CK EC S _R TE RE PO ES D SP NS PO O E_ NS NS LE E E_ NG _C EX TH RC PE CT CM D_ IN DE X Register 7.13: CMD_REG (continued) (0x002C) 31 30 29 28 27 26 25 24 23 22 21 0 0 1 0 0 0 0 0 0 0 0 20 16 0x00 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 5 0 0x00 Reset UPDATE_CLOCK_REGISTERS_ONLY (R/W) 0: Normal command sequence. 1: Do not send commands, just update clock register value into card clock domain Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. CARD_NUMBER Card number in use. Represents physical slot number of card being accessed. In MMC-Ver3.3-only mode, up to two cards are supported. In SD-only mode, up to two cards are supported. (R/W) SEND_INITIALIZATION (R/W) 0: Do not send initialization sequence (80 clocks of 1) before sending this command. 1: Send initialization sequence before sending this command. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. STOP_ABORT_CMD (R/W) 0: Neither stop nor abort command can stop current data transfer. If abort is sent to functionnumber currently selected or not in data-transfer mode, then bit should be set to 0. 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. Espressif Systems 161 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER ST A (re RT_ se C US rve MD E d) (re _HO se L (re rve E se d) (re rve se d) (re rve se d) (re rve se d) CC rve S d) RE _EX A P UP D_C EC DA EA TED TE TA _C _D LO EV CK IC CA _R E RD EG _N IS TE UM RS BE _O R SE NL Y N ST D_I O NIT W P_A IA AI B LIZ SE T_P OR AT N RV T_ IO TR D_A DA CM N A U TA D RE NS TO _C A FE _S OM DA D/W R_M TO P T R O P LET CH A_E ITE DE E E XP RE CK EC S _R TE RE PO ES D SP NS PO O E_ NS NS LE E E_ NG _C EX TH RC PE CT CM D_ IN DE X Register 7.14: CMD_REG (continued) (0x002C) 31 30 29 28 27 26 25 24 23 22 21 0 0 1 0 0 0 0 0 0 0 0 20 16 0x00 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 5 0 0x00 Reset WAIT_PRVDATA_COMPLETE (R/W) 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The wait_prvdata_complete = 0 option is typically used to query status of card during data transfer or to stop current data transfer. card_number should be same as in previous command. SEND_AUTO_STOP (R/W) 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. TRANSFER_MODE (R/W) 0: Block data transfer command; 1: Stream data transfer command. Don’t care if no data expected. READ/WRITE (R/W) 0: Read from card; 1: Write to card. Don’t care if no data is expected from card. DATA_EXPECTED (R/W) 0: No data transfer expected. 1: Data transfer expected. CHECK_RESPONSE_CRC (R/W) 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. RESPONSE_LENGTH (R/W) 0: Short response expected from card; 1: Long response expected from card. RESPONSE_EXPECT (R/W) 0: No response expected from card; 1: Response expected from card. CMD_INDEX Command index. (R/W) Espressif Systems 162 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Register 7.15: RESP0_REG (0x0030) 31 0 0x000000000 Reset RESP0_REG Bit[31:0] of response. (RO) Register 7.16: RESP1_REG (0x0034) 31 0 0x000000000 Reset RESP1_REG Bit[63:32] of long response. (RO) Register 7.17: RESP2_REG (0x0038) 31 0 0x000000000 Reset RESP2_REG Bit[95:64] of long response. (RO) Register 7.18: RESP3_REG (0x003C) 31 0 0x000000000 Reset RESP3_REG Bit[127:96] of long response. (RO) Espressif Systems 163 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 31 18 0 17 16 SK M S_ ST AT U IN T_ SD (re s IO er _I ve d) NT E RR UP T_ M SK Register 7.19: MINTSTS_REG (0x0040) 15 0x0 0 0x00000 Reset SDIO_INTERRUPT_MSK Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). (RO) INT_STATUS_MSK Interrupt enabled only if corresponding bit in interrupt mask register is set. (RO) Bit 15 (EBE): End-bit error, read/write (no CRC) Bit 14 (ACD): Auto command done Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt Bit 12 (HLE): Hardware locked write error Bit 11 (FRUN): FIFO underrun/overrun error Bit 10 (HTO): Data starvation by host timeout (HTO) Bit 9 (DTRO): Data read timeout Bit 8 (RTO): Response timeout Bit 7 (DCRC): Data CRC error Bit 6 (RCRC): Response CRC error Bit 5 (RXDR): Receive FIFO data request Bit 4 (TXDR): Transmit FIFO data request Bit 3 (DTO): Data transfer over Bit 2 (CD): Command done Bit 1 (RE): Response error Bit 0 (CD): Card detect Espressif Systems 164 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 31 16 0x00000 17 16 RA W ST AT US _ IN T_ SD (re s IO er ve d) _I NT E RR UP T_ RA W Register 7.20: RINTSTS_REG (0x0044) 31 0x0 18 0x00000 Reset SDIO_INTERRUPT_RAW Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. (R/W) 0: No SDIO interrupt from card; 1: SDIO interrupt from card. In MMC-Ver3.3-only mode, these bits are always 0. Bits are logged regardless of interrupt-mask status. (R/W) INT_STATUS_RAW Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. (R/W) Bit 15 (EBE): End-bit error, read/write (no CRC) Bit 14 (ACD): Auto command done Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt Bit 12 (HLE): Hardware locked write error Bit 11 (FRUN): FIFO underrun/overrun error Bit 10 (HTO): Data starvation by host timeout (HTO) Bit 9 (DTRO): Data read timeout Bit 8 (RTO): Response timeout Bit 7 (DCRC): Data CRC error Bit 6 (RCRC): Response CRC error Bit 5 (RXDR): Receive FIFO data request Bit 4 (TXDR): Transmit FIFO data request Bit 3 (DTO): Data transfer over Bit 2 (CD): Command done Bit 1 (RE): Response error Bit 0 (CD): Card detect Espressif Systems 165 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER _I ND EX T 30 0 0 O NS E O UN FI RE SP FO _C se (re rve se d) rv ed ) (re 31 29 DA T DA A_S TA TA DA _B TE TA US _M _3 Y C_ BU _S TA SY TU CO S M M AN D_ FS FI M FO _S FI _FU TA FO L TE FI _EM L S FO P FI _TX TY FO _ _R WA X_ TE W R AT MA ER R M K AR K Register 7.21: STATUS_REG (0x0048) 17 16 11 0x000 0x00 10 9 8 1 1 1 7 4 0x01 3 2 1 0 0 1 1 0 Reset FIFO_COUNT FIFO count, number of filled locations in FIFO. (RO) RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. (RO) DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy. (RO) DATA_BUSY Inverted version of raw selected card_data[0]. (RO) 0: Card data not busy; 1: Card data busy. DATA_3_STATUS Raw selected card_data[3], checks whether card is present. (RO) 0: card not present; 1: card present. COMMAND_FSM_STATES Command FSM states. (RO) 0: Idle 1: Send init sequence 2: Send cmd start bit 3: Send cmd tx bit 4: Send cmd index + arg 5: Send cmd crc7 6: Send cmd end bit 7: Receive resp start bit 8: Receive resp IRQ response 9: Receive resp tx bit 10: Receive resp cmd idx 11: Receive resp data 12: Receive resp crc7 13: Receive resp end bit 14: Cmd path wait NCC 15: Wait, cmd-to-response turnaround FIFO_FULL FIFO is full status. (RO) FIFO_EMPTY FIFO is empty status. (RO) FIFO_TX_WATERMARK FIFO reached Transmit watermark level, not qualified with data transfer. (RO) FIFO_RX_WATERMARK FIFO reached Receive watermark level, not qualified with data transfer. (RO) Espressif Systems 166 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 31 0 28 0x0 27 26 0 x 16 x x x x x AR M TX _W RX (re s er _W ve M d) AR K K UL TI PL er E_ ve TR d) A M 30 (re s A_ DM (re se rv ed ) NS AC TI O N_ SI ZE Register 7.22: FIFOTH_REG (0x004C) x x x x 15 x 0 12 0 0 11 0 0 0x0000 Reset DMA_MULTIPLE_TRANSACTION_SIZE Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. (R/W) RX_WMARK FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number (FIFO_RX_WATERMARK), DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. (R/W) TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number (FIFO_TX_WATERMARK), DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. (R/W) (re se rv ed ) CA RD _D E TE CT _N Register 7.23: CDETECT_REG (0x0050) 31 2 0x0 1 0 0x0 Reset CARD_DETECT_N Value on card_detect_n input ports (1 bit per card), read-only bits.0 represents presence of card. Only NUM_CARDS number of bits are implemented. (RO) Espressif Systems 167 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER W RI T (re se rv E_ ed ) PR O TE CT Register 7.24: WRTPRT_REG (0x0054) 31 2 1 0x0 0 0x0 Reset WRITE_PROTECT Value on card_write_prt input ports (1 bit per card).1 represents write protection. Only NUM_CARDS number of bits are implemented. (RO) Register 7.25: TCBCNT_REG (0x005C) 31 0 0x000000000 Reset TCBCNT_REG Number of bytes transferred by CIU unit to card. (RO) Register 7.26: TBBCNT_REG (0x0060) 31 0 0x000000000 Reset TBBCNT_REG Number of bytes transferred between Host/DMA memory and BIU FIFO. (RO) (re DE se BO rv e UN d) CE _C O UN T Register 7.27: DEBNCE_REG (0x0064) 31 0 24 0 0 0 0 0 0 23 0 0 0x0000000 Reset DEBOUNCE_COUNT Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 ~ 25 ms to prevent the card instability when the card is inserted or removed. (R/W) Espressif Systems 168 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Register 7.28: USRID_REG (0x0068) 31 0 0x000000000 Reset USRID_REG User identification register, value set by user. Default reset value can be picked by user while configuring core before synthesis. Can also be used as a scratchpad register by user. (R/W) RS (re se T_ rv ed ) CA R D_ R ES ET Register 7.29: RST_N_REG (0x0078) 31 2 0 1 0 0x1 Reset RST_CARD_RESET Hardware reset.1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. CARD_RESET[0] should be set to 1’b0 to reset card0, CARD_RESET[1] should be set to 1’b0 to reset card1.The number of bits implemented is restricted to NUM_CARDS. (R/W) 31 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 8 0x0 7 6 0 BM O BM D_ O FB D_ SW ed ) (re se rv D_ DE BM O (re BM se O rv e D_ d) PB L R Register 7.30: BMOD_REG (0x0080) 2 0x00 1 0 0 0 Reset BMOD_PBL Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. (R/W) BMOD_DE IDMAC Enable. When set, the IDMAC is enabled. (R/W) BMOD_FB Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. (R/W) BMOD_SWR Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. (R/W) Espressif Systems 169 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Register 7.31: PLDMND_REG (0x0080) 31 0 0x000000000 Reset PLDMND_REG Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only register, PD bit is write-only. (WO) Register 7.32: DBADDR_REG (0x0088) 0 31 0x000000000 Reset DBADDR_REG Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. (R/W) Espressif Systems 170 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER 31 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 13 0x00 _F BE ID _C ST O DE ID S_ ST AI S S_ (re NIS se rv ed ID ST ) ID S_ ST CE (re S_ S se DU ID rve ST d) ID S_ ST FB ID S_ E ST RI S_ TI TS ID S ID ST (re se r ve d) S_ FS M Register 7.33: IDSTS_REG (0x008C) 12 10 0x0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset IDSTS_FSM DMAC FSM present state: (RO) 0: DMA_IDLE; 1: DMA_SUSPEND; 2: DESC_RD; 3: DESC_CHK; 4: DMA_RD_REQ_WAIT 5: DMA_WR_REQ_WAIT; 6: DMA_RD; 7: DMA_WR; 8: DESC_CLOSE. IDSTS_FBE_CODE Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. (RO) 3b001: Host Abort received during transmission; 3b010: Host Abort received during reception; Others: Reserved. IDSTS_AIS Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. (R/W) IDSTS_NIS Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. (R/W) IDSTS_CES Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error, RTO : Response Timeout/Boot Ack Timeout, RCRC : Response CRC, SBE : Start Bit Error, DRTO : Data Read Timeout/BDS timeout, DCRC : Data CRC for Receive, RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. (R/W) IDSTS_DU Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing 1 clears this bit. (R/W) IDSTS_FBE Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. (R/W) IDSTS_RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. (R/W) IDSTS_TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. (R/W) Espressif Systems 171 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER (re se r ve d) ID IN ID TEN IN _ TE AI (re N_N se I rv ed ID ) IN ID TEN IN _ (re TEN CES se _ ID rve DU IN d) ID TEN IN _ ID TEN FBE IN _ TE RI N_ TI Register 7.34: IDINTEN_REG (0x0090) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset IDINTEN_AI Abnormal Interrupt Summary Enable. (R/W) When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2]: Fatal Bus Error Interrupt; IDINTEN[4]: DU Interrupt. IDINTEN_NI Normal Interrupt Summary Enable. (R/W) When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0]: Transmit Interrupt; IDINTEN[1]: Receive Interrupt. IDINTEN_CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. (R/W) IDINTEN_DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. (R/W) IDINTEN_FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. (R/W) IDINTEN_RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. (R/W) IDINTEN_TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. (R/W) Register 7.35: DSCADDR_REG (0x0094) 31 0 0x000000000 Reset DSCADDR_REG Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. (RO) Espressif Systems 172 ESP32 Technical Reference Manual V2.0 7. SD/MMC HOST CONTROLLER Register 7.36: BUFADDR_REG (0x0098) 31 0 0x000000000 Reset BUFADDR_REG Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. (RO) Espressif Systems 173 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 8. I2C Controller 8.1 Overview An I2C (Inter-Integrated Circuit) bus can be used for communication with several external devices connected to the same bus as ESP32. The ESP32 has dedicated hardware to communicate with peripherals on the I2C bus. 8.2 Features The I2C controller has the following features: • Supports both master mode and slave mode • Supports multi-master and multi-slave communication • Supports standard mode (100 kbit/s) • Supports fast mode (400 kbit/s) • Supports 7-bit addressing and 10-bit addressing • Supports continuous data transmission with disabled Serial Clock Line (SCL) • Supports programmable digital noise filter 8.3 Functional Description 8.3.1 Introduction I2C is a two-wire bus, consisting of an SDA and an SCL line. These lines are configured to open the drain output. The lines are shared by two or more devices, usually one or more masters and one or more slaves. Communication starts when a master sends out a start condition: it will pull the SDA line low, and will then pull the SCL line high. It will send out nine clock pulses over the SCL line. The first eight pulses are used to shift out a byte, consisting of a 7-bit address and a read/write bit. If a slave with this address is active on the bus, the slave can answer by pulling the SDA low on the ninth clock pulse. The master can now send out more 9-bit clock pulse clusters and, depending on the read/write bit sent, the device or the master will shift out data on the SDA line, with the other side acknowledging the transfer by pulling SDA low on the ninth clock pulse. During data transfer, the SDA line changes only when the SCL line is low. When the master has finished the communication, it will send a stop condition on the bus by raising SDA, while SCL will already be high. The ESP32 I2C peripheral can handle the I2C protocol, freeing up the processor cores for other tasks. Espressif Systems 174 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 8.3.2 Architecture Figure 33: I2C Master Architecture Figure 34: I2C Slave Architecture An I2C controller can operate either in master mode or slave mode. The I2C_MS_MODE register is used to select the mode. Figure 33 shows the I2C Master architecture, while Figure 34 shows the I2C Slave architecture. The I2C controller contains the following units: • RAM, the size of which is 32 x 8 bit and it is directly mapped onto the address space of the CPU cores, starting at address REG_I2C_BASE+0x100. Each byte of I2C data is stored in a 32-bit word of memory (so the first byte is at +0x100, the second byte at +0x104, the third byte at +0x108, etc.) • A CMD_Controller and 16 command registers (cmd0 ~ cmd15), which are used by I2C Master to control data transmission. One command at a time is executed by the I2C controller. • SCL_FSM: A state machine that controls the SCL clock. The I2C_SCL_HIGH_PERIOD_REG and I2C_SCL_LOW_PERIOD_REG registers are used to configure the frequency and duty cycle of the signal on the SCL line. • SDA_FSM: A state machine that controls the SDA data line. • DATA_Shifter which converts the byte data to an outgoing bitstream, or converts an incoming bitstream to byte data. I2C_RX_LSB_FIRST and I2C_TX_LSB_FIRST can be used for configuring whether the LSB or MSB is stored or transmitted first. Espressif Systems 175 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER • SCL_Filter and SDA_Filter: Input noise filter for the I2C_Slave. The filter can be enabled or disabled by configuring I2C_SCL_FILTER_EN and I2C_SDA_FILTER_EN. The filter can remove line glitches with pulse width less than I2C_SCL_FILTER_THRES and I2C_SDA_FILTER_THRES ABP clock cycles. 8.3.3 I2C Bus Timing Figure 35: I2C Sequence Chart Figure 35 is an I2C sequence chart. When the I2C controller works in master mode, SCL is an output signal. In contrast, when the I2C controller works in slave mode, SCL becomes an input signal. According to the I2C protocol, each transmission of data begins with a START condition and ends with a STOP condition. Data is transmitted by one byte a time, and each byte has an ACK bit. The receiver informs the transmitter to continue transmission by pulling down SDA, which indicates an ACK. The receiver can also indicate it wants to stop the transmission by not pulling down the SDA line, thereby not giving an ACK. Figure 35 also shows the registers that can configure the START bit, STOP bit, SDA hold time, and SDA sample time. If the SCL pad is set to the open-drain mode, it will take SCL more time from low level to high level, resulting in a smaller frequency value than the theoretical value. 8.3.4 I2C cmd Structure Figure 36: Structure of The I2C Command Register The Command register is active only in I2C master mode, with its internal structure shown in Figure 36. CMD_DONE: The CMD_DONE bit of every command can be read by software to tell if the command has been handled by hardware. op_code: op_code is used to indicate the command. The I2C controller supports four commands: Espressif Systems 176 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER • RSTART: op_code = 0 is the RSTART command to control the transmission of a START or RESTART I2C condition. • WRITE: op_code = 1 is the WRITE command for the I2C Master to transmit data. • READ: op_code = 2 is the READ command for the I2C Master to receive data. • STOP: op_code = 3 is the STOP command to control the transmission of a STOP I2C condition. • END: op_code = 4 is the END command for continuous data transmission. When the END command is given, SCL is temporarily disabled to allow software to reload the command and data registers for subsequent events before resuming. Transmission will then continue seamlessly. A complete data transmission process begins with an RSTART command, and ends with a STOP command. ack_value: When receiving data, this bit is used to indicate whether the receiver will send an ACK after this byte has been received. ack_exp: This bit is to set an expected ACK value for the transmitter. ack_check_en: When transmitting a byte, this bit enables checking the ACK value received against the ack_exp value. Checking is enabled by 1, while 0 disables it. byte_num: This register specifies the length of data to be read or written. When the op_code is RSTART, STOP or END, this value has no meaning. 8.3.5 I2C Master Writes to Slave Figure 37: I2C Master Writes to Slave with 7-bit Address Figure 37 shows the I2C Master writing N bytes of data to an external I2C Slave; both are supposed to be ESP32 I2C controllers. According to the I2C protocol, the first byte is the Slave address. As shown in the diagram, the first byte of the RAM unit has been populated with the Slave’s 7-bit address plus the 1-bit read/write flag. In this case, the flag is zero, indicating a write operation. The rest of the RAM unit stores N bytes of data that are ready for transmission. The cmd unit has been populated with the sequence of commands for the operation. The FIFO offset in RAM can be configured via the TXFIFO_START_ADDR field in the RXFIFO_ST_REG register. When all registers are ready, the I2C_TRANS_START bit in I2C_CTR_REG is set to start the transmission. Then, the I2C Master initiates a START condition to activate the slave devices. I2C Master will then progress to the Espressif Systems 177 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER WRITE command which will cause N+1 bytes to be fetched from RAM and sent to the Slave. The first of these bytes is the address byte. Each slave device will compare this to its own. If the addresses do not match, the slave will ignore the rest of the transmission. If they do match, the slave will ACK the initial byte and the I2C master will continue sending the rest of the data; when ack_check_en is set to ’one’, Master will check ACK value. Figure 38: I2C Master Writes to Slave with 10-bit Address The I2C controller uses 7-bit addressing by default. However, 10-bit addressing can also be used. In the master, this is done by sending a second I2C address byte after the first address byte. In the slave, the I2C_SLAVE_ADDR_10BIT_EN register bit can be set to activate a 10-bit addressing. I2C_SLAVE_ADDR is used to configure I2C Slave’s address, as per usual. Figure 38 shows the equivalent of I2C Master operation writing N-bytes of data to an I2C Slave with a 10-bit address. Since 10-bit Slave addresses require an extra address byte, both the byte_num field of the WRITE command and the number of total bytes in RAM increase by one. Figure 39: I2C Master Writes to addrM in RAM of Slave with 7-bit Address One way many I2C Slave devices are designed is by exposing a register block containing various settings. The I2C Master can write one or more of these registers by sending the Slave a register address. The ESP32 I2C Slave controller has hardware support for such a scheme. Specifically, on the Slave, I2C_FIFO_ADDR_CFG_EN can be set so that the I2C Master can write to a specified register address inside the I2C Slave memory block. Figure 39 shows the I2C Master writing N-bytes of data byte0 ~ byte(N-1) from the RAM unit to register address M (determined by addrM in RAM unit) with the Slave. Espressif Systems 178 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER Figure 40: I2C Master Writes to Slave with 7-bit Address in Two Segments If the data size exceeds the RAM unit capacity of 32 bytes, the END command can be called to enable segmented transmission. Figure 40 shows I2C Master writing data in two segments to Slave. The upper part of the figure shows the configuration of the first sequence of bytes in the transfer. I2C Master will turn off SCL clock, after executing the END command and after the controller generates the I2C_END_DETECT_INT interrupt. On receiving I2C_END_DETECT_INT (or polling the CMD_DONE bit of the command register the END was placed into), software should refresh the contents of the cmd and RAM units, as shown in the lower part of the figure. Subsequently, it should clear the I2C_END_DETECT_INT interrupt and resume the transaction by setting the I2C_TRANS_START bit in CTR_CTR_REG. 8.3.6 I2C Master Reads from Slave Figure 41: I2C Master Reads from Slave with 7-bit Address Figure 41 shows the I2C Master reading N-bytes of data from an I2C Slave with a 7-bit address. At first, the I2C Master needs to send the address of the I2C Slave, so cmd1 is a WRITE command. The byte that this command Espressif Systems 179 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER sends is the I2C slave address plus the R/W flag, which in this case is 1 and, therefore, indicates that this is going to be a read operation. According to the I2C protocol, I2C Master will not return ACK on receiving the last byte of data read from the slave; consequently, READ is divided into two segments. The I2C Master replies ACK to N-1 bytes in cmd2 and does not reply ACK to the single byte READ command in cmd3, i.e., the last transmitted data. When storing the received data, I2C Master will start from the first address in RAM. Byte0 (Slave address + 1-bit R/W marker bit) will be overwritten. The FIFO RAM offsets reading and writing data which can then be configured via the RXFIFO_START_ADDR and TXFIFO_START_ADDR fields in the RXFIFO_ST_REG register. Figure 42: I2C Master Reads from Slave with 10-bit Address Figure 42 shows the I2C Master reading data from a slave with a 10-bit address. In the Slave, this mode is enabled by setting I2C_SLAVE_ADDR_10BIT_EN register. In the Master, two bytes of RAM are used for a 10-bit address. Figure 43: I2C Master Reads N Bytes of Data from addrM in Slave with 7-bit Address Figure 43 shows the I2C Master selecting a register address inside the I2C Slave device and then reading data from it and subsequent addresses. This mode is enabled by setting the I2C_FIFO_ADDR_CFG_EN register in the Slave. The internal register address of the Slave, M, is stored in the RAM byte following the address. The WRITE command has a length of two data bytes to compensate for this. Espressif Systems 180 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER Figure 44: I2C Master Reads from Slave with 7-bit Address in Two Segments Figure 44 shows the I2C Master reading N+M bytes of data in two segments from I2C Slave by using the END command. This allows for more data to be read than what can be fitted into the RAM. The upper part of the figure shows the configuration of Segment0. The Master will update the configuration of cmd after executing the END command, as shown in the lower part of the figure. I2C Slave will refresh the data before its RAM is empty. 8.3.7 Interrupts • I2C_TX_SEND_EMPTY_INT: Triggered when I2C sends more data than nonfifo_tx_thres. • I2C_RX_REC_FULL_INT: Triggered when I2C receives more data than nonfifo_rx_thres. • I2C_ACK_ERR_INT: Triggered when I2C receives a wrong ACK bit.. • I2C_TRANS_START_INT: Triggered when I2C sends the START bit. • I2C_TIME_OUT_INT: Triggered when I2C takes too long to receive data. • I2C_TRANS_COMPLETE_INT: Triggered when I2C Master has finished STOP command or when I2C Slave detects STOP bit. • I2C_MASTER_TRAN_COMP_INT: Triggered when I2C Master sends or receives a byte. • I2C_ARBITRATION_LOST_INT: Triggered when I2C Master has lost the usage right of I2C Bus. • I2C_END_DETECT_INT: Triggered when I2C deals with the END command. Espressif Systems 181 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 8.4 Register Summary Name Description I2C0 I2C1 Acc I2C_SLAVE_ADDR_REG Configures the I2C slave address 0x3FF53010 0x3FF67010 R/W I2C_RXFIFO_ST_REG FIFO status register 0x3FF53014 0x3FF67014 RO I2C_FIFO_CONF_REG FIFO configuration register 0x3FF53018 0x3FF67018 R/W Configuration registers Timing registers I2C_SDA_HOLD_REG I2C_SDA_SAMPLE_REG I2C_SCL_LOW_PERIOD_REG I2C_SCL_HIGH_PERIOD_REG I2C_SCL_START_HOLD_REG I2C_SCL_RSTART_SETUP_REG I2C_SCL_STOP_HOLD_REG I2C_SCL_STOP_SETUP_REG Configures the hold time after a negative SCL edge Configures the sample time after a positive SCL edge Configures the low level width of the SCL clock Configures the high level width of the SCL clock Configures the delay between the SDA and SCL negative edge for a start condition Configures the delay between the positive edge of SCL and the negative edge of SDA Configures the delay after the SCL clock edge for a stop condition Configures the delay between the SDA and SCL positive edge for a stop condition 0x3FF53030 0x3FF67030 R/W 0x3FF53034 0x3FF67034 R/W 0x3FF53000 0x3FF67000 R/W 0x3FF53038 0x3FF67038 R/W 0x3FF53040 0x3FF67040 R/W 0x3FF53044 0x3FF67044 R/W 0x3FF53048 0x3FF67048 R/W 0x3FF5304C 0x3FF6704C R/W Filter registers I2C_SCL_FILTER_CFG_REG SCL filter configuration register 0x3FF53050 0x3FF67050 R/W I2C_SDA_FILTER_CFG_REG SDA filter configuration register 0x3FF53054 0x3FF67054 R/W I2C_INT_RAW_REG Raw interrupt status 0x3FF53020 0x3FF67020 RO I2C_INT_ENA_REG Interrupt enable bits 0x3FF53028 0x3FF67028 R/W I2C_INT_CLR_REG Interrupt clear bits 0x3FF53024 0x3FF67024 WO I2C_COMD0_REG I2C command register 0 0x3FF53058 0x3FF67058 R/W I2C_COMD1_REG I2C command register 1 0x3FF5305C 0x3FF6705C R/W I2C_COMD2_REG I2C command register 2 0x3FF53060 0x3FF67060 R/W I2C_COMD3_REG I2C command register 3 0x3FF53064 0x3FF67064 R/W I2C_COMD4_REG I2C command register 4 0x3FF53068 0x3FF67068 R/W I2C_COMD5_REG I2C command register 5 0x3FF5306C 0x3FF6706C R/W I2C_COMD6_REG I2C command register 6 0x3FF53070 0x3FF67070 R/W I2C_COMD7_REG I2C command register 7 0x3FF53074 0x3FF67074 R/W I2C_COMD8_REG I2C command register 8 0x3FF53078 0x3FF67078 R/W I2C_COMD9_REG I2C command register 9 0x3FF5307C 0x3FF6707C R/W I2C_COMD10_REG I2C command register 10 0x3FF53080 0x3FF67080 R/W I2C_COMD11_REG I2C command register 11 0x3FF53084 0x3FF67084 R/W I2C_COMD12_REG I2C command register 12 0x3FF53088 0x3FF67088 R/W Interrupt registers Command registers Espressif Systems 182 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER Name Description I2C0 I2C_COMD13_REG I2C command register 13 0x3FF5308C 0x3FF6708C R/W I2C_COMD14_REG I2C command register 14 0x3FF53090 0x3FF67090 R/W I2C_COMD15_REG I2C command register 15 0x3FF53094 0x3FF67094 R/W Espressif Systems 183 I2C1 Acc ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 8.5 Registers I2 (re se rv ed ) C_ SC L_ LO W _P ER IO D Register 8.1: I2C_SCL_LOW_PERIOD_REG (0x0000) 31 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SCL_LOW_PERIOD This register is used to configure the low-level width of the SCL clock signal, in APB clock cycles. (R/W) (re I2 C se r ve d) _ I2 RX C_ _L I2 TX_ SB_ C_ L F S I2 TR B_ IRS C_ AN F T I M (re S S_ RS se _M ST T I2 rve OD AR C_ d ) E T I2 SA C_ M P I2 SC LE C_ L_ _S SD FO C A_ RC L_L FO E EV RC _OU EL E_ T O UT Register 8.2: I2C_CTR_REG (0x0004) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 Reset I2C_RX_LSB_FIRST This bit is used to control the storage mode for received data. (R/W) 1: receive data from the least significant bit; 0: receive data from the most significant bit. I2C_TX_LSB_FIRST This bit is used to control the sending mode for data needing to be sent. (R/W) 1: send data from the least significant bit; 0: send data from the most significant bit. I2C_TRANS_START Set this bit to start sending the data in txfifo. (R/W) I2C_MS_MODE Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. (R/W) I2C_SAMPLE_SCL_LEVEL 1: sample SDA data on the SCL low level; 0: sample SDA data on the SCL high level. (R/W) I2C_SCL_FORCE_OUT 0: direct output; 1: open drain output. (R/W) I2C_SDA_FORCE_OUT 0: direct output; 1: open drain output. (R/W) Espressif Systems 184 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 31 30 0 0 0 27 26 0 0 0 23 0 0 0 0 0 se I2 rve C_ d ) I2 BY C_ TE I2 SL _TR C_ AV A I2 BU E_A NS C_ S D _ I2 AR BU DR C_ B S ES _ Y SE I2 TIM LO C_ E S D T _ I2 SL OU C_ AV T AC E_ K_ R W RE C XF IF 17 0 0 14 0 (re I2 (re se 18 0 C_ R rv ed ) C_ TX FI F I2 24 0 O _C NT NT O _C AI N_ CL _M d) 28 I2 C_ S ve (re s er _S I2 C (re se rv ed ) CL _S TA TE _L AS T ST AT E _L AS T Register 8.3: I2C_SR_REG (0x0008) 0 13 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Reset I2C_TXFIFO_CNT This field stores the amount of received data in RAM. (RO) I2C_RXFIFO_CNT This field represents the amount of data needed to be sent. (RO) I2C_BYTE_TRANS This field changes to 1 when one byte is transferred. (RO) I2C_SLAVE_ADDRESSED When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level. (RO) I2C_BUS_BUSY 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. (RO) I2C_ARB_LOST When the I2C controller loses control of SCL line, this register changes to 1. (RO) I2C_TIME_OUT When the I2C controller takes more than I2C_TIME_OUT clocks to receive a data bit, this field changes to 1. (RO) I2C_SLAVE_RW When in slave mode, 1: master reads from slave; 0: master writes to slave. (RO) I2C_ACK_REC This register stores the value of the received ACK bit. (RO) I2 (re se C_ T rv e IM d) E_ O UT Register 8.4: I2C_TO_REG (0x000c) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_TIME_OUT This register is used to configure the timeout for receiving a data bit in APB clock cycles. (R/W) Espressif Systems 185 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER LA VE I2 C_ S (re I2 C se _S rv ed ) LA VE _A _A DD DD R R_ 10 BI T_ EN Register 8.5: I2C_SLAVE_ADDR_REG (0x0010) 31 30 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SLAVE_ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode. (R/W) I2C_SLAVE_ADDR When configured as an I2C Slave, this field is used to configure the slave address. (R/W) 0 0 0 0 0 0 0 0 0 0 15 0 0 0 14 0 0 10 0 0 0 DR AD R T_ DD TA R _S _E FO FO RX FI RX FI C_ C_ I2 I2 I2 C 19 0 0 ND FI FI FO _R X _R X I2 C 20 0 _T X _T X FO FI d) ve (re se r 31 _A FO FI FO _E _S ND TA R T_ _A D AD DR DR Register 8.6: I2C_RXFIFO_ST_REG (0x0014) 9 0 0 5 0 0 0 4 0 0 0 0 0 0 0 Reset I2C_TXFIFO_END_ADDR This is the offset address of the last sent data, as described in nonfifo_tx_thres register. (RO) I2C_TXFIFO_START_ADDR This is the offset address of the first sent data, as described in nonfifo_tx_thres register. (RO) I2C_RXFIFO_END_ADDR This is the offset address of the first received data, as described in nonfifo_rx_thres_register. (RO) I2C_RXFIFO_START_ADDR This is the offset address of the last received data, as described in nonfifo_rx_thres_register. (RO) Espressif Systems 186 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 0 0 0 0 25 20 19 0x15 N rv ed I2 C_ ) I2 FIF C_ O NO _A NF DDR IF _C O _E FG N _E se (re I2 C_ N 26 0 I2 C_ NO O NF ) ed rv se (re 31 0 NF IF O IF O _T X _T HR ES _R X_ TH RE S Register 8.7: I2C_FIFO_CONF_REG (0x0018) 14 0x15 13 12 11 10 0 0 0 0 Reset I2C_NONFIFO_TX_THRES When I2C sends more than nonfifo_tx_thres bytes of data, it will generate a tx_send_empty_int_raw interrupt and update the current offset address of the sent data. (R/W) I2C_NONFIFO_RX_THRES When I2C receives more than nonfifo_rx_thres bytes of data, it will generate a rx_send_full_int_raw interrupt and update the current offset address of the received data. (R/W) I2C_FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. (R/W) I2C_NONFIFO_EN Set this bit to enble APB nonfifo access. (R/W) Espressif Systems 187 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER (re se rv ed ) I2 C_ I2 TX_ C_ S I2 RX END C_ _R _ I2 AC EC EM C_ K _F P T _ I2 TR ER ULL Y_ C_ AN R _ IN _ I T I2 TIM S_ INT NT _R C_ E ST _ _R A W R I2 TR _OU AR AW AW C_ AN T T_ I2 MA S_ _IN INT C_ S C T_ _R T O I2 AR ER MP RA AW W C_ B _ EN ITR TR LET D_ AT AN E_ DE ION _C INT TE _L OM _R CT OS P_ AW _I T_ IN NT IN T_ _R T_ RA AW RA W W Register 8.8: I2C_INT_RAW_REG (0x0020) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 3 0 0 0 0 0 0 0 0 0 0 Reset I2C_TX_SEND_EMPTY_INT_RAW The raw interrupt status bit for the I2C_TX_SEND_EMPTY_INT interrupt. (RO) I2C_RX_REC_FULL_INT_RAW The raw interrupt status bit for the I2C_RX_REC_FULL_INT interrupt. (RO) I2C_ACK_ERR_INT_RAW The raw interrupt status bit for the I2C_ACK_ERR_INT interrupt. (RO) I2C_TRANS_START_INT_RAW The raw interrupt status bit for the I2C_TRANS_START_INT interrupt. (RO) I2C_TIME_OUT_INT_RAW The raw interrupt status bit for the I2C_TIME_OUT_INT interrupt. (RO) I2C_TRANS_COMPLETE_INT_RAW The raw interrupt status bit for the for the for the I2C_TRANS_COMPLETE_INT interrupt. (RO) I2C_MASTER_TRAN_COMP_INT_RAW The raw interrupt status bit I2C_MASTER_TRAN_COMP_INT interrupt. (RO) I2C_ARBITRATION_LOST_INT_RAW The raw interrupt status bit I2C_ARBITRATION_LOST_INT interrupt. (RO) I2C_END_DETECT_INT_RAW The raw interrupt status bit for the I2C_END_DETECT_INT interrupt. (RO) Espressif Systems 188 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER I2 (re s er ve d) C_ I2 TX_ C_ S I2 RX END C_ _R _ I2 AC EC EM C_ K _F P T _ I2 TR ER ULL Y_ C_ AN R _ IN _ I T I2 TIM S_ INT NT _C C_ E ST _ _C L R C I2 TR _OU AR LR LR C_ AN T T_ I2 MA S_ _IN INT C_ S C T_ _C T O I2 AR ER MP CLR LR C_ B _ EN ITR TR LET D_ AT AN E_ DE ION _C INT TE _L OM _C CT OS P_ LR _I T_ IN NT IN T_ _C T_ CL LR CL R R Register 8.9: I2C_INT_CLR_REG (0x0024) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 3 0 0 0 0 0 0 0 0 0 0 Reset I2C_TX_SEND_EMPTY_INT_CLR Set this bit to clear the I2C_TX_SEND_EMPTY_INT interrupt. (WO) I2C_RX_REC_FULL_INT_CLR Set this bit to clear the I2C_RX_REC_FULL_INT interrupt. (WO) I2C_ACK_ERR_INT_CLR Set this bit to clear the I2C_ACK_ERR_INT interrupt. (WO) I2C_TRANS_START_INT_CLR Set this bit to clear the I2C_TRANS_START_INT interrupt. (WO) I2C_TIME_OUT_INT_CLR Set this bit to clear the I2C_TIME_OUT_INT interrupt. (WO) I2C_TRANS_COMPLETE_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. (WO) I2C_MASTER_TRAN_COMP_INT_CLR Set this bit to clear the I2C_MASTER_TRAN_COMP_INT interrupt. (WO) I2C_ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. (WO) I2C_END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. (WO) Espressif Systems 189 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER I2 (re s er ve d) C_ I2 TX_ C_ S I2 RX END C_ _R _ I2 AC EC EM C_ K _F P T _ I2 TR ER ULL Y_ C_ AN R _ IN _ I T I2 TIM S_ INT NT _E C_ E ST _ _E N A E I2 TR _OU AR NA NA C_ AN T T_ I2 MA S_ _IN INT C_ S C T_ _E T O I2 AR ER MP EN NA A C_ B _ EN ITR TR LET D_ AT AN E_ DE ION _C INT TE _L OM _E CT OS P_ NA _I T_ IN NT IN T_ _E T_ EN NA EN A A Register 8.10: I2C_INT_ENA_REG (0x0028) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 3 0 0 0 0 0 0 0 0 0 0 Reset I2C_TX_SEND_EMPTY_INT_ENA The interrupt enable bit for the I2C_TX_SEND_EMPTY_INT interrupt. (R/W) I2C_RX_REC_FULL_INT_ENA The interrupt enable bit for the I2C_RX_REC_FULL_INT interrupt. (R/W) I2C_ACK_ERR_INT_ENA The interrupt enable bit for the I2C_ACK_ERR_INT interrupt. (R/W) I2C_TRANS_START_INT_ENA The interrupt enable bit for the I2C_TRANS_START_INT interrupt. (R/W) I2C_TIME_OUT_INT_ENA The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. (R/W) I2C_TRANS_COMPLETE_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. (R/W) I2C_MASTER_TRAN_COMP_INT_ENA The interrupt enable bit for the I2C_MASTER_TRAN_COMP_INT interrupt. (R/W) I2C_ARBITRATION_LOST_INT_ENA The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. (R/W) I2C_END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. (R/W) Espressif Systems 190 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER (re s er ve d) I2 C_ I2 TX_ C_ S I2 RX END C_ _R _ I2 AC EC EM C_ K _F P T _ I2 TR ER ULL Y_ C_ AN R _ IN _ I T I2 TIM S_ INT NT _S C_ E ST _ _S T S I2 TR _OU AR T T C_ AN T T_ I2 MA S_ _IN INT C_ S C T_ _S T O I2 AR ER MP ST T C_ B _ EN ITR TR LET D_ AT AN E_ DE ION _C INT TE _L OM _S CT OS P_ T _I T_ IN NT IN T_ _S T_ ST T ST Register 8.11: I2C_INT_STATUS_REG (0x002c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 3 0 0 0 0 0 0 0 0 0 0 Reset I2C_TX_SEND_EMPTY_INT_ST The masked interrupt status bit for the I2C_TX_SEND_EMPTY_INT interrupt. (RO) I2C_RX_REC_FULL_INT_ST The masked interrupt status bit for the I2C_RX_REC_FULL_INT interrupt. (RO) I2C_ACK_ERR_INT_ST The masked interrupt status bit for the I2C_ACK_ERR_INT interrupt. (RO) I2C_TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. (RO) I2C_TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. (RO) I2C_TRANS_COMPLETE_INT_ST The masked interrupt status bit for the for the for the I2C_TRANS_COMPLETE_INT interrupt. (RO) I2C_MASTER_TRAN_COMP_INT_ST The masked interrupt status bit I2C_MASTER_TRAN_COMP_INT interrupt. (RO) I2C_ARBITRATION_LOST_INT_ST The masked interrupt status bit I2C_ARBITRATION_LOST_INT interrupt. (RO) I2C_END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. (RO) I2 (re se C_ SD rv ed ) A_ HO LD _T IM E Register 8.12: I2C_SDA_HOLD_REG (0x0030) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SDA_HOLD_TIME This register is used to configure the time to hold the data after the negative edge of SCL, in APB clock cycles. (R/W) Espressif Systems 191 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER (re s er I2 C_ SD ve d) A_ SA M PL E_ TI M E Register 8.13: I2C_SDA_SAMPLE_REG (0x0034) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SDA_SAMPLE_TIME This register is used to configure the delay between the positive edge of SCL and the I2C controller sampling SDA, in APB clock cycles. (R/W) I2 C (re se _S rv CL ed ) _H IG H_ PE RI O D Register 8.14: I2C_SCL_HIGH_PERIOD_REG (0x0038) 31 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SCL_HIGH_PERIOD This register is used to configure how long SCL is kept high, in APB clock cycles. (R/W) I2 (re se r C_ S CL ve d ) _S TA R T_ HO LD _ TI M E Register 8.15: I2C_SCL_START_HOLD_REG (0x0040) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 1 0 0 0 Reset I2C_SCL_START_HOLD_TIME This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in APB clock cycles. (R/W) Espressif Systems 192 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER (re se rv ed ) I2 C_ SC L_ RS TA R T_ SE TU P_ TI M E Register 8.16: I2C_SCL_RSTART_SETUP_REG (0x0044) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 1 0 0 0 Reset I2C_SCL_RSTART_SETUP_TIME This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in APB clock cycles. (R/W) I2 C_ (re se rv SC ed ) L_ ST O P_ HO LD _T IM E Register 8.17: I2C_SCL_STOP_HOLD_REG (0x0048) 31 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SCL_STOP_HOLD_TIME This register is used to configure the delay after the STOP condition’s positive edge, in APB clock cycles. (R/W) I2 (re se rv C_ SC ed ) L_ ST O P_ S ET UP _T IM E Register 8.18: I2C_SCL_STOP_SETUP_REG (0x004C) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_SCL_STOP_SETUP_TIME This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in APB clock cycles. (R/W) Espressif Systems 193 ESP32 Technical Reference Manual V2.0 8. I2C CONTROLLER 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT E CL _F I C_ S I2 I2 C (re s er ve d) _S CL _ FI LT ER _E N R_ TH RE S Register 8.19: I2C_SCL_FILTER_CFG_REG (0x0050) 4 3 2 0 0 1 0 0 0 Reset I2C_SCL_FILTER_EN This is the filter enable bit for SCL. (R/W) I2C_SCL_FILTER_THRES When a pulse on the SCL input has smaller width than this register value in APB clock cycles, the I2C controller will ignore that pulse. (R/W) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE TH R_ A_ SD C_ I2 I2 C (re se rv _S D ed ) A_ FI LT E FI LT E R_ EN S Register 8.20: I2C_SDA_FILTER_CFG_REG (0x0054) 4 3 2 0 0 1 0 0 0 Reset I2C_SDA_FILTER_EN This is the filter enable bit for SDA. (R/W) I2C_SDA_FILTER_THRES When a pulse on the SDA input has smaller width than this register value in APB clock cycles, the I2C controller will ignore that pulse. (R/W) 30 0 0 M CO I2 (re I2 31 C_ se rv e C_ CO d) M M M AN Dn AN Dn _D O NE Register 8.21: I2C_COMDn_REG (n: 0-15) (0x58+4*n) 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2C_COMMANDn_DONE When command n is done in I2C Master mode, this bit changes to high level. (R/W) I2C_COMMANDn This is the content of command n. It consists of three parts: (R/W) op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. Espressif Systems 194 ESP32 Technical Reference Manual V2.0 9. I2S 9. I2S 9.1 Overview The I2S bus provides a flexible communication interface for streaming digital data in multimedia applications, especially digital audio applications. The ESP32 includes two I2S interfaces: I2S0 and I2S1. The I2S standard bus defines three signals: a clock signal, a channel selection signal, and a serial data signal. A basic I2S data bus has one master and one slave. The roles remain unchanged throughout the communication. The I2S modules on the ESP32 provide separate transmit and receive channels for high performance. Figure 45: I2S System Block Diagram Figure 45 is the system block diagram of the ESP32 I2S module. In the figure above, the value of ”n” can be either 0 or 1. There are two independent I2S modules embedded in ESP32, namely I2S0 and I2S1. Each I2S module contains a Tx (transmit) unit and a Rx (receive) unit. Both the Tx unit and the Rx unit have a three-wire interface that includes a clock line, a channel selection line and a serial data line. The serial data line of the Tx unit is fixed as output, and the serial data line of the receive unit is fixed as input. The clock line and the channel selection line of the Tx and Rx units can be configured to both master transmitting mode and slave receiving mode. In the LCD mode, the serial data line extends to the parallel data bus. Both the Tx unit and the Rx unit have a 32-bit-wide FIFO with a depth of 64. Besides, only I2S0 supports on-chip DAC/ADC modes, as well as receiving and transmitting PDM signals. The right side of Figure 45 shows the signal bus of the I2S module. The signal naming rule of the Rx and Tx units is I2SnA_B_C, where ”n” stands for either I2S0 or I2S1; ”A” represents the direction of I2S module’s data bus signal, ”I” represents input, ”O” represents output; ”B” represents signal function; ”C” represents the signal direction, ”in” means that the signal is input into the I2S module, while ”out” means that the I2S module outputs the signal. For a detailed description of the I2S signal bus, please refer to Table 36. Espressif Systems 195 ESP32 Technical Reference Manual V2.0 9. I2S Table 36: I2S Signal Bus Description Signal Bus Signal Direction Data Signal Direction I2SnI_BCK_in In slave mode, I2S module accepts signals. I2S module receives data. I2SnI_BCK_out In master mode, I2S module outputs signals. I2S module receives data. I2SnI_WS_in In slave mode, I2S module accepts signals. I2S module receives data. I2SnI_WS_out In master mode, I2S module outputs signals. I2S module receives data. In I2S mode, I2SnI_Data_in[15] is the I2SnI_Data_in serial data bus of I2S. In LCD mode, I2S module accepts signals. the data bus width can be configured as needed. In I2S mode, I2SnO_Data_out[23] is I2SnO_Data_out the serial data bus of I2S. In LCD I2S module outputs signals. mode, the data bus width can be configured as needed. I2SnO_BCK_in In slave mode, I2S module accepts signals. I2S module sends data. I2SnO_BCK_out In master mode, I2S module outputs signals. I2S module sends data. I2SnO_WS_in In slave mode, I2S module accepts signals. I2S module sends data. I2SnO_WS_out In master mode, I2S module outputs signals. I2S module sends data. I2Sn_CLK I2S module outputs signals. It is used as a clock source for peripheral chips. I2Sn_H_SYNC I2Sn_V_SYNC In Camera mode, I2S module accepts signals. The signals are sent from the Camera. I2Sn_H_ENABLE Table 36 describes the signal bus of the I2S module. Except for the I2Sn_CLK signal, all other signals are mapped to the chip pin via the GPIO matrix and IO MUX. The I2Sn_CLK signal is mapped to the chip pin via the IO_MUX. For details, please refer to the chapter about IO_MUX and the GPIO Matrix. 9.2 Features I2S mode • Configurable high-precision output clock • Full-duplex and half-duplex data transmit and receive modes • Supports multiple digital audio standards • Embedded A-law compression/decompression module • Configurable clock signal • Supports PDM signal input and output • Configurable data transmit and receive modes LCD mode • Supports multiple LCD modes, including external LCD • Supports external Camera Espressif Systems 196 ESP32 Technical Reference Manual V2.0 9. I2S • Supports on-chip DAC/ADC modes I2S interrupts • Standard I2S interface interrupts • I2S DMA interface interrupts 9.3 The Clock of I2S Module As is shown in Figure 46, I2Sn_CLK, as the master clock of I2S module, is derived from the 160 MHz clock PLL_D2_CLK or the configurable analog PLL output clock APLL_CLK. The serial clock (BCK) of the I2S module is derived from I2Sn_CLK. The I2S_CLKA_ENA bit of register I2S_CLKM_CONF_REG is used to select either PLL_D2_CLK or APLL_CLK as the clock source for I2Sn. PLL_D2_CLK is used as the clock source for I2Sn, by default. For high performance audio applications, the analog PLL output clock source APLL_CLK must be used to acquire highly accurate I2Sn_CLK and BCK. For further details, please refer to the chapter entitled Reset and Clock. Figure 46: I2S Clock The relation between I2Sn_CLK frequency fi2s and the divider clock source frequency fpll can be seen in the equation below: fi2s = fpll N + ba ”N” corresponds to the REG _CLKM_DIV_NUM [7: 0] bits of register I2S_CLKM_CONF_REG , ”b” is the I2S_CLKM_DIV_B[5:0] bit and ”a” is the I2S_CLKM_DIV_A[5:0] bit. In master mode, the serial clock BCK in the I2S module is derived from I2Sn_CLK, that is: fBCK = fi2s M In master transmitting mode, ”M” is the I2S_TX_BCK_DIV_NUM[5:0] bit of register I2S_SAMPLE_RATE_CONF_REG. In master receiving mode, ”M” is the I2S_RX_BCK_DIV_NUM[5:0] bit of register I2S_SAMPLE_RATE_CONF_REG. 9.4 I2S Mode The ESP32 I2S module integrates an A-law compression/decompression module to enable compression/decompression of the received audio data. The RX_PCM_BYPASS bit and the TX_PCM_BYPASS bit of register I2S_CONF1_REG should be cleared when using the A-law compression/decompression module. Espressif Systems 197 ESP32 Technical Reference Manual V2.0 9. I2S 9.4.1 Supported Audio Standards In the I2S bus, BCK is the serial clock, WS is the left- /right-channel selection signal (also called word select signal), and SD is the serial data signal for transmitting/receiving digital audio data. WS and SD signals in the I2S module change on the falling edge of BCK, while the SD signal can be sampled on the rising edge of BCK. If the I2S_RX_RIGHT_FIRST bit and the I2S_TX_RIGHT_FIRST bit of register I2S_CONF_REG are set to 1, the I2S module is configured to receive and transmit right-channel data first. Otherwise, the I2S module receives and transmits left-channel data first. 9.4.1.1 Philips Standard Figure 47: Philips Standard As is shown in Figure 47, the Philips I2S bus specifications require that the WS signal starts to change a BCK clock cycle earlier than the SD signal, which means that the WS signal takes effect a clock cycle before the first bit of the current channel-data transmission, while the WS signal continues until the end of the current channel-data transmission. The SD signal line transmits the most significant bit of audio data first. If the I2S_RX_MSB_SHIFT bit and the I2S_TX_MSB_SHIFT bit of register I2S_CONF_REG are set to 1, respectively, the I2S module will use the Philips standard when receiving and transmitting data. 9.4.1.2 MSB Alignment Standard Figure 48: MSB Alignment Standard The MSB alignment standard is shown in Figure 48. WS and SD signals both change simultaneously on the falling edge of BCK under the MSB alignment standard. The WS signal continues until the end of the current channel-data transmission, and the SD signal line transmits the most significant bit of audio data first. If the I2S_RX_MSB_SHIFT and I2S_TX_MSB_SHIFT bits of register I2S_CONF_REG are cleared, the I2S module will use the MSB alignment standard when receiving and transmitting data. Espressif Systems 198 ESP32 Technical Reference Manual V2.0 9. I2S 9.4.1.3 PCM Standard As is shown in Figure 49, under the short frame synchronization mode of the PCM standard, the WS signal starts to change a BCK clock cycle earlier than the SD signal, which means that the WS signal takes effect a clock cycle earlier than the first bit of the current channel-data transmission and continues for one extra BCK clock cycle. The SD signal line transmits the most significant bit of audio data first. If the I2S_RX_SHORT_SYNC and I2S_TX_SHORT_SYNC bits of register I2S_CONF_REG are set, the I2S module will receive and transmit data in the short frame synchronization mode. Figure 49: PCM Standard 9.4.2 Module Reset The four low-order bits in register I2S_CONF_REG, that is, I2S_TX_RESET, I2S_RX_RESET, I2S_TX_FIFO_RESET and I2S_RX_FIFO_RESET reset the receive module, the transmit module and the corresponding FIFO buffer, respectively. In order to finish a reset operation, the corresponding bit should be set and then cleared by software. 9.4.3 FIFO Operation The data read/write packet length for a FIFO operation is 32 bits. The data packet format for the FIFO buffer can be configured using configuration registers. As shown in Figure 45, both sent and received data should be written into FIFO first and then read from FIFO. There are two approaches to accessing the FIFO; one is to directly access the FIFO using a CPU, the other is to access the FIFO using a DMA controller. Generally, both the I2S_RX_FIFO_MOD_FORCE_EN bit and I2S_TX_FIFO_MOD_FORCE_EN bits of register I2S_FIFO_CONF_REG should be set to 1. I2S_TX_DATA_NUM[5:0] bit and I2S_RX_DATA_NUM[5:0] are used to control the length of the data that have been sent, received and buffered. Hardware inspects the received-data length RX_LEN and the transmitted-data length TX_LEN. Both the received and the transmitted data are buffered in the FIFO method. When RX_LEN is greater than I2S_RX_DATA_NUM[5:0], the received data, which is buffered in FIFO, has reached the set threshold and needs to be read out to prevent an overflow. When TX_LEN is less than I2S_TX_DATA_NUM[5:0], the transmitted data, which is buffered in FIFO, has not reached the set threshold and software can continue feeding data into FIFO. 9.4.4 Sending Data The ESP32 I2S module carries out a data-transmit operation in three stages: • Read data from internal storage and transfer it to FIFO • Read data to be sent from FIFO Espressif Systems 199 ESP32 Technical Reference Manual V2.0 9. I2S • Clock out data serially, or in parallel, as configured by the user Figure 50: Tx FIFO Data Mode Table 37: Register Configuration Tx FIFO mode0 Tx FIFO mode1 I2S_TX_FIFO_MOD[2:0] Description 0 16-bit dual channel data 2 32-bit dual channel data 3 32-bit single channel data 1 16-bit single channel data At the first stage, there are two modes for data to be sent and written into FIFO. In Tx FIFO mode0, the Tx data-to-be-sent are written into FIFO according to the time order. In Tx FIFO mode1, the data-to-be-sent are divided into 16 high- and 16 low-order bits. Then, both the 16 high- and 16 low-order bits are recomposed and ′ written into FIFO. The details are shown in Figure 50 with the corresponding registers listed in Table 37. Dn ′′ consists of 16 high-order bits of Dn and 16 zeros. Dn consists of 16 low-order bits of Dn and 16 zeros. That is ′ ′′ to say, Dn = {Dn [31 : 16], 16′ h0}, Dn = {Dn [15 : 0], 16′ h0}. At the second stage, the system reads data that will be sent from FIFO, according to the relevant register configuration. The mode in which the system reads data from FIFO is relevant to the configuration of I2S_TX_FIFO_MOD[2.0] and I2S_TX_CHAN_MOD[2:0]. I2S_TX_FIFO_MOD[2.0] determines whether the data are 16-bit or 32-bit, as shown in Table 37, while I2S_TX_CHAN_MOD[2:0] determines the format of the data-to-be-sent, as shown in Table 38. Table 38: Send Channel Mode I2S_TX_CHAN_MOD[2:0] Description 0 Dual channel mode Mono mode When I2S_TX_MSB_RIGHT equals 0, the left-channel data are ”holding” 1 their values and the right-channel data change into the left-channel data. When I2S_TX_MSB_RIGHT equals 1, the right-channel data are ”holding” their values and the left-channel data change into the right-channel data. Mono mode When I2S_TX_MSB_RIGHT equals 0, the right-channel data are ”holding” 2 their values and the left-channel data change into the right-channel data. When I2S_TX_MSB_RIGHT equals 1, the left-channel data are ”holding” their values and the right-channel data change into the left-channel data. Espressif Systems 200 ESP32 Technical Reference Manual V2.0 9. I2S I2S_TX_CHAN_MOD[2:0] Description Mono mode When I2S_TX_MSB_RIGHT equals 0, the left-channel data are constants 3 in the range of REG[31:0]. When I2S_TX_MSB_RIGHT equals 1, the right-channel data are constants in the range of REG[31:0]. Mono mode When I2S_TX_MSB_RIGHT equals 0, the right-channel data are constants 4 in the range of REG[31:0]. When I2S_TX_MSB_RIGHT equals 1, the left-channel data are constants in the range of REG[31:0]. REG[31:0] is the value of register I2S_CONF_SINGLE_DATA_REG[31:0]. The output of the third stage is determined by the mode of the I2S and I2S_TX_BITS_MOD[5:0] bits of register I2S_SAMPLE_RATE_CONF_REG. 9.4.5 Receiving Data The data-receive phase of the ESP32 I2S module consists of another three stages: • The input serial-bit stream is transformed into a 64-bit parallel-data stream in I2S mode. In LCD mode, the input parallel-data stream will be extended to a 64-bit parallel-data stream. • Received data are written into FIFO. • Data are read from FIFO by CPU/DMA and written into the internal memory. At the first stage of receiving data, the received-data stream is expanded to a zero-padded parallel-data stream with 32 high-order bits and 32 low-order bits, according to the level of the I2SnI_WS_out (or I2SnI_WS_in) signal. The I2S_RX_MSB_RIGHT bit of register I2S_CONF_REG is used to determine how the data are to be expanded. Figure 51: The First Stage of Receiving Data For example, as is shown in Figure 51, if the width of serial data is 16 bits, when I2S_RX_RIGHT_FIRST equals 1, Data0 will be discarded and I2S will start receiving data from Data1. If I2S_RX_MSB_RIGHT equals 1, data of the first stage would be {0xF EDC0000, 0x32100000}. If I2S_RX_MSB_RIGHT equals 0, data of the first stage would be {0x32100000, 0xF EDC0000}. When I2S_RX_RIGHT_FIRST equals 0, I2S will start receiving data from Data0. If I2S_RX_MSB_RIGHT equals 1, data of the first stage would be {0xF EDC0000, 0x76540000}. If I2S_RX_MSB_RIGHT equals 0, data of the first stage would be {0x76540000, 0xF EDC0000}. As is shown in Table 39 and Figure 52, at the second stage, the received data of the Rx unit is written into FIFO. There are four modes of writing received data into FIFO. Each mode corresponds to a value of I2S_RX_FIFO_MOD[2:0] bit. Espressif Systems 201 ESP32 Technical Reference Manual V2.0 9. I2S Table 39: Modes of Writing Received Data into FIFO and the Corresponding Register Configuration I2S_RX_FIFO_MOD[2:0] Data format 0 16-bit dual channel data 1 16-bit single channel data 2 32-bit dual channel data 3 32-bit single channel data Figure 52: Modes of Writing Received Data into FIFO At the third stage, CPU or DMA will read data from FIFO and write them into the internal memory directly. The register configuration that each mode corresponds to is shown in Table 40. Table 40: The Register Configuration to Which the Four Modes Correspond I2S_RX_MSB_RIGHT I2S_RX_CHAN_MOD mode0 0 1 0 2 left channel mode1 mode2 mode3 - - left channel + left channel + left channel + right channel right channel + left channel left channel + right channel right channel + right channel right channel 3 - - 0 - - right channel + right channel + 1 1 2 right channel right channel right channel right channel + left channel left channel + + left channel left channel + 3 left channel left channel - - 9.4.6 I2S Master/Slave Mode The ESP32 I2S module can be configured to act as a master or slave device on the I2S bus. The module supports slave transmitter and receiver configurations in addition to master transmitter and receiver configurations. All these modes can support full-duplex and half-duplex communication over the I2S bus. I2S_RX_SLAVE_MOD bit and I2S_TX_SLAVE_MOD bit of register I2S_CONF_REG can configure I2S to slave receiving mode and slave transmitting mode, respectively. Espressif Systems 202 ESP32 Technical Reference Manual V2.0 9. I2S I2S_TX_START bit of register I2S_CONF_REG is used to enable transmission. When I2S is in master transmitting mode and this bit is set, the module will keep driving the clock signal and data of left and right channels. If FIFO sends out all the buffered data and there are no new data to shift, the last batch of data will be looped on the data line. When this bit is reset, master will stop driving clock and data lines. When I2S is configured to slave transmitting mode and this bit is set, the module will wait for the master BCK clock to enable a transmit operation. The I2S_RX_START bit of register I2S_CONF_REG is used to enable a receive operation. When I2S is in master transmitting mode and this bit is set, the module will keep driving the clock signal and sampling the input data stream until this bit is reset. If I2S is configured to slave receiving mode and this bit is set, the receiving module will wait for the master BCK clock to enable a receiving operation. 9.4.7 I2S PDM As is shown in Figure 45, ESP32 I2S0 allows for pulse density modulation (PDM), which enables fast conversion between pulse code modulation (PCM) and PDM signals. The output clock of PDM is mapped to the I2S0*_WS_out signal. Its configuration is identical to I2S’s BCK. Please refer to section 9.3, ”The Clock of I2S Module”, for further details. The bit width for both received and transmitted I2S PCM signals is 16 bits. Figure 53: PDM Transmitting Module The PDM transmitting module is used to convert PCM signals into PDM signals, as shown in Figure 53. HPF is a high-speed channel filter, and LPF is a low-speed channel filter. The PDM signal is derived from the PCM signal, after upsampling and filtering. Signal I2S_TX_PDM_HP_BYPASS of register I2S_PDM_CONF_REG can be set to bypass the HPF at the PCM input. Filter module group0 carries out the upsampling. If the frequency of the PDM signal is fpdm and the frequency of the PCM signal is fpcm , the relation between fpdm and fpcm is given by: fpdm = 64×fpcm × I2S_T X_P DM _F P I2S_T X_P DM _F S The upsampling factor of 64 is the result of the two upsampling stages. Table 41 lists the configuration rates of the I2S_TX_PDM_FP bit and the I2S_TX_PDM_FS bit of register I2S_PDM_FREQ_CONF_REG, whose output PDM signal frequency remains 48×128 KHz at different PCM signal frequencies. Table 41: Upsampling Rate Configuration fpcm (KHz) I2S_TX_PDM_FP I2S_TX_PDM_FS 48 960 480 44.1 960 441 32 960 320 24 960 240 16 960 160 8 960 80 Espressif Systems 203 fpdm (KHz) 48×128 ESP32 Technical Reference Manual V2.0 9. I2S The I2S_TX_PDM_SINC_OSR2 bit of I2S_PDM_CONF_REG is the upsampling rate of the Filter group0. ⌊ ⌋ I2S_T X_P DM _F P I2S_T X_P DM _SIN C_OSR2 = I2S_T X_P DM _F S As is shown in Figure 54, the I2S_TX_PDM_EN bit and the I2S_PCM2PDM_CONV_EN bit of register I2S_PDM_CONF_REG should be set to 1 to use the PDM sending module. The I2S_TX_PDM_SIGMADELTA_IN_SHIFT bit, I2S_TX_PDM_SINC_IN_SHIFT bit, I2S_TX_PDM_LP_IN_SHIFT bit and I2S_TX_PDM_HP_IN_SHIFT bit of register I2S_PDM_CONF_REG are used to adjust the size of the input signal of each filter module. Figure 54: PDM Sends Signal As is shown in Figure 55, the I2S_RX_PDM_EN bit and the I2S_PDM2PCM_CONV_EN bit of register I2S_PDM_CONF_REG should be set to 1, in order to use the PDM receiving module. As is shown in Figure 56, the PDM receiving module will convert the received PDM signal into a 16-bit PCM signal. Filter group1 is used to downsample the PDM signal, and the I2S_RX_PDM_SINC_DSR_16_EN bit of register I2S_PDM_CONF_REG is used to adjust the corresponding down-sampling rate. Figure 55: PDM Receives Signal Figure 56: PDM Receive Module Table 42 shows the configuration of the I2S_RX_PDM_SINC_DSR_16_EN bit whose PCM signal frequency remains 48 KHz at different PDM signal frequencies. Espressif Systems 204 ESP32 Technical Reference Manual V2.0 9. I2S Table 42: Down-sampling Configuration PDM freq (KHz) I2S_RX_PDM_SINC_DSR_16_EN fpcm ×128 1 fpcm ×64 0 PCM freq (KHz) fpcm 9.5 LCD Mode There are three operational modes in the LCD mode of ESP32 I2S: • LCD master transmitting mode • Camera slave receiving mode • ADC/DAC mode The clock configuration of the LCD master transmitting mode is identical to I2S’s clock configuration. In the LCD mode, the frequency of WS is half of f BCK . 9.5.1 LCD Master Transmitting Mode As is shown in Figure 57, the WR signal of LCD connects to the WS signal of I2S. The LCD data bus width is 24 bits. Figure 57: LCD Master Transmitting Mode The I2S_LCD_EN bit of register I2S_CONF2_REG needs to be set and the I2S_TX_SLAVE_MOD bit of register I2S_CONF_REG needs to be cleared, in order to configure I2S to the LCD master transmitting mode. Meanwhile, data should be sent under the correct mode, according to the I2S_TX_CHAN_MOD[2:0] bit of register I2S_CONF_CHAN_REG and the I2S_TX_FIFO_MOD[2:0] bit of register I2S_FIFO_CONF_REG. The WS signal needs to be inverted when it is routed through the GPIO Matrix. For details, please refer to the chapter about IO_MUX and the GPIO Matrix. The I2S_LCD_TX_SDX2_EN bit and the I2S_LCD_TX_WRX2_EN bit of register I2S_CONF2_REG should be set to the LCD master transmitting mode, so that both the data bus and WR signal work in the appropriate mode. Figure 58: LCD Master Transmitting Data Frame, Form 1 Espressif Systems 205 ESP32 Technical Reference Manual V2.0 9. I2S Figure 59: LCD Master Transmitting Data Frame, Form 2 As is shown in Figure 58 and Figure 59, the I2S_LCD_TX_WRX2_EN bit should be set to 1 and the I2S_LCD_TX_SDX2_EN bit should be set to 0 in the data frame, form 1. Both I2S_LCD_TX_SDX2_EN bit and I2S_LCD_TX_WRX2_EN bit are set to 1 in the data frame, form 2. 9.5.2 Camera Slave Receiving Mode ESP32 I2S supports a camera slave mode for high-speed data transfer from external camera modules. As shown in Figure 60, in this mode, I2S is set to slave receiving mode. Besides the 16-channel data signal bus I2SnI_Data_in, there are other signals, such as I2Sn_H_SYNC, I2Sn_V_SYNC and I2Sn_H_ENABLE. The PCLK in the Camera module connects to I2SnI_WS_in in the I2S module, as Figure 60 shows. Figure 60: Camera Slave Receiving Mode When I2S is in the camera slave receiving mode, and when I2Sn_H_SYNC, I2S_V_SYNC and I2S_H_REF are held high, the master starts transmitting data, that is, transmission_start = (I2Sn_H_SY N C == 1)&&(I2Sn_V _SY N C == 1)&&(I2Sn_H_EN ABLE == 1) Thus, during data transmission, these three signals should be kept at a high level. For example, if the I2Sn_V_SYNC signal of a camera is at low level during data transmission, it will be inverted when routed to the I2S module. ESP32 supports signal inversion through the GPIO matrix. For details, please refer to the chapter about IO_MUX and the GPIO Matrix. In order to make I2S work in camera mode, the I2S_LCD_EN bit and the I2S_CAMERA_EN bit of register I2S_CONF2_REG are set to 1, the I2S_RX_SLAVE_MOD bit of register I2S_CONF_REG is set to 1, the I2S_RX_MSB_RIGHT bit and the I2S_RX_RIGHT_FIRST bit of I2S_CONF_REG are set to 0. Thus, I2S works in the LCD slave receiving mode. At the same time, in order to use the correct mode to receive data, both the I2S_RX_CHAN_MOD[2:0] bit of register I2S_CONF_CHAN_REG and the I2S_RX_FIFO_MOD[2:0] bit of register I2S_FIFO_CONF_REG are set to 1. Espressif Systems 206 ESP32 Technical Reference Manual V2.0 9. I2S 9.5.3 ADC/DAC mode In LCD mode, ESP32’s ADC and DAC can receive data. When the I2S0 module connects to the on-chip ADC, the I2S0 module should be set to master receiving mode. Figure 61 shows the signal connection between the I2S0 module and the ADC. Figure 61: ADC Interface of I2S0 Firstly, the I2S_LCD_EN bit of register I2S_CONF2_REG is set to 1, and the I2S_RX_SLAVE_MOD bit of register I2S_CONF_REG is set to 0, so that the I2S0 module works in LCD master receiving mode, and the I2S0 module clock is configured such that the WS signal of I2S0 outputs an appropriate frequency. Then, the APB_CTRL_SARADC_DATA_TO_I2S bit of register APB_CTRL_APB_SARADC_CTRL_REG is set to 1. Enable I2S to receive data after configuring the relevant registers of SARADC. For details, please refer to the chapter about on-chip sensors. Figure 62: DAC Interface of I2S Figure 63: Data Input by I2S DAC Interface The I2S0 module should be configured to master transmitting mode when it connects to the on-chip DAC. Figure 62 shows the signal connection between the I2S0 module and the DAC. The DAC’s control module regards I2S_CLK as the clock in this configuration. As shown in Figure 63, when the data bus inputs data to the DAC’s control module, the latter will input right-channel data to DAC1 module and left-channel data to DAC2 module. When using the I2S DMA module, 8 bits of data-to-be-transmitted are shifted to the left by 8 bits of data-to-be-received into the DMA double-byte type of buffer. The I2S_LCD_EN bit of register I2S_CONF2_REG should be set to 1, while I2S_RX_SHORT_SYNC, Espressif Systems 207 ESP32 Technical Reference Manual V2.0 9. I2S I2S_TX_SHORT_SYNC, I2S_CONF_REG , I2S_RX_MSB_SHIFT and I2S_TX_MSB_SHIFT should all be reset to 0. The I2S_TX_SLAVE_MOD bit of register I2S_CONF_REG should be set to 0, as well, when using the DAC mode of I2S0. Select a suitable transmit mode according to the standards of transmitting a 16-bit digital data stream. Configure the I2S0 module clock to output a suitable frequency for the I2S_CLK and the WS of I2S. Enable I2S0 to send data after configuring the relevant DAC registers. 9.6 I2S Interrupts 9.6.1 FIFO Interrupts • I2S_TX_HUNG_INT: Triggered when transmitting data is timed out. • I2S_RX_HUNG_INT: Triggered when receiving data is timed out. • I2S_TX_REMPTY_INT: Triggered when the transmit FIFO is empty. • I2S_TX_WFULL_INT: Triggered when the transmit FIFO is full. • I2S_RX_REMPTY_INT: Triggered when the receive FIFO is empty. • I2S_RX_WFULL_INT: Triggered when the receive FIFO is full. • I2S_TX_PUT_DATA_INT: Triggered when the transmit FIFO is almost empty. • I2S_RX_TAKE_DATA_INT: Triggered when the receive FIFO is almost full. 9.6.2 DMA Interrupts • I2S_OUT_TOTAL_EOF_INT: Triggered when all transmitting linked lists are used up. • I2S_IN_DSCR_EMPTY_INT: Triggered when there are no valid receiving linked lists left. • I2S_OUT_DSCR_ERR_INT: Triggered when invalid rxlink descriptors are encountered. • I2S_IN_DSCR_ERR_INT: Triggered when invalid txlink descriptors are encountered. • I2S_OUT_EOF_INT: Triggered when rxlink has finished sending a packet. • I2S_OUT_DONE_INT: Triggered when all transmitted and buffered data have been read. • I2S_IN_SUC_EOF_INT: Triggered when all data have been received. • I2S_IN_DONE_INT: Triggered when the current txlink descriptor is handled. 9.7 Register Summary Name Description I2S0 I2S1 Acc I2S_CONF_REG Configuration and start/stop bits 0x3FF4F008 0x3FF6D008 R/W I2S_CONF1_REG PCM configuration register 0x3FF4F0A0 0x3FF6D0A0 R/W 0x3FF4F0A8 0x3FF6D0A8 R/W 0x3FF4F01C 0x3FF6D01C R/W Configuration registers I2S_CONF2_REG I2S_TIMING_REG Espressif Systems ADC/LCD/camera configuration register Signal delay and timing parameters 208 ESP32 Technical Reference Manual V2.0 9. I2S I2S_FIFO_CONF_REG FIFO configuration 0x3FF4F020 0x3FF6D020 R/W I2S_CONF_SINGLE_DATA_REG Static channel output value 0x3FF4F028 0x3FF6D028 R/W I2S_CONF_CHAN_REG Channel configuration 0x3FF4F02C 0x3FF6D02C R/W I2S_LC_HUNG_CONF_REG Timeout detection configuration 0x3FF4F074 0x3FF6D074 I2S_CLKM_CONF_REG Bitclock configuration 0x3FF4F0AC 0x3FF6D0AC R/W I2S_SAMPLE_RATE_CONF_REG Sample rate configuration 0x3FF4F0B0 0x3FF6D0B0 R/W I2S_PD_CONF_REG Power-down register 0x3FF4F0A4 0x3FF6D0A4 R/W I2S_STATE_REG I2S status register 0x3FF4F0BC 0x3FF6D0BC RO I2S_LC_CONF_REG DMA configuration register 0x3FF4F060 0x3FF6D060 R/W I2S_RXEOF_NUM_REG Receive data count 0x3FF4F024 0x3FF6D024 R/W 0x3FF4F030 0x3FF6D030 R/W 0x3FF4F034 0x3FF6D034 R/W 0x3FF4F038 0x3FF6D038 RO 0x3FF4F03C 0x3FF6D03C RO 0x3FF4F040 0x3FF6D040 RO 0x3FF4F048 0x3FF6D048 RO 0x3FF4F04C 0x3FF6D04C RO 0x3FF4F050 0x3FF6D050 RO 0x3FF4F054 0x3FF6D054 RO 0x3FF4F058 0x3FF6D058 RO 0x3FF4F05C 0x3FF6D05C RO R/W DMA registers I2S_OUT_LINK_REG I2S_IN_LINK_REG I2S_OUT_EOF_DES_ADDR_REG I2S_IN_EOF_DES_ADDR_REG I2S_OUT_EOF_BFR_DES_ADDR_REG I2S_INLINK_DSCR_REG I2S_INLINK_DSCR_BF0_REG I2S_INLINK_DSCR_BF1_REG I2S_OUTLINK_DSCR_REG I2S_OUTLINK_DSCR_BF0_REG I2S_OUTLINK_DSCR_BF1_REG DMA transmit linked list configuration and address DMA receive linked list configuration and address The address of transmit link descriptor producing EOF The address of receive link descriptor producing EOF The address of transmit buffer producing EOF The address of current inlink descriptor The address of next inlink descriptor The address of next inlink data buffer The address of current outlink descriptor The address of next outlink descriptor The address of next outlink data buffer I2S_LC_STATE0_REG DMA receive status 0x3FF4F06C 0x3FF6D06C RO I2S_LC_STATE1_REG DMA transmit status 0x3FF4F070 0x3FF6D070 RO Pulse density (DE) modulation registers I2S_PDM_CONF_REG PDM configuration 0x3FF4F0B4 0x3FF6D0B4 R/W I2S_PDM_FREQ_CONF_REG PDM frequencies 0x3FF4F0B8 0x3FF6D0B8 R/W I2S_INT_RAW_REG Raw interrupt status 0x3FF4F00C 0x3FF6D00C RO I2S_INT_ST_REG Masked interrupt status 0x3FF4F010 0x3FF6D010 RO I2S_INT_ENA_REG Interrupt enable bits 0x3FF4F014 0x3FF6D014 R/W I2S_INT_CLR_REG Interrupt clear bits 0x3FF4F018 0x3FF6D018 WO Interrupt registers Espressif Systems 209 ESP32 Technical Reference Manual V2.0 9. I2S 9.8 Registers (re s er ve d) I2 S_ I2 SIG S_ _ L I2 RX OO S_ _M P I2 TX_ SB BAC S_ M _R K I2 RX SB IGH S_ _M _R T I2 TX_ ON IGH S_ M O T I2 RX ON S_ _S O I2 TX_ HO S_ S R T I2 RX HO _S S_ _M RT YN I2 TX_ SB _SY C S_ M _S N I2 RX SB HIF C S_ _R _S T I2 TX_ IGH HIF S_ R T T _ I2 RX IGH FIR S_ _S T S _F T L T I2 X_ AV IR S_ S E S T I2 RX LAV _MO S_ _S E _M D T T I2 X_ AR O S_ S T D I2 RX TAR S_ _F T I2 TX_ IFO S_ F _R I I2 RX FO ES S_ _R _R ET TX ES ES _R ET ET ES ET Register 9.1: I2S_CONF_REG (0x0008) 31 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_SIG_LOOPBACK Enable signal loopback mode, with transmitter module and receiver module sharing the same WS and BCK signals. (R/W) I2S_RX_MSB_RIGHT Set this to place right-channel data at the MSB in the receive FIFO. (R/W) I2S_TX_MSB_RIGHT Set this bit to place right-channel data at the MSB in the transmit FIFO. (R/W) I2S_RX_MONO Set this bit to enable receiver’s mono mode in PCM standard mode. (R/W) I2S_TX_MONO Set this bit to enable transmitter’s mono mode in PCM standard mode. (R/W) I2S_RX_SHORT_SYNC Set this bit to enable receiver in PCM standard mode. (R/W) I2S_TX_SHORT_SYNC Set this bit to enable transmitter in PCM standard mode. (R/W) I2S_RX_MSB_SHIFT Set this bit to enable receiver in Philips standard mode. (R/W) I2S_TX_MSB_SHIFT Set this bit to enable transmitter in Philips standard mode. (R/W) I2S_RX_RIGHT_FIRST Set this bit to receive right-channel data first. (R/W) I2S_TX_RIGHT_FIRST Set this bit to transmit right-channel data first. (R/W) I2S_RX_SLAVE_MOD Set this bit to enable slave receiver mode. (R/W) I2S_TX_SLAVE_MOD Set this bit to enable slave transmitter mode. (R/W) I2S_RX_START Set this bit to start receiving data. (R/W) I2S_TX_START Set this bit to start transmitting data. (R/W) I2S_RX_FIFO_RESET Set this bit to reset the receive FIFO. (R/W) I2S_TX_FIFO_RESET Set this bit to reset the transmit FIFO. (R/W) I2S_RX_RESET Set this bit to reset the receiver. (R/W) I2S_TX_RESET Set this bit to reset the transmitter. (R/W) Espressif Systems 210 ESP32 Technical Reference Manual V2.0 9. I2S (re se r ve d) I2 S_ I2 OU S_ T_ I2 IN_ TO S_ D TA S I2 OU CR L_E S_ T_ _ O E I2 IN_ DS MP F_I S_ D C T NT R S I2 OU CR _E Y_I _R S_ T_ _ R NT AW E R (re OU EO RR _IN _R se T_ F_ _I T AW I2 rve DO INT NT _RA S_ d N _R _R W ) E_ A A I2 IN_ IN W W S_ S T_ U RA I2 IN_ C_ S_ D E W O O T I2 X_ NE F_ S_ H _ IN I I2 RX UN NT T_R S_ _H G _R A _ I2 TX_ UN INT AW W S_ R G _ _ R I2 TX_ EM INT AW S_ W PT _ R I2 RX FU Y_I AW S_ _R LL N T I2 RX EM _IN _R S_ _W P T_ A W T I2 TX_ FU Y_ RA S_ P LL IN W RX UT _I T_ _T _D NT RA AK AT _R W E_ A_ AW D A IN TA T_R _I A NT W _R AW Register 9.2: I2S_INT_RAW_REG (0x000c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for the I2S_OUT_TOTAL_EOF_INT interrupt. (RO) I2S_IN_DSCR_EMPTY_INT_RAW The raw interrupt status bit for the I2S_IN_DSCR_EMPTY_INT interrupt. (RO) I2S_OUT_DSCR_ERR_INT_RAW The raw interrupt status bit for the I2S_OUT_DSCR_ERR_INT interrupt. (RO) I2S_IN_DSCR_ERR_INT_RAW The raw interrupt status bit for the I2S_IN_DSCR_ERR_INT interrupt. (RO) I2S_OUT_EOF_INT_RAW The raw interrupt status bit for the I2S_OUT_EOF_INT interrupt. (RO) I2S_OUT_DONE_INT_RAW The raw interrupt status bit for the I2S_OUT_DONE_INT interrupt. (RO) I2S_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the I2S_IN_SUC_EOF_INT interrupt. (RO) I2S_IN_DONE_INT_RAW The raw interrupt status bit for the I2S_IN_DONE_INT interrupt. (RO) I2S_TX_HUNG_INT_RAW The raw interrupt status bit for the I2S_TX_HUNG_INT interrupt. (RO) I2S_RX_HUNG_INT_RAW The raw interrupt status bit for the I2S_RX_HUNG_INT interrupt. (RO) I2S_TX_REMPTY_INT_RAW The raw interrupt status bit for the I2S_TX_REMPTY_INT interrupt. (RO) I2S_TX_WFULL_INT_RAW The raw interrupt status bit for the I2S_TX_WFULL_INT interrupt. (RO) I2S_RX_REMPTY_INT_RAW The raw interrupt status bit for the I2S_RX_REMPTY_INT interrupt. (RO) I2S_RX_WFULL_INT_RAW The raw interrupt status bit for the I2S_RX_WFULL_INT interrupt. (RO) I2S_TX_PUT_DATA_INT_RAW The raw interrupt status bit for the I2S_TX_PUT_DATA_INT interrupt. (RO) I2S_RX_TAKE_DATA_INT_RAW The raw interrupt status bit for the I2S_RX_TAKE_DATA_INT interrupt. (RO) Espressif Systems 211 ESP32 Technical Reference Manual V2.0 9. I2S (re se rv ed ) I2 S_ I2 OU S_ T_ I2 IN_ TO S_ D TA S I2 OU CR L_E S_ T_ _ O E I2 IN_ DS MP F_I S_ D C T NT R S I2 OU CR _E Y_I _ST S_ T_ _ R NT E R (re OU EO RR _IN _S se T_ F_ _I T T I2 rve DO INT NT _ST S_ d N _S _S ) E_ T T I2 IN_ IN S_ S T_ U ST I2 TX_ C_ S_ D E O O T I2 X_ N F_ S_ H E_ IN I2 RX UN INT T_S S_ _H G _S T _ I2 TX_ UN INT T S_ R G _ _ S I2 TX_ EM INT T S_ W PT _ S I2 RX FU Y_I T S_ _R LL N T I2 RX EM _IN _S S_ _W P T_ T T I2 TX_ FU Y_ ST S _ P LL IN RX UT _I T_ _T _D NT ST AK AT _S E_ A_ T D A IN TA T_S _I T NT _S T Register 9.3: I2S_INT_ST_REG (0x0010) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the I2S_OUT_TOTAL_EOF_INT interrupt. (RO) I2S_IN_DSCR_EMPTY_INT_ST The masked interrupt status bit for the I2S_IN_DSCR_EMPTY_INT interrupt. (RO) I2S_OUT_DSCR_ERR_INT_ST The masked interrupt status bit for the I2S_OUT_DSCR_ERR_INT interrupt. (RO) I2S_IN_DSCR_ERR_INT_ST The masked interrupt status bit for the I2S_IN_DSCR_ERR_INT interrupt. (RO) I2S_OUT_EOF_INT_ST The masked interrupt status bit for the I2S_OUT_EOF_INT interrupt. (RO) I2S_OUT_DONE_INT_ST The masked interrupt status bit for the I2S_OUT_DONE_INT interrupt. (RO) I2S_IN_SUC_EOF_INT_ST The masked interrupt status bit for the I2S_IN_SUC_EOF_INT interrupt. (RO) I2S_IN_DONE_INT_ST The masked interrupt status bit for the I2S_IN_DONE_INT interrupt. (RO) I2S_TX_HUNG_INT_ST The masked interrupt status bit for the I2S_TX_HUNG_INT interrupt. (RO) I2S_RX_HUNG_INT_ST The masked interrupt status bit for the I2S_RX_HUNG_INT interrupt. (RO) I2S_TX_REMPTY_INT_ST The masked interrupt status bit for the I2S_TX_REMPTY_INT interrupt. (RO) I2S_TX_WFULL_INT_ST The masked interrupt status bit for the I2S_TX_WFULL_INT interrupt. (RO) I2S_RX_REMPTY_INT_ST The masked interrupt status bit for the I2S_RX_REMPTY_INT interrupt. (RO) I2S_RX_WFULL_INT_ST The masked interrupt status bit for the I2S_RX_WFULL_INT interrupt. (RO) I2S_TX_PUT_DATA_INT_ST The masked interrupt status bit for the I2S_TX_PUT_DATA_INT interrupt. (RO) I2S_RX_TAKE_DATA_INT_ST The masked interrupt status bit for the I2S_RX_TAKE_DATA_INT interrupt. (RO) Espressif Systems 212 ESP32 Technical Reference Manual V2.0 9. I2S (re se rv ed ) I2 S_ I2 OU S_ T_ I2 IN_ TO S_ D TA S I2 OU CR L_E S_ T_ _ O E I2 IN_ DS MP F_I S_ D C T NT R S I2 OU CR _E Y_I _EN S_ T_ _ R NT A E R (re OU EO RR _IN _EN se T_ F_ _I T A I2 rve DO INT NT _EN S_ d N _E _E A ) E_ N N I2 IN_ IN A A S_ S T_ U EN I2 IN_ C_ S_ D E A O O T I2 X_ NE F_ S_ H _ IN I I2 RX UN NT T_E S_ _H G _E N _ I2 TX_ UN INT NA A S_ R G _ _ E I2 TX_ EM INT NA S_ W PT _ E I2 RX FU Y_I NA S_ _R LL N T I2 RX EM _IN _E S_ _W P T_ N A T I2 TX_ FU Y_ EN S_ P LL IN A RX UT _I T_ _T _D NT EN AK AT _E A E_ A_ NA D A IN TA T_E _I N NT A _E NA Register 9.4: I2S_INT_ENA_REG (0x0014) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the I2S_OUT_TOTAL_EOF_INT interrupt. (R/W) I2S_IN_DSCR_EMPTY_INT_ENA The interrupt enable bit for the I2S_IN_DSCR_EMPTY_INT interrupt. (R/W) I2S_OUT_DSCR_ERR_INT_ENA The interrupt enable bit for the I2S_OUT_DSCR_ERR_INT interrupt. (R/W) I2S_IN_DSCR_ERR_INT_ENA The interrupt enable bit for the I2S_IN_DSCR_ERR_INT interrupt. (R/W) I2S_OUT_EOF_INT_ENA The interrupt enable bit for the I2S_OUT_EOF_INT interrupt. (R/W) I2S_OUT_DONE_INT_ENA The interrupt enable bit for the I2S_OUT_DONE_INT interrupt. (R/W) I2S_IN_SUC_EOF_INT_ENA The interrupt enable bit for the I2S_IN_SUC_EOF_INT interrupt. (R/W) I2S_IN_DONE_INT_ENA The interrupt enable bit for the I2S_IN_DONE_INT interrupt. (R/W) I2S_TX_HUNG_INT_ENA The interrupt enable bit for the I2S_TX_HUNG_INT interrupt. (R/W) I2S_RX_HUNG_INT_ENA The interrupt enable bit for the I2S_RX_HUNG_INT interrupt. (R/W) I2S_TX_REMPTY_INT_ENA The interrupt enable bit for the I2S_TX_REMPTY_INT interrupt. (R/W) I2S_TX_WFULL_INT_ENA The interrupt enable bit for the I2S_TX_WFULL_INT interrupt. (R/W) I2S_RX_REMPTY_INT_ENA The interrupt enable bit for the I2S_RX_REMPTY_INT interrupt. (R/W) I2S_RX_WFULL_INT_ENA The interrupt enable bit for the I2S_RX_WFULL_INT interrupt. (R/W) I2S_TX_PUT_DATA_INT_ENA The interrupt enable bit for the I2S_TX_PUT_DATA_INT interrupt. (R/W) I2S_RX_TAKE_DATA_INT_ENA The interrupt enable bit for the I2S_RX_TAKE_DATA_INT interrupt. (R/W) Espressif Systems 213 ESP32 Technical Reference Manual V2.0 9. I2S (re se r ve d) I2 S_ I2 OU S_ T_ I2 IN_ TO S_ D TA S I2 OU CR L_E S_ T_ _ O E I2 IN_ DS MP F_I S_ D C T NT R S I2 OU CR _E Y_I _C S_ T_ _ R NT LR E R (re OU EO RR _IN _C se T_ F_ _I T LR I2 rve DO INT NT _CL S_ d N _C _C R ) E_ L L I2 IN_ IN R R S_ S T_ U CL I2 IN_ C_ S_ D E R O O T I2 X_ NE F_ S_ H _ IN I I2 RX UN NT T_C S_ _H G _C L _ I2 TX_ UN INT LR R S_ R G _ _ C I2 TX_ EM INT LR S_ W PT _ C I2 RX FU Y_I LR S_ _R LL N T I2 RX EM _IN _C S_ _W P T_ LR T I2 TX_ FU Y_ CL S_ P LL IN R RX UT _I T_ _T _D NT CL AK AT _C R E_ A_ LR D A IN TA T_C _I LR NT _C LR Register 9.5: I2S_INT_CLR_REG (0x0018) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_OUT_TOTAL_EOF_INT_CLR Set this bit to clear the I2S_OUT_TOTAL_EOF_INT interrupt. (WO) I2S_IN_DSCR_EMPTY_INT_CLR Set this bit to clear the I2S_IN_DSCR_EMPTY_INT interrupt. (WO) I2S_OUT_DSCR_ERR_INT_CLR Set this bit to clear the I2S_OUT_DSCR_ERR_INT interrupt. (WO) I2S_IN_DSCR_ERR_INT_CLR Set this bit to clear the I2S_IN_DSCR_ERR_INT interrupt. (WO) I2S_OUT_EOF_INT_CLR Set this bit to clear the I2S_OUT_EOF_INT interrupt. (WO) I2S_OUT_DONE_INT_CLR Set this bit to clear the I2S_OUT_DONE_INT interrupt. (WO) I2S_IN_SUC_EOF_INT_CLR Set this bit to clear the I2S_IN_SUC_EOF_INT interrupt. (WO) I2S_IN_DONE_INT_CLR Set this bit to clear the I2S_IN_DONE_INT interrupt. (WO) I2S_TX_HUNG_INT_CLR Set this bit to clear the I2S_TX_HUNG_INT interrupt. (WO) I2S_RX_HUNG_INT_CLR Set this bit to clear the I2S_RX_HUNG_INT interrupt. (WO) I2S_TX_REMPTY_INT_CLR Set this bit to clear the I2S_TX_REMPTY_INT interrupt. (WO) I2S_TX_WFULL_INT_CLR Set this bit to clear the I2S_TX_WFULL_INT interrupt. (WO) I2S_RX_REMPTY_INT_CLR Set this bit to clear the I2S_RX_REMPTY_INT interrupt. (WO) I2S_RX_WFULL_INT_CLR Set this bit to clear the I2S_RX_WFULL_INT interrupt. (WO) I2S_TX_PUT_DATA_INT_CLR Set this bit to clear the I2S_TX_PUT_DATA_INT interrupt. (WO) I2S_RX_TAKE_DATA_INT_CLR Set this bit to clear the I2S_RX_TAKE_DATA_INT interrupt. (WO) Espressif Systems 214 ESP32 Technical Reference Manual V2.0 9. I2S 0 0 0 0 I2 S BC TX _ I2 S S_ I2 0 _D ) ed rv se (re 31 0 K AT _IN _I A_ NV EN _R AB I2 X S_ _D TX SY LE_ DE _D N I2 LA SY C_ S_ S Y N W RX _B C_S CK W I2 S_ _O RX UT _W _D EL S I2 _ AY S_ O UT TX _D _S EL D_ I2 AY O S_ U TX T_ DE _W LA S_ I2 Y O S_ UT TX _ _B DE CK LA I2 _O Y S_ RX UT _S _D D_ EL I2 IN AY S_ _ RX DE _W LA Y S_ I2 S_ IN _ RX DE _B LA C Y I2 K_ S_ IN TX _D _W EL S AY I2 _I S_ N_ TX DE _B LA CK Y _I N_ DE LA Y Register 9.6: I2S_TIMING_REG (0x001c) 25 24 23 22 21 20 19 18 0 0 0 0 0 0 0 0 0 17 16 15 0 0 14 13 0 0 12 11 0 0 10 9 0 0 8 7 0 0 6 5 0 0 4 3 0 0 2 1 0 0 0 0 Reset I2S_TX_BCK_IN_INV Set this bit to invert the BCK signal into the slave transmitter. (R/W) I2S_DATA_ENABLE_DELAY Number of delay cycles for data valid flag. (R/W) I2S_RX_DSYNC_SW Set this bit to synchronize signals into the receiver in double sync method. (R/W) I2S_TX_DSYNC_SW Set this bit to synchronize signals into the transmitter in double sync method. (R/W) I2S_RX_BCK_OUT_DELAY Number of delay cycles for BCK signal out of the receiver. (R/W) I2S_RX_WS_OUT_DELAY Number of delay cycles for WS signal out of the receiver. (R/W) I2S_TX_SD_OUT_DELAY Number of delay cycles for SD signal out of the transmitter. (R/W) I2S_TX_WS_OUT_DELAY Number of delay cycles for WS signal out of the transmitter. (R/W) I2S_TX_BCK_OUT_DELAY Number of delay cycles for BCK signal out of the transmitter. (R/W) I2S_RX_SD_IN_DELAY Number of delay cycles for SD signal into the receiver. (R/W) I2S_RX_WS_IN_DELAY Number of delay cycles for WS signal into the receiver. (R/W) I2S_RX_BCK_IN_DELAY Number of delay cycles for BCK signal into the receiver. (R/W) I2S_TX_WS_IN_DELAY Number of delay cycles for WS signal into the transmitter. (R/W) I2S_TX_BCK_IN_DELAY Number of delay cycles for BCK signal into the transmitter. (R/W) Espressif Systems 215 ESP32 Technical Reference Manual V2.0 9. I2S 31 0 0 0 0 0 0 0 0 0 0 21 20 19 18 0 0 0 0 16 0 15 0 0 0 13 12 0 1 _D AT A_ NU M _N UM RX _D AT A S_ S_ TX 11 I2 I2 (re s er ve d ) I2 S_ I2 RX S_ _F TX IFO _F _ IF MO O I2 _ M D_ S_ RX O FO D_ R _F FO CE IF O RC _E _M E_ N O I2 EN D S_ TX _F IF O I2 _M S_ DS O D CR _E N Register 9.7: I2S_FIFO_CONF_REG (0x0020) 6 5 32 0 32 Reset I2S_RX_FIFO_MOD_FORCE_EN The bit should always be set to 1. (R/W) I2S_TX_FIFO_MOD_FORCE_EN The bit should always be set to 1. (R/W) I2S_RX_FIFO_MOD Receive FIFO mode configuration bit. (R/W) I2S_TX_FIFO_MOD Transmit FIFO mode configuration bit. (R/W) I2S_DSCR_EN Set this bit to enable I2S DMA mode. (R/W) I2S_TX_DATA_NUM Threshold of data length in the transmit FIFO. (R/W) I2S_RX_DATA_NUM Threshold of data length in the receive FIFO. (R/W) Register 9.8: I2S_RXEOF_NUM_REG (0x0024) 31 0 64 Reset I2S_RXEOF_NUM_REG The length of the data to be received. It will trigger I2S_IN_SUC_EOF_INT. (R/W) Register 9.9: I2S_CONF_SINGLE_DATA_REG (0x0028) 31 0 0 Reset I2S_CONF_SINGLE_DATA_REG The right channel or the left channel outputs constant values stored in this register according to TX_CHAN_MOD and I2S_TX_MSB_RIGHT. (R/W) Espressif Systems 216 ESP32 Technical Reference Manual V2.0 9. I2S 31 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 RX _C HA N_ I2 S_ M O TX D _C HA N_ M O D I2 (re S_ se rv ed ) Register 9.10: I2S_CONF_CHAN_REG (0x002c) 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 3 2 0 0 0 0 0 Reset I2S_RX_CHAN_MOD I2S receiver channel mode configuration bits. Please refer to Section 9.4.5 for further details. (R/W) I2S_TX_CHAN_MOD I2S transmitter channel mode configuration bits. Please refer to Section 9.4.4 for further details. (R/W) 31 30 29 28 27 0 0 0 0 0 R DD _A LI NK ) _O UT ve d I2 S (re se r (re se I2 rve S_ d ) I2 OU S_ TL I2 OU INK S_ TL _ O IN RE UT K S LI _S TA NK TA RT _S RT TO P Register 9.11: I2S_OUT_LINK_REG (0x0030) 20 0 0 0 0 0 0 19 0 0 0x000000 Reset I2S_OUTLINK_RESTART Set this bit to restart outlink descriptor. (R/W) I2S_OUTLINK_START Set this bit to start outlink descriptor. (R/W) I2S_OUTLINK_STOP Set this bit to stop outlink descriptor. (R/W) I2S_OUTLINK_ADDR The address of first outlink descriptor. (R/W) 31 30 29 28 27 0 0 0 0 0 R DD _A NK LI d) IN rv e I2 S_ (re se (re se I2 rve S_ d ) I2 INL S_ IN I2 INL K_R S_ IN E IN K_ ST LI S A NK TA RT _S RT TO P Register 9.12: I2S_IN_LINK_REG (0x0034) 20 0 0 0 0 0 0 19 0 0 0x000000 Reset I2S_INLINK_RESTART Set this bit to restart inlink descriptor. (R/W) I2S_INLINK_START Set this bit to start inlink descriptor. (R/W) I2S_INLINK_STOP Set this bit to stop inlink descriptor. (R/W) I2S_INLINK_ADDR The address of first inlink descriptor. (R/W) Espressif Systems 217 ESP32 Technical Reference Manual V2.0 9. I2S Register 9.13: I2S_OUT_EOF_DES_ADDR_REG (0x0038) 31 0 0x000000000 Reset I2S_OUT_EOF_DES_ADDR_REG The address of outlink descriptor that produces EOF. (RO) Register 9.14: I2S_IN_EOF_DES_ADDR_REG (0x003c) 31 0 0x000000000 Reset I2S_IN_EOF_DES_ADDR_REG The address of inlink descriptor that produces EOF. (RO) Register 9.15: I2S_OUT_EOF_BFR_DES_ADDR_REG (0x0040) 31 0 0x000000000 Reset I2S_OUT_EOF_BFR_DES_ADDR_REG The address of the buffer corresponding to the outlink descriptor that produces EOF. (RO) Register 9.16: I2S_INLINK_DSCR_REG (0x0048) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_INLINK_DSCR_REG The address of current inlink descriptor. (RO) Register 9.17: I2S_INLINK_DSCR_BF0_REG (0x004c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 Reset I2S_INLINK_DSCR_BF0_REG The address of next inlink descriptor. (RO) Register 9.18: I2S_INLINK_DSCR_BF1_REG (0x0050) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_INLINK_DSCR_BF1_REG The address of next inlink data buffer. (RO) Espressif Systems 218 ESP32 Technical Reference Manual V2.0 9. I2S Register 9.19: I2S_OUTLINK_DSCR_REG (0x0054) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset I2S_OUTLINK_DSCR_REG The address of current outlink descriptor. (RO) Register 9.20: I2S_OUTLINK_DSCR_BF0_REG (0x0058) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 Reset I2S_OUTLINK_DSCR_BF0_REG The address of next outlink descriptor. (RO) Register 9.21: I2S_OUTLINK_DSCR_BF1_REG (0x005c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_OUTLINK_DSCR_BF1_REG The address of next outlink data buffer. (RO) Espressif Systems 219 ESP32 Technical Reference Manual V2.0 9. I2S I2 S (re s er ve d) _ I2 CH S_ EC I2 OU K_ S_ T_ O W I2 IND DA N S_ S TA ER C I2 OU R_ _BU S_ TD B R (re OU SC UR ST se T_ R_ ST _E I2 rve EO BU _EN N S_ d F_ R ) M ST I2 OU O _ S_ T_ DE EN I2 OU AU S_ T_ TO I2 IN_ LO _W S_ LO O R P I2 AH OP _T BAC S_ BM _ ES K T I2 AH _R ES T S_ BM S T T I2 OU _F S_ T_ IF IN R O_ _R ST R ST ST Register 9.22: I2S_LC_CONF_REG (0x0060) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset I2S_CHECK_OWNER Set this bit to check the owner bit by hardware. (R/W) I2S_OUT_DATA_BURST_EN Transmitter data transfer mode configuration bit. (R/W) 1: Transmit data in burst mode; 0: Transmit data in byte mode. I2S_INDSCR_BURST_EN DMA inlink descriptor transfer mode configuration bit. (R/W) 1: Transfer inlink descriptor in burst mode; 0: Transfer inlink descriptor in byte mode. I2S_OUTDSCR_BURST_EN DMA outlink descriptor transfer mode configuration bit. (R/W) 1: Transfer outlink descriptor in burst mode; 0: Transfer outlink descriptor in byte mode. I2S_OUT_EOF_MODE DMA I2S_OUT_EOF_INT generation mode. (R/W) 1: When DMA has popped all data from the FIFO; 0: When AHB has pushed all data to the FIFO. I2S_OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. (R/W) I2S_OUT_LOOP_TEST Set this bit to loop test outlink. (R/W) I2S_IN_LOOP_TEST Set this bit to loop test inlink. (R/W) I2S_AHBM_RST Set this bit to reset AHB interface of DMA. (R/W) I2S_AHBM_FIFO_RST Set this bit to reset AHB interface cmdFIFO of DMA. (R/W) I2S_OUT_RST Set this bit to reset out DMA FSM. (R/W) I2S_IN_RST Set this bit to reset in DMA FSM. (R/W) Register 9.23: I2S_LC_STATE0_REG (0x006c) 31 0 0x000000000 Reset I2S_LC_STATE0_REG Receiver DMA channel status register. (RO) Espressif Systems 220 ESP32 Technical Reference Manual V2.0 9. I2S Register 9.24: I2S_LC_STATE1_REG (0x0070) 31 0 0x000000000 Reset I2S_LC_STATE1_REG Transmitter DMA channel status register. (RO) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 11 10 0 1 0 EO UT UT _ _T IM FI FO IF O LC _ _F I2 S_ S_ LC I2 I2 (re S_ se r ve d) LC _F I FO _T _T IM IM EO EO UT _ EN A SH IF T Register 9.25: I2S_LC_HUNG_CONF_REG (0x0074) 8 0 7 0 0 0x010 Reset I2S_LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout. (R/W) I2S_LC_FIFO_TIMEOUT_SHIFT The bits are used to set the tick counter threshold. The tick counter is reset when the counter value >= 88000/2i2s_lc_fifo_timeout_shift . (R/W) I2S_LC_FIFO_TIMEOUT When the value of FIFO hung counter is equal to this bit value, sending data-timeout interrupt or receiving data-timeout interrupt will be triggered. (R/W) Espressif Systems 221 ESP32 Technical Reference Manual V2.0 9. I2S (re s er ve d) I2 S_ I2 TX_ S_ S RX TO _P P_ CM EN I2 S_ _B RX YP _P AS C S I2 M S_ _C TX O NF _P CM I2 S_ _B TX YP _P AS CM S _C O NF Register 9.26: I2S_CONF1_REG (0x00a0) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 0 0 1 6 4 0x0 3 2 0 1 0x1 Reset I2S_TX_STOP_EN Set this bit and the transmitter will stop transmitting BCK signal and WS signal when tx FIFO is empty. (R/W) I2S_RX_PCM_BYPASS Set this bit to bypass the Compress/Decompress module for the received data. (R/W) I2S_RX_PCM_CONF Compress/Decompress module configuration bit. (R/W) 0: Decompress received data; 1: Compress received data. I2S_TX_PCM_BYPASS Set this bit to bypass the Compress/Decompress module for the transmitted data. (R/W) I2S_TX_PCM_CONF Compress/Decompress module configuration bit. (R/W) 0: Decompress transmitted data; 1: Compress transmitted data. (re se r ve d) (re se (re rve se d) I2 rve S_ d ) I2 FIF S_ O _ FI FO FO R _F C O E_ RC PU E_ PD Register 9.27: I2S_PD_CONF_REG (0x00a4) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 1 0 1 0 Reset I2S_FIFO_FORCE_PU Force FIFO power-up. (R/W) I2S_FIFO_FORCE_PD Force FIFO power-down. (R/W) Espressif Systems 222 ESP32 Technical Reference Manual V2.0 9. I2S I2 S (re s er ve d) _ I2 INT S_ E R I2 EXT _V S_ _ AL LC AD ID _ (re D_E C_S EN se N TA rv RT ed _E I2 S_ ) N L I2 C S_ D_ I2 LC TX_ S_ D_ S CA TX DX M _W 2_ ER R EN A_ X2 EN _E N Register 9.28: I2S_CONF2_REG (0x00a8) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 0 Reset I2S_INTER_VALID_EN Set this bit to enable camera’s internal validation. (R/W) I2S_EXT_ADC_START_EN Set this bit to enable the start of external ADC . (R/W) I2S_LCD_EN Set this bit to enable LCD mode. (R/W) I2S_LCD_TX_SDX2_EN Set this bit to duplicate data pairs (Data Frame, Form 2) in LCD mode. (R/W) I2S_LCD_TX_WRX2_EN One datum will be written twice in LCD mode. (R/W) I2S_CAMERA_EN Set this bit to enable camera mode. (R/W) 21 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _D IV _ _B 19 14 0x00 CL KM I2 I2 S_ _C S_ CL LK M _D KM _D IV IV _ A 22 I2 S I2 S_ (re CL se KA rv _E ed N ) A ) ve d (re se r 31 NU M Register 9.29: I2S_CLKM_CONF_REG (0x00ac) 13 8 0x00 7 0 4 Reset I2S_CLKA_ENA Set this bit to enable clk_apll. (R/W) I2S_CLKM_DIV_A Fractional clock divider’s denominator value. (R/W) I2S_CLKM_DIV_B Fractional clock divider’s numerator value. (R/W) I2S_CLKM_DIV_NUM I2S clock divider’s integral value. (R/W) Espressif Systems 223 ESP32 Technical Reference Manual V2.0 9. I2S 0 0 0 0 0 0 23 18 16 17 12 16 _B CK _D IV _ NU M V_ NU M _B CK _D I TX RX S_ S_ 11 I2 I2 I2 S_ I2 S_ 24 0 TX _B IT S _B IT S RX ve d) er (re s 31 0 _M _M O O D D Register 9.30: I2S_SAMPLE_RATE_CONF_REG (0x00b0) 6 6 5 0 6 Reset I2S_RX_BITS_MOD Set the bits to configure the bit length of I2S receiver channel. (R/W) I2S_TX_BITS_MOD Set the bits to configure the bit length of I2S transmitter channel. (R/W) I2S_RX_BCK_DIV_NUM Bit clock configuration bit in receiver mode. (R/W) I2S_TX_BCK_DIV_NUM Bit clock configuration bit in transmitter mode. (R/W) Espressif Systems 224 ESP32 Technical Reference Manual V2.0 9. I2S 31 0 0 0 0 0 26 25 24 0 0 1 23 22 0x1 21 20 19 0x1 18 0x1 17 16 0x1 15 8 0 0 0 0 0 _S IN _ C_ I2 PD O S_ M SR 2 I2 PC PC 2 S_ M M 2 I2 RX PD _CO S_ _P M N TX DM _C V _ P _ O _E DM EN NV N _E _E N N M _P D TX I2 S S_ I2 (re I2 S se rv ed ) _ I2 TX_ S_ P RX DM _P _H I2 D P S_ TX M_ _BY SI _P P DM NC AS I2 _D S S_ _S SR TX IG _1 M _P 6_ A DM DE EN I2 S_ LT _S A_ TX IN IN C_ _P _S IN DM I2 HI _ SH S_ _L FT P_ TX IF T IN _P _S DM HI _H FT P_ IN _S HI FT (re se rv ed ) Register 9.31: I2S_PDM_CONF_REG (0x00b4) 0 0 7 0 4 0x02 3 2 1 0 1 1 0 0 Reset I2S_TX_PDM_HP_BYPASS Set this bit to bypass the transmitter’s PDM HP filter. (R/W) I2S_RX_PDM_SINC_DSR_16_EN PDM downsampling rate for filter group 1 in receiver mode. (R/W) 1: downsampling rate = 128; 0: downsampling rate = 64. I2S_TX_PDM_SIGMADELTA_IN_SHIFT Adjust the size of the input signal into filter module. (R/W) 0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4. I2S_TX_PDM_SINC_IN_SHIFT Adjust the size of the input signal into filter module. (R/W) 0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4. I2S_TX_PDM_LP_IN_SHIFT Adjust the size of the input signal into filter module. (R/W) 0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4. I2S_TX_PDM_HP_IN_SHIFT Adjust the size of the input signal into filter module. (R/W) 0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4. I2S_TX_PDM_SINC_OSR2 Upsampling rate = 64×i2s_tx_pdm_sinc_osr2 (R/W) I2S_PDM2PCM_CONV_EN Set this bit to enable PDM-to-PCM converter. (R/W) I2S_PCM2PDM_CONV_EN Set this bit to enable PCM-to-PDM converter. (R/W) I2S_RX_PDM_EN Set this bit to enable receiver’s PDM mode. (R/W) I2S_TX_PDM_EN Set this bit to enable transmitter’s PDM mode. (R/W) _P D TX ed ) 0 0 0 0 0 0 0 0 0 0 19 I2 I2 20 0 S_ S_ se rv (re 31 0 TX _P DM M _F _F S P Register 9.32: I2S_PDM_FREQ_CONF_REG (0x00b8) 10 9 960 0 441 Reset I2S_TX_PDM_FP PCM-to-PDM converter’s PDM frequency parameter. (R/W) I2S_TX_PDM_FS PCM-to-PDM converter’s PCM frequency parameter. (R/W) Espressif Systems 225 ESP32 Technical Reference Manual V2.0 9. I2S I2 (re s er ve d) S_ I2 RX S_ _F I2 TX_ IFO S_ F _R TX IFO ES _ I _R E D L E T_ E SE BA T_ C BA K CK Register 9.33: I2S_STATE_REG (0x00bc) 31 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 1 Reset I2S_RX_FIFO_RESET_BACK This bit is used to confirm if the Rx FIFO reset is done. 1: reset is not ready; 0: reset is ready. (RO) I2S_TX_FIFO_RESET_BACK This bit is used to confirm if the Tx FIFO reset is done. 1: reset is not ready; 0: reset is ready. (RO) I2S_TX_IDLE The status bit of the transmitter. 1: the transmitter is idle; 0: the transmitter is busy. (RO) Espressif Systems 226 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 10. UART Controllers 10.1 Overview Embedded applications often require a simple method of exchanging data between devices that need minimal system resources. The Universal Asynchronous Receiver/Transmitter (UART) is one such standard that can realize a flexible full-duplex data exchange among different devices. The three UART controllers available on a chip are compatible with UART-enabled devices from various manufacturers. The UART can also carry out an IrDA (Infrared Data Exchange), or function as an RS-485 modem. All UART controllers integrated in the ESP32 feature an identical set of registers for ease of programming and flexibility. In this documentation, these controllers are referred to as UARTn, where n = 0, 1, and 2, referring to UART0, UART1, and UART2, respectively. 10.2 UART Features The UART modules have the following main features: • Programmable baud rate • 1024 x 8-bit RAM shared by three UART transmit-FIFOs and receive-FIFOs • Supports input baud rate self-check • Supports 5/6/7/8 bits of data length • Supports 1/1.5/2/3/4 STOP bits • Supports parity bit • Supports RS485 Protocol • Supports IrDA Protocol • Supports DMA to communicate data in high speed • Supports UART wake-up • Supports both software and hardware flow control 10.3 Functional Description 10.3.1 Introduction UART is a character-oriented data link that can be used to achieve communication between two devices. The asynchronous mode of transmission means that it is not necessary to add clocking information to the data being sent. This, in turn, requires that the data rate, STOP bits, parity, etc., be identical at the transmitting and receiving end for the devices to communicate successfully. A typical UART frame begins with a START bit, followed by a “character” and an optional parity bit for error detection, and it ends with a STOP condition. The UART controllers available on the ESP32 provide hardware support for multiple lengths of data and STOP bits. In addition, the controllers support both software and hardware flow control, as well as DMA, for seamless high-speed data transfer. This allows the developer to employ multiple UART ports in the system with minimal software overhead. Espressif Systems 227 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 10.3.2 UART Architecture Figure 64: UART Basic Structure Figure 64 shows the basic block diagram of the UART controller. The UART block can derive its clock from two sources: the 80-MHz APB_CLK, or the reference clock REF_TICK (please refer to Chapter Reset and Clock for more details). These two clock sources can be selected by configuring UART_TICK_REF_ALWAYS_ON. Then, a divider in the clock path divides the selected clock source to generate clock signals that drive the UART module. UART_CLKDIV_REG contains the clock divider value in two parts — UART_CLKDIV (integral part) and UART_CLKDIV_FRAG (decimal part). The UART controller can be further broken down into two functional blocks — the transmit block and the receive block. The transmit block contains a transmit-FIFO buffer, which buffers data awaiting to be transmitted. Software can write Tx_FIFO via APB, and transmit data into Tx_FIFO via DMA. Tx_FIFO_Ctrl is used to control read- and write-access to the Tx_FIFO. When Tx_FIFO is not null, Tx_FSM reads data via Tx_FIFO_Ctrl, and transmits data out according to the set frame format. The outgoing bit stream can be inverted by appropriately configuring the register UART_TXD_INV. The receive-block contains a receive-FIFO buffer, which buffers incoming data awaiting to be processed. The input bit stream, rxd_in, is fed to the UART controller. Negation of the input stream can be controlled by configuring the UART_RXD_INV register. Baudrate_Detect measures the baud rate of the input signal by measuring the minimum pulse width of the input bit stream. Start_Detect is used to detect a START bit in a frame of incoming data. After detecting the START bit, RX_FSM stores data retrieved from the received frame into Rx_FIFO through Rx_FIFO_Ctrl. Software can read data in the Rx_FIFO through the APB. In order to free the CPU from engaging in data transfer operations, the DMA can be configured for sending or receiving data. HW_Flow_Ctrl is able to control the data flow of rxd_in and txd_out through standard UART RTS and CTS flow control signals (rtsn_out and ctsn_in). SW_Flow_Ctrl controls the data flow by inserting special characters in the incoming and outgoing data flow. When UART is in Light-sleep mode (refer to Chapter RTC), Wakeup_Ctrl will start counting pulses in rxd_in. If the number of pulses is greater than UART_ACTIVE_THRESHOLD, a wake_up signal will be generated and sent to RTC. RTC will then wake up the UART controller. Espressif Systems 228 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 10.3.3 UART RAM Figure 65: UART shared RAM Three UART controllers share a 1024 x 8-bit RAM space. As illustrated in Figure 65, RAM is allocated in different blocks. One block holds 128 x 8-bit data. Figure 65 illustrates the default RAM allocated to Tx_FIFO and Rx_FIFO of the three UART controllers. Tx_FIFO of UARTn can be extended by setting UARTn_TX_SIZE, while Rx_FIFO of UARTn can be extended by setting UARTn_RX_SIZE. NOTICE: Extending the FIFO space of a UART controller may take up the FIFO space of another UART controller. If none of the UART controllers is active, setting UART_MEM_PD, UART1_MEM_PD, and UART2_MEM_PD can prompt the RAM to enter low-power mode. 10.3.4 Baud Rate Detection Setting UART_AUTOBAUD_EN for a UART controller will enable the baud rate detection function. The Baudrate_Detect block shown in Figure 64 can filter glitches with a pulse width lower than UART_GLITCH_FILT. In order to use the baud rate detection feature, some random data should be sent to the receiver before starting the UART communication stream. This is required so that the baud rate can be determined based on the pulse width. UART_LOWPULSE_MIN_CNT stores minimum low-pulse width, UART_HIGHPULSE_MIN_CNT stores minimum high-pulse width. By reading these two registers, software can calculate the baud rate of the transmitter. 10.3.5 UART Data Frame Figure 66 shows the basic data frame structure. A data frame starts with a START condition and ends with a STOP condition. The START condition requires 1 bit and the STOP condition can be realized using 1/1.5/2/3/4-bit widths (as set by UART_BIT_NUM, UART_DL1_EN, and UAR_DL0_EN). The START is low level, while the STOP is high level. Espressif Systems 229 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS Figure 66: UART Data Frame Structure The length of a character (BIT0 to BITn) can comprise 5 to 8 bits and can be configured by UART_BIT_NUM. When UART_PARITY_EN is set, the UART controller hardware will add the appropriate parity bit after the data. UART_PARITY is used to select odd parity or even parity. If the receiver detects an error in the input character, interrupt UART_PARITY_ERR_INT will be generated. If the receiver detects an error in the frame format, interrupt UART_FRM_ERR_INT will be generated. Interrupt UART_TX_DONE_INT will be generated when all data in Tx_FIFO have been transmitted. When UART_TXD_BRK is set, the transmitter sends several NULL characters after the process of sending data is completed. The number of NULL characters can be configured by UART_TX_BRK_NUM. After the transmitter finishes sending all NULL characters, interrupt UART_TX_BRK_DONE_INT will be generated. The minimum interval between data frames can be configured with UART_TX_IDLE_NUM. If the idle time of a data frame is equal to, or larger than, the configured value of register UART_TX_IDLE_NUM, interrupt UART_TX_BRK_IDLE_DONE_INT will be generated. Figure 67: AT_CMD Character Format Figure 67 shows a special AT_CMD character format. If the receiver constantly receives UART_AT_CMD_CHAR characters and these characters satisfy the following conditions, interrupt UART_AT_CMD_CHAR_DET_INT will be generated. • Between the first UART_AT_CMD_CHAR and the last non-UART_AT_CMD_CHAR, there are at least UART_PER_IDLE_NUM APB clock cycles. • Between every UART_AT_CMD_CHAR character there are at least UART_RX_GAP_TOUT APB clock cycles. • The number of received UART_AT_CMD_CHAR characters must be equal to, or greater than, UART_CHAR_NUM. • Between the last UART_AT_CMD_CHAR character received and the next non-UART_AT_CMD_CHAR, there are at least UART_POST_IDLE_NUM APB clock cycles. 10.3.6 Flow Control UART controller supports both hardware and software flow control. Hardware flow control regulates data flow through input signal dsrn_in and output signal rtsn_out. Software flow control regulates data flow by inserting special characters in the flow of sent data and by detecting special characters in the flow of received data. Espressif Systems 230 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 10.3.6.1 Hardware Flow Control Figure 68: Hardware Flow Control Figure 68 illustrates how the UART hardware flow control works. In hardware flow control, a high state of the output signal rtsn_out signifies that a data transmission is requested, while a low state of the same signal notifies the counterpart to stop data transmission until rtsn_out is pulled high again. There are two ways for a transmitter to realize hardware flow control: • UART_RX_FLOW_EN is 0: The level of rtsn_out can be changed by configuring UART_SW_RTS. • UART_RX_FLOW_EN is 1: If data in Rx_FIFO is greater than UART_RXFIFO_FULL_THRHD, the level of rtsn_out will be lowered. If the UART controller detects an edge on ctsn_in, it will generate interrupt UART_CTS_CHG_INT and will stop transmitting data, once the current data transmission is completed. The high level of the output signal dtrn_out signifies that the transmitter has finished data preparation. UART controller will generate interrupt UART_DSR_CHG_INT, after it detects an edge on the input signal dsrn_in. After the software detects the above-mentioned interrupt, the input signal level of dsrn_in can be figured out by reading UART_DSRN. The software then decides whether it is able to receive data at that time or not. Setting UART_LOOPBACK will enable the UART loopback detection function. In this mode, the output signal txd_out of UART is connected to its input signal rxd_in, rtsn_out is connected to ctsn_in, and dtrn_out is connected to dsrn_out. If the data transmitted corresponds to the data received, UART is able to transmit and receive data normally. 10.3.6.2 Software Flow Control Software can force the transmitter to stop transmitting data by setting UART_FORCE_XOFF, as well as force the transmitter to continue sending data by setting UART_FORCE_XON. Espressif Systems 231 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS UART can also control the software flow by transmitting special characters. Setting UART_SW_FLOW_CON_EN will enable the software flow control function. If the number of data bytes that UART has received exceeds that of the UART_XOFF threshold, the UART controller can send UART_XOFF_CHAR to instruct its counterpart to stop data transmission. When UART_SW_FLOW_CON_EN is 1, software can send flow control characters at any time. When UART_SEND_XOFF is set, the transmitter will insert a UART_XOFF_CHAR and send it after the current data transmission is completed. When UART_SEND_XON is set, the transmitter will insert a UART_XON_CHAR and send it after the current data transmission is completed. 10.3.7 UART DMA For information on the UART DMA, please refer to Chapter BUS DMA. 10.3.8 UART Interrupts • UART_AT_CMD_CHAR_DET_INT: Triggered when the receiver detects the configured at_cmd char. • UART_RS485_CLASH_INT: Triggered when a collision is detected between transmitter and receiver in RS-485 mode. • UART_RS485_FRM_ERR_INT: Triggered when a data frame error is detected in RS-485. • UART_RS485_PARITY_ERR_INT: Triggered when a parity error is detected in RS-485 mode. • UART_TX_DONE_INT: Triggered when the transmitter has sent out all FIFO data. • UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter’s idle state has been kept to a minimum after sending the last data. • UART_TX_BRK_DONE_INT: Triggered when the transmitter completes sending NULL characters, after all data in transmit-FIFO are sent. • UART_GLITCH_DET_INT: Triggered when the receiver detects a START bit. • UART_SW_XOFF_INT: Triggered, if the receiver gets an Xon char when uart_sw_flow_con_en is set to 1. • UART_SW_XON_INT: Triggered, if the receiver gets an Xoff char when uart_sw_flow_con_en is set to 1. • UART_RXFIFO_TOUT_INT: Triggered when the receiver takes more time than rx_tout_thrhd to receive a byte. • UART_BRK_DET_INT: Triggered when the receiver detects a 0 level after the STOP bit. • UART_CTS_CHG_INT: Triggered when the receiver detects an edge change of the CTSn signal. • UART_DSR_CHG_INT: Triggered when the receiver detects an edge change of the DSRn signal. • UART_RXFIFO_OVF_INT: Triggered when the receiver gets more data than the FIFO can store. • UART_FRM_ERR_INT: Triggered when the receiver detects a data frame error . • UART_PARITY_ERR_INT: Triggered when the receiver detects a parity error in the data. • UART_TXFIFO_EMPTY_INT: Triggered when the amount of data in the transmit-FIFO is less than what tx_mem_cnttxfifo_cnt specifies. • UART_RXFIFO_FULL_INT: Triggered when the receiver gets more data than what (rx_flow_thrhd_h3, rx_flow_thrhd) specifies. Espressif Systems 232 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 10.3.9 UCHI Interrupts • UHCI_SEND_A_REG_Q_INT: When using the always_send registers to send a series of short packets, this is triggered when DMA has sent a short packet. • UHCI_SEND_S_REG_Q_INT: When using the single_send registers to send a series of short packets, this is triggered when DMA has sent a short packet. • UHCI_OUT_TOTAL_EOF_INT: Triggered when all data have been sent. • UHCI_OUTLINK_EOF_ERR_INT: Triggered when there are some errors in EOF in the outlink descriptor. • UHCI_IN_DSCR_EMPTY_INT: Triggered when there are not enough inlinks for DMA. • UHCI_OUT_DSCR_ERR_INT: Triggered when there are some errors in the inlink descriptor. • UHCI_IN_DSCR_ERR_INT: Triggered when there are some errors in the outlink descriptor. • UHCI_OUT_EOF_INT: Triggered when the current descriptor’s EOF bit is 1. • UHCI_OUT_DONE_INT: Triggered when an outlink descriptor is completed. • UHCI_IN_ERR_EOF_INT: Triggered when there are some errors in EOF in the inlink descriptor. • UHCI_IN_SUC_EOF_INT: Triggered when a data packet has been received. • UHCI_IN_DONE_INT: Triggered when an inlink descriptor has been completed. • UHCI_TX_HUNG_INT: Triggered when DMA takes much time to read data from RAM. • UHCI_RX_HUNG_INT: Triggered when DMA takes much time to receive data . • UHCI_TX_START_INT: Triggered when DMA detects a separator char. • UHCI_RX_START_INT: Triggered when a separator char has been sent. 10.4 Register Summary Name Description UART0 UART1 UART2 Acc UART_CONF0_REG Configuration register 0 0x3FF40020 0x3FF50020 0x3FF6E020 R/W UART_CONF1_REG Configuration register 1 0x3FF40024 0x3FF50024 0x3FF6E024 R/W 0x3FF40014 0x3FF50014 0x3FF6E014 R/W 0x3FF40034 0x3FF50034 0x3FF6E034 R/W 0x3FF4003C 0x3FF5003C 0x3FF6E03C R/W 0x3FF40038 0x3FF50038 0x3FF6E038 R/W 0x3FF40040 0x3FF50040 0x3FF6E040 R/W 0x3FF40044 0x3FF50044 0x3FF6E044 R/W Configuration registers UART_CLKDIV_REG UART_FLOW_CONF_REG UART_SWFC_CONF_REG UART_SLEEP_CONF_REG UART_IDLE_CONF_REG UART_RS485_CONF_REG Clock divider configuration Software flow-control configuration Software flow-control character configuration Sleep-mode configuration Frame-end idle configuration RS485 mode configuration Status registers Espressif Systems 233 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS UART_STATUS_REG UART status register 0x3FF4001C 0x3FF5001C 0x3FF6E01C RO 0x3FF40018 0x3FF50018 0x3FF6E018 R/W 0x3FF40028 0x3FF50028 0x3FF6E028 RO 0x3FF4002C 0x3FF5002C 0x3FF6E02C RO 0x3FF40068 0x3FF50068 0x3FF6E068 RO 0x3FF4006C 0x3FF5006C 0x3FF6E06C RO 0x3FF40030 0x3FF50030 0x3FF6E030 RO 0x3FF40048 0x3FF50048 0x3FF6E048 R/W 0x3FF4004C 0x3FF5004C 0x3FF6E04C R/W 0x3FF40050 0x3FF50050 0x3FF6E050 R/W 0x3FF40054 0x3FF50054 0x3FF6E054 R/W 0x3FF40000 0x3FF50000 0x3FF6E000 RO 0x3FF40058 0x3FF50058 0x3FF6E058 R/W 0x3FF40064 0x3FF50064 0x3FF6E064 RO 0x3FF40004 0x3FF50004 0x3FF6E004 RO 0x3FF40008 0x3FF50008 0x3FF6E008 RO Autobaud registers UART_AUTOBAUD_REG Autobaud configura- tion register Autobaud UART_LOWPULSE_REG low minimum pulse duration register Autobaud UART_HIGHPULSE_REG high minimum pulse duration register UART_POSPULSE_REG UART_NEGPULSE_REG UART_RXD_CNT_REG Autobaud high pulse register Autobaud low pulse register Autobaud edge change count register AT escape seqence detection configuration UART_AT_CMD_PRECNT_REG UART_AT_CMD_POSTCNT_REG UART_AT_CMD_GAPTOUT_REG UART_AT_CMD_CHAR_REG Pre-sequence timing configuration Post-sequence timing configuration Timeout configuration AT escape sequence detection configuration FIFO configuration UART_FIFO_REG UART_MEM_CONF_REG UART_MEM_CNT_STATUS_REG FIFO data register UART threshold and allocation configuration Receive and transmit memory configuration Interrupt registers UART_INT_RAW_REG UART_INT_ST_REG Raw interrupt status Masked interrupt status UART_INT_ENA_REG Interrupt enable bits 0x3FF4000C 0x3FF5000C 0x3FF6E00C R/W UART_INT_CLR_REG Interrupt clear bits 0x3FF40010 0x3FF50010 0x3FF6E010 WO Name Description UDMA0 UDMA1 Acc 0x3FF54000 0x3FF4C000 R/W Configuration registers UHCI_CONF0_REG UHCI_CONF1_REG UHCI_ESCAPE_CONF_REG UHCI_HUNG_CONF_REG Espressif Systems UART and frame separation config UHCI config register 0x3FF5402C 0x3FF4C02C R/W Escape characters configuration Timeout configuration 234 0x3FF54064 0x3FF4C064 R/W 0x3FF54068 0x3FF4C068 R/W ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS UHCI_ESC_CONF0_REG UHCI_ESC_CONF1_REG UHCI_ESC_CONF2_REG UHCI_ESC_CONF3_REG Escape sequence configuration register 0 Escape sequence configuration register 1 Escape sequence configuration register 2 Escape sequence configuration register 3 0x3FF540B0 0x3FF4C0B0 R/W 0x3FF540B4 0x3FF4C0B4 R/W 0x3FF540B8 0x3FF4C0B8 R/W 0x3FF540BC 0x3FF4C0BC R/W DMA configuration UHCI_DMA_OUT_LINK_REG UHCI_DMA_IN_LINK_REG Link descriptor address and control Link descriptor address and control 0x3FF54024 0x3FF4C024 R/W 0x3FF54028 0x3FF4C028 R/W UHCI_DMA_OUT_PUSH_REG FIFO data push register 0x3FF54018 0x3FF4C018 R/W UHCI_DMA_IN_POP_REG FIFO data pop register 0x3FF54020 0x3FF4C020 RO DMA FIFO status 0x3FF54014 0x3FF4C014 RO 0x3FF54038 0x3FF4C038 RO 0x3FF54044 0x3FF4C044 RO DMA status UHCI_DMA_OUT_STATUS_REG UHCI_DMA_OUT_EOF_DES_ADDR_REG UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG UHCI_DMA_IN_DSCR_REG UHCI_DMA_IN_DSCR_BF0_REG UHCI_DMA_IN_DSCR_BF1_REG UHCI_DMA_OUT_DSCR_REG UHCI_DMA_OUT_DSCR_BF0_REG UHCI_DMA_OUT_DSCR_BF1_REG Out EOF link descriptor address on success Out EOF link descriptor address on error In EOF link descriptor address on success In EOF link descriptor address on error Current inlink descriptor, first word Current inlink descriptor, second word Current inlink descriptor, third word Current outlink descriptor, first word Current outlink descriptor, second word Current outlink descriptor, third word 0x3FF5403C 0x3FF4C03C RO 0x3FF54040 0x3FF4C040 RO 0x3FF5404C 0x3FF4C04C RO 0x3FF54050 0x3FF4C050 RO 0x3FF54054 0x3FF4C054 RO 0x3FF54058 0x3FF4C058 RO 0x3FF5405C 0x3FF4C05C RO 0x3FF54060 0x3FF4C060 RO Interrupt registers UHCI_INT_RAW_REG Raw interrupt status 0x3FF54004 0x3FF4C004 RO UHCI_INT_ST_REG Masked interrupt status 0x3FF54008 0x3FF4C008 RO UHCI_INT_ENA_REG Interrupt enable bits 0x3FF5400C 0x3FF4C00C R/W UHCI_INT_CLR_REG Interrupt clear bits 0x3FF54010 Espressif Systems 235 0x3FF4C010 WO ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 10.5 Registers (re UA R se rv ed ) T_ RX FI FO _R D_ B YT E Register 10.1: UART_FIFO_REG (0x0) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 Reset UART_RXFIFO_RD_BYTE This register stores one byte of data, as read from the Rx FIFO. (RO) Espressif Systems 236 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re s er ve d) UA R UA T_A RT T_ UA _R CM R S D UA T_R 485 _C R S _C HA UA T_R 485 LA R_ R S _F S DE UA T_T 485 RM H_I T_ R X _P _ NT INT UA T_T _DO AR ERR _R _R R X N IT _ AW AW UA T_T _BR E_I Y_E INT R X K NT R _R UA T_G _BR _ID _R R_I AW R L K LE AW NT_ UA T_S ITC _DO _DO RA R W H_ N N W UA T_S _X DE E_I E_ I O N N T R W F _ T T UA T_R _X F_I INT _R _R RT XF ON NT _R AW AW UA _B IF _IN _R AW R R O_ T AW UA T_C K_D TO _RA R T E UT W UA T_D S_C T_I _IN R S H NT T_ UA T_R R_C G_ _R RA R X H IN AW W UA T_F FIF G_ T_R R R O_ IN AW UA T_P M_ OV T_R R A E R F_ A UA T_T RIT R_ INT W RT XF Y_E INT _R _R IFO RR _R AW XF _E _I AW IF M NT O P _ _F TY RA UL _I W L_ NT IN _R T_ A RA W W Register 10.2: UART_INT_RAW_REG (0x4) 31 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UART_AT_CMD_CHAR_DET_INT_RAW The raw interrupt status bit for the UART_AT_CMD_CHAR_DET_INT interrupt. (RO) UART_RS485_CLASH_INT_RAW The raw interrupt status bit for the UART_RS485_CLASH_INT interrupt. (RO) UART_RS485_FRM_ERR_INT_RAW The raw interrupt status bit for the UART_RS485_FRM_ERR_INT interrupt. (RO) UART_RS485_PARITY_ERR_INT_RAW The raw interrupt status bit for the UART_RS485_PARITY_ERR_INT interrupt. (RO) UART_TX_DONE_INT_RAW The raw interrupt status bit for the UART_TX_DONE_INT interrupt. (RO) UART_TX_BRK_IDLE_DONE_INT_RAW The raw interrupt status bit for the UART_TX_BRK_IDLE_DONE_INT interrupt. (RO) UART_TX_BRK_DONE_INT_RAW The raw interrupt status bit for the UART_TX_BRK_DONE_INT interrupt. (RO) UART_GLITCH_DET_INT_RAW The raw interrupt status bit for the UART_GLITCH_DET_INT interrupt. (RO) UART_SW_XOFF_INT_RAW The raw interrupt status bit for the UART_SW_XOFF_INT interrupt. (RO) UART_SW_XON_INT_RAW The raw interrupt status bit for the UART_SW_XON_INT interrupt. (RO) UART_RXFIFO_TOUT_INT_RAW The raw interrupt status bit for the UART_RXFIFO_TOUT_INT interrupt. (RO) UART_BRK_DET_INT_RAW The raw interrupt status bit for the UART_BRK_DET_INT interrupt. (RO) UART_CTS_CHG_INT_RAW The raw interrupt status bit for the UART_CTS_CHG_INT interrupt. (RO) UART_DSR_CHG_INT_RAW The raw interrupt status bit for the UART_DSR_CHG_INT interrupt. (RO) UART_RXFIFO_OVF_INT_RAW The raw interrupt status bit for the UART_RXFIFO_OVF_INT interrupt. (RO) UART_FRM_ERR_INT_RAW The raw interrupt status bit for the UART_FRM_ERR_INT interrupt. (RO) UART_PARITY_ERR_INT_RAW The raw interrupt status bit for the UART_PARITY_ERR_INT interrupt. (RO) UART_TXFIFO_EMPTY_INT_RAW The raw interrupt status bit for the UART_TXFIFO_EMPTY_INT interrupt. (RO) UART_RXFIFO_FULL_INT_RAW The raw interrupt status bit for the UART_RXFIFO_FULL_INT interrupt. (RO) Espressif Systems 237 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re se rv ed ) UA R UA T_A RT T_ UA _R CM R S D UA T_R 485 _C R S _C HA UA T_R 485 LA R_ R S _F S DE UA T_T 485 RM H_I T_ R X _P _ NT INT UA T_T _DO AR ERR _ST _S T R X N IT _ UA T_T _BR E_I Y_E INT _ N R K X S R T UA T_G _BR _ID _S R_I T RT LI K_ LE_ T NT_ UA _S TC DO DO ST R W H_ N N UA T_S _X DE E_I E_ R W OF T_ NT INT UA T_R _X F_I INT _S _S R X ON NT _S T T UA T_B FIF _IN _S T R R O_ T T UA T_C K_D TO _ST R T E UT UA T_D S_C T_I _IN R S H NT T_ UA T_R R_C G_ _S ST R X H INT T UA T_F FIF G_ _S R R O_ IN T UA T_P M_ OV T_S R A E R F_ T UA T_T RIT R_ INT RT XF Y_E INT _S _R IFO RR _S T XF _E _I T IF M NT O P _ _F TY ST UL _I L_ NT IN _S T_ T ST Register 10.3: UART_INT_ST_REG (0x8) 31 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UART_AT_CMD_CHAR_DET_INT_ST The masked interrupt status bit for the UART_AT_CMD_CHAR_DET_INT interrupt. (RO) UART_RS485_CLASH_INT_ST The masked interrupt status bit for the UART_RS485_CLASH_INT interrupt. (RO) UART_RS485_FRM_ERR_INT_ST The masked interrupt status bit for the UART_RS485_FRM_ERR_INT interrupt. (RO) UART_RS485_PARITY_ERR_INT_ST The masked interrupt status bit for the UART_RS485_PARITY_ERR_INT interrupt. (RO) UART_TX_DONE_INT_ST The masked interrupt status bit for the UART_TX_DONE_INT interrupt. (RO) UART_TX_BRK_IDLE_DONE_INT_ST The masked interrupt status bit for the UART_TX_BRK_IDLE_DONE_INT interrupt. (RO) UART_TX_BRK_DONE_INT_ST The masked interrupt status bit for the UART_TX_BRK_DONE_INT interrupt. (RO) UART_GLITCH_DET_INT_ST The masked interrupt status bit for the UART_GLITCH_DET_INT interrupt. (RO) UART_SW_XOFF_INT_ST The masked interrupt status bit for the UART_SW_XOFF_INT interrupt. (RO) UART_SW_XON_INT_ST The masked interrupt status bit for the UART_SW_XON_INT interrupt. (RO) UART_RXFIFO_TOUT_INT_ST The masked interrupt status bit for the UART_RXFIFO_TOUT_INT interrupt. (RO) UART_BRK_DET_INT_ST The masked interrupt status bit for the UART_BRK_DET_INT interrupt. (RO) UART_CTS_CHG_INT_ST The masked interrupt status bit for the UART_CTS_CHG_INT interrupt. (RO) UART_DSR_CHG_INT_ST The masked interrupt status bit for the UART_DSR_CHG_INT interrupt. (RO) UART_RXFIFO_OVF_INT_ST The masked interrupt status bit for the UART_RXFIFO_OVF_INT interrupt. (RO) UART_FRM_ERR_INT_ST The masked interrupt status bit for the UART_FRM_ERR_INT interrupt. (RO) UART_PARITY_ERR_INT_ST The masked interrupt status bit for the UART_PARITY_ERR_INT interrupt. (RO) UART_TXFIFO_EMPTY_INT_ST The masked interrupt status bit for the UART_TXFIFO_EMPTY_INT interrupt. (RO) UART_RXFIFO_FULL_INT_ST The masked interrupt status bit for UART_RXFIFO_FULL_INT. (RO) Espressif Systems 238 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re s er ve d) UA R UA T_A RT T_ UA _R CM R S D UA T_R 485 _C R S _C HA UA T_R 485 LA R_ R S _F S DE UA T_T 485 RM H_I T_ R X _P _ NT INT UA T_T _DO AR ERR _EN _E R X N IT _ A NA UA T_T _BR E_I Y_E INT R X K NT R _E UA T_G _BR _ID _E R_I NA R L K LE NA NT_ UA T_S ITC _DO _DO EN R W H_ N N A UA T_S _X DE E_I E_ I O N N T R W F _ T T UA T_R _X F_I INT _E _E RT XF ON NT _E NA NA UA _B IF _IN _E NA R R O_ T NA UA T_C K_D TO _EN R T E UT A UA T_D S_C T_I _IN R S H NT T_ UA T_R R_C G_ _E EN R X H IN NA A UA T_F FIF G_ T_E R R O_ IN NA UA T_P M_ OV T_E R A E R F_ N UA T_T RIT R_ INT A RT XF Y_E INT _E _R IFO RR _E NA XF _E _I NA IF M NT O P _ _F TY EN UL _I A L_ NT IN _E T_ N EN A A Register 10.4: UART_INT_ENA_REG (0xC) 31 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UART_AT_CMD_CHAR_DET_INT_ENA The interrupt enable bit for the UART_AT_CMD_CHAR_DET_INT interrupt. (R/W) UART_RS485_CLASH_INT_ENA The interrupt enable bit for the UART_RS485_CLASH_INT interrupt. (R/W) UART_RS485_FRM_ERR_INT_ENA The interrupt enable bit for the UART_RS485_FRM_ERR_INT interrupt. (R/W) UART_RS485_PARITY_ERR_INT_ENA The interrupt enable bit for the UART_RS485_PARITY_ERR_INT interrupt. (R/W) UART_TX_DONE_INT_ENA The interrupt enable bit for the UART_TX_DONE_INT interrupt. (R/W) UART_TX_BRK_IDLE_DONE_INT_ENA The interrupt enable bit for the UART_TX_BRK_IDLE_DONE_INT interrupt. (R/W) UART_TX_BRK_DONE_INT_ENA The interrupt enable bit for the UART_TX_BRK_DONE_INT interrupt. (R/W) UART_GLITCH_DET_INT_ENA The interrupt enable bit for the UART_GLITCH_DET_INT interrupt. (R/W) UART_SW_XOFF_INT_ENA The interrupt enable bit for the UART_SW_XOFF_INT interrupt. (R/W) UART_SW_XON_INT_ENA The interrupt enable bit for the UART_SW_XON_INT interrupt. (R/W) UART_RXFIFO_TOUT_INT_ENA The interrupt enable bit for the UART_RXFIFO_TOUT_INT interrupt. (R/W) UART_BRK_DET_INT_ENA The interrupt enable bit for the UART_BRK_DET_INT interrupt. (R/W) UART_CTS_CHG_INT_ENA The interrupt enable bit for the UART_CTS_CHG_INT interrupt. (R/W) UART_DSR_CHG_INT_ENA The interrupt enable bit for the UART_DSR_CHG_INT interrupt. (R/W) UART_RXFIFO_OVF_INT_ENA The interrupt enable bit for the UART_RXFIFO_OVF_INT interrupt. (R/W) UART_FRM_ERR_INT_ENA The interrupt enable bit for the UART_FRM_ERR_INT interrupt. (R/W) UART_PARITY_ERR_INT_ENA The interrupt enable bit for the UART_PARITY_ERR_INT interrupt. (R/W) UART_TXFIFO_EMPTY_INT_ENA The interrupt enable bit for the UART_TXFIFO_EMPTY_INT interrupt. (R/W) UART_RXFIFO_FULL_INT_ENA The interrupt enable bit for the UART_RXFIFO_FULL_INT interrupt. (R/W) Espressif Systems 239 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re s er ve d) UA R UA T_A RT T_ UA _R CM R S D UA T_R 485 _C R S _C HA UA T_R 485 LA R_ R S _ F S DE UA T_T 485 RM H_I T_ R X _P _ NT INT UA T_T _DO AR ERR _C _C R X N IT _ LR LR UA T_T _BR E_I Y_E INT R X K NT R _C UA T_G _BR _ID _C R_I LR R L K LE LR NT_ UA T_S ITC _DO _DO CL R W H_ N N R UA T_S _X DE E_I E_ I O N N T R W F _ T T UA T_R _X F_I INT _C _C RT XF ON NT _C LR LR UA _B IF _IN _C LR R R O _ T LR UA T_C K_D TO _CL R T E UT R UA T_D S_C T_I _IN R S H NT T_ UA T_R R_C G_ _C CL R X H INT LR R UA T_F FIF G_ _C R R O_ IN LR UA T_P M_ OV T_C R A ER F_ LR UA T_T RIT R_ INT RT XF Y_E INT _C _R IFO RR _C LR XF _E _I LR IF M NT O P _ _F TY C UL _I LR L_ NT IN _C T_ LR CL R Register 10.5: UART_INT_CLR_REG (0x10) 31 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UART_AT_CMD_CHAR_DET_INT_CLR Set this bit to clear the UART_AT_CMD_CHAR_DET_INT interrupt. (WO) UART_RS485_CLASH_INT_CLR Set this bit to clear the UART_RS485_CLASH_INT interrupt. (WO) UART_RS485_FRM_ERR_INT_CLR Set this bit to clear the UART_RS485_FRM_ERR_INT interrupt. (WO) UART_RS485_PARITY_ERR_INT_CLR Set this bit to clear the UART_RS485_PARITY_ERR_INT interrupt. (WO) UART_TX_DONE_INT_CLR Set this bit to clear the UART_TX_DONE_INT interrupt. (WO) UART_TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear the UART_TX_BRK_IDLE_DONE_INT interrupt. (WO) UART_TX_BRK_DONE_INT_CLR Set this bit to clear the UART_TX_BRK_DONE_INT interrupt. (WO) UART_GLITCH_DET_INT_CLR Set this bit to clear the UART_GLITCH_DET_INT interrupt. (WO) UART_SW_XOFF_INT_CLR Set this bit to clear the UART_SW_XOFF_INT interrupt. (WO) UART_SW_XON_INT_CLR Set this bit to clear the UART_SW_XON_INT interrupt. (WO) UART_RXFIFO_TOUT_INT_CLR Set this bit to clear the UART_RXFIFO_TOUT_INT interrupt. (WO) UART_BRK_DET_INT_CLR Set this bit to clear the UART_BRK_DET_INT interrupt. (WO) UART_CTS_CHG_INT_CLR Set this bit to clear the UART_CTS_CHG_INT interrupt. (WO) UART_DSR_CHG_INT_CLR Set this bit to clear the UART_DSR_CHG_INT interrupt. (WO) UART_RXFIFO_OVF_INT_CLR Set this bit to clear the UART_RXFIFO_OVF_INT interrupt. (WO) UART_FRM_ERR_INT_CLR Set this bit to clear the UART_FRM_ERR_INT interrupt. (WO) UART_PARITY_ERR_INT_CLR Set this bit to clear the UART_PARITY_ERR_INT interrupt. (WO) UART_TXFIFO_EMPTY_INT_CLR Set this bit to clear the UART_TXFIFO_EMPTY_INT interrupt. (WO) UART_RXFIFO_FULL_INT_CLR Set this bit to clear the UART_RXFIFO_FULL_INT interrupt. (WO) Espressif Systems 240 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS LK D ) 0 0 0 0 0 UA UA 24 0 RT RT _C ed se rv (re 31 0 _C LK DI V IV _ FR AG Register 10.6: UART_CLKDIV_REG (0x14) 23 0 20 19 0 0x00 0x0002B6 Reset UART_CLKDIV_FRAG The decimal part of the frequency divider factor. (R/W) UART_CLKDIV The integral part of the frequency divider factor. (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 8 0x010 UT _A UA RT (re se rv _G RT UA 16 0 ed ) LI T ) er ve d (re s 31 0 O CH BA UD _F ILT _E N Register 10.7: UART_AUTOBAUD_REG (0x18) 7 0 0 0 0 0 0 1 0 0 0 Reset UART_GLITCH_FILT When the input pulse width is lower than this value, the pulse is ignored. This register is used in the autobauding process. (R/W) UART_AUTOBAUD_EN This is the enable bit for autobaud. (R/W) Espressif Systems 241 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 30 29 28 27 0x000 0 31 0 0 0 0 23 0 0 0 0 0 0 0 0 15 14 13 12 11 0 0 0 0 0 0 UA R RT _S T_ RX F IF O T_ UR X_ O _C NT UT 16 UA RT UA 24 0 UA R UA T_R RT XD UA _C R T (re T_D SN se S rv RN ed ) IF O _T XF T_ UT _S RT UA UA R UA T_T R X UA T_R D R T (re T_D SN se T rv RN ed ) X_ _C N T O UT Register 10.8: UART_STATUS_REG (0x1C) 8 0 0 7 0 0 0 0 0 0 0 0 0 0 Reset UART_TXD This bit represents the level of the internal UART RxD signal. (RO) UART_RTSN This bit corresponds to the level of the internal UART CTS signal. (RO) UART_DTRN This bit corresponds to the level of the internal UAR DSR signal. (RO) UART_ST_UTX_OUT This register stores the state of the transmitter’s finite state machine. 0: TX_IDLE; 1: TX_STRT; 2: TX_DAT0; 3: TX_DAT1; 4: TX_DAT2; 5: TX_DAT3; 6: TX_DAT4; 7: TX_DAT5; 8: TX_DAT6; 9: TX_DAT7; 10: TX_PRTY; 11: TX_STP1; 12: TX_STP2; 13: TX_DL0; 14: TX_DL1. (RO) UART_TXFIFO_CNT (tx_mem_cnt, txfifo_cnt) stores the number of bytes of valid data in transmitFIFO. tx_mem_cnt stores the three most significant bits, txfifo_cnt stores the eight least significant bits. (RO) UART_RXD This bit corresponds to the level of the internal UART RxD signal. (RO) UART_CTSN This bit corresponds to the level of the internal UART CTS signal. (RO) UART_DSRN This bit corresponds to the level of the internal UAR DSR signal. (RO) UART_ST_URX_OUT This register stores the value of the receiver’s finite state machine. 0: RX_IDLE; 1: RX_STRT; 2: RX_DAT0; 3: RX_DAT1; 4: RX_DAT2; 5: RX_DAT3; 6: RX_DAT4; 7: RX_DAT5; 8: RX_DAT6; 9: RX_DAT7; 10: RX_PRTY; 11: RX_STP1; 12:RX_STP2; 13: RX_DL1. (RO) UART_RXFIFO_CNT (rx_mem_cnt, rxfifo_cnt) stores the number of bytes of valid data in the receiveFIFO. rx_mem_cnt register stores the three most significant bits, rxfifo_cnt stores the eight least significant bits. (RO) Espressif Systems 242 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 31 0 0 0 (re UA (re s er ve d) RT _T IC K_ se RE rv ed F_ UA ) AL RT W UA _D AY RT TR S_ UA _R _I O N R T TS NV UA _T _I R X NV UA T_D D_I R S NV UA T_C R_I R T NV UA T_R S_I R X NV UA T_T D_I R X NV UA T_R FIFO R X _ UA T_I FIF RS R RD O_ T UA T_T A_ RS R X EN T UA T_L _FL R O OW UA T_I OP _E R RD BA N UA T_I A_ CK R RD RX UA T_I A_ _IN R RD TX V UA T_I A_ _IN R RD W V UA T_I A_ CTL R RD TX UA T_T A_ _EN R X DP UA T_S D_B LX RT W RK _ _D UA SW TR RT _R _S TS TO UA P_ BI RT T_ _B NU UA IT _ M RT NU UA _P M RT AR _P ITY AR _ IT EN Y Register 10.9: UART_CONF0_REG (0x20) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 1 2 3 1 0 0 0 Reset UART_TICK_REF_ALWAYS_ON This register is used to select the clock; 1: APB clock; 0: REF_TICK. (R/W) UART_DTR_INV Set this bit to invert the level of the UART DTR signal. (R/W) UART_RTS_INV Set this bit to invert the level of the UART RTS signal. (R/W) UART_TXD_INV Set this bit to invert the level of the UART TxD signal. (R/W) UART_DSR_INV Set this bit to invert the level of the UART DSR signal. (R/W) UART_CTS_INV Set this bit to invert the level of the UART CTS signal. (R/W) UART_RXD_INV Set this bit to invert the level of the UART Rxd signal. (R/W) UART_TXFIFO_RST Set this bit to reset the UART transmit-FIFO. (R/W) UART_RXFIFO_RST Set this bit to reset the UART receive-FIFO. (R/W) UART_IRDA_EN Set this bit to enable the IrDA protocol. (R/W) UART_TX_FLOW_EN Set this bit to enable the flow control function for the transmitter. (R/W) UART_LOOPBACK Set this bit to enable the UART loopback test mode. (R/W) UART_IRDA_RX_INV Set this bit to invert the level of the IrDA receiver. (R/W) UART_IRDA_TX_INV Set this bit to invert the level of the IrDA transmitter. (R/W) UART_IRDA_WCTL 1: The IrDA transmitter’s 11th bit is the same as its 10th bit; 0: set IrDA transmitter’s 11th bit to 0. (R/W) UART_IRDA_TX_EN This is the start enable bit of the IrDA transmitter. (R/W) UART_IRDA_DPLX Set this bit to enable the IrDA loopback mode. (R/W) UART_TXD_BRK Set this bit to enable the transmitter to send NULL, when the process of sending data is completed. (R/W) UART_SW_DTR This register is used to configure the software DTR signal used in software flow control. (R/W) UART_SW_RTS This register is used to configure the software RTS signal used in software flow control. (R/W) UART_STOP_BIT_NUM This register is used to set the length of the stop bit; 1: 1 bit, 2: 1.5 bits. (R/W) UART_BIT_NUM This register is used to set the length of data; 0: 5 bits, 1: 6 bits, 2: 7 bits, 3: 8 bits. (R/W) UART_PARITY_EN Set this bit to enable the UART parity check. (R/W) UART_PARITY This register is used to configure the parity check mode; 0: even, 1: odd. (R/W) Espressif Systems 243 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 31 30 0 0 0 0 0 0 0 24 23 0 0 15 UL L O _F M _E 0 RX FI F 14 8 0x60 7 UA R T_ ) (re UA R se rv T_ ed TX d) ve er (re s 16 0x00 FI FO _F LO RX T_ UA R 22 _T HR HD Y_ TH RH D PT W _T HR HD _E N O W X_ FL _R RT UA UA UA RT _R RT _R X_ X_ TO TO UT UT _E N _T HR HD Register 10.10: UART_CONF1_REG (0x24) 6 0 0 0x60 Reset UART_RX_TOUT_EN This is the enable bit for the UART receive-timeout function. (R/W) UART_RX_TOUT_THRHD This register is used to configure the UART receiver’s timeout value when receiving a byte. (R/W) UART_RX_FLOW_EN This is the flow enable bit of the UART receiver; 1: choose software flow control by configuring the sw_rts signal; 0: disable software flow control. (R/W) UART_RX_FLOW_THRHD When the receiver gets more data than its threshold value, the receiver produces a signal that tells the transmitter to stop transferring data. The threshold value is (rx_flow_thrhd_h3, rx_flow_thrhd). (R/W) UART_TXFIFO_EMPTY_THRHD When the data amount in transmit-FIFO is less than its threshold value, it will produce a TXFIFO_EMPTY_INT_RAW interrupt. The threshold value is (tx_mem_empty_thrhd, txfifo_empty_thrhd). (R/W) UART_RXFIFO_FULL_THRHD When the receiver gets more data than its threshold value, the receiver will produce an RXFIFO_FULL_INT_RAW interrupt. The threshold value is (rx_flow_thrhd_h3, rxfifo_full_thrhd). (R/W) UA (re se RT rv e _L d) O W PU LS E_ M IN _C NT Register 10.11: UART_LOWPULSE_REG (0x28) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0x0FFFFF Reset UART_LOWPULSE_MIN_CNT This register stores the value of the minimum duration of the low-level pulse. It is used in the baud rate detection process. (RO) Espressif Systems 244 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS UA (re s er RT ve d) _H IG HP UL S E_ M IN _C NT Register 10.12: UART_HIGHPULSE_REG (0x2C) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0x0FFFFF Reset UART_HIGHPULSE_MIN_CNT This register stores the value of the minimum duration of the high level pulse. It is used in baud rate detection process. (RO) (re UA se r RT ve _R d) XD _E DG E_ CN T Register 10.13: UART_RXD_CNT_REG (0x30) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0x000 Reset UART_RXD_EDGE_CNT This register stores the count of the RxD edge change. It is used in the baud rate detection process. (RO) UA (re se rv ed ) R UA T_S R T EN UA _S D R E _X UA T_F ND OF R O _X F UA T_F RC ON R O E_ UA T_X RC XO RT ON E_X FF _S O ON W FF _F _D LO EL W _C O N_ EN Register 10.14: UART_FLOW_CONF_REG (0x34) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reset UART_SEND_XOFF Hardware auto-clear; set to 1 to send Xoff char. (R/W) UART_SEND_XON Hardware auto-clear; set to 1 to send Xon char. (R/W) UART_FORCE_XOFF Set this bit to set the CTSn and enable the transmitter to continue sending data. (R/W) UART_FORCE_XON Set this bit to clear the CTSn and stop the transmitter from sending data. (R/W) UART_XONOFF_DEL Set this bit to remove the flow-control char from the received data. (R/W) UART_SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. (R/W) Espressif Systems 245 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re s UA R er T_ ve d) AC TI VE _T HR ES HO LD Register 10.15: UART_SLEEP_CONF_REG (0x38) 31 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0x0F0 Reset UART_ACTIVE_THRESHOLD When the input RxD edge changes more times than what this register indicates, the system emerges from Light-sleep mode and becomes active. (R/W) 23 SH SH RE RE N_ TH UA UA RT RT _X O _X O FF _ CH N_ O RT _X UA 24 0x013 TH AR R HA _C FF O _X RT UA 31 O O LD LD Register 10.16: UART_SWFC_CONF_REG (0x3C) 16 15 0x011 8 7 0x0E0 0 0x000 Reset UART_XOFF_CHAR This register stores the Xoff flow control char. (R/W) UART_XON_CHAR This register stores the Xon flow control char. (R/W) UART_XOFF_THRESHOLD When the data amount in receive-FIFO is less than what this register indicates, it will send an Xon char, with uart_sw_flow_con_en set to 1. (R/W) UART_XON_THRESHOLD When the data amount in receive-FIFO is more than what this register indicates, it will send an Xoff char, with uart_sw_flow_con_en set to 1. (R/W) Espressif Systems 246 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 0 0 0 27 20 0 RX _I DL E DL E T_ TX _I T_ UA R UA R RT UA 28 _T _N UM M NU _B RK _ _T X d) ve er (re s 31 HR HD Register 10.17: UART_IDLE_CONF_REG (0x40) 19 10 0x00A 9 0 0x100 0x100 Reset UART_TX_BRK_NUM This register is used to configure the number of zeros (0) sent, after the process of sending data is completed. It is active when txd_brk is set to 1. (R/W) UART_TX_IDLE_NUM This register is used to configure the duration between transfers. (R/W) UART_RX_IDLE_THRHD When the receiver takes more time to receive Byte data than what this register indicates, it will produce a frame-end signal. (R/W) S4 RT _R ve d) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UA UA (re se r 31 0 85 _T X_ RT DL UA _R Y_ RT S4 NU UA _R 85 M RT S4 _R UA _R 85 X_ R S R DL UA T_D 485 XBY Y_ R L TX _ NU UA T_D 1_E _R TX_ M RT L0 N X_ EN EN _R _E S4 N 85 _E N Register 10.18: UART_RS485_CONF_REG (0x44) 9 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reset UART_RS485_TX_DLY_NUM This register is used to delay the transmitter’s internal data signal. (R/W) UART_RS485_RX_DLY_NUM This register is used to delay the receiver’s internal data signal. (R/W) UART_RS485RXBY_TX_EN 1: enable the RS-485 transmitter to send data, when the RS-485 receiver line is busy; 0: the RS-485 transmitter should not send data, when its receiver is busy. (R/W) UART_RS485TX_RX_EN Set this bit to enable the transmitter’s output signal loop back to the receiver’s input signal. (R/W) UART_DL1_EN Set this bit to delay the STOP bit by 1 bit. (R/W) UART_DL0_EN Set this bit to delay the STOP bit by 1 bit. (R/W) UART_RS485_EN Set this bit to choose the RS-485 mode. (R/W) Espressif Systems 247 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS UA (re s er RT ve d) _P RE _I DL E_ NU M Register 10.19: UART_AT_CMD_PRECNT_REG (0x48) 31 0 24 0 0 0 0 0 0 23 0 0 0x0186A00 Reset UART_PRE_IDLE_NUM This register is used to configure the idle-time duration before the first at_cmd is received by the receiver. When the duration is less than what this register indicates, it will not take the next data received as an at_cmd char. (R/W) UA (re se r RT _P ve d) O ST _I D LE _N U M Register 10.20: UART_AT_CMD_POSTCNT_REG (0x4c) 31 0 24 0 0 0 0 0 0 23 0 0 0x0186A00 Reset UART_POST_IDLE_NUM This register is used to configure the duration between the last at_cmd and the next data. When the duration is less than what this register indicates, it will not take the previous data as an at_cmd char. (R/W) (re UA se RT _R rv ed ) X_ G AP _T O UT Register 10.21: UART_AT_CMD_GAPTOUT_REG (0x50) 31 0 24 0 0 0 0 0 0 23 0 0 0x0001E00 Reset UART_RX_GAP_TOUT This register is used to configure the duration between the at_cmd chars. When the duration is less than what this register indicates, it will not take the data as continuous at_cmd chars. (R/W) Espressif Systems 248 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 31 0 16 0 0 0 0 0 0 0 CM T_ AT _ UA R (re UA se RT rv ed ) _C HA R_ NU M D_ CH AR Register 10.22: UART_AT_CMD_CHAR_REG (0x54) 0 0 0 0 0 0 0 15 8 0 7 0 0x003 0x02B Reset UART_CHAR_NUM This register is used to configure the number of continuous at_cmd chars received by the receiver. (R/W) UART_AT_CMD_CHAR This register is used to configure the content of an at_cmd char. (R/W) 31 0 30 28 27 0x0 25 0x0 22 18 0x0 H3 RH 0x0 14 0 0 0 10 6 0x01 3 0x01 UA RT _M d) rv e (re se UA 7 EM _P SI ZE RT RT UA 11 0 _R X_ _T ed ) se rv (re 15 X_ SI ZE W LO _F _R X RT UA 17 D _T H RH _T O _R X 20 D_ H3 D_ _H LD UT _T H SH RE RT UA 21 0x0 O HO ES N_ TH HR _X O UA 23 0x0 RT RT UA 24 2 LD _H 2 RH TH FF _T _X O X_ _R RT UA RT UA (re se rv ed _T X ) _M EM M EM _E M PT _F UL L_ Y_ TH R D HD Register 10.23: UART_MEM_CONF_REG (0x58) 2 1 0 0 0 0 Reset UART_TX_MEM_EMPTY_THRHD Refer to the description of txfifo_empty_thrhd. (R/W) UART_RX_MEM_FULL_THRHD Refer to the description of rxfifo_full_thrhd. (R/W) UART_XOFF_THRESHOLD_H2 Refer to the description of uart_xoff_threshold. (R/W) UART_XON_THRESHOLD_H2 Refer to the description of uart_xon_threshold. (R/W) UART_RX_TOUT_THRHD_H3 Refer to the description of rx_tout_thrhd. (R/W) UART_RX_FLOW_THRHD_H3 Refer to the description of rx_flow_thrhd. (R/W) UART_TX_SIZE This register is used to configure the amount of memory allocated to the transmitFIFO. The default number is 128 bytes. (R/W) UART_RX_SIZE This register is used to configure the amount of memory allocated to the receiveFIFO. The default number is 128 bytes. (R/W) UART_MEM_PD Set this bit to power down the memory. When the reg_mem_pd register is set to 1 for all UART controllers, Memory will enter the low-power mode. (R/W) Espressif Systems 249 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 31 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 3 0 0 0 EM RT _R X_ M UA (re s UA R er v T_ TX ed ) _M EM _C NT _C NT Register 10.24: UART_MEM_CNT_STATUS_REG (0x64) 2 0 0 0 0 0 Reset UART_TX_MEM_CNT Refer to the description of txfifo_cnt. (RO) UART_RX_MEM_CNT Refer to the description of rxfifo_cnt. (RO) UA (re se r RT ve _P d) O SE DG E_ M IN _C N T Register 10.25: UART_POSPULSE_REG (0x68) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0x0FFFFF Reset UART_POSEDGE_MIN_CNT This register stores the count of RxD positive edges. It is used in the autobaud detection process. (RO) (re UA RT se rv e _N d) EG ED G E_ M IN _C N T Register 10.26: UART_NEGPULSE_REG (0x6c) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0x0FFFFF Reset UART_NEGEDGE_MIN_CNT This register stores the count of RxD negative edges. It is used in the autobaud detection process. (RO) Espressif Systems 250 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 31 0 0 0 0 0 0 0 0 0 22 21 20 19 18 17 16 15 0 1 1 0 1 1 1 0 0 0 12 11 10 9 17 0 0 0 0 0 (re se rv ed ) UH C UH I_U C AR UH I_U T2 CI AR _C _U T1 E AR _C T0 E _C E UH (re s er ve d) C UH I_E C NC UH I_L OD C EN E UH I_U _E _C C AR OF RC UH I_C T_ _E _E C R ID N N UH I_H C_R LE_ CI EA EC EO _S D_ _E F_ EP EN N EN ER _E (re N se rv ed ) Register 10.27: UHCI_CONF0_REG (0x0) 9 0 0 0 0 0 0 0 0 Reset UHCI_ENCODE_CRC_EN Reserved. Please initialize it to 0. (R/W) UHCI_LEN_EOF_EN Reserved. Please initialize it to 0. (R/W) UHCI_UART_IDLE_EOF_EN Reserved. Please initialize it to 0. (R/W) UHCI_CRC_REC_EN Reserved. Please initialize it to 0. (R/W) UHCI_HEAD_EN Reserved. Please initialize it to 0. (R/W) UHCI_SEPER_EN Set this bit to use a special char and separate the data frame. (R/W) UHCI_UART2_CE Set this bit to use UART2 and transmit or receive data. (R/W) UHCI_UART1_CE Set this bit to use UART1 and transmit or receive data. (R/W) UHCI_UART0_CE Set this bit to use UART and transmit or receive data. (R/W) Espressif Systems 251 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re s er ve d) UH C UH I_O CI UT UH _O _T C U O UH I_IN TLIN TAL C _ K _E UH I_O DSC _E OF C U R OF _IN UH I_IN T_D _E _ER T_ C _ S MP R RA UH I_O DSC CR_ TY _IN W C U R E _IN T_ UH I_O T_E _E RR_ T_ RA C U O RR IN RA W UH I_IN T_D F_IN _IN T_ W C _ O T T_ RA UH I_IN ERR NE _RA RA W C _ _ _IN W W UH I_IN SUC EO T_ C _ _ F_ RA UH I_T DO EO INT W C X_ NE F_ _R UH I_R HU _IN INT AW C X_ NG T_ _R UH I_T HU _I RA AW CI X_S NG NT_ W _R T _ R X_ AR INT AW ST T_ _R AR IN AW T_ T_R IN A T_ W RA W Register 10.28: UHCI_INT_RAW_REG (0x4) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UHCI_OUT_TOTAL_EOF_INT_RAW The 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset raw interrupt status bit for the for the for the UHCI_OUT_TOTAL_EOF_INT interrupt. (RO) UHCI_OUTLINK_EOF_ERR_INT_RAW The raw interrupt status bit UHCI_OUTLINK_EOF_ERR_INT interrupt. (RO) UHCI_IN_DSCR_EMPTY_INT_RAW The raw interrupt status bit UHCI_IN_DSCR_EMPTY_INT interrupt. (RO) UHCI_OUT_DSCR_ERR_INT_RAW The raw interrupt status bit for the UHCI_OUT_DSCR_ERR_INT interrupt. (RO) UHCI_IN_DSCR_ERR_INT_RAW The raw interrupt status bit for the UHCI_IN_DSCR_ERR_INT interrupt. (RO) UHCI_OUT_EOF_INT_RAW The raw interrupt status bit for the UHCI_OUT_EOF_INT interrupt. (RO) UHCI_OUT_DONE_INT_RAW The raw interrupt status bit for the UHCI_OUT_DONE_INT interrupt. (RO) UHCI_IN_ERR_EOF_INT_RAW The raw interrupt status bit for the UHCI_IN_ERR_EOF_INT interrupt. (RO) UHCI_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the UHCI_IN_SUC_EOF_INT interrupt. (RO) UHCI_IN_DONE_INT_RAW The raw interrupt status bit for the UHCI_IN_DONE_INT interrupt. (RO) UHCI_TX_HUNG_INT_RAW The raw interrupt status bit for the UHCI_TX_HUNG_INT interrupt. (RO) UHCI_RX_HUNG_INT_RAW The raw interrupt status bit for the UHCI_RX_HUNG_INT interrupt. (RO) UHCI_TX_START_INT_RAW The raw interrupt status bit for the UHCI_TX_START_INT interrupt. (RO) UHCI_RX_START_INT_RAW The raw interrupt status bit for the UHCI_RX_START_INT interrupt. (RO) Espressif Systems 252 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re se r ve d) UH C UH I_D C M UH I_S A_I C EN NF UH I_S D_ IFO C EN A_ _F UH I_O D_ RE UL C U S_ G L_ UH I_O T_T RE _Q_ WM C U O G IN _ UH I_IN TLIN TAL _Q_ T_S INT C _ K _E IN T _ST UH I_O DSC _E OF T_S C U R OF _IN T UH I_IN T_D _E _ER T_ C _ S MP R ST UH I_O DSC CR_ TY _IN C U R E _IN T_ UH I_O T_E _E RR_ T_ ST C U O RR IN ST UH I_IN T_D F_IN _IN T_ C _ O T T_ ST UH I_IN ERR NE _ST ST C _ _ _IN UH I_IN SUC EO T_ C _ _ F_ ST UH I_T DO EO INT C X_ NE F_ _S UH I_R HU _IN INT T C X_ NG T_ _S UH I_T HU _I ST T CI X_S NG NT_ _R T _ S X_ AR INT T ST T_ _S AR IN T T_ T_S IN T T_ ST Register 10.29: UHCI_INT_ST_REG (0x8) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_SEND_A_REG_Q_INT_ST The masked interrupt status bit for the UHCI_SEND_A_REG_Q_INT interrupt. (RO) UHCI_SEND_S_REG_Q_INT_ST The masked interrupt status bit for the UHCI_SEND_S_REG_Q_INT interrupt. (RO) UHCI_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the UHCI_OUT_TOTAL_EOF_INT interrupt. (RO) UHCI_OUTLINK_EOF_ERR_INT_ST The masked interrupt status bit for the UHCI_OUTLINK_EOF_ERR_INT interrupt. (RO) UHCI_IN_DSCR_EMPTY_INT_ST The masked interrupt status bit for the UHCI_IN_DSCR_EMPTY_INT interrupt. (RO) UHCI_OUT_DSCR_ERR_INT_ST The masked interrupt status bit for the UHCI_OUT_DSCR_ERR_INT interrupt. (RO) UHCI_IN_DSCR_ERR_INT_ST The masked interrupt status bit for the UHCI_IN_DSCR_ERR_INT interrupt. (RO) UHCI_OUT_EOF_INT_ST The masked interrupt status bit for the UHCI_OUT_EOF_INT interrupt. (RO) UHCI_OUT_DONE_INT_ST The masked interrupt status bit for the UHCI_OUT_DONE_INT interrupt. (RO) UHCI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the UHCI_IN_ERR_EOF_INT interrupt. (RO) UHCI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the UHCI_IN_SUC_EOF_INT interrupt. (RO) UHCI_IN_DONE_INT_ST The masked interrupt status bit for the UHCI_IN_DONE_INT interrupt. (RO) UHCI_TX_HUNG_INT_ST The masked interrupt status bit for the UHCI_TX_HUNG_INT interrupt. (RO) UHCI_RX_HUNG_INT_ST The masked interrupt status bit for the UHCI_RX_HUNG_INT interrupt. (RO) UHCI_TX_START_INT_ST The masked interrupt status bit for the UHCI_TX_START_INT interrupt. (RO) UHCI_RX_START_INT_ST The masked interrupt status bit for the UHCI_RX_START_INT interrupt. (RO) Espressif Systems 253 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re se r ve d) UH C UH I_D C M UH I_S A_I C EN NF UH I_S D_ IFO C EN A_ _F UH I_O D_ RE UL C U S_ G L_ UH I_O T_T RE _Q_ WM C U O G IN _ UH I_IN TLIN TAL _Q_ T_E INT C _ K _E IN N _E UH I_O DSC _E OF T_E A NA C U R OF _IN N UH I_IN T_D _E _ER T_ A C _ S MP R EN UH I_O DSC CR_ TY _IN A C U R E _IN T_ UH I_O T_E _E RR_ T_ EN C U O RR IN EN A UH I_IN T_D F_IN _IN T_ A C _ O T T_ EN UH I_IN ERR NE _EN EN A C _ _ _IN A A UH I_IN SUC EO T_ C _ _ F_ EN UH I_T DO EO INT A C X_ NE F_ _E UH I_R HU _IN INT NA C X_ NG T_ _E UH I_T HU _I EN NA CI X_S NG NT_ A _R T _ E X_ AR INT NA ST T_ _E AR IN NA T_ T_E IN N T_ A EN A Register 10.30: UHCI_INT_ENA_REG (0xC) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_SEND_A_REG_Q_INT_ENA The interrupt enable bit for the UHCI_SEND_A_REG_Q_INT interrupt. (R/W) UHCI_SEND_S_REG_Q_INT_ENA The interrupt enable bit for the UHCI_SEND_S_REG_Q_INT interrupt. (R/W) UHCI_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the UHCI_OUT_TOTAL_EOF_INT interrupt. (R/W) UHCI_OUTLINK_EOF_ERR_INT_ENA The interrupt enable bit for the UHCI_OUTLINK_EOF_ERR_INT interrupt. (R/W) UHCI_IN_DSCR_EMPTY_INT_ENA The interrupt enable bit for the UHCI_IN_DSCR_EMPTY_INT interrupt. (R/W) UHCI_OUT_DSCR_ERR_INT_ENA The interrupt enable bit for the UHCI_OUT_DSCR_ERR_INT interrupt. (R/W) UHCI_IN_DSCR_ERR_INT_ENA The interrupt enable bit for the UHCI_IN_DSCR_ERR_INT interrupt. (R/W) UHCI_OUT_EOF_INT_ENA The interrupt enable bit for the UHCI_OUT_EOF_INT interrupt. (R/W) UHCI_OUT_DONE_INT_ENA The interrupt enable bit for the UHCI_OUT_DONE_INT interrupt. (R/W) UHCI_IN_ERR_EOF_INT_ENA The interrupt enable bit for the UHCI_IN_ERR_EOF_INT interrupt. (R/W) UHCI_IN_SUC_EOF_INT_ENA The interrupt enable bit for the UHCI_IN_SUC_EOF_INT interrupt. (R/W) UHCI_IN_DONE_INT_ENA The interrupt enable bit for the UHCI_IN_DONE_INT interrupt. (R/W) UHCI_TX_HUNG_INT_ENA The interrupt enable bit for the UHCI_TX_HUNG_INT interrupt. (R/W) UHCI_RX_HUNG_INT_ENA The interrupt enable bit for the UHCI_RX_HUNG_INT interrupt. (R/W) UHCI_TX_START_INT_ENA The interrupt enable bit for the UHCI_TX_START_INT interrupt. (R/W) UHCI_RX_START_INT_ENA The interrupt enable bit for the UHCI_RX_START_INT interrupt. (R/W) Espressif Systems 254 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re se rv ed ) UH C UH I_D C M UH I_S A_I C EN NF UH I_S D_ IFO C EN A_ _F UH I_O D_ RE UL C U S_ G L_ UH I_O T_T RE _Q_ WM C U O G IN _ UH I_IN TLIN TAL _Q_ T_C INT C _ K _E IN L _C UH I_O DSC _E OF T_C R LR C U R OF _IN L UH I_IN T_D _E _ER T_ R C _ S MP R CL UH I_O DSC CR_ TY _IN R C U R E _IN T_ UH I_O T_E _E RR_ T_ CL C U O RR IN CL R UH I_IN T_D F_IN _IN T_ R C _ O T T_ CL UH I_IN ERR NE _CL CL R C _ _ _IN R R UH I_IN SUC EO T_ C _ _ F_ CL UH I_T DO EO INT R C X_ NE F_ _C UH I_R HU _IN INT LR C X_ NG T_ _C UH I_T HU _I CL LR CI X_S NG NT_ R _R T _ C X_ AR INT LR ST T_ _C AR IN LR T_ T_C IN LR T_ CL R Register 10.31: UHCI_INT_CLR_REG (0x10) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_SEND_A_REG_Q_INT_CLR Set this bit to clear the UHCI_SEND_A_REG_Q_INT interrupt. (WO) UHCI_SEND_S_REG_Q_INT_CLR Set this bit to clear the UHCI_SEND_S_REG_Q_INT interrupt. (WO) UHCI_OUT_TOTAL_EOF_INT_CLR Set this bit to clear the UHCI_OUT_TOTAL_EOF_INT interrupt. (WO) UHCI_OUTLINK_EOF_ERR_INT_CLR Set this bit to clear the UHCI_OUTLINK_EOF_ERR_INT interrupt. (WO) UHCI_IN_DSCR_EMPTY_INT_CLR Set this bit to clear the UHCI_IN_DSCR_EMPTY_INT interrupt. (WO) UHCI_OUT_DSCR_ERR_INT_CLR Set this bit to clear the UHCI_OUT_DSCR_ERR_INT interrupt. (WO) UHCI_IN_DSCR_ERR_INT_CLR Set this bit to clear the UHCI_IN_DSCR_ERR_INT interrupt. (WO) UHCI_OUT_EOF_INT_CLR Set this bit to clear the UHCI_OUT_EOF_INT interrupt. (WO) UHCI_OUT_DONE_INT_CLR Set this bit to clear the UHCI_OUT_DONE_INT interrupt. (WO) UHCI_IN_ERR_EOF_INT_CLR Set this bit to clear the UHCI_IN_ERR_EOF_INT interrupt. (WO) UHCI_IN_SUC_EOF_INT_CLR Set this bit to clear the UHCI_IN_SUC_EOF_INT interrupt. (WO) UHCI_IN_DONE_INT_CLR Set this bit to clear the UHCI_IN_DONE_INT interrupt. (WO) UHCI_TX_HUNG_INT_CLR Set this bit to clear the UHCI_TX_HUNG_INT interrupt. (WO) UHCI_RX_HUNG_INT_CLR Set this bit to clear the UHCI_RX_HUNG_INT interrupt. (WO) UHCI_TX_START_INT_CLR Set this bit to clear the UHCI_TX_START_INT interrupt. (WO) UHCI_RX_START_INT_CLR Set this bit to clear the UHCI_RX_START_INT interrupt. (WO) Espressif Systems 255 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re se rv ed ) UH C UH I_O CI UT _O _E UT M _F PTY UL L Register 10.32: UHCI_DMA_OUT_STATUS_REG (0x14) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 Reset UHCI_OUT_EMPTY 1: DMA inlink descriptor’s FIFO is empty. (RO) UHCI_OUT_FULL 1: DMA outlink descriptor’s FIFO is full. (RO) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 0 0 0 UT _O ed ) CI rv UH (re se UH (re se r CI _O ve d ) UT FI F O FI FO _W _P U SH DA TA Register 10.33: UHCI_DMA_OUT_PUSH_REG (0x18) 9 0 0 0 0 0 8 0 0 0x000 Reset UHCI_OUTFIFO_PUSH Set this bit to push data into DMA FIFO. (R/W) UHCI_OUTFIFO_WDATA This is the data that need to be pushed into DMA FIFO. (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 FI _I N d) CI rv e UH (re UH 31 0 se CI (re se r _I ve d ) NF IF O FO _R D _P O P AT A Register 10.34: UHCI_DMA_IN_POP_REG (0x20) 17 16 15 0 0 0 12 0 0 11 0 0 0x0000 Reset UHCI_INFIFO_POP Set this bit to pop data from DMA FIFO. (R/W) UHCI_INFIFO_RDATA This register stores the data popping from DMA FIFO. (RO) Espressif Systems 256 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS UH UH CI _ O UT LI NK _A D DR C UH I_O C U UH I_O TLIN C U K UH I_O TLIN _PA CI UT K_ RK _O LI R UT NK ES LI _S TA NK TA RT _S RT TO P (re se rv ed ) Register 10.35: UHCI_DMA_OUT_LINK_REG (0x24) 31 30 29 28 27 0 0 0 0 0 20 0 0 0 0 0 0 19 0 0 0x000000 Reset UHCI_OUTLINK_PARK 1: the outlink descriptor’s FSM is in idle state; 0: the outlink descriptor’s FSM is working. (RO) UHCI_OUTLINK_RESTART Set this bit to restart the outlink descriptor from the last address. (R/W) UHCI_OUTLINK_START Set this bit to start a new outlink descriptor. (R/W) UHCI_OUTLINK_STOP Set this bit to stop dealing with the outlink descriptor. (R/W) UHCI_OUTLINK_ADDR This register stores the least significant 20 bits of the first outlink descriptor’s address. (R/W) 31 30 29 28 27 0 0 0 0 0 DR K_ AD IN CI _I NL ve d) UH se r (re UH CI UH _IN C L UH I_IN INK CI LIN _PA UH _IN K R CI LIN _R K E _I NL K_ ST IN ST AR K_ AR T ST T O P Register 10.36: UHCI_DMA_IN_LINK_REG (0x28) 20 0 0 0 0 0 0 19 0 0 0x000000 Reset UHCI_INLINK_PARK 1: the inlink descriptor’s FSM is in idle state; 0: the inlink descriptor’s FSM is working. (RO) UHCI_INLINK_RESTART Set this bit to mount new inlink descriptors. (R/W) UHCI_INLINK_START Set this bit to start dealing with the inlink descriptors. (R/W) UHCI_INLINK_STOP Set this bit to stop dealing with the inlink descriptors. (R/W) UHCI_INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor’s address. (R/W) Espressif Systems 257 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS (re se rv ed ) UH C UH I_T CI X_A _T C X_ K_ (re CH N se U rv ed ECK M_ UH ) _S RE C UM UH I_C _R CI HE E _C C HE K_ S CK EQ _S _E UM N _E N Register 10.37: UHCI_CONF1_REG (0x2C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 1 1 0 0 1 1 Reset UHCI_TX_ACK_NUM_RE Reserved. Please initialize to 0. (R/W) UHCI_TX_CHECK_SUM_RE Reserved. Please initialize to 0. (R/W) UHCI_CHECK_SEQ_EN Reserved. Please initialize to 0. (R/W) UHCI_CHECK_SUM_EN Reserved. Please initialize to 0. (R/W) Register 10.38: UHCI_DMA_OUT_EOF_DES_ADDR_REG (0x38) 31 0 0x000000000 Reset UHCI_DMA_OUT_EOF_DES_ADDR_REG This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. (RO) Register 10.39: UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG (0x3C) 31 0 0x000000000 Reset UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. (RO) Register 10.40: UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG (0x40) 31 0 0x000000000 Reset UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG This register stores the address of the inlink descriptor when there are some errors in this descriptor. (RO) Espressif Systems 258 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS Register 10.41: UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG (0x44) 31 0 0x000000000 Reset UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG This register stores the address of the outlink descriptor when there are some errors in this descriptor. (RO) Register 10.42: UHCI_DMA_IN_DSCR_REG (0x4C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_DMA_IN_DSCR_REG The address of the current inlink descriptor x. (RO) Register 10.43: UHCI_DMA_IN_DSCR_BF0_REG (0x50) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_DMA_IN_DSCR_BF0_REG The address of the last inlink descriptor x-1. (RO) Register 10.44: UHCI_DMA_IN_DSCR_BF1_REG (0x54) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_DMA_IN_DSCR_BF1_REG The address of the second-to-last inlink descriptor x-2. (RO) Register 10.45: UHCI_DMA_OUT_DSCR_REG (0x58) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 Reset UHCI_DMA_OUT_DSCR_REG The address of the current outlink descriptor y. (RO) Register 10.46: UHCI_DMA_OUT_DSCR_BF0_REG (0x5C) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UHCI_DMA_OUT_DSCR_BF0_REG The address of the last outlink descriptor y-1. (RO) Espressif Systems 259 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS Register 10.47: UHCI_DMA_OUT_DSCR_BF1_REG (0x60) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset UHCI_DMA_OUT_DSCR_BF1_REG The address of the second-to-last outlink descriptor y-2. (RO) UH (re s er ve d) C UH I_R C X_ UH I_R 13 C X_ _E UH I_R 11 SC C X_ _E _E UH I_R DB SC N C X_ _E _E UH I_T C0 SC N C X_ _E _E UH I_T 13_ SC N C X_ E _E UH I_T 11_ SC_ N CI X_D ES EN _T B C X_ _E _E C0 SC N _E _E SC N _E N Register 10.48: UHCI_ESCAPE_CONF_REG (0x64) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 1 1 Reset UHCI_RX_13_ESC_EN Set this bit to enable replacing flow control char 0x13, when DMA sends data. (R/W) UHCI_RX_11_ESC_EN Set this bit to enable replacing flow control char 0x11, when DMA sends data. (R/W) UHCI_RX_DB_ESC_EN Set this bit to enable replacing 0xdb char, when DMA sends data. (R/W) UHCI_RX_C0_ESC_EN Set this bit to enable replacing 0xc0 char, when DMA sends data. (R/W) UHCI_TX_13_ESC_EN Set this bit to enable decoding flow control char 0x13, when DMA receives data. (R/W) UHCI_TX_11_ESC_EN Set this bit to enable decoding flow control char 0x11, when DMA receives data. (R/W) UHCI_TX_DB_ESC_EN Set this bit to enable decoding 0xdb char, when DMA receives data. (R/W) UHCI_TX_C0_ESC_EN Set this bit to enable decoding 0xc0 char, when DMA receives data. (R/W) Espressif Systems 260 ESP32 Technical Reference Manual V2.0 10. UART CONTROLLERS 31 0 0 0 0 0 0 0 24 23 22 0 1 0 UH CI 20 0 UT UH CI _T XF IF UH O _T CI IM _T EO XF IF UT O _E _T NA IM EO UT _S HI FT UH CI _T XF IF O _T IM EO UT IM FO _T _R X FI FI FO _T RX CI _ UH (re se UH CI _ rv ed RX ) FI FO _T IM EO EO UT _E NA IM EO UT _S HI FT Register 10.49: UHCI_HUNG_CONF_REG (0x68) 19 12 0 0x010 11 10 1 0 8 0 7 0 0 0x010 Reset UHCI_RXFIFO_TIMEOUT_ENA This is the enable bit for DMA send-data timeout. (R/W) UHCI_RXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value is equal to or greater than (17’d8000»reg_rxfifo_timeout_shift). (R/W) UHCI_RXFIFO_TIMEOUT This register stores the timeout value. When DMA takes more time to read data from RAM than what this register indicates, it will produce the UHCI_RX_HUNG_INT interrupt. (R/W) UHCI_TXFIFO_TIMEOUT_ENA The enable bit for Tx FIFO receive-data timeout (R/W) UHCI_TXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value is equal to or greater than (17’d8000»reg_txfifo_timeout_shift). (R/W) UHCI_TXFIFO_TIMEOUT This register stores the timeout value. When DMA takes more time to receive data than what this register indicates, it will produce the UHCI_TX_HUNG_INT interrupt. (R/W) 0 0 0 0 0 0 23 2 ES C_ SE Q UH UH CI CI _ _E _E UH CI 24 0 SC SC d) rv e (re se 31 0 _S _S EQ EQ 2_ 2_ C CH HA AR R0 1 Register 10.50: UHCI_ESC_CONFn_REG (n: 0-3) (0xB0+4*n) 16 15 0x0DF 8 0x0DB 7 0 0x013 Reset UHCI_ESC_SEQ2_CHAR1 This register stores the second char used to replace the reg_esc_seq2 in data. (R/W) UHCI_ESC_SEQ2_CHAR0 This register stores the first char used to replace the reg_esc_seq2 in data. (R/W) UHCI_ESC_SEQ2 This register stores the flow_control char to turn off the flow_control. (R/W) Espressif Systems 261 ESP32 Technical Reference Manual V2.0 11. LED_PWM 11. LED_PWM 11.1 Introduction The LED_PWM controller is primarily designed to control the intensity of LEDs, although it can be used to generate PWM signals for other purposes as well. It has 16 channels which can generate independent waveforms that can be used to drive RGB LED devices. For maximum flexibility, the high-speed as well as the low-speed channels can be driven from one of four high-speed/low-speed timers. The PWM controller also has the ability to automatically increase or decrease the duty cycle gradually, allowing for fades without any processor interference. To increase resolution, the LED_PWM controller is also able to dither between two values, when a fractional PWM value is configured. The LED_PWM controller has eight high-speed and eight low-speed PWM generators. In this document, they will be referred to as hschn and lschn, respectively. These channels can be driven from four timers which will be indicated by h_timerx and l_timerx. 11.2 Functional Description 11.2.1 Architecture Figure 69: LED_PWM Architecture Figure 69 shows the architecture of the LED_PWM controller. As can be seen in the figure, the LED_PWM controller contains eight high-speed and eight low-speed channels. There are four high-speed clock modules for the high-speed channels, from which one h_timerx can be selected. There are also four low-speed clock modules for the low-speed channels, from which one l_timerx can be selected. Figure 70: LED_PWM High-speed Channel Diagram Espressif Systems 262 ESP32 Technical Reference Manual V2.0 11. LED_PWM Figure 70 illustrates a PWM channel with its selected timer; in this instance a high-speed channel and associated high-speed timer. 11.2.2 Timers A high-speed timer consists of a multiplexer to select one of two clock sources: either REF_TICK or APB_CLK. For more information on the clock sources, please see Chapter Reset And Clock. The input clock is divided down by a divider first. The division factor is specified by LEDC_DIV_NUM_HSTIMERx which contains a fixed point number: the highest 10 bits represent the integer portion, while the lowest eight bits contain the fractional portion. The divided clock signal is then fed into a 20-bit counter. This counter will count up to the value specified in LEDC_HSTIMERx_LIM. An overflow interrupt will be generated once the counting value reaches this limit, at which point the counter restarts counting from zero. It is also possible to reset, suspend, and read the values of the counter by software. The output signal of the timer is the 20-bit value generated by the counter. The cycle period of this signal defines the frequency of the signals of any PWM channels connected to this timer. This frequency depends on both the division factor of the divider, as well as the range of the counter: fsig_out = fREF_TICK · (!LEDC_TICK_SEL_HSTIMERx) + fAPB_CLK · LEDC_TICK_SEL_HSTIMERx LEDC_DIV_NUM_HSTIMERx · 2LEDC_HSTIMERx_LIM The low-speed timers l_timerx on the low-speed channel differ from the high-speed timers h_timerx in two aspects: 1. Where the high-speed timer clock source can be clocked from REF_TICK or APB_CLK, the low speed timers are sourced from either REF_TICK or SLOW_CLOCK. The SLOW_CLOCK source can be either APB_CLK (80 MHz) or 8 MHz, and can be selected using LEDC_APB_CLK_SEL. 2. The high-speed counter and divider are glitch-free, which means that if the software modifies the maximum counter or divisor value, the update will come into effect after the next overflow interrupt. In contrast, the low-speed counter and divider will update these values only when LEDC_LSTIMERx_PARA_UP is set. 11.2.3 Channels A channel takes the 20-bit value from the counter of the selected high-speed timer and compares it to a set of two values in order to set the channel output. The first value it is compared to is the content of LEDC_HPOINT_HSCHn; if these two match, the output will be latched high. The second value is the sum of LEDC_HPOINT_HSCHn and LEDC_DUTY_HSCHn[24..4]. When this value is reached, the output is latched low. By using these two values, the relative phase and the duty cycle of the PWM output can be set. Figure 71 illustrates this. Figure 71: LED PWM Output Signal Diagram Espressif Systems 263 ESP32 Technical Reference Manual V2.0 11. LED_PWM LEDC_DUTY_HSCHn is a fixed-point register with four fractional bits. As mentioned before, when LEDC_DUTY_HSCHn[24..4] is used in the PWM calculation directly, LEDC_DUTY_HSCHn[3..0] can be used to dither the output. If this value is non-zero, with a statistical chance of LEDC_DUTY_HSCHn[3..0]/16, the actual PWM pulse will be one cycle longer. This effectively increases the resolution of the PWM generator to 24 bits, but at the cost of a slight jitter in the duty cycle. The channels also have the ability to automatically fade from one duty cycle value to another. This feature is enabled by setting LEDC_DUTY_START_HSCHn. When this bit is set, the PWM controller will automatically increment or decrement the value in LEDC_DUTY_HSCHn, depending on whether the bit LEDC_DUTY_INC_HSCHn is set or cleared, respectively. The speed the duty cycle changes is defined as such: every time the LEDC_DUTY_CYCLE_HSCHn cycles, the content of LEDC_DUTY_SCALE_HSCHn is added to or subtracted from LEDC_DUTY_HSCHn[24..4]. The length of the fade can be limited by setting LEDC_DUTY_NUM_HSCHn: the fade will only last that number of cycles before finishing. A finished fade also generates an interrupt. Figure 72: Output Signal Diagram of Gradient Duty Cycle Figure 72 is an illustration of this. In this configuration, LEDC_DUTY_NUM_HSCHn_R increases by LEDC_DUTY_SCALE_HSCHn for every LEDC_DUTY_CYCLE_HSCHn clock cycles, which is reflected in the duty cycle of the output signal. 11.2.4 Interrupts • LEDC_DUTY_CHNG_END_LSCHn_INT: Triggered when a fade on a low-speed channel has finished. • LEDC_DUTY_CHNG_END_HSCHn_INT: Triggered when a fade on a high-speed channel has finished. • LEDC_HS_TIMERx_OVF_INT: Triggered when a high-speed timer has reached its maximum counter value. • LEDC_LS_TIMERx_OVF_INT: Triggered when a low-speed timer has reached its maximum counter value. 11.3 Register Summary Name Description Address Access LEDC_CONF_REG Global ledc configuration register 0x3FF59190 R/W LEDC_HSCH0_CONF0_REG Configuration register 0 for high-speed channel 0 0x3FF59000 R/W LEDC_HSCH1_CONF0_REG Configuration register 0 for high-speed channel 1 0x3FF59014 R/W LEDC_HSCH2_CONF0_REG Configuration register 0 for high-speed channel 2 0x3FF59028 R/W LEDC_HSCH3_CONF0_REG Configuration register 0 for high-speed channel 3 0x3FF5903C R/W LEDC_HSCH4_CONF0_REG Configuration register 0 for high-speed channel 4 0x3FF59050 R/W Configuration registers Espressif Systems 264 ESP32 Technical Reference Manual V2.0 11. LED_PWM Name Description Address Access LEDC_HSCH5_CONF0_REG Configuration register 0 for high-speed channel 5 0x3FF59064 R/W LEDC_HSCH6_CONF0_REG Configuration register 0 for high-speed channel 6 0x3FF59078 R/W LEDC_HSCH7_CONF0_REG Configuration register 0 for high-speed channel 7 0x3FF5908C R/W LEDC_HSCH0_CONF1_REG Configuration register 1 for high-speed channel 0 0x3FF5900C R/W LEDC_HSCH1_CONF1_REG Configuration register 1 for high-speed channel 1 0x3FF59020 R/W LEDC_HSCH2_CONF1_REG Configuration register 1 for high-speed channel 2 0x3FF59034 R/W LEDC_HSCH3_CONF1_REG Configuration register 1 for high-speed channel 3 0x3FF59048 R/W LEDC_HSCH4_CONF1_REG Configuration register 1 for high-speed channel 4 0x3FF5905C R/W LEDC_HSCH5_CONF1_REG Configuration register 1 for high-speed channel 5 0x3FF59070 R/W LEDC_HSCH6_CONF1_REG Configuration register 1 for high-speed channel 6 0x3FF59084 R/W LEDC_HSCH7_CONF1_REG Configuration register 1 for high-speed channel 7 0x3FF59098 R/W LEDC_LSCH0_CONF0_REG Configuration register 0 for low-speed channel 0 0x3FF590A0 R/W LEDC_LSCH1_CONF0_REG Configuration register 0 for low-speed channel 1 0x3FF590B4 R/W LEDC_LSCH2_CONF0_REG Configuration register 0 for low-speed channel 2 0x3FF590C8 R/W LEDC_LSCH3_CONF0_REG Configuration register 0 for low-speed channel 3 0x3FF590DC R/W LEDC_LSCH4_CONF0_REG Configuration register 0 for low-speed channel 4 0x3FF590F0 R/W LEDC_LSCH5_CONF0_REG Configuration register 0 for low-speed channel 5 0x3FF59104 R/W LEDC_LSCH6_CONF0_REG Configuration register 0 for low-speed channel 6 0x3FF59118 R/W LEDC_LSCH7_CONF0_REG Configuration register 0 for low-speed channel 7 0x3FF5912C R/W LEDC_LSCH0_CONF1_REG Configuration register 1 for low-speed channel 0 0x3FF590AC R/W LEDC_LSCH1_CONF1_REG Configuration register 1 for low-speed channel 1 0x3FF590C0 R/W LEDC_LSCH2_CONF1_REG Configuration register 1 for low-speed channel 2 0x3FF590D4 R/W LEDC_LSCH3_CONF1_REG Configuration register 1 for low-speed channel 3 0x3FF590E8 R/W LEDC_LSCH4_CONF1_REG Configuration register 1 for low-speed channel 4 0x3FF590FC R/W LEDC_LSCH5_CONF1_REG Configuration register 1 for low-speed channel 5 0x3FF59110 R/W LEDC_LSCH6_CONF1_REG Configuration register 1 for low-speed channel 6 0x3FF59124 R/W LEDC_LSCH7_CONF1_REG Configuration register 1 for low-speed channel 7 0x3FF59138 R/W LEDC_HSCH0_DUTY_REG Initial duty cycle for high-speed channel 0 0x3FF59008 R/W LEDC_HSCH1_DUTY_REG Initial duty cycle for high-speed channel 1 0x3FF5901C R/W LEDC_HSCH2_DUTY_REG Initial duty cycle for high-speed channel 2 0x3FF59030 R/W LEDC_HSCH3_DUTY_REG Initial duty cycle for high-speed channel 3 0x3FF59044 R/W LEDC_HSCH4_DUTY_REG Initial duty cycle for high-speed channel 4 0x3FF59058 R/W LEDC_HSCH5_DUTY_REG Initial duty cycle for high-speed channel 5 0x3FF5906C R/W LEDC_HSCH6_DUTY_REG Initial duty cycle for high-speed channel 6 0x3FF59080 R/W LEDC_HSCH7_DUTY_REG Initial duty cycle for high-speed channel 7 0x3FF59094 R/W LEDC_HSCH0_DUTY_R_REG Current duty cycle for high-speed channel 0 0x3FF59010 RO LEDC_HSCH1_DUTY_R_REG Current duty cycle for high-speed channel 1 0x3FF59024 RO LEDC_HSCH2_DUTY_R_REG Current duty cycle for high-speed channel 2 0x3FF59038 RO LEDC_HSCH3_DUTY_R_REG Current duty cycle for high-speed channel 3 0x3FF5904C RO LEDC_HSCH4_DUTY_R_REG Current duty cycle for high-speed channel 4 0x3FF59060 RO LEDC_HSCH5_DUTY_R_REG Current duty cycle for high-speed channel 5 0x3FF59074 RO LEDC_HSCH6_DUTY_R_REG Current duty cycle for high-speed channel 6 0x3FF59088 RO LEDC_HSCH7_DUTY_R_REG Current duty cycle for high-speed channel 7 0x3FF5909C RO Duty-cycle registers Espressif Systems 265 ESP32 Technical Reference Manual V2.0 11. LED_PWM Name Description Address Access LEDC_LSCH0_DUTY_REG Initial duty cycle for low-speed channel 0 0x3FF590A8 R/W LEDC_LSCH1_DUTY_REG Initial duty cycle for low-speed channel 1 0x3FF590BC R/W LEDC_LSCH2_DUTY_REG Initial duty cycle for low-speed channel 2 0x3FF590D0 R/W LEDC_LSCH3_DUTY_REG Initial duty cycle for low-speed channel 3 0x3FF590E4 R/W LEDC_LSCH4_DUTY_REG Initial duty cycle for low-speed channel 4 0x3FF590F8 R/W LEDC_LSCH5_DUTY_REG Initial duty cycle for low-speed channel 5 0x3FF5910C R/W LEDC_LSCH6_DUTY_REG Initial duty cycle for low-speed channel 6 0x3FF59120 R/W LEDC_LSCH7_DUTY_REG Initial duty cycle for low-speed channel 7 0x3FF59134 R/W LEDC_LSCH0_DUTY_R_REG Current duty cycle for low-speed channel 0 0x3FF590B0 RO LEDC_LSCH1_DUTY_R_REG Current duty cycle for low-speed channel 1 0x3FF590C4 RO LEDC_LSCH2_DUTY_R_REG Current duty cycle for low-speed channel 2 0x3FF590D8 RO LEDC_LSCH3_DUTY_R_REG Current duty cycle for low-speed channel 3 0x3FF590EC RO LEDC_LSCH4_DUTY_R_REG Current duty cycle for low-speed channel 4 0x3FF59100 RO LEDC_LSCH5_DUTY_R_REG Current duty cycle for low-speed channel 5 0x3FF59114 RO LEDC_LSCH6_DUTY_R_REG Current duty cycle for low-speed channel 6 0x3FF59128 RO LEDC_LSCH7_DUTY_R_REG Current duty cycle for low-speed channel 7 0x3FF5913C RO LEDC_HSTIMER0_CONF_REG High-speed timer 0 configuration 0x3FF59140 R/W LEDC_HSTIMER1_CONF_REG High-speed timer 1 configuration 0x3FF59148 R/W LEDC_HSTIMER2_CONF_REG High-speed timer 2 configuration 0x3FF59150 R/W LEDC_HSTIMER3_CONF_REG High-speed timer 3 configuration 0x3FF59158 R/W LEDC_HSTIMER0_VALUE_REG High-speed timer 0 current counter value 0x3FF59144 RO LEDC_HSTIMER1_VALUE_REG High-speed timer 1 current counter value 0x3FF5914C RO LEDC_HSTIMER2_VALUE_REG High-speed timer 2 current counter value 0x3FF59154 RO LEDC_HSTIMER3_VALUE_REG High-speed timer 3 current counter value 0x3FF5915C RO LEDC_LSTIMER0_CONF_REG Low-speed timer 0 configuration 0x3FF59160 R/W LEDC_LSTIMER1_CONF_REG Low-speed timer 1 configuration 0x3FF59168 R/W LEDC_LSTIMER2_CONF_REG Low-speed timer 2 configuration 0x3FF59170 R/W LEDC_LSTIMER3_CONF_REG Low-speed timer 3 configuration 0x3FF59178 R/W LEDC_LSTIMER0_VALUE_REG Low-speed timer 0 current counter value 0x3FF59164 RO LEDC_LSTIMER1_VALUE_REG Low-speed timer 1 current counter value 0x3FF5916C RO LEDC_LSTIMER2_VALUE_REG Low-speed timer 2 current counter value 0x3FF59174 RO LEDC_LSTIMER3_VALUE_REG Low-speed timer 3 current counter value 0x3FF5917C RO LEDC_INT_RAW_REG Raw interrupt status 0x3FF59180 RO LEDC_INT_ST_REG Masked interrupt status 0x3FF59184 RO LEDC_INT_ENA_REG Interrupt enable bits 0x3FF59188 R/W LEDC_INT_CLR_REG Interrupt clear bits 0x3FF5918C WO Timer registers Interrupt registers Espressif Systems 266 ESP32 Technical Reference Manual V2.0 11. LED_PWM 11.4 Registers (re s er ve d) LE D LE C_I DC DL _ E_ LE SIG LV_ DC _O HS U C _T IM T_E Hn N ER _S _HS EL C _H Hn SC Hn Register 11.1: LEDC_HSCHn_CONF0_REG (n: 0-7) (0x1C+0x10*n) 31 4 0x00000000 3 2 0 0 1 0 0 Reset LEDC_IDLE_LV_HSCHn This bit is used to control the output value when high-speed channel n is inactive. (R/W) LEDC_SIG_OUT_EN_HSCHn This is the output enable control bit for high-speed channel n. (R/W) LEDC_TIMER_SEL_HSCHn There are four high-speed timers. These two bits are used to select one of them for high-speed channel n: (R/W) 0: select hstimer0; 1: select hstimer1; 2: select hstimer2; 3: select hstimer3. (re LE se r DC _H ve d) PO IN T_ HS CH n Register 11.2: LEDC_HSCHn_HPOINT_REG (n: 0-7) (0x20+0x10*n) 31 20 19 0 0x0000 0x000000 Reset LEDC_HPOINT_HSCHn The output value changes to high when htimerx(x=[0,3]), selected by highspeed channel n, has reached reg_hpoint_hschn[19:0]. (R/W) Espressif Systems 267 ESP32 Technical Reference Manual V2.0 11. LED_PWM (re LE se rv ed ) DC _D UT Y_ HS CH n Register 11.3: LEDC_HSCHn_DUTY_REG (n: 0-7) (0x24+0x10*n) 31 25 24 0 0x00 0x0000000 Reset LEDC_DUTY_HSCHn The register is used to control output duty. When hstimerx(x=[0,3]), selected by high-speed channel n, has reached reg_lpoint_hschn, the output signal changes to low. (R/W) reg_lpoint_hschn=(reg_hpoint_hschn[19:0]+reg_duty_hschn[24:4]) (1) reg_lpoint_hschn=(reg_hpoint_hschn[19:0]+reg_duty_hschn[24:4] +1) (2) See the Functional Description for more information on when (1) or (2) is chosen. 31 30 0 1 29 SC _H LE E_ CA CL _S CY TY Y_ DU UT C_ _D LE D DC LE 20 0x000 Hn n CH HS Hn SC _H UM _N TY _D U DC LE LE D LE C_D DC U _D TY_ UT ST Y_ AR IN T_ C_ H HS SC CH Hn n Register 11.4: LEDC_HSCHn_CONF1_REG (n: 0-7) (0x28+0x10*n) 19 10 9 0x000 0 0x000 Reset LEDC_DUTY_START_HSCHn When REG_DUTY_NUM_HSCHn, REG_DUTY_CYCLE_HSCHn and REG_DUTY_SCALE_HSCHn has been configured, these register will not take effect until REG_DUTY_START_HSCHn is set. This bit is automatically cleared by hardware. (R/W) LEDC_DUTY_INC_HSCHn This register is used to increase or decrease the duty of output signal for high-speed channel n. (R/W) LEDC_DUTY_NUM_HSCHn This register is used to control the number of times the duty cycle is increased or decreased for high-speed channel n. (R/W) LEDC_DUTY_CYCLE_HSCHn This register is used to increase or decrease the duty cycle every time REG_DUTY_CYCLE_HSCHn cycles for high-speed channel n. (R/W) LEDC_DUTY_SCALE_HSCHn This register is used to increase or decrease the step scale for highspeed channel n. (R/W) Espressif Systems 268 ESP32 Technical Reference Manual V2.0 11. LED_PWM (re se rv ed ) LE DC _D UT Y_ HS CH n _R Register 11.5: LEDC_HSCHn_DUTY_R_REG (n: 0-7) (0x2C+0x10*n) 31 25 24 0 0x00 0x0000000 Reset LEDC_DUTY_HSCHn_R This register represents the current duty cycle of the output signal for highspeed channel n. (RO) (re se rv e d) LE D LE C_P D A LE C_I RA_ DC DL UP _ E_ _ LE SIG LV_ LSC DC _O LS H U C n _T IM T_E Hn N ER _S _LS C EL _L Hn SC Hn Register 11.6: LEDC_LSCHn_CONF0_REG (n: 0-7) (0xBC+0x10*n) 31 5 0x0000000 4 3 2 0 0 0 1 0 0 Reset LEDC_PARA_UP_LSCHn This bit is used to update register LEDC_LSCHn_HPOINT and LEDC_LSCHn_DUTY for low-speed channel n. (R/W) LEDC_IDLE_LV_LSCHn This bit is used to control the output value, when low-speed channel n is inactive. (R/W) LEDC_SIG_OUT_EN_LSCHn This is the output enable control bit for low-speed channel n. (R/W) LEDC_TIMER_SEL_LSCHn There are four low-speed timers, the two bits are used to select one of them for low-speed channel n. (R/W) 0: select lstimer0; 1: select lstimer1; 2: select lstimer2; 3: select lstimer3. Espressif Systems 269 ESP32 Technical Reference Manual V2.0 11. LED_PWM (re s er ve d) LE DC _H PO IN T_ LS CH n Register 11.7: LEDC_LSCHn_HPOINT_REG (n: 0-7) (0xC0+0x10*n) 31 20 19 0 0x0000 0x000000 Reset LEDC_HPOINT_LSCHn The output value changes to high when lstimerx(x=[0,3]), selected by lowspeed channel n, has reached reg_hpoint_lschn[19:0]. (R/W) (re LE D se C_ rv e d) DU TY _L SC Hn Register 11.8: LEDC_LSCHn_DUTY_REG (n: 0-7) (0xC4+0x10*n) 31 25 24 0 0x00 0x0000000 Reset LEDC_DUTY_LSCHn The register is used to control output duty. When lstimerx(x=[0,3]), chosen by low-speed channel n, has reached reg_lpoint_lschn,the output signal changes to low. (R/W) reg_lpoint_lschn=(reg_hpoint_lschn[19:0]+reg_duty_lschn[24:4]) (1) reg_lpoint_lschn=(reg_hpoint_lschn[19:0]+reg_duty_lschn[24:4] +1) (2) See the Functional Description for more information on when (1) or (2) is chosen. Espressif Systems 270 ESP32 Technical Reference Manual V2.0 11. LED_PWM 31 30 0 1 29 CH n CH n DC _D UT LE DC _D UT Y Y_ CY CL E _S CA LE _ LS _L S _L SC Hn M _N U UT Y C_ D LE LE D LE D LE C_D DC U _D TY_ UT ST Y_ AR IN T_ C_ LS LS C CH H n n Register 11.9: LEDC_LSCHn_CONF1_REG (n: 0-7) (0xC8+0x10*n) 20 19 0x000 LEDC_DUTY_START_LSCHn When 10 9 0 0x000 0x000 reg_duty_num_hschn, reg_duty_cycle_hschn Reset and reg_duty_scale_hschn have been configured, these settings will not take effect until set reg_duty_start_hschn. This bit is automatically cleared by hardware. (R/W) LEDC_DUTY_INC_LSCHn This register is used to increase or decrease the duty of output signal for low-speed channel n. (R/W) LEDC_DUTY_NUM_LSCHn This register is used to control the number of times the duty cycle is increased or decreased for low-speed channel n. (R/W) LEDC_DUTY_CYCLE_LSCHn This register is used to increase or decrease the duty every reg_duty_cycle_lschn cycles for low-speed channel n. (R/W) LEDC_DUTY_SCALE_LSCHn This register is used to increase or decrease the step scale for lowspeed channel n. (R/W) (re LE se r DC _D ve d ) UT Y_ LS CH n_ R Register 11.10: LEDC_LSCHn_DUTY_R_REG (n: 0-7) (0xCC+0x10*n) 31 25 24 0 0x00 0x0000000 Reset LEDC_DUTY_LSCHn_R This register represents the current duty of the output signal for low-speed channel n. (RO) Espressif Systems 271 ESP32 Technical Reference Manual V2.0 11. LED_PWM 31 26 25 24 23 0 1 0 0x00 x ER ER x_ LI M IM _H ST IM NU M DC _H ST IV _ C_ D LE LE D (re s er ve d) LE D LE C_T D IC LE C_H K_ DC S SE _H TIM L_H ST ER ST IM x_ IM ER RS ER x_ T x PA US E Register 11.11: LEDC_HSTIMERx_CONF_REG (x: 0-3) (0x140+8*x) 22 5 4 0 0x00000 0x00 Reset LEDC_TICK_SEL_HSTIMERx This bit is used to select APB_CLK or REF_TICK for high-speed timer x. (R/W) 1: APB_CLK; 0: REF_TICK. LEDC_HSTIMERx_RST This bit is used to reset high-speed timer x. The counter value will be ’zero’ after reset. (R/W) LEDC_HSTIMERx_PAUSE This bit is used to suspend the counter in high-speed timer x. (R/W) LEDC_DIV_NUM_HSTIMERx This register is used to configure the division factor for the divider in high-speed timer x. The least significant eight bits represent the fractional part. (R/W) LEDC_HSTIMERx_LIM This register is used to control the range of the counter in high-speed timer x. The counter range is [0,2**reg_hstimerx_lim], the maximum bit width for counter is 20. (R/W) (re LE DC _H se rv ed ) ST IM ER x_ C NT Register 11.12: LEDC_HSTIMERx_VALUE_REG (x: 0-3) (0x144+8*x) 31 20 0x0000 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset LEDC_HSTIMERx_CNT Software can read this register to get the current counter value of high-speed timer x. (RO) Espressif Systems 272 ESP32 Technical Reference Manual V2.0 11. LED_PWM 31 27 0x00 26 25 24 23 0 0 1 0 x ER IM TI M x_ L _L S IM ER NU M ST IV _ DC _L C_ D LE LE D (re se rv ed ) LE D LE C_L DC ST LE _T IM D IC ER LE C_L K_ x_P DC ST SE A _L IM L_L RA_ ST ER ST U IM x_ IM P ER RS ER x_ T x PA US E Register 11.13: LEDC_LSTIMERx_CONF_REG (x: 0-3) (0x160+8*x) 22 5 4 0 0x00000 LEDC_LSTIMERx_PARA_UP Set this bit to 0x00 update Reset REG_DIV_NUM_LSTIMEx and REG_LSTIMERx_LIM. (R/W) LEDC_TICK_SEL_LSTIMERx This bit is used to select SLOW_CLK or REF_TICK for low-speed timer x. (R/W) 1: SLOW_CLK; 0: REF_TICK. LEDC_LSTIMERx_RST This bit is used to reset low-speed timer x. The counter will show 0 after reset. (R/W) LEDC_LSTIMERx_PAUSE This bit is used to suspend the counter in low-speed timer x. (R/W) LEDC_DIV_NUM_LSTIMERx This register is used to configure the division factor for the divider in low-speed timer x. The least significant eight bits represent the fractional part. (R/W) LEDC_LSTIMERx_LIM This register is used to control the range of the counter in low-speed timer x. The counter range is [0,2**reg_lstimerx_lim], the max bit width for counter is 20. (R/W) (re se LE DC _L S rv ed ) TI M ER x_ C NT Register 11.14: LEDC_LSTIMERx_VALUE_REG (x: 0-3) (0x164+8*x) 31 20 0x0000 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset LEDC_LSTIMERx_CNT Software can read this register to get the current counter value of low-speed timer x. (RO) Espressif Systems 273 ESP32 Technical Reference Manual V2.0 0 0 0 0 0 0 0 0 0 0 Espressif Systems 0 0 LE D LE C_D D U LE C_D TY_ DC U C LE _D TY_ HN D U C G_ LE C_D TY_ HN EN D U C G_ D_ LE C_D TY_ HN EN LS DC U C G_ D_ CH LE _D TY_ HN EN LS 7_ D U C G_ D_ CH IN LE C_D TY_ HN EN LS 6_ T_S D U C G_ D_ CH IN T LE C_D TY_ HN EN LS 5_ T_S D U C G_ D_ CH IN T LE C_D TY_ HN EN LS 4_ T_S D U C G_ D_ CH IN T LE C_D TY_ HN EN LS 3_ T_S DC U C G_ D_ CH IN T LE _D TY_ HN EN LS 2_ T_S D U C G_ D_ CH IN T LE C_D TY_ HN EN LS 1_ T_S D U C G_ D_ CH IN T LE C_D TY_ HN EN HS 0_ T_S D U C G_ D_ C IN T LE C_D TY_ HN EN HS H7_ T_S D U C G_ D_ C IN T LE C_D TY_ HN EN HS H6_ T_S D U C G_ D_ C IN T LE C_D TY_ HN EN HS H5_ T_S D U C G_ D_ C IN T LE C_L TY_ HN EN HS H4_ T_S D S C G_ D_ C IN T LE C_L TIM HN EN HS H3_ T_S D S ER G_ D_ C IN T LE C_L TIM 3_ EN HS H2_ T_S D S ER OV D_ C IN T LE C_L TIM 2_ F_ HS H1_ T_S D S ER OV INT C IN T LE C_H TIM 1_ F_ _S H0_ T_S D S ER OV INT T IN T T_ LE C_H TIM 0_ F_ _S ST DC S ER OV INT T LE _H TIM 3_ F_ _S I DC S ER OV NT T _H TIM 2_ F_ _S ST ER OV INT T IM 1_ F_ _S ER OV IN T 0_ F_ T_S O IN T VF T_ _I ST NT _S T d) rv e se (re LE D LE C_D D U LE C_D TY_ DC U C LE _D TY_ HN D U C G_ LE C_D TY_ HN EN D U C G_ D_ LE C_D TY_ HN EN LS DC U C G_ D_ CH LE _D TY_ HN EN LS 7_ D U C G_ D_ CH IN LE C_D TY_ HN EN LS 6_ T_R D U C G_ D_ CH IN A LE C_D TY_ HN EN LS 5_ T_R W D U C G_ D_ CH IN A LE C_D TY_ HN EN LS 4_ T_R W D U C G_ D_ CH IN A LE C_D TY_ HN EN LS 3_ T_R W DC U C G_ D_ CH IN AW LE _D TY_ HN EN LS 2_ T_R D U C G_ D_ CH IN A LE C_D TY_ HN EN LS 1_ T_R W D U C G_ D_ CH IN A LE C_D TY_ HN EN HS 0_ T_R W D U C G _ D _ C IN A LE C_D TY_ HN EN HS H7_ T_R W D U C G_ D_ C IN A LE C_D TY_ HN EN HS H6_ T_R W D U C G_ D_ C IN A LE C_D TY_ HN EN HS H5_ T_R W D U C G_ D_ C IN A LE C_L TY_ HN EN HS H4_ T_R W D S C G_ D_ C IN A LE C_L TIM HN EN HS H3_ T_R W D S ER G_ D_ C IN A LE C_L TIM 3_ EN HS H2_ T_R W D S ER OV D_ C IN A LE C_L TIM 2_ F_ HS H1_ T_R W D S ER OV INT C IN A LE C_H TIM 1_ F_ _R H0_ T_R W D S ER OV INT AW IN A T_ W LE C_H TIM 0_ F_ _R RA DC S ER OV INT AW W LE _H TIM 3_ F_ _R I DC S ER OV NT AW T _ _H IM 2_ F_ R ST ER OV INT AW IM 1_ F_ _R ER OV IN AW 0_ F_ T_R O IN A VF T_ W _I R NT AW _R AW d) ve er (re s 11. LED_PWM Register 11.15: LEDC_INT_RAW_REG (0x0180) 31 0 31 0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset LEDC_DUTY_CHNG_END_LSCHn_INT_RAW The LEDC_DUTY_CHNG_END_LSCHn_INT_ST The LEDC_DUTY_CHNG_END_HSCHn_INT_ST The 274 raw LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (RO) LEDC_DUTY_CHNG_END_HSCHn_INT_RAW The raw masked masked interrupt status bit for the interrupt status bit for the LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (RO) LEDC_LSTIMERx_OVF_INT_RAW The raw interrupt status bit for the LEDC_LSTIMERx_OVF_INT interrupt. (RO) LEDC_HSTIMERx_OVF_INT_RAW The raw interrupt status bit for the LEDC_HSTIMERx_OVF_INT interrupt. (RO) Register 11.16: LEDC_INT_ST_REG (0x0184) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (RO) interrupt status bit for the interrupt status bit for the LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (RO) LEDC_LSTIMERx_OVF_INT_ST The masked interrupt status bit for the LEDC_LSTIMERx_OVF_INT interrupt. (RO) LEDC_HSTIMERx_OVF_INT_ST The masked interrupt status bit for the LEDC_HSTIMERx_OVF_INT interrupt. (RO) ESP32 Technical Reference Manual V2.0 0 0 0 0 0 0 0 0 0 0 Espressif Systems 0 0 LE D LE C_D D U LE C_D TY_ D U C LE C_D TY_ HN DC U C G_ LE _D TY_ HN EN D U C G_ D_ LE C_D TY_ HN EN LS DC U C G_ D_ CH LE _D TY_ HN EN LS 7_ D U C G_ D_ CH IN LE C_D TY_ HN EN LS 6_ T_C D U C G_ D_ CH IN L LE C_D TY_ HN EN LS 5_ T_C R D U C G_ D_ CH IN L LE C_D TY_ HN EN LS 4_ T_C R D U C G_ D_ CH IN L LE C_D TY_ HN EN LS 3_ T_C R DC U C G_ D_ CH IN LR LE _D TY_ HN EN LS 2_ T_C D U C G_ D_ CH IN L LE C_D TY_ HN EN LS 1_ T_C R D U C G_ D_ CH IN L LE C_D TY_ HN EN HS 0_ T_C R D U C G _ D_ C IN L LE C_D TY_ HN EN HS H7_ T_C R D U C G_ D_ C IN L LE C_D TY_ HN EN HS H6_ T_C R D U C G_ D_ C IN L LE C_D TY_ HN EN HS H5_ T_C R D U C G_ D_ C IN L LE C_L TY_ HN EN HS H4_ T_C R DC ST C G_ D_ CH IN L LE _L IM HN EN HS 3_ T_C R D S ER G_ D_ C IN L LE C_L TIM 3_ EN HS H2_ T_C R D S ER OV D_ C IN L LE C_L TIM 2_ F_ HS H1_ T_C R D S ER OV INT C IN L LE C_H TIM 1_ F_ _C H0_ T_C R D S ER OV INT LR IN L T_ R LE C_H TIM 0_ F_ _C CL DC S ER OV INT LR R LE _H TIM 3_ F_ _C I DC S ER OV NT LR T _ _H IM 2_ F_ C ST ER OV INT LR IM 1_ F_ _C ER OV IN LR 0_ F_ T_C O IN L VF T_ R _I C NT LR _C LR ) rv ed se (re LE D LE C_D D U LE C_D TY_ DC U C LE _D TY_ HN D U C G_ LE C_D TY_ HN EN D U C G_ D_ LE C_D TY_ HN EN LS DC U C G_ D_ CH LE _D TY_ HN EN LS 7_ D U C G_ D_ CH IN LE C_D TY_ HN EN LS 6_ T_E D U C G_ D_ CH IN N LE C_D TY_ HN EN LS 5_ T_E A D U C G_ D_ CH IN N LE C_D TY_ HN EN LS 4_ T_E A D U C G_ D_ CH IN N LE C_D TY_ HN EN LS 3_ T_E A DC U C G_ D_ CH IN NA LE _D TY_ HN EN LS 2_ T_E D U C G_ D_ CH IN N LE C_D TY_ HN EN LS 1_ T_E A D U C G_ D_ CH IN N LE C_D TY_ HN EN HS 0_ T_E A D U C G _ D _ C IN N LE C_D TY_ HN EN HS H7_ T_E A D U C G_ D_ C IN N LE C_D TY_ HN EN HS H6_ T_E A D U C G_ D_ C IN N LE C_D TY_ HN EN HS H5_ T_E A D U C G_ D_ C IN N LE C_L TY_ HN EN HS H4_ T_E A D S C G_ D_ C IN N LE C_L TIM HN EN HS H3_ T_E A D S ER G_ D_ C IN N LE C_L TIM 3_ EN HS H2_ T_E A D S ER OV D_ C IN N LE C_L TIM 2_ F_ HS H1_ T_E A D S ER OV INT C IN N LE C_H TIM 1_ F_ _E H0_ T_E A D S ER OV INT NA IN N T_ A LE C_H TIM 0_ F_ _E EN DC S ER OV INT NA A LE _H TIM 3_ F_ _E I DC S ER OV NT NA T _ _H IM 2_ F_ E ST ER OV INT NA IM 1_ F_ _E ER OV IN NA 0_ F_ T_E O IN N VF T_ A _I EN NT A _E NA ) ed rv se (re 11. LED_PWM Register 11.17: LEDC_INT_ENA_REG (0x0188) 31 0 31 0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset LEDC_DUTY_CHNG_END_LSCHn_INT_ENA The interrupt LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (R/W) LEDC_DUTY_CHNG_END_HSCHn_INT_ENA The LEDC_DUTY_CHNG_END_LSCHn_INT_CLR Set LEDC_DUTY_CHNG_END_HSCHn_INT_CLR Set 275 interrupt this this enable bit for the enable bit for the LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (R/W) LEDC_LSTIMERx_OVF_INT_ENA The interrupt enable bit for the LEDC_LSTIMERx_OVF_INT interrupt. (R/W) LEDC_HSTIMERx_OVF_INT_ENA The interrupt enable bit for the LEDC_HSTIMERx_OVF_INT interrupt. (R/W) Register 11.18: LEDC_INT_CLR_REG (0x018C) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (WO) bit to clear the bit to clear the LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (WO) LEDC_LSTIMERx_OVF_INT_CLR Set this bit to clear the LEDC_LSTIMERx_OVF_INT interrupt. (WO) LEDC_HSTIMERx_OVF_INT_CLR Set this bit to clear the LEDC_HSTIMERx_OVF_INT interrupt. (WO) ESP32 Technical Reference Manual V2.0 11. LED_PWM (re s LE D er ve C_ A d) PB _C L K_ SE L Register 11.19: LEDC_CONF_REG (0x0190) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset LEDC_APB_CLK_SEL This bit is used to set the frequency of SLOW_CLK. (R/W) 0: 8 MHz; 1: 80 MHz. Espressif Systems 276 ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL 12. Remote Controller Peripheral 12.1 Introduction The RMT (Remote Control) module is primarily designed to send and receive infrared remote control signals that use on-off-keying of a carrier frequency, but due to its design it can be used to generate various types of signals. An RMT transmitter does this by reading consecutive duration values for an active and inactive output from the built-in RAM block, optionally modulating it with a carrier wave. A receiver will inspect its input signal, optionally filtering it, and will place the lengths of time the signal is active and inactive in the RAM block. The RMT module has eight channels, numbered zero to seven; registers, signals and blocks that are duplicated in each channel are indicated by an n which is used as a placeholder for the channel number. 12.2 Functional Description 12.2.1 RMT Architecture Figure 73: RMT Architecture The RMT module contains eight channels; each channel has a transmitter and receiver, of which one can be active per channel. The eight channels share a 512x32-bit RAM block which can be read and written by the processor cores over the APB bus, read by the transmitters, and written by the receivers. The transmitted signal can optionally be modulated by a carrier wave. Each channel is clocked by a divided-down signal derived from either the APB bus clock or REF_TICK. Espressif Systems 277 ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL 12.2.2 RMT RAM Figure 74: Data Structure The data structure in RAM is shown in Figure 74. Each 32-bit value contains two 16-bit entries, containing two fields each: ”level” indicates whether a high-/low-level value was received or is going to be sent, and ”period” is the duration (in channel clock periods) for which the level lasts. A zero period is interpreted as an end-marker: the transmitter will stop transmitting once it has read this, and the receiver will write this, once it has detected that the signal it received has gone idle. Normally, only one block of 64x32-bit worth of data can be sent or received. If the data size is larger than this block size, blocks can either be extended or the channel can be configured for wraparound mode. The RMT RAM can be accessed via APB bus. The initial address is RMT base address + 0x800. The RAM block is divided into eight 64x32-bit blocks. By default, each channel uses one block (block zero for channel zero, block one for channel one, and so on). Users can extend the memory for a specific channel by configuring RMT_MEM_SIZE_CHn register; setting this to >1 will prompt the channel to use the memory of subsequent channels as well. The RAM address range for channel n is start_addr_CHn to end_addr_CHn, which are defined by: start_addr_chn = RMT base address + 0x800 + 64 ∗ 4 ∗ n, and end_addr_chn = RMT base address + 0x800 + �64 ∗ 4 ∗ n + 64 ∗ 4 ∗ RMT_MEM_SIZE_CHn�mod�512 ∗ 4� To protect a receiver from overwriting the blocks a transmitter is about to transmit, RMT_MEM_OWNER_CHn can be configured to assign the owner, i.e. transmitter or receiver, of channel n’s RAM block. If this ownership is violated, the RMT_CHn_ERR interrupt will be generated. 12.2.3 Clock The main clock for a channel is generated by taking either the 80 MHz APB clock or REF_TICK (usually 1MHz), according to the state of RMT_REF_ALWAYS_ON_CHn. (For more information on the clock sources, please see Chapter Reset And Clock.) Then, the aforementioned state gets scaled down using a configurable 8-bit divider to create the channel clock which is used by both the carrier wave generator and the counter. The divider value can be set by configuring RMT_DIV_CNT_CHn. 12.2.4 Transmitter When the RMT_TX_START_CHn register is 1, the transmitter of channel n will start reading data from RAM and sending it. The transmitter will receive a 32-bits value each time it reads from RAM. Of these 32 bits, the low 16-bit entry is sent first and the high entry second. To transmit more data than can be fitted in the channel’s RAM, wraparound mode can be enabled. In this mode, when the transmitter has reached the last entry in the channel’s memory, it will loop back to the first byte. To use this mechanism to send more data than can be fitted in the channel’s RAM, fill the RAM with the initial events and Espressif Systems 278 ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL set RMT_CHn_TX_LIM_REG to cause an RMT_CHn_TX_THR_EVENT_INT interrupt before the wraparound happens. Then, when the interrupt happens, the already sent data should be replaced by subsequent events: when the wraparound happens the transmitter will seamlessly continue sending the new events. With or without wraparound mode enabled, transmission ends when an entry with zero length is encountered. When this happens, the transmitter will generate a RMT_CHn_TX_END_INT interrupt, and return to the idle state. When a transmitter is in the idle state, users can configure RMT_IDLE_OUT_EN_CHn and RMT_IDLE_OUT_LV_CHn to control the transmitter output manually. The output of the transmitter can be modulated using a carrier wave by setting RMT_CARRIER_EN_CHn. The carrier frequency and duty cycle can be configured by adjusting its high and low durations in channel clock cycles, in RMT_CARRIER_HIGH_CHn and RMT_CARRIER_HIGH_CHn. 12.2.5 Receiver When RMT_RX_EN_CHn is set to 1, the receiver in channel n becomes active, measuring the duration between input signal edges. These will be written as period/level value pairs to the channel RAM in the same fashion as the transmitter sends them. Receiving ends when the receiver detects no change in signal level for more than RMT_IDLE_THRES_CHn channel clock ticks; the receiver will write a final entry with 0 period, generate an RMT_CHn_RX_END_INT_RAW interrupt, and return to the idle state. The receiver has an input signal filter which can be configured using RMT_RX_FILTER_EN_CHn: The filter will remove pulses with a length of less than RMT_RX_FILTER_THRES_CHn in APB clock periods. When the RMT module is inactive, the RAM can be put into low-power mode by setting the RMT_MEM_PD register to 1. 12.2.6 Interrupts • RMT_CHn_TX_THR_EVENT_INT: Triggered when the number of events the transmitter has sent matches the contents of the RMT_CHn_TX_LIM_REG register. • RMT_CHn_TX_END_INT: Triggered when the transmitter has finished transmitting the signal. • RMT_CHn_RX_END_INT: Triggered when the receiver has finished receiving a signal. 12.3 Register Summary Name Description Address Access RMT_CH0CONF0_REG Channel 0 config register 0 0x3FF56020 R/W RMT_CH0CONF1_REG Channel 0 config register 1 0x3FF56024 R/W RMT_CH1CONF0_REG Channel 1 config register 0 0x3FF56028 R/W RMT_CH1CONF1_REG Channel 1 config register 1 0x3FF5602C R/W RMT_CH2CONF0_REG Channel 2 config register 0 0x3FF56030 R/W RMT_CH2CONF1_REG Channel 2 config register 1 0x3FF56034 R/W RMT_CH3CONF0_REG Channel 3 config register 0 0x3FF56038 R/W RMT_CH3CONF1_REG Channel 3 config register 1 0x3FF5603C R/W RMT_CH4CONF0_REG Channel 4 config register 0 0x3FF56040 R/W Configuration registers Espressif Systems 279 ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL RMT_CH4CONF1_REG Channel 4 config register 1 0x3FF56044 R/W RMT_CH5CONF0_REG Channel 5 config register 0 0x3FF56048 R/W RMT_CH5CONF1_REG Channel 5 config register 1 0x3FF5604C R/W RMT_CH6CONF0_REG Channel 6 config register 0 0x3FF56050 R/W RMT_CH6CONF1_REG Channel 6 config register 1 0x3FF56054 R/W RMT_CH7CONF0_REG Channel 7 config register 0 0x3FF56058 R/W RMT_CH7CONF1_REG Channel 7 config register 1 0x3FF5605C R/W RMT_INT_RAW_REG Raw interrupt status 0x3FF560A0 RO RMT_INT_ST_REG Masked interrupt status 0x3FF560A4 RO RMT_INT_ENA_REG Interrupt enable bits 0x3FF560A8 R/W RMT_INT_CLR_REG Interrupt clear bits 0x3FF560AC WO RMT_CH0CARRIER_DUTY_REG Channel 0 duty cycle configuration register 0x3FF560B0 R/W RMT_CH1CARRIER_DUTY_REG Channel 1 duty cycle configuration register 0x3FF560B4 R/W RMT_CH2CARRIER_DUTY_REG Channel 2 duty cycle configuration register 0x3FF560B8 R/W RMT_CH3CARRIER_DUTY_REG Channel 3 duty cycle configuration register 0x3FF560BC R/W RMT_CH4CARRIER_DUTY_REG Channel 4 duty cycle configuration register 0x3FF560C0 R/W RMT_CH5CARRIER_DUTY_REG Channel 5 duty cycle configuration register 0x3FF560C4 R/W RMT_CH6CARRIER_DUTY_REG Channel 6 duty cycle configuration register 0x3FF560C8 R/W RMT_CH7CARRIER_DUTY_REG Channel 7 duty cycle configuration register 0x3FF560CC R/W RMT_CH0_TX_LIM_REG Channel 0 Tx event configuration register 0x3FF560D0 R/W RMT_CH1_TX_LIM_REG Channel 1 Tx event configuration register 0x3FF560D4 R/W RMT_CH2_TX_LIM_REG Channel 2 Tx event configuration register 0x3FF560D8 R/W RMT_CH3_TX_LIM_REG Channel 3 Tx event configuration register 0x3FF560DC R/W RMT_CH4_TX_LIM_REG Channel 4 Tx event configuration register 0x3FF560E0 R/W RMT_CH5_TX_LIM_REG Channel 5 Tx event configuration register 0x3FF560E4 R/W RMT_CH6_TX_LIM_REG Channel 6 Tx event configuration register 0x3FF560E8 R/W RMT_CH7_TX_LIM_REG Channel 7 Tx event configuration register 0x3FF560EC R/W RMT-wide configuration register 0x3FF560F0 R/W Interrupt registers Carrier wave duty cycle registers Tx event configuration registers Other registers RMT_APB_CONF_REG Espressif Systems 280 ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL 12.4 Registers 31 30 29 28 0x0 0 1 1 27 24 0x01 CH n S_ CH n _C NT _ _T HR E T_ DI V T_ ID LE 23 RM RM (re se RM rve T d) RM _M T EM RM _C _P T_ ARR D CA IE RR R_ IE OU R_ T RM EN _LV T_ _C _C M EM Hn Hn _S IZ E_ CH n Register 12.1: RMT_CHnCONF0_REG (n: 0-7) (0x0058+8*n) 8 7 0x01000 0 0x002 RMT_MEM_PD This bit is used to power down the entire RMT RAM block. Reset (It only exists in RMT_CH0CONF0). 1: power down memory; 0: power up memory. (R/W) RMT_CARRIER_OUT_LV_CHn This bit is used for configuration when the carrier wave is being transmitted. Transmit on low output level with 1, and transmit on high output level with 0. (R/W) RMT_CARRIER_EN_CHn This is the carrier modulation enable control bit for channeln. Carrier modulation is enabled with 1, while carrier modulation is disabled with 0. (R/W) RMT_MEM_SIZE_CHn This register is used to configure the amount of memory blocks allocated to channel n (R/W) RMT_IDLE_THRES_CHn In receive mode, when no edge is detected on the input signal for longer than reg_idle_thres_chn channel clock cycles, the receive process is finished. (R/W) RMT_DIV_CNT_CHn This register is used to set the divider for the channel clock of channel n. (R/W) Espressif Systems 281 ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL 31 RM (re s er ve d) T RM _ID T LE RM _ID _O T LE UT RM _R _O _E T_ EF_ UT N_C RE AL _LV H F_ WA _C n CN Y H T_ S_O n RS N T_ _C CH Hn RM n T_ RX _F ILT ER _T HR ES RM _C Hn T_ RM R X T _ RM _TX FILT T_ _C ER (re M O _E se EM NT N RM rve _O I_M _CH T d) WN OD n RM _M ER E_ T EM _C CH RM _M _R Hn n E D T M RM _R _W _RS T_ X_E R_ T_ TX N_ RS CH _ S C H T_ n TA n C Hn RT _C Hn Register 12.2: RMT_CHnCONF1_REG (n: 0-7) (0x005c+8*n) 20 0x0000 19 18 17 16 0 0 0 0 15 8 0x00F 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 Reset RMT_IDLE_OUT_EN_CHn This is the output enable control bit for channel n in IDLE state. (R/W) RMT_IDLE_OUT_LV_CHn This bit configures the output signals level for channel n in IDLE state. (R/W) RMT_REF_ALWAYS_ON_CHn This bit is used to select the channel’s base clock. 1:clk_apb; 0:clk_ref. (R/W) RMT_REF_CNT_RST_CHn Setting this bit resets the clock divider of channel n. (R/W) RMT_RX_FILTER_THRES_CHn In receive mode, channel n ignores input pulse when the pulse width is smaller than this value in APB clock periods. (R/W) RMT_RX_FILTER_EN_CHn This is the receive filter enable bit for channel n. (R/W) RMT_TX_CONTI_MODE_CHn If this bit is set, instead of going to idle when the transmission ends, the transmitter will restart transmission. This results in a repeating output signal. (R/W) RMT_MEM_OWNER_CHn This bit marks channel n’s RAM block ownership. Number 1 stands for the receiver using the RAM, while 0 stands for the transmitter using the RAM. (R/W) RMT_MEM_RD_RST_CHn Set this bit to reset read RAM address for channel n by transmitter access. (R/W) RMT_MEM_WR_RST_CHn Set this bit to reset write RAM address for channel n by receiver access. (R/W) RMT_RX_EN_CHn Set this bit to enable receiving data on channel n. (R/W) RMT_TX_START_CHn Set this bit to start sending data on channel n. (R/W) Espressif Systems 282 ESP32 Technical Reference Manual V2.0 RM C T H7 RM _C _T X T H6 _ RM _C _T THR X T H5 _ _ RM _C _T THR EVE X_ _ N H T 4 RM _C _T THR EVE T_IN X T_ H3_ _T _E NT T_ RM C T HR VE _IN ST X T H2 _ _ N T RM _C _T THR EVE T_IN _ST X_ _ N T H T 1 RM _C _T THR EVE T_IN _ST X T H0 _ _ N T RM _C _T THR EVE T_IN _ST X H T 7 _ _ N T RM _C _E THR EVE T_IN _ST R T H7 R _ N T RM _C _R _IN EVE T_IN _ST H T 7 X_ T_ N T RM _C _T EN ST T_IN _ST X D T_ T H6 _ _ RM _C _E END INT ST RR _ _ H T 6 S RM _C _R _IN INT T T H6 X_ T_ _S RM _C _T EN ST T X D T H5 _ _ RM _C _E END INT R H T 5 R _ _S RM _C _R _IN INT T T H5 X_ T_ _S RM _C _T EN ST T X D T H4 _ _ RM _C _E END INT R H T 4 R _ _S RM _C _R _IN INT T T H4 X_ T_ _S RM _C _T EN ST T X D T H3 _ _ RM _C _E END INT R T H3 R _ _S RM _C _R _IN INT T H T 3 X_ T_ _S RM _C _T EN ST T X D T H2 _ _ RM _C _E END INT R T H2 R _ _S RM _C _R _IN INT T H T 2 X_ T_ _S RM _C _T EN ST T X D T H1 _ _ RM _C _E END INT R H T 1 R _ _S RM _C _R _IN INT T T H1 X_ T_ _S RM _C _T EN ST T X D T H0 _ _ RM _C _E END INT R H T_ 0_ R_ _IN _ST CH RX IN T 0_ _E T_S _ST TX ND T _E _I ND NT _I _S NT T _S T T_ RM T RM _C T H7 RM _C _T X T H6 _ RM _C _T THR X T H5 _ _ RM _C _T THR EVE X_ _ N H T 4 RM _C _T THR EVE T_IN X T H3 _ _ N T RM _C _T THR EVE T_IN _RA X T H2 _ _ N T W RM _C _T THR EVE T_IN _RA X H T 1 _ _ N T W RM _C _T THR EVE T_IN _RA X T H0 _ _ N T W RM _C _T THR EVE T_IN _RA X_ _ N T W H T 7 RM _C _E THR EVE T_IN _RA R T H7 R _ N T W RM _C _R _IN EVE T_IN _RA H T 7 X_ T_ N T W RM _C _T EN RA T_IN _RA X D T H 6 _ _ W T_ W RM _C _E END INT RA R W T H6 R _ _R RM _C _R _IN INT AW T_ H6_ X_E T_R _RA RM C T N A W X D T H5 _ _ W RM _C _E END INT R H T 5 R _ _R RM _C _R _IN INT AW T H5 X_ T_ _R RM _C _T EN RA AW X D T H4 _ _ W RM _C _E END INT R H T 4 R _ _R RM _C _R _IN INT AW T H4 X_ T_ _R RM _C _T EN RA AW X D T H3 _ _ W RM _C _E END INT R T H3 R _ _R RM _C _R _IN INT AW H T 3 X_ T_ _R RM _C _T EN RA AW X D T H2 _ _ W RM _C _E END INT R T H2 R _ _R RM _C _R _IN INT AW H T 2 X_ T_ _R RM _C _T EN RA AW X D T H1 _ _ W RM _C _E END INT R H T 1 R _ _R RM _C _R _IN INT AW T H1 X_ T_ _R RM _C _T EN RA AW X D T H0 _ _ W RM _C _E END INT R H T_ 0_ R_ _IN _RA CH RX IN T W 0_ _E T_R _RA TX ND A W _E _I W ND NT _ I _R NT A _R W AW RM 12. REMOTE CONTROLLER PERIPHERAL Register 12.3: RMT_INT_RAW_REG (0x00a0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RMT_CHn_TX_THR_EVENT_INT_RAW The RMT_CHn_TX_THR_EVENT_INT_ST The Espressif Systems raw 283 interrupt masked status interrupt status bit bit for for the RMT_CHn_TX_THR_EVENT_INT interrupt. (RO) RMT_CHn_ERR_INT_RAW The raw interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO) RMT_CHn_RX_END_INT_RAW The raw interrupt status bit for the RMT_CHn_RX_END_INT interrupt. (RO) RMT_CHn_TX_END_INT_RAW The raw interrupt status bit for the RMT_CHn_TX_END_INT interrupt. (RO) Register 12.4: RMT_INT_ST_REG (0x00a4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset the RMT_CHn_TX_THR_EVENT_INT interrupt. (RO) RMT_CHn_ERR_INT_ST The masked interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO) RMT_CHn_RX_END_INT_ST The masked interrupt status bit for the RMT_CHn_RX_END_INT inter- rupt. (RO) RMT_CHn_TX_END_INT_ST The masked interrupt status bit for the RMT_CHn_TX_END_INT inter- rupt. (RO) ESP32 Technical Reference Manual V2.0 RM C T H7 RM _C _T X T H6 _ RM _C _T THR X T H5 _ _ RM _C _T THR EVE X H T 4 _ _ N RM _C _T THR EVE T_IN X T H3 _ _ N T RM _C _T THR EVE T_IN _C X L T H2 _ _ N T R RM _C _T THR EVE T_IN _C X_ _ N T LR H T 1 RM _C _T THR EVE T_IN _C X L T H0 _ _ N T R RM _C _T THR EVE T_IN _C X_ _ N T LR H T 7 RM _C _E THR EVE T_IN _C L R T H7 R _ N T R RM _C _R _IN EVE T_IN _C L T H7 X_ T_ N T R RM _C _T EN CL T_IN _C X_ D R H T_ LR _ T 6 RM _C _E END INT CL R R T H6 R _ _C RM _C _R _IN INT LR T_ H6_ X_E T_C _CL RM C T N L R X D T H5 _ _ R RM _C _E END INT R H T 5 R _ _C RM _C _R _IN INT LR T H5 X_ T_ _C RM _C _T EN CL LR X D T H4 _ _ R RM _C _E END INT R H T 4 R _ _C RM _C _R _IN INT LR T H4 X_ T_ _C RM _C _T EN CL LR X D T H3 _ _ R RM _C _E END INT R T H3 R _ _C RM _C _R _IN INT LR H T 3 X_ T_ _C RM _C _T EN CL LR X D T H2 _ _ R RM _C _E END INT R T H2 R _ _C RM _C _R _IN INT LR H T 2 X_ T_ _C RM _C _T EN CL LR X D T H1 _ _ R RM _C _E END INT R H T 1 R _ _C RM _C _R _IN INT LR T H1 X_ T_ _C RM _C _T EN CL LR X D T H0 _ _ R RM _C _E END INT R H T_ 0_ R_ _IN _C CH RX IN T LR 0_ _E T_C _CL TX ND L R _E _I R ND NT _I _C NT LR _C LR T_ RM T RM _C T H7 RM _C _T X T H6 _ RM _C _T THR X T H5 _ _ RM _C _T THR EVE X_ _ N H T 4 RM _C _T THR EVE T_IN X T H3 _ _ N T RM _C _T THR EVE T_IN _EN X T H2 _ _ N T A RM _C _T THR EVE T_IN _EN X H T 1 _ _ N T A RM _C _T THR EVE T_IN _EN X T H0 _ _ N T A RM _C _T THR EVE T_IN _EN X_ _ N T A H T 7 RM _C _E THR EVE T_IN _EN R T H7 R _ N T A RM _C _R _IN EVE T_IN _EN H T 7 X_ T_ N T A RM _C _T EN EN T_IN _EN X D T_ A T H6 _ _ A RM _C _E END INT EN RR _ _ H A T 6 E RM _C _R _IN INT NA T_ H6_ X_E T_E _EN RM C T N N A X D T H5 _ _ A RM _C _E END INT R H T 5 R _ _E RM _C _R _IN INT NA T H5 X_ T_ _E RM _C _T EN EN NA X D T H4 _ _ A RM _C _E END INT R H T 4 R _ _E RM _C _R _IN INT NA T H4 X_ T_ _E RM _C _T EN EN NA X D T H3 _ _ A RM _C _E END INT R T H3 R _ _E RM _C _R _IN INT NA H T 3 X_ T_ _E RM _C _T EN EN NA X D T H2 _ _ A RM _C _E END INT R T H2 R _ _E RM _C _R _IN INT NA H T 2 X_ T_ _E RM _C _T EN EN NA X D T H1 _ _ A RM _C _E END INT R H T 1 R _ _E RM _C _R _IN INT NA T H1 X_ T_ _E RM _C _T EN EN NA X D T H0 _ _ A RM _C _E END INT R H T_ 0_ R_ _IN _EN CH RX IN T A 0_ _E T_E _EN TX ND N A _ E _I A ND NT _I _E NT N _E A NA RM 12. REMOTE CONTROLLER PERIPHERAL Register 12.5: RMT_INT_ENA_REG (0x00a8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RMT_CHn_TX_THR_EVENT_INT_ENA The Espressif Systems interrupt 284 enable bit for the RMT_CHn_TX_THR_EVENT_INT interrupt. (R/W) RMT_CHn_ERR_INT_ENA The interrupt enable bit for the RMT_CHn_ERROR_INT interrupt. (R/W) RMT_CHn_RX_END_INT_ENA The interrupt enable bit for the RMT_CHn_RX_END_INT interrupt. (R/W) RMT_CHn_TX_END_INT_ENA The interrupt enable bit for the RMT_CHn_TX_END_INT interrupt. (R/W) Register 12.6: RMT_INT_CLR_REG (0x00ac) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RMT_CHn_TX_THR_EVENT_INT_CLR Set this bit to clear the RMT_CHn_TX_THR_EVENT_INT in- terrupt. (WO) RMT_CHn_ERR_INT_CLR Set this bit to clear the RMT_CHn_ERRINT interrupt. (WO) RMT_CHn_RX_END_INT_CLR Set this bit to clear the RMT_CHn_RX_END_INT interrupt. (WO) RMT_CHn_TX_END_INT_CLR Set this bit to clear the RMT_CHn_TX_END_INT interrupt. (WO) ESP32 Technical Reference Manual V2.0 12. REMOTE CONTROLLER PERIPHERAL RM RM T_ CA T_ CA RR IE RR IE R_ L R_ H IG H_ O W _C Hn CH n Register 12.7: RMT_CHnCARRIER_DUTY_REG (n: 0-7) (0x00cc+4*n) 31 16 15 0 0x00040 0x00040 Reset RMT_CARRIER_HIGH_CHn This field is used to configure the carrier wave high-level duration (in channel clock periods) for channel n. (R/W) RMT_CARRIER_LOW_CHn This field is used to configure the carrier wave low-level duration (in channel clock periods) for channel n. (R/W) RM (re se r T_ ve d) TX _L IM _C Hn Register 12.8: RMT_CHn_TX_LIM_REG (n: 0-7) (0x00ec+4*n) 31 9 8 0x000000 0 0x080 Reset RMT_TX_LIM_CHn When channel n sends more entries than specified here, it produces a TX_THR_EVENT interrupt. (R/W) (re RM se T_ M rv e d) EM _T X_ W RA P_ EN Register 12.9: RMT_APB_CONF_REG (0x00f0) 31 2 0x00000000 1 0 Reset RMT_MEM_TX_WRAP_EN bit enables wraparound mode: when the transmitter of a channel has reached the end of its memory block, it will resume sending at the start of its memory region. (R/W) Espressif Systems 285 ESP32 Technical Reference Manual V2.0 13. MCPWM 13. MCPWM 13.1 Introduction The Motor Control Pulse Width Modulator (MCPWM) peripheral is intended for motor and power control. It provides six PWM outputs that can be set up to operate in several topologies. One common topology uses a pair of PWM outputs driving an H-bridge to control motor rotation speed and rotation direction. The timing and control resources inside are allocated into two major types of submodules: PWM timers and PWM operators. Each PWM timer provides timing references that can either run freely or be synced to other timers or external sources. Each PWM operator has all necessary control resources to generate waveform pairs for one PWM channel. The MCPWM peripheral also contains a dedicated capture submodule that is used in systems where accurate timing of external events is important. ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1. Their control registers are located in 4-KB memory blocks starting at memory locations 0x3FF5E000 and 0x3FF6C000 respectively. 13.2 Features Each MCPWM peripheral has one clock divider (prescaler), three PWM timers, three PWM operators, and a capture module. Figure 75 shows the submodules inside and the signals on the interface. PWM timers are used for generating timing references. The PWM operators generate desired waveform based on the timing references. Any PWM operator can be configured to use the timing references of any PWM timers. Different PWM operators can use the same PWM timer’s timing references to produce related PWM signals. PWM operators can also use different PWM timers’ values to produce the PWM signals that work alone. Different PWM timers can also be synced together. Figure 75: MCPWM Module Overview An overview of the submodules’ function in Figure 75 is shown below: Espressif Systems 286 ESP32 Technical Reference Manual V2.0 13. MCPWM • PWM Timers 0, 1 and 2 – Every PWM timer has a dedicated 8-bit clock prescaler. – The 16-bit counter in the PWM timer can work in count-up mode, count-down mode or count-up-down mode. – A hardware sync can trigger a reload on the PWM timer with a phase register. It will also trigger the prescaler’ restart, so that the timer’s clock can also be synced. The source of the sync can come from any GPIO or any other PWM timer’s sync_out. • PWM Operators 0, 1 and 2 – Every PWM operator has two PWM outputs: PWMxA and PWMxB. They can work independently, in symmetric and asymmetric configuration. – Software, asynchronous override control of PWM signals. – Configurable dead-time on rising and falling edges; each set up independently. – All events can trigger CPU interrupts. – Modulating of PWM output by high-frequency carrier signals, useful when gate drives are insulated with a transformer. – Period, time stamps and important control registers have shadow registers with flexible updating methods. • Fault Detection Module – Programmable fault handling allocated on fault condition in both cycle-by-cycle mode and one-shot mode. – A fault condition can force the PWM output to either high or low logic levels. • Capture Module – Speed measurement of rotating machinery (for example, toothed sprockets sensed with Hall sensors) – Measurement of elapsed time between position sensor pulses – Period and duty-cycle measurement of pulse train signals – Decoding current or voltage amplitude derived from duty-cycle-encoded signals from current/voltage sensors – Three individual capture channels, each of which has a time-stamp register (32 bits) – Selection of edge polarity and prescaling of input capture signal – The capture timer can sync with a PWM timer or external signals. – Interrupt on each of the three capture channels Espressif Systems 287 ESP32 Technical Reference Manual V2.0 13. MCPWM 13.3 Submodules 13.3.1 Overview This section lists the configuration parameters of key submodules. For information on adjusting a specific parameter, e.g. synchronization source of PWM timer, please refer to Section 13.3.2 for details. 13.3.1.1 Prescaler Submodule Figure 76: Prescaler Submodule Configuration parameter: • Scale the PWM clock according to CLK_160M. 13.3.1.2 Timer Submodule Figure 77: Timer Submodule Configuration parameters: • Set the PWM timer frequency or period. • Configure the working mode for the timer: – Count-Up Mode: for asymmetric PWM outputs – Count-Down Mode: for asymmetric PWM outputs – Count-Up-Down Mode: for symmetric PWM outputs • Configure the the reloading phase (including the value and the phase) used during software and hardware synchronization. Espressif Systems 288 ESP32 Technical Reference Manual V2.0 13. MCPWM • Synchronize the PWM timers with each other. Either hardware or software synchronization may be used. • Configure the source of the PWM timer’s the synchronization input to one of the seven sources below: – The three PWM timer’s synchronization outputs. – Three synchronization signals from the GPIO matrix: SYNC0, SYNC1, SYNC2. – No synchronization input signal selected • Configure the source of the PWM timer’s synchronization output to one of the four sources below: – Synchronization input signal – Event generated when value of the PWM timer is equal to zero – Event generated when value of the PWM timer is equal to period – No synchronization output generated • Configure the method of period updating. 13.3.1.3 Operator Submodule Figure 78: Operator Submodule The configuration parameters of the operator submodule are shown in Table 48. Espressif Systems 289 ESP32 Technical Reference Manual V2.0 13. MCPWM Table 48: Configuration Parameters of the Operator Submodule Submodule PWM Generator Configuration Parameter or Option • Set up the PWM duty cycle for PWMxA and/or PWMxB output. • Set up at which time the timing events occur. • Define what action should be taken on timing events: – Switch high or low PWMxA and/or PWMxB outputs – Toggle PWMxA and/or PWMxB outputs – Take no action on outputs • Use direct s/w control to force the state of PWM outputs • Add a dead time to raising and / or failing edge on PWM outputs. • Configure update method for this submodule. Dead Time Generator • Control of complementary dead time relationship between upper and lower switches. • Specify the dead time on rising edge. • Specify the dead time on falling edge. • Bypass the dead time generator module. The PWM waveform will pass through without inserting dead time. • Allow PWMxB phase shifting with respect to the PWMxA output. • Configure updating method for this submodule. PWM Carrier • Enable carrier and set up carrier frequency. • Configure duration of the first pulse in the carrier waveform. • Set up the duty cycle of the following pulses. • Bypass the PWM carrier module. The PWM waveform will be passed through without modification. Fault Handler • Configure if and how the PWM module should react the fault event signals. • Specify the action taken when a fault event occurs: – Force PWMxA and/or PWMxB high. – Force PWMxA and/or PWMxB low. – Configure PWMxA and/or PWMxB to ignore any fault event. • Configure how often the PWM should react to fault events: – One-shot – Cycle-by-cycle • Generate interrupts. • Bypass the fault handler submodule entirely. • Set up an option for cycle-by-cycle actions clearing. • If desired, independently-configured actions can be taken when time-base counter is counting down or up. Espressif Systems 290 ESP32 Technical Reference Manual V2.0 13. MCPWM 13.3.1.4 Fault Detection Submodule Figure 79: Fault Detection Submodule Configuration parameters: • Enable fault event generation and configure the polarity of fault event generation for every fault signal • Generate fault event interrupts 13.3.1.5 Capture Submodule Figure 80: Capture Submodule Configuration parameters: • Select the edge polarity and prescaling of the capture input. • Set up a software-triggered capture. • Configure the capture timer’s sync trigger and sync phase. • Software syncs the capture timer. 13.3.2 PWM Timer Submodule Each MCPWM module has three PWM timer submodules. Any of them can determine the necessary event timing for any of the three PWM operator submodules. Built-in synchronization logic allows multiple PWM timer submodules, in one or more MCPWM modules, to work together as a system, when using synchronization signals from the GPIO matrix. 13.3.2.1 Configurations of the PWM Timer Submodule Users can configure the following functions of the PWM timer submodule: • Control how often events occur by specifying the PWM timer frequency or period. Espressif Systems 291 ESP32 Technical Reference Manual V2.0 13. MCPWM • Configure a particular PWM timer to synchronize with other PWM timers or modules. • Get a PWM timer in phase with other PWM timers or modules. • Set one of the following timer counting modes: count-up, count-down, count-up-down. • Change the rate of the PWM timer clock (PT_clk) with a prescaler. Each timer has its own prescaler configured with PWM_TIMERx_PRESCALE of register PWM_TIMER0_CFG0_REG. The PWM timer increments or decrements at a slower pace, depending on the setting of this register. 13.3.2.2 PWM Timer’s Working Modes and Timing Event Generation The PWM timer has three working modes, selected by the PWMx timer mode register: • Count-Up Mode: In this mode, the PWM timer increments from zero until reaching the value configured in the period register. Once done, the PWM timer returns to zero and starts increasing again. PWM period is equal to the period value configured in register. • Count-Down Mode: The PWM timer decrements to zero, starting from the value configured in the period register. After reaching zero, it is set back to the period value. Then it starts to decrement again. In this case, the PWM period is also equal to the value configured in the period register. • Count-Up-Down Mode: This is a combination of the two modes mentioned above. The PWM timer starts increasing from zero until the period value is reached. Then, the timer decreases back to zero. This pattern is then repeated. The PWM period is the result of the value in the period register multiplied by 2. Figures 81 to 84 show PWM timer waveforms in different modes, including timer behavior during synchronization events. Figure 81: Count-Up Mode Waveform Espressif Systems 292 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 82: Count-Down Mode Waveforms Figure 83: Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event Figure 84: Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event Espressif Systems 293 ESP32 Technical Reference Manual V2.0 13. MCPWM When the PWM timer is running, it generates the following timing events periodically and automatically: • UTEP The timing event generated when the PWM timer’s value equals to the value of the period register (PWM_TIMERx_PERIOD) and when the PWM timer is increasing. • UTEZ The timing event generated when the PWM timer’s value equals to zero and when the PWM timer is increasing. • DTEP The timing event generated when the PWM timer’s value equals to the value of the period register (PWM_TIMERx_PERIOD) and when the PWM timer is decreasing. • DTEZ The timing event generated when the PWM timer’s value equals to zero and when the PWM timer is decreasing. Figures 85 to 87 show the timing waveforms of U/DTEP and U/DTEZ. Figure 85: UTEP and UTEZ Generation in Count-Up Mode Espressif Systems 294 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 86: DTEP and DTEZ Generation in Count-Down Mode Figure 87: DTEP and UTEZ Generation in Count-Up-Down Mode Espressif Systems 295 ESP32 Technical Reference Manual V2.0 13. MCPWM 13.3.2.3 PWM Timer Shadow Register The PWM timer’s period register and the PWM timer’s clock prescaler register have shadow registers. The purpose of a shadow register is to save a copy of the value to be written into the active register at a specific moment synchronized with the hardware. Both register types are defined as follows: • Active Register This register is directly responsible for controlling all actions performed by hardware. • Shadow Register It acts as a temporary buffer for a value to be written on the active register. Before this happens, the content of the shadow register has no direct effect on the controlled hardware. At a specific, user-configured point in time, the value saved in the shadow register is copied to the active register. This helps to prevent spurious operation of the hardware, which may happen when a register is asynchronously modified by software. Both the shadow register and the active register have the same memory address. The software always writes into, or reads from the shadow register. The moment of updating the active register is determined by its specific update method register. The update can start when the PWM timer is equal to zero, when the PWM timer is equal to period,at a synchronization moment, or immediately. Software can trigger a globally forced update which will prompt all registers in the module to be updated according to shadow registers. 13.3.2.4 PWM Timer Synchronization and Phase Locking The PWM modules adopt a flexible synchronization method. Each PWM timer has a synchronization input and a synchronization output. The synchronization input can be selected from three synchronization outputs and three synchronization signals from the GPIO matrix. The synchronization output can be generated from the synchronization input signal, or when the PWM timer’s value is equal to period or zero. Thus, the PWM timers can be chained together with their phase locked. During synchronization, the PWM timer clock prescaler will reset its counter in order to synchronize the PWM timer clock. 13.3.3 PWM Operator Submodule The PWM Operator submodule has the following functions: • Generates a PWM signal pair, based on timing references obtained from the corresponding PWM timer. • Each signal out of the PWM signal pair includes a specific pattern of dead time. • Superimposes a carrier on the PWM signal, if configured to do so. • Handles response under fault conditions. Figure 88 shows the block diagram of a PWM operator. Espressif Systems 296 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 88: Submodules Inside the PWM Operator 13.3.3.1 PWM Generator Submodule Purpose of the PWM Generator Submodule In this submodule, important timing events are generated or imported. The events are then converted into specific actions to generate the desired waveforms at the PWMxA and PWMxB outputs. The PWM generator submodule performs the following actions: • Generation of timing events based on time stamps configured using the A and B registers. Events happen when the following conditions are satisfied: – UTEA: the PWM timer is counting up and its value is equal to register A. – UTEB: the PWM timer is counting up and its value is equal to register B. – DTEA: the PWM timer is counting down and its value is equal to register A. – DTEB: the PWM timer is counting down and its value is equal to register B. • Generation of U/DT1, U/DT2 timing events based on fault or synchronization events. • Management of priority when these timing events occur concurrently. • Qualification and generation of set, clear and toggle actions, based on the timing events. • Controlling of the PWM duty cycle, depending on configuration of the PWM generator submodule. • Handling of new time stamp values, using shadow, registers to prevent glitches in the PWM cycle. PWM Operator Shadow Registers The time stamp registers A and B, as well as action configuration registers PWM_GENx_A_REG and PWM_GENx_B_REG are shadowed. Shadowing provides a way of updating registers in sync with the hardware. For a description of the shadow registers, please see 13.3.2.3. Espressif Systems 297 ESP32 Technical Reference Manual V2.0 13. MCPWM Timing Events For convenience, all timing signals and events are summarized in Table 49. Table 49: Timing Events Used in PWM Generator Signal Event Description PWM Timer Operation DTEP PWM timer value is equal to the period register value DTEZ PWM timer value is equal to zero DTEA PWM timer value is equal to A register DTEB PWM timer value is equal to B register DT0 event Based on fault or synchronization events DT1 event Based on fault or synchronization events UTEP PWM timer value is equal to the period register value UTEZ PWM timer value is equal to zero UTEA PWM timer value is equal to A register UTEB PWM timer value is equal to B register UT0 event Based on fault or synchronization events UT1 event Based on fault or synchronization events Software-force event Software-initiated asynchronous event PWM timer counts down. PWM timer counts up. N/A The purpose of a software-force event is to impose non-continuous or continuous changes on the PWMxA and PWMxB outputs. The change is done asynchronously. Software-force control is handled by the PWM_PWM_GENx_FORCE_REG registers. The selection and configuration of T0/T1 in the PWM generator submodule is independent of the configuration of fault events in the fault handler submodule. A particular trip event may or may not be configured to cause trip action in the fault handler submodule, but the same event can be used by the PWM generator to trigger T0/T1 for controlling PWM waveforms. It is important to know that when the PWM timer is in count-up-down mode, it will always decrement after a TEP event, and will always increment after a TEZ event. So when the PWM timer is in count-up-down mode, DTEP and UTEZ events will occur, while the events UTEP and DTEZ will never occur. The PWM generator can handle multiple events at the same time. Events are prioritized by the hardware and relevant details are provided in Table 50 and Table 51. Priority levels range from 1 (the highest) to 7 (the lowest). Please note that the priority of TEP and TEZ events depends on the PWM timer’s direction. If the value of A or B is set to be greater than the period, then U/DTEA and U/DTEB will never occur. Table 50: Timing Events Priority When PWM Timer Increments Priority Level Event 1 (highest) Software-force event 2 UTEP 3 UT0 4 UT1 5 UTEB 6 UTEA 7 (lowest) UTEZ Espressif Systems 298 ESP32 Technical Reference Manual V2.0 13. MCPWM Table 51: Timing Events Priority when PWM Timer Decrements Priority level Event 1 (highest) Software-force event 2 DTEZ 3 DT0 4 DT1 5 DTEB 6 DTEA 7 (lowest) DTEP Notes: 1. UTEP and UTEZ do not happen simultaneously. When the PWM timer is in count-up mode, UTEP will always happen one cycle earlier than UTEZ, as demonstrated in Figure 85, so their action on PWM signals will not interrupt each other. When the PWM timer is in count-up-down mode, UTEP will not occur. 2. DTEP and DTEZ do not happen simultaneously. When the PWM timer is in count-down mode, DTEZ will always happen one cycle earlier than DTEP, as demonstrated in Figure 86, so their action on PWM signals will not interrupt each other. When the PWM timer is in count-up-down mode, DTEZ will not occur. PWM Signal Generation The PWM generator submodule controls the behavior of outputs PWMxA and PWMxB when a particular timing event occurs. The timing events are further qualified by the PWM timer’s counting direction (up or down). Knowing the counting direction, the submodule may then perform an independent action at each stage of the PWM timer counting up or down. The following actions may be configured on outputs PWMxA and PWMxB: • Set High: Set the output of PWMxA or PWMxB to a high level. • Clear Low: Clear the output of PWMxA or PWMxB by setting it to a low level. • Toggle: Change the current output level of PWMxA or PWMxB to the opposite value. If it is currently pulled high, pull it low, or vice versa. • Do Nothing: Keep both outputs PWMxA and PWMxB unchanged. In this state, interrupts can still be triggered. The configuration of actions on outputs is done by using registers PWN_GENx_A_REG and PWN_GENx_B_REG. So, the action to be taken on each output is set independently. Also there is great flexibility in selecting actions to be taken on a given output based on events. More specifically, any event listed in Table 49 can operate on either output PWMxA or PWMxB. To check out registers for particular generator 0, 1 or 2, please refer to register description in Section 13.4. Espressif Systems 299 ESP32 Technical Reference Manual V2.0 13. MCPWM Waveforms for Common Configurations Figure 89 presents the symmetric PWM waveform generated when the PWM timer is counting up and down. DC 0%–100% modulation can be calculated via the formula below: Duty = (P eriod − A) ÷ P eriod If A matches the PWM timer value and the PWM timer is incrementing, then the PWM output is pulled up. If A matches the PWM timer value while the PWM timer is decrementing, then the PWM output is pulled low. Figure 89: Symmetrical Waveform in Count-Up-Down Mode The PWM waveforms in Figures 90 to 93 show some common PWM operator configurations. The following conventions are used in the figures: • Period A and B refer to the values written in the corresponding registers. • PWMxA and PWMxB are the output signals of PWM Operator x. Espressif Systems 300 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 90: Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High The duty modulation for PWMxA is set by B, active high and proportional to B. The duty modulation for PWMxB is set by A, active high and proportional to A. P eriod = (P W M _T IM ERx_P ERIOD + 1) × TP T _clk Espressif Systems 301 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 91: Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA Pulses may be generated anywhere within the PWM cycle (zero – period). PWMxA’s high time duty is proportional to (B – A). P eriod = (P W M _T IM ERx_P ERIOD + 1) × TP T _clk Espressif Systems 302 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 92: Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Active High The duty modulation for PWMxA is set by A, active high and proportional to A. The duty modulation for PWMxB is set by B, active high and proportional to B. Outputs PWMxA and PWMxB can drive independent switches. P eriod = 2 × P W M _T IM ERx_P ERIOD × TP T _clk Espressif Systems 303 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 93: Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and PWMxB — Complementary The duty modulation of PWMxA is set by A, is active high and proportional to A. The duty modulation of PWMxB is set by B, is active low and proportional to B. Outputs PWMx can drive upper/lower (complementary) switches. Dead-time = B – A; Edge placement is fully programmable by software. Use the dead-time generator module if another edge delay method is required. P eriod = 2 × P W M _T IM ERx_P ERIOD × TP T _clk Espressif Systems 304 ESP32 Technical Reference Manual V2.0 13. MCPWM Software-Force Events There are two types of software-force events inside the PWM generator: • Non-continuous-immediate (NCI) software-force events Such types of events are immediately effective on PWM outputs when triggered by software. The forcing is non-continuous, meaning the next active timing events will be able to alter the PWM outputs. • Continuous (CNTU) software-force events Such types of events are continuous. The forced PWM outputs will continue until they are released by software. The events’ triggers are configurable. They can be timing events or immediate events. Figure 94 shows a waveform of NCI software-force events. NCI events are used to force PWMxA output low. Forcing on PWMxB is disabled in this case. Figure 94: Example of an NCI Software-Force Event on PWMxA Espressif Systems 305 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 95 shows a waveform of CNTU software-force events. UTEZ events are selected as triggers for CNTU software-force events. CNTU is used to force the PWMxB output low. Forcing on PWMxA is disabled. Figure 95: Example of a CNTU Software-Force Event on PWMxB Espressif Systems 306 ESP32 Technical Reference Manual V2.0 13. MCPWM 13.3.3.2 Dead Time Generator Submodule Purpose of the Dead Time Generator Submodule Several options to generate signals on PWMxA and PWMxB outputs, with a specific placement of signal edges, have been discussed in section 13.3.3.1. The required dead time is obtained by altering the edge placement between signals and by setting the signal’s duty cycle. Another option is to control the dead time using a specialized submodule – the Dead Time Generator. The key functions of the dead time generator submodule are as follows: • Generating signal pairs (PWMxA and PWMxB) with a dead time from a single PWMxA input • Creating a dead time by adding delay to signal edges: – Rising edge delay (RED) – Falling edge delay (FED) • Configuring the signal pairs to be: – Active high complementary (AHC) – Active low complementary (ALC) – Active high (AH) – Active low (AL) • This submodule may also be bypassed, if the dead time is configured directly in the generator submodule. Dead Time Generator’s Shadow Registers Delay registers RED and FED are shadowed with registers PWM_DTx_RED_CFG_REG and PWM_DTx_FED_CFG_REG. For the description of shadow registers, please see section 13.3.2.3. Espressif Systems 307 ESP32 Technical Reference Manual V2.0 13. MCPWM Highlights for Operation of the Dead Time Generator Options for setting up the dead-time submodule are shown in Figure 96. Figure 96: Options for Setting up the Dead Time Generator Submodule S0-8 in the figure above are switches controlled by registers PWM_DTx_CFG_REG shown in Table 52. Table 52: Dead Time Generator Switches Control Registers Switch Register S0 PWM_DTx_B_OUTBYPASS S1 PWM_DTx_A_OUTBYPASS S2 PWM_DTx_RED_OUTINVERT S3 PWM_DTx_FED_OUTINVERT S4 PWM_DTx_RED_INSEL S5 PWM_DTx_FED_INSEL S6 PWM_DTx_A_OUTSWAP S7 PWM_DTx_B_OUTSWAP S8 PWM_DTx_DEB_MODE All switch combinations are supported, but not all of them represent the typical modes of use. Table 53 documents some typical dead time configurations. In these configurations the position of S4 and S5 sets PWMxA as the common source of both falling-edge and rising-edge delay. The modes presented in table 53 may be categorized as follows: • Mode 1: Bypass delays on both falling (FED) as well as raising edge (RED) In this mode the dead time submodule is disabled. Signals PWMxA and PWMxB pass through without any modifications. • Mode 2-5: Classical Dead Time Polarity Settings These modes represent typical configurations of polarity and should cover the active-high/low modes in available industry power switch gate drivers. The typical waveforms are shown in Figures 97 to 100. • Modes 6 and 7: Bypass delay on falling edge (FED) or rising edge (RED) Espressif Systems 308 ESP32 Technical Reference Manual V2.0 13. MCPWM In these modes, either RED (Rising Edge Delay) or FED (Falling Edge Delay) is bypassed. As a result, the corresponding delay is not applied. Table 53: Typical Dead Time Generator Operating Modes Mode Mode Description S0 S1 S2 S3 1 PWMxA and PWMxB Pass Through/No Delay 1 1 X X 2 Active High Complementary (AHC), see Figure 97 0 0 0 1 3 Active Low Complementary (ALC), see Figure 98 0 0 1 0 4 Active High (AH), see Figure 99 0 0 0 0 5 Active Low (AL), see Figure 100 0 0 1 1 6 PWMxA Output = PWMxA In (No Delay) 0 1 0 or 1 0 or 1 1 0 0 or 1 0 or 1 PWMxB Output = PWMxA Input with Falling Edge Delay 7 PWMxA Output = PWMxA Input with Rising Edge Delay PWMxB Output = PWMxB Input with No Delay Note: For all the modes above, the position of the binary switches S4 to S8 is set to 0. Figure 97: Active High Complementary (AHC) Dead Time Waveforms Rising edge (RED) and falling edge (FED) delays may be set up independently. The delay value is programmed using the 16-bit registers PWM_DTx_RED and PWM_DTx_FED. The register value represents the number of clock (DT_clk) periods by which a signal edge is delayed. DT_CLK can be selected from PWM_clk or PT_clk through register PWM_DTx_CLK_SEL. To calculate the delay on falling edge (FED) and rising edge (RED), use the following formulas: F ED = P W M _DT x_F ED × TDT _clk RED = P W M _DT x_RED × TDT _clk Espressif Systems 309 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 98: Active Low Complementary (ALC) Dead Time Waveforms Figure 99: Active High (AH) Dead Time Waveforms Figure 100: Active Low (AL) Dead Time Waveforms Espressif Systems 310 ESP32 Technical Reference Manual V2.0 13. MCPWM 13.3.3.3 PWM Carrier Submodule The coupling of PWM output to a motor driver may need isolation with a transformer. Transformers deliver only AC signals, while the duty cycle of a PWM signal may range anywhere from 0% to 100%. The PWM carrier submodule passes such a PWM signal through a transformer by using a high frequency carrier to modulate the signal. Function Overview The following key characteristics of this submodule are configurable: • Carrier frequency • Pulse width of the first pulse • Duty cycle of the second and the subsequent pulses • Enabling/disabling the carrier function Operational Highlights The PWM carrier clock (PC_clk) is derived from PWM_clk. The frequency and duty cycle are configured by the PWM_CARRIERx_PRESCALE and PWM_CARRIERx_DUTY bits in the PWM_CARRIERx_CFG_REG register. The purpose of one-shot pulses is to provide high-energy impulse to reliably turn on the power switch. Subsequent pulses sustain the power-on status. The width of a one-shot pulse is configurable with the PWM_CARRIERx_OSHTWTH bits. Enabling/disabling of the carrier submodule is done with the PWM_CARRIERx_EN bit. Waveform Examples Figure 101 shows an example of waveforms, where a carrier is superimposed on original PWM pulses. This figure do not show the first one-shot pulse and the duty-cycle control. Related details are covered in the following two sections. Espressif Systems 311 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 101: Example of Waveforms Showing PWM Carrier Action One-Shot Pulse The width of the first pulse is configurable. It may assume one of 16 possible values and is described by the formula below: T1stpulse = TP W M _clk × 8 × (P W M _CARRIERx_P RESCALE + 1) × (P W M _CARRIERx_OSHT W T H + 1) Where: • TP M W _clk is the period of the PWM clock (PWM_clk). • (P W M _CARRIERx_OSHT W T H + 1) is the width of the first pulse (whose value ranges from 1 to 16). • (P W M _CARRIERx_P RESCALE + 1) is the PWM carrier clock’s (PC_clk) prescaler value. The first one-shot pulse and subsequent sustaining pulses are shown in Figure 102. Duty Cycle Control After issuing the first one-shot pulse, the remaining PWM signal is modulated according to the carrier frequency. Users can configure the duty cycle of this signal. Tuning of duty may be required, so that the signal passes through the isolating transformer and can still operate (turn on/off) the motor drive, changing rotation speed and direction. The duty cycle may be set to one of seven values, using PWM_CARRIERx_DUTY, or bits [7:5] of register PWM_CARRIERx_CFG_REG. Below is the formula for calculating the duty cycle: Duty = P W M _CARRIERx_DU T Y ÷ 8 Espressif Systems 312 ESP32 Technical Reference Manual V2.0 13. MCPWM Figure 102: Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule All seven settings of the duty cycle are shown in Figure 103. Figure 103: Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 13.3.3.4 Fault Handler Submodule Each MCPWM peripheral is connected to three fault signals (FAULT0, FAULT1 and FAULT2) which are sourced from the GPIO matrix. These signals are intended to indicate external fault conditions, and may be preprocessed by the fault detection submodule to generate fault events. Fault events can then execute the user code to control Espressif Systems 313 ESP32 Technical Reference Manual V2.0 13. MCPWM MCPWM outputs in response to specific faults. Function of Fault Handler Submodule The key actions performed by the fault handler submodule are: • Forcing outputs PWMxA and PWMxB, upon detected fault, to one of the following states: – High – Low – Toggle – No action taken • Execution of one-shot trip (OST) upon detection of over-current conditions/short circuits. • Cycle-by-cycle tripping (CBC) to provide current-limiting operation. • Allocation of either one-shot or cycle-by-cycle operation for each fault signal. • Generation of interrupts for each fault input. • Support for software-force tripping. • Enabling or disabling of submodule function as required. Operation and Configuration Tips This section provides the operational tips and set-up options for the fault handler submodule. Fault signals coming from pads are sampled and synced in the GPIO matrix. In order to guarantee the successful sampling of fault pulses, each pulse duration must be at least two APB clock cycles. The fault detection submodule will then sample fault signals by using PWM_clk. So, the duration of fault pulses coming from GPIO matrix must be at least one PWM_clk cycle. Differently put, regardless of the period relation between APB clock and PWM_clk, the width of fault signal pulses on pads must be at least equal to the sum of two APB clock cycles and one PWM_clk cycle. Each level of fault signals, FAULT0 to FAULT2, can be used by the fault handler submodule to generate fault events (fault_event0 to fault_event2). Every fault event can be configured individually to provide CBC action, OST action, or none. • Cycle-by-Cycle (CBC) action: When CBC action is triggered, the state of PWMxA and PWMxB will be changed immediately according to the configuration of registers PWM_FHx_A_CBC_U/D and PWM_FHx_B_CBC_U/D. Different actions can be indicted when the PWM timer is incrementing or decrementing. Different CBC action interrupts can be triggered for different fault events. Status register PWM_FHx_CBC_ON indicates whether a CBC action is on or off. When the fault event is no longer present, CBC actions on PWMxA/B will be cleared at a specified point, which is either a D/UTEP or D/UTEZ event. Register PWM_FHx_CBCPULSE determines at which event PWMxA and PWMxB will be able to resume normal actions. Therefore, in this mode, the CBC action is cleared or refreshed upon every PWM cycle. • One-Shot (OST) action: Espressif Systems 314 ESP32 Technical Reference Manual V2.0 13. MCPWM When OST action is triggered, the state of PWMxA and PWMxB will be changed immediately, depending on the setting of registers PWM_FHx_A_OST_U/D and PWM_FHx_B_OST_U/D. Different actions can be configured when PWM timer is incrementing or decrementing. Different OST action interrupts can be triggered form different fault events. Status register PWM_FHx_OST_ON indicates whether an OST action is on or off. The OST actions on PWMxA/B are not automatically cleared when the fault event is no longer present. One-shot actions must be cleared manually by negating the value stored in register PWM_FHx_CLR_OST. 13.3.4 Capture Submodule 13.3.4.1 Introduction The capture submodule contains three complete capture channels. Channel inputs CAP0, CAP1 and CAP2 are sourced from the GPIO matrix. Thanks to the flexibility of the GPIO matrix, CAP0, CAP1 and CAP2 can be configured from any PAD input. Multiple capture channels can be sourced from the same PAD input, while prescaling for each channel can be set differently. Also, capture channels are sourced from different PADs. This provides several options for handling capture signals by hardware in the background, instead of having them processed directly by the CPU. A capture submodule has the following independent key resources: • One 32-bit timer (counter) which can be synchronized with the PWM timer, another submodule or software. • Three capture channels, each equipped with a 32-bit time-stamp and a capture prescaler. • Independent edge polarity (rising/falling edge) selection for any capture channel. • Input capture signal prescaling (from 1 to 256). • Interrupt capabilities on any of the three capture events. 13.3.4.2 Capture Timer The capture timer is a 32-bit counter incrementing continuously, once enabled. On the input it has an APB clock running typically at 80 MHz. At a sync event the counter is loaded with phase stored in register PWM_CAP_TIMER_PHASE_REG. Sync events can come from PWM timers sync-out, PWM module sync-in or software. The capture timer provides timing references for all three capture channels. 13.3.4.3 Capture Channel The capture signal coming to a capture channel will be inverted first, if needed, and then prescaled. Finally, specified edges of preprocessed capture signal will trigger capture events. When a capture event occurs, the capture timer’s value is stored in time-stamp register PWM_CAP_CHx_REG. Different interrupts can be generated for different capture channels at capture events. The edge that triggers a capture event is recorded in register PWM_CAPx_EDGE. The capture event can be also forced by software. Espressif Systems 315 ESP32 Technical Reference Manual V2.0 13. MCPWM 13.4 Register Summary Name Description PWM0 PWM1 Acc Configuration of the prescaler 0x3FF5E000 0x3FF6C000 R/W Prescaler configuration PWM_CLK_CFG_REG PWM Timer 0 Configuration and status PWM_TIMER0_CFG0_REG Timer period and update method 0x3FF5E004 0x3FF6C004 R/W PWM_TIMER0_CFG1_REG Working mode and start/stop control 0x3FF5E008 0x3FF6C008 R/W PWM_TIMER0_SYNC_REG Synchronization settings 0x3FF5E00C 0x3FF6C00C R/W PWM_TIMER0_STATUS_REG Timer status 0x3FF5E010 0x3FF6C010 RO PWM Timer 1 Configuration and Status PWM_TIMER1_CFG0_REG Timer update method and period 0x3FF5E014 0x3FF6C014 R/W PWM_TIMER1_CFG1_REG Working mode and start/stop control 0x3FF5E018 0x3FF6C018 R/W PWM_TIMER1_SYNC_REG Synchronization settings 0x3FF5E01C 0x3FF6C01C R/W PWM_TIMER1_STATUS_REG Timer status 0x3FF5E020 0x3FF6C020 RO PWM Timer 2 Configuration and status PWM_TIMER2_CFG0_REG Timer update method and period 0x3FF5E024 0x3FF6C024 R/W PWM_TIMER2_CFG1_REG Working mode and start/stop control 0x3FF5E028 0x3FF6C028 R/W PWM_TIMER2_SYNC_REG Synchronization settings 0x3FF5E02C 0x3FF6C02C R/W PWM_TIMER2_STATUS_REG Timer status 0x3FF5E030 0x3FF6C030 RO 0x3FF5E034 0x3FF6C034 R/W 0x3FF5E038 0x3FF6C038 R/W 0x3FF5E03C 0x3FF6C03C R/W Common configuration for PWM timers PWM_TIMER_SYNCI_CFG_REG Synchronization input selection for timers PWM_OPERATOR_TIMERSEL_REG Select specific timer for PWM operators PWM Operator 0 Configuration and Status PWM_GEN0_STMP_CFG_REG Transfer status and update method for time stamp registers A and B PWM_GEN0_TSTMP_A_REG Shadow register for register A 0x3FF5E040 0x3FF6C040 R/W PWM_GEN0_TSTMP_B_REG Shadow register for register B 0x3FF5E044 0x3FF6C044 R/W PWM_GEN0_CFG0_REG Fault event T0 and T1 handling 0x3FF5E048 0x3FF6C048 R/W PWM_GEN0_FORCE_REG Permissives to force PWM0A and 0x3FF5E04C 0x3FF6C04C R/W PWM0B outputs by software PWM_GEN0_A_REG Actions triggered by events on 0x3FF5E050 0x3FF6C050 R/W triggered by events on 0x3FF5E054 0x3FF6C054 R/W Dead time type selection and configu- 0x3FF5E058 0x3FF6C058 R/W 0x3FF5E05C 0x3FF6C05C R/W 0x3FF5E060 0x3FF6C060 R/W 0x3FF5E064 0x3FF6C064 R/W PWM0A PWM_GEN0_B_REG Actions PWM0B PWM_DT0_CFG_REG ration PWM_DT0_FED_CFG_REG Shadow register for falling edge delay (FED) PWM_DT0_RED_CFG_REG Shadow register for rising edge delay (RED) PWM_CARRIER0_CFG_REG Espressif Systems Carrier enable and configuration 316 ESP32 Technical Reference Manual V2.0 13. MCPWM Name Description PWM0 PWM1 Acc PWM_FH0_CFG0_REG Actions on PWM0A and PWM0B on 0x3FF5E068 0x3FF6C068 R/W 0x3FF5E06C 0x3FF6C06C R/W 0x3FF5E070 0x3FF6C070 RO 0x3FF5E074 0x3FF6C074 R/W trip events PWM_FH0_CFG1_REG Software triggers for fault handler actions PWM_FH0_STATUS_REG Status of fault events PWM Operator 1 Configuration and Status PWM_GEN1_STMP_CFG_REG Transfer status and update method for time stamp registers A and B PWM_GEN1_TSTMP_A_REG Shadow register for register A 0x3FF5E078 0x3FF6C078 R/W PWM_GEN1_TSTMP_B_REG Shadow register for register B 0x3FF5E07C 0x3FF6C07C R/W PWM_GEN1_CFG0_REG Fault event T0 and T1 handling 0x3FF5E080 0x3FF6C080 R/W PWM_GEN1_FORCE_REG Permissives to force PWM1A and 0x3FF5E084 0x3FF6C084 R/W PWM1B outputs by software PWM_GEN1_A_REG Actions triggered by events on 0x3FF5E088 0x3FF6C088 R/W triggered by events on 0x3FF5E08C 0x3FF6C08C R/W Dead time type selection and configu- 0x3FF5E090 0x3FF6C090 R/W PWM1A PWM_GEN1_B_REG Actions PWM1B PWM_DT1_CFG_REG ration PWM_DT1_FED_CFG_REG Shadow register for FED 0x3FF5E094 0x3FF6C094 R/W PWM_DT1_RED_CFG_REG Shadow register for RED 0x3FF5E098 0x3FF6C098 R/W PWM_CARRIER1_CFG_REG Carrier enable and configuration 0x3FF5E09C 0x3FF6C09C R/W PWM_FH1_CFG0_REG Actions on PWM1A and PWM1B on 0x3FF5E0A0 0x3FF6C0A0 R/W 0x3FF5E0A4 0x3FF6C0A4 R/W 0x3FF5E0A8 0x3FF6C0A8 RO 0x3FF5E0AC 0x3FF6C0AC R/W fault events PWM_FH1_CFG1_REG Software triggers for fault handler actions PWM_FH1_STATUS_REG Status of fault events PWM Operator 2 Configuration and Status PWM_GEN2_STMP_CFG_REG Transfer status and updating method for time stamp registers A and B PWM_GEN2_TSTMP_A_REG Shadow register for register A 0x3FF5E0B0 0x3FF6C0B0 R/W PWM_GEN2_TSTMP_B_REG Shadow register for register B 0x3FF5E0B4 0x3FF6C0B4 R/W PWM_GEN2_CFG0_REG Fault event T0 and T1 handling 0x3FF5E080 0x3FF6C080 R/W PWM_GEN2_FORCE_REG Permissives to force PWM2A and 0x3FF5E0BC 0x3FF6C0BC R/W PWM2B outputs by software PWM_GEN2_A_REG Actions triggered by events on 0x3FF5E0C0 0x3FF6C0C0 R/W triggered by events on 0x3FF5E0C4 0x3FF6C0C4 R/W Dead time type selection and configu- 0x3FF5E0C8 0x3FF6C0C8 R/W PWM2A PWM_GEN2_B_REG Actions PWM2B PWM_DT2_CFG_REG ration PWM_DT2_FED_CFG_REG Shadow register for FED 0x3FF5E0CC 0x3FF6C0CC R/W PWM_DT2_RED_CFG_REG Shadow register for RED 0x3FF5E0D0 0x3FF6C0D0 R/W PWM_CARRIER2_CFG_REG Carrier enable and configuration 0x3FF5E0D4 0x3FF6C0D4 R/W Espressif Systems 317 ESP32 Technical Reference Manual V2.0 13. MCPWM Name Description PWM0 PWM1 Acc PWM_FH2_CFG0_REG Actions at PWM2A and PWM2B on 0x3FF5E0D8 0x3FF6C0D8 R/W 0x3FF5E0DC 0x3FF6C0DC R/W 0x3FF5E0E0 0x3FF6C0E0 RO 0x3FF5E0E4 0x3FF6C0E4 R/W trip events PWM_FH2_CFG1_REG Software triggers for fault handler actions PWM_FH2_STATUS_REG Status of fault events Fault Detection Configuration and Status PWM_FAULT_DETECT_REG Fault detection configuration and status Capture Configuration and Status PWM_CAP_TIMER_CFG_REG Configure capture timer 0x3FF5E0E8 0x3FF6C0E8 R/W PWM_CAP_TIMER_PHASE_REG Phase for capture timer sync 0x3FF5E0EC 0x3FF6C0EC R/W PWM_CAP_CH0_CFG_REG Capture channel 0 configuration and 0x3FF5E0F0 0x3FF6C0F0 R/W 0x3FF5E0F4 0x3FF6C0F4 R/W 0x3FF5E0F8 0x3FF6C0F8 R/W enable PWM_CAP_CH1_CFG_REG Capture channel 1 configuration and enable PWM_CAP_CH2_CFG_REG Capture channel 2 configuration and enable PWM_CAP_CH0_REG Value of last capture on channel 0 0x3FF5E0FC 0x3FF6C0FC RO PWM_CAP_CH1_REG Value of last capture on channel 1 0x3FF5E100 0x3FF6C100 RO PWM_CAP_CH2_REG Value of last capture on channel 2 0x3FF5E104 0x3FF6C104 RO PWM_CAP_STATUS_REG Edge of last capture trigger 0x3FF5E108 0x3FF6C108 RO Enable update 0x3FF5E10C 0x3FF6C10C R/W INT_ENA_PWM_REG Interrupt enable bits 0x3FF5E110 0x3FF6C110 R/W INT_RAW_PWM_REG Raw interrupt status 0x3FF5E114 0x3FF6C114 RO INT_ST_PWM_REG Masked interrupt status 0x3FF5E118 0x3FF6C118 RO INT_CLR_PWM_REG Interrupt clear bits 0x3FF5E11C 0x3FF6C11C WO Enable update of active registers PWM_UPDATE_CFG_REG Manage Interrupts 13.5 Registers (re PW M se rv ed ) _C LK _P RE SC AL E Register 13.1: PWM_CLK_CFG_REG (0x0000) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0x000 Reset PWM_CLK_PRESCALE Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). (R/W) Espressif Systems 318 ESP32 Technical Reference Manual V2.0 13. MCPWM D 0 0 0 0 25 0 24 PR 0_ 0_ ER ER _T IM _T IM PW PW M M M _T PW 26 0 ES O RI PE ER ER 0_ P IM ) rv ed se (re 31 CA L E IO D_ UP M ET HO D Register 13.2: PWM_TIMER0_CFG0_REG (0x0004) 23 8 0 7 0 0x000FF 0x000 Reset PWM_TIMER0_PERIOD_UPMETHOD Updating method for active register of PWM timer0 period. 0: immediately, 1: update at TEZ, 2: update at sync, 3: update at TEZ or sync. TEZ here and below means that the event that happens when the timer equals to zero. (R/W) PWM_TIMER0_PERIOD Period shadow register of PWM timer0. (R/W) PWM_TIMER0_PRESCALE Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1). (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 0x0 M PW M PW 5 0 _T I IM _T d) rv e se (re 31 0 M ER ER 0_ 0_ M O D ST AR T Register 13.3: PWM_TIMER0_CFG1_REG (0x0008) 2 0 0x0 Reset PWM_TIMER0_MOD PWM timer0 working mode. 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode. (R/W) PWM_TIMER0_START PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ; 1: if timer0 starts, then stops at TEP; 2: PWM timer0 starts and runs on; 3: timer0 starts and stops at the next TEZ; 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period. (R/W) Espressif Systems 319 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 21 0 0 0 0 0 0 0 0 0 4 0 M M ER0 PW _T _S YN M IME _T R CO IM 0_ _S ER SY 0_ NC EL SY _ NC SW I_ EN _T I M 20 0 3 PW PW PW (re s M er ve _T d) IM ER 0_ PH AS E Register 13.4: PWM_TIMER0_SYNC_REG (0x000c) 2 0 1 0 0 0 Reset PWM_TIMER0_PHASE Phase for timer reload at sync event. (R/W) PWM_TIMER1_SYNCO_SEL PWM timer0 sync_out selection. 0: sync_in; 1: TEZ; 2: TEP; otherwise: sync_out is always 0. (R/W) PWM_TIMER1_SYNC_SW Toggling this bit will trigger a software sync. (R/W) PWM_TIMER1_SYNCI_EN When set, timer reloading with phase on sync input event is enabled. (R/W) 0 0 0 0 0 0 0 0 IM M ER 0 0 0 0 16 0 0 PW PW M 0 17 M _T _T I ve d) (re se r 31 0 ER 0_ 0_ DI RE VA LU E CT IO N Register 13.5: PWM_TIMER0_STATUS_REG (0x0010) 15 0 0 Reset PWM_TIMER0_DIRECTION Current direction of the PWM timer0 counter. 0: increment, 1: decrement. (RO) PWM_TIMER0_VALUE Current value of the PWM timer0 counter. (RO) Espressif Systems 320 ESP32 Technical Reference Manual V2.0 13. MCPWM D 0 0 0 0 25 0 24 PR 1_ 1_ ER ER _T IM _T IM PW PW M M M _T PW 26 0 ES O RI PE ER ER 1_ P IM ) rv ed se (re 31 CA L E IO D_ UP M ET HO D Register 13.6: PWM_TIMER1_CFG0_REG (0x0014) 23 8 0 7 0 0x000FF 0x000 Reset PWM_TIMER1_PERIOD_UPMETHOD Updating method for the active register of PWM timer1 period. 0: immediately, 1: update at TEZ, 2: update at sync, 3: update at TEZ or sync. (R/W) PWM_TIMER1_PERIOD Period shadow register of the PWM timer1. (R/W) PWM_TIMER1_PRESCALE Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1) (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 0x0 M PW M PW 5 0 _T I IM _T d) rv e se (re 31 0 M ER ER 1_ 1_ M O D ST AR T Register 13.7: PWM_TIMER1_CFG1_REG (0x0018) 2 0 0x0 Reset PWM_TIMER1_MOD PWM timer1 working mode. 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode. (R/W) PWM_TIMER1_START PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ; 1: if PWM timer1 starts, then stops at TEP; 2: PWM timer1 starts and runs on; 3: PWM timer1 starts and stops at the next TEZ; 4: PWM timer1 starts and stops at the next TEP. (R/W) Espressif Systems 321 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 21 0 0 0 0 0 0 0 0 0 4 0 M M ER1 PW _T _S YN M IME _T R CO IM 1_ _S ER SY 1_ NC EL SY _ NC SW I_ EN _T I M 20 0 3 PW PW PW (re s M er ve _T d) IM ER 1_ PH AS E Register 13.8: PWM_TIMER1_SYNC_REG (0x001c) 2 0 1 0 0 0 Reset PWM_TIMER1_PHASE Phase for timer reload at sync event. (R/W) PWM_TIMER1_SYNCO_SEL PWM timer1 sync_out selection. 0: sync_in; 1: TEZ; 2: TEP; otherwise: sync_out is always 0. (R/W) PWM_TIMER1_SYNC_SW Toggling this bit will trigger a software sync. (R/W) PWM_TIMER1_SYNCI_EN When set, timer reloading with phase at a sync input event is enabled. (R/W) 0 0 0 0 0 0 0 0 IM M ER 0 0 0 0 16 0 0 PW PW M 0 17 M _T _T I ve d) (re se r 31 0 ER 1_ 1_ DI RE VA LU E CT IO N Register 13.9: PWM_TIMER1_STATUS_REG (0x0020) 15 0 0 Reset PWM_TIMER1_DIRECTION Current direction of the PWM timer1 counter. 0: increment 1: decrement. (RO) PWM_TIMER1_VALUE Current value of the PWM timer1 counter. (RO) Espressif Systems 322 ESP32 Technical Reference Manual V2.0 13. MCPWM D 0 0 0 0 25 0 24 PR 2_ 2_ ER ER _T IM _T IM PW PW M M M _T PW 26 0 ES O RI PE ER ER 2_ P IM ) rv ed se (re 31 CA L E IO D_ UP M ET HO D Register 13.10: PWM_TIMER2_CFG0_REG (0x0024) 23 8 0 7 0 0x000FF 0x000 Reset PWM_TIMER2_PERIOD_UPMETHOD Updating method for active register of PWM timer2 period. 0: immediately, 1: update at TEZ, 2: update at sync, 3: update at TEZ or sync. (R/W) PWM_TIMER2_PERIOD Period shadow register of PWM timer2. (R/W) PWM_TIMER2_PRESCALE Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1). (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 0x0 M PW M PW 5 0 _T I IM _T d) rv e se (re 31 0 M ER ER 2_ 2_ M O D ST AR T Register 13.11: PWM_TIMER2_CFG1_REG (0x0028) 2 0 0x0 Reset PWM_TIMER2_MOD PWM timer2 working mode. 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode. (R/W) PWM_TIMER2_START PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ; 1: if PWM timer2 starts, then stops at TEP; 2: PWM timer2 starts and runs on; 3: PWM timer2 starts and stops at the next TEZ; 4: PWM timer2 starts and stops at the next TEP. (R/W) Espressif Systems 323 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 21 0 0 0 0 0 0 0 0 0 4 0 M M ER2 PW _T _S YN M IME _T R CO IM 2_ _S ER SY 2_ NC EL SY _ NC SW I_ EN _T I M 20 0 3 PW PW PW (re s M er ve _T d) IM ER 2_ PH AS E Register 13.12: PWM_TIMER2_SYNC_REG (0x002c) 2 0 1 0 0 0 Reset PWM_TIMER2_PHASE Phase for timer reload at sync event. (R/W) PWM_TIMER2_SYNCO_SEL PWM timer2 sync_out selection. 0: sync_in; 1: TEZ; 2: TEP; otherwaise: sync_out is always 0. (R/W) PWM_TIMER2_SYNC_SW Toggling this bit will trigger a software sync. (R/W) PWM_TIMER2_SYNCI_EN When set, timer reloading with phase on sync input event is enabled. (R/W) 0 0 0 0 0 0 0 0 IM M ER 0 0 0 0 16 0 0 PW PW M 0 17 M _T _T I ve d) (re se r 31 0 ER 2_ 2_ DI RE VA LU E CT IO N Register 13.13: PWM_TIMER2_STATUS_REG (0x0030) 15 0 0 Reset PWM_TIMER2_DIRECTION Current direction of the PWM timer2 counter. 0: increment, 1: decrement. (RO) PWM_TIMER2_VALUE Current value of the PWM timer2 counter. (RO) Espressif Systems 324 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed ) PW M PW _E M XTE P W _E R M XTE NA _E R L_ XT NA SY ER L_ N PW NA SY CI2 M L_ NC _IN _T SY I1 VE IM ER NC _IN RT 2_ I0 VE _I R S PW YN NV T CI ER M _T SE T IM L ER 1_ SY PW NC M IS _T EL IM ER 0_ SY NC IS EL Register 13.14: PWM_TIMER_SYNCI_CFG_REG (0x0034) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 11 10 9 0 0 0 0 8 6 5 3 0 2 0 0 0 Reset PWM_EXTERNAL_SYNCI2_INVERT Invert SYNC2 from GPIO matrix. (R/W) PWM_EXTERNAL_SYNCI1_INVERT Invert SYNC1 from GPIO matrix. (R/W) PWM_EXTERNAL_SYNCI0_INVERT Invert SYNC0 from GPIO matrix. (R/W) PWM_TIMER2_SYNCISEL Select sync input for PWM timer2. 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W) PWM_TIMER1_SYNCISEL Select sync input for PWM timer1. 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W) PWM_TIMER0_SYNCISEL Select sync input for PWM timer0. 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W) 31 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 0 _O M PW (re PW M se r ve _O d) PE RA TO R2 PE _T IM RA PW ER T M O SE _O R1 L PE _T IM RA ER TO SE R0 L _T IM ER SE L Register 13.15: PWM_OPERATOR_TIMERSEL_REG (0x0038) 3 2 0 1 0 0 Reset PWM_OPERATOR2_TIMERSEL Select the PWM timer for PWM operator2’s timing reference. 0: timer0, 1: timer1, 2: timer2. (R/W) PWM_OPERATOR1_TIMERSEL Select the PWM timer for PWM operator1’s timing reference. 0: timer0, 1: timer1, 2: timer2. (R/W) PWM_OPERATOR0_TIMERSEL Select the PWM timer for PWM operator0’s timing reference. 0: timer0, 1: timer1, 2: timer2. (R/W) Espressif Systems 325 ESP32 Technical Reference Manual V2.0 13. MCPWM (re PW se rv ed ) M PW _G M EN _ G 0_ EN B_ 0_ SH A_ D PW SH W_ M D W FU _G EN _F LL 0_ UL B_ L UP M ET PW HO M D _G EN 0_ A_ UP M ET HO D Register 13.16: PWM_GEN0_STMP_CFG_REG (0x003c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 9 8 0 0 0 7 4 0 3 0 0 Reset PWM_GEN0_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 0 time stamp B’s shadow register.ister is filled and to be transferred to time stamp B’s active register. If cleared, time stamp B’s active register has been updated with Shadow register latest value. (RO) PWM_GEN0_A_SHDW_FULL Set and reset by hardware. If set, PWM generator 0 time stamp A’s shadow register.ister is filled and to be transferred to time stamp A’s active register. If cleared, time stamp A’s active register has been updated with Shadow register latest value. (RO) PWM_GEN0_B_UPMETHOD Updating method for PWM generator 0 time stamp B’s active register. When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) PWM_GEN0_A_UPMETHOD Updating method for PWM generator 0 time stamp A’s active register. When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) (re PW se r M _G ve d) EN 0_ A Register 13.17: PWM_GEN0_TSTMP_A_REG (0x0040) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_GEN0_A PWM generator 0 time stamp A’s shadow register. (R/W) (re PW M _G se rv ed ) EN 0_ B Register 13.18: PWM_GEN0_TSTMP_B_REG (0x0044) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_GEN0_B PWM generator 0 time stamp B’s shadow register. (R/W) Espressif Systems 326 ESP32 Technical Reference Manual V2.0 13. MCPWM EL L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 7 6 0 _G EN 0_ T0 EN 0_ M _G PW M PW M PW 10 CF G _S _S E T1 EN 0_ _G d) ve (re se r 31 _U P M ET HO D Register 13.19: PWM_GEN0_CFG0_REG (0x0048) 4 0 3 0 0 Reset PWM_GEN0_T1_SEL Source selection for PWM generator 0 event_t1, taking effect immediately. 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W) PWM_GEN0_T0_SEL Source selection for PWM generator 0 event_t0, taking effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W) PWM_GEN0_CFG_UPMETHOD Updating method for PWM generator 0’s active register of configuration. When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) Espressif Systems 327 ESP32 Technical Reference Manual V2.0 13. MCPWM PW (re s er ve d) M _G PW EN 0 M _G _B PW EN _NC IF 0 M O _G _B RC PW EN _NC E_ IF 0_ M M O A_ _G O R CE DE NC PW EN IF 0 M O _G _A_ RC NC EN E_ PW IF 0_ M O B_ RC OD M CN _G E E EN TU 0_ FO A_ RC CN E_ TU M O PW FO DE RC M _G E_ EN M O 0_ DE CN TU FO RC E_ UP M ET HO D Register 13.20: PWM_GEN0_FORCE_REG (0x004c) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 11 0 10 0 9 8 0 7 6 0 5 0 0x20 Reset PWM_GEN0_B_NCIFORCE_MODE Non-continuous immediate software-force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN0_B_NCIFORCE Trigger of non-continuous immediate software-force event for PWM0B; a toggle will trigger a force event. (R/W) PWM_GEN0_A_NCIFORCE_MODE Non-continuous immediate software-force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN0_A_NCIFORCE Trigger of non-continuous immediate software-force event for PWM0A; a toggle will trigger a force event. (R/W) PWM_GEN0_B_CNTUFORCE_MODE Continuous software-force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN0_A_CNTUFORCE_MODE Continuous software-force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN0_CNTUFORCE_UPMETHOD Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: TEA; when bit3 is set to 1: TEB; when bit4 is set to 1: sync; when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer’s value equals to that of register A/B.) (R/W) Espressif Systems 328 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 24 0 0 0 0 0 0 0 23 _G EN 0_ A_ M DT _G 1 EN PW 0_ A_ M DT _G 0 EN PW 0_ A M _D _G TE EN B PW 0_ A_ M DT _G EA EN PW 0_ A M _D _G TE EN P PW 0_ A M _D _G TE EN Z PW 0_ A_ M UT _G 1 EN PW 0_ A_ M UT _G 0 EN PW 0_ A M _U _G TE EN B PW 0_ A_ M UT _G EA EN PW 0_ A M _U _G TE EN P 0_ A_ UT EZ PW (re PW se M rv ed ) Register 13.21: PWM_GEN0_A_REG (0x0050) 22 0 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 0 5 4 0 3 2 0 1 0 0 Reset PWM_GEN0_A_DT1 Action on PWM0A triggered by event_t1 when the timer decreases. 0: no change, 1: low, 2: high, 3: toggle. (R/W) PWM_GEN0_A_DT0 Action on PWM0A triggered by event_t0 when the timer decreases. (R/W) PWM_GEN0_A_DTEB Action on PWM0A triggered by event TEB when the timer decreases. (R/W) PWM_GEN0_A_DTEA Action on PWM0A triggered by event TEA when the timer decreases. (R/W) PWM_GEN0_A_DTEP Action on PWM0A triggered by event TEP when the timer decreases. (R/W) PWM_GEN0_A_DTEZ Action on PWM0A triggered by event TEZ when the timer decreases. (R/W) PWM_GEN0_A_UT1 Action on PWM0A triggered by event_t1 when the timer increases. (R/W) PWM_GEN0_A_UT0 Action on PWM0A triggered by event_t0 when the timer increases. (R/W) PWM_GEN0_A_UTEB Action on PWM0A triggered by event TEB when the timer increases. (R/W) PWM_GEN0_A_UTEA Action on PWM0A triggered by event TEA when the timer increases. (R/W) PWM_GEN0_A_UTEP Action on PWM0A triggered by event TEP when the timer increases. (R/W) PWM_GEN0_A_UTEZ Action on PWM0A triggered by event TEZ when the timer increases. (R/W) Espressif Systems 329 ESP32 Technical Reference Manual V2.0 13. MCPWM EN ) _G ed 0 0 0 0 0 0 0 23 PW PW 24 22 0 M M rv se (re 31 0 0_ B_ DT _G 1 EN PW 0_ B_ M DT _G 0 EN PW 0_ B M _D _G TE EN B PW 0_ B_ M DT _G EA EN PW 0_ B M _D _G TE EN P PW 0_ B M _D _G TE EN Z PW 0_ B_ M UT _G 1 EN PW 0_ B_ M UT _G 0 EN PW 0_ B M _U _G TE EN B PW 0_ B_ M UT _G EA EN PW 0_ B M _U _G TE EN P 0_ B_ UT EZ Register 13.22: PWM_GEN0_B_REG (0x0054) 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 0 5 4 0 3 2 0 1 0 0 Reset PWM_GEN0_B_DT1 Action on PWM0B triggered by event_t1 when the timer decreases. 0: no change, 1: low, 2: high, 3: toggle. (R/W) PWM_GEN0_B_DT0 Action on PWM0B triggered by event_t0 when the timer decreases. (R/W) PWM_GEN0_B_DTEB Action on PWM0B triggered by event TEB when the timer decreases. (R/W) PWM_GEN0_B_DTEA Action on PWM0B triggered by event TEA when the timer decreases. (R/W) PWM_GEN0_B_DTEP Action on PWM0B triggered by event TEP when the timer decreases. (R/W) PWM_GEN0_B_DTEZ Action on PWM0B triggered by event TEZ when the timer decreases. (R/W) PWM_GEN0_B_UT1 Action on PWM0B triggered by event_t1 when the timer increases. (R/W) PWM_GEN0_B_UT0 Action on PWM0B triggered by event_t0 when the timer increases. (R/W) PWM_GEN0_B_UTEB Action on PWM0B triggered by event TEB when the timer increases. (R/W) PWM_GEN0_B_UTEA Action on PWM0B triggered by event TEA when the timer increases. (R/W) PWM_GEN0_B_UTEP Action on PWM0B triggered by event TEP when the timer increases. (R/W) PWM_GEN0_B_UTEZ Action on PWM0B triggered by event TEZ when the timer increases. (R/W) Espressif Systems 330 ESP32 Technical Reference Manual V2.0 13. MCPWM (re PW se rv ed ) M PW _D M T0 PW _D _C M T0 LK PW _D _B _S M T0 _O EL PW _D _A UT M T0 _O BY PW _D _F UT PA M T0 ED BY SS PW _D _R _O PA M T0 ED UT SS PW _D _F _O INV M T0 ED U E PW _D _R _IN TIN RT V M T0 ED S E PW _D _B _IN EL RT _ M T0_ OU SE _D A T L T0 _O SW _D UT A EB SW P PW _M A M _D O P DE T0 _R ED _U PM PW ET HO M _D D T0 _F ED _U PM ET HO D Register 13.23: PWM_DT0_CFG_REG (0x0058) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 18 17 16 15 14 13 12 11 10 9 8 0 0 1 1 0 0 0 0 0 0 0 7 4 0 3 0 0 Reset PWM_DT0_CLK_SEL Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk. (R/W) PWM_DT0_B_OUTBYPASS S0 in Table 52. (R/W) PWM_DT0_A_OUTBYPASS S1 in Table 52. (R/W) PWM_DT0_FED_OUTINVERT S3 in Table 52. (R/W) PWM_DT0_RED_OUTINVERT S2 in Table 52. (R/W) PWM_DT0_FED_INSEL S5 in Table 52. (R/W) PWM_DT0_RED_INSEL S4 in Table 52. (R/W) PWM_DT0_B_OUTSWAP S7 in Table 52. (R/W) PWM_DT0_A_OUTSWAP S6 in Table 52. (R/W) PWM_DT0_DEB_MODE S8 in Table 52, dual-edge B mode. 0: FED/RED take effect on different paths separately, 1: FED/RED take effect on B path. (R/W) PWM_DT0_RED_UPMETHOD Updating method for RED (rising edge delay) active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) PWM_DT0_FED_UPMETHOD Updating method for FED (falling edge delay) active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) (re se PW M rv ed _D T ) 0_ FE D Register 13.24: PWM_DT0_FED_CFG_REG (0x005c) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_DT0_FED Shadow register for FED. (R/W) Espressif Systems 331 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se PW M rv ed _D T ) 0_ RE D Register 13.25: PWM_DT0_RED_CFG_REG (0x0060) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_DT0_RED Shadow register for RED. (R/W) (re se r ve d) PW M PW _C M AR _C R AR IER RI 0_ ER IN PW 0_ _IN M O VE _C UT R AR _I T NV RI ER ER 0_ T O PW SH M W _C TH AR RI ER 0_ DU PW TY M _C AR RI ER PW 0_ M PR _C ES AR CA RI ER LE 0_ EN Register 13.26: PWM_CARRIER0_CFG_REG (0x0064) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 0 0 0 11 8 0 7 5 0 4 1 0 0 0 Reset PWM_CARRIER0_IN_INVERT When set, invert the input of PWM0A and PWM0B for this submodule. (R/W) PWM_CARRIER0_OUT_INVERT When set, invert the output of PWM0A and PWM0B for this submodule. (R/W) PWM_CARRIER0_OSHWTH Width of the first pulse�in number of periods of the carrier. (R/W) PWM_CARRIER0_DUTY Carrier duty selection. Duty = PWM_CARRIER0_DUTY/8. (R/W) PWM_CARRIER0_PRESCALE PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1). (R/W) PWM_CARRIER0_EN When set, carrier0 function is enabled. When cleared, carrier0 is bypassed. (R/W) Espressif Systems 332 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 24 0 0 0 0 0 0 0 23 _F H0 _B _O M ST _F _U H0 _B PW _ O M ST _F _D H0 _B PW _ CB M _F C_ H0 U _B PW _C M BC _F H0 _D _ PW A_ O M ST _F _U H0 _A PW _O M ST _F _D H0 _A PW _C M BC _F _U PW H0 _A M _ PW _F CB M H0 C_ PW _F _F D M H0_ 0_O PW _F F S M H0 1_ T PW _F _F OS M H0 2_ T PW _F _S OS M H0 W T PW _F _F _OS M H0 0_ T PW _F _F CB M H0_ 1_C C _F F B H0 2_ C _S CB W C _C BC 22 0 PW PW (re s M er ve d) Register 13.27: PWM_FH0_CFG0_REG (0x0068) 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset PWM_FH0_B_OST_U One-shot mode action on PWM0B when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_B_OST_D One-shot mode action on PWM0B when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_B_CBC_U Cycle-by-cycle mode action on PWM0B when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_B_CBC_D Cycle-by-cycle mode action on PWM0B when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_A_OST_U One-shot mode action on PWM0A when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_A_OST_D One-shot mode action on PWM0A when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_A_CBC_U Cycle-by-cycle mode action on PWM0A when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_A_CBC_D Cycle-by-cycle mode action on PWM0A when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH0_F0_OST event_f0 will trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH0_F1_OST event_f1 will trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH0_F2_OST event_f2 will trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH0_SW_OST Enable register for software-forced one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH0_F0_CBC event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH0_F1_CBC event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH0_F2_CBC event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH0_SW_CBC Enable register for software-forced cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) Espressif Systems 333 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed ) PW M PW _F M H0_ _F F PW H0 OR _F C M O E_ _F RC O S PW H0 _C E_C T M B BC _F H0 CP _C U L LR SE _O ST Register 13.28: PWM_FH0_CFG1_REG (0x006c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 0 0 0 2 1 0 0 0 Reset PWM_FH0_FORCE_OST A toggle (software negation of this bit’s value) triggers a one-shot mode action. (R/W) PWM_FH0_FORCE_CBC A toggle triggers a cycle-by-cycle mode action. (R/W) PWM_FH0_CBCPULSE The cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ; when bit1 is set to 1: TEP. (R/W) PWM_FH0_CLR_OST A toggle will clear on-going one-shot mode action. (R/W) (re se rv ed ) PW M PW _F M H0_ _F O H0 ST _C _O BC N _O N Register 13.29: PWM_FH0_STATUS_REG (0x0070) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset PWM_FH0_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO) PWM_FH0_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going. (RO) Espressif Systems 334 ESP32 Technical Reference Manual V2.0 13. MCPWM (re PW se rv ed ) M PW _G M EN _ G 1_ EN B_ 1_ SH A_ D PW SH W_ M D W FU _G EN _F LL 1_ UL B_ L UP M ET PW HO M D _G EN 1_ A_ UP M ET HO D Register 13.30: PWM_GEN1_STMP_CFG_REG (0x0074) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 9 8 0 0 0 7 4 3 0 0 0 Reset PWM_GEN1_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 1 time stamp B’s shadow register is filled and to be transferred to time stamp B’s active register. If cleared, time stamp B’s active register has been updated with shadow register’s latest value. (RO) PWM_GEN1_A_SHDW_FULL Set and reset by hardware. If set, PWM generator 1 time stamp A’s shadow register is filled and to be transferred to time stamp A’s active register. If cleared, time stamp A’s active register has been updated with shadow register latest value. (RO) PWM_GEN1_B_UPMETHOD Updating method for PWM generator 1 time stamp B’s active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) PWM_GEN1_A_UPMETHOD Updating method for PWM generator 1 time stamp A’s active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) (re PW se r M _G ve d) EN 1_ A Register 13.31: PWM_GEN1_TSTMP_A_REG (0x0078) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_GEN1_A PWM generator 1 time stamp A’s shadow register. (R/W) (re PW M _G se rv ed ) EN 1_ B Register 13.32: PWM_GEN1_TSTMP_B_REG (0x007c) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_GEN1_B PWM generator 1 time stamp B’s shadow register. (R/W) Espressif Systems 335 ESP32 Technical Reference Manual V2.0 13. MCPWM EL L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 7 6 0 _G EN 1_ T0 EN 1_ M _G PW M PW M PW 10 CF G _S _S E T1 EN 1_ _G d) ve (re se r 31 4 0 _U P M ET HO D Register 13.33: PWM_GEN1_CFG0_REG (0x0080) 3 0 0 Reset PWM_GEN1_T1_SEL Source selection for PWM generator1 event_t1, taking effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W) PWM_GEN1_T0_SEL Source selection for PWM generator1 event_t0, taking effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W) PWM_GEN1_CFG_UPMETHOD Updating method for PWM generator1’s active register of configuration. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync. bit3: disable the update. (R/W) Espressif Systems 336 ESP32 Technical Reference Manual V2.0 13. MCPWM PW (re s er ve d) M _G PW EN 1 M _G _B PW EN _NC IF 1 M O _G _B RC PW EN _NC E_ IF 1_ M M O A_ _G O R CE DE NC PW EN IF 1 M O _G _A_ RC NC EN E_ PW IF 1_ M O B_ RC OD M CN _G E E EN TU 1_ FO A_ RC CN E_ TU M O PW FO DE RC M _G E_ EN M O 1_ DE CN TU FO RC E_ UP M ET HO D Register 13.34: PWM_GEN1_FORCE_REG (0x0084) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 11 0 10 0 9 8 0 7 6 0 5 0 0x20 Reset PWM_GEN1_B_NCIFORCE_MODE Non-continuous immediate software-force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN1_B_NCIFORCE Trigger of non-continuous immediate software-force event for PWM1B; a toggle will trigger a force event. (R/W) PWM_GEN1_A_NCIFORCE_MODE Non-continuous immediate software-force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN1_A_NCIFORCE Trigger of non-continuous immediate software-force event for PWM1A; a toggle will trigger a force event. (R/W) PWM_GEN1_B_CNTUFORCE_MODE Continuous software-force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN1_A_CNTUFORCE_MODE Continuous software-force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN1_CNTUFORCE_UPMETHOD Updating method for continuous software force of PWM generator1. When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: TEA; when bit3 is set to 1: TEB; when bit4 is set to 1: sync; when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer’s value equals to that of register A/B). (R/W) Espressif Systems 337 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 24 0 0 0 0 0 0 0 23 _G EN 1_ A_ M DT _G 1 EN PW 1_ A_ M DT _G 0 EN PW 1_ A M _D _G TE EN B PW 1_ A_ M DT _G EA EN PW 1_ A M _D _G TE EN P PW 1_ A M _D _G TE EN Z PW 1_ A_ M UT _G 1 EN PW 1_ A_ M UT _G 0 EN PW 1_ A M _U _G TE EN B PW 1_ A_ M UT _G EA EN PW 1_ A M _U _G TE EN P 1_ A_ UT EZ PW (re PW se M rv ed ) Register 13.35: PWM_GEN1_A_REG (0x0088) 22 0 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 0 5 4 0 3 2 0 1 0 0 Reset PWM_GEN1_A_DT1 Action on PWM1A triggered by event_t1 when the timer decreases. 0: no change, 1: low, 2: high, 3: toggle. (R/W) PWM_GEN1_A_DT0 Action on PWM1A triggered by event_t0 when the timer decreases. (R/W) PWM_GEN1_A_DTEB Action on PWM1A triggered by event TEB when the timer decreases. (R/W) PWM_GEN1_A_DTEA Action on PWM1A triggered by event TEA when the timer decreases. (R/W) PWM_GEN1_A_DTEP Action on PWM1A triggered by event TEP when the timer decreases. (R/W) PWM_GEN1_A_DTEZ Action on PWM1A triggered by event TEZ when the timer decreases. (R/W) PWM_GEN1_A_UT1 Action on PWM1A triggered by event_t1 when the timer increases. (R/W) PWM_GEN1_A_UT0 Action on PWM1A triggered by event_t0 when the timer increases. (R/W) PWM_GEN1_A_UTEB Action on PWM1A triggered by event TEB when the timer increases. (R/W) PWM_GEN1_A_UTEA Action on PWM1A triggered by event TEA when the timer increases. (R/W) PWM_GEN1_A_UTEP Action on PWM1A triggered by event TEP when the timer increases. (R/W) PWM_GEN1_A_UTEZ Action on PWM1A triggered by event TEZ when the timer increases. (R/W) Espressif Systems 338 ESP32 Technical Reference Manual V2.0 13. MCPWM EN ) _G ed 0 0 0 0 0 0 0 23 PW PW 24 22 0 M M rv se (re 31 0 1_ B_ DT _G 1 EN PW 1_ B_ M DT _G 0 EN PW 1_ B M _D _G TE EN B PW 1_ B_ M DT _G EA EN PW 1_ B M _D _G TE EN P PW 1_ B M _D _G TE EN Z PW 1_ B_ M UT _G 1 EN PW 1_ B_ M UT _G 0 EN PW 1_ B M _U _G TE EN B PW 1_ B_ M UT _G EA EN PW 1_ B M _U _G TE EN P 1_ B_ UT EZ Register 13.36: PWM_GEN1_B_REG (0x008c) 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 0 5 4 0 3 2 0 1 0 0 Reset PWM_GEN1_B_DT1 Action on PWM1B triggered by event_t1 when the timer decreases. 0: no change, 1: low, 2: high, 3: toggle. (R/W) PWM_GEN1_B_DT0 Action on PWM1B triggered by event_t0 when the timer decreases. (R/W) PWM_GEN1_B_DTEB Action on PWM1B triggered by event TEB when the timer decreases. (R/W) PWM_GEN1_B_DTEA Action on PWM1B triggered by event TEA when the timer decreases. (R/W) PWM_GEN1_B_DTEP Action on PWM1B triggered by event TEP when the timer decreases. (R/W) PWM_GEN1_B_DTEZ Action on PWM1B triggered by event TEZ when the timer decreases. (R/W) PWM_GEN1_B_UT1 Action on PWM1B triggered by event_t1 when the timer increases. (R/W) PWM_GEN1_B_UT0 Action on PWM1B triggered by event_t0 when the timer increases. (R/W) PWM_GEN1_B_UTEB Action on PWM1B triggered by event TEB when the timer increases. (R/W) PWM_GEN1_B_UTEA Action on PWM1B triggered by event TEA when the timer increases. (R/W) PWM_GEN1_B_UTEP Action on PWM1B triggered by event TEP when the timer increases. (R/W) PWM_GEN1_B_UTEZ Action on PWM1B triggered by event TEZ when the timer increases. (R/W) Espressif Systems 339 ESP32 Technical Reference Manual V2.0 13. MCPWM (re PW se rv ed ) M PW _D M T1 PW _D _C M T1 LK PW _D _B _S M T1 _O EL PW _D _A UT M T1 _O BY PW _D _F UT PA M T1 ED BY SS PW _D _R _O PA M T1 ED UT SS PW _D _F _O INV M T1 ED U E PW _D _R _IN TIN RT V M T1 ED S E PW _D _B _IN EL RT _ M T1_ OU SE _D A T L T1 _O SW _D UT A EB SW P PW _M A M _D O P DE T1 _R ED _U PM PW ET HO M _D D T1 _F ED _U PM ET HO D Register 13.37: PWM_DT1_CFG_REG (0x0090) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 18 17 16 15 14 13 12 11 10 9 8 0 0 1 1 0 0 0 0 0 0 0 7 4 0 3 0 0 Reset PWM_DT1_CLK_SEL Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk. (R/W) PWM_DT1_B_OUTBYPASS S0 in Table 52. (R/W) PWM_DT1_A_OUTBYPASS S1 in Table 52. (R/W) PWM_DT1_FED_OUTINVERT S3 in Table 52. (R/W) PWM_DT1_RED_OUTINVERT S2 in Table 52. (R/W) PWM_DT1_FED_INSEL S5 in Table 52. (R/W) PWM_DT1_RED_INSEL S4 in Table 52. (R/W) PWM_DT1_B_OUTSWAP S7 in Table 52. (R/W) PWM_DT1_A_OUTSWAP S6 in Table 52. (R/W) PWM_DT1_DEB_MODE S8 in Table 52; dual-edge B mode. 0: FED/RED take effect on different paths separately; 1: FED (falling edge delay)/RED (rising edge delay) take effect on B path. (R/W) PWM_DT1_RED_UPMETHOD Updating method for RED active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) PWM_DT1_FED_UPMETHOD Updating method for FED active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) (re se PW M rv ed _D T ) 1_ FE D Register 13.38: PWM_DT1_FED_CFG_REG (0x0094) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_DT1_FED Shadow register for FED. (R/W) Espressif Systems 340 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se PW M rv ed _D T ) 1_ RE D Register 13.39: PWM_DT1_RED_CFG_REG (0x0098) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_DT1_RED Shadow register for RED. (R/W) (re se r ve d) PW M PW _C M AR _C R AR IER RI 1_ ER IN PW 1_ _IN M O VE _C UT R AR _I T NV RI ER ER 1_ T O PW SH M W _C TH AR RI ER 1_ DU PW TY M _C AR RI ER PW 1_ M PR _C ES AR CA RI ER LE 1_ EN Register 13.40: PWM_CARRIER1_CFG_REG (0x009c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 0 0 0 11 8 0 7 5 0 4 1 0 0 0 Reset PWM_CARRIER1_IN_INVERT When set, invert the input of PWM1A and PWM1B for this submodule. (R/W) PWM_CARRIER1_OUT_INVERT When set, invert the output of PWM1A and PWM1B for this submodule. (R/W) PWM_CARRIER1_OSHWTH Width of the first pulse in number of periods of the carrier. (R/W) PWM_CARRIER1_DUTY Carrier duty selection. Duty = PWM_CARRIER1_DUTY/8. (R/W) PWM_CARRIER1_PRESCALE PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1). (R/W) PWM_CARRIER1_EN When set, carrier1 function is enabled. When cleared, carrier1 is bypassed. (R/W) Espressif Systems 341 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 24 0 0 0 0 0 0 0 23 _F H1 _B _O M ST _F _U H1 _B PW _ O M ST _F _D H1 _B PW _ CB M _F C_ H1 U _B PW _C M BC _F H1 _D _ PW A_ O M ST _F _U H1 _A PW _O M ST _F _D H1 _A PW _C M BC _F _U PW H1 _A M _ PW _F CB M H1 C_ PW _F _F D M H1_ 0_O PW _F F S M H1 1_ T PW _F _F OS M H1 2_ T PW _F _S OS M H1 W T PW _F _F _OS M H1 0_ T PW _F _F CB M H1_ 1_C C _F F B H1 2_ C _S CB W C _C BC 22 0 PW PW (re s M er ve d) Register 13.41: PWM_FH1_CFG0_REG (0x00a0) 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset PWM_FH1_B_OST_U One-shot mode action on PWM1B when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_B_OST_D One-shot mode action on PWM1B when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_B_CBC_U Cycle-by-cycle mode action on PWM1B when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_B_CBC_D Cycle-by-cycle mode action on PWM1B when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_A_OST_U One-shot mode action on PWM1A when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_A_OST_D One-shot mode action on PWM1A when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_A_CBC_U Cycle-by-cycle mode action on PWM1A when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_A_CBC_D Cycle-by-cycle mode action on PWM1A when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH1_F0_OST Enable event_f0 to trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH1_F1_OST Enable event_f1 to trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH1_F2_OST Enable event_f2 to trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH1_SW_OST Enable the register for software-forced one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH1_F0_CBC Enable event_f0 to trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH1_F1_CBC Enable event_f1 to trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH1_F2_CBC Enable event_f2 to will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH1_SW_CBC Enable the register for software-forced cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) Espressif Systems 342 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed ) PW M PW _F M H1_ _F F PW H1 OR _F C M O E_ _F RC O S PW H1 _C E_C T M B BC _F H1 CP _C U L LR SE _O ST Register 13.42: PWM_FH1_CFG1_REG (0x00a4) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 0 0 0 2 1 0 0 0 Reset PWM_FH1_FORCE_OST A toggle (software negation of this bit’s value) triggers a one-shot mode action. (R/W) PWM_FH1_FORCE_CBC A toggle triggers a cycle-by-cycle mode action. (R/W) PWM_FH1_CBCPULSE The cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ; when bit1 is set to 1: TEP. (R/W) PWM_FH1_CLR_OST A toggle will clear on-going one-shot mode action. (R/W) (re se rv ed ) PW M PW _F M H1_ _F O H1 ST _C _O BC N _O N Register 13.43: PWM_FH1_STATUS_REG (0x00a8) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset PWM_FH1_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO) PWM_FH1_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going. (RO) Espressif Systems 343 ESP32 Technical Reference Manual V2.0 13. MCPWM (re PW se rv ed ) M PW _G M EN _ G 2_ EN B_ 2_ SH A_ D PW SH W_ M D W FU _G EN _F LL 2_ UL B_ L UP M ET PW HO M D _G EN 2_ A_ UP M ET HO D Register 13.44: PWM_GEN2_STMP_CFG_REG (0x00ac) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 9 8 0 0 0 7 4 3 0 0 0 Reset PWM_GEN2_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 2 time stamp B’s shadow register is filled and to be transferred to time stamp B’s active register. If cleared, time stamp B’s active register has been updated with shadow register’s latest value. (RO) PWM_GEN2_A_SHDW_FULL Set and reset by hardware. If set, PWM generator 2 time stamp A’s shadow register is filled and to be transferred to time stamp A’s active register. If cleared, time stamp A’s active register has been updated with shadow register’s latest value. (RO) PWM_GEN2_B_UPMETHOD Updating method for PWM generator 2 time stamp B’s active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) PWM_GEN2_A_UPMETHOD Updating method for PWM generator 2 time stamp A’s active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) (re PW se r M _G ve d) EN 2_ A Register 13.45: PWM_GEN2_TSTMP_A_REG (0x00b0) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_GEN2_A PWM generator 2 time stamp A’s shadow register. (R/W) (re PW M _G se rv ed ) EN 2_ B Register 13.46: PWM_GEN2_TSTMP_B_REG (0x00b4) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_GEN2_B PWM generator 2 time stamp B’s shadow register. (R/W) Espressif Systems 344 ESP32 Technical Reference Manual V2.0 13. MCPWM EL L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 7 6 0 _G EN 2_ T0 EN 2_ M _G PW M PW M PW 10 CF G _S _S E T1 EN 2_ _G d) ve (re se r 31 4 0 _U P M ET HO D Register 13.47: PWM_GEN2_CFG0_REG (0x00b8) 3 0 0 Reset PWM_GEN2_T1_SEL Source selection for PWM generator2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W) PWM_GEN2_T0_SEL Source selection for PWM generator2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W) PWM_GEN2_CFG_UPMETHOD Updating method for PWM generator2’s active register of configuration. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync. bit3: disable the update. (R/W) Espressif Systems 345 ESP32 Technical Reference Manual V2.0 13. MCPWM PW (re s er ve d) M _G PW EN 2 M _G _B PW EN _NC IF 2 M O _G _B RC PW EN _NC E_ IF 2_ M M O A_ _G O R CE DE NC PW EN IF 2 M O _G _A_ RC NC EN E_ PW IF 2_ M O B_ RC OD M CN _G E E EN TU 2_ FO A_ RC CN E_ TU M O PW FO DE RC M _G E_ EN M O 2_ DE CN TU FO RC E_ UP M ET HO D Register 13.48: PWM_GEN2_FORCE_REG (0x00bc) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 11 0 10 0 9 8 0 7 6 0 5 0 0x20 Reset PWM_GEN2_B_NCIFORCE_MODE Non-continuous immediate software-force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN2_B_NCIFORCE Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. (R/W) PWM_GEN2_A_NCIFORCE_MODE Non-continuous immediate software-force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN2_A_NCIFORCE Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. (R/W) PWM_GEN2_B_CNTUFORCE_MODE Continuous software-force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN2_A_CNTUFORCE_MODE Continuous software-force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled. (R/W) PWM_GEN2_CNTUFORCE_UPMETHOD Updating method for continuous software force of PWM generator2. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: TEA; when bit3 is set to 1: TEB; when bit4 is set to 1: sync; when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer value equals that of register A/B.) (R/W) Espressif Systems 346 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 24 0 0 0 0 0 0 0 23 _G EN 2_ A_ M DT _G 1 EN PW 2_ A_ M DT _G 0 EN PW 2_ A M _D _G TE EN B PW 2_ A_ M DT _G EA EN PW 2_ A M _D _G TE EN P PW 2_ A M _D _G TE EN Z PW 2_ A_ M UT _G 1 EN PW 2_ A_ M UT _G 0 EN PW 2_ A M _U _G TE EN B PW 2_ A_ M UT _G EA EN PW 2_ A M _U _G TE EN P 2_ A_ UT EZ PW (re PW se M rv ed ) Register 13.49: PWM_GEN2_A_REG (0x00c0) 22 0 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 0 5 4 0 3 2 0 1 0 0 Reset PWM_GEN2_A_DT1 Action on PWM2A triggered by event_t1 when the timer decreases. 0: no change, 1: low, 2: high, 3: toggle. (R/W) PWM_GEN2_A_DT0 Action on PWM2A triggered by event_t0 when the timer decreases. (R/W) PWM_GEN2_A_DTEB Action on PWM2A triggered by event TEB when the timer decreases. (R/W) PWM_GEN2_A_DTEA Action on PWM2A triggered by event TEA when the timer decreases. (R/W) PWM_GEN2_A_DTEP Action on PWM2A triggered by event TEP when the timer decreases. (R/W) PWM_GEN2_A_DTEZ Action on PWM2A triggered by event TEZ when the timer decreases. (R/W) PWM_GEN2_A_UT1 Action on PWM2A triggered by event_t1 when the timer increases. (R/W) PWM_GEN2_A_UT0 Action on PWM2A triggered by event_t0 when the timer increases. (R/W) PWM_GEN2_A_UTEB Action on PWM2A triggered by event TEB when the timer increases. (R/W) PWM_GEN2_A_UTEA Action on PWM2A triggered by event TEA when the timer increases. (R/W) PWM_GEN2_A_UTEP Action on PWM2A triggered by event TEP when the timer increases. (R/W) PWM_GEN2_A_UTEZ Action on PWM2A triggered by event TEZ when the timer increases. (R/W) Espressif Systems 347 ESP32 Technical Reference Manual V2.0 13. MCPWM EN ) _G ed 0 0 0 0 0 0 0 23 PW PW 24 22 0 M M rv se (re 31 0 2_ B_ DT _G 1 EN PW 2_ B_ M DT _G 0 EN PW 2_ B M _D _G TE EN B PW 2_ B_ M DT _G EA EN PW 2_ B M _D _G TE EN P PW 2_ B M _D _G TE EN Z PW 2_ B_ M UT _G 1 EN PW 2_ B_ M UT _G 0 EN PW 2_ B M _U _G TE EN B PW 2_ B_ M UT _G EA EN PW 2_ B M _U _G TE EN P 2_ B_ UT EZ Register 13.50: PWM_GEN2_B_REG (0x00c4) 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 0 5 4 0 3 2 0 1 0 0 Reset PWM_GEN2_B_DT1 Action on PWM2B triggered by event_t1 when the timer decreases. 0: no change, 1: low, 2: high, 3: toggle. (R/W) PWM_GEN2_B_DT0 Action on PWM2B triggered by event_t0 when the timer decreases. (R/W) PWM_GEN2_B_DTEB Action on PWM2B triggered by event TEB when the timer decreases. (R/W) PWM_GEN2_B_DTEA Action on PWM2B triggered by event TEA when the timer decreases. (R/W) PWM_GEN2_B_DTEP Action on PWM2B triggered by event TEP when the timer decreases. (R/W) PWM_GEN2_B_DTEZ Action on PWM2B triggered by event TEZ when the timer decreases. (R/W) PWM_GEN2_B_UT1 Action on PWM2B triggered by event_t1 when the timer increases. (R/W) PWM_GEN2_B_UT0 Action on PWM2B triggered by event_t0 when the timer increases. (R/W) PWM_GEN2_B_UTEB Action on PWM2B triggered by event TEB when the timer increases. (R/W) PWM_GEN2_B_UTEA Action on PWM2B triggered by event TEA when the timer increases. (R/W) PWM_GEN2_B_UTEP Action on PWM2B triggered by event TEP when the timer increases. (R/W) PWM_GEN2_B_UTEZ Action on PWM2B triggered by event TEZ when the timer increases. (R/W) Espressif Systems 348 ESP32 Technical Reference Manual V2.0 13. MCPWM (re PW se rv ed ) M PW _D M T2 PW _D _C M T2 LK PW _D _B _S M T2 _O EL PW _D _A UT M T2 _O BY PW _D _F UT PA M T2 ED BY SS PW _D _R _O PA M T2 ED UT SS PW _D _F _O INV M T2 ED U E PW _D _R _IN TIN RT V M T2 ED S E PW _D _B _IN EL RT _ M T2_ OU SE _D A T L T2 _O SW _D UT A EB SW P PW _M A M _D O P DE T2 _R ED _U PM PW ET HO M _D D T2 _F ED _U PM ET HO D Register 13.51: PWM_DT2_CFG_REG (0x00c8) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 18 17 16 15 14 13 12 11 10 9 8 0 0 1 1 0 0 0 0 0 0 0 7 4 0 3 0 0 Reset PWM_DT2_CLK_SEL Dead time generator 1 clock selection. 0: PWM_clk; 1: PT_clk. (R/W) PWM_DT2_B_OUTBYPASS S0 in Table 52. (R/W) PWM_DT2_A_OUTBYPASS S1 in Table 52. (R/W) PWM_DT2_FED_OUTINVERT S3 in Table 52. (R/W) PWM_DT2_RED_OUTINVERT S2 in Table 52. (R/W) PWM_DT2_FED_INSEL S5 in Table 52. (R/W) PWM_DT2_RED_INSEL S4 in Table 52. (R/W) PWM_DT2_B_OUTSWAP S7 in Table 52. (R/W) PWM_DT2_A_OUTSWAP S6 in Table 52. (R/W) PWM_DT2_DEB_MODE S8 in Table 52, dual-edge B mode, 0: FED/RED take effect on different path separately, 1: FED/RED take effect on B path. (R/W) PWM_DT2_RED_UPMETHOD Updating method for RED (rising edge delay) active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) PWM_DT2_FED_UPMETHOD Updating method for FED (falling edge delay) active register. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) (re se PW M rv ed _D T ) 2_ FE D Register 13.52: PWM_DT2_FED_CFG_REG (0x00cc) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_DT2_FED Shadow register for FED. (R/W) Espressif Systems 349 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se PW M rv ed _D T ) 2_ RE D Register 13.53: PWM_DT2_RED_CFG_REG (0x00d0) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 Reset PWM_DT2_RED Shadow register for RED. (R/W) (re se r ve d) PW M PW _C M AR _C R AR IER RI 2_ ER IN PW 2_ _IN M O VE _C UT R AR _I T NV RI ER ER 2_ T O PW SH M W _C TH AR RI ER 2_ DU PW TY M _C AR RI ER PW 2_ M PR _C ES AR CA RI ER LE 2_ EN Register 13.54: PWM_CARRIER2_CFG_REG (0x00d4) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 0 0 0 11 8 0 7 5 0 4 1 0 0 0 Reset PWM_CARRIER2_IN_INVERT When set, invert the input of PWM2A and PWM2B for this submodule. (R/W) PWM_CARRIER2_OUT_INVERT When set, invert the output of PWM2A and PWM2B for this submodule. (R/W) PWM_CARRIER2_OSHWTH Width of the first pulse in number of periods of the carrier. (R/W) PWM_CARRIER2_DUTY Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8. (R/W) PWM_CARRIER2_PRESCALE PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1). (R/W) PWM_CARRIER2_EN When set, carrier2 function is enabled. When cleared, carrier2 is bypassed. (R/W) Espressif Systems 350 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 24 0 0 0 0 0 0 0 23 _F H2 _B _O M ST _F _U H2 _B PW _ O M ST _F _D H2 _B PW _ CB M _F C_ H2 U _B PW _C M BC _F H2 _D _ PW A_ O M ST _F _U H2 _A PW _O M ST _F _D H2 _A PW _C M BC _F _U PW H2 _A M _ PW _F CB M H2 C_ PW _F _F D M H2_ 0_O PW _F F S M H2 1_ T PW _F _F OS M H2 2_ T PW _F _S OS M H2 W T PW _F _F _OS M H2 0_ T PW _F _F CB M H2_ 1_C C _F F B H2 2_ C _S CB W C _C BC 22 0 PW PW (re s M er ve d) Register 13.55: PWM_FH2_CFG0_REG (0x00d8) 21 20 0 19 18 0 17 16 0 15 14 0 13 12 0 11 10 0 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset PWM_FH2_B_OST_U One-shot mode action on PWM2B when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_B_OST_D One-shot mode action on PWM2B when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_B_CBC_U Cycle-by-cycle mode action on PWM2B when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_B_CBC_D Cycle-by-cycle mode action on PWM2B when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_A_OST_U One-shot mode action on PWM2A when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_A_OST_D One-shot mode action on PWM2A when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_A_CBC_U Cycle-by-cycle mode action on PWM2A when a fault event occurs and the timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_A_CBC_D Cycle-by-cycle mode action on PWM2A when a fault event occurs and the timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W) PWM_FH2_F0_OST event_f0 will trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH2_F1_OST event_f1 will trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH2_F2_OST event_f2 will trigger one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH2_SW_OST Enable register for software-forced one-shot mode action. 0: disable, 1: enable. (R/W) PWM_FH2_F0_CBC event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH2_F1_CBC event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH2_F2_CBC event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH2_SW_CBC Enable register for software-forced cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) Espressif Systems 351 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed ) PW M PW _F M H2_ _F F PW H2 OR _F C M O E_ _F RC O S PW H2 _C E_C T M B BC _F H2 CP _C U L LR SE _O ST Register 13.56: PWM_FH2_CFG1_REG (0x00dc) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 0 0 0 2 1 0 0 0 Reset PWM_FH2_FORCE_OST A toggle (software negation of this bit’s value) triggers a one-shot mode action. (R/W) PWM_FH2_FORCE_CBC A toggle triggers a cycle-by-cycle mode action. (R/W) PWM_FH2_CBCPULSE The cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ; when bit1 is set to 1:TEP. (R/W) PWM_FH2_CLR_OST A toggle will clear on-going one-shot mode action. (R/W) (re se rv ed ) PW M PW _F M H2_ _F O H2 ST _C _O BC N _O N Register 13.57: PWM_FH2_STATUS_REG (0x00e0) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset PWM_FH2_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO) PWM_FH2_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going. (RO) Espressif Systems 352 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed ) PW M PW _E M VE PW _E NT M VE _F PW _E NT 2 M VE _F PW _F NT 1 M 2_ _F PW _F PO 0 M 1_ LE PW _F PO M 0_ LE PW _F PO M 2_ LE PW _F EN M 1_E _F N 0_ EN Register 13.58: PWM_FAULT_DETECT_REG (0x00e4) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Reset PWM_EVENT_F2 Set and reset by hardware. If set, event_f2 is on-going. (RO) PWM_EVENT_F1 Set and reset by hardware. If set, event_f1 is on-going. (RO) PWM_EVENT_F0 Set and reset by hardware. If set, event_f0 is on-going. (RO) PWM_F2_POLE Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high. (R/W) PWM_F1_POLE Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high. (R/W) PWM_F0_POLE Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high. (R/W) PWM_F2_EN Set to enable the generation of event_f2. (R/W) PWM_F1_EN Set to enable the generation of event_f1. (R/W) PWM_F0_EN Set to enable the generation of event_f0. (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 P_ _C A M PW 0 0 0 0 0 0 0 0 0 0 0 6 5 0 0 PW M ed ) (re se rv 31 0 SY NC _C _S AP W _S PW YN M CI PW _C _S M AP EL _C _S AP YN _T C IM I_E ER N _E N Register 13.59: PWM_CAP_TIMER_CFG_REG (0x00e8) 4 2 0 1 0 0 0 Reset PWM_CAP_SYNC_SW Set this bit to force a capture timer sync; the capture timer is loaded with the value in the phase register. (WO) PWM_CAP_SYNCI_SEL Capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix. (R/W) PWM_CAP_SYNCI_EN When set, the capture timer sync is enabled. (R/W) PWM_CAP_TIMER_EN When set, the capture timer incrementing under APB_clk is enabled. (R/W) Espressif Systems 353 ESP32 Technical Reference Manual V2.0 13. MCPWM Register 13.60: PWM_CAP_TIMER_PHASE_REG (0x00ec) 31 0 0 Reset PWM_CAP_TIMER_PHASE_REG Phase value for the capture timer sync operation. (R/W) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 0 0 0 M _C PW AP 0 M _C _M AP OD E 0_ EN ES 0_ PR AP _C M PW PW (re PW se rv ed ) M PW _C M AP _C 0_ AP SW 0_ IN _I NV E RT CA LE Register 13.61: PWM_CAP_CH0_CFG_REG (0x00f0) 10 3 2 0 1 0 0 0 Reset PWM_CAP0_SW When set, a software-forced capture on channel 0 is triggered. (WO) PWM_CAP0_IN_INVERT When set, CAP0 form GPIO matrix is inverted before prescaling. (R/W) PWM_CAP0_PRESCALE Prescaling value on the positive edge of CAP0. Prescaling value = PWM_CAP0_PRESCALE + 1. (R/W) PWM_CAP0_MODE Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge; When bit1 is set to 1: enable capture on the positive edge. (R/W) PWM_CAP0_EN When set, capture on channel 0 is enabled. (R/W) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 0 0 0 10 3 0 PW M _C PW AP 1 M _C _M AP OD E 1_ EN _C AP 1_ P M PW (re se rv e d) PW M PW _C M AP _C 1_ AP SW 1_ IN _I N VE R T RE SC AL E Register 13.62: PWM_CAP_CH1_CFG_REG (0x00f4) 2 1 0 0 0 Reset PWM_CAP1_SW Write 1 will trigger a software-forced capture on channel 1. (WO) PWM_CAP1_IN_INVERT When set, CAP1 form GPIO matrix is inverted before prescaling. (R/W) PWM_CAP1_PRESCALE Value of prescale on the positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1. (R/W) PWM_CAP1_MODE Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge; When bit1 is set to 1: enable capture on the positive edge. (R/W) PWM_CAP1_EN When set, capture on channel 1 is enabled. (R/W) Espressif Systems 354 ESP32 Technical Reference Manual V2.0 13. MCPWM 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 0 0 0 M _C PW AP 2 M _C _M AP OD E 2_ EN ES 2_ PR AP _C M PW PW (re PW se rv ed ) M PW _C M AP _C 2_ AP SW 2_ IN _I NV E RT CA LE Register 13.63: PWM_CAP_CH2_CFG_REG (0x00f8) 10 3 0 2 1 0 0 0 Reset PWM_CAP2_SW When set, a software-forced capture on channel 2 is triggered. (WO) PWM_CAP2_IN_INVERT When set, CAP2 form GPIO matrix is inverted before prescaling. (R/W) PWM_CAP2_PRESCALE Prescaling value on the positive edge of CAP2. Prescaling value = PWM_CAP2_PRESCALE + 1. (R/W) PWM_CAP2_MODE Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge; when bit1 is set to 1: enable capture on the positive edge. (R/W) PWM_CAP2_EN When set, capture on channel 2 is enabled. (R/W) Register 13.64: PWM_CAP_CH0_REG (0x00fc) 31 0 0 Reset PWM_CAP_CH0_REG Value of the last capture on channel 0. (RO) Register 13.65: PWM_CAP_CH1_REG (0x0100) 31 0 0 Reset PWM_CAP_CH1_REG Value of the last capture on channel 1. (RO) Register 13.66: PWM_CAP_CH2_REG (0x0104) 31 0 0 Reset PWM_CAP_CH2_REG Value of the last capture on channel 2. (RO) Espressif Systems 355 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed ) PW M PW _C M AP PW _C 2_ M AP ED _C 1_ G E AP ED 0_ GE ED G E Register 13.67: PWM_CAP_STATUS_REG (0x0108) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 0 Reset PWM_CAP2_EDGE Edge of the last capture trigger on channel 2. 0: posedge; 1: negedge. (RO) PWM_CAP1_EDGE Edge of the last capture trigger on channel 1. 0: posedge; 1: negedge. (RO) PWM_CAP0_EDGE Edge of the last capture trigger on channel 0. 0: posedge; 1: negedge. (RO) (re se rv ed ) PW M PW _O M P2 PW _O _F M P OR PW _O 2_U CE M P P _ PW _O 1_F _EN UP M P OR PW _O 1_U CE M P P _ PW _O 0_F _EN UP M P OR PW _G 0_U CE M LO P_ _U _G B EN P LO AL_ BA FO L_ RC UP E _E _UP N Register 13.68: PWM_UPDATE_CFG_REG (0x010c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 0 1 Reset PWM_OP2_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of active registers in PWM operator 2. (R/W) PWM_OP2_UP_EN When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled (R/W) PWM_OP1_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of active registers in PWM operator 1. (R/W) PWM_OP1_UP_EN When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled. (R/W) PWM_OP0_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of active registers in PWM operator 0. (R/W) PWM_OP0_UP_EN When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled. (R/W) PWM_GLOBAL_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of all active registers in the MCPWM module. (R/W) PWM_GLOBAL_UP_EN The global enable of update of all active registers in the MCPWM module. (R/W) Espressif Systems 356 ESP32 Technical Reference Manual V2.0 13. MCPWM IN (re s er ve d T_ ) C IN A T_ P2 IN CA _IN T_ P1 T_ IN CA _IN EN T_ P0 T_ A IN FH _IN EN T_ 2_ T_ A IN FH OS EN T_ 1_ T_ A IN FH OS INT T_ 0_ T_ _E IN FH OS INT NA T_ 2_ T_ _E IN FH CB INT NA T_ 1_ C_ _E IN FH CB INT NA T_ 0_ C_ _E IN OP CB INT NA T_ 2_ C_ _E IN OP TEB INT NA T_ 1_ _ _E IN OP TEB INT NA T_ 0_ _ _E IN OP TEB INT NA T_ 2_ _ _E IN OP TEA INT NA T_ 1_ _ _E IN OP TEA INT NA T_ 0_ _ _E IN FAU TEA INT NA T _ L _ _E IN FAU T2_ INT NA T _ L C _E L IN FAU T1_ R_ NA T_ L C IN L T F IN AU 0_ R_ T_E T_ L C IN N L IN FAU T2_ R_ T_E A T_ L IN IN N IN FAU T1_ T_E T_E A T_ L IN N N IN TIM T0_ T_E A A T_ E IN N IN TIM R2_ T_E A T_ E TE N IN TIM R1_ P_ A T_ E TE IN IN TIM R0_ P_ T_E T _ E T E IN N IN TIM R2_ P_ T_E A T _ E TE IN N IN TIM R1_ Z_ T_E A T_ E TE IN N IN TIM R0_ Z_ T_E A T_ E TE IN N A IN TIM R2_ Z_ T_E T _ E S IN N TI R1 TO T_ A M _ P EN ER ST _I A 0_ OP NT ST _I _E O NT NA P_ _E IN N T_ A EN A Register 13.69: INT_ENA_PWM_REG (0x0110) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset INT_CAP2_INT_ENA The enable bit for the interrupt triggered by capture on channel 2. (R/W) INT_CAP1_INT_ENA The enable bit for the interrupt triggered by capture on channel 1. (R/W) INT_CAP0_INT_ENA The enable bit for the interrupt triggered by capture on channel 0. (R/W) INT_FH2_OST_INT_ENA The enable bit for the interrupt triggered by a one-shot mode action on PWM2. (R/W) INT_FH1_OST_INT_ENA The enable bit for the interrupt triggered by a one-shot mode action on PWM0. (R/W) INT_FH0_OST_INT_ENA The enable bit for the interrupt triggered by a one-shot mode action on PWM0. (R/W) INT_FH2_CBC_INT_ENA The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. (R/W) INT_FH1_CBC_INT_ENA The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. (R/W) INT_FH0_CBC_INT_ENA The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. (R/W) INT_OP2_TEB_INT_ENA The enable bit for the interrupt triggered by a PWM operator 2 TEB event (R/W) INT_OP1_TEB_INT_ENA The enable bit for the interrupt triggered by a PWM operator 1 TEB event (R/W) INT_OP0_TEB_INT_ENA The enable bit for the interrupt triggered by a PWM operator 0 TEB event (R/W) INT_OP2_TEA_INT_ENA The enable bit for the interrupt triggered by a PWM operator 2 TEA event (R/W) INT_OP1_TEA_INT_ENA The enable bit for the interrupt triggered by a PWM operator 1 TEA event (R/W) INT_OP0_TEA_INT_ENA The enable bit for the interrupt triggered by a PWM operator 0 TEA event (R/W) INT_FAULT2_CLR_INT_ENA The enable bit for the interrupt triggered when event_f2 ends. (R/W) INT_FAULT1_CLR_INT_ENA The enable bit for the interrupt triggered when event_f1 ends. (R/W) INT_FAULT0_CLR_INT_ENA The enable bit for the interrupt triggered when event_f0 ends. (R/W) INT_FAULT2_INT_ENA The enable bit for the interrupt triggered when event_f2 starts. (R/W) INT_FAULT1_INT_ENA The enable bit for the interrupt triggered when event_f1 starts. (R/W) INT_FAULT0_INT_ENA The enable bit for the interrupt triggered when event_f0 starts. (R/W) INT_TIMER2_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 2 TEP event. (R/W) INT_TIMER1_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 1 TEP event. (R/W) INT_TIMER0_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 0 TEP event. (R/W) INT_TIMER2_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. (R/W) INT_TIMER1_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. (R/W) INT_TIMER0_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. (R/W) INT_TIMER2_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 2 stops. (R/W) INT_TIMER1_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 1 stops. (R/W) INT_TIMER0_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 0 stops. (R/W) Espressif Systems 357 ESP32 Technical Reference Manual V2.0 13. MCPWM (re se rv ed IN T_ ) IN CA T_ P2 IN CA _IN T_ P1 T_ IN CA _IN RA T_ P0 T_ W IN FH _IN RA T_ 2_ T_ W IN FH OS RA T_ 1_ T_ W IN FH OS INT T_ 0_ T_ _R IN FH OS INT AW T_ 2_ T_ _R IN FH CB INT AW T_ 1_ C_ _R IN FH CB INT AW T_ 0_ C_ _R IN OP CB INT AW T_ 2_ C_ _R IN OP TEB INT AW T_ 1_ _ _R IN OP TEB INT AW T_ 0_ _ _R IN OP TEB INT AW T_ 2_ _ _R IN OP TEA INT AW T_ 1_ _ _R IN OP TEA INT AW T_ 0_ _ _R IN FAU TEA INT AW T _ L _ _R IN FAU T2_ INT AW T _ L C _R L IN FAU T1_ R_ AW T_ L C IN L T F IN AU 0_ R_ T_R T_ L C IN A L IN FAU T2_ R_ T_R W T_ L IN IN A IN FAU T1_ T_R T_R W T_ L IN A A IN TIM T0_ T_R W W T_ E IN A IN TIM R2_ T_R W T_ E TE A IN TIM R1_ P_ W T_ E TE IN IN TIM R0_ P_ T_R T _ E T E IN A IN TIM R2_ P_ T_R W T _ E TE IN A IN TIM R1_ Z_ T_R W T_ E TE IN A IN TIM R0_ Z_ T_R W T_ E TE IN A W IN TIM R2_ Z_ T_R T _ E S IN A TI R1 TO T_ W M _ P R ER ST _I AW 0_ OP NT ST _I _R O NT AW P_ _R IN A T_ W RA W Register 13.70: INT_RAW_PWM_REG (0x0114) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset INT_CAP2_INT_RAW The raw status bit for the interrupt triggered by capture on channel 2. (RO) INT_CAP1_INT_RAW The raw status bit for the interrupt triggered by capture on channel 1. (RO) INT_CAP0_INT_RAW The raw status bit for the interrupt triggered by capture on channel 0. (RO) INT_FH2_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. (RO) INT_FH1_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. (RO) INT_FH0_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. (RO) INT_FH2_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. (RO) INT_FH1_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. (RO) INT_FH0_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. (RO) INT_OP2_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 2 TEB event. (RO) INT_OP1_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 1 TEB event. (RO) INT_OP0_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 0 TEB event. (RO) INT_OP2_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 2 TEA event. (RO) INT_OP1_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 1 TEA event. (RO) INT_OP0_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 0 TEA event. (RO) INT_FAULT2_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f2 ends. (RO) INT_FAULT1_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f1 ends. (RO) INT_FAULT0_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f0 ends. (RO) INT_FAULT2_INT_RAW The raw status bit for the interrupt triggered when event_f2 starts. (RO) INT_FAULT1_INT_RAW The raw status bit for the interrupt triggered when event_f1 starts. (RO) INT_FAULT0_INT_RAW The raw status bit for the interrupt triggered when event_f0 starts. (RO) INT_TIMER2_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. (RO) INT_TIMER1_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. (RO) INT_TIMER0_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. (RO) INT_TIMER2_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. (RO) INT_TIMER1_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. (RO) INT_TIMER0_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. (RO) INT_TIMER2_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 2 stops. (RO) INT_TIMER1_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 1 stops. (RO) INT_TIMER0_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 0 stops. (RO) Espressif Systems 358 ESP32 Technical Reference Manual V2.0 13. MCPWM IN (re se rv ed T_ ) IN CA T_ P2 IN CA _IN T_ P1 T_ IN CA _IN ST T_ P0 T_ IN FH _IN ST T_ 2_ T_ IN FH OS ST T_ 1_ T_ IN FH OS INT T_ 0_ T_ _S IN FH OS INT T T_ 2_ T_ _S IN FH CB INT T T_ 1_ C_ _S IN FH CB INT T T_ 0_ C_ _S IN OP CB INT T T_ 2_ C_ _S IN OP TEB INT T T_ 1_ _ _S IN OP TEB INT T T_ 0_ _ _S IN OP TEB INT T T_ 2_ _ _S IN OP TEA INT T T_ 1_ _ _S IN OP TEA INT T T_ 0_ _ _S IN FAU TEA INT T T _ L _ _S IN FAU T2_ INT T T _ L C _S L IN FAU T1_ R_ T T_ L C IN L T F IN AU 0_ R_ T_S T_ L C IN T L IN FAU T2_ R_ T_S T_ L IN IN T IN FAU T1_ T_S T_S T_ L IN T T IN TIM T0_ T_S T_ E IN T IN TIM R2_ T_S T_ E TE T IN TIM R1_ P_ T_ E TE IN IN TIM R0_ P_ T_S T _ E T E IN T IN TIM R2_ P_ T_S T _ E TE IN T IN TIM R1_ Z_ T_S T_ E TE IN T IN TIM R0_ Z_ T_S T_ E TE IN T IN TIM R2_ Z_ T_S T _ E S IN T TI R1 TO T_ M _ P ST ER ST _I 0_ OP NT ST _I _S O NT T P_ _S IN T T_ ST Register 13.71: INT_ST_PWM_REG (0x0118) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset INT_CAP2_INT_ST The masked status bit for the interrupt triggered by capture on channel 2. (RO) INT_CAP1_INT_ST The masked status bit for the interrupt triggered by capture on channel 1. (RO) INT_CAP0_INT_ST The masked status bit for the interrupt triggered by capture on channel 0. (RO) INT_FH2_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. (RO) INT_FH1_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. (RO) INT_FH0_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. (RO) INT_FH2_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. (RO) INT_FH1_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. (RO) INT_FH0_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. (RO) INT_OP2_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 2 TEB event. (RO) INT_OP1_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 1 TEB event. (RO) INT_OP0_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 0 TEB event. (RO) INT_OP2_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 2 TEA event. (RO) INT_OP1_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 1 TEA event. (RO) INT_OP0_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 0 TEA event. (RO) INT_FAULT2_CLR_INT_ST The masked status bit for the interrupt triggered when event_f2 ends. (RO) INT_FAULT1_CLR_INT_ST The masked status bit for the interrupt triggered when event_f1 ends. (RO) INT_FAULT0_CLR_INT_ST The masked status bit for the interrupt triggered when event_f0 ends. (RO) INT_FAULT2_INT_ST The masked status bit for the interrupt triggered when event_f2 starts. (RO) INT_FAULT1_INT_ST The masked status bit for the interrupt triggered when event_f1 starts. (RO) INT_FAULT0_INT_ST The masked status bit for the interrupt triggered when event_f0 starts. (RO) INT_TIMER2_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. (RO) INT_TIMER1_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. (RO) INT_TIMER0_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. (RO) INT_TIMER2_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. (RO) INT_TIMER1_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. (RO) INT_TIMER0_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. (RO) INT_TIMER2_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 2 stops. (RO) INT_TIMER1_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 1 stops. (RO) INT_TIMER0_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 0 stops. (RO) Espressif Systems 359 ESP32 Technical Reference Manual V2.0 13. MCPWM IN (re se rv ed T_ ) IN CA T_ P2 IN CA _IN T_ P1 T_ IN CA _IN CL T_ P0 T_ R IN FH _IN CL T_ 2_ T_ R IN FH OS CL T_ 1_ T_ R IN FH OS INT T_ 0_ T_ _C IN FH OS INT LR T_ 2_ T_ _C IN FH CB INT LR T_ 1_ C_ _C IN FH CB INT LR T_ 0_ C_ _C IN OP CB INT LR T_ 2_ C_ _C IN OP TEB INT LR T_ 1_ _ _C IN OP TEB INT LR T_ 0_ _ _C IN OP TEB INT LR T_ 2_ _ _C IN OP TEA INT LR T_ 1_ _ _C IN OP TEA INT LR T_ 0_ _ _C IN FAU TEA INT LR T _ L _ _C IN FAU T2_ INT LR T _ L C _C L IN FAU T1_ R_ LR T_ L C IN L T F IN AU 0_ R_ T_C T_ L C IN L L IN FAU T2_ R_ T_C R T_ L IN IN L IN FAU T1_ T_C T_C R T_ L IN L L IN TIM T0_ T_C R R T_ E IN L IN TIM R2_ T_C R T_ E TE L IN TIM R1_ P_ R T_ E TE IN IN TIM R0_ P_ T_C T _ E T E IN L R IN TIM R2_ P_ T_C T _ E TE IN L R IN TIM R1_ Z_ T_C T_ E TE IN L R IN TIM R0_ Z_ T_C T_ E TE IN L R R T IN TIM 2_ Z_ _C T _ E S IN L TI R1 TO T_ R M _ P C ER ST _I LR 0_ OP NT ST _I _C O NT LR P_ _C IN L T_ R CL R Register 13.72: INT_CLR_PWM_REG (0x011c) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset INT_CAP2_INT_CLR Set this bit to clear interrupt triggered by capture on channel 2. (WO) INT_CAP1_INT_CLR Set this bit to clear interrupt triggered by capture on channel 1. (WO) INT_CAP0_INT_CLR Set this bit to clear interrupt triggered by capture on channel 0. (WO) INT_FH2_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM2. (WO) INT_FH1_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM1. (WO) INT_FH0_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM0. (WO) INT_FH2_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on PWM2. (WO) INT_FH1_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on PWM1. (WO) INT_FH0_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on PWM0. (WO) INT_OP2_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 2 TEB event. (WO) INT_OP1_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 1 TEB event. (WO) INT_OP0_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 0 TEB event. (WO) INT_OP2_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 2 TEA event. (WO) INT_OP1_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 1 TEA event. (WO) INT_OP0_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 0 TEA event. (WO) INT_FAULT2_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f2 ends. (WO) INT_FAULT1_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f1 ends. (WO) INT_FAULT0_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f0 ends. (WO) INT_FAULT2_INT_CLR Set this bit to clear interrupt triggered when event_f2 starts. (WO) INT_FAULT1_INT_CLR Set this bit to clear interrupt triggered when event_f1 starts. (WO) INT_FAULT0_INT_CLR Set this bit to clear interrupt triggered when event_f0 starts. (WO) INT_TIMER2_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 2 TEP event. (WO) INT_TIMER1_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 1 TEP event. (WO) INT_TIMER0_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 0 TEP event. (WO) INT_TIMER2_TEZ_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event. (WO) INT_TIMER1_TEZ_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event. (WO) INT_TIMER0_TEZ_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event. (WO) INT_TIMER2_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 2 stops. (WO) INT_TIMER1_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 1 stops. (WO) INT_TIMER0_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 0 stops. (WO) Espressif Systems 360 ESP32 Technical Reference Manual V2.0 14. PULSE_CNT 14. PULSE_CNT 14.1 Introduction The pulse counter module is designed to count the number of rising and/or falling edges of an input signal. Each pulse counter unit has a 16-bit signed counter register and two channels that can be configured to either increment or decrement the counter. Each channel has a signal input that accepts signal edges to be detected, as well as a control input that can be used to enable or disable the signal input. The inputs have optional filters that can be used to discard unwanted glitches in the signal. The pulse counter has eight independent units, referred to as PULSE_CNT_Un. 14.2 Functional Description 14.2.1 Architecture Figure 104: PULSE_CNT Architecture The architecture of a pulse counter unit is illustrated in Figure 104. Each unit has two channels: ch0 and ch1, which are functionally equivalent. Each channel has a signal input, as well as a control input, which can both be connected to I/O pads. The counting behavior on both the positive and negative edge can be configured separately to increase, decrease, or do nothing to the counter value. Separately, for both control signal levels, the hardware can be configured to modify the edge action: invert it, disable it, or do nothing. The counter itself is a 16-bit signed up/down counter. Its value can be read by software directly, but is also monitored by a set of comparators which can trigger an interrupt. 14.2.2 Counter Channel Inputs As stated before, the two inputs of a channel can affect the pulse counter in various ways. The specifics of this behaviour are set by LCTRL_MODE and HCTRL_MODE in this case when the control signal is low or high, respectively, and POS_MODE and NEG_MODE for positive and negative edges of the input signal. Setting POS_MODE and NEG_MODE to 1 will increase the counter when an edge is detected, setting them to 2 will decrease the counter and setting at any other value will neutralize the effect of the edge on the counter. LCTR_MODE and HCTR_MODE modify this behaviour, when the control input has the corresponding low or high Espressif Systems 361 ESP32 Technical Reference Manual V2.0 14. PULSE_CNT value: 0 does not modify the NEG_MODE and POS_MODE behaviour, 1 inverts it (setting POS_MODE/NEG_MODE to increase the counter should now decrease the counter and vice versa) and any other value disables counter effects for that signal level. To summarize, a few examples have been considered. In this table, the effect on the counter for a rising edge is shown for both a low and a high control signal, as well as various other configuration options. For clarity, a short description in brackets is added after the values. Note: x denotes ’do not care’. POS_ MODE LCTRL_ MODE HCTRL_ MODE sig l→h when ctrl=0 sig l→h when ctrl=1 1 (inc) 0 (-) 0 (-) Inc ctr Inc ctr 2 (dec) 0 (-) 0 (-) Dec ctr Dec ctr 0 (-) x x No action No action 1 (inc) 0 (-) 1 (inv) Inc ctr Dec ctr 1 (inc) 1 (inv) 0 (-) Dec ctr Inc ctr 2 (dec) 0 (-) 1 (inv) Dec ctr Inc ctr 1 (inc) 0 (-) 2 (dis) Inc ctr No action 1 (inc) 2 (dis) 0 (-) No action Inc ctr This table is also valid for negative edges (sig h→l) on substituting NEG_MODE for POS_MODE. Each pulse counter unit also features a filter on each of the four inputs, adding the option to ignore short glitches in the signals. If a PCNT_FILTER_EN_Un can be set to filter the four input signals of the unit. If this filter is enabled, any pulses shorter than REG_FILTER_THRES_Un number of APB_CLK clock cycles will be filtered out and will have no effect on the counter. With the filter disabled, in theory infinitely small glitches could possibly trigger pulse counter action. However, in practice the signal inputs are sampled on APB_CLK edges and even with the filter disabled, pulse widths lasting shorter than one APB_CLK cycle may be missed. Apart from the input channels, software also has some control over the counter. In particular, the counter value can be frozen to the current value by configuring PCNT_CNT_PAUSE_Un. It can also be reset to 0 by configuring PCNT_PULSE_CNT_RST_Un. 14.2.3 Watchpoints The pulse counters have five watchpoints that share one interrupt. Interrupt generation can be enabled or disabled for each individual watchpoint. The watchpoints are: • Maximum count value: Triggered when PULSE_CNT >= PCNT_THR_H_LIM_Un. Additionally, this will reset the counter to 0. • Minimum count value: Triggered when PULSE_CNT <= PCNT_THR_L_LIM_Un. Additionally, this will reset the counter to 0. This is most useful when PCNT_THR_L_LIM_Un is set to a negative number. • Two threshold values: Triggered when PULSE_CNT = PCNT_THR_THRES0_Un or PCNT_THR_THRES1_Un. • Zero: Triggered when PULSE_CNT = 0. Espressif Systems 362 ESP32 Technical Reference Manual V2.0 14. PULSE_CNT 14.2.4 Examples Figure 105: PULSE_CNT Upcounting Diagram Figure 105 shows channel 0 being used as an up-counter. The configuration of channel 0 is shown below. • CNT_CH0_POS_MODE_Un = 1: increase counter on the rising edge of sig_ch0_un. • PCNT_CH0_NEG_MODE_Un = 0: no counting on the falling edge of sig_ch0_un. • PCNT_CH0_LCTRL_MODE_Un = 0: Do not modify counter mode when sig_ch0_un is low. • PCNT_CH0_HCTRL_MODE_Un = 2: Do not allow counter increments/decrements when sig_ch0_un is high. • PCNT_THR_H_LIM_Un = 5: PULSE_CNT resets to 0 when the count value increases to 5. Figure 106: PULSE_CNT Downcounting Diagram Figure 106 shows channel 0 decrementing the counter. The configuration of channel 0 differs from that in Figure 105 in the following two aspects: • PCNT_CH0_LCTRL_MODE_Un = 1: invert counter mode when ctrl_ch0_un is at low level, so it will decrease, rather than increase, the counter. • PCNT_THR_H_LIM_Un = -5: PULSE_CNT resets to 0 when the count value decreases to -5. 14.2.5 Interrupts PCNT_CNT_THR_EVENT_Un_INT: This interrupt gets triggered when one of the five channel comparators detects a match. 14.3 Register Summary Name Description Address Access Configuration registers Espressif Systems 363 ESP32 Technical Reference Manual V2.0 14. PULSE_CNT Name Description Address Access PCNT_U0_CONF0_REG Configuration register 0 for unit 0 0x3FF57000 R/W PCNT_U1_CONF0_REG Configuration register 0 for unit 1 0x3FF5700C R/W PCNT_U2_CONF0_REG Configuration register 0 for unit 2 0x3FF57018 R/W PCNT_U3_CONF0_REG Configuration register 0 for unit 3 0x3FF57024 R/W PCNT_U4_CONF0_REG Configuration register 0 for unit 4 0x3FF57030 R/W PCNT_U5_CONF0_REG Configuration register 0 for unit 5 0x3FF5703C R/W PCNT_U6_CONF0_REG Configuration register 0 for unit 6 0x3FF57048 R/W PCNT_U7_CONF0_REG Configuration register 0 for unit 7 0x3FF57054 R/W PCNT_U0_CONF1_REG Configuration register 1 for unit 0 0x3FF57004 R/W PCNT_U1_CONF1_REG Configuration register 1 for unit 1 0x3FF57010 R/W PCNT_U2_CONF1_REG Configuration register 1 for unit 2 0x3FF5701C R/W PCNT_U3_CONF1_REG Configuration register 1 for unit 3 0x3FF57028 R/W PCNT_U4_CONF1_REG Configuration register 1 for unit 4 0x3FF57034 R/W PCNT_U5_CONF1_REG Configuration register 1 for unit 5 0x3FF57040 R/W PCNT_U6_CONF1_REG Configuration register 1 for unit 6 0x3FF5704C R/W PCNT_U7_CONF1_REG Configuration register 1 for unit 7 0x3FF57058 R/W PCNT_U0_CONF2_REG Configuration register 2 for unit 0 0x3FF57008 R/W PCNT_U1_CONF2_REG Configuration register 2 for unit 1 0x3FF57014 R/W PCNT_U2_CONF2_REG Configuration register 2 for unit 2 0x3FF57020 R/W PCNT_U3_CONF2_REG Configuration register 2 for unit 3 0x3FF5702C R/W PCNT_U4_CONF2_REG Configuration register 2 for unit 4 0x3FF57038 R/W PCNT_U5_CONF2_REG Configuration register 2 for unit 5 0x3FF57044 R/W PCNT_U6_CONF2_REG Configuration register 2 for unit 6 0x3FF57050 R/W PCNT_U7_CONF2_REG Configuration register 2 for unit 7 0x3FF5705C R/W PCNT_U0_CNT_REG Counter value for unit 0 0x3FF57060 RO PCNT_U1_CNT_REG Counter value for unit 1 0x3FF57064 RO PCNT_U2_CNT_REG Counter value for unit 2 0x3FF57068 RO PCNT_U3_CNT_REG Counter value for unit 3 0x3FF5706C RO PCNT_U4_CNT_REG Counter value for unit 4 0x3FF57070 RO PCNT_U5_CNT_REG Counter value for unit 5 0x3FF57074 RO PCNT_U6_CNT_REG Counter value for unit 6 0x3FF57078 RO PCNT_U7_CNT_REG Counter value for unit 7 0x3FF5707C RO Control register for all counters 0x3FF570B0 R/W PCNT_INT_RAW_REG Raw interrupt status 0x3FF57080 RO PCNT_INT_ST_REG Masked interrupt status 0x3FF57084 RO PCNT_INT_ENA_REG Interrupt enable bits 0x3FF57088 R/W PCNT_INT_CLR_REG Interrupt clear bits 0x3FF5708C WO Counter values Control registers PCNT_CTRL_REG Interrupt registers Espressif Systems 364 ESP32 Technical Reference Manual V2.0 14. PULSE_CNT 14.4 Registers 31 30 0 29 28 0 27 26 0 25 24 0 23 22 0 21 20 0 19 18 0 17 16 15 14 13 12 11 10 0 0 1 1 1 1 0 Un S_ HR E _T ER FI LT PC NT _ PC NT _C H1 PC _L CT NT RL _C _M H1 PC O _H DE NT CT _U _C RL n H1 _M PC _P O DE O NT S_ _U _C M n H1 O D PC _N E_ NT EG Un _C _M H0 O DE PC _L _U CT NT n RL _C _ H0 M PC O _H DE NT CT _U _C RL n H0 _M PC _P O D O NT E_ S_ _ Un M PC CH O DE NT 0_N _U PC _T E n NT HR G_M PC _T _T O D N H H E_ PC T_T R_T RE Un NT HR HR S1_ PC _T _L E EN N H _L S0 _ PC T_T R_H IM _EN Un NT HR _L _EN _U _F _Z IM _U n ILT ER _E n ER O N_ _E _EN Un N_ _ Un Un Register 14.1: PCNT_Un_CONF0_REG (n: 0-7) (0x0+0x0C*n) 9 0 0x010 Reset PCNT_CH1_LCTRL_MODE_Un This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be modified when the control signal is low. (R/W) 0: No modification; 1: Invert behaviour (increase -> decrease, decrease -> increase); 2, 3: Inhibit counter modification PCNT_CH1_HCTRL_MODE_Un This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be modified when the control signal is low. (R/W) 0: No modification; 1: Invert behaviour (increase -> decrease, decrease -> increase); 2, 3: Inhibit counter modification PCNT_CH1_POS_MODE_Un This register sets the behaviour when the signal input of channel 1 detects a positive edge. (R/W) 1: Increment the counter; 2: Decrement the counter; 0, 3: No effect on counter PCNT_CH1_NEG_MODE_Un This register sets the behaviour when the signal input of channel 1 detects a negative edge. (R/W) 1: Increment the counter; 2: Decrement the counter; 0, 3: No effect on counter PCNT_CH0_LCTRL_MODE_Un This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the control signal is low. (R/W) 0: No modification; 1: Invert behaviour (increase -> decrease, decrease -> increase); 2, 3: Inhibit counter modification PCNT_CH0_HCTRL_MODE_Un This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the control signal is low. (R/W) 0: No modification; 1: Invert behaviour (increase -> decrease, decrease -> increase); 2, 3: Inhibit counter modification PCNT_CH0_POS_MODE_Un This register sets the behaviour when the signal input of channel 0 detects a positive edge. (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No effect on counter PCNT_CH0_NEG_MODE_Un This register sets the behaviour when the signal input of channel 0 detects a negative edge. (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No effect on counter PCNT_THR_THRES1_EN_Un This is the enable bit for unit n’s thres1 comparator. (R/W) PCNT_THR_THRES0_EN_Un This is the enable bit for unit n’s thres0 comparator. (R/W) PCNT_THR_L_LIM_EN_Un This is the enable bit for unit n’s thr_l_lim comparator. (R/W) PCNT_THR_H_LIM_EN_Un This is the enable bit for unit n’s thr_h_lim comparator. (R/W) PCNT_THR_ZERO_EN_Un This is the enable bit for unit n’s zero comparator. (R/W) PCNT_FILTER_EN_Un This is the enable bit for unit n’s input filter. (R/W) PCNT_FILTER_THRES_Un This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses lasting shorter than this will be ignored when the filter is enabled. (R/W) Espressif Systems 365 ESP32 Technical Reference Manual V2.0 14. PULSE_CNT PC NT _ PC NT _ CN CN T_ T T_ TH RE S HR ES 0_ 1_ Un Un Register 14.2: PCNT_Un_CONF1_REG (n: 0-7) (0x4+0x0C*n) 31 16 15 0x000 0 0x000 Reset PCNT_CNT_THRES1_Un This register is used to configure the thres1 value for unit n. (R/W) PCNT_CNT_THRES0_Un This register is used to configure the thres0 value for unit n. (R/W) PC PC NT NT _C _C NT _L NT _H _L _L IM IM _U _U n n Register 14.3: PCNT_Un_CONF2_REG (n: 0-7) (0x8+0x0C*n) 31 16 15 0x000 0 0x000 Reset PCNT_CNT_L_LIM_Un This register is used to configure the thr_l_lim value for unit n. (R/W) PCNT_CNT_H_LIM_Un This register is used to configure the thr_h_lim value for unit n. (R/W) PC NT (re se rv _P ed ) LU S_ CN T_ Un Register 14.4: PCNT_Un_CNT_REG (n: 0-7) (0x28+0x0C*n) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0x00000 Reset PCNT_PLUS_CNT_Un This register stores the current pulse count value for unit n. (RO) Espressif Systems 366 ESP32 Technical Reference Manual V2.0 Espressif Systems 8 0x0000000 raw PCNT_CNT_THR_EVENT_Un_INT_ENA The 367 interrupt 31 8 0x0000000 masked 31 interrupt interrupt 8 0x0000000 enable PC _C N N PC T_C T_T N N H PC T_C T_T R_E N N H V PC T_C T_T R_E EN N N H V T_ PC T_C T_T R_E EN U7_ N N H V T_ IN PC T_C T_T R_E EN U6_ T_S N N H V T_ IN T PC T_C T_T R_E EN U5_ T_S NT N HR VE T_U IN T _C T_T _E NT 4_ T_S NT HR VE _U INT T _T _E NT 3_ _S HR VE _U IN T _E NT 2_ T_S VE _U IN T NT 1_ T_S _U IN T 0_ T_S IN T T_ ST NT PC 31 PC _C N N PC T_C T_T NT N HR PC _C T_T _E N N H V PC T_C T_T R_E EN N N H V T_ PC T_C T_T R_E EN U7_ N N H V T_ IN PC T_C T_T R_E EN U6_ T_E N N H V T_ IN N PC T_C T_T R_E EN U5_ T_E A NT N HR VE T_U IN NA _C T_T _E NT 4_ T_E NT HR VE _U INT NA _T _E NT 3_ _E HR VE _U IN N _E NT 2_ T_E A VE _U IN NA NT 1_ T_E _U IN NA 0_ T_E IN N T_ A EN A PCNT_CNT_THR_EVENT_Un_INT_ST The NT d) rv e se (re PCNT_CNT_THR_EVENT_Un_INT_RAW The PC d) se rv e (re ) rv ed PC N PC T_C N N PC T_C T_T NT N HR PC _C T_T _E N N H V PC T_C T_T R_E EN N N H V T_ PC T_C T_T R_E EN U7_ N N H V T_ IN PC T_C T_T R_E EN U6_ T_R N N H V T_ IN A PC T_C T_T R_E EN U5_ T_R W NT N HR VE T_U IN AW _C T_T _E NT 4_ T_R NT HR VE _U INT AW _T _E NT 3_ _R HR VE _U IN A _E NT 2_ T_R W VE _U IN AW NT 1_ T_R _U IN AW 0_ T_R IN A T_ W RA W se (re 14. PULSE_CNT Register 14.5: PCNT_INT_RAW_REG (0x0080) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset status bit status bit for bit for the PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Register 14.6: PCNT_INT_ST_REG (0x0084) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset for the PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Register 14.7: PCNT_INT_ENA_REG (0x0088) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset the PCNT_CNT_THR_EVENT_Un_INT interrupt. (R/W) ESP32 Technical Reference Manual V2.0 31 0x0000 Espressif Systems (re se PC rve N d) PC T_C N N PC T_P T_P N L A PC T_C US US NT N _CN E_U PC _P T_P T 7 N L A _R PC T_C US US ST_ N N _C E_ U PC T_P T_P NT U6 7 N L A _R PC T_C US US ST_ N N _C E_ U PC T_P T_P NT U5 6 N L A _R PC T_C US US ST_ N N _C E_ U PC T_P T_P NT U4 5 N L A _R PC T_C US US ST_ N N _C E_ U PC T_P T_P NT U3 4 N L A _R PC T_C US US ST_ N N _C E_ U PC T_P T_P NT U2 3 N L A _R PC T_C US US ST_ NT N _CN E_U U2 _P T_P T_ 1 LU AU RS S_ SE T_ CN _U U1 T_ 0 RS T_ U0 ) ve d (re se r d) PC N PC T_C N N PC T_C T_T NT N HR PC _C T_T _E N N H V PC T_C T_T R_E EN N N H V T_ PC T_C T_T R_E EN U7_ N N H V T_ IN PC T_C T_T R_E EN U6_ T_C N N H V T_ IN L PC T_C T_T R_E EN U5_ T_C R NT N HR VE T_U IN LR _C T_T _E NT 4_ T_C NT HR VE _U INT LR _T _E NT 3_ _C HR VE _U IN LR _E NT 2_ T_C VE _U IN LR NT 1_ T_C _U IN LR 0_ T_C IN L T_ R CL R ve er (re s 14. PULSE_CNT Register 14.8: PCNT_INT_CLR_REG (0x008c) 31 8 0x0000000 17 368 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset PCNT_CNT_THR_EVENT_Un_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_Un_INT interrupt. (WO) Register 14.9: PCNT_CTRL_REG (0x00b0) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reset PCNT_CNT_PAUSE_Un Set this bit to freeze unit n’s counter. (R/W) PCNT_PLUS_CNT_RST_Un Set this bit to clear unit n’s counter. (R/W) ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS 15. 64-bit Timers 15.1 Introduction There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit auto-reload-capable up/downcounters. The ESP32 contains two timer modules, each containing two timers. The two timers in a block are indicated by an x in TIMGn_Tx; the blocks themselves are indicated by an n. The timers feature: • A 16-bit clock prescaler, from 2 to 65536 • A 64-bit time-base counter • Configurable up/down time-base counter: incrementing or decrementing • Halt and resume of time-base counter • Auto-reload at alarm • Software-controlled instant reload • Level and edge interrupt generation 15.2 Functional Description 15.2.1 16-bit Prescaler Each timer uses the APB clock (APB_CLK, normally 80 MHz) as the basic clock. This clock is then divided down by a 16-bit precaler which generates the time-base counter clock (TB_clk). Every cycle of TB_clk causes the time-base counter to increment or decrement by one. The timer must be disabled (TIMGn_Tx_EN is cleared) before changing the prescaler divisor which is configured by TIMGn_Tx_DIVIDER register; changing it on an enabled timer can lead to unpredictable results. The prescaler can divide the APB clock by a factor from 2 to 65536. Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2; when TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will cause the clock to be divided by exactly that value. 15.2.2 64-bit Time-base Counter The 64-bit time-base counter can be configured to count either up or down, depending on whether TIMGn_Tx_INCREASE is set or cleared, respectively. It supports both auto-reload and software instant reload. An alarm event can be set when the counter reaches a value specified by the software. Counting can be enabled and disabled by setting and clearing TIMGn_Tx_EN. Clearing this bit essentially freezes the counter, causing it to neither count up nor count down; instead, it retains its value until TIMGn_Tx_EN is set again. Reloading the counter when TIMGn_Tx_EN is cleared will change its value, but counting will not be resumed until TIMGn_Tx_EN is set. Software can set a new counter value by setting registers TIMGn_Tx_LOAD_LO and TIMGn_Tx_LOAD_HI to the intended new value. The hardware will ignore these register settings until a reload; a reload will cause the contents of these registers to be copied to the counter itself. A reload event can be triggered by an alarm (auto-reload at alarm) or by software (software instant reload). To enable auto-reload at alarm, the register Espressif Systems 369 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS TIMGn_Tx_AUTORELOAD should be set. If auto-reload at alarm is not enabled, the time-base counter will continue incrementing or decrementing after the alarm. To trigger a software instant reload, any value can be written to the register TIMGn_Tx_LOAD_REG; this will cause the counter value to change instantly. Software can also change the direction of the time-base counter instantly by changing the value of TIMGn_Tx_INCREASE. The time-base counter can also be read by software, but because the counter is 64-bit, the CPU can only get the value as two 32-bit values, the counter value needs to be latched onto TIMGn_TxLO_REG and TIMGn_TxHI_REG first. This is done by writing any value to TIMGn_TxUPDATE_REG; this will instantly latch the 64-bit timer value onto the two registers. Software can then read them at any point in time. This approach stops the timer value being read erroneously when a carry-over happens between reading the low and high word of the timer value. 15.2.3 Alarm Generation The timer can trigger an alarm, which can cause a reload and/or an interrupt to occur. The alarm is triggered when the alarm registers TIMGn_Tx_ALARMLO_REG and TIMGn_Tx_ALARMHI_REG match the current timer value. In order to simplify the scenario where these registers are set ’too late’ and the counter has already passed these values, the alarm also triggers when the current timer value is higher (for an up-counting timer) or lower (for a down-counting timer) than the current alarm value: if this is the case, the alarm will be triggered immediately upon loading the alarm registers. 15.2.4 MWDT Each timer module also contains a Main System Watchdog Timer and its associated registers. While these registers are described here, their functional description can be found in the chapter entitled Watchdog Timer. 15.2.5 Interrupts • TIMGn_Tx_INT_WDT_INT: Generated when a watchdog timer interrupt stage times out. • TIMGn_Tx_INT_T1_INT: An alarm event on timer 1 generates this interrupt. • TIMGn_Tx_INT_T0_INT: An alarm event on timer 0 generates this interrupt. 15.3 Register Summary Name Description TIMG0 TIMG1 Acc Timer 0 configuration and control registers TIMGn_T0CONFIG_REG Timer 0 configuration register 0x3FF5F000 0x3FF60000 R/W TIMGn_T0LO_REG Timer 0 current value, low 32 bits 0x3FF5F004 0x3FF60004 RO TIMGn_T0HI_REG Timer 0 current value, high 32 bits 0x3FF5F008 0x3FF60008 RO TIMGn_T0UPDATE_REG Write to copy current timer value to TIMGn_T0_(LO/HI)_REG 0x3FF5F00C 0x3FF6000C WO TIMGn_T0ALARMLO_REG Timer 0 alarm value, low 32 bits 0x3FF5F010 0x3FF60010 R/W TIMGn_T0ALARMHI_REG Timer 0 alarm value, high bits 0x3FF5F014 0x3FF60014 R/W TIMGn_T0LOADLO_REG Timer 0 reload value, low 32 bits 0x3FF5F018 0x3FF60018 R/W Espressif Systems 370 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS Name TIMGn_T0LOAD_REG Description Write to TIMG0 reload timer from TIMGn_T0_(LOADLOLOADHI)_REG TIMG1 Acc 0x3FF5F020 0x3FF60020 WO Timer 1 configuration and control registers TIMGn_T1CONFIG_REG Timer 1 configuration register 0x3FF5F024 0x3FF60024 R/W TIMGn_T1LO_REG Timer 1 current value, low 32 bits 0x3FF5F028 0x3FF60028 RO TIMGn_T1HI_REG Timer 1 current value, high 32 bits 0x3FF5F02C 0x3FF6002C RO TIMGn_T1UPDATE_REG Write to copy current timer value to TIMGn_T1_(LO/HI)_REG 0x3FF5F030 0x3FF60030 WO TIMGn_T1ALARMLO_REG Timer 1 alarm value, low 32 bits 0x3FF5F034 0x3FF60034 R/W TIMGn_T1ALARMHI_REG Timer 1 alarm value, high 32 bits 0x3FF5F038 0x3FF60038 R/W TIMGn_T1LOADLO_REG Timer 1 reload value, low 32 bits 0x3FF5F03C 0x3FF6003C R/W TIMGn_T1LOAD_REG Write to reload timer from TIMGn_T1_(LOADLOLOADHI)_REG 0x3FF5F044 0x3FF60044 WO System watchdog timer configuration and control registers TIMGn_Tx_WDTCONFIG0_REG Watchdog timer configuration register 0x3FF5F048 0x3FF60048 R/W TIMGn_Tx_WDTCONFIG1_REG Watchdog timer prescaler register 0x3FF5F04C 0x3FF6004C R/W TIMGn_Tx_WDTCONFIG2_REG Watchdog timer stage 0 timeout value 0x3FF5F050 0x3FF60050 R/W TIMGn_Tx_WDTCONFIG3_REG Watchdog timer stage 1 timeout value 0x3FF5F054 0x3FF60054 R/W TIMGn_Tx_WDTCONFIG4_REG Watchdog timer stage 2 timeout value 0x3FF5F058 0x3FF60058 R/W TIMGn_Tx_WDTCONFIG5_REG Watchdog timer stage 3 timeout value 0x3FF5F05C 0x3FF6005C R/W TIMGn_Tx_WDTFEED_REG Write to feed the watchdog timer 0x3FF5F060 0x3FF60060 WO TIMGn_Tx_WDTWPROTECT_REG Watchdog write protect register 0x3FF5F064 0x3FF60064 R/W Interrupt registers TIMGn_Tx_INT_RAW_REG Raw interrupt status 0x3FF5F09C 0x3FF6009C RO TIMGn_Tx_INT_ST_REG Masked interrupt status 0x3FF5F0A0 0x3FF600A0 RO TIMGn_Tx_INT_ENA_REG Interrupt enable bits 0x3FF5F098 0x3FF60098 R/W TIMGn_Tx_INT_CLR_REG Interrupt clear bits 0x3FF5F0A4 0x3FF600A4 WO Espressif Systems 371 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS 15.4 Registers 31 30 29 0 1 1 R DI VI DE n_ Tx _ G TI M TI M G TI n_ M T G x TI n_ _EN M T G x_ n_ IN Tx CR _A E UT AS O E RE LO AD TI M G TI n_ M T G x TI n_ _ED M T G x_ GE n_ LE _ Tx V INT _A EL _ LA _IN EN RM T_ _E EN N Register 15.1: TIMGn_TxCONFIG_REG (x: 0-1) (0x0+0x24*x) 28 13 0x00001 12 11 10 0 0 0 Reset TIMGn_Tx_EN When set, the timer x time-base counter is enabled. (R/W) TIMGn_Tx_INCREASE When set, the timer x time-base counter will increment every clock tick. When cleared, the timer x time-base counter will decrement. (R/W) TIMGn_Tx_AUTORELOAD When set, timer x auto-reload at alarm is enabled. (R/W) TIMGn_Tx_DIVIDER Timer x clock (Tx_clk) prescale value. (R/W) TIMGn_Tx_EDGE_INT_EN When set, an alarm will generate an edge type interrupt. (R/W) TIMGn_Tx_LEVEL_INT_EN When set, an alarm will generate a level type interrupt. (R/W) TIMGn_Tx_ALARM_EN When set, the alarm is enabled. (R/W) Register 15.2: TIMGn_TxLO_REG (x: 0-1) (0x4+0x24*x) 31 0 0x000000000 Reset TIMGn_TxLO_REG After writing to TIMGn_TxUPDATE_REG, the low 32 bits of the time-base counter of timer x can be read here. (RO) Register 15.3: TIMGn_TxHI_REG (x: 0-1) (0x8+0x24*x) 31 0 0x000000000 Reset TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter of timer x can be read here. (RO) Espressif Systems 372 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS Register 15.4: TIMGn_TxUPDATE_REG (x: 0-1) (0xC+0x24*x) 31 0 0x000000000 Reset TIMGn_TxUPDATE_REG Write any value to trigger a timer x time-base counter value update (timer x current value will be stored in registers above). (WO) Register 15.5: TIMGn_TxALARMLO_REG (x: 0-1) (0x10+0x24*x) 31 0 0x000000000 Reset TIMGn_TxALARMLO_REG Timer x alarm trigger time-base counter value, low 32 bits. (R/W) Register 15.6: TIMGn_TxALARMHI_REG (x: 0-1) (0x14+0x24*x) 31 0 0x000000000 Reset TIMGn_TxALARMHI_REG Timer x alarm trigger time-base counter value, high 32 bits. (R/W) Register 15.7: TIMGn_TxLOADLO_REG (x: 0-1) (0x18+0x24*x) 31 0 0x000000000 Reset TIMGn_TxLOADLO_REG Low 32 bits of the value that a reload will load onto timer x time-base counter. (R/W) Register 15.8: TIMGn_TxLOADHI_REG (x: 0-1) (0x1C+0x24*x) 31 0 0x000000000 Reset TIMGn_TxLOADHI_REG High 32 bits of the value that a reload will load onto timer x time-base counter. (R/W) Espressif Systems 373 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS Register 15.9: TIMGn_TxLOAD_REG (x: 0-1) (0x20+0x24*x) 31 0 0x000000000 Reset TIMGn_TxLOAD_REG Write any value to trigger a timer x time-base counter reload. (WO) 31 0 TI M TI M G n_ Tx _W G D n_ Tx T_E _ N W TI M DT G _S n_ TG Tx _W 0 TI M DT G _S n_ TG Tx _W 1 TI M DT G _S n_ TG Tx TI _W M 2 G DT TI n_ M T _S G x_ TG n_ W 3 Tx DT _W _ TI E M D DT G G _L E_ n_ EV IN Tx _W EL T_ _I EN DT NT _C TI _E M P N U_ G n_ R Tx ES _W ET TI M DT _L G EN _ n_ SY G Tx S_ TH _W RE DT SE _F T_ LA LE SH NG BO TH O T_ M O D_ EN Register 15.10: TIMGn_Tx_WDTCONFIG0_REG (0x0048) 30 29 0 28 27 0 26 25 0 24 23 0 22 21 0 0 20 18 0x1 17 15 0x1 14 1 Reset TIMGn_Tx_WDT_EN When set, MWDT is enabled. (R/W) TIMGn_Tx_WDT_STG0 Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W) TIMGn_Tx_WDT_STG1 Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W) TIMGn_Tx_WDT_STG2 Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W) TIMGn_Tx_WDT_STG3 Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W) TIMGn_Tx_WDT_EDGE_INT_EN When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt. (R/W) TIMGn_Tx_WDT_LEVEL_INT_EN When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt. (R/W) TIMGn_Tx_WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W) TIMGn_Tx_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W) TIMGn_Tx_WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. (R/W) Espressif Systems 374 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS TI M G n_ Tx _ W DT _C LK _P RE S CA L E Register 15.11: TIMGn_Tx_WDTCONFIG1_REG (0x004c) 31 16 0x00001 Reset TIMGn_Tx_WDT_CLK_PRESCALE MWDT clock prescale value. MWDT clock period = 12.5 ns * TIMGn_Tx_WDT_CLK_PRESCALE. (R/W) Register 15.12: TIMGn_Tx_WDTCONFIG2_REG (0x0050) 31 0 26000000 Reset TIMGn_Tx_WDTCONFIG2_REG Stage 0 timeout value, in MWDT clock cycles. (R/W) Register 15.13: TIMGn_Tx_WDTCONFIG3_REG (0x0054) 31 0 0x007FFFFFF Reset TIMGn_Tx_WDTCONFIG3_REG Stage 1 timeout value, in MWDT clock cycles. (R/W) Register 15.14: TIMGn_Tx_WDTCONFIG4_REG (0x0058) 31 0 0x0000FFFFF Reset TIMGn_Tx_WDTCONFIG4_REG Stage 2 timeout value, in MWDT clock cycles. (R/W) Register 15.15: TIMGn_Tx_WDTCONFIG5_REG (0x005c) 31 0 0x0000FFFFF Reset TIMGn_Tx_WDTCONFIG5_REG Stage 3 timeout value, in MWDT clock cycles. (R/W) Espressif Systems 375 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS Register 15.16: TIMGn_Tx_WDTFEED_REG (0x0060) 31 0 0x000000000 Reset TIMGn_Tx_WDTFEED_REG Write any value to feed the MWDT. (WO) Register 15.17: TIMGn_Tx_WDTWPROTECT_REG (0x0064) 31 0 0x050D83AA1 Reset TIMGn_Tx_WDTWPROTECT_REG If the register contains a different value than its reset value, write protection is enabled. (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI 31 TI (re se rv e d) M G n M _T G x_ TI n_ IN M T T_ G x_ W n_ IN D Tx T_ T _I T1 _IN NT _ T _T INT _E 0_ _E NA IN N T_ A EN A Register 15.18: TIMGn_Tx_INT_ENA_REG (0x0098) 3 2 1 0 0 0 0 0 Reset TIMGn_Tx_INT_WDT_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_WDT_INT interrupt. (R/W) (R/W) TIMGn_Tx_INT_T1_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_T1_INT interrupt. (R/W) (R/W) TIMGn_Tx_INT_T0_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_T0_INT interrupt. (R/W) (R/W) Espressif Systems 376 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS TI (re s er ve d) M G TI n_ M T G x TI n_ _IN M T T_ G x_ W n_ IN D Tx T_ T _I T1 _IN NT _ T _T INT _R 0_ _R AW IN A T_ W RA W Register 15.19: TIMGn_Tx_INT_RAW_REG (0x009c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 0 Reset TIMGn_Tx_INT_WDT_INT_RAW The raw interrupt status bit for the TIMGn_Tx_INT_WDT_INT interrupt. (RO) TIMGn_Tx_INT_T1_INT_RAW The raw interrupt status bit for the TIMGn_Tx_INT_T1_INT interrupt. (RO) TIMGn_Tx_INT_T0_INT_RAW The raw interrupt status bit for the TIMGn_Tx_INT_T0_INT interrupt. (RO) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n M _T G x TI n_ _IN M T T_ G x_ W n_ IN D Tx T_ T _I T1 _IN NT _ T _T INT _S 0_ _S T IN T T_ ST TI TI M G (re se rv ed ) Register 15.20: TIMGn_Tx_INT_ST_REG (0x00a0) 3 2 1 0 0 0 0 0 Reset TIMGn_Tx_INT_WDT_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_WDT_INT interrupt. (RO) TIMGn_Tx_INT_T1_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_T1_INT interrupt. (RO) TIMGn_Tx_INT_T0_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_T0_INT interrupt. (RO) Espressif Systems 377 ESP32 Technical Reference Manual V2.0 15. 64-BIT TIMERS 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI TI (re s er ve d) M G n M _T G x_ TI n_ IN M T T_ G x_ W n_ IN D Tx T_ T _I T1 _IN NT _ T _T INT _C 0_ _C LR IN L T_ R CL R Register 15.21: TIMGn_Tx_INT_CLR_REG (0x00a4) 3 2 1 0 0 0 0 0 Reset TIMGn_Tx_INT_WDT_INT_CLR Set this bit to clear the TIMGn_Tx_INT_WDT_INT interrupt. (WO) TIMGn_Tx_INT_T1_INT_CLR Set this bit to clear the TIMGn_Tx_INT_T1_INT interrupt. (WO) TIMGn_Tx_INT_T0_INT_CLR Set this bit to clear the TIMGn_Tx_INT_T0_INT interrupt. (WO) Espressif Systems 378 ESP32 Technical Reference Manual V2.0 16. WATCHDOG TIMERS 16. Watchdog Timers 16.1 Introduction The ESP32 has three watchdog timers: one in each of the two timer modules (called Main System Watchdog Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These watchdog timers are intended to recover from an unforeseen fault, causing the application program to abandon its normal sequence. A watchdog timer has four stages. Each stage may take one out of three or four actions upon the expiry of a programmed period of time for this stage, unless the watchdog is fed or disabled. The actions are: interrupt, CPU reset, core reset and system reset. Only the RWDT can trigger the system reset, and is able to reset the entire chip and the main system including the RTC itself. A timeout value can be set for each stage individually. During flash boot, the RWDT and the first MWDT start automatically in order to detect and recover from booting problems. 16.2 Features • Four stages, each of which can be configured or disabled separately • Programmable time period for each stage • One out of three or four possible actions (interrupt, CPU reset, core reset and system reset) upon the expiry of each stage • 32-bit expiry counter • Write protection, to prevent the RWDT and MWDT configuration from being inadvertently altered. • Flash boot protection If the boot process from an SPI flash does not complete within a predetermined period of time, the watchdog will reboot the entire main system. 16.3 Functional Description 16.3.1 Clock The RWDT is clocked from the RTC slow clock, which usually will be 32 KHz. The MWDT clock source is derived from the APB clock via a pre-MWDT 16-bit configurable prescaler. For either watchdog, the clock source is fed into the 32-bit expiry counter. When this counter reaches the timeout value of the current stage, the action configured for the stage will execute, the expiry counter will be reset and the next stage will become active. Espressif Systems 379 ESP32 Technical Reference Manual V2.0 16. WATCHDOG TIMERS 16.3.1.1 Operating Procedure When a watchdog timer is enabled, it will proceed in loops from stage 0 to stage 3, then back to stage 0 and start again. The expiry action and time period for each stage can be configured individually. Every stage can be configured for one of the following actions when the expiry timer reaches the stage’s timeout value: • Trigger an interrupt When the stage expires an interrupt is triggered. • Reset a CPU core When the stage expires the designated CPU core will be reset. MWDT0 CPU reset only resets the PRO CPU. MWDT1 CPU reset only resets the APP CPU. The RWDT CPU reset can reset either of them, or both, or none, depending on configuration. • Reset the main system When the stage expires, the main system, including the MWDTs, will be reset. In this article, the main system includes the CPU and all peripherals. The RTC is an exception to this, and it will not be reset. • Reset the main system and RTC When the stage expires the main system and the RTC will both be reset. This action is only available in the RWDT. • Disabled This stage will have no effects on the system. When software feeds the watchdog timer, it returns to stage 0 and its expiry counter restarts from 0. 16.3.1.2 Write Protection Both the MWDTs, as well as the RWDT, can be protected from accidental writing. To accomplish this, they have a write-key register (TIMERS_WDT_WKEY for the MWDT, RTC_CNTL_WDT_WKEY for the RWDT.) On reset, these registers are initialized to the value 0x50D83AA1. When the value in this register is changed from 0x50D83AA1, write protection is enabled. Writes to any WDT register, including the feeding register (but excluding the write-key register itself), are ignored. The recommended procedure for accessing a WDT is: 1. Disable the write protection 2. Make the required modification or feed the watchdog 3. Re-enable the write protection 16.3.1.3 Flash Boot Protection During flash booting, the MWDT in timer group 0 (TIMG0), as well as the RWDT, are automatically enabled. Stage 0 for the enabled MWDT is automatically configured to reset the system upon expiry; stage 0 for the RWDT resets the RTC when it expires. After booting, the register TIMERS_WDT_FLASHBOOT_MOD_EN should be cleared to stop the flash boot protection procedure for the MWDT, and RTC_CNTL_WDT_FLASHBOOT_MOD_EN should be cleared to do the same for the RWDT. After this, the MWDT and RWDT can be configured by software. Espressif Systems 380 ESP32 Technical Reference Manual V2.0 16. WATCHDOG TIMERS 16.3.1.4 Registers The MWDT registers are part of the timer submodule and are described in the Timer Registers section. The RWDT registers are part of the RTC submodule and are described in the RTC Registers section. Espressif Systems 381 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 17. eFuse Controller 17.1 Introduction The ESP32 has a number of eFuses which store system parameters. Fundamentally, an eFuse is a single bit of non-volatile memory with the restriction that once an eFuse bit is programmed to 1, it can never be reverted to 0. Software can instruct the eFuse Controller to program each bit for each system parameter as needed. Some of these system parameters can be read by software using the eFuse Controller. Some of the system parameters are also directly used by hardware modules. 17.2 Features • Configuration of 26 system parameters • Optional write-protection • Optional software-read-protection 17.3 Functional Description 17.3.1 Structure Twenty-six system parameters with different bit width are stored in the eFuses. The name of each system parameter and the corresponding bit width are shown in Table 58. Among those parameters, efuse_wr_disable, efuse_rd_disable, and coding_scheme are directly used by the eFuse Controller. Table 58: System Parameter Name Bit width Program Software-Read -Protection by -Protection by Description efuse_wr_disable efuse_rd_disable efuse_wr_disable 16 1 - controls the eFuse Controller efuse_rd_disable 4 0 - controls the eFuse Controller flash_crypt_cnt 8 2 - WIFI_MAC_Address 56 3 - SPI_pad_config_hd 5 3 - chip_version 4 3 - chip version XPD_SDIO_REG 1 5 - powers up the flash regulator governs the flash encryption/ decryption Wi-Fi MAC address and CRC configures the SPI I/O to a certain pad configures the flash regulator SDIO_TIEH 1 5 - voltage: set to 1 for 3.3 V and set to 0 for 1.8 V determines whether sdio_force 1 5 - XPD_SDIO_REG and SDIO_TIEH can control the flash regulator Espressif Systems 382 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER Name Bit width Program Software-Read -Protection by -Protection by Description efuse_wr_disable efuse_rd_disable SPI_pad_config_clk 5 6 - SPI_pad_config_q 5 6 - SPI_pad_config_d 5 6 - SPI_pad_config_cs0 5 6 - flash_crypt_config 4 10 3 coding_scheme 2 10 3 console_debug_disable 1 15 - abstract_done_0 1 12 - abstract_done_1 1 13 - configures the SPI I/O to a certain pad configures the SPI I/O to a certain pad configures the SPI I/O to a certain pad configures the SPI I/O to a certain pad governs flash encryption/ decryption controls the eFuse Controller disables serial output from the BootROM when set to 1 determines the status of Secure Boot determines the status of Secure Boot disables access to the JTAG_disable 1 14 - JTAG controllers so as to effectively disable external use of JTAG governs flash encryption/ download_dis_encrypt 1 15 - download_dis_decrypt 1 15 - download_dis_cache 1 15 - key_status 1 10 3 BLOCK1 256/192/128 7 0 BLOCK2 256/192/128 8 1 key for Secure Boot BLOCK3 256/192/128 9 2 key for user purposes decryption governs flash encryption/ decryption disables cache when boot mode is the Download Mode determines whether BLOCK3 is deployed for user purposes governs flash encryption/ decryption 17.3.1.1 System Parameter efuse_wr_disable The system parameter efuse_wr_disable determines whether all of the system parameters are write-protected. Since efuse_wr_disable is a system parameter as well, it also determines whether it itself is write-protected. If a system parameter is not write-protected, its unprogrammed bits can be programmed from 0 to 1. The bits previously programmed to 1 will remain 1. When a system parameter is write-protected, none of its bits can be programmed: The unprogrammed bits will always remain 0 and the programmed bits will always remain 1. Espressif Systems 383 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER The write-protection status of each system parameter corresponds to a bit in efuse_wr_disable. When the corresponding bit is set to 0, the system parameter is not write-protected. When the corresponding bit is set to 1, the system parameter is write-protected. If a system parameter is already write-protected, it will remain write-protected. The column entitled ”Program-Protection by efuse_wr_disable” in Table 58 lists the corresponding bits that determine the write-protection status of each system parameter. 17.3.1.2 System Parameter efuse_rd_disable Of the 26 system parameters, 20 are not constrained by software-read-protection. These are marked by ”-” in the column entitled ”Software-Read-Protection by efuse_rd_disable” in Table 58. Those system parameters, some of which are used by software and hardware modules at the same time, can be read by software via the eFuse Controller at any time. When not software-read-protected, the other six system parameters can both be read by software and used by hardware modules. When they are software-read-protected, they can only be used by the hardware modules. The column ”Software-Read-Protection by efuse_rd_disable” in Table 58 lists the corresponding bits in efuse_rd_disable that determine the software read-protection status of the six system parameters. If a bit in the system parameter efuse_rd_disable is 0, the system parameter controlled by the bit is not software-read-protected. If a bit in the system parameter efuse_rd_disable is 1, the system parameter controlled by the bit is software-read-protected. If a system parameter is software-read-protected, it will remain in this state. 17.3.1.3 System Parameter coding_scheme As Table 58 shows, only three system parameters, BLOCK1, BLOCK2, and BLOCK3, have variable bit width. Their bit width is controlled by another system parameter, coding_scheme. Despite their variable bit width, BLOCK1, BLOCK2, and BLOCK3 are assigned a fixed number of bits in eFuse. There is an encoding mapping between these three system parameters and their corresponding stored values in eFuse. For details please see Table 59. Table 59: BLOCK1/2/3 Encoding coding_scheme[1:0] Width of BLOCK1/2/3 Coding scheme Number of bits in eFuse 00/11 256 None 256 01 192 3/4 256 10 128 Repeat 256 The three coding schemes are explained as follows: • BLOCKN represents any of the following three system parameters: BLOCK1, BLOCK2 or BLOCK3. • BLOCKN [255 : 0], BLOCKN [191 : 0], and BLOCKN [127 : 0] represent each bit of the three system parameters in the three encoding schemes. e • BLOCKN [255 : 0] represents each corresponding bit of those system parameters in eFuse after being encoded. Espressif Systems 384 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER None e BLOCKN [255 : 0] = BLOCKN [255 : 0] 3/4 e e BLOCKNij [7 : 0] = BLOCKN [48i + 8j + 7 : 48i + 8j] i ∈ {0, 1, 2, 3} j ∈ {0, 1, 2, 3, 4, 5} BLOCKN ji [7 : 0] = e BLOCKN [64i + 8j + 7 : 64i + 8j] i ∈ {0, 1, 2, 3} j ∈ {0, 1, 2, 3, 4, 5, 6, 7} BLOCKN ji [7 : 0] = BLOCKNij [7 : 0] BLOCKNi0 [7 : 0] ⊕ BLOCKNi1 [7 : 0] ⊕ BLOCKNi2 [7 : 0] ⊕ BLOCKNi3 [7 : 0] j ∈ {6} ⊕ BLOCKNi4 [7 : 0] ⊕ BLOCKNi5 [7 : 0] 5 7 ∑ ∑ (l + 1) BLOCKNil [k] j ∈ {7} l=0 j ∈ {0, 1, 2, 3, 4, 5} i ∈ {0, 1, 2, 3} k=0 ⊕ means bitwise XOR ∑ and + mean summation Repeat e e BLOCKN [255 : 128] = BLOCKN [127 : 0] = BLOCKN [127 : 0] 17.3.2 Programming of System Parameters The programming of variable-length system parameters BLOCK1, BLOCK2, and BLOCK3 is different from that of e the fixed-length system parameters. We program the BLOCKN [255 : 0] value of encoded system parameters BLOCK1, BLOCK2, and BLOCK3 instead of directly programming the system parameters. e The bit width of BLOCKN [255 : 0] is always 256. Fixed-length system parameters, in contrast, are programmed without encoding them first. Each bit of the 23 fixed-length system parameters and the three encoded variable-length system parameters corresponds to a program register bit, as shown in Table 60. The register bits will be used when programming system parameters. Table 60: Program Register System parameter Register Name Width Bit efuse_wr_disable 16 [15:0] efuse_rd_disable 4 [3:0] flash_crypt_cnt 8 [7:0] WIFI_MAC_Address 56 SPI_pad_config_hd 5 [4:0] chip_version 4 [3:0] XPD_SDIO_REG 1 [0] SDIO_TIEH 1 [0] sdio_force 1 [0] Espressif Systems Name Bit [15:0] EFUSE_BLK0_WDATA0_REG [19:16] [27:20] [31:0] EFUSE_BLK0_WDATA1_REG [31:0] [55:32] EFUSE_BLK0_WDATA2_REG [23:0] EFUSE_BLK0_WDATA3_REG [8:4] [12:9] [14] EFUSE_BLK0_WDATA4_REG [15] [16] 385 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER System parameter Register Name Width Bit SPI_pad_config_clk 5 [4:0] [4:0] SPI_pad_config_q 5 [4:0] [9:5] SPI_pad_config_d 5 [4:0] SPI_pad_config_cs0 5 [4:0] [19:15] flash_crypt_config 4 [3:0] [31:28] coding_scheme 2 [1:0] [1:0] console_debug_disable 1 [0] [2] abstract_done_0 1 [0] [4] abstract_done_1 1 [0] [5] JTAG_disable 1 [0] download_dis_encrypt 1 [0] [7] download_dis_decrypt 1 [0] [8] download_dis_cache 1 [0] [9] key_status 1 [0] [10] BLOCK1 BLOCK2 BLOCK3 256/192/128 256/192/128 256/192/128 Name EFUSE_BLK0_WDATA5_REG EFUSE_BLK0_WDATA6_REG Bit [14:10] [6] [31:0] EFUSE_BLK1_WDATA0_REG [31:0] [63:32] EFUSE_BLK1_WDATA1_REG [31:0] [95:64] EFUSE_BLK1_WDATA2_REG [31:0] [127:96] EFUSE_BLK1_WDATA3_REG [31:0] [159:128] EFUSE_BLK1_WDATA4_REG [31:0] [191:160] EFUSE_BLK1_WDATA5_REG [31:0] [223:192] EFUSE_BLK1_WDATA6_REG [31:0] [255:224] EFUSE_BLK1_WDATA7_REG [31:0] [31:0] EFUSE_BLK2_WDATA0_REG [31:0] [63:32] EFUSE_BLK2_WDATA1_REG [31:0] [95:64] EFUSE_BLK2_WDATA2_REG [31:0] [127:96] EFUSE_BLK2_WDATA3_REG [31:0] [159:128] EFUSE_BLK2_WDATA4_REG [31:0] [191:160] EFUSE_BLK2_WDATA5_REG [31:0] [223:192] EFUSE_BLK2_WDATA6_REG [31:0] [255:224] EFUSE_BLK2_WDATA7_REG [31:0] [31:0] EFUSE_BLK3_WDATA0_REG [31:0] [63:32] EFUSE_BLK3_WDATA1_REG [31:0] [95:64] EFUSE_BLK3_WDATA2_REG [31:0] [127:96] EFUSE_BLK3_WDATA3_REG [31:0] [159:128] EFUSE_BLK3_WDATA4_REG [31:0] [191:160] EFUSE_BLK3_WDATA5_REG [31:0] [223:192] EFUSE_BLK3_WDATA6_REG [31:0] [255:224] EFUSE_BLK3_WDATA7_REG [31:0] The process of programming system parameters is as follows: 1. Configure EFUSE_CLK_SEL0 bit, EFUSE_CLK_SEL1 bit of register EFUSE_CLK, and EFUSE_DAC_CLK_DIV bit of register EFUSE_DAC_CONF. 2. Set the corresponding register bit of the system parameter bit to be programmed to 1. Espressif Systems 386 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 3. Write 0x5A5A into register EFUSE_CONF. 4. Write 0x2 into register EFUSE_CMD. 5. Poll register EFUSE_CMD until it is 0x0, or wait for a program-done interrupt. 6. Write 0x5AA5 into register EFUSE_CONF. 7. Write 0x1 into register EFUSE_CMD. 8. Poll register EFUSE_CMD until it is 0x0, or wait for a read-done interrupt. 9. Set the corresponding register bit of the programmed bit to 0. The configuration values of the EFUSE_CLK_SEL0 bit, EFUSE_CLK_SEL1 bit of register EFUSE_CLK, and the EFUSE_DAC_CLK_DIV bit of register EFUSE_DAC_CONF are based on the current APB_CLK frequency, as is shown in Table 61. Table 61: Timing Configuration Configuration Value APB_CLK Frequency 26 MHz 40 MHz 80 MHz EFUSE_CLK_SEL0[7:0] 8’d250 8’d160 8’d80 EFUSE_CLK_SEL1[7:0] 8’d255 8’d255 8’d128 EFUSE_DAC_CLK_DIV[7:0] 8’d52 8’d80 8’d160 Register EFUSE_CLK EFUSE_DAC_CONF The two methods to identify the generation of program/read-done interrupts are as follows: Method One: 1. Poll bit 1/0 in register EFUSE_INT_RAW until bit 1/0 is 1, which represents the generation of an program/read-done interrupt. 2. Set the bit 1/0 in register EFUSE_INT_CLR to 1 to clear the program/read-done interrupts. Method Two: 1. Set bit 1/0 in register EFUSE_INT_ENA to 1 to enable eFuse Controller to post a program/read-done interrupt. 2. Configure Interrupt Matrix to enable the CPU to respond to an EFUSE_INT interrupt. 3. A program/read-done interrupt is generated. 4. Read bit 1/0 in register EFUSE_INT_ST to identify the generation of the program/read-done interrupt. 5. Set bit 1/0 in register EFUSE_INT_CLR to 1 to clear the program/read-done interrupt. The programming of different system parameters and even the programming of different bits of the same system parameter can be completed separately in multiple programmings. It is, however, recommended that users minimize programming cycles, and program all the bits that need to be programmed in a system parameter in one programming action. In addition, after all system parameters controlled by a certain bit of efuse_wr_disable are programmed, that bit should be immediately programmed. The programming of system parameters controlled by a certain bit of efuse_wr_disable, and the programming of that bit can even be completed at the same time. Repeated programming of programmed bits is strictly forbidden. Espressif Systems 387 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 17.3.3 Software Reading of System Parameters Each bit of the 23 fixed-length system parameters and the three variable-length system parameters corresponds to a software-read register bit, as shown in Table 62. Software can use the value of each system parameter by reading the value in the corresponding register. The bit width of system parameters BLOCK1, BLOCK2, and BLOCK3 is variable. Although 256 register bits have been assigned to each of the three parameters, as shown in Table 62, some of the 256 register bits are useless in the 3/4 coding and the Repeat coding scheme. In the None coding scheme, the corresponding register bit of each bit of BLOCKN [255 : 0] is used. In the 3/4 coding scheme, only the corresponding register bits of BLOCKN [191 : 0] are useful. In Repeat coding scheme, only the corresponding bits of BLOCKN [127 : 0] are useful. In different coding schemes, the values of useless register bits read by software are invalid. The values of useful register bits read by software are the system parameters BLOCK1, BLOCK2, and BLOCK3 themselves instead of their values after being encoded. Table 62: Software Read Register System parameter Register Name Bit Width Bit efuse_wr_disable 16 [15:0] efuse_rd_disable 4 [3:0] flash_crypt_cnt 8 [7:0] WIFI_MAC_Address 56 SPI_pad_config_hd 5 [4:0] chip_version 4 [3:0] XPD_SDIO_REG 1 [0] SDIO_TIEH 1 [0] sdio_force 1 [0] [16] SPI_pad_config_clk 5 [4:0] [4:0] SPI_pad_config_q 5 [4:0] [9:5] SPI_pad_config_d 5 [4:0] SPI_pad_config_cs0 5 [4:0] [19:15] flash_crypt_config 4 [3:0] [31:28] coding_scheme 2 [1:0] [1:0] console_debug_disable 1 [0] [2] abstract_done_0 1 [0] [4] abstract_done_1 1 [0] [5] JTAG_disable 1 [0] download_dis_encrypt 1 [0] [7] download_dis_decrypt 1 [0] [8] download_dis_cache 1 [0] [9] key_status 1 [0] [10] Espressif Systems Name Bit [15:0] EFUSE_BLK0_RDATA0_REG [19:16] [27:20] [31:0] EFUSE_BLK0_RDATA1_REG [31:0] [55:32] EFUSE_BLK0_RDATA2_REG [23:0] 388 EFUSE_BLK0_RDATA3_REG [8:4] [12:9] [14] EFUSE_BLK0_RDATA4_REG EFUSE_BLK0_RDATA5_REG EFUSE_BLK0_RDATA6_REG [15] [14:10] [6] ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER System parameter Name Bit Width BLOCK1 BLOCK2 BLOCK3 256/192/128 256/192/128 256/192/128 Register Bit Name Bit [31:0] EFUSE_BLK1_RDATA0_REG [31:0] [63:32] EFUSE_BLK1_RDATA1_REG [31:0] [95:64] EFUSE_BLK1_RDATA2_REG [31:0] [127:96] EFUSE_BLK1_RDATA3_REG [31:0] [159:128] EFUSE_BLK1_RDATA4_REG [31:0] [191:160] EFUSE_BLK1_RDATA5_REG [31:0] [223:192] EFUSE_BLK1_RDATA6_REG [31:0] [255:224] EFUSE_BLK1_RDATA7_REG [31:0] [31:0] EFUSE_BLK2_RDATA0_REG [31:0] [63:32] EFUSE_BLK2_RDATA1_REG [31:0] [95:64] EFUSE_BLK2_RDATA2_REG [31:0] [127:96] EFUSE_BLK2_RDATA3_REG [31:0] [159:128] EFUSE_BLK2_RDATA4_REG [31:0] [191:160] EFUSE_BLK2_RDATA5_REG [31:0] [223:192] EFUSE_BLK2_RDATA6_REG [31:0] [255:224] EFUSE_BLK2_RDATA7_REG [31:0] [31:0] EFUSE_BLK3_RDATA0_REG [31:0] [63:32] EFUSE_BLK3_RDATA1_REG [31:0] [95:64] EFUSE_BLK3_RDATA2_REG [31:0] [127:96] EFUSE_BLK3_RDATA3_REG [31:0] [159:128] EFUSE_BLK3_RDATA4_REG [31:0] [191:160] EFUSE_BLK3_RDATA5_REG [31:0] [223:192] EFUSE_BLK3_RDATA6_REG [31:0] [255:224] EFUSE_BLK3_RDATA7_REG [31:0] 17.3.4 The Use of System Parameters by Hardware Modules Hardware modules are directly hardwired to the ESP32 in order to use the system parameters. Software cannot change this behaviour. Hardware modules use the decoded values of system parameters BLOCK1, BLOCK2, and BLOCK3, not their encoded values. 17.3.5 Interrupts • EFUSE_PGM_DONE_INT: Triggered when eFuse programming has finished. • EFUSE_READ_DONE_INT: Triggered when eFuse reading has finished. 17.4 Register Summary Name Description Address Access EFUSE_BLK0_RDATA0_REG Returns data word 0 in eFuse BLOCK 0 0x3FF5A000 RO EFUSE_BLK0_RDATA1_REG Returns data word 1 in eFuse BLOCK 0 0x3FF5A004 RO EFUSE_BLK0_RDATA2_REG Returns data word 2 in eFuse BLOCK 0 0x3FF5A008 RO eFuse data read registers Espressif Systems 389 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER Name Description Address Access EFUSE_BLK0_RDATA3_REG Returns data word 3 in eFuse BLOCK 0 0x3FF5A00C RO EFUSE_BLK0_RDATA4_REG Returns data word 4 in eFuse BLOCK 0 0x3FF5A010 RO EFUSE_BLK0_RDATA5_REG Returns data word 5 in eFuse BLOCK 0 0x3FF5A014 RO EFUSE_BLK0_RDATA6_REG Returns data word 6 in eFuse BLOCK 0 0x3FF5A018 RO EFUSE_BLK1_RDATA0_REG Returns data word 0 in eFuse BLOCK 1 0x3FF5A038 RO EFUSE_BLK1_RDATA1_REG Returns data word 1 in eFuse BLOCK 1 0x3FF5A03C RO EFUSE_BLK1_RDATA2_REG Returns data word 2 in eFuse BLOCK 1 0x3FF5A040 RO EFUSE_BLK1_RDATA3_REG Returns data word 3 in eFuse BLOCK 1 0x3FF5A044 RO EFUSE_BLK1_RDATA4_REG Returns data word 4 in eFuse BLOCK 1 0x3FF5A048 RO EFUSE_BLK1_RDATA5_REG Returns data word 5 in eFuse BLOCK 1 0x3FF5A04C RO EFUSE_BLK1_RDATA6_REG Returns data word 6 in eFuse BLOCK 1 0x3FF5A050 RO EFUSE_BLK1_RDATA7_REG Returns data word 7 in eFuse BLOCK 1 0x3FF5A054 RO EFUSE_BLK2_RDATA0_REG Returns data word 0 in eFuse BLOCK 2 0x3FF5A058 RO EFUSE_BLK2_RDATA1_REG Returns data word 1 in eFuse BLOCK 2 0x3FF5A05C RO EFUSE_BLK2_RDATA2_REG Returns data word 2 in eFuse BLOCK 2 0x3FF5A060 RO EFUSE_BLK2_RDATA3_REG Returns data word 3 in eFuse BLOCK 2 0x3FF5A064 RO EFUSE_BLK2_RDATA4_REG Returns data word 4 in eFuse BLOCK 2 0x3FF5A068 RO EFUSE_BLK2_RDATA5_REG Returns data word 5 in eFuse BLOCK 2 0x3FF5A06C RO EFUSE_BLK2_RDATA6_REG Returns data word 6 in eFuse BLOCK 2 0x3FF5A070 RO EFUSE_BLK2_RDATA7_REG Returns data word 7 in eFuse BLOCK 2 0x3FF5A074 RO EFUSE_BLK3_RDATA0_REG Returns data word 0 in eFuse BLOCK 3 0x3FF5A078 RO EFUSE_BLK3_RDATA1_REG Returns data word 1 in eFuse BLOCK 3 0x3FF5A07C RO EFUSE_BLK3_RDATA2_REG Returns data word 2 in eFuse BLOCK 3 0x3FF5A080 RO EFUSE_BLK3_RDATA3_REG Returns data word 3 in eFuse BLOCK 3 0x3FF5A084 RO EFUSE_BLK3_RDATA4_REG Returns data word 4 in eFuse BLOCK 3 0x3FF5A088 RO EFUSE_BLK3_RDATA5_REG Returns data word 5 in eFuse BLOCK 3 0x3FF5A08C RO EFUSE_BLK3_RDATA6_REG Returns data word 6 in eFuse BLOCK 3 0x3FF5A090 RO EFUSE_BLK3_RDATA7_REG Returns data word 7 in eFuse BLOCK 3 0x3FF5A094 RO EFUSE_BLK0_WDATA0_REG Writes data to word 0 in eFuse BLOCK 0 0x3FF5A01c R/W EFUSE_BLK0_WDATA1_REG Writes data to word 1 in eFuse BLOCK 0 0x3FF5A020 R/W EFUSE_BLK0_WDATA2_REG Writes data to word 2 in eFuse BLOCK 0 0x3FF5A024 R/W EFUSE_BLK0_WDATA3_REG Writes data to word 3 in eFuse BLOCK 0 0x3FF5A028 R/W EFUSE_BLK0_WDATA4_REG Writes data to word 4 in eFuse BLOCK 0 0x3FF5A02c R/W EFUSE_BLK0_WDATA5_REG Writes data to word 5 in eFuse BLOCK 0 0x3FF5A030 R/W EFUSE_BLK0_WDATA6_REG Writes data to word 6 in eFuse BLOCK 0 0x3FF5A034 R/W EFUSE_BLK1_WDATA0_REG Writes data to word 0 in eFuse BLOCK 1 0x3FF5A098 R/W EFUSE_BLK1_WDATA1_REG Writes data to word 1 in eFuse BLOCK 1 0x3FF5A09c R/W EFUSE_BLK1_WDATA2_REG Writes data to word 2 in eFuse BLOCK 1 0x3FF5A0a0 R/W EFUSE_BLK1_WDATA3_REG Writes data to word 3 in eFuse BLOCK 1 0x3FF5A0a4 R/W EFUSE_BLK1_WDATA4_REG Writes data to word 4 in eFuse BLOCK 1 0x3FF5A0a8 R/W EFUSE_BLK1_WDATA5_REG Writes data to word 5 in eFuse BLOCK 1 0x3FF5A0ac R/W EFUSE_BLK1_WDATA6_REG Writes data to word 6 in eFuse BLOCK 1 0x3FF5A0b0 R/W EFUSE_BLK1_WDATA7_REG Writes data to word 7 in eFuse BLOCK 1 0x3FF5A0b4 R/W eFuse data write registers Espressif Systems 390 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER Name Description Address Access EFUSE_BLK2_WDATA0_REG Writes data to word 0 in eFuse BLOCK 2 0x3FF5A0b8 R/W EFUSE_BLK2_WDATA1_REG Writes data to word 1 in eFuse BLOCK 2 0x3FF5A0bc R/W EFUSE_BLK2_WDATA2_REG Writes data to word 2 in eFuse BLOCK 2 0x3FF5A0c0 R/W EFUSE_BLK2_WDATA3_REG Writes data to word 3 in eFuse BLOCK 2 0x3FF5A0c4 R/W EFUSE_BLK2_WDATA4_REG Writes data to word 4 in eFuse BLOCK 2 0x3FF5A0c8 R/W EFUSE_BLK2_WDATA5_REG Writes data to word 5 in eFuse BLOCK 2 0x3FF5A0cc R/W EFUSE_BLK2_WDATA6_REG Writes data to word 6 in eFuse BLOCK 2 0x3FF5A0d0 R/W EFUSE_BLK2_WDATA7_REG Writes data to word 7 in eFuse BLOCK 2 0x3FF5A0d4 R/W EFUSE_BLK3_WDATA0_REG Writes data to word 0 in eFuse BLOCK 3 0x3FF5A0d8 R/W EFUSE_BLK3_WDATA1_REG Writes data to word 1 in eFuse BLOCK 3 0x3FF5A0dc R/W EFUSE_BLK3_WDATA2_REG Writes data to word 2 in eFuse BLOCK 3 0x3FF5A0e0 R/W EFUSE_BLK3_WDATA3_REG Writes data to word 3 in eFuse BLOCK 3 0x3FF5A0e4 R/W EFUSE_BLK3_WDATA4_REG Writes data to word 4 in eFuse BLOCK 3 0x3FF5A0e8 R/W EFUSE_BLK3_WDATA5_REG Writes data to word 5 in eFuse BLOCK 3 0x3FF5A0ec R/W EFUSE_BLK3_WDATA6_REG Writes data to word 6 in eFuse BLOCK 3 0x3FF5A0f0 R/W EFUSE_BLK3_WDATA7_REG Writes data to word 7 in eFuse BLOCK 3 0x3FF5A0f4 R/W EFUSE_CLK_REG Timing configuration register 0x3FF5A0F8 R/W EFUSE_CONF_REG Opcode register 0x3FF5A0FC R/W EFUSE_CMD_REG Read/write command register 0x3FF5A104 R/W EFUSE_INT_RAW_REG Raw interrupt status 0x3FF5A108 RO EFUSE_INT_ST_REG Masked interrupt status 0x3FF5A10C RO EFUSE_INT_ENA_REG Interrupt enable bits 0x3FF5A110 R/W EFUSE_INT_CLR_REG Interrupt clear bits 0x3FF5A114 WO EFUSE_DAC_CONF_REG Efuse timing configuration 0x3FF5A118 R/W EFUSE_DEC_STATUS_REG Status of 3/4 coding scheme 0x3FF5A11C RO Control registers Interrupt registers Misc registers Espressif Systems 391 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 17.5 Registers 0 0 0 20 0 0 0 0 DI S R_ E_ W US RD _E F EF US 27 0 0 EF US E_ E_ EF US 28 E_ RD ) ed rv se (re 31 RD _E _F LA FU S SH E_ RD _C RY P _D IS T_ CN T Register 17.1: EFUSE_BLK0_RDATA0_REG (0x000) 0 0 19 0 0 16 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 Reset EFUSE_RD_FLASH_CRYPT_CNT This field returns the value of flash_crypt_cnt. (RO) EFUSE_RD_EFUSE_RD_DIS This field returns the value of efuse_rd_disable. (RO) EFUSE_RD_EFUSE_WR_DIS This field returns the value of efuse_wr_disable. (RO) Register 17.2: EFUSE_BLK0_RDATA1_REG (0x004) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFUSE_BLK0_RDATA1_REG This field returns the value of the lower 32 bits of WIFI_MAC_Address. (RO) (re EF US E_ se rv ed ) RD _W IF I_ M AC _C RC _H IG H Register 17.3: EFUSE_BLK0_RDATA2_REG (0x008) 31 0 24 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_RD_WIFI_MAC_CRC_HIGH This field returns the value of the higher 24 bits of WIFI_MAC_Address. (RO) Espressif Systems 392 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 31 0 9 0 0 0 0 0 0 0 0 0 0 0 0 ed ) (re se rv (re s er EF US ve d) E_ RD _S P I_ PA D_ CO NF IG _H D Register 17.4: EFUSE_BLK0_RDATA3_REG (0x00c) 0 0 0 0 0 0 0 0 0 8 0 0 4 0 0 0 7 4 0 0 0 0 0 Reset EFUSE_RD_SPI_PAD_CONFIG_HD This field returns the value of SPI_pad_config_hd. (RO) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 27 0 0 0 0 0 ed ) se rv (re (re se rv ed ) EF U EF SE_ U R EF SE_ D_S US RD D E_ _S IO_ RD D FO _X IO_ RC PD TIE E _S H DI O Register 17.5: EFUSE_BLK0_RDATA4_REG (0x010) 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_RD_SDIO_FORCE This field returns the value of sdio_force. (RO) EFUSE_RD_SDIO_TIEH This field returns the value of SDIO_TIEH. (RO) EFUSE_RD_XPD_SDIO This field returns the value of XPD_SDIO_REG. (RO) Espressif Systems 393 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 0 0 20 0 0 0 0 0 0 15 0 0 0 14 0 0 10 0 0 0 _C LK NF IG PI D_ S _R US E EF 9 5 0 0 _P AD _C O NF IG PA D_ CO I_ RD _S P E_ EF US EF 19 0 0 _Q _D NF IG _C O _S P _R D US E US E EF 27 0 0 I_ I_ _R d) ve er (re s 28 0 D_ SP LA D_ F _R US E EF 31 PA D PA D SH _C _C O RY P T_ C NF IG O NF _C S0 IG Register 17.6: EFUSE_BLK0_RDATA5_REG (0x014) 0 0 0 4 0 0 0 0 0 0 0 Reset EFUSE_RD_FLASH_CRYPT_CONFIG This field returns the value of flash_crypt_config. (RO) EFUSE_RD_SPI_PAD_CONFIG_CS0 This field returns the value of SPI_pad_config_cs0. (RO) EFUSE_RD_SPI_PAD_CONFIG_D This field returns the value of SPI_pad_config_d. (RO) EFUSE_RD_SPI_PAD_CONFIG_Q This field returns the value of SPI_pad_config_q. (RO) EFUSE_RD_SPI_PAD_CONFIG_CLK This field returns the value of SPI_pad_config_clk. (RO) (re se rv e d) EF U EF SE_ US RD EF E_ _K U R E EF SE_ D_D Y_S US RD IS TA EF E_ _D AB TU U R IS LE S EF SE_ D_D AB _D U R IS LE L_ EF SE_ D_D AB _D CA U R IS LE L_ CH (re SE_ D_A AB _D DE E se R B LE L_ CR EF rve D_A S_D _JT EN YP US d) BS O AG CR T YP E _D NE T EF _RD O _1 NE US _C _ E_ O 0 RD NS _C OL E_ O DI D NG EB UG _S _D CH EM ISA BL E E Register 17.7: EFUSE_BLK0_RDATA6_REG (0x018) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_RD_KEY_STATUS This field returns the value of key_status. (RO) EFUSE_RD_DISABLE_DL_CACHE This field returns the value of download_dis_cache. (RO) EFUSE_RD_DISABLE_DL_DECRYPT This field returns the value of download_dis_decrypt. (RO) EFUSE_RD_DISABLE_DL_ENCRYPT This field returns the value of download_dis_encrypt. (RO) EFUSE_RD_DISABLE_JTAG This field returns the value of JTAG_disable. (RO) EFUSE_RD_ABS_DONE_1 This field returns the value of abstract_done_1. (RO) EFUSE_RD_ABS_DONE_0 This field returns the value of abstract_done_0. (RO) EFUSE_RD_CONSOLE_DEBUG_DISABLE This field returns the value of console_debug_disable. (RO) EFUSE_RD_CODING_SCHEME This field returns the value of coding_scheme. (RO) Espressif Systems 394 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 0 0 27 0 0 20 0 0 0 0 R_ DI S W EF US E_ EF US EF US 28 0 E_ FL A E_ d) ve er (re s 31 RD _D SH IS _C RY P T_ C NT Register 17.8: EFUSE_BLK0_WDATA0_REG (0x01c) 0 0 19 0 0 16 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_FLASH_CRYPT_CNT This field programs the value of flash_crypt_cnt. (R/W) EFUSE_RD_DIS This field programs the value of efuse_rd_disable. (R/W) EFUSE_WR_DIS This field programs the value of efuse_wr_disable. (R/W) Register 17.9: EFUSE_BLK0_WDATA1_REG (0x020) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_BLK0_WDATA1_REG This field programs the value of lower 32 bits of WIFI_MAC_Address. (R/W) (re EF US E_ se rv ed ) W IF I_ M AC _C RC _H IG H Register 17.10: EFUSE_BLK0_WDATA2_REG (0x024) 31 0 24 0 0 0 0 0 0 23 0 0 0 0 0 0 0 EFUSE_WIFI_MAC_CRC_HIGH This 0 0 field 0 0 0 0 programs 0 0 the 0 0 value 0 0 of 0 0 0 higher 0 24 0 0 bits 0 Reset of WIFI_MAC_Address. (R/W) Espressif Systems 395 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER 31 0 9 0 0 0 0 0 0 0 0 0 0 0 0 ed ) (re se rv (re s er EF US ve d) E_ SP I_ PA D_ CO NF IG _H D Register 17.11: EFUSE_BLK0_WDATA3_REG (0x028) 0 0 0 0 0 0 0 0 0 8 4 0 0 0 0 0 7 4 0 0 0 0 0 Reset EFUSE_SPI_PAD_CONFIG_HD This field programs the value of SPI_pad_config_hd. (R/W) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 27 0 0 0 0 0 ) rv ed (re se (re se r ve d) EF U EF SE_ U S EF SE_ DIO US SD _F E_ IO OR XP _T CE D_ IEH SD IO Register 17.12: EFUSE_BLK0_WDATA4_REG (0x02c) 14 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_SDIO_FORCE This field programs the value of SDIO_TIEH. (R/W) EFUSE_SDIO_TIEH This field programs the value of SDIO_TIEH. (R/W) EFUSE_XPD_SDIO This field programs the value of XPD_SDIO_REG. (R/W) 31 0 28 0 0 27 0 0 20 0 0 0 0 0 0 19 0 0 15 0 0 0 14 0 0 0 0 9 0 0 _C LK IG NF IG PA D_ CO NF PA D_ CO EF US E_ SP I_ I_ SP E_ US EF 10 0 _Q _D IG NF _P AD _C O _S PI EF US E SE _S PI EF U (re EF US se rv E_ ed ) FL AS H_ _P AD _C O CR YP NF T_ IG CO _C NF S0 IG Register 17.13: EFUSE_BLK0_WDATA5_REG (0x030) 5 0 0 0 4 0 0 0 0 0 0 0 Reset EFUSE_FLASH_CRYPT_CONFIG This field programs the value of flash_crypt_config. (R/W) EFUSE_SPI_PAD_CONFIG_CS0 This field programs the value of SPI_pad_config_cs0. (R/W) EFUSE_SPI_PAD_CONFIG_D This field programs the value of SPI_pad_config_d. (R/W) EFUSE_SPI_PAD_CONFIG_Q This field programs the value of SPI_pad_config_q. (R/W) EFUSE_SPI_PAD_CONFIG_CLK This field programs the value of SPI_pad_config_clk. (R/W) Espressif Systems 396 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER (re s er ve d) EF U EF SE_ U K EF SE_ EY_ U D ST EF SE_ ISA AT U D BL US EF SE_ ISA E_ US DI BL DL EF E_ SA E_ _C U D BL DL AC EF SE_ ISA E_ _DE HE U A BL DL C (re SE_ BS_ E_ _EN RY se A D JTA C PT EF rve BS_ ON G RY PT US d) DO E_ E_ NE 1 C EF _0 US ON SO E_ CO LE _D DI NG EB UG _S _D CH EM ISA BL E E Register 17.14: EFUSE_BLK0_WDATA6_REG (0x034) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_KEY_STATUS This field programs the value of key_status. (R/W) EFUSE_DISABLE_DL_CACHE This field programs the value of download_dis_cache. (R/W) EFUSE_DISABLE_DL_DECRYPT This field programs the value of download_dis_decrypt. (R/W) EFUSE_DISABLE_DL_ENCRYPT This field programs the value of download_dis_encrypt. (R/W) EFUSE_DISABLE_JTAG This field programs the value of JTAG_disable. (R/W) EFUSE_ABS_DONE_1 This field programs the value of abstract_done_1. (R/W) EFUSE_ABS_DONE_0 This field programs the value of abstract_done_0. (R/W) EFUSE_CONSOLE_DEBUG_DISABLE This field programs the value of console_debug_disable. (R/W) EFUSE_CODING_SCHEME This field programs the value of coding_scheme. (R/W) Register 17.15: EFUSE_BLK1_RDATAn_REG (n: 0-7) (0x38+4*n) 31 0 0x000000000 Reset EFUSE_BLK1_RDATAn_REG This field returns the value of word n in BLOCK1. (RO) Register 17.16: EFUSE_BLK2_RDATAn_REG (n: 0-7) (0x58+4*n) 31 0 0x000000000 Reset EFUSE_BLK2_RDATAn_REG This field returns the value of word n in BLOCK2. (RO) Espressif Systems 397 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER Register 17.17: EFUSE_BLK3_RDATAn_REG (n: 0-7) (0x78+4*n) 31 0 0x000000000 Reset EFUSE_BLK3_RDATAn_REG This field returns the value of word n in BLOCK3. (RO) Register 17.18: EFUSE_BLK1_WDATAn_REG (n: 0-7) (0x98+4*n) 31 0 0x000000000 Reset EFUSE_BLK1_WDATAn_REG This field programs the value of word n in of BLOCK1. (R/W) Register 17.19: EFUSE_BLK2_WDATAn_REG (n: 0-7) (0xB8+4*n) 31 0 0x000000000 Reset EFUSE_BLK2_WDATAn_REG This field programs the value of word n in of BLOCK2. (R/W) Register 17.20: EFUSE_BLK3_WDATAn_REG (n: 0-7) (0xD8+4*n) 31 0 0x000000000 Reset EFUSE_BLK3_WDATAn_REG This field programs the value of word n in of BLOCK3. (R/W) 0 0 0 0 0 0 0 US EF US EF 16 0 E_ CL E_ d) rv e (re se 31 0 CL K_ K_ SE SE L1 L0 Register 17.21: EFUSE_CLK_REG (0x0f8) 0 0 0 0 0 0 15 0 8 0x040 7 0 0x052 Reset EFUSE_CLK_SEL1 eFuse clock configuration field. (R/W) EFUSE_CLK_SEL0 eFuse clock configuration field. (R/W) Espressif Systems 398 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER (re se r EF US E_ ve d) O P_ CO DE Register 17.22: EFUSE_CONF_REG (0x0fc) 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0x00000 Reset EFUSE_OP_CODE eFuse operation code register. (R/W) (re se rv ed ) EF U EF SE_ US PG E_ M RE _C AD MD _C M D Register 17.23: EFUSE_CMD_REG (0x104) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset EFUSE_PGM_CMD Set this to 1 to start a program operation. Reverts to 0 when the program operation is done. (R/W) EFUSE_READ_CMD Set this to 1 to start a read operation. Reverts to 0 when the read operation is done. (R/W) (re se rv e d) EF U EF SE_ US PG E_ M RE _D AD ON _D E_ O INT NE _ _I RA NT W _R AW Register 17.24: EFUSE_INT_RAW_REG (0x108) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset EFUSE_PGM_DONE_INT_RAW The raw interrupt status bit for the EFUSE_PGM_DONE_INT interrupt. (RO) EFUSE_READ_DONE_INT_RAW The raw interrupt status bit for the EFUSE_READ_DONE_INT interrupt. (RO) Espressif Systems 399 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER (re s er v ed ) EF U EF SE_ US PG E_ M RE _D AD ON _D E_ O INT NE _ _I ST NT _S T Register 17.25: EFUSE_INT_ST_REG (0x10c) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset EFUSE_PGM_DONE_INT_ST The masked interrupt status bit for the EFUSE_PGM_DONE_INT interrupt. (RO) EFUSE_READ_DONE_INT_ST The masked interrupt status bit for the EFUSE_READ_DONE_INT interrupt. (RO) (re EF se rv ed ) U EF SE_ US PG E_ M RE _D AD ON _D E_ O INT NE _ _I EN NT A _E NA Register 17.26: EFUSE_INT_ENA_REG (0x110) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset EFUSE_PGM_DONE_INT_ENA The interrupt enable bit for the EFUSE_PGM_DONE_INT interrupt. (R/W) EFUSE_READ_DONE_INT_ENA The interrupt enable bit for the EFUSE_READ_DONE_INT interrupt. (R/W) (re se rv ed ) EF U EF SE_ US PG E_ M RE _D AD ON _D E_ O INT NE _ _I CL NT R _C LR Register 17.27: EFUSE_INT_CLR_REG (0x114) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 Reset EFUSE_PGM_DONE_INT_CLR Set this bit to clear the EFUSE_PGM_DONE_INT interrupt. (WO) EFUSE_READ_DONE_INT_CLR Set this bit to clear the EFUSE_READ_DONE_INT interrupt. (WO) Espressif Systems 400 ESP32 Technical Reference Manual V2.0 17. EFUSE CONTROLLER EF (re s er US E ve d) _D AC _C LK _D IV Register 17.28: EFUSE_DAC_CONF_REG (0x118) 31 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 40 Reset EFUSE_DAC_CLK_DIV Efuse timing configuration register. (R/W) (re se r EF US ve d) E_ DE C_ W AR NI NG S Register 17.29: EFUSE_DEC_STATUS_REG (0x11c) 31 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset EFUSE_DEC_WARNINGS If a bit is set in this register, it means some errors were corrected while decoding the 3/4 encoding scheme. (RO) Espressif Systems 401 ESP32 Technical Reference Manual V2.0 18. AES ACCELERATOR 18. AES Accelerator 18.1 Introduction The AES Accelerator speeds up AES operations significantly, compared to AES algorithms implemented solely in software. The AES Accelerator supports six algorithms of FIPS PUB 197, specifically AES-128, AES-192 and AES-256 encryption and decryption. 18.2 Features • Supports AES-128 encryption and decryption • Supports AES-192 encryption and decryption • Supports AES-256 encryption and decryption • Supports four variations of key endianness and four variations of text endianness 18.3 Functional Description 18.3.1 AES Algorithm Operations The AES Accelerator supports six algorithms of FIPS PUB 197, specifically AES-128, AES-192 and AES-256 encryption and decryption. The AES_MODE_REG register can be configured to different values to enable different algorithm operations, as shown in Table 64. Table 64: Operation Mode AES_MODE_REG[2:0] Operation 0 AES-128 Encryption 1 AES-192 Encryption 2 AES-256 Encryption 4 AES-128 Decryption 5 AES-192 Decryption 6 AES-256 Decryption 18.3.2 Key, Plaintext and Ciphertext The encryption or decryption key is stored in AES_KEY_n_REG, which is a set of eight 32-bit registers. For AES-128 encryption/decryption, the 128-bit key is stored in AES_KEY_0_REG ~ AES_KEY_3_REG. For AES-192 encryption/decryption, the 192-bit key is stored in AES_KEY_0_REG ~ AES_KEY_5_REG. For AES-256 encryption/decryption, the 256-bit key is stored in AES_KEY_0_REG ~ AES_KEY_7_REG. Plaintext and ciphertext is stored in the AES_TEXT_m_REG registers. There are four 32-bit registers. To enable AES-128/192/256 encryption, initialize the AES_TEXT_m_REG registers with plaintext before encryption. When encryption is finished, the AES Accelerator will store back the resulting ciphertext in the AES_TEXT_m_REG registers. To enable AES-128/192/256 decryption, initialize the AES_TEXT_m_REG registers with ciphertext before decryption. When decryption is finished, the AES Accelerator will store back the resulting plaintext in the AES_TEXT_m_REG registers. Espressif Systems 402 ESP32 Technical Reference Manual V2.0 18. AES ACCELERATOR 18.3.3 Endianness Key Endianness Bit 0 and bit 1 in AES_ENDIAN_REG define the key endianness. For detailed information, please see Table 66, Table 67 and Table 68. w[0] ~ w[3] in Table 66, w[0] ~ w[5] in Table 67 and w[0] ~ w[7] in Table 68 are “the first Nk words of the expanded key” as specified in “5.2: Key Expansion” of FIPS PUB 197. “Column Bit” specifies the bytes in the word from w[0] to w[7]. The bytes of AES_KEY_n_REG comprise “the first Nk words of the expanded key”. Text Endianness Bit 2 and bit 3 in AES_ENDIAN_REG define the endianness of input text, while Bit 4 and Bit 5 define the endianness of output text. The input text refers to the plaintext in AES-128/192/256 encryption and the ciphertext in decryption. The output text refers to the ciphertext in AES-128/192/256 encryption and the plaintext in decryption. For details, please see Table 65. “State” in Table 65 is defined as that in “3.4: The State” of FIPS PUB 197: “The AES algorithm operations are performed on a two-dimensional array of bytes called the State”. The ciphertext or plaintexts stored in each byte of AES_TEXT_m_REG comprise the State. Table 65: AES Text Endianness AES_ENDIAN_REG[3]/[5] AES_ENDIAN_REG[2]/[4] Plaintext/Ciphertext c State 0 0 r 0 1 2 3 0 AES_TEXT_3_REG[31:24] AES_TEXT_2_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_0_REG[31:24] 1 AES_TEXT_3_REG[23:16] AES_TEXT_2_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_0_REG[23:16] 2 AES_TEXT_3_REG[15:8] AES_TEXT_2_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_0_REG[15:8] 3 AES_TEXT_3_REG[7:0] AES_TEXT_2_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_0_REG[7:0] c State 0 1 r 0 1 2 3 0 AES_TEXT_3_REG[7:0] AES_TEXT_2_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_0_REG[7:0] 1 AES_TEXT_3_REG[15:8] AES_TEXT_2_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_0_REG[15:8] 2 AES_TEXT_3_REG[23:16] AES_TEXT_2_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_0_REG[23:16] 3 AES_TEXT_3_REG[31:24] AES_TEXT_2_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_0_REG[31:24] c State 1 0 r 0 1 2 3 0 AES_TEXT_0_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24] AES_TEXT_3_REG[31:24] 1 AES_TEXT_0_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16] AES_TEXT_3_REG[23:16] 2 AES_TEXT_0_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8] AES_TEXT_3_REG[15:8] 3 AES_TEXT_0_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0] AES_TEXT_3_REG[7:0] c State 1 1 r Espressif Systems 0 1 2 3 0 AES_TEXT_0_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0] AES_TEXT_3_REG[7:0] 1 AES_TEXT_0_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8] AES_TEXT_3_REG[15:8] 2 AES_TEXT_0_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16] AES_TEXT_3_REG[23:16] 3 AES_TEXT_0_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24] AES_TEXT_3_REG[31:24] 403 ESP32 Technical Reference Manual V2.0 AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] 0 0 0 1 1 0 1 1 Bit w[0] w[1] w[2] w[3] [31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [31:24] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [23:16] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [15:8] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [7:0] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] [23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] [15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] [7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] 18. AES ACCELERATOR Espressif Systems Table 66: AES-128 Key Endianness Table 67: AES-192 Key Endianness AES_ENDIAN_REG[1] 0 AES_ENDIAN_REG[0] 0 404 0 1 1 0 ESP32 Technical Reference Manual V2.0 1 1 Bit w[0] w[1] w[2] w[3] w[4] w[5] [31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [31:24] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [23:16] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [15:8] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [7:0] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] [23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] [15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] [7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] Table 68: AES-256 Key Endianness AES_ENDIAN_REG[1] 0 0 1 1 AES_ENDIAN_REG[0] 0 1 0 1 Bit w[0] w[1] w[2] w[3] w[4] w[5] w[6] w[7] [31:24] AES_KEY_7_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [23:16] AES_KEY_7_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [15:8] AES_KEY_7_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [7:0] AES_KEY_7_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [31:24] AES_KEY_7_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [23:16] AES_KEY_7_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [15:8] AES_KEY_7_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [7:0] AES_KEY_7_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24] [23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16] [15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8] [7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0] [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0] [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8] [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16] [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24] 18. AES ACCELERATOR 18.3.4 Encryption and Decryption Operations Single Operation 1. Initialize AES_MODE_REG, AES_KEY_n_REG, AES_TEXT_m_REG and AES_ENDIAN_REG. 2. Write 1 to AES_START_REG. 3. Wait until AES_IDLE_REG reads 1. 4. Read results from AES_TEXT_m_REG. Consecutive Operations Every time an operation is completed, only AES_TEXT_m_REG is modified by the AES Accelerator. Initialization can, therefore, be simplified in a series of consecutive operations. 1. Update contents of AES_MODE_REG, AES_KEY_n_REG and AES_ENDIAN_REG, if required. 2. Load AES_TEXT_m_REG. 3. Write 1 to AES_START_REG. 4. Wait until AES_IDLE_REG reads 1. 5. Read results from AES_TEXT_m_REG. 18.3.5 Speed The AES Accelerator requires 11 to 15 clock cycles to encrypt a message block, and 21 or 22 clock cycles to decrypt a message block. 18.4 Register Summary Name Description Address Access AES_MODE_REG Mode of operation of the AES Accelerator 0x3FF01008 R/W AES_ENDIAN_REG Endianness configuration register 0x3FF01040 R/W AES_KEY_0_REG AES key material register 0 0x3FF01010 R/W AES_KEY_1_REG AES key material register 1 0x3FF01014 R/W AES_KEY_2_REG AES key material register 2 0x3FF01018 R/W AES_KEY_3_REG AES key material register 3 0x3FF0101C R/W AES_KEY_4_REG AES key material register 4 0x3FF01020 R/W AES_KEY_5_REG AES key material register 5 0x3FF01024 R/W AES_KEY_6_REG AES key material register 6 0x3FF01028 R/W AES_KEY_7_REG AES key material register 7 0x3FF0102C R/W Configuration registers Key registers Encrypted/decrypted data registers AES_TEXT_0_REG AES encrypted/decrypted data register 0 0x3FF01030 R/W AES_TEXT_1_REG AES encrypted/decrypted data register 1 0x3FF01034 R/W AES_TEXT_2_REG AES encrypted/decrypted data register 2 0x3FF01038 R/W AES_TEXT_3_REG AES encrypted/decrypted data register 3 0x3FF0103C R/W Control/status registers Espressif Systems 405 ESP32 Technical Reference Manual V2.0 18. AES ACCELERATOR Name Description Address Access AES_START_REG AES operation start control register 0x3FF01000 WO AES_IDLE_REG AES idle status register 0x3FF01004 RO Espressif Systems 406 ESP32 Technical Reference Manual V2.0 18. AES ACCELERATOR 18.5 Registers AE (re s S_ er ve d) ST AR T Register 18.1: AES_START_REG (0x000) 31 1 0x00000000 0 x Reset AES_START Write 1 to start the AES operation. (WO) (re AE S_ se r ve d) ID LE Register 18.2: AES_IDLE_REG (0x004) 31 1 0x00000000 0 1 Reset AES_IDLE AES Idle register. Reads ’zero’ while the AES Accelerator is busy processing; reads ’one’ otherwise. (RO) (re AE se S_ M rv e O d) DE Register 18.3: AES_MODE_REG (0x008) 31 3 2 0x00000000 0 0 Reset AES_MODE Selects the AES accelerator mode of operation. See Table 64 for details. (R/W) Register 18.4: AES_KEY_n_REG (n: 0-7) (0x10+4*n) 31 0 0x000000000 Reset AES_KEY_n_REG (n: 0-7) AES key material register. (R/W) Register 18.5: AES_TEXT_m_REG (m: 0-3) (0x30+4*m) 31 0 0x000000000 Reset AES_TEXT_m_REG (m: 0-3) Plaintext and ciphertext register. (R/W) Espressif Systems 407 ESP32 Technical Reference Manual V2.0 18. AES ACCELERATOR AE (re se rv ed ) S_ EN DI AN Register 18.6: AES_ENDIAN_REG (0x040) 31 6 0x0000000 5 1 0 1 1 1 1 1 Reset AES_ENDIAN Endianness selection register. See Table 65 for details. (R/W) Espressif Systems 408 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR 19. SHA Accelerator 19.1 Introduction The SHA Accelerator is included to speed up SHA hashing operations significantly, compared to SHA hashing algorithms implemented solely in software. The SHA Accelerator supports four algorithms of FIPS PUB 180-4, specifically SHA-1, SHA-256, SHA-384 and SHA-512. 19.2 Features Hardware support for popular secure hashing algorithms: • SHA-1 • SHA-256 • SHA-384 • SHA-512 19.3 Functional Description 19.3.1 Padding and Parsing the Message The SHA Accelerator can only accept one message block at a time. Software divides the message into blocks according to “5.2 Parsing the Message” in FIPS PUB 180-4 and writes one block to the SHA_TEXT_n_REG registers each time. For SHA-1 and SHA-256, software writes a 512-bit message block to SHA_TEXT_0_REG ~ SHA_TEXT_15_REG each time. For SHA-384 and SHA-512, software writes a 1024-bit message block to SHA_TEXT_0_REG ~ SHA_TEXT_31_REG each time. The SHA Accelerator is unable to perform the padding operation of “5.1 Padding the Message” in FIPS PUB 180-4; Note that the user software is expected to pad the message before feeding it into the accelerator. (i) (i) As described in “2.2.1: Parameters” in FIPS PUB 180-4, “M0 is the leftmost word of message block i”. M0 is stored in SHA_TEXT_0_REG. In the same fashion, the SHA_TEXT_1_REG register stores the second left-most (N ) word of a message blockH1 , etc. 19.3.2 Message Digest When the hashing operation is finished, the message digest will be refreshed by SHA Accelerator and will be stored in SHA_TEXT_n_REG. SHA-1 produces a 160-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_4_REG. SHA-256 produces a 256-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_7_REG. SHA-384 produces a 384-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_11_REG. SHA-512 produces a 512-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_15_REG. As described in “2.2.1 Parameters” in FIPS PUB 180-4, “H (N ) is the final hash value, and is used to determine (i) (N ) the message digest”, while “H0 is the leftmost word of hash value i”, so the leftmost word H0 digest is stored in SHA_TEXT_0_REG. In the same fashion, the second leftmost word (N ) H1 in the message in the message digest is stored in SHA_TEXT_1_REG, etc. Espressif Systems 409 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR 19.3.3 Hash Operation There is a set of control registers for SHA-1, SHA-256, SHA-384 and SHA-512, respectively; different hashing algorithms use different control registers. SHA-1 uses SHA_SHA1_START_REG, SHA_SHA1_CONTINUE_REG, SHA_SHA1_LOAD_REG and SHA_SHA1_BUSY_REG. SHA-256 uses SHA_SHA256_START_REG, SHA_SHA256_CONTINUE_REG, SHA_SHA256_LOAD_REG and SHA_SHA256_BUSY_REG. SHA-384 uses SHA_SHA384_START_REG, SHA_SHA384_CONTINUE_REG, SHA_SHA384_LOAD_REG and SHA_SHA384_BUSY_REG. SHA-512 uses SHA_SHA512_START_REG, SHA_SHA512_CONTINUE_REG, SHA_SHA512_LOAD_REG and SHA_SHA512_BUSY_REG. The following steps describe the operation in a detailed manner. 1. Feed the accelerator with the first message block: (a) Use the first message block to initialize SHA_TEXT_n_REG. (b) Write 1 to SHA_X_START_REG. (c) Wait for SHA_X_BUSY_REG to read 0, indicating that the operation is completed. 2. Similarly, feed the accelerator with subsequent message blocks: (a) Initialize SHA_TEXT_n_REG using the subsequent message block. (b) Write 1 to SHA_X_CONTINUE_REG. (c) Wait for SHA_X_BUSY_REG to read 0, indicating that the operation is completed. 3. Get message digest: (a) Write 1 to SHA_X_LOAD_REG. (b) Wait for SHA_X_BUSY_REG to read 0, indicating that operation is completed. (c) Read message digest from SHA_TEXT_n_REG. 19.3.4 Speed The SHA Accelerator requires 60 to 100 clock cycles to process a message block and 8 to 20 clock cycles to calculate the final digest. 19.4 Register Summary Name Description Address Access Encrypted/decrypted data registers SHA_TEXT_0_REG SHA encrypted/decrypted data register 0 0x3FF03000 R/W SHA_TEXT_1_REG SHA encrypted/decrypted data register 1 0x3FF03004 R/W SHA_TEXT_2_REG SHA encrypted/decrypted data register 2 0x3FF03008 R/W SHA_TEXT_3_REG SHA encrypted/decrypted data register 3 0x3FF0300C R/W SHA_TEXT_4_REG SHA encrypted/decrypted data register 4 0x3FF03010 R/W SHA_TEXT_5_REG SHA encrypted/decrypted data register 5 0x3FF03014 R/W SHA_TEXT_6_REG SHA encrypted/decrypted data register 6 0x3FF03018 R/W SHA_TEXT_7_REG SHA encrypted/decrypted data register 7 0x3FF0301C R/W Espressif Systems 410 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR Name Description Address Access SHA_TEXT_8_REG SHA encrypted/decrypted data register 8 0x3FF03020 R/W SHA_TEXT_9_REG SHA encrypted/decrypted data register 9 0x3FF03024 R/W SHA_TEXT_10_REG SHA encrypted/decrypted data register 10 0x3FF03028 R/W SHA_TEXT_11_REG SHA encrypted/decrypted data register 11 0x3FF0302C R/W SHA_TEXT_12_REG SHA encrypted/decrypted data register 12 0x3FF03030 R/W SHA_TEXT_13_REG SHA encrypted/decrypted data register 13 0x3FF03034 R/W SHA_TEXT_14_REG SHA encrypted/decrypted data register 14 0x3FF03038 R/W SHA_TEXT_15_REG SHA encrypted/decrypted data register 15 0x3FF0303C R/W SHA_TEXT_16_REG SHA encrypted/decrypted data register 16 0x3FF03040 R/W SHA_TEXT_17_REG SHA encrypted/decrypted data register 17 0x3FF03044 R/W SHA_TEXT_18_REG SHA encrypted/decrypted data register 18 0x3FF03048 R/W SHA_TEXT_19_REG SHA encrypted/decrypted data register 19 0x3FF0304C R/W SHA_TEXT_20_REG SHA encrypted/decrypted data register 20 0x3FF03050 R/W SHA_TEXT_21_REG SHA encrypted/decrypted data register 21 0x3FF03054 R/W SHA_TEXT_22_REG SHA encrypted/decrypted data register 22 0x3FF03058 R/W SHA_TEXT_23_REG SHA encrypted/decrypted data register 23 0x3FF0305C R/W SHA_TEXT_24_REG SHA encrypted/decrypted data register 24 0x3FF03060 R/W SHA_TEXT_25_REG SHA encrypted/decrypted data register 25 0x3FF03064 R/W SHA_TEXT_26_REG SHA encrypted/decrypted data register 26 0x3FF03068 R/W SHA_TEXT_27_REG SHA encrypted/decrypted data register 27 0x3FF0306C R/W SHA_TEXT_28_REG SHA encrypted/decrypted data register 28 0x3FF03070 R/W SHA_TEXT_29_REG SHA encrypted/decrypted data register 29 0x3FF03074 R/W SHA_TEXT_30_REG SHA encrypted/decrypted data register 30 0x3FF03078 R/W SHA_TEXT_31_REG SHA encrypted/decrypted data register 31 0x3FF0307C R/W SHA_SHA1_START_REG Control register to initiate SHA1 operation 0x3FF03080 WO SHA_SHA1_CONTINUE_REG Control register to continue SHA1 operation 0x3FF03084 WO SHA_SHA1_LOAD_REG Control register to calculate the final SHA1 hash 0x3FF03088 WO SHA_SHA1_BUSY_REG Status register for SHA1 operation 0x3FF0308C RO SHA_SHA256_START_REG Control register to initiate SHA256 operation 0x3FF03090 WO SHA_SHA256_CONTINUE_REG Control register to continue SHA256 operation 0x3FF03094 WO 0x3FF03098 WO Control/status registers SHA_SHA256_LOAD_REG Control register to calculate the final SHA256 hash SHA_SHA256_BUSY_REG Status register for SHA256 operation 0x3FF0309C RO SHA_SHA384_START_REG Control register to initiate SHA384 operation 0x3FF030A0 WO SHA_SHA384_CONTINUE_REG Control register to continue SHA384 operation 0x3FF030A4 WO 0x3FF030A8 WO SHA_SHA384_LOAD_REG Control register to calculate the final SHA384 hash SHA_SHA384_BUSY_REG Status register for SHA384 operation 0x3FF030AC RO SHA_SHA512_START_REG Control register to initiate SHA512 operation 0x3FF030B0 WO SHA_SHA512_CONTINUE_REG Control register to continue SHA512 operation 0x3FF030B4 WO 0x3FF030B8 WO 0x3FF030BC RO SHA_SHA512_LOAD_REG SHA_SHA512_BUSY_REG Espressif Systems Control register to calculate the final SHA512 hash Status register for SHA512 operation 411 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR 19.5 Registers Register 19.1: SHA_TEXT_n_REG (n: 0-31) (0x0+4*n) 31 0 0x000000000 Reset SHA_TEXT_n_REG (n: 0-31) SHA Message block and hash result register. (R/W) (re SH se r A_ ve SH d) A1 _S TA R T Register 19.2: SHA_SHA1_START_REG (0x080) 31 1 0x00000000 0 0 Reset SHA_SHA1_START Write 1 to start an SHA-1 operation on the first message block. (WO) SH (re s er A_ SH ve d ) A1 _C O NT IN UE Register 19.3: SHA_SHA1_CONTINUE_REG (0x084) 31 1 0x00000000 0 0 Reset SHA_SHA1_CONTINUE Write 1 to continue the SHA-1 operation with subsequent blocks. (WO) (re se rv e d) SH A_ SH A1 _L O AD Register 19.4: SHA_SHA1_LOAD_REG (0x088) 31 1 0x00000000 0 0 Reset SHA_SHA1_LOAD Write 1 to finish the SHA-1 operation to calculate the final message hash. (WO) Espressif Systems 412 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR (re se r SH A_ ve d) SH A1 _B US Y Register 19.5: SHA_SHA1_BUSY_REG (0x08C) 31 1 0x00000000 0 0 Reset SHA_SHA1_BUSY SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) (re SH se A_ rv e SH d) A2 56 _S TA R T Register 19.6: SHA_SHA256_START_REG (0x090) 31 1 0x00000000 0 0 Reset SHA_SHA256_START Write 1 to start an SHA-256 operation on the first message block. (WO) (re SH se r A_ ve SH d) A2 56 _C O NT IN U E Register 19.7: SHA_SHA256_CONTINUE_REG (0x094) 31 1 0x00000000 0 0 Reset SHA_SHA256_CONTINUE Write 1 to continue the SHA-256 operation with subsequent blocks. (WO) (re SH A_ se rv e SH d) A2 56 _L O AD Register 19.8: SHA_SHA256_LOAD_REG (0x098) 31 1 0x00000000 0 0 Reset SHA_SHA256_LOAD Write 1 to finish the SHA-256 operation to calculate the final message hash. (WO) Espressif Systems 413 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR (re s er SH A_ ve d) SH A2 56 _B US Y Register 19.9: SHA_SHA256_BUSY_REG (0x09C) 31 1 0x00000000 0 0 Reset SHA_SHA256_BUSY SHA-256 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) (re SH se A_ rv e SH d) A3 84 _S TA R T Register 19.10: SHA_SHA384_START_REG (0x0A0) 31 1 0x00000000 0 0 Reset SHA_SHA384_START Write 1 to start an SHA-384 operation on the first message block. (WO) (re SH se A_ SH rv ed ) A3 84 _C O NT IN U E Register 19.11: SHA_SHA384_CONTINUE_REG (0x0A4) 31 1 0x00000000 0 0 Reset SHA_SHA384_CONTINUE Write 1 to continue the SHA-384 operation with subsequent blocks. (WO) (re se rv ed ) SH A_ SH A3 84 _L O AD Register 19.12: SHA_SHA384_LOAD_REG (0x0A8) 31 1 0x00000000 0 0 Reset SHA_SHA384_LOAD Write 1 to finish the SHA-384 operation to calculate the final message hash. (WO) Espressif Systems 414 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR (re s er SH A_ ve d) SH A3 84 _B US Y Register 19.13: SHA_SHA384_BUSY_REG (0x0AC) 31 1 0x00000000 0 0 Reset SHA_SHA384_BUSY SHA-384 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) (re SH se A_ rv e SH d) A5 12 _S TA R T Register 19.14: SHA_SHA512_START_REG (0x0B0) 31 1 0x00000000 0 0 Reset SHA_SHA512_START Write 1 to start an SHA-512 operation on the first message block. (WO) (re SH se A_ SH rv ed ) A5 12 _C O NT IN U E Register 19.15: SHA_SHA512_CONTINUE_REG (0x0B4) 31 1 0x00000000 0 0 Reset SHA_SHA512_CONTINUE Write 1 to continue the SHA-512 operation with subsequent blocks. (WO) (re se rv ed ) SH A_ SH A5 12 _L O AD Register 19.16: SHA_SHA512_LOAD_REG (0x0B8) 31 1 0x00000000 0 0 Reset SHA_SHA512_LOAD Write 1 to finish the SHA-512 operation to calculate the final message hash. (WO) Espressif Systems 415 ESP32 Technical Reference Manual V2.0 19. SHA ACCELERATOR (re s er SH A_ ve d) SH A5 12 _B US Y Register 19.17: SHA_SHA512_BUSY_REG (0x0BC) 31 1 0x00000000 0 0 Reset SHA_SHA512_BUSY SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) Espressif Systems 416 ESP32 Technical Reference Manual V2.0 20. RSA ACCELERATOR 20. RSA Accelerator 20.1 Introduction The RSA Accelerator provides hardware support for multiple precision arithmetic operations used in RSA asymmetric cipher algorithms. Sometimes, multiple precision arithmetic is also called ”bignum arithmetic”, ”bigint arithmetic” or ”arbitrary precision arithmetic”. 20.2 Features • Support for large-number modular exponentiation • Support for large-number modular multiplication • Support for large-number multiplication • Support for various lengths of operands 20.3 Functional Description 20.3.1 Initialization The RSA Accelerator is activated by enabling the corresponding peripheral clock, and by clearing the DPORT_RSA_PD bit in the DPORT_RSA_PD_CTRL_REG register. This releases the RSA Accelerator from reset. When the RSA Accelerator is released from reset, the register RSA_CLEAN_REG reads 0 and an initialization process begins. Hardware initializes the four memory blocks by setting them to 0. After initialization is complete, RSA_CLEAN_REG reads 1. For this reason, software should query RSA_CLEAN_REG after being released from reset, and before writing to any RSA Accelerator memory blocks or registers for the first time. 20.3.2 Large Number Modular Exponentiation Large-number modular exponentiation performs Z = X Y mod M . The operation is based on Montgomery multiplication. Aside from the arguments X, Y , and M , two additional ones are needed — r and M ′ . These arguments are calculated in advance by software. The RSA Accelerator supports operand lengths of N ∈ {512, 1024, 1536, 2048, 2560, 3072, 3584, 4096} bits. The bit length of arguments Z, X, Y , M , and r can be any one from the N set, but all numbers in a calculation must be of the same length. The bit length of M ′ is always 32. To represent the numbers used as operands, define a base-b positional notation, as follows: b = 232 Espressif Systems 417 ESP32 Technical Reference Manual V2.0 20. RSA ACCELERATOR In this notation, each number is represented by a sequence of base-b digits, where each base-b digit is a 32-bit word. Representing an N -bit number requires n base-b digits (all of the possible N lengths are multiples of 32). n= N 32 Z = (Zn−1 Zn−2 · · · Z0 )b X = (Xn−1 Xn−2 · · · X0 )b Y = (Yn−1 Yn−2 · · · Y0 )b M = (Mn−1 Mn−2 · · · M0 )b r = (rn−1 rn−2 · · · r0 )b Each of the n values in Zn−1 ~ Z0 , Xn−1 ~ X0 , Yn−1 ~ Y0 , Mn−1 ~ M0 , rn−1 ~ r0 represents one base-b digit (a 32-bit word). Zn−1 , Xn−1 , Yn−1 , Mn−1 and rn−1 are the most significant bits of Z, X, Y , M , while Z0 , X0 , Y0 , M0 and r0 are the least significant bits. If we define R = bn then, we can calculate the additional arguments, as follows: r = R2 mod M M ′′ × M + 1 = R × R−1 (1) (2) M ′ = M ′′ mod b (Equation 2 is written in a form suitable for calculations using the extended binary GCD algorithm.) Software can implement large-number modular exponentiations in the following order: N 1. Write ( 512 − 1) to RSA_MODEXP_MODE_REG. 2. Write Xi , Yi , Mi and ri (i ∈ [0, n) ∩ N) to memory blocks RSA_X_MEM, RSA_Y_MEM, RSA_M_MEM and RSA_Z_MEM. The capacity of each memory block is 128 words. Each word of each memory block can store one base-b digit. The memory blocks use the little endian format for storage, i.e. the least significant digit of each number is in the lowest address. Users need to write data to each memory block only according to the length of the number; data beyond this length are ignored. 3. Write M ′ to RSA_M_PRIME_REG. 4. Write 1 to RSA_MODEXP_START_REG. 5. Wait for the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR interrupt is generated. 6. Read the result Zi (i ∈ [0, n) ∩ N) from RSA_Z_MEM. 7. Write 1 to RSA_INTERRUPT_REG to clear the interrupt. After the operation, the RSA_MODEXP_MODE_REG register, memory blocks RSA_Y_MEM and RSA_M_MEM, as well as the RSA_M_PRIME_REG will not have changed. However, Xi in RSA_X_MEM and ri in RSA_Z_MEM Espressif Systems 418 ESP32 Technical Reference Manual V2.0 20. RSA ACCELERATOR will have been overwritten. In order to perform another operation, refresh the registers and memory blocks, as required. 20.3.3 Large Number Modular Multiplication Large-number modular multiplication performs Z = X × Y mod M . This operation is based on Montgomery multiplication. The same values r and M ′ are derived by software using the formulas 1 and 2 shown above. The RSA Accelerator supports large-number modular multiplication with eight different operand lengths, which are the same as in the large-number modular exponentiation. The operation is performed by a combination of software and hardware. The software performs two hardware operations in sequence. The software process is as follows: N 1. Write ( 512 − 1) to RSA_MULT_MODE_REG. 2. Write Xi , Mi and ri (i ∈ [0, n) ∩ N) to registers RSA_X_MEM, RSA_M_MEM and RSA_Z_MEM. Write data to each memory block only according to the length of the number. Data beyond this length are ignored. 3. Write M ′ to RSA_M_PRIME_REG. 4. Write 1 to RSA_MULT_START_REG. 5. Wait for the first round of the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR interrupt is generated. 6. Write 1 to RSA_INTERRUPT_REG to clear the interrupt. 7. Write Yi (i ∈ [0, n) ∩ N) to RSA_X_MEM. Users need to write to the memory block only according to the length of the number. Data beyond this length are ignored. 8. Write 1 to RSA_MULT_START_REG. 9. Wait for the second round of the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR interrupt is generated. 10. Read the result Zi (i ∈ [0, n) ∩ N) from RSA_Z_MEM. 11. Write 1 to RSA_INTERRUPT_REG to clear the interrupt. After the operation, the RSA_MULT_MODE_REG register, and memory blocks RSA_M_MEM and RSA_M_PRIME_REG remain unchanged. Users do not need to refresh these registers or memory blocks if the values remain the same. 20.3.4 Large Number Multiplication Large-number multiplication performs Z = X × Y . The length of Z is twice that of X and Y . Therefore, the RSA Accelerator supports large-number multiplication with only four operand lengths of N ∈ {512, 1024, 1536, 2048} bits. The length N̂ of the result Z is 2 × N bits. Operands X and Y need to be extended to form arguments X̂ and Ŷ which have the same length (N̂ bits) as Espressif Systems 419 ESP32 Technical Reference Manual V2.0 20. RSA ACCELERATOR the result Z. X is left-extended and Y is right-extended, and defined as follows: N 32 N̂ = 2 × N n= N̂ = 2n 32 X̂ = (X̂n̂−1 X̂n̂−2 · · · X̂0 )b = (00 · · · 0} X)b = (00 · · · 0} Xn−1 Xn−2 · · · X0 )b | {z | {z n̂ = n n Ŷ = (Ŷn̂−1 Ŷn̂−2 · · · Ŷ0 )b = (Y 00 · · · 0})b = (Yn−1 Yn−2 · · · Y0 00 · · · 0})b | {z | {z n n Software performs the operation in the following order: N̂ 1. Write ( 512 − 1 + 8) to RSA_MULT_MODE_REG. 2. Write X̂i and Ŷi (i ∈ [0, n̂) ∩ N) to RSA_X_MEM and RSA_Z_MEM, respectively. Write the valid data into each number’s memory block, according to their lengths. Values beyond this length are ignored. Half of the base-b positional notations written to the memory are zero (using the derivations shown above). These zero values are indispensable. 3. Write 1 to RSA_MULT_START_REG. 4. Wait for the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR interrupt is generated. 5. Read the result Zi (i ∈ [0, n̂) ∩ N) from RSA_Z_MEM. 6. Write 1 to RSA_INTERRUPT_REG to clear the interrupt. After the operation, only the RSA_MULT_MODE_REG register remains unmodified. 20.4 Register Summary Name Description Address Access Register to store M’ 0x3FF02800 R/W RSA_MODEXP_MODE_REG Modular exponentiation mode 0x3FF02804 R/W RSA_MODEXP_START_REG Start bit 0x3FF02808 WO RSA_MULT_MODE_REG Modular multiplication mode 0x3FF0280C R/W RSA_MULT_START_REG Start bit 0x3FF02810 WO RSA_INTERRUPT_REG RSA interrupt register 0x3FF02814 R/W RSA_CLEAN_REG RSA clean register 0x3FF02818 RO Configuration registers RSA_M_PRIME_REG Modular exponentiation registers Modular multiplication registers Misc registers Espressif Systems 420 ESP32 Technical Reference Manual V2.0 20. RSA ACCELERATOR 20.5 Registers Register 20.1: RSA_M_PRIME_REG (0x800) 31 0 0x000000000 Reset RSA_M_PRIME_REG This register contains M’. (R/W) RS (re se rv A_ M O ed ) DE XP _M O DE Register 20.2: RSA_MODEXP_MODE_REG (0x804) 31 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 Reset RSA_MODEXP_MODE This register contains the mode of modular exponentiation. (R/W) RS (re s A_ er M ve d O ) DE XP _S TA R T Register 20.3: RSA_MODEXP_START_REG (0x808) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset RSA_MODEXP_START Write 1 to start modular exponentiation. (WO) (re RS A_ M se rv ed ) UL T_ M O DE Register 20.4: RSA_MULT_MODE_REG (0x80C) 31 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 Reset RSA_MULT_MODE This register contains the mode of modular multiplication and multiplication. (R/W) Espressif Systems 421 ESP32 Technical Reference Manual V2.0 20. RSA ACCELERATOR RS A_ (re se r M ve d) UL T_ ST AR T Register 20.5: RSA_MULT_START_REG (0x810) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset RSA_MULT_START Write 1 to start modular multiplication or multiplication. (WO) (re RS se A_ rv e IN T d) ER RU PT Register 20.6: RSA_INTERRUPT_REG (0x814) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset RSA_INTERRUPT RSA interrupt status register. Will read 1 once an operation has completed. (R/W) RS (re s A_ er ve d ) CL EA N Register 20.7: RSA_CLEAN_REG (0x818) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset RSA_CLEAN This bit will read 1 once the memory initialization is completed. (RO) Espressif Systems 422 ESP32 Technical Reference Manual V2.0 21. RANDOM NUMBER GENERATOR 21. Random Number Generator 21.1 Introduction The ESP32 contains a true random number generator, whose values can be used as a basis for cryptographical operations, among other things. 21.2 Feature It can generate true random numbers. 21.3 Functional Description When used correctly, every 32-bit value the system reads from the RNG_DATA_REG register of the random number generator is a true random number. These true random numbers are generated based on the noise in the Wi-Fi/BT RF system. When Wi-Fi and BT are disabled, the random number generator will give out pseudo-random numbers. When Wi-Fi or BT is enabled, the random number generator is fed two bits of entropy every APB clock cycle (normally 80 MHz). Thus, for the maximum amount of entropy, it is advisable to read the random register at a maximum rate of 5 MHz. A data sample of 2 GB, read from the random number generator with Wi-Fi enabled and the random register read at 5 MHz, has been tested using the Dieharder Random Number Testsuite (version 3.31.1). The sample passed all tests. 21.4 Register Summary Name Description Address Access RNG_DATA_REG Random number data 0x3FF75144 RO 21.5 Register Register 21.1: RNG_DATA_REG (0x144) 31 0 0x000000000 Reset RNG_DATA_REG Random number source. (RO) Espressif Systems 423 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU 22. PID/MPU/MMU 22.1 Introduction Every peripheral and memory section in the ESP32 is accessed through either an MMU (Memory Management Unit) or an MPU (Memory Protection Unit). An MPU can allow or disallow the access of an application to a memory range or peripheral, depending on what kind of permission the OS has given to that particular application. An MMU can perform the same operation, as well as a virtual-to-physical memory address translation. This can be used to map an internal or external memory range to a certain virtual memory area. These mappings can be application-specific. Therefore, each application can be adjusted and have the memory configuration that is necessary for it to run properly. To differentiate between the OS and applications, there are eight Process Identifiers (or PIDs) that each application, or OS, can run. Furthermore, each application, or OS, is equipped with their own sets of mappings and rights. 22.2 Features • Eight processes in each of the PRO_CPU and APP_CPU • MPU/MMU management of on-chip memories, off-chip memories, and peripherals, based on process ID • On-chip memory management by MPU/MMU • Off-chip memory management by MMU • Peripheral management by MPU 22.3 Functional Description 22.3.1 PID Controller In the ESP32, a PID controller acts as an indicator that signals the MMU/MPU the owner PID of the code that is currently running. The intention is that the OS updates the PID in the PID controller every time it switches context to another application. The PID controller can detect interrupts and automatically switch PIDs to that of the OS, if so configured. There are two peripheral PID controllers in the system, one for each of the two CPUs in the ESP32. Having a PID controller per CPU allows running different processes on different CPUs, if so desired. Espressif Systems 424 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU 22.3.2 MPU/MMU The MPU and MMU manage on-chip memories, off-chip memories, and peripherals. To do this they are based on the process of accessing the peripheral or memory region. More specifically, when a code tries to access a MMU/MPU-protected memory region or peripheral, the MMU or MPU will receive the PID from the PID generator that is associated with the CPU on which the process is running. For on-chip memory and peripherals, the decisions the MMU and MPU make are only based on this PID, whereas the specific CPU the code is running on is not taken into account. Subsequently, the MMU/MPU configuration for the internal memory and peripherals allows entries only for the eight different PIDs. In contrast, the MMU moderating access to the external memory takes not only the PID into account, but also the CPU the request is coming from. This means that MMUs have configuration options for every PID when running on the APP_CPU, as well as every PID when running on the PRO_CPU. While, in practice, accesses from both CPUs will be configured to have the same result for a specific process, doing so is not a hardware requirement. The decision an MPU can make, based on this information, is to allow or deny a process to access the memory region or peripheral. An MMU has the same function, but additionally it redirects the virtual memory access, which the process acquired, into a physical memory access that can possibly reach out an entirely different physical memory region. This way, MMU-governed memory can be remapped on a process-by-process basis. 22.3.2.1 Embedded Memory The on-chip memory is governed by fixed-function MPUs, configurable MPUs, and MMUs: Table 73: MPU and MMU Structure for Internal Memory Name Size ROM0 ROM1 SRAM0 SRAM1 (aliases) SRAM2 RTC FAST (aliases) RTC SLOW Address range Governed by From To 384 KB 0x4000_0000 0x4005_FFFF Static MPU 64 KB 0x3FF9_0000 0x3FF9_FFFF Static MPU 64 KB 0x4007_0000 0x4007_FFFF Static MPU 128 KB 0x4008_0000 0x4009_FFFF SRAM0 MMU 128 KB 0x3FFE_0000 0x3FFF_FFFF Static MPU 128 KB 0x400A_0000 0x400B_FFFF Static MPU 32 KB 0x4000_0000 0x4000_7FFF Static MPU 72 KB 0x3FFA_E000 0x3FFB_FFFF Static MPU 128 KB 0x3FFC_0000 0x3FFD_FFFF SRAM2 MMU 8 KB 0x3FF8_0000 0x3FF8_1FFF RTC FAST MPU 8 KB 0x400C_0000 0x400C_1FFF RTC FAST MPU 8 KB 0x5000_0000 0x5000_1FFF RTC SLOW MPU Static MPUs ROM0, ROM1, the lower 64 KB of SRAM0, SRAM1 and the lower 72 KB of SRAM2 are governed by a static MPU. The behaviour of these MPUs are hardwired and cannot be configured by software. They moderate access to the memory region solely through the PID of the current process. When the PID of the process is 0 or 1, the memory can be read (and written when it is RAM) using the addresses specified in Table 73. When it is 2 ~ 7, the memory cannot be accessed. Espressif Systems 425 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU RTC FAST & RTC SLOW MPU The 8 KB RTC FAST Memory as well as the 8 KB of RTC SLOW Memory are governed by two configurable MPUs. The MPUs can be configured to allow or deny access to each individual PID, using the RTC_CNTL_RTC_PID_CONFIG_REG and DPORT_AHBLITE_MPU_TABLE_RTC_REG registers. Setting a bit in these registers will allow the corresponding PID to read or write from the memory; clearing the bit disallows access. Access for PID 0 and 1 to RTC SLOW memory cannot be configured and is always enabled. Table 74 and 75 define the bit-to-PID mappings of the registers. Table 74: MPU for RTC FAST Memory Boundary address Size Authority PID Low High 8 KB 0x3FF8_0000 0x3FF8_1FFF 01234567 8 KB 0x400C_0000 0x400C_1FFF 01234567 RTC_CNTL_RTC_PID_CONFIG bit Table 75: MPU for RTC SLOW Memory Boundary address Size 8 KB Low High 0x5000_0000 0x5000_1FFF Authority PID PID = 0/1 DPORT_AHBLITE_MPU_TABLE_RTC_REG bit Read/Write 234567 012345 Register RTC_CNTL_RTC_PID_CONFIG_REG is part of the RTC peripheral and can only be modified by processes with a PID of 0; register DPORT_AHBLITE_MPU_TABLE_RTC_REG is a Dport register and can be changed by processes with a PID of 0 or 1. SRAM0 and SRAM2 upper 128 KB MMUs Both the upper 128 KB of SRAM0 and the upper 128 KB of SRAM2 are governed by an MMU. Not only can these MMUs allow or deny access to the memory they govern (just like the MPUs do), but they are also capable of translating the address a CPU reads from or writes to (which is a virtual address) to a possibly different address in memory (the physical address). In order to accomplish this, the internal RAM MMUs divide the memory range they govern into 16 pages. The page size is configurable as 8 KB, 4 KB and 2 KB. When the page size is 8 KB, the 16 pages span the entire 128 KB memory region; when the page size is 4 KB or 2 KB, a non-MMU-covered region of 64 or 96 KB, respectively, will exist at the end of the memory space. Similar to the virtual and physical addresses, it is also possible to imagine the pages as having a virtual and physical component. The MMU can convert an address within a virtual page to an address within a physical page. For PID 0 and 1, this mapping is 1-to-1, meaning that a read from or write to a certain virtual page will always be converted to a read from or write to the exact same physical page. This allows an operating system, running under PID 0 and/or 1, to always have access to the entire physical memory range. For PID 2 to 7, however, every virtual page can be reconfigured, on a per-PID basis, to map to a different physical page. This way, reads and writes to an offset within a virtual page get translated into reads and writes to the Espressif Systems 426 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU same offset within a different physical page. This is illustrated in Figure 107: the CPU (running a process with a PID between 2 to 7) tries to access memory address 0x3FFC_2345. This address is within the virtual Page 1 memory region, at offset 0x0345. The MMU is instructed that for this particular PID, it should translate an access to virtual page 1 into physical Page 2. This causes the memory access to be redirected to the same offset as the virtual memory access, yet in Page 2, which results in the effective access of physical memory address 0x3FFC_4345. The page size in this example is 8 KB. VIRTUAL CPU MMU PHYSICAL 3FFC_0000 3FFC_0000 PAGE 0 PAGE 0 3FFC_2000 3FFC_2345 3FFC_2000 PAGE 1 PAGE 1 3FFC_4000 3FFC_4345 PAGE 2 3FFC_4000 PAGE 2 3FFC_6000 3FFC_6000 3FFD_E000 3FFD_E000 PAGE 15 PAGE 15 3FFE_0000 3FFE_0000 Figure 107: MMU Access Example Table 76: Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2 DPORT_IMMU_PAGE_MODE DPORT_DMMU_PAGE_MODE Page size 0 0 8 KB 1 1 4 KB 2 2 2 KB Non-MMU Governed Memory For the MMU-managed region of SRAM0 and SRAM2, the page size is configurable as 8 KB, 4 KB and 2 KB. The configuration is done by setting the DPORT_IMMU_PAGE_MODE (for SRAM0) and DPORT_DMMU_PAGE_MODE (for SRAM2) bits in registers DPORT_IMMU_PAGE_MODE_REG and DPORT_DMMU_PAGE_MODE_REG, as detailed in Table 76. Because the number of pages for either region is fixed at 16, the total amount of memory covered by these pages is 128 KB when 8 KB pages are selected, 64 KB when 4 KB pages are selected, and 32 KB when 2 KB pages are selected. This implies that for 8 KB pages, the entire MMU-managed range is used, but for the other page sizes there will be a part of the 128 KB memory that will not be governed by the MMU settings. Concretely, for a page size of 4 KB, these regions are 0x4009_0000 to 0x4009_FFFF and 0x3FFD_0000 to 0x3FFD_FFFF; for a page size of 2 KB, the regions are 0x4008_8000 to 0x4009_FFFF and 0x3FFC_8000 to 0x3FFD_FFFF. These ranges are readable and writable by processes with a PID of 0 or 1; processes with other PIDs cannot access this memory. The layout of the pages in memory space is linear, namely, an SRAM0 MMU page n covers address space 0x40080000 + (pagesize ∗ n) to 0x40080000 + (pagesize ∗ (n + 1) − 1); similarily, an SRAM2 MMU page n covers 0x3F F C0000 + (pagesize ∗ n) to 0x3F F C0000 + (pagesize ∗ (n + 1) − 1). Tables 77 and 78 show the resulting addresses in full. Espressif Systems 427 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Table 77: Page Boundaries for SRAM0 MMU Page 8 KB Pages 4 KB Pages 2 KB Pages Bottom Top Bottom Top Bottom Top 0 40080000 40081FFF 40080000 40080FFF 40080000 400807FF 1 40082000 40083FFF 40081000 40081FFF 40080800 40080FFF 2 40084000 40085FFF 40082000 40082FFF 40081000 400817FF 3 40086000 40087FFF 40083000 40083FFF 40081800 40081FFF 4 40088000 40089FFF 40084000 40084FFF 40082000 400827FF 5 4008A000 4008BFFF 40085000 40085FFF 40082800 40082FFF 6 4008C000 4008DFFF 40086000 40086FFF 40083000 400837FF 7 4008E000 4008FFFF 40087000 40087FFF 40083800 40083FFF 8 40090000 40091FFF 40088000 40088FFF 40084000 400847FF 9 40092000 40093FFF 40089000 40089FFF 40084800 40084FFF 10 40094000 40095FFF 4008A000 4008AFFF 40085000 400857FF 11 40096000 40097FFF 4008B000 4008BFFF 40085800 40085FFF 12 40098000 40099FFF 4008C000 4008CFFF 40086000 400867FF 13 4009A000 4009BFFF 4008D000 4008DFFF 40086800 40086FFF 14 4009C000 4009DFFF 4008E000 4008EFFF 40087000 400877FF 15 4009E000 4009FFFF 4008F000 4008FFFF 40087800 40087FFF Rest - - 40090000 4009FFFF 4008800 4009FFFF Table 78: Page Boundaries for SRAM2 MMU Page 8 KB Pages 4 KB Pages 2 KB Pages Bottom Top Bottom Top Bottom Top 0 3FFC0000 3FFC1FFF 3FFC0000 3FFC0FFF 3FFC0000 3FFC07FF 1 3FFC2000 3FFC3FFF 3FFC1000 3FFC1FFF 3FFC0800 3FFC0FFF 2 3FFC4000 3FFC5FFF 3FFC2000 3FFC2FFF 3FFC1000 3FFC17FF 3 3FFC6000 3FFC7FFF 3FFC3000 3FFC3FFF 3FFC1800 3FFC1FFF 4 3FFC8000 3FFC9FFF 3FFC4000 3FFC4FFF 3FFC2000 3FFC27FF 5 3FFCA000 3FFCBFFF 3FFC5000 3FFC5FFF 3FFC2800 3FFC2FFF 6 3FFCC000 3FFCDFFF 3FFC6000 3FFC6FFF 3FFC3000 3FFC37FF 7 3FFCE000 3FFCFFFF 3FFC7000 3FFC7FFF 3FFC3800 3FFC3FFF 8 3FFD0000 3FFD1FFF 3FFC8000 3FFC8FFF 3FFC4000 3FFC47FF 9 3FFD2000 3FFD3FFF 3FFC9000 3FFC9FFF 3FFC4800 3FFC4FFF 10 3FFD4000 3FFD5FFF 3FFCA000 3FFCAFFF 3FFC5000 3FFC57FF 11 3FFD6000 3FFD7FFF 3FFCB000 3FFCBFFF 3FFC5800 3FFC5FFF 12 3FFD8000 3FFD9FFF 3FFCC000 3FFCCFFF 3FFC6000 3FFC67FF 13 3FFDA000 3FFDBFFF 3FFCD000 3FFCDFFF 3FFC6800 3FFC6FFF 14 3FFDC000 3FFDDFFF 3FFCE000 3FFCEFFF 3FFC7000 3FFC77FF 15 3FFDE000 3FFDFFFF 3FFCF000 3FFCFFFF 3FFC7800 3FFC7FFF Rest - - 3FFD0000 3FFDFFFF 3FFC8000 3FFDFFFF Espressif Systems 428 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU MMU Mapping For each of the SRAM0 and SRAM2 MMUs, access rights and virtual to physical page mapping are done by a set of 16 registers. In contrast to most of the other MMUs, each register controls a physical page, not a virtual one. These registers control which of the PIDs have access to the physical memory, as well as which virtual page maps to this physical page. The bits in the register are described in Table 79. Keep in mind that these registers only govern accesses from processes with PID 2 to 7; PID 0 and 1 always have full read and write access to all pages and no virtual-to-physical mapping is done. In other words, if a process with a PID of 0 or 1 accesses virtual page x, the access will always go to physical page x, regardless of these register settings. These registers, as well as the page size selection registers DPORT_IMMU_PAGE_MODE_REG and DPORT_DMMU_PAGE_MODE_REG, are only writable from a process with PID 0 or 1. Table 79: DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG [6:4] Access rights for PID 2 ~ 7 [3:0] Address authority 0 None of PIDs 2 ~ 7 have access. 0x00 Virtual page 0 accesses this physical page. 1 All of PIDs 2 ~ 7 have access. 0x01 Virtual page 1 accesses this physical page. 2 Only PID 2 has access. 0x02 Virtual page 2 accesses this physical page. 3 Only PID 3 has access. 0x03 Virtual page 3 accesses this physical page. 4 Only PID 4 has access. 0x04 Virtual page 4 accesses this physical page. 5 Only PID 5 has access. 0x05 Virtual page 5 accesses this physical page. 6 Only PID 6 has access. 0x06 Virtual page 6 accesses this physical page. 7 Only PID 7 has access. 0x07 Virtual page 7 accesses this physical page. 0x08 Virtual page 8 accesses this physical page. 0x09 Virtual page 9 accesses this physical page. 0x10 Virtual page 10 accesses this physical page. 0x11 Virtual page 11 accesses this physical page. 0x12 Virtual page 12 accesses this physical page. 0x13 Virtual page 13 accesses this physical page. 0x14 Virtual page 14 accesses this physical page. 0x15 Virtual page 15 accesses this physical page. Differences Between SRAM0 and SRAM2 MMU The memory governed by the SRAM0 MMU is accessed through the processors I-bus, while the processor accesses the memory governed by the SRAM2 MMU through the D-bus. Thus, the normal envisioned use is for the code to be stored in the SRAM0 MMU pages and data in the MMU pages of SRAM2. In general, applications running under a PID of 2 to 7 are not expected to modify their own code, because for these PIDs access to the MMU pages of SRAM0 is read-only. These applications must, however, be able to modify their data section, so that they are allowed to read as well as write MMU pages located in SRAM2. As stated before, processes running under PID 0 or 1 always have full read-and-write access to both memory ranges. DMA MPU Applications may want to configure the DMA to send data straight from or to the peripherals they can control. With access to DMA, a malicious process may also be able to copy data from or to a region it cannot normally Espressif Systems 429 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU access. In order to be secure against that scenario, there is a DMA MPU which can be used to disallow DMA transfers from memory regions with sensitive data in them. For each 8 KB region in the SRAM1 and SRAM2 regions, there is a bit in the DPORT_AHB_MPU_TABLE_n_REG registers which tells the MPU to either allow or disallow DMA access to this region. The DMA MPU uses only these bits to decide if a DMA transfer can be started; the PID of the process is not a factor. This means that when the OS wants to restrict its processes in a heterogenous fashion, it will need to re-load these registers with the values applicable to the process to be run on every context switch. The register bits that govern access to the 8 KB regions are detailed in Table 80. When a register bit is set, DMA can read/write the corresponding 8 KB memory range. When the bit is cleared, access to that memory range is denied. Table 80: MPU for DMA Size Boundary address Low Authority High Register Bit Internal SRAM 2 8 KB 0x3FFA_E000 0x3FFA_FFFF DPORT_AHB_MPU_TABLE_0_REG 0 8 KB 0x3FFB_0000 0x3FFB_1FFF DPORT_AHB_MPU_TABLE_0_REG 1 8 KB 0x3FFB_2000 0x3FFB_3FFF DPORT_AHB_MPU_TABLE_0_REG 2 8 KB 0x3FFB_4000 0x3FFB_5FFF DPORT_AHB_MPU_TABLE_0_REG 3 8 KB 0x3FFB_6000 0x3FFB_7FFF DPORT_AHB_MPU_TABLE_0_REG 4 8 KB 0x3FFB_8000 0x3FFB_9FFF DPORT_AHB_MPU_TABLE_0_REG 5 8 KB 0x3FFB_A000 0x3FFB_BFFF DPORT_AHB_MPU_TABLE_0_REG 6 8 KB 0x3FFB_C000 0x3FFB_DFFF DPORT_AHB_MPU_TABLE_0_REG 7 8 KB 0x3FFB_E000 0x3FFB_FFFF DPORT_AHB_MPU_TABLE_0_REG 8 8 KB 0x3FFC_0000 0x3FFC_1FFF DPORT_AHB_MPU_TABLE_0_REG 9 8 KB 0x3FFC_2000 0x3FFC_3FFF DPORT_AHB_MPU_TABLE_0_REG 10 8 KB 0x3FFC_4000 0x3FFC_5FFF DPORT_AHB_MPU_TABLE_0_REG 11 8 KB 0x3FFC_6000 0x3FFC_7FFF DPORT_AHB_MPU_TABLE_0_REG 12 8 KB 0x3FFC_8000 0x3FFC_9FFF DPORT_AHB_MPU_TABLE_0_REG 13 8 KB 0x3FFC_A000 0x3FFC_BFFF DPORT_AHB_MPU_TABLE_0_REG 14 8 KB 0x3FFC_C000 0x3FFC_DFFF DPORT_AHB_MPU_TABLE_0_REG 15 8 KB 0x3FFC_E000 0x3FFC_FFFF DPORT_AHB_MPU_TABLE_0_REG 16 8 KB 0x3FFD_0000 0x3FFD_1FFF DPORT_AHB_MPU_TABLE_0_REG 17 8 KB 0x3FFD_2000 0x3FFD_3FFF DPORT_AHB_MPU_TABLE_0_REG 18 8 KB 0x3FFD_4000 0x3FFD_5FFF DPORT_AHB_MPU_TABLE_0_REG 19 8 KB 0x3FFD_6000 0x3FFD_7FFF DPORT_AHB_MPU_TABLE_0_REG 20 8 KB 0x3FFD_8000 0x3FFD_9FFF DPORT_AHB_MPU_TABLE_0_REG 21 8 KB 0x3FFD_A000 0x3FFD_BFFF DPORT_AHB_MPU_TABLE_0_REG 22 8 KB 0x3FFD_C000 0x3FFD_DFFF DPORT_AHB_MPU_TABLE_0_REG 23 8 KB 0x3FFD_E000 0x3FFD_FFFF DPORT_AHB_MPU_TABLE_0_REG 24 Internal SRAM 1 8 KB 0x3FFE_0000 0x3FFE_1FFF DPORT_AHB_MPU_TABLE_0_REG 25 8 KB 0x3FFE_2000 0x3FFE_3FFF DPORT_AHB_MPU_TABLE_0_REG 26 8 KB 0x3FFE_4000 0x3FFE_5FFF DPORT_AHB_MPU_TABLE_0_REG 27 8 KB 0x3FFE_6000 0x3FFE_7FFF DPORT_AHB_MPU_TABLE_0_REG 28 Espressif Systems 430 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Size Boundary address Authority Low High Register Bit 8 KB 0x3FFE_8000 0x3FFE_9FFF DPORT_AHB_MPU_TABLE_0_REG 29 8 KB 0x3FFE_A000 0x3FFE_BFFF DPORT_AHB_MPU_TABLE_0_REG 30 8 KB 0x3FFE_C000 0x3FFE_DFFF DPORT_AHB_MPU_TABLE_0_REG 31 8 KB 0x3FFE_E000 0x3FFE_FFFF DPORT_AHB_MPU_TABLE_1_REG 0 8 KB 0x3FFF_0000 0x3FFF_1FFF DPORT_AHB_MPU_TABLE_1_REG 1 8 KB 0x3FFF_2000 0x3FFF_3FFF DPORT_AHB_MPU_TABLE_1_REG 2 8 KB 0x3FFF_4000 0x3FFF_5FFF DPORT_AHB_MPU_TABLE_1_REG 3 8 KB 0x3FFF_6000 0x3FFF_7FFF DPORT_AHB_MPU_TABLE_1_REG 4 8 KB 0x3FFF_8000 0x3FFF_9FFF DPORT_AHB_MPU_TABLE_1_REG 5 8 KB 0x3FFF_A000 0x3FFF_BFFF DPORT_AHB_MPU_TABLE_1_REG 6 8 KB 0x3FFF_C000 0x3FFF_DFFF DPORT_AHB_MPU_TABLE_1_REG 7 8 KB 0x3FFF_E000 0x3FFF_FFFF DPORT_AHB_MPU_TABLE_1_REG 8 Registers DPROT_AHB_MPU_TABLE_0_REG�DPROT_AHB_MPU_TABLE_1_REG are located in the DPort address space. Only processes with a PID of 0 or 1 can modify these two registers. 22.3.2.2 External Memory Accesses to the external flash and external SPI RAM are done through a cache and are also handled by an MMU. This Cache MMU can apply different mappings, depending on the PID of the process as well as the CPU the process is running on. The MMU does this in a way that is similar to the internal memory MMU, that is, for every page of virtual memory, it has a register detailing which physical page this virtual page should map to. There are differences between the MMUs governing the internal memory and the Cache MMU, though. First of all, the Cache MMU has a fixed page size (which is 64 KB for external flash and 32 KB for external RAM) and secondly, instead of specifying access rights in the MMU entries, the Cache MMU has explicit mapping tables for each PID and processor core. The MMU mapping configuration registers will be referred to as ’entries’ in the rest of this chapter. These registers are only accessible from processes with a PID of 0 or 1; processes with a PID of 2 to 7 will have to delegate to one of the above-mentioned processes to change their MMU settings. The MMU entries, as stated before, are used for mapping a virtual memory page access to a physical memory page access. The MMU controls five regions of virtual address space, detailed in Table 81. V Addr1 to V Addr4 are used for accessing external flash, whereas V AddrRAM is used for accessing external RAM. Note that V Addr4 is a subset of V Addr0 . Espressif Systems 431 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Table 81: Virtual Address for External Memory Name Size V Addr0 Boundary address Page quantity Low High 4 MB 0x3F40_0000 0x3F7F_FFFF 64 V Addr1 4 MB 0x4000_0000 0x403F_FFFF 64* V Addr2 4 MB 0x4040_0000 0x407F_FFFF 64 V Addr3 4 MB 0x4080_0000 0x40BF_FFFF 64 V Addr4 1 MB 0x3F40_0000 0x3F4F_FFFF 16 V AddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF 128 * The configuration entries for address range 0x4000_0000 ~ 0x403F_FFFF are implemented and documented as if it were a full 4 MB address range, but it is not accessible as such. Instead, the address range 0x4000_0000 ~ 0x400C_1FFF accesses on-chip memory. This means that some of the configuration entries for V Addr1 will not be used. External Flash For flash, the relationships among entry numbers, virtual memory ranges, and PIDs are detailed in Tables 82 and 83, which for every memory region and PID combination specify the first MMU entry governing the mapping. This number refers to the MMU entry governing the very first page; the entire region is described by the amount of pages specified in the ’count’ column. These two tables are essentially the same, with the sole difference being that the APP_CPU entry numbers are 2048 higher than the corresponding PRO_CPU numbers. Note that memory regions V Addr0 and V Addr1 are only accessible using PID 0 and 1, while V Addr4 can only be accessed by PID 2 ~ 7. Table 82: MMU Entry Numbers for PRO_CPU VAddr Count V Addr0 First MMU entry for PID 0/1 2 3 4 5 6 7 64 0 - - - - - - V Addr1 64 64 - - - - - - V Addr2 64 128 256 384 512 640 768 896 V Addr3 64 192 320 448 576 704 832 960 V Addr4 16 - 1056 1072 1088 1104 1120 1136 Table 83: MMU Entry Numbers for APP_CPU First MMU entry for PID VAddr Count 0/1 2 3 4 5 6 7 V Addr0 64 2048 - - - - - - V Addr1 64 2112 - - - - - - V Addr2 64 2176 2304 2432 2560 2688 2816 2944 V Addr3 64 2240 2368 2496 2624 2752 2880 3008 V Addr4 16 - 3104 3120 3136 3152 3168 3184 As these tables show, virtual address V Addr1 can only be used by processes with a PID of 0 or 1. There is a Espressif Systems 432 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU special mode to allow processes with a PID of 2 to 7 to read the External Flash via address V Addr1 . When the DPORT_PRO_SINGLE_IRAM_ENA bit of register DPORT_PRO_CACHE_CTRL_REG is 1, the MMU enters this special mode for PRO_CPU memory accesses. Similarily, when the DPORT_APP_SINGLE_IRAM_ENA bit of register DPORT_APP_CACHE_CTRL_REG is 1, the APP_CPU accesses memory using this special mode. In this mode, the process and virtual address page supported by each configuration entry of MMU are different. For details please see Table 84 and 85. As shown in these tables, in this special mode V Addr2 and V Addr3 cannot be used to access External Flash. Table 84: MMU Entry Numbers for PRO_CPU (Special Mode) VAddr Count V Addr0 First MMU entry for PID 0/1 2 3 4 5 6 7 64 0 - - - - - - V Addr1 64 64 256 384 512 640 768 896 V Addr2 64 - - - - - - - V Addr3 64 - - - - - - - V Addr4 16 - 1056 1072 1088 1104 1120 1136 Table 85: MMU Entry Numbers for APP_CPU (Special Mode) VAddr Count V Addr0 First MMU entry for PID 0/1 2 3 4 5 6 7 64 2048 - - - - - - V Addr1 64 2112 2304 2432 2560 2688 2816 2944 V Addr2 64 - - - - - - - V Addr3 64 - - - - - - - V Addr4 16 - 3104 3120 3136 3152 3168 3184 Every configuration entry of MMU maps a virtual address page of a CPU process to a physical address page. An entry is 32 bits wide. Of these, bits 0~7 indicate the physical page the virtual page is mapped to. Bit 8 should be cleared to indicate that the MMU entry is valid; entries with this bit set will not map any physical address to the virtual address. Bits 10 to 32 are unused and should be written as zero. Because there are eight address bits in an MMU entry, and the page size for external flash is 64 KB, a maximum of 256 * 64 KB = 16 MB of external flash is supported. Examples Example 1. A PRO_CPU process, with a PID of 1, needs to read external flash address 0x07_2375 via virtual address 0x3F70_2375. The MMU is not in the special mode. • According to Table 81, virtual address 0x3F70_2375 resides in the 0x30’th page of V Addr0 . • According to Table 82, the MMU entry for V Addr0 for PID 0/1 for the PRO_CPU starts at 0. • The modified MMU entry is 0 + 0x30 = 0x30. • Address 0x07_2375 resides in the 7’th 64 KB-sized page. • MMU entry 0x30 needs to be set to 7 and marked as valid by setting the 8’th bit to 0. Thus, 0x007 is written to MMU entry 0x30. Espressif Systems 433 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Example 2. An APP_CPU process, with a PID of 4, needs to read external flash address 0x44_048C via virtual address 0x4044_048C. The MMU is not in special mode. • According to Table 81, virtual address 0x4044_048C resides in the 0x4’th page of V Addr2 . • According to Table 83, the MMU entry for V Addr2 for PID 4 for the APP_CPU starts at 2560. • The modified MMU entry is 2560 + 0x4 = 2564. • Address 0x44_048C resides in the 0x44’th 64 KB-sized page. • MMU entry 2564 needs to be set to 0x44 and marked as valid by setting the 8’th bit to 0. Thus, 0x044 is written to MMU entry 2564. External RAM Processes running on PRO_CPU and APP_CPU can read and write External SRAM via the Cache at virtual address range V AddrRAM , which is 0x3F80_0000 ~ 0x3FBF_FFFF. As with the flash MMU, the address space and the physical memory are divided into pages. For the External RAM MMU, the page size is 32 KB and the MMU is able to map 256 physical pages into the virtual address space, allowing for 32 KB * 256 = 8 MB of physical external RAM to be mapped. The mapping of virtual pages into this memory range depends on the mode this MMU is in: Low-High mode, Even-Odd mode, or Normal mode. In all cases, the DPORT_PRO_DRAM_HL bit and DPORT_PRO_DRAM_SPLIT bit in register DPORT_PRO_CACHE_CTRL_REG, the DPORT_APP_DRAM_HL bit and DPORT_APP_DRAM_SPLIT bit in register DPORT_APP_CACHE_CTRL_REG determine the virtual address mode for External SRAM. For details, please see Table 86. If a different mapping for the PRO_CPU and APP_CPU is required, the Normal Mode should be selected, as it is the only mode that can provide this. If it is allowable for the PRO_CPU and the APP_CPU to share the same mapping, using either High-Low or Even-Odd mode can give a speed gain when both CPUs access memory frequently. In case the APP_CPU cache is disabled, which renders the region of 0x4007_8000 to 0x4007_FFFF usable as normal internal RAM, the usability of the various cache modes changes. Normal mode will allow PRO_CPU access to external RAM to keep functioning, but the APP_CPU will be unable to access the external RAM. High-Low mode allows both CPUs to use external RAM, but only for the 2 MB virtual memory addresses from 0x3F80_0000 to 0x3F9F_FFFF. It is not advised to use Even-Odd mode with the APP_CPU cache region disabled. Table 86: Virtual Address Mode for External SRAM Mode DPORT_PRO_DRAM_HL DPORT_PRO_DRAM_SPLIT DPORT_APP_DRAM_HL DPORT_APP_DRAM_SPLIT Low-High 1 0 Even-Odd 0 1 Normal 0 0 In normal mode, the virtual-to-physical page mapping can be different for both CPUs. Page mappings for PRO_CPU are set using the MMU entries for L V AddrRAM , and page mappings for the APP_CPU can be configured using the MMU entries for R V AddrRAM . In this mode, all 128 pages of both L V Addr and R V Addr are fully used, allowing a maximum of 8 MB of memory to be mapped; 4 MB into PRO_CPU address space and a possibly different 4 MB into the APP_CPU address space, as can be seen in Table 87. Espressif Systems 434 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Table 87: Virtual Address for External SRAM ( Normal Mode ) Virtual address Size L V AddrRAM 4 MB Virtual address Size R 4 MB V AddrRAM PRO_CPU address Low High 0x3F80_0000 0x3FBF_FFFF APP_CPU address Low High 0x3F80_0000 0x3FBF_FFFF In Low-High mode, both the PRO_CPU and the APP_CPU use the same mapping entries. In this mode L V AddrRAM is used for the lower 2 MB of the virtual address space, while R V AddrRAM is used for the upper 2 MB. This also means that the upper 64 MMU entries for L V AddrRAM , as well as the lower 64 entries for R V AddrRAM , are unused. Table 88 details these address ranges. Table 88: Virtual Address for External SRAM ( Low-High Mode ) Virtual address Size L V AddrRAM R V AddrRAM PRO_CPU/APP_CPU address Low High 2 MB 0x3F80_0000 0x3F9F_FFFF 2 MB 0x3FA0_0000 0x3FBF_FFFF In Even-Odd memory, the VRAM is split into 32-byte chunks. The even chunks are resolved through the MMU entries for L V AddrRAM , the odd chunks through the entries for R V AddrRAM . Generally, the MMU entries for L V AddrRAM and R V AddrRAM are set to the same values, so that the virtual pages map to a contiguous region of physical memory. Table 89 details this mode. Table 89: Virtual Address for External SRAM ( Even-Odd Mode ) Virtual address Size L Low High 32 Bytes 0x3F80_0000 0x3F80_001F V AddrRAM 32 Bytes 0x3F80_0020 0x3F80_003F V AddrRAM 32 Bytes 0x3F80_0040 0x3F80_005F 32 Bytes 0x3F80_0060 0x3F80_007F V AddrRAM R L PRO_CPU/APP_CPU address R V AddrRAM ··· L V AddrRAM R V AddrRAM 32 Bytes 0x3FBF_FFC0 0x3FBF_FFDF 32 Bytes 0x3FBF_FFE0 0x3FBF_FFFF The bit configuration of the External RAM MMU entries is the same as for the flash memory: the entries are 32-bit registers, with the lower nine bits being used. Bits 0~7 contain the physical page the entry should map its associate virtual page address to, while bit 8 is cleared when the entry is valid and set when it is not. Table 90 details the first MMU entry number for L V AddrRAM and R V AddrRAM for all PIDs. Espressif Systems 435 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Table 90: MMU Entry Numbers for External RAM VAddr Count L V AddrRAM R V AddrRAM First MMU entry for PID 0/1 2 3 4 5 6 7 128 1152 1280 1408 1536 1664 1792 1920 128 3200 3328 3456 3584 3712 3840 3968 Examples Example 1. A PRO_CPU process, with a PID of 7, needs to read or write external RAM address 0x7F_A375 via virtual address 0x3FA7_2375. The MMU is in Low-High mode. • According to Table 81, virtual address 0x3FA7_2375 resides in the 0x4E’th 32-KB-page of V AddrRAM . • According to Table 88, virtual address 0x3FA7_2375 is governed by R V AddrRAM . • According to Table 90, the MMU entry for R V AddrRAM for PID 7 for the PRO_CPU starts at 3968. • The modified MMU entry is 3968 + 0x4E = 4046. • Address 0x7F_A375 resides in the 255’th 32 KB-sized page. • MMU entry 4046 needs to be set to 255 and marked as valid by clearing the 8’th bit. Thus, 0x0FF is written to MMU entry 4046. Example 2. An APP_CPU process, with a PID of 5, needs to read or write external RAM address 0x55_5805 up to 0x55_5823 starting at virtual address 0x3F85_5805. The MMU is in Even-Odd mode. • According to Table 81, virtual address 0x3F85_5805 resides in the 0x0A’th 32-KB-page of V AddrRAM . • According to Table 89, the range to be read/written spans both a 32-byte region in R V AddrRAM and L V AddrRAM . • According to Table 90, the MMU entry for L V AddrRAM for PID 5 starts at 1664. • According to Table 90, the MMU entry for R V AddrRAM for PID 5 starts at 3712. • The modified MMU entries are 1664 + 0x0A = 1674 and 3712 + 0x0A = 3722. • The addresses 0x55_5805 to 0x55_5823 reside in the 0xAA’th 32 KB-sized page. • MMU entries 1674 and 3722 need to be set to 0xAA and marked as valid by setting the 8’th bit to 0. Thus, 0x0AA is written to MMU entries 1674 and 3722. This mapping applies to both the PRO_CPU and the APP_CPU. Example 3. A PRO_CPU process, with a PID of 1, and an APP_CPU process whose PID is also 1, need to read or write external RAM using virtual address 0x3F80_0876. The PRO_CPU needs this region to access physical address 0x10_0876, while the APP_CPU wants to access physical address 0x20_0876 through this virtual address. The MMU is in Normal mode. • According to Table 81, virtual address 0x3F80_0876 resides in the 0’th 32-KB-page of V AddrRAM . • According to Table 90, the MMU entry for PID 1 for the PRO_CPU starts at 1152. • According to Table 90, the MMU entry for PID 1 for the APP_CPU starts at 3200. • The MMU entries that are modified are 1152 + 0 = 1152 for the PRO_CPU and 3200 + 0 = 3200 for the APP_CPU. • Address 0x10_0876 resides in the 0x20’th 32 KB-sized page. • Address 0x20_0876 resides in the 0x40’th 32 KB-sized page. • For the PRO_CPU, MMU entry 1152 needs to be set to 0x20 and marked as valid by clearing the 8’th bit. Thus, 0x020 is written to MMU entry 1152. Espressif Systems 436 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU • For the APP_CPU, MMU entry 3200 needs to be set to 0x40 and marked as valid by clearing the 8’th bit. Thus, 0x040 is written to MMU entry 3200. • Now, the PRO_CPU and the APP_CPU can access different physical memory regions through the same virtual address. 22.3.2.3 Peripheral The Peripheral MPU manages the 41 peripheral modules. This MMU can be configured per peripheral to only allow access from a process with a certain PID. The registers to configure this are detailed in Table 91. Table 91: MPU for Peripheral Peripheral Authority PID = 0/1 PID = 2 ~ 7 DPort Register Access Forbidden AES Accelerator Access Forbidden RSA Accelerator Access Forbidden SHA Accelerator Access Forbidden Secure Boot Access Forbidden Cache MMU Table Access Forbidden PID Controller Access Forbidden UART0 Access DPORT_AHBLITE_MPU_TABLE_UART_REG SPI1 Access DPORT_AHBLITE_MPU_TABLE_SPI1_REG SPI0 Access DPORT_AHBLITE_MPU_TABLE_SPI0_REG GPIO Access DPORT_AHBLITE_MPU_TABLE_GPIO_REG RTC Access DPORT_AHBLITE_MPU_TABLE_RTC_REG IO MUX Access DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_HINF_REG UDMA1 Access DPORT_AHBLITE_MPU_TABLE_UHCI1_REG I2S0 Access DPORT_AHBLITE_MPU_TABLE_I2S0_REG UART1 Access DPORT_AHBLITE_MPU_TABLE_UART1_REG I2C0 Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG UDMA0 Access DPORT_AHBLITE_MPU_TABLE_UHCI0_REG SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG RMT Access DPORT_AHBLITE_MPU_TABLE_RMT_REG PCNT Access DPORT_AHBLITE_MPU_TABLE_PCNT_REG SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_SLC_REG LED PWM Access DPORT_AHBLITE_MPU_TABLE_LEDC_REG Efuse Controller Access DPORT_AHBLITE_MPU_TABLE_EFUSE_REG Flash Encryption Access DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG PWM0 Access DPORT_AHBLITE_MPU_TABLE_PWM0_REG TIMG0 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG TIMG1 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG SPI2 Access DPORT_AHBLITE_MPU_TABLE_SPI2_REG SPI3 Access DPORT_AHBLITE_MPU_TABLE_SPI3_REG SYSCON Access DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG Espressif Systems 437 ESP32 Technical Reference Manual V2.0 22. PID/MPU/MMU Peripheral Authority PID = 0/1 PID = 2 ~ 7 I2C1 Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG SDMMC Access DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG EMAC Access DPORT_AHBLITE_MPU_TABLE_EMAC_REG PWM1 Access DPORT_AHBLITE_MPU_TABLE_PWM1_REG I2S1 Access DPORT_AHBLITE_MPU_TABLE_I2S1_REG UART2 Access DPORT_AHBLITE_MPU_TABLE_UART2_REG PWM2 Access DPORT_AHBLITE_MPU_TABLE_PWM2_REG PWM3 Access DPORT_AHBLITE_MPU_TABLE_PWM3_REG RNG Access DPORT_AHBLITE_MPU_TABLE_PWR_REG Each bit of register DPORT_AHBLITE_MPU_TABLE_X_REG determines whether each process can access the peripherals managed by the register. For details please see Table 92. When a bit of register DPORT_AHBLITE_MPU_TABLE_X_REG is 1, it means that a process with the corresponding PID can access the corresponding peripheral of the register. Otherwise, the process cannot access the corresponding peripheral. Table 92: DPORT_AHBLITE_MPU_TABLE_X_REG PID 234567 DPORT_AHBLITE_MPU_TABLE_X_REG bit 012345 All the DPORT_AHBLITE_MPU_TABLE_X_REG registers are in peripheral DPort Register. Only processes with PID 0/1 can modify these registers. Espressif Systems 438 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 23. On-Chip Sensors and Analog Signal Processing 23.1 Introduction ESP32 has three types of built-in sensors for various applications: a capacitive touch sensor with up to 10 inputs, a Hall effect sensor and a temperature sensor. The processing of analog signals is done by two successive approximation ADCs (SAR ADC). There are five controllers dedicated to operating ADCs. This provides flexibility when it comes to converting analog inputs in both high-performance and low-power modes, with minimum processor overhead. There is an attractive complement to the input of SAR ADC1, which processes small signals – the low noise analog amplifier with an adjustable amplification ratio. ESP32 is also capable of generating analog signals, using two independent DACs and a cosine waveform generator. 23.2 Capacitive Touch Sensor 23.2.1 Introduction A touch-sensor system is built on a substrate which carries electrodes and relevant connections under a protective flat surface; see Figure 108. When a user touches the surface, the capacitance variation is triggered and a binary signal is generated to indicate whether the touch is valid. Figure 108: Touch Sensor 23.2.2 Features • Up to 10 capacitive touch pads / GPIOs • The sensing pads can be arranged in different combinations, so that a larger area or more points can be detected. • The touch pad sensing process is under the control of a hardware-implemented finite-state machine (FSM) which is initiated by software or a dedicated hardware timer. • Information that a pad has been touched can be obtained: Espressif Systems 439 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING – by checking touch-sensor registers directly through software, – from an interrupt triggered by a touch detection, – by waking up the CPU from deep sleep upon touch detection. • Support for low-power operation in the following scenarios: – CPU waiting in deep sleep and saving power until touch detection and subsequent wake up – Touch detection managed by the ULP coprocessor The user program in ULP coprocessor can trigger a scanning process by checking and writing into specific registers, in order to verify whether the touch threshold is reached. 23.2.3 Available GPIOs All 10 available sensing GPIOs (pads) are listed in Table 93. Table 93: ESP32 Capacitive Sensing Touch Pads Touch Sensing Signal Name Pin Name T0 GPIO4 T1 GPIO0 T2 GPIO2 T3 MTDO T4 MTCK T5 MTDI T6 MTMS T7 GPIO27 T8 32K_XN T9 32K_XP 23.2.4 Functional Description The internal structure of the touch sensor is shown in Figure 109. The operating flow is shown in Figure 110. Figure 109: Touch Sensor Structure The capacitance of a touch pad is periodically charged and discharged. The chart ”Pad Voltage” shows the Espressif Systems 440 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING charge/discharge voltage that swings from DREFH (reference voltage high) to DREFL (reference voltage low). During each swing, the touch sensor generates an output pulse, shown in the chart as ”OUT”. The swing slope is different when the pad is touched (high capacitance) and when it is not (low capacitance). By comparing the difference between the output pulse counts during the same time interval, we can conclude whether the touch pad has been touched. TIE_OPT is used to establish the initial voltage level that starts the charge/discharge cycle. Figure 110: Touch Sensor Operating Flow 23.2.5 Touch FSM The Touch FSM performs a measurement sequence described in section 23.2.4. Software can operate the Touch FSM through dedicated registers. The internal structure of a touch FSM is shown in Figure 111. The functions of Touch FSM include: • Receipt of a start signal, either from software or a timer – when SENS_SAR_TOUCH_START_FORCE=1, SENS_SAR_TOUCH_START_EN is used to initiate a single measurement – when SENS_SAR_TOUCH_START_FORCE=0, measurement is triggered periodically with a timer. The Touch FSM can be active in sleep mode. The SENS_SAR_TOUCH_SLEEP_CYCLES register can be used to set the cycles. The sensor is operated by FAST_CLK, which normally runs at 8 MHz. More information on that can be found in chapter Reset and Clock. • Generation of XPD_TOUCH_BIAS / TOUCH_XPD / TOUCH_START with adjustable timing sequence To select enabled pads, TOUCH_XPD / TOUCH_START is masked by the 10-bit register SENS_SAR_TOUCH_PAD_WORKEN. • Counting of pulses on TOUCH0_OUT ~ TOUCH9_OUT The result can be read from SENS_SAR_TOUCH_MEAS_OUTn. All ten touch sensors can work simultaneously. • Generation of a wakeup interrupt The FSM regards the touch pads as “touched”, if the number of counted pulses is below the threshold. The 10-bit registers SENS_TOUCH_PAD_OUTEN1 & SENS_TOUCH_PAD_OUTEN2 define two sets of touch pads, i.e. SET1 & SET2. If at least one of the pads in SET1 is “touched”, the wakeup interrupt will be Espressif Systems 441 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING generated by default. It is also possible to configure the wakeup interrupt to be generated only when pads from both sets are “touched”. Figure 111: Touch FSM Structure 23.3 SAR ADC 23.3.1 Introduction ESP32 integrates two 12-bit SAR ADCs. They are managed by five SAR ADC controllers, and are able to measure signals from one to 18 analog pads. It is also possible to measure internal signals, such as vdd33. Some of the pads can be used to build a programmable gain-amplifier which measures small analog signals. The SAR ADC controllers have specialized uses. Two of them support high-performance multiple-channel scanning. Another two are used for low-power operation during deep sleep, and the last one is dedicated to PWDET / PKDET (power and peak detection). A diagram of the SAR ADCs is shown in Figure 112. Espressif Systems 442 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Figure 112: SAR ADC Depiction 23.3.2 Features • Two SAR ADCs, with simultaneous sampling and conversion • Up to five SAR ADC controllers for different purposes (e.g. high performance, low power or PWDET / PKDET). • Up to 18 analog input pads • One channel for internal voltage vdd33, two for pa_pkdet (available on selected controllers) • Low-noise amplifier for small analog signals (available on one controller) • 12-bit, 11-bit, 10-bit, 9-bit configurable resolution • DMA support (available on one controller) • Multiple channel-scanning modes (available on two controllers) • Operation during deep sleep (available on one controller) • Controlled by a ULP coprocessor (available on two controllers) 23.3.3 Outline of Function The SAR ADC module’s major components, and their interconnections, are shown in Figure 113. Espressif Systems 443 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Figure 113: SAR ADC Outline of Function A summary of all the analog signals that may be sent to the SAR ADC module for processing by either ADC1 or ADC2 is presented in Table 94. Table 94: Inputs of SAR ADC module Signal Name Pad # VDET_2 7 VDET_1 6 32K_XN 5 32K_XP 4 SENSOR_VN 3 SENSOR_CAPN 2 SENSOR_CAPP 1 SENSOR_VP 0 Hall sensor n/a GPIO26 9 GPIO25 8 GPIO27 7 MTMS 6 MTDI 5 MTCK 4 MTDO 3 GPIO2 2 GPIO0 1 GPIO4 0 pa_pkdet1 n/a pa_pkdet2 n/a vdd33 n/a Espressif Systems 444 Processed by SAR ADC1 SAR ADC2 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING There are five ADC controllers in ESP32: RTC ADC1 CTRL, RTC ADC2 CTRL, DIG ADC1 CTRL, DIG ADC2 CTRL and PWDET CTRL. The differences between them are summarized in Table 95. Table 95: ESP32 SAR ADC Controllers RTC ADC1 RTC ADC2 DIG ADC1 DIG ADC2 PWDET DAC Y - - - - Low-Noise Amplifier Y - - - - Support deep sleep Y Y - - - ULP coprocessor Y Y - - - vdd33 - Y - Y - PWDET/PKDET - - - - Y Hall sensor Y - - - - DMA - - Y - - 23.3.4 RTC SAR ADC Controllers The purpose of SAR ADC controllers in the RTC power domain – RTC ADC1 CTRL and RTC ADC2 CTRL – is to provide ADC measurement with minimal power consumption in a low frequency. The outline of a single controller’s function is shown in Figure 114. For each controller, the start of analog-to-digital conversion can be triggered by register SENS_SAR_MEASn_START_SAR. The measurement’s result can be obtained from register SENS_SAR_MEASn_DATA_SAR. Espressif Systems 445 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Figure 114: RTC SAR ADC Outline of Function The controllers are intertwined with the ULP coprocessor, as the ULP coprocessor has a built-in instruction to start an ADC measurement. In many cases, the controllers need to cooperate with the ULP coprocessor, e.g.: • when periodically monitoring a channel during deep sleep, where the ULP coprocessor is the only trigger source during this mode; • when scanning channels continuously in a sequence. Continuous scanning or DMA is not supported by the controllers. However, it is possible with the help of the ULP coprocessor. The SAR ADC1 controller supports the low-noise amplifier, as well as DAC. As such, SAR ADC1 can be used in complex application scenarios. 23.3.5 DIG SAR ADC Controllers Compared to RTC SAR ADC controllers, DIG SAR ADC controllers have optimized performance and throughput. Some of their features are: • High performance; the clock is much faster, therefore, the sample rate is highly increased. • Multiple-channel scanning mode; there is a pattern table that defines the measurement rule for each SAR ADC. The scanning mode can be configured as a single mode, double mode, or alternate mode. • The scanning can be started by software or I2S. • DMA support; an interrupt will be generated when scanning is finished. Note: We do not use the term “start of conversion” in this section, because there is no direct access to starting a single SAR analog-to-digital conversion. We use “start of scan” instead, which implies that we expect to scan a sequence of channels with DIG ADC controllers. Figure 115 shows a diagram of DIG SAR ADC controllers. Espressif Systems 446 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Figure 115: Diagram of DIG SAR ADC Controllers The pattern tables contain the measurement rules mentioned above. Each table has 16 items which store information on channel selection, resolution and attenuation. When scanning starts, the controller reads measurement rules one-by-one from a pattern table. For each controller the scanning sequence includes 16 different rules at most, before repeating itself. The 8-bit item (the pattern table register) is composed of three fields that contain channel, resolution and attenuation information, as shown in Table 96. Table 96: Fields of the Pattern Table Register Pattern Table Register [7:0] ch_sel[3:0] bit_width[1:0] atten[1:0] channel to be scanned resolution attenuation There are three scanning modes: single mode, double mode and alternate mode. • Single mode: channels of either SAR ADC1 or SAR ADC2 will be scanned. • Double mode: channels of SAR ADC1 and SAR ADC2 will be scanned simultaneously. • Alternate mode: channels of SAR ADC1 and SAR ADC2 will be scanned alternately. ESP32 supports up to a 12-bit SAR ADC resolution. The 16-bit data in DMA is composed of the ADC result and some necessary information related to the scanning mode: • For single mode, only 4-bit information on channel selection is added. • For double mode or alternate mode, 4-bit information on channel selection is added plus one extra bit indicating which SAR ADC was selected. For each scanning mode there is a corresponding data format, called Type I and Type II. Both data formats are described in Tables 97 and 98. Espressif Systems 447 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Table 97: Fields of Type I DMA Data Format Type I DMA Data Format [15:0] ch_sel[3:0] data[11:0] channel SAR ADC data Table 98: Fields of Type II DMA Data Format Type II DMA Data Format [15:0] sar_sel ch_sel[3:0] SAR ADC data[10:0] SAR ADCn channel SAR ADC data For Type I the resolution of SAR ADC is up to 12 bits, while for Type II the resolution is 11 bits at most. DIG SAR ADC Controllers allow the use of I2S for direct memory access. The WS signal of I2S acts as a measurement-trigger signal. The DATA signal provides the information that the measurement result is ready. Software can configure APB_SARADC_DATA_TO_I2S, in order to connect ADC to I2S. 23.4 Low-Noise Amplifier 23.4.1 Introduction ESP32 integrates an analog amplifier designed to amplify a small DC signal that is then passed on to SAR ADC1 for sampling. The amplification gain is adjustable with two off-chip capacitors. 23.4.2 Features • Configurable gain by changing the value of two sampling capacitors connected to pins SENSOR_CAPP / SENSOR_VP and SENSOR_CAPN / SENSOR_VN; see Figure 116. • Designed to operate with other on-chip components like e.g. DAC or ULP coprocessor. 23.4.3 Overview of Function The structure of the low-noise amplifier is shown in Figure 116: Figure 116: Structure of Low-Noise Amplifier Espressif Systems 448 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING The amplifier’s sequence of operation is shown in Figure 117: Figure 117: Low-Noise Amplifier – Sequence of Operation 1. The process is started by en_sar_amp. The amplifier is powered up and connected to the SAR ADC1. 2. A pulse on amp_rst_fb resets the amplifier. Vin is sampled by charging external capacitors. 3. Finally, amp_short_ref is closed. This starts integrating the Vin sample by the amplifier. Vampo = Vin · C + Vcm C is the value of external capacitors in pF. Vcm is the common-mode voltage of the amplifier output, which is fixed. If the common-mode voltage input, Vin , is about 0V, amp_short_ref_gnd could take the place of amp_short_ref . In other cases, the bit controlling this signal should be always cleared. After the Vampo becomes stable, the SAR ADC1 converts it into a digital value. Since the low-power amplifier works always together with SAR ADC, it is usually controlled by the FSM in RTC ADC1 CTRL. 23.5 Hall Sensor 23.5.1 Introduction The Hall effect is the generation of a voltage difference across an n-type semiconductor passing electrical current, when a magnetic field is applied to it in a direction perpendicular to that of the flow of the current. The voltage is proportional to the product of the magnetic field’s strength and current value. A Hall-effect sensor could be used to measure the strength of a magnetic field, when constant current flows through it, or when the current is in the presence of a constant magnetic field. As the heart of many applications, the Hall-effect sensors provide proximity detection, positioning, speed measurement, and current sensing. Inside of ESP32 there is a Hall sensor for magnetic field-sensing applications, which is designed to feed voltage signals to the ultra-low noise amplifier and SAR ADC. It can be controlled by the ULP coprocessor, when low-power operation is required. Such functionality, which enhances the power-processing and flexibility of ESP32, makes it an attractive solution for position sensing, proximity detection, speed measurement, etc. Espressif Systems 449 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 23.5.2 Features • Built-in Hall element with amplifier • Designed to operate with low-noise amplifier and ADC • Capable of outputting both analog voltage and digital signals related to the strength of the magnetic field • Powerful and easy-to-implement functionality, due to its integration with built-in ULP coprocessor, GPIOs, CPU, Wi-Fi, etc. 23.5.3 Functional Description The Hall sensor converts the magnetic field into voltage, feeds it into an amplifier, and then outputs it through pin SENSOR_VP and pin SENSOR_VN. ESP32’s built-in low-noise amplifier and ADC convert the voltage into a digital value for processing by the CPU in the digital domain. The inner structure of a Hall sensor is shown in Figure 118. Figure 118: Hall Sensor The configuration of a Hall sensor for reading is done with registers SENS_SAR_TOUCH_CTRL1_REG and RTCIO_HALL_SENS_REG, which are used to power up the Hall sensor and connect it to the low-noise amplifier. The subsequent processing is done by SAR ADC1. The result is obtained from the RTC ADC1 controller. For more details, please refer to sections 23.4 and 23.3. 23.6 Temperature Sensor 23.6.1 Introduction The temperature sensor generates a voltage that changes linearly with temperature. The output voltage is then converted with ADC into a digital value. The temperature measurement range is -40°C ~ 125°C. It should be noted that temperature measurements are affected by heat generated by Wi-Fi circuitry. This depends on power transmission, data transfer, module / PCB construction and the related dispersion of heat. Also, temperature-versus-voltage characteristics have different offset from chip to chip, due to process variation. Espressif Systems 450 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Therefore, the temperature sensor is suitable mainly for applications that detect temperature changes rather than the absolute value of temperature. Improvement of accuracy in absolute temperature measurement is possible by performing sensor calibration and by operating ESP32 in low-power modes which reduce variation and the amount of heat generated by the module itself. 23.6.2 Features • Temperature measurement range: -40°C to 125°C • Suitable for applications that detect changes in temperature rather than the absolute value of temperature. 23.6.3 Functional Description A generic schematic description of the temperature sensor’s operation is provided in Figure 119. The temperature-sensing device converts the temperature into voltage; then, the ADC samples and converts the voltage into a digital value. Eventually, this value can be processed by a user application. Figure 119: Temperature Sensor The configuration of the temperature sensor is done by using register SENS_SAR_TSENS_CTRL_REG. The conversion status is available in register SENS_TSENS_RDY_OUT. The measurement result can be read from SENS_TSENS_OUT. 23.7 DAC 23.7.1 Introduction Two 8-bit DAC channels can be used to convert digital values into analog output signals (up to two of them). The design structure is composed of integrated resistor strings and a buffer. This dual DAC supports power supply and uses it as input voltage reference. The dual DAC also supports independent or simultaneous signal conversions inside of its channels. 23.7.2 Features The features of DAC are as follows: • Two 8-bit DAC channels • Independent or simultaneous conversion in channels • Voltage reference from the VDD3P3_RTC pin Espressif Systems 451 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING • Cosine waveform (CW) generator • DMA capability • Start of conversion can be triggered by software or SAR ADC FSM (please refer to the SAR ADC chapter for more details) • Can be fully controlled by the ULP coprocessor A diagram showing the DAC channel’s function is presented in Figure 120. For a detailed description, see the sections below. Figure 120: Diagram of DAC function 23.7.3 Structure The two 8-bit DAC channels can be configured independently. For each DAC channel, the output analog voltage can be calculated as follows: DACn_OUT = VDD3P3_RTC · PDACn_DAC/256 • VDD3P3_RTC is the voltage on pin VDD3P3_RTC (typically 3.3V). • PDACn_DAC has multiple sources: CW generator, register RTCIO_PAD_DACn_REG, and DMA. The start of conversion is determined by register RTCIO_PAD_PDACn_XPD_DAC. The conversion process itself is controlled by software or SAR ADC FSM; see Figure 120. 23.7.4 Cosine Waveform Generator The cosine waveform (CW) generator can be used to generate a cosine / sine tone. A diagram showing cosine waveform generator’s function is presented in Figure 121. The CW generator has the following features: • Adjustable frequency The frequency of CW can be adjusted by register SENS_SAR_SW_FSTEP[15:0]: freq = dig_clk_rtc_freq · SENS_SAR_SW_FSTEP/65536 The frequency of dig_clk_rtc is typically 8 MHz. Espressif Systems 452 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING • Scaling Configuring register SENS_SAR_DAC_SCALEn[1:0]; the amplitude of a CW can be multiplied by 1, 1/2, 1/4 or 1/8. • DC offset The offset may be introduced by register SENS_SAR_DAC_DCn[7:0]. The result will be saturated. • Phase shift A phase-shift of 0 / 90 / 180 / 270 degrees can be added by setting register SENS_SAR_DAC_INVn[1:0]. Figure 121: Cosine Waveform (CW) Generator 23.7.5 DMA support A DMA controller with dual DMA channels can be used to set the output of two DAC channels. By configuring SENS_SAR_DAC_DIG_FORCE, I2S_clk can be connected to DAC clk, and I2S_DATA_OUT can be connected to DAC_DATA for direct memory access. For details, please refer to chapter DMA. 23.8 Register Summary Note: The registers listed below have been grouped, according to their functionality. This particular grouping does not reflect the exact sequential order of their place in memory. 23.8.1 Sensors Name Description Address Access Touch pad setup and control registers SENS_SAR_TOUCH_CTRL1_REG Touch pad control 0x3FF48858 R/W SENS_SAR_TOUCH_CTRL2_REG Touch pad control and status 0x3FF48884 RO SENS_SAR_TOUCH_ENABLE_REG Wakeup interrupt control and working set 0x3FF4888C R/W SENS_SAR_TOUCH_THRES1_REG Threshold setup for pads 0 and 1 0x3FF4885C R/W SENS_SAR_TOUCH_THRES2_REG Threshold setup for pads 2 and 3 0x3FF48860 R/W SENS_SAR_TOUCH_THRES3_REG Threshold setup for pads 4 and 5 0x3FF48864 R/W SENS_SAR_TOUCH_THRES4_REG Threshold setup for pads 6 and 7 0x3FF48868 R/W SENS_SAR_TOUCH_THRES5_REG Threshold setup for pads 8 and 9 0x3FF4886C R/W SENS_SAR_TOUCH_OUT1_REG Counters for pads 0 and 1 0x3FF48870 RO Espressif Systems 453 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING SENS_SAR_TOUCH_OUT2_REG Counters for pads 2 and 3 0x3FF48874 RO SENS_SAR_TOUCH_OUT3_REG Counters for pads 4 and 5 0x3FF48878 RO SENS_SAR_TOUCH_OUT4_REG Counters for pads 6 and 6 0x3FF4887C RO SENS_SAR_TOUCH_OUT5_REG Counters for pads 8 and 9 0x3FF48880 RO SAR ADC1 and ADC2 control 0x3FF4882C R/W SENS_SAR_READ_CTRL_REG SAR ADC1 data and sampling control 0x3FF48800 R/W SENS_SAR_MEAS_START1_REG SAR ADC1 conversion control and status 0x3FF48854 RO SENS_SAR_READ_CTRL2_REG SAR ADC2 data and sampling control 0x3FF48890 R/W SENS_SAR_MEAS_START2_REG SAR ADC2 conversion control and status 0x3FF48894 RO 0x3FF48818 R/W SAR ADC control register SENS_SAR_START_FORCE_REG SAR ADC1 control registers SAR ADC2 control registers ULP coprocessor configuration register SENS_ULP_CP_SLEEP_CYC0_REG Sleep cycles for ULP coprocessor Pad attenuation configuration registers SENS_SAR_ATTEN1_REG 2-bit attenuation for each pad 0x3FF48834 R/W SENS_SAR_ATTEN2_REG 2-bit attenuation for each pad 0x3FF48838 R/W SENS_SAR_TSENS_CTRL_REG Temperature sensor configuration 0x3FF4884C R/W SENS_SAR_SLAVE_ADDR3_REG Temperature sensor readout 0x3FF48844 RO SENS_SAR_DAC_CTRL1_REG DAC control 0x3FF48898 R/W SENS_SAR_DAC_CTRL2_REG DAC output control 0x3FF4889C R/W Address Access Temperature sensor registers DAC control registers 23.8.2 Advanced Peripheral Bus Name Description SAR ADC1 and ADC2 common configuration registers APB_SARADC_CTRL_REG SAR ADC common configuration 0x06002610 R/W APB_SARADC_CTRL2_REG SAR ADC common configuration 0x06002614 R/W APB_SARADC_FSM_REG SAR ADC FSM sample cycles configuration 0x06002618 R/W APB_SARADC_SAR1_PATT_TAB1_REG Items 0 - 3 of pattern table 0x0600261C R/W APB_SARADC_SAR1_PATT_TAB2_REG Items 4 - 7 of pattern table 0x06002620 R/W APB_SARADC_SAR1_PATT_TAB3_REG Items 8 - 11 of pattern table 0x06002624 R/W APB_SARADC_SAR1_PATT_TAB4_REG Items 12 - 15 of pattern table 0x06002628 R/W APB_SARADC_SAR2_PATT_TAB1_REG Items 0 - 3 of pattern table 0x0600262C R/W APB_SARADC_SAR2_PATT_TAB2_REG Items 4 - 7 of pattern table 0x06002630 R/W APB_SARADC_SAR2_PATT_TAB3_REG Items 8 - 11 of pattern table 0x06002634 R/W APB_SARADC_SAR2_PATT_TAB4_REG Items 12 - 15 of pattern table 0x06002638 R/W SAR ADC1 pattern table registers SAR ADC2 pattern table registers 23.8.3 RTC I/O For details, please refer to Section Register Summary in Chapter IO_MUX and GPIO Matrix. Espressif Systems 454 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 23.9 Registers 23.9.1 Sensors 28 27 26 0 0 0 0 T 0 0 0 0 0 0 0 17 _D IV _C LK AM R1 _S SA R1 NS _ SA SE SE NS _ _S NS SE 18 0 PL E_ E_ PL AM 1_ S AR ) ed er v (re s SE 29 BI E 0 SE _S NS AR _S 1_ AR DA 1_ TA DI _IN G _F V O RC ) 0 NS ed rv se (re 31 CY CL E Register 23.1: SENS_SAR_READ_CTRL_REG (0x0000) 16 15 3 8 7 9 0 2 Reset SENS_SAR1_DATA_INV Invert SAR ADC1 data. (R/W) SENS_SAR1_DIG_FORCE 1: SAR ADC1 controlled by DIG ADC1 CTR, 0: SAR ADC1 controlled by RTC ADC1 CTRL. (R/W) SENS_SAR1_SAMPLE_BIT Bit width of SAR ADC1, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11: for 12-bit. (R/W) SENS_SAR1_SAMPLE_CYCLE Sample cycles for SAR ADC1. (R/W) SENS_SAR1_CLK_DIV Clock divider. (R/W) Register 23.2: SENS_ULP_CP_SLEEP_CYC0_REG (0x0018) 31 0 200 Reset SENS_ULP_CP_SLEEP_CYC0_REG Sleep cycles for ULP coprocessor timer. (R/W) Espressif Systems 455 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 31 0 0 0 0 0 0 0 24 23 22 21 0 0 0 0 0 0 se SE rve N d) SE S_U NS LP _U _C LP P_ SE _C ST NS P_ AR FO T_ _S RC TO AR SE 2_ E_ P PW NS ST AR _S DE SE A T_ T_ TO NS R2_ CC EN P _S T AR _T E SE 2_ BI ST NS T_ _S W AR ID TH 1_ BI T_ W ID TH NI T PC _I NS _ 0 0 0 (re SE (re s er ve d) SE N SE S_S NS AR _S 1_ AR ST 2_ OP ST O P Register 23.3: SENS_SAR_START_FORCE_REG (0x002c) 0 0 0 0 11 10 9 8 7 0 0 0 0 0 0 5 4 3 2 1 0 0 1 1 1 0 1 Reset SENS_SAR1_STOP Stop SAR ADC1 conversion. (R/W) SENS_SAR2_STOP Stop SAR ADC2 conversion. (R/W) SENS_PC_INIT Initialized PC for ULP coprocessor. (R/W) SENS_ULP_CP_START_TOP Write 1 to start ULP coprocessor; it is active only when reg_ulp_cp_force_start_top = 1. (R/W) SENS_ULP_CP_FORCE_START_TOP 1: ULP coprocessor is started by SW, 0: ULP coprocessor is started by timer. (R/W) SENS_SAR2_PWDET_CCT SAR2_PWDET_CCT, PA power detector capacitance tuning. (R/W) SENS_SAR2_EN_TEST SAR2_EN_TEST is active only when reg_sar2_dig_force = 0. (R/W) SENS_SAR2_BIT_WIDTH Bit width of SAR ADC1, 00: 9 bits, 01: 10 bits, 10: 11 bits, 11: 12 bits. (R/W) SENS_SAR1_BIT_WIDTH Bit width of SAR ADC2, 00: 9 bits, 01: 10 bits, 10: 11 bits, 11: 12 bits. (R/W) Register 23.4: SENS_SAR_ATTEN1_REG (0x0034) 31 0 0x0FFFFFFFF Reset SENS_SAR_ATTEN1_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB, [1:0] is used for ADC1_CH0, [3:2] is used for ADC1_CH1, etc. (R/W) Register 23.5: SENS_SAR_ATTEN2_REG (0x0038) 31 0 0x0FFFFFFFF Reset SENS_SAR_ATTEN2_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB, [1:0] is used for ADC2_CH0, [3:2] is used for ADC2_CH1, etc (R/W) Espressif Systems 456 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 30 0 0 rv _T se NS (re SE (re 31 ed ) SE NS se SE rve NS d) _T SE NS _R D _O UT Y_ O UT Register 23.6: SENS_SAR_SLAVE_ADDR3_REG (0x0044) 29 22 0x000 43 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SENS_TSENS_RDY_OUT This indicates that the temperature sensor’s output is ready. (RO) SENS_TSENS_OUT Temperature sensor data output. (RO) 31 0 0 0 0 rv e d) SE _T N S SE S_T ENS NS SE _D _T NS UM SE _P P NS O _O _P WE UT O R_ W U ER P_ _U FO SE P RC NS E _T SE NS _C LK _D IV SE NS _T SE NS _I N_ IN V 27 26 25 24 0 0 0 0 23 16 6 SENS_TSENS_DUMP_OUT Temperature 15 29 0 0 sensor se (re (re SE NS se rv ed ) Register 23.7: SENS_SAR_TSENS_CTRL_REG (0x004c) 15 0 0 0 dump 0 0 0 output; 0 0 0 active 0 0 0 only 0 0 Reset when reg_tsens_power_up_force = 1. (R/W) SENS_TSENS_POWER_UP_FORCE 1: Temperature sensor dump output & power-up controlled by SW; 0: controlled by FSM. (R/W) SENS_TSENS_POWER_UP Temperature sensor power-up. (R/W) SENS_TSENS_CLK_DIV Temperature sensor clock divider. (R/W) SENS_TSENS_IN_INV Invert temperature sensor data. (R/W) Espressif Systems 457 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 31 30 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 0 0 0 0 0 R SA _D AT A_ EA S1 M NS _ SE SE SE NS _ NS _ SA SA R1 R1 _E _E N_ PA D N_ PA D _F O RC E SE N SE S_M N E SE S_M AS NS E 1_ _M AS STA EA 1_S RT S1 TA _F _D RT OR O _S CE NE A _S R AR Register 23.8: SENS_SAR_MEAS_START1_REG (0x0054) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SENS_SAR1_EN_PAD_FORCE 1: SAR ADC1 pad enable bitmap is controlled by SW, 0: SAR ADC1 pad enable bitmap is controlled by ULP coprocessor. (R/W) SENS_SAR1_EN_PAD SAR ADC1 pad enable bitmap; active only when reg_sar1_en_pad_force = 1. (R/W) SENS_MEAS1_START_FORCE 1: SAR ADC1 controller (in RTC) is started by SW, 0: SAR ADC1 controller is started by ULP coprocessor. (R/W) SENS_MEAS1_START_SAR SAR ADC1 controller (in RTC) starts conversion; active only when reg_meas1_start_force = 1. (R/W) SENS_MEAS1_DONE_SAR SAR ADC1 conversion-done indication. (RO) SENS_MEAS1_DATA_SAR SAR ADC1 data. (RO) Espressif Systems 458 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 31 0 0 0 28 27 26 25 24 0 0 0 1 0 23 16 DE LA Y S_ EA UC H_ M TO NS _ SE N SE S_H NS A SE _X LL_ N P P SE S_T D_H HAS NS OU AL E_ _ T C L_ FO O H_ FO RC UC O R E H_ UT CE O _1E UT N _S EL SE NS _T O UC H_ XP D_ W AI T (re SE se rv ed ) Register 23.9: SENS_SAR_TOUCH_CTRL1_REG (0x0058) 15 0x004 0 0x01000 Reset SENS_HALL_PHASE_FORCE 1: HALL PHASE is controlled by SW, 0: HALL PHASE is controlled by FSM in ULP coprocessor. (R/W) SENS_XPD_HALL_FORCE 1: XPD HALL is controlled by SW, 0: XPD HALL is controlled by FSM in ULP coprocessor. (R/W) SENS_TOUCH_OUT_1EN 1: wakeup interrupt is generated if SET1 is touched, 0: wakeup interrupt is generated only if both SET1 & SET2 are touched. (R/W) SENS_TOUCH_OUT_SEL 1: the touch pad is considered touched when the value of the counter is greater than the threshold, 0: the touch pad is considered touched when the value of the counter is less than the threshold. (R/W) SENS_TOUCH_XPD_WAIT The waiting time (in 8 MHz cycles) between TOUCH_START and TOUCH_XPD. (R/W) SENS_TOUCH_MEAS_DELAY The measurement’s duration (in 8 MHz cycles). (R/W) 31 SE SE N NS _T O S_ TO UC UC H_ O H_ O UT UT _T _T H0 H1 Register 23.10: SENS_SAR_TOUCH_THRES1_REG (0x005c) 16 15 0x00000 0 0x00000 Reset SENS_TOUCH_OUT_TH0 The threshold for touch pad 0. (R/W) SENS_TOUCH_OUT_TH1 The threshold for touch pad 1. (R/W) Espressif Systems 459 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING SE SE NS NS _ _T TO O UC H_ O UC H_ O UT UT _ _T H2 TH 3 Register 23.11: SENS_SAR_TOUCH_THRES2_REG (0x0060) 31 16 15 0x00000 0 0x00000 Reset SENS_TOUCH_OUT_TH2 The threshold for touch pad 2. (R/W) SENS_TOUCH_OUT_TH3 The threshold for touch pad 3. (R/W) SE SE NS NS _T _T O O UC UC H_ H_ O O UT UT _T _T H 4 H5 Register 23.12: SENS_SAR_TOUCH_THRES3_REG (0x0064) 31 16 15 0x00000 0 0x00000 Reset SENS_TOUCH_OUT_TH4 The threshold for touch pad 4. (R/W) SENS_TOUCH_OUT_TH5 The threshold for touch pad 5. (R/W) 31 SE SE N NS _T O S_ TO UC UC H_ O H_ O UT _T H6 UT _T H7 Register 23.13: SENS_SAR_TOUCH_THRES4_REG (0x0068) 16 15 0x00000 0 0x00000 Reset SENS_TOUCH_OUT_TH6 The threshold for touch pad 6. (R/W) SENS_TOUCH_OUT_TH7 The threshold for touch pad 7. (R/W) Espressif Systems 460 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING SE SE NS NS _ _T TO O UC H_ O UC H_ O UT UT _ _T H8 TH 9 Register 23.14: SENS_SAR_TOUCH_THRES5_REG (0x006c) 31 16 15 0 0x00000 0x00000 Reset SENS_TOUCH_OUT_TH8 The threshold for touch pad 8. (R/W) SENS_TOUCH_OUT_TH9 The threshold for touch pad 9. (R/W) SE SE NS NS _T _T O O UC UC H_ M H_ M EA EA S_ S_ O O UT UT 0 1 Register 23.15: SENS_SAR_TOUCH_OUT1_REG (0x0070) 31 16 15 0 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT0 The counter for touch pad 0. (RO) SENS_TOUCH_MEAS_OUT1 The counter for touch pad 1. (RO) SE SE NS NS _T _T O O UC UC H_ M H_ M EA EA S_ S_ O O UT 2 UT 3 Register 23.16: SENS_SAR_TOUCH_OUT2_REG (0x0074) 31 16 15 0 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT2 The counter for touch pad 2. (RO) SENS_TOUCH_MEAS_OUT3 The counter for touch pad 3. (RO) Espressif Systems 461 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING SE SE NS _ NS _ TO TO UC H _M UC H_ M EA EA S_ S_ O O UT 4 UT 5 Register 23.17: SENS_SAR_TOUCH_OUT3_REG (0x0078) 31 16 15 0 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT4 The counter for touch pad 4. (RO) SENS_TOUCH_MEAS_OUT5 The counter for touch pad 5. (RO) SE SE NS NS _T _T O O UC UC H_ M H_ M EA EA S_ S_ O O UT UT 6 7 Register 23.18: SENS_SAR_TOUCH_OUT4_REG (0x007c) 31 16 15 0 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT6 The counter for touch pad 6. (RO) SENS_TOUCH_MEAS_OUT7 The counter for touch pad 7. (RO) SE SE NS NS _T _T O O UC UC H_ M H_ M EA S_ O EA S_ O UT UT 8 9 Register 23.19: SENS_SAR_TOUCH_OUT5_REG (0x0080) 31 16 15 0 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT8 The counter for touch pad 8. (RO) SENS_TOUCH_MEAS_OUT9 The counter for touch pad 9. (RO) Espressif Systems 462 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING CL ES R P_ CY _C L UC H_ SL EE S_ EN EA M _T O UC H_ SE NS se SE rve NS d) _T O (re 31 30 0 0 SE N SE S_T NS OU SE _T C N O H_ SE S_T UC ST NS OU H_ AR _T C STA T_F O H_ R O UC S T R H_ TAR _EN CE M T_ EA F S_ SM DO _E NE N SE NS _T O UC H_ M EA S_ EN Register 23.20: SENS_SAR_TOUCH_CTRL2_REG (0x0084) 29 14 0x00100 13 12 11 10 0 0 1 0 9 0 0x000 Reset SENS_TOUCH_MEAS_EN_CLR Set to clear reg_touch_meas_en. (WO) SENS_TOUCH_SLEEP_CYCLES Sleep cycles for timer. (R/W) SENS_TOUCH_START_FORCE 1: starts the Touch FSM via software; 0: starts the Touch FSM via timer. (R/W) SENS_TOUCH_START_EN 1: starts the Touch FSM; this is valid when reg_touch_start_force is set. (R/W) SENS_TOUCH_START_FSM_EN 1: TOUCH_START & TOUCH_XPD are controlled by the Touch FSM; 0: TOUCH_START & TOUCH_XPD are controlled by registers. (R/W) SENS_TOUCH_MEAS_DONE Set to 1 by FSM, indicating that touch measurement is done. (RO) SENS_TOUCH_MEAS_EN 10-bit register indicating which pads are touched. (RO) 30 0 0 20 0x3FF 19 EN RK O _W H_ PA D UC O _T SE SE SE 29 NS O NS _T d) rv e se (re 31 NS _T O UC UC H_ PA D H_ PA D _O _O UT UT EN EN 2 1 Register 23.21: SENS_SAR_TOUCH_ENABLE_REG (0x008c) 10 9 0x3FF 0 0x3FF Reset SENS_TOUCH_PAD_OUTEN1 Bitmap defining SET1 for generating a wakeup interrupt; SET1 is considered touched if at least one of the touch pads in SET1 is touched. (R/W) SENS_TOUCH_PAD_OUTEN2 Bitmap defining SET2 for generating a wakeup interrupt; SET2 is considered touched if at least one of the touch pads in SET2 is touched. (R/W) SENS_TOUCH_PAD_WORKEN Bitmap defining the working set during measurement. (R/W) Espressif Systems 463 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 30 29 28 27 0 0 0 0 0 0 0 0 0 0 0 0 R2 SA NS _ SA SE SE NS _ NS SE 0 17 _C LK _D IV M _S A R2 2_ S AR _S d) ve er (re s 18 0 PL E_ E_ BI T AM PL d) NS SE _S NS AR _S 2_ AR DA 2_ TA DI _IN G _F V O RC E ve er SE (re s 31 CY CL E Register 23.22: SENS_SAR_READ_CTRL2_REG (0x0090) 16 15 8 3 7 0 9 2 Reset SENS_SAR2_DATA_INV Invert SAR ADC2 data. (R/W) SENS_SAR2_DIG_FORCE 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL, 0: SAR ADC2 controlled by RTC ADC2 CTRL (R/W) SENS_SAR2_SAMPLE_BIT Bit width of SAR ADC2, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11: for 12-bit. (R/W) SENS_SAR2_SAMPLE_CYCLE Sample cycles of SAR ADC2. (R/W) SENS_SAR2_CLK_DIV Clock divider. (R/W) 31 30 0 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 15 0 0 0 0 0 R SA _D AT A_ S2 _M EA NS SE SE SE NS NS _S _S AR AR 2_ 2_ EN EN _P AD _P AD _F O RC E SE N SE S_M N E SE S_M AS NS E 2_ _M AS STA EA 2_S RT S2 TA _F _D RT OR O _S CE NE A _S R AR Register 23.23: SENS_SAR_MEAS_START2_REG (0x0094) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SENS_SAR2_EN_PAD_FORCE 1: SAR ADC2 pad enable bitmap is controlled by SW, 0: SAR ADC2 pad enable bitmap is controlled by ULP coprocessor. (R/W) SENS_SAR2_EN_PAD SAR ADC2 pad enable bitmap; active only when reg_sar2_en_pad_force = 1. (R/W) SENS_MEAS2_START_FORCE 1: SAR ADC2 controller (in RTC) is started by SW, 0: SAR ADC2 controller is started by ULP coprocessor. (R/W) SENS_MEAS2_START_SAR SAR ADC2 controller (in RTC) starts conversion; active only when reg_meas2_start_force = 1. (R/W) SENS_MEAS2_DONE_SAR SAR ADC2-conversion-done indication. (RO) SENS_MEAS2_DATA_SAR SAR ADC2 data. (RO) Espressif Systems 464 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 31 0 0 0 0 0 26 25 24 23 22 21 0 0 0 0 0 0 0 0 EP _E N ST NE SW _F _T O NS _ SW SE NS _ SE (re se rv ed ) SE N SE S_D N A SE S_D C_ NS A CL SE _D C_ K_I NS A CL NV _D C_C K_F AC LK OR _D _F CE IG OR _H _F C IG (re O E_ H se RC L rv ed E OW ) Register 23.24: SENS_SAR_DAC_CTRL1_REG (0x0098) 17 16 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SENS_DAC_CLK_INV 1: inverts PDAC_CLK, 0: no inversion. (R/W) SENS_DAC_CLK_FORCE_HIGH forces PDAC_CLK to be 1. (R/W) SENS_DAC_CLK_FORCE_LOW forces PDAC_CLK to be 0. (R/W) SENS_DAC_DIG_FORCE 1: DAC1 & DAC2 use DMA, 0: DAC1 & DAC2 do not use DMA. (R/W) SENS_SW_TONE_EN 1: enable CW generator, 0: disable CW generator. (R/W) SENS_SW_FSTEP Frequency step for CW generator; can be used to adjust the frequency. (R/W) 31 0 0 0 0 0 26 25 24 23 22 21 0 1 1 0 0 0 20 19 0 0 18 17 0 0 16 _D AC _D NS SE 15 0 0 C1 C2 _D AC _D NS SE (re se rv ed ) SE N SE S_D NS A _ C_ SE DA CW NS C_ _E _D CW N2 AC _E N SE _I NV 1 NS 2 _D AC SE _I NV NS 1 _D AC SE _S NS CA _D LE AC 2 _S CA LE 1 Register 23.25: SENS_SAR_DAC_CTRL2_REG (0x009c) 8 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 Reset SENS_DAC_CW_EN2 1: selects CW generator as source for PDAC2_DAC[7:0], 0: selects register reg_pdac2_dac[7:0] as source for PDAC2_DAC[7:0]. (R/W) SENS_DAC_CW_EN1 1: selects CW generator as source for PDAC1_DAC[7:0], 0: selects register reg_pdac1_dac[7:0] as source for PDAC1_DAC[7:0]. (R/W) SENS_DAC_INV2 DAC2, 00: does not invert any bits, 01: inverts all bits, 10: inverts MSB, 11: inverts all bits except for MSB. (R/W) SENS_DAC_INV1 DAC1, 00: does not invert any bits, 01: inverts all bits, 10: inverts MSB, 11: inverts all bits except for MSB. (R/W) SENS_DAC_SCALE2 DAC2, 00: no scale, 01: scale to 1/2, 10: scale to 1/4, scale to 1/8. (R/W) SENS_DAC_SCALE1 DAC1, 00: no scale, 01: scale to 1/2, 10: scale to 1/4, scale to 1/8. (R/W) SENS_DAC_DC2 DC offset for DAC2 CW generator. (R/W) SENS_DAC_DC1 DC offset for DAC1 CW generator. (R/W) Espressif Systems 465 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING 23.9.2 Advanced Peripheral Bus AP (re s er ve d) B AP _SA B R AP _SA AD B_ RA C_ AP SA D DA B_ RA C_ TA_ SA D DA TO RA C_ TA_ _I DC SA SA 2S AP _S R2_ R_ B_ AR PA SE SA 1_ TT L RA PA _P TT _C DC _P LE _S _C AR AR LE 2_ AR AP PA TT B_ _L SA EN RA DC _S AR 1_ PA TT _L EN AP B_ SA RA DC _S AR _C LK AP _D B IV AP _SA B_ RA S D AP AR C_ B_ AD SA C_ R_ S SA CL AP AR A B_ DC R_S K_G AP SA EL AT _W B R ED O AP _SA AD RK B_ RA C_ _ M SA D SA O DE RA C_ R2 DC STA _M _S R T UX TA RT _F O RC E Register 23.26: APB_SARADC_CTRL_REG (0x10) 31 0 0 0 0 27 26 25 24 23 0 0 0 0 0 22 19 15 18 15 14 15 7 4 6 5 1 0 4 3 0 2 1 0 0 0 0 Reset APB_SARADC_DATA_TO_I2S 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix. (R/W) APB_SARADC_DATA_SAR_SEL 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case, the resolution should not contain more than 11 bits; 0: using 12-bit SAR ADC resolution. (R/W) APB_SARADC_SAR2_PATT_P_CLEAR Clears the pointer of pattern table for DIG ADC2 CTRL. (R/W) APB_SARADC_SAR1_PATT_P_CLEAR Clears the pointer of pattern table for DIG ADC1 CTRL. (R/W) APB_SARADC_SAR2_PATT_LEN SAR ADC2, 0 - 15 means pattern table length of 1 - 16. (R/W) APB_SARADC_SAR1_PATT_LEN SAR ADC1, 0 - 15 means pattern table length of 1 - 16. (R/W) APB_SARADC_SAR_CLK_DIV SAR clock divider. (R/W) APB_SARADC_SAR_CLK_GATED Reserved. Please initialize to 0b1 (R/W) APB_SARADC_SAR_SEL 0: SAR1, 1: SAR2, this setting is applicable in the single SAR mode. (R/W) APB_SARADC_WORK_MODE 0: single mode, 1: double mode, 2: alternate mode. (R/W) APB_SARADC_SAR2_MUX 1: SAR ADC2 is controlled by DIG ADC2 CTRL, 0: SAR ADC2 is controlled by PWDET CTRL. (R/W) APB_SARADC_START Reserved. Please initialize to 0 (R/W) APB_SARADC_START_FORCE Reserved. Please initialize to 0 (R/W) Espressif Systems 466 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING AP (re s er ve d) B AP _SA B_ RA SA D RA C_ DC SA _S R2_ AR IN 1_ V IN V AP B_ SA RA DC _M AX _M EA AP S_ B_ NU SA M RA DC _M EA S_ NU M _L IM IT Register 23.27: APB_SARADC_CTRL2_REG (0x14) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 0 0 0 8 1 255 0 0 Reset APB_SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted, 0: data is not inverted. (R/W) APB_SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted, 0: data is not inverted. (R/W) APB_SARADC_MAX_MEAS_NUM Max conversion number. (R/W) APB_SARADC_MEAS_NUM_LIMIT Reserved. Please initialize to 0b1 (R/W) 31 (re AP B_ se rv SA ed ) RA DC _S A M PL E_ CY CL E Register 23.28: APB_SARADC_FSM_REG (0x18) 24 2 47 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset APB_SARADC_SAMPLE_CYCLE Sample cycles. (R/W) Register 23.29: APB_SARADC_SAR1_PATT_TAB1_REG (0x1C) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR1_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC1, one byte for each pattern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation, [23:20] pattern1_channel, etc. (R/W) Espressif Systems 467 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Register 23.30: APB_SARADC_SAR1_PATT_TAB2_REG (0x20) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR1_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC1, one byte for each pattern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation, [23:20] pattern5_channel, etc. (R/W) Register 23.31: APB_SARADC_SAR1_PATT_TAB3_REG (0x24) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR1_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC1, one byte for each pattern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation, [23:20] pattern9_channel, etc. (R/W) Register 23.32: APB_SARADC_SAR1_PATT_TAB4_REG (0x28) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR1_PATT_TAB4_REG Pattern tables 12 - 15 for SAR ADC1, one byte for each pattern table: [31:28] pattern12_channel, [27:26] pattern12_bit_width, [25:24] pat- tern12_attenuation, [23:20] pattern13_channel, etc. (R/W) Register 23.33: APB_SARADC_SAR2_PATT_TAB1_REG (0x2C) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR2_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC2, one byte for each pattern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation, [23:20] pattern1_channel, etc. (R/W) Register 23.34: APB_SARADC_SAR2_PATT_TAB2_REG (0x30) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR2_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC2, one byte for each pattern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation, [23:20] pattern5_channel, etc. (R/W) Espressif Systems 468 ESP32 Technical Reference Manual V2.0 23. ON-CHIP SENSORS AND ANALOG SIGNAL PROCESSING Register 23.35: APB_SARADC_SAR2_PATT_TAB3_REG (0x34) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR2_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC2, one byte for each pattern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation, [23:20] pattern9_channel, etc. (R/W) Register 23.36: APB_SARADC_SAR2_PATT_TAB4_REG (0x38) 31 0 0x00F0F0F0F Reset APB_SARADC_SAR2_PATT_TAB4_REG Pattern tables 12 - 15 for SAR ADC2, one byte for each pattern table: [31:28] pattern12_channel, [27:26] pattern12_bit_width, [25:24] pat- tern12_attenuation, [23:20] pattern13_channel, etc. (R/W) 23.9.3 RTC I/O For details, please refer to Section Registers in Chapter IO_MUX and GPIO Matrix. Espressif Systems 469 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24. ULP Co-processor 24.1 Introduction The ULP co-processor is an ultra-low-power processor that remains powered on during the Deep-sleep mode of the main SoC. Hence, the developer can store in the RTC memory a program for the ULP co-processor to access peripheral devices, internal sensors and RTC registers during deep sleep. This is useful for designing applications where the CPU needs to be woken up by an external event, or timer, or a combination of these, while maintaining minimal power consumption. 24.2 Features • Contains up to 8 KB of SRAM for instructions and data • Uses RTC_FAST_CLK, which is 8 MHz • Works both in normal and deep sleep • Is able to wake up the digital core or send an interrupt to the CPU • Can access peripheral devices, internal sensors and RTC registers • Contains four 16-bit general-purpose registers (R0, R1, R2, R3) for manipulating data and accessing memory • Includes one 8-bit Stage_cnt register which can be manipulated by ALU and used in JUMP instructions bridge APB Bus RTC CNTL REG RTC Memory RTC IO REG Arbiter SARADC REG I2C CTRL RTC I2C REG TSENS CTRL SAR CTRL ULP Coprocessor RTC Timer ESP32 RTC Figure 122: ULP Co-processor Diagram Espressif Systems 470 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24.3 Functional Description The ULP co-processor is a programmable FSM (Finite State Machine) that can work during deep sleep. Like general-purpose CPUs, ULP co-processor also has some instructions which can be useful for a relatively complex logic, and also some special commands for RTC controllers/peripherals. The 8 KB of SRAM RTC slow memory can be accessed by both the ULP co-processor and the CPU; hence, it is usually used to store instructions and share data between the ULP co-processor and the CPU. The ULP co-processor can be started by software or a periodically-triggered timer. The operation of the ULP co-processor is ended by executing the HALT instruction. Meanwhile, it can access almost every module in RTC domain, either through built-in instructions or RTC registers. In many cases the ULP co-processor can be a good supplement to, or replacement of, the CPU, especially for power-sensitive applications. Figure 122 shows the overall layout of a ULP co-processor. 24.4 Instruction Set The ULP co-processor provides the following instructions: • Perform arithmetic and logic operations - ALU • Load and store data - LD, ST, REG_RD and REG_WR • Jump to a certain address - JUMP • Manage program execution - WAIT/HALT • Control sleep period of ULP co-processor - SLEEP • Wake up/communicate with SoC - WAKE • Take measurements - TSENS and ADC • Communicate using I2C - I2C_RD/I2C_WR The ULP co-processor’s instruction format is shown in Figure 123. 31 28 27 0 OpCode Operands Figure 123: The ULP Co-processor Instruction Format An instruction, which has one OpCode, can perform various different operations, depending on the setting of Operands bits. A good example is the ALU instruction, which is able to perform ten arithmetic and logic operations; or the JUMP instruction, which may be conditional or unconditional, absolute or relative. Each instruction has a fixed width of 32 bits. A series of instructions can make a program be executed by the ULP co-processor. The execution flow inside the program uses 32-bit addressing. The program is stored in a dedicated region called Slow Memory (RTC_SLOW_MEM), which is visible to the main CPUs as one that has an address range of 0x5000_0000 to 0x5000_1FFF (8 KB). Espressif Systems 471 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24.4.1 ALU - Perform Arithmetic/Logic Operations The ALU (Arithmetic and Logic Unit) performs arithmetic and logic operations on values stored in ULP co-processor registers, and on immediate values stored in the instruction itself. The following operations are supported: • Arithmetic: ADD and SUB • Logic: AND and OR • Bit shifting: LSH and RSH • Moving data to register: MOVE • Stage count register manipulation: STAGE_RST, STAGE_INC and STAGE_DEC The ALU instruction, which has one OpCode, can perform various different arithmetic and logic operations, depending on the setting of the instruction’s bits [27:21] accordingly. 24.4.1.1 Operations among Registers 31 28 27 3’d7 25 24 5 21 ALU_sel 1’b0 4 3 2 1 0 Rsrc2Rsrc1 Rdst Figure 124: Instruction Type — ALU for Operations among Registers When bits [27:25] of the instruction in Figure 124 are set to 1’b0, ALU performs operations, using the ULP co-processor register R[0-3]. The types of operations depend on the setting of the instruction’s bits [24:21] presented in Table 101. Operand Description - see Figure 124 ALU_sel Type of ALU operation Rdst Register R[0-3], destination Rsrc1 Register R[0-3], source Rsrc2 Register R[0-3], source ALU_sel Instruction Operation Description 0 ADD Rdst = Rsrc1 + Rsrc2 Add to register 1 SUB Rdst = Rsrc1 - Rsrc2 Subtract from register 2 AND Rdst = Rsrc1 & Rsrc2 Logical AND of two operands 3 OR Rdst = Rsrc1 | Rsrc2 Logical OR of two operands 4 MOVE Rdst = Rsrc1 Move to register 5 LSH Rdst = Rsrc1 <<�Rsrc2 Logical Shift Left 6 RSH Rdst = Rsrc1 >>�Rsrc2 Logical Shift Right Table 101: ALU Operations among Registers Note: • ADD/SUB operations can be used to set/clear the overflow flag in ALU. • All ALU operations can be used to set/clear the zero flag in ALU. Espressif Systems 472 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24.4.1.2 Operations with Immediate Value 31 28 27 3’d7 25 24 1’b1 19 21 4 ALU_sel 3 2 1 0 Rsrc1 Rdst Imm Figure 125: Instruction Type — ALU for Operations with Immediate Value When bits [27:25] of the instruction in Figure 125 are set to 1’b1, ALU performs operations, using register R[0-3] and the immediate value stored in [19:4]. The types of operations depend on the setting of the instruction’s bits [24:21] presented in Table 102. Operand Description - see Figure 125 ALU_sel Type of ALU operation Rdst Register R[0-3], destination Rsrc1 Register R[0-3], source Imm 16-bit signed value ALU_sel Instruction Operation Description 0 ADD Rdst = Rsrc1 + Imm Add to register 1 SUB Rdst = Rsrc1 - Imm Subtract from register 2 AND Rdst = Rsrc1 & Imm Logical AND of two operands 3 OR Rdst = Rsrc1 | Imm Logical OR of two operands 4 MOVE Rdst = Imm Move to register 5 LSH Rdst = Rsrc1 <<�Imm Logical Shift to the Left 6 RSH Rdst = Rsrc1 >>�Imm Logical Shift to the Right Table 102: ALU Operations with Immediate Value Note: • ADD/SUB operations can be used to set/clear the overflow flag in ALU. • All ALU operations can be used to set/clear the zero flag in ALU. 24.4.1.3 Operations with Stage Count Register 31 28 27 3’d7 25 24 1’b2 11 21 ALU_sel 4 Imm Figure 126: Instruction Type — ALU for Operations with Stage Count Register ALU is also able to increment/decrement by a given value, or reset the 8-bit register Stage_cnt. To do so, bits [27:25] of instruction in Figure 126 should be set to 1’b2. The type of operation depends on the setting of the instruction’s bits [24:21] presented in Table 103. The Stage_cnt is a separate register and is not a part of the instruction in Figure 126. Operand Description - see Figure 126 ALU_sel Type of ALU operation Stage_cnt Stage count register, a separate register [7:0] used to store variables, such as loop index Imm 8-bit value Espressif Systems 473 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR ALU_sel Instruction Operation Description 0 STAGE_INC Stage_cnt = Stage_cnt + Imm Increment stage count register 1 STAGE_DEC Stage_cnt = Stage_cnt - Imm Decrement stage count register 2 STAGE_RST Stage_cnt = 0 Reset stage count register Table 103: ALU Operations with Stage Count Register 24.4.2 ST – Store Data in Memory 31 28 27 3’d6 25 3’b100 20 4’b0 10 3 6’b0 Offset 2 1 0 Rsrc Rdst Figure 127: Instruction Type — ST Operand Description - see Figure 127 Offset 10-bit signed value, offset expressed in 32-bit words Rsrc Register R[0-3], 16-bit value to store Rdst Register R[0-3], address of the destination, expressed in 32-bit words Description The instruction stores the 16-bit value of Rsrc in the lower half-word of memory with address Rdst + Offset. The upper half-word is written with the current program counter (PC) expressed in words and shifted to the left by 5 bits: Mem [ Rdst + Offset ]{31:0} = {PC[10:0], 5’b0, Rsrc[15:0]} The application can use the higher 16 bits to determine which instruction in the ULP program has written any particular word into memory. Note: • This instruction can only access 32-bit memory words. • Data from Rsrc is always stored in the lower 16 bits of a memory word. Differently put, it is not possible to store Rsrc in the upper 16 bits of memory. • The ”Mem” written is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP co-processor, corresponds to address 0x50000000, as seen by the main CPUs. 24.4.3 LD – Load Data from Memory 31 28 20 3’d13 10 3 2 1 0 Rsrc Rdst Offset Figure 128: Instruction Type — LD Operand Description - see Figure 128 Offset 10-bit signed value, offset expressed in 32-bit words Rsrc Register R[0-3], address of destination memory, expressed in 32-bit words Rdst Register R[0-3], destination Description The instruction loads the lower 16-bit half-word from memory with address Rsrc + offset into the destination register Rdst: Espressif Systems 474 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR Rdst[15:0] = Mem[ Rsrc + Offset ][15:0] Note: • This instruction can only access 32-bit memory words. • In any case, it is always the lower 16 bits of a memory word that are loaded. Differently put, it is not possible to read the upper 16 bits. • The ”Mem” loaded is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP co-processor, corresponds to address 0x50000000, as seen by the main CPUs. 24.4.4 JUMP – Jump to an Absolute Address 28 27 3’d8 25 24 1’b0 22 21 Type 12 2 Sel 31 ImmAddr 1 0 Rdst Figure 129: Instruction Type — JUMP Operand Description - see Figure 129 Rdst Register R[0-3], address to jump to ImmAddr 13-bit address, expressed in 32-bit words Sel Selects the address to jump to: 0 - jump to the address contained in ImmAddr 1 - jump to the address contained in Rdst Type Jump type: 0 - make an unconditional jump 1 - jump only if the last ALU operation has set the zero flag 2 - jump only if the last ALU operation has set the overflow flag Description The instruction prompts a jump to the specified address. The jump can be either unconditional or based on the ALU flag. Note: All jump addresses are expressed in 32-bit words. 24.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) 28 27 3’d8 17 16 15 25 24 1’b1 Step Cond 31 0 Threshold Figure 130: Instruction Type — JUMPR Operand Description - see Figure 130 Step Relative shift from current position, expressed in 32-bit words: if Step[7] = 0 then PC = PC + Step[6:0] if Step[7] = 1 then PC = PC - Step[6:0] Threshold Threshold value for condition (see Cond below) to jump Cond Condition to jump: 0 - jump if R0 < Threshold 1 - jump if R0 >= Threshold Espressif Systems 475 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR Description The instruction prompts a jump to a relative address, if the above-mentioned condition is true. The condition itself is the result of comparing the R0 register value and the Threshold value. Note: All jump addresses are expressed in 32-bit words. 24.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register) 31 28 27 3’d8 17 16 15 25 24 1’b2 Step 7 0 Threshold Cond Figure 131: Instruction Type — JUMP Operand Description - see Figure 131 Step Relative shift from current position, expressed in 32-bit words: if Step[7] = 0, then PC = PC + Step[6:0] if Step[7] = 1, then PC = PC - Step[6:0] Threshold Threshold value for condition (see Cond below) to jump Cond Condition of jump: 1X - jump if Stage_cnt == Threshold 00 - jump if Stage_cnt < Threshold 01 - jump if Stage_cnt > Threshold Note: • A description of how to set the stage count register is provided in section 24.4.1.3. • All jump addresses are expressed in 32-bit words. Description The instruction prompts a jump to a relative address if the above-mentioned condition is true. The condition itself is the result of comparing the value of Stage_cnt (stage count register) and the Threshold value. 24.4.7 HALT – End the Program 31 28 0 3’d11 Figure 132: Instruction Type — HALT Description The instruction ends the operation of the processor and puts it into power-down mode. Note: After executing this instruction, the ULP co-processor timer gets started. Espressif Systems 476 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24.4.8 WAKE – Wake up the Chip 28 27 3’d9 25 0 1’b1 31 1’b0 Figure 133: Instruction Type — WAKE Description This instruction sends an interrupt from the ULP co-processor to the RTC controller. • If the SoC is in Deep-sleep mode, and the ULP wake-up is enabled, the above-mentioned interrupt will wake up the SoC. • If the SoC is not in Deep-sleep mode, and the ULP interrupt bit (RTC_CNTL_ULP_CP_INT_ENA) is set in register RTC_CNTL_INT_ENA_REG, a RTC interrupt will be triggered. 24.4.9 Sleep – Set the ULP Timer’s Wake-up Period 31 28 27 3’d9 25 3 0 sleep_reg 1’b1 Figure 134: Instruction Type — SLEEP Operand Description - see Figure 134 sleep_reg Selects one of five SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) as the wake-up period of the ULP co-processor Description The instruction selects which one of the SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) register values is to be used by the ULP timer as the wake-up period. By default, the value of SENS_ULP_CP_SLEEP_CYC0_REG is used. 24.4.10 WAIT – Wait for a Number of Cycles 31 15 28 0 Cycles 3’d4 Figure 135: Instruction Type — WAIT Operand Description - see Figure 135 Cycles the number of cycles to wait between sleeps Description The instruction will delay the ULP co-processor from getting into sleep for a certain number of Cycles. 24.4.11 TSENS – Take Measurements with the Temperature Sensor 31 15 28 2 Wait_Delay 3’d10 1 0 Rdst Figure 136: Instruction Type — TSENS Operand Description - see Figure 136 Rdst Destination Register R[0-3], results will be stored in this register. Wait_Delay Number of cycles needed to obtain a measurement Espressif Systems 477 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR Description Longer Wait_Delay can improve the accuracy of measurement. The instruction prompts a measurement to be taken with the use of the on-chip temperature sensor. The measurement result is stored into a general-purpose register. ADC – Take Measurement with ADC 31 28 6 Sel 24.4.12 3’d5 5 2 Sar Mux 1 0 Rdst Figure 137: Instruction Type — ADC Operand Description - see Figure 137 Rdst Destination Register R[0-3], results will be stored in this register. Sel Selected ADC : 0 = SAR ADC1, 1 = SAR ADC2, see Table 104. Sar Mux SARADC Pad [Sar_Mux - 1] is enabled, see Table 104. Table 104: Input Signals Measured using the ADC Instruction Pad Name/Signal/GPIO Sar_Mux SENSOR_VP (GPIO36) 1 SENSOR_CAPP (GPIO37) 2 SENSOR_CAPN (GPIO38) 3 SENSOR_VN (GPIO39) 4 32K_XP (GPIO33) 5 32K_XN (GPIO32) 6 VDET_1 (GPIO34) 7 VDET_2 (GPIO35) 8 Hall phase 1 9 Hall phase 0 10 GPIO4 1 GPIO0 2 GPIO2 3 MTDO (GPIO15) 4 MTCK (GPIO13) 5 MTDI (GPIO12) 6 MTMS (GPIO14) 7 GPIO27 8 GPIO25 9 GPIO26 10 Processed by /Sel SAR ADC1/Sel = 0 SAR ADC2/Sel = 1 Description The instruction prompts the taking of measurements with the use of ADC. Pads/signals available for ADC measurement are provided in Table 104. Espressif Systems 478 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR I2C_RD/I2C_WR – Read/Write I2C 31 28 27 25 R/W 24.4.13 3’d3 22 21 I2C Sel 19 18 High 16 15 Low 8 7 Data 0 Sub-addr Figure 138: Instruction Type — I2C Operand Description - see Figure 138 Sub-addr Slave register address Data Data to write in I2C_WR operation (not used in I2C_RD operation) Low High part of bit mask High Low part of bit mask I2C Sel Select register n of SENS_I2C_SLAVE_ADDRn (n: 0-7), which contains the I2C slave address. R/W I2C communication direction: 1 - I2C write 0 - I2C read Description Communicate (read/write) with external I2C slave devices. Details on using the RTC I2C peripheral are provided in section 24.6. Note: When working in master mode, RTC_I2C samples the SDA input on the negative edge of SCL. 24.4.14 REG_RD – Read from Peripheral Register 31 28 27 3’d2 23 22 High 18 9 Low 0 Addr Figure 139: Instruction Type — REG_RD Operand Description - see Figure 139 Addr Register address, expressed in 32-bit words High High part of R0 Low Low part of R0 Description The instruction prompts a read of up to 16 bits from a peripheral register into a general-purpose register: R0 = REG[Addr][High:Low] In case of more than 16 bits being requested, i.e. High - Low + 1 > 16, then the instruction will return [Low+15:Low]. Note: • This instruction can access registers in RTC_CNTL, RTC_IO, SENS and RTC_I2C peripherals. The address of the register, as seen from the ULP co-processor, can be calculated from the address of the same register on the DPORT bus, as follows: addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE)/4 Espressif Systems 479 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR • The addr_ulp is expressed in 32-bit words (not in bytes), and value 0 maps onto the DR_REG_RTCCNTL_BASE (as seen from the main CPUs). Thus, 10 bits of address cover a 4096-byte range of peripheral register space, including regions DR_REG_RTCCNTL_BASE, DR_REG_RTCIO_BASE, DR_REG_SENS_BASE and DR_REG_RTC_I2C_BASE. 24.4.15 REG_WR – Write to Peripheral Register 31 28 27 3’d2 23 22 High 18 17 10 Low 9 Data 0 Addr Figure 140: Instruction Type — REG_WR Operand Description - see Figure 140 Addr Register address, expressed in 32-bit words High High part of R0 Low Low part of R0 Data Value to write, 8 bits Description The instruction prompts the writing of up to 8 bits from a general-purpose register into a peripheral register. REG[Addr][High:Low] = Data If more than 8 bits are requested, i.e. High - Low + 1 > 8, then the instruction will pad with zeros the bits above the eighth bit. Note: See notes regarding addr_ulp in section 24.4.14 above. 24.5 ULP Program Execution The ULP co-processor is designed to operate independently of the main CPUs, while they are either in deep sleep or running. In a typical power-saving scenario, the ULP co-processor operates while the main CPUs are in deep sleep. To save power even further, the ULP co-processor can get into sleep mode, as well. In such a scenario, there is a specific hardware timer in place to wake up the ULP co-processor, since there is no software program running at the same time. This timer should be configured in advance by setting and then selecting one of the SENS_ULP_CP_SLEEP_CYCn_REG registers that contain the expiration period. This can be done either by the main program, or the ULP program with the REG_WR and SLEEP instructions. Then, the ULP timer should be enabled by setting bit RTC_CNTL_ULP_CP_SLP_TIMER_EN in the RTC_CNTL_STATE0_REG register. The ULP co-processor puts itself into sleep mode by executing the HALT instruction. This also triggers the ULP timer to start counting RTC_SLOW_CLK ticks which, by default, originate from an internal 150 kHz RC oscillator. Once the timer expires, the ULP co-processor is powered up and runs a program with the program counter (PC) which is stored in register SENS_PC_INIT. The relationship between the described signals and registers is shown in Figure 141. On reset or power-up the above-mentioned ULP program may start up only after the expiration of SENS_ULP_CP_SLEEP_CYC0_REG, which is the default selection period of the ULP timer. Espressif Systems 480 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR Figure 141: Control of ULP Program Execution A sample operation sequence of the ULP program is shown in Figure 142, where the following steps are executed: 1. Software enables the ULP timer by using bit RTC_CNTL_ULP_CP_SLP_TIMER_EN. 2. The ULP timer expires and the ULP co-processor starts running the program at PC = SENS_PC_INIT. 3. The ULP program executes the HALT instruction; the ULP co-processor is halted and the timer gets restarted. 4. The ULP program executes the SLEEP instruction to change the sleep timer period register. 5. The ULP program, or software, disables the ULP timer by using bit RTC_CNTL_ULP_CP_SLP_TIMER_EN. Espressif Systems 481 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR Figure 142: Sample of a ULP Operation Sequence 24.6 RTC_I2C Controller The ULP co-processor can use a separate I2C controller, located in the RTC domain, to communicate with external I2C slave devices. RTC_I2C has a limited feature set, compared to I2C0/I2C1 peripherals. 24.6.1 Configuring RTC_I2C Before the ULP co-processor can use the I2C instruction, certain parameters of the RTC_I2C need to be configured. This can be done by the program running on one of the main CPUs, or by the ULP co-processor itself. Configuration is performed by writing certain timing parameters into the RTC_I2C registers: 1. Set the low and high SCL half-periods by using RTC_I2C_SCL_LOW_PERIOD_REG and RTC_I2C_SCL_HIGH_PERIOD_REG in RTC_FAST_CLK cycles (e.g. RTC_I2C_SCL_LOW_PERIOD=40, RTC_I2C_SCL_HIGH_PERIOD=40 for 100 kHz frequency). 2. Set the number of cycles between the SDA switch and the falling edge of SCL by using RTC_I2C_SDA_DUTY_REG in RTC_FAST_CLK (e.g. RTC_I2C_SDA_DUTY=16). 3. Set the waiting time after the START condition by using RTC_I2C_SCL_START_PERIOD_REG (e.g. RTC_I2C_SCL_START_PERIOD=30). 4. Set the waiting time before the END condition by using RTC_I2C_SCL_STOP_PERIOD_REG (e.g. RTC_I2C_SCL_STOP_PERIOD=44). 5. Set the transaction timeout by using RTC_I2C_TIMEOUT_REG (e.g. RTC_I2C_TIMEOUT=200). 6. Enable the master mode (set the RTC_I2C_MS_MODE bit in RTC_I2C_CTRL_REG). 7. Write the address(es) of external slave(s) to SENS_I2C_SLAVE_ADDRn (n: 0-7). Up to eight slave addresses can be pre-programmed this way. One of these addresses can then be selected for each transaction as part of the ULP I2C instruction. Once RTC_I2C is configured, instructions ULP I2C_RD and I2C_WR can be used. 24.6.2 Using RTC_I2C The ULP co-processor supports two instructions (with a single OpCode) for using RTC_I2C: I2C_RD (read) and I2C_WR (write). Espressif Systems 482 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24.6.2.1 I2C_RD - Read a Single Byte The I2C_RD instruction performs the following I2C transaction (see Figure 143): 1. Master generates a START condition. 2. Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_RD instruction. 3. Slave generates ACK. 4. Master sends slave register address (given as an argument to the I2C_RD instruction). 5. Slave generates ACK. 6. Master generates a repeated START condition. 7. Master sends slave address, with r/w bit set to 1 (“read”). 8. Slave sends one byte of data. 9. Master generates NACK. Slave 8 9 10 NACK Reg Address 7 Slave Address R STOP 5 6 4 RSTRT Slave Address W 3 ACK 2 ACK Master 1 START 10. Master generates a STOP condition. Data Figure 143: I2C Read Operation Note: The RTC_I2C peripheral samples the SDA signals on the falling edge of SCL. If the slave changes SDA in less than 0.38 microseconds, the master will receive incorrect data. The byte received from the slave is stored into the R0 register. 24.6.2.2 I2C_WR - Write a Single Byte The I2C_WR instruction performs the following I2C transaction (see Figure 144): 1. Master generates a START condition. 2. Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_WR instruction. 3. Slave generates ACK. 4. Master sends slave register address (given as an argument to the I2C_WR instruction). 5. Slave generates ACK. 6. Master generates a repeated START condition. 7. Master sends slave address, with r/w bit set to 0 (“write”). 8. Master sends one byte of data. 9. Slave generates ACK. Espressif Systems 483 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 8 Slave Address W Data 9 10 STOP Reg Address 7 ACK Slave 5 6 4 RSTRT Slave Address W 3 ACK 2 ACK Master 1 START 10. Master generates a STOP condition. Figure 144: I2C Write Operation 24.6.2.3 Detecting Error Conditions ULP I2C_RD and I2C_WR instructions will not report error conditions, such as a NACK from a slave, via ULP registers. Instead, applications can query specific bits in the RTC_I2C_INT_ST_REG register to determine if the transaction was successful. To enable checking for specific communication events, their corresponding bits should be set in register RTC_I2C_INT_EN_REG. Note that the bit map is shifted by 1. If a specific communication event is detected and set in register RTC_I2C_INT_ST_REG, it can then be cleared using RTC_I2C_INT_CLR_REG. 24.6.2.4 Connecting I2C Signals SDA and SCL signals can be mapped onto two out of the four GPIO pins, which are identified in the ESP32 pin lists in ESP32 Datasheet, using the RTCIO_SAR_I2C_IO_REG register. 24.7 Register Summary 24.7.1 SENS_ULP Address Space Name Description Address Access SENS_ULP_CP_SLEEP_CYC0_REG Timer cycles setting 0 0x3FF48818 R/W SENS_ULP_CP_SLEEP_CYC1_REG Timer cycles setting 1 0x3FF4881C R/W SENS_ULP_CP_SLEEP_CYC2_REG Timer cycles setting 2 0x3FF48820 R/W SENS_ULP_CP_SLEEP_CYC3_REG Timer cycles setting 3 0x3FF48824 R/W SENS_ULP_CP_SLEEP_CYC4_REG Timer cycles setting 4 0x3FF48828 R/W SENS_SAR_SLAVE_ADDR1_REG I2C addresses 0 and 1 0x3FF4883C R/W SENS_SAR_SLAVE_ADDR2_REG I2C addresses 2 and 4 0x3FF48840 R/W SENS_SAR_SLAVE_ADDR3_REG I2C addresses 4 and 5 0x3FF48844 R/W SENS_SAR_SLAVE_ADDR4_REG I2C addresses 6 and 7, I2C control 0x3FF48848 R/W I2C control registers 0x3FF48850 R/W Description Address Access ULP Timer cycles select RTC I2C slave address select RTC I2C control SENS_SAR_I2C_CTRL_REG 24.7.2 RTC_I2C Address Space Name RTC I2C control registers Espressif Systems 484 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR RTC_I2C_CTRL_REG Transmission setting 0x3FF48C04 R/W RTC_I2C_DEBUG_STATUS_REG Debug status 0x3FF48C08 R/W RTC_I2C_TIMEOUT_REG Timeout setting 0x3FF48C0C R/W RTC_I2C_SLAVE_ADDR_REG Local slave address setting 0x3FF48C10 R/W Configures the SDA hold time after a nega- 0x3FF48C30 R/W RTC I2C signal setting registers RTC_I2C_SDA_DUTY_REG tive SCL edge RTC_I2C_SCL_LOW_PERIOD_REG Configures the low level width of SCL 0x3FF48C00 R/W RTC_I2C_SCL_HIGH_PERIOD_REG Configures the high level width of SCL 0x3FF48C38 R/W Configures the delay between the SDA and 0x3FF48C40 R/W 0x3FF48C44 R/W Clear status of I2C communication events 0x3FF48C24 R/W Enable capture of I2C communication sta- 0x3FF48C28 R/W 0x3FF48C2C R/O RTC_I2C_SCL_START_PERIOD_REG RTC_I2C_SCL_STOP_PERIOD_REG SCL negative edge for a start condition Configures the delay between the SDA and SCL positive edge for a stop condition RTC I2C interrupt registers - listed only for debugging RTC_I2C_INT_CLR_REG RTC_I2C_INT_EN_REG RTC_I2C_INT_ST_REG tus events Status of captured I2C communication events Note: Interrupts from RTC_I2C are not connected. The interrupt registers above are listed only for debugging purposes. Espressif Systems 485 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR 24.8 Registers 24.8.1 SENS_ULP Address Space Register 24.1: SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) (0x18+0x4*n) 31 0 20 Reset SENS_ULP_CP_SLEEP_CYCn_REG ULP timer cycles setting n; the ULP co-processor can select one of such registers by using the SLEEP instruction. (R/W) (re SE se NS rv e _P d) C_ IN IT (re se SE rve N d) SE S_U NS LP _U _C LP P_ _C ST P_ AR FO T_ RC TO E_ P (re ST se AR rv T_ ed TO ) P Register 24.2: SENS_SAR_START_FORCE_REG (0x002c) 31 0 22 0 0 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 15 0 0 0 0 0 8 0 0 0 0 0 0 0 Reset SENS_PC_INIT ULP PC entry address. (R/W) SENS_ULP_CP_START_TOP Set this bit to start the ULP co-processor; it is active only when SENS_ULP_CP_FORCE_START_TOP = 1. (R/W) SENS_ULP_CP_FORCE_START_TOP 1: ULP co-processor is started by SENS_ULP_CP_START_TOP; 0: ULP co-processor is started by timer. (R/W) 0 0 0 0 0 _I NS NS 0 0 0 SE SE 22 0 2C 2C _I (re se rv ed ) 31 0 _S _S LA VE _A DD LA VE _A DD R R1 0 Register 24.3: SENS_SAR_SLAVE_ADDR1_REG (0x003c) 21 11 0x000 10 0 0x000 Reset SENS_I2C_SLAVE_ADDR0 I2C slave address 0. (R/W) SENS_I2C_SLAVE_ADDR1 I2C slave address 1. (R/W) Espressif Systems 486 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR NS SE 22 0 0 0 0 SE NS _I 2 _I 2C d) ve er (re s 31 0 C_ S _S L AV E LA VE _A DD _A DD R2 R3 Register 24.4: SENS_SAR_SLAVE_ADDR2_REG (0x0040) 0 0 0 0 21 0 11 10 0x000 0 0x000 Reset SENS_I2C_SLAVE_ADDR2 I2C slave address 2. (R/W) SENS_I2C_SLAVE_ADDR3 I2C slave address 3. (R/W) 0 0 0 0 C_ S_ I2 SE N NS SE 22 0 SL C_ SL _I 2 ve d) (re se r 31 0 AV E AV E _A _A DD DD R5 R4 Register 24.5: SENS_SAR_SLAVE_ADDR3_REG (0x0044) 0 0 0 21 0 11 10 0x000 0 0x000 Reset SENS_I2C_SLAVE_ADDR4 I2C slave address 4. (R/W) SENS_I2C_SLAVE_ADDR5 I2C slave address 5. (R/W) 30 0 0 29 _A _A 22 LA VE _S 2C _I NS SE SE SE NS NS _I _I 2 2C C_ _R SL AV E DA TA NE O (re se SE rve NS d) _I 2C _D 31 DD DD R7 R6 Register 24.6: SENS_SAR_SLAVE_ADDR4_REG (0x0048) 21 0x000 11 0x000 10 0 0x000 Reset SENS_I2C_DONE Indicate I2C done. (RO) SENS_I2C_RDATA I2C read data. (RO) SENS_I2C_SLAVE_ADDR6 I2C slave address 6. (R/W) SENS_I2C_SLAVE_ADDR7 I2C slave address 7. (R/W) Espressif Systems 487 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR SE SE (re se rv NS _ SA R_ I2 C_ CT RL ed ) NS SE _S NS AR _S _I AR 2C _I _ST 2C A _S RT TA _F RT OR C E Register 24.7: SENS_SAR_I2C_CTRL_REG (0x0050) 31 30 29 28 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset SENS_SAR_I2C_START_FORCE 1: I2C started by SW, 0: I2C started by FSM. (R/W) SENS_SAR_I2C_START Start I2C; active only when SENS_SAR_I2C_START_FORCE = 1. (R/W) SENS_SAR_I2C_CTRL I2C control data; active only when SENS_SAR_I2C_START_FORCE = 1. (R/W) 24.8.2 RTC_I2C Address Space RT C_ I2 C (re se rv ed ) _S CL _L O W _P ER IO D Register 24.8: RTC_I2C_SCL_LOW_PERIOD_REG (0x000) 31 0 19 0 0 0 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SCL_LOW_PERIOD Number of FAST_CLK cycles when SCL == 0. (R/W) Espressif Systems 488 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR RT (re s er ve d) C RT _I2 C C_ RT _I2 RX C C_ _L RT _I2 TX_ SB_ C_ C_ LS FI I2 TR B RS (re C_ AN _FIR T M S se S _S ST rv ed _M TA O R RT ) DE T C RT _I2 C C_ _ I2 SC C_ L_ SD FO A_ RC FO E RC _OU E_ T O UT Register 24.9: RTC_I2C_CTRL_REG (0x004) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_RX_LSB_FIRST Send LSB first. (R/W) RTC_I2C_TX_LSB_FIRST Receive LSB first. (R/W) RTC_I2C_TRANS_START Force to generate a start condition. (R/W) RTC_I2C_MS_MODE Master (1), or slave (0). (R/W) RTC_I2C_SCL_FORCE_OUT SCL is push-pull (1) or open-drain (0). (R/W) RTC_I2C_SDA_FORCE_OUT SDA is push-pull (1) or open-drain (0). (R/W) ST AT E N_ AI d) _M rv e I2 C 27 0 0 25 0 RT se (re RT 28 0 C_ I2 C_ SC L_ ST AT E 0 C_ ) 30 0 RT rv ed (re se 31 C RT _I2 C C_ RT _I2 BY C C_ TE RT _I2 SL _TR C C_ AV A RT _I2 BU E_A NS C C_ S_ D RT _I2 AR BU DR C C_ B_ SY _M AT RT _I2 TIM LO CH C_ C_ ED ST S I2 L _O C_ AV U AC E_ T K_ RW VA L Register 24.10: RTC_I2C_DEBUG_STATUS_REG (0x008) 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SCL_STATE State of SCL machine. (R/W) RTC_I2C_MAIN_STATE State of the main machine. (R/W) RTC_I2C_BYTE_TRANS 8-bit transmit done. (R/W) RTC_I2C_SLAVE_ADDR_MATCH Indicates whether the addresses are matched, when in slave mode. (R/W) RTC_I2C_BUS_BUSY Operation is in progress. (R/W) RTC_I2C_ARB_LOST Indicates the loss of I2C bus control, when in master mode. (R/W) RTC_I2C_TIMED_OUT Transfer has timed out. (R/W) RTC_I2C_SLAVE_RW Indicates the value of the received R/W bit, when in slave mode. (R/W) RTC_I2C_ACK_VAL The value of ACK signal on the bus. (R/W) Espressif Systems 489 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR (re RT se rv ed ) C_ I2 C_ T IM EO UT Register 24.11: RTC_I2C_TIMEOUT_REG (0x00c) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_TIMEOUT Maximum number of FAST_CLK cycles that the transmission can take. (R/W) 30 0 0 _S C_ rv RT (re se RT 31 I2 C ed ) C_ I2 C_ SL LA VE AV E _A _A D DD R DR _1 0 BI T Register 24.12: RTC_I2C_SLAVE_ADDR_REG (0x010) 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SLAVE_ADDR_10BIT Set if local slave address is 10-bit. (R/W) RTC_I2C_SLAVE_ADDR Local slave address. (R/W) Espressif Systems 490 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR (re se rv ed ) RT C RT _I2 C_ C_ RT I2 TIM C C_ E RT _I2 TR _OU C C_ AN T RT _I2 MA S_ _IN C_ C_ ST CO T_C I2 AR ER MP LR C_ B _ SL ITR TR LET AV AT AN E_ (re E_ IO S_ INT se TR N_ CO _C rv ed AN LO M LR ) S_ ST PLE CO _IN T E M T_C _IN PL L T ET R _C LR E_ IN T_ CL R Register 24.13: RTC_I2C_INT_CLR_REG (0x024) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 7 0 0 0 0 0 0 0 4 0 0 0 Reset RTC_I2C_TIME_OUT_INT_CLR Clear interrupt upon timeout. (R/W) RTC_I2C_TRANS_COMPLETE_INT_CLR Clear interrupt upon detecting a stop pattern. (R/W) RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR Clear interrupt upon completion of transaction, when in master mode. (R/W) RTC_I2C_ARBITRATION_LOST_INT_CLR Clear interrupt upon losing control of the bus, when in master mode. (R/W) RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR Clear interrupt upon completion of transaction, when in slave mode. (R/W) Espressif Systems 491 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR RT (re se rv ed ) C RT _I2 C C_ RT _I2 TIM C C_ E RT _I2 TR _OU C C_ AN T RT _I2 MA S_ _IN C_ C_ ST CO T_E I2 AR ER MP N A C_ B _ SL ITR TR LET AN E A A (re VE TIO _ _IN se _T N CO T_ rv RA _L M EN ed N_ OS P_ A ) CO T_ INT M INT _EN P_ _E A IN NA T_ EN A Register 24.14: RTC_I2C_INT_EN_REG (0x028) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 7 4 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_TIME_OUT_INT_ENA Enable interrupt upon timeout. (R/W) RTC_I2C_TRANS_COMPLETE_INT_ENA Enable interrupt upon detecting a stop pattern. (R/W) RTC_I2C_MASTER_TRAN_COMP_INT_ENA Enable interrupt upon completion of transaction, when in master mode. (R/W) RTC_I2C_ARBITRATION_LOST_INT_ENA Enable interrupt upon losing control of the bus, when in master mode. (R/W) RTC_I2C_SLAVE_TRAN_COMP_INT_ENA Enable interrupt upon completion of transaction, when in slave mode. (R/W) 31 0 0 0 0 0 0 0 0 0 0 0 0 0 RT I2 C C_ RT _I2 TIM C C_ E RT _I2 TR _OU C C_ AN T RT _I2 MA S_ _IN C_ C_ ST CO T_S I2 AR ER MP T C_ B _ SL ITR TR LET (re AV AT AN E_ se E_ IO _C INT rv ed TR N_ OM _S ) AN LO P T _C ST _IN O _IN T_ M T ST P_ _S IN T T_ ST (re RT C_ se rv e d) Register 24.15: RTC_I2C_INT_ST_REG (0x02c) 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 5 0 0 0 0 0 0 0 3 0 0 Reset RTC_I2C_TIME_OUT_INT_ST Detected timeout. (R/O) RTC_I2C_TRANS_COMPLETE_INT_ST Detected stop pattern on I2C bus. (R/O) RTC_I2C_MASTER_TRAN_COMP_INT_ST Transaction completed, when in master mode. (R/O) RTC_I2C_ARBITRATION_LOST_INT_ST Bus control lost, when in master mode. (R/O) RTC_I2C_SLAVE_TRAN_COMP_INT_ST Transaction completed, when in slave mode. (R/O) Espressif Systems 492 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR RT (re s er ve d) C_ I2 C_ S DA _D UT Y Register 24.16: RTC_I2C_SDA_DUTY_REG (0x030) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SDA_DUTY Number of FAST_CLK cycles between the SDA switch and the falling edge of SCL. (R/W) RT (re se C_ I2 C rv ed ) _S CL _H IG H_ PE RI O D Register 24.17: RTC_I2C_SCL_HIGH_PERIOD_REG (0x038) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SCL_HIGH_PERIOD Number of FAST_CLK cycles when SCL == 1. (R/W) (re RT C_ I2 se rv e d) C_ SC L_ ST AR T_ PE RI O D Register 24.18: RTC_I2C_SCL_START_PERIOD_REG (0x040) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SCL_START_PERIOD Number of FAST_CLK cycles to wait before generating a start condition. (R/W) Espressif Systems 493 ESP32 Technical Reference Manual V2.0 24. ULP CO-PROCESSOR RT (re s er C_ I ve d) 2C _S CL _S TO P_ PE RI O D Register 24.19: RTC_I2C_SCL_STOP_PERIOD_REG (0x044) 31 0 20 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset RTC_I2C_SCL_STOP_PERIOD Number of FAST_CLK cycles to wait before generating a stop condition. (R/W) Espressif Systems 494 ESP32 Technical Reference Manual V2.0
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