Implementing The Design I CEcube201708User Guide

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iCEcube2 User Guide
August 2017
iCEcube2 User Guide www.latticesemi.com 2
Copyright
Copyright © 2017 Lattice Semiconductor Corporation. All rights reserved. This document may
not, in whole or part, be reproduced, modified, distributed, or publicly displayed without prior
written consent from Lattice Semiconductor Corporation (“Lattice”).
Trademarks
All Lattice trademarks are as listed at www.latticesemi.com/legal. Synopsys and Synplify Pro are
trademarks of Synopsys, Inc. Aldec and Active-HDL are trademarks of Aldec, Inc. All other
trademarks are the property of their respective owners.
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WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING
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assumes no obligation to correct any errors contained herein or to advise any user of this
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Contact Information
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon 97124-6421
United States of America
Tel: +1 503 268 8000
Fax: +1 503 268 8347
http://www.latticesemi.com.
iCEcube2 User Guide www.latticesemi.com 3
TABLE OF CONTENTS
Preface ............................................................................................. 7
About this Document ................................................................................................................... 7
Software Version ......................................................................................................................... 7
Platform Requirements................................................................................................................ 7
Programming Hardware .............................................................................................................. 7
Programming Software................................................................................................................ 8
Chapter 1 Overview ......................................................................... 9
iCEcube2 Tool Suite.................................................................................................................... 9
Design Flow ............................................................................................................................... 10
Chapter 2 Quick Start Guide ......................................................... 11
Creating a Project ...................................................................................................................... 11
Synthesizing the Design ............................................................................................................ 15
Programming the Device ........................................................................................................... 25
Addendum: ................................................................................................................................ 29
Importing Physical Constraints from iCEcube to iCEcube2 .................................................. 29
Chapter 3 iCEcube2 Project Setup and Navigation .................... 34
Introduction ................................................................................................................................ 34
Project Manager GUI................................................................................................................. 34
Adding/Deleting Design and Constraint Files ........................................................................... 34
Selecting Synthesis Tool and Setting synthesis Options .......................................................... 36
Selecting the Target Device and Operating Conditions ............................................................ 39
Output Window .......................................................................................................................... 40
Simulation Wizard ..................................................................................................................... 40
PLL Module Generator .............................................................................................................. 41
PLL Dynamic Reconfiguration ................................................................................................... 50
SPI/I2C Module Generator ........................................................................................................ 52
Chapter 4 Lattice Synthesis Engine ............................................. 60
Changing the LSE Tool Options ................................................................................................ 60
BRAM Utilization ................................................................................................................... 60
Carry Chain Length ............................................................................................................... 60
Command Line Options ........................................................................................................ 60
Fix Gated Clocks ................................................................................................................... 60
FSM Encoding Style ............................................................................................................. 61
Intermediate File Dump ......................................................................................................... 61
Max Fanout Limit .................................................................................................................. 61
Memory Initial Value File Search Path .................................................................................. 61
Number of Critical Paths ....................................................................................................... 61
Optimization Goal ................................................................................................................. 61
Propagate Constants ............................................................................................................ 61
RAM Style ............................................................................................................................. 61
Remove Duplicate Registers ................................................................................................ 62
Resolve Mixed Drivers .......................................................................................................... 62
Resource Sharing ................................................................................................................. 62
ROM Style ............................................................................................................................. 62
RW Check on RAM ............................................................................................................... 62
Target Frequency .................................................................................................................. 63
Top-Level Unit ....................................................................................................................... 63
Use Carry Chain ................................................................................................................... 63
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Use IO Insertion .................................................................................................................... 63
Use IO Registers ................................................................................................................... 63
Optimizing LSE for Area and Speed ......................................................................................... 63
FSM Encoding Style ............................................................................................................. 64
Max Fanout Limit .................................................................................................................. 64
Optimization Goal ................................................................................................................. 64
Remove Duplicate Registers ................................................................................................ 64
Resource Sharing ................................................................................................................. 65
Target Frequency .................................................................................................................. 65
LSE Options versus Synplify Pro .............................................................................................. 65
Coding Tips for LSE .................................................................................................................. 66
LSE Differences with Synplify Pro ........................................................................................ 66
About Inferring Memory ........................................................................................................ 67
Inferring RAM ...................................................................................................................... 68
Inferring RAM with Synchronous Read .............................................................................. 69
Inferring Pseudo Dual-Port RAM ........................................................................................ 71
Initializing Inferred RAM ..................................................................................................... 73
Inferring ROM ..................................................................................................................... 74
About Verilog Blocking Assignments .................................................................................... 75
Inferring DSP Multipliers ....................................................................................................... 76
Verilog Examples ................................................................................................................ 76
VHDL Examples ................................................................................................................. 78
Inferring I/O ........................................................................................................................... 80
Event Inside an Event ........................................................................................................... 81
HDL Attributes and Directives ................................................................................................... 82
black_box_pad_pin ............................................................................................................... 82
syn_black_box ...................................................................................................................... 83
syn_encoding ........................................................................................................................ 83
syn_hier................................................................................................................................. 84
syn_keep ............................................................................................................................... 85
syn_maxfan ........................................................................................................................... 86
syn_multstyle ........................................................................................................................ 87
syn_noprune ......................................................................................................................... 88
syn_pipeline .......................................................................................................................... 89
syn_preserve ........................................................................................................................ 90
syn_ramstyle ......................................................................................................................... 91
syn_romstyle ......................................................................................................................... 92
syn_use_carry_chain ............................................................................................................ 93
syn_useioff ............................................................................................................................ 94
Synthesis Macro ................................................................................................................... 95
translate_off/translate_on ..................................................................................................... 95
Synopsys Design Constraints (SDC) ........................................................................................ 96
create_clock .......................................................................................................................... 96
set_false_path ....................................................................................................................... 97
set_input_delay ..................................................................................................................... 98
set_max_delay ...................................................................................................................... 98
set_multicycle_path .............................................................................................................. 99
set_output_delay ................................................................................................................... 99
Chapter 5 iCEcube2 Physical Implementation Tools ............... 100
Overview ................................................................................................................................. 100
Tools for Physical Implementation .......................................................................................... 100
Placing and Routing the Design .............................................................................................. 101
Floor Planner ........................................................................................................................... 102
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Package View .......................................................................................................................... 109
Pin Constraints Editor.............................................................................................................. 111
Power Estimator ...................................................................................................................... 112
Generating a Bitmap ............................................................................................................... 114
Programming the Device ......................................................................................................... 116
Diamond Programmer ......................................................................................................... 116
Memory Initializer .................................................................................................................... 118
Memory initialization file Format (.mem) : ........................................................................... 120
Simulating the Routed Design ................................................................................................. 121
Chapter 6 Timing Constraints and Static Timing Analysis ...... 122
Overview ................................................................................................................................. 122
Specifying Constraints Using the Timing Constraints Editor (TCE) ........................................ 122
SDC Constraints in TCE ..................................................................................................... 124
Clock Constraints ................................................................................................................ 124
Generated Clock Constraints .............................................................................................. 124
Source Clock Latency Constraints ...................................................................................... 125
Input Delay Constraints ....................................................................................................... 125
Output Delay Constraints .................................................................................................... 126
Max Delay Constraints ........................................................................................................ 126
False Path Exceptions ........................................................................................................ 127
Multi Cycle Path Exceptions ............................................................................................... 128
Analyzing Reports Generated by the Static Timing Analyzer (STA) ....................................... 129
Clock Summary Pane ......................................................................................................... 129
Clock Relationship Summary .............................................................................................. 133
Data Sheet .......................................................................................................................... 133
Analyzing Constrained Paths .............................................................................................. 135
By Slack ............................................................................................................................ 135
By Paths ........................................................................................................................... 137
Point to Point .................................................................................................................... 139
Other Features .................................................................................................................... 140
Detailed Timing Report............................................................................................................ 142
Chapter 7 Physical Constraints in iCEcube2 ............................ 146
Specifying Physical Constraints after Design Import and Before Placement ......................... 147
Absolute Placement ............................................................................................................ 147
Constraining Logic or RAMs ............................................................................................. 147
Constraining IOs ............................................................................................................... 147
Constraining SPI Configuration IOs .................................................................................. 148
Relative Placement ............................................................................................................. 148
Region Constraints ............................................................................................................. 152
IO/FF Merge ........................................................................................................................ 153
Global Buffer Promotion/Demotion ..................................................................................... 155
Modifying the Device Floor Plan after Placement ................................................................... 157
Chapter 8 Generating/Integrating Fixed Placement IP Blocks . 160
IP Generation Flow .................................................................................................................. 160
System Design Flow................................................................................................................ 164
Chapter 9 Hierarchical Project Flow .......................................... 169
Create Top Level Project ........................................................................................................ 169
Create Sub-Projects for IP blocks ........................................................................................... 173
Synthesize Top Level Project .................................................................................................. 175
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Chapter 10 Simulating Design with ALDEC Active-HDL .......... 178
ALDEC Active-HDL ................................................................................................................. 178
Pre-Compiled iCE Simulation Libraries ................................................................................... 178
VHDL ................................................................................................................................ 179
VERILOG .......................................................................................................................... 179
Design ..................................................................................................................................... 180
Pre-Synthesis Simulation ........................................................................................................ 181
Post Place-n-Route Functional Simulation (Verilog/VHDL) .................................................... 188
Post Place-n-Route Timing Simulation (Verilog/VHDL) .......................................................... 190
Chapter 11 iCEcube2 Command Line Interface ........................ 196
Overview ................................................................................................................................. 196
Running LSE in batch mode ................................................................................................... 196
Running Synplify-pro in batch mode ....................................................................................... 197
Running iCEcube2 Backend tools in batch mode ................................................................... 199
Backend tool Options .......................................................................................................... 200
Edif Parser ........................................................................................................................ 200
Placer ................................................................................................................................ 200
Router ............................................................................................................................... 201
Bitmap ............................................................................................................................... 201
Command Line Execution ....................................................................................................... 201
Chapter 12 High Drive IO with configurable drive strengths ... 204
Chapter 13 Open Drain LED IO ................................................... 206
Appendix A: PCF Syntax ............................................................ 207
iCEcube2 User Guide www.latticesemi.com 7
Preface
About this Document
The iCEcube2 User Guide provides iCE FPGA designers with an overview of the software tools
and the design process using iCEcube2. This document covers the iCEcube2 tools for Project
Setup, Navigation, Synthesis and Physical Implementation on the iCE FGPA device.
For information on the Synopsys Synplify Pro software, please refer to the Synplify Pro
documentation provided in the synpbase/doc directory in the iCEcube2 software installation
(<icecube2_install_dir>/synpbase/doc), and on the Lattice website.
For information on the Aldec Active-HDL design tool, please refer to the Active-HDL
documentations available at <icecube2_install_dir>/Aldec/Active-HDL/BOOKS.
Software Version
This User Guide documents the features of iCEcube2 Software Version 2017.08.
For more information about acquiring the iCEcube2 software, please visit the Lattice
Semiconductor website: http://www.latticesemi.com.
Platform Requirements
The iCEcube2 software can be installed on a platform satisfying the following minimum
requirements.
A Pentium 4 computer (500 MHz) with 256 MB of RAM, 256MB of Virtual Memory, and running
one of the following Operating Systems :
Windows 10 OS, 32-bit / 64-bit
Windows 8/8.1 OS, 32-bit / 64-bit
Windows 7 OS, 32-bit / 64-bit
Windows XP Professional
Red Hat Enterprise Linux WS v4, 5, and 6
Programming Hardware
Here are the following ways to program iCE FPGA devices:
A third party programmer or a processor, using the programming files generated by the
iCEcube2 Physical Implementation Tools. Consult the third party programmer user
manual for instructions.
The iCEblink and iCEman evaluation Board, which not only serves as a vehicle to
evaluate iCE FPGAs, but also includes an integrated device programmer. This
programmer can be used to program devices on the evaluation board, or it can be used
to program devices in a target system. Please visit Lattice Semiconductor website:
http://www.latticesemi.com for additional information on the Evaluation Boards.
Digilent USB cables to program the external SPI Flash.
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The iCE Programming hardware: iCEcable, iCEprog (Programmer base module) and
iCEsab (socket adaptor). Refer to lattice website: http://www.latticesemi.com for more
details on programming hardware.
Programming Software
Standalone Lattice Diamond Programmer software is required to program iCE40 FPGA devices
or SPI flash. Download and install the latest standalone programmer from
http://www.latticesemi.com/ispvm.
For more information about Diamond Programmer, refer “Diamond Programmer” on page 116.
iCEcube2 User Guide www.latticesemi.com 9
Chapter 1 Overview
iCEcube2 Tool Suite
The iCEcube2 Tool Suite is comprised of several integrated components, running under either
the Microsoft Windows or the Red Hat Linux environments. Please refer to Platform
Requirements for additional information on supported operating systems.
The Figure 1-1 below depicts the design flow using the iCEcube2 Tool Suite. The components in
blue signify functionality supported by Lattice Semiconductor’s proprietary Synthesis Engine
(LSE) and iCEcube2 place and route software, and the components in purple indicate the
functionality supported by Synopsys’ Synplify Pro synthesis tools and the Aldec Active-HDL
simulation tool. The iCEcube2 software, Synopsys Synplify Pro and the Aldec Active-HDL
software constitutes the iCEcube2 Tool Suite.
Note: The Aldec Active-HDL tool is available only in Windows environments.
Figure 1-1: The iCEcube2 Design Flow
iCEcube2 User Guide www.latticesemi.com 10
Design Flow
The following steps provide an overview of the design flow using the iCEcube2 Tool Suite.
1. Create a new project in the iCEcube2 Project Navigator and specify a target device and its
operating conditions. Add your HDL (Verilog or VHDL) design files and your Constraint files
to the project.
2. iCEcube2 software supports Synplify-Pro Synthesis tool and Lattice Synthesis (LSE) tool.
Synplify-pro is the default synthesis tool in iCEcube2. Synthesis your design using the
selected synthesis tool.
3. Perform Placement and Routing using the iCEcube2 place and route tools. iCEcube2 also
supports physical implementation tools such as floor planning, allowing users to manually
place logic cells and IOs.
4. Perform timing simulation of your design using the Aldec Active-HDL simulation tool or any
industry-standard HDL simulation tool. The files necessary for simulation are automatically
generated by the iCEcube2 Physical Implementation tools, after the routing phase.
5. Perform Static Timing Analysis using the iCEcube2 static timing analyzer.
6. Generate the device programming and configuration files from the iCEcube2 Physical
Implementation tools.
7. Program your device using the device programming hardware provided by Lattice.
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Chapter 2 Quick Start Guide
This chapter provides a brief introduction to the iCEcube2 design flow. The goal of this chapter is
to familiarize the user with the fundamental steps needed to create a design project, synthesize
and implement the design, generate the necessary device configuration files, and program the
target device.
Detailed information on tool features and usage is provided in subsequent chapters.
Creating a Project
Starting the iCEcube2 software for the first time, you will see the following interface shown in
Figure 2-1.
Figure 2-1 : Create a New Project
The first step is to create a new design project and add the appropriate design files to your
project. You can create a new project by either selecting File > New Project from the iCEcube2
menu, or by clicking the Create a New Project icon as seen in Figure 2-1. The New Project
Wizard GUI is displayed in Figure 2-2.
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Figure 2-2: New Project Setup Wizard for iCE40 Family
This example is targeted for iCE40 family device. Follow the following steps to setup the project
properties.
1. Project Name Field: Specify a project name (quick_start) in the Project Name field.
2. Project Directory Field: Specify any directory where you want to place the project directory
in the Project Directory field.
3. Device Family Fields: This section allows you to specify the Lattice iCE device family you
are targeting. For this example, change the Device Family to iCE40.
4. Device Fields: This section allows you to specify the Lattice device and package you are
targeting. For this example, change the Device to HX1K and change the device package to
the VQ100.
5. Operating Condition Fields: This section allows you to specify the operating conditions of
the device which will be used for timing and power analysis.
iCEcube2 User Guide www.latticesemi.com 13
6. Start From Synthesis: This option allows you to start the flow from Synthesis. For current
example, select this option.
7. Start From BackEnd: This option allows you to start from Post Synthesis flow.
After the above selections the New Project GUI Wizard has the following settings as shown in
Figure 2-3.
`
Figure 2-3: Tutorial Project Settings
8. Click Next to go to the Add Files dialog box shown in Figure 2-4. You will be prompted to
create a new project directory. Click Yes.
9. In the Add Files dialog box, navigate to: <iCEcube2 installation directory>/examples/blinky
Highlight the following files:
blinky.vhd
blinky_syn.sdc*
iCEcube2 User Guide www.latticesemi.com 14
Select each file and click >> to add the selected file, or click >>> to add all the files in the
open directory (files can be removed using << and <<<) to your project. Click Finish to create
the project.
* The SDC file is a Synopsys constraint file, which contains timing constraint information.
Figure 2-4: Add Files Dialog Box
After successfully setting up your project, you will return to the iCEcube2 Project Navigator
screen shown in Figure 2-5.
iCEcube2 User Guide www.latticesemi.com 15
Figure 2-5: iCECube2 Project Navigator View after Completing Project Setup
Synthesizing the Design
After a successful project setup, select a synthesis tool:
1. In the iCEcube2 window, right-click Synthesis Tool and choose Select Synthesis Tools.
The Select Synthesis Tool dialog box opens.
2. Select a tool: Synplify Pro or Lattice LSE.
3. Click OK.
The Run <Tool> Synthesis command changes to show the selected tool.
For this tutorial, select Lattice LSE.
Next, set options for the synthesis tool. Select Tool > Tool Options. In the Tool Options dialog
box, click the tab of the tool. To change the value of an option, either click in its Value cell and
start typing to replace the value or double-click to edit the value or to see a menu of values. In the
Synplify Pro tab, click on the word “here” to open Synplify Pro. Then, in the Synplify Pro window,
click Implementation Options.
For now, do not change any option settings. Click Cancel.
Double-click Run Lattice LSE Synthesis in the project navigator window. See Figure 2-6. This
starts the Lattice Synthesis Engine running. See Figure 2-7.
iCEcube2 User Guide www.latticesemi.com 16
Figure 2-6: Launch Synthesis Tool
Once synthesis is complete, you will see a green checkmark next to the Run Lattice LSE
Synthesis command. The Output tab shows the actions taken along with any warning or error
messages. Scroll down toward the bottom to see the area, clock, and timing reports. See Figure
2-7.
iCEcube2 User Guide www.latticesemi.com 17
Figure 2-7: Synthesis Run Status
View Timing Constraints
Double Click on the blinky_syn.sdc file under the Constraint Files folder. See Figure 2-8. It will
open the timing constraints for the project shown in Figure 2-9.
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Figure 2-8: Open the SDC File to View Timing Constraints
Figure 2-9: View Timing Constraints
iCEcube2 User Guide www.latticesemi.com 19
Select Implementation
Double-click on Select Implementation. See Figure 2-10. This will tell iCEcube2 which
synthesis implementation to process for place and route. If you have different synthesis
implementations, you will be able to select the synthesis implementation you wish to place and
route. Since we only have one implementation, select OK when the Select Synthesis
Implementation dialog box appears.
Figure 2-10: Select Synthesis Implementation
Importing Physical Constraints
Physical constraints such as pin assignments are stored in a .PCF file (Physical Constraint File).
Add the .PCF file to your project.
In the iCEcube2 Project Navigator, Right Click on Constraint Files. Select Add Files… See
Figure 2-11.
Note: For information on importing physical constraints from iCEcube to iCEcube2, please refer
to the Importing Physical Constraints from iCEcube to iCEcube2 section at the end of this
quick start guide.
iCEcube2 User Guide www.latticesemi.com 20
Figure 2-11: Add Constraints Files for Place and Route
Navigate to the <iCEcube2 Installation Directory>/examples/blinky and Add blinky.pcf file. See
Figure 2-12.
Figure 2-12: Add .pcf File
iCEcube2 User Guide www.latticesemi.com 21
Import Place & Route Input Files
The next step is to import the files for Place and Route. Double-click on Import P&R Input
Files in the Project Navigator. See Figure 2-13. Once completed you will see a green check
next to Import P&R Input Files. See Figure 2-14.
Figure 2-13: Import P&R Input Files
Figure 2-14: Successful Import of P&R Input Files
iCEcube2 User Guide www.latticesemi.com 22
Place the Design
Double-click on Run Placer.
Once placement is complete, a green check will appear and the Output window will show
information about the placement of the design. See Figure 2-15.
Figure 2-15: Placer Run Status Display
View Floor Planner
At this point, since placement has been completed, you can view the placement of the design by
opening the Floor Planner. You can open the Floor Planner by going to the menu and selecting
Tool > Floor Planner or you can also select the Floor Planner Icon. See Figure 2-16.
iCEcube2 User Guide www.latticesemi.com 23
Figure 2-16: Floorplanner View
View the Package View
You can also see how pins were placed for your design by selecting the Package View. You can
select the package viewer by going to the menu and selecting Tool > Package View or you can
also select the Package View Icon. See Figure 2-17.
Figure 2-17: Package View
iCEcube2 User Guide www.latticesemi.com 24
Route the Design
Double-click on Run Router in the project navigation window. Place and Route have been
separated into different steps as to allow you to re-route the design after making placement
modifications in the floor planner without having to re-run the placer.
Perform Static Timing Analysis
Now that you have routed the design, you can perform timing analysis to check to see if the
design meets your timing requirements. To launch the timing analyzer, go to the menu and
select Tool > Timing Analysis. You can also select the Timing Analysis Icon. See Figure 2-18.
Figure 2-18: Timing Analysis Summary
You can see from the timing analysis that our 32-kHz design is running at over 395 MHz and our
32-MHz clock is running at over 222 MHz (worst case timing). If we were not meeting timing, the
timing analyzer would allow you to see your failing paths and do a more in-depth analysis. For
this tutorial, we won’t go into details on timing slack analysis.
Perform Power Analysis
iCEcube2 also comes with power estimator tool. To launch the power estimator, go to the menu
and select Tool > Power Estimator. You can alternatively select the power estimator icon.
There are multiple tabs in the Power Estimator tool including Summary, IO, and Clock Domain as
shown in Figure 2-19. On the Summary tab, change the Core Vdd to 1.2V and make sure all IO
voltages are at 2.5V. Then hit Calculate. The estimator will update with power information for
iCEcube2 User Guide www.latticesemi.com 25
both static and dynamic power. For more information on using the IO and Clock Domain tabs,
please refer to the detailed section on the Power Estimator tool.
Figure 2-19: Power Estimator
Programming the Device
In order to program a device, you will need to generate a programming file. In the project
navigator, double click on Generate Bitmap.
You are now ready to program an iCE40 device with the generated bitmap.
Start the stand-alone Diamond Programmer. In Windows, from the Start menu, choose Lattice
Diamond Programmer <version_number> > Diamond Programmer.
The Diamond Programmer Getting Started dialog box appears, as shown in Figure 2-20.
Figure 2-20 : Getting Started Dialog Box
iCEcube2 User Guide www.latticesemi.com 26
Choose Create a New Project from a Scan button and click OK. The Diamond Programmer
main window appears. In the Cable Settings box in the upper right, click Detect Cable.
Diamond Programmer will indicate in the bottom output tab that the Lattice HW-USBN-2A USB
programming cable was detected, as shown in
Figure
2-21.
Figure 2-21 : Diamond Programmer Main Window
In the Device Family field, click the Generic JTAG Device box and choose iCE40 from the drop-
down menu, as shown in Figure 2-22 .
iCEcube2 User Guide www.latticesemi.com 27
Figure 2-22: Choosing iCE40 Device Family
In the Device column, choose iCE40HX1K from the drop-down menu, as shown in Figure 2-23.
Figure 2-23 : Choosing iCE40HX1K Device
There are three basic programming flows for configuring the iCE40 device. This section explains
programming iCE40 device using an external SPI Flash device available in iCEblink40-HX1K
evaluation board.
iCEcube2 User Guide www.latticesemi.com 28
Choose Edit > Device Properties, or double-click the Operation box to display the Device
Properties dialog box, as shown in Figure 2-24.
In the Device Properties dialog box, set options as follows:
Access Mode: SPI Flash Programming
Operation: SPI Flash Erease,Program,Verify
In the Programming File box, browse to the .hex file you generated with iCEcube2.
In the SPI Flash Options box, choose the following options:
Family : SPI Serial Flash
Vendor : STMicro
Device : SPI-M25P 10-A
Package : 8-pin SOIC
The Device Properties dialog box should be configured as shown in Figure 2-24. In the Device
Properties dialog box, click OK.
Figure 2-24 : Device Properties Dialog Box
In the Diamond Programmer main window, choose Design > Program, or click the Program icon
in the toolbar, as shown in Figure 2-25. Once the SPI Flash is programmed, the output tab in the
lower left portion of Diamond Programmer indicates Operation successful.
iCEcube2 User Guide www.latticesemi.com 29
Figure 2-25 : Program the device.
The external SPI Flash on the Lattice iCEblink40-HX1K evaluation board has been programmed,
and the iCE40 is configured from the SPI flash.
Addendum:
Importing Physical Constraints from iCEcube to iCEcube2
For users who have created physical constraints using iCEcube, this section describes how to
import and convert those constraints for use in iCEcube2. This section will demonstrate how to
import a .MTCL file from iCEcube and save it into .PCF format used in iCEcube2.
In the iCEcube2 project navigator, Right-click on Constraint Files and select Add Files. See
Figure 2-26.
iCEcube2 User Guide www.latticesemi.com 30
Figure 2-26: Add Constraint File
Navigate to the <iCEcube2 Installation Directory>/examples/blinky and Add blinky.mtcl file. See
Figure 2-27.
Figure 2-27: Add .mtcl File
iCEcube2 User Guide www.latticesemi.com 31
Import Place & Route Input Files
The next step is to import the files for Place and Route. Double-click on Import P&R Input
Files in the Project Navigator. See Figure 2-28. Once importing of files completed you will see a
green check next to Import P&R Input Files. See Figure 2-29.
Figure 2-28: Double-Clock on Import P&R Input Files
iCEcube2 User Guide www.latticesemi.com 32
Figure 2-29: Successful Import of P & R Input Files
Saving Physical Constraints into .pcf Format
Open the Pin Constraints Editor by going to the menu and selecting Tool > Pin Constraints
Editor or you can also select the Pin Constraints Editor Icon. See Figure 2-30. You will see a list
of pin assignments that are locked under the locked column. Uncheck and Recheck one of the
pins under the locked column. The save icon will now become an active icon. Click on the
Save physical constraints icon. This will bring up a dialog box where you can save the PCF
file. Hit OK. See Figure 2-31. The .PCF file contains physical constraints in the design used for
place and route.
iCEcube2 User Guide www.latticesemi.com 33
Figure 2-30: Pin Constraints Editor
Figure 2-31: Save Physical Constraints File
iCEcube2 User Guide www.latticesemi.com 34
Chapter 3 iCEcube2 Project Setup and Navigation
Introduction
This chapter describes the features of the iCEcube2 Project Manager and how to set up a design
Project. The primary functions of the Project Manager include project setup, launching the Lattice
Synthesis Engine (LSE) or Synplify pro for synthesis, placing and routing the design, launching
the Aldec Active-HDL for simulation and launching the software required to Program the target
device.
This chapter assumes that the reader is familiar with the New Project creation process as
described in Chapter 2 Quick Start.
Project Manager GUI
Figure 3-1 below displays the Project Manager GUI. A new project can be opened by clicking on
the New Project icon or the File > New Project menu item. Similarly, an existing project can be
opened or closed using the Open Project and Close Project icons.
Figure 3-1 : iCEcube2 Project Flow Manager
Adding/Deleting Design and Constraint Files
Design and Constraint files can be added or removed from the project by selecting Design Files
or Constraint Files respectively as displayed in Figure 3-2.
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Figure 3-2 : Adding/Removing Design Files to the design project
Deleting a specific file can be accomplished by selecting the file name and clicking the right-
button on the mouse. Figure 3-3 below displays the state of the GUI upon clicking the mouse
button.
Figure 3-3 : Removing Files from the design project
iCEcube2 User Guide www.latticesemi.com 36
Selecting Synthesis Tool and Setting synthesis Options
The iCEcube2 software supports Synplify-pro synthesis tool and Lattice Synthesis tool (LSE) to
synthesis the design. In order to change the synthesis tool, click right-mouse button on
Synthesis Tool” item and select the synthesis tool as shown in Figure 3-5.
Figure 3-4 : Select Synthesis Tool
Figure 3-5 : Synthesis Tool Selection Wizard
To set the LSE synthesis tool options, clickright- mousebutton on the “Run LSE Synthesisas
shown in Figure 3-6.
iCEcube2 User Guide www.latticesemi.com 37
Figure 3-6 : Open LSE Tool Options Wizard
Set the LSE tool options and click on “OK” button to save the changes. Rerun the LSE synthesis.
Figure 3-7 : LSE tool options wizard
To set the Synplify-Pro synthesis tool options, click right-mousebutton on the “Run Synplify-
Pro Synthesis” item. This will pop up the “Tool Options” wizard. In the Synplify Pro” tab select
the word “here” to open the Synplify-Pro GUI.
iCEcube2 User Guide www.latticesemi.com 38
Figure 3-8: Invoke Synplify-Pro GUI
In the Synplify-Pro window, Select “Implementation Options”, set the tool options and save. Rerun
the Synplify synthesis.
Figure 3-9: Set Implementation Options
iCEcube2 User Guide www.latticesemi.com 39
Selecting the Target Device and Operating Conditions
The iCEcube2 software provides the ability to specify the operating conditions for the target
device. In order to change the Target Family, Device and/or the Operating Conditions, click the
right-button on the mouse, in the Device/Operating Condition window to display the Edit
action. This is shown in Figure 3-10.
Figure 3-10 : Modifying the Device Selection/Operating Conditions
Device options wizard is shown in Figure 3-11.
Figure 3-11: Device Options for iCE40 Family
iCEcube2 User Guide www.latticesemi.com 40
In order to specify a suitable target Device, the following steps need to be performed:
1. Specify a Device Family
2. Specify a Device using the drop-down menu
3. Select a suitable Device Package for the device selected in the previous step
Specifying the Operating Conditions for the target device involves the following steps:
1. Junction Temperature
a. Select an appropriate Junction Temperature Range from the options available.
Depending on the Power Grade selected for the target device, the software provides
built-in options such as Commercial and Industrial temperature ranges.
b. If the device’s operating conditions do not fall into either the Commercial or the
Industrial temperature ranges, the software also permits the user to specify a
customized junction temperature. This is accomplished by selecting the Custom option,
and manually specifying the Best, Typical and Worst Case junction temperatures.
2. Core Voltage: Select a Voltage Tolerance Range from the provided options.
3. IO Bank Voltage: This option is available only for iCE40 family as shown in Figure 3-11.
Select a bank voltage from the provided options for the top, bottom, left, right banks. The
specified IO Voltage values are used by Power Estimator and Static Timing Analysis tools.
In order for Static Timing Analysis to be performed at the desired Operating Conditions, the
software provides the ability to select the Best Case, Typical Case or Worst Case conditions.
Output Window
The iCEcube2 Project Flow Manager software provides an Output Window to display messages,
warnings and errors.
Simulation Wizard
The iCEcube2 windows software installs Aldec Active-HDL, a windows based simulator tool to
perform functional and timing verification of the implemented designs. The “Simulation Wizard” in
the project navigator allows the user to create a simulation project for Aldec Active-HDL, select
the simulation netlist, simulation language and invokes the Aldec Active-HDL interface.
Select Active-HDL icon to invoke the “Simulation Wizard” as shown in Figure 3-12. Refer to
chapter “Simulating Design with ALDEC Active-HDL” for more details about simulation wizard and
simulation steps with Aldec Active-HDL.
iCEcube2 User Guide www.latticesemi.com 41
Figure 3-12 : Invoking Simulation Wizard.
PLL Module Generator
Certain devices of the iCE40 family include a Phase Lock Loop (PLL) function. The PLL function
requires configuration before it can be used in a design. To help configure the PLL, the iCEcube2
Project Flow Manager includes a PLL Module Generator, which can be launched from the Tool >
Configure > Configure PLL Module menu item, as displayed in Figure 3-13.
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Figure 3-13: Launching the PLL Module Generator
The PLL Module Generator allows the user to create a new PLL configuration, or edit an existing
one as shown in Figure 3-14.
The output of the PLL Module Generator is a PLL module file (Verilog), that instantiates a PLL, as
configured by the user. A secondary file (wrapper), that includes an instance of the PLL module,
is generated in order to help instantiate the PLL module in the user’s design. Note that the PLL
module file should be included in the list of design files.
Once a PLL module file has been generated, it can be edited, by selecting the “Modify an existing
PLL configuration” option (Figure 3-14).
iCEcube2 User Guide www.latticesemi.com 43
Figure 3-14: Create/Modify a PLL configuration
Configuring the iCE65 PLL
In the PLL Module Generator wizard, select Device Family as iCE65 and provide the PLL
Module Name. Click on the OK button. The PLL Module Generator launches a wizard to help the
user configure the PLL as per the design requirements. This section describes the features of
iCE65 family PLL modules.
PLL Type
The connectivity of the PLL to its surrounding logic determines the PLL Type. The iCEcube2
software supports the following PLL types. These PLL type options can be selected on the first
page of the wizard, as displayed in Figure 3-15.
1. General Purpose IO Pad or Core Logic: In this scenario, the PLL input (source clock) is
driven by a signal from the FPGA fabric. This signal can either be generated on the FPGA
core, or it can be an external signal that was brought onto the FPGA using a General
Purpose IO pad. The PLL output (generated clock) is available on the FPGA to drive a global
clock network, as well as regular routing.
2. Clock Pad: The PLL input clock (source) is driven by a dedicated clock pad located in IO
Bank 2
a. The PLL output (generated clock) is available to drive a global clock network, as well
as regular routing. The PLL source clock is not available on the FPGA.
b. The PLL output (generated clock) is available to drive a global clock network, as well
a regular routing. The PLL source clock is also available on the FPGA, and can drive
a global clock network, as well as regular routing.
iCEcube2 User Guide www.latticesemi.com 44
Figure 3-15: Selecting the PLL Type and Operation Mode
PLL Operation Modes
The PLL can be configured to operate in one of multiple modes. An Operation Mode determines
the feedback path of the PLL and enables phase alignment of the generated clock with respect to
the source clock.
The iCEcube2 software supports the following PLL Operation modes:
1. No Compensation mode: The PLL can be used for generating the desired output frequency,
without the ability to control the phase of the generated clock.
2. Delay Compensation using only the Fine Delay Adjustment (FDA) Block: In this mode, the
feedback path is internal to the PLL but traverses through a fine delay adjustment circuit that
permits user control of the feedback path delay in 16 steps of 0.15 ns each. The delay
adjustment can be controlled dynamically through signals connected to the PLL, or it can be
fixed i.e. once configured, the delay contributed by the delay block can only be changed upon
re-programming the FPGA with a different bit configuration.
3. Delay Compensation using the Phase Shifter and the Fine Delay Adjustment (FDA) Block:
The Phase Shifter provides four outputs corresponding to a phase shift of 0 degrees, 90
degrees, 180 degrees or 270 degrees. In addition, this feedback path provides additional
delay adjustment through the FDA block.
4. Delay Compensation using a feedback path external to the PLL: The feedback path traverses
through FPGA routing (external to the PLL) followed by the Fine Delay Adjustment (FDA)
iCEcube2 User Guide www.latticesemi.com 45
Block. Hence, in effect, two delay controls are available the external path for coarse
adjustment and the FDA block for fine delay adjustment.
Figure 3-16 : PLL Module Generator Frequency Specification
Fine Delay Adjustment: The delay contributed by the FDA block can be Fixed or controlled
dynamically during FPGA operation. If Fixed, it is necessary to provide a number (n) in the range
0-15 to specify the delay contributed to the feedback path. The delay for a setting “n” is calculated
as follows
FDA delay = (n+1)*0.15 ps, where “n” is the value specified by the user, and 0 ≤ n ≤ 15
Frequency Specification: The input and output frequency of the PLL should be specified in MHz
as shown in Figure 3-16. Depending on the values provided by the user, the PLL is internally
configured to generate the specified output frequency.
In case the frequency specified is not in the range permitted by the Operation Mode, the software
provides appropriate feedback, as displayed in Figure 3-17.
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Figure 3-17: Frequency Validation by PLL Configurator
Other options:
LOCK: A Lock signal is provided to indicate that the PLL has locked on to the incoming signal.
Lock asserts High to indicate that the PLL has achieved frequency lock with a good phase lock.
BYPASS: A BYPASS signal is provided which both powers-down the PLL core and bypasses it
such that the PLL output tracks the input reference frequency.
Low Power Mode: A control is provided to dynamically put the PLL into a Lower Power Mode
through the iCEGate feature. The iCEGate feature latches the PLL Output signal, and prevents
unnecessary toggling.
The RESET (Active Low) port is always generated, and an explicit PLL reset operation is required
to initialize the PLL functionality.
Configuring the iCE40 PLL
Most devices in the iCE40 family provide two PLL functions, each of which can be configured
independently.
In the PLL Module Generator wizard, select Device Family as iCE40 and provide the PLL
Module Name. Click on the OK button. The PLL Module Generator launches a wizard to help the
user configure the PLL as per the design requirements.
PLL Type
The connectivity of the PLL to its surrounding logic determines the PLL Type. The iCEcube2
software supports the following PLL types. These PLL type options can be selected on the first
page of the wizard, as displayed in Figure 3-18.
1. Select the number of global networks to be driven by the PLL output. Setting the value to “1”
generates a PLL which drives a single global clock network, as well as regular routing.
Setting the value to “2” generates a PLL which drives two global clock networks as well as
two regular routing resources.
2. Specify the input to the PLL:
iCEcube2 User Guide www.latticesemi.com 47
General Purpose IO Pad or Core Logic: In this scenario, the PLL input (source clock) is
driven by a signal from the FPGA fabric. This signal can either be generated on the FPGA
core, or it can be an external signal that was brought onto the FPGA using a General
Purpose IO pad.
Dedicated Clock Pad (Single Ended): The PLL input clock (source) is driven by a dedicated
single ended clock pad located in IO Bank 2 (Bottom bank) or IO Bank 0 (Top bank). (In case
two global networks were selected in the previous step, the input signal can be used as-is on
the logic fabric, i.e. it can bypass the PLL. In the rare situation that this is required, select the
check-box, “The PLL source clock will be used on chip without frequency/phase/delay
adjustments”.)
Figure 3-18: iCE40 PLL - Selecting PLL Type and Operation Modes
PLL Operation Modes
The PLL can be configured to operate in one of multiple modes. An Operation Mode determines
the feedback path of the PLL, and enables phase alignment of the generated clock with respect
to the source clock.
The iCEcube2 software supports the following PLL Operation modes:
1. No Compensation mode: The PLL can be used for generating the desired output frequency,
without the ability to control the phase of the generated clock.
2. Delay Compensation using only the Fine Delay Adjustment (FDA) Block: In this mode, the
feedback path is internal to the PLL but traverses through a fine delay adjustment circuit that
permits user control of the feedback path delay in 16 steps of 0.15 ns each. The delay
adjustment can be controlled dynamically through signals connected to the PLL, or it can be
fixed i.e. once configured, the delay contributed by the delay block can only be changed upon
re-programming the FPGA with a different bit configuration.
3. Delay Compensation using the Phase Shifter and the Fine Delay Adjustment (FDA) Block.
For single port PLL types the Phase Shifter provides two outputs corresponding to a phase
shift of 0 degrees and 90 degrees. For two port PLL types, the Phase Shifter has two modes:
iCEcube2 User Guide www.latticesemi.com 48
Divide-by-4 mode and Divide-by-7. In Divide-by-4 mode, the output of B port can be shifted
either 0 degrees or 90 degrees w.r.t to A port outputs. In Divide-by-7 mode, the B port output
frequency can be set to have a frequency ratio of 3.5:1 or 7:1 w.r.t the port A output
frequency. In addition to the delay compensation provided by the phase shifter, this feedback
path provides additional delay adjustment through the FDA block.
4. Delay Compensation using a feedback path external to the PLL: The feedback path traverses
through FPGA routing (external to the PLL) followed by the Fine Delay Adjustment (FDA)
Block. Hence, in effect, two delay controls are available the external path for coarse
adjustment and the FDA block for fine delay adjustment.
Fine Delay Adjustment: The delay contributed by the FDA block can be Fixed or controlled
dynamically during FPGA operation. If Fixed, it is necessary to provide a number (n) in the range
0-15 to specify the delay contributed to the feedback path. The delay for a setting “n” is calculated
as follows
FDA delay = (n+1)*0.15 ps, where n is the value specified by the user, and 0 n 15.
Additional Delay Adjustment: In addition to Fine Delay Adjustment in the feedback path, the user
can specify additional delay on the PLL output ports as shown in Figure 3-19. The delay
contributed by the delay block can be Fixed or controlled dynamically during FPGA operation. If
Fixed, it is necessary to provide a number (n) in the range 0-15 to specify the delay contributed to
the feedback path. The delay for a setting “n” is calculated as follows
FDA delay = (n+1)*0.15 ps, where n is the value specified by the user, and 0 n 15.
This additional delay is applied on the output of single port PLL and port A of two port PLL types.
Phase Shift Specification: Phase Shift specification allows the user to specify 0 degrees or 90
degrees phase shift.
Figure 3-19: iCE40 PLL - Additional Delay and Phase Shift Options
iCEcube2 User Guide www.latticesemi.com 49
Frequency Specification: The input and output frequency of the PLL should be specified in MHz
as shown in Figure 3-20. Depending on the values provided by the user, the PLL is internally
configured to generate the specified output frequency.
Frequency Specification window also checks for the input and output frequencies given by the
user. If the specified frequencies are at a range that cannot be generated by the PLL, then a
popup dialog box is displayed as shown in Figure 3-17 asking the user to enter the frequencies in
valid range.
LOCK: A Lock signal is provided to indicate that the PLL has locked on to the incoming signal.
Lock asserts High to indicate that the PLL has achieved frequency lock with a good phase lock.
BYPASS: A BYPASS signal is provided which both powers-down the PLL core and bypasses it
such that the PLL output tracks the input reference frequency.
Low Power Mode: A control is provided to dynamically put the PLL into a Lower Power Mode
through the iCEGate feature. The iCEGate feature latches the PLL Output signal, and prevents
unnecessary toggling.
The RESET (Active Low) port is always generated, and an explicit PLL reset operation is required
to initialize the PLL functionality.
Figure 3-20: iCE40 PLL - Frequency Specification
PLL Summary: The PLL Configuration summary is shown in Figure 3-21. Click on “Save” to
save the PLL configuration file.
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Figure 3-21 : PLL Summary
PLL Dynamic Reconfiguration
iCE5LP devices supports dynamic reconfiguration of PLL to change the output frequency, phase
shift and clock delays at runtime. Reconfiguration of PLL directly accesses the configuration bits
and changes the configuration on the fly while the design is running. This allows the user to run
the design at different frequencies.
To enable dynamic PLL reconfiguration, user needs to set the TEST_MODE parameter of the
PLL instance. Reconfiguration of PLL is done using the serial data input pin SDI. The
configuration bits are latched in a 27 bit shift register (PLLCFGREG) in the PLL block by
configuration clock SCLK.
The user can reconfigure the PLL either by using a build in configuration load module or by using
external control signals connected to the device.
PLL Reconfiguration Process
1. Assert the PLL RESET (Active low) signal.
2. Load the serial configuration bits via SDI pin. The data should be available at positive
edge of SCLK and the data is latched at negative edge of SCLK. The shift out bit is
available in SDO pin.
3. After 27 clock cycles stop the configuration clock signal. The recommended configuration
clock frequency range is 2 MHz to 12 MHz.
4. At the end of 27 clock cycles, the PLLCFGREG is loaded with 27 bit configuration bit.
The first data shifted in is available at PLLCFGREG [26].
5. De-assert the RESET signal after 10ns.
6. Wait for the PLL to lock.
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Dynamic configuration PLL instance model is given below. If the TEST_MODE is set, the PLL
output frequency is based on the PLLCFGREG settings.
Verilog:
SB_PLL40_PAD instSBPLL (
.PACKAGEPIN (REFCLK),
.EXTFEEDBACK (),
.DYNAMICDELAY (),
.BYPASS (BYPASS),
.RESETB (RESETB),
.LATCHINPUTVALUE (LATCHINPUTVALUE),
.LOCK (LOCK),
.SDI(SDI), // serial data in
.SDO(SDO), // serial data out
.SCLK(SCLK), // Configuration clock
.PLLOUTCORE (PLLOUTCORE_net),
.PLLOUTGLOBAL (PLLOUTGLOBAL_net)
);
// INPUT Fin=20MHz, Fout=200MHz
defparam instSBPLL.DIVR = 4'b0001;
defparam instSBPLL.DIVF = 7'b1001111;
defparam instSBPLL.DIVQ = 3'b010;
defparam instSBPLL.FILTER_RANGE = 3'b001;
defparam instSBPLL.FEEDBACK_PATH = "SIMPLE";
defparam instSBPLL.DELAY_ADJUSTMENT_MODE_FEEDBACK= "FIXED";
defparam instSBPLL.FDA_RELATIVE = 4'b0000;
defparam instSBPLL.PLLOUT_SELECT = "GENCLK";
defparam instSBPLL.SHIFTREG_DIV_MODE = 2'b00;
defparam instSBPLL.ENABLE_ICEGATE = 1;
// Enable Dynamic PLL configuration
defparam instSBPLL.TEST_MODE = 1;
PLL Configuration Register Mapping
The following table maps the PLL configuration register bits to PLL parameter settings.
Configuration
Register
PLL Parameter Map
Description
PLLCFGREG[3:0]
DIVR
REFERENCECLK
divider value
PLLCFGREG[10:4]
DIVF
Feedback divider value
PLLCFGREG[13:11]
DIVQ
VCO Divider
PLLCFGREG[16:14]
FILTER_RANGE
PLL Filter Range
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PLLCFGREG[25,18,17]
FEEDBACK_PATH
SIMPLE Feedback
(Internal )
DELAY
PHASE_AND_DELAY
EXTERNAL
PLLCFGREG[26,21]
SHIFTREG_DIV_MODE
Divide by 4
Divide by 7
Invalid setting
Divide by 5
PLLCFGREG[20:19],
PLLCFGREG[24:23]
PLLOUT_SELECT_PORTB,
PLLOUT_SELECT_PORTA
GENCLK
GENCLK_HALF
SHIFTREG_90deg
SHIFTREG_0deg
PLLCFGREG[22]
Set PLL Primitive type.
CORE PLL
PAD PLL
The sample configuration register setting for a PAD PLL with 20 MHz reference clock and 200
MHz output frequency is
PLLCFGREG [26:0] =27'b0_1_00_00_00_00_001_010_1001111_0001;
SPI/I2C Module Generator
iCE40LM, iCE5LP (iCE40 Ultra) device families contains hardened I2C and SPI IP blocks. These
devices do not pre-load the hard IP registers during configuration. A soft IP is required to
configure the I2C/SPI hard IP blocks in the design.
The iCEcube2 Project Flow Manager includes an I2C/SPI Module Generator to generate soft IP
modules. Launch the module generator from Tool > Configure > Configure SPI/I2C Module
menu item, as shown in Figure 3-22.
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Figure 3-22 : Launch I2C/SPI Module Generator.
The I2C/SPI Module Generator allows the user to create a new configuration, or edit an existing
one as shown in Figure 3-23.
Figure 3-23: Create New I2C/SPI Module
The output of the Module Generator is a module file (Verilog), that instantiates a SPI/I2C, as
configured by the user. Note that the I2C/SPI module file should be included in the list of design
files.
Once an I2C/SPI module file has been generated, it can be edited, by selecting the “Modify an
existing PLL configuration” option (Figure 3-24).
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Figure 3-24: Modify Existing I2C/SPI configuration
Configuring I2C/SPI Hard IP
iCE40LM, iCE5LP (iCE40 Ultra) device contains two I2C and SPI hard IP blocks, each of which
can be configured independently.
In the I2C/SPI Module Generator wizard, select “Create a new I2C/SPI configuration” and provide
the module Name. Click on the OK button. The Module generator launches a wizard to help the
user configure the I2C/SPI as per the design requirements. This section explains the options in
the wizard to enable and configure the I2C/SPI soft IP wrappers.
Enable Hard IP
The ‘Hard IP Enables’ tab allows the user to enable the required left/right I2C, left/right SPI
instances in the wrapper and specify the system bus clock frequency. Selecting the hard IP type
enables the I2C and SPI Tabs in the wizard as shown in Figure 3-25.
Figure 3-25 : Enable Hard IP
Enable hard user I2C left: This option allows the user to enable left I2C on the I2C Tab.
Enable hard user I2C Right: This option allows the user to enable right I2C on the I2C Tab.
Enable hard user SPI Left: This option allows the user to enable left SPI on the SPI Tab.
Enable hard user SPI Right: This option allows the user to enable right SPI on the SPI Tab.
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System Clock: Specify the system clock frequency in Mhz. This value is used to derive the
divider settings of the I2C and SPI hard IP master clocks. “Generate” button is enabled once the
value is set in this field.
Configure I2C
I2C Tab allows the user to configure the left and right I2C blocks independently as shown in
Figure 3-26. I2C Tab is enabled only when I2C hard IP is selected in the Hard IP Enables Tab.
Figure 3-26: Configure Left/Right I2C hard IP.
I2C Controller General Options:
General Call Enable: This setting enables the I2C General Call response (addresses all devices
on the bus using the I2C address 0) in Slave mode. This setting can be modified dynamically by
enabling the GCEN bit in the I2C Control Register I2CCR1.
Wakeup Enable: Turns on the I2C wakeup on address match. The WKUPEN bit in the I2CCR1
can be modified dynamically allowing the Wake Up function to be enabled or disabled.
Include IO Buffers: Include buffers to the I2C_SCL, I2C_SDA pins.
Master Clock (Desired): Specify the desired I2C master clock frequency. A calculation is then
made to determine a divider value to generate a clock close to this value from the input clock.
The frequency of the input System Bus clock is specified on the main/general tab. The divider
value is rounded to the nearest integer after dividing the input System Bus clock by the value
entered in this field.
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Master Clock (Actual): Since it is not always possible to divide the input System Bus clock to
the exact value requested by the user, the actual value will be returned in this read-only field.
I2C Addressing: This option allows the user to set 7-bit or 10-bit addressing and define the Hard
I2C address.
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I2C Controller Interrupts:
Arbitration Lost Interrupts: An interrupt which indicates I2C lost arbitration. This interrupt is bit
IRQARBL of the register I2CIRQ. When enabled, it indicates that ARBL is asserted. Writing a ‘1’
to this bit clears the interrupt. This option can be changed dynamically by modifying the bit
IRQARBLEN in the register I2CIRQEN.
TX/RX Ready: An interrupt which indicates that the I2C transmit data register (I2CTXDR) is
empty or that the receive data register (I2CRXDR) is full. The interrupt bit is IRQTRRDY of the
register I2CIRQ. When enabled, it indicates that TRRDY is asserted. Writing a ‘1’ to this bit clears
the interrupt. This option can be changed dynamically by modifying the bit IRQTRRDYEN in the
register I2CIRQEN.
Overrun or NACK: An interrupt which indicates that the I2CRXDR received new data before the
previous data. The interrupt is bit IRQROE of the register I2CIRQ. When enabled, it indicates that
ROE is asserted. Writing a ‘1’ to this bit clears the interrupt. This option can be changed
dynamically by modifying the bit IRQROEEN in the register I2CIRQEN.
General Call Interrupts: An interrupt which indicates that a general call has occurred. The
interrupt is bit IRQHGC of the register I2CIRQ. When enabled, it indicates that ROE is asserted.
Writing a ‘1’ to this bit clears the interrupt. This option can be changed dynamically by modifying
the bit IRQHGCEN in the register I2CIRQEN.
I2C SDA delays
This option is available only for iCE5LP (iCE40 Ultra) devices. Using these options, the user can
add 50ns delay to the SDA input, output signals.
SDA input: By default 50ns is added to the SDA input. Turn off this option if delay is not required.
SDA output: Turn on this setting to add 50ns delay to the SDA output.
Configure SPI
SPI Tab allows the user to configure the left and right SPI blocks independently as shown in
Figure 3-27. SPI Tab is enabled only when SPI hard IP is selected in the Hard IP Enables Tab.
Figure 3-27: Configure Left/Right SPI hard IP.
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Enable Slave Interface: This option allows the user to enable Slave Mode interface for the initial
state of the SPI block. By default, Slave Mode interface is enabled.
Enable Master Interface: This option allows the user to enable Master Mode interface for the
initial state of the SPI block. This option can be updated dynamically by modifying the MSTR bit
of the register SPICR2.
Master Clock Rate (Desired): Specify the desired SPI master clock frequency. A calculation is
then made to determine a divider value to generate a clock close to this value from the input
System Bus clock frequency. The divider value is rounded to the nearest integer after dividing the
input System Bus clock by the value entered in this field.
Master Clock Rate (Actual): Since it is not always possible to divide the input System Bus clock
exactly to that requested by the user, the actual value will be returned in this read-only field.
When both the desired SPI clock and System Bus clock fields have valid data and either is
updated, this field returns the value (System Bus Frequency / SPI_CLK_DIVIDER), rounded to
two decimal places.
Master Chip Selects: The core has the ability to provide up to 4 individual chip select outputs for
master operation. This field allows the user to prevent extra chip selects from being brought out of
the core. This option can be updated dynamically by modifying the register SPICSR.
SPI Controller Interrupts
TX Ready: An interrupt which indicates the SPI transmit data register (SPITXDR) is empty. The
interrupt bit is IRQTRDY of the register SPIIRQ. When enabled, indicates TRDY was asserted.
Write 1 to this bit to clear the interrupt. This option can be change dynamically by modifying the
bit IRQTRDYEN in the register SPIIRQEN.
TX Overrun: An interrupt which indicates the Slave SPI chip select (SPI_SCSN) was driven low
while a SPI Master. The interrupt is bit IRQMDF of the register SPIIRQ. When enabled, indicates
MDF (Mode Fault) was asserted. Write “1” to this bit to clear the interrupt. This option can be
change dynamically by modifying the bit IRQMDFEN in the register SPIIRQEN.
RX Ready: An interrupt which indicates the receive data register (SPIRXDR) contains valid
receive data. The interrupt is bit IRQRRDY of the register SPIIRQ. When enabled, indicates
RRDY was asserted. Write 1 to this bit to clear the interrupt. This option can be change
dynamically by modifying the bit IRQRRDYEN in the register SPICSR.
RX Overrun: An interrupt which indicates SPIRXDR received new data before the previous data.
The interrupt is bit IRQROE of the register SPIIRQ. When enabled, indicates ROE was asserted.
Write a 1to this bit to clear the interrupt. This option can be change dynamically by modifying
the bit IRQROEEN in the register SPIIRQEN.
SPI Controller General Options:
Wakeup Enable: The core can optionally provide a wakeup signal to the device to resume from
low power mode. This option can be updated dynamically by modifying the bit WKUPEN_USER
in the register SPICR1.
LSB First: This setting specifies the order of the serial shift of a byte of data. The data order
(MSB or LSB first) is programmable within the SPI core. This option can be updated dynamically
by modifying the LSBF bit in the register SPICR2.
Inverted Clock: Select this option to invert the clock polarity used to sample input and output
data. When selected the edge changes from the rising to the falling clock edge. This option can
be updated dynamically by accessing the CPOL bit of register SPICR2.
iCEcube2 User Guide www.latticesemi.com 59
Phase Adjust: An alternate clock-data relationship is available for SPI devices with particular
requirements. This option allows the user to specify a phase change to match the application.
This option can be updated dynamically by accessing the CPHA bit in the register SPICR2.
Slave Handshake Mode: Enables Lattice proprietary extension to the SPI protocol. For use
when the internal sup-port circuit (e.g. WISHBONE host) cannot respond with initial data within
the time required, and to make the Slave read out data predictably available at high SPI clock
rates. This option can be updated dynamically by accessing the SDBRE bit in the register
SPICR2.
Include IO Buffers: Include buffers to the SPI_MISO, SPI_MOSI, SPI_SCK, SPI_MCSNO [0]
pins.
Generate Module
Once the settings are done generate the soft IP module by selecting “Generate” button. The
wizard displays the status and the generated file details in the “Generate Log” tab as shown in
Figure 3-28.
Figure 3-28: I2C/SPI soft IP module generation.
iCEcube2 User Guide www.latticesemi.com 60
Chapter 4 Lattice Synthesis Engine
Lattice Synthesis Engine (LSE) is the integrated synthesis tool that comes with iCEcube2.
This chapter describes:
LSE tool options
HDL coding tips
Attributes and directives supported by LSE
Synopsys design constraints (SDC) supported by LSE
LSE is a synthesis tool custom-built for Lattice products and fully integrated with iCEcube2.
Depending on the design, LSE may lead to a more compact or faster placement of the design
than another synthesis tool would do.
Also, LSE offers the following advantages:
More granular control through the tool options
Enhanced RAM and ROM inference and mapping, including:
o Dual-port RAM in write-through, normal, and read-before-write modes mapped to
BRAM
o Clock enable and read enable packing
o Mapping for the minimal number of BRAM blocks
o BRAM mapping for minimal timing
Post-synthesis Verilog netlist suitable for simulation
Changing the LSE Tool Options
The LSE options can be changed by selecting Tool > Tool Options > LSE. This section lists all
the tool options associated with LSE. The following sections describe how to set the options to
optimize synthesis for either area or speed and some of the differences between LSE and
Synplify Pro options.
BRAM Utilization
Specifies BRAM utilization target setting in percent of total vacant sites. LSE will honor the setting
and do the resource computation accordingly. Default is 100 (in percentage).
Carry Chain Length
Specifies the maximum number of output bits that get mapped to a single carry chain. Default is
0, which is interpreted as infinite length.
Command Line Options
Enables additional command line options for the LSE synthesis process. Type in the option and
its value (if any) in the Value column.
Fix Gated Clocks
Turns on (True) or off (False) converting all gated clocks to data enables for best performance.
Turn off to save power. Default is True.
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FSM Encoding Style
Specifies the encoding style to use for finite state machines: Binary, Gray, or One-Hot. Default is
Auto, meaning that LSE chooses a style for each finite state machine.
Intermediate File Dump
If you set this to True, LSE will dump about 20 intermediate encrypted Verilog files. If you supply
Lattice with these files, they can be decrypted and analyzed for problems. This option is good for
analyzing simulation issues.
Max Fanout Limit
Specifies the maximum fanout setting. LSE will make sure that any net in the design does not
exceed this limit. Default is 10000 fanouts.
Memory Initial Value File Search Path
Allows you to specify a path to locate memory initialization files (.mem) used in the design. The
software will add the specified paths to the list of directories to search when resolving file
references.
To specify a search path, double-click the Value box, and directly enter the path.
Number of Critical Paths
Specifies the number of critical timing paths to be reported in the timing report.
Optimization Goal
Enables LSE to optimize the design for area, speed, or both. Valid options are:
Area (default) Optimizes the design for area by reducing the total amount of logic used
for design implementation.
When Optimization Goal is set to Area, LSE ignores the Target Frequency setting and
uses 1 MHz instead.
Timing Optimizes the design for speed by reducing the levels of logic.
When Optimization Goal is set to Timing and a create_clock constraint is available in an
.ldc file, LSE ignores the Target Frequency setting and uses the value from the
create_clock constraint instead.
Balanced Optimizes the design for both area and timing.
Propagate Constants
When set to True (default), enables constant propagation to reduce area, where possible. LSE
will then eliminate the logic used when constant inputs to logic cause their outputs to be constant.
You can turn off the operation by setting this option to False.
RAM Style
Sets the type of random access memory globally to BRAM or registers.
The default is Auto which attempts to determine the best implementation. That is, LSE will map to
RAM resources based on the resource availability.
This option will apply a syn_ramstyle attribute globally in the source to a module or to a RAM
instance. To turn off RAM inference, set its value to Registers.
iCEcube2 User Guide www.latticesemi.com 62
Other options are:
Registers Causes an inferred RAM to be mapped to registers (flip-flops and logic)
rather than the technology-specific RAM resources.
BRAM Causes the RAM to be implemented using the dedicated RAM resources. If your
RAM resources are limited, for whatever reason, you can map additional RAMs to
registers instead of the dedicated BRAM resources using this attribute.
Remove Duplicate Registers
Specifies the removal of duplicate registers. When set to True (default), LSE removes a register if
it is identical to another register. If two registers generate the same logic, the second one will be
deleted and the first one will be made to fan out to the second one's destinations. LSE will not
remove duplicate registers if this option is set to False.
Resolve Mixed Drivers
If a net is driven by a VCC or GND and active drivers, setting this option to True connects the net
to the VCC or GND driver.
Resource Sharing
When this is set to True (default), the synthesis tool uses resource sharing techniques to optimize
for area. With resource sharing, synthesis uses the same arithmetic operators for mutually
exclusive statements; for example, with the branches of a case statement. Conversely, you can
improve timing by disabling resource sharing, but at the expense of increased area.
ROM Style
Allows you to globally implement ROM architectures using dedicated, distributed ROM, or a
combination of the two (Auto).
This applies the syn_romstyle attribute globally to the design by adding the attribute to the
module or entity. You can also specify this attribute on a single module or ROM instance.
This option specifies a syn_romstyle attribute globally or on a module or ROM instance with a
value of:
Auto (default) Allows the synthesis tool to choose the best implementation to meet the
design requirements for speed, size, and so on.
BRAM Causes the ROM to be mapped to dedicated BRAM resources. ROM address or
data should be registered to map it to an BRAM block. If your ROM resources are limited,
for whatever reason, you can map additional ROM to registers instead of the dedicated or
distributed RAM resources using this attribute.
Logic Causes the ROM to be implemented using the normal logic.
Infer ROM architectures using a CASE statement in your code. For the synthesis tool to
implement a ROM, at least half of the available addresses in the CASE statement must be
assigned a value. For example, consider a ROM with six address bits (64 unique addresses). The
CASE statement for this ROM must specify values for at least 32 of the available addresses.
RW Check on RAM
Adds (True) or does not add (False) the glue logic to resolve read/write conflicts wherever
needed. Default is False.
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Target Frequency
Specifies the target frequency setting. This frequency applies to all the clocks in the design. If
there are some clocks defined in an .sdc file, the remaining clocks will get this frequency setting.
When Optimization Goal is set to Area, LSE ignores the Target Frequency setting and uses
1 MHz instead.
When Optimization Goal is set to Timing and a create_clock constraint is available in an .sdc file,
LSE ignores the Target Frequency setting and uses the value from the create_clock constraint
instead.
Top-Level Unit
It is a good practice to specify the top-level unit (or module) of the design. If you don’t, LSE will try
to determine the top-level unit. While usually accurate, there is no guarantee that LSE will get the
correct unit.
You may also want to change the top-level unit when experimenting with different designs or
switching between simulation and synthesis.
If the design is mix of EDIF and Verilog or VHDL, you cannot set an EDIF module as the top-level
unit.
Use Carry Chain
Turns on (True) or off (False) carry chain implementation for adders. Default is True. This option
is equivalent to the “-use_carry_chain” command in LSE.
Use IO Insertion
Turns on (True) or off (False) the use of I/O insertion. Default is True.
Use IO Registers
Enables (True) or disables (False) register packing. True forces the synthesis tool to pack all
input, output, and I/O registers into I/O pad cells based on timing requirements. Default is Auto,
which selects True or False based on how Optimization Goal is set.
You can place the syn_useioff attribute on an individual register or port. When applied to a
register, the synthesis tool packs the register into the pad cell, and when applied to a port, packs
all registers attached to the port into the pad cell. The syn_useioff attribute can be set on a:
Top-level port
Register driving the top-level port
Lower-level port if the register is specified as part of the port declaration
Optimizing LSE for Area and Speed
The following strategy settings for LSE can help reduce the amount of FPGA resources that your
design requires or increase the speed with which it runs. (For other synthesis tools, see those
tools’ documentation.) Use these methods along with other, generic coding methods to optimize
your design.
Minimizing area often produces larger delays, making it more difficult to meet timing
requirements. Maximizing frequency often produces larger designs, making it more difficult to
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meet area requirements. Either goal, pushed to an extreme, may cause the place and route
process to run longer or not complete routing.
To control the global performance of LSE, modify the tool options. Choose Tool > Tool Options.
In the Tool Options dialog box, set the following options, which are found in the LSE tab. See the
following text for explanations and more details.
LSE Tool Options for Area and Speed
Option
Area
Speed
FSM Encoding Style
Binary or Gray
One-Hot
Max Fanout Limit
<maximum>
<minimum>
Optimization Goal
Area
Timing
Remove Duplicate Registers
True
False
Resource Sharing
True
False
Target Frequency
<minimum>
FSM Encoding Style
If your design includes large finite state machines, the Binary or Gray style may use fewer
resources than One-Hot. Which one is best depends on the design. One-Hot is usually the fastest
style. However, if the finite state machine is followed by a large output decoder, the Gray style
may be faster.
Max Fanout Limit
A larger fanout limit means less duplicated logic and fewer buffers. A lower fanout limit may
reduce delays. The default is 10000, which is essentially unlimited fanout. To minimize area, don’t
lower this value any more than needed to meet other requirements. To maximize speed, try much
lower values, such as 50.
You can change the fanout limit for portions of the design by using the syn_maxfan attribute. See
“syn_maxfan” on page 86. Set Max Fanout Limit to meet your most demanding requirement.
Then add syn_maxfan to help other requirements.
Optimization Goal
If set to Area, LSE will choose smaller design forms over faster whenever possible. LSE will also
ignore the Target Frequency option, using a low 1 MHz target instead. If set to Timing, LSE will
choose faster design forms over smaller whenever possible. LSE will also use the timing
constraints in the design’s .sdc file to guide the optimization. If you are having trouble meeting
one requirement (area or speed) while optimizing for the other, try setting this option to
Balanced.
Remove Duplicate Registers
Removing duplicate registers reduces area, but keeping duplicate registers may reduce delays.
iCEcube2 User Guide www.latticesemi.com 65
Resource Sharing
If set to True, LSE will share arithmetic components such as adders, multipliers, and counters
whenever possible.
If the critical path includes such resources, turning this option off may reduce delays. However, it
may also increase delays elsewhere, possibly reducing the overall frequency.
Target Frequency
A lower frequency target means LSE can focus more on area. A higher frequency target may
force LSE to increase area. Try setting this value to about 10% higher than your minimum
requirement. However, if Optimization Goal is set to Area, LSE will ignore the Target Frequency
value, using a low 1 MHz target instead. If Optimization Goal is set to Timing and a create_clock
constraint is available in an .sdc file, LSE will use the value from the create_clock constraint
instead.
LSE Options versus Synplify Pro
If you are moving from using Synplify Pro to LSE, there are many differences in the options to
consider. Many of the Synplify Pro options have similar LSE options. But many also do not. See
the following table. And there are many LSE options that have no Synplify Pro equivalents. See
the lists following the table. For more information about the options, see Changing the LSE Tool
Options” on page 60.
Synplify Pro Tool Options and LSE Equivalents
Synplify Pro Option
LSE Equivalent
Synplify Pro
Default
LSE
Default
Allow Duplicate Modules
None
False
Area
Optimization Goal
False
Balanced
Arrange VHDL Files
None
True
Clock Conversion
None
True
Command Line Options
Command Line Options
Default Enum Encoding
FSM Encoding Style
Default
Auto
Disable IO Insertion
Use IO Insertion
False
True
Export Diamond Settings to Synplify Pro GUI
None
No
Fanout Guide
Max Fanout Limit
10000
1000
Force GSR
None
False
Frequency
Target Frequency
200
FSM Encoding
None
True
Number of Critical Paths
Number of Critical Paths
3
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Number of Start/End Points
None
Output Netlist Format
None
None
Output Preference File
None
True
Pipelining and Retiming
None
Pipelining Only
Push Tristates
None
True
Resolved Mixed Drivers
Resolve Mixed Drivers
False
False
Resource Sharing
Resource Sharing
True
True
Update Compile Point Timing Data
None
False
Use Clock Period for Unconstrained I/O
None
False
Verilog Input
None
Verilog 2001
VHDL 2008
None
False
LSE has additional options that provide more granular control than Synplify Pro. These options
include:
Carry Chain Length
BRAM Utilization
RAM Style
ROM Style
Other LSE options without Synplify Pro equivalents:
Intermediate File Dump
Memory Initial Value Search Path
Use Carry Chain
Use IO Registers
Propagate Constants
Remove Duplicate Registers
Coding Tips for LSE
If you are going to use LSE to synthesize the design, the following coding tips may help. Mostly
the tips are about writing code so that blocks of memory are “inferred”: that is, automatically
implemented using logic cells or block RAM (BRAM) instead of registers. There are also tips
about inferring types of I/O ports and about style differences with Synplify Pro.
LSE Differences with Synplify Pro
LSE tends to apply the Verilog and VHDL specifications strictly, sometimes more strictly than
other synthesis tools including Synplify Pro. Following are some coding practices that can cause
problems with LSE:
iCEcube2 User Guide www.latticesemi.com 67
Semicolons (;) to separate ports in a Verilog module statement. For example:
module COUNTER (
input CLK ,
input RESET ; // LSE error on semicolon.
output TIMEOUT
);
Spaces in the location path.
Duplicate instantiation names (due to names in generate statements).
Module instances without instance names.
Multiple files with the same module names. Synplify Pro will error out but LSE will not.
This could cause designs in LSE to use the incorrect module.
Global VHDL signals.
Modules that have a port mismatch between instance and definition.
Both ieee.std_logic_signed and unsigned packages in VHDL. When preparing VHDL
code for LSE, you can include either:
USE ieee.std_logic_signed.ALL;
or:
USE ieee.std_logic_unsigned.ALL;
Code with both signed and unsigned packages could fail to synthesize because
operators would have multiple definitions.
Mismatched variable types in VHDL. A std_logic_vector signal cannot be assigned to a
std_logic signal and an unsigned type cannot be assigned to a std_logic_vector signal.
For example:
din : in unsigned (data_width - 1 downto 0);
dout : out std_logic_vector (data_width - 1 downto 0));
...
dout <= din; // Illegal, mismatched assignment.
Such mismatched assignments generate errors that stop synthesis.
About Inferring Memory
Inferring memory means that LSE, based on aspects of the code, implements a block of memory
using logic cells or block RAM (BRAM)logic cells for small memories, BRAM for largeinstead
of registers. LSE can infer synchronous RAM that is:
single-port or pseudo dual-port
with or without asynchronous reset of the output
with or without write enables
with or without clock enables
LSE can also infer synchronous ROM.
In some old VHDL coding styles, one-dimensional memories and CASE statements were used to
create two-dimensional memories. This coding style does not translate to memories properly in
LSE.
iCEcube2 User Guide www.latticesemi.com 68
The following sections describe how to write code to infer different kinds of memory with LSE.
Inferring RAM
The basic inferred RAM is synchronous. It can have synchronous or asynchronous reads and can
be either single- or dual-port. You can also set initial values. Other features, such as resets and
clock enables, can be added as desired. The following text lists the rules for coding inferred RAM.
Following that, Figure 4-1 (Verilog) and Figure 4-2 (VHDL) show the code for a simple, single-port
RAM with asynchronous read.
To code RAM to be inferred, do the following:
Define the RAM as an indexed array of registers.
To control how the RAM is implemented (with block RAM), consider adding the
syn_ramstyle attribute. See “syn_ramstyle” on page 86.
Control the RAM with a clock edge and a write enable signal.
For synchronous reads, see Inferring RAM with Synchronous Read” on page 69.
For single-port RAM, use the same address bus for reading and writing.
For pseudo dual-port RAM, see “Inferring Pseudo Dual-Port RAM on page 71.
If desired, assign initial values to the RAM as described in Initializing Inferred RAMon
page 73.
module ram (din, addr, write_en, clk, dout);
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
// Define RAM as an indexed memory array.
always @(posedge clk) // Control with a clock edge.
begin
if (write_en) // And control with a write enable.
mem[(addr)] <= din;
end
assign dout = mem[addr];
endmodule
Figure 4-1: Simple, Single-Port RAM in Verilog
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram is
generic (
addr_width : natural := 8;
data_width : natural := 8);
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port (
addr : in std_logic_vector (addr_width - 1 downto 0);
write_en : in std_logic;
clk : in std_logic;
din : in std_logic_vector (data_width - 1 downto 0);
dout : out std_logic_vector (data_width - 1 downto 0));
end ram;
architecture rtl of ram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;
-- Define RAM as an indexed memory array.
begin
process (clk)
begin
if (clk'event and clk = '1') then -- Control with clock
edge
if (write_en = '1') then -- Control with a write
enable.
mem(conv_integer(addr)) <= din;
end if;
end if;
end process;
dout <= mem(conv_integer(addr));
end rtl;
Figure 4-2: Simple, Single-Port RAM in VHDL
Inferring RAM with Synchronous Read
For synchronous reads, add a register for the read address or for the data output. Load the
register inside the procedure or process that is controlled by the clock. See the following
examples. They show the simple RAM of “Inferring RAM” on page 68 modified for synchronous
reads. Changes are in bold text.
Verilog Examples
module ram (din, addr, write_en, clk, dout);
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout; // Register for output.
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge clk)
begin
if (write_en)
mem[(addr)] <= din;
dout = mem[addr]; // Output register controlled by
clock.
end
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endmodule
Figure 4-3: RAM with Registered Output in Verilog
module ram (din, addr, write_en, clk, dout);
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] raddr; // Register for read address.
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge clk)
begin
if (write_en)
begin
mem[(addr)] <= din;
end
raddr <= addr; // Read addr. register controlled by
clock.
end
assign dout = mem[raddr];
endmodule
Figure 4-4: RAM with Registered Read Address in Verilog
VHDL Examples
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram is
generic (
addr_width : natural := 8;
data_width : natural := 8);
port (
addr : in std_logic_vector (addr_width - 1 downto 0);
write_en : in std_logic;
clk : in std_logic;
din : in std_logic_vector (data_width - 1 downto 0);
dout : out std_logic_vector (data_width - 1 downto 0));
end ram;
architecture rtl of ram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;
begin
process (clk)
begin
iCEcube2 User Guide www.latticesemi.com 71
if (clk'event and clk = '1') then
if (write_en = '1') then
mem(conv_integer(addr)) <= din;
end if;
end if;
dout <= mem(conv_integer(addr));
-- Output register controlled by clock.
Figure 4-5: RAM with Registered Output in VHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram is
generic (
addr_width : natural := 8;
data_width : natural := 8);
port (
addr : in std_logic_vector (addr_width - 1 downto 0);
write_en : in std_logic;
clk : in std_logic;
din : in std_logic_vector (data_width - 1 downto 0);
dout : out std_logic_vector (data_width - 1 downto 0));
end ram;
architecture rtl of ram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (write_en = '1') then
mem(conv_integer(addr)) <= din;
end if;
raddr <= addr;
-- Read address register controlled by clock.
end if;
end process;
dout <= mem(conv_integer(raddr));
end rtl;
Figure 4-6: RAM with Registered Read Address in VHDL
Inferring Pseudo Dual-Port RAM
For pseudo dual-port RAM:
Use two address buses.
iCEcube2 User Guide www.latticesemi.com 72
If the design does not simultaneously read and write the same address, add the
syn_ramstyle attribute with the no_rw_check value to minimize overhead logic.
If writing in Verilog, use non-blocking assignments as described in About Verilog
Blocking Assignments” on page 75.
The following examples are based on the simple RAM of “Inferring RAM” on page 68.
Verilog Examples
module ram (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
Figure 4-7: Pseudo Dual-Port RAM in Verilog
VHDL Examples
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram is
generic (
addr_width : natural := 8;
data_width : natural := 8);
port (
write_en : in std_logic;
waddr : in std_logic_vector (addr_width - 1 downto 0);
wclk : in std_logic;
raddr : in std_logic_vector (addr_width - 1 downto 0);
rclk : in std_logic;
din : in std_logic_vector (data_width - 1 downto 0);
dout : out std_logic_vector (data_width - 1 downto 0));
end ram;
architecture rtl of ram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
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signal mem : mem_type;
attribute syn_ramstyle: string;
attribute syn_ramstyle of mem: signal is "no_rw_check";
begin
process (wclk) -- Write memory.
begin
if (wclk'event and wclk = '1') then
if (write_en = '1') then
mem(conv_integer(waddr)) <= din;
-- Using write address bus.
end if;
end if;
end process;
process (rclk) -- Read memory.
begin
if (rclk'event and rclk = '1') then
dout <= mem(conv_integer(raddr));
-- Using read address bus.
end if;
end process;
end rtl;
Figure 4-8: Pseudo Dual-Port RAM in VHDL
Initializing Inferred RAM
Create initial values for inferred RAM in the usual ways for initializing memory.
Verilog
In Verilog, initialize RAM with the standard $readmemb or $readmemh tasks in an initial block.
Create a separate file with the initial values in either binary or hexadecimal form. For example, to
initialize a RAM block named “ram”:
reg [7:0] ram [0:255];
initial
begin
$readmemh ("ram.ini", ram);
end
The data file has one word of data on each line. The data needs to be in the same order in which
the array was defined. That is, for “ram [0:255]” the data starts with address 0; for “ram [255:0]”
the data starts with address 255. The ram.ini file might start like this:
0A /* Address 0 */
23
5C
...
VHDL
In VHDL, initialize RAM with either signal declarations or variable declarations. Define an entity
with the same ports and architecture as the memory. Use this entity in either a signal or variable
statement with the initial values as shown below.
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For example, to initialize a RAM block named “ram,” define an entity such as:
entity ram_init is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
din : in std_logic_vector(7 downto 0);
we : in std_logic;
dout : out std_logic_vector(7 downto 0));
end;
architecture arch of ram_init is
type ram_init_arch is array(0 to 255)
of std_logic_vector (7 downto 0);
Then use the entity in a signal statement:
signal ram : ram_init_arch := (
"00001010",
"00100011",
"01011100",
...
others => (others => '0'));
Or use the entity in a variable statement:
variable ram : ram_init_arch := (
1 => "00001010",
...
others => (1=>'1', others => '0'));
Inferring ROM
To code ROM to be inferred, do the following:
Define the ROM with a case statement or equivalent if statements.
Assign constant values, all of the same width.
Assign values for at least 16 addresses or half of the address space, whichever is
greater. For example, if the address has 6 bits, the address space is 64 words, and at
least 32 of them must be assigned values.
To control how the ROM is implemented (with distributed or block ROM), consider adding
the syn_romstyle attribute. See syn_romstyle” on page 92.
module rom(data, addr);
output [3:0] data;
input [4:0] addr;
always @(addr) begin
case (addr)
0 : data = 'h4;
1 : data = 'h9;
2 : data = 'h1;
...
15 : data = 'h8;
16 : data = 'h1;
17 : data = 'h0;
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default : data = 'h0;
endcase
end
endmodule
Figure 4-9: ROM Inferred with Case Statement in Verilog
entity rom is
port (addr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(3 downto 0) );
end rom;
architecture behave of rom is
begin
process(addr)
begin
if addr = 0 then data <= "0100";
elsif addr = 1 then data <= "1001";
elsif addr = 2 then data <= "0001";
...
elsif addr = 15 then data <= "1000";
elsif addr = 16 then data <= "0001";
elsif addr = 17 then data <= "0000";
else data <= "0000";
end if;
end process;
end behave;
Figure 4-10: ROM Inferred with If Statement in VHDL
About Verilog Blocking Assignments
LSE support for Verilog blocking assignments to inferred RAM and ROM, such as
“ram[(addr)] = data;,” is limited to a single such assignment. Multiple blocking assignments, such
as you might use for dual-port RAM (see Figure 4-11), or a mix of blocking and non-blocking
assignments are not supported. Instead, use non-blocking assignments (<=). See Figure 4-12.
always @(posedge clka)
begin
if (write_ena)
ram[addra] = dina; // Blocking assignment A
douta = ram[addra];
end
always @(posedge clkb)
begin
if (write_enb)
ram[addrb] = dinb; // Blocking assignment B
doutb = ram[addrb];
end
Figure 4-11: Example of RAM with Multiple Blocking Assignments (Wrong)
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always @(posedge clka)
begin
if (write_ena)
ram[addra] <= dina;
douta <= ram[addra];
end
always @(posedge clkb)
begin
if (write_enb)
ram[addrb] <= dinb;
doutb <= ram[addrb];
end
Figure 4-12: Example Rewritten with Non-blocking Assignments (Right)
Inferring DSP Multipliers
LSE can infer the following types of multipliers and map them to MAC16+ blocks:
Multiplier
Multiply/Add (multiplier followed by an addition)
Multiply/Sub (multiplier followed by a subtraction)
Multiply/Accumulate (multiplier followed by an accumulator)
Inferring works with multipliers with 3 to 16-bit inputs.
All multiplier types can have any combination of input, output, and pipeline registers.
Control signals (clock, enable, and reset) for any registers in a multiplier must be shared by all the
registers. That is, there can only be one clock, one enable, and one reset signal in a given
multiplier.
To control how the multiplier is implemented (with logic or DSP), consider adding the
syn_multstyle attribute. See syn_multstyle on page 87.
The following sections show code written to infer different kinds of DSP multipliers with LSE.
Verilog Examples
module mult_unsign_7_6(a,b,c);
parameter A_WIDTH = 7;
parameter B_WIDTH = 6;
input unsigned [(A_WIDTH - 1):0] a;
input unsigned [(B_WIDTH - 1):0] b;
output unsigned [(A_WIDTH + B_WIDTH - 1):0] c;
assign c = a * b;
endmodule
Figure 4-13 : Basic Multiplier without Registers
module multaddsub_add_unsign_7_6(a,b,c,din);
parameter A_WIDTH = 7;
parameter B_WIDTH = 6;
input unsigned [(A_WIDTH - 1):0] a;
input unsigned [(B_WIDTH - 1):0] b;
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input unsigned [(A_WIDTH + B_WIDTH - 1):0] din;
output unsigned [(A_WIDTH + B_WIDTH - 1):0] c;
assign c = a * b + din;
endmodule
Figure 4-14: Multiply/Add without Registers
module multaddsub_sub_sign_ir_7_6(clk,a,b,din,c,rst,set);
parameter A_WIDTH = 7;
parameter B_WIDTH = 6;
input rst;
input set;
input clk;
input signed [(A_WIDTH - 1):0] a;
input signed [(B_WIDTH - 1):0] b;
input signed [(A_WIDTH + B_WIDTH - 1):0] din;
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
reg signed [(A_WIDTH - 1):0] reg_a;
reg signed [(B_WIDTH - 1):0] reg_b;
reg signed [(A_WIDTH + B_WIDTH - 1):0] reg_din;
assign c = reg_a * reg_b - reg_din;
always @(posedge clk)
begin
if(rst)
begin
reg_a <= 0;
reg_b <= 0;
reg_din <= 0;
end
else if(set)
begin
reg_a <= -1;
reg_b <= -1;
reg_din <= -1;
end
else
begin
reg_a <= a;
reg_b <= b;
reg_din <= din;
end
end
endmodule
Figure 4-15: Multiplier/Sub with Input Registers
module multacc_unsign_7_6(clk,a,b,c,set);
parameter A_WIDTH = 7;
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parameter B_WIDTH = 6;
input set;
input clk;
input unsigned [(A_WIDTH - 1):0] a;
input unsigned [(B_WIDTH - 1):0] b;
output unsigned [(A_WIDTH + B_WIDTH - 1):0] c;
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
if(set)
begin
reg_tmp_c <= 0;
end
else
begin
reg_tmp_c <= a * b + c;
end
end
endmodule
Figure 4-16 : Multiplier/Accumulator without Registers
VHDL Examples
entity m_07x06 is
generic (widtha : natural := 7;
widthb : natural := 6);
port (
ina : in std_logic_vector (0 to widtha - 1);
inb : in std_logic_vector (0 to widthb - 1);
mout : out std_logic_vector (0 to widtha+widthb - 1));
end m_07x06;
architecture rtl of m_07x06 is
begin
mout <= ina * inb ;
end rtl;
Figure 4-17 : Basic Multiplier without Registers
entity mult_add_07x06 is
generic (widtha : natural := 7;
widthb : natural := 6);
port (
ina : in std_logic_vector (widtha - 1 downto 0);
inb : in std_logic_vector (widthb - 1 downto 0);
mout : out std_logic_vector (widtha+widthb - 1 downto 0);
inc : in std_logic_vector (widtha+widthb - 1 downto 0)
);
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end mult_add_07x06;
architecture rtl of mult_add_07x06 is
begin
mout <= ina * inb + inc ;
end rtl;
Figure 4-18 : Multiply/Add without Registers
entity mult_sub_07x06_ir_r is
generic (widtha : natural := 7;
widthb : natural := 6);
port (
ina : in std_logic_vector (widtha - 1 downto 0);
inb : in std_logic_vector (widthb - 1 downto 0);
clk : in std_logic;
reset: in std_logic;
mout : out std_logic_vector (widtha+widthb - 1 downto 0);
inc : in std_logic_vector (widtha+widthb - 1 downto 0)
);
end mult_sub_07x06_ir_r;
architecture rtl of mult_sub_07x06_ir_r is
signal reg1_ina : std_logic_vector(widtha - 1 downto 0);
signal reg1_inb : std_logic_vector(widthb - 1 downto 0);
begin
mout <= reg1_ina * reg1_inb-inc;
process (clk,reset) begin
if(reset ='1') then
reg1_ina <= (others => '0');
reg1_inb <= (others => '0');
elsif rising_edge (clk) then
reg1_ina <= ina;
reg1_inb <= inb;
end if;
end process;
end rtl;
Figure 4-19 : Multiplier/Sub with Input Registers
entity multacc_07x06_up is
generic (widtha : natural := 7;
widthb : natural := 6);
port (
ina : in std_logic_vector (widtha - 1 downto 0);
inb : in std_logic_vector (widthb - 1 downto 0);
clk : in std_logic;
reset : in std_logic;
mout : out std_logic_vector (widtha+widthb - 1 downto 0)
);
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end multacc_07x06_up;
architecture rtl of multacc_07x06_up is
signal reg_mout:std_logic_vector(widtha+widthb-1 downto 0);
signal mout_s :std_logic_vector(widtha+widthb-1 downto 0);
begin
mout <= mout_s ;
mout_s <= reg_mout;
process (clk,reset) begin
if(reset ='1') then
reg_mout <= (others => '0');
elsif rising_edge (clk) then
reg_mout <= ina * inb + mout_s ;
end if;
end process;
end rtl;
Figure 4-20: Multiplier/Accumulator without Registers
Inferring I/O
To specify types of I/O ports, follow these models.
Verilog
Open Drain:
output <
port
>;
wire <
output_enable
>;
assign <
port
> = <
output_enable
> ? 1'b0 : 1'bz;
Bidirectional:
inout <
port
>;
wire <
output_enable
>;
wire <
output_driver
>;
wire <
input_signal
>;
assign <
port
> = <
output_enable
> ? <
output_driver
> : 1'bz;
assign <
input_signal
> = <
port
>;
VHDL
Tristate:
library ieee;
use ieee.std_logic_1164.all;
entity <tbuf> is
port (
<enable> : std_logic;
<input_sig> : in std_logic_vector (1 downto 0);
<output_sig> : out std_logic_vector (1 downto 0));
end tbuf2;
architecture <port> of <tbuf> is
begin
<output_sig> <= <input_sig> when <enable> = '1' else "ZZ";
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end;
Open Drain:
library ieee;
use ieee.std_logic_1164.all;
entity <
od
> is
port (
<
enable
> : std_logic;
<
output_sig
> : out std_logic_vector (1 downto 0));
end od2;
architecture <
port
> of <
od
> is
begin
<
output_sig
> <= "00" when <
enable
> = '1' else "ZZ";
end;
Bidirectional:
library ieee;
use ieee.std_logic_1164.all;
entity <
bidir
> is
port (
<
direction
> : std_logic;
<
input_sig
> : in std_logic_vector (1 downto 0);
<
output_sig
> : out std_logic_vector (1 downto 0);
<
bidir_sig
> : inout std_logic_vector (1 downto 0));
end bidir2;
architecture <
port
> of <
bidir
> is
begin
<
bidir_sig
> <= <
input_sig
> when <
direction
> = '0' else
"ZZ";
<
output_sig
> <= <
bidir_sig
>;
end;
Event Inside an Event
Do not code an event within another event such as shown below:
always begin :main
guess = 0;
@(posedge clk or posedge rst);
if (rst) disable main;
while(1) begin
while(!result ) begin
guess = 0;
while(!result ) begin
@(posedge clk or posedge rst);
if (rst) disable main;
end
@(posedge clk or posedge rst);
if (rst) disable main;
end
while(result) begin
guess = 1;
while(result) begin
@(posedge clk or posedge rst);
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if (rst) disable main;
end
@(posedge clk or posedge rst);
if (rst) disable main;
end
end
end
Figure 4-21: Event within an Event (Wrong)
HDL Attributes and Directives
This section describes the Synplify Lattice attributes and directives that are supported by LSE.
These attributes and directives are directly interpreted by the engine and influence the
optimization or structure of the output netlist. Traditional HDL attributes, such as UGROUP, are
also compatible with LSE and are passed into the netlist to direct place and route.
black_box_pad_pin
Directive. Specifies pins on a user-defined black-box component as I/O pads that are visible to
the environment outside of the black box. If there is more than one port that is an I/O pad, list the
ports inside double-quotes ("), separated by commas (,), and without enclosed spaces.
Verilog Syntaxobject /* synthesis syn_black_box black_box_pad_pin = "portList" */ ;
where portList is a spaceless, comma-separated list of the names of the ports on black boxes that
are I/O pads.
module BBDLHS(D,E,GIN,GOUT,PAD,Q)
/* synthesis syn_black_box black_box_pad_pin="GIN[2:0],Q"
*/;
Figure 4-22: Verilog Example
VHDL Syntax
attribute black_box_pad_pin of object : objectType is "portList" ;
where object is an architecture or component declaration of a black box. Data type is string;
portList is a spaceless, comma-separated list of the black-box port names that are I/O pads.
library ieee;
use ieee.std_logic_1164.all;
package my_components is
component BBDLHS
port (D: in std_logic;
E: in std_logic;
GIN : in std_logic_vector(2 downto 0);
Q : out std_logic );
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of BBDLHS : component is true;
attribute black_box_pad_pin : string;
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attribute black_box_pad_pin of BBDLHS : component is
"GIN(2:0),Q";
end package my_components;
Figure 4-23: VHDL Example
syn_black_box
Directive. Specifies that a module or component is a black box with only its interface defined for
synthesis. The contents of a black box cannot be optimized during synthesis. A module can be a
black box whether it is empty or not. This directive has an implicit Boolean value of 1 or true.
Verilog Syntax
object /* synthesis syn_black_box */ ;
where object is a module declaration.
module bl_box(out,data,clk) /* synthesis syn_black_box */;
Figure 4-24: Verilog Example
VHDL Syntax
attribute syn_black_box of object : objectType is true ;
where object is a component declaration, label of an instantiated component to define as a black
box, architecture, or component. Data type is Boolean.
architecture top of top-entity is
component ram4
port (myclk : in bit;
opcode : in bit_vector(2 downto 0);
a, b : in bit_vector(7 downto 0);
rambus : out bit_vector(7 downto 0) );
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of ram4: component is true;
Figure 4-25: VHDL Example
syn_encoding
Directive for VHDL designs. Defines how enumerated data types are implemented. The type of
implementation affects the performance and device utilization.
VHDL Syntax
attribute syn_encoding of object : objectType is "value" ;
Where object is an enumerated type and value is one of the following: default, sequential, onehot,
or gray.
package testpkg is
type mytype is (red, yellow, blue, green, white,
violet, indigo, orange);
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attribute syn_encoding : string;
attribute syn_encoding of mytype : type is "sequential";
end package testpkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.testpkg.all;
entity decoder is
port (sel : in std_logic_vector(2 downto 0);
color : out mytype );
end decoder;
architecture rtl of decoder is
begin
process(sel)
begin
case sel is
when "000" => color <= red;
when "001" => color <= yellow;
when "010" => color <= blue;
when "011" => color <= green;
when "100" => color <= white;
when "101" => color <= violet;
when "110" => color <= indigo;
when others => color <= orange;
end case;
end process;
end rtl;
Figure 4-26: VHDL Example
syn_hier
Attribute. Allows you to control the amount of hierarchical transformation that occurs across
boundaries on module or component instances during optimization.
syn_hier Values
The following value can be used for syn_hier:
hard Preserves the interface of the design unit with no exceptions. This attribute affects only the
specified design units.
object /* synthesis syn_hier = "value" */ ;
where object can be a module declaration and value can be any of the values described in
syn_hier Values. Check the attribute values to determine where to attach the attribute.
module top1 (Q, CLK, RST, LD, CE, D)
/* synthesis syn_hier = "hard" */;
Figure 4-27: Verilog Example
VHDL Syntax
attribute syn_hier of object : architecture is "value" ;
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where object is an architecture name and value can be any of the values described in syn_hier
Values. Check the attribute values to determine the level at which to attach the attribute.
architecture struct of cpu is
attribute syn_hier : string;
attribute syn_hier of struct: architecture is "hard";
Figure 4-28: VHDL Example
syn_keep
Directive. Keeps the specified net intact during optimization and synthesis.
Verilog Syntax
object /* synthesis syn_keep = 1 */ ;
where object is a wire or reg declaration. Make sure that there is a space between the object
name and the beginning of the comment slash (/).
module example2(out1, out2, clk, in1, in2);
output out1, out2;
input clk;
input in1, in2;
wire and_out;
wire keep1 /* synthesis syn_keep=1 */;
wire keep2 /* synthesis syn_keep=1 */;
reg out1, out2;
assign and_out=in1&in2;
assign keep1=and_out;
assign keep2=and_out;
always @(posedge clk)begin;
out1<=keep1;
out2<=keep2;
end
endmodule
Figure 4-29: Verilog Example
VHDL Syntax
attribute syn_keep of object : objectType is true ;
where object is a single or multiple-bit signal.
entity example2 is
port (in1, in2 : in bit;
clk : in bit;
out1, out2 : out bit );
end example2;
architecture rt1 of example2 is
attribute syn_keep : boolean;
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signal and_out, keep1, keep2: bit;
attribute syn_keep of keep1, keep2 : signal is true;
begin
and_out <= in1 and in2;
keep1 <= and_out;
keep2 <= and_out;
process(clk)
begin
if (clk'event and clk = '1') then
out1 <= keep1;
out2 <= keep2;
end if;
end process;
end rt1;
Figure 4-30: VHDL Example
syn_maxfan
Attribute. Overrides the default (global) fan-out guide for an individual input port, net, or register
output.
Verilog Syntax
object /* synthesis syn_maxfan = "value" */ ;
module test (registered_data_out, clock, data_in);
output [31:0] registered_data_out;
input clock;
input [31:0] data_in /* synthesis syn_maxfan=1000 */;
reg [31:0] registered_data_out /* synthesis syn_maxfan=1000
*/;
Figure 4-31: Verilog Example
VHDL Syntax
attribute syn_maxfan of object : objectType is "value" ;
entity test is
port (clock : in bit;
data_in : in bit_vector(31 downto 0);
registered_data_out: out bit_vector(31 downto 0)
);
attribute syn_maxfan : integer;
attribute syn_maxfan of data_in : signal is 1000;
Figure 4-32: VHDL Example
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syn_multstyle
Attribute. Specifies whether to use logic or DSP blocks. Multiply, multiply/add, and
multiply/accumulate blocks are automatically implemented as MAC16+ blocks when available
unless the syn_multstyle attribute is used.
The following values can be specified globally or on a module:
Logic Causes multiply, multiply/add, and multiply/accumulate blocks to be mapped
to logic.
DSP Causes multiply, multiply/add, and multiply/accumulate blocks to be mapped
to DSP blocks.
Verilog Syntax
object /* synthesis syn_multstyle = "string" */ ;
Where object is a multiply, multiply/add, and multiply/accumulate definition. The data type is
string.
module mult(a,b,c,r,en);
input [7:0] a,b;
output [15:0] r;
input [15:0] c;
input en;
wire [15:0] temp /* synthesis syn_multstyle="logic" */;
assign temp = a*b;
assign r = en ? temp: c;
endmodule
Figure 4-33: Verilog Example
VHDL Syntax
attribute syn_multstyle of object : objectType is "string" ;
Where object is a signal that defines a multiply, multiply/add, and multiply/accumulate block. The
data type is string.
library ieee ;
use ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
entity mult is
port (clk : in std_logic ;
a : in std_logic_vector(7 downto 0) ;
b : in std_logic_vector(7 downto 0) ;
c : out std_logic_vector(15 downto 0))
end mult ;
architecture rtl of mult is
signal mult_i : std_logic_vector(15 downto 0) ;
attribute syn_multstyle : string ;
attribute syn_multstyle of mult_i : signal is "logic" ;
begin
mult_i <= std_logic_vector(unsigned(a)*unsigned(b)) ;
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process(clk)
begin
if (clk'event and clk = '1') then
c <= mult_i ;
end if ;
end process
Figure 4-34 : VHDL Example
syn_noprune
Directive. Prevents instance optimization for black-box modules (including technology-specific
primitives) with unused output ports.
Verilog Syntax
object /* synthesis syn_noprune = 1 */ ;
where object is a module declaration or an instance. The data type is Boolean.
module top(a1,b1,c1,d1,y1,clk);
output y1;
input a1,b1,c1,d1;
input clk;
wire x2,y2;
reg y1;
syn_noprune u1(a1,b1,c1,d1,x2,y2) /* synthesis
syn_noprune=1 */;
always @(posedge clk)
y1<= a1;
endmodule
Figure 4-35: Verilog Example
VHDL Syntax
attribute syn_noprune of object : objectType is true ;
where the data type is boolean, and object is an architecture, a component, or a label of an
instantiated component.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (a1, b1 : in std_logic;
c1,d1,clk : in std_logic;
y1 :out std_logic );
end ;
architecture behave of top is
component noprune
port (a, b, c, d : in std_logic;
x,y : out std_logic );
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end component;
signal x2,y2 : std_logic;
attribute syn_noprune : boolean;
attribute syn_noprune of u1 : label is true;
begin
u1: noprune port map(a1, b1, c1, d1, x2, y2);
process begin
wait until (clk = '1') and clk'event;
y1 <= a1;
end process;
end;
Figure 4-36: VHDL Example
syn_pipeline
This attribute permits registers to be moved to improve timing. Depending on the criticality of the
path, the tool move the suitable output registers to the input side to improve timing. If there is no
candidate register identified for pipelining, this attribute will not be honored.
syn_pipeline attribute is applicable only for Timing and Balance mode optimization. The tool
ignores the attribute in Area mode optimization.
Verilog Syntax
object /* synthesis syn_pipeline = {1|0} */ ;
where object is a register declaration.
module pipeline (a, b, clk,r);
input [3:0] a,b;
input clk;
output [7:0] r;
reg [3:0] a_reg,b_reg;
reg [7:0] temp2/* synthesis syn_pipeline = 1 */;
reg [7:0] temp3;
wire [7:0] temp1;
assign temp1 = a_reg * b_reg;
always @(posedge clk)
begin
a_reg <= a;
b_reg <= b;
temp2 <= temp1;
temp3 <= temp2;
end
assign r = temp3;
endmodule
Figure 4-37 : Verilog Example
VHDL Syntax
attribute syn_pipeline of object : objectType is {true|false} ;
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library ieee ;
use ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity pipeline is
port (clk : in std_logic ;
a : in std_logic_vector(3 downto 0) ;
b : in std_logic_vector(3 downto 0) ;
r : out std_logic_vector(7 downto 0) );
end pipeline ;
architecture rtl of pipeline is
signal a_reg : std_logic_vector(3 downto 0) ;
signal b_reg : std_logic_vector(3 downto 0) ;
signal temp1 : std_logic_vector(7 downto 0) ;
signal temp2 : std_logic_vector(7 downto 0) ;
signal temp3 : std_logic_vector(7 downto 0) ;
attribute syn_pipeline : string ;
attribute syn_pipeline of temp2 : signal is "true" ;
begin
process(clk)
begin
if (clk'event and clk = '1') then
temp1 <= a_reg * b_reg;
a_reg <= a;
b_reg <= b;
temp2 <= temp1;
temp3 <= temp2;
r <= temp3;
end if ;
end process ;
end rtl ;
Figure 4-38 : VHDL Example
syn_preserve
Directive. Prevents sequential optimization such as constant propagation, inverter push-through,
and FSM extraction.
Verilog Syntax
object /* synthesis syn_preserve = 1 */ ;
where object is a register definition signal or a module.
module syn_preserve (out1,out2,clk,in1,in2)/* synthesis
syn_preserve=1 */;
output out1, out2;
input clk;
input in1, in2;
reg out1;
reg out2;
reg reg1;
reg reg2;
always@ (posedge clk)begin
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reg1 <= in1 &in2;
reg2 <= in1&in2;
out1 <= !reg1;
out2 <= !reg1 & reg2;
end
endmodule
Figure 4-39: Verilog Example
VHDL Syntax
attribute syn_preserve of object : objectType is true ;
where object is an output port or an internal signal that holds the value of a state register or
architecture.
library ieee;
use ieee.std_logic_1164.all;
entity simpledff is
port (q : out std_logic_vector(7 downto 0);
d : in std_logic_vector(7 downto 0);
clk : in std_logic );
-- Turn on flip-flop preservation for the q output
attribute syn_preserve : boolean;
attribute syn_preserve of q : signal is true;
end simpledff;
architecture behavior of simpledff is
begin
process(clk)
begin
if rising_edge(clk) then
-- Notice the continual assignment of "11111111" to q.
q <= (others => '1');
end if;
end process;
end behavior;
Figure 4-40: VHDL Example
syn_ramstyle
Attribute. The syn_ramstyle attribute specifies the implementation to use for an inferred RAM.
You apply syn_ramstyle globally to a module or to a RAM instance. To turn off RAM inference,
set its value to registers.
The following values can be specified globally or on a module or RAM instance:
registers Causes an inferred RAM to be mapped to registers (flip-flops and logic) rather
than the technology-specific RAM resources.
block_ram Causes the RAM to be implemented using the dedicated RAM resources. If
your RAM resources are limited, you can use this attribute to map additional RAMs to
registers instead of the dedicated or distributed RAM resources.
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no_rw_check (some modes, but all technologies). You cannot specify this value alone.
Without no_rw_check, the synthesis tool inserts bypass logic around the RAM to prevent
the mismatch. If you know your design does not read and write to the same address
simultaneously, use no_rw_check to eliminate bypass logic. Use this value only when
you cannot simultaneously read and write to the same RAM location and you want to
minimize overhead logic.
Verilog Syntax
object /* synthesis syn_ramstyle = "string" */ ;
where object is a register definition (reg) signal. The data type is string.
module ram4 (datain,dataout,clk);
output [31:0] dataout;
input clk;
input [31:0] datain;
reg [7:0] dataout[31:0] /* synthesis
syn_ramstyle="block_ram" */;
Figure 4-41: Verilog Example
VHDL Syntax
attribute syn_ramstyle of object : objectType is "string" ;
where object is a signal that defines a RAM or a label of a component instance. Data type is
string.
library ieee;
use ieee.std_logic_1164.all;
entity ram4 is
port (d : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(2 downto 0);
we : in std_logic;
clk : in std_logic;
ram_out : out std_logic_vector(7 downto 0) );
end ram4;
library synplify;
architecture rtl of ram4 is
type mem_type is array (127 downto 0) of std_logic_vector
(7 downto 0);
signal mem : mem_type; -- mem is the signal that defines
the RAM
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";
Figure 4-42: VHDL Example
syn_romstyle
Attribute. Allows you to implement ROM architectures using dedicated or distributed ROM. Infer
ROM architectures using a CASE statement in your code.
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For the synthesis tool to implement a ROM, at least half of the available addresses in the CASE
statement must be assigned a value. For example, consider a ROM with six address bits (64
unique addresses). The case statement for this ROM must specify values for at least 32 of the
available addresses. You can apply the syn_romstyle attribute globally to the design by adding
the attribute to the module or entity.
The following values can be specified globally on a module or ROM instance:
auto (default) Allows the synthesis tool to chose the best implementation to meet the
design requirements for speed, size, and so on.
logic Causes the ROM to be implemented using logic cells.
BRAM Causes the ROM to be implemented using the dedicated ROM resources. If
your ROM resources are limited, you can use this attribute to map additional ROM to
registers instead of the dedicated or distributed RAM resources.
Verilog Syntax
object /* syn_romstyle = "auto | logic | BRAM" */ ;
reg [8:0] z /* synthesis syn_romstyle = "BRAM" */;
Figure 4-43: Verilog Example
VHDL Syntax
attribute syn_romstyle of object : object_type is "block_rom | logic" ;
signal z : std_logic_vector(8 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of z : signal is "logic";
Figure 4-44: VHDL Example
syn_use_carry_chain
Attribute. Used to turn on or off the carry chain implementation for adders.
Verilog Syntax
object synthesis syn_use_carry_chain = {1 | 0} */ ;
Verilog Example
To use this attribute globally, apply it to the module.
module test (a, b, clk, rst, d) /* synthesis
syn_use_carry_chain = 1 */;
VHDL Syntax
attribute syn_use_carry_chain of object : objectType is true | false ;
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architecture archtest of test is
signal temp : std_logic;
signal temp1 : std_logic;
signal temp2 : std_logic;
signal temp3 : std_logic;
attribute syn_use_carry_chain : boolean;
attribute syn_use_carry_chain of archtest : architecture is
true;
Figure 4-45: VHDL Example
syn_useioff
Attribute. Overrides the default behavior to pack registers into I/O pad cells based on timing
requirements for the target Lattice families. Attribute syn_useioff is Boolean-valued: 1 enables
(default) and 0 disables register packing. You can place this attribute on an individual register or
port or apply it globally. When applied globally, the synthesis tool packs all input, output, and I/O
registers into I/O pad cells. When applied to a register, the synthesis tool packs the register into
the pad cell; and when applied to a port, it packs all registers attached to the port into the pad
cell.
The syn_useioff attribute can be set on the following ports:
top-level port
register driving the top-level port
lower-level port, if the register is specified as part of the port declaration
Verilog Syntax
object synthesis syn_useioff = {1 | 0} */ ;
Verilog Example
To use this attribute globally, apply it to the module. To use this attribute on individual ports, apply
it to individual port declarations.
module test (a, b, clk, rst, d) /* synthesis syn_useioff =
1 */;
Figure 4-46: Verilog Example Applied Globally
module test (a, b, clk, rst, d);
input a;
input b /* synthesis syn_useioff = 1 */;
Figure 4-47: Verilog Example Applied to a Port
VHDL Syntax
attribute syn_useioff of object : objectType is true | false ;
architecture archtest of test is
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signal temp : std_logic;
signal temp1 : std_logic;
signal temp2 : std_logic;
signal temp3 : std_logic;
attribute syn_useioff : boolean;
attribute syn_useioff of archtest : architecture is true;
Figure 4-48: VHDL Example
Synthesis Macro
Use this text macro along with the Verilog `ifdef compiler directive to conditionally exclude part of
your Verilog code from being synthesized. The most common use of the synthesis macro is to
avoid synthesizing stimulus that only has meaning for logic simulation. The synthesis macro is
defined so that the statement `ifdef synthesis is true. The statements in the `ifdef branch are
compiled; the stimulus statements in the `else branch are ignored. Because Verilog simulators do
not recognize a synthesis macro, the compiler for your simulator will use the stimulus in the `else
branch.
module top (a,b,c);
input a,b;
output c;
`ifdef synthesis
assign c = a & b;
`else
assign c = a | b;
`endif
Endmodule
Figure 4-49: Verilog Example
translate_off/translate_on
Directive. Allows you to synthesize designs originally written for use with other synthesis tools
without needing to modify source code. All source code that is between these two directives is
ignored during synthesis.
Verilog Syntax
/* pragma translate_off */
/* pragma translate_on */
module real_time (ina, inb, out);
input ina, inb;
output out;
/* pragma translate_off */
realtime cur_time;
/* pragma translate_on */
assign out = ina & inb;
endmodule
Figure 4-50: Verilog Example
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VHDL Syntax
pragma translate_off
pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port (a, b, cin:in std_logic;
sum, cout:out std_logic );
end adder;
architecture behave of adder is
signal a1:std_logic;
--pragma translate_off
constant a1:std_logic:='0';
--pragma translate_on
begin
sum <= (a xor b xor cin);
cout <= (a and b) or (a and cin) or (b and cin); end
behave;
Figure 4-51: VHDL Example
Synopsys Design Constraints (SDC)
This section describes the Synopsys Design Constraint (SDC) language elements for timing-
driven synthesis that are supported by the Lattice Synthesis Engine (LSE). The SDC constraints
will drive optimization of the design if LSE’s Optimization Goal is set for either timing or Balanced
in the active strategy file. Furthermore, in Timing or Balanced Optimization Goal, the SDC
constraints are forward annotated to post P&R’s Static Timing Analysis (STA) software, thus
saving the need for users to create another set of timing constraints.
In the case of LSE’s optimization Goal is set to Area, SDC constraints will be ignored and not
forward annotated to STA. To enter timing constraints for STA, refer to Timing Constraints and
Static Timing Analysis”.
To add SDC constraints to LSE, create the .sdc file using a text editor and add the file to
Synthesis Tool > Synthesis Input Files > Constraint Files. Do not use Timing Constraints Editor
as it used to enter timing constraints for STA for use with backend processes.
The current LSE timing does not take the PLL/DLL frequency or phase shift properties into
account. It also does not model the different IO_TYPE in the PIO. Therefore, it is necessary to
adjust the timing constraint. For example, you can explicitly include a timing constraint on the PLL
outputs with the phase-shift property.
create_clock
Creates a clock and defines its characteristics.
Note
In LSE timing, interclock domain paths are always blocked for create_clock. However, the interclock domain
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path is still valid for constraints such as set_false_path and set_multicycle_path.
Syntax
create_clock -name name -period period_value source
Arguments
-name name
Specifies the name of the clock constraint, which can be referenced by other constraints.
-period period_value
Specifies the clock period in nanoseconds. The value you specify is the minimum time over which
the clock waveform repeats. The period_value must be greater than zero.
source
Specifies the source of the clock constraint. The source can be ports or nets (signals) in the
design. If you specify a clock constraint on a port or net that already has a clock, the new clock
will replace the existing one. Only one source is accepted. Wildcards are accepted as long as the
resolution shows one port or net.
Example
The following example creates two clocks on ports CK1 and CK2 with a period of 6:
create_clock -name my_user_clock -period 6 [ get_ports CK1
]
create_clock -name my_other_user_clock period 6 [get_nets
CK2]
set_false_path
Identifies paths that are considered false and excluded from timing analysis.
Syntax
set_false_path [-from port or cell] [-to port or cell]
or
set_false_path [-through through_net]
Arguments
-from port or cell
Specifies the timing path start point. A valid timing starting point is a clock, a primary input, a
combinational logic cell, or a sequential cell (clock-pin).
-to port or cell
Specifies the timing path end point. A valid timing end point is a primary output, a combinational
logic cell, or a sequential cell (data-pin).
-through through_net
Specifies a net through which the paths should be blocked.
Examples
The following example specifies all paths from clock pins of the registers in clock domain clk1 to
data pins of a specific register in clock domain clk2 as false paths:
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set_false_path from [get_ports clk1] to [get_cells reg_2]
The following example specifies all paths through the net UO/sigA as false:
set_false_path through [get_nets UO/sigA]
set_input_delay
Defines the arrival time of an input relative to a clock.
Syntax
set_input_delay delay_value -clock clock_ref input_port
Arguments
delay_value
Specifies the arrival time in nanoseconds that represents the amount of time for which the signal
is available at the specified input after a clock edge.
-clock clock_ref
Specifies the clock reference to which the specified input delay is related. This is a mandatory
argument.
input_port
Provides one or more input ports in the current design to which delay_value is assigned. You can
also use the keyword “all_inputs” to include all input ports.
Example
The following example sets an input delay of 1.2 ns for port data1 relative to the rising edge of
CLK1:
set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports
data1]
set_max_delay
Specifies the maximum delay for the timing paths.
Syntax
set_max_delay delay_value [-from port or cell] [-to port or cell]
Arguments
delay_value
Specifies a floating point number in nanoseconds that represents the required maximum delay
value for specified paths.
If the path ending point is on a sequential device, the tool includes library setup time in the
computed delay.
-from port or cell
Specifies the timing path start point. A valid timing start point is a clock, a primary input, a
combinational logic cell, or a sequential cell (clock pin).
-to port or cell
Specifies the timing path end point. A valid timing end point is a primary output, a combinational
logic cell, or a sequential cell (data pin).
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Examples
The following example sets a maximum delay by constraining all paths from ff1a:CLK to ff2e:D
with a delay less than 5 ns:
set_max_delay 5 -from [get_cells ff1a] -to [get_cells ff2e]
set_multicycle_path
Defines a path that takes multiple clock cycles.
Syntax
set_multicycle_path ncycles [-from net or cell] [-to net or cell]
Arguments
ncycles
Specifies a value that represents the number of cycles the data path must have for setup check.
The value is relative to the ending point clock and is defined as the delay required for arrival at
the ending point.
-from net or cell
Specifies the timing path start point. A valid timing start point is a sequential cell (clock pin) or a
clock net (signal). You can also use the keyword “all_registers to include all registers’ clock
inputs.
-to net or cell
Specifies the timing path end point. A valid timing end point is a sequential cell (data-pin) or a
clock-net (signal). You can also use the keyword all_registers” to include all registers data
inputs.
Example
The following example sets all paths between reg1 and reg2 to 3 cycles for setup check. Hold
check is measured at the previous edge of the clock at reg2.
set_multicycle_path 3 from [get_cells reg1] to [get_cells
reg2]
set_output_delay
Defines the output delay of an output relative to a clock.
Syntax
set_output_delay delay_value -clock clock_ref output_port
Arguments
delay_value
Specifies the amount of time from a “clock_ref” to a primary “output_port.”
-clock clock_ref
Specifies the clock reference to which the specified output delay is related. This is a mandatory
argument.
output_port
Provides one or more (by wildcard) output ports in the current design to which delay_value is
assigned. You can also use the keyword “all_outputs” to include all output ports.
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Example
The following example sets an output delay of 1.2 ns for all outputs relative to clki_c:
set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports
OUT1]
set_output_delay 1.2 -clock [get_clocks CLK1] [all_outputs]
Chapter 5 iCEcube2 Physical Implementation Tools
Overview
The iCEcube2 Physical Implementation software constitutes the second half of the iCE design
flow, and is used to implement the design on the iCE FPGA devices. The inputs to Physical
Implementation Tools are an EDIF netlist and SDC constraint files.
In addition, the software supports additional Timing Constraints in SDC format, as well as
Physical Constraints in PCF format, that can be passed directly to the Physical Implementation
tools.
The outputs are the device configuration files used to program the device, and Verilog/VHDL and
SDF files for timing simulation in an industry standard simulator.
In addition, the software also provides several powerful and useful back-end tools such as a
Timing Constraints Editor (SDC), a Floor Planner, a Pin Constraints Editor, a device Package
Viewer, a Power Estimator, and a Static Timing Analyzer.
Tools for Physical Implementation
In addition to the Placer and the Router, iCEcube2 provides the following tools to appropriately
constrain, analyze/verify the design and program the target device.
1. Timing Constraint Editor (TCE): This tool allows the user to specify timing constraints in the
SDC format, which can be used to constrain the Placer and Router. Additional details on
using TCE are provided in a subsequent chapter.
2. Timing Analysis: The Static Timing Analysis tool provides design performance analysis, to
help identify critical paths in the design. The usage of this tool is explained in subsequent
chapters.
3. Physical Constraints Editor / Floor Plan Viewer: This tool has a dual function: It allows the
user to create physical constraints after importing the design, which are honored by the
Placer. After the Placer has run, this tool allows the user to view the logic and pin placement
before final bitmap generation. At this stage of the design flow, it allows the user to modify the
placement of logic cells, IO cells and RAM cells, before final routing.
4. Package View: This utility allows the user to view the pin assignments before final bitmap
generation. It also allows the user to modify the pin placement.
5. Pin Attributes Editor: This tool allows the user to view and configure pin properties, such as
pin location, the IO standard and the optional pin Pull Up resistor.
6. Power Estimator: This utility assists users in estimating device power for a given design via
a spreadsheet listing the various utilized resources of the device, the estimated maximum
operating frequency, the core voltage etc.
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7. Bitmap Generator: To support device programming, the iCEcube2 Physical Implementation
Tools include a utility for generating device configuration data, referred to as a bitmap.
8. Device Programmer: The iCEcube2 Physical Implementation Tools also include a utility for
programming the iCE FPGA device
Placing and Routing the Design
Once the synthesized design is loaded into the iCEcube2 Physical Implementation software, the
next step is to place and route the design. The placement and routing process is started by
clicking on the Run Placer and Run Router icons respectively. Note that if the placer/router is yet
to be run, there is a green arrow next to the appropriate icon. Upon successful completion of the
operation, the green arrow changes into a green check mark.
Changing the Placer Options
The placer options can be changed by selecting Tool > Tool Options > Placer. The options are
shown in Figure 5-1.
1. Effort Level: Placer supports three effort levels for placement Optimization. Standard,
Medium and high.
2. Auto Lut Cascade: This option is ON by default and the placer cascades four input LUTs
via dedicated LUT output routing to implement larger logic functions in iCE40 Devices.
3. Auto Ram Cascade: This option is ON by default and the placer cascades the 4K RAM
Blocks to implement larger Block RAM in iCE40 Devices.
4. Power Driven: Enable this option to run the placer in power driven optimization mode.
5. Area Driven: Enable this option to pack for dense area. Default is for timing.
Figure 5-1: Placer Tool Options
Changing the Router Options
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The router options can be changed by selecting Tool > Tool Options > Router. Note that all
changes to the options as shown in Figure 5-2 require the router to be rerun. The options are as
follows:
1. Timing Driven: The router algorithms try to honor the timing constraints specified by the
user.
2. Pin Permutation: This option is ON by default, and aids the router in making intelligent
decisions when routing signals to the inputs of the Look-Up table Logic cell.
Figure 5-2 : Router Options
Floor Planner
The device Floor Plan (Figure 5-3) can be viewed by selecting Tool > Floor Planner from the
Tool menu, by or clicking the Floor Planner icon in the Tools tree in the Project Name pane.
The subsequent details in this section pertain to the viewing capabilities of the Floor Planner.
The Floor Planner also allows the user to manually modify the placement of logic (Logic Cells and
RAM blocks) as well as IO pins. Additional details on the creation/application of Physical
Constraints are provided in 0
Physical Constraints in iCEcube2.
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Figure 5-3 : The Floor Planner
Viewing the Device Floor Plan
The Floor Planner displays the placement of the netlist on the selected device, as shown in
Figure 5-4 with utilized resources depicted in green.
The IO Tiles are depicted in grey, and are located along the periphery of the chip. Each IO Tile
has two or three IO Pin locations. Non-bonded IOs i.e. an IO cell that does not bond out to a pin
on the device package is unusable. Such non-bonded IOs are depicted in a dark shade of grey.
The RAM block locations are depicted by the two brown columns, running vertically through the
Floor Plan. Utilized RAM blocks are depicted in green, and the corresponding RAM Tile in a dark
brown.
The Logic Tiles are depicted by the blue tiles, and contain eight rectangular blocks, each
signifying a Logic Cell (4-input LUT, a flip-flop, and Carry logic), and a small square in the bottom-
left corner of each tile, signifying the Carry-In from the Logic Tile directly below it.
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The layout of the cells follows an (X, Y, Z) co-ordinate numbering scheme, with the origin at the
bottom-left corner of the device. Mousing over the logic and IO tiles displays the location co-
ordinates of the tile as a two dimensional (X, Y) co-ordinate location. Since each IO and Logic tile
has multiple IO and logic cells respectively, the IO and Logic cells within a tile are identified by the
Z co-ordinate, resulting in a (X, Y, Z) triplet that uniquely identifies each cell.
As mentioned above, the Logic Cell has multiple resources (LUT, flip-flop, Carry logic). It is
possible to view the utilized portions by performing a right-mouse-click > Show Content on a
selected Logic Cell, as displayed in Figure 5-4. This brings up a window that shows the portions
that have logic placed within. An example of a Logic Cell which contains a used LUT and flip-flop
but an unused Carry-In is displayed in Figure 5-5 below.
Figure 5-4: Viewing the utilized portions of a Logic Cell
Figure 5-5: Example of the utilized portions of a Logic Cell
The View > Zoom In and View > Zoom Out menu items zoom in and out of the Floor Plan
respectively. Mousing over a cell or net also displays instance information for that cell or net.
A World View pane provides a view of the entire Floor Plan, and can be used to navigate the
floor plan when the Zoom In factor is high.
The placed Logic tiles in the Floor Planner have the following Color conventions. White color
represents an empty cell; Green color represents a placed cell. When you select a particular cell
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it would be highlighted in Yellow. A cell which was locked at a location would be highlighted in
green color with red checks. Also, a Lock symbol would be shown on the cell.
Navigating the Design Placement
Through the Floor Plan View, the user can trace the connectivity of an implemented design. This
can be achieved via a combination of the Logic/IO/RAM/Net pane and the Fan-in/Fan-out
functionality available for each used resource.
The Logic/IO/RAM/Net pane displays the used resources on the device. Selection of a node
within this pane highlights the corresponding cell/net in the Floor Plan view.
The right-button of the mouse brings up a context sensitive menu specific to the particular type of
resource selected. This menu allows the user to Search for specific nodes, or to Sort the listed
nodes. As an example, the menu for Logic Cells is displayed in Figure 5-6.
Figure 5-6: Invoking the Sort and Search functionality in the Logic/IO/RAM/Net pane
Selecting the Sort by Name option sorts the Logic instances based on instance names as shown
below
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Figure 5-7: Sort by Name Option
Selecting Sort by Cell option sorts the p