Ngspice User Manual V27

• I Ngspice User Manual
  • 1 Introduction
    • 1.1 Simulation Algorithms
      • 1.1.1 Analog Simulation
      • 1.1.2 Digital Simulation
      • 1.1.3 Mixed-Mode Simulation
      • 1.1.4 Mixed-Level Simulation
    • 1.2 Supported Analyses
      • 1.2.1 DC Analyses
      • 1.2.2 AC Small-Signal Analysis
      • 1.2.3 Transient Analysis
      • 1.2.4 Pole-Zero Analysis
      • 1.2.5 Small-Signal Distortion Analysis
      • 1.2.6 Sensitivity Analysis
      • 1.2.7 Noise Analysis
      • 1.2.8 Periodic Steady State Analysis
    • 1.3 Analysis at Different Temperatures
    • 1.4 Convergence
      • 1.4.1 Voltage convergence criterion
      • 1.4.2 Current convergence criterion
      • 1.4.3 Convergence failure
  • 2 Circuit Description
    • 2.1 General Structure and Conventions
      • 2.1.1 Input file structure
      • 2.1.2 Circuit elements (device instances)
      • 2.1.3 Some naming conventions
    • 2.2 Basic lines
      • 2.2.1 .TITLE line
      • 2.2.2 .END Line
      • 2.2.3 Comments
      • 2.2.4 End-of-line comments
    • 2.3 .MODEL Device Models
    • 2.4 .SUBCKT Subcircuits
      • 2.4.1 .SUBCKT Line
      • 2.4.2 .ENDS Line
      • 2.4.3 Subcircuit Calls
    • 2.5 .GLOBAL
    • 2.6 .INCLUDE
    • 2.7 .LIB
    • 2.8 .PARAM Parametric netlists
      • 2.8.1 .param line
      • 2.8.2 Brace expressions in circuit elements:
      • 2.8.3 Subcircuit parameters
      • 2.8.4 Symbol scope
      • 2.8.5 Syntax of expressions
      • 2.8.6 Reserved words
      • 2.8.7 Alternative syntax
    • 2.9 .FUNC
    • 2.10 .CSPARAM
    • 2.11 .TEMP
    • 2.12 .IF Condition-Controlled Netlist
    • 2.13 Parameters, functions, expressions, and command scripts
      • 2.13.1 Parameters
      • 2.13.2 Nonlinear sources
      • 2.13.3 Control commands, Command scripts
  • 3 Circuit Elements and Models
    • 3.1 General options and information
      • 3.1.1 Paralleling devices with multiplier m
      • 3.1.2 Technology scaling
      • 3.1.3 Model binning
      • 3.1.4 Initial conditions
    • 3.2 Elementary Devices
      • 3.2.1 Resistors
      • 3.2.2 Semiconductor Resistors
      • 3.2.3 Semiconductor Resistor Model (R)
      • 3.2.4 Resistors, dependent on expressions (behavioral resistor)
      • 3.2.5 Capacitors
      • 3.2.6 Semiconductor Capacitors
      • 3.2.7 Semiconductor Capacitor Model (C)
      • 3.2.8 Capacitors, dependent on expressions (behavioral capacitor)
      • 3.2.9 Inductors
      • 3.2.10 Inductor model
      • 3.2.11 Coupled (Mutual) Inductors
      • 3.2.12 Inductors, dependent on expressions (behavioral inductor)
      • 3.2.13 Capacitor or inductor with initial conditions
      • 3.2.14 Switches
      • 3.2.15 Switch Model (SW/CSW)
  • 4 Voltage and Current Sources
    • 4.1 Independent Sources for Voltage or Current
      • 4.1.1 Pulse
      • 4.1.2 Sinusoidal
      • 4.1.3 Exponential
      • 4.1.4 Piece-Wise Linear
      • 4.1.5 Single-Frequency FM
      • 4.1.6 Amplitude modulated source (AM)
      • 4.1.7 Transient noise source
      • 4.1.8 Random voltage source
      • 4.1.9 External voltage or current input
      • 4.1.10 Arbitrary Phase Sources
    • 4.2 Linear Dependent Sources
      • 4.2.1 Gxxxx: Linear Voltage-Controlled Current Sources (VCCS)
      • 4.2.2 Exxxx: Linear Voltage-Controlled Voltage Sources (VCVS)
      • 4.2.3 Fxxxx: Linear Current-Controlled Current Sources (CCCS)
      • 4.2.4 Hxxxx: Linear Current-Controlled Voltage Sources (CCVS)
      • 4.2.5 Polynomial Source Compatibility
  • 5 Non-linear Dependent Sources (Behavioral Sources)
    • 5.1 Bxxxx: Nonlinear dependent source (ASRC)
      • 5.1.1 Syntax and usage
      • 5.1.2 Special B-Source Variables time, temper, hertz
      • 5.1.3 par('expression')
      • 5.1.4 Piecewise Linear Function: pwl
    • 5.2 Exxxx: non-linear voltage sourceTo get this functionality, the compatibility mode has to be set in spinit or .spiceinit by set ngbehavior=all.
      • 5.2.1 VOL
      • 5.2.2 VALUE
      • 5.2.3 TABLE
      • 5.2.4 POLY
      • 5.2.5 LAPLACE
    • 5.3 Gxxxx: non-linear current sourceTo get this functionality, the compatibility mode has to be set in spinit or .spiceinit by set ngbehavior=all.
      • 5.3.1 CUR
      • 5.3.2 VALUE
      • 5.3.3 TABLE
      • 5.3.4 POLY
      • 5.3.5 LAPLACE
      • 5.3.6 Example
    • 5.4 Debugging a behavioral source
  • 6 Transmission Lines
    • 6.1 Lossless Transmission Lines
    • 6.2 Lossy Transmission Lines
      • 6.2.1 Lossy Transmission Line Model (LTRA)
    • 6.3 Uniform Distributed RC Lines
      • 6.3.1 Uniform Distributed RC Model (URC)
    • 6.4 KSPICE Lossy Transmission Lines
      • 6.4.1 Single Lossy Transmission Line (TXL)
      • 6.4.2 Coupled Multiconductor Line (CPL)
  • 7 Diodes
    • 7.1 Junction Diodes
    • 7.2 Diode Model (D)
    • 7.3 Diode Equations
  • 8 BJTs
    • 8.1 Bipolar Junction Transistors (BJTs)
    • 8.2 BJT Models (NPN/PNP)
  • 9 JFETs
    • 9.1 Junction Field-Effect Transistors (JFETs)
    • 9.2 JFET Models (NJF/PJF)
      • 9.2.1 JFET level 1 model with Parker Skellern modification
      • 9.2.2 JFET level 2 Parker Skellern model
  • 10 MESFETs
    • 10.1 MESFETs
    • 10.2 MESFET Models (NMF/PMF)
      • 10.2.1 Model by Statz e.a.
      • 10.2.2 Model by Ytterdal e.a.
      • 10.2.3 hfet1
      • 10.2.4 hfet2
  • 11 MOSFETs
    • 11.1 MOSFET devices
    • 11.2 MOSFET models (NMOS/PMOS)
      • 11.2.1 MOS Level 1
      • 11.2.2 MOS Level 2
      • 11.2.3 MOS Level 3
      • 11.2.4 MOS Level 6
      • 11.2.5 Notes on Level 1-6 models
      • 11.2.6 BSIM Models
      • 11.2.7 BSIM1 model (level 4)
      • 11.2.8 BSIM2 model (level 5)
      • 11.2.9 BSIM3 model (levels 8, 49)
      • 11.2.10 BSIM4 model (levels 14, 54)
      • 11.2.11 EKV model
      • 11.2.12 BSIMSOI models (levels 10, 58, 55, 56, 57)
      • 11.2.13 SOI3 model (level 60)
      • 11.2.14 HiSIM models of the University of Hiroshima
  • 12 Mixed-Mode and Behavioral Modeling with XSPICE
    • 12.1 Code Model Element & .MODEL Cards
      • 12.1.1 Syntax
      • 12.1.2 Examples
      • 12.1.3 Search path for file input
    • 12.2 Analog Models
      • 12.2.1 Gain
      • 12.2.2 Summer
      • 12.2.3 Multiplier
      • 12.2.4 Divider
      • 12.2.5 Limiter
      • 12.2.6 Controlled Limiter
      • 12.2.7 PWL Controlled Source
      • 12.2.8 Filesource
      • 12.2.9 multi_input_pwl block
      • 12.2.10 Analog Switch
      • 12.2.11 Zener Diode
      • 12.2.12 Current Limiter
      • 12.2.13 Hysteresis Block
      • 12.2.14 Differentiator
      • 12.2.15 Integrator
      • 12.2.16 S-Domain Transfer Function
      • 12.2.17 Slew Rate Block
      • 12.2.18 Inductive Coupling
      • 12.2.19 Magnetic Core
      • 12.2.20 Controlled Sine Wave Oscillator
      • 12.2.21 Controlled Triangle Wave Oscillator
      • 12.2.22 Controlled Square Wave Oscillator
      • 12.2.23 Controlled One-Shot
      • 12.2.24 Capacitance Meter
      • 12.2.25 Inductance Meter
      • 12.2.26 Memristor
      • 12.2.27 2D table model
      • 12.2.28 3D table model
    • 12.3 Hybrid Models
      • 12.3.1 Digital-to-Analog Node Bridge
      • 12.3.2 Analog-to-Digital Node Bridge
      • 12.3.3 Controlled Digital Oscillator
      • 12.3.4 Node bridge from digital to real with enable
      • 12.3.5 A Z**-1 block working on real data
      • 12.3.6 A gain block for event-driven real data
      • 12.3.7 Node bridge from real to analog voltage
    • 12.4 Digital Models
      • 12.4.1 Buffer
      • 12.4.2 Inverter
      • 12.4.3 And
      • 12.4.4 Nand
      • 12.4.5 Or
      • 12.4.6 Nor
      • 12.4.7 Xor
      • 12.4.8 Xnor
      • 12.4.9 Tristate
      • 12.4.10 Pullup
      • 12.4.11 Pulldown
      • 12.4.12 D Flip Flop
      • 12.4.13 JK Flip Flop
      • 12.4.14 Toggle Flip Flop
      • 12.4.15 Set-Reset Flip Flop
      • 12.4.16 D Latch
      • 12.4.17 Set-Reset Latch
      • 12.4.18 State Machine
      • 12.4.19 Frequency Divider
      • 12.4.20 RAM
      • 12.4.21 Digital Source
      • 12.4.22 LUT
      • 12.4.23 General LUT
    • 12.5 Predefined Node Types for event driven simulation
      • 12.5.1 Digital Node Type
      • 12.5.2 Real Node Type
      • 12.5.3 Int Node Type
      • 12.5.4 (Digital) Input/Output
  • 13 Verilog A Device models
    • 13.1 Introduction
    • 13.2 adms
    • 13.3 How to integrate a Verilog-A model into ngspice
      • 13.3.1 How to setup a *.va model for ngspice
      • 13.3.2 Adding admsXml to your build environment
  • 14 Mixed-Level Simulation (ngspice with TCAD)
    • 14.1 Cider
    • 14.2 GSS, Genius
  • 15 Analyses and Output Control (batch mode)
    • 15.1 Simulator Variables (.options)
      • 15.1.1 General Options
      • 15.1.2 DC Solution Options
      • 15.1.3 AC Solution Options
      • 15.1.4 Transient Analysis Options
      • 15.1.5 ELEMENT Specific options
      • 15.1.6 Transmission Lines Specific Options
      • 15.1.7 Precedence of option and .options commands
    • 15.2 Initial Conditions
      • 15.2.1 .NODESET: Specify Initial Node Voltage Guesses
      • 15.2.2 .IC: Set Initial Conditions
    • 15.3 Analyses
      • 15.3.1 .AC: Small-Signal AC Analysis
      • 15.3.2 .DC: DC Transfer Function
      • 15.3.3 .DISTO: Distortion Analysis
      • 15.3.4 .NOISE: Noise Analysis
      • 15.3.5 .OP: Operating Point Analysis
      • 15.3.6 .PZ: Pole-Zero Analysis
      • 15.3.7 .SENS: DC or Small-Signal AC Sensitivity Analysis
      • 15.3.8 .TF: Transfer Function Analysis
      • 15.3.9 .TRAN: Transient Analysis
      • 15.3.10 Transient noise analysis (at low frequency)
      • 15.3.11 .PSS: Periodic Steady State Analysis
    • 15.4 Measurements after AC, DC and Transient Analysis
      • 15.4.1 .meas(ure)
      • 15.4.2 batch versus interactive mode
      • 15.4.3 General remarks
      • 15.4.4 Input
      • 15.4.5 Trig Targ
      • 15.4.6 Find ... When
      • 15.4.7 AVG|MIN|MAX|PP|RMS|MIN_AT|MAX_AT
      • 15.4.8 Integ
      • 15.4.9 param
      • 15.4.10 par('expression')
      • 15.4.11 Deriv
      • 15.4.12 More examples
    • 15.5 Safe Operating Area (SOA) warning messages
      • 15.5.1 Resistor and Capacitor SOA model parameters
      • 15.5.2 Diode SOA model parameter
      • 15.5.3 BJT SOA model parameter
      • 15.5.4 MOS SOA model parameter
    • 15.6 Batch Output
      • 15.6.1 .SAVE: Name vector(s) to be saved in raw file
      • 15.6.2 .PRINT Lines
      • 15.6.3 .PLOT Lines
      • 15.6.4 .FOUR: Fourier Analysis of Transient Analysis Output
      • 15.6.5 .PROBE: Name vector(s) to be saved in raw file
      • 15.6.6 par('expression'): Algebraic expressions for output
      • 15.6.7 .width
    • 15.7 Measuring current through device terminals
      • 15.7.1 Adding a voltage source in series
      • 15.7.2 Using option 'savecurrents'
  • 16 Starting ngspice
    • 16.1 Introduction
    • 16.2 Where to obtain ngspice
    • 16.3 Command line options for starting ngspice and ngnutmeg
    • 16.4 Starting options
      • 16.4.1 Batch mode
      • 16.4.2 Interactive mode
      • 16.4.3 Control mode (Interactive mode with control file or control section)
    • 16.5 Standard configuration file spinit
    • 16.6 User defined configuration file .spiceinit
    • 16.7 Environmental variables
      • 16.7.1 Ngspice specific variables
      • 16.7.2 Common environment variables
    • 16.8 Memory usage
    • 16.9 Simulation time
    • 16.10 Ngspice on multi-core processors using OpenMP
      • 16.10.1 Introduction
      • 16.10.2 Some results
      • 16.10.3 Usage
      • 16.10.4 Literature
    • 16.11 Server mode option -s
    • 16.12 Ngspice control via input, output fifos
    • 16.13 Compatibility
      • 16.13.1 Compatibility mode
      • 16.13.2 Missing functions
      • 16.13.3 Devices
      • 16.13.4 Controls and commands
    • 16.14 Tests
    • 16.15 Reporting bugs and errors
  • 17 Interactive Interpreter
    • 17.1 Introduction
    • 17.2 Expressions, Functions, and Constants
    • 17.3 Plots
    • 17.4 Command Interpretation
      • 17.4.1 On the console
      • 17.4.2 Scripts
      • 17.4.3 Add-on to circuit file
    • 17.5 Commands
      • 17.5.1 Ac*: Perform an AC, small-signal frequency response analysis
      • 17.5.2 Alias: Create an alias for a command
      • 17.5.3 Alter*: Change a device or model parameter
      • 17.5.4 Altermod*: Change model parameter(s)
      • 17.5.5 Asciiplot: Plot values using old-style character plots
      • 17.5.6 Aspice*: Asynchronous ngspice run
      • 17.5.7 Bug: Mail a bug report
      • 17.5.8 Cd: Change directory
      • 17.5.9 Cdump: Dump the control flow to the screen
      • 17.5.10 Circbyline*: Enter a circuit line by line
      • 17.5.11 Codemodel*: Load an XSPICE code model library
      • 17.5.12 Compose: Compose a vector
      • 17.5.13 Dc*: Perform a DC-sweep analysis
      • 17.5.14 Define: Define a function
      • 17.5.15 Deftype: Define a new type for a vector or plot
      • 17.5.16 Delete*: Remove a trace or breakpoint
      • 17.5.17 Destroy: Delete an output data set
      • 17.5.18 Devhelp: information on available devices
      • 17.5.19 Diff: Compare vectors
      • 17.5.20 Display: List known vectors and types
      • 17.5.21 Echo: Print text
      • 17.5.22 Edit*: Edit the current circuit
      • 17.5.23 Edisplay: Print a list of all the event nodes
      • 17.5.24 Eprint: Print an event driven node
      • 17.5.25 Eprvcd: Dump event nodes in VCD format
      • 17.5.26 FFT: fast Fourier transform of vectors
      • 17.5.27 Fourier: Perform a Fourier transform
      • 17.5.28 Gnuplot: Graphics output via gnuplot
      • 17.5.29 Hardcopy: Save a plot to a file for printing
      • 17.5.30 Help: Print summaries of Ngspice commands
      • 17.5.31 History: Review previous commands
      • 17.5.32 Inventory: Print circuit inventory
      • 17.5.33 Iplot*: Incremental plot
      • 17.5.34 Jobs*: List active asynchronous ngspice runs
      • 17.5.35 Let: Assign a value to a vector
      • 17.5.36 Linearize*: Interpolate to a linear scale
      • 17.5.37 Listing*: Print a listing of the current circuit
      • 17.5.38 Load: Load rawfile data
      • 17.5.39 Meas*: Measurements on simulation data
      • 17.5.40 Mdump*: Dump the matrix values to a file (or to console)
      • 17.5.41 Mrdump*: Dump the matrix right hand side values to a file (or to console)
      • 17.5.42 Noise*: Noise analysis
      • 17.5.43 Op*: Perform an operating point analysis
      • 17.5.44 Option*: Set a ngspice option
      • 17.5.45 Plot: Plot vectors on the display
      • 17.5.46 Pre_<command>: execute commands prior to parsing the circuit
      • 17.5.47 Print: Print values
      • 17.5.48 Quit: Leave Ngspice or Nutmeg
      • 17.5.49 Rehash: Reset internal hash tables
      • 17.5.50 Remcirc*: Remove the current circuit
      • 17.5.51 Reset*: Reset an analysis
      • 17.5.52 Reshape: Alter the dimensionality or dimensions of a vector
      • 17.5.53 Resume*: Continue a simulation after a stop
      • 17.5.54 Rspice*: Remote ngspice submission
      • 17.5.55 Run*: Run analysis from the input file
      • 17.5.56 Rusage: Resource usage
      • 17.5.57 Save*: Save a set of outputs
      • 17.5.58 Sens*: Run a sensitivity analysis
      • 17.5.59 Set: Set the value of a variable
      • 17.5.60 Setcirc*: Change the current circuit
      • 17.5.61 Setplot: Switch the current set of vectors
      • 17.5.62 Setscale: Set the scale vector for the current plot
      • 17.5.63 Settype: Set the type of a vector
      • 17.5.64 Shell: Call the command interpreter
      • 17.5.65 Shift: Alter a list variable
      • 17.5.66 Show*: List device state
      • 17.5.67 Showmod*: List model parameter values
      • 17.5.68 Snload*: Load the snapshot file
      • 17.5.69 Snsave*: Save a snapshot file
      • 17.5.70 Source: Read a ngspice input file
      • 17.5.71 Spec: Create a frequency domain plot
      • 17.5.72 Status*: Display breakpoint information
      • 17.5.73 Step*: Run a fixed number of time-points
      • 17.5.74 Stop*: Set a breakpoint
      • 17.5.75 Strcmp: Compare two strings
      • 17.5.76 Sysinfo*: Print system information
      • 17.5.77 Tf*: Run a Transfer Function analysis
      • 17.5.78 Trace*: Trace nodes
      • 17.5.79 Tran*: Perform a transient analysis
      • 17.5.80 Transpose: Swap the elements in a multi-dimensional data set
      • 17.5.81 Unalias: Retract an alias
      • 17.5.82 Undefine: Retract a definition
      • 17.5.83 Unlet: Delete the specified vector(s)
      • 17.5.84 Unset: Clear a variable
      • 17.5.85 Version: Print the version of ngspice
      • 17.5.86 Where*: Identify troublesome node or device
      • 17.5.87 Wrdata: Write data to a file (simple table)
      • 17.5.88 Write: Write data to a file (Spice3f5 format)
      • 17.5.89 Wrs2p: Write scattering parameters to file (Touchstone® format)
      • 17.5.90 Xgraph: use the xgraph(1) program for plotting.
    • 17.6 Control Structures
      • 17.6.1 While - End
      • 17.6.2 Repeat - End
      • 17.6.3 Dowhile - End
      • 17.6.4 Foreach - End
      • 17.6.5 If - Then - Else
      • 17.6.6 Label
      • 17.6.7 Goto
      • 17.6.8 Continue
      • 17.6.9 Break
    • 17.7 Internally predefined variables
    • 17.8 Scripts
      • 17.8.1 Variables
      • 17.8.2 Vectors
      • 17.8.3 Commands
      • 17.8.4 control structures
      • 17.8.5 Example script 'spectrum'
      • 17.8.6 Example script for random numbers
      • 17.8.7 Parameter sweep
      • 17.8.8 Output redirection
    • 17.9 Scattering parameters (s-parameters)
      • 17.9.1 Intro
      • 17.9.2 S-parameter measurement basics
      • 17.9.3 Usage
    • 17.10 MISCELLANEOUS
    • 17.11 Bugs
  • 18 Ngspice User Interfaces
    • 18.1 MS Windows Graphical User Interface
    • 18.2 MS Windows Console
    • 18.3 Linux
    • 18.4 CygWin
    • 18.5 Error handling
    • 18.6 Postscript printing options
    • 18.7
    • 18.8 Integration with CAD software and `third party' GUIs
      • 18.8.1 KJWaves
      • 18.8.2 GNU Spice GUI
      • 18.8.3 XCircuit
      • 18.8.4 GEDA
      • 18.8.5 CppSim
      • 18.8.6 NGSPICE Online
      • 18.8.7 Spicy Schematics
      • 18.8.8 MSEspice
      • 18.8.9 PartSim
  • 19 ngspice as shared library or dynamic link library
    • 19.1 Compile options
      • 19.1.1 How to get the sources
      • 19.1.2 Linux, MINGW, CYGWIN
      • 19.1.3 MS Visual Studio
    • 19.2 Linking shared ngspice to a calling application
      • 19.2.1 Linking during creating the caller
      • 19.2.2 Loading at runtime
    • 19.3 Shared ngspice API
      • 19.3.1 structs and types defined for transporting data
      • 19.3.2 Exported functions
      • 19.3.3 Callback functions
    • 19.4 General remarks on using the API
      • 19.4.1 Loading a netlist
      • 19.4.2 Running the simulation
      • 19.4.3 Accessing data
      • 19.4.4 Altering model or device parameters
      • 19.4.5 Output
      • 19.4.6 Error handling
    • 19.5 Example applications
    • 19.6 ngspice parallel
      • 19.6.1 Go parallel!
      • 19.6.2 Additional exported functions
      • 19.6.3 Additional callback functions
      • 19.6.4 Parallel ngspice example
  • 20 TCLspice
    • 20.1 tclspice framework
    • 20.2 tclspice documentation
    • 20.3 spicetoblt
    • 20.4 Running TCLspice
    • 20.5 examples
      • 20.5.1 Active capacitor measurement
      • 20.5.2 Optimization of a linearization circuit for a Thermistor
      • 20.5.3 Progressive display
    • 20.6 Compiling
      • 20.6.1 Linux
      • 20.6.2 MS Windows
    • 20.7 MS Windows 32 Bit binaries
  • 21 Example Circuits
    • 21.1 AC coupled transistor amplifier
    • 21.2 Differential Pair
    • 21.3 MOSFET Characterization
    • 21.4 RTL Inverter
    • 21.5 Four-Bit Binary Adder (Bipolar)
    • 21.6 Four-Bit Binary Adder (MOS)
    • 21.7 Transmission-Line Inverter
  • 22 Statistical circuit analysis
    • 22.1 Introduction
    • 22.2 Using random param(eters)
    • 22.3 Behavioral sources (B, E, G, R, L, C) with random control
    • 22.4 ngspice scripting language
    • 22.5 Monte-Carlo Simulation
      • 22.5.1 Example 1
      • 22.5.2 Example 2
      • 22.5.3 Example 3
      • 22.5.4 Example 4
    • 22.6 Data evaluation with
  • 23 Circuit optimization with ngspice
    • 23.1 Optimization of a circuit
    • 23.2 ngspice optimizer using ngspice scripts
    • 23.3 ngspice optimizer using tclspice
    • 23.4 ngspice optimizer using a Python script
    • 23.5 ngspice optimizer using ASCO
      • 23.5.1 Three stage operational amplifier
      • 23.5.2 Digital inverter
      • 23.5.3 Bandpass
      • 23.5.4 Class-E power amplifier
  • 24 Notes
    • 24.1 Glossary
    • 24.2 Acronyms and Abbreviations
• II XSPICE Software User's Manual
  • 25 XSPICE Basics
    • 25.1 ngspice with the XSPICE option
    • 25.2 The XSPICE Code Model Subsystem
    • 25.3 XSPICE Top-Level Diagram
  • 26 Execution Procedures
    • 26.1 Simulation and Modeling Overview
      • 26.1.1 Describing the Circuit
    • 26.2 Circuit Description Syntax
      • 26.2.1 XSPICE Syntax Extensions
    • 26.3 How to create code models
  • 27 Example circuits
    • 27.1 Amplifier with XSPICE model `gain'
    • 27.2 XSPICE advanced usage
      • 27.2.1 Circuit example C3
      • 27.2.2 Running example C3
  • 28 Code Models and User-Defined Nodes
    • 28.1 Code Model Data Type Definitions
    • 28.2 Creating Code Models
    • 28.3 Creating User-Defined Nodes
    • 28.4 Adding a new code model library
    • 28.5 Compiling and loading the new code model (library)
    • 28.6 Interface Specification File
      • 28.6.1 The Name Table
      • 28.6.2 The Port Table
      • 28.6.3 The Parameter Table
      • 28.6.4 Static Variable Table
    • 28.7 Model Definition File
      • 28.7.1 Macros
      • 28.7.2 Function Library
    • 28.8 User-Defined Node Definition File
      • 28.8.1 Macros
      • 28.8.2 Function Library
      • 28.8.3 Example UDN Definition File
  • 29 Error Messages
    • 29.1 Preprocessor Error Messages
    • 29.2 Simulator Error Messages
    • 29.3 Code Model Error Messages
      • 29.3.1 Code Model aswitch
      • 29.3.2 Code Model climit
      • 29.3.3 Code Model core
      • 29.3.4 Code Model d_osc
      • 29.3.5 Code Model d_source
      • 29.3.6 Code Model d_state
      • 29.3.7 Code Model oneshot
      • 29.3.8 Code Model pwl
      • 29.3.9 Code Model s_xfer
      • 29.3.10 Code Model sine
      • 29.3.11 Code Model square
      • 29.3.12 Code Model triangle
• III CIDER
  • 30 CIDER User’s Manual
    • 30.1 SPECIFICATION
      • 30.1.1 Examples
    • 30.2 BOUNDARY, INTERFACE
      • 30.2.1 DESCRIPTION
      • 30.2.2 PARAMETERS
      • 30.2.3 EXAMPLES
    • 30.3 COMMENT
      • 30.3.1 DESCRIPTION
      • 30.3.2 EXAMPLES
    • 30.4 CONTACT
      • 30.4.1 DESCRIPTION
      • 30.4.2 PARAMETERS
      • 30.4.3 EXAMPLES
      • 30.4.4 SEE ALSO
    • 30.5 DOMAIN, REGION
      • 30.5.1 DESCRIPTION
      • 30.5.2 PARAMETERS
      • 30.5.3 EXAMPLES
      • 30.5.4 SEE ALSO
    • 30.6 DOPING
      • 30.6.1 DESCRIPTION
      • 30.6.2 PARAMETERS
      • 30.6.3 EXAMPLES
      • 30.6.4 SEE ALSO
    • 30.7 ELECTRODE
      • 30.7.1 DESCRIPTION
      • 30.7.2 PARAMETERS
      • 30.7.3 EXAMPLES
      • 30.7.4 SEE ALSO
    • 30.8 END
      • 30.8.1 DESCRIPTION
    • 30.9 MATERIAL
      • 30.9.1 DESCRIPTION
      • 30.9.2 PARAMETERS
      • 30.9.3 EXAMPLES
      • 30.9.4 SEE ALSO
    • 30.10 METHOD
      • 30.10.1 DESCRIPTION
      • 30.10.2 Parameters
      • 30.10.3 Examples
    • 30.11 Mobility
      • 30.11.1 Description
      • 30.11.2 Parameters
      • 30.11.3 Examples
      • 30.11.4 SEE ALSO
      • 30.11.5 BUGS
    • 30.12 MODELS
      • 30.12.1 DESCRIPTION
      • 30.12.2 Parameters
      • 30.12.3 Examples
      • 30.12.4 See also
      • 30.12.5 Bugs
    • 30.13 OPTIONS
      • 30.13.1 DESCRIPTION
      • 30.13.2 Parameters
      • 30.13.3 Examples
      • 30.13.4 See also
    • 30.14 OUTPUT
      • 30.14.1 DESCRIPTION
      • 30.14.2 Parameters
      • 30.14.3 Examples
      • 30.14.4 SEE ALSO
    • 30.15 TITLE
      • 30.15.1 DESCRIPTION
      • 30.15.2 EXAMPLES
      • 30.15.3 BUGS
    • 30.16 X.MESH, Y.MESH
      • 30.16.1 DESCRIPTION
      • 30.16.2 Parameters
      • 30.16.3 EXAMPLES
      • 30.16.4 SEE ALSO
    • 30.17 NUMD
      • 30.17.1 DESCRIPTION
      • 30.17.2 Parameters
      • 30.17.3 EXAMPLES
      • 30.17.4 SEE ALSO
      • 30.17.5 BUGS
    • 30.18 NBJT
      • 30.18.1 DESCRIPTION
      • 30.18.2 Parameters
      • 30.18.3 EXAMPLES
      • 30.18.4 SEE ALSO
      • 30.18.5 BUGS
    • 30.19 NUMOS
      • 30.19.1 DESCRIPTION
      • 30.19.2 Parameters
      • 30.19.3 EXAMPLES
      • 30.19.4 SEE ALSO
    • 30.20 Cider examples
• IV Appendices
  • 31 Model and Device Parameters
    • 31.1 Accessing internal device parameters
    • 31.2 Elementary Devices
      • 31.2.1 Resistor
      • 31.2.2 Capacitor - Fixed capacitor
      • 31.2.3 Inductor - Fixed inductor
      • 31.2.4 Mutual - Mutual Inductor
    • 31.3 Voltage and current sources
      • 31.3.1 ASRC - Arbitrary source
      • 31.3.2 Isource - Independent current source
      • 31.3.3 Vsource - Independent voltage source
      • 31.3.4 CCCS - Current controlled current source
      • 31.3.5 CCVS - Current controlled voltage source
      • 31.3.6 VCCS - Voltage controlled current source
      • 31.3.7 VCVS - Voltage controlled voltage source
    • 31.4 Transmission Lines
      • 31.4.1 CplLines - Simple Coupled Multiconductor Lines
      • 31.4.2 LTRA - Lossy transmission line
      • 31.4.3 Tranline - Lossless transmission line
      • 31.4.4 TransLine - Simple Lossy Transmission Line
      • 31.4.5 URC - Uniform R. C. line
    • 31.5 BJTs
      • 31.5.1 BJT - Bipolar Junction Transistor
      • 31.5.2 BJT - Bipolar Junction Transistor Level 2
      • 31.5.3 VBIC - Vertical Bipolar Inter-Company Model
    • 31.6 MOSFETs
      • 31.6.1 MOS1 - Level 1 MOSFET model with Meyer capacitance model
      • 31.6.2 MOS2 - Level 2 MOSFET model with Meyer capacitance model
      • 31.6.3 MOS3 - Level 3 MOSFET model with Meyer capacitance model
      • 31.6.4 MOS6 - Level 6 MOSFET model with Meyer capacitance model
      • 31.6.5 MOS9 - Modified Level 3 MOSFET model
      • 31.6.6 BSIM1 - Berkeley Short Channel IGFET Model
      • 31.6.7 BSIM2 - Berkeley Short Channel IGFET Model
      • 31.6.8 BSIM3
      • 31.6.9 BSIM4
  • 32 Compilation notes
    • 32.1 Ngspice Installation under Linux (and other 'UNIXes')
      • 32.1.1 Prerequisites
      • 32.1.2 Install from Git
      • 32.1.3 Install from a tarball, e.g. ngspice-rework-27.tgz
      • 32.1.4 Compilation using an user defined directory tree for object files
      • 32.1.5 Advanced Install
      • 32.1.6 Compilers and Options
      • 32.1.7 Compiling For Multiple Architectures
      • 32.1.8 Installation Names
      • 32.1.9 Optional Features
      • 32.1.10 Specifying the System Type
      • 32.1.11 Sharing Defaults
      • 32.1.12 Operation Controls
    • 32.2 Ngspice Compilation under Windows OS
      • 32.2.1 Compile ngspice with MS Visual Studio 2015 or 2017
      • 32.2.2 How to make ngspice with MINGW and MSYS
      • 32.2.3 64 Bit executables with MINGW-w64
      • 32.2.4 make ngspice with pure CYGWIN
      • 32.2.5 ngspice mingw or cygwin console executable w/o graphics
      • 32.2.6 ngspice for MS Windows, cross compiled from Linux
      • 32.2.7 make ngspice with CYGWIN and external MINGW32
      • 32.2.8 make ngspice with CYGWIN and internal MINGW32 (use config.h made above)
    • 32.3 Reporting errors
  • 33 Copyrights and licenses
    • 33.1 Documentation license
      • 33.1.1 Spice documentation copyright
      • 33.1.2 XSPICE SOFTWARE (documentation) copyright
      • 33.1.3 CIDER RESEARCH SOFTWARE AGREEMENT (superseded by 33.2.1)
    • 33.2 ngspice license
      • 33.2.1 `Modified' BSD license
      • 33.2.2 XSPICE
      • 33.2.3 tclspice, numparam
      • 33.2.4 Linking to GPLd libraries (e.g. readline, fftw, table.cm):