STM32F10xxx Cortex M3 Programming Manual Stm32
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- 1 About this document
- 2 The Cortex-M3 processor
- 2.1 Programmers model
- 2.1.1 Processor mode and privilege levels for software execution
- 2.1.2 Stacks
- 2.1.3 Core registers
- Figure 2. Processor core registers
- Table 2. Core register set summary
- Figure 3. APSR, IPSR and EPSR bit assignments
- Figure 4. PSR bit assignments
- Table 3. PSR register combinations
- Table 4. APSR bit definitions
- Table 5. IPSR bit definitions
- Table 6. EPSR bit definitions
- Figure 5. PRIMASK bit assignments
- Table 7. PRIMASK register bit definitions
- Figure 6. FAULTMASK bit assignments
- Table 8. FAULTMASK register bit definitions
- Figure 7. BASEPRI bit assignments
- Table 9. BASEPRI register bit assignments
- Figure 8. CONTROL bit assignments
- Table 10. CONTROL register bit definitions
- 2.1.4 Exceptions and interrupts
- 2.1.5 Data types
- 2.1.6 The Cortex microcontroller software interface standard (CMSIS)
- 2.2 Memory model
- Figure 9. Memory map
- 2.2.1 Memory regions, types and attributes
- 2.2.2 Memory system ordering of memory accesses
- 2.2.3 Behavior of memory accesses
- 2.2.4 Software ordering of memory accesses
- 2.2.5 Bit-banding
- 2.2.6 Memory endianness
- 2.2.7 Synchronization primitives
- 2.2.8 Programming hints for the synchronization primitives
- 2.3 Exception model
- 2.4 Fault handling
- 2.5 Power management
- 2.1 Programmers model
- 3 The Cortex-M3 instruction set
- 3.1 Instruction set summary
- 3.2 Intrinsic functions
- 3.3 About the instruction descriptions
- 3.4 Memory access instructions
- 3.5 General data processing instructions
- 3.6 Multiply and divide instructions
- 3.7 Saturating instructions
- 3.8 Bitfield instructions
- 3.9 Miscellaneous instructions
- 4 Core peripherals
- 4.1 About the STM32 core peripherals
- 4.2 Nested vectored interrupt controller (NVIC)
- 4.2.1 The CMSIS mapping of the Cortex-M3 NVIC registers
- 4.2.2 Interrupt set-enable registers (NVIC_ISERx)
- 4.2.3 Interrupt clear-enable registers (NVIC_ICERx)
- 4.2.4 Interrupt set-pending registers (NVIC_ISPRx)
- 4.2.5 Interrupt clear-pending registers (NVIC_ICPRx)
- 4.2.6 Interrupt active bit registers (NVIC_IABRx)
- 4.2.7 Interrupt priority registers (NVIC_IPRx)
- 4.2.8 Software trigger interrupt register (NVIC_STIR)
- 4.2.9 Level-sensitive and pulse interrupts
- 4.2.10 NVIC design hints and tips
- 4.2.11 NVIC register map
- 4.3 System control block (SCB)
- 4.3.1 CPUID base register (SCB_CPUID)
- 4.3.2 Interrupt control and state register (SCB_ICSR)
- 4.3.3 Vector table offset register (SCB_VTOR)
- 4.3.4 Application interrupt and reset control register (SCB_AIRCR)
- 4.3.5 System control register (SCB_SCR)
- 4.3.6 Configuration and control register (SCB_CCR)
- 4.3.7 System handler priority registers (SHPRx)
- 4.3.8 System handler control and state register (SCB_SHCSR)
- 4.3.9 Configurable fault status register (SCB_CFSR)
- 4.3.10 Hard fault status register (SCB_HFSR)
- 4.3.11 Memory management fault address register (SCB_MMFAR)
- 4.3.12 Bus fault address register (SCB_BFAR)
- 4.3.13 System control block design hints and tips
- 4.3.14 SCB register map
- 4.4 SysTick timer (STK)
- 5 Revision history