CC2538 System On Chip Solution For 2.4 GHz IEEE 802.15.4 And ZigBee®/ZigBee IP® Applications (Rev. C) Swru319c Users Guide

swru319c-Users_Guide

cc2538_emote3_users_guide

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CC2538 System-on-Chip Solution for 2.4-GHz
IEEE 802.15.4 and ZigBee®/ZigBee IP®
Applications
Texas Instruments CC2538™ Family of Products
Version C

User's Guide

Literature Number: SWRU319C
April 2012 – Revised May 2013

WARNING: EXPORT NOTICE
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without obtaining prior authorisation from U.S. Department of Commerce
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Agreement.
According to our best knowledge of the state and end-use of this
product or technology, and in compliance with the export control
regulations of dual-use goods in force in the origin and exporting
countries, this technology is classified as follows:
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EU ECCN: 5E002
And may require export or re-export license for shipping it in compliance
with the applicable regulations of certain countries.

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Contents
...................................................................................................................................... 26
Architectural Overview ....................................................................................................... 32
1.1
Target Applications ........................................................................................................ 33
1.2
Overview .................................................................................................................... 33
1.3
Functional Overview ...................................................................................................... 36
1.3.1 ARM Cortex-M3 ................................................................................................... 36
1.3.1.1
Processor Core ............................................................................................. 36
1.3.1.2
Memory Map ................................................................................................ 36
1.3.1.3
System Timer (SysTick) ................................................................................... 36
1.3.1.4
Nested Vector Interrupt Controller ....................................................................... 37
1.3.1.5
System Control Block ...................................................................................... 37
1.3.1.6
MPU .......................................................................................................... 37
1.3.2 On-Chip Memory ................................................................................................. 37
1.3.2.1
SRAM ........................................................................................................ 37
1.3.2.2
Flash Memory ............................................................................................... 37
1.3.2.3
ROM ......................................................................................................... 38
1.3.3 Radio ............................................................................................................... 38
1.3.4 AES Engine with 128, 192 256 Bit Key Support ............................................................. 38
1.3.5 Programmable Timers ........................................................................................... 38
1.3.5.1
MAC Timer .................................................................................................. 39
1.3.5.2
Watchdog Timer ............................................................................................ 39
1.3.5.3
Sleep Timer ................................................................................................. 39
1.3.5.4
CCP Pins .................................................................................................... 39
1.3.6 Direct Memory Access ........................................................................................... 39
1.3.7 System Control and Clock ....................................................................................... 40
1.3.8 Serial Communications Peripherals ............................................................................ 41
1.3.8.1
USB .......................................................................................................... 41
1.3.8.2
UART ........................................................................................................ 41
1.3.8.3
I2C ............................................................................................................ 42
1.3.8.4
SSI ........................................................................................................... 43
1.3.9 Programmable GPIOs ........................................................................................... 43
1.3.10 Analog ............................................................................................................ 43
1.3.10.1 ADC .......................................................................................................... 44
1.3.10.2 Analog Comparator ........................................................................................ 44
1.3.10.3 Random Number Generator .............................................................................. 44
1.3.11 cJTAG, JTAG and SWO ........................................................................................ 44
1.3.12 Packaging and Temperature ................................................................................... 44
The Cortex-M3 Processor ................................................................................................... 45
2.1
The Cortex-M3 Processor Introduction ................................................................................. 46
2.2
Block Diagram ............................................................................................................. 46
2.3
Overview .................................................................................................................... 47
2.3.1 System-Level Interface .......................................................................................... 47
2.3.2 Integrated Configurable Debug ................................................................................. 47
2.3.3 Trace Port Interface Unit ........................................................................................ 48

Preface
1

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2.4

2.5

Cortex™-M3 Peripherals
3.1
3.2

3.3
3.4
3.5

..................................................................................................... 65

................................................................................................................... 155

Memory Model ............................................................................................................
4.1.1 Memory Regions, Types, and Attributes .....................................................................
4.1.2 Memory System Ordering of Memory Accesses ............................................................
4.1.3 Behavior of Memory Accesses ................................................................................
4.1.4 Software Ordering of Memory Accesses .....................................................................
4.1.5 Bit-Banding .......................................................................................................
4.1.5.1
Directly Accessing an Alias Region ....................................................................
4.1.5.2
Directly Accessing a Bit-Band Region .................................................................
4.1.6 Data Storage .....................................................................................................
4.1.7 Synchronization Primitives .....................................................................................

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........................................................................................................................ 164
Exception Model ......................................................................................................... 165
5.1.1 Exception States ................................................................................................ 165
5.1.2 Exception Types ................................................................................................ 165
5.1.3 Exception Handlers ............................................................................................. 170
5.1.4 Vector Table ..................................................................................................... 170
5.1.5 Exception Priorities ............................................................................................. 171
5.1.6 Interrupt Priority Grouping ..................................................................................... 172
5.1.7 Exception Entry and Return ................................................................................... 172
5.1.7.1
Exception Entry ........................................................................................... 172
5.1.7.2
Exception Return ......................................................................................... 173

Interrupts
5.1

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Cortex™-M3 Peripherals Introduction .................................................................................. 66
Functional Description .................................................................................................... 66
3.2.1 SysTick ............................................................................................................. 66
3.2.2 NVIC ................................................................................................................ 67
3.2.2.1
Level-Sensitive and Pulse Interrupts .................................................................... 67
3.2.2.2
Hardware and Software Control of Interrupts .......................................................... 67
3.2.3 SCB ................................................................................................................ 68
3.2.4 MPU ................................................................................................................ 68
3.2.4.1
Updating an MPU Region ................................................................................. 69
3.2.4.1.1 Updating an MPU Region Using Separate Words ................................................ 69
3.2.4.1.2 Updating an MPU Region Using Multiple-Word Writes ........................................... 70
3.2.4.1.3 Subregions .............................................................................................. 70
3.2.4.2
MPU Access Permission Attributes ...................................................................... 71
3.2.4.2.1 MPU Configuration for a CC2538 Microcontroller ................................................. 72
3.2.4.3
MPU Mismatch ............................................................................................. 72
Register Map ............................................................................................................... 72
SysTick Register Descriptions ........................................................................................... 76
NVIC Register Descriptions .............................................................................................. 77
3.5.1 System Control Block (SCB) Register Descriptions ........................................................ 126
3.5.2 MPU Register Descriptions .................................................................................... 143

Memory Map
4.1

2.3.4 Cortex-M3 System Component Details ........................................................................
Programming Model .......................................................................................................
2.4.1 Processor Mode and Privilege Levels for Software Execution .............................................
2.4.2 Stacks ..............................................................................................................
2.4.3 Register Map ......................................................................................................
2.4.4 Register Descriptions ............................................................................................
2.4.5 Exceptions and Interrupts .......................................................................................
2.4.6 Data Types ........................................................................................................
Instruction Set Summary .................................................................................................

Contents

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5.2

JTAG Interface
6.1
6.2
6.3
6.4

6.5

6.6
6.7

Fault Handling ............................................................................................................
5.2.1 Fault Types ......................................................................................................
5.2.2 Fault Escalation and Hard Faults .............................................................................
5.2.3 Fault Status Registers and Fault Address Registers .......................................................
5.2.4 Lockup ............................................................................................................
5.2.5 PKA Interrupt ....................................................................................................

7.1

7.2

7.3

7.4

7.5
7.6

................................................................................................................ 177

Debug Port ................................................................................................................
IEEE 1149.7 ..............................................................................................................
Switching Debug Interface from 2-pin cJTAG to 4-pin JTAG ......................................................
Debugger Connection ...................................................................................................
6.4.1 ICEPick Module .................................................................................................
6.4.1.1
Default Boot Mode ........................................................................................
6.4.1.2
CM3 DAP Access .........................................................................................
Primary Debug Support .................................................................................................
6.5.1 Processor Native Debug Support .............................................................................
6.5.1.1
Cortex™-M3 MPU ........................................................................................
6.5.2 Suspend ..........................................................................................................
Debug Access Security Through ICEPick ............................................................................
6.6.1 Unlocking the Debug Interface ................................................................................
CM3 Debug Interrupt ....................................................................................................

System Control

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................................................................................................................ 184

Power Management .....................................................................................................
7.1.1 Control Inputs to Power Management ........................................................................
7.1.1.1
Clock Gating Registers ..................................................................................
7.1.1.2
Deep Sleep Selector (SYSCTRL Register) ...........................................................
7.1.1.3
Power Mode Configuration Register (PMCTL Register) .............................................
7.1.1.4
WFI - Operational Mode Initiator (Wait For Interrupt) ................................................
7.1.2 Using Power Management .....................................................................................
7.1.2.1
Sequencing when using Power Modes ................................................................
7.1.2.2
Time Considerations for Active, Sleep and PM0 .....................................................
7.1.2.3
Time Considerations for PM1, PM2 and PM3 ........................................................
7.1.2.3.1 Enter Power Mode when Running on 16 MHz System Clock ..................................
7.1.2.3.2 Enter Power Mode when Running on 32 MHz System Clock ..................................
7.1.2.4
Exit from Power Modes ..................................................................................
7.1.2.4.1 32 MHz XOSC Startup Time ........................................................................
7.1.2.4.2 32 MHz Qualification Time ..........................................................................
7.1.3 Power Consumption ............................................................................................
Oscillators and Clocks ...................................................................................................
7.2.1 High Frequency Oscillators ....................................................................................
7.2.1.1
16 MHz RCOSC Calibration .............................................................................
7.2.2 Low Frequency Oscillators .....................................................................................
7.2.2.1
32 kHz RCOSC Calibration .............................................................................
System Clock Gating ....................................................................................................
7.3.1 Clocks for UART and SSI ......................................................................................
7.3.2 Clocks for GPT, I2C, and SEC .................................................................................
Reset ......................................................................................................................
7.4.1 Reset of Peripherals ............................................................................................
7.4.2 Power-On Reset and Brownout Detector ....................................................................
7.4.3 Clock Loss Detector ............................................................................................
Emulator in Power Modes ..............................................................................................
Chip State Retention ....................................................................................................
7.6.1 CRC Check on State Retention ...............................................................................

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7.7

System Control Registers ...............................................................................................
7.7.1 SYS_CTRL Registers ..........................................................................................
7.7.1.1
SYS_CTRL Registers Mapping Summary .............................................................
7.7.1.2
SYS_CTRL Register Descriptions ......................................................................

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............................................................................................................... 214
8.1
Introduction ............................................................................................................... 215
8.2
Flash Memory Organization ............................................................................................ 215
8.2.1 Information Page ................................................................................................ 215
8.2.2 Lock Bit Page .................................................................................................... 215
8.3
Flash Write ................................................................................................................ 215
8.3.1 Flash Write Procedure .......................................................................................... 215
8.3.2 Writing Multiple Times to a Word ............................................................................. 216
8.3.3 DMA Flash Write ................................................................................................ 217
8.3.4 CPU Flash Write ................................................................................................ 218
8.4
Flash DMA Trigger ....................................................................................................... 219
8.5
Flash Page Erase ........................................................................................................ 219
8.5.1 Performing Flash Erase from Flash Memory ................................................................ 219
8.6
Flash Lock Bit Page and Customer Configuration Area (CCA) .................................................... 219
8.6.1 Flash Image Valid Bits in Lock Bit Page ..................................................................... 221
8.6.2 ROM Boot Loader Backdoor Configuration in Lock Bit Page ............................................. 221
8.7
Flash Mass Erase ........................................................................................................ 222
8.7.1 Flash Mass Erase Procedure .................................................................................. 223
8.8
ROM Sub System ........................................................................................................ 224
8.9
SRAM ...................................................................................................................... 224
8.10 Flash Control Registers ................................................................................................. 225
8.10.1 FLASH_CTRL Registers ...................................................................................... 225
8.10.1.1 FLASH_CTRL Registers Mapping Summary ......................................................... 225
8.10.1.2 FLASH_CTRL Register Descriptions .................................................................. 225
General-Purpose Inputs/Outputs ....................................................................................... 230
9.1
I/O Control ................................................................................................................ 231
9.1.1 I/O Muxing ....................................................................................................... 231
9.2
GPIO ....................................................................................................................... 232
9.2.1 General-Purpose Inputs/Outputs .............................................................................. 232
9.2.2 Functional Description .......................................................................................... 232
9.2.2.1
Data Control ............................................................................................... 234
9.2.2.1.1 Data Direction Operation ............................................................................ 234
9.2.2.1.2 Data Register Operation ............................................................................ 234
9.2.2.2
Interrupt Control ........................................................................................... 234
9.2.2.2.1 Power-Up Interrupt ................................................................................... 235
9.2.2.3
Mode Control .............................................................................................. 235
9.2.2.4
Commit Control ........................................................................................... 235
9.2.2.5
Pad Control ................................................................................................ 236
9.2.3 Configuration .................................................................................................... 237
9.2.4 Radio Test Output Signals ..................................................................................... 238
9.2.5 Power-Down Signal MUX (PMUX) ............................................................................ 238
9.3
I/O Control and GPIO Registers ....................................................................................... 238
9.3.1 GPIO Registers .................................................................................................. 238
9.3.1.1
GPIO Registers Mapping Summary .................................................................... 238
9.3.1.1.1 GPIO Common Registers Mapping ................................................................ 238
9.3.1.1.2 GPIO Instances Register Mapping Summary .................................................... 239
9.3.1.2
GPIO Common Register Descriptions ................................................................. 241
9.3.2 IOC Registers ................................................................................................... 255
9.3.2.1
IOC Registers Mapping Summary ...................................................................... 255

Contents

Internal Memory

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............................................................................... 257
Micro Direct Memory Access ............................................................................................. 285
10.1 μDMA Introduction ....................................................................................................... 286
10.2 Block Diagram ............................................................................................................ 286
10.3 Functional Description ................................................................................................... 287
10.3.1 Channel Assignments ......................................................................................... 287
10.3.2 Priority ........................................................................................................... 289
10.3.3 Arbitration Size ................................................................................................. 289
10.3.4 Request Types ................................................................................................. 289
10.3.4.1 Single Request ............................................................................................ 290
10.3.4.2 Burst Request ............................................................................................. 290
10.3.5 Channel Configuration ........................................................................................ 290
10.3.6 Transfer Modes ................................................................................................ 291
10.3.6.1 Stop Mode ................................................................................................. 291
10.3.6.2 Basic Mode ................................................................................................ 292
10.3.6.3 Auto Mode ................................................................................................. 292
10.3.6.4 Ping-Pong .................................................................................................. 292
10.3.6.5 Memory Scatter-Gather .................................................................................. 293
10.3.6.6 Peripheral Scatter-Gather ............................................................................... 297
10.3.7 Transfer Size and Increment ................................................................................. 300
10.3.8 Peripheral Interface ............................................................................................ 300
10.3.9 Software Request .............................................................................................. 300
10.3.10 Interrupts and Errors ......................................................................................... 301
10.4 Initialization and Configuration ......................................................................................... 301
10.4.1 Module Initialization ............................................................................................ 301
10.4.2 Configuring a Memory-to-Memory Transfer ................................................................ 301
10.4.2.1 Configure the Channel Attributes ....................................................................... 301
10.4.2.2 Configure the Channel Control Structure .............................................................. 302
10.4.2.2.1 Configure the Source and Destination ............................................................ 302
10.4.2.3 Start the Transfer ......................................................................................... 302
10.4.3 Configuring a Peripheral for Simple Transmit .............................................................. 303
10.4.3.1 Configure the Channel Attributes ....................................................................... 303
10.4.3.2 Configure the Channel Control Structure .............................................................. 303
10.4.3.2.1 Configure the Source and Destination ............................................................ 303
10.4.3.3 Start the Transfer ......................................................................................... 304
10.4.4 Configuring a Peripheral for Ping-Pong Receive .......................................................... 304
10.4.4.1 Configure the Channel Attributes ....................................................................... 304
10.4.4.2 Configure the Channel Control Structure .............................................................. 304
10.4.4.2.1 Configure the Source and Destination ............................................................ 305
10.4.4.3 Configure the Peripheral Interrupt ...................................................................... 305
10.4.4.4 Enable the μDMA Channel .............................................................................. 306
10.4.4.5 Process Interrupts ........................................................................................ 306
10.4.5 Configuring Channel Assignments .......................................................................... 306
10.5 µDMA Registers .......................................................................................................... 306
10.5.1 UDMA Registers ............................................................................................... 306
10.5.1.1 UDMA Registers Mapping Summary ................................................................... 306
10.5.1.2 UDMA Register Descriptions ............................................................................ 307
General-Purpose Timers ................................................................................................... 318
11.1 General-Purpose Timers ................................................................................................ 319
11.2 Block Diagram ............................................................................................................ 319
11.3 Functional Description ................................................................................................... 320
11.3.1 GPTM Reset Conditions ...................................................................................... 320
11.3.2 Timer Modes .................................................................................................... 321
9.3.2.2

IOC Register Descriptions

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11.4

11.5

MAC Timer
12.1

12.2
12.3
12.4

12.5

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356

..................................................................................................................... 362

General ....................................................................................................................
Timer Compare ...........................................................................................................
Timer Capture ............................................................................................................
Sleep Timer Registers ...................................................................................................
13.4.1 SMWDTHROSC Registers ...................................................................................
13.4.1.1 SMWDTHROSC Registers Mapping Summary .......................................................
13.4.1.2 SMWDTHROSC Register Descriptions ................................................................

Watchdog Timer
14.1
14.2

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328
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331
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...................................................................................................................... 350

Timer Operation ..........................................................................................................
12.1.1 General ..........................................................................................................
12.1.2 Up Counter ......................................................................................................
12.1.3 Timer Overflow .................................................................................................
12.1.4 Timer Delta Increment .........................................................................................
12.1.5 Timer Compare .................................................................................................
12.1.6 Overflow Count .................................................................................................
12.1.7 Overflow-Count Update .......................................................................................
12.1.8 Overflow-Count Overflow .....................................................................................
12.1.9 Overflow-Count Compare .....................................................................................
12.1.10 Capture Input .................................................................................................
Interrupts ..................................................................................................................
Event Outputs (DMA Trigger and Radio Events) ....................................................................
Timer Start and Stop Synchronization ................................................................................
12.4.1 General ..........................................................................................................
12.4.2 Timer Synchronous Stop ......................................................................................
12.4.3 Timer Synchronous Start .....................................................................................
MAC Timer Registers ....................................................................................................
12.5.1 RFCORE_SFR Registers .....................................................................................
12.5.1.1 RFCORE_SFR Registers Mapping Summary ........................................................
12.5.1.2 RFCORE_SFR Register Descriptions .................................................................

Sleep Timer
13.1
13.2
13.3
13.4

11.3.2.1 One-Shot or Periodic Timer Mode ......................................................................
11.3.2.2 Input Edge-Count Mode .................................................................................
11.3.2.3 Input Edge-Time Mode ...................................................................................
11.3.2.4 PWM Mode ................................................................................................
11.3.3 Wait-for-Trigger Mode .........................................................................................
11.3.4 Synchronizing GP Timer Blocks .............................................................................
11.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values .......................................
Initialization and Configuration .........................................................................................
11.4.1 One-Shot and Periodic Timer Modes .......................................................................
11.4.2 Input Edge-Count Mode .......................................................................................
11.4.3 Input Edge-Timing Mode ......................................................................................
11.4.4 PWM Mode .....................................................................................................
General-Purpose Timer Registers .....................................................................................
11.5.1 GPTIMER Registers ...........................................................................................
11.5.1.1 GPTIMER Registers Mapping Summary ..............................................................
11.5.1.1.1 GPTIMER Common Registers Mapping ..........................................................
11.5.1.1.2 GPTIMER Instances Register Mapping Summary ..............................................
11.5.1.2 GPTIMER Common Register Descriptions ............................................................

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.............................................................................................................. 370

Watchdog Timer ..........................................................................................................
Watchdog Timer Registers .............................................................................................
14.2.1 SMWDTHROSC Registers ...................................................................................
14.2.1.1 SMWDTHROSC Registers Mapping Summary .......................................................

Contents

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................................................................
ADC ...............................................................................................................................
15.1 ADC Introduction .........................................................................................................
15.2 ADC Operation ...........................................................................................................
15.2.1 ADC Inputs ......................................................................................................
15.2.2 ADC Conversion Sequences .................................................................................
15.2.3 Single ADC Conversion .......................................................................................
15.2.4 ADC Operating Modes ........................................................................................
15.2.5 ADC Conversion Results .....................................................................................
15.2.6 ADC Reference Voltage ......................................................................................
15.2.7 ADC Conversion Timing ......................................................................................
15.2.8 ADC Interrupts .................................................................................................
15.2.9 ADC DMA Triggers ............................................................................................
15.3 Analog-to-Digital Converter Registers .................................................................................
15.3.1 SOC_ADC Registers ..........................................................................................
15.3.1.1 SOC_ADC Registers Mapping Summary .............................................................
15.3.1.2 SOC_ADC Register Descriptions .......................................................................
Random Number Generator ..............................................................................................
16.1 Introduction ...............................................................................................................
16.2 Random-Number-Generator Operation ...............................................................................
16.2.1 Pseudo-random Sequence Generation .....................................................................
16.2.2 Seeding .........................................................................................................
16.2.3 CRC16 ...........................................................................................................
16.3 Random Number Generator Registers ................................................................................
16.3.1 SOC_ADC Registers ..........................................................................................
16.3.1.1 SOC_ADC Registers Mapping Summary .............................................................
16.3.1.2 SOC_ADC Register Descriptions .......................................................................
Analog Comparator ..........................................................................................................
17.1 Introduction ...............................................................................................................
17.2 Analog Comparator Registers ..........................................................................................
17.2.1 SOC_ADC Registers ..........................................................................................
17.2.1.1 SOC_ADC Registers Mapping Summary .............................................................
17.2.1.2 SOC_ADC Register Descriptions .......................................................................
Universal Asynchronous Receivers and Transmitters ..........................................................
18.1 Universal Asynchronous Receivers and Transmitters ..............................................................
18.2 Block Diagram ............................................................................................................
18.3 Signal Description ........................................................................................................
18.4 Functional Description ...................................................................................................
18.4.1 Transmit and Receive Logic ..................................................................................
18.4.2 Baud-Rate Generation ........................................................................................
18.4.3 Data Transmission .............................................................................................
18.4.4 Modem Handshake Support ..................................................................................
18.4.4.1 Signaling ...................................................................................................
18.4.4.2 Flow Control ...............................................................................................
18.4.4.2.1 Hardware Flow Control (RTS and CTS) ..........................................................
18.4.5 LIN Support .....................................................................................................
18.4.5.1 LIN Master .................................................................................................
18.4.5.2 LIN Slave ..................................................................................................
18.4.6 9-Bit UART Mode ..............................................................................................
18.4.7 FIFO Operation .................................................................................................
18.4.8 Interrupts ........................................................................................................
18.4.9 Loopback Operation ...........................................................................................
14.2.1.2

SMWDTHROSC Register Descriptions

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18.5
18.6

Synchronous Serial Interface
19.1
19.2
19.3
19.4

19.5
19.6
19.7

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............................................................................................ 415

Synchronous Serial Interface ...........................................................................................
Block Diagram ............................................................................................................
Signal Description ........................................................................................................
Functional Description ...................................................................................................
19.4.1 Bit Rate Generation ............................................................................................
19.4.2 FIFO Operation .................................................................................................
19.4.2.1 Transmit FIFO .............................................................................................
19.4.2.2 Receive FIFO .............................................................................................
19.4.3 Interrupts ........................................................................................................
19.4.4 Frame Formats .................................................................................................
19.4.4.1 Texas Instruments Synchronous Serial Frame Format ..............................................
19.4.4.2 Freescale SPI Frame Format ...........................................................................
19.4.4.2.1 SPO Clock Polarity Bit ..............................................................................
19.4.4.2.2 SPH Phase Control Bit ..............................................................................
19.4.4.3 Freescale SPI Frame Format With SPO = 0 and SPH = 0 .........................................
19.4.4.4 Freescale SPI Frame Format With SPO = 0 and SPH = 1 .........................................
19.4.4.5 Freescale SPI Frame Format With SPO = 1 and SPH = 0 .........................................
19.4.4.6 Freescale SPI Frame Format With SPO = 1 and SPH = 1 .........................................
19.4.4.7 MICROWIRE Frame Format ............................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .........................................................................................
SSI Registers .............................................................................................................
19.7.1 SSI Registers ...................................................................................................
19.7.1.1 SSI Registers Mapping Summary ......................................................................
19.7.1.1.1 SSI Common Registers Mapping ..................................................................
19.7.1.1.2 SSI Instances Register Mapping Summary ......................................................
19.7.1.2 SSI Common Register Descriptions ....................................................................

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418
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420
421
421
422
423
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........................................................................................ 434
Inter-Integrated Circuit Interface ....................................................................................... 435
Block Diagram ............................................................................................................ 435
Functional Description ................................................................................................... 435
20.3.1 I2C Bus Functional Overview ................................................................................. 436
20.3.1.1 Start and Stop Conditions ............................................................................... 436
20.3.1.2 Data Format With 7-Bit Address ........................................................................ 437
20.3.1.3 Data Validity ............................................................................................... 437
20.3.1.4 Acknowledge .............................................................................................. 437
20.3.1.5 Arbitration .................................................................................................. 438
20.3.2 Available Speed Modes ....................................................................................... 438
20.3.2.1 Standard and Fast Modes ............................................................................... 438
20.3.3 Interrupts ........................................................................................................ 438
20.3.3.1 I2C Master Interrupts ..................................................................................... 439
20.3.3.2 I2C Slave Interrupts ....................................................................................... 439
20.3.4 Loopback Operation ........................................................................................... 439
20.3.5 Command Sequence Flow Charts ........................................................................... 439
20.3.5.1 I2C Master Command Sequences ...................................................................... 439

Inter-Integrated Circuit Interface
20.1
20.2
20.3

Initialization and Configuration .........................................................................................
UART Registers ..........................................................................................................
18.6.1 UART Registers ................................................................................................
18.6.1.1 UART Registers Mapping Summary ...................................................................
18.6.1.1.1 UART Common Registers Mapping ...............................................................
18.6.1.1.2 UART Instances Register Mapping Summary ...................................................
18.6.1.2 UART Common Register Descriptions .................................................................

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20.4
20.5

USB Controller
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8

21.9

21.10

21.11
21.12
21.13
21.14

20.3.5.2 I2C Slave Command Sequences ........................................................................
Initialization and Configuration .........................................................................................
I2C Registers ..............................................................................................................
20.5.1 I2CM Registers .................................................................................................
20.5.1.1 I2CM Registers Mapping Summary ....................................................................
20.5.1.2 I2CM Register Descriptions .............................................................................
20.5.2 I2CS Registers .................................................................................................
20.5.2.1 I2CS Registers Mapping Summary ....................................................................
20.5.2.2 I2CS Register Descriptions ..............................................................................

22.1

................................................................................................................ 457

USB Introduction .........................................................................................................
USB Enable ...............................................................................................................
48-MHz USB PLL ........................................................................................................
USB Interrupts ............................................................................................................
USB Reset ................................................................................................................
USB Index Register ......................................................................................................
USB Suspend and Resume ............................................................................................
21.7.1 USB Suspend and Resume Procedure .....................................................................
Endpoint 0 ................................................................................................................
21.8.1 Zero Data Requests ...........................................................................................
21.8.2 Write Requests .................................................................................................
21.8.3 Read Requests .................................................................................................
EndPoint 0 Interrupts ....................................................................................................
21.9.1 Error Conditions ................................................................................................
21.9.2 SETUP Transactions (IDLE State) ..........................................................................
21.9.3 IN Transactions (TX State) ...................................................................................
21.9.4 OUT Transactions (RX State) ................................................................................
Endpoints 1–5 ............................................................................................................
21.10.1 FIFO Management ...........................................................................................
21.10.2 Double-Buffering ..............................................................................................
21.10.3 FIFO Access ..................................................................................................
21.10.4 Endpoint 1–5 Interrupts ......................................................................................
21.10.5 Bulk and Interrupt IN Endpoint ..............................................................................
21.10.6 Isochronous IN Endpoint ....................................................................................
21.10.7 Bulk and Interrupt OUT Endpoint ...........................................................................
21.10.8 Isochronous OUT Endpoint .................................................................................
DMA .......................................................................................................................
Remote Wake-Up ........................................................................................................
USB Registers Overview ...............................................................................................
USB Registers ...........................................................................................................
21.14.1 USB Registers ................................................................................................
21.14.1.1 USB Registers Mapping Summary ....................................................................
21.14.1.2 USB Register Descriptions .............................................................................

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PKA Engine ...............................................................................................................
22.1.1 Terms and Conventions Used in this Manual ..............................................................
22.1.1.1 Acronyms ..................................................................................................
22.1.1.2 Formulae and Nomenclature ............................................................................
22.1.2 Overview ........................................................................................................
22.1.2.1 Feature List ................................................................................................
22.1.2.2 Performance ...............................................................................................
22.1.3 Functional Description .........................................................................................
22.1.3.1 Module Architecture ......................................................................................

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22.2

22.1.3.2 PKA RAM ..................................................................................................
22.1.3.3 PKCP Operations .........................................................................................
22.1.3.4 Sequencer Operations ...................................................................................
22.1.3.4.1 Modular Exponentiation Operations ...............................................................
22.1.3.4.2 PKA RAM Size Needed for Exponentiation Operations ........................................
22.1.3.4.3 Modular Inversion Operation .......................................................................
22.1.3.4.4 Modular Inversion With an Even Modulus ........................................................
22.1.3.4.5 Modular Inversion With a Prime Modulus .........................................................
22.1.3.4.6 ECC Operations ......................................................................................
22.1.4 Performance ....................................................................................................
22.1.4.1 Basic PKCP Operations Performance .................................................................
22.1.4.2 ExpMod Performance ....................................................................................
22.1.4.3 Modular Inversion Performance ........................................................................
22.1.4.4 ECC Operation Performance ............................................................................
22.1.5 Interfaces ........................................................................................................
22.1.5.1 Functional Interface ......................................................................................
22.1.5.1.1 External Interface Address Map ....................................................................
22.1.5.1.2 PKA Engine Control Registers .....................................................................
22.1.5.1.3 PKA Vector_A Address (PKA_APTR) .............................................................
22.1.5.1.4 PKA Vector_B Address (PKA_BPTR) .............................................................
22.1.5.1.5 PKA Vector_C Address (PKA_CPTR) ............................................................
22.1.5.1.6 PKA Vector_D Address (PKA_DPTR) ............................................................
22.1.5.1.7 PKA Vector_A Length (PKA_ALENGTH) .........................................................
22.1.5.1.8 PKA Vector_B Length (PKA_BLENGTH) .........................................................
22.1.5.1.9 PKA Bit Shift Value (PKA_SHIFT) .................................................................
22.1.5.1.10 PKA Function (PKA_FUNCTION) ................................................................
22.1.5.1.11 PKA Compare Result (PKA_COMPARE) .......................................................
22.1.5.1.12 PKA Most-Significant-Word of Result Vector (PKA_MSW) ...................................
22.1.5.1.13 PKA Most-Significant-Word of Divide Remainder (PKA_DIVMSW) .........................
22.1.5.1.14 PKA Sequencer Control/Status Register (PKA_SEQ_CTRL) ................................
22.1.5.1.15 PKA HW Options Register (PKA_OPTIONS) ...................................................
22.1.5.1.16 PKA Firmware Revision and Capabilities Register (PKA_SW_REV) ........................
22.1.5.1.17 PKA HW Revision Register (PKA_REVISION) .................................................
22.1.5.1.18 PKA Vector Ram (PKA_RAM) ....................................................................
22.1.5.1.19 Sequencer Program RAM (PKA_PROGRAM) ..................................................
22.1.5.2 Operation Sequences ....................................................................................
22.1.6 Appendix A: RSA, ELGAMAL, DH, AND DSA Use Cases ...............................................
22.1.6.1 A1: RSA Use Cases ......................................................................................
22.1.6.2 A2: Diffie-Hellman Use Cases ..........................................................................
22.1.6.3 A3: ElGamal Use Cases .................................................................................
22.1.6.4 A4: DSA Use Cases ......................................................................................
AES and SHA Cryptoprocessor ........................................................................................
22.2.1 Architecture Overview .........................................................................................
22.2.1.1 Functional Description ...................................................................................
22.2.1.1.1 Basic DMA Controller With AHB Master Interface ...............................................
22.2.1.1.2 Key Store ..............................................................................................
22.2.1.1.3 AES Crypto Engine ..................................................................................
22.2.1.1.4 SHA-256 Hash Engine ..............................................................................
22.2.1.1.5 Master Control and Interrupts ......................................................................
22.2.1.1.6 Debug Capabilities ...................................................................................
22.2.1.1.7 Exception Handling ..................................................................................
22.2.2 Hardware Description .........................................................................................
22.2.2.1 Slave Bus ..................................................................................................

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22.2.2.1.1 Functional Description ...............................................................................
22.2.2.1.2 Endianness ...........................................................................................
22.2.2.1.3 Performance ..........................................................................................
22.2.2.2 Master Bus ................................................................................................
22.2.2.3 Interrupts ...................................................................................................
22.2.3 Module Description ............................................................................................
22.2.3.1 Introduction ................................................................................................
22.2.3.2 Global and Detailed Memory Map ......................................................................
22.2.3.3 DMA Controller ............................................................................................
22.2.3.3.1 Operation ..............................................................................................
22.2.3.3.2 Channels and Arbiter ................................................................................
22.2.3.3.3 Control/Status Registers ............................................................................
22.2.3.4 Master Control and Select ...............................................................................
22.2.3.4.1 Algorithm Select ......................................................................................
22.2.3.4.2 Master PROT Enable ................................................................................
22.2.3.4.3 Software Reset .......................................................................................
22.2.3.4.4 Interrupt ...............................................................................................
22.2.3.4.5 Version and Configuration Registers ..............................................................
22.2.3.5 AES Engine ................................................................................................
22.2.3.5.1 Second Key / GHASH Key (internal, but clearable) .............................................
22.2.3.5.2 AES Key Registers (internal) .......................................................................
22.2.3.5.3 AES Initialization Vector Registers ................................................................
22.2.3.5.4 ES Input/Output Buffer Control & Mode Register ................................................
22.2.3.5.5 AES Crypto Length Registers ......................................................................
22.2.3.5.6 Authentication Length Register ....................................................................
22.2.3.5.7 Data Input/Output Registers ........................................................................
22.2.3.5.8 TAG Registers ........................................................................................
22.2.3.6 HASH Core ................................................................................................
22.2.3.6.1 Introduction ...........................................................................................
22.2.3.6.2 Data Input Registers .................................................................................
22.2.3.6.3 Input/Output Buffer Control & Status Register ...................................................
22.2.3.6.4 Mode Registers .......................................................................................
22.2.3.6.5 Length Registers .....................................................................................
22.2.3.6.6 Hash Digest Registers ...............................................................................
22.2.3.7 Key Store ..................................................................................................
22.2.3.7.1 Key Store Write Area Register .....................................................................
22.2.3.7.2 Key Store Written Area Register ...................................................................
22.2.3.7.3 Key Store Size Register .............................................................................
22.2.3.7.4 Key Store Read Area Register .....................................................................
22.2.4 Performance ....................................................................................................
22.2.4.1 Introduction ................................................................................................
22.2.4.2 Performance ...............................................................................................
22.2.5 Programming Guidelines ......................................................................................
22.2.5.1 One Time Initialization After a Reset ...................................................................
22.2.5.2 DMAC and Master Control ..............................................................................
22.2.5.2.1 Regular use ...........................................................................................
22.2.5.2.2 Interrupting DMA Transfers .........................................................................
22.2.5.2.3 Interrupts and HW/SW Synchronization ..........................................................
22.2.5.3 Hashing ....................................................................................................
22.2.5.3.1 Data Format and Byte Order .......................................................................
22.2.5.3.2 Basic Hash With Data From the DMA .............................................................
22.2.5.3.3 HMAC ..................................................................................................
22.2.5.3.4 Alternative Basic Hash Where Data Originates From the Slave Interface ...................
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22.3

22.4

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Radio

.............................................................................................................................. 659

23.1

RF Core ...................................................................................................................
23.1.1 Interrupts ........................................................................................................
23.1.2 Interrupt Registers .............................................................................................
FIFO Access ..............................................................................................................
DMA .......................................................................................................................
Memory Map ..............................................................................................................

23.2
23.3
23.4
14

22.2.5.4 Encryption/Decryption ....................................................................................
22.2.5.4.1 Data Format and Byte Order .......................................................................
22.2.5.4.2 Key Store ..............................................................................................
22.2.5.4.3 Basic AES Modes ....................................................................................
22.2.5.4.4 AES-GCM .............................................................................................
22.2.5.4.5 CBC-MAC .............................................................................................
22.2.5.4.6 AES-CCM .............................................................................................
22.2.5.5 Exceptions Handling ......................................................................................
22.2.5.5.1 Soft Reset .............................................................................................
22.2.5.5.2 External Port Errors ..................................................................................
22.2.5.5.3 Key Store Errors .....................................................................................
22.2.6 Conventions and Compliances ...............................................................................
22.2.6.1 Conventions Used in This Manual ......................................................................
22.2.6.1.1 Acronyms .............................................................................................
22.2.6.1.2 Terminology ...........................................................................................
22.2.6.1.3 Formulae and Nomenclature .......................................................................
22.2.6.1.4 Register Information .................................................................................
22.2.6.2 Compliances ...............................................................................................
Public Key Processor ....................................................................................................
22.3.1 Advanced Interrupt Controller ................................................................................
22.3.2 Registers ........................................................................................................
22.3.2.1 Register Address Map ...................................................................................
22.3.2.2 Register Description ......................................................................................
22.3.2.2.1 Engine Registers .....................................................................................
22.3.3 Advanced Interrupt Controller (Optional) ...................................................................
22.3.3.1 Introduction ................................................................................................
22.3.3.2 Functional Description ...................................................................................
22.3.3.3 Interrupt Sources .........................................................................................
22.3.3.4 AIC Registers .............................................................................................
22.3.3.4.1 AIC Polarity Control Register (AIC_POL_CTRL) ................................................
22.3.3.4.2 AIC Type Control Register (AIC_TYPE_CTRL) ..................................................
22.3.3.4.3 4.4.3 AIC Enable Control Register (AIC_ENABLE_CTRL) .....................................
22.3.3.4.4 AIC Raw Source Status Register (AIC_RAW_STAT) ...........................................
22.3.3.4.5 AIC Enabled Status Register (AIC_ENABLED_STAT) .........................................
22.3.3.4.6 AIC Acknowledge Register (AIC_ACK) ...........................................................
22.3.3.4.7 AIC Enable Set Register (AIC_ENABLE_SET) ..................................................
22.3.3.4.8 AIC Enable Clear Register (AIC_ENABLE_CLR) ................................................
22.3.3.4.9 AIC Options Register (AIC_OPTIONS) ...........................................................
22.3.3.4.10 AIC Version Register (AIC_VERSION) ..........................................................
AES and PKA Registers ................................................................................................
22.4.1 AES Registers ..................................................................................................
22.4.1.1 AES Registers Mapping Summary .....................................................................
22.4.1.2 AES Register Descriptions ..............................................................................
22.4.2 PKA Registers ..................................................................................................
22.4.2.1 PKA Registers Mapping Summary .....................................................................
22.4.2.2 PKA Register Descriptions ..............................................................................

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23.5
23.6
23.7

23.8

23.9

23.10

23.11
23.12
23.13

23.4.1 RX FIFO .........................................................................................................
23.4.2 TX FIFO .........................................................................................................
23.4.3 Frame-Filtering and Source-Matching Memory Map ......................................................
Frequency and Channel Programming ................................................................................
IEEE 802.15.4-2006 Modulation Format ..............................................................................
IEEE 802.15.4-2006 Frame Format ...................................................................................
23.7.1 PHY Layer ......................................................................................................
23.7.2 MAC Layer ......................................................................................................
Transmit Mode ...........................................................................................................
23.8.1 TX Control ......................................................................................................
23.8.2 TX State Timing ................................................................................................
23.8.3 TX FIFO Access ...............................................................................................
23.8.4 Retransmission .................................................................................................
23.8.5 Error Conditions ................................................................................................
23.8.6 TX Flow Diagram ..............................................................................................
23.8.7 Frame Processing .............................................................................................
23.8.8 Synchronization Header .......................................................................................
23.8.9 Frame-Length Field ............................................................................................
23.8.10 Frame-Check Sequence .....................................................................................
23.8.11 Interrupts ......................................................................................................
23.8.12 Clear-Channel Assessment .................................................................................
23.8.13 Output Power Programming ................................................................................
23.8.14 Tips and Tricks ...............................................................................................
Receive Mode ............................................................................................................
23.9.1 RX Control ......................................................................................................
23.9.2 RX State Timing ................................................................................................
23.9.3 Frame Processing .............................................................................................
23.9.4 Synchronization Header and Frame-Length Fields .......................................................
23.9.5 Frame Filtering .................................................................................................
23.9.5.1 Filtering Algorithm ........................................................................................
23.9.5.2 Interrupts ...................................................................................................
23.9.5.3 Tips and Tricks ............................................................................................
23.9.6 Source Address Matching ....................................................................................
23.9.6.1 Applications ................................................................................................
23.9.6.2 The Source Address Table ..............................................................................
23.9.6.3 Address Enable Registers ...............................................................................
23.9.6.4 Matching Algorithm .......................................................................................
23.9.6.5 Interrupts ...................................................................................................
23.9.6.6 Tips and Tricks ............................................................................................
23.9.7 Frame-Check Sequence ......................................................................................
23.9.8 Acknowledgement Transmission ............................................................................
23.9.8.1 Transmission Timing .....................................................................................
23.9.8.2 Manual Control ............................................................................................
23.9.8.3 Automatic Control (AUTOACK) .........................................................................
23.9.8.4 Automatic Setting of the Frame Pending Field (AUTOPEND) ......................................
RX FIFO Access .........................................................................................................
23.10.1 Using the FIFO and FIFOP Signals ........................................................................
23.10.2 Error Conditions ..............................................................................................
23.10.3 RSSI ............................................................................................................
23.10.4 Link Quality Indication .......................................................................................
Radio Control State-Machine ..........................................................................................
Random Number Generation ..........................................................................................
Packet Sniffing and Radio Test Output Signals .....................................................................

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23.14 Command Strobe/CSMA-CA Processor ..............................................................................
23.14.1 Instruction Memory ...........................................................................................
23.14.2 Data Registers ................................................................................................
23.14.3 Program Execution ...........................................................................................
23.14.4 Interrupt Requests ............................................................................................
23.14.5 Random Number Instruction ................................................................................
23.14.6 Running CSP Programs .....................................................................................
23.14.7 CSP Registers ................................................................................................
23.14.8 Instruction Set Summary ....................................................................................
23.14.9 Instruction Set Definition .....................................................................................
23.14.9.1 DECZ ......................................................................................................
23.14.9.2 DECY .....................................................................................................
23.14.9.3 DECX .....................................................................................................
23.14.9.4 INCZ .......................................................................................................
23.14.9.5 INCY ......................................................................................................
23.14.9.6 INCX ......................................................................................................
23.14.9.7 INCMAXY .................................................................................................
23.14.9.8 RANDXY ..................................................................................................
23.14.9.9 INT .........................................................................................................
23.14.9.10 WAITX ...................................................................................................
23.14.9.11 SETCMP1 ...............................................................................................
23.14.9.12 WAIT W .................................................................................................
23.14.9.13 WEVENT1 ..............................................................................................
23.14.9.14 WEVENT2 ..............................................................................................
23.14.9.15 LABEL ...................................................................................................
23.14.9.16 RPT C ...................................................................................................
23.14.9.17 SKIP S, C ...............................................................................................
23.14.9.18 STOP ....................................................................................................
23.14.9.19 SNOP ....................................................................................................
23.14.9.20 SRXON ..................................................................................................
23.14.9.21 STXON ..................................................................................................
23.14.9.22 STXONCCA ............................................................................................
23.14.9.23 SSAMPLECCA .........................................................................................
23.14.9.24 SRFOFF .................................................................................................
23.14.9.25 SFLUSHRX .............................................................................................
23.14.9.26 SFLUSHTX .............................................................................................
23.14.9.27 SACK ....................................................................................................
23.14.9.28 SACKPEND .............................................................................................
23.14.9.29 SNACK ..................................................................................................
23.14.9.30 SRXMASKBITSET .....................................................................................
23.14.9.31 SRXMASKBITCLR .....................................................................................
23.14.9.32 ISSTOP ..................................................................................................
23.14.9.33 ISSTART ................................................................................................
23.14.9.34 ISRXON .................................................................................................
23.14.9.35 ISRXMASKBITSET ....................................................................................
23.14.9.36 ISRXMASKBITCLR ....................................................................................
23.14.9.37 ISTXON .................................................................................................
23.14.9.38 ISTXONCCA ............................................................................................
23.14.9.39 ISSAMPLECCA ........................................................................................
23.14.9.40 ISRFOFF ................................................................................................
23.14.9.41 ISFLUSHRX ............................................................................................
23.14.9.42 ISFLUSHTX .............................................................................................
23.14.9.43 ISACK ...................................................................................................
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24
A

B
C

D
E

23.14.9.44 ISACKPEND ............................................................................................
23.14.9.45 ISNACK .................................................................................................
23.14.9.46 ISCLEAR ................................................................................................
23.15 Register Settings Update ...............................................................................................
23.16 Radio Registers ..........................................................................................................
23.16.1 RFCORE_FFSM Registers .................................................................................
23.16.1.1 RFCORE_FFSM Registers Mapping Summary .....................................................
23.16.1.2 RFCORE_FFSM Register Descriptions ..............................................................
23.16.2 RFCORE_XREG Registers .................................................................................
23.16.2.1 RFCORE_XREG Registers Mapping Summary .....................................................
23.16.2.2 RFCORE_XREG Register Descriptions ..............................................................
23.16.3 RFCORE_SFR Registers ...................................................................................
23.16.3.1 RFCORE_SFR Registers Mapping Summary .......................................................
23.16.3.2 RFCORE_SFR Register Descriptions ................................................................
23.16.4 CCTEST Registers ...........................................................................................
23.16.4.1 CCTEST Registers Mapping Summary ..............................................................
23.16.4.2 CCTEST Register Descriptions ........................................................................
23.16.5 ANA_REGS Registers .......................................................................................
23.16.5.1 ANA_REGS Registers Mapping Summary ...........................................................
23.16.5.2 ANA_REGS Register Descriptions ....................................................................

702
703
703
703
704
704
704
705
712
712
715
748
749
749
752
752
752
757
757
757

............................................................................................................
Available Software ...........................................................................................................
A.1
SmartRF™ Studio Software for Evaluation (www.ti.com/smartrfstudio) ..........................................
A.2
TIMAC Software (www.ti.com/timac) ..................................................................................
A.3
Z-Stack™ Software (www.ti.com/z-stack) ............................................................................
Abbreviations ..................................................................................................................
Additional Information ......................................................................................................
C.1
Texas Instruments Low-Power RF Web Site .........................................................................
C.2
Low-Power RF Online Community .....................................................................................
C.3
Texas Instruments Low-Power RF Developer Network .............................................................
C.4
Low-Power RF eNewsletter .............................................................................................
References ......................................................................................................................
Revision History ..............................................................................................................
E.1
Revision History – External .............................................................................................

759

Voltage Regulator

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Contents
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List of Figures
1-1.

CC2538 Block Diagram ...................................................................................................

2-1.

CPU Block Diagram .......................................................................................................

2-2.

TPIU Block Diagram

......................................................................................................

2-3.

Cortex-M3 Register Set ...................................................................................................

3-1.

SRD Use Example

........................................................................................................
Bit-Band Mapping ........................................................................................................
Data Storage..............................................................................................................
Vector Table ..............................................................................................................
Exception Stack Frame .................................................................................................
Test/Debug System Top Level Diagram ..............................................................................
Flow Diagram for Operational Modes .................................................................................
Simple Flow Diagram for Power Management .......................................................................
Timing Example for Transition from 32 MHz to PM's ...............................................................
Simplified Figure of Current Consumption in PM1 ..................................................................
Simplified Figure of Current Consumption in PM2 and PM3 .......................................................
Block Diagram Oscillators and Clocks ................................................................................
Flash Write Using DMA .................................................................................................
Digital I/O Pads (The Diagram Shows One of 32 Possible I/O Pins) .............................................
GPIODATA Write Example .............................................................................................
GPIODATA Read Example .............................................................................................
PAD Configuration Override Registers ................................................................................
μDMA Block Diagram ...................................................................................................
Example of Ping-Pong μDMA Transaction ...........................................................................
Memory Scatter-Gather, Setup and Configuration ..................................................................
Memory Scatter-Gather, μDMA Copy Sequence ....................................................................
Peripheral Scatter-Gather, Setup and Configuration ................................................................
Peripheral Scatter-Gather, μDMA Copy Sequence .................................................................
GPTM Module Block Diagram ..........................................................................................
Input Edge-Count Mode Example, Counting Down .................................................................
Input Edge-Time Mode Example .......................................................................................
16-bit PWM Mode Example ............................................................................................
CCP Output, GPTIMER_TnMATCHR > GPTIMER_TnILR ........................................................
CCP Output, GPTIMER_TnMATCHR = GPTIMER_TnILR ........................................................
CCP Output, GPTIMER_TnILR > GPTIMER_TnMATCHR ........................................................
Timer Daisy-Chain .......................................................................................................
Sleep timer Capture .....................................................................................................
ADC Block Diagram .....................................................................................................
Basic Structure of the RNG .............................................................................................
Analog Comparator ......................................................................................................
UART Module Block Diagram ..........................................................................................
UART Character Frame .................................................................................................
LIN Message..............................................................................................................
LIN Synchronization Field ...............................................................................................
SSI Module Block Diagram .............................................................................................
TI Synchronous Serial Frame Format (Single Transfer) ............................................................
TI Synchronous Serial Frame Format (Continuous Transfer) ......................................................
Freescale SPI Format (Single Transfer) With SPO = 0 and SPH = 0 ............................................

4-1.
4-2.
5-1.
5-2.
6-1.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
8-1.
9-1.
9-2.
9-3.
9-4.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
13-1.
15-1.
16-1.
17-1.
18-1.
18-2.
18-3.
18-4.
19-1.
19-2.
19-3.
19-4.
18

List of Figures

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19-5.

Freescale SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0 ......................................

19-6.

Freescale SPI Frame Format With SPO = 0 and SPH = 1 .........................................................

421

19-7.

Freescale SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0 ....................................

421

19-8.

Freescale SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0 ..............................

422

19-9.

Freescale SPI Frame Format With SPO = 1 and SPH = 1 .........................................................

422

19-10. MICROWIRE Frame Format (Single Frame) .........................................................................

423

420

................................................................

424

19-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements .....................................

424

20-1.

I2C Block Diagram........................................................................................................

435

20-2.

I C Bus Configuration ....................................................................................................

436

20-3.

Start and Stop Conditions...............................................................................................

436

20-4.

Complete Data Transfer With a 7-Bit Address .......................................................................

437

20-5.

R/S Bit in First Byte ......................................................................................................

437

20-6.

Data Validity During Bit Transfer on the I2C Bus.....................................................................

437

20-7.

Master Single TRANSMIT ..............................................................................................

440

20-8.

Master Single RECEIVE ................................................................................................

441

20-9.

Master TRANSMIT With Repeated Start Condition .................................................................

442

19-11. MICROWIRE Frame Format (Continuous Transfer)

20-10. Master RECEIVE With Repeated Start Condition ...................................................................

443

20-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition .....................

444

20-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition .....................

445

20-13. Slave Command Sequence

446

21-1.

............................................................................................
USB Controller Block Diagram .........................................................................................
USB Interrupt Service Routine .........................................................................................
Endpoint 0 States ........................................................................................................
Endpoint 0 Service Routine.............................................................................................
SETUP Phase of Control Transfer.....................................................................................
SETUP Phase Control Transactions ..................................................................................
IN Data Phase for Control Transfer ...................................................................................
IN Phase Control Transactions.........................................................................................
Control Transactions Following Status Stage (TX Mode) ..........................................................
OUT Data Phase for Control Transfer ................................................................................
OUT Phase Control Transactions......................................................................................
Control Transactions Following Status Stage (RX Mode) ..........................................................
IN/OUT FIFOs ............................................................................................................
Bulk and Interrupt IN Transactions ....................................................................................
Isochronous IN Transactions ...........................................................................................
Bulk and Interrupt OUT Transactions .................................................................................
Isochronous OUT Transactions ........................................................................................
Operation Sequences and Main Interrupt ............................................................................
DMA Controller and Its Integration ....................................................................................
Symmetric Crypto Processing Steps ..................................................................................
Implementation of Secure HMAC Operation .........................................................................
AIC: Functional Logic of one Interrupt Source .......................................................................
Modulation ................................................................................................................
I and Q Phases When Transmitting a Zero-Symbol Chip Sequence, tC = 0.5 μs ...............................
Schematic View of the IEEE 802.15.4 Frame Format ..............................................................
Format of the Frame Control Field (FCF) .............................................................................
Frame Data Written to the TX FIFO ...................................................................................
TX Flow....................................................................................................................

458

21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
22-1.
22-2.
22-3.
22-4.
22-5.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.

SWRU319C – April 2012 – Revised May 2013
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List of Figures
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23-7.

Transmitted Synchronization Header..................................................................................

670

23-8.

FCS Hardware Implementation ........................................................................................

671

23-9.

SFD Signal Timing .......................................................................................................

673

23-10. Filtering Scenarios (Exceptions Generated During Reception) ....................................................

675

23-11. Matching Algorithm for Short and Extended Addresses ............................................................

677

23-12. Interrupts Generated by Source Address Matching .................................................................

678

23-13. Data in RX FIFO for Different Settings ................................................................................

679

23-14. Acknowledge Frame Format

679

23-15.

...........................................................................................
Acknowledgement Timing...............................................................................................
Command Strobe Timing ...............................................................................................
Behavior of FIFO and FIFOP Signals .................................................................................
Main FSM .................................................................................................................
FFT of the Random Bytes ..............................................................................................
Histogram of 20 Million Bytes Generated With the RANDOM Instruction ........................................
Running a CSP Program ................................................................................................

680

23-16.
23-17.
23-18.
23-19.
23-20.
23-21.

List of Figures

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List of Tables
0-1.

Document Conventions ...................................................................................................

2-1.

Summary of Processor Mode, Privilege Level, and Stack Use

.....................................................
Processor Register Map ..................................................................................................
PSR Register Combinations .............................................................................................
Cortex-M3 Instruction Summary .........................................................................................
Core Peripheral Register Regions ......................................................................................
Memory Attributes Summary .............................................................................................
TEX, S, C, and B Bit Field Encoding....................................................................................
Cache Policy for Memory Attribute Encoding ..........................................................................
AP Bit Field Encoding .....................................................................................................
Memory Region Attributes for a CC2538 Microcontroller ............................................................
Peripherals Register Map ................................................................................................
Memory Map ..............................................................................................................
Memory Access Behavior ...............................................................................................
SRAM Memory Bit-Banding Regions ..................................................................................
Peripheral Memory Bit-Banding Regions .............................................................................
Exception Types .........................................................................................................
Interrupts ..................................................................................................................
Exception Return Behavior .............................................................................................
Faults ......................................................................................................................
Fault Status and Fault Address Registers ............................................................................
IEEE 1149.7 Signals .....................................................................................................
IEEE 1149.7 Features Subset..........................................................................................
Data Register description for instruction 0x0E(Read Only) ........................................................
Data Register Description for 0x0A ....................................................................................
Power Management Matrix .............................................................................................
Clock Gate Matrix ........................................................................................................
SYS_CTRL Register Summary ........................................................................................
Example Write Sequence ...............................................................................................
Flash Size Configuration ................................................................................................
Upper 32 Bytes of Lock Bit Page and CCA layout ..................................................................
Fields at POR/ Reset ....................................................................................................
32 Bitfield of the Lock bit page .........................................................................................
Layout of Byte 2007 .....................................................................................................
Flash Controller Priorities ...............................................................................................
ICEpick TAP State .......................................................................................................
Data Register Description for Instruction 0x0E (READ ONLY) ....................................................
FLASH_CTRL Register Summary .....................................................................................
Pheripheral Signal Select Values (Same for All IOC_Pxx_SEL Registers) ......................................
GPIO Common Registers Mapping Summary .......................................................................
GPIO_A Register Summary ............................................................................................
GPIO_B Register Summary ............................................................................................
GPIO_C Register Summary ............................................................................................
GPIO_D Register Summary ............................................................................................
IOC Register Summary .................................................................................................
μDMA Channel Assignments ...........................................................................................
Request Type Support ..................................................................................................

2-2.
2-3.
2-4.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
4-1.
4-2.
4-3.
4-4.
5-1.
5-2.
5-3.
5-4.
5-5.
6-1.
6-2.
6-3.
6-4.
7-1.
7-2.
7-3.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
10-1.
10-2.

SWRU319C – April 2012 – Revised May 2013
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List of Tables
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50
56
61
66
69
71
72
72
72
73
156
158
160
160
166
167
173
174
175
178
179
183
183
186
195
197
216
219
220
221
221
221
222
223
223
225
231
238
239
240
240
241
255
288
290
21

Public Version

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10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
12-1.
13-1.
14-1.
15-1.
16-1.
17-1.
18-1.
18-2.
18-3.
18-4.
18-5.
19-1.
19-2.
19-3.
19-4.
20-1.
20-2.
20-3.
21-1.
21-2.
21-3.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22

........................................................................................
Channel Control Structure ..............................................................................................
μDMA Read Example: 8-Bit Peripheral ...............................................................................
μDMA Interrupt Assignments ...........................................................................................
Channel Control Structure Offsets for Channel 30 ..................................................................
Channel Control Word Configuration for Memory Transfer Example .............................................
Channel Control Structure Offsets for Channel 7 ....................................................................
Channel Control Word Configuration for Peripheral Transmit Example ..........................................
Primary and Alternate Channel Control Structure Offsets for Channel 8 .........................................
Channel Control Word Configuration for Peripheral Ping-Pong Receive Example .............................
UDMA Register Summary ..............................................................................................
General-Purpose Timer Capabilities ..................................................................................
16-Bit Timer With Prescaler Configurations ..........................................................................
Counter Values When the Timer is Enabled in Input Edge-Count Mode .........................................
Counter Values When the Timer is Enabled in Input Event-Count Mode ........................................
Counter Values When the Timer is Enabled in PWM Mode .......................................................
Time-out Actions for GPTM Modes ....................................................................................
GPTIMER Common Registers Mapping Summary ..................................................................
GPTIMER0 Register Summary ........................................................................................
GPTIMER1 Register Summary ........................................................................................
GPTIMER2 Register Summary ........................................................................................
GPTIMER3 Register Summary ........................................................................................
RFCORE_SFR Register Summary ....................................................................................
SMWDTHROSC Register Summary ..................................................................................
SMWDTHROSC Register Summary ..................................................................................
SOC_ADC Register Summary .........................................................................................
SOC_ADC Register Summary .........................................................................................
SOC_ADC Register Summary .........................................................................................
Signals for UART (64LQFP) ............................................................................................
Flow Control Mode .......................................................................................................
UART Common Registers Mapping Summary .......................................................................
UART0 Register Summary .............................................................................................
UART1 Register Summary .............................................................................................
Signals for SSI (64LQFP) ...............................................................................................
SSI Common Registers Mapping Summary ..........................................................................
SSI0 Register Summary ................................................................................................
SSI1 Register Summary ................................................................................................
Examples of I2C Master Timer Period versus Speed Mode ........................................................
I2CM Register Summary ................................................................................................
I2CS Register Summary ................................................................................................
USB Interrupt Flags and Associated Interrupt-Enable Mask Registers ...........................................
FIFO Sizes for EP1–EP5 ...............................................................................................
USB Register Summary .................................................................................................
Performance ..............................................................................................................
Summary of PKCP Vector Operations ................................................................................
Restrictions On Input Vectors for PKCP Operations ................................................................
PKCP Result Vector Memory Allocation ..............................................................................
PKCP Result Vector / Input Vector overlap restrictions.............................................................
Summary of ExpMod Operations ......................................................................................
Control Structure Memory Map

List of Tables

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291
300
301
302
302
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303
304
305
306
320
322
322
323
325
328
331
332
332
333
334
355
365
371
377
383
387
390
393
396
397
398
417
426
426
427
438
447
452
459
476
486
502
503
504
504
505
505

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22-7.

Restrictions on Input Vectors for ExpMod Operations ..............................................................

22-8.

ExpMod Result Vector/Scratchpad Area Memory Allocation.......................................................

507

22-9.

ExpMod Scratchpad Area / Input Vector Overlap Restrictions

....................................................
Required PKA RAM Sizes for Exponentiations ......................................................................
Maximum Number of Odd Powers for 2K Byte PKA RAM Size ...................................................
Summary of ModInv Operation.........................................................................................
PKA_SHIFT Result Values for ModInv Operation ...................................................................
Operational Restrictions on Input Vectors for the ModInv Operation .............................................
ModInv Scratchpad Area / Input Vector Overlap Restrictions......................................................
ModInv Result Vector/Scratchpad Area Memory Allocation........................................................
Summary of ECC Operations ..........................................................................................
PKA_SHIFT Result Values for ECC Operations .....................................................................
Operational Restrictions on Input Vectors for ECC Operations....................................................
ECC Scratchpad Area / Input Vector Overlap Restrictions .........................................................
ECC Result Vector/Scratchpad Area memory Allocation ...........................................................
Basic PKCP Operations Performance ................................................................................
Exponentiation Performance for 16-bit PKCP-only ..................................................................
ModInv Performance ....................................................................................................
ECC-ADD Performance .................................................................................................
ECC-MUL Performance .................................................................................................
PKA_APTR ...............................................................................................................
PKA_BPTR ...............................................................................................................
PKA_CPTR ...............................................................................................................
PKA_DPTR ...............................................................................................................
PKA_ALENGTH ..........................................................................................................
PKA_BLENGTH ..........................................................................................................
PKA_SHIFT ...............................................................................................................
PKA_FUNCTION .........................................................................................................
PKA_COMPARE .........................................................................................................
PKA_MSW ................................................................................................................
PKA_DIVMSW ...........................................................................................................
PKA_SEQ_CTRL ........................................................................................................
PKA_OPTIONS ..........................................................................................................
PKA_SW_REV ...........................................................................................................
PKA_REVISION ..........................................................................................................
PKA_RAM.................................................................................................................
PKA_PROGRAM .........................................................................................................
Register Names and Detail .............................................................................................
Supported DMAC Operations ..........................................................................................
DMAC Channel Control Register ......................................................................................
DMAC Channel External Address .....................................................................................
DMAC Channel Length ..................................................................................................
DMAC Status .............................................................................................................
DMAC Software Reset ..................................................................................................
DMAC Master Run-Time Parameters .................................................................................
DMAC Port Error Raw Status ..........................................................................................
DMAC Options Register.................................................................................................
DMAC Version Register .................................................................................................
Master Control Algorithm Select (CTRL_ALG_SEL) ................................................................

507

22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
22-51.
22-52.
22-53.
22-54.
22-55.

SWRU319C – April 2012 – Revised May 2013
Submit Documentation Feedback

List of Tables
Copyright © 2012–2013, Texas Instruments Incorporated

506

508
508
508
509
509
509
509
510
510
511
511
511
511
512
514
514
515
516
516
516
517
517
517
518
518
519
520
520
521
522
522
523
523
524
532
536
536
537
537
538
538
539
540
540
541
541
23

Public Version

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.....................................................................
22-57. Master Control Algorithm Select .......................................................................................
22-58. Software Reset ...........................................................................................................
22-59. Interrupt Configuration...................................................................................................
22-60. Interrupt Enable ..........................................................................................................
22-61. Interrupt Clear ............................................................................................................
22-62. Interrupt Set...............................................................................................................
22-63. Interrupt Status ...........................................................................................................
22-64. Options Register .........................................................................................................
22-65. Version Register .........................................................................................................
22-66. AES_KEY .................................................................................................................
22-67. AES_KEY .................................................................................................................
22-68. .............................................................................................................................
22-69. Key Registers Used Per Key Size .....................................................................................
22-70. Table 39AES Initialization Vector Registers .........................................................................
22-71. AES Input/Output Control and Mode Register .......................................................................
22-72. Crypto Data Length Register (LSW) ...................................................................................
22-73. Crypto Data Length Register (MSW) ..................................................................................
22-74. Authentication Length Register ........................................................................................
22-75. Data Input/Output Register .............................................................................................
22-76. .............................................................................................................................
22-77. Input/Output Block Format Per Operating Mode .....................................................................
22-78. AES Tag Output Register ...............................................................................................
22-79. Hash Data Input Register ..............................................................................................
22-80. Hash I/O Buffer Control .................................................................................................
22-81. Hash Mode Register .....................................................................................................
22-82. Hash Length Register ..................................................................................................
22-83. Hash Digest Registers...................................................................................................
22-84. Key Store Write Area Register .........................................................................................
22-85. Key Store Written Area (Status) Register.............................................................................
22-86. Key Store Size Register .................................................................................................
22-87. Key Store Read Area Register .........................................................................................
22-88. Performance Table for DMA-Based Operations .....................................................................
22-89. Mapping of Internal Address Bus to the External Address Bus ....................................................
22-90. PKP_REVISION ..........................................................................................................
22-91. PKP_OPTIONS ..........................................................................................................
22-92. PKP Interrupt Sources ..................................................................................................
22-93. AIC_POL_CTRL..........................................................................................................
22-94. AIC_TYPE_CTRL ........................................................................................................
22-95. AIC_ENABLE_CTRL ....................................................................................................
22-96. AIC_RAW_STAT .........................................................................................................
22-97. AIC_ENABLED_STAT ..................................................................................................
22-98. AIC_ACK ..................................................................................................................
22-99. AIC_ENABLE_SET ......................................................................................................
22-100. AIC_ENABLE_CLR.....................................................................................................
22-101. AIC_OPTIONS ..........................................................................................................
22-102. AIC_VERSION ..........................................................................................................
22-103. AES Register Summary ...............................................................................................
22-104. PKA Register Summary ...............................................................................................
22-56. Valid Combinations for CTRL_ALG_SEL Flags

List of Tables

542
543
543
544
544
545
545
546
547
548
549
549
550
550
551
551
554
554
555
556
556
558
558
559
560
563
563
564
565
566
567
567
569
588
588
589
591
592
593
593
594
594
594
595
595
596
596
597
648

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23-1.

Interrupt Registers Register Map ......................................................................................

23-2.

Frame Filtering and Source Matching Memory Map ................................................................

662

23-3.

IEEE 802.15.4-2006 Symbol-to-Chip Mapping.......................................................................

664

23-4.

FSM State Mapping

.....................................................................................................
CSP Registers Register Map ...........................................................................................
Instruction Set Summary ................................................................................................
Registers That Require Update From Their Default Value .........................................................
RFCORE_FFSM Register Summary ..................................................................................
RFCORE_XREG Register Summary ..................................................................................
RFCORE_SFR Register Summary ....................................................................................
CCTEST Register Summary ...........................................................................................
ANA_REGS Register Summary........................................................................................

684

23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.

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661

689
690
703
704
712
749
752
757

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Preface
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About This Document
This user's guide provides information on how to use the CC2538 and describes the functional blocks of
the system-on-chip (SoC) designed around the ARM® Cortex™-M3 core and an IEEE 802.15.4 radio.

Audience
This manual is intended for system software developers, hardware designers, and application developers.

About This Manual
This document is organized into sections that correspond to each major feature. This document does not
contain performance characteristics of the device or modules. These are gathered in the corresponding
device data sheet.

Related Documents
The following related documents are available on the CC2538 product page at www.ti.com:
• CC2538 Data Sheet
• CC2538 Errata
• CC2538 ROM User's Guide
• CC2538 Peripheral Driver Library User's Guide
The following related documents are also referenced:
• IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This list of documents was current as of publication date. Check the web site for additional documentation,
including application notes and white papers.

Document Conventions
Table 0-1. Document Conventions
Register

Meaning
General Register Notation

Bit

A single bit in a register

Bit field

Two or more consecutive and related bits

Offset 0xnnn

APB registers are indicated in uppercase bold. For example,
GPTIMER_CFG configures the global operation of general
purpose timers. If a register name contains a lowercase n, it
represents more than one register. For example,
GPTIMER_TnMR represents any of the timer A or B mode
control registers: GPTIMER_TAMR, GPTIMER_TBMR.

A hexadecimal increment to the address of a register, relative to
the base address of that module as specified in

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Table 0-1. Document Conventions (continued)
Register

Meaning

Registers are numbered consecutively throughout the document
to aid in referencing them. The register number has no meaning
to software.

Reserved

Register bits marked reserved are reserved for future use. In
most cases, reserved bits are set to 0; however, user software
should not rely on the value of a reserved bit. To provide
software compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.

yy:xx

The range of register bits inclusive from xx to yy. For example,
31:15 means bits 15 through 31 in that register.

This value in the register bit diagram indicates whether software
running on the controller can change the value of the bit field.

Software can read this field. The bit or field is cleared by
hardware after reading the bit or field.

Software can read this field. Always write the chip reset value.

R/W

Software can read or write this field.

R/WC

Software can read or write this field. Writing to it with any value
clears the register.

R/W1C

Software can read or write this field. Writing 0 to a W1C bit does
not affect the bit value in the register. Writing 1 clears the value
of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status
bits where the read operation provides the interrupt status and
the write of the read value clears only the interrupts being
reported at the time the register was read.

R/W1S

Software can read or write 1 to this field. Writing 0 to a R/W1S
bit does not affect the bit value in the register.

W1C

Software can write this field. Writing 0 to a W1C bit does not
affect the bit value in the register. Writing 1 clears the value of
the bit in the register; the remaining bits remain unchanged.
Reading the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an
interrupt register.

Only a write by software is valid; a read of the register returns no
meaningful data.

This value in the register bit diagram shows the bit or field value
after any reset, unless noted.

Bit is cleared to 0 on chip reset.

Bit is set to 1 on chip reset.

–

Nondeterministic
Pin and Signal Notation

[]

Pin alternate function; a pin defaults to the signal without the
brackets.

Refers to the physical connection on the package.

Signal

Refers to the electrical signal encoding of a pin.

Assert a signal

deassert a signal

SIGNAL

Change the value of the signal from the logically False state to
the logically True state. For active high signals, the asserted
signal value is 1 (high); for active low signals, the asserted
signal value is 0 (low). The active polarity (high or low) is defined
by the signal name (see SIGNAL and SIGNAL below).
Change the value of the signal from the logically True state to
the logically False state.
Signal names are in uppercase and in the Courier font. An
overbar on a signal name indicates that it is active low. To
assert SIGNAL is to drive it low; to deassert SIGNAL is to drive it
high

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Table 0-1. Document Conventions (continued)
Register

Meaning

SIGNAL

Signal names are in uppercase and in the Courier font. An active
high signal has no overbar. To assert SIGNAL is to drive it high;
to deassert SIGNAL is to drive it low.
Numbers

An uppercase X indicates any of several values is allowed,
where X can be any legal pattern. For example, a binary value
of 0X00 can be 0100 or 0000, a hex value of 0xX is 0x0 or 0x1,
and so on.

Hexadecimal numbers have a prefix of 0x. For example, 0x00FF
is the hexadecimal number FF. All other numbers within register
tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix (for example,
1011b) and decimal numbers are written without a prefix or
suffix.

The Device
The CC2538 integrates an IEEE 802.15.4 (2.4 GHz) radio, ARM Cortex-M3 processor, security
acceleration, and enough flash and RAM to run the ZigBee IP® stack and SE2.0 profile without requiring
external memory. The CC2538 also includes hardware support for ECC and RSA public key calculations
and is aimed at Smart Grid applications such as ZigBee Smart Energy 2.0. The CC2538 device familiy
currently supports TI’s ZigBee PRO stack Z-Stack™ with associated profiles and the ZigBee IP stack with
Smart Energy 2.0 profile.
The usage is, however, not limited to these protocols alone. The CC2538 is, for example, also suitable for
6LoWPAN and wireless HART implementations.
The CC2538 is suited for systems where very low power consumption is required. Very low-power sleep
modes are available. Short transition times between operating modes further enable low power
consumption.
For a complete feature list of any of the devices, see the corresponding data sheet.

Community Resources
All technical support is channeled through the TI Product Information Centers (PIC) - www.ti.com/support.
To send an E-mail request, please enter your contact information, along with your request at the following
link – PIC request form.
The following link connects to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki — Texas Instruments Embedded Processors Wiki
Established to assist developers using the many Embedded Processors from TI to get started, help each
other innovate, and foster the growth of general knowledge about the hardware and software surrounding
these devices.

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Register, Field, and Bit Calls
The naming convention applied for a call consists of:
• For a register call: .; for example: UART.UASR
• For a bit field call:
– .[End:Start] field; for example, UART.UASR[4:0]
SPEED bit field
– field .[End:Start]; for example, SPEED bit field
UART.UASR[4:0]
• For a bit call:
– .[pos] bit; for example, UART.UASR[5]
BIT_BY_CHAR bit
– bit .[pos]; for example, BIT_BY_CHAR bit
UART.UASR[5]
To help the reader navigate the document, each register call is hyperlinked to its register description in the
register manual section. After each register description, a table summarizes all hyperlinked register calls.
To navigate in the PDF documents, see Acrobat Reader Tips.

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Flow Chart Rules
Flow charts follow the following rules:
Shape

Start/Stop

The height of the text box
and its associated line
increases or decreases as
you add text. To change the
width of the comment, drag
the side handle.

Name

Definition

Process

Any computational steps or processing function of a program; defined
operation(s) causing change in value, form, or location of information

Decision

A decision or switching-type operation that determines which of a number
of alternate paths is followed

Predefined process or subprocess

One or more named operations or program steps specified in a
subroutine or another set of flow charts

Data or I/O

General I/O function; information available for processing (input) or
recording of processed information (output)

Terminator

Terminal point in a flow chart: start, stop, halt, delay, or interrupt; may
show exit from a closed subroutine

Annotation

Additional descriptive clarification, comment

On page connector (reference)

Exit to, or entry from, another part of chart in the same page

Off page connector (reference)

The flow continues on a different page.

Summing Junction

Logical AND

Logical OR

Parallel mode (ISO)

Beginning or end of two or more simultaneous operations

Flow Line

Lines indicate the sequence of steps and the direction of flow.

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Acrobat Reader Tips
Acrobat includes two methods to search for words in a PDF:
• The Find toolbar provides a basic set of options to locate a word in the current PDF.
• The Search window lists words or partial words that match your text in the current PDF.
These guidelines apply to Acrobat Reader 5.x, 6.0, and 7.0.
For more information on Acrobat Reader search features, see the Adobe Reader Help.
To search for words in a document using the Find dialog box:
1. Open the document.
2. To display the Find toolbar, right-click in the toolbar area and select Find.
3. In the Find box, type the word, words, or partial words for which you want to search.
4. From the Find Options menu, select options as desired.
5. To view each search result, click the Find toolbar, the Find Previous button, or the Find Next button to
go backward or forward through the document.
To search for words in a document using the Search PDF window:
1. Open the document.
2. Click the Search button on the File toolbar or right-click on your document and select Search.
3. Type the word, words, or part of a word for which you want to search.
4. Click Search.
5. The results appear in page order and, if applicable, show a few words of context. Each result displays
an icon to identify the type of occurrence. All other searchable areas display the Search Result icon.
6. To display the page that contains a search result, click an item in the Results list. The occurrence is
highlighted.
7. To navigate to the next result, choose Edit > Search Results > Next Result (or Ctrl+G).
8. To navigate to the previous result, choose Edit > Search Results > Previous Result (or Shift+Ctrl+G).
Navigate through your previous view
To retrace your path within an Adobe PDF document:
• For the previous view: Choose View > Go To > Previous View or Alt+Left Arrow.
• For the next view: Choose View > Go To > Next View or Alt+Right Arrow. The Next View command is
available only if you have chosen Previous View.
If you view the PDF document in a browser, use options on the Navigation toolbar to move between
views.
• Right-click the toolbar area, and then choose Navigation.
• Click the Go To Previous View button or the Go To Next View button.
NOTE: This navigation tip is useful to return to your previous view after clicking on a register call
hyperlink.

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Chapter 1
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Architectural Overview
The CC2538 device family provides solutions for a wide range of applications. To help the user develop
these applications, this user's guide focuses on the use of the different building blocks of the CC2538
device family. For detailed device descriptions, complete feature lists, and performance numbers, see the
data sheet. To provide easy access to relevant information, the following subsections guide the reader to
the different chapters in this guide.
The CC2538 system-on-chip (SoC) is tailored to the requirements of complex mesh networking Internet Of
Things applications of which ZigBee® Smart Energy 2.0 is the most demanding on the hardware. The
combination of 32-MHz ARM® Cortex™-M3 processing, sufficient memory, and a wide selection of
peripherals makes the CC2538 device family ideal for single-chip implementation of ZigBee nodes.
Topic

1.1
1.2
1.3

...........................................................................................................................

Page

Target Applications ........................................................................................... 33
Overview .......................................................................................................... 33
Functional Overview .......................................................................................... 36

Architectural Overview

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Target Applications

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1.1

Target Applications
The CC2538 family is positioned for low-power wireless applications such as:
• IEEE 802.15.4 Radio Networks
• ZigBee Smart Energy 1.x and to 2.0 profiles
• Home and building automation
• Intelligent lighting systems
• Internet of Things - 6LoWPAN
• Industrial control and monitoring
• Consumer electronics
• Health care

1.2

Overview
Figure 1-1 shows the different building blocks of the CC2538.

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Overview

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ARM
Cortex – M3

DAP

128-KB/256-KB/512-KB flash

SWO
NVIC

32 MHz

MPU

16-KB retention SRAM

Debug
Interface

16-KB standard SRAM
c-JTAG/JTAG

4-KB ROM

ICEPick

SysTick timer
2 UARTS
Serial Interfaces

Timer/PWM/CCP
4x (32-bit or 2x16-bit)

2 SSI/SPI
Watchdog timer
USB Full Speed
Device

Security

32ch DMA

System

32 GPIO
2

32 MHz XTAL

AES-128/256
SHA-256

and 16-MHz RC oscillator

ECC
RSA-2048

and 32-kHz RC oscillator

32 kHz XTAL

32-bit sleep timer

Command strobe
processor
LDO regulator
Power-on reset and brown-out

MAC timer

detection

RF chain

Low-power
comparator

Demod

Synth

Modulator

Analog

IEEE 802.15.4 Radio

Packet handling
processor

12-bit ADC
With Temp Sensor

Figure 1-1. CC2538 Block Diagram
34

Architectural Overview

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The CC2538 device has the following features:
•

•

•
•
•

ARM Cortex-M3 processor core
– 32-MHz operation
– ARM Cortex SysTick timer
– Nested vectored interrupt controller (NVIC)
On-chip memory
– Up to 512KB single-cycle flash memory up to 16 MHz; a prefetch buffer improves performance
above 16 MHz
– Up to 32KB single-cycle SRAM
• Boot loader and utility library in ROM
Advanced serial integration
– USB 2.0 full-speed (FS) device (12 Mbps)
– Two universal asynchronous receiver/transmitters (UARTs) with IrDA, 9-bit (one UART with modem
flow control)
– One inter-integrated circuit (I2C™) module
– Two synchronous serial interface modules (SSIs)
System integration
– Direct memory access (DMA) controller
– System control and clocks including on-chip 16-MHz oscillator and 32-MHz crystal oscillator
– Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and
synchronization
– 32-bit, 32-kHz sleep timer
– Watchdog timer
– Clock loss detection circuit
– 32 GPIOs
– 8 GPIOs with analog capability; 4 of the GPIOs have 20-mA drive capability
– Fully flexible pin muxing allows use as GPIO or any peripheral function
– Power-management system with powerful low-power modes down to 500 nA with pin wakeup and
retention
Analog
– 12-bit analog-to-digital converter (ADC) with eight analog input channels
– Low-power analog comparator
– On-chip temperature and supply voltage sensing with the ADC
– On-chip voltage regulator
IEEE 1149.7 compliant cJTAG with legacy 1149.1 JTAG® support
56-pin QFN 8x8 mm package
Extended (–40°C to 125°C) temperature range

For applications requiring extreme conservation of power, the CC2538 device features a powermanagement system to efficiently power down the CC2538 device to a low-power state during extended
periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (which is a real-time
clock [RTC]) with interrupt and 16KB of RAM with retention in all power modes positions the CC2538
microcontroller perfectly for battery applications.
In addition, the CC2538 microcontroller offers the advantages of ARM's widely available development
tools, SoC infrastructure IP applications, and a large user community. Additionally, the microcontroller
uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby,
cost.

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TI offers a complete solution to get to market quickly, with evaluation and development boards, white
papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and
distributor network.

1.3

Functional Overview
The following sections provide an overview of the features of the CC2538 microcontroller. The page
number in parentheses indicates where that feature is discussed in detail.

1.3.1 ARM Cortex-M3
The following sections provide an overview of the ARM Cortex-M3 processor core and instruction set, the
integrated system timer (SysTick), and the NVIC.
1.3.1.1

Processor Core

The CC2538 is designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor
provides the core for a high-performance, low-cost platform that meets the needs of minimal memory
implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of
a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling data to be efficiently packed into memory
• Fast code execution permits slower processor clock or increases sleep mode time.
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system and memories
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Memory protection unit (MPU) provides a privileged mode for protected operating system functionality.
• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes
• cJTAG reduces the number of pins required for debugging.
• Ultra-low power consumption with integrated sleep modes
• 32-MHz operation
1.3.1.2

Memory Map

A memory map lists the location of instructions and data in memory. The memory map for the CC2538
can be found in the Memories section of this User's Guide. Register addresses are given as a
hexadecimal increment, relative to the base address of the module as shown in the memory map.
1.3.1.3

System Timer (SysTick)

ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-onwrite, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways; for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using the system clock 11
36

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•
•
•
1.3.1.4

A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter.
A simple counter used to measure time to completion and time used
An internal clock-source control based on missing or meeting durations
Nested Vector Interrupt Controller

The CC2538 controller includes the ARM NVIC. The NVIC and Cortex-M3 prioritize and handle all
exceptions in handler mode. The processor state is automatically stored to the stack on an exception and
automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector
is fetched in parallel to the state saving, thus enabling efficient interrupt entry. The processor supports tailchaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and
restoration. Software can set eight priority levels on seven exceptions (system handlers) and CC2538
interrupts.
• Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
• External nonmaskable interrupt (NMI) signal available for immediate execution of NMI handler for
safety critical applications
• Dynamically re-prioritizable interrupts
• Exceptional interrupt handling through hardware implementation of required register manipulations
1.3.1.5

System Control Block

The system control block (SCB) provides system implementation information and system control, including
configuration, control, and reporting of system exceptions.
1.3.1.6

MPU

The MPU supports the standard ARM7 protected memory system architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions, and
exporting memory attributes to the system.

1.3.2 On-Chip Memory
The following sections describe the on-chip memory modules.
1.3.2.1

SRAM

The CC2538 provides a 16KB block of single-cycle on-chip SRAM with full retention in all power modes. In
addition, some variants offer an additional 16KB of single-cycle on-chip SRAM without retention in the
lowest power modes.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding
technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory
map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic
operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.
1.3.2.2

Flash Memory

The flash block provides in-circuit programmable nonvolatile program memory for the device. The flash
memory is organized as a set of 2KB pages that can be individually erased. Erasing a block causes the
entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In
addition to holding program code and constants, the nonvolatile memory allows the application to save
data that must be preserved such that it is available after restarting the device. Using this feature one can,
for example, use saved network-specific data to avoid the need for a full start-up and network find-and-join
process.

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1.3.2.3

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ROM

The ROM is preprogrammed with a serial boot loader (SPI or UART). For applications that require in-field
programmability, the royalty-free CC2538 boot loader can act as an application loader and support in-field
firmware updates.

1.3.3 Radio
The CC2538 device family provides a highly integrated low-power IEEE 802.15.4-compliant radio
transceiver. The radio subsystem provides an interface between the MCU and the radio which makes it
possible to issue commands, read status, and automate and sequence radio events. The radio also
includes a packet-filtering and address-recognition module.

1.3.4 AES Engine with 128, 192 256 Bit Key Support
•
•
•
•
•
•
•
•

CCM, GCM, CTR, CBC-MAC, ECB modes of operation
SHA-256 hash function
Secure key storage memory
High throughput, low latency
Public key accelerator
Elliptic Curve Cryptography (ECC) and RSA-2048
Support for RSA-2048 makes it ideal for ESIs
Keeps the key exchange algorithms out of the CPU cycle budget and reduces energy consumption

1.3.5 Programmable Timers
Programmable timers can be used to count or time external events that drive the timer input pins. Each
16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer.
The general-purpose timer module (GPTM) contains four 16- or 32-bit GPTM blocks with the following
functional options:
•

•
•
•
•
•
•
•

16- or 32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM
signal
Count up or down
Eight 16- or 32-bit capture compare PWM pins (CCP)
Daisy-chaining of timer modules to allow a single timer to initiate multiple timing events
Timer synchronization allows selected timers to start counting on the same clock cycle.
User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the
interrupt service routine.
Efficient transfers using the µDMA controller:
– Dedicated channel for each timer
– Burst request generated on timer interrupt

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1.3.5.1

MAC Timer

The MAC timer is specially designed for supporting an IEEE 802.15.4 MAC or other time-slotted protocol
in software. The MAC timer has a configurable timer period and a 24-bit overflow counter that can be used
to keep track of the number of periods that have transpired. A 40-bit capture register is also used to record
the exact time at which a start-of-frame delimiter is received or transmitted or the exact time at which
transmission ends, as well as two 16-bit output compare registers and two 24-bit overflow compare
registers that can send various command strobes (start RX, start TX, and so forth) at specific times to the
radio modules.
1.3.5.2

Watchdog Timer

A watchdog timer is used to regain control when a system fails due to a software error or because an
external device does not respond in the expected way. When enabled by software, the watchdog timer
must be cleared periodically; otherwise, the watchdog timer resets the CC2538 device when it times out.
1.3.5.3

Sleep Timer

The sleep timer is an ultralow-power 32-bit timer that counts 32-kHz crystal oscillator or 32-kHz RC
oscillator periods. The sleep timer runs continuously in all operating modes except power mode 3 (PM3).
Typical applications of this timer are as a real-time counter or as a wake-up timer for coming out of power
mode 1 (PM1) or power mode 2 (PM2).
• 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution
• 32-bit RTC match register for timed wake-up and interrupt generation
1.3.5.4

CCP Pins

CCP pins can be used by the GPTM to time or count external events using the CCP pin as an input.
Alternatively, the GPTM can generate a simple PWM output on the CCP pin.
Any of the GPIOs can be programmed to operate in the following modes:
•
•

•

Capture: The GPTM is incremented or decremented by programmed events on the CCP input. The
GPTM captures and stores the current timer value when a programmed event occurs.
Compare: The GPTM is incremented or decremented by programmed events on the CCP input. The
GPTM compares the current value with a stored value and generates an interrupt when a match
occurs.
PWM: The GPTM is incremented or decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register; the PWM signal
is then output on the CCP pin.

1.3.6 Direct Memory Access
The CC2538 microcontroller includes a DMA controller, known as μDMA. The μDMA controller provides a
way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the
processor and the available bus bandwidth. The μDMA controller can perform transfers between memory
and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to
automatically perform transfers between peripherals and memory as the peripheral is ready to transfer
more data. The μDMA controller provides the following features:
•
•

•

ARM PrimeCell 32-channel configurable µDMA controller
Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer
modes:
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
Highly flexible and configurable channel operation:
– Independently configured and operated channels

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– Dedicated channels for supported on-chip modules
– Primary and secondary channel assignments
– Flexible channel assignments
– One channel each for RX and TX path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
Two levels of priority
Design optimizations for improved bus access performance between the µDMA controller and the
processor core:
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
Data sizes of 8, 16, and 32 bits
Transfer size is programmable in binary steps from 1 to 1024.
Source and destination address increment size of byte, half-word, word, or no increment
Maskable peripheral requests
Interrupt on transfer completion, with a separate interrupt per channel

1.3.7 System Control and Clock
System control determines the overall operation of the CC2538 device. System control provides
information about the CC2538 device, controls power-saving features, controls the clocking of the CC2538
device and individual peripherals, and handles reset detection and reporting.
•
•

•

Device identification information: version, part number, SRAM size, flash memory size, and so forth
Power control:
– On-chip fixed low drop-out (LDO) voltage regulator
– Handles the power-up and power-down sequencing and control for the core digital logic and analog
circuits
– Low-power options for the CC2538 microcontroller: Sleep and deep-sleep modes with clock gating
– Low-power options for on-chip modules: Software controls shutdown of individual peripherals and
memory
• General-purpose input/output (GPIO) states are retained in all power modes
• 16KB RAM and configuration registers are retained in all power modes
– Control pin option for control of external DC-DC regulator
– Configurable wakeup from sleep timer or any GPIO interrupt
– 3.3-V supply power-on-reset (POR) and 1.8-V brown-out reset (BOR) detection and reset
generation
Multiple clock sources for microcontroller system clock:
– RC oscillator (RCOSC16M): On-chip resource providing a 16-MHz frequency:
• Automatically calibrated against the 32-MHz XTAL oscillator when running
• Software power-down control for low-power modes
– 32-MHz crystal oscillator (XOSC32M): A frequency-accurate clock source by one of two means: an
external single-ended clock source is connected to the XOSC32M_Q1 input pin, or an external
crystal is connected across the XOSC32M_Q1 input and XOSC32M_Q2 output pins.
– Internal 32-kHz RC oscillator: on chip resource providing a 30 kHz frequency, used during powersaving modes
• Automatically calibrated against the 32-MHz XTAL oscillator when running
– 32.768-kHz crystal oscillator: A frequency-accurate clock source by one of two means: an external

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•

single-ended clock source is connected to the XOSC32K_Q1 input pin, or an external crystal is
connected across the XOSC32K_Q1 input and XOSC32K_Q2 output pins.
• Ideal for accurate RTC operation or synchronous network timing
– CPU and periphery clock division options down to 256 kHz
Flexible reset sources
– POR
– Reset pin assertion
– BOR detector alerts to system power drops
– Software reset
– Watchdog timer reset

1.3.8 Serial Communications Peripherals
The CC2538 device supports both asynchronous and synchronous serial communications with:
• USB 2.0 FS device
• Two UARTs with 9-bit
• I2C module
• Two SSI
The following sections provide more detail on each of these communications functions.
1.3.8.1

USB

Universal serial bus (USB) is a serial bus standard designed to allow peripherals to be connected and
disconnected using a standardized interface.
The CC2538 device supports the USB 2.0 FS configuration in device mode and has the following features:
•
•
•
•
•
•
•
1.3.8.2

Complies with USB-IF certification standards
USB 2.0 full speed (12 Mbps) operation with integrated PHY
4 transfer types: control, interrupt, bulk, and isochronous
Five IN and five OUT configurable endpoints
Support for packet sizes between 8 to 256 bytes and remote wake-up.
1KB of dedicated endpoint memory flexibly assigned to the different endpoints
Efficient transfers using the µDMA controller
UART

A UART is an integrated circuit used for RS-232C serial communications, containing a transmitter
(parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.
The CC2538 microcontroller includes two fully programmable 16C550-type UARTs. Although the
functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can
generate individually masked interrupts from the receive (RX), transmit (TX), modem flow control, and
error conditions. The module generates a single combined interrupt when any of the interrupts are
asserted and are unmasked.
The two UARTs have the following features:
• Programmable baud-rate generator allowing speeds up to 2 Mbps for regular speed (divide by 16) and
4 Mbps for high speed (divide by 8)
• Separate 16x8 TX and RX FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered
interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
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Line-break generation and detection
Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation and detection
– 1 or 2 stop-bit generation
Full modem handshake support (on UART1)
Modem flow control (on UART1)
LIN protocol support
EIA-485 9-bit support
Standard FIFO-level and end-of-transmission (EoT) interrupts
Efficient transfers using the µDMA controller:
– Separate channels for TX and RX
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
I2C

The I2C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a
serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and
ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system
testing and diagnostic purposes in product development and manufacturing.
Each device on the I2C bus can be designated as a master or a slave. Each I2C module supports both
sending and receiving data as either a master or a slave and can operate simultaneously as both a master
and a slave. Both the I2C master and slave can generate interrupts.
The CC2538 microcontroller includes an I2C module with the following features:
•

•

•
•
•
•

Devices on the I2C bus can be designated as either a master or a slave:
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
Four I2C modes:
– Master transmit
– Master receive
– Slave transmit
– Slave receive
Two transmission speeds: Standard (100 Kbps) and fast (400 Kbps)
Clock low time-out interrupt
Dual slave address capability
Master and slave interrupt generation:
– Master generates interrupts when a TX or RX operation completes (or aborts due to an error).
– Slave generates interrupts when data is transferred or requested by a master or when a START or
STOP condition is detected.
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

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1.3.8.4

SSI

An SSI module is a 4-wire bidirectional communications interface that converts data between parallel and
serial. The SSI performs serial-to-parallel conversion on data received from a peripheral device, and
parallel-to-serial conversion on data transmitted to a peripheral device. The SSI can be configured as
either a master or slave device. As a slave device, the SSI can also be configured to disable its output,
which allows coupling of a master device with multiple slave devices. The TX and RX paths are buffered
with separate internal FIFOs.
The SSI also includes a programmable bit rate clock divider and prescaler to generate the output serial
clock derived from the input clock of the SSI. Bit rates are generated based on the input clock, and the
maximum bit rate is determined by the connected peripheral.
The CC2538 includes two SSI modules with the following features:
•
•
•
•
•
•
•
•

Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces
Master or slave operation
Programmable clock bit rate and prescaler
Separate TX and RX FIFOs, each 16 bits wide and 8 locations deep
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic and debug testing
Standard FIFO-based interrupts and EoT interrupt
Efficient transfers using the µDMA controller:
– Separate channels for TX and RX
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains four entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted when
FIFO contains four entries

1.3.9 Programmable GPIOs
GPIO pins offer flexibility for a variety of connections. The CC2538 GPIO module is comprised of four
GPIO blocks, each corresponding to an individual GPIO port. The GPIO module supports CC2538
programmable I/O pins. The number of GPIOs available depends on the peripherals being used (see
Chapter 5 for the signals available to each GPIO pin).
•
•
•
•

•
•
•
•
•

Up to 32 GPIOs, depending on configuration
4 pins with 20-mA drive strength, 28 pins with 4-mA drive strength
Fully flexible digital pin muxing allows use as GPIO or any of several peripheral functions
Programmable control for GPIO interrupts:
– Interrupt generation masking per pin
– Edge-triggered on rising or falling
Bit masking in read and write operations through address lines
Can be used to initiate a μDMA transfer
Pin state can be retained during all sleep modes
Pins configured as digital inputs are Schmitt-triggered
Programmable control for GPIO pad configuration:
– Weak pull up or pull down resistors
– Digital input enables

1.3.10 Analog
The CC2538 microcontroller provides analog functions integrated into the device, including:
• A 12-bit ADC with eight analog input channels
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Low-power analog comparator
On-chip voltage regulator

The following provides more detail on these analog functions.
1.3.10.1 ADC
An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number. The ADC
module features 12-bit conversion resolution and supports eight input channels plus an internal division of
the battery voltage and a temperature sensor.
•
•
•
•
•
•
•

Eight shared analog input channels
12-bit precision ADC with up to 11.5 ENOB
Single-ended and differential-input configurations
On-chip internal temperature sensor
Periodic sampling or conversion over a sequence of channels
Converter uses an internal regulated reference, AVDD or an external reference
Efficient transfers using the µDMA controller
– Dedicated channel for each sample sequencer

1.3.10.2 Analog Comparator
An analog comparator is a peripheral that compares two analog voltages, two external pin inputs, and
provides a logical output that signals the comparison result. The CC2538 microcontroller provides an
independent integrated and low-power analog comparator that can be active in all power modes. The
comparator output is mapped into the digital I/O port, and the MCU can treat the comparator output as a
regular digital input.
1.3.10.3 Random Number Generator
The random number generator (RNG) uses a 16-bit LFSR to generate pseudorandom numbers, which can
be read by the CPU or used directly by the command strobe processor. The RNG can be seeded with
random data from noise in the radio ADC.

1.3.11 cJTAG, JTAG and SWO
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for
controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be
used to test the interconnections of assembled printed circuit boards and obtain manufacturing information
on the components. The JTAG port also provides a means of accessing and controlling design-for-test
features such as I/O pin observation and control, scan testing, and debugging. The compact JTAG
(cJTAG) interface has the following features:
• IEEE 1149.1-1990-compatible TAP controller
• IEEE 1149.7 cJTAG interface
• ICEPick™ JTAG router
• Four-bit IR chain for storing JTAG instructions
• IEEE standard instructions: BYPASS, IDCODE, SAMPLE and PRELOAD, EXTEST and INTEST
• ARM additional instructions: APACC, DPACC, and ABORT

1.3.12 Packaging and Temperature
•
•

56-pin 8x8 mm QFN package
Extended operating temperature from –40°C to +125°C

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The Cortex-M3 Processor
This chapter describes the Cortex-M3 processor.
Topic

2.1
2.2
2.3
2.4
2.5

...........................................................................................................................
The Cortex-M3 Processor Introduction .................................................................
Block Diagram ..................................................................................................
Overview ..........................................................................................................
Programming Model ..........................................................................................
Instruction Set Summary ....................................................................................

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The Cortex-M3 Processor Introduction
The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system
requirements of minimal memory implementation, reduced pin count, and low power consumption, while
delivering outstanding computational performance and exceptional system response to interrupts.
Features include:
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•

32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
Outstanding processing performance combined with fast interrupt handling
Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of
a few kilobytes of memory for microcontroller-class applications:
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling data to be efficiently packed into memory
Fast code execution permits slower processor clock or increases sleep mode time.
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system and memories
Hardware division and fast digital-signal-processing orientated multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality
Enhanced system debug with extensive breakpoint and trace capabilities
Serial wire trace reduce the number of pins required for debugging and tracing.
Migration from the ARM7™ processor family for better performance and power efficiency
Optimized for single-cycle flash memory use
Ultra-low power consumption with integrated sleep modes
32-MHz operation
1.25 DMIPS/MHz

The CC2538 builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded
microcontroller applications, such as factory automation and control, industrial control power devices,
building and home automation, and stepper motor control.
This chapter provides information on the CC2538 implementation of the Cortex-M3 processor, including
the programming model, the memory model, the exception model, fault handling, and power management.
For technical details on the instruction set, see the Cortex™-M3 Instruction Set Technical User's Manual.

2.2

Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional
power efficiency through an efficient instruction set and extensively optimized design, which provides highend processing hardware. The instruction set includes a range of single-cycle and SIMD multiplication and
multiply-with-accumulate capabilities, saturating arithmetic, and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and system
debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set based
on Thumb-2 technology, thus ensuring high code density and reduced program memory requirements.
The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit
architecture, with the high code density of 8-bit and 16-bit microcontrollers.

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The Cortex-M3 processor closely integrates a nested vector interrupt controller (NVIC) to deliver industryleading interrupt performance. The CC2538 NVIC includes a nonmaskable interrupt (NMI) and provides
eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution
of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of
registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt
latency. Interrupt handlers do not require any assembler stubs, thus removing code overhead from the
ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to
another. To optimize low-power designs, the NVIC integrates with the sleep modes, including deep-sleep
mode, which enables the entire device to be rapidly powered down.

Interrupts
NVIC

ARM
Cortex-M3

CM3 core

Sleep
Debug

Instructions

Data
Trace
port
interface
unit

MPU

Flash
patch and
breakpoint

Data
watchpoint
and trace

Instrumentation
trace macrocell
ROM
table

Private peripheral
bus
(internal)

Adv. peripheral
bus
Bus
matrix

JTAG debug
port

Serial
wire
output
trace
port
(SWO)

Debug
access port

I-code bus
D-code bus
System bus

Figure 2-1. CPU Block Diagram

2.3

Overview

2.3.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA™ technology to provide high-speed,
low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.
An MPU in the Cortex-M3 processor provides fine-grain memory control, enabling applications to
implement security privilege levels and separate code, data and stack on a task-by-task basis.

2.3.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility
of the processor and memory through a traditional JTAG® port.

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For system trace, the processor integrates an instrumentation trace macrocell (ITM) alongside data watch
points and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a serial
wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through a single pin.
The flash patch and breakpoint unit (FPB) provides up to eight hardware breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the
program code in the CODE memory region. Remap functions enable patching of applications stored in a
read-only area of flash memory into another area of on-chip SRAM or flash memory. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed,
the accesses are redirected to a remap table specified in the FPB configuration.
For more information on the Cortex-M3 debug capabilities, see the ARM® Debug Interface V5
Architecture Specification.

2.3.3 Trace Port Interface Unit
The trace port interface unit (TPIU) acts as a bridge between the Cortex-M3 trace data from the ITM, and
an off-chip trace port analyzer (see Figure 2-2).

Debug
ATB
slave
port

ATB
interface

APB
slave
port

APB
interface

Asynchronous FIFO

Trace out
(serializer)

Serial wire
trace port
(SWO)

Figure 2-2. TPIU Block Diagram

2.3.4 Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
• SysTick: A 24-bit count-down timer that can be used as a real-time operating system (RTOS) tick timer
or as a simple counter (see Section 3.2.1)
• NVIC: An embedded interrupt controller (INTC) that supports low-latency interrupt processing (see
Section 3.2.2)
• System control block (SCB): The programming model interface to the processor. The SCB provides
system implementation information and system control, including configuration, control, and reporting
of system exceptions (see Section 3.2.3).
• MPU: Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
Section 3.2.4).

2.4

Programming Model
This section describes the Cortex-M3 programming model. In addition to the descriptions of the individual
core registers, information about the processor modes and privilege levels for software execution and
stacks is included.

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2.4.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 has two modes of operation:
• Thread mode: Used to execute application software. The processor enters thread mode when it comes
out of reset.
• Handler mode: Used to handle exceptions. When the processor completes exception processing, it
returns to thread mode.
In addition, the Cortex-M3 has two privilege levels, unprivileged and privileged.
• In unprivileged mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
• In privileged mode, software can use all the instructions and has access to all resources.
In thread mode, the CONTROL register (see Control Register (CONTROL)) controls whether software
execution is privileged or unprivileged. In handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to
transfer control to privileged software.

2.4.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item
on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer
and then writes the item to the new memory location. The processor implements two stacks: the main
stack and the process stack, with a pointer for each held in independent registers (see the SP register on
Stack Pointer (SP), Stack Pointer (SP)).
In thread mode, the CONTROL register (see Control Register (CONTROL)) controls whether the
processor uses the main stack or the process stack. In handler mode, the processor always uses the main
stack. Table 2-1 lists the options for processor operations.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode

Use

Privilege Level

Thread

Applications

Privileged or unprivileged

Handler

Exception handlers

Always privileged

(1)

Stack Used
(1)

Main stack or process stack
Main stack

See CONTROL (Control Register (CONTROL)).

2.4.3 Register Map
Figure 2-3 shows the Cortex-M3 register set. Table 2-2 lists the core registers. The core registers are not
memory mapped and are accessed by register name, so the base address is N/A (not applicable) and
there is no offset.

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R0
R1
R2
R3

Low registers

R4
R5
R6

General-purpose registers

R7
R8
R9
High registers

R10
R11
R12

Stack pointer

SP (R13)

Link register

LR (R14)

Program counter

PC (R15)

PSP

PSR

MSP

See Note.

Program status register

PRIMASK
FAULTMASK

Exception mask registers

Special registers

BASEPRI
CONTROL

Control register

NOTE:: Banked version of SP

Figure 2-3. Cortex-M3 Register Set
Table 2-2. Processor Register Map
Offset

Name

Type

Reset

Description

Link

–

R/W

–

Cortex general-purpose register 0

See Cortex GeneralPurpose Register 0 (R0) .

–

R/W

–

Cortex general-purpose register 1

See Cortex GeneralPurpose Register 1 (R1).

–

R/W

–

Cortex general-purpose register 2

See Cortex GeneralPurpose Register 2 (R2).

–

R/W

–

Cortex general-purpose register 3

See Cortex GeneralPurpose Register 3 (R3).

–

R/W

–

Cortex general-purpose register 4

See Cortex GeneralPurpose Register 4 (R4).

–

R/W

–

Cortex general-purpose register 5

See Cortex GeneralPurpose Register 5 (R5).

–

R/W

–

Cortex general-purpose register 6

See Cortex GeneralPurpose Register 6 (R6).

–

R/W

–

Cortex general-purpose register 7

See Cortex GeneralPurpose Register 7 (R7).

–

R/W

–

Cortex general-purpose register 8

See Cortex GeneralPurpose Register 8 (R8).

–

R/W

–

Cortex general-purpose register 9

See Cortex GeneralPurpose Register 9 (R9).

–

R10

R/W

–

Cortex general-purpose register 10

See Cortex GeneralPurpose Register 10 (R10)
.

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Table 2-2. Processor Register Map (continued)
Offset

Name

Type

Reset

Description

Link

–

R11

R/W

–

Cortex general-purpose register 11

See Cortex GeneralPurpose Register 11 (R11)
.

–

R12

R/W

–

Cortex general-purpose register 12

See Cortex GeneralPurpose Register 12 (R12).

–

R/W

–

Stack pointer

See Stack Pointer (SP).

–

R/W

0xFFFF FFFF

Link register

See Link Register (LR).

–

R/W

–

Program counter

See Program Counter (PC).

–

PSR

R/W

0x0100 0000

Program status register

See Program Status
Register (PSR).

–

PRIMASK

R/W

0x0000 0000

Priority mask register

See Priority Mask Register
(PRIMASK).

–

FAULTMASK

R/W

0x0000 0000

Fault mask register

See Fault Mask Register
(FAULTMASK).

–

BASEPRI

R/W

0x0000 0000

Base priority mask register

See Base Priority Mask
Register (BASEPRI).

–

CONTROL

R/W

0x0000 0000

Control register

See Control Register
(CONTROL).

2.4.4 Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3. The core
registers are not memory mapped and are accessed by register name rather than offset.
NOTE:

The register type shown in the register descriptions refers to type during program
execution in thread mode and handler mode. Debug access can differ.
Cortex General-Purpose Register 0 (R0)

Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 1 (R1)
Address Offset

Reset

Physical Address

–

Instance

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 2 (R2)
Address Offset

Reset

Physical Address

–

Instance

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 3 (R3)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 4 (R4)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

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Cortex General-Purpose Register 5 (R5)
Address Offset

Reset

Physical Address

–

Instance

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 6 (R6)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 7 (R7)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 8 (R8)
Address Offset

Reset

Physical Address

–

Instance

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA

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Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 9 (R9)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 10 (R10)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 11 (R11)
Address Offset

Reset

Physical Address

–

Instance

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Cortex General-Purpose Register 12 (R12)
Address Offset

Reset

Physical Address

Instance

–

Description

The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

Type

R/W

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

DATA
Bits

Field Name

Description

Type

Reset

31:0

DATA

—

Stack Pointer (SP)
Address Offset

Reset

Physical Address

Instance

–

Description
The Stack Pointer (SP) is register R13. In thread mode, the function of this register changes depending on the ASP bit in the Control
Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this
register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address
0x0000 0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

SP
Bits

Field Name

Description

31:0

This field is the address of the stack pointer.

Type

Reset

—

Link Register (LR)
Address Offset

Reset

Physical Address

Instance

0xFFFF FFFF

Description
The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be
accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 5-3 for the values and description.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

LINK
Bits

Field Name

Description

31:0

LINK

This field is the return address.

Type

Reset

0xFFFF FFFF

Program Counter (PC)
Address Offset

Reset

Physical Address

Instance

–

Description
The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the
value of the reset vector, which is at address 0x0000 0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR register at
reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

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Bits

Field Name

Description

31:0

This field is the current program address.

Type

Reset

—

Table 2-3. PSR Register Combinations
Register

Type

PSR

R/W

IEPSR

EPSR and IPSR

IAPSR

R/W

APSR and IPSR

EAPSR

R/W

APSR and EPSR

(1)

Combination

(1) (2)

APSR, EPSR, and IPSR

The processor ignores writes to the IPSR bits.
Reads of the EPSR bits return 0, and the processor ignores writes to these bits.

(2)

Program Status Register (PSR)
Address Offset

Reset

Physical Address

Instance

0x0100 0000

Description
Note: This register is also referred to as xPSR.
The
•
•
•

Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions:
Application Program Status Register (APSR), bits 31:27
Execution Program Status Register (EPSR), bits 26:24, 15:10
Interrupt Program Status Register (IPSR), bits 6:0

The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be accessed in privileged or
unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction
(ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using
the MSR instruction always return 0. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see Section 5.1.7).
IPSR contains the exception type number of the current ISR.
These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument
to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be
written to using APSR with the MSR instruction. Program Status Register (PSR) shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual for more information about how to
access the program status registers.
R/W

Bits
31

ICI / IT

THUMB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

Type

ICI / IT

Description

Type

Reset

APSR Negative or Less Flag

R/W

Description

The previous operation result was negative or less than.

The previous operation result was positive, zero, greater
than, or equal

ISRNUM

Field Name

Value

The value of this bit is meaningful only when accessing PSR or
APSR.
30

APSR Zero Flag
Value

Description

The previous operation result was zero.

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Bits

Field Name

Description
0

Type

Reset

R/W

The previous operation result was nonzero.

The value of this bit is meaningful only when accessing PSR or
APSR.
29

APSR Carry or Borrow Flag
Value

Description

The previous add operation resulted in a carry bit or the
previous subtract operation did not result in a borrow bit.

The previous add operation did not result in a carry bit or
the previous subtract operation resulted in a borrow bit.

The value of this bit is meaningful only when accessing PSR or
APSR.
28

APSR Overflow Flag
Value

Description

The previous operation resulted in an overflow.

The previous operation did not result in an overflow.

The value of this bit is meaningful only when accessing PSR or
APSR.
27

APSR DSP Overflow and Saturation Flag
Value

Description

DSP overflow or saturation has occurred.

DSP overflow or saturation has not occurred since reset
or since the bit was last cleared.

The value of this bit is meaningful only when accessing PSR or
APSR.
This bit is cleared by software using an MRS instruction.
26:25

ICI / IT

EPSR ICI / IT status
These bits, along with bits 15:10, contain the ICI field for an
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When EPSR holds the ICI
execution state, bits 26:25 are 0. The If-Then block contains up to
four instructions following an IT instruction. Each instruction in the
block is conditional. The conditions for the instructions are either all
the same, or some can be the inverse of others. See the Cortex™M3 Instruction Set Technical User's Manual for more information.
The value of this field is meaningful only when accessing PSR or
EPSR.

0x0

THUMB

EPSR Thumb state
This bit indicates the Thumb state and should always be set. The
following can clear the THUMB bit:

0x00

• The BLX, BX and POP{PC} instructions
• Restoration from the stacked xPSR value on an exception return
• Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a
fault or lockup. For more information, see Section 5.2.4. The value
of this bit is meaningful only when accessing PSR or EPSR.
23:16

RESERVED

Reserved

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Field Name

Description

ICI / IT

9:7

6:0

15:10

Type

Reset

EPSR ICI / IT status
These bits, along with bits 26:25, contain the InterruptibleContinuable Instruction (ICI) field for an interrupted load multiple or
store multiple instruction or the execution state bits of the IT
instruction. When an interrupt occurs during the execution of an
LDM, STM, PUSH, or POP instruction, the processor stops the load
multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits
15:12. After servicing the interrupt, the processor returns to the
register pointed to by bits 15:12 and resumes execution of the
multiple load or store instruction. When EPSR holds the ICI
execution state, bits 11:10 are 0. The If-Then block contains up to
four instructions following a 16-bit IT instruction. Each instruction in
the block is conditional. The conditions for the instructions are
either all the same, or some can be the inverse of others. See the
Cortex™-M3 Instruction Set Technical User's Manual for more
information. The value of this field is meaningful only when
accessing PSR or EPSR.

0x0

RESERVED

Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.

0x0

ISRNUM

IPSR ISR Number
This field contains the exception type number of the current ISR.

0x00

Value

Description

0x00

Thread mode

0x01

Reserved

0x02

NMI

0x03

Hard fault

0x04

Memory management fault

0x05

Bus fault

0x06

Usage fault

0x070x0A

Reserved

0x0B

SVCall

0x0C

Reserved for debug

0x0D

Reserved

0x0E

PendSV

0x0F

SysTick

0x10

Interrupt vector 0

0x11

Interrupt vector 1

...

0x46

Interrupt vector 54

0x470x7F

Reserved

For more information, see Section 5.1.2.
The value of this field is meaningful only when accessing PSR or
IPSR.

Priority Mask Register (PRIMASK)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The Priority Mask (PRIMASK) register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI),
and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks.
This register is accessible only in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS
instruction may be used to change the value of the PRIMASK register. For more information on these instructions, see the Cortex™-M3
Instruction Set Technical User's Manual. For more information on exception priority levels, see Section 5.1.2.
Type

R/W

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9

RESERVED

Bits

Field Name

Description

Type

Reset

31:1

RESERVED

Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.

0x0000 000

PRIMASK

Priority Mask

R/W

0
PRIMASK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Value

Description

Prevents the activation of all exceptions with configurable
priority.

No effect.

Fault Mask Register (FAULTMASK)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The Fault Mask FAULTMASK register prevents activation of all exceptions except for the NMI. Exceptions should be disabled when they
might impact the timing of critical tasks. This register is accessible only in privileged mode. The MSR and MRS instructions are used to
access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the
Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority
levels, see Section 5.1.2.
R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

Bits

Field Name

Description

31:1

RESERVED

FAULTMASK

Type

Reset

Reserved

0x0000 000

Fault Mask

R/W

Value

Description

Prevents the activation of all exceptions except for NMI.

No effect.

0
FAULTMASK

Type

The processor clears the FAULTMASK bit on exit from any
exception handler except the NMI handler.

Base Priority Mask Register (BASEPRI)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The Base Priority Mask BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value,
it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when
they might impact the timing of critical tasks. This register is accessible only in privileged mode. For more information on exception priority
levels, see Section 5.1.2.
Type

R/W

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

BASEPRI

Bits

Field Name

Description

Type

Reset

31:8

RESERVED

Reserved

0x0000 00

7:5

BASEPRI

Base Priority
Any exception that has a programmable priority level with the same
or lower priority as the value of this field is masked. The PRIMASK
register can be used to mask all exceptions with programmable
priority levels. Higher priority exceptions have lower priority levels.

R/W

0x0

4:0

RESERVED

Value

Description

0x0

All exceptions are unmasked.

0x1

All exceptions with priority levels 1–7 are masked.

0x2

All exceptions with priority levels 2–7 are masked.

0x3

All exceptions with priority levels 3–7 are masked.

0x4

All exceptions with priority levels 4–7 are masked.

0x5

All exceptions with priority levels 5–7 are masked.

0x6

All exceptions with priority levels 6 and 7 are masked.

0x7

All exceptions with priority level 7 are masked.

Reserved

RESERVED

Control Register (CONTROL)
Address Offset

Reset

Physical Address

Instance

0x0000 0000

Description
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode. This
register is accessible only in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in handler mode.
The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 53). In an OS environment, threads running in thread mode should use the process stack and the kernel and exception handlers should use
the main stack. By default, thread mode uses MSP. To switch the stack pointer used in thread mode to PSP, either use the MSR instruction
to set the ASP bit, as detailed in the Cortex™-M3 Instruction Set Technical User's Manual, or perform an exception return to thread mode
with the appropriate EXC_RETURN value, as shown in Table 5-3.
Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that
instructions after the ISB instruction executes use the new stack pointer. See the Cortex™-M3 Instruction Set Technical User's Manual.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

Bits

Field Name

Description

31:2

RESERVED

Reserved

ASP

Active Stack Pointer

Value

Description

PSP is the current stack pointer.

MSP is the current stack pointer

0
TMPL

R/W

ASP

Type

Reset

0x0000 000

R/W

In handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
0

TMPL

Thread Mode Privilege Level
Value

Description

Unprivileged software can be executed in thread mode.

Only privileged software can be executed in thread mode.

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2.4.5 Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the NVIC
prioritize and handle all exceptions. An exception changes the normal flow of software control. The
processor uses handler mode to handle all exceptions except for reset. For more information, see
Section 5.1.7.
The NVIC registers control interrupt handling. For more information, see Section 3.2.2.

2.4.6 Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64bit data transfer instructions. All instruction and data memory accesses are little endian. For more
information, see Section 4.1.1.

2.5

Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-4 lists the supported
instructions.
NOTE:

In Table 2-4:
• Angle brackets, <>, enclose alternative forms of the operand.
• Braces, {}, enclose optional operands.
• The Operands column is not exhaustive.
• Op2 is a flexible second operand that can be either a register or a constant.
• Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction
descriptions in the Cortex™-M3 Instruction Set Technical User's Manual.

NOTE: This summary table is copied from the the Cortex™-M3 Instruction Set Technical User's
Manual. Changes made in the manual must be made in Table 2-4.

Table 2-4. Cortex-M3 Instruction Summary
Mnemonic

Operands

Brief Description

Flags

ADC, ADCS

{Rd,} Rn, Op2

Add with carry

N, Z, C, V

ADD, ADDS

{Rd,} Rn, Op2

Add

N, Z, C, V

ADD, ADDW

{Rd,} Rn , #imm12

Add

N, Z, C, V

ADR

Rd, label

Load PC-relative address

–

AND, ANDS

{Rd,} Rn, Op2

Logical AND

N, Z, C

ASR, ASRS

Rd, Rm,

Arithmetic shift right

N, Z, C

label

Branch

–

BFC

Rd, #lsb, #width

Bit field clear

–

BFI

Rd, Rn, #lsb, #width

Bit field insert

–

BIC, BICS

{Rd,} Rn, Op2

Bit clear

N, Z, C

BKPT

#imm

Breakpoint

–

label

Branch with link

–

BLX

Branch indirect with link

–

Branch indirect

–

CBNZ

Rn, label

Compare and branch if
nonzero

–

CBZ

Rn, label

Compare and branch if zero

–

CLREX

–

Clear exclusive

–

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Table 2-4. Cortex-M3 Instruction Summary (continued)
Mnemonic

Operands

Brief Description

Flags

CLZ

Rd, Rm

Count leading zeros

–

CMN

Rn, Op2

Compare negative

N, Z, C, V

CMP

Rn, Op2

Compare

N, Z, C, V

CPSID

Change processor state,
disable interrupts

–

CPSIE

Change processor state,
enable interrupts

–

DMB

–

Data memory barrier

–

DSB

–

Data synchronization barrier

–

EOR, EORS

{Rd,} Rn, Op2

Exclusive OR

N, Z, C

ISB

–

Instruction synchronization
barrier

–

If‑Then condition block

–

LDM

Rn{!}, reglist

Load multiple registers,
increment after

–

LDMDB, LDMEA

Rn{!}, reglist

Load multiple registers,
decrement before

–

LDMFD, LDMIA

Rn{!}, reglist

Load multiple registers,
increment after

–

LDR

Rt, [Rn, #offset]

Load register with word

–

LDRB, LDRBT

Rt, [Rn, #offset]

Load register with byte

–

LDRD

Rt, Rt2, [Rn, #offset]

Load register with 2 bytes

–

LDREX

Rt, [Rn, #offset]

Load register exclusive

–

LDREXB

Rt, [Rn]

Load register exclusive with
byte

–

LDREXH

Rt, [Rn]

Load register exclusive with
halfword

–

LDRH, LDRHT

Rt, [Rn, #offset]

Load register with halfword

–

LDRSB, LDRSBT

Rt, [Rn, #offset]

Load register with signed byte

–

LDRSH, LDRSHT

Rt, [Rn, #offset]

Load register with signed
halfword

–

LDRT

Rt, [Rn, #offset]

Load register with word

–

LSL, LSLS

Rd, Rm,

Logical shift left

N, Z, C

LSR, LSRS

Rd, Rm,

Logical shift right

N, Z, C

MLA

Rd, Rn, Rm, Ra

Multiply with accumulate, 32-bit
–
result

MLS

Rd, Rn, Rm, Ra

Multiply and subtract, 32-bit
result

–

MOV, MOVS

Rd, Op2

Move

N, Z, C

MOV, MOVW

Rd, #imm16

Move 16-bit constant

N, Z, C

MOVT

Rd, #imm16

Move top

–

MRS

Rd, spec_reg

Move from special register to
general register

–

MSR

spec_reg, Rm

Move from general register to
special register

N, Z, C, V

MUL, MULS

{Rd,} Rn, Rm

Multiply, 32-bit result

N, Z

MVN, MVNS

Rd, Op2

Move NOT

N, Z, C

NOP

–

No operation

–

ORN, ORNS

{Rd,} Rn, Op2

Logical OR NOT

N, Z, C

ORR, ORRS

{Rd,} Rn, Op2

Logical OR

N, Z, C

POP

reglist

Pop registers from stack

–

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Table 2-4. Cortex-M3 Instruction Summary (continued)
Mnemonic

Operands

Brief Description

Flags

PUSH

reglist

Push registers onto stack

–

RBIT

Rd, Rn

Reverse bits

–

REV

Rd, Rn

Reverse byte order in a word

–

REV16

Rd, Rn

Reverse byte order in each
halfword

–

REVSH

Rd, Rn

Reverse byte order in bottom
halfword and sign extend

–

ROR, RORS

Rd, Rm,

Rotate right

N, Z, C

RRX, RRXS

Rd, Rm

Rotate right with extend

N, Z, C

RSB, RSBS

{Rd,} Rn, Op2

Reverse subtract

N, Z, C, V

SBC, SBCS

{Rd,} Rn, Op2

Subtract with carry

N, Z, C, V

SBFX

Rd, Rn, #lsb, #width

Signed bit field extract

–

SDIV

{Rd,} Rn, Rm

Signed divide

–

SEV

–

Send event

–

SMLAL

RdLo, RdHi, Rn, Rm

Signed multiply with
accumulate (32 × 32 + 64), 64bit result

–

SMULL

RdLo, RdHi, Rn, Rm

Signed multiply (32 × 32), 64bit result

–

SSAT

Rd, #n, Rm {,shift #s}

Signed saturate

STM

Rn{!}, reglist

Store multiple registers,
increment after

–

STMDB, STMEA

Rn{!}, reglist

Store multiple registers,
decrement before

–

STMFD, STMIA

Rn{!}, reglist

Store multiple registers,
increment after

–

STR

Rt, [Rn {, #offset}]

Store register word

–

STRB, STRBT

Rt, [Rn {, #offset}]

Store register byte

–

STRD

Rt, Rt2, [Rn {, #offset}]

Store register two words

–

STREX

Rt, Rt, [Rn {, #offset}]

Store register exclusive

–

STREXB

Rd, Rt, [Rn]

Store register exclusive byte

–

STREXH

Rd, Rt, [Rn]

Store register exclusive
halfword

–

STRH, STRHT

Rt, [Rn {, #offset}]

Store register halfword

–

STRSB, STRSBT

Rt, [Rn {, #offset}]

Store register signed byte

–

STRSH, STRSHT

Rt, [Rn {, #offset}]

Store register signed halfword

–

STRT

Rt, [Rn {, #offset}]

Store register word

–

SUB, SUBS

{Rd,} Rn, Op2

Subtract

N, Z, C, V

SUB, SUBW

{Rd,} Rn, #imm12

Subtract 12-bit constant

N, Z, C, V

SVC

#imm

Supervisor call

–

SXTB

{Rd,} Rm {,ROR #n}

Sign extend a byte

–

SXTH

{Rd,} Rm {,ROR #n}

Sign extend a halfword

–

TBB

[Rn, Rm]

Table branch byte

–

TBH

[Rn, Rm, LSL #1]

Table branch halfword

–

TEQ

Rn, Op2

Test equivalence

N, Z, C

TST

Rn, Op2

Test

N, Z, C

UBFX

Rd, Rn, #lsb, #width

Unsigned bit field extract

–

UDIV

{Rd,} Rn, Rm

Unsigned divide

–

RdLo, RdHi, Rn, Rm

Unsigned multiply with
accumulate (32 × 32 + 32 +
32), 64-bit result

–

UMLAL

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Table 2-4. Cortex-M3 Instruction Summary (continued)
Mnemonic

Operands

Brief Description

Flags

UMULL

RdLo, RdHi, Rn, Rm

Unsigned multiply (32 × 2), 64bit result

–

USAT

Rd, #n, Rm {,shift #s}

Unsigned saturate

UXTB

{Rd,} Rm, {,ROR #n}

Zero extend a byte

–

UXTH

{Rd,} Rm, {,ROR #n}

Zero extend a halfword

–

USAT

Rd, #n, Rm {,shift #s}

Unsigned saturate

UXTB

{Rd,} Rm {,ROR #n}

Zero extend a byte

–

UXTH

{Rd,} Rm {,ROR #n}

Zero extend a halfword

–

WFE

–

Wait for event

–

WFI

–

Wait for interrupt

–

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Cortex™-M3 Peripherals
This chapter describes the Cortex™-M3 peripherals.
Topic

3.1
3.2
3.3
3.4
3.5

...........................................................................................................................
Cortex™-M3 Peripherals Introduction ..................................................................
Functional Description .......................................................................................
Register Map ....................................................................................................
SysTick Register Descriptions ............................................................................
NVIC Register Descriptions ................................................................................

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Cortex™-M3 Peripherals Introduction
This chapter provides information on the CC2538 implementation of the Cortex-M3 processor peripherals,
including:
• System timer (SysTick) (see SysTick): Provides a simple, 24-bit clear-on-write, decrementing, wrap-onzero counter with a flexible control mechanism.
• Nested vectored interrupt controller (NVIC) (see NVIC):
– Facilitates low-latency exception and interrupt handling
– Works with system controller (see Chapter 7) to control power management
– Implements system control registers
• M3 system control block (SCB) (see SCB): Provides system implementation information and system
control, including configuration, control, and reporting of system exceptions.
• Memory protection unit (MPU) (see MPU): Supports the standard ARMv7 protected memory system
architecture (PMSA) model. The MPU provides full support for protection regions, overlapping
protection regions, access permissions, and exporting memory attributes to the system.
Table 3-1 lists the address map of the private peripheral bus (PPB). Some peripheral register regions are
split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions

3.2

ADDRESS

CORE PERIPHERAL

LINK

0xE000 E010 – 0xE000 E01F

System Timer (SysTick)

SysTick

0xE000 E100 – 0xE000 E4EF
0xE000 EF00 – 0xE000 EF03

Nested Vectored Interrupt Controller
(NVIC)

NVIC

0xE000 E008 – 0xE000 E00F
0xE000 ED00 – 0xE000 ED3F

System Control Block (SCB)

SCB

0xE000 ED90 – 0xE000 EDB8

Memory Protection Unit (MPU)

MPU

Functional Description
This chapter provides information on the CC2538 implementation of the Cortex-M3 processor peripherals:
• SysTick
• NVIC
• SCB
• MPU

3.2.1 SysTick
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write,
decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways. For example, the counter can be:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
• A high-speed alarm timer using the system clock.
• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter.
• A simple counter used to measure time to completion and time used.
• An internal clock source control based on missing and/or meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
• SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the
counter, enable the SysTick interrupt, and determine counter status
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•
•

SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the wrap
value of the counter
SysTick Current Value (STCURRENT): The current value of the counter

When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) to the
value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing
the STRELOAD register disables the counter on the next wrap. When the counter reaches 0, the COUNT
status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not
trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the
register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the
SysTick counter stops. Ensure that software uses aligned word accesses to access the SysTick registers.
NOTE:

When the processor is halted for debugging, the counter does not decrement.

3.2.2 NVIC
This section describes the NVIC and the registers it uses. The NVIC supports:
•
•
•
•
•
•
•
•
•

48 interrupts in alternate interrupt mapping mode.
147 interrupt in regular interrupt mapping mode.
A programmable priority level of 0 to 7 for each interrupt. A higher level corresponds to a lower priority,
so level 0 is the highest interrupt priority.
Low-latency exception and interrupt handling
Level and pulse detection of interrupt signals
Dynamic reprioritization of interrupts
Grouping of priority values into group priority and sub priority fields
Interrupt tail-chaining
An external nonmaskable interrupt (NMI)

The processor automatically stacks its state on exception entry and un-stacks this state on exception exit,
with no instruction overhead, providing low latency exception handling.
3.2.2.1

Level-Sensitive and Pulse Interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as
edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral de-asserts the interrupt signal. Typically this
happens because the interrupt service routine (ISR) accesses the peripheral, causing it to clear the
interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the
processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal
for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (for
more information, see Hardware and Software Control of Interrupts). For a level-sensitive interrupt, if the
signal is not de-asserted before the processor returns from the ISR, the interrupt becomes pending again,
and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal
asserted until it no longer needs servicing.
3.2.2.2

Hardware and Software Control of Interrupts

The Cortex-M3 processor latches all interrupts. A peripheral interrupt becomes pending for one of the
following reasons:
• The NVIC detects that the interrupt signal is asserted and the interrupt is not active.
• The NVIC detects a rising edge on the interrupt signal.
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Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a software-generated interrupt pending. See the INT bit in the
PEND0 register in Interrupt 0–31 Set Pending (PEND0), or SWTRIG in Software Trigger Interrupt
(SWTRIG).

A pending interrupt remains pending until one of the following:
• The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to
active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes
to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the
state of the interrupt changes to pending and active. In this case, when the processor returns from
the ISR the state of the interrupt changes to pending, which might cause the processor to
immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR,
when the processor returns from the ISR the state of the interrupt changes to inactive.
• Software writes to the corresponding interrupt clear-pending register bit:
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does
not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive if the state was pending, or to
active if the state was active and pending.

3.2.3 SCB
The SCB provides system implementation information and system control, including configuration, control,
and reporting of the system exceptions.

3.2.4 MPU
This section describes the MPU. The MPU divides the memory map into a number of regions and defines
the location, size, access permissions, and memory attributes of each region. The MPU supports
independent attribute settings for each region, overlapping regions, and export of memory attributes to the
system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines
eight separate memory regions, 0 to 7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any region
that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have
the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a
memory management fault, causing a fault exception and possibly causing termination of the process in
an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically
based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types (for more information, see Section 4.1.1).
Table 3-2 shows the possible MPU region attributes. For guidelines for programming a microcontroller
implementation, see MPU Configuration for a CC2538 Microcontroller.

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Table 3-2. Memory Attributes Summary
MEMORY TYPE

DESCRIPTION

Strongly ordered

All accesses to strongly ordered memory occur in program
order.

Device

Memory-mapped peripherals

Normal

Normal memory

To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the
interrupt handlers might access.
Ensure that software uses aligned accesses of the correct size to access MPU registers:
• Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be
accessed with aligned word accesses.
• The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to
prevent any previous region settings from affecting the new MPU setup.
3.2.4.1

Updating an MPU Region

To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region
Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be
programmed separately or with a multiple-word write to program all of these registers. The MPUBASEx
and MPUATTRx aliases can be used to program up to four regions simultaneously using an STM
instruction.
3.2.4.1.1 Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]

;
;
;
;
;

0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute

Disable a region before writing new region settings to the MPU if the region being changed was previously
enabled. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
BIC R2, R2, #1
STRH R2, [R0, #0x8]
STR R4, [R0, #0x4]
STRH R3, [R0, #0xA]
ORR R2, #1
STRH R2, [R0, #0x8]

;
;
;
;
;
;
;
;

0xE000ED98, MPU region number register
Region Number
Disable
Region Size and Enable
Region Base Address
Region Attribute
Enable
Region Size and Enable

Software must use memory barrier instructions:
• Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might
be affected by the change in MPU settings.
• After MPU setup, if it includes memory transfers that must use the new MPU settings.

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However, memory barrier instructions are not required if the MPU setup process starts by entering an
exception handler, or is followed by an exception return, because the exception entry and exception return
mechanisms cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU
through the PPB, which is a strongly ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required
after changing MPU settings, such as at the end of context switch. An ISB is required if the code that
programs the MPU region or regions is entered using a branch or call. If the programming sequence is
entered using a return from exception, or by taking an exception, then an ISB is not required.
3.2.4.1.2 Updating an MPU Region Using Multiple-Word Writes
The MPU can be programmed directly using multiple-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable

An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region number, address, attribute, size and enable

This operation can be done in two words for prepacked information, meaning that the MPU Region Base
Address (MPUBASE) register (see MPU Region Base Address (MPUBASE)) contains the required region
number and has the VALID bit set. This method can be used when the data is statically packed, for
example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable

3.2.4.1.3 Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in
the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see MPU Region Attribute
and Size (MPUATTR)) to disable a subregion. The least-significant bit (LSB) of the SRD field controls the
first subregion, and the most-significant bit (MSB) controls the last subregion. Disabling a subregion
means another region overlapping the disabled range matches instead. If no other enabled region
overlaps the disabled subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field
must be configured to 0x00, otherwise the MPU behavior is unpredictable.
3.2.4.1.3.1 Example of SRD Use
Two regions with the same base address overlap. Region 1 is 128KB, and region 2 is 512KB. To ensure
the attributes from region 1 apply to the first 128-KB region, configure the SRD field for region 2 to 0x03 to
disable the first two subregions, as Figure 3-1 shows.

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Region 2, with
subregions

Region 1

Base address of both regions

Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0

Figure 3-1. SRD Use Example

3.2.4.2

MPU Access Permission Attributes

The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 lists the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for
completeness; however, the current implementation of the Cortex-M3 does not support the concept of
cacheability or shareability. For information on programming the MPU for CC2538 implementations, see
MPU Configuration for a CC2538 Microcontroller.
Table 3-3. TEX, S, C, and B Bit Field Encoding
TEX

000b

MEMORY TYPE

SHAREABILITY

OTHER ATTRIBUTES

Strongly Ordered

Shareable

000

–

Device

Shareable

–

000

Normal

Not shareable

Outer and inner write-through.
No write allocate.

000

Normal

Shareable

000

Normal

Not shareable

000

Normal

Shareable

001

Normal

Not shareable

001

Normal

Shareable

001

Reserved encoding

–

001

Reserved encoding

–

001

Normal

Not shareable

Outer and inner write-back.
Write and read allocate.

001

Normal

Shareable

010

Device

Not shareable

Nonshared device

010

Reserved encoding

–

010

Reserved encoding

–

–
Cached memory (BB = outer
policy, AA = inner policy). See
Table 3-4 for the encoding of the
AA and BB bits.

(1)

1BB

Normal

Not shareable

1BB

Normal

Shareable

(1)

Outer and inner noncacheable

The MPU ignores the value of this bit.

Table 3-4 lists the cache policy for memory attribute encodings with a TEX value in the range of 0x4 to
0x7.

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Table 3-4. Cache Policy for Memory Attribute Encoding
ENCODING, AA or BB

CORRESPONDING CACHE POLICY

Noncacheable

Write back, write and read allocate

Write through, no write allocate

Write back, no write allocate

Table 3-5 lists the AP encodings in the MPUATTR register that define the access permissions for
privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
AP BIT FIELD

PRIVILEGED PERMISSIONS

UNPRIVILEGED
PERMISSIONS

DESCRIPTION

000

No access

All accesses generate a permission fault.

001

R/W

No access

Access from privileged software only

010

R/W

Writes by unprivileged software generate a
permission fault.

011

R/W

Full access

100

Unpredictable

Reserved

101

No access

Reads by privileged software only

110

Read-only, by privileged or unprivileged
software

111

Read-only, by privileged or unprivileged
software

3.2.4.2.1 MPU Configuration for a CC2538 Microcontroller
CC2538 microcontrollers have only a single processor and no caches. As a result, the MPU should be
programmed as shown in Table 3-6.
Table 3-6. Memory Region Attributes for a CC2538 Microcontroller
MEMORY REGION TEX

MEMORY TYPE AND ATTRIBUTES

Flash memory

b000

Normal memory, nonshareable, write-through

Internal SRAM

b000

Normal memory, shareable, write-through

External SRAM

b000

Normal memory, shareable, write-back, write-allocate

Peripherals

b000

Device memory, shareable

In current CC2538 microcontroller implementations, the shareability and cache policy attributes do not
affect the system behavior. However, using these settings for the MPU regions can make the application
code more portable. The values given in Table 3-6 are for typical situations.
3.2.4.3

MPU Mismatch

When an access violates the MPU permissions, the processor generates a memory management fault (for
more information, see Section 2.4.5). The MFAULTSTAT register indicates the cause of the fault. For
more information, see Configurable Fault Status (FAULTSTAT).

3.3

Register Map
Table 3-7 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU, and SCB registers. The offset listed is a
hexadecimal increment to the register address, relative to the core peripherals base address of 0xE000
E000 (ending address of 0xE000 EFFF).

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NOTE: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.

Table 3-7. Peripherals Register Map
OFFSET

NAME

TYPE

RESET

DESCRIPTION

LINK

SysTick Registers
0x010

STCTRL

R/W

0x0000 0004

SysTick Control and
Status Register

SysTick Control and Status Register
(STCTRL)

0x014

STRELOAD

R/W

0x0000 0000

SysTick Reload Value
Register

SysTick Reload Value Register
(STRELOAD)

0x018

STCURRENT

R/WC

0x0000 0000

SysTick Current Value
Register

SysTick Current Value Register
(STCURRENT)

NVIC Registers
0x100

EN0

R/W

0x0000 0000

Interrupt 0–31 Set
Enable

Interrupt 0–31 Set Enable (EN0)

0x104

EN1

R/W

0x0000 0000

Interrupt 32–63 Set
Enable

Interrupt 32–63 Set Enable (EN1)

0x108

EN2

R/W

0x0000 0000

Interrupt 64–95 Set
Enable

Interrupt 64–95 Set Enable (EN2)

0x10C

EN3

R/W

0x0000 0000

Interrupt 96–127 Set
Enable

Interrupt 96–127 Set Enable (EN3)

0x110

EN4

R/W

0x0000 0000

Interrupt 128–147 Set
Enable

Interrupt 128–147 Set Enable (EN4)

0x180

DIS0

R/W

0x0000 0000

Interrupt 0–31 Clear
Enable

Interrupt 0–31 Clear Enable (DIS0)

0x184

DIS1

R/W

0x0000 0000

Interrupt 32–63 Clear
Enable

Interrupt 32–63 Clear Enable (DIS1)

0x188

DIS2

R/W

0x0000 0000

Interrupt 64–95 Clear
Enable

Interrupt 64–95 Clear Enable (DIS2)

0x18C

DIS3

R/W

0x0000 0000

Interrupt 96–127 Clear
Enable

Interrupt 96–127 Clear Enable
(DIS3)

0x190

DIS4

R/W

0x0000 0000

Interrupt 128–147
Clear Enable

Interrupt 128–147 Clear Enable
(DIS4)

0x200

PEND0

R/W

0x0000 0000

Interrupt 0–31 Set
Pending

Interrupt 0–31 Set Pending (PEND0)

0x204

PEND1

R/W

0x0000 0000

Interrupt 32–63 Set
Pending

Interrupt 32–63 Set Pending
(PEND1)

0x208

PEND2

R/W

0x0000 0000

Interrupt 64–95 Set
Pending

Interrupt 64–95 Set Pending
(PEND2)

0x20C

PEND3

R/W

0x0000 0000

Interrupt 96–127 Set
Pending

Interrupt 96–127 Set Pending
(PEND3)

0x210

PEND4

R/W

0x0000 0000

Interrupt 128–147 Set
Pending

Interrupt 128–147 Set Pending
(PEND4)

0x280

UNPEND0

R/W

0x0000 0000

Interrupt 0–31 Clear
Pending

Interrupt 0–31 Clear Pending
(UNPEND0)

0x284

UNPEND1

R/W

0x0000 0000

Interrupt 32–63 Clear
Pending

Interrupt 32–63 Clear Pending
(UNPEND1)

0x288

UNPEND2

R/W

0x0000 0000

Interrupt 64–95 Clear
Pending

Interrupt 64–95 Clear Pending
(UNPEND2)

0x28C

UNPEND3

R/W

0x0000 0000

Interrupt 96–127 Clear
Pending

Interrupt 96–127 Clear Pending
(UNPEND3)

0x290

UNPEND4

R/W

0x0000 0000

Interrupt 128–147
Clear Pending

Interrupt 128–147 Clear Pending
(UNPEND4)

0x300

ACTIVE0

0x0000 0000

Interrupt 0–31 Active
Bit

Interrupt 0–31 Active Bit (ACTIVE0)

0x304

ACTIVE1

0x0000 0000

Interrupt 32–63 Active
Bit

Interrupt 32–63 Active Bit (ACTIVE1)

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Table 3-7. Peripherals Register Map (continued)

OFFSET

NAME

TYPE

RESET

DESCRIPTION

LINK

0x308

ACTIVE2

0x0000 0000

Interrupt 64–95 Active
Bit

Interrupt 64–95 Active Bit (ACTIVE2)

0x30C

ACTIVE3

0x0000 0000

Interrupt 96–127 Active Interrupt 96–127 Active Bit
Bit
(ACTIVE3)

0x310

ACTIVE4

0x0000 0000

Interrupt 128–147
Active Bit

Interrupt 128–147 Active Bit
(ACTIVE4)

0x400

PRI0

R/W

0x0000 0000

Interrupt 0–3 Priority

Interrupt 0–3 Priority (PRI0)

0x404

PRI1

R/W

0x0000 0000

Interrupt 4–7 Priority

Interrupt 4–7 Priority (PRI1)

0x408

PRI2

R/W

0x0000 0000

Interrupt 8–11 Priority

Interrupt 8–11 Priority (PRI2)

0x40C

PRI3

R/W

0x0000 0000

Interrupt 12–15 Priority

Interrupt 12–15 Priority (PRI3)

0x410

PRI4

R/W

0x0000 0000

Interrupt 16–19 Priority

Interrupt 16–19 Priority (PRI4)

0x414

PRI5

R/W

0x0000 0000

Interrupt 20–23 Priority

Interrupt 20–23 Priority (PRI5)

0x418

PRI6

R/W

0x0000 0000

Interrupt 24–27 Priority

Interrupt 24–27 Priority (PRI6)

0x41C

PRI7

R/W

0x0000 0000

Interrupt 28–31 Priority

Interrupt 28–31 Priority (PRI7)

0x420

PRI8

R/W

0x0000 0000

Interrupt 32–35 Priority

Interrupt 32–35 Priority (PRI8)

0x424

PRI9

R/W

0x0000 0000

Interrupt 36–39 Priority

Interrupt 36–39 Priority (PRI9)

0x428

PRI10

R/W

0x0000 0000

Interrupt 40–43 Priority

Interrupt 40–43 Priority (PRI10)

0x42C

PRI11

R/W

0x0000 0000

Interrupt 44–47 Priority

Interrupt 44–47 Priority (PRI11)

0x430

PRI12

R/W

0x0000 0000

Interrupt 48–51 Priority

Interrupt 48–51 Priority (PRI12)

0x434

PRI13

R/W

0x0000 0000

Interrupt 52–55 Priority

Interrupt 52–55 Priority (PRI13)

0x438

PRI14

R/W

0x0000 0000

Interrupt 56–59 Priority

Interrupt 56–59 Priority (PRI14)

0x43C

PRI15

R/W

0x0000 0000

Interrupt 60–63 Priority

Interrupt 60–63 Priority (PRI15)

0x440

PRI16

R/W

0x0000 0000

Interrupt 64–67 Priority

Interrupt 64–67 Priority (PRI16)

0x444

PRI17

R/W

0x0000 0000

Interrupt 68–71 Priority

Interrupt 68–71 Priority (PRI17)

0x448

PRI18

R/W

0x0000 0000

Interrupt 72–75 Priority

Interrupt 72–75 Priority (PRI18)

0x44C

PRI19

R/W

0x0000 0000

Interrupt 76–79 Priority

Interrupt 76–75 Priority (PRI19)

0x450

PRI20

R/W

0x0000 0000

Interrupt 80–83 Priority

Interrupt 80–83 Priority (PRI20)

0x454

PRI21

R/W

0x0000 0000

Interrupt 84–87 Priority

Interrupt 84–87 Priority (PRI21)

0x458

PRI22

R/W

0x0000 0000

Interrupt 88–91 Priority

Interrupt 88–91 Priority (PRI22)

0x45C

PRI23

R/W

0x0000 0000

Interrupt 92–95 Priority

Interrupt 92–95 Priority (PRI23)

0x460

PRI24

R/W

0x0000 0000

Interrupt 96–99 Priority

Interrupt 96–99 Priority (PRI24)

0x464

PRI25

R/W

0x0000 0000

Interrupt 100–103
Priority

Interrupt 100–103 Priority (PRI25)

0x468

PRI26

R/W

0x0000 0000

Interrupt 104–107
Priority

Interrupt 104–107 Priority (PRI26)

0x46C

PRI27

R/W

0x0000 0000

Interrupt 108–111
Priority

Interrupt 108–111 Priority (PRI27)

0x470

PRI28

R/W

0x0000 0000

Interrupt 112–115
Priority

Interrupt 112–115 Priority (PRI28)

0x474

PRI29

R/W

0x0000 0000

Interrupt 116–119
Priority

Interrupt 116–119 Priority (PRI29)

0x478

PRI30

R/W

0x0000 0000

Interrupt 120–123
Priority

Interrupt 120–123 Priority (PRI30)

0x47C

PRI31

R/W

0x0000 0000

Interrupt 124–127
Priority

Interrupt 124–127 Priority (PRI31)

0x480

PRI32

R/W

0x0000 0000

Interrupt 128–131
Priority

Interrupt 128–131 Priority (PRI32)

0x484

PRI33

R/W

0x0000 0000

Interrupt 132–135
Priority

Interrupt 132–135 Priority (PRI33)

0x488

PRI34

R/W

0x0000 0000

Interrupt 136–139
Priority

Interrupt 136–139 Priority (PRI34)

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Table 3-7. Peripherals Register Map (continued)
OFFSET

NAME

TYPE

RESET

DESCRIPTION

LINK

0x48C

PRI35

R/W

0x0000 0000

Interrupt 140–143
Priority

Interrupt 140–143 Priority (PRI35)

0x490

PRI36

R/W

0x0000 0000

Interrupt 144–147
Priority

Interrupt 144–147 Priority (PRI36)

0xF00

SWTRIG

0x0000 0000

Software Trigger
Interrupt

Software Trigger Interrupt (SWTRIG)

SCB Registers
0x008

ACTLR

R/W

0x0000 0000

Auxiliary Control

Auxiliary Control (ACTLR)

0xD00

CPUID

0x412F C230

CPU ID Base

CPU ID Base (CPUID)

0xD04

INTCTRL

R/W

0x0000 0000

Interrupt Control and
State

Interrupt Control and State
(INTCTRL)

0xD08

VTABLE

R/W

0x0000 0000

Vector Table Offset

Vector Table Offset (VTABLE)

0xD0C

APINT

R/W

0xFA05 0000

Application Interrupt
and Reset Control

Application Interrupt and Reset
Control (APINT)

0xD10

SYSCTRL

R/W

0x0000 0000

System Control

System Control (SYSCTRL)

0xD14

CFGCTRL

R/W

0x0000 0200

Configuration and
Control

Configuration and Control
(CFGCTRL)

0xD18

SYSPRI1

R/W

0x0000 0000

System Handler
Priority 1

System Handler Priority 1
(SYSPRI1)

0xD1C

SYSPRI2

R/W

0x0000 0000

System Handler
Priority 2

System Handler Priority 2
(SYSPRI2)

0xD20

SYSPRI3

R/W

0x0000 0000

System Handler
Priority 3

System Handler Priority 3
(SYSPRI3)

0xD24

SYSHNDCTRL

R/W

0x0000 0000

System Handler
Control and State

System Handler Control and State
(SYSHNDCTRL)

0xD28

FAULTSTAT

R/W1C

0x0000 0000

Configurable Fault
Status

Configurable Fault Status
(FAULTSTAT)

0xD2C

HFAULTSTAT

R/W1C

0x0000 0000

Hard Fault Status

Hard Fault Status (HFAULTSTAT)

0xD34

MMADDR

R/W

–

Memory Management
Fault Address

Memory Management Fault Address
(MMADDR)

0xD38

FAULTADDR

R/W

–

Bus Fault Address

Bus Fault Address (FAULTADDR)

MPU Registers
0xD90

MPUTYPE

0x0000 0800

MPU Type

MPU Type (MPUTYPE)

0xD94

MPUCTRL

R/W

0x0000 0000

MPU Control

MPU Control (MPUCTRL)

0xD98

MPUNUMBER

R/W

0x0000 0000

MPU Region Number

MPU Region Number
(MPUNUMBER)

0xD9C

MPUBASE

R/W

0x0000 0000

MPU Region Base
Address

MPU Region Base Address
(MPUBASE)

0xDA0

MPUATTR

R/W

0x0000 0000

MPU Region Attribute
and Size

MPU Region Attribute and Size
(MPUATTR)

0xDA4

MPUBASE1

R/W

0x0000 0000

MPU Region Base
Address Alias 1

MPU Region Base Address Alias 1
(MPUBASE1)

0xDA8

MPUATTR1

R/W

0x0000 0000

MPU Region Attribute
and Size Alias 1

MPU Region Attribute and Size Alias
1 (MPUATTR1), Offset 0xDA8

0xDAC

MPUBASE2

R/W

0x0000 0000

MPU Region Base
Address Alias 2

MPU Region Base Address Alias 2
(MPUBASE2)

0xDB0

MPUATTR2

R/W

0x0000 0000

MPU Region Attribute
and Size Alias 2

MPU Region Attribute and Size Alias
2 (MPUATTR2)

0xDB4

MPUBASE3

R/W

0x0000 0000

MPU Region Base
Address Alias 3

MPU Region Base Address Alias 3
(MPUBASE3)

0xDB8

MPUATTR3

R/W

0x0000 0000

MPU Region Attribute
and Size Alias 3

MPU Region Attribute and Size Alias
3 (MPUATTR3)

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SysTick Register Descriptions

3.4

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SysTick Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
SysTick Control and Status Register (STCTRL)

Address Offset

0x010

Reset

Physical Address

0xE000 E000

Instance

0x0000 0004

Description
Note: This register can be accessed only from privileged mode.
The SysTick STCTRL register enables the SysTick features.

RESERVED

Bits

Field Name

Description

31:17

RESERVED

Reserved

COUNT

Count flag

RESERVED

Value

Description

The SysTick timer has not counted to 0 since the last
time this bit was read.

The SysTick timer has counted to 0 since the last time
this bit was read.

0
ENABLE

COUNT

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INTEN

R/W

CLK_SRC

Type

Reset

0x000

This bit is cleared by a read of the register or if the STCURRENT
register is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear.
Otherwise, the COUNT bit is not changed by the debugger read.
For more information on MasterType, see the ARM Debug
Interface V5 Architecture Specification.
15:3
2

RESERVED

Reserved

0x000

CLK_SRC

Clock source

R/W

Value

Description

External reference clock (not implemented for CC2538
microcontrollers)

System clock

Because an external reference clock is not implemented, this bit
must be set in order for SysTick to operate.
1

INTEN

ENABLE

Interrupt enable
Value

Description

Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached
0.

An interrupt is generated to the NVIC when SysTick
counts to 0.

Enable
Value

Description

The counter is disabled.

Enables SysTick to operate in a multiple-shot way. That
is, the counter loads the RELOAD value and begins
counting down. On reaching 0, the COUNT bit is set and
an interrupt is generated if enabled by INTEN. The
counter then loads the RELOAD value again and begins
counting.

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SysTick Reload Value Register (STRELOAD)
Address Offset

0x014

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter
reaches 0. The start value can be between 0x1 and 0x00FF FFFF. A start value of 0 is possible but has no effect because the SysTick
interrupt and the COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multiple-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to
0x00FF FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED

RELOAD

Bits

Field Name

Description

31:24

RESERVED

Reserved

Type
RO

Reset
0x00

23:0

RELOAD

Reload value
Value to load into the SysTick Current Value (STCURRENT)
register when the counter reaches 0.

R/W

0x00 0000

SysTick Current Value Register (STCURRENT)
Address Offset

0x018

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
Type

R/WC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bits

CURRENT

Field Name

Description

31:24

Reserved

23:0

CURRENT

Current value
This field contains the current value at the time the register is
accessed. No read-modify-write protection is provided, so change
with care.
This register is write-clear. Writing to it with any value clears the
register. Clearing this register also clears the COUNT bit of the
STCTRL register

3.5

Type

Reset

0x00

R/WC

0x00 0000

NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in
unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other
unprivileged mode access causes a bus fault.
Ensure that software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.

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Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of
the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For
more information, see Vector Table Offset (VTABLE).
Interrupt 0–31 Set Enable (EN0)
Address Offset

0x100

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
See Table 5-2 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt
signal changes the interrupt state to pending, but the NVIC never activates the interrupt regardless of its priority.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt enable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can be cleared only by setting the corresponding INT[n] bit in
the DISn register.

Interrupt 32–63 Set Enable (EN1)
Address Offset

0x104

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 31 corresponds to
Interrupt 63. See Table 5-2 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt
signal changes the interrupt state to pending, but the NVIC never activates the interrupt regardless of its priority.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt enable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can be cleared only by setting the corresponding INT[n] bit in
the DIS1 register.

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Interrupt 64–95 Set Enable (EN2)
Address Offset

0x108

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The EN2 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 64; bit 31 corresponds to
Interrupt 95. See Table 5-2 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt
signal changes the interrupt state to pending, but the NVIC never activates the interrupt regardless of its priority.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt enable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can be cleared only by setting the corresponding INT[n] bit in
the DISn register.

Interrupt 96–127 Set Enable (EN3)
Address Offset

0x10C

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The EN3 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 96; bit 31 corresponds to
Interrupt 127. See Table 5-2 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt
signal changes the interrupt state to pending, but the NVIC never activates the interrupt regardless of its priority.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt enable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

A bit can be cleared only by setting the corresponding INT[n] bit in
the DISn register.

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Interrupt 128–147 Set Enable (EN4)
Address Offset

0x110

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The EN4 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 128; bit 19 corresponds to
Interrupt 147. See Table 5-2 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt
signal changes the interrupt state to pending, but the NVIC never activates the interrupt regardless of its priority.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED

INT

Bits

Field Name

Description

Type

31:20

RESERVED

Reserved

0x000

19:0

INT

Interrupt enable

R/W

0x0 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.

Reset

A bit can be cleared only by setting the corresponding INT[n] bit in
the DISn register.

Interrupt 0–31 Clear Enable (DIS0)
Address Offset

0x180

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt disable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the
EN0 register, disabling interrupt [n].

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Interrupt 32–63 Clear Enable (DIS1)
Address Offset

0x184

Reset

Physical Address

0xE000 E000

Instance

0xE000 E000

Description
Note: This register can be accessed only from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. See Table 5-2 for interrupt
assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt disable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the
EN1 register, disabling interrupt [n]

Interrupt 64–95 Clear Enable (DIS2)
Address Offset

0x188

Reset

Physical Address

0xE000 E000

Instance

0xE000 E000

Description
Note: This register can be accessed only from privileged mode.
The DIS2 register disables interrupts. Bit 0 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. See Table 5-2 for interrupt
assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt disable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the
EN2 register, disabling interrupt [n]

Interrupt 96–127 Clear Enable (DIS3)
Address Offset

0x18C

Reset

Physical Address

0xE000 E000

Instance

0xE000 E000

Description
Note: This register can be accessed only from privileged mode.
The DIS3 register disables interrupts. Bit 0 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. See Table 5-2 for interrupt
assignments.
Type

R/W

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt disable

R/W

0x0000 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the
EN3 register, disabling interrupt [n]

Interrupt 128–147 Clear Enable (DIS4)
Address Offset

0x190

Reset

Physical Address

0xE000 E000

Instance

0xE000 E000

Description
Note: This register can be accessed only from privileged mode.
The DIS4 register disables interrupts. Bit 0 corresponds to Interrupt 128; bit 19 corresponds to Interrupt 147. See Table 5-2 for interrupt
assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED

INT

Bits

Field Name

Description

31:20

RESERVED

Reserved

Type
RO

0x000

19:0

INT

Interrupt disable

R/W

0x0 0000

Value

Description

On a read, indicates the interrupt is disabled.
On a write, no effect.

On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the
EN4 register, disabling interrupt [n]

Reset

Interrupt 0–31 Set Pending (PEND0)
Address Offset

0x200

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt set pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

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Bits

Field Name

Description
1

Type

Reset

On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

If the corresponding interrupt is already pending, setting a bit has
no effect.
A bit can be cleared only by setting the corresponding INT[n] bit in
the UNPEND0 register.

Interrupt 32–63 Set Pending (PEND1)
Address Offset

0x204

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit
31 corresponds to Interrupt 63. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt set pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

If the corresponding interrupt is already pending, setting a bit has
no effect.
A bit can be cleared only by setting the corresponding INT[n] bit in
the UNPEND1 register.

Interrupt 64–95 Set Pending (PEND2)
Address Offset

0x208

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The PEND2 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 64; bit
31 corresponds to Interrupt 95. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt set pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

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Bits

Field Name

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Description

Type

Reset

If the corresponding interrupt is already pending, setting a bit has
no effect.
A bit can be cleared only by setting the corresponding INT[n] bit in
the UNPEND2 register.

Interrupt 96–127 Set Pending (PEND3)
Address Offset

0x20C

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The PEND3 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 96; bit
31 corresponds to Interrupt 127. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt set pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

If the corresponding interrupt is already pending, setting a bit has
no effect.
A bit can be cleared only by setting the corresponding INT[n] bit in
the UNPEND3 register.

Interrupt 128–147 Set Pending (PEND4)
Address Offset

0x210

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The PEND4 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 128; bit
19 corresponds to Interrupt 147. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED

INT

Bits

Field Name

Description

Type

31:20

RESERVED

Reserved

0x000

19:0

INT

Interrupt set pending

R/W

0x0 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.

Reset

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Bits

Field Name

Description

Type

Reset

If the corresponding interrupt is already pending, setting a bit has
no effect.
A bit can be cleared only by setting the corresponding INT[n] bit in
the UNPEND4 register.

Interrupt 0–31 Clear Pending (UNPEND0)
Address Offset

0xE000 E000

Reset

Physical Address

0x280

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt clear pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the
PEND0 register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the
corresponding interrupt.

Interrupt 32–63 Clear Pending (UNPEND1)
Address Offset

0x284

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt
32; bit 31 corresponds to Interrupt 63. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt clear pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the
PEND1 register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the
corresponding interrupt.

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Interrupt 64–95 Clear Pending (UNPEND2)
Address Offset

0x288

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The UNPEND2 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt
64; bit 31 corresponds to Interrupt 95. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt clear pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the
PEND2 register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the
corresponding interrupt.

Interrupt 96–127 Clear Pending (UNPEND3)
Address Offset

0x28C

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The UNPEND3 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt
96; bit 31 corresponds to Interrupt 127. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

Type

Reset

31:0

INT

Interrupt clear pending

R/W

0x0000 0000

Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the
PEND3 register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the
corresponding interrupt.

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Interrupt 128–147 Clear Pending (UNPEND4)
Address Offset

0x290

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The UNPEND4 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt
128; bit 19 corresponds to Interrupt 147. See Table 5-2 for interrupt assignments.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED

INT

Bits

Field Name

Description

31:20

RESERVED

Reserved

19:0

INT

Interrupt clear pending
Value

Description

On a read, indicates that the interrupt is not pending.
On a write, no effect.

On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the
PEND4 register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the
corresponding interrupt.

Type

Reset

0x0

R/W

0x0 0000

Interrupt 0–31 Active Bit (ACTIVE0)
Address Offset

0x300

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
See Table 5-2 for interrupt assignments.
Caution: Do not manually set or clear the bits in this register.
Type

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

31:0

INT

Interrupt active
Value

Description

The corresponding interrupt is not active.

The corresponding interrupt is active, or active and
pending.

Type

Reset

0x0000 0000

Interrupt 32–63 Active Bit (ACTIVE1)
Address Offset

0x304

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. See
Table 5-2 for interrupt assignments.
Caution: Do not manually set or clear the bits in this register.
Type

RO
87

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

31:0

INT

Interrupt active
Value

Description

The corresponding interrupt is not active.

The corresponding interrupt is active, or active and
pending.

Type

Reset

0x0000 0000

Interrupt 64–95 Active Bit (ACTIVE2)
Address Offset

0x308

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The ACTIVE2 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. See
Table 5-2 for interrupt assignments.
Caution: Do not manually set or clear the bits in this register.
Type

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

31:0

INT

Interrupt active
Value

Description

The corresponding interrupt is not active.

The corresponding interrupt is active, or active and
pending.

Type

Reset

0x0000 0000

Interrupt 96–127 Active Bit (ACTIVE3)
Address Offset

0x30C

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The ACTIVE3 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. See
Table 5-2 for interrupt assignments.
Caution: Do not manually set or clear the bits in this register.
Type

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

INT
Bits

Field Name

Description

31:0

INT

Interrupt active
Value

Description

The corresponding interrupt is not active.

The corresponding interrupt is active, or active and
pending.

Type

Reset

0x0000 0000

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Interrupt 128–147 Active Bit (ACTIVE4)
Address Offset

0x310

Reset

Physical Address

0xE000 E000

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The ACTIVE4 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 128; bit 19 corresponds to Interrupt 147. See
Table 5-2 for interrupt assignments.
Caution: Do not manually set or clear the bits in this register.
Type

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED

INT

Bits

Field Name

Description

Type

31:20

RESERVED

Reserved

0x000

19:0

INT

Interrupt active

0x0 0000

Value

Description

The corresponding interrupt is not active.

The corresponding interrupt is active, or active and
pending.

Reset

Interrupt 0–3 Priority (PRI0)
Address Offset

0xE000 E000

Reset

Physical Address

0x400

Instance

0x0000 0000

Description
Note: This register can be accessed only from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields
that are assigned to interrupts as follows:
PRIn Register Bit Field

Interrupt

Bits 31:29

Interrupt [4n+3]

Bits 23:21

Interrupt [4n+2]

Bits 15:13

Interrupt [4n+1]

Bits 7:5

Interrupt [4n]

See Table 5-2 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and
Reset Control (APINT) register (see Application Interrupt and Reset Control (APINT)) indicates the position of the binary point that splits
the priority and subpriority fields.
These registers can be accessed only from privileged mode.
Type

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INTD
Bits

RESERVED

INTC

RESERVED

INTB

RESERVED

6
INTA

RESERVED

Field Name

Description

Type

Reset

31:29

INTD

Interrupt priority for interrupt [4n+3]
This field holds a priority value, 0–7, for the interrupt with the
number [4n+3], where n is the number of the Interrupt Priority
register (n=0 for PRI0, and so on). The lower the value, the greater
the priority of the corresponding interrupt.

R/W

0x0

28:24

RESERVED

Reserved

0x00

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Field Name

Description

Type

Reset

23:21

INTC

Interrupt priority for interrupt [4n+2]
This field holds a priority value, 0–7, for the interrupt with the
number [4n+2], where n is the number of the Interrupt Priority
register (n=0 for PRI0, and so on). The lower the value, the greater
the priority of the corresponding interrupt.

R/W

0x0

20:16

RESERVED

Reserved

0x00

15:13

INTB

Interrupt priority for interrupt [4n+1]
This field holds a priority value, 0–7, for the interrupt with the
number [4n+1], where n is the number of the Interrupt Priority
register (n=0 for PRI0, and so on). The lower the value, the greater
the priority of the corresponding interrupt.

R/W

0x0

12:8

RESERVED

Reserved

0x00

7:5

INTA

Interrupt priority for interrupt [4n]
This field holds a priority value, 0–7, for the interrupt with the
number [4n], where n is the number of the Interrupt Priority
register (n=0 for PRI0, and so on). The lower the value, the greater
the priority of the corresponding interrupt.

R/W

0x0

4:0

RESERVED

Reserved

0x00

Interrupt 4–7 Priority (PRI1)
Address Offset

0xE000 E000

Reset

Physical Address

0x0000 0000

Instance

Interrupt

Bits 31:29

Interrupt [4n+3]

Bits 23:21

Interrupt [4n+2]

Bits 15:13

Interrupt [4n+1]

Bits 7:5

Interrupt [4n]

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INTD
Bits

RESERVED

INTC

RESERVED

INTB

RESERVED

6
INTA

Field Name

Description

Type

Reset

31:29

INTD

R/W

0x0

28:24

RESERVED

Reserved

0x00

23:21

INTC

R/W

0x0

20:16

RESERVED

Reserved

0x00

RESERVED

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Bits

Field Name

Description

Type

Reset

15:13

INTB

R/W

0x0

12:8

RESERVED

Reserved

0x00

7:5

INTA

R/W

0x0

4:0

RESERVED

Reserved

0x00

Interrupt 8–11 Priority (PRI2)
Address Offset

0xE000 E000

Reset

Physical Address

0x408

Instance

0x0000 0000

Interrupt

Bits 31:29

Interrupt [4n+3]

Bits 23:21

Interrupt [4n+2]

Bits 15:13

Interrupt [4n+1]

Bits 7:5

Interrupt [4n]

R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INTD
Bits

RESERVED

INTC

RESERVED

INTB

RESERVED

6
INTA

RESERVED

Field Name

Description

Type

Reset