Performance Designed PL051003T Afterglow Nur PS4/PS3 Wireless Stand User Manual AV6301 Datasheet Rev 0 4x

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Preliminary Datasheet
AV6301
Wireless Audio Sender IC
General Description
AV6301
The AV6301 / 6302 chipset is optimized for building
wireless gaming headsets and point to multi-point
audio distribution solutions such as rear speakers
and subwoofers in home theater systems..The
chipset is comprised of two ICs: AV6301 (sender)
and AV6302 (client). These devices share the VMI
RF Protocol and may be mixed and matched with
other VMI chips (AAV6200, V6201, and AV6202).
The AV6301 is a highly integrated, single-chip,
wireless audio sender IC. It integrates the following: a
complete 2.4 GHz RF transceiver, PHY & MAC,
advanced power management hardware, audio DSP,
USB 2.0 transceiver and a full complement of
programmable digital interfaces to support a wide
range of end-product user-interface requirements,
including SPI and TWI interfaces.
The AV6301 / 02 chipset achieves the goal of
enabling a single core design to service multiple
game platforms (PC or Console), External Digital
Signal Processing (DSP) is also easily supported
for all gaming platforms.
The chip set provides all functions necessary to
complete a bidirectional wireless audio link with
high quality voice and music performance.
Operation in the worldwide 2.4 GHz spectrum
addresses the need for global application.
The device incorporates a complete USB 2.0
transceiver and enumerates as a USB Audio device
as well as USB Human Interface Device (HID) without
the need for external drivers, enabling true plug &
play. Additionally, the device makes available 3
independent I2S interfaces, allowing independent
processing of non-USB audio sources. Simultaneous
use of the USB and I2S ports is enhanced by
additional audio processing capability, allowing for
independent control and mixing of the different audio
sources.
System / Chipset Features
AV6301 Features
Stereo audio path: >93 dB SNR, 20 kHz
USB Port Enumerates as Audio and / or
Human interface device (HID)
Mono voice path: >70 dB SNR, 6.5 kHz
voice
Sophisticated audio routing and mixing
options to meet demands of multiple gaming
headset platforms
Over-the-air (OTA) serial interface: >2
kbps, bi-directional, full duplex
Works within 3 inches of WIFI Client
without impairment to Audio or WIFI throughput
Advanced forward error correction coding,
error detection, and audio-specific error
concealment
Diversity antenna support
Low and Fixed Latency: <16 ms,
Long Range: 15m (non-line-of-site)
Auto search/sync/standby/wakeup/shutdown
All Voltage Regulators on-chip
Interoperability with VMI (AV6201 / 02)
Chipset
Advanced Signal Routing Capability
BW
Three available I2S ports
9 Simultaneous operation of USB and I2S
ports
Expansive Digital I/O Capability
20 General Purpose Input / Output Pins
Master and Slave SPI and TWI interfaces
Pulse Width Modulated (PWM) I/O support
Straightforward implementation of external
EEPROM, DSP, Audio Codec and Host uC for
advanced applications
On-Chip One-Time-Programmable (OTP)
Memory
Applications
PC Game Wireless Headset
Game Console Wireless Headset
I2S based Wireless Audio
Wireless Rear Speakers
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA
Packaging
The AV6301 is packaged in a 7 x 7 mm, 48 pin
QFN and is rated for operation over the commercial
temperature range (0 to 70 degrees C)
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
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AV6301 Datasheet (Preliminary)
revision 0.2
Revision History
Revision
Change Summary
Release Date
0.1
0.2
Preliminary release of datasheet
Add AV6xxx Selection Grid, Update Audio Routing, Block Diagram, Application
Circuit, Pin Out and Pin Description. RF TX Electrical characteristics update.
Update Selector Grid
CORRECTION to I2S assignments to GPIO ports (stereo in, stereo out and mono
out have all changed).I2S assignments reflected in Applications Diagram. Update
of selection grid.
10/7/11
10/27/11
0.3
0.4
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
11/4/11
11/15/11
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AV6301 Datasheet (Preliminary)
revision 0.2
Table of Contents
General Description .............................................................................................................................................................. 1
System / Chipset Features ................................................................................................................................................... 1
AV6301................................................................................................................................................................................. 1
AV6301 Features.................................................................................................................................................................. 1
Applications .......................................................................................................................................................................... 1
Packaging............................................................................................................................................................................. 2
Revision History.................................................................................................................................................................... 3
Table 0-1 AV6xxx Selection Grid .......................................................................................................................................... 6
REFERENCE DIAGRAMS .......................................................................................................................................... 7
1.1 Wireless Arbiter Solution Diagram.......................................................................................................................... 7
1.2 Functional Diagram ................................................................................................................................................ 8
1.3 Audio Signal Routing Diagram ............................................................................................................................... 8
1.4 Application Circuit – Wireless Universal Gaming Arbiter ........................................................................................ 9
PIN INFORMATION .................................................................................................................................................. 10
2.1 Pin Diagram.......................................................................................................................................................... 10
2.2 Pin Description ..................................................................................................................................................... 11
ELECTRICAL SPECIFICATIONS ............................................................................................................................. 13
3.1 Absolute Maximum Ratings.................................................................................................................................. 13
3.2 DC Electrical Characteristics ................................................................................................................................ 14
3.3 Electrical Characteristics – Voltage Supervisory Circuit ....................................................................................... 14
3.4 Electrical Characteristics – RF Receiver .............................................................................................................. 15
3.5 Electrical Characteristics – RF Transmitter .......................................................................................................... 15
3.6 Electrical Characteristics – End-to-end Audio Characteristics.............................................................................. 15
PACKAGE INFORMATION....................................................................................................................................... 16
4.1 Package Outline Drawing ..................................................................................................................................... 16
4.2 Package Marking.................................................................................................................................................. 17
CONTACT INFO & LEGAL DISCLAIMER................................................................................................................. 18
List of Tables
Table 0-1 AV6xxx Selection Grid .......................................................................................................................................... 6
Table 2-2-1 AV301 pin description...................................................................................................................................... 11
Table 3-1 Absolute Maximum Ratings ................................................................................................................................ 13
Table 3-2 AV6301 DC Electrical Characteristics ................................................................................................................ 14
Table 3-3 AV6301 Electrical Characteristics - Voltage Supervisory ................................................................................... 14
Table 3-4 AV6301 Electrical Characteristics - RF Receiver................................................................................................ 15
Table 3-5 AV6301 Electrical Characteristics - RF Transmitter............................................................................................ 15
Table 3-6 AV6301 Electrical Characteristics - End-to-End Audio Characteristics............................................................... 15
List of Figures
Figure 1-1 AV6301 Wireless Arbiter Solution ....................................................................................................................... 7
Figure 1-2 AV6301 Functional Diagram................................................................................................................................ 8
Figure 1-3 AV6301 Audio Routing ........................................................................................................................................ 8
Figure 1-4 AV6301 Application Circuit .................................................................................................................................. 9
Figure 2-1 AV6301 Pin Diagram ......................................................................................................................................... 10
Figure 4-1 AV6301 48 Pin QFN Outline Drawing ............................................................................................................... 16
Figure 4-2 Package Marking Layout ................................................................................................................................... 17
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
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AV6301 Datasheet (Preliminary)
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
revision 0.2
AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA
AV6301 Datasheet (Preliminary)
revision 0.2
Table 0-1 AV6xxx Selection Grid
Part Number
Role
I2S IN
I2S Out
AV6200
AV6201
Stereo
N/A
Sender
No
No
AV6301
AV6200
AV6202
AV6302
Stereo
Stereo
Mono
Audio /
HID
No
No
N/A
Stereo
Receiver
Mono
Stereo
No
HID
Mono
Stereo
Mono
HID
No
No
Yes
Yes
Yes
Yes
USB Port
No
MIC Amp
Headphone
Driver Amp
Battery
Charger
General
Purpose
ADCs
Button
Support
Rotary
Encoder
Support
LED Support
No
No
Audio /
HID
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No
No
No
N/A
N/A
N/A
N/A
No
Yes
N/A
N/A
N/A
N/A
Yes
Yes
N/A
No
Yes
N/A
N/A
N/A
N/A
N/A
N/A
No
No
Yes
I2S LoopBack
(external
DSP)
MIC path
input to I2S
out
MIC Sidetone Mix
Game / Chat
Mix on TX
Game / Chat
Mix at RX
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AV6301 Datasheet (Preliminary)
revision 0.2
1 REFERENCE DIAGRAMS
1.1
Wireless Arbiter Solution Diagram
Figure 1-1 AV6301 Wireless Arbiter Solution
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AV6301 Datasheet (Preliminary)
1.2
revision 0.2
Functional Diagram
VDC
3.6V
LDO
USB
Spnd
XTAL
SUP
VBG
REF
DIG
Regs
3.3V
REG
V3P6
MCU
RFP
RFN
ROM
RAM
OTP
GPIO
20
RF/IF
Transceiver
PHY
Audio
Proc
USB
GPIO
DSCP,DSCN
SPI, I2C
GPIO (Buttons, LEDs)
I2S
DP
DM
Figure 1-2 AV6301 Functional Diagram
1.3
Audio Signal Routing Diagram
Figure 1-3 AV6301 Audio Routing
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AV6301 Datasheet (Preliminary)
1.4
revision 0.2
Application Circuit – Wireless Universal Gaming Arbiter
Figure 1-4 AV6301 Application Circuit
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AV6301 Datasheet (Preliminary)
revision 0.2
2 PIN INFORMATION
2.1
Pin Diagram
Figure 2-1 AV6301 Pin Diagram
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AV6301 Datasheet (Preliminary)
2.2
revision 0.2
Pin Description
Table 2-2-1 AV301 pin description
Pin No.
6,8,10-14,
16, 19, 20,
23
15
17
18
21
22
24
25
26
27
28
29
30
32
31
33
34
35
36
37
Symbol
GPIO1
DSCN
DPA-EN
GPIO0
DSCP
DSC
XTALP
XTALN
VDDXO
N/C
Pin Type
Digital Output
IREF
BGOUT
VDDRXADC
RFP
RFN
VDC
V3P6
RESETN
GPIO16
PWM2
GPIO15
I2S MONO OUT
PWM1
GPIO14
I2S STEREO IN
GPIO13
I2S STEREO OUT
GPIO12
WCLK
GPIO11
BCLK
PWM1
VDDIO
GPIO10
MCLK
PWM0
GPIO9
M_MISO (SPI Mater)
M_SCL (TWI Master)
SCL (TWI)
GPIO8
M_MOSI (SPI Master)
M_SDA (TWI Master)
SDA (TWI)
GPIO7
M_SCLK (SPI Master)
PWM1
GPIO6
M_SSB (SPI Master)
PWM0
GPIO19
Analog pin
Analog bypass
Bypass
RF I/O
RF I/O
Supply pin
Bypass
Digital input
Digital I/O
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
Description
GPIO port 1; Usage is programmable to GPIO OR to
Antenna Diversity Switch – OR to
Power Amplifier Enable
GPIO port 0; Usage is programmable to GPIO OR to
Antenna Diversity Switch + OR to
Single Polarity Diversity Switch Control
External crystal input
External crystal input
Crystal oscillator regulator bypass pin
No connection – Leave unconnected – Do not Ground
Digital Output
Analog input
Analog input
Analog
Reference current setting resistor connection
Bandgap reference bypass pin
Bypass pin for Receiver Data Converter Supply
RF input/output positive
RF input/output negative
5V input supply voltage from USB
Bypass pin for 3.6V main regulator
RESET signal; active low
GPIO port 16, usage is programmable to GPIO OR to
PWM resource #2
GPIO port 15, usage is programmable to GPIO OR to
I2S port 2 MONO OUT Data
PWM resource #1
GPIO port 14; usage is programmable to GPIO OR to
I2S Port 1 STEREO IN Data
GPIO port 13; usage is programmable to GPIO OR to
I2S Port 0 STEREO OUT Data
GPIO port 12; usage is programmable to GPIO OR to
I2S Word Clock
GPIO port 11; usage is programmable to GPIO OR to
I2S Bit Clock OR to
PWM resource #1
Supply bypass capacitor pin for digital I/O
GPIO port 10; usage is programmable to GPIO OR to
I2S Master Clock OR to
PWM resource #0
GPIO port 9; usage is programmable to GPIO OR to
M_MISO OR to
M_SCL OR to
SCL
GPIO port 8; usage is programmable to GPIO OR to
M-MOSI OR to
M_SDA OR to
SDA
GPIO port 7; usage is programmable to GPIO OR to
M_SCLK OR to
PWM resource #1
GPIO port 6; usage is programmable to GPIO OR to
M-SSB OR to
PWM resource #0
GPIO port 19, usage is programmable to GPIO OR to
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
11
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AV6301 Datasheet (Preliminary)
Pin No.
38
39
40
41
42
43
44
45
46
47
48
Symbol
PWM2
VDDDIG
VDD18
VDDIO
DM
DP
GPIO18
PWM1
GPIO5
S_MISO (SPI Slave)
S_SCL (TWI Slave)
GPIO4
S_MOSI (SPI Slave)
S_SDA (TWI Slave)
GPIO3
S_SCLK (SPI Slave)
UART_RX
PWM1
GPIO2
S_SSB (SPI Slave)
UART_TX
PWM0
GPIO17
PWM2
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
revision 0.2
Pin Type
Description
PWM resource #2
Bypass capacitor pin for 1.35V digital core regulator
Bypass capacitor pin for 1.8V digital regulator (LDO)
Bypass capacitor pin for 3.3V digital I/O regulator
USB negative input
USB positive input
GPIO port 18, usage is programmable to GPIO OR to
PWM resource #1
GPIO port 5; usage is programmable to GPIO OR to
S_MISO OR to
S_SCL
GPIO port 4; usage is programmable to GPIO OR to
S_MOSI OR to
S_SDA
GPIO port 3; usage is programmable to GPIO OR to
S_SCLK OR to
The UART Receiver OR to
PWM resource #1
GPIO port 2; usage is programmable to GPIO OR to
S_SSB OR to
The UART Transmitter OR to
PWM resource #0
GPIO port 17, usage is programmable to GPIO OR to
PWM resource #2
Bypass
Bypass
Bypass
USB I/O
USB I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
12
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AV6301 Datasheet (Preliminary)
revision 0.2
ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to
instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Absolute Maximum Ratings are
stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits.
Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at
the test conditions specified.
Table 3-1 Absolute Maximum Ratings
CONDITION
MIN
MAX
Units
Supply (relative to AGND and DGND)
-0.3
6.0
Input Voltage Range – Digital Inputs
VDC
-0.3
3.6
Input Voltage Range – Analog Inputs
-0.3
3.6
--
continuous
Short circuit to GND (any pin)
Operating Temperature
-40
+85
ºC
Storage Temperature
-40
+100
ºC
--
+300
ºC
Lead Temperature (10s)
Static Discharge Voltage – HBM (All pins )
3000
Static Discharge Voltage – MM
300
Note:
1)
HBM = ESD Human Body Model; C = 100pF, R = 1kΩ
2)
MM = ESD Machine Model; C = 100pF; R = 300Ω
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AV6301 Datasheet (Preliminary)
revision 0.2
3.2 DC Electrical Characteristics
Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0ºC to +70 ºC; Typical specifications at TA = 25ºC, VDC = 5.0V.
Table 3-2 AV6301 DC Electrical Characteristics
PARAMETER
CONDITIONS
MIN
VDC Supply Voltage Input
4.4
TYP
MAX
5.0
5.5
UNIT
V3P6
Internally regulated voltage
3.6
VDDIO (Digital 3.3V I/O) Reg. Voltage
Internally regulated voltage
3.3
VDDDIG (Digital Core) Reg. Voltage
Internally regulated voltage
1.35
VDD1P8
Internally regulated voltage
1.8
Supply Current (IVDC) – USB chip
Reset
TBD
USB Suspend Mode
1.0
Arbiter Search Mode
TBD
TBD
mA
55
TBD
mA
TBD
mA
0.8
0.4
Arbiter Headset Link Mode
GPIO Source Current
mA
CMOS I/O Logic Levels – 3.3V I/O
Input Voltage Logic Low, VIL
VVDDIO = 3.3V
Input Voltage Logic High, VIH
VVDDIO = 3.3V
Output Voltage Logic Low, VOL
VVDDIO = 3.3V ; ILOAD=1mA
Output Voltage Logic High, VOH
VVDDIO = 3.3V; ILOAD=1mA
2.0
2.9
USB Interface
DP Logic Output High
refer to USB spec; voltage relative to VDDIO
0.8*VDD
IO
DM Logic Output Low
refer to USB spec; voltage relative to VDDIO
0.2*VDD
IO
DP Logic Input High
refer to USB spec; voltage relative to VDDIO
0.7*VDD
IO
DM Logic Input Low
refer to USB spec; voltage relative to VDDIO
0.3*VDD
IO
USB Differential Input Sensitivity
0.2
USB Differential Common Mode
0.8
2.5
USB Single Ended RX Threshold
0.8
2.0
0.3
USB IO Pin Static Output (Low)
Rl=1.5k to 3.6V
3.3 Electrical Characteristics – Voltage Supervisory Circuit
Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0ºC to +70 ºC; Typical specifications at TA = 25ºC, VDC = 5.0V.
Table 3-3 AV6301 Electrical Characteristics - Voltage Supervisory
PARAMETER
CONDITIONS
Voltage Monitor Low Thres. (assert reset)
Monitoring the voltage on V3P6
2.7
Voltage Monitor High Thres. (de-assert reset)
Monitoring the voltage on V3P6
3.0
Brownout bandwidth
Monitoring the voltage on V3P6
100
kHz
2.2
Reset Threshold (assert)
Reset Threshold (de-assert)
RESETN Minimum Time
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
0.1uF external capacitor
14
MIN
TYP
MAX
UNIT
1.1
11
ms
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AV6301 Datasheet (Preliminary)
revision 0.2
3.4 Electrical Characteristics – RF Receiver
Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0ºC to +70 ºC; RF Channel Freq = 2403.35-2477.35MHz, measured at
the single-ended input of the RF balun (with external impedance matching). Typical specifications at TA = 25ºC, VDC = 5.0V.
Table 3-4 AV6301 Electrical Characteristics - RF Receiver
PARAMETER
CONDITIONS
RF Channel Frequency Range
LO frequency (driving the mixers)
RF carrier frequency
MIN
TYP
2402
2403.35
Modulated Signal Offset from LO
MAX
UNIT
2478
2479.35
MHz
MHz
1.35
MHz
Sensitivity (Note 1)
TA=25ºC, LNA = High gain mode; max IF gain
-89
dBm
Max input signal (desired signal) (Note 1)
TA=25ºC, LNA = low gain mode; min IF gain
-5
dBm
Input Blocker Level – High Gain mode
> 2MHz offset
-45
dBm
Out-of-band blocker level
<2400 MHz; >2483.5 MHz
TBD
dBm
Spurious RF outputs
<2400 MHz
>2483.5 MHz
-75
-75
dBm
dBm
Note 1:
Sensitivity and max signal level are defined as the onset of 0.2% Block Error Rate. )BLER)
3.5 Electrical Characteristics – RF Transmitter
Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0ºC to +70 ºC; RF Channel Freq = 2403.35-2477.35MHz, measured at
the single-ended input of the RF balun (with external impedance matching). Typical specifications at TA = 25ºC, VDC = 5.0V.
Table 3-5 AV6301 Electrical Characteristics - RF Transmitter
PARAMETER
CONDITIONS
MIN
RF Channel Frequency Range
LO frequency (driving the mixers)
RF carrier frequency
TYP
2402
2403.35
Modulated Signal Offset from LO
MAX
UNIT
2478
2479.35
MHz
MHz
1.35
MHz
Modulated Signal Bandwidth
-10dB point
1.8
MHz
Output Power
Pi/4 DQPSK modulated signal
ACPR: Adj < -23dBc, Alt < -30dBc
+2
dBm
Output harmonics
2 harmonic, Pout = 0dBm
rd
3 harmonic, Pout = 0dBm
-52
-50
dBm
dBm
Out-of-band Spurious Output
RF < 2390MHz, > 2483.5MHz, 1MHz RBW
<-62
dBm
Output Noise Floor
RF < 2390MHz, > 2483.5MHz, 1MHz RBW
<-62
dBm
nd
3.6 Electrical Characteristics – End-to-end Audio Characteristics
Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0ºC to +70 ºC; Typical specifications at TA = 25ºC,
VDC = 5.0V.
Table 3-6 AV6301 Electrical Characteristics - End-to-End Audio Characteristics
PARAMETER
CONDITIONS
SNR
Forward stereo path
93
dB
Reverse mono path
68
dB
End-to-end audio BW; 0.1dB point
20
kHz
End-to-end audio BW; 0.1dB point
6.5
kHz
Audio Latency
AV6201 USB to AV6202 analog output
AV6201 I2S to AV6202 I2S output
<16
<16
msec
msec
Voice Latency
AV6202 analog input to AV6201 USB output
<16
msec
Audio/Voice Bandwidth
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
MIN
15
TYP
MAX
UNITS
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AV6301 Datasheet (Preliminary)
revision 0.2
4 PACKAGE INFORMATION
4.1
Package Outline Drawing
Figure 4-1 AV6301 48 Pin QFN Outline Drawing
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
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AV6301 Datasheet (Preliminary)
4.2
revision 0.2
Package Marking
Figure 4-2 Package Marking Layout
Abbreviations:
AVDDDD
Product number (i.e. AV6301)
CC
Country Code (i.e. MY for Malaysia)
YY
2 digit year code
WW
2 digit work week
XX
Production revision
LLLLLL
Silicon Lot number
TT
Wafer split (1 by default)
Assembly Lot
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AV6301 Datasheet (Preliminary)
revision 0.2
5 CONTACT INFO & LEGAL DISCLAIMER
Avnera Corporation
16505 Bethany Court, Suite 100
Beaverton, Oregon 97006
U.S.A.
Main: +1.503.718.4100
Fax: +1.503.718.4101
www.avnera.com
Avnera Corporation reserves the right to make changes without notice to the product to improve function, reliability, or
performance.
Avnera Corporation does not assume any liability arising from the application or use of the products or circuits described
herein.
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE
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