Sequans Communications VZM20Q VZM20Q User Manual VZM20Q Module Integration Guide Revision 1

Sequans Communications VZM20Q VZM20Q Module Integration Guide Revision 1

Contents

Module integration guide

Sequans Module VZM20QModule Integration GuideSEQUANS Communications15-55, Boulevard Charles de Gaulle92700 Colombes, FrancePhone. +33.1.70.72.16.00Fax. +33.1.70.72.16.09www.sequans.comcontact@sequans.com
MODULE INTEGRATION GUIDE PROPRIETARY iSEQUANS CommunicationsPrefaceLegal NoticesCopyright© 2016, SEQUANS CommunicationsAll information contained herein and disclosed by this document is confidential and the proprietary property of SEQUANS Communications, and all rights therein are expressly reserved. Acceptance of this material signifies agreement by the recipient that the information contained in this document is confidential and that it will be used solely for the purposes set forth herein. Acceptance of this material signifies agreement by the recipient that it will not be used, reproduced in whole or in part, disclosed, distributed, or conveyed to others in any manner or by any means – graphic, electronic, or mechanical, including photocopying, recording, taping, or information storage and retrieval systems – without the express written permission of SEQUANS Communications.All Sequans’ logos and trademarks are the property of SEQUANS Communications. Unauthorized usage is strictly prohibited without the express written permission of SEQUANS Communications. All other company and product names may be trademarks or registered trademarks of their respective owners. Products and services of SEQUANS Communications, and those of its licensees may be protected by one or more pending or issued U.S. or foreign patents.Because of continuing developments and improvements in design, manufacturing, and deployment, material in this document is subject to change without notification and does not represent any commitment or obligation on the part of SEQUANS Communications. SEQUANS Communications shall have no liability for any error or damages resulting from the use of this document.
ii PROPRIETARY MODULE INTEGRATION GUIDESEQUANS CommunicationsDocument Revision HistoryRevision Date Product Application01 November 2016 First edition of the VZM20Q Module Integration Guide.
MODULE INTEGRATION GUIDE PROPRIETARY iiiSEQUANS CommunicationsAbout this GuidePurpose and ScopeThis Application note is intended to help customers who want to deviate from the Sequans’ Reference Designs to successfully integrate and test their product based on module.It presents Integration Guidelines for:• All VZM20Q Interface Requirements• Tips and “how-to”s for troubleshootingDevelopment of the Hardware should follow a process that ensures the solution will be optimum and it is the purpose / goal of this document to reach this. For this to occur it is recommended that these processes are followed in order. This document is delivered as three sections:1. System Overview2. Hardware and software design guidelines3. Bring-up verification and testCaution: It is highly recommended that Sequans support teams are involved during all processes to ensure the very best can be achieved for the alternative design.Who Should Read this DocumentThis Application Note is for hardware designers of user applications based on Sequans VZM20Q Module.Important: Reference design source files are based on the application PADS® from Mentor Graphics® (www.mentor.com). Customers using the other CAD applications can use schematics translators and viewers, such as Elgris® (www.elgris.com). Such translators may save time and prevent mistakes during manual PADs conversion.
iv PROPRIETARY MODULE INTEGRATION GUIDESEQUANS CommunicationsReference Documentation1. DV Tool User Guide2. Sequans Hardware Platform User Guide3. mTools Reference Manual4. Nimbelink™ Evaluation Kit User ManualSee http://nimbelink.com/Changes in this DocumentThis is the first edition of the document.
MODULE INTEGRATION GUIDE PROPRIETARY vSEQUANS CommunicationsDocumentation ConventionsThis section illustrates the conventions that are used in this document.General ConventionsNote Important information requiring the user’s attention.Caution A condition or circumstance that may cause damage to the equipment or loss of data.Warning A condition or circumstance that may cause personal injury.Italics Italic font style denotes• emphasis of an important word;• first use of a new term;• title of a document.Screen Name Sans serif, bold font denotes• on-screen name of a window, dialog box or field;• keys on a keyboard;• labels printed on the equipment.Software ConventionsCode Regular Courier font denotes code or text displayed on-screen.Code Bold Courier font denotes commands and parameters that you enter exactly as shown. Multiple parameters are grouped in brackets [ ]. If you are to choose only one among grouped parameters, the choices are separated with a pipe: [parm1 | parm2 | parm3] If there is no pipe separator, you must enter each parameter: [parm1 parm2 parm3]Code Italic Courier font denotes parameters that require you to enter a value or variable. Multiple parameters are grouped in brackets [ ]. If you are to choose only one among grouped parameters, the choices are separated with a pipe: [parm1 | parm2 | parm3] If there is no pipe separator, you must enter a value for each parameter: [parm1 parm2 parm3]
Proprietary viSEQUANS CommunicationsTable of ContentsPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iLegal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iDocument Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiAbout this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiPurpose and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiWho Should Read this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiReference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ivChanges in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ivDocumentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vChapter 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Recommended Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.1 Design Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.2 Schematics Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.3 PCB Placement and Layout Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.4 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.5 Functional Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.6 Manufacturing Recommended Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Chapter 2Manufacturing Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Manufacturing Process Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Module Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Chapter 3Hardware Integration Recommendations . . . . . . . . . . . . . . . . . . . 63.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1.1 Synthesis of the Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1.2 Power Supply Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1.3 Module Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.2 SIM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.2.1 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.2.2 Other Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.2.3 Software-Configurable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3 Host Communications Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table of ContentsProprietary viiSEQUANS Communications3.3.1 Introduction to UART Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3.2 General Notes on UART Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3.3 UART0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3.4 UART1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3.5 UART2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4 RF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4.1 RF Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4.2 Circuit Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.4.3 Test Points and Measurement Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.4.4 Antennas and RF Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.5 Reset and Environmental Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.6 GPIO Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.6.1 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.6.2 Software Configurable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Chapter 4PCB Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.1 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.2 Trace Characteristic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.2.1 Digital Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.2.2 Power Supply Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.2.3 RF Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.2.4 Controlled Impedance Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.2.5 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Chapter 5Bring-Up and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.2 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.3 Functional Verification without Assembled Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285.3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285.3.2 RF Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.4 Functional Verification with Assembled Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.4.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.4.2 Confirm Module Power-Up Operation (UART1) . . . . . . . . . . . . . . . . . . . . . . . . . . 325.4.3 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.4.4 SIM Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345.5 LTE RF Performance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355.5.1 Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355.5.2 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365.5.3 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Appendix AHardware Test Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . 37A.1 RF Interfaces Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table of Contentsviii Proprietary MODULE INTEGRATION GUIDESEQUANS CommunicationsA.1.1 LTE RF Test Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Appendix BAbbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MODULE INTEGRATION GUIDE PROPRIETARY 1SEQUANS Communications1Introduction1.1 System ArchitectureFigure 1-1 provides an overview of the Host to VZM20Q interfacing relationship. The various interfaces are explained in detail later in this document.It provides summary details of:• Digital interfaces between the VZM20Q and the host platform• Power supply requirement (Vbat).Note: VBAT1 range is 3.1 V to 4.5 V.It does not show the VZM20Q local terminations.Figure 1-1: VZM20Q-Based System Architecture,K^dW>d&KZDsDϮϬYZ&ŽĂdž/&džZyͬdysdsϭͺWsϮͺWsdϭZ^dEDKh>ͺKE:d'^/DhZdϭ;KƉƚŝŽŶĂůͿDŽĚĞŵ/ŶƚĞƌĨĂĐĞ;hZdϬͿ'W/KϯsϬĞďƵŐ;hZdϮͿ;ĞďƵŐ͕DĂŶƵĨĂĐƚƵƌŝŶŐ͕ĐŽŶƐŽůĞ͕͙Ϳ
INTRODUCTIONSYSTEM ARCHITECTURE2PROPRIETARY MODULE INTEGRATION GUIDESEQUANS CommunicationsFigure 1-2: VZM20Q Mounted on Skywire™ 4G LTE CAT M1 Embedded ModemFigure 1-3: Skywire™ 4G LTE CAT M1 Embedded Modem - Bottom View
INTRODUCTIONRECOMMENDED DESIGN FLOWMODULE INTEGRATION GUIDE PROPRIETARY 3SEQUANS CommunicationsNote: The hardware design package of VZM20Q reference design is available from your Sequans local contact.1.2 Recommended Design FlowTo ensure that the customer benefits from the details of this document we recommend to carefully take the following information into account during the design process.1.2.1 Design ModificationsCompared to Nimbelink™ reference design, only the following modifications to the BOM are allowed to designers:• SIM connector•Level shifter on UARTs• Circuitry on RESETNNote: Any GNSS/GPS function is out of scope of VZM20Q Reference Design.Consultancy with Sequans is highly recommended to verify these alternate preferences.1.2.2 Schematics ReviewEnsuring that the circuit design by analysis will be compliant with the Sequans’ chipset. It is recommended that the review of the design includes Sequans’ technical support team.1.2.3 PCB Placement and Layout ReviewTo ensure the PCB layout is compliant, it is recommended that the review of this CAD activity includes Sequans at several iterative steps such as component placement, RF and digital routing, final layout levels etc. This might avoid later rework.
INTRODUCTIONRECOMMENDED DESIGN FLOW4PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications1.2.4 OptimizationWhen the design returns from the manufacture, it might occur that improvements have to be made to the circuits. It is also recommended to communicate such results to Sequans who can help to verify the implementation.1.2.5 Functional ValidationThe test of the design performance should be done in thorough detail. This will ensure the compliance with the test standard as the final design will be subjected to a formal qualification. It is the designer’s responsibility to meet this goal. Sharing the results with Sequans will help identify any particular problem that could be fixed at an early stage to ensure strong confidence of qualification. This should be done for all the tests that involve Sequans chipsets. Hardware Test Preparation on page 37 provides you with the hardware setup required to proceed with test phases.1.2.6 Manufacturing Recommended Process Manufacturing Process on page 5 provides information on the process required to achieve the manufacturing of your product.
MODULE INTEGRATION GUIDE PROPRIETARY 5SEQUANS Communications2Manufacturing Process2.1 Manufacturing Process OverviewNote: The contents of this section will be provided in a future revision of the document.2.2 Module UpgradeNote: The contents of this section will be provided in a future revision of the document.
MODULE INTEGRATION GUIDE PROPRIETARY 6SEQUANS Communications3Hardware Integration RecommendationsThis chapter provides the information necessary to understand the various interface requirements to interconnect with the VZM20Q, associated software-configurable items for the respective interface and, more generally, good practices for board design when considering the various interface types.Table 3-1 describes the requirements for trace characteristics.Important: Different signals require different special needs. Please consider carefully the interfacing requirement of each relevant connection.Table 3-1: Requirements Overview: Trace Characteristics Trace Characteristics DescriptionDigital Generic digital trace if reasonable high impedanceSupply Broader trace routing based on the power needs of the load50 Ohm Conventionally used for RF routing. Track must be retained to this impedanceQuiet Intention is to keep away from digital signals and as short as possible, possibly burying the signalGround Shortest VZM20Q Ground to Host Ground possible, best possible lowest impedance path
HARDWARE INTEGRATION RECOMMENDATIONSPOWER SUPPLYMODULE INTEGRATION GUIDE PROPRIETARY 7SEQUANS Communications3.1 Power Supply3.1.1 Synthesis of the Power SuppliesTable 3-2 and Table 3-3 provide a synthesis of the power supplies and their characteristics. Please see typical voltage values in VZM20Q Datasheet.Note: Each output reference voltage (pads 3, 9, 11) can be either running or powered off depending on the internal software configuration. They should not be used to power external IC or parts that require permanent supply.Table 3-2: Power Supply Signals Pin NamePinNumberTraceStyle Direction Notes1V8 3 Supply Out Reference voltage. See the note above.3V0 9,11 Supply Out To be only connected to VCC1_PA and VCC2_PA. These pads should not be used for any other usage. See the note above.GNSS_VCC1 100 Supply In Reserved. Do not connect.GNSS_VCC2 101 Supply Out Reserved. Do not connect.GNSS_VCC3 102 Supply In Reserved. Do not connect.VBAT1 107, 108 Supply In Voltage used for qualification is 3.8 V, range 3.1 V to 4.5 V VCC1_PA 97 Supply In To be connected to 3V0VCC2_PA 98, 99 Supply In To be connected to 3V0Table 3-3: Power Supply Digital Enable Signals Pin NamePinNumberTraceStyle DirectionTypical Voltage Ref NotesPOWER_EN 106 Digital In 1V8
HARDWARE INTEGRATION RECOMMENDATIONSSIM INTERFACE8PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.1.2 Power Supply Circuit Example3.1.2.1 Test Points and Measurement AccessTest point access is recommended on all supply nets so that the supply voltages can be measured.3.1.2.2 Special Layout ConsiderationsPLease refer to Section 4.2.2 Power Supply Traces on page 24.3.1.3 Module Operating ModeNote: The contents of this section will be provided in a future revision of the document.3.2 SIM Interface3.2.1 Interface DescriptionTable 3-4 lists the VZM20Q pins related to the SIM interface.Table 3-4: SIM Interface Signals Pin NamePin Number Trace Style DirectionElectrical CharacteristicsSIM_CLK 14 Digital Output from Module SIM_VCCSIM_DETECT11. SIM_DETECT=1 signals that a card is present. SIM_DETECT=0 signals that no card is present.16 Digital Input to Module 1V8SIM_IO 17 Digital Input or Output to/from Module SIM_VCCSIM_RESETN 12 Digital Output from Module SIM_VCCSIM_VCC 18 Digital Output from Module 1V8 or 3V0
HARDWARE INTEGRATION RECOMMENDATIONSHOST COMMUNICATIONS SIGNALSMODULE INTEGRATION GUIDE PROPRIETARY 9SEQUANS Communications3.2.2 Other Hardware Considerations• When considering the placement of the SIM connector and Monarch SIM interface, try to keep the distance between them as small as possible. This is to avoid supply trace inductance buildup which could cause unexpected SIM VCC supply drops under specific SIM control situations. If it is unavoidable, then be sure to add 4.7µF decoupling capacitor at the SIM connector itself to act as a charge reserve in help in such situations.• Please ensure that a good ground return exists between the SIM card and the VZM20Q.• If the application requires the support of the hot insertion or removal of SIM card, then the SIM card handler must include a removal/insertion pad detector in order to allow the software to process the event immediately.• The software support of the “hot removal” feature is not currently avail-able. Please contact your Sequans’ representative for details.3.2.3 Software-Configurable OptionsNote: The content of this section will be provided in a future revision of the document.3.3 Host Communications Signals3.3.1 Introduction to UART InterfacesThe communication between the VZM20Q and the host platform is supported as follows by 3 UART interfaces.• UART0 is dedicated to Host-Modem interface• UART1 is an optional additional Host-Modem interface. It is reserved for future use.• UART2 is reserved for debug usage and Sequans’ manufacturing and hard-ware qualification tools such as DMTool or DVTool.The following sections detail those interfaces.
HARDWARE INTEGRATION RECOMMENDATIONSHOST COMMUNICATIONS SIGNALS10 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.3.2 General Notes on UART ConnectionsVZM20Q uses the DCE-DTE convention for UART lines.The TXD output from the device at one end of the link connects to the RXD input at the other end of the link and vice versa. Figure 3-1 represents the typical implementation for the UART connection (including hardware flow control in case of high-speed UART).TXD and RXD signals are mandatory for all interfaces. The other signals are optional. Only UART0 interface supports all data transfer signals.The DCE (Data Communication Equipment) device will communicate with the customer application (DTE) using the following signals:• Port TXD on Application sends data to the VZM20Q's TXD signal line.• Port RXD on Application receives data from the VZM20Q's RXD signal line.Figure 3-1: UART0, UART1, UART2 Connection ImplementationsDϮdžY ƉƉůŝĐĂƚŝŽŶdyϬͬϭͬϮ dyZyϬͬϭͬϮ ZyZd^ϬͬϭͬϮ Zd^d^ϬͬϭͬϮ d^><ϬͬϭͬϮ ><dZϬ dZ^ZϬ ^ZϬ Z/E'Ϭ Z/E'
HARDWARE INTEGRATION RECOMMENDATIONSHOST COMMUNICATIONS SIGNALSMODULE INTEGRATION GUIDE PROPRIETARY 11SEQUANS Communications3.3.3 UART0 Interface3.3.3.1 Interface DescriptionImportant:• See the Section 3.3.2 General Notes on UART Connections on page 10 for usage of UART0.• If not used, the UART0 signals should be connected to test points.Table 3-4 lists the VZM20Q pins related to the UART0 interface.Table 3-5: UART Interface Signals Pin NamePin NumberTrace Style DirectionElectrical Characteristics NotesRXD0 79 Digital Out 1.8 V UART0 RXDTXD0 77 Digital In 1.8 V UART0 TXDRTS0 75 Digital In 1.8 V UART0 RTSCTS0 76 Digital Out 1.8 V UART0 CTSGPIO19/CLK0 7 Digital In/Out 1.8 V UART0 CLK optional signal multiplexed with GPIO19. Default setting is GPIO. GPIO41/DTR0 84 Digital In 1.8 V UART0 DTR optional signal multiplexed with GPIO41. Default setting is GPIO. GPIO39/DSR0 85 Digital Out 1.8 V UART0 DSR optional signal multiplexed with GPIO39. Default setting is GPIO. GPIO24/DCD0 88 Digital Out 1.8 V UART0 DCD optional signal multiplexed with GPIO24. Default setting is GPIO. GPIO25/RING0 89 Digital Out 1.8 V UART0 RING optional signal multiplexed with GPIO25. Default setting is GPIO.
HARDWARE INTEGRATION RECOMMENDATIONSHOST COMMUNICATIONS SIGNALS12 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.3.3.2 Default ConfigurationThe default software configuration of UART0 is AT Commands mode.The serial link settings are as follows:• Baud rate: 921600• Data: 8 bits•Parity: None• Stop : 1 bit• Flow control: Hardware (RTS/CTS)3.3.4 UART1 Interface3.3.4.1 Interface DescriptionImportant:• See the Section 3.3.2 General Notes on UART Connections on page 10 for usage of UART1.• If not used, the UART1 signals should be connected to test points.Table 3-6 lists the VZM20Q pins related to the UART1 interface.Table 3-6: UART1 Interface Signals Pin NamePin NumberTrace Style DirectionElectrical Characteristics NotesGPIO15/RXD1 80 Digital Out 1.8 V UART1 RXD optional signal multiplexed with GPIO15. Default setting is RXD1.GPIO14/TXD1 78 Digital In 1.8 V UART1 TXD optional signal multiplexed with GPIO14. Default setting is TXD1.GPIO16/RTS1 83 Digital In 1.8 V UART1 RTS optional signal multiplexed with GPIO16. Default setting is GPIO.GPIO17/CTS1 81 Digital Out 1.8 V UART1 CTS optional signal multiplexed with GPIO17. Default setting is GPIO.GPIO38/CLK1 82 Digital In/Out 1.8 V UART1 CLK optional signal multiplexed with GPIO38. Default setting is GPIO.
HARDWARE INTEGRATION RECOMMENDATIONSHOST COMMUNICATIONS SIGNALSMODULE INTEGRATION GUIDE PROPRIETARY 13SEQUANS Communications3.3.4.2 Default ConfigurationThe default software configuration of UART1 is console mode. Boot traces are sent on this interface as shown on Section 5.4.2 Confirm Module Power-Up Operation (UART1) on page 32.The serial link settings are as follows:• Baud rate: 115200• Data: 8 bits•Parity: None• Stop : 1 bit•Flow control: None3.3.5 UART2 Interface3.3.5.1 Interface DescriptionImportant:• See the Section 3.3.2 General Notes on UART Connections on page 10 for usage of UART2.• If not used, the UART2 signals should be connected to test points.Table 3-7 lists the VZM20Q pins related to the UART2 interface.Table 3-7: UART2 Interface Signals Pin NamePin NumberTrace Style DirectionElectrical Characteristics NotesRXD2 56 Digital Out 1.8 V UART2 RXD. TXD2 58 Digital In 1.8 V UART2 TXDGPIO28/RTS2 10 Digital In 1.8 V UART2 RTS optional signal multiplexed with GPIO28. Default setting is RTS.GPIO27/CTS2 8 Digital Out 1.8 V UART2 CTS optional signal multiplexed with GPIO27. Default setting is CTS.GPIO26/CLK2 91 Digital In/Out 1.8 V UART2 CLK optional signal multiplexed with GPIO26. Default setting is GPIO
HARDWARE INTEGRATION RECOMMENDATIONSHOST COMMUNICATIONS SIGNALS14 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.3.5.2 Default ConfigurationUART2 default software configuration allows firmware upload when the device is configured in FFH mode, then it switchs in debug mode (enabling DVTool, DMTool).The serial link settings are as follows:• Baud rate: 921600• Data: 8 bits•Parity: None• Stop : 1 bit• Flow control: Hardware (RTS/CTS)
HARDWARE INTEGRATION RECOMMENDATIONSRF INTERFACEMODULE INTEGRATION GUIDE PROPRIETARY 15SEQUANS Communications3.4 RF Interface3.4.1 RF Signals3.4.1.1 RF Interface Signals3.4.1.2 RF Control SignalsTable 3-8: RF Interface Signals Pin NamePinNumberTraceStyle DirectionElectricalCharacteristics NotesLTE_ANT0 54 RF In/Out RF LTE antenna. Special RF routing conditionsGNSS_ANT1 44 Reserved Reserved. Do not connect.Table 3-9: RF Control Signals Pin NamePinNumberTraceStyle DirectionElectricalCharacteristics NotesRFDATA12 39 Digital In/Out Reserved.RFDATA16 40 Digital In/Out Reserved.RFDATA17 41 Digital In/Out Reserved.
HARDWARE INTEGRATION RECOMMENDATIONSRF INTERFACE16 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.4.2 Circuit Diagram ExampleImportant: Figure 3-4 should be strictly followed as a topology reference. It is recommended not to deviate from this circuit from your applica-tion. More information is provided in this document on the layout constraint which are too very important to abide by.The RF inter-connect called P1 is for example purposes only. Depending on the antenna, interfacing system will dictate the RF inter-connect.Figure 3-2: RF Typical CircuitLTE_ANT0 is the primary (main) antenna pin and carries TX and RX signals.Connect 50 Ohm transmission lines from this pins to the 50 Ohm Primary Antenna/Antenna-connector.Figure 3-2 shows, included in the connection between ANT and the antenna connectors, T-type network for matching.See Section 3.4.4 Antennas and RF Design Considerations on page 17 for more detail on connecting to these pins and for information on the T-type matching network and ESD protection.
HARDWARE INTEGRATION RECOMMENDATIONSRF INTERFACEMODULE INTEGRATION GUIDE PROPRIETARY 17SEQUANS Communications3.4.3 Test Points and Measurement Access50 Ohm termination points, for example P1 in Figure 3-2, are needed for Engineering and Production teams for the validation of the RF performance.The potential need to optimize the Pi-type matching network in the antenna path means that access to the IOs of this matching network is needed, so that a coaxial cable (usually 1.25mm diameter semi-rigid) can be manually attached for precision impedance measurements. Critically, a sufficient area of GND metal on the top layer adjacent to these matching networks and well-grounded to the transmission line reference GND is needed to permit robust physical attachment of the coaxial cable and with short GND connection. This area of GND metal does not need any resist removal as this can be removed manually where needed.Please refer to Section 3.4.4 Antennas and RF Design Considerations on page 17 for more detail on managing RF Trace Design.3.4.4 Antennas and RF Design ConsiderationsAntennas require special interfacing for optimum RX and TX Performance.3.4.4.1 T-Type MatchingA 3-component T-type matching network is recommended to be fitted. The purpose of the T-type matching network is to transform the impedance of the RF-path that extends beyond to 50 Ohm if needed. The 3 components in this matching network should be as close together as possible to minimise the interconnecting track lengths.By default the component pads should be for a 0201-size capacitor which can be a No Fit by default. There should be a short low-impedance connection connecting the GND node of this component.The series matching element should be connected at the junction where first shunt component and by default a 0 Ohm 0201-size resistor should be fitted but if matching is needed the pads needs to be able to take 0201-size inductor;The final shunt matching element should be connected from the node where the series matching component ends to the signal ground connection. By default the component pads should be for a 0201-size capacitor which can be a No Fit by default. There should be a short low-impedance connection connecting the GND node of this component to the GND node of the first shunt component. There should be a short low-impedance connection connecting the GND node of this component to the GND reference of the 50 Ohm transmission line that continues beyond to the Antenna/Antenna-connector.
HARDWARE INTEGRATION RECOMMENDATIONSRF INTERFACE18 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.4.4.2 ESD ProtectionESD protection is a discretionary requirement and only required if necessary, for higher ESD specifications than those provided by the VZM20Q.It is recommended to select an ESD device with very low capacitance and small size (0201) to prevent further RF matching compensation.3.4.4.3 Standard Impedance Transmission LinesThere are 2 possible methods to design 50 Ohm transmission lines:1. With the RF track on the outer metal layer both micro-strip and coplanar types can be implemented.2. With the RF track on an inner metal layer embedded micro-strip and strip-line topologies can be used.Irrespective of which one is selected the following guidelines are recommended:• Design the transmission line tracks appropriately wide to minimise the RF insertion loss between the Antenna/Antenna-connector and VZM20Q. The maximum insertion loss of the conducted path should be < 0.5dB• Transmission lines EM fields will couple to adjacent metal layers.For microstrip implementation, make sure that a minimum of twice the spacing exists between transmission-line and associated GND. This clear-ance to adjacent metal layers will ensure that the designed transmission line impedance is not impacted.For co-planar design, the spacing helps to define the controlled impedance. Take special care to make the calculations correctly.Whether these are microstrip or co-planar designed transmission lines, make sure that the adjacent metal GND areas are connected to the GND reference plane using periodic via connections, as to effectively terminate these leakage EM fields.
HARDWARE INTEGRATION RECOMMENDATIONSRF INTERFACEMODULE INTEGRATION GUIDE PROPRIETARY 19SEQUANS CommunicationsFigure 3-3: Transmission Line Implementation ExamplesFigure 3-3 provides examples of both transmission line implementations, specifically showing:a) The clearance from the transmission line to adjacent metal on layer 1.b) The periodic via connections connecting metal-1 layer through to the reference GND layer for the transmission line.• Avoid routing of noisy signal tracks adjacent to RF transmission lines to minimize interference coupling into VZM20Q RF ports.• The component pads for the SMD terminals of the matching components used in the 3-component T-type matching circuit are effectively very short transmission lines. To minimise the RF insertion loss caused by the discon-tinuity in width differences, the ideal width of the 50 Ohm track should be as close as possible to the width of the component pads.• If connectors are used in-line on antenna paths design the PCB interface tracking and cut-out carefully to these connectors to keep the transmission line impedance to 50 Ohm.
HARDWARE INTEGRATION RECOMMENDATIONSRESET AND ENVIRONMENTAL SIGNALS20 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.5 Reset and Environmental SignalsTable 3-10 lists the Reset and other environmental signals and the following subsections describe their purpose and termination requirements.Table 3-10: Non-Interfacing Signals Pin NamePin Number DirectionElectrical Characteristics NotesRESETN 47 Out 1V8GPIO3/STATUS_LED 2 In/Out 1V8 - GPIO - Optional STATUS_LED. Note that the LED function is currently not available.RESERVED/FFF_FFH 5 In 1V8 Reserved pad: it must be PU & connected to a Test Point.ADC 57 In An external switch should be connected to the AuxADC pins to prevent current leakage in low power modes.WAKE0 104 InWAKE1 96 In/OutJTAG_TDO 48 Out JTAG interface, should be connected to a test point.JTAG_TRSTN 49 In JTAG interface, should be connected to a test point.JTAG_TMS 50 In JTAG interface, should be connected to a test point.JTAG_TDI 51 In JTAG interface, should be connected to a test point.JTAG_TCK 52 In JTAG interface, should be connected to a test point.
HARDWARE INTEGRATION RECOMMENDATIONSGPIO CONTROL INTERFACEMODULE INTEGRATION GUIDE PROPRIETARY 21SEQUANS Communications3.6 GPIO Control Interface3.6.1 Interface DescriptionSeveral general purpose IOs are available:Table 3-11: GPIOs Signals Pin Name Pin Number DirectionElectrical Characteristics NotesGPIO14/TXD1 78 In/Out 1V8 UART1 TXD (Input) alternate function to GPIO. See Section UART1 Interface.GPIO15/RXD1 80 In/Out 1V8 UART1 RXD (Output) alternate function to GPIO. See Section UART1 Interface.GPIO17/CTS1 81 In/Out 1V8 Optional UART1 CTS (Output) alternate function to GPIO. See Section UART1 Interface.GPIO38/CLK1 82 In/Out 1V8 Optional UART1 CLK (I/O) alternate function to GPIO. See Section UART1 Interface.GPIO16/RTS1 83 In/Out 1V8 Optional UART1 RTS (Input) alternate function to GPIO. See Section UART1 Interface.GPIO41/DTR0 84 In/Out 1V8 Optional UART0 DTR (Input) alternate function to GPIO. See Section UART0 Interface.GPIO39/DSR0 85 In/Out 1V8 Optional UART0 DSR (Output) alternate function to GPIO. See Section UART0 Interface.GPIO24/DCD0 88 In/Out 1V8 Optional UART0 DCD (Output) alternate function to GPIO. See Section UART0 Interface.GPIO25/RING0 89 In/Out 1V8 Optional UART0 RING (Output) alternate function to GPIO. See Section UART0 Interface.
HARDWARE INTEGRATION RECOMMENDATIONSGPIO CONTROL INTERFACE22 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3.6.2 Software Configurable OptionsNote: The content of this section will be provided in a future revision of the document.GPIO40/POWER_SHDN 90 In/Out 1V8 GPIO, emergency power shutdown signal (Input) in option. In emergency powershutdown mode, 1 kOhm PU needed, pin should be forced low level to trigger emergency shutdown procedure. Note that this feature is currently not available.GPIO2/POWER_MON 6 In/Out 1V8 GPIO or Power monitor (Output) in option.POWER_MON is high right after POWER_ON, then remains high until shutdown procedure is completed. Module can be safely electrically power off as soon as POWER_MON goes low. Note that this feature is currently not available.GPIO26/CLK2 91 In/Out 1V8 Optional UART2 CLK (I/O) alternate function to GPIO. See Section UART2 Interface.GPIO21 95 In/Out 1V8GPIO23 93 In/Out 1V8GPIO29/32KHZ_CLK_OUT 103 In/Out 1V8 Optional 32 kHz (Output)GPIO42/SAR_DETECT 105 In/Out 1V8 GPIO, SAR detection signal (Input, active low) in option. In this SAR detection mode, 1 kOhm PU needed. Note that this feature is currently not available.Table 3-11: GPIOs Signals (Continued)Pin Name Pin Number DirectionElectrical Characteristics Notes
MODULE INTEGRATION GUIDE PROPRIETARY 23SEQUANS Communications4PCB Layout RulesThis section provides general good practices in defining a PCB layout.4.1 PlacementIt is good to perform the placement of all the major components blocks before routing any section of the PCB design. The considerations here are:• VZM20Q module•RF interfaceInitial placement of these parts allows assessment of the PCB floor plan usage and avoids any significant changes to final routed areas of the design if a placement issue is found. This also provides an opportunity for Sequans to review the placement.The following information presents considerations when performing this placement:1. Keep them in a similar quadrant to interface they connect to.2. Consider orientation to avoid crossing traces when routing3. Keep them as close as possible to the VZM20Q module where possible.Note: You can consider keeping 4mm from the perimeter of the module for component placement to allow possible update of alternative Sequans' module solution such as US130Q.
PCB LAYOUT RULESTRACE CHARACTERISTIC DESIGN24 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications4.2 Trace Characteristic DesignThis section explains some standard design rules when considering different types of signals involved (digital, power supply, RF).4.2.1 Digital Traces1. Careful and logical placement of digital signals are required to ensure sepa-ration of digital interference between each other and unrelated traces.2. Consider the flow of ground currents during routing. Make sure that the grounding surrounding the traces (from source to load) remains contin-uous, with no cut or breaks. This will avoid long convoluted ground return currents which can create EMI-type problems.3. Ensure the steps provided in Section Controlled Impedance Traces are taken into account for digital traces requiring specific impedance.4. For those with no impedance requirements, be practical with the trace thickness. Keep them thin to avoid a buildup of capacitance, but make sure they are suitable to manufacture.5. If routing traces on alternate layers, avoid paralleling them and keep them orthogonal. Good practice is to run traces on alternative layer from vertical to horizontal and so forth. This avoid traces directly coupling.6. Important recommendation related to SIM connector placement can be found in Section 3.2.2 Other Hardware Considerations on page 9.4.2.2 Power Supply Traces1. Size the power supply traces appropriately for low impedance source. Pay attention to the number of vias used when routing traces across multiple layers. This is especially true for high current signals such as PA supply voltage.2. For each power supply output, the decoupling capacitors ground pad must be connected to ground return of the power supply source.3. Make sure that the digital traces remain well away from the power supply traces.4. Appropriate dimensioning of the width and length of each supply track and the number of any interlayer connecting vias is needed to minimize the resistive losses in each supply track.
PCB LAYOUT RULESTRACE CHARACTERISTIC DESIGNMODULE INTEGRATION GUIDE PROPRIETARY 25SEQUANS Communications4.2.3 RF Traces1. Avoid burying these traces as much as possible, because it increases RF losses compared with routing on the top.2. Keep as short as possible to help reduce RF losses.3. Design the impedance of the trace keeping in mind that the footprint of the RF components should be of similar width. This help avoid impedance discontinuities.4. Ensure the steps provided in Section Controlled Impedance Traces are taken into account when making the trace width.4.2.4 Controlled Impedance Traces• Calculation of traces width and spacing:Use simple RF design tools to calculate the copper trace thicknesses based upon:a) Thickness of the dielectric substrate that is used between the RF copper trace and the ground planeb) Spacing between the copper trace and the adjacent ground plane (on the same layer)c) Dielectric constant of the substrate material being used for manufac-ture. It happens that the required trace width is impossible to manufac-ture. It must be reconsidered until feasible. In this case, consider implementation of one of the following:- Thicker substrate- Moving the ground plane reference to the next layer down by removing the ground plane under the transmission line of interest• General good practice guidelinesa) Careful placement is required to keep RF traces short and kink-free.b) Do not route RF traces on intermediate layers.c) Ground planes beneath RF traces should be continuous.d) The ground fill around RF traces should have sufficient clearance to maintain the desired impedance.• RF matching component footprintsDepending on the substrate thickness and the size of the components pads used can deviate the desired transmission impedance from the wanted (nominally 50 Ohm).For RF devices, if any copper pad in relation to RF signals is significantly larger than the transmission line width, then the ground reference could be moved to the next layer down.
PCB LAYOUT RULESTRACE CHARACTERISTIC DESIGN26 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications4.2.5 Grounding1. Stitch ground areas together with vias where flooded ground remains unterminated.2. Stitch ground areas together in general to keep common ground imped-ance the same across the region.3. RF ground planes should be as large and continuous as possible and not be cut into small islands. Check that strings of vias do not inadvertently create slots in ground or power planes.
MODULE INTEGRATION GUIDE PROPRIETARY 27SEQUANS Communications5Bring-Up and Testing5.1 IntroductionThe purpose of this chapter is to describe what has to be done for board bring-up, test and qualification.The expectations at this stage of the product’s life are:1. Consider any inconsistent and potentially hazardous manufacturing faults to be eliminated.2. Confirm that it is safe to proceed to further detailed calibration and measurement steps.3. Evaluate board performances.5.2 PrerequisitesThe following lists the necessary tools to perform all aspects of the Hardware Qualification.1. Device under testa) Without VZM20Q assembled:- to check RF extra loss between the VZM20Q RF ports and product RF output- to perform sanity check of connection with VZM20Q- for debugging if necessaryb) With VZM20Q assembled: to do hardware qualification2. External Host PC / Laptop for UART interfaceNote: Detailed information will be provided in a future revision of this document.
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITHOUT ASSEMBLED MODULE28 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications3. LTE RF test equipments Setupa) Shielding box to avoid any RF performances results degradation due to environmentb) RF components such as: cable, splitter, 50 Ohm loads corresponding to the RF working band4. Power supply with current measuring ability5.3 Functional Verification without Assembled ModuleAttention: If a fault is discovered, consider the impact of the issue observed on all the manufactured samples.The purpose of this section is to establish a sanity check of the board before soldering the module, in order to avoid any damage due to a manufacturing issue.This test covers VBAT power supply.5.3.1 Power Supply5.3.1.1 Test ProcedureFigure 5-1 presents the equipment necessary to perform the next following test steps and the required configuration for test.Figure 5-1: Pre-Test Configuration (No Module on Board)
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITHOUT ASSEMBLED MODULEMODULE INTEGRATION GUIDE PROPRIETARY 29SEQUANS Communications• Test voltage valuesTest the DC nature of the voltage with an oscilloscope before connecting the DUT. Once the DC source is confirmed, you can power the DUT and measure accurately the test points voltage with a multimeter. At this stage, only VBAT1 can be tested.Check at each voltage test point, as illustrated on Figure 5-2, that the voltage value corresponds to what is expected. The values must be in the range specified in the VZM20Q Datasheet, section Electrical Operating Condi-tions.Figure 5-2: Measuring Voltage Value (VZM20Q)5.3.1.2 Troubleshooting• One power supply is incorrect– If the voltage is zero for one or more supply outputs- Check any resistor link to detect unexpected shunts or open circuits.– If the voltage is incorrect for one of more supply outputs- Check any resistor link to detect unexpected shunts or open circuits.dWϭsϴsDϮϬYϬZϬZϬZsϭͺWsϮͺWsdϭsddWdWdW'EϬZϯsϬ
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITHOUT ASSEMBLED MODULE30 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications5.3.2 RF Path5.3.2.1 Test ProcedureImportant: Those tests should be run or supervised by engineers with RF measurement preparation and test experience.• RF path checkTo avoid any issue on RF extra path (from the VZM20Q module antenna output to the board antenna connector), the purpose of this part is to check its integrity. It corresponds to losses between VZM20Q pin 54 and/or pin 44 and the antenna ports of the board.Figure 5-3 provides an overview of the equipment configuration for this test. The connection to the block RF is a connection to the VZM20Q pin 54, using an RF soldered coaxial probe and RF cable connected to the SMA RF connector.Figure 5-3: RF Path Check Setupa) Measure and record the insertion loss on LTE band 4 and LTE band 13 for the first antenna from pin 54 of the VZM20Q to LTE port antennab) By design, the extra RF path loss must be lower than 0.5 dB, to assume having good RF performances.5.3.2.2 Troubleshooting• In case of unexpected RF lossesa) Ensure that the assembly of the coaxial connectors are correct :- No dry joints.- The right way round.b) Ensure that the soldered SMA is not short circuit or open circuit- Test with digital voltmeter.c) Verify the RF equipment calibration, including coaxial cable used to connect to the VZM20Q pin and RF cabled) Verify that the RF matching is good
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITH ASSEMBLED MODULEMODULE INTEGRATION GUIDE PROPRIETARY 31SEQUANS Communications5.4 Functional Verification with Assem-bled ModuleAttention: If a fault is discovered, consider the impact of the issue observed on all manufactured samples.The purpose of this section is to validate the assembly process of the module.This test covers:1. VZM20Q pins and features:a) Power supplyb) UART1 console output during power-up operationc) SIM Interfaced) GPIOs2. Nominal power consumption3. VZM20Q boot 5.4.1 Power Supply5.4.1.1 Procedure1. Turn on the device under test in FFH mode.2. Confirm voltages of the power supplies remain the same before VZM20Q is assembled.Caution: If, at this point, the voltages are incorrect, stop immediately to diagnose the cause of the issue.3. Confirm that the current is nominal from the internal power supplyObserve the current drawn and ensure it is in line with the expected one.a) Expected VZM20Q current with no firmware loaded will be provided in a future revision of this document.
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITH ASSEMBLED MODULE32 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications5.4.1.2 Troubleshooting• Excessive current drawCheck all VZM20Q voltage supplies. Confirm that there is no VZM20Q supply short circuits. Voltage should read according to the nominal requirement.• No current draw or current less than expecteda) Check the external power supply wiringb) Check for dry joint between VZM20Q pin(s) and the power supply source.5.4.2 Confirm Module Power-Up Operation (UART1)An example of the output on UART1 console is provided below (boot in FFH mode):[0000000000] RBGerbil 11.5@26553 '5.0.0.0 [26553]'[0000000004] Reset cause 'EXT'(real 'EXT' ) (bootWDG : '0') [rawRst '0x00000001'][0000000011] regConfig 0xEF317ABF@1[0000000014] Running sector 0x1C040000[0000000018] boot: Current flash, timeout 10000, proto thp[0000000023] FFH forced.[0000000025] boot: Switched to uart1, timeout 60000, proto at[0000000031] uart: using uart1 with baudrate 921600[0000000035] [AT] Info: Forcing baudrate to 115200 for AT negociation
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITH ASSEMBLED MODULEMODULE INTEGRATION GUIDE PROPRIETARY 33SEQUANS Communications5.4.3 GPIOs5.4.3.1 ProcedureThis section helps to confirm a GPIO’s behavior.Use the mTools command AT+SMGT.The first 32-bits triplet of parameters is a bitmask to address the GPIO, the second 32-bits triplet of parameters is the bitmask of the value to drive on the GPIO, and the third 32-bits triplet provides the expected polarity setting for the GPIO. Refer to mTools Reference Manual for more detail on this command.The following command tests SQN3330_GPIO_22 (GPIO[22]) setting to 1, active high. Value 22 is represented by bitmask 0x400000, coded as triplet 0,0,0x400000.AT+SMGT=0,0,0x400000,0,0,0x400000,0,0,0The following command tests SQN3330_GPIO_38 (GPIO[38]) setting to 1, active low. Value 38 is represented by bitmask 0x4000000000, coded as triplet 0,0x40,0.AT+SMGT=0,0x40,0,0,0x40,0,0,0x40,0Test the expected behavior as needed by your implementation.5.4.3.2 Troubleshooting• Unexpected AT command errorMake sure that the version of Firmware used is the correct version.• Unexpected GPIO behavior– Ensure that there exists no short or open circuit between the test point and the VZM20Q.
BRING-UP AND TESTINGFUNCTIONAL VERIFICATION WITH ASSEMBLED MODULE34 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications5.4.4 SIM Communication5.4.4.1 ProcedureConfirmation of SIM behavior:Insert the following command to verify the SIM is working properly.Send AT commands <AT+SMST?>, as described in mTools Reference Manual.Response will display +SMST=<status>, where <status> can be:OK: Test completed with a positive status.NO SIM: No SIM card was detected.NOK: Test completed and detected a problem.5.4.4.2 Troubleshooting• Unexpected AT command errorMake sure that the version of Firmware used is the correct version.• Unexpected SIM behavior– Check all the connections between the SIM housing and the VZM20Q module are done according to Section 3.2 SIM Interface on page 8.– Ensure that there exists no short or open circuit between the SIM housing and the VZM20Q.
BRING-UP AND TESTINGLTE RF PERFORMANCE TESTMODULE INTEGRATION GUIDE PROPRIETARY 35SEQUANS Communications5.5 LTE RF Performance TestThe purpose of this part is to check LTE RF performances of module in non-signaling mode. This test allows validation of TX and RX path using mTools firmware. For this part, the board has to be used in FFH mode.5.5.1 Test ConfigurationThe test configuration is as follows:Figure 5-4: RF Performance Test Configuration1. VZM20Q UART2 connection routed to an External PC/Laptop running:a) VZM20Q mTools firmware (already validated with Sequans Reference DUT)b) Sequans DVTool (already validated with LTE RF test Equipment)2. RF connection via coaxial cable to the coaxial test points of the VZM20Q and LTE RF Test Equipment3. The board is configured in FFH mode by configuring FFF_FFH level.sdŽŽů,ŽƐƚƉƉůŝĐĂƚŝŽŶ^ĞƋƵĂŶƐĚƌŝǀĞƌ^ĞƌǀŝĐĞŶĂůLJnjĞƌ'ĞŶĞƌĂƚŽƌ^ƉůŝƚƚĞƌhd^ĞƋƵĂŶƐ͛DŽĚƵůĞhZdϮ
BRING-UP AND TESTINGLTE RF PERFORMANCE TEST36 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS Communications5.5.2 Procedure1. Apply the power from the local Host to the VZM20Q.2. Launch DVTool on UART2. Guidelines for using DVTool can be found in document 4G-EZ DV Tool User Manual.a) Ensure that the external RF losses from VZM20Q to MXA / MXG are configured into DVToolb) Perform the Rx and TX Screening3. Change DV Tool configuration so as to perform Rx test in each band at mid-frequency and mid input level (typically -60 dBm), and check the usual criteria on RSRP and CINR for RX.Notes:•DVTool contains a board suite of RF test tools to help validate the RF performance against the 3GPP test specification. It is highly recommended that once the screening is validated a full DVTool test campaign is performed for both RF bands. This should include releasing such results to Sequans for qualification.• Final product pre-conformance test at a reputable test facility to test stan-dards TS 36.521-1 & 36.521-2 is further recommended in advance of final conformance test requirements. Releasing results to Sequans for checking is also highly recommended.5.5.3 TroubleshootingNote: The most frequent problems that can occur at this stage either can be solved with recommendations deduced from other sections in this document, or will be provided in a future edition of this docu-ment.
MODULE INTEGRATION GUIDE PROPRIETARY 37SEQUANS CommunicationsAHardware Test PreparationA.1 RF Interfaces PreparationA.1.1 LTE RF Test PreparationNote: The list of the test equipment compatible with the tests is to be found in Section 1.2 of 4G-EZ DV Tool User Manual.To ensure that the RF test platform will provide the most reliable interface for testing. The following setup is proposed when measuring RF characteristics of the VZM20Q System.The shield box cavity is configured as shown on Figure A-1:• The DUT is connected to the computer by UART2.• The DUT is also connected by one RF cable.
RF INTERFACES PREPARATION38 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS CommunicationsFigure A-1: Shield Box Cavity ViewFigure A-2 shows the required configuration for calibration and screening. It consists of:• 1 x ZN2PD2-50-S + power splitter if the signal analyzer and the signal generator are two distinct equipments. R&S® CMW500 for instance allows the use of a single bidirectional RF port and prevents the need of a power splitter.• 1 x RF cable to the MXA (if needed)• 1 x RF cable to the MXG (if needed)• 1 x RF cable to the DUT (in the shield box)
RF INTERFACES PREPARATIONMODULE INTEGRATION GUIDE PROPRIETARY 39SEQUANS CommunicationsFigure A-2: Configuration for Calibration and Screening
MODULE INTEGRATION GUIDE PROPRIETARY 40SEQUANS CommunicationsBAbbreviationsAC Alternate CurrentACLR Adjacent Channel Leakage RatioLTE_ANT0 Antenna 0 for LTEAT Command Modem-type commands prefixed with AT charactersATR Answer To Reset (SIM)BOM Bill Of MaterialcDRX Connected Discontinuous ReceptionCLI Command Line InterfaceCMOS Complementary Metal Oxide SemiconductorCOM Communication CPU Central Processing UnitCS Chip SelectdB decibelDC Direct CurrentDL DownlinkDRX Discontinuous ReceptionDUT Device Under TestDVM Digital VoltmeterDV Tool Diagnostic and Validation ToolEEPROM Electricaly Erasable Programable Read-Only Memory
MODULE INTEGRATION GUIDE PROPRIETARY 41SEQUANS CommunicationsEM ElectromagneticEMI Electromagnetic interferenceFFF Firmware From Flash module boot mode FFH Firmware From Host module boot mode FS File SystemFW FirmwareGND GroundGNSS Global Navigation Satellite System, such as GPS, GLONASS, IRNSS, BeiDou-2tf, or GALILEO.GPIO General Purpose Input/OutputGPS Global Positioning System (see GNSS)HW HardwareIC Integrated CircuitIMEI International Mobile Equipment IdentityIT InterruptLNA Low-Noise AmplifierLTE Long-Term Evolution. See also www.3gpp.org/.MAC Medium Access Control protocol layerMII Medim Independant InterfaceMIO Multiple Input/OutputMXA Signal AnalyzerMXG Signal GeneratorNIE Sequans’ internal format for data representationOBB Opaque Binary Blob file formatPA Power amplifierPC Personal ComputerPCB Printed Circuit Board
42 PROPRIETARY MODULE INTEGRATION GUIDESEQUANS CommunicationsPMIC Power Management Integrated CircuitPPS Protocol and Parameters Selection (SIM)PS Power SupplyPS-P Power supply state. See section Operating Modes.PS-PA Power supply state. See section Operating Modes.PSI Platform Specification InterfaceR Short notation for OhmRF Radio FrequencyRFIC Radio Frequency Integrated CircuitRX ReceptionS/N Serial NumberSIM Subscriber Identity ModuleSMA RF connector typeSMD Storage Module DeviceSPI Serial Peripheral InterfaceSW SoftwareTX Transmission or EmissionUART Universal Asynchronous Receiver TransmitterUE User EquipmentUL UplinkUSB Universal Serial BusUSIM Universal SIM. WP Write Protect

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