Silicon Image Silicondrive Cf Ssd C08Gi 3150 Users Manual

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DATA SHEET
SILICONDRIVE CF
SSD-CXXX(I)-3150
OVERVIEW

FEATURES

SiliconDrive
combines
all
the
high
performance, high reliability, and multiyear
lifecycle benefits of the standard SiliconDrive
with a comprehensive suite of patented and
patent-pending technologies that provide
multiple security options to safeguard
application data and software IP in embedded
systems.
Applications requiring advanced levels of
security such as data recorders, wearable and
field computers, medical monitoring and
diagnostic equipment, POS systems, and
voting machines are able to activate security
options to protect application data and
software IP from theft, falling into the wrong
hands from deployments in high-risk areas,
corruption, and accidental or malicious
overwrites.
PowerArmor prevents data corruption and loss
from power disturbances by integrating
patented technology into every SiliconDrive.
SiSMART acts as an early warning system to
eliminate unscheduled downtime by constantly
monitoring and reporting the exact amount of
remaining storage system useful life.
SiSecure is a comprehensive suite of userselectable security technologies that solves
the critical need for robust storage security for
embedded systems applications that have a
small footprint and low-power requirement.

• Integrated PowerArmor, SiSMART, and
SiSecure technologies
• Capacity range: 32MB to 8GB
• Supports both 8-bit and 16-bit data register
transfers
• Supports dual-voltage 3.3V or 5V interface
•
•
•
•
•
•

Data reliability <1 error in 1014 bits read
MTBF 4,000,000 hours
ATA-3 compliant
Industry standard Type I CF form factor
RoHS 5 of 6 compliant
Supports PIO modes 0-4 and DMA modes
0-2

8GB
SSD-C08G(I)-3150

SISECURE
PowerArmor Eliminates drive corruption.
SiZone
Data zones with different
security parameters.
SiKey
Ties SiliconDrive to a specific
host and/or software IP.
SiProtect
Protection software for
password-required, read/write,
or read-only access.
SiSweep
Ultra-fast data erasure.
SiPurge
Non-recoverable data erasure.

Click here

SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
26840 ALISO VIEJO PARKWAY, ALISO VIEJO, CA 92656

3150C-10DSR

• PHONE: 949.900.9400 • FAX: 949.900.9500 • http://www.siliconsystems.com
FEBRUARY 2, 2009

REVISION HISTORY

SSD-CXXX(I)-3150 DATA SHEET

REVISION HISTORY
Document No.

Release Date

Changes

3150C-09DSR

February 2, 2009

Updated:
• "System Reliability" table and changed the
name to "Reliability."
• "Related Documentation" table.
Added:
• “Projected Operational Life Span.”

3150C-08DSR

June 17, 2008

Updated:
• “Overview.”
• “SiliconDrive Technology” to “SiSecure.”

3150C-07DSR

May 14, 2008

Updated:
• “Overview.”
• SiliconDrive Secure to SiSecure.
• SiProtect information.

SSDS06-3150C-R

January 28, 2008

Added a Note below the “DC Characteristics”
table.

SSDS05-3150C-R

December 11, 2007

Updated the tRWD Maximum in the “True IDE
Multiword DMA Read/Write Access Timing”
table.

SSDS05-3150C-R

August 1, 2007

Updated:
• Cylinder Low in the “Task File Register
Specification” table.
• “Sample Label.”

SSDS04-3150C-R

May 22, 2007

• Updated "SiliconDrive Secure Technology."
• Removed NOP command from the "ATA
Command Set" table.

SSDS03-3150C-R

February 7, 2007

Updated:
• VIH symbol from 2.0 to 2.5 in the "DC
Characteristics" table.
• "Common
Memory
Description
and
Operation" tables.

SSDS02-3150C-R

December 29, 2006

Updated the -CS0, -CS1 signals in the "Signal
Description" table.

SSDS01-3150C-R

July 6, 2006

Updated the temperature in “Environmental
Specifications” table.

SSDS00-3150C-R

June 8, 2006

Initial release.

SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

PAGE II

FEBRUARY 2, 2009

TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

TABLE OF CONTENTS
Overview .......................................................................................................................... i
SiSecure........................................................................................................................... i
Features ........................................................................................................................... i
Revision History..............................................................................................................II
List of Figures ............................................................................................................... VII
List of Tables ................................................................................................................ VIII
Physical Specifications ................................................................................................. 1
Physical Dimensions .................................................................................................... 1
Product Specifications .................................................................................................. 2
System Performance.................................................................................................... 2
System Power Requirements....................................................................................... 2
Reliability ...................................................................................................................... 3
Projected Operational Life Span .................................................................................. 3
Product Capacity Specifications................................................................................... 4
Environmental Specifications ....................................................................................... 4
Electrical Specification.................................................................................................. 5
Pin Assignments........................................................................................................... 5
Signal Descriptions....................................................................................................... 6
Absolute Maximum Ratings........................................................................................ 14
Capacitance ............................................................................................................... 15
DC Characteristics ..................................................................................................... 15
AC Characteristics...................................................................................................... 16
Attribute and Common Memory Read Timing ...................................................... 16
Attribute and Common Memory Write Timing ...................................................... 17
I/O Access Read Timing....................................................................................... 18
I/O Access Write Timing....................................................................................... 19
True IDE Read/Write Access Timing.................................................................... 20

SILICONSYSTEMS PROPRIETARY
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3150C-10DSR

PAGE III

FEBRUARY 2, 2009

TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

True IDE Multiword DMA Read/Write Access Timing .......................................... 21
Attribute Memory Description and Operation ........................................................... 22
Attribute Memory Read Operations............................................................................ 22
Attribute Memory Write Operations ............................................................................ 23
Attribute Memory Map ................................................................................................ 24
Card Information Structure ......................................................................................... 25
Configuration Option Register (200h)......................................................................... 36
Configuration and Status Register (202h) .................................................................. 37
Pin Placement Register (204h) .................................................................................. 38
Socket and Copy Register (206h) .............................................................................. 39
Common Memory Description and Operation .......................................................... 40
Common Memory Read Operations........................................................................... 40
Common Memory Write Operations........................................................................... 40
I/O Space Description and Operation ........................................................................ 41
I/O Space Read Operations ....................................................................................... 41
I/O Space Write Operations ....................................................................................... 41
ATA and True IDE Register Decoding ........................................................................ 42
Memory-Mapped Register Decoding.......................................................................... 42
Independent I/O Mode Register Decoding ................................................................. 43
Primary and Secondary I/O Mapped Register Decoding ........................................... 44
Task File Register Specification ................................................................................. 45
ATA Registers............................................................................................................... 46
Data Register ............................................................................................................. 46
Error Register ............................................................................................................. 46
Feature Register......................................................................................................... 47
Sector Count Register ................................................................................................ 48
Sector Number Register............................................................................................. 49
Cylinder Low Register ................................................................................................ 50
Cylinder High Register ............................................................................................... 51

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FEBRUARY 2, 2009

TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

Drive/Head Register ................................................................................................... 52
Status Register........................................................................................................... 53
Command Register .................................................................................................... 54
Alternate Status Register ........................................................................................... 55
Device Control Register ............................................................................................. 56
Device Address Register............................................................................................ 57
ATA Command Block and Set Description ................................................................ 58
ATA Command Set .................................................................................................... 58
Check Power Mode — 98h, E5h .......................................................................... 60
Executive Drive Diagnostic — 90h ....................................................................... 61
Format Track — 50h ............................................................................................ 62
Identify Drive — ECh............................................................................................ 63
Identify Drive — Drive Attribute Data ............................................................. 64
Idle — 97h, E3h.................................................................................................... 67
Idle Immediate — 95h, E1h.................................................................................. 68
Initialize Drive Parameters — 91h........................................................................ 69
Recalibrate — 1Xh ............................................................................................... 70
Read Buffer — E4h .............................................................................................. 71
Read DMA — C8h................................................................................................ 72
Read Multiple — C4h ........................................................................................... 73
Read Sector — 20h, 21h...................................................................................... 74
Read Long Sector(s) — 22h, 23h......................................................................... 75
Read Verify Sector(s) — 40h, 41h ....................................................................... 76
Seek — 7Xh ......................................................................................................... 77
Set Features — EFh............................................................................................. 78
Set Multiple Mode — C6h .................................................................................... 79
Set Sleep Mode — 99h, E6h................................................................................ 80
Standby — 96h, E2h ............................................................................................ 81
Standby Immediate — 94h, E0h .......................................................................... 82

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FEBRUARY 2, 2009

TABLE OF CONTENTS

SSD-CXXX(I)-3150 DATA SHEET

Write Buffer — E8h .............................................................................................. 83
Write DMA — CAh ............................................................................................... 84
Write Multiple — C5h ........................................................................................... 85
Write Sector(s) — 30h, 31h.................................................................................. 86
Write Long Sector(s) — 32h, 33h......................................................................... 87
Erase Sector(s) — C0h ........................................................................................ 88
Request Sense — 03h ......................................................................................... 89
Translate Sector — 87h ....................................................................................... 90
Wear-Level — F5h ............................................................................................... 91
Write Multiple w/o Erase — CDh.......................................................................... 92
Write Sector(s) w/o Erase — 38h......................................................................... 93
Write Verify — 3Ch............................................................................................... 94
Sales and Support ....................................................................................................... 95
Part Numbering ............................................................................................................ 95
Nomenclature ............................................................................................................. 95
Part Numbers ............................................................................................................. 96
Sample Label ............................................................................................................. 96
Related Documentation............................................................................................... 97

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PAGE VI

FEBRUARY 2, 2009

LIST OF FIGURES

SSD-CXXX(I)-3150 DATA SHEET

LIST OF FIGURES
Figure 1: Physical Dimensions......................................................................................... 1
Figure 2: Attribute and Common Memory Read Timing Diagram.................................. 16
Figure 3: Attribute and Common Memory Write Timing Diagram .................................. 17
Figure 4: I/O Access Read Timing Diagram .................................................................. 18
Figure 5: I/O Access Write Timing Diagram................................................................... 19
Figure 6: True IDE Read/Write Access Timing Diagram ............................................... 20
Figure 7: True IDE Multiword DMA Read/Write Access Timing..................................... 21
Figure 8: Sample Label.................................................................................................. 96

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PAGE VII

FEBRUARY 2, 2009

LIST OF TABLES

SSD-CXXX(I)-3150 DATA SHEET

LIST OF TABLES
Table 1: System Performance ......................................................................................... 2
Table 2: System Power Requirements ............................................................................ 2
Table 3: Reliability............................................................................................................ 3
Table 4: Operational Life Span ........................................................................................ 3
Table 5: Product Capacity Specifications ........................................................................ 4
Table 6: Environmental Specifications............................................................................. 4
Table 7: Pin Assignments ................................................................................................ 5
Table 8: Signal Descriptions ............................................................................................ 6
Table 9: Absolute Maximum Ratings ............................................................................. 14
Table 10: Capacitance ................................................................................................... 15
Table 11: DC Characteristics ......................................................................................... 15
Table 12: Attribute and Common Memory Read Timing................................................ 16
Table 13: Attribute and Common Memory Write Timing................................................ 17
Table 14: I/O Access Read Timing ................................................................................ 18
Table 15: I/O Access Write Timing ................................................................................ 19
Table 16: True IDE Read/Write Access Timing ............................................................. 20
Table 17: True IDE Multiword DMA Read/Write Access Timing.................................... 21
Table 18: Attribute Memory Read Operations ............................................................... 22
Table 19: Attribute Memory Write Operations................................................................ 23
Table 20: Attribute Memory Map.................................................................................... 24
Table 21: Card Information Structure............................................................................. 25
Table 22: Configuration Option Register (200h) ............................................................ 36
Table 23: Configuration and Status Register (202h)...................................................... 37
Table 24: Pin Placement Register (204h) ...................................................................... 38
Table 25: Socket and Copy Register (206h).................................................................. 39
Table 26: Common Memory Read Operations .............................................................. 40
Table 27: Common Memory Write Operations .............................................................. 40

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All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

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FEBRUARY 2, 2009

LIST OF TABLES

SSD-CXXX(I)-3150 DATA SHEET

Table 28: I/O Space Read Operations........................................................................... 41
Table 29: I/O Space Write Operations ........................................................................... 41
Table 30: Memory-Mapped Register Decoding ............................................................. 42
Table 31: Independent I/O Mode Register Decoding..................................................... 43
Table 32: Primary and Secondary I/O Mapped Register Decoding ............................... 44
Table 33: Task File Register Specification..................................................................... 45
Table 34: Error Register................................................................................................. 46
Table 35: Feature Register ............................................................................................ 47
Table 36: Sector Count Register.................................................................................... 48
Table 37: Sector Number Register ................................................................................ 49
Table 38: Cylinder Low Register.................................................................................... 50
Table 39: Cylinder High Register ................................................................................... 51
Table 40: Drive/Head Register....................................................................................... 52
Table 41: Status Register .............................................................................................. 53
Table 42: Command Register ........................................................................................ 54
Table 43: Alternate Status Register ............................................................................... 55
Table 44: Device Control Register ................................................................................. 56
Table 45: Device Address Register ............................................................................... 57
Table 46: ATA Command Block and Set Description .................................................... 58
Table 47: ATA Command Set ........................................................................................ 58
Table 48: Check Power Mode — 98h, E5h.................................................................... 60
Table 49: Executive Drive Diagnostic — 90h................................................................. 61
Table 50: Format Track — 50h ...................................................................................... 62
Table 51: Identify Drive — ECh ..................................................................................... 63
Table 52: Identify Drive — Drive Attribute Data ............................................................. 64
Table 53: Idle — 97h, E3h ............................................................................................. 67
Table 54: Idle Immediate — 95h, E1h ........................................................................... 68
Table 55: Initialize Drive Parameters — 91h ................................................................. 69
Table 56: Recalibrate — 1Xh......................................................................................... 70

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3150C-10DSR

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FEBRUARY 2, 2009

LIST OF TABLES

SSD-CXXX(I)-3150 DATA SHEET

Table 57: Read Buffer — E4h........................................................................................ 71
Table 58: Read DMA — C8h ......................................................................................... 72
Table 59: Read Multiple — C4h..................................................................................... 73
Table 60: Read Sector — 20h, 21h ............................................................................... 74
Table 61: Read Long Sector(s) — 22h, 23h .................................................................. 75
Table 62: Read Verify Sector(s) — 40h, 41h ................................................................. 76
Table 63: Seek — 7Xh................................................................................................... 77
Table 64: Set Features — EFh ...................................................................................... 78
Table 65: Set Features’ Attributes ................................................................................. 78
Table 66: Set Multiple Mode — C6h .............................................................................. 79
Table 67: Set Sleep Mode — 99h, E6h ......................................................................... 80
Table 68: Standby — 96h, E2h...................................................................................... 81
Table 69: Standby Immediate — 94h, E0h .................................................................... 82
Table 70: Write Buffer — E8h ........................................................................................ 83
Table 71: Write DMA — CAh ......................................................................................... 84
Table 72: Write Multiple — C5h ..................................................................................... 85
Table 73: Write Sector(s) — 30h, 31h ........................................................................... 86
Table 74: Write Long Sector(s) — 32h, 33h .................................................................. 87
Table 75: Erase Sector(s) — C0h.................................................................................. 88
Table 76: Request Sense — 03h................................................................................... 89
Table 77: Extended Error Codes ................................................................................... 89
Table 78: Translate Sector — 87h ................................................................................. 90
Table 79: Wear-Level — F5h......................................................................................... 91
Table 80: Write Multiple w/o Erase — CDh ................................................................... 92
Table 81: Write Sector(s) w/o Erase — 38h .................................................................. 93
Table 82: Write Verify — 3Ch ........................................................................................ 94
Table 83: Part Numbering Nomenclature ...................................................................... 95
Table 84: Part Numbers................................................................................................. 96
Table 85: Related Documentation ................................................................................. 97

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FEBRUARY 2, 2009

PHYSICAL SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

PHYSICAL SPECIFICATIONS
The SiliconDrive CF products are offered in an industry-standard Type I form
factor. See "Part Numbering" on page 95 for details regarding CF capacities.

PHYSICAL DIMENSIONS
This section provides diagrams that describe the physical dimensions for the
CF.

Figure 1: Physical Dimensions

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PRODUCT SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

PRODUCT SPECIFICATIONS
Note: All SiliconDrive CF values quoted are typical at 25°C and nominal
supply voltage.

SYSTEM PERFORMANCE
Table 1: System Performance
Reset to Ready Startup Time (Typical/Maximum)
Read Transfer Rate (Typical)
Write Transfer Rate (Typical)
Burst Transfer Rate
Controller Overhead (Command to DRQ)

200ms/400ms
8MBps
6MBps
16.7MBps
2ms (maximum)

SYSTEM POWER REQUIREMENTS
Table 2: System Power Requirements
DC Input Voltage
Sleep (Standby Current)
Read (Typical/Peak)
Write (Typical/Peak)

3.3 ± 10%
<0.5mA
20mA/75mA
30mA/75mA

5.0 ± 10%
<1.0mA
30mA/100mA
40mA/100mA

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PRODUCT SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

RELIABILITY
Table 3: Reliability
MTBF (@ 25ºC)
Bit Error Rate

4,000,000 hours
<1 non-recoverable error in 1014 bits read

PROJECTED OPERATIONAL LIFE SPAN
Table 4: Operational Life Span
SiliconDrive Part#

Capacity

Service Life*

GB Written per Day

SSD-C08G-3150

8GB

324.3 Years

@ 135.2GB

SSD-C04G-3150
SSD-C02G-3150
SSD-C01G-3150
SSD-C51M-3150
SSD-C25M-3150
SSD-C12M-3150
SSD-C64M-3150
SSD-C32M-3150

4GB
2GB
1GB
512MB
256MB
128MB
64MB
32MB

162.2 Years
81.1 Years
40.5 Years
20.3 Years
10.1 Years
5.1 Years
2.5 Years
1.3 Years

@
@
@
@
@
@
@
@

135.2GB
135.2GB
135.2GB
135.2GB
135.2GB
135.2GB
135.2GB
135.2GB

* There are unlimited read cycles. Service life is determined using
SiliconSystems’ LifeEst calculation at 100% duty cycle with 25% write cycles.
LifeEst is a comprehensive measurement that considers numerous factors to
determine the projected life span of a SiliconDrive. A white paper that
describes the benefits of LifeEst and how to calculate it can be found at http://
www.siliconsystems.com/resources/Documents/Whitepaper/
SiliconSystems_NAND_Evolution.pdf.
The actual life of a SiliconDrive is dependant on the customer usage model.
SiSMART is a patented technology of SiliconSystems that enables host
systems to monitor actual usage of a SiliconDrive in real time. SiSMART
measures and reports the remaining life of a SiliconDrive. For more
information on SiSMART, refer to the Eliminating Unscheduled Downtime by
Forecasting Useable Life white paper at http://www.siliconsystems.com/
technology/pdfs/SiliconDrive_SiSMART.pdf.

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FEBRUARY 2, 2009

PRODUCT SPECIFICATIONS

SSD-CXXX(I)-3150 DATA SHEET

PRODUCT CAPACITY SPECIFICATIONS
Table 5: Product Capacity Specifications
Product Capacity
Capacity (Bytes)

Number of
Sectors

Number of
Number of Number
Sectors/
Cylinders of Heads
Track

32MB
64MB
128MB
256MB
512MB
1GB
2GB
4GB
8GB

63,872
128,128
254,208
508,928
1,019,088
2,046,240
4,098,528
8,251,488
16,514,064

499
1001
993
994
1011
2030
4066
8186
16,383*

32,702,464
65,601,536
130,154,496
260,571,136
521,773,056
1,047,674,880
2,098,446,336
4,224,761,856
8,455,200,768

4
4
8
16
16
16
16
16
16

32
32
32
32
63
63
63
63
63

* = All IDE drives 8GB and larger use 16383 cylinders, 16 heads, and 63 sectors/track due to
interface restrictions.

ENVIRONMENTAL SPECIFICATIONS
Table 6: Environmental Specifications
Temperature
Humidity
Vibration
Shock
Altitude

0ºC to 70ºC (Commercial)
-40ºC to 85ºC (Industrial)
8% to 95% non-condensing
16.3gRMS, MIL-STD-810F, Method 514.5, Procedure I,
Category 24
1000G, Half-sine, 0.5ms Duration
50g Pk, MIL-STD-810F, Method 516.5, Procedure I
80,000ft, MIL-STD-810F, Method 500.4, Procedure II

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

ELECTRICAL SPECIFICATION
PIN ASSIGNMENTS
The following table describes the SiliconDrive CF 50-pin IDE connector
signals.
Table 7: Pin Assignments
PC Card
Memory
Mode

PC Card
I/O Mode

IDE-ATA
Mode

PC Card
Memory
Pin
Mode

PC Card
I/O Mode

IDE-ATA
Mode

GND

CD1#

D11

D111

D121

D131

D141

D151

CE1#

CE2#

A10

VS1#

OE#

IORD#

A92

IOWR#

A82

WE#

A7 2

RDY/BSY

IREQ

RDY/BSY

VCC

A62

CSEL#

A52

VS2#

A42

RESET#

A32

WAIT#

INPACK#

DMARQ

REG#

DMACK#

BVD2

SPKR#

DASP#

BVD1

STSCHG# PDIAG#

D81

D91

-IOIS16

D101

CD2#

GND

CD1#
1

Notes:
1 = These signals are required only for 16-bit access, and not required when installed in
8-bit systems.
2 = Should be grounded by the host.

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

SIGNAL DESCRIPTIONS
Table 8: Signal Descriptions
Signal Name

A10-A0

8, 10, 11, I
12, 14, 15,
16, 17, 18,
19, 20

These address lines along with the
-REG signal are used to select the
following:

18, 19, 20 I

In true IDE mode, only A[2:0] are used
to select the one of eight registers in
the Task File. The remaining address
lines should be grounded by the host.

A10-A0
(PC Card I/O
mode)
A2-A0
(True IDE mode)

BVD1
46
(PC Card memory
mode)
-STSCHG
(PC Card I/O
mode)

Type Description

I/O

-PDIAG
(True IDE mode)
BVD2
45
(PC Card memory
mode)

I/O

• The I/O port address registers
within the SiliconDrive CF
• The memory-mapped port address
registers within the SiliconDrive CF
• A byte in the card's information
structure and its configuration
control and status registers
This signal is the same as the PC
Card Memory Mode signal.

This signal is asserted high, because
BVD1 is not supported.
This signal is asserted low to alert the
host to changes in the RDY/-BSY and
Write Protect states while the I/O
interface is configured. This signal’s
use is controlled by the Card
Configuration and Status register.
In the true IDE mode, this input/output
is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
This signal is asserted high, as BVD2
is not supported.

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ELECTRICAL SPECIFICATION

SSD-CXXX(I)-3150 DATA SHEET

Table 8: Signal Descriptions (Continued)
Signal Name

Type Description

-SPKR
(PC Card I/O
mode)
-DASP
(True IDE mode)
-CD1, -CD2
26, 25
(PC Card memory
mode)
-CD1, -CD2
(PC Card I/O
Mode)
-CD1, -CD2
(True IDE mode)
-CE1, -CE2
7, 32
(PC Card memory
mode)
Card Enable

This line is the Binary Audio output
from the card. If the Card does not
support the Binary Audio function, this
line should be held negated.
In the true IDE mode, this input/output
is the Disk Active/Slave Present
signal in the Master/Slave handshake
protocol.
These Card Detect pins are
connected to ground on the
SiliconDrive CF, and are used by the
host to determine that the SiliconDrive
CF is fully inserted into its socket.
This signal is the same for all modes.

This signal is the same for all modes.
I

These input signals are used both to
select the card and to indicate to the
card whether a byte or a word
operation is being performed.
• -CE2 always accesses the odd
byte of the word.
• -CE1 accesses the even byte or
the odd byte of the word depending
on A0 and -CE2.
A multiplexing scheme based on A0,
-CE1, and -CE2 allows 8-bit hosts to
access all data on D0-D7. See
"Attribute Memory Read Operations"
on page 22, "Attribute Memory Write
Operations" on page 23, "Common
Memory Read Operations" on page
40, and "Common Memory Write
Operations" on page 40.

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Table 8: Signal Descriptions (Continued)
Signal Name

Type Description

-CE1, -CE2
(PC Card I/O
mode)
Card Enable
-CS0, -CS1
(True IDE mode)

-CSEL
39
(PC Card memory
mode)

-CSEL
(PC Card I/O
mode)
-CSEL
(True IDE mode)

This signal is the same as the PC
Card Memory Mode signal. See "I/O
Space Read Operations" on page 41
and "I/O Space Write Operations" on
page 41.
In the true IDE mode, -CS0 is the chip
select for the task file registers while
-CS1 is used to select the Alternate
Status register and the Device Control
register.
This signal is not used for this mode.

This signal is not used for this mode.

This internally pulled-up signal is used
to configure this device as a master or
slave when configured in the true IDE
mode.
When this pin is:

-INPACK
43
(PC Card memory
mode)
-INPACK
(PC Card I/O
mode)
Input Acknowledge

• Grounded, this device is configured
as a master.
• Open, this device is configured as
a slave.
This signal is not used in this mode.

This signal is asserted by the
SiliconDrive CF when the card is
selected and responding to an I/O
read cycle at the address that is on
the address bus. This signal is used
by the host to control the enabling of
any input data buffers between the
SiliconDrive CF and the CPU.

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Table 8: Signal Descriptions (Continued)
Signal Name

Type Description

DMARQ
(True IDE mode)

D15-D00
31, 30, 29, I/O
(PC Card memory 28, 27, 49,
48, 47, 6,
mode)
5, 4, 3, 2,
23, 22, 21

D15-D00
(PC Card I/O
mode)
D15-D00
(True IDE mode)
GND
1, 50
(PC Card memory
mode)
GND
(PC Card I/O
mode)
GND
(True IDE mode)

In true IDE mode, this signal is used
for DMA transfers between the host
and device. DMARQ is asserted by
the device when the device is ready to
transfer data to/from the host. The
direction of data transfer is controlled
by -IORD and -IOWR. This signal is
used in a handshake manner with
-DMACK (i.e., the device waits until
the host asserts -DMACK before
negating DMARQ, and reasserts
DMARQ if there is more data to
transfer). The DMARQ/-DMACK
handshake is used to provide flow
control during the transfer.
These lines carry the data,
commands, and status information
between the host and the controller.
• D00 is the LSB of the word’s even
byte.
• D08 is the LSB of the word’s odd
byte.
This signal is the same as the PC
Card Memory Mode signal.
In true IDE mode, all Task File
operations occur in byte mode on the
low-order bus D00-D07, while all data
transfers are 16 bits using D00-D15.
Ground.

This signal is the same for all modes.

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Table 8: Signal Descriptions (Continued)
Signal Name

-IORD
34
(PC Card memory
mode)
-IORD
(PC Card I/O
mode)

Type Description
I

This is an I/O read strobe generated
by the host. This signal gates I/O data
onto the bus from the SiliconDrive CF
when the card is configured to use the
I/O interface.
In true IDE mode, this signal has the
same function as the PC Card I/O
mode.

-IORD
(True IDE mode)
-IOWR
35
(PC Card memory
mode)
-IOWR
(PC Card I/O
mode)

-IOWR
(True IDE mode)
-OE
9
(PC Card memory
mode)

This signal is not used in this mode.

The I/O write strobe pulse is used to
clock I/O data on the Card data bus
into the SiliconDrive CF controller
registers when the SiliconDrive CF is
configured to use the I/O interface.
The clocking occurs on the negativeto-positive edge of the signal (the
trailing edge).
In true IDE mode, this signal has the
same function as the PC Card I/O
mode.
This is an output enable strobe
generated by the host interface, which
is used to read:
• Data from the SiliconDrive CF in
memory mode.
• The CIS and configuration
registers.
In PC Card I/O mode, this signal is
used to read the CIS and
configuration registers.

-OE
(PC Card I/O
mode)

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Table 8: Signal Descriptions (Continued)
Signal Name

-ATA SEL
(True IDE mode)
-RDY/-BSY
37
(PC Card memory
mode)

Type Description
To enable true IDE mode, this input
should be grounded by the host.
O

In memory mode, this signal is:
• Set high when the SiliconDrive CF
is ready to accept a new data
transfer operation.
• Held low when the card is busy.
The host memory card socket must
provide a pull-up resistor.
At power-up and reset, the RDY/-BSY
signal is held low (busy) until the
SiliconDrive CF has completed its
power-up or reset function. No access
of any type should be made to the
SiliconDrive CF during this time. The
RDY/-BSY signal is held high
(disabled from being busy) whenever
the SiliconDrive CF has been
powered up with +RESET
continuously disconnected or
asserted.

-IREQ
(PC Card I/O
mode)
Input Acknowledge

I/O Operation. After the SiliconDrive
CF has been configured for I/O
operation, this signal is used as
-Interrupt Request. This line is strobed
low to generate a pulse mode
interrupt or held low for a level mode
interrupt.
In true IDE mode, this signal is the
active high Interrupt Request to the
host.

-IREQ
(True IDE mode)

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Table 8: Signal Descriptions (Continued)
Signal Name

-REG
44
(PC Card memory
mode)
Attribute Memory
Select

Type Description
I

This signal is used during memory
cycles to distinguish between
common memory and register
(attribute) memory accesses. This
signal is set:
• High for common memory.
• Low for attribute memory.
The signal must also be active (low)
during I/O cycles when the I/O
address is on the bus.

-REG
(PC Card I/O
mode)
-DMACK
(True IDE mode)

-RESET
41
(PC Card memory
mode)

-RESET
(PC Card I/O
mode)
-RESET
(True IDE mode)
13, 38

VCC

In true IDE mode, this signal is used
by the host in response to DMARQ to
initiate DMA transfers. The DMARQ/
-DMACK handshake is used to
provide flow control during the
transfer. When -DMACK is asserted,
-CS0 and -CS1 are not asserted and
transfers are 16-bits wide.
When the pin is high, this signal
resets the SiliconDrive CF. The
SiliconDrive CF is reset only at powerup if this pin is left high or open from
power-up. The SiliconDrive CF is also
reset when the Soft Reset bit in the
Card Configuration Option register is
set.
This signal is the same as the PC
Card Memory Mode signal.
In the true IDE mode, this input pin is
the active low hardware reset from the
host.
+5V, +3.3V power.

(PC Card memory
mode)

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Table 8: Signal Descriptions (Continued)
Signal Name

Type Description

VCC

This signal is the same for all modes.

(PC Card I/O
mode)
VCC

This signal is the same for all modes.

(True IDE mode)
-VS1, -VS2

33, 40

-VS1, -VS2
(PC Card I/O
mode)
-VS1, -VS2
(True IDE mode)
-WAIT
42
(PC Card memory
mode)
-WAIT
(PC Card I/O
mode)
-IORDY
(True IDE mode)
-WE
36
(PC Card memory
mode)

Voltage Sense Signals.
• -VS1 is grounded so that the
SiliconDrive CF CIS can be read at
3.3V.
• -VS2 is reserved by PC Card for a
secondary voltage.
This signal is the same for all modes.

This signal is the same for all modes.
O

The -WAIT signal is driven low by the
SiliconDrive CF to signal the host to
delay completion of a memory or I/O
cycle that is in progress.
This signal is the same as the PC
Card Memory Mode signal.
In true IDE mode, this output signal
may be used as IORDY.

-WE
(PC Card I/O
mode)

This is a signal driven by the host and
used for strobing memory write data
to the registers of the SiliconDrive CF
when the card is configured in the
memory interface mode. This signal is
also used for writing the configuration
registers.
In PC Card I/O mode, this signal is
used for writing the configuration
registers.

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Table 8: Signal Descriptions (Continued)
Signal Name

Type Description

-WE
(True IDE mode)

In true IDE mode, this input signal is
not used and should be connected to
VCC by the host.

WP
24
(PC Card memory
mode)

-IOIS16
(PC Card I/O
mode)

-IOIS16
(True IDE mode)

Write Protect Memory Mode. The
SiliconDrive CF does not have a write
protect switch. This signal is held low
after the completion of the reset
initialization sequence.
I/O Operation. When the SiliconDrive
CF is configured for I/O operation, pin
24 is used for the -I/O Selected, which
is a 16-bit port (-IOIS16) function. A
low signal indicates that a 16-bit or
odd byte only operation can be
performed at the addressed port.
In true IDE mode, this output signal is
asserted low when this device is
expecting a word data transfer cycle.

ABSOLUTE MAXIMUM RATINGS
Table 9: Absolute Maximum Ratings
Symbol

Parameter

Minimum Maximum Units

Storage Temperature

-55

125

°C

Operating Temperature

-40

°C

VCC

VCC with Respect to GND

-0.3

6.7

Vin

Input Voltage

-0.5

3.8

Vout

Output Voltage

-0.3

3.6

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CAPACITANCE
Table 10: Capacitance
Symbol

Parameter

Maximum

Units

Cin

Input Capacitance

Cout

Output Capacitance

CI/O

Bidirectional Capacitance

DC CHARACTERISTICS
Table 11: DC Characteristics
3.3 V ±10%

Symbol Parameter

5V ±10%

Units

Minimum Maximum Minimum Maximum
VCC
ILI
ILO

VCCR
VCCW
VCCS
VIL
VIH
VOL
VOH

Power Supply 3.0
Voltage
Input Leakage *(1) Current
Output
Leakage *(1)
Current

3.6

4.5

5.5

μA

VCC Read
Current
VCC Write
Current
VCC Standby
Current
Input Low
Voltage
Input High
Voltage
Output Low
Voltage
Output High
Voltage

0.3

0.5

-0.3

0.3 x VCC -0.3

0.3 x VCC V

2.5

VCC + 0.3 2.5

VCC + 0.3 V

0.4

2.4

*(1) Except the pulled-up/pulled-down pin.

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AC CHARACTERISTICS
Attribute and Common Memory Read Timing
tRC

tGHAX

tA(A)

____
A[10::0],REG
tA(CE)

tAXQX

tELWL

__
CE
tAVWL

__
OE

tGHEH

tA(OE)

tDIS(OE)
tEN(OE)

D[15::0]

Figure 2: Attribute and Common Memory Read Timing Diagram
Table 12: Attribute and Common Memory Read Timing
Symbol

Parameter

Minimum

Maximum

Units

tRC

Read Cycle Time

100

tA(A)

Address Access Time

100

tA(CE)

Card Enable Access Time

100

tA(OE)

Output Enable Access Time

tDIS(OE)

Output Disable Time from OE

tEN(OE)

Output Enable Time from OE

tAXQX

Data Valid from Address Change

tAVWL

Address Setup Time

tAXQX

Address Hold Time

tELWL

Card Enable Setup Time before OE

tGHEH

Card Enable Hold Time following OE

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Attribute and Common Memory Write Timing
tWR

____
A[10::0],REG
tELWH
tELWL

__
CE

tGHEH

tAVWH

__
OE
tWLWH

tAVWL

tWHAX

___
WE

tWHOL
tWLOL

tDVWH

tWHDX

D[15:0](Dout)

tOLWH

tWLQZ

tOHDX
tWHOX

D[15:0](Dout)

Figure 3: Attribute and Common Memory Write Timing Diagram
Table 13: Attribute and Common Memory Write Timing
Symbol

Parameter

Minimum

Maximum

Units

tWR

Write Cycle Time

100

tWLWH

Write Pulse Width

tAVWL

Address Setup Time

tAVWH

Address Setup Time for WE

tELWH

Card Enable Setup Time for WE

tWHDX

Data Hold Time

tWHAX

Write Recover Time

tWLQZ

Output Disable Time from WE

tOLWH

Output Disable Time from OE

100

tWHOX

Output Enable Time from WE

tOHDX

Output Enable Time from OE

tWLOL

Output Enable Setup for WE

tWHOL

Output Enable Hold from WE

tELWL

Card Enable Setup Time before WE

tGHEH

Card Enable Hold Time from WE

tDVWH

Data Setup Time

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I/O Access Read Timing

A[10::0]
tGHAX
tRLIGL

____
REG

tRHIGH

tCLIGL

__
CE

tCHIGH

tIGLIGH

___
IORD

tIGHINH

tAVIGL

______
INPACK
tIGLINL

______
IOIS16

tAXISH

tAVISL
tIGHQX

tDVRL

D[15::0]

Figure 4: I/O Access Read Timing Diagram
Table 14: I/O Access Read Timing
Symbol

Parameter

Minimum

Maximum

Units

tDVRL

Data Delay after IORD

tIGHQX

Data Hold following IORD

tIGLIGH

IORD Pulse Width

tAVIGL

Address Setup before IORD

tGHAX

Address Hold following IORD

tCLIGL

CE Setup before IORD

tCHIGH

CE Hold following IORD

tRLIGL

REG Setup before IORD

tRHIGH

REG Hold following IORD

tIGLINL

INPACK Delay falling from IORD

(1)

tIGHINH

INPACK Delay Rising from IORD

(1)

tAVISL

IOIS16 Delay Falling from Address

(1)

tAXISH

IOIS16 Delay Rising from Address

(1)

Note: (1) IOIS16 and INPACK are not supported.

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I/O Access Write Timing

A[10::0]
tAXIGH
tRLIGL

____
REG

tRHIGH

tCHIGH

tCLIGL

__
CE

tIGLIGH

_____
IOWR
tAVIGL

______
IOIS16

tAXISH

tAVISL
tIGHQX

tIGHDX

D[15::0]

Figure 5: I/O Access Write Timing Diagram
Table 15: I/O Access Write Timing
Symbol

Parameter

Minimum

Maximum

Units

tIGHDX

Data Hold following IOWR

tIGHQX

Data Setup before IOWR

tIGLIGH

IOWR Pulse Width

tAVIGL

Address Setup before IOWR

tAXIGH

Address Hold following IOWR

tCLIGL

CE Setup before IOWR

tCHIGH

CE Hold following IOWR

tRLIGL

REG Setup before IOWR

tRHIGH

REG Hold following IOWR

tAVISL

IOIS16 Delay Falling from Address

(1)

tAXISH

IOIS16 Delay Rising from Address

(1)

Note: (1) IOIS16 and INPACK are not supported.
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ELECTRICAL SPECIFICATION

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True IDE Read/Write Access Timing
tICL

ADDRESS Valid
CS0, CS1, DA[2::0]
tAVRWL

tAX16H

tAXRWH
tRWPW

____ _____
DIOR,DIOW

tDVWL

WRITE
DD[15::00]
tDXWH

READ
DD[15::00]
tDVRL
tIOST

IORDY
______
IOIS16

tDXRH
tIOPW

tAV16L

Figure 6: True IDE Read/Write Access Timing Diagram
Table 16: True IDE Read/Write Access Timing
Symbol Parameter

Minimum Maximum Units

tICL

Cycle Time

100

tAVRWL

Address Valid to DIOR,DIOW Setup Time

tRWPW

DIOR, DIOW Pulse Width

tDVWL

DIOW Data Setup Time

tDXWH

DIOW Data Hold Time

tDVRL

DIOR Data Setup Time

tDXRH

DIOR Data Hold Time

tAV16L

Address Valid to IOCS16 Assertion

(1)

tAX16H

Address Valid to IOCS16 Negation

(1)

tAXRWH

DIOW,DIOR to Address Valid Hold Time

tIOST

IORDY Setup Time

(1)

tIOPW

IORDY Pulse Width

(1)

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ELECTRICAL SPECIFICATION

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True IDE Multiword DMA Read/Write Access Timing
This function does not apply to SiliconDrives that have DMA disabled.

Figure 7: True IDE Multiword DMA Read/Write Access Timing
Table 17: True IDE Multiword DMA Read/Write Access Timing
Symbol

Parameter

Minimum

Maximum

Units

tRWC

Cycle Time (mode 2)

100

tRWPW

DIOR/DIOW Pulse Width

tRDA

DIOR Data Access

tRWSU

DIOR/DIOW Data Setup Time

tWH

DIOW Data Hold Time

tRH

DIOR Data Hold Time

tDMRW

DMACK to DIOR/DIOW Setup Time

tRWDH

DIOR/DIOW to DMACK Hold Time

tRWN

DIOR/DIOW negated Pulse Width

tRWD

DIOR/DIOW to DMARQ Delay

tCSRW

CS(1:0) valid to DIOR/DIOW

tCSH

CS(1:0) Hold Time

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION
The attribute memory plane can be read or written to by asserting the REG#
signal, qualified by the appropriate combination of CE1#, OE#, and WE#. An
attribute memory map describing the type and location of the information
maintained in the attribute memory plane is provided in "Attribute Memory
Map" on page 24.
With respect to SiliconDrive CF, attribute memory consists of two sections:
• Card Information Structure (CIS), which contains a description of the Card’s
capabilities and specifications.
• Function Configuration Registers (FCRs), which consists of four registers,
that can be read or written to by a host to configure the Card for specific
purposes.

ATTRIBUTE MEMORY READ OPERATIONS
Attribute memory read operations are enabled by asserting REG#, OE#, and
CE1# low. Odd byte read operations from the attribute memory plane are not
valid.
Table 18: Attribute Memory Read Operations
Function
Mode
Standby
Byte Access
Word Access
Odd Byte
Only Access

REG# CE1# CE2# A0

OE# WE# D[15:8]

D[7:0]

L
L
L
L
L

X
L
L
L
H

High-Z
Even
Not Valid
Even
High-Z

H
L
H
L
L

H
H
L
L
H

X
L
H
X
X

X
H
H
H
H

High-Z
High-Z
High-Z
Not Valid
Not Valid

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

ATTRIBUTE MEMORY WRITE OPERATIONS
Attribute memory write operations are enabled by asserting REG#, WE#, and
CE1# low. Odd byte write operations from the attribute memory plane are not
valid.
Table 19: Attribute Memory Write Operations
Function
Mode
Standby
Byte Access
Word Access
Odd Byte
Only Access

REG# CE1# CE2# A0

OE# WE# D[15:8]

D[7:0]

L
L
L
L
L

X
H
H
H
H

High-Z
Even
Not Valid
Even
High-Z

H
L
H
L
L

H
H
L
L
H

X
L
H
X
X

X
L
L
L
H

High-Z
High-Z
High-Z
Not Valid
Not Valid

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

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ATTRIBUTE MEMORY MAP
As stated earlier, the Attribute Memory plane is comprised of two components,
the CIS and the FCRs. The following tables detail the type, location, and read/
write requirements for each of the four FCRs maintained in the attribute
memory plane.
Table 20: Attribute Memory Map
Register

Operation Addr CE1# REG# WE#

OE#

Card Information Structure

Read
Write
Read
Write
Read

X
X
200h
200h
202h

0
0
0
0
0

1
0
1
0
1

0
1
0
1
0

Write
Read
Write
Read
Write

202h
204h
204h
206h
206h

0
0
0
0
0

0
1
0
1
0

1
0
1
0
1

Configuration Option
Card Configuration and
Status
Pin Replacement
Socket and Copy

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All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

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FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

CARD INFORMATION STRUCTURE
The CIS is data that describes the SiliconDrive CF, and is described by the
CFA standard. This information can be used by the host system to determine a
number of things about the Card that has been inserted. For information
regarding the exact nature of this data and how to design the host software to
interpret it, refer to the PC Card Standard Metaformat Specification.
Table 21: Card Information Structure
Attribute
Data
Offset
00h

01h

02h

03h

04h

D9h

0 Description of Contents

CISTPL_DEVICE
Device Type
Code
Dh = I/O

Device
Speed
1

CIS Function

Device information tuple

Tuple code

Link length is 3 bytes

Link to next tuple

•
•
•

I/O device
No WP
Speed = 100ns

Device ID
WPS
Device speed

06h

01h

2KB of address space

Device size

08h

FFh

List End Marker

0Ah

1Ch

CISTPL_DEVICE_OC

End of device

END marker

0Ch

04h

0Eh

02h

10h

D9h

Device Type

12h

01h

14h

FFh

List End Marker

16h

18h

CISTPL_JEDEC_C

18h

02h

TPL_LINK

1Ah

DFh

PCMCIA Manufacturer’s JEDEC

1Ch

01h

PCMCIA JEDEC Device Code

1Eh

20h

CISTPL_MANFID

20h

04h

TPL_LINK

22h

00h

24h

00h

High Byte of PCMCIA
Manufacturer’s Code

Code of 0, because the other byte is the High byte of the
JEDEC 1 byte manufacturer’s ID
manufacturer’s
code

26h

00h

Low Byte of Product Code

Manufacturer’s code for SiliconDrive CF Low byte of the
product code

28h

00h

High Byte of Product Code

Manufacturer’s code for SiliconDrive CF High byte of the
product code

2Ah

21h

CISTPL_FUNCID

2Ch

02h

TPL_LINK

Other conditions device in tuple code

Tuple code

TPL_LINK

Link length is 4 bytes

Link to next tuple

EXT Reserved VCC
MWAIT

3V, wait is Not Used

Other conditions
information field

•
•
•

W
P
S

Device
Speed
2K units

Device type = DH: I/O
Device WPS = 1: No WP
Device speed = 1: 250ns

2KB of address space

Device size

End of device

End marker

JEDEC ID common memory

Tuple code

Link length is 2 bytes

Link to next tuple

Manufacturer’s ID code
-

JEDEC ID

Second byte of JEDEC ID

Manufacturer’s ID code

Tuple code

Low Byte of PCMCIA Manufacturer’s JEDEC manufacturer’s ID
Code

Low byte of
manufacturer’s
code

Function ID tuple

Tuple code

Link length is 2 bytes

Link to next tuple

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All unauthorized use and/or reproduction is prohibited.

3150C-10DSR

PAGE 25

FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

0 Description of Contents

CIS Function

2Eh

04h

TPLFID_FUNCTION = 04H

Disk function, which may be silicon or
removable

PC Card function
code

30h

01h

Reserved

•
•

System initialization
byte

32h

22h

CISTPL_FUNCE

34h

02h

36h

01h

TPL_LINK

38h

01h

Disk Interface Type

3Ah

22h

CISTPL_FUNCE

3Ch

03h

TPL_LINK

3Eh

02h

40h

04h

Function extension tuple

Tuple code

Link length is 2 bytes

Link to next tuple

Disk Function Extension Tuple Type Disk interface type
PC Card interface type

07h

44h

1Ah

Tuple code
Link to next tuple

No Vpp, silicon, single drive

P3 P2 P1 P0 •
•
•
•
•
•
•
•

CISTPL_CONFIG

46h

05h

48h

01h

TPL_LINK

4Ah

07h

TPCC_LAST

4Ch

00h

TPCC_RADR (LSB)

4Eh

02h

50h

0Fh

RAS

RMS

RAS

V = 0: No Vpp required
S = 0: Silicon
U = 1: Unique serial number
D = 0: Single drive on Card

Extension tuple type
for disk
Basic ATA option
parameters byte 1

P0: Sleep mode supported
Basic ATA option
P1: Standby mode supported
parameters byte 2
P2: Idle mode supported
P3: Drive auto power control
N: Some configuration excludes 3X7
E: Index bit is emulated
I: Twin IOIS16# data register only
R: Reserved

Configuration tuple

Tuple code

Link length is 5 bytes

Link to next tuple

•
•
•
•
•

Size of fields byte
TPCC_SZ

RFS: Reserved
RMS: TPCC RMSK size -1 = 0
RAS: TPCC_RADR size -1 = 1
1-byte register mask
2-byte configuration base address

Entry with configuration index of 7 is final Last entry of
entry in table
configuration
registers

TPCC_RADR (MSB)
Reserved

Interface type

Function extension tuple

Disk Function Extension Tuple Type Basic PCMCIA-ATA extension tuple
Reserved

Extension tuple type
for disk

Link length is 3 bytes

•
•
•
•
42h

R = 0: No BIOS ROM
P = 1: Configure card at power-on

52h

1Bh

CISTPL_TABLE_ENTRY

54h

0Bh

TPL_LINK

Configuration registers are located at
200H in REG space

Location of
configuration
registers

•
•
•
•

I: Configuration index
C: Configuration and status
P: Pin replacement
S: Socket and copy

Configuration
registers present
mask
TPCC_RMSK

Configuration table entry tuple

Tuple code

Link length is 11 bytes

Link to next tuple

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3150C-10DSR

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FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

56h

C0h

0 Description of Contents

Configuration index

58h

C0h

5Ah

A1h

M MS IR

Memory-mapped I/O configuration

Interface Type

I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 0

•
•
•
•
•

W = 0: Wait not used
R = 1: Ready active
P = 0: WP used
B = 0: BVD1 and BVD2 not used
IF type = 0: Memory interface

•

M = 1: Miscellaneous information
Feature selection
present
byte TPCE_FS
MS = 01: Memory space information
single 2-byte length
IR = 0: No interrupt information
present
IO = 0: No I/O port information
present
T = 0: No timing information present
P = 1: VCC only information

•
•
•
•
27h

SI HV LV NV Nominal voltage only follows
•
•
•
•
•
•
•
•

Mantissa

R: Reserved
DI: Powerdown current information
PI: Peak current information
AI: Average current information
SI: Static current information
HV: Maximum voltage information
LV: Minimum voltage information
NV: Nominal voltage information

Interface description
field TPCE_IF

Power parameters
for VCC

5Eh

55h

Nominal voltage = 5V

VCC nominal value

60h

4Dh

Mantissa

Exponent

VCC nominal 4.5V

VCC minimum value

62h

5Dh

Mantissa

Exponent

VCC nominal 5.5V

VCC maximum value

64h

75h

Mantissa

Exponent

Maximum average current over 10ms is Maximum average
80mA
current

66h

08h

Length in 256 bytes pages (LSB)

Length of memory space is 2KB

Memory space
description
structures
(TPCE_MS)

68h

00h

Length in 256 bytes pages (MSB) Length of memory space is 2KB

Memory space
description
structures
(TPCE_MS)

6Ah

21h

6Ch

1Bh

CISTPL_TABLE_ENTRY

6Eh

06h

TPL_LINK

Exponent

Configuration table
index byte
TPCE_INDX

•
•
•

•

5Ch

CIS Function

•
•
•
•
•
•

X = 0: No more miscellaneous fields Miscellaneous
R: Reserved
features field
P = 1: Powerdown supported
TPCE_MI
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

Configuration table entry tuple

Tuple code

Link length is 6 bytes

Link to next tuple

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3150C-10DSR

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

70h

72h

00h

01h

M MS IR

0 Description of Contents
-

Memory-mapped I/O configuration
I = 0: No interface byte
D = 0: No default entry
Configuration index = 0

•
•

M = 0: No miscellaneous information Feature selection
byte
MS = 00: No memory space
information
TPCE_FS
IR = 0: No interrupt information
present
IO = 0: No I/O port information
present
T = 0: No timing information present
P = 1: VCC only information

•
•
•
21h

HV/LV/NV Nominal voltage only follows
•
•
•
•
•
•
•
•

76h

B5h

78h

1Eh

Mantissa

Exponent

7Ah

4Dh

7Ch

1Bh

CISTPL_TABLE_ENTRY

7Eh

0Dh

TPL_LINK

80h

C1h

Extension
X

Mantissa

Exponent

D Configuration

INDEX

Configuration table
index byte
TPCE_INDX

•
•
•

•

74h

CIS Function

Power parameters
for VCC

Nominal voltage = 3.0 V

VCC nominal value

+0.3 V

Extension byte

Maximum average current over 10ms is Maximum average
45 mA
current
Configuration table entry tuple

Tuple code

Link length is 10 bytes

Link to next tuple

Contiguous I/O mapped ATA registers
configuration

Configuration table
index byte
TPCE_INDX

•
•
•

I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 1

82h

41h

Interface Type

•
•
•
•
•

W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not used
IF type = 1: I/O interface

84h

99h

M MS IR

•

M = 1: Miscellaneous information
Feature selection
present
byte TPCE_FS
MS = 00: No memory space
information
IR = 1: Interrupt information present
IO = 1: I/O port information present
T = 0: No timing information present
P = 1: VCC only information

•
•
•
•
•

Interface description
field TPCE_IF

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

86h

SI HV LV NV Nominal voltage only follows

27h

0 Description of Contents

•
•
•
•
•
•
•
•
88h

55h

Mantissa

Exponent

CIS Function
Power parameters
for VCC

Nominal voltage = 5V

VCC nominal value

8Ah

4Dh

Mantissa

Exponent

VCC nominal 4.5V

VCC minimum value

8Ch

5Dh

Mantissa

Exponent

VCC nominal 5.5V

VCC maximum value

8Eh

75h

Mantissa

Exponent

Maximum average current over 10ms is Maximum average
80mA
current

90h

64h

92h

F0h

94h

FFh

IR SiliconSystems recommends the IRQ
Q level to be routed 0 to 15

IR SiliconSystems recommends routing to
any normal, maskable IRQ.
Q

15 14 13 12

96h

FFh

98h

21h

9Ah

1Bh

9Ch

06h

9Eh

01h

AddrLine

CISTPL__TABLE_ENTRY
I

•
•
•

N •
•
•
•
•
•
•
•

•
•
•
•
•
•

S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLine: 4 lines decoded

I/O space
description field
TPCE_IO

S = 1: Share logic active
P = 1: Pulse mode IRQ supported
L = 1: Level mode IRQ supported
M = 1: Bit mask of IRQs present
V = 0: No vender unique IRQ
B = 0: No bus error IRQ
I = 0: No IO check IRQ
N = 0: No NMI

Interrupt request
description structure
TPCE_IR

Mask extension
byte 1 TPCE_IR

Mask extension
byte 2 TPCE_IR

X = 0: No more miscellaneous fields Miscellaneous
features field
R: Reserved
TPCE_MI
P = 1: Powerdown supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

Configuration table entry tuple

Tuple code

TPL_LINK

Link length is 6 bytes

Link to next tuple

Configuration Index

Contiguous I/O mapped ATA registers
configuration

Configuration table
index
Byte TPCE_INDX

•
•
•

I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 1

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

A0h

M MS IR

01h

0 Description of Contents
-

•
•
•
•
•
•

A2h

21h

M = 0: No miscellaneous information Feature selection
byte TPCE_FS
MS = 00: No memory space
information
IR = 0: No interrupt information
present
IO = 0: No I/O port information
present
T = 0: No timing information present
P = 1: VCC only information

SI HV LV NV Nominal voltage only follows
•
•
•
•
•
•
•
•

CIS Function

Power parameters
for VCC

A4h

B5h

Mantissa

Exponent

Nominal voltage = 3.0V

VCC nominal value

A6h

1Eh

Mantissa

Exponent

+0.3V

Extension byte

A8h

4Dh

Mantissa

Exponent

Maximum average current over 10ms is Maximum average
45mA
current

AAh

1Bh

CISTPL_TABLE_ENTRY

Configuration table entry tuple

Extension byte

ACh

12h

TPL_LINK

Link length is 18 bytes

Link to next tuple

AEh

C2h

Configuration Index

ATA primary I/O mapped configuration

Configuration table
index byte
TPCE_INDX

•
•
•

I = 1: Interface byte follows
D = 1: default entry follows
Configuration index = 2

B0h

41h

Interface Type

•
•
•
•
•

W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not used
IF type = 1: I/O interface

B2h

99h

M MS IR

•

•
•
•
•
•
B4h

27h

SI HV LV NV Nominal voltage only follows
•
•
•
•
•
•
•
•

Interface description
field TPCE_IF

Power parameters
for VCC

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

B6h

55h

Mantissa

Exponent

Nominal voltage = 5V

VCC nominal value

B8h

4Dh

Mantissa

Exponent

VCC nominal 4.5V

VCC minimum value

BAh

5Dh

Mantissa

Exponent

VCC nominal 5.5V

VCC maximum value

BCh

75h

Mantissa

Exponent

Maximum average current over 10ms is Maximum average
80mA
current

BEh

EAh

C0h

61h

LS AS

C2h

F0h

First I/0 Base Address

First I/O base address (LSB)

First I/O range
address

C4h

01h

First I/0 Base Address

First I/O base address (MSB)

C6h

07h

First I/0 Base Address

First I/O length -1

First I/O range
length

C8h

F6h

Second I/O Base Address

Second I/O base address (LSB)

Second I/O range
address

CAh

03h

Second I/O Base Address

Second I/O base address (MSB)

CCh

01h

Second I/O Range Length

Second I/O length -1

Second I/O range
length

CEh

EEh

M IRQ

•
•
•
•

S = 1: Share logic active
P = 1: Pulse mode IRQ supported
L = 1: Level mode IRQ supported
M = 0: Bit mask of IRQs present —
IRQ level is IRQ14

Interrupt request
description structure
TPCE_IR

D0h

21h

•
•
•
•
•
•

X = 0: No more miscellaneous fields Miscellaneous
features field
R: Reserved
TPCE_MI
P = 1: Powerdown supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

D2h

1Bh

CISTPL_TABLE_ENTRY

Configuration table entry tuple

Tuple code

D4h

06h

TPL_LINK

Link length is 6 bytes

Link to next tuple

D6h

02h

Configuration Index

ATA primary I/O mapped configuration

Configuration table
index byte
TPCE_INDX

0 Description of Contents

AddrLine

N Range

Level

•
•
•

R = 1: Range follows
S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines decoded

I/O space
description field
TPCE_IO

•
•
•

LS = 1: Size of lengths is 1 byte
AS = 2: Size of address is 2 bytes
N Range = 1: Address Range-1

I/O range format
description

•
•
•
D8h

01h

Configuration Index

CIS Function

I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 2

Contiguous I/O mapped ATA registers
configuration
•
•
•

I = 0: No interface byte
D = 0: No default entry
Configuration index = 1

Configuration table
index byte
TPCE_INDX

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

DAh

M MS IR

21h

0 Description of Contents
-

•
•
•
•
•
•

DCh

B5h

DEh

1Eh

E0h

4Dh

Mantissa

Extension

E2h

1Bh

CISTPL_TABLE_ENTRY

E4h

12h

TPL_LINK

E6h

C3h

M MS IR

Exponent

Nominal voltage = 3.0V

VCC nominal value
Extension byte

Configuration table entry tuple

Tuple code

Link length is 18 bytes

Link to next tuple

•
•

•
•
•

EAh

41h

99h

M MS IR

M = 0: No miscellaneous information Feature selection
MS = 00: No memory space
byte TPCE_FS
information
IR = 0: No interrupt information
present
IO = 0: No I/O port information
present
T = 0: No timing information present
P = 1: VCC only information

SI HV LV NV Nominal voltage only follows

Power parameters
for VCC

+0.3V

•

E8h

SI HV LV NV Nominal voltage only follows
•
•
•
•
•
•
•
•

CIS Function

Power parameters
for VCC

•
•
•
•
•
•
•
•

•
•

M = 1: No miscellaneous information Feature selection
MS = 00: No Memory space
byte TPCE_FS
information
IR = 1: No interrupt information
present
IO = 1: No I/O port information
present
T = 0: No timing information present
P = 01: VCC only information

•
•
•
•

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3150C-10DSR

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FEBRUARY 2, 2009

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

ECh

SI HV LV NV Nominal voltage only follows

27h

0 Description of Contents

•
•
•
•
•
•
•
•

CIS Function
Power parameters
for VCC

EEh

55h

Mantissa

Exponent

Nominal voltage = 5V

VCC nominal value

F0h

4Dh

Mantissa

Exponent

VCC nominal 4.5V

VCC minimum value

F2h

5Dh

Mantissa

Exponent

VCC nominal 5.5V

VCC maximum value

F4h

75h

Mantissa

Exponent

Maximum average current over 10ms is Maximum average
80mA
current

F6h

EAh

F8h

61h

LS AS

FAh

•
•
•
•

R = 1: Range follows
S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines decoded

I/O space
description field
TPCE_IO

N Range

•
•
•

LS = 1: Size of lengths is 1 byte
AS = 2: Size of address is 2 bytes
N Range = 1: Address range -1

I/O range format
description

70h

First I/O base address (LSB)

First I/O range
address

FCh

01h

First I/O base address (MSB)

FEh

07h

First I/O length -1

First I/O range
length

100h

76h

Second I/O base address (LSB)

Second I/O range
address

102h

03h

Second I/O base address (MSB)

104h

01h

Second I/O length

Second I/O range
length

106h

EEh

M IRQ

•
•
•
•

S = 1: Share logic active
P = 1: Pulse mode IRQ supported
L = 1: Level mode IRQ supported
M = 0: Bit mask of IRQs present —
IRQ level is IRQ14

Interrupt request
description structure
TPCE_IR
miscellaneous
features field
TPCE_MI

108h

21h

•
•
•
•
•
•

X = 0: No more miscellaneous fields R: Reserved
P = 1: Powerdown supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

AddrLine

Level

10Ah

1Bh

CISTPL_TABLE_ENTRY

10Ch

06h

TPL_LINK

Configuration table entry tuple

Tuple code

Link length is 6 bytes

Link to next tuple

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

10Eh

110h

03h

01h

0 Description of Contents

Configuration Index

M MS IR

ATA primary I/O mapped configuration
I = 0: No interface byte
D = 0: No default entry
Configuration index = 2

•
•

•
•
•
21h

SI HV LV NV Nominal voltage only follows
•
•
•
•
•
•
•
•

114h

B5h

116h

1Eh

118h

4Dh

Mantissa

Exponent

Extension
X

Mantissa

Exponent

Configuration table
index byte
TPCE_INDX

•
•
•

•

112h

CIS Function

Power parameters
for VCC

Nominal voltage = 3.0V

VCC nominal value

+0.3V

Extension byte

Maximum average current over 10ms is Maximum average
45mA
current

11Ah

1Bh

CISTPL_MANFID

Manufacturer’s ID code

Tuple code

11Ch

04h

TPL_LINK

Link length is 4 bytes

Link to next tuple

11Eh

07h

Configuration Index

AT fixed disk secondary I/O 3.3V
configuration

TPCE_INDX

120h

00h

M MS IR

P: Power information type

TPCL_FS

122h

28h

Manufacturer code for SiliconDrive CF

Reserved

124h

D3h

Manufacturer code for SiliconDrive CF

Reserved

126h

14h

CISTPL_NO_LINK

128h

00h

12Ah

15h

CISTPL_VERS_1

Level 1 version

Tuple code

12Ch

1Ah

TPL_LINK

Link length is 26h bytes

Link to next tuple

12Eh

04h

TPPLV1_MAJOR

PC Card 2.0/JEIDA4.1

END marker

130h

01h

TPPLV1_MINOR

PC Card 2.0/JEIDA4.1

Tuple code

132h

53h

Information string

134h

49h

136h

4Ch

138h

49h

13Ah

43h

No link control tuple

Tuple code

Link is 0 bytes

Link to next tuple

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-CXXX(I)-3150 DATA SHEET

Table 21: Card Information Structure (Continued)
Attribute
Data
Offset

0 Description of Contents

CIS Function

13Ch

4Fh

13Eh

4Eh

140h

53h

142h

59h

144h

53h

146h

54h

45h

4Dh

14Ah
14Ch

53h

14Eh

00h

Space

150h

56h

152h

45h

154h

52h

156h

32h

158h

2Eh

15Ah

30h

15Ch

30h

00h

FFh

160h

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

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CONFIGURATION OPTION REGISTER (200H)
The Configuration Option register is used to configure the SiliconDrive CF,
define the address decoding, and initiate the software RESET sequence.
Table 22: Configuration Option Register (200h)
D7

Operation
Read/
Write
Default
Value

SRESET LevIREQ
0

Configuration Index
0

Bit(s)

Description

SRESET

When set, this bit initiates a software-reset sequence, which
is equivalent to a power-on reset or hardware reset.
IREQ# interrupt signal level mode select:

LevlREQ

Configuration
Index

•
•
•
•
•
•

Logic 0 = Pulse mode
Logic 1 = Level mode
Memory-mapped mode
Independent I/O mode
Primary mode
Secondary mode

000000B
000001B
000010B
000011B

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

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CONFIGURATION AND STATUS REGISTER (202H)
The Configuration and Status Register (CSR) informs the host of any status
changes with regard to power-down.
Table 23: Configuration and Status Register (202h)
Operation
Read
Write
Default
Value

Changed SigChg IOis8
Changed SigChg IOis8
0
0
0

0
0
0

PwrDn
PwrDn
0

Int
Int
0

0
0
0

Bit(s)

Description

Changed

Indicates that either CREADY (D5) or CWPort (D4) of the Pin
Replacement register is set. Additionally, this bit changes state
as the Powerdown (D2) bit changes.
Outputs the inverse state of the Changed bit to the hardware
interface signal STSCHG# at the card interface.
Informs the host of the valid data bus width for the operations in
progress:

SigChg
Iois8

PwrDwn

Int

• 0 = 16-bit data transfer
• 1 = 8-bit data transfer
Indicates the state of the Card, which is either operating -0 or
powerdown mode 1. During powerdown mode, no commands
are accepted. Additionally, the host may not initiate a
powerdown request when the card is busy via the Status
register or the Hardware RDY/BSY pin.
Indicates the inverse of the IREQ# status signal.

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

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PIN PLACEMENT REGISTER (204H)
Table 24: Pin Placement Register (204h)
Operation

Read/
Write
Default
Value

CBVD1 CBVD2 CRDY CWProt RBVD1 RBVD2 RRDY RWProt

Bit(s)

Description

CRDY

Indicates a bit change in the RRDY (D1) bit.

CWProt
RRDY

Indicates a bit change in the RWProt (D0) bit.
When set:

RWProt

• High 1 informs the host that the card is ready
• Low 0 state indicates the card is busy
Indicates Write Protect is enabled when set to 1, and disabled
when 0.

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ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

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SOCKET AND COPY REGISTER (206H)
Table 25: Socket and Copy Register (206h)
D7

Operation
Read/Write
Default Value

RFU
0

Copy Number
0
0
0

Socket Number
0
0

D0
0

Bit(s)

Description

RFU
Copy
Number

Reserved for future use.
Indicates the card number. Allows the host to differentiate
between identical cards by writing to the bit of the card that is
being accessed. This value is compared to the DRV bit in the
ATA Drive/Head register.

Socket
Number

• Card 0: 000B = (D6, D5, D4) (default)
• Card 1: 001B = (D6, D5, D4) (alternate)
The host writes the socket number that identifies the inserted
card.

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COMMON MEMORY DESCRIPTION AND OPERATION

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COMMON MEMORY DESCRIPTION AND OPERATION
Common memory space can be accessed when the SiliconDrive is configured
in memory-mapped mode.

COMMON MEMORY READ OPERATIONS
Common memory read operations are issued by asserting CE1#, CE2#, or
both, and OE# low, REG#, and WE# must be inactive.
Table 26: Common Memory Read Operations
Function Mode REG# CE1# CE2# A0 OE#

WE#

D[15:8] D[7:0]

Standby

High-Z High-Z

Byte Access

H
H
H
H

L
L
L
H

H
H
L
L

L
H
X
X

L
L
L
L

H
H
H
H

High-Z
High-Z
Odd
Odd

Word Access
Odd Byte Only
Access

Even
Odd
Even
High-Z

COMMON MEMORY WRITE OPERATIONS
Common memory write operations are issued by asserting CE1#, CE2#, or
both, and WE# low, REG#, and OE# must be inactive.
Table 27: Common Memory Write Operations
Function Mode REG# CE1# CE2# A0 OE#

WE#

D[15:8] D[7:0]

Standby
Byte Access

X
L
L
L
L

High-Z
High-Z
High-Z
Odd
Odd

Word Access
Odd Byte Only
Access

X
H
H
H
H

H
L
L
L
H

H
H
H
L
L

X
L
H
X
X

X
H
H
H
H

High-Z
Even
Odd
Even
High-Z

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I/O SPACE DESCRIPTION AND OPERATION

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I/O SPACE DESCRIPTION AND OPERATION
I/O SPACE READ OPERATIONS
Table 28: I/O Space Read Operations
Function Mode REG# CE1# CE2# A0

IORD# IOWR# D[15:8] D[7:0]

Standby
Byte Access

X
L
L
L
L
L

Word Access
I/O Inhibit
Odd Byte Only
Access

X
L
L
L
H
L

H
L
L
L
X
H

H
H
H
L
X
L

X
L
H
L
X
X

X
H
H
H
H
H

High-Z
High-Z
High-Z
Odd
High-Z
Odd

High-Z
Even
Odd
Even
High-Z
High-Z

I/O SPACE WRITE OPERATIONS
Table 29: I/O Space Write Operations
Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0]
Standby

Byte Access

L
L
L
H
L

L
L
L
X
H

H
H
L
X
L

L
H
L
X
X

H
H
H
H
H

L
L
L
L
L

X
X
Odd
X
Odd

Even
Odd
Even
X
X

Word Access
I/O Inhibit
Odd Byte Only
Access

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ATA AND TRUE IDE REGISTER DECODING

SSD-CXXX(I)-3150 DATA SHEET

ATA AND TRUE IDE REGISTER DECODING
SiliconDrive can be configured as either a a memory-mapped or an an I/O
devices. As noted earlier, communication to and from the drive is
accomplished using the ATA Command Block.

MEMORY-MAPPED REGISTER DECODING
In memory-mapped mode, the SiliconDrive registers are accessed via
standard memory references (i.e., OE# and WE#). The ATA registers are
mapped to common memory space in a 2KB window starting at address 0.
Table 30: Memory-Mapped Register Decoding
Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L

WE# = L

Even Data
Read
Error

Even Data
Write
Feature

1
1

2
3

0
0

X
X

0
0

1
1

0
1

1
1
1
1
1

4
5
6
7
8

0
0
0
0
0

X
X
X
X
X

0
0
0
0
1

1
1
1
1
0

0
0
1
1
0

0
1
0
1
0

Sector Count
Sector
Number
Cylinder Low
Cylinder High
Drive/Head
Status
Duplicate
Even Data
Read

Sector Count
Sector
Number
Cylinder Low
Cylinder High
Drive/Head
Command

1
1

F
X

0
1

X
X

1
X

1
0

Odd Data
Read

Odd Data
Write

Duplicate
Even Data
Write
Duplicate Odd Duplicate Odd
Data Read
Data Write
Duplicate
Duplicate
Error
Feature
Alternate
Device Control
Status
Drive Address Reserved
Even Data
Even Data
Read
Write

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ATA AND TRUE IDE REGISTER DECODING

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INDEPENDENT I/O MODE REGISTER DECODING
Independent I/O mode or contiguous I/O mode requires the host to decode a
continuous block of 16 I/O registers to select the SiliconDrive.
Table 31: Independent I/O Mode Register Decoding
Reg# Offset A10 A9:A4 A3 A2 A1 A0 OE# = L

WE# = L

0
0
0

1
2
3

X
X
X

0
0
0

0
1
1

1
0
1

0
0
0
0
0

4
5
6
7
8

X
X
X
X
X

0
0
0
0
1

1
1
1
1
0

0
0
1
1
0

0
1
0
1
0

Even Data
Write
Feature
Sector Count
Sector
Number
Cylinder Low
Cylinder High
Drive/Head
Command

Even Data
Read
Error
Sector Count
Sector
Number
Cylinder Low
Cylinder High
Drive/Head
Status
Duplicate
Even Data
Read
Duplicate Odd
Data Read
Duplicate Error

Duplicate
Even Data
Write
Duplicate Odd
Data Write
Duplicate
Feature
Device Control

Alternate
Status
Drive Address Reserved

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ATA AND TRUE IDE REGISTER DECODING

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PRIMARY AND SECONDARY I/O MAPPED REGISTER DECODING
Table 32: Primary and Secondary I/O Mapped Register Decoding
Reg# A10

A9:A4 A9:A4
A3 A2 A1 A0 IORD# = L
Primary Secondary

1Fxh

17xh

0
0

X
X

1Fxh
1Fxh

17xh
17xh

0
0

0
1

1
0

1Fxh

17xh

1Fxh

17xh

1Fxh

17xh

0
0
0

X
X
X

1Fxh
1Fxh
3Fxh

17xh
17xh
37xh

0
0
0

1
1
1

0
1
0

3Fxh

37xh

Even Data
Read
Error
Sector
Count
Sector
Number
Cylinder
Low
Cylinder
High
Drive/Head
Status
Alternate
Status
Drive
Address

IOWR# = L
Even Data
Write
Feature
Sector
Count
Sector
Number
Cylinder
Low
Cylinder
High
Drive/Head
Command
Device
Control
Reserved

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ATA AND TRUE IDE REGISTER DECODING

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TASK FILE REGISTER SPECIFICATION
The Task File registers are used for reading and writing the storage data in the
SiliconDrive. The decoded addresses are as shown in the following table.
Table 33: Task File Register Specification
CS0#

CS1#

DA02

DA01

DA00

DIOR# = L

DIOW# = L

0
0
0
0
0

1
1
1
1
1

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

Data
Error
Sector Count
Sector Number
Cylinder Low

Data
Feature
Sector Count
Sector Number
Cylinder Low

0
0
0
0
1
1
1

1
1
1
0
1
0
0

1
1
1
X
X
0
1

0
1
1
X
X
X
0

1
0
1
X
X
X
X

Cylinder High
Drive/Head
Status
Invalid
High-Z
High-Z
High-Z

Cylinder High
Drive/Head
Command
Invalid
Not Used
Not Used
Not Used

1
1

0
0

1
1

0
1

Alternate Status Device Control
Device Address Not Used

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ATA REGISTERS

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ATA REGISTERS
DATA REGISTER
The Data register is a 16-bit register used to transfer data blocks between the
host and drive buffers. The register may set to 8-bit mode by using the Set
Features Command defined in "Seek — 7Xh" on page 77.

ERROR REGISTER
The Error register contains the error status, if any, generated from the last
executed ATA command. The contents are qualified by the ERR bit being set
in "Status Register" on page 53.
Table 34: Error Register
Operation
Read
Default
Value

BBK
0

UNC
0

MC
0

IDNF
0

MCR
0

ABRT TKNOF AMNF
0
0
0

Bit(s)

Description

7
6

Bad Block Detected (BBK). Set when a bad block is detected.
Uncorrectable Data Error (UNC). Set when an uncorrectable error
is encountered.
Media Changed (MC). Set to 0.
ID Not Found (IDNF). Set when the sector ID is not found.
MCR (Media Change Request). Set to 0.
Aborted Command (ABRT). Set when a command is aborted due
to a drive error.
Track 0 Not Found (TKONF). Set when the execute drive
diagnostic command is executed.
Address Mark Not Found (AMNF). Set in the case of a general
error.

5
4
3
2
1
0

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ATA REGISTERS

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FEATURE REGISTER
The Feature register is command-specific and used to enable and disable
interface features. This register supports only either odd or even byte data
transfers.
Table 35: Feature Register
Operation

Read/Write

Feature Byte

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ATA REGISTERS

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SECTOR COUNT REGISTER
The Sector Count register is used to read or write the sector count of the data
for which an ATA transfer has been made.
Table 36: Sector Count Register
Operation

Read/Write
Default Value

Sector Count
0

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ATA REGISTERS

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SECTOR NUMBER REGISTER
The Sector Number register is set by the host to specify the starting sector
number associated with the next ATA command to be executed. Following a
qualified ATA command sequence, the device sets the register value to the
last sector read or written as a result of the previous AT command.
When Logical Block Addressing (LBA) mode is implemented and the host
issues a command, the contents of the register describe the Logical Block
Number bits A[7:0]. Following an ATA command, the device loads the register
with the LBA block number resulting from the last ATA command.
Table 37: Sector Number Register
Operation

Read/Write

Sector Number (CHS Addressing)
Logical Block Number bits A07-A00 (LBA Addressing)

Default Value

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ATA REGISTERS

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CYLINDER LOW REGISTER
The Cylinder Low register is set by the host to specify the cylinder number low
byte. Following an ATA command, the content of the register is written by the
device, identifying the cylinder number low byte.
In LBA mode, the 8-bit register maintains the contents of the Logical Block
number address bits A15:A08.
Table 38: Cylinder Low Register
Operation

Read/Write

Cylinder Number Low Byte (CHS Addressing)
Logical Block Number bits A15-A08 (LBA Addressing)

Default Value

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ATA REGISTERS

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CYLINDER HIGH REGISTER
The Cylinder High register is set by the host to specify the cylinder number
high byte. Following an ATA command, the content of the register is set
internally by the device, identifying the cylinder number high byte.
In LBA mode, the 8-bit register maintains the contents of the Logical Block
number address bits A23:A16.
Table 39: Cylinder High Register
Operation

Read/Write

Cylinder Number Low Byte (CHS Addressing)
Logical Block Number bits A23-A16 (LBA Addressing)

Default Value

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ATA REGISTERS

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DRIVE/HEAD REGISTER
The Drive/Head register is used by the host and the device to select the type
of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head
number in CHS mode or logical block number bits 27-24 in LBA mode.
Table 40: Drive/Head Register
Operation

Read/Write

LBA

DRV

Default
Value

HS3
HS2
HS1
HS0
LBA27 LBA26 LBA25 LBA24
0
0
0
0

The Drive/Head register is used by the host to specify one of a pair of ATA
drives present in the platform.
Bit(s)

Description

6
4

LBA. Selects between CHS (0) and LBA (1) addressing mode.
Drive Address (DRV). Indicates the drive number selected by the
host, either 0 or 1.
HS3 to 0. Indicates bits 3-0 of the head number in CHS addressing
mode or LBA bits 27-24 in LBA mode.

3-0

• CHS to LBA conversion: LBA = (C x HpC + H) x SpH + S -1
• LBA to CHS conversion:
C = LBA/(HpC x SpH)
¶ H = (LBA/SpH) mod (HpC)
¶ S = (LBA mod(SpH)) + 1
¶

...where:
¶
¶
¶
¶
¶

C is the cylinder number
H is the head number
S is the sector count
HpC is the head count per cylinder count
SpH is the sector count per head count (track)

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ATA REGISTERS

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STATUS REGISTER
The Status register provides the device’s current status to the host. The status
register is an 8-bit read-only register. When the contents of the register are
read by the host, the IREQ# bit is cleared.
Table 41: Status Register
Operation

Read/Write

BSY

DRDY

DWF

DSC

DRQ

CORR

IDX

ERR

Default Value

Bit(s)

Description

Busy (BSY). Set when the drive is busy and unable to process any
new ATA commands.
Data Ready (DRDY). Set when the device is ready to accept ATA
commands from the host.
Drive Write Fault (DWF). Always set to 0.
Drive Seek Complete (DSC). Set when the drive heads have been
positioned over a specific track.
Data Request (DRQ). Set when a device is ready to transfer a word
or byte of data to or from the host and the device.
Corrected Data (CORR). Always set to 0.
Index (IDX). Always set to 0.
Error (ERR). Set when an error occurs during the previous ATA
command.

6
5
4
3
2
1
0

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ATA REGISTERS

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COMMAND REGISTER
The Command register specifies the ATA command code being issued to the
drive by the host. Execution of the command begins immediately following the
issuance of the command register code by the host.
Table 42: Command Register
Operation
Read/Write

ATA Command Code

See "ATA Command Block and Set Description" on page 58 for a listing of the
supported ATA commands.

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ATA REGISTERS

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ALTERNATE STATUS REGISTER
The Alternate Status register is a read-only register indicating the status of the
device, following the previous ATA command. See "Status Register" on page
53 for specific details.
Table 43: Alternate Status Register
Operation

Read/Write

BSY

DRDY

DWF

DSC

DRQ

CORR

IDX

ERR

Default Value

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ATA REGISTERS

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DEVICE CONTROL REGISTER
The Device Control register is used to control the interrupt request and issue
ATA software resets.
Table 44: Device Control Register
Operation
Write

SRST

nIEN

Bit(s)

Description

7-4

Reserved bits.

3
2
1

Always set to 1.
Software Reset (SRST). When set, resets the ATA software.
Interrupt Enable (nIEN). When set, device interrupts are disabled.
There is no function in the memory-mapped mode.
Always set to 0.

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ATA REGISTERS

SSD-CXXX(I)-3150 DATA SHEET

DEVICE ADDRESS REGISTER
The Device Address register is used to maintain compatibility with ATA disk
drive interfaces.
Table 45: Device Address Register
Operation

Read/Write

Default Value

nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0
0

Bit(s)

Description

7
6
5-2

Reserved bit.
Write Gate (nWTG). Low when a write to the device is in process.
nHS3 to nHS0. The negated binary address of the currently selected
head.
nDS1. Low when drive 1 is selected and active.
nDS0. Low when drive 0 is selected and active.

1
0

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ATA COMMAND BLOCK AND SET DESCRIPTION

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ATA COMMAND BLOCK AND SET DESCRIPTION
In accordance with the ANSI ATA Specification, the device implements seven
registers that are used to transfer instructions to the device by the host. These
commands follow the ANSI standard ATA protocol. A description of the ATA
command block is provided in the following table.
Table 46: ATA Command Block and Set Description
Operation

Feature

Sector Count

Sector Number

Cylinder Low

Cylinder High

Drive Head

LBA

Drive

Command

X
X

ATA COMMAND SET
Table 47: ATA Command Set
Registers Used

Class Command Name

Command
Code
FR

LBA

1
1

98h, E5h
90h

D
D

C0h
50h
ECh
97h, E3h
95h, E1h
91h

Y
Y
Y
Y

Y
-

Y
Y
-

Y
Y
D
D
D
Y

Y
Y
-

E4h
C8h
C4h

Y
Y

D
Y
Y

Y
Y

1
2
1
1
1
1
1
1
1

Check Power Mode
Execute Drive
Diagnostics
Erase Sector
Format Track
Identify Drive
Idle
Idle Immediate
Initialize Drive
Parameters
Read Buffer
Read DMA*
Read Multiple

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Table 47: ATA Command Set (Continued)
Class Command Name

Command
Code
FR

1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
3
3

22h, 23h
20h, 21h
40h, 41h
1Xh
03h
7Xh
EFh
C6h
99h, E6h
96h, E2h
94h, E0h
87h
F5h
E8h
CAh
32h, 33h
C5h
CDh

2
2
3

Read Long Sector
Read Sector(s)
Read Verify Sector(s)
Recalibrate
Request Sense
Seek
Set Features
Set Multiple Mode
Set Sleep Mode
Standby
Standby Immediate
Translate Sector
Wear Level
Write Buffer
Write DMA*
Write Long Sector
Write Multiple
Write Multiple w/o
Erase
Write Sector(s)
Write Sector(s) w/o
Erase
Write Verify

Registers Used
SC

LBA

Y
-

Y
Y

Y
Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
D
Y
D
D
D
D
D
Y
Y
D
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y
Y

30h, 31h
38h

Y
Y

3Ch

Y
Y
Y

* = This function does not apply to SiliconDrives that have DMA disabled.

Notes:
• CY = Cylinder
• SC = Sector Count
• DH = Drive/Head
• SN = Sector Number
• FR = Feature LBA — LBA bit of the Drive/Head register (D denotes that
only the drive bit is used)

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Check Power Mode — 98h, E5h
The Check Power Mode command verifies the device’s current power mode.
When the device is configured for standby mode or is entering or exiting
standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY
bit is cleared. In idle mode, BSY is set and the Sector Count register is set to
FFh. The BSY bit is then cleared and an interrupt is issued.
Table 48: Check Power Mode — 98h, E5h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
98h or E5h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Executive Drive Diagnostic — 90h
The Executive Drive Diagnostic performs an internal read write diagnostic test
using (AA55h and 55AAh). If an error is detected in the read/write buffer, the
Error register reports the appropriate diagnostic code.
Table 49: Executive Drive Diagnostic — 90h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
90h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Format Track — 50h
The Format Track command formats the common solid-state memory array.
Table 50: Format Track — 50h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
50h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Identify Drive — ECh
Issued by the host, the Identify Drive command provides 256 bytes of drive
attribute data (i.e., sector size, count, and so on) The identify drive data
structure is detailed in the following table.
Table 51: Identify Drive — ECh
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
ECh

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Identify Drive — Drive Attribute Data
Table 52: Identify Drive — Drive Attribute Data
Word
Data Default
Address
0

1
2
3
4
5
6
7-8
9
10-19

Bytes Data Description

044Ah (fixed 2
ID bit) in IDE
mode
848A
(removable ID
bit) in PCMCIA
memory and I/
O modes

XXXXh
0000h
00XXh
0000h
XXXXh
XXXXh
XXXXh
0000h
XXXXh

2
2
2
2
2
2
4
2
20

General configuration bit information
• 15: Non-magnetic disk
• 14: Formatting speed latency
permissible gap needed
• 13: Track Offset option supported
• 12: Data Strobe Offset option supported
• 11: Over 0.5% rotational speed
difference
• 10: Disk transfer rate >10Mbps
• 9: 10Mbps >= disk transfer rate >5Mbps
• 8: 5Mbps >= disk transfer rate
• 7: Removable cartridge drive
• 6: Fixed drive
• 5: Spindle Motor Control option
executed
• 4: Over 15μs changing head time
• 3: Non-MFM encoding
• 2: Soft sector allocation
• 1: Hard sector allocation
• 0: Reserved
Number of cylinders
Reserved
Number of heads
Number of unformatted bytes per track
Number of unformatted bytes per sector
Number of sectors per track
Number of sectors per device
Reserved
Serial number

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Table 52: Identify Drive — Drive Attribute Data (Continued)
Word
Data Default
Address

Bytes Data Description

0002h

21
22

0002h
0004h

2
2

23-26
27-46
47

XXXXh
XXXXh
0001h

8
40
2

48
49

0000h
0002h

2
2

50
51
52
53

0000h
0100h
0000h
0000h

2
2
2
2

54
55
56
57-58
59

XXXXh
XXXXh
XXXXh
XXXXh
010Xh

2
2
2
4
2

60-61

XXXXh

0000h

Buffer type
• 0000h: Not specified
• 0001h: A single-ported, single-sector
buffer
• 0002h: A dual-ported multisector buffer
• 0003h: A dual-ported multisector buffer
with a read caching
Buffer size in 512-byte increments
Number of ECC bytes passed on read/
write long commands
Firmware revision (eight ASCII characters)
Model number (40 ASCII characters)
7-0: Maximum number of sectors that can
be transferred with a Read/Write Multiple
command per interrupt
Double word (32 bit) not supported
• 11: IORDY supported
• 9: LBA supported
• 8: DMA supported
Reserved
15-8: PIO data transfer cycle timing
15-8: DMA data transfer cycle timing
• 1: Words 64-70 are valid
• 0: Words 54-58 are valid
Current number of cylinders
Current number of heads
Current sectors per track
Current capacity in sectors
7-0: Current sectors can be transferred
with a Read/Write Multiple command per
interrupt
Total number of sectors addressable in
LBA mode
Single-word DMA modes supported

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Table 52: Identify Drive — Drive Attribute Data (Continued)
Word
Data Default
Address

Bytes Data Description

63
64
65

0407h
0003h
0078h

2
2
2

0078h

69-127
0000h
128-159 0000h
160-255 0000h

118
64
192

Multiword DMA modes supported
PIO modes supported
Minimum DMA transfer cycle time per
word (ns)
Manufacturer’s recommended DMA
transfer cycle time (ns)
Minimum PIO transfer cycle time without
flow control (ns)
Minimum PIO transfer cycle time with
IORDY flow controls (ns)
Reserved
Vendor-unique
Reserved

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Idle — 97h, E3h
When issued by the host, the device’s internal controller sets the BSY bit,
enters the Idle mode, clears the BSY bit, and generates an interrupt. If the
sector count is non-zero, it is interpreted as a timer count with each count
being 5ms, and the automatic power-down mode is enabled. If the sector
count is zero, the automatic power-down mode is disabled.
Table 53: Idle — 97h, E3h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
Timer Count (5ms increments)
X
X
X
X
Drive
X
97h or E3h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Idle Immediate — 95h, E1h
When issued by the host, the device’s internal controller sets the BSY bit,
enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is
issued whether or not the Idle mode is fully entered.
Table 54: Idle Immediate — 95h, E1h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
95h or E1h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Initialize Drive Parameters — 91h
Initialize Drive Parameters allows the host to set the sector counts per track
and the head counts per cylinder to 1 Fixed. Upon issuance of the command,
the device sets the BSY bit and associated parameters, clears the BSY bit,
and issues an interrupt.
Table 55: Initialize Drive Parameters — 91h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
Sector Count (Number of Sectors)
X
X
X
0
X
Drive
Head Number
(Number of Heads — 1)
91h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Recalibrate — 1Xh
The Recalibrate command sets the cylinder low and high, head number to 0h,
and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector
number is set to 0h.
Table 56: Recalibrate — 1Xh
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
1

LBA

Drive
1Xh

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Read Buffer — E4h
The Read Buffer command allows the host to read the contents of the sector
buffer. When issued, the device sets the BSY bit and sets up the sector buffer
data in preparation for the read operation. When the data is ready, the DRQ bit
is set and the BSY bit in the Status register are set and cleared, respectively.
Table 57: Read Buffer — E4h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
E4h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Read DMA — C8h
The Read DMA command allows the host to read data using the DMA transfer
protocol.
Note: This function does not apply to SiliconDrives that have DMA
disabled.
Table 58: Read DMA — C8h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
C8h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Read Multiple — C4h
The Read Multiple command executes similarly to the Read Sector command,
with the exception that interrupts are issued only when a block containing the
counts of sectors defined by the Set Multiple command is transferred.
Table 59: Read Multiple — C4h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
C4h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Read Sector — 20h, 21h
The Read Sector command allows the host to read sectors 1 to 256 as
specified in the Sector Count register. If the sector count is set to 0h, all 256
sectors of data are made available. When the command code is issued and
the first sector of data has been transferred to the buffer, the DRQ bit is set.
The Read Sector command is terminated by writing the cylinder, head, and
sector number of the last sector read in the task file. On error, the read
operation is aborted in the errant sector.
Table 60: Read Sector — 20h, 21h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
20h or 21h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Read Long Sector(s) — 22h, 23h
The Read Long Sector(s) command operates similarly to the Read Sector(s)
command, with the exception that it transfers requested data sectors and ECC
data. The long instruction ECC byte transfer for Long commands is a byte
transfer at a fixed length of 4 bytes.
Table 61: Read Long Sector(s) — 22h, 23h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
X
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
22h or 23h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Read Verify Sector(s) — 40h, 41h
The Read Verify Sector(s) command operates similarly to the Read Sector(s)
command, with the exception that is does not set the DRQ bit and does not
transfer data to the host. When the requested sectors are verified, the onboard
controller clears the BSY bit and issues an interrupt.
Table 62: Read Verify Sector(s) — 40h, 41h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
40h or 41h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Seek — 7Xh
The Seek command seeks and picks up the head to the tracks specified in the
task file. When the command is issued, the solid-state memory chips do not
need to be formatted. After an appropriate amount of time, the DSC bit is set.
Table 63: Seek — 7Xh
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
X
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
7Xh

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Set Features — EFh
The Set Features command allows the host to configure the feature set of the
device according to the attributes listed in Table 65.
Table 64: Set Features — EFh
D7

Feature
X
X
X
X
Drive
EFh

Table 65: Set Features’ Attributes
Feature

Operation

01h
66h

Enable 8-bit data transfer
Disable reverting to power on defaults

81h
BBh
CCh

Disable 8-bit data transfer
4 bytes of data apply on Read/Write Long commands
Enable revert to power on defaults

On power-up or following a hardware reset, the device is set to the default
mode 81h.

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Set Multiple Mode — C6h
The Set Multiple Mode command allows the host to access the drive via Read
Multiple and Write Multiple ATA commands. Additionally, the command sets
the block count (i.e., the number of sectors within the block) for the Read/Write
Multiple command. The sector count per block is set in the Sector Count
register.
Table 66: Set Multiple Mode — C6h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
Sector Count
X
X
X
Drive
C6h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Set Sleep Mode — 99h, E6h
The Set Sleep Mode command allows the host to set the device in sleep
mode. When the onboard controller transitions to sleep mode, it clears the
BSY bit and issues an interrupt. The device interface then becomes inactive.
Sleep mode can be exited by issuing either a hardware or software reset.
Table 67: Set Sleep Mode — 99h, E6h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
99h or E6h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Standby — 96h, E2h
When the Standby command is issued by the host, it transitions the device into
standby mode. If the Sector Count register is set to a value other than 0h, the
Auto Powerdown function is enabled and the device returns to Idle mode.
Table 68: Standby — 96h, E2h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
Timer Count (5ms x Timer Count)
X
X
X
X
X
Drive
X
96h or E2h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Standby Immediate — 94h, E0h
When the Standby Immediate command is issued by the host, it transitions the
device into standby mode.
Table 69: Standby Immediate — 94h, E0h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
94h or E0h

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ATA COMMAND BLOCK AND SET DESCRIPTION

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Write Buffer — E8h
The Write Buffer command allows the host to rewrite the contents of the
512- byte data buffer with the wanted data.
Table 70: Write Buffer — E8h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
X

Drive
E8h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write DMA — CAh
The Write DMA command allows the host to write data using the DMA transfer
protocol.
Note: This function does not apply to SiliconDrives that have DMA
disabled.
Table 71: Write DMA — CAh
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low(LBA15-8)
Cylinder High(LBA23-16)
X
Drive Head Number(LBA27-24)
CAh

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Multiple — C5h
The Write Multiple command operates in the same manner as the Write Sector
command. When issued, the device sets the BSY bit within 400ns and
generates an interrupt at the completion of a transferred block of sectors. The
DRQ bit is set at the beginning of a block transfer.
Table 72: Write Multiple — C5h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low(LBA15-8)
Cylinder High(LBA23-16)
X
Drive Head Number(LBA27-24)
C5h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Sector(s) — 30h, 31h
The Write Sector(s) command writes from 1 to 256 sectors as specified in the
Sector Count register. A sector count of 0 requests 256 sectors. When issued,
the device sets the BSY bit within 400ns and generates an interrupt at the
completion of a transferred block of sectors. The DRQ bit is set at the
beginning of a block transfer.
Table 73: Write Sector(s) — 30h, 31h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
X
Drive Head Number (LBA27-24)
30h or 31h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Long Sector(s) — 32h, 33h
The Write Long Sector(s) command operates in the same manner as the Write
Sector command — when issued, the device sets the BSY bit within 400ns
and generates an interrupt at the completion of a transferred block of sectors.
The DRQ bit is set at the beginning of a block transfer.
Table 74: Write Long Sector(s) — 32h, 33h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
X
Drive Head Number (LBA27-24)
32h or 33h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Erase Sector(s) — C0h
The Erase Sector(s) command is issued prior to the issuance of a Write
Sector(s) or Write Multiple w/o Erase command.
Table 75: Erase Sector(s) — C0h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
X
Drive Head Number (LBA27-24)
C0h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Request Sense — 03h
The Request Sense command identifies the extended error codes generated
by the preceding ATA command. The Request Sense command must be
issued immediately following the detection of an error via the Error register.
Table 76: Request Sense — 03h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
X
X
X
X
1

Drive
03h

The extended error codes are defined in the following table.
Table 77: Extended Error Codes
Extended Error Codes

Description

00h
01h
09h
20h
21h
2Fh
35h, 36h
11h
18h
05h, 30h-32h, 37h,3Eh

No error detected
Self test is OK (no error)
Miscellaneous error
Invalid command
Invalid address (requested head or sector invalid)
Address overflow (address too large)
Supply or generated voltage out of tolerance
Uncorrectable ECC error
Corrected ECC error
Self test of diagnostic failed

10h, 14h
3Ah
1Fh
0Ch, 38h, 3Bh, 3Ch, 3Fh
03h

ID not found
Spare sectors exhausted
Data transfer error/aborted command
Computed media format
Write/erase failed

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Translate Sector — 87h
The Translate Sector command is not currently supported by the
SiliconSystems’ SiliconDrive. If the host issues this command, the device
responds with 0x00h in the data register.
Table 78: Translate Sector — 87h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
1
Drive Head Number (LBA27-24)
87h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Wear-Level — F5h
The Wear-Level command is supported as an NOP command for the
purposes of backward compatibility with the ANSI AT attachment standard.
This command sets the Sector Count register to 0x00h.
Table 79: Wear-Level — F5h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

X
Completion Status
X
X
X
X
Drive
F5h

Flag

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Multiple w/o Erase — CDh
The Write Multiple w/o Erase command functions identically to the Write
Multiple command, with the exception that the implied pre-erase (i.e., Erase
Sector(s) command) is not issued prior to writing the sectors.
Table 80: Write Multiple w/o Erase — CDh
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
X
Drive Head Number (LBA27-24)
CDh

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Sector(s) w/o Erase — 38h
The Write Sector(s) w/o Erase command functions similar to the Write Sector
command, with the exception that the implied pre-erase (i.e., Erase Sector(s)
command) is not issued prior to writing the sectors.
Table 81: Write Sector(s) w/o Erase — 38h
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
X
Drive Head Number (LBA27-24)
38h

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ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-CXXX(I)-3150 DATA SHEET

Write Verify — 3Ch
The Write Verify command verifies each sector immediately after it is written.
This command performs identically to the Write Sector(s) command, with the
added feature of verifying each sector written.
Table 82: Write Verify — 3Ch
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command

LBA

X
Sector Count
Sector Number (LBA7-0)
Cylinder Low (LBA15-8)
Cylinder High (LBA23-16)
X
Drive Head Number (LBA27-24)
3Ch

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SALES AND SUPPORT

SSD-CXXX(I)-3150 DATA SHEET

SALES AND SUPPORT
To order or obtain information on pricing and delivery, contact your
SiliconSystems Sales Representative.

PART NUMBERING
NOMENCLATURE
The following table defines the SiliconDrive CF part numbering scheme.
Table 83: Part Numbering Nomenclature
SSD-

YYY

-3150

Part number suffix —
contact your
SiliconSystems’ Sales
Representative
Temperature Range:
• Blank = Commercial
• I = Industrial
Capacity: 32M = 32MB to 08G = 8GB
Form Factor:
• C = CF
• D = 2.5" Drive
• M = Module
• P = PC Card
SiliconSystems’ SiliconDrive

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PART NUMBERING

SSD-CXXX(I)-3150 DATA SHEET

PART NUMBERS
The following table lists the SiliconDrive’s part numbers.
Table 84: Part Numbers
Part Number

Capacity

SSD-C08G(I)-3150
SSD-C04G(I)-3150
SSD-C02G(I)-3150
SSD-C01G(I)-3150
SSD-C51M(I)-3150
SSD-C25M(I)-3150
SSD-C12M(I)-3150
SSD-C64M(I)-3150
SSD-C32M(I)-3150

8GB
4GB
2GB
1GB
512MB
256MB
128MB
64MB
32MB

SAMPLE LABEL
Standard Back Label with
Lot Code Information

Front Label

SiliconSystems, Inc.

SiliconDrive

8GB

8GB
SSD-C08G(I)-3150
A123/3150

Figure 8: Sample Label

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Silicon Image Silicondrive Cf Ssd C08Gi 3150 Users Manual

SSD-C08G(I)-3150 to the manual 6cbf3487-d32f-458a-833b-3c9b81a9a264

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