Smsc Lan9420 Users Manual LAN9420/LAN9420i Single Chip Ethernet Controller With HP And Auto MDIX Support PCI Interface Datasheet

2015-02-05

• Chapter 1 Introduction
  • 1.1 Block Diagrams
    • Figure 1.1 System Level Block Diagram
    • Figure 1.2 LAN9420/LAN9420i Internal Block Diagram
  • 1.2 General Description
  • 1.3 PCI Bridge
  • 1.4 DMA Controller
  • 1.5 Ethernet MAC
  • 1.6 Ethernet PHY
  • 1.7 System Control Block
    • 1.7.1 Interrupt Controller
    • 1.7.2 PLL and Power Management
    • 1.7.3 EEPROM Controller
    • 1.7.4 GPIO/LED Controller
    • 1.7.5 General Purpose Timer
    • 1.7.6 Free Run Counter
  • 1.8 Control and Status Registers (CSR)
• Chapter 2 Pin Description and Configuration
  • Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View)
  • 2.1 Pin List
    • Table 2.1 PCI Bus Interface Pins
    • Table 2.2 EEPROM
    • Table 2.3 GPIO and LED Pins
    • Table 2.4 Configuration Pins
    • Table 2.5 PLL and Ethernet PHY Pins
    • Table 2.6 Power and Ground Pins
    • Table 2.7 No-Connect Pins
    • Table 2.8 128-VTQFP Package Pin Assignments
  • 2.2 Buffer Types
• Chapter 3 Functional Description
  • 3.1 Functional Overview
  • 3.2 PCI Bridge (PCIB)
    • 3.2.1 PCI Bridge (PCIB) Block Diagram
      • Figure 3.1 PCI Bridge Block Diagram
    • 3.2.2 PCI Interface Environments
      • Figure 3.2 Device Operation
    • 3.2.3 PCI Master Interface
    • 3.2.4 PCI Target Interface
      • Table 3.1 PCI Address Spaces
      • Figure 3.3 CSR Double Endian Mapping
      • Figure 3.4 I/O Bar Mapping
    • 3.2.5 Interrupt Gating Logic
      • Figure 3.5 Interrupt Generation
  • 3.3 System Control Block (SCB)
    • 3.3.1 Interrupt Controller
      • Figure 3.6 Interrupt Controller Block Diagram
    • 3.3.2 Wake Event Detection Logic
    • 3.3.3 General Purpose Timer (GPT)
    • 3.3.4 Free-Run Counter (FRC)
    • 3.3.5 EEPROM Controller (EPC)
      • Table 3.2 EEPROM Format
      • Table 3.3 EEPROM Variable Defaults
      • Figure 3.7 EEPROM Access Flow Diagram
      • Figure 3.8 EEPROM ERASE Cycle
      • Figure 3.9 EEPROM ERAL Cycle
      • Figure 3.10 EEPROM EWDS Cycle
      • Figure 3.11 EEPROM EWEN Cycle
      • Figure 3.12 EEPROM READ Cycle
      • Figure 3.13 EEPROM WRITE Cycle
      • Figure 3.14 EEPROM WRAL Cycle
      • Table 3.4 Required EECLK Cycles
    • 3.3.6 System Control and Status Registers (SCSR)
  • 3.4 DMA Controller (DMAC)
    • 3.4.1 DMA Controller Architecture
    • 3.4.2 Data Descriptors and Buffers
      • Figure 3.15 Ring and Chain Descriptor Structures
      • Figure 3.16 Receive Descriptor
      • Table 3.5 RDES0 Bit Fields
      • Table 3.6 RDES1 Bit Fields
      • Table 3.7 RDES2 Bit Fields
      • Table 3.8 RDES3 Bit Fields
      • Figure 3.17 Transmit Descriptor
      • Table 3.9 TDES0 Bit Fields
      • Table 3.10 TDES1 Bit Fields
      • Table 3.11 TDES2 Bit Fields
      • Table 3.12 TDES3 Bit Fields
    • 3.4.3 Initialization
    • 3.4.4 Transmit Operation
    • 3.4.5 Receive Operation
    • 3.4.6 Receive Descriptor Acquisition
    • 3.4.7 Suspend State Behavior
    • 3.4.8 Stopping Transmission and Reception
    • 3.4.9 TX Buffer Fragmentation Rules
    • 3.4.10 DMAC Interrupts
    • 3.4.11 DMAC Control and Status Registers (DCSR)
  • 3.5 10/100 Ethernet MAC
    • 3.5.1 Flow Control
    • 3.5.2 Virtual Local Area Network (VLAN) Support
      • Figure 3.18 VLAN Frame
    • 3.5.3 Address Filtering Functional Description
      • Table 3.13 Address Filtering Modes
    • 3.5.4 Wakeup Frame Detection
      • Table 3.14 Wakeup Frame Filter Register Structure
      • Table 3.15 Filter i Byte Mask Bit Definitions
      • Table 3.16 Filter i Command Bit Definitions
      • Table 3.17 Filter i Offset Bit Definitions
      • Table 3.18 Filter i CRC-16 Bit Definitions
      • Table 3.19 Wakeup Generation Cases
    • 3.5.5 Receive Checksum Offload Engine (RXCOE)
      • Figure 3.19 RXCOE Checksum Calculation
      • Figure 3.20 Type II Ethernet Frame
      • Figure 3.21 Ethernet Frame with VLAN Tag
      • Figure 3.22 Ethernet Frame with Length Field and SNAP Header
      • Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header
      • Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP Header
    • 3.5.6 Transmit Checksum Offload Engine (TXCOE)
      • Table 3.20 TX Checksum Preamble
    • 3.5.7 MAC Control and Status Registers (MCSR)
  • 3.6 10/100 Ethernet PHY
    • Figure 3.25 100BASE-TX Data Path
    • 3.6.1 100BASE-TX Transmit
      • Table 3.21 4B/5B Code Table
      • Figure 3.26 Receive Data Path
    • 3.6.2 100BASE-TX Receive
    • 3.6.3 10BASE-T Transmit
    • 3.6.4 10BASE-T Receive
    • 3.6.5 Auto-negotiation
    • 3.6.6 Parallel Detection
    • 3.6.7 HP Auto-MDIX
      • Figure 3.27 Direct Cable Connection vs. Cross-Over Cable Connection
    • 3.6.8 PHY Power-Down Modes
    • 3.6.9 PHY Resets
    • 3.6.10 Required Ethernet Magnetics
    • 3.6.11 PHY Registers
  • 3.7 Power Management
    • 3.7.1 Overview
    • 3.7.2 Related External Signals and Power Supplies
    • 3.7.3 Device Clocking
    • 3.7.4 Power States
      • Figure 3.28 LAN9420/LAN9420i Device Power States
    • 3.7.5 Resets
      • Table 3.22 Reset Map
      • Table 3.23 PHY Resets
    • 3.7.6 Detecting Power Management Events
      • Figure 3.29 Wake Event Detection Block Diagram
    • 3.7.7 Enabling Link Status Change (Energy Detect) Wake Events
• Chapter 4 Register Descriptions
  • Figure 4.1 LAN9420/LAN9420i CSR Memory Map
  • 4.1 Register Nomenclature
    • Table 4.1 Register Bit Types
  • 4.2 System Control and Status Registers (SCSR)
    • Table 4.2 System Control and Status Register Addresses
    • 4.2.1 ID and Revision (ID_REV)
    • 4.2.2 Interrupt Control Register (INT_CTL)
    • 4.2.3 Interrupt Status Register (INT_STS)
    • 4.2.4 Interrupt Configuration Register (INT_CFG)
    • 4.2.5 General Purpose Input/Output Configuration Register (GPIO_CFG)
      • Table 4.3 EEPROM Enable Bit Definitions
    • 4.2.6 General Purpose Timer Configuration Register (GPT_CFG)
    • 4.2.7 General Purpose Timer Current Count Register (GPT_CNT)
    • 4.2.8 Bus Master Bridge Configuration Register (BUS_CFG)
    • 4.2.9 Power Management Control Register (PMT_CTRL)
    • 4.2.10 Free Run Counter (FREE_RUN)
    • 4.2.11 EEPROM Command Register (E2P_CMD)
    • 4.2.12 EEPROM Data Register (E2P_DATA)
  • 4.3 DMAC Control and Status Registers (DCSR)
    • Table 4.4 DMAC Control and Status Register (DCSR) Map
    • 4.3.1 Bus Mode Register (BUS_MODE)
    • 4.3.2 Transmit Poll Demand Register (TX_POLL_DEMAND)
    • 4.3.3 Receive Poll Demand Register (RX_POLL_DEMAND)
    • 4.3.4 Receive List Base Address Register (RX_BASE_ADDR)
    • 4.3.5 Transmit List Base Address Register (TX_BASE_ADDR)
    • 4.3.6 DMA Controller Status Register (DMAC_STATUS)
    • 4.3.7 DMA Controller Control (Operation Mode) Register (DMAC_CONTROL)
    • 4.3.8 DMA Controller Interrupt Enable Register (DMAC_INTR_ENA)
    • 4.3.9 Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)
    • 4.3.10 Current Transmit Buffer Address Register (TX_BUFF_ADDR)
    • 4.3.11 Current Receive Buffer Address Register (RX_BUFF_ADDR)
  • 4.4 MAC Control and Status Registers (MCSR)
    • Table 4.5 MAC Control and Status Register (MCSR) Map
    • 4.4.1 MAC Control Register (MAC_CR)
    • 4.4.2 MAC Address High Register (ADDRH)
    • 4.4.3 MAC Address Low Register (ADDRL)
      • Table 4.6 ADDRL, ADDRH Byte Ordering
      • Figure 4.2 Example ADDRL, ADDRH Address Ordering
    • 4.4.4 Multicast Hash Table High Register (HASHH)
    • 4.4.5 Multicast Hash Table Low Register (HASHL)
    • 4.4.6 MII Access Register (MII_ACCESS)
    • 4.4.7 MII Data Register (MII_DATA)
    • 4.4.8 Flow Control Register (FLOW)
    • 4.4.9 VLAN1 Tag Register (VLAN1)
    • 4.4.10 VLAN2 Tag Register (VLAN2)
    • 4.4.11 Wakeup Frame Filter (WUFF)
    • 4.4.12 Wakeup Control and Status Register (WUCSR)
    • 4.4.13 Checksum Offload Engine Control Register (COE_CR)
  • 4.5 PHY Registers
    • Table 4.7 PHY Control and Status Registers
    • 4.5.1 Basic Control Register
    • 4.5.2 Basic Status Register
    • 4.5.3 PHY Identifier 1
    • 4.5.4 PHY Identifier 2
    • 4.5.5 Auto Negotiation Advertisement
    • 4.5.6 Auto Negotiation Link Partner Ability
    • 4.5.7 Auto Negotiation Expansion
    • 4.5.8 Mode Control/Status
    • 4.5.9 Special Modes
      • Table 4.8 MODE Control
    • 4.5.10 Special Control/Status Indications
    • 4.5.11 Interrupt Source Flag
    • 4.5.12 Interrupt Mask
    • 4.5.13 PHY Special Control/Status
  • 4.6 PCI Configuration Space CSR (CONFIG CSR)
    • Table 4.9 PCI Configuration Space CSR (CONFIG CSR) Address Map
    • Table 4.10 Standard PCI Header Registers Supported
    • 4.6.1 PCI Power Management Capabilities Register (PCI_PMC)
    • 4.6.2 PCI Power Management Control and Status Register (PCI_PMCSR)
• Chapter 5 Operational Characteristics
  • 5.1 Absolute Maximum Ratings*
  • 5.2 Operating Conditions**
  • 5.3 Power Consumption
    • 5.3.1 D0 - Normal Operation with Ethernet Traffic
      • Table 5.1 D0 - Normal Operation - Supply and Current (Typical)
    • 5.3.2 D3 - Enabled for Wake Up Packet Detection
      • Table 5.2 D3 - Enabled for Wake Up Packet Detection - Supply and Current (Typical)
    • 5.3.3 D3 - Enabled for Link Status Change Detection (Energy Detect)
      • Table 5.3 D3 - Enabled for Link Status Change Detection - Supply and Current (Typical)
    • 5.3.4 D3 - PHY in General Power Down Mode
      • Table 5.4 D3 - PHY in General Power Down Mode - Supply and Current (Typical)
    • 5.3.5 Maximum Power Consumption
      • Table 5.5 Maximum Power Consumption - Supply and Current (Maximum)
  • 5.4 DC Specifications
    • Table 5.6 I/O Buffer Characteristics
    • Table 5.7 100BASE-TX Transceiver Characteristics
    • Table 5.8 10BASE-T Transceiver Characteristics
  • 5.5 AC Specifications
    • 5.5.1 Equivalent Test Load (Non-PCI Signals)
      • Figure 5.1 Output Equivalent Test Load
  • 5.6 PCI Clock Timing
    • Figure 5.2 PCI Clock Timing
    • Table 5.9 PCI Clock Timing Values
  • 5.7 PCI I/O Timing
    • Figure 5.3 PCI I/O Timing
    • Table 5.10 PCI I/O Timing Measurement Conditions
    • Table 5.11 PCI I/O Timing Values
  • 5.8 EEPROM Timing
    • Figure 5.4 EEPROM Timing
    • Table 5.12 EEPROM Timing Values
  • 5.9 Clock Circuit
    • Table 5.13 LAN9420/LAN9420i Crystal Specifications
• Chapter 6 Package Outline
  • 6.1 128-VTQFP Package
    • Figure 6.1 LAN9420/LAN9420i 128-VTQFP Package Definition
    • Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions
    • Figure 6.2 LAN9420/LAN9420i 128-VTQFP Recommended PCB Land Pattern
• Chapter 7 Revision History
  • Table 7.1 Customer Revision History