Smsc Usb3250 Users Manual Hi Speed USB Device Transceiver With UTMI Interface Data Brief

USB3250 to the manual 8884f095-0a95-4f98-95c4-3744b81f8e4b

2015-02-05

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USB3250
Hi-Speed USB Device
Transceiver with UTMI
Interface

PRODUCT FEATURES

Data Brief

USB-IF "Hi-Speed" certified to USB 2.0 electrical
specification
Interface compliant with the UTMI specification
(60MHz 8-bit unidirectional interface or 30MHz 16-bit
bidirectional interface)
Supports 480Mbps High Speed (HS) and 12Mbps
Full Speed (FS) serial data transmission rates
Integrated 45Ω and 1.5kΩ termination resistors
reduce external component count
Internal short circuit protection of DP and DM lines
On-chip oscillator operates with low cost 12MHz
crystal
Robust and low power digital clock and data recovery
circuit
SYNC and EOP generation on transmit packets and
detection on receive packets
NRZI encoding and decoding
Bit stuffing and unstuffing with error detection
Supports the USB suspend state, HS detection, HS
Chirp, Reset and Resume
Support for all test modes defined in the USB 2.0
specification
Draws 72mA (185mW) maximum current
consumption in HS mode - ideal for bus powered
functions
On-die decoupling capacitance and isolation for
immunity to digital switching noise
Available in a 56-pin QFN package
Full industrial operating temperature range from
-40oC to +85oC (ambient)

SMSC USB3250

Applications
The Universal Serial Bus (USB) is the preferred
interface to connect Hi-Speed PC peripherals.
Digital Still and Video Cameras
MP3 Players
External Hard Drives
Scanners
Entertainment Devices
Printers
Test and Measurement Systems
POS Terminals
Set Top Boxes

PRODUCT PREVIEW

Revision 1.7 (05-11-07)

Hi-Speed USB Device Transceiver with UTMI Interface

ORDER NUMBER:
USB3250-ABZJ FOR 56 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE, 8 X 8 X 0.85MM

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2007 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.7 (05-11-07)

PRODUCT PREVIEW

SMSC USB3250

Hi-Speed USB Device Transceiver with UTMI Interface

General Description
The USB3250 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is
available in a 56 pin QFN.
The USB3250 is a USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary
technology results in low power dissipation, which is ideal for building a bus powered USB 2.0
peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit bidirectional parallel
interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It
supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol
at 12Mbps.
All required termination for the USB 2.0 Transceiver is internal. Internal 5.25V short circuit protection
of DP and DM lines is provided for USB compliance.
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.

Block Diagram
XO

VDD1.8

VDD3.3

PWR
CONTROL
TX
LOGIC

TX
RPU_EN
1.5k Ω

TX State
Machine

VPO
VMO

Parallel to
Serial
Conversion

DATABUS16_8
RESET

XCVRSELECT

HS_DATA
HS_DRIVE_ENABLE
HS_CS_ENABLE

NRZ
Encode

TERMSELECT

FS
TX

OEB

Bit Stuff

SUSPENDN

System
Clocking

PLL and
XTAL OSC

HS
TX

OPMODE[1:0]

LINESTATE[1:0]

TXREADY
VALIDH

RXVALID
RXACTIVE

RX
LOGIC

FS
SE+

RX State
Machine

VP
VM

Serial to
Parallel
Conversion

FS
SE-

Clock
Recovery Unit
Clock
and
Data
Recovery

Bit Unstuff
NRZI
Decode

RXERROR

FS
RX
MUX

DATA[15:0] *

TXVALID

UTMI Interface

CLKOUT

Elasticity
Buffer

BIASING
Bandgap Voltage Reference

HS
RX

HS
SQ

RBIAS

Current Reference

Figure 1 USB3250 Functional Block Diagram
SMSC USB3250

PRODUCT PREVIEW

Revision 1.7 (05-11-07)

Hi-Speed USB Device Transceiver with UTMI Interface

VALIDH

RXVALID

TXVALID

DATA[0]

VDD3.3

CLKOUT

VSS

RXACTIVE
50

TXREADY
51

VDD1.8

RXERROR

DATABUS16_8
54

VSS
55

VSS
56

Pin Configuration

VSSA

DATA[1]

DATA[2]

DATA[3]

DATA[4]

VDD1.8

DATA[5]

DATA[6]

DATA[7]

DATA[8]

VSS

DATA[9]

DATA[10]

DATA[11]

DATA[12]

RBIAS

VDDA3.3

OPMODE[0]

LINESTATE[1]

LINESTATE[0]

VDD1.8

RESET

DATA[15]

DATA[14]

DATA[13]

VDD3.3

VSS

OPMODE[1]

SUSPENDN

VDDA1.8

TERMSELECT

XCVRSELECT

VSSA

USB 2.0
USB3250
PHY IC

VDD1.8

VDDA3.3

VDD3.3

Figure 2 56-Pin USB3250 Pin Configuration (Top View)

Revision 1.7 (05-11-07)

PRODUCT PREVIEW

SMSC USB3250

Hi-Speed USB Device Transceiver with UTMI Interface

Pin Description Tables
Table 1 System Interface Pins

DIRECTION

ACTIVE
LEVEL

RESET

Input

High

Reset. Reset all state machines. After coming out of reset, must
wait 5 rising edges of clock before asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to CLKOUT.
De-assertion of Reset: Must be synchronous to CLKOUT unless
RESET is asserted longer than two periods of CLKOUT.

XCVRSELECT

Input

N/A

Transceiver Select. This signal selects between the FS and HS
transceivers:
0: HS transceiver enabled
1: FS transceiver enabled.

TERMSELECT

Input

N/A

Termination Select. This signal selects between the FS and HS
terminations:
0: HS termination enabled
1: FS termination enabled

SUSPENDN

Input

Low

Suspend. Places the transceiver in a mode that draws minimal
power from supplies. Shuts down all blocks not necessary for
Suspend/Resume operation. While suspended, TERMSELECT
must always be in FS mode to ensure that the 1.5k Ω pull-up on
DP remains powered.
0: Transceiver circuitry drawing suspend current
1: Transceiver circuitry drawing normal current

Output

Rising Edge

System Clock. This output is used for clocking receive and
transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit
mode). When in 8-bit mode, this specification refers to CLKOUT
as CLK60. When in 16-bit mode, CLKOUT is referred to as
CLK30.

Input

N/A

Operational Mode. These signals select between the various
operational modes:
[1] [0] Description
0
0
0: Normal Operation
0
1
1: Non-driving (all terminations removed)
1
0
2: Disable bit stuffing and NRZI encoding
1
1
3: Reserved

LINESTATE[1:0]

Output

N/A

Line State. These signals reflect the current state of the USB
data bus in FS mode, with [0] reflecting the state of DP and [1]
reflecting the state of DM. When the device is suspended or
resuming from a suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0
0
0: SE0
0
1
1: J State
1
0
2: K State
1
1
3: SE1

DATABUS16_8

Input

N/A

Databus Select. Selects between 8-bit and 16-bit data transfers.
0: 8-bit data path enabled. VALIDH is undefined. CLKOUT =
60MHz.
1: 16-bit data path enabled. CLKOUT = 30MHz.

NAME

CLKOUT

OPMODE[1:0]

SMSC USB3250

DESCRIPTION

PRODUCT PREVIEW

Revision 1.7 (05-11-07)

Hi-Speed USB Device Transceiver with UTMI Interface

Table 2 Data Interface Pins

NAME

DIRECTION

ACTIVE
LEVEL

DESCRIPTION

Bidir

N/A

DATA BUS. 16-BIT BIDIRECTIONAL MODE.

DATA[15:0]

TXVALID

RXVALID

VALIDH

DATA[15:0]

Not used

DATA[7:0] output is valid
for receive
VALIDH is an output

DATA[15:0] output is
valid for receive
VALIDH is an output

DATA[7:0] input is valid
for transmit
VALIDH is an input

DATA[15:0] input is valid
for transmit
VALIDH is an input

DATA BUS. 8-BIT UNIDIRECTIONAL MODE.

TXVALID

Input

High

TXVALID

RXVALID

DATA[15:0]

Not used

DATA[15:8] output is valid for receive

DATA[7:0] input is valid for transmit

Transmit Valid. Indicates that the TXDATA bus is valid for
transmit. The assertion of TXVALID initiates the transmission of
SYNC on the USB bus. The negation of TXVALID initiates EOP
on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)
must not be changed on the de-assertion or assertion of TXVALID.
The PHY must be in a quiescent state when these inputs are
changed.

TXREADY

VALIDH

Output

High

Transmit Data Ready. If TXVALID is asserted, the SIE must
always have data available for clocking into the TX Holding
Register on the rising edge of CLKOUT. TXREADY is an
acknowledgement to the SIE that the transceiver has clocked the
data from the bus and is ready for the next transfer on the bus. If
TXVALID is negated, TXREADY can be ignored by the SIE.

Bidir

N/A

Transmit/Receive High Data Bit Valid (used in 16-bit mode
only). When TXVALID = 1, the 16-bit data bus direction is
changed to inputs, and VALIDH is an input. If VALIDH is asserted,
DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0]
is valid for transmission. The DATA bus is driven by the SIE.
When TXVALID = 0 and RXVALID = 1, the 16-bit data bus
direction is changed to outputs, and VALIDH is an output. If
VALIDH is asserted, the DATA[15:0] outputs are valid for receive.
If deasserted, only DATA[7:0] is valid for receive. The DATA bus
is read by the SIE.

RXVALID

Output

High

Receive Data Valid. Indicates that the RXDATA bus has received
valid data. The Receive Data Holding Register is full and ready to
be unloaded. The SIE is expected to latch the RXDATA bus on the
rising edge of CLKOUT.

RXACTIVE

Output

High

Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.

RXERROR

Output

High

Receive Error. 0: Indicates no error. 1: Indicates a receive error
has been detected. This output is clocked with the same timing as
the RXDATA lines and can occur at anytime during a transfer.

Revision 1.7 (05-11-07)

PRODUCT PREVIEW

SMSC USB3250

Hi-Speed USB Device Transceiver with UTMI Interface

Table 3 USB I/O Pins

DIRECTION

ACTIVE
LEVEL

I/O

N/A

USB Positive Data Pin.

I/O

N/A

USB Negative Data Pin.

NAME

DESCRIPTION

Table 4 Biasing and Clock Oscillator Pins

DIRECTION

ACTIVE
LEVEL

RBIAS

Input

N/A

External 1% bias resistor. Requires a 12KΩ resistor to ground.
Used for setting HS transmit current level and on-chip termination
impedance.

XI/XO

Input

N/A

External crystal. 12MHz crystal connected from XI to XO.

NAME

DESCRIPTION

Table 5 Power and Ground Pins

NAME

DIRECTION

ACTIVE
LEVEL

DESCRIPTION

VDD3.3

N/A

3.3V Digital Supply. Powers digital pads. See Note 2.1

VDD1.8

N/A

1.8V Digital Supply. Powers digital core.

VSS

N/A

Digital Ground. See Note 2.2

VDDA3.3

N/A

3.3V Analog Supply. Powers analog I/O and 3.3V analog
circuitry.

VDDA1.8

N/A

1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 2.1

VSSA

N/A

Analog Ground. See Note 2.2

Note 2.1

A Ferrite Bead (with DC resistance <.5 Ohms) is recommended for filtering between both
the VDD3.3 and VDDA3.3 supplies and the VDD1.8 and VDDA1.8 Supplies.

Note 2.2

All VSS and VSSA are bonded to the exposed pad under the IC in the package. The
exposed pad must be connected to solid GND plane on printed circuit board.

SMSC USB3250

PRODUCT PREVIEW

Revision 1.7 (05-11-07)

Hi-Speed USB Device Transceiver with UTMI Interface

Application Diagram
VDD3.3

VDD1.8

UTMI

Voltage
Regulator

1uF

10uF

1uF

44
42
41
40
39
37
36
35
34
32
31
30
29
27
26
25

DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7

TXVALID
TXREADY
RXACTIVE
RXVALID
RXERROR
VALIDH
DATABUS16_8

17
XCVRSELECT
18
TERMSELECT
13
SUSPENDN
24
RESET

DATA 8
DATA 9
DATA 10
DATA 11
DATA 12
DATA 13
DATA 14
DATA 15

20
OPMODE 0
19
OPMODE 1
LINESTATE 0 22
LINESTATE 1 21

USB
C LOAD

45
51
50
46
52
47
54

CLKOUT 49
6
RBIAS
DP

12KΩ

1ΜΩ

12MHz
Crystal

USB-B

C LOAD
POWER
12 VDDA1.8
Ferrite Bead
10uF

16
VDD1.8
23
VDD1.8
38
VDD1.8
53
VDD1.8

VDD1.8

4 VDDA3.3
7
VDDA3.3
Ferrite Bead

15 VDD3.3
28 VDD3.3
43 VDD3.3

VSSA
VSSA
VSSA
VSSA

VSS
VSS
VSS
VSS
VSS

1
5
8
9

14
33
48
55
56

VDD3.3

GND

Figure 3 Application Diagram for 56-pin QFN Package

Revision 1.7 (05-11-07)

PRODUCT PREVIEW

SMSC USB3250

RE VI SIO N HIST ORY
R EV ISION

T E R M IN A L #1
IDEN T IF IE R AR EA
(D /2 X E/2)

D E SC R I PTIO N

D ATE

R E LE AS E D BY

IN IT IA L R ELEASE

2/07/04

S .K .I LIEV

R EM O V E "PR E LIM INARY" NO TE

10/7/04

S .K .I LIEV

7/2/ 05

S .K .I LIEV

L(M A X ) F R O M 0.55 T O 0.50. AD D E D D2/E2 VARIATIO NS TABLE

3
T E R M IN A L #1
IDEN T IF IER AR EA
(D 1 /2 X E 1/2)
E1

E XP O S E D PAD

56X L

56X b

4X 45°X 0.6 M A X (O PTIONAL)

9
PRODUCT PREVIEW

T OP V IEW

BOT TO M VIEW

A
A1

S ID E VIEW
D 2 / E2 V ARIATIONS
C ATAL OG P ART

N O T ES:
1 . A LL DIM ENS IO N S A RE IN M IL LIM ETER.
2 . PO SITIO N T OL ER AN CE O F EA CH TER M INA L AN D EX PO SE D PA D IS ± 0 .0 5m m AT M AXIM UM M ATERIAL
C ON DITION . DIM E NS IO NS "b" A PP LIES T O PL AT ED T ER M INA LS A ND IT IS M EASURED BETW EEN 0.15 AND
0.3 0 m m F RO M TH E TERM INA L TIP.
3 . DE TA IL S OF T ER M INA L #1 IDE NTIF IE R ARE OP TION AL B UT M US T BE L OC AT ED W IT HIN TH E AREA INDICATED.
U N LES S O TH E R W ISE SPECIFIED
D IM EN SIO N S AR E IN M ILLIMETERS
AN D T O LERANCES ARE:

SMSC USB3250

D E C I MAL
±0.1
X .X
±0.05
X .XX
X .X XX ±0.025

T H IRD A N G LE P R O JE CT ION

80 A R KA Y DRIVE
H AU P PA U G E , N Y 11788
U SA

A N G U LAR
± 1°

T IT LE

N A ME

D I M A N D T O L P ER A SM E Y14.5M - 1994
M A T E R IAL

3-D V IE W S
F IN ISH

P R I N T W I TH "SC ALE TO FIT"
D O N O T SC A LE DRAW ING

D A TE

DR AWN

S .K.ILIEV

2 /06/04

C H EC KED

S .K.ILIEV

D W G N U M BER

S TD C OM PLIA N CE

S C ALE

2 /07/04

R EV

M O -56-Q FN -8x8

2 /07/04

A PPR OVED

S .K.ILIEV

P AC KA G E O UTLINE
56 TE RM IN AL Q FN , 8x8m m BO DY , 0.5m m PITCH

1:1

J EDEC : MO -220

C
S H EET

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Hi-Speed USB Device Transceiver with UTMI Interface

Revision 1.7 (05-11-07)

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