TCL Technoly Electronics PS000012 Bluetooth Module User Manual Product Data Sheet

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Document ID	2430058
Application ID	3zPAQd74gKAn4MR/YL5wYQ==
Document Description	TBM-CBC5_User Manual_REV2
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Document Type	User Manual
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Date Submitted	2014-10-29 00:00:00
Date Available	2014-10-29 00:00:00
Creation Date	2011-02-16 14:55:58
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Document Lastmod	2014-10-28 20:58:10
Document Title	Product Data Sheet
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Document Author:	Bluegiga

TONLY
TBM-CBC5
DATA SHEET
Monday, 29 September 2014
Version 1.1
Datasheet by Peter.huang
Revision History
Date
Version
Description
2013-10-21
V1.0
2014-09-29
V1.1
n Correct 8DQPSK to 8DPSK
First Release
Author
TBM–CBC5 Bluetooth Audio Module
FEATURES:
DESCRIPTION:
•
TBM–CBC5 is first generation of TCL Bluetooth
modules.It provides highest level of
integration with integrated 2.4GHz radio, DSP,
battery charger, stereo codec mono
and
stereo audio applications.TBM–CBC5 is also
ready to support the lates Bluetooth 3.0 standard
•
•
•
•
•
•
The embedded DSP core allows enhancement
of the product with features such as advanced
audio decoding (MP3, AAC, AAC+), echo
cancellation, noise reduction, and data
manipulation.
•
TCL’s TONLY flexible firmware enables
device manufacturers to easily add wireless,
secure, and standard- based Bluetooth
connectivity into new or existing applications
with very limited development and
manufacturing effort.
TBM–CBC5 Bluetooth module Solution
For mono and Stereo Audio Solutions
Integrated DSP, Stereo Codec, and
Battery Charger
Bluetooth 3.0 + EDR Compliant
Class 2 - Range up to 30 Meters
Temperature range from
-30C to +85C
Low Power Consumption
TCL TONLY Firmware for Controlling
Connections and Configuring Settings
Supported Bluetooth Profiles: A2DP,
AVRCP, HFP, HFP-AG, SPP, OPP, FTP,
HSP, DUN, PBAP and HID ect...
40-BTP518HFD4G
APPLICATIONS:
•
•
•
•
•
•
•
High quality wireless stereo headsets
Wireless mono headsets
Wireless speakers
USB multimedia dongles
MP3 players
VoIP handsets
Hands-free car kits
Size: 13.5*21 mm
2 Block Diagram and Descriptions
Flash
BC05-MM
UART/USB
RAM
2.4
GHz
Radio
Baseband
DSP
PIO
I/O
Audio In/Out
MCU
PCM/I2S/SPDIF
Kalimba DSP
SPI
XTAL
Reset
circuitry
Figure 1: Block diagram of TBM–CBC5
BC05-MM
The BlueCore05-MM is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems. It provides
a fully compliant Bluetooth system to v3.0+EDR of the specification for data and voice.
BlueCore05-MM contains the Kalimba DSP co-processor with double the MIPS of BlueCore03-MM,
supporting enhanced audio applications. BlueCore05-MM integrates a 16-bit stereo codec and it has a
fully differential audio interface with a low noise microphone bias.
Crystal
The crystal oscillates at 26MHz.
Flash
Flash memory is used for storing the Bluetooth protocol stack and Virtual Machine applications. It can
also be used as an optional external RAM for memory-intensive applications.
Balanced Filter
Combined balun and filter changes the balanced input/output signal of the module to unbalanced signal
of the antenna. The filter is a band pass filter (ISM band).
Antenna
TBM–CBC5 uses ceramic chip antenna with high dielectric constant, which makes the antenna very
insensitive to surrounding environment and thus gives high design freedom around the antenna.
USB
The USB interface is a full speed Universal Serial Bus (USB) interface for communicating with other
compatible digital devices.TBM–CBC5 acts as a USB peripheral, responding to requests from a Master host
controller such as a Personal Computer (PC).
Synchronous Serial Interface
This interface is a synchronous serial port interface (SPI) for interfacing with other digital devices. The
SPI port can be used for system debugging. It can also be used for programming the Flash memory.
UART
This interface is a standard Universal Asynchronous Receiver Transmitter (UART) interface for
communicating with other serial devices.
PCM / I2S / SPDIF Interface
This interface is a bi-directional serial programmable audio interface supporting PCM, I2S and SPDIF
formats.
Audio Interface
The audio interface of TBM–CBC5 has fully differential inputs and outputs and a microphone bias output. A
high-quality stereo audio Bluetooth application can be implemented with minimum amount of external
components.
Programmable I/O
BTP518B has a total of 10 digital programmable I/O terminals. These are controlled by the firmware running
on the device.
Reset
TBM–CBC5 has a reset circuitry that is used to reset the module in the startup to ensure proper operation of
the flash memory. Alternatively, the reset can be externally driven by using a TBM–CBC5 reset pin.
802.11 Coexistence Interface
Dedicated hardware is provided to implement a variety of coexistence schemes. Channel skipping AFH
(Adaptive Frequency Hopping), priority signaling, channel signaling, and host passing of channel
instructions are all supported. The features are configured in firmware. Since the details of some
methods are proprietary (e.g. Intel WCS)
3 Electrical Characteristics
Absolute maximum ratings
Min
-40
-30
-0.4
-0.4
-0.4
-0.4
Storage temperature
Operating temperature
VDD_IO
VDD_BAT
VDD_CHG
Terminal voltages
Max
85
85
3.6
4.4
6.5
Vdd + 0,4
Unit
°C
°C
The module should not continuously run under these conditions. Exposure to absolute maximum rating conditions
for extended periods of time may affect reliability and cause permanent damage to the device.
Table 1: Absolute maximum ratings
Recommended operating conditions
Min
-40
1.7
2.5
Operating temperature
VDD_IO
VDD_BAT
VDD_CHG
Terminal voltages
Table 2: Recommended operating conditions
Max
85
3.6
4.4
6.5
VDD
Unit
°C
Terminal characteristics
Min
Typ
Max
Unit
VIL input logic level low
-0.4
0.25xVDD
VIH input logic level high
0.625xVDD
Vdd + 0.3
VOL output logic level low
0.125
VOH output logic level high
Reset terminal
0.75xVDD
VDD
0.64
0.85
1.5
I/O voltage levels
VTH,res threshold voltage
RIRES input resistance
220
kΩ
CIRES input capacitance
Input and tri-state current with
Strong pull-up
Strong pull-down
Weak pull-up
Weak pull-down
I/O pad leakage current
LED driver pad
Off current
220
nF
-100
10
-5
0.2
-1
-40
40
-1
-10
100
-0.2
µΑ
µΑ
µΑ
µΑ
µΑ
µΑ
On resistance (VPAD < 0.5 V)
20
33
Ω
On resistance, pad enabled by battery charger
(VPAD < 0.5 V)
20
50
Ω
Table 3: Terminal characteristics
Battery charger
Battery charger
VDD_CHG
Charging mode (VDD_BAT rising to 4.2 V)
(a)
Supply current
Maximum setting
Battery trickle charge
(b) (c)
current
Minimum setting
(e)
Headroom > 0.7 V
Maximum battery fast
(d) (c)
charge current
Headroom = 0.3 V
Headroom > 0.7 V
Minimum battery fast
(d) (c)
charge current
Headroom = 0.3 V
Trickle charge voltage threshold
Float voltage (with correct trim value set),
(f)
VFLOAT
(f)
Float voltage trim step size
Battery charge termination current, as a
percentage of the fast charge current
Min
4.5
Typ
Max
6.5
Unit
4.5
14
140
120
40
35
2.9
mA
mA
mA
mA
mA
mA
mA
4.17
4.2
4.23
50
mV
10
20
1.5
-5
200
mA
μA
mV
3.9
3.7
0.22
0.17
1.5
mA
μA
Standby Mode (BAT_P falling from 4.2V)
(a)
Supply current
Battery current
(g)
Battery recharge hysteresis
100
Shutdown Mode (VDD_CHG too low or disabled by firmware)
VDD_CHG underVDD_CHG rising
voltage
VDD_CHG falling
threshold
VDD_CHG - BAT_P
VDD_CHG rising
lockout
VDD_CHG falling
threshold
Supply current
Battery current
-1
(a)
Current into VDD_CHG - does not include current delivered to battery (I VDD_CHG - I BAT_P)
(b)
BAT_P < Float voltage
(c)
Charge current can be set in 16 equally spaced steps
(d)
Trickle charge threshold < BAT_P < Float voltage
(e)
Where headroom = VDD_CHG - BAT_P
(f)
Float voltage can be adjusted in 15 steps. Trim setting is determined in production test and must be loaded into the battery
charger by firmware during boot-up sequence
(g)
Hysteresis of (VFLOAT - BAT_P) for charging to restart
Table 4: Battery charger characteristics
Stereo CODEC Analogue to Digital Converter
Parameter
Resolution
Conditions
Input Sample Rate,
Fsample
Fsample
8 kHz
fin = 1kHz
11.025
kHz
B/W = 20Hz→20kHz
Signal to Noise
16 kHz
A-Weighted
Ratio, SNR
THD+N < 1%
22.050 kHz
150mVpk-pk input
32 kHz
44.1 kHz
Digital Gain
Digital Gain Resolution = 1/32dB
Analogue Gain
Analogue Gain Resolution = 3dB
Input full scale at maximum gain (differential)
Input full scale at minimum gain (differential)
3dB Bandwidth
Microphone mode input impedance
THD+N (microphone input) @ 30mV rms input
Min
Typ
Max
16
Unit
Bits
44.1
kHz
-24
-3
82
81
80
79
79
78
800
20
6.0
0.04
21.5
42
dB
dB
dB
dB
dB
dB
dB
dB
mV rms
mV rms
kHz
kΩ
Table 5: Stereo CODEC ADC characteristics
Stereo CODEC Digital to Analog Converter
Parameter
Resolution
Conditions
Input Sample
Rate, Fsample
Fsample
8 kHz
fin = 1kHz
11.025 kHz
B/W = 20Hz→20kHz
Signal to Noise
A-Weighted
16 kHz
Ratio, SNR
THD+N < 1%
22.050 kHz
150mVpk-pk input
32 kHz
44.1 kHz
Digital Gain
Digital Gain Resolution = 1/32dB
Analogue Gain
Analogue Gain Resolution = 3dB
Output voltage full scale swing (differential)
Resistive
Allowed Load
Capacitive
THD+N 100kΩ load
THD+N 16Ω load
SNR (Load = 16Ω, 0dBFS input relative to digital silence)
Min
Typ
Max
16
Unit
Bits
48
kHz
-24
16(8)
95
95
95
95
95
95
750
95
21.5
-21
OC
500
0.01
0.1
dB
dB
dB
dB
dB
dB
dB
dB
mV rms
Ω
pF
dB
Table 6: Stereo CODEC DAC characteristics
Radio characteristics and general specifications
Operating frequency range
Specification
Note
(2400 ... 2483,5) MHz
ISM Band
Lower quard band
2 MHz
Upper quard band
3,5 MHz
Carrier frequency
2402 MHz ... 2480 MHz
GFSK (1 Mbps)
∏/4 DQPSK (2Mbps)
8DPSK (3Mbps)
1600 hops/s, 1 MHz channel space
Modulation method
Hopping
Maximum data rate
f = 2402 + k,
k = 0...78
GFSK:
Asynchronous, 723.2 kbps
/ 57.6 kbps
Synchronous: 433.9 kbps /
433.9 kbps
∏/4 DQPSK:
Asynchronous, 1448.5
kbps / 115.2 kbps
Synchronous: 869.7 kbps /
869.7 kbps
Asynchronous, 2178.1
kbps / 177.2 kbps
Synchronous: 1306.9 kbps
/ 1306.9 kbps
8DPSK:
Receiving signal range
TBD
Typical condition
Receiver IF frequency
1.5 MHz
Center frequency
Min
Max
Transmission power
RF input impedance
Compliance
TBD
TBD
50 Ω
Bluetooth specification, version 2.1 + EDR
USB specification, version 1.1 (USB 2.0
compliant)
USB specification
TRM/CA/01/C (Output Power)
Packet Length Tested: DH5
Hopping ON
Average Power
Max Power
Min Power
Peak Power
Low
1.81
1.82
1.80
1.96
dBm
dBm
dBm
dBm
Med
1.98
2.00
1.98
2.15
dBm
dBm
dBm
dBm
High
1.91
1.92
1.90
2.10
Limits
dBm
dBm
dBm
dBm
< 20.00 dBm
> -6.00 dBm
< 23.00 dBm
RCV/CA/01/C (Single Sensitivity)
Power Level: -87.5 dBm, Dirty Tx Status: ON
Hopping ON
Overall BER
Overall FER
Any
0.03%
5.67%
Limits
<= 0.1%
<= 100%
Table 7: Radio characteristics and general specifications
4 TBM–CBC5 Pin Description
Figure 2: TBM–CBC5 connection diagram(top view)
NOTE: VREG_ENA pin is only available with the production version of the module. With engineering
samples the VREG_ENA is internally connected to VDD_BAT.
4.1 Device Terminal Functions
DGND
Connect digital GND pins to the ground plane of the PCB.
VDD_IO
Supply voltage connection for the digital I/Os of the module. Supply voltage at this pin can vary between
1.8 V and 3.3 V. Output voltage swing at the digital terminals ofTBM–CBC5 2 is 0 to VDD_IO.
VDD_BAT
Input for an internal 1.8 V switched mode regulator combined with output of the internal battery charger.
See chapter 5.3 for detailed description for the charger. When not powered from a battery, VDD_IO and
VDD_BAT can be combined to a single 3.3 V supply voltage.
VREG_ENA
Enable pin for the internal 1,8 V regulator. This pin is only available with production version. With the
engineering samples VREG_ENA is internally connected to VDD_BAT.
VDD_CHG
charger is not used, this pin should be left floating. See chapter 5.3 for detailed description of the
Charger input voltage. The charger will start operating when voltage to this pin is applied. When the
RES
The RESET pin is an active high reset and is internally filtered using the internal low frequency clock
oscillator. A reset will be performed between 1.5 and 4.0ms following RESET being active. It is
recommended that RESET be applied for a period greater than 5ms.
10
PIO0 – PIO15
Programmable digital I/O lines. All PIO lines can be configured through software to have either weak or
strong pull-ups or pull-downs. Configuration for each PIO line depends on the application. See section
16 “I/O parallel ports” for detailed descriptions for each terminal. Default conf iguration for all of the PIO
lines is input with weak internal pull-up.
AIO0 – AIO1
AIOs can be used to monitor analogue voltages such as a temperature sensor for the battery charger.
AIOs can also be configured to be used as digital I/Os. The voltage level at these pins is 0 V to 1,5 V.
UART_NRTS
A CMOS output with a weak internal pull-up. This pin can be used to implement RS232 hardware flow
control where RTS (request to send) is an active low indicator. The UART interface requires an external
RS232 transceiver chip.
UART_NCTS
A CMOS input with a weak internal pull-down. This pin can be used to implement RS232 hardware flow
control where CTS (clear to send) is an active low indicator. The UART interface requires an external
RS232 transceiver chip.
UART_RXD
A CMOS input with a weak internal pull-down. RXD is used to implement UART data transfer from
another device to TBM–CBC5.The UART interface requires an external RS232 transceiver chip.
UART_TXD
A CMOS output with a weak internal pull-up. TXD is used to implement UART data transfer from T BM–CBC5
to another device. The UART interface requires external RS232 transceiver chip.
11
PCM_OUT
A CMOS output with a weak internal pull-down. Used in the PCM (pulse code modulation) interface to
transmit digitized audio. The PCM interface is shared with the I S interface.
PCM_IN
A CMOS input with a weak internal pull-down. Used in the PCM interface to receive digitized audio. The
PCM interface is shared with the I S interface.
PCM_CLK
A bi-directional synchronous data clock signal pin with a weak internal pull-down. PCMC is used in the
PCM interface to transmit or receive the CLK signal. When configured as a master, WT32 generates the
clock signal for the PCM interface. When configured as a slave, the PCMC is an input and receives the
clock signal from another device. The PCM interface is shared with the I S interface.
PCM_SYNC
A bi-directional synchronous data strobe with a weak internal pull-down. When configured as a master,
TBM–CBC5 generates the SYNC signal for the PCM interface. When configured as a slave, the PCMS is
an input and receives the SYNC signal from another device.The PCM interface is shared with the I 2S
interface.
USB_D+
A bi-directional USB data line with a selectable internal 1.5 kΩ pull-up implemented as a current source
(compliant with USB specification v1.2) An external series resistor is required to match the connection
to the characteristic impedance of the USB cable.
USB_DA bi -directional USB data line. An external series resistor is required to match the connection to the
characteristic impedance of the USB cable.
SPI_NCSB
A CMOS input with a weak internal pull-down. Active low chip select for SPI (serial peripheral interface).
SPI_CLK
A CMOS input for the SPI clock signal with a weak internal pull-down. TBM–CBC5 is the slave and receives
the clock signal from the device operating as a master.
SPI_MISO
An SPI data output with a weak internal pull-down.
SPI_MOSI
An SPI data input with a weak internal pull-down.
RF
This pin can be used when not using a chip antenna or w.fl connector of the module.
AUDIO_IN_P_RIGHT and AUDIO_IN_N_RIGHT
12
Right channel audio inputs. This dual audio input can be configured to be either single-ended or fully
differential and programmed for either microphone or line input. Route differential pairs close to each
other and use a solid dedicated audio ground plane for the audio signals.
AUDIO_IN_P_LEFT and AUDIO_IN_N_LEFT
Left channel audio input. ESD protection and layout considerations similar to right channel audio should
be used.
AUDIO_OUT_P_RIGHT and AUDIO_OUT_N_RIGHT
Right channel audio output. The audio output lines should be routed differentially to either the speakers
or to the output amplifier, depending on whether or not a single-ended signal is required. Use low
impedance ground plane dedicated for the audio signals.
AUDIO_OUT_P_LEFT and AUDIO_OUT_N_LEFT
Left channel audio output. The same guidelines apply to this section as discussed previously.
MIC_BIAS
Bias voltage output for a microphone. Use the same layout guidelines as discussed previously with
other audio signals.
LED0
TBM–CBC5 includes a pad dedicated to driving LED indicators. This terminal may be controlled by firmware
and it can also be set by the battery charger. The terminal is an open-drain output, so the LED must be
connected from a positive supply rail to the pad in series with a current limiting resistor.
It is recommended that the LED pad is operated with a pad voltage below 0.5V. In this case, the pad
can be thought of as a resistor, RON. The resistance together with the external series resistor will set
the current, ILED, in the LED. Value for the external series resistance can be calculated from the
Equation 1
RLED =
VDD − VF
− RON
I LED
Equation 1: LED series resistor
Where VF is the forward voltage drop of the LED, ILED is the forward current of the LED and RON is the
on resistance (typically 20 Ω) of the LED driver.
13
◇
The BM153 is a Class 2 Bluetooth sub-system using BlueCore5-Multimedia
External
chipset from
leading Bluetooth chipset supplier Cambridge Silicon Radio. BM153
interfaces
to 8Mbit of external
Flash memory When used with the CSR Bluetooth software stack, it provides
a fully
compliant
Bluetooth system to v2.1+EDR of the specification for data and voice
communications The module
and device firmware is fully compliant with the Bluetooth specification
V2.1+EDR,
The working
frequency is 2402~2480GHz total of 79 channels. It’s the master crystal
frequency
is 26MHz.
BlueCore5-Multimedia External ：The BlueCore5-Multimedia External is a
single-chip radio and
baseband IC for Bluetooth 2.4GHz systems.
FLASH: It is to save the firmware.
XTAL: Generate 26MHz system clock.
Balun：2.4GHz Balun, the unbalanced signal to balanced signal.
Filter：2.4GHz Bandpass filter
Modulated Type： GFSK π/4 DQPSK 8DPSK
5. TBM–CBC5 Physical Dimensions
Recommended PCB land pattern for TBM–CBC5
14
Internal Photo
Sony Corporation
Personal Audio System
[Model : SRS-X５]
Internal Photo
Sony Corporation
Personal Audio System
[Model : SRS-X５]
Internal Photo
ＣＮ ｂｏａｒｄ ｐｈｏｔｏ
Sony Corporation
Personal Audio System
[Model : SRS-X５]
How to fixed the module to SRS‐X5.
When the PCBA Main board, CN board and others is OK.
Insert FFC cable into Jack XP19 on Main board, insert the speaker cable into Jack XS1, XS2 on
Main board, as follow photo(The device under application):
Insert NFC cable into Jack XP15 on Main board, and insert the Main board to plastic case,
as follow photo
Connect the Main board to cn board with the FFC cable, insert the battery cable into Jack XP1001
on the CN board, insert the MIC cable into Jack XP589 on the Main board, as follow photo;
Connect the speaker cable to speaker and fix the speaker on the plastic case, as follow photo;
Fix the Front panel on the plastic case, as follow photo;
Fix the MIC on the plastic case, as follow photo;
Fix the Iron nets on the plastic case, as follow photo;
Fix the bottom cover on the plastic case, as follow photo;
Now, one of SRS‐X3 is fixed OK, as follow photo;
Front View
Back View
FCC Statement
Changes or modifications not expressly approved by the party responsible for compliance could
void the user's authority to operate the equipment
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) this device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
IC Statement
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject
to the following two conditions: (1) this device may not cause interference, and (2) this device
must accept any interference, including interference that may cause undesired operation of the
device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio
exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne
doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage
radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
The end host device should bear the label which indicate""Contains FCC ID:ZVAPS000012".or
"Contains IC:9976A-PS000012".

---

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