Toshiba H1 Series Tlcs 900 Users Manual TMP92CZ26AXBG_ETD_rev0.2

2014-12-13

: Toshiba Toshiba-H1-Series-Tlcs-900-Users-Manual-127535 toshiba-h1-series-tlcs-900-users-manual-127535 toshiba pdf

Open the PDF directly: View PDF PDF.
Page Count: 751

DownloadToshiba Toshiba-H1-Series-Tlcs-900-Users-Manual- TMP92CZ26AXBG_ETD_rev0.2 Toshiba-h1-series-tlcs-900-users-manual
Open PDF In BrowserView PDF
Data Book

32bit Micro controller
TLCS-900/H1 series

TMP92CZ26AXBG

TENTATIVE
It’s first version technical data sheet.
Since this revision 0.2 is still under working, there may
be some mistakes in it.
When you will start to design, please order the latest
one.

Rev0.2

09/Dec./2005

Table of Contents
TLCS-900/H1 Devices
TMP92CZ26A
1. Outline and Features ････････････････････････････････････････ 92CZ26A-1
2. Pin Assignment and Pin Functions ････････････････････････････ 92CZ26A-6
2.1 Pin Assignment Diagram ････････････････････････････････ 92CZ26A-6
2.2 Pin names and Functions ･･･････････････････････････････

92CZ26A-8

3. Operation ･･････････････････････････････････････････････････ 92CZ26A-14
3.1 CPU ･･･････････････････････････････････････････････････ 92CZ26A-14
3.2 Memory Map ･･････････････････････････････････････････

92CZ26A-19

3.3 Clock Function and Standby Function ････････････････････ 92CZ26A-20
3.4 Boot ROM ･････････････････････････････････････････････

92CZ26A-43

3.5 Interrupts ･･････････････････････････････････････････････ 92CZ26A-67
3.6 DMAC (DMA controller) ････････････････････････････････

92CZ26A-88

3.7 Function of Ports･････････････････････････････････････････ 92CZ26A-110
3.7.1 Port 1 ･････････････････････････････････････････････ 92CZ26A-117
3.7.2 Port 4 ･････････････････････････････････････････････ 92CZ26A-119
3.7.3 Port 5 ･････････････････････････････････････････････ 92CZ26A-121
3.7.4 Port 6 ･････････････････････････････････････････････ 92CZ26A-123
3.7.5 Port 7 ･････････････････････････････････････････････ 92CZ26A-125
3.7.6 Port 8 ･･････････････････････････････････････････････ 92CZ26A-128
3.7.7 Port 9 ･･････････････････････････････････････････････ 92CZ26A-130
3.7.8 Port A ･･････････････････････････････････････････････ 92CZ26A-133
3.7.9 Port C ･･････････････････････････････････････････････ 92CZ26A-135
3.7.10 Port F ･････････････････････････････････････････････ 92CZ26A-139
3.7.11 Port G ････････････････････････････････････････････ 92CZ26A-143
3.7.12 Port J ･････････････････････････････････････････････ 92CZ26A-145
3.7.13 Port K ･････････････････････････････････････････････92CZ26A-148
3.7.14 Port L ･･･････････････････････････････････････････ 92CZ26A-150
3.7.15 Port M ･･･････････････････････････････････････････ 92CZ26A-152
3.7.16 Port N ････････････････････････････････････････････ 92CZ26A-155
3.7.17 Port P ･･･････････････････････････････････････････ 92CZ26A-157
3.7.18 Port R ････････････････････････････････････････････ 92CZ26A-161
3.7.19 Port T ････････････････････････････････････････････ 92CZ26A-164
3.7.20 Port U ･･･････････････････････････････････････････ 92CZ26A-166
3.7.21 Port V ････････････････････････････････････････････ 92CZ26A-169
3.7.22 Port W ･･････････････････････････････････････････ 92CZ26A-172
3.7.23 Port X ･･･････････････････････････････････････････ 92CZ26A-174
3.7.24 Port Z ････････････････････････････････････････････ 92CZ26A-177
3.8 Memory Controller (MEMC) ･････････････････････････････ 92CZ26A-180
3.9 External Memory Extension Function (MMU) ･････････････ 92CZ26A-204
3.10 SDRAM Controller (SDRAMC) ････････････････････････ 92CZ26A-220
3.11 NAND-Flash controller ････････････････････････････････ 92CZ26A-238

3.12 8 bit timers (TMRA) ･･････････････････････････････････

92CZ26A-266

3.13 16 bit timer (TMRB) ･･････････････････････････････････

92CZ26A-294

3.14 Serial channel (SIO) ･･････････････････････････････････

92CZ26A-315

3.15 Serial Bus Interface (SBI) ･････････････････････････････ 92CZ26A-344
3.16 USB controller ･･････････････････････････････････････

92CZ26A-366

3.17 SPIC (SPI controller) ･････････････････････････････････

92CZ26A-477

3.18 I2S ･････････････････････････････････････････････････

92CZ26A-496

3.19 LCD controller (LCDC) ･･･････････････････････････････

92CZ26A-508

3.20 Touch screen interface (TSI) ･･････････････････････････

92CZ26A-564

3.21 Real time clock (RTC) ････････････････････････････････

92CZ26A-574

3.22 Melody/Alarm generator ･･･････････････････････････････ 92CZ26A-589
3.23 Analog/Digital Converter ･････････････････････････････

92CZ26A-595

3.24 Watch dog timer ････････････････････････････････････

92CZ26A-615

3.25 Power Management Circuit (PMC) ････････････････････

92CZ26A-619

3.26 Multiply and Accumulate Calculation unit (MAC) ･･･････

92CZ26A-628

3.27 Debug mode ･････････････････････････････････････････

92CZ26A-633

4. Electrical Characteristics ･･･････････････････････････････････

92CZ26A-640

5. Table of Special function registers (SFRs) ･････････････････････ 92CZ26A-665
6. Package ････････････････････････････････････････････････････ 92CZ26A-748

TMP92CZ26A

CMOS 32-Bit Micro controllers

TMP92CZ26AXBG
1.

Outline and Features
TMP92CZ26A is high-speed advanced 32-bit micro-controller developed for controlling equipment which
processes mass data.
TMP92CZ26AXBG is housed in a 228-pin BGA package.
(1)

CPU : 32-bit CPU(High-speed 900/H1 CPU)
•

Compatible with TLCS-900/L1 instruction code

•

16Mbytes of linear address space

•

General-purpose register and register banks

•

Micro DMA : 8channels (62.5ns/4 bytes at fSYS = 80MHz, best case)

(2)

Minimum instruction execution time : 12.5ns ( at fSYS = 80MHz)

(3)

Internal RAM: 288K-byte (can be used for program, data and display memory)
Internal ROM: 8 K-byte(memory for Boot only)
It enables that load user program from USB, UART to Internal RAM.

92CZ26A-1

TMP92CZ26A

(4)

(5)

External memory expansion
•

Expandable up to 3.1G bytes (shared program/data area)

•

Can simultaneously support 8/16-bit width external data bus
…… Dynamic data bus sizing

•

Separate bus system

Memory controller
•

Chip select output

•

One channel in 4 channels is enabled detailed AC enable setting

: 4 channel

(6)

8-bit timers

: 8 channels

(7)

16-bit timer/event counter

: 2 channel

(8)

General-purpose serial interface : 1 channels
•

UART/synchronous mode

•

IrDA ver1.0 (115.2 kbps) selectable :
(There is the restriction in the setting baud rate when use this function together other functions)

(9)

Serial bus interface: 1 channel
•

I2C bus mode only

(10) USB (universal serial bus) controller: 1 channel
•

Support to USB (REV1.1)

•

Full-speed (12 Mbps) (Low-speed is not supported.)

•

Endpoint 0: Control 64 bytes × 1-FIFO
Endpoint 1: BULK (output) 64 bytes × 2-FIFO
Endpoint 2: BULK (input) 64 bytes × 2-FIFO
Endpoint 3: Interrupt (input) 8 bytes × 1-FIFO

•

Descriptor RAM: 384 bytes

(11) I2S (Inter-IC Sound)interface: 2 channel
•

I2S bus mode selectable (Master, transmission only)

•

Data Format is supported Left/Right Justify

•

Built in FIFO buffer of 128 bytes (64 bytes × 2) every each channels.

(12) LCD controller
•

Supported up to monochrome, 4, 16 and 64 gray levels and 256/4096 color for STN

•

Supported up to 4096/65536/262144/16777216 color for TFT

•

Supported up to PIP (Picture In Picture Display)

•

Supported up to H/W Rotation function for support to various LCDM

(13) SDRAM controller :1 channel
•

Supported 16M, 64M, 128M, 256M and 512Mbit SDR (Single-data-rate) SDRAM

•

Can use not only as Data RAM for LCD display but also operate program direct from SDRAM

(14) Timer for real-time clock (RTC)
•

Based on TC8521A

(15) Key-on wakeup (Interrupt key input)
(16) 10-bit A/D converter (Built in Sample Hold circuit)

92CZ26A-2

: 6 channels

TMP92CZ26A
(17) Touch screen interface
•

Built-in Switch of Low-resistor, and available to delete external components for shift change
row/column

(18) Watch dog timer
(19) Melody/alarm generator
•

Melody: Output of clock 4 to 5461Hz

•

Alarm: Output of the 8 kinds of alarm pattern

•

5 kinds of interval interrupt

(20) MMU
•

Expandable up to 3.1G bytes (3 local area/8 bank method)

•

Independent bank for each Program, Read-data, Write-data, Source and Destination of DMAC (Odd
channel/Even channel) and LCD-display-data

(21) Interrupts: 56 interrupts
• 9 CPU interrupts

……

Software interrupt instruction and illegal instruction

• 38 internal interrupts

……

Seven selectable priority levels

• 9 external interrupts

……

Seven selectable priority levels
(8 interrupt selectable negative/positive of edge)

(22) DMAC function: 6 channels
•

High-speed data transfer enable by controlling which convert micro DMA function and this function

(23) Input/Output ports : 136 pins (Except Data bus (16bit), Address bus (24bit) and RD pin)
(24) Nand_Flash interface: 2 channel
•

Available to connect directly with NAND flash

•

Supported up to SLC type and MLC type

•

Data Bus 8/16 Bit, Page Size 512/2048 Bytes

•

Built-in Rees Solomon calculation circuits which enabled correct 4-address, and detect error more
than 5-address

(25) SPI controller : 1 channel
•

Supported up to SPI mode of SD card and MMC card

•

Built-in FIFO buffer of 32 bytes to each Input/Output

(26) Product/Sum calculation: 1 channel
•

calculation 32×32+64 =64Bit , 64-32×32 = 64Bit , 32×32-64 =64Bit

•

I/O method

(27) Signed calculation is supported.

92CZ26A-3

TMP92CZ26A
(28) Stand-by function
•

Three Halt modes

•

Each pin status programmable for stand-by mode

•

Built-in power supply management circuits (PMC) for leak current provision

: IDLE2 (programmable), IDLE1, STOP

(29) Clock controller
•

Built-in two blocks of clock doubler (PLL). PLL supplies 48 MHz for USB and 80 MHz for CPU from
10MHz

•

Clock gear function: Selectable high-frequency clock fc to fc/16

•

Clock for Timer (fs = 32.768 kHz)

(30) Operating voltage:
•

Internal VCC= 1.5V, External I/O Vcc = 3.0 to 3.6 V

•

2 power supplies (Internal power supply (1.4 to 1.6), External power supply (3.0 to 3.6)

(31) Package
•

228 pin FBGA :P-FBGA228-1515-0.80A5

92CZ26A-4

TMP92CZ26A
(AN0 to AN1)PG0 to PG1
(AN2, MX)PG2
(AN3, MY, ADTRG )PG3
(AN4 to AN5)PG4 to PG5
AVCC, AVSS
VREFH, VREFL

10-bit 6ch
AD
Converter

900/H1 CPU

XWA

W

A

XBC

B

C

XDE

D

E

H

L

(PY)P97

Touch Screen
I/F
(TSI)

(TXD0)P90
(RXD0)P91

SERIAL I/O
SIO0

XHL
XIX

IX

I2 S
(I2S0)

XIY

IY

XIZ

IZ

I2 S
(I2S1)

XSP

SP

(PX, INT4)P96

(CTS0, SCLK0)P92

(I2S0CKO)PF0
(I2S0DO)PF1
(I2S0WS)PF2
(I2S1CKO)PF3
(I2S1DO)PF4
(I2S1WS)PF5
(SDA)PV6
(SCL)PV7
D+
D(X1USB) PX5

2

SBI (I Cbus)
USB

8BIT TIMER
(TMRA0)

(TA1OUT, MLDALM)PM1

8BIT TIMER
(TMRA1)

(TA2IN, INT3)PC3

8BIT TIMER
(TMRA2)

(TA3OUT)PP1

8BIT TIMER
(TMRA3)

8BIT TIMER
(TMRA4)

(TA7OUT, INT5)PP3
(TB0IN0, INT6)PP4
(TB0OUT0)PP6
(TB1IN0, INT7)PP5
(TB1OUT0)PP7
(SPDI)PR0
(SPDO)PR1
( SPCS ) PR2
(SPCLK)PR3
(LCP0)PK0
(LLOAD)PK1
(LFR)PK2
(LVSYNC)PK3
(LHSYNC)PK4
(LGOE2 to 0)PK7 to 5
(LD7 to 0)PL7 to 0
(LD15 to 8)PT7 to 0
(LD22 to 16)PU6 to 0
(LD23, EO_TRGOUT)PU7
(CLKOUT, LDIV)PX4
PX7
( SDRAS , SRLLB )PJ0
( SDCAS , SRLUB )PJ1
( SDWE , SRWR )PJ2
(SDLLDQM)PJ3
(SDLUDQM)PJ4
(SDCKE)PJ7
(SDCLK)PF7

8BIT TIMER
(TMRA5)
8BIT TIMER
(TMRA6)

H-OSC

DVCC1C [1]
DVSS1C [1]

X1
X2

Clock gear
L-OSC

XT1
XT2
AM [1:0]

32bit
SR

PLL

RESET
DBGE

DSU
F

PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3(EI_REFCLK)
PZ4(EI_TRGIN)
PZ5(EI_COMRESET)
PZ6(EO_MCUDATA)
PZ7(EO_MCUREQ)

P C
PMC

Controller

(TA0IN, INT1)PC1

(TA5OUT)PP2

DVCC3A [12]
DVCC3B [1]
DVCC1A [5]
DVCC1B [1]
DVSSCOM

WATCH-DOG TIMER
MMU
MAC

DMAC

PORT1

PC0 (INT0)
PC2 (INT2)
D0 to D7
P10 to P17 (D8 to D15)

PORT4

P40 to P47 (A0 to A7)

PORT5

P50 to P57 (A8 to A15)

PORT6

P60 to P67 (A16 to A23)

Interrupt
Controller

PORT7

8BIT TIMER
(TMRA7)
16BIT TIMER
(TMRB0)

PORT8

16BIT TIMER
(TMRB1)

SPI
Controller
288KB RAM

NAND-FLASH
I/F (2ch)

KEY-BOARD

LCD
Controller

I/F
BOOT ROM 8KB

PM7 (PWE)

RTC

P70 ( RD )
P73 (EA24)
P74 (EA25)
P75(R/ W , NDR/ B )
P76 ( WAIT )
P80 ( CS0 )
P81 ( CS1 , SDCS )
P82 ( CS2 , CSZA , SDCS )
P83 ( CS3 , CSXA )
P84 ( CSZB )
P85 ( CSZC )
P71 ( WRLL , NDRE )
P72 ( WRLU , NDWE )
P86 ( CSZD , ND0CE )
P87 ( CSXB , ND1CE )
PJ5 (NDALE)
PJ6 (NDCLE)
PA0 to PA7 (KI0 to KI7)
PN0 to PN7 (KO0 to KO7)
PC7 (KO8)
PM2 ( ALARM , MLDALM )

MELODY/
ALARM-OUT
PORTV

PV3
PV4
PV0 (SCLK0)
PV1
PV2
PW7 to 0
PC4 (EA26)
PC5 (EA27)
PC6 (EA28)

SDRAM
Controller

Figure 1.1 Block Diagram of TMP92CZ26A

92CZ26A-5

TMP92CZ26A

2. Pin Assignment and Pin Functions
The assignment of input/output pins for TMP92CZ26A, their names and functions are as follows;

2.1 Pin Assignment Diagram (Top View)
Figure 2.1.1 shows the pin assignment of the TMP92CZ26A.

A1

A2

A3

A4

A5

A6

A7

A8

A9 A10 A11 A12 A13 A14 A15 A16 A17

B1

B2

B3

B4

B5

B6

B7

B8

B9 B10 B11 B12 B13 B14 B15 B16 B17

C1

C2

C3

C4

C5

C6

C7

C8

C9 C10 C11 C12 C13 C14 C15 C16 C17

D1

D2

D3

D5

D6

D7

D8

D9 D10 D11 D12 D13

E1

E2

E3

E4

F1

F2

F3

F4

D15 D16 D17
E14 E15 E16 E17

F6

F7

F8

F9 F10 F11

F14 F15 F16 F17

G1 G2 G3 G4

G6 G7

G12

G14 G15 G16 G17

H1

H2

H3

H4

H6

H12

H14 H15 H16 H17

J1

J2

J3

J4

J6

TMP92CZ26A

J12

J14 J15 J16 J17

K1

K2

K3

K4

K6

P-FBGA228

K12

K14 K15 K16 K17

L1

L2

L3

L4

L6

TOP VIEW

L12

L14 L15 L16 L17

M6 M7 M8 M9 M10 M11 M12

M14 M15 M16 M17

M1 M2 M3 M4
N1

N2

N3

P1

P2

P3

R1

R2

R3

T1

T2

U1

U2

N4

N14 N15 N16 N17
P5

P6

P7

P8

P9 P10 P11 P12 P13

P15 P16 P17

R4

R5

R6

R7

R8

R9 R10 R11 R12 R13 R14 R15 R16 R17

T3

T4

T5

T6

T7

T8

T9 T10 T11 T12 T13 T14 T15 T16 T17

U3

U4

U5

U6

U7

U8

U9 U10 U11 U12 U13 U14 U15 U16 U17

Figure 2.1.1 Pin assignment diagram (P-FBGA228)
4 balls of A1, A17, U1 and U17 (most outside 4 corner of BGA package) are Dummy Balls.
These balls are not connected with internal LSI chip, electrical characteristics.
A1 and U1, A17 and U17 are shorted in internal package. It is recommended that using to
OPEN check of mounting if mounting this LSI to Target board.

Example: If checking signal (or voltage) via A1-U1-U17-A17, short U17 and U1 on Target board
beforehand, and input signal (or voltage) from A1, and check voltage of A17.

92CZ26A-6

TMP92CZ26A
Table 2.1.1 Pin number and the name
Ball
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D1
D2
D3
D5
D6
D7
D8

Pin name
Dummy1
PG2,AN2, MX
PA6,KI6
PA5,KI5
PA3,KI3
PA1,KI1
DVCC1A5
PF1,I2S0DO
PJ6,NDCLE
PJ1, SDCAS , SRLUB
P87, CSXB , ND1CE
P83, CS3 , CSXA
P81, CS1 , SDCS
P72, WRLU , NDWE
P70, RD
P65,A21
Dummy3
VREFH
PG5,AN5
PG3,AN3,MY, ADTRG
PA7,KI7
PA2,KI2
PA0,KI0
PF2,I2S0WS
PF0,I2S0CKO
PJ5,NDALE
PJ2, SDWE , SRWR
PJ0, SDRAS , SRLLB
P86. CSZD , ND0CE
P82, CS2 , CSZA , SDCS
P75,R/ W ,NDR/ B
P71, WRLL , NDRE
P64,A20
DVCC1A4
AVCC
VREFL
PG4,AN4
PG1,AN1
PA4,KI4
PC5,EA27
P76, WAIT
PF5,I2S1WS
PF3,I2S1CKO
PJ7,SDCKE
PJ3,SDLLDQM
P84, CSZB
P80, CS0
P67,A23
P66,A22
P63,A19
P62,A18
P97,PY
AVSS
PW0
PG0,AN0
PC6,EA28
PC4,EA26
P74,EA25

Ball
No.
D9
D10
D11
D12
D13
D15
D16
D17
E1
E2
E3
E4
E14
E15
E16
E17
F1
F2
F3
F4
F6
F7
F8
F9
F10
F11
F14
F15
F16
F17
G1
G2
G3
G4
G6
G7
G12
G14
G15
G16
G17
H1
H2
H3
H4
H6
H12
H14
H15
H16
H17
J1
J2
J3
J4
J6
J12
J14

Pin name
P73,EA24
PF4,I2S1DO
PF7,SDCLK
PJ4,SDLUDQM
P85, CSZC
PU6,LD22
P61,A17
P60,A16
P96,PX,INT4
PW1
PW2
PW3
PU7,LD23,EO_TRGOUT
PU4,LD20
P57,A15
P56,A14
DVCC1B1
PW6
PW5
PW4
DVCC3A12
DVCC3A11
DVSS11
DVCC3A10
DVSS10
DVCC3A9
PU5,LD21
PU2,LD18
P55,A13
P54,A12
DVCC3B1
PW7
PV0,SCLK0
PV1
DVSS1
DVSS12
DVSS9
PU3,LD19
PU0,LD16
P53,A11
P52,A10
PV7,SCL
PV6,SDA
PV3
PV2
DVCC3A1
DVCC3A8
PU1,LD17
PT7,LD15
P51,A9
P50,A8
PN2,KO2
PN1,KO1
PN0,KO0
PV4
DVSS2
DVSS8
PT6,LD14

Ball
No.
J15
J16
J17
K1
K2
K3
K4
K6
K12
K14
K15
K16
K17
L1
L2
L3
L4
L6
L12
L14
L15
L16
L17
M1
M2
M3
M4
M6
M7
M8
M9
M10
M11
M12
M14
M15
M16
M17
N1
N2
N3
N4
N14
N15
N16
N17
P1
P2
P3
P5
P6
P7
P8
P9
P10
P11
P12
P13

Pin name
PT5,LD13
P47,A7
P46,A6
PN3,KO3
PN4,KO4
PN5,KO5
PN6,KO6
DVCC3A2
DVCC3A7
PT4,LD12
PT3,LD11
P45,A5
P44,A4
PK2,LFR
PN7,KO7
PM1,MLDALM,TA1OUT
PM7,PWE
DVSS3
DVSS7
PT2,LD10
PT1,LD9
P43,A3
P42,A2
PK3,LVSYNC
PC0,INT0
PM2, ALARM , MLDALM
P90,TXD0
DVCC3A3
DVSS4
DVCC3A4
DVSS5
DVCC3A5
DVSS6
DVCC3A6
PK7,LGOE2
PT0,LD8
P41,A1
P40,A0
DVCC1A1
PC1,INT1,TA0IN
P91,RXD0
DVSS1C
PK6,LGOE1
PK5,LGOE0
P17,D15
P16,D14
DVCC1C
PC2,INT2
P92,SCLK0, CTS0
PX4,CLKOUT, LDIV
PP2,TA5OUT
PP4,INT6,TB0IN0
PR0,SPDI
PR3,SPCLK
DBGE
PZ1,EI_SYNCLK
PZ3,EI_REFCLK
PZ5,EI_COMRESET

Note1: The P96, P97 and PG0~PG5 operate with the AVCC power supply.
Note2: The PW0~PW7 and PV0~PV7 operate with the DVCC3B power supply.
Note3: The X1 and X2 operate with the DVCC1C power supply.

92CZ26A-7

Ball
No.
P15
P16
P17
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17

Pin name
PK4,LHSYNC
P13,D11
P14,D12
X2
PC7,KO8
PC3,INT3,TA2IN
PX5,X1USB
PP7,TB1OUT0
PP1,TA3OUT
PP3,INT5,TA7OUT
PP5,INT7,TB1IN0
PR2, SPCS
PX7
PZ0,EI_PODDATA
PZ2,EI_PODREQ
PZ4,EI_TRGIN
PZ6,EO_MCUDATA
PZ7,EO_MCUREQ
P15,D13
DVCC1A3
X1
AM0
AM1
PP6,TB0OUT0
PL0,LD0
PL2,LD2
PL4,LD4
PL5,LD5
PR1,SPDO
PL6,LD6
PK1,LLOAD
P00,D0
P02,D2
P04,D4
P06,D6
P11,D9
P12,D10
Dummy2
RESET
D+
DDVCC1A2
PL1,LD1
PL3,LD3
XT1
XT2
PL7.LD7
PK0,LCP0
P01,D1
P03,D3
P05,D5
P07,D7
P10,D8
Dummy4

TMP92CZ26A

2.2 Pin names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin names and functions (1/6)
Pin name
D0 to D7
P10 to P17
D8 to D15
P40 to P47
A0 to A7
P50 to P57
A8 to A15
P60 to P67
A16 to A23
P70

Number of
Pins
8
8
8
8
8
1
1

Functions

I/O

Data: Data bus D0 to D7.

I/O

Port 1: I/O port. Input or output is specifiable in units of bit.

I/O

Data : Data bus D8 to D15.

Output

Port 4: Output port.

Output

Address : Address bus A0 to A7.

Output

Port 5: Output port.

Output
I/O

Address : Address bus A8 to A15.
Port 6 : I/O port. Input or output is specifiable in units of bit.

Output

Address : Address bus A16 to A23.

Output

Port 70 : Output port.

Output

RD

P71

I/O

I/O

Read : Outputs strobe signal to read external memory.
Port 71 : Output port.

WRLL

Output

Write : Outputs strobe signal to write data on pins D0 to D7.

NDRE

Output

NAND Flash read : Outputs strobe signal to read external NAND-Flash.

P72

1

I/O

Port 72 : I/O port.

WRLU

Output

Write : Outputs strobe signal to write data on pins D8 to D15.

NDWE

Output

NAND Flash write : Write enable for NAND Flash.

P73

1

EA24
P74

1

EA25
P75
R/ W

WAIT

P80

I/O
Output

1

I/O
Output
Input

NDR/ B
P76

I/O
Output

1
1

I/O
Input
Output

Port 73 : I/O port.
Expanded address 24.
Port 74 : I/O port.
Expanded address 25.
Port 75 : I/O port.
Read/Write : “High” represents read or dummy cycle and “Low” write cycle.
NAND Flash Ready(1) / Busy(0) input.
Port 76: I/O port.
Wait: Signal used to request CPU bus wait.
Port 80: Output port.

Output

Chip select 0: Outputs “Low” when address is within specified address area.

Output

Port 81 : Output port

CS1

Output

Chip select 1: Outputs “Low” when address is within specified address area.

SDCS

Output

Chip select for SDRAM : Outputs “Low” when the address is within SDRAM address area.

Output

Port 82 : Output port.

CS2

Output

Chip select 2: Outputs “Low” when address is within specified address area.

CSZA

Output

Expanded address ZA : Outputs “Low” when address is within specified address area.

SDCS

Output

Chip select for SDRAM : Outputs “0” when the address is within SDRAM address area.

Output

Port 83 : Output port.

CS3

Output

Chip select 3: Outputs “Low” when address is within specified address area.

CSXA

Output

Expanded address XA : Outputs “Low” when address is within specified address area.

Output

Port 84 : Output port.

Output

Expanded address ZB : Outputs “Low” when address is within specified address area.

Output

Port 85 : Output port.

Output

Expanded address ZC : Outputs “Low” when address is within specified address area.

CS0

P81

P82

P83

P84

1

1

1

1

CSZB

P85
CSZC

1

92CZ26A-8

TMP92CZ26A
Table 2.2.1 Pin names and functions (2/6)
Pin name

Number
of Pins

P86

I/O

Functions

Output

Port 86 : Output port.

Output

Expanded address ZD : Outputs “Low” when address is within specified address area.

ND0CE

Output

Chip select of NAND Flash 0: Outputs “Low” when NAND Flash 0 is enable.

P87

Output

Port 87 : Output port.

CSZD

CSXB

1

1

ND1CE

P90
TXD0
P91
RXD0

1
1

P92
SCLK0

1

CTS 0

P96

1

INT4

KI0 to KI7
PC0
INT0

1

8
1

PC1
INT1

INT2

1

PC3
INT3

EA26
PC5
EA27
PC6
EA28
PC7
KO8

I/O
Input

1

1
1
1

Transmit data of serial 0: programmable open drain output.
Port 91: I/O port. (Schmitt input)
Receive data of serial 0.
Port 92: I/O port. (Schmitt input)

I/O

Clock I/O of serial 0

Input

Enable to send data of serial 0 (Clear to send).

Input

Port 96: Input port. (schmitt input, with pull-up resistor)
Interrupt request pin 4 : Interrupt request pin with programmable rising/falling edge.
X-Plus : Pin connected to X+ pin for Touch Screen I/F.

Input

Port 97: Input port. (schmitt input)

Output

Y-Plus : Pin connected to Y+ pin for Touch Screen I/F.

Input

Port A0 to A7: Input port.

Input

Key input 0 to 7: For key on wake-up 0 to 7. (Schmitt input, with pull-up resistor)

I/O
Input

Port C0: I/O port. (Schmitt input)
Interrupt request pin 0 : Interrupt request pin with programmable rising/falling edge.
Port C1: I/O port. (Schmitt input)

Input

Interrupt request pin 1 : Interrupt request pin with programmable rising/falling edge.

Input

Timer A0 input: Input pin of 8 bit timer 0.

I/O
Input
Input
Input

1

Port 90: I/O port.

I/O

I/O

TA2IN
PC4

I/O
Output

I/O
1

TA0IN
PC2

Chip select of NAND Flash 1: Outputs “Low” when NAND Flash 1 is enable.

Output

PY
PA0 to PA7

Expanded address XB : Outputs “Low” when address is within specified address area.

Output

Input

PX
P97

Output

I/O
Output
I/O
Output
I/O
Output
I/O
Output

Port C2: I/O port. (Schmitt input)
Interrupt request pin 2 : Interrupt request pin with programmable rising/falling edge.
Port C3: I/O port. (Schmitt input)
Interrupt request pin 3 : Interrupt request pin with programmable rising/falling edge.
Timer A2 input: Input pin of 8 bit timer 2.
Port C4: I/O port.
Expanded address 26.
Port C5: I/O port.
Expanded address 27.
Port C6: I/O port.
Expanded address 28.
Port C7: I/O port.
Key output 8: Key scan strobe pin (programmable open drain output).

92CZ26A-9

TMP92CZ26A
Table 2.2.1 Pin names and functions (3/6)
Pin name
PF0
I2S0CKO
PF1
I2S0DO
PF2
I2S0WS
PF3
I2S0WS
PF4
I2S1CKO
PF5
I2S1WS
PF7
SDCLK
PG0 to PG1
AN0 to AN1

Number of
Pins
1
1
1
1
1
1
1
2

PG2
AN2

1

I/O
I/O
Output
I/O
Output
I/O
Output
I/O
Output
I/O
Output
I/O

Functions
Port F0: I/O port.
Outputs clock of I2S0.
Port F1: I/O port.
Outputs data of I2S0.
Port F2: I/O port.
Outputs word select signal of I2S0.
Port F3: I/O port.
Outputs clock of I2S1.
Port F4: I/O port.
Outputs data of I2S1.
Port F5: I/O port.

Output

Outputs word select signal of I2S1.

Output

Port F7: Output port.

Output

Clock for SDRAM.

Input

Port G0 to G1: Input port.

Input

Analog input pin 0 to 1 : Input pin of A/D converter.

Input

Port G2: Input port.

Input

Analog input pin 2 : Input pin of A/D converter.

MX

Output

PG3

Input

Port G3: Input port.

AN3

Input

Analog input pin 3 : Input pin of A/D converter.

MY

1

Output

X-Minus : Pin connected to X- pin for Touch Screen I/F.

Y-Minus : Pin connected to Y- pin for Touch Screen I/F.

ADTRG

Input

A/D Trigger : Request signal of A/D start.

PG4 to PG5

Input

Port G4 to G5: Input port.

AN4 to AN5

2

PJ0
SDRAS

1

Input

Analog input pin 4 to 5 : Input pin of A/D converter.

Output

Port J0: Output port.

Output

Outputs strobe signal of SDRAM row address.

SRLLB

Output

Data enable signal for D0 to D7 of SRAM.

PJ1

Output

Port J1: Output port.

Output

Outputs strobe signal of SDRAM column address.

Output

Data enable signal for D8 to D15 of SRAM.

Output

Port J2: Output port.

Output

Outputs write enable signal of SDRAM.

SRWR

Output

Write enable of SRAM: Outputs strobe signal to write data.

PJ3

Output

Port J3: Output port.

Output

Data enable signal for D0 to D7 of SDRAM.

Output

Port J4: Output port.

Output

Data enable signal for D8 to D15 of SDRAM.

SDCAS

1

SRLUB

PJ2
SDWE

SDLLDQM
PJ4
SDLUDQM
PJ5
NDALE
PJ6
NDCLE
PJ7
SDCKE

1

1
1
1
1
1

I/O
Output
I/O

Port J5: I/O port.
Address latch enable signal of NAND Flash.
Port J6: I/O port.

Output

Command latch enable signal of NAND Flash.

Output

Port J7: Output port.

Output

Clock enable signal of SDRAM.

92CZ26A-10

TMP92CZ26A

Table 2.2.1 Pin names and functions (4/6)
Pin name
PK0
LCP0
PK1
LLOAD
PK2
LFR
PK3
LVSYNC
PK4
LHSYNC
PK5
LGOE0
PK6
LGOE1
PK7
LGOE2
PL0 to PL7
LD0 to LD7

Number of
Pins
1
1
1
1
1
1
1
1
8

PM1
TA1OUT

1

I/O

Functions

Output

Port K0: Output port.

Output

Signal for LCD driver.

Output

Port K1: Output port.

Output

Signal for LCD driver.: Data load signal

Output

Port K2: Output port.

Output

Signal for LCD driver.

Output

Port K3: Output port.

Output

Signal for LCD driver. : Vertical sync signal

Output

Port K4: Output port.

Input

Signal for LCD driver. : Horizontal sync signal.

Output

Port K5: Output port.

Output

Signal for LCD driver.

Output

Port K6: Output port.

Output

Signal for LCD driver.

Output

Port K7: Output port.

Output

Signal for LCD driver.

Output

Port L0 to L7: Output port.

Output

Data bus for LCD driver: LD0 to LD7.

Output

Port M1: Output port.

Output

Timer A1 output: Output pin of 8 bit timer 1.

MLDALM

Output

Melody / Alarm output pin.

PM2

Output

Port M2: Output port.

Output

Alarm output from RTC.

MLDALM

Output

Melody / Alarm output pin (inverted).

PM7

Output

Port M7 : Output port

PWE

Output

External power supply control output: Pin to control ON/OFF of external power

ALARM

1

1

supply. In stand-by mode, outputs “L” level. In other than stand-by mode, outputs
“H” level.

PN0 to PN7
KO0 to KO7
PP1
TA3OUT
PP2
TA5OUT

8
1
1

PP3
INT5

1

1

TB1OUT0
PR0
SPDI
PR1
SPDO
PR2
SPCS

Input

Input
I/O

1

TB1IN0

PP7

I/O
Output

Input

PP5

TB0OUT0

Output

I/O

TB0IN0

PP6

I/O

Output

PP4

INT7

Output

I/O

TA7OUT
INT6

I/O

Input
Input

1
1
1
1
1

Port N: I/O port.
Key output 0 to 7 : Key scan strobe pin (programmable open drain output).
Port P1: I/O port.
Timer A3 output: Output pin of 8 bit timer 3.
Port P2: I/O port.
Timer A5 output: Output pin of 8 bit timer 5.
Port P3: I/O port. (Schmitt input)
Interrupt request pin 5 : Interrupt request pin with programmable rising/falling edge.
Timer A7 output: Output pin of 8 bit timer 7.
Port P4: I/O port. (Schmitt input)
Interrupt request pin 6 : Interrupt request pin with programmable rising/falling edge.
Timer B0 input: Input pin of 16 bit timer 0.
Port P5: I/O port. (Schmitt input)
Interrupt request pin 7 : Interrupt request pin with programmable rising/falling edge.
Timer B1 input: Input pin of 16 bit timer 1.

Output

Port P6: I/O port.

Output

Timer B0 output: Output pin of 16 bit timer 0.

Output

Port P7: I/O port.

Output

Timer B1 output: Output pin of 16 bit timer 1.

I/O
Input
I/O
Output
I/O
Output

Port R0: I/O port.
Data input pin of SD card.
Port R1: I/O port.
Data output pin of SD card.
Port R2: I/O port.
Chip select signal of SD card.

92CZ26A-11

TMP92CZ26A
Table 2.2.1 Pin names and functions (5/6)
Pin name
PR3
SPCLK
PT0 to PT7
LD8 to LD15
PU0 to PU4,PU6
LD16 to LD20,LD22

PU5
LD21

Number of
Pins
1
8
6
1

PU7
LD23

SCLK0

I/O
Output
I/O
Output
I/O
Output
I/O
Output
I/O

1

EO_TRGOUT
PV0

I/O

Output
Output

1

I/O
Output

Functions
Port R3: I/O port.
Clock output pin of SD card.
Port T0 to T7: I/O port.
Data bus for LCD driver: LD8 to LD15.
Port U0 to U4 , U6: I/O port
Data bus for LCD driver: LD16 to LD20, LD22.
Port U5: I/O port
Data bus for LCD driver: LD21
Port U7: I/O port
Data bus for LCD driver: LD23
Debug mode output pin
Port V0 : I/O port
Clock I/O of serial 0.

PV1

1

I/O

Port V1: I/O port.

PV2

1

I/O

Port V2: I/O port.

PV3 to PV4

2

Output

PV6
SDA
PV7
SCL
PW0 to PW7

1
1
8

PX4
CLKOUT

1

LDIV
PX5
X1USB
PX7
PZ0
EI_PODDATA
PZ1
EI_SYNCLK
PZ2
EI_PODREQ
PZ3
EI_REFCLK
PZ4
EI_TRGIN
PZ5
EI_COMRESET
PZ6
EO_MCUDATA
PZ7
EO_MCUREQ

1
1
1
1
1
1
1
1
1
1

Port V3 to V4: Output port.

I/O

Port V6: I/O port

I/O

Send/receive data in I C mode.

I/O

Port V7: I/O port

I/O

Input/output clock in I C mode.

I/O

2

2

Port W0 to W7: I/O port.

Output

Port X4 : Output port

Output

Internal clock output pin

Output

Output pin for LCD driver

I/O
Input

Port X5: I/O port.
Clock input pin of USB.

I/O

Port X7: I/O port.

I/O

Port Z0: I/O port. (Schmitt input)

Input
I/O
Input
I/O
Input
I/O
Input
I/O
Input
I/O
Input
I/O
Output
I/O
Output

Debug mode input pin
Port Z1: I/O port. (Schmitt input)
Debug mode input pin
Port Z2: I/O port. (Schmitt input)
Debug mode input pin
Port Z3: I/O port. (Schmitt input)
Debug mode input pin
Port Z4: I/O port. (Schmitt input)
Debug mode input pin
Port Z5: I/O port. (Schmitt input)
Debug mode input pin
Port Z6: I/O port. (Schmitt input)
Debug mode output pin
Port Z7: I/O port. (Schmitt input)
Debug mode output pin

92CZ26A-12

TMP92CZ26A
Table 2.2.1 Pin names and functions (6/6)
Pin name

Number of
Pins

I/O

Functions
Data pin connected to USB.

D+, D-

2

I/O

In case USB is not used, connect both pins to pull-up(DVCC3A) or pull-down resistor for protect
current flows it.

CLKOUT

1

Output

Internal clock output pin.
Operation mode;
Fix to AM1=”0”,AM0=”1” for 16 bit external bus starting.

AM1,AM0

2

Input

Fix to AM1=”1”,AM0=”0” is prohibit to set.
Fix to AM1=”1”,AM0=”1” for BOOT (32 bit internal Mask ROM) starting.
Fix to AM1=”0”,AM0=”0” is prohibited to set.

DBGE

1

Input

X1/X2

2

I/O

High-frequency oscillator circuit connection pin.

XT1/XT2

2

I/O

Low-frequency oscillator circuit connection pin.

Input pin in debug mode. (This pin is set to “Debug mode” by input “0”.)

RESET

1

Input

Reset : Initialize TMP92CZ26A (schmitt input , with pull-up resistor)

VREFH

1

Input

Pin for reference voltage input to A/D converter(H).

VREFL

1

Input

Pin for reference voltage input to A/D converter(L).

AVCC

1

−

Power supply pin for A/D converter.

AVSS

1

−

GND pin for AD converter (0V).

DVCC3A

12

−

Power supply pin for peripheral I/O-A (Connect all DVCC3A pins to power supply pin.)

DVCC3B

1

−

Power supply pin for peripheral I/O-B (Connect all DVCC3B pins to power supply pin.)

DVCC1A

5

−

Power supply pin for internal logic-A. (Connect all DVCC1A pins to power supply pin.)

DVCC1B

1

−

Power supply pin for internal logic-B. (Keep the voltage DVCC1A level.)

DVSSCOM

12

−

GND pin (0V). (Connect all DVSS pins to GND(0V).)

DVCC1C

1

−

Power supply pin for High speed oscillator. (Keep the voltage DVCC1A level.)

DVSS1C

1

−

GND pin (0V). (Connect to GND(0V).)

Dummy4-1

4

−

Dummy1 and Dummy2, Dummy3 and Dummy4 are shorted in package. (These pins are not
connected with internal LSI chip.)

Table 2.2.2 shows the range of operational voltage for power supply pins.

Table 2.2.2 the range of operational voltage for power supply pins
Power supply pin

Range of
operational
voltage

DVCC1A
DVCC1B

1.4V~1.6V

DVCC1C
DVCC3A
DVCC3B

3.0V~3.6V

AVCC

92CZ26A-13

TMP92CZ26A

3.

Operation
This section describes the basic components, functions and operation of the TMP92CZ26A.

3.1 CPU
The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU)

3.1.1

CPU Outline
900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1
CPU has expanded 32-bit internal data bus to process Instructions more quickly.
Outline is as follows:
Table 3.1.1Outline of TMP92CZ26A
Parameter

TMP92CZ26A

Width of CPU Address Bus

24-bit

Width of CPU Data Bus

32-bit

Internal Operating Frequency

Max 80MHz

Minimum Bus Cycle

1-clock access

Internal RAM

32-bit 2-1-1-1 clock access

(12.5ns at 80MHz)
Internal Boot ROM

32 bit 2-clock access

Internal I/O

8-bit,

INTC,SDRAMC,

2-clock access

MEMC,LCDC,
TSI,PORT,
PMC

16-bit,

MMU,USB,

2-clock access

NDFC,SPIC,DMAC

32-bit,

I2S

2-clock access

MAC

32-bit,

MAC

1-clock access
8-bit,

TMRA,TMRB,

5 to 6-clock access

SIO,RTC,
MLD/ALM, SBI
CGEAR,ADC,WDT

External memory

8/16-bit 2-clock access

(SRAM, MASKROM etc.)

(can insert some waits)

External memory

16-bit 1-clock access

(SDRAM)
External memory

8/16-bit 2-clock access

(NAND FLASH)

(can inset some waits)

Minimum Instruction

1-clock(12.5ns at 80MHz)

Execution Cycle
Conditional Jump

2-clock(25.0ns at 80MHz)

Instruction Queue Buffer

12-byte

Instruction Set

Compatible with TLCS-900/L1
(LDX instruction is deleted)

CPU mode

Only maximum mode

Micro DMA

8-channel

Hardware DMA

6-channel

92CZ26A-14

TMP92CZ26A

3.1.2

Reset Operation
When resetting the TMP92CZ26A microcontroller, ensure that the power supply voltage
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at
X1=10MHz).
At reset, since the clock doublers (PLL0) is bypassed and clock-gear is set to 1/16, system
clock operates at 625 kHz(X1=10MHz).
When the Reset has been accepted, the CPU performs the following. CPU internal
registers do not change when the Reset is released.
•

Sets the Stack Pointer (XSP) to 00000000H.

•

Sets bits  of the Status Register (SR) to “111” (thereby setting the Interrupt
Level Mask Register to level 7).

•

Clears bits  of the Status Register to 00 (thereby selecting Register Bank 0).

When the Reset is released, the CPU starts executing instructions according to the
Program Counter settings.
•

Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored
at address FFFF00H~FFFF02H:
PC<7:0>

←

data in location FFFF00H

PC<15:8>

←

data in location FFFF01H

PC<23:16>

←

data in location FFFF02H

When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•

Initializes the internal I/O registers as table of “Special Function Register” in Section
5.

Note1: This LSI builds in RAM internally. However, the data in internal RAM may not be held by Reset
operation. After reset, initialize the data in internal RAM.
Note2: This LSI builds in PMC function (for reducing stand-by current by blocking the power supply of
DVCC1A and DVCC1C). However, if executing reset operation without supplying DVCC1A and
DVCC1C, the current may flow to internal. When reset this LSI, supply the power of DVCC1A and
DVCC1C first and wait until the power supply stabilizes.

Figure 3.1.2 shows reset timing chart. Figure 3.1.2 shows the example of order of supplying
power and the timing of releasing reset.

92CZ26A-15

92CZ26A-16

Figure 3.1.1 TMP92CZ26A Reset timing chart

SRxxB

SRWR

WRxx

D0∼15

SRxxB

RD

D0∼15

CS2

CS0,1, 3

A23∼0

RESET

: High-Z

DATA-OUT

DATA-IN

Sampling

Sampling

fSYS×(15.5∼16.5) Clock

(After reset is released, it is started
from 1 wait read cycle)

DATA-IN

0FFFF00H

e
t
i
r
W

d
a
e
R

fsys

TMP92CZ26A

TMP92CZ26A
This LSI has the restriction for the order of supplying power. Be sure to supply external
3.3V power with 1.5V power is supplied.
Power On

Stand-by Mode (PMC)

Power Off

DVCC1A
1.5V
Power

DVCC1B
DVCC1C
Power supply is rising with
After 1.5V power

in 100mS, and stabilizes.

Power supply is falling with
in 100mS, and stabilizes.
After 1.5V power

supply is rising,
set 3.3V to ON.

3.3V
Power

supply is falling, set
3.3V to OFF.

DVCC3A

DVCC3B

High-frequency oscillation

AVCC

stabilization time
＋20 system clock

RESET

PWE terminal

Note1: Inernal 1.5 V and External 3.3V power supply can be set to ON/OFF at the same time. However, external pin
may become unstable condition momentary. Therefore, set external power supply to ON/OFF during internal
power supply is stabile like above figure if there is possibility to affect machinery connected with micro controller.
Note2: When setting to ON, don’t set 3.3V power supply earlier than 1.5V power supply. When setting to OFF, don’t
set to 3.3V power supply later than 1.5 V power supply.

Figure 3.1.2 Power on Reset Timing Example

92CZ26A-17

TMP92CZ26A

3.1.3

Setting of AM0 and AM1
Set AM1 and AM0 pins as Table 3.1.2 shows according to system usage.
Table 3.1.2 Operation Mode Setup Table
Mode Setup input pin
RESET

AM1

AM0

0

1

1

0

0

Debug mode

1

16-bit external bus starting

0
1
0

1

1

0

0

Operation Mode

DBGE

1
0

1

Test mode (Prohibit to set)
Test mode (Prohibit to set)
BOOT(32-bit internal-MROM )
starting
(BOOT mode)
Test mode (Prohibit to set)

92CZ26A-18

TMP92CZ26A

3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP92CZ26A.
000000H

Internal I/O
(8 Kbyte)

Direct area(n)

000100H
64Kbyte area
(nn)

001FF0H
002000H
010000H
Internal RAM
(288 Kbyte)
046000H
04A000H

(Internal Back Up RAM 16kbyte)

External memory
16Mbyte area
(R)
F00000H

Provisional Emulator Control Area
(64kbyte)

(−R)
(R+)

(Note1)

(R + R8/16)

F10000H

(R + d8/16)
(nnn)

External memory

FFFF00H
FFFFFFH

Vector table (256 Byte)
(

=

Internal area)

Figure 3.2.1 Memory Map
Note1: Don’t use specified 64kbyte area of above 16M byte when using debug mode. This is because the area is reserved
for control in the debug mode.
Note2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved as internal area.

92CZ26A-19

TMP92CZ26A

3.3 Clock Function and Standby Function
TMP92CZ26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4)
noise-reducing circuit. They are used for low-power, low-noise systems.
This chapter is organized as follows:
3.3.1 Block diagram of system clock
3.3.2 SFRs
3.3.3 System clock controller
3.3.4 Prescaler clock controller
3.3.5 Noise-reducing circuit
3.3.7 Standby controller

92CZ26A-20

TMP92CZ26A
The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only),
(b) PLL-ON Mode (X1, X2, and PLL).
Figure 3.3.1 shows a transition figure.

The clock frequency input from the X1 and X2 pins is called fOSCH and the clock
frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by
SYSCR1 is called the system clock fSYS. And one cycle of fSYS is defined to
as one state.
Reset
(fOSCH/16)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)

release Reset

instruction
interrupt
instruction
interrupt
(a)

PLL-OFF mode
(fOSCH/gear value)

instruction
interrupt

STOP mode
(Stops all circuits)

PLL-OFF mode transition figure
Reset
(fOSCH/16)

IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)

instruction
interrupt
instruction
interrupt

release Reset
instruction
PLL-OFF mode
interrupt
/gear value)
(f
OSCH

STOP mode
(Stops all circuits)

Instruction (Note)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)

instruction
interrupt
instruction
interrupt

PLL-ON mode
((12 or 16)×fOSCH/gear value)

(b)

PLL-OFF , PLL-ON mode transition figure

Note 1: If you shift from PLL-ON mode to PLL-OFF mode, execute following setting in the same order.
(1) Change CPU clock (Set “0” to PLLCR0)
(2) Stop PLL circuit (Set “0” to PLLCR1)
Note 2: It’s prohibited to shift from PLL-ON mode to STOP mode directly.
You should set PLL-OFF mode once, and then shift to STOP mode.

Figure 3.3.1 System clock block diagram

The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is
called fs. The clock frequency selected by SYSCR1 is called the system clock fSYS. And one cycle of fSYS is defined
to as one state.

92CZ26A-21

TMP92CZ26A
3.3.1

Block diagram of system clock
SYSCR0
SYSCR2
φT0

÷4

Warming up timer
(High/Low frequency oscillator circuit)

φT0TMR

÷2
Lock up timer
(PLL)

÷2

÷8

SYSCR0
XT1
XT2

Low frequency
Oscillator circuit

SYSCR0

PLLCR1,
PLLCR0

fs

fs
fc
fc/2
fc/4

X1
X2

Clock Doubler0
(PLL0)
× (12 or16)

fSYS

fc/8

fPLL

÷2

fc/16
÷2
÷2

High frequency
Oscillator circuit fOSCH

÷4

÷8 ÷16

fIO

SYSCR1

Clock gear
PLLCR0
SYSCR0

Clock Doubler1
(PLL1)× 24

÷5

fPLLUSB
fUSB

X1USB

fSYS
fio
φT0TMR

CPU

LCDC

RAM

Memory
Controller

Interrupt
Controller

NAND-Flash

I/O ports

IS

SDRAMC

TSI

DMAC

SPIC

TMRA0:7,TMRB0:1
Prescaler

SIO0
φT0

Controller
2

Prescaler

SBI
Prescaler

MAC
RTC
fs
MLD/ALM

ADC

USB

fUSB

Figure 3.3.2 Block Diagram of System clock

92CZ26A-22

fOSCH4

TMP92CZ26A

TMP92CZ26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1).
Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz.
Don’t connect oscillator more than10MHz. When clock is input by using external oscillator,
range of input frequency is 6 to10MHz. Don’t input the clock over 10MHz.
Table 3.3.1 Setting example for fOSCH

(a) PLL, USB (PLL0 ON/PLL1ON)

High frequency:
fOSCH

System
clock:
fSYS

System
clock:
fSYS

USB
clock:
fUSB

10.0 MHz

Max 80 MHz

Max 60 MHz

48 MHz

(b) PLL, No USB (PLL0 ON/PLL1OFF)

Max 10.0 MHz

Max 80 MHz

Max 60 MHz

−

(c) No PLL, No USB (PLL0 OFF/PLL1OFF)

Max 10.0 MHz

Max 10 MHz

Max 10 MHz

−

Note: When using USB, set high-frequency oscillator to 10.0 MHz.

92CZ26A-23

TMP92CZ26A
3.3.2

SFR
7

SYSCR0
(10E0H)

6

5

4

bit Symbol

XTEN

USBCLK1

USBCLK0

WUEF

PRCK

Read/write

R/W

R/W

R/W

R/W

R/W

0

0

After Reset

1

3

2

1

0

0

0

Low

Select the clock of

Warm-up

Select

-frequency

USB(fUSB)

Timer

Prescaler

oscillator

00:Disable

0: Write

clock

circuit (fs)

01: Reserved

Don’t care

0: Stop

10:X1USB

Note3

0: fSYS/2

1: Write

1: fSYS/8

1: Oscillation 11:fPLLUSB

Function

start timer
0: Read
end
warm-up
1: Read
do not end
warm-up

7
SYSCR1
(10E1H)

6

5

4

3

bit Symbol

2

1

0

GEAR2

GEAR1

GEAR0

Read/write

R/W

After Reset

1

0

0

Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4

Function

011: fc/8
100: fc/16
101: Reserved
110: Reserved
111: Reserved

SYSCR2
(10E2H)

7

6

5

4

3

2

bit Symbol

–

CKOSEL

WUPTM1

WUPTM0

HALTM1

HALTM0

Read/write

R/W

R/W

R/W

R/W

R/W

R/W

After Reset

0

0

1

0

1

1

Function

Always

Select

Warm-Up Timer

HALT mode

write “0”

CLKOUT

00: reserved

00: Reserved

0: fSYS

01: 28/inputted frequency

01: STOP mode

1: fS

10:214/inputted frequency

10: IDLE1 mode

11:216/inputted frequency

11: IDLE2 mode

1

0

Note1: SYSCR0,SYSCR1 and SYSCR2 are read as undefined value.
Note2: By reset, low frequency oscillator circuit is enabled.
Note3: Don’t write SYSCR0 resiter during warming up. Because the warm-up end flag doesn’t become enable if
write ”0” to SYSCR0 bit during warming up.
( Read-modify-write is prohibited for SYSCR0 register during warming up.)

Figure 3.3.3 SFR for system clock

92CZ26A-24

TMP92CZ26A

7
EMCCR0
(10E3H)

4

3

2

1

0

PROTECT

−

EXTIN

DRVOSCH

DRVOSCL

Read/Write

R

R/W

R/W

R/W

R/W

After reset

0

0

0

1

1

Protect flag

Always

1: External

fc oscillator

fs oscillator

0: OFF

write “0”.

clock

drive ability

drive ability

1: NORMAL

1: NORMAL

0: WEAK

0: WEAK

1: ON

Bit symbol
Read/Write
After reset
Function

EMCCR2
(10E5H)

5

Bit symbol

Function

EMCCR1
(10E4H)

6

st

nd

Switching the protect ON/OFF by write to following 1 -KEY,2 -KEY
st

Bit symbol

1 -KEY: EMCCR1=5AH,EMCCR2=A5H in succession write
nd

2 -KEY: EMCCR1=A5H,EMCCR2=5AH in succession write

Read/Write
After reset
Function
Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set
EMCCR0, =”1”.

Figure 3.3.4 SFR for system clock

92CZ26A-25

TMP92CZ26A

7
PLLCR0
(10E8H)

6

5

bit symbol

FCSEL

LUPFG

Read/Write

R/W

R

After reset

0

0

Function

4

Select

Lock-up

fc-clock

timer

0 : fOSCH

Status flag

1 : fPLL

0 : not end

3

2

1

0

1 : end

Note: Be carefull that logic of PLLCR0 is different from 900/L1’s DFM.

PLLCR1
(10E9H)

7

6

5

bit symbol

PLL0

PLL1

LUPSEL

PLLTIMES

Read/Write

R/W

R/W

R/W

R/W

After reset

0

Function

0

4

3

2

1

0

0

0

PLL0 for

PLL1 for

Select

Select the

CPU

USB

stage of

number of

0: Off

0: Off

Lock up

PLL

1: On

1: On

counter

0: ×12

0: 12 stage

1: ×16

(for PLL0)
1:13 stage
(for PLL1)

Figure 3.3.5 SFR for PLL

PxDR
(xxxxH)

bit symbol

7

6

5

4

Px7D

Px6D

Px5D

Px4D

Read/Write

3

2

1

0

Px3D

Px2D

Px1D

Px0D

1

1

1

1

R/W

After reset

1

1

1

Function

1

Output/Input buffer drive-register for standby-mode

(Purpose and method of using)
•
•
•
•

This register is used to set each pin-status at stand-by mode.
All ports have this format’s register. (“x” means port-name.)
For each register, refer to 3.5 Function of Ports.
Before “HALT” instruction is executed, set each register pin-status. They will be
effective after CPU executes “HALT” instruction.
• This register is effective in all stand-by modes (IDLE2, IDLE1 or STOP).
• This register is effective when using PMC function. For details, refer to PMC
section.
The truth table to control Output/Input-buffer is below.
OE

PxnD

Output buffer

Input buffer

0

0

OFF

OFF

0

1

OFF

ON

1

0

OFF

OFF

1

1

ON

OFF

Note1: OE means an output enable signal before stand-by mode. Basically, PxCR is used as OE.
Note2: “n” in PxnD means bit-number of PORTx.

Figure 3.3.6 SFR for drive register

92CZ26A-26

TMP92CZ26A
3.3.3

System clock controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and
internal I/O.
SYSCR0 and SYSCR0 control enabling and disabling of each oscillator.
SYSCR1 sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4,
fc/8, fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
The combination of settings  = “1”,  = “0” and  = “100” will
be PLL-OFF mode and cause the system clock (fSYS) to be set to fc/16 after reset.
For example, fSYS is set to 625 kHz when the 10MHz oscillator is connected to the X1 and
X2 pins.
(1) Clock gear controller
fSYS is set according to the contents of the Clock Gear Select Register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fSYS
reduces power consumption.
(Example)
Changing clock gear
SYSCR1

EQU

10E1H

LD

(SYSCR1),XXXXX001B

LD

(DUMMY),00H

;

Changes system clock fSYS to fc/2
Dummy instruction

X: don't care

(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1 register.
It is necessary the warming up time until changing after writing the register value.
There is the possibility that the instruction next to the clock gear changing instruction is
executed by the clock gear before changing. To execute the instruction next to the clock gear
switching instruction by the clock gear after changing, input the dummy instruction as
follows (instruction to execute the write cycle).
(Example)
SYSCR1

EQU

10E1H

LD

(SYSCR1),XXXXX010B

;

Changes fSYS to fc/4

LD

(DUMMY),00H

;

Dummy instruction

Instruction to be executed after clock gear changed

92CZ26A-27

TMP92CZ26A
3.3.4

Clock doubler (PLL)
PLL0 outputs the fPLL clock signal, which is 12 or 16 times as fast as fOSCH. That is, the
low-speed frequency oscillator can be used as external oscillator, even though the internal
clock is high-frequency.
Since Reset initializes PLL0 to stop status, setting to PLLCR0 and PLLCR1-register is
needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time
and it is measured by 12-stage binary counter. Lock-up time is about 0.41ms at fOSCH =
10MHz.
PLL (PLL1) which is special for USB is build in. Lock-up time is about 0.82ms at fOSCH =
10MHz measured by 13-stage binary counter.
Note1: Input frequency limitation for PLL
The limitation of input frequency (High frequency oscillation) for PLL is following.
fOSCH = X to X MHz (Vcc = 1.4 to 1.6V)
Note2: PLLCR0
The logic of PLLCR0 is different from 900/L1’s DFM.
Be careful to judge an end of lock-up time.
Note3: PLLCR1, PLLCR1
It’s prohibited to turn ON both PLL0 and PLL1 simultaneously.
If turning ON simultaneously, one PLL should be turn ON after finishing the lock up of the other PLL.

Figure 3.3.7 shows the frequency of fSYS when using PLL and clock gear at fOSCH
=10MHz.

fOSH
10MHz

fPLL
fOSH

fc

fc/2

Frequency of fSYS
fc/4
fc/8

fc/16

10MHz

10MHz

5MHz

2.5MHz

1.25MHz

625KHz

×12 120MHz

60MHz

30MHz

15MHz

7.5MHz

3.75MHz

×16 160MHz

80MHz

40MHz

20MHz

10MHz

5MHz

Figure 3.3.7 The frequency of fSYS at fOSH =10MHz

92CZ26A-28

TMP92CZ26A

The following is a setting example for PLL0-starting and PLL0-stopping.
(Example-1) PLL0-starting
PLLCR0

EQU

10E8H

PLLCR1

EQU

10E9H

LUP:

Enables PLL0 operation and starts lock-up.

LD

(PLLCR1),1XXXXXXXXB

;

BIT

5,(PLLCR0)

;

JR

Z,LUP

;

LD

(PLLCR0), X1XXXXXXB

; Changes fc from 10 MHz to 60 MHz.

Detects end of lock-up

X: Don't care


PLL output: fPLL
Lockup timer

Counts up by fOSCH



During lock-up

After lock-up

System clock fSYS
Starts PLL0 operation and
Starts lock-up.

Changes from 10MHz to 60MHz.
Ends of lock-up

(Example-2) PLL0-stopping
PLLCR0

EQU

10E8H

PLLCR1

EQU

10E9H

LD

(PLLCR0),X0XXXXXXB

;

Changes fc from 60 MHz to10 MHz.

LD

(PLLCR1),0XXXXXXXB

;

Stop PLL

X: Don't care


PLL0 output: fPLL
System clock fSYS
Changes from 60MHz to 10 MHz.
Stops PLL0 operation .

Note) PLL1 operates as well.

92CZ26A-29

TMP92CZ26A

Limitation point on the use of PLL0
1. If you stop PLL operation during using PLL0, you should execute following setting in
the same order.
LD

(PLLCR0),X0XXXXXXB

;

Change the clock fPLL to fOSCH

LD

(PLLCR1),0XXXXXXXB

;

Stop PLL0

X: Don't care

2. If you shift to STOP mode during using PLL, you should execute following setting in the
same order.
LD

(SYSCR2),XXXX01XXB

;

Set the STOP mode

LD

(PLLCR0), X0XXXXXXB

;

LD

(PLLCR1), 0XXXXXXXB

;

Change the system clock fPLL to fOSCH
Stop PLL0

;

Shift to STOP mode

HALT
X: Don't care

Examples of settings are below;
(1) Start Up / Change Control
(OK) High frequency oscillator operation mode(fOSCH )→PLL0 start up
→ PLL0 use mode (fPLL )
LUP:

LD

(PLLCR1), 1XXXXXXXB

;

BIT

5,(PLLCR0)

;

PLL0 start up / lock up start

JR

Z,LUP

;

Check for the flag of lock up end

LD

(PLLCR0), X1XXXXXXB

;

Change the system clock fOSCH to fPLL

X: Don't care

(2) Change / Stop Control
(OK) PLL0 use mode (fPLL )→ High frequency oscillator operation mode(fOSCH )
→ PLL0 Stop
LD

(PLLCR0),X0XXXXXXB

;

Change the system clock fPLL to fOSCH

LD

(PLLCR1),0XXXXXXXB

;

Stop PLL0

X: Don't care

(OK) PLL0 use mode (fPLL ) → Set the STOP mode
→High frequency oscillator operation mode (fOSCH) → PLL stop
→ HALT(High frequency oscillator stop)
LD

(SYSCR2),XXXX01XXB

;

Set the STOP mode

LD

(PLLCR0),X0XXXXXXB

;

(This command can be executed before use of PLL0)
Change the system clock fPLL to fOSCH

LD

(PLLCR1),0XXXXXXXB

;

Stop PLL0

;

Shift to STOP mode

HALT
X: Don't care

(NG) PLL0 use mode (fPLL) → Set the STOP mode
→ HALT(High frequency oscillator stop)
LD

(SYSCR2),XXXX01XXB

;

Set the STOP mode
(This command can be executed before use of PLL0)

HALT

;

Shift to STOP mode

X: Don't care

92CZ26A-30

TMP92CZ26A

3.3.5

Noise reduction circuits
Noise reduction circuits are built in, allowing implementation of the following features.
(1) Reduced drivability for high-frequency oscillator circuit
(2) Reduced drivability for low-frequency oscillator circuit
(3) Single drive for high-frequency oscillator circuit
(4) SFR protection of register contents
These are set in EMCCR0 to EMCCR2 registers.

(1) Reduced drivability for high-frequency oscillator circuit
(Purpose)
Reduces noise and power for oscillator when a resonator is used.
(Clock diagram)
fOSCH
C1

X1 pin
Enable oscillation

resonator

EMCCR0

C2
X2 pin

(Setting method)
The drivability of the oscillator is reduced by writing”0” to EMCCR0
register. By reset,  is initialized to “1” and the oscillator starts oscillation
by normal-drivability when the power-supply is on.
Note: This function (EMCCR0= “0”) is available to use in case fOSCH = 6 to 10MHz condition.

92CZ26A-31

TMP92CZ26A
(2) Reduced drivability for low-frequency oscillator circuit
(Purpose)
Reduces noise and power for oscillator when a resonator is used.
(Block diagram)

C1

XT1 pin
Enable oscillation

Resonator

EMCCR0

C2

fS
XT2 pin

(Setting method)
The drivability of the oscillator is reduced by writing 0 to the EMCCR0
register. By Reset,  is initialized to “1”.
(3) Single drive for high-frequency oscillator circuit
(Purpose)
Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when
the external-oscillator is used.
(Block diagram)
fOSCH
X1 pin
Enable oscillation

EMCCR0

X2 pin

(Setting method)
The oscillator is disabled and starts operation as buffer by writing “1” to
EMCCR0 register. X2-pin is always outputted”1”.
By reset, is initialized to “0”.
Note: Do not write EMCCR0 = “1” when using external resonator.

92CZ26A-32

TMP92CZ26A
(4) Runaway provision with SFR protection register
(Purpose)
Provision in runaway of program by noise mixing.
Write operation to specified SFR is prohibited so that provision program in runaway
prevents that it is in the state which is fetch impossibility by stopping of clock,
memory control register (Memory controller, MMU) is changed.
And error handling in runaway becomes easy by INTP0 interruption.
Specified SFR list
1. Memory controller
B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR,
MEMCR0, CSTMGCR, WRTMGCR, RDTMGCR0
RDTMGCR1, BROMCR
2. MMU
LOCALPX/PY/PZ, LOCALLX/LY/LZ,
LOCALRX/RY/RZ, LOCALWX/WY/WZ,
LOCALESX/ESY/ESZ, LOCALEDX/EDY/EDZ,
LOCALOSX/OSY/OSZ, LOCALODX/ODY/ODZ
3. Clock gear
SYSCR0, SYSCR1, SYSCR2, EMCCR0
4. PLL
PLLCR0,PLLCR1
5. PMC
PMCCTL

(Operation explanation)
Execute and release of protection (write operation to specified SFR) becomes
possible by setting up a double key to EMCCR1 and EMCCR2 register.
(Double key)
1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2
2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2
A state of protection can be confirmed by reading EMCCR0.
By reset, protection becomes OFF.
And INTP0 interruption occurs when write operation to specified SFR was executed
with protection on state.

92CZ26A-33

TMP92CZ26A
3.3.6

Standby controller
(1) Halt Modes and Port Drive-register
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP Mode, depending on the contents of the SYSCR2
register and each pin-status is set according to PxDR-register.

PxDR
(xxxxH)

bit symbol

7

6

5

4

Px7D

Px6D

Px5D

Px4D

Read/Write

3

2

1

0

Px3D

Px2D

Px1D

Px0D

1

1

1

1

R/W

After reset

1

1

Function

1

1

Output/Input buffer drive-register for standby-mode

(Purpose and method of using)
•
•
•
•

This register is used to set each pin-status at stand-by mode.
All ports have this format’s register. (“x” means port-name.)
For each register, refer to 3.5 Function of Ports.
Before “HALT” instruction is executed, set each register pin-status. They will be
effective after CPU executes “HALT” instruction.
• This register is effective in all stand-by modes (IDLE2, IDLE1 or STOP).
• This register is effective when using PMC function. For details, refer to PMC
section.
The truth table to control Output/Input-buffer is below.
OE

PxnD

Output buffer

Input buffer

0

0

OFF

OFF

0

1

OFF

ON

1

0

OFF

OFF

1

1

ON

OFF

Note1: OE means an output enable signal before stand-by mode.Basically, PxCR is used as OE.
Note2: “n” in PxnD means bit-number of PORTx.

The subsequent actions performed in each mode are as follows:
a. IDLE2: Only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by
setting the following register.
Table 3.3.2 shows the registers of setting operation during IDLE2 mode.
Table 3.3.2 SFR setting operation during IDLE2 mode
Internal I/O

SFR

TMRA01

TA01RUN

TMRA23

TA23RUN

TMRA45

TA45RUN

TMRA67

TA67RUN

TMRB0

TB0RUN

TMRB1

TB1RUN

SIO0

SC0MOD1

SBI

SBIBR0

A/D converter

ADMOD1

WDT

WDMOD

b. IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to
operate.
c. STOP: All internal circuits stop operating.

92CZ26A-34

TMP92CZ26A

The operation of each of the different Halt Modes is described in Table 3.3.3.
Table 3.3.3 I/O operation during Halt Modes
Halt Mode
SYSCR2 

IDLE2
11

IDLE1
10

CPU, MAC

STOP
01

Stop

I/O ports

Depends on PxDR register setting

TMRA, TMRB
Available to select
Operation block

SIO,SBI
A/D converter
Block

WDT

Stop

I2S, LCDC, SDRAMC,
Interrupt controller,
SPIC,
USB

DMAC,

NDFC,

Operate

RTC, MLD

Operate

(2) How to release the Halt mode
These HALT states can be released by resetting or requesting an interrupt. The halt
release sources are determined by the combination between the states of interrupt
mask register  and the halt modes. The details for releasing the HALT status
are shown in Table 3.3.4.
• Released by requesting an interrupt
The operating released from the halt mode depends on the interrupt enabled status.
When the interrupt request level set before executing the HALT instruction exceeds
the value of interrupt mask register, the interrupt due to the source is processed after
releasing the halt mode, and CPU status executing an instruction that follows the
HALT instruction. When the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, releasing the halt
mode is not executed.(in non-maskable interrupts, interrupt processing is processed
after releasing the halt mode regardless of the value of the mask register.) However
only for INT0 to INT5, INT6, INT7(unsynchronous interrupt), INTKEY,INTRTC,
INTALM interrupts, even if the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, releasing the halt
mode is executed. In this case, interrupt processing, and CPU starts executing the
instruction next to the HALT instruction, but the interrupt request flag is held at “1”.
• Releasing by resetting
Releasing all halt status is executed by resetting.
When the STOP mode is released by RESET, it is necessary enough resetting time to
set the operation of the oscillator to be stable.
When releasing the halt mode by resetting, the internal RAM data keeps the state
before the “HALT” instruction is executed. However the other settings contents are
initialized. (Releasing due to interrupts keeps the state before the “HALT” instruction
is executed.)

92CZ26A-35

TMP92CZ26A
Table 3.3.4 Source of Halt state clearance and Halt clearance operation
Status of Received Interrupt
Halt mode

Interrupt

×



INTWDT

Source of Halt state clearance

Interrupt Enabled
(interrupt level) ≥ (interrupt mask)
IDLE2
IDLE1
STOP

INT0 to 5 (Note1)
INTKEY



INTUSB



×




Interrupt Disabled
(interrupt level) < (interrupt mask)
IDLE2
IDLE1
STOP



*2

*1

×

INT6 to 7(PORT) (Note1)







INT6 to 7(TMRB)



×

INTALM, INTRTC



*1

−

−

−

{

{

{

{

{

*2

*1

×
*1

{

{

{

×

×

×

×



×

{

{

×

×

×

×

×

×

INTTA0 to 7, INTTP0
INTTB00 to 01, INTTB10 to 11
INTRX,INTTX, INTSBI
INTI2S0 to 1, INTLCD,
INTAD, INTADHP



INTSPIRX,INTSPITX
INTRSC, INTRDY
INTDMA0 to 5
RESET

Reset initializes the LSI

: After clearing the Halt mode, CPU starts interrupt processing.
{: After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction.
×: It can not be used to release the halt mode.
−: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is

not this combination type.
*1: Releasing the halt mode is executed after passing the warmming-up time.
*2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, the system of low
power dissipation can be built. However, the way of use is limited as below.
• Shift to IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
• Release from IDLE1 mode :
Release Halt state by the request of INT_RESUME or INT_CLKON ( request of release SUSPEND )
Release Halt state by the request of INT_URST_STR or INT_URST_END ( request of RESET )

Note1: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level
H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly
started.

92CZ26A-36

TMP92CZ26A

(Example - releasing IDLE1 Mode)
An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode.

Address
8200H

LD

(PCFC), 02H

; Sets PC1 to INT0 interrupt.

8203H
8206H

LD
LD

(IIMC0), 00H
(INTE0), 06H

; Select INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.

8209H

EI

5

; Sets CPU interrupt level to 5.

820BH
820EH

LD
HALT

(SYSCR2), 28H

; Sets Halt mode to IDLE1 mode.
; Halts CPU.

INT0

INT0 interrupt routine.
RETI

820FH

LD

XX, XX

92CZ26A-37

TMP92CZ26A
(3) Operation
a. IDLE2 Mode
In IDLE2 Mode, only specific internal I/O operations, as designated by the
IDLE2 Setting Register, can take place. Instruction execution by the CPU stops.
Figure 3.3.8 illustrates an example of the timing for clearance of the IDLE2
Mode Halt state by an interrupt.

X1
A0~A23
D0~D31

Data

Data

RD

WR

Interrupt for
releasing Halt
IDLE2
mode

Figure 3.3.8 Timing chart for IDLE2 Mode Halt state cleared by interrupt

b. IDLE1 Mode
In IDLE1 Mode, only the internal oscillator and the RTC and MLD continue to
operate. The system clock stops.
In the Halt state, the interrupt request is sampled asynchronously with the
system clock; however, clearance of the Halt state (i.e. restart of operation) is
synchronous with it.
Figure 3.3.9 illustrates the timing for clearance of the IDLE1 Mode Halt state by
an interrupt.

X1
A0~A23
D0~D31

Data

Data

RD

WR

Interrupt for
releasing Halt
IDLE1
mode

Figure 3.3.9 Timing chart for IDLE1 Mode Halt state cleared by interrupt

92CZ26A-38

TMP92CZ26A
c.

STOP Mode

When STOP Mode is selected, all internal circuits stop, including the internal
oscillator.
After STOP Mode has been cleared system clock output starts when the warm-up
time has elapsed, in order to allow oscillation to stabilize.
Figure 3.3.10 illustrates the timing for clearance of the STOP Mode Halt state by an
interrupt.
Warm-up
time
X1
A0~A23
D0~D31

Data

Data

RD

Interrupt for
releasing Halt
STOP
mode

Figure 3.3.10 Timing chart for STOP Mode Halt state cleared by interrupt

Table 3.3.5 Example of warming-up time after releasing STOP-mode
@fOSCH =10 MHz

SYSCR2
8

01 (2 )

10 (214)

11 (216)

25.6 us

1.6384 ms

6.5536 ms

92CZ26A-39

TMP92CZ26A
Table 3.3.6 Input Buffer State Table
Input Buffer State
Port Name

Input Function
Name

When the CPU is operating
During Reset
When Used as When Used
function Pin as Input port

D0-D7

D0-D7

P10-P17

D8-D15

P60-P67

−

P71-P74

−

P75

NDR/ W

P76

WAIT

P90

−

P91

RXD0

P92

CTS0 ,SCLK0

P96 *1

INT4

P97

−

PA0-PA7 *1

KI0-7

PC0

INT0

PC1

INT1,TA0IN

PC2

INT2

PC3

INT3,TA2IN

PC4-PC7

−

PF0-PF5

−

PG0-PG2

−

PG4,PG5 *2
PG3 *2

ADTRG

PJ5-PJ6

−

PN0-PN7

−

PP1-PP2

−

PP3

INT5

PP4

INT6,TB0IN0

PP5

INT7,TB1IN0

PR0

SPDI

PR1-PR3

−

PT0-PT7

−

PU0-PU4,

−

PU6,PU7
PU5

−

OFF
16bit Start OFF
Boot Start ON
16bit Start OFF
Boot Start ON

ON upon

−

−
OFF

−

−

−

−

−

−

ON

ON

OFF

−

−

−

ON

OFF

external read

ON
ON
ON

OFF

−

−

ON

ON

OFF

−

−

−

−
ON

ON upon port
read

−

−

ON

−

OFF

ON

ON

−

−

−

ON

ON

OFF

−

−

−

OFF

ON

ON

−

PV6-PV7

SDA, SCL

PW0-PW7

−

PX5

X1USB

PX7

−
EI_PODDATA,
EI_SYNCLK,
EI_PODREQ,
EI_REFCLK,
EI_TRGIN,
EI_COMRESET

ON

PZ6-PZ7

−

−

DBGE

−

D+, D-

−

RESET

−

AM0,AM1

−

X1,XT1

−
OFF

PV0-PV2

PZ0-PZ5

In HALT mode (IDLE2/1/STOP)
=1
=0
When Used When Used When Used When Used
as function as Input port as function as Input port
Pin
Pin

ON

OFF

ON

ON

−

−

Always ON

−

IDLE2/DLE1: ON

ON: The buffer is always turned on. A current flows the input buffer if the input *1: Port having a pull-up/pull-down resistor.
*2: AIN input does not cause a current to flow through the buffer.

pin is not driven.
OFF: The buffer is always turned off.
- : No applicable

92CZ26A-40

TMP92CZ26A
Table 3.3.7 Output buffer State Table (1/2)
Output Buffer State
Port Name

Output Function
Name

D0-7

D0-7

P10-17

D8-15

During Reset

OFF
16bit Start ON
Boot Start OFF

P40-P47

A0-A7

P50-P57

A8-A15

P60-67

A16-A23

16bit Start ON
Boot Start OFF

P70

RD

ON

P71

WRLL , NDRE

P72

WRLU , NDWE

P73

EA24

P74

EA25

P75

R/ W

P76

−

P80

CS0

P81

CS1 , SDCS

P82

CS2 , CSZA ,
SDCS

P83

CS3 , CSXA

P84

CSZB

P85

CSZC

P86

CSZD , ND0CE

P87

CSXB , ND1CE

P90

TXD0

P91

−

P92

SCLK0

P96

PX

P97

PY

PC0-PC3

−

PC4

EA26

PC5

EA27

PC6

EA28

PC7

KO8

PF0

I2S0CKO

PF1

I2S0DO

PF2

I2S0WS

PF3

I2S1CKO

PF4

I2S1DO

PF5

I2S1WS

PF7

SDCLK

PG2

MX

PG3

MY

PJ0

SDRAS , SRLLB

PJ1

SDCAS , SRLUB

PJ2

SDWE , SRWR

PJ3

SDLLDQM

PJ4

SDLUDQM

PJ5

NDALE

PJ6

NDCLE

PJ7

SDCKE

PK0

LCP0

PK1

LLOAD

PK2

LFR

PK3

LVSYNC

PK4

LHSYNC

PK5

LGOE0

PK6

LGOE1

PK7

LGOE2

PL0-PL7

LD0-LD7

In HALT mode (IDLE2/1/STOP)

When the CPU is operating

When Used
as function
Pin
ON upon
external write

When Used
as Output
port

=1

When Used
as function
Pin

−
ON

=0

When Used
as Output
port

When Used When Used
as function as Output
Pin
port

−
OFF

−

ON

ON

OFF
ON

ON

OFF

−

−
ON

ON

OFF

−

ON

ON

OFF

−

−

−

ON

−

−

OFF

ON

ON

−

−

OFF

−

−

OFF
ON

ON

OFF

−

−

−

ON
OFF

ON

ON

ON

OFF

OFF

ON

ON

92CZ26A-41

ON

OFF

TMP92CZ26A

Table 3.3.8 Output buffer state table (2/2)
Output Buffer State

Port Name

Output Function
Name

PM1

MLDALM,TA1OUT

PM2

MLDALM

, ALARM

PM7

PWE

PN0-PN7

KO0-KO7

PP1

TA3OUT

PP2

TA5OUT

PP3

TA7OUT

PP4-PP5

−

PP6

TB0OUT0

PP7

TB1OUT0

PR0

−

PR1

SPDO

PR2

SPCS

PR3

SPCLK

PT0-PT7

LD8-LD15

PU0-PU6

LD16-LD22

PU7

In HALT mode (IDLE2/1/STOP)

When the CPU is operating
During Reset

=1

=0

When Used
as function

When Used
as Output

When Used
as function

When Used
as Output

Pin

port

Pin

port

When Used When Used
as function
as Output
Pin

port

ON

ON

ON

OFF

−

−

−

ON

ON

OFF

−

−

−

ON

ON

OFF

ON

OFF
OFF

ON

ON

OFF

LD23
EO_TRGOUT

ON

PV0

SCLK0

OFF

PV1

−

PV2

−

PV3-PV4

−

PV6

SDA

PV7

SCL

PW0-PW7

−

PX4

CLKOUT, LDIV

PX5

−

PX7

−

PZ0-PZ5

−

PZ6-PZ7

EO_MCUDATA,
EO_MCUREQ

D+, D-

−

X2

−

XT2

−

−

−

−

ON

ON

OFF

ON

OFF

ON

−

−

−

ON

ON

OFF

−

−

−

ON

ON

ON

OFF

OFF

ON/OF depend on USBC operation
IDLE2/1:ON,
Always ON

STOP: output ”H”
IDLE2/1:ON,
STOP: output ”HZ”

ON: The buffer is always turned on. When the bus is released,

*1: Port having a pull-up/pull-down resistor.

however, output buffers for some pins are turned off.
OFF: The buffer is always turned off.
- : No applicable

92CZ26A-42

TMP92CZ26A

3.4

Boot ROM
The TMP92CZ26A contains boot ROM for downloading a user program, and supports two
kinds of downloading methods.

3.4.1

Operation Modes
The TMP92CZ26A has two operation modes: MULTI mode and BOOT mode. The
operation mode is selected according to the AM1 and AM0 pin levels when RESET is
asserted.
(1) MULTI mode:

After reset, the CPU fetches instructions from external memory and
executes them.

(2) BOOT mode:

After reset, the CPU fetches instructions from internal boot ROM
and executes them. The boot ROM loads a user program into internal
RAM from USB, or via UART, and then branches to the internal
RAM. In this way the user program starts boot operation. Table 3.4.2
shows an outline of boot operation.
Table 3.4.1 Operation Modes

Mode Setting Pins
Operation Mode

RESET

AM1

AM0

0

1

MULTI

Start from external 16-bit bus memory

1

0

TEST (Setting prohibited)

1

1

BOOT (Start from internal boot ROM)

0

0

TEST (Setting prohibited)

Table 3.4.2 Outline of Boot Operation
Loading
Name

Operation after

Priority
Source

I/F

(a)

1

PC (UART)

UART

(b)

2

PC (USB_HOST)

USB

92CZ26A-43

Destination

Loading

Internal RAM

Branch to internal
RAM

TMP92CZ26A
3.4.2

Hardware Specifications of Internal Boot ROM
(1) Memory map
Figure 3.4.1 shows a memory map of BOOT mode.
The boot ROM incorporated in the TMP92CZ26A is an 8-Kbyte ROM area mapped to
addresses 3FE000H to 3FFFFFH.
In MULTI mode, the boot ROM is not mapped and the above area is mapped as an
external area.
000000H
Internal I/O
001FF0H
002000H
010000H
Internal RAM
(288 Kbytes)

046000H (Internal Backup RAM 16 Kbytes)
04A000H

3FE000H
Internal Boot ROM
(8 Kbytes)
3FFF00H
400000H

FFFF00H
FFFFFFH

(B) Reset/Interrupt (Note)
Vector Area (256 bytes)

(A) Reset/Interrupt (Note)
Vector Area (256 bytes)

Note: BROMCR = “1” : (B) when booting
BROMCR = “0” : (A) when multi mode

Figure 3.4.1 Memory Map of BOOT Mode
(2) Switching the boot ROM area to an external area
After the boot sequence is executed in BOOT mode, an application system program
may start running without a reset being asserted. In this case, it is possible to switch
the boot ROM area to an external area.

92CZ26A-44

TMP92CZ26A

3.4.3

Outline of Boot Operation
The method for downloading a user program can be selected from two types: from UART,
or via USB.
After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2.
Regardless of the downloading method used, the boot program downloads a user program
into the internal RAM and then branches to the internal RAM. Figure 3.4.3 shows how the
boot program uses the internal RAM (common to all the downloading methods).

Start
Yes
RESUME check
PMCCTL=1
No

Clock setting
• fSYS = fOSCH
• fUSB = fOSCH × 24/5
(a)

(b)
UART
check
No
No

Yes

Download via UART

USB
check
Yes
Download via
USB

Branch to internal RAM
46000h

Branch to internal RAM
3000h

Note 1: To download a user program via USB, a USB device driver and special application software are needed on
the PC.
Note 2: To download a user program via UART, special application software is needed on the PC.
Note 3: The (a), (b) in the above flowchart indicate points where the settings of external port pins are changed. For
details, see Table 3.4.3.

Figure 3.4.2 Flowchart for Internal Boot ROM Operation

92CZ26A-45

TMP92CZ26A

002000H
Work Area for Boot Program
(4 Kbytes)

003000H

Download Area for
User Program
(282 Kbytes)

049800H
Stack Area for
Boot Program
(2 Kbytes)
049FFFH

Figure 3.4.3 How the Boot Program Uses Internal RAM

92CZ26A-46

TMP92CZ26A

(1) Port settings
Table 3.4.3 shows the port settings by the boot program. When designing your
application system, please also refer to Table 3.4.4 for recommended pin connections
for using the boot program.
The boot program only sets the ports shown in the table below; other ports are left as
they are after reset or at startup of the boot program.

Table 3.4.3 Port Settings by the Boot Program
Port Name
UART

USB

Function
Name

Description
I/O

P90

TXD0

Output

P91

RXD0

Input

−−−

D+

I/O

−−−

D−

I/O

PU6

PUCTL

Output

(a)

(b)

No change from after reset
state (input port)

No change from (a)

Set as RXD0 input pin

(c)
Set as TXD0 output pin
No change from (b)

No change
No change from after reset
state (input port)

92CZ26A-47

Set as output port

No change from (b)

TMP92CZ26A

Table 3.4.4 Recommended Pin Connections
Port Name
UART

USB

Function
Name

Recommended Pin Connections for Each Download Method
I/O
UART
Connect to the level shifter.

USB

P90

TXD0

Output

No special setting is needed
for booting via USB.

P91

RXD0

Input

−−−

D+

I/O

No special setting is needed
for booting via UART.

−−−

D−

I/O

Connect to the USB connector
by adding a dumping resistor
If USB is not used, add a
(27Ω recommended). When
pull-up or pull-down resistor to
USB is not accessed, the pin
prevent flow-through current
level should be fixed with a
on the D+/D- pins.
resistor to prevent flow-through
current.

PU6

PUCTL

Output

Add a pull-up resistor (100
kΩ recommended) to prevent
transition to UART processing.

−

Connect to the USB connector
by adding a dumping resistor
(27Ω recommended) and a
programmable pull-up resistor
(1.5 kΩ recommended). When
USB is not accessed, the pin
level should be fixed with a
resistor to prevent flow-through
current.

This pin is used to control
ON/OFF of the D+ pin’s
pull-up resistor. Add a switch
externally so that the pull-up is
turned on when “1”. Reset sets
this pin as an input port, so
add a pull-down resistor (100
kΩ recommended).

Note 1: When a user program is downloaded from UART and USB is used in the system, the pull-up resistor for USB’s D+ pin
should not be turned on in BOOT mode.
Note 2: When a user program is downloaded via USB, do not start the UART application software on the PC.
Note 3: When a user program is downloaded via UART, do not connect a USB connector.
Note 4: When USB is not used, the D+ and D- pins must be pulled up or down to prevent flow-through current.

92CZ26A-48

TMP92CZ26A

(2) I/O register settings
Table 3.4.5 shows the I/O registers that are set by the boot program.
After the boot sequence, if execution moves to an application system program
without a reset being asserted, the settings of these I/O registers must be taken into
account. Also note that the registers in the CPU and the internal RAM remain in the
state after execution of the boot program.
Table 3.4.5 I/O Register Settings by Boot Program
Register Name

Set Value

Description

WDMOD

00H

Watchdog timer not active

WDCR

B1H

Watchdog timer disabled

SYSCR0

70H

High-frequency and low-frequency oscillators operating

SYSCR1

00H

Clock gear = 1/1

SYSCR2

2CH

Initial value

PLLCR0

00H

PLL clock not used

PLLCR1

00H

Normally PLL is disabled.

60H

or

However, only in the case of booting via USB, PLL is
activated for USB.

INTEUSB

04H

USB interrupt level setting

INTETC01

44H

INTTC interrupt level setting

Note:

The values to be set in the I/O registers for UART and USB are not described here. If these functions are
needed in a user program, set each I/O register as necessary.

92CZ26A-49

TMP92CZ26A

3.4.4

Downloading a User Program via UART
(1) Connection example
Figure 3.4.4 shows an example of connections for downloading a user program via
UART (using a 16-bit NOR Flash memory device as program memory).

UART 3 pins
TXD
Level RXD
Shifter

PC

TXD0 P90 (OUT)
RXD0, P91 (IN)

RTS

AM0

D+ DP82, CS2
P70, RD
PJ2, SRWR

TMP92CZ26A
D0 to D15

CE
OE
WE

NOR
Flash Memory
D0 toD15

AM1
A1 to 20

A0 toA19

Note: When USB is not used, add a pull-up or pull-down resistor to the D+ and D- pins to prevent flow-through
current.

Figure 3.4.4 UART Connection Example

(2) UART interface specifications
SIO channel 0 is used for downloading a user program.
The UART communication format in BOOT mode is shown below. Before booting, the
PC must also be set up with the same conditions.
Although the default baud rate is 9600 bps, this can be changed as shown in Table
3.4.8.
Serial transfer mode:

: UART (asynchronous) mode, full-duplex

Data length

: 8 bits

Parity bit

: None

STOP bit

: 1 bit

Handshake

: None

Baud rate (default)

: 9600 bps

92CZ26A-50

TMP92CZ26A

(3) UART data transfer format
Table 3.4.6 to Table 3.4.11 show the supported frequencies, data transfer format, baud
rate modification command, operation command, and version management
information, respectively.
Please also refer to the description of boot program operation later in this section.
Table 3.4.6 Supported Frequencies (X1)
6.00 MHz

8.00 MHz

9.00 MHz

10.00 MHz

Note: The built-in PLL (clock multiplier) is not used regardless of the oscillation frequency.

Table 3.4.7 Transfer Format
Byte Number to

Transfer data from PC to TMP92CZ26A

Baud Rate

Transfer data from TMP92CZ26A to PC

Transfer
Boot

1st byte

Matching data (5AH)

2nd byte

−

9600 bps

ROM

− (Frequency measurement and baud
rate auto setting)
OK: Echo back data (5AH)
Error: No transfer

3rd byte
to

−

Version management information
(See Table 3.4.10)

6th byte
7th byte

−

Frequency information

8th byte

Baud rate modification command
(See Table 3.4.8.)

−

9th byte

OK: Echo back data

−
10th byte
to

Error: Error code x 3

User program

New baud rate NG: Operation stop by checksum error

Intel Hex format (binary)

(n − 4)th byte
(n − 3)th byte

−

OK: SUM (High)

(n − 2)th byte

−

OK: SUM (Low)

(n − 1)th byte

User program start command (C0H)
(See Table 3.4.9.)

−

(See (4)-c).)

OK: Echo back data (C0H)
Error: Error code x 3

n’th byte
−
RAM

−

Branch to user program start address
“Error code x 3” means that the error code is transmitted three times. For example, if the error code is 62H, the
TMP92CZ26A transmits 62H three times. For error codes, see (4)-b).

92CZ26A-51

TMP92CZ26A

Table 3.4.8 Baud Rate Modification Command
Baud Rate (bps)

9600

19200

38400

57600

115200

Modification Command

28H

18H

07H

06H

03H

Note 1:

If fOSCH (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported.

Note 2:

If fOSCH (oscillation frequency) is 6.00, 8.00, or 9.00 MHz, 38400, 57600, and 115200 bps are not
supported.

Table 3.4.9 Operation Command
Operation Command

Operation

C0H

User program start

Table 3.4.10 Version Management Information
Version Information

ASCII Code

FRM1

46H, 52H, 4DH, 31H

Table 3.4.11 data of measuring frequency
X1-X2 oscillator frequency
(MHz)

6.000

8.000

9.000

10.000

09H

0AH

08H

0BH

(4) Description of the UART boot program operation
The boot program receives a user program sent from the PC via UART and transfers
it to the internal RAM. If the transfer ends normally, the boot program calculates
SUM and sends the result to the PC before executing the user program. The execution
start address is the first address received. The boot program enables users to perform
customized on-board programming.
When UART is used to download a user program, the maximum allowed program
size is 282 Kbytes (3000H – 49800H). (The extended Intel Hex format is supported.)
a)

Operation procedure
1. Connect the serial cable. This must be done before the microcontroller is reset.
2. Set the AM1 and AM0 pins to “1” and reset the microcontroller.
3. The receive data in the 1st byte is matching data (5AH). Upon starting in
BOOT mode, the boot program goes to a state in which it waits for matching
data. When matching data is received, the initial baud rate of the serial
channel is automatically set to 9600 bps.
4. The 2nd byte is used to echo back 5AH to the PC upon completion of the
automatic baud rate setting in the 1st byte. If automatic baud rate setting fails,
the boot program stops operation.
5. The 3rd through 6th bytes are used to send the version management
information of the boot program in ASCII code. The PC should check that the
correct version of the boot program is used.
6. The 7th byte is used to send information on the measured frequency. The PC
should check that the frequency of the resonator is measured correctly.
7.

The receive data in the 8th byte is baud rate modification data. The five kinds
of baud rate modification data shown in Table 3.4.8 are available. Even when

92CZ26A-52

TMP92CZ26A
the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must
be sent. Baud rate modification becomes effective after the echo back
transmission is completed.
8.

The 9th byte is used to echo back the received data to the PC when the data
received in the 8th byte is one of the baud rate modification data
corresponding to the operating frequency of the microcontroller. Then, the
baud rate is changed. If the received baud rate data does not correspond to the
operating frequency, the boot program stops operation after sending the baud
rate modification error code (62H).

9.

The receive data in the 10th to (n-4)th bytes is received as binary data in Intel
Hex format. No echo back data is returned to the PC.
The boot program ignores received data and does not send error code to the PC
until it receives the start mark (3AH for “:”) of Intel Hex format. After
receiving the start mark, the boot program receives a range of data from
record length to checksum and writes the received data to the specified RAM
addresses successively.
If a receive error or checksum error occurs, the boot program stops operation
without sending error code to the PC.
The boot program executes the SUM calculation routine upon detecting the
end record. Thus, after sending the end record, the PC should be placed in a
state in which it waits for SUM data.

10. The (n-3)th and (n-2)th bytes are used to send the SUM value to the PC in the
order of upper byte and lower byte. For details on how to calculate SUM, see
“SUM calculation” to be described later. SUM calculation is performed after
detecting the end record only when no receives error or checksum error has
occurred. Immediately after SUM calculation is completed, the boot program
sends the SUM value to the PC. After sending the end record, the PC should
determine whether or not writing to RAM has completed successfully based
on whether or not the SUM value is received from the boot program.
11. After sending the SUM value, the boot program waits for the user program
start command (C0H). If the SUM value is correct, the PC should send the
user program start command in the (n-1)th byte.
12. The n’th byte is used to echo back the user program start command to the PC.
After sending the echo back data, the boot program sets the stack pointer to
4A000H and jumps to the address that is received first as Intel Hex format
data.
13. If the user program start command is not correct or a receive error has
occurred, the boot program stops operation after sending the error code to the
PC three times.

92CZ26A-53

TMP92CZ26A

b) Error codes
The boot program uses the error codes shown in Table 3.4.12 to notify the
PC of its processing status.
Table 3.4.12 Error Codes
Error Code
62H

Meaning
Unsupported baud rate

64H

Invalid operation command

A1H

Framing error in received data

A3H

Overrun error in received data

Note 1: If a receive error occurs while a user program is being received, no error code will be sent to the PC.
Note 2: After sending an error code, the boot program stops operation.

c)

SUM calculation
1.

Calculation method
SUM is calculated by adding data in bytes and is returned in words, as
explained below.
Example:
If the data to be calculated consists of the 4 bytes
A1H

shown to the left, SUM is calculated as follows:

B2H

A1H + B2H + C3H + D4H = 02EAH

C3H

SUM (HIGH) = 02H
SUM (LOW) = EAH

D4H

2.

Data to be calculated
SUM is calculated from the data at the first received address through the last
received address.
Even if received addresses are not continuous, unwritten addresses are also
included in SUM calculation. The user program should not contain unwritten
gaps.

92CZ26A-54

TMP92CZ26A

d)

Notes on Intel Hex format (binary)
1.

After receiving the checksum of a record, the boot program waits for the start
mark (3AH for “:”) of the next record. If data other than 3AH is received
between records, it is ignored.

2.

Once the PC program has finished sending the checksum of an end record, it
must wait for 2 bytes of data (upper and lower bytes of SUM) before sending
any other data. This is because after receiving the checksum of an end record,
the boot program calculates SUM and returns the result to the PC in 2 bytes.

3.

Writing to areas other than internal RAM may cause incorrect operation. To
transfer a record, set the paragraph address to 0000H.

4.

Since the address pointer is initially set to 00H, the record type to be
transferred first does not have to be an address record.

5.

Addresses 3000H to 49800H are allocated as the user program download
area.

6.

A user program in Intel Hex format (ASCII codes) must be converted into
binary data in advance, as explained in the example below.
Example: How to convert an Intel Hex file into binary format
The following shows how an Intel Hex format file is displayed on a text editor.
: 103000000607F100030000F201030000B1F16010B7
: 00000001FF
However, the actual data consists of ASCII codes, as shown below.
3A3130333030303030303630374631303030333030303046323031303330303030
423146313630313042370D0A3A303030303030303146460D0A
Thus, the ASCII codes must be converted into binary data based on the conversion rules
shown in the table below.

ASCII Code

Binary Data

3A

3A (Only 3A remains the same.)

30 to 39

0 to 9

41 or 61

A

42 or 62

B

43 or 63

C

44 or 64

D

45 or 65

E

46 or 66

F

0D0A

Delete

Intel Hex format
Data record

3A 10 3000 00 0607F100030000F201030000B1F16010 B7
Data
Record type
Address
Record length

End record

: (Start mark)
3A 00 0000 01 FF
Data
Record type
Address
Record length
: (Start mark)

92CZ26A-55

Checksum

TMP92CZ26A

e)

User program receive error
If either of the following error conditions occurs while a user program is being
received, the boot program stops operation.
If the record type is other than 00H, 01H, or 02H
If a checksum error occurs

f)

Measured frequency/baud rate error
When the boot program receives matching data, it measures the oscillation
frequency. If an error is within plus or minus 3%, the boot program decides on that
frequency.
Each baud rate includes a setting error as shown in Table 3.4.13. For example,
in the case of 10.00 MHz /9600 bps, the baud rate is actually set at 9615.38 bps. To
establish communication, the sum of the baud rate setting error and the measured
frequency error must be within plus or minus 3 %.
Table 3.4.13 Baud Rate Setting Errors (%)
9600 bps

19200 bps

38400 bps

57600 bps

115200 bps

6.000 MHz

0.2

0.2

−

−

−

8.000 MHz

0.2

0.2

−

−

−

9.000 MHz

0.2

−0.7

−

−

−

10.000 MHz

0.2

0.2

−1.4

−

−
−: Not supported

92CZ26A-56

TMP92CZ26A

(5) Others
a)

Handshake function
Although the CTS pin is available in the TMP92CZ26A, the boot program does
not use it for transfer control.

b)

RS-232C connector
The RS-232C connector must not be connected or disconnected while the boot
program is running.

c)

Software on the PC
When downloading a user program via UART, special application software is
needed on the PC.

92CZ26A-57

TMP92CZ26A
3.4.5

Downloading a User Program via USB
(1) Connection example
Figure 3.4.5 shows an example of connections for downloading a user program via
USB (using a 16-bit NOR Flash memory device as program memory).

PUCTL

R1 = 1.5 kΩ

R4 =
100 kΩ
R2 = 27 Ω

PC
R3 = 27 Ω

PU6, LD22

RXD,P91
P82, CS2
P70, RD
PJ2, SRWR

D+
D−

TMP92CZ26A

AM0

D0 to D15

CE
OE
WE

NOR Flash
D0 to D15

AM1
A0 to A19

A1 to A20

Note 1:

The value of pull-up and pull-down resistors are recommended values.

Note 2:

The PU6 and LD22 pins are assigned as PUCTL (pull-up control) output for USB. Be careful about this if the
system uses the 24-bit TFT display function.

Note 3:

Since the input gates of the D+ and D- pins are always open even at unused (unaccessed) times, these pins
must be set to a fixed level to prevent flow-through current. Although the level setting is not specified in the
above diagram, be sure to fix the level of the D+ and D- pins by referring to the chapter on USB.

Figure 3.4.5 USB Connection Example

(2) USB interface specifications
When a user program is downloaded via USB, the oscillation frequency should be set
to 10.00 MHz. The transfer speed should be fixed to full speed (12 Mbps).
The boot program uses the following two transfer types.
Table 3.4.14 Transfer Types Used by the Boot Program
Transfer Type
Control Transfer
Bulk Transfer

Description
Used for transmitting standard requests and vendor requests.
Used for responding to vendor requests and transmitting a user program.

92CZ26A-58

TMP92CZ26A

The following shows an overview of the USB communication flow.
(Legends)
Control Transfer
Bulk Transfer

Host (PC)
Connection
Recognition

TMP92CZ26A
Send GET_DISCRIPTOR

Send DESCRIPTOR information

Send the microcontroller information command

Send microcontroller information data

Prepare microcontroller
information data

Check data

Data Transfer
Convert Intel Hex
format data into binary
data

Send the microcontroller information command

Send microcontroller information data

Prepare microcontroller
information data

Check data
Send the user program transfer start command

Send data

Send a user program

Load the received data into the
specified RAM address area
& prepare microcontroller
information data
(If the received data cannot be loaded
into RAM for some reason, it is
discarded.)

Transfer End
Processing
Transmit the transfer result
command 2 seconds after
completion of user
program transfer

Send the transfer result command

Send transfer result data

Prepare transfer result data

Check data

Branch to
internal RAM

Figure 3.4.6 Overall Flowchart

92CZ26A-59

TMP92CZ26A

Table 3.4.15 Vendor Request Commands
Command Name

Value of

Operation

Notes

bRequest
Microcontroller information
command

00H

Send microcontroller
information

Microcontroller information data is
sent by bulk IN transfer after the
setup stage is completed.

User program transfer start
command

02H

Receive a user
program

Set the size of a user program in
wIndex.
The user program is received by bulk
OUT transfer after the setup stage is
completed.

User program transfer result
command

04H

Send the transfer
result

Transfer result data is sent by bulk IN
transfer after the setup stage is
completed.

Table 3.4.16 Setup Command Data Structure
Field Name
bmRequestType

bRequest

Value
40H

00H, 02H, 04H

Meaning
D7

0: Host to Device

D6-D5

2: Vendor

D4-D0

0: Device

00H: Microcontroller information
02H: User program transfer start
04H: User program transfer result

wValue

00H~FFFFH

Own data number
(Not used by boot program)

wIndex

00H~FFFFH

User program size
(Used when starting a user program transfer)

wLength

0000H

92CZ26A-60

Fixed

TMP92CZ26A

Table 3.4.17 Standard Request Commands
Standard Request

Response Method

GET_STATUS

Automatic response by hardware

CLEAR_FEATURE

Automatic response by hardware

SET_FEATURE

Automatic response by hardware

SET_ADDRESS

Automatic response by hardware

GET_DISCRIPTOR

Automatic response by hardware

SET_DISCRIPTOR

Not supported

GET_CONFIGRATION

Automatic response by hardware

SET_CONFIGRATION

Automatic response by hardware

GET_INTERFACE

Automatic response by hardware

SET_INTERFACE

Automatic response by hardware

SYNCH_FRAME

Ignored

Table 3.4.18 Information Returned by GET_DISCRIPTOR
DeviceDescriptor
Field Name

Value

Meaning

Blength

12H

18 bytes

BdescriptorType

01H

Device descriptor

BcdUSB

0110H

USB Version 1.1

BdeviceClass

00H

Device class (Not in use)

BdeviceSubClass

00H

Sub command (Not in use)

BdeviceProtocol

00H

Protocol (Not in use)

BmaxPacketSize0

40H

EP0 maximum packet size (64 bytes)

IdVendor

0930H

Vendor ID

IdProduct

6504H

Product ID (0)

BcdDevice

0001H

Device version (v0.1)

Imanufacturer

00H

Index value of string descriptor indicating manufacturer
name

Iproduct

00H

Index value of string descriptor indicating product name

IserialNumber

00H

Index value of string descriptor indicating product serial
number

BnumConfigurations

01H

There is one configuration.

92CZ26A-61

TMP92CZ26A

ConfigrationDescriptor
Field Name

Value

bLength

09H

bDescriptorType

02H

wTotalLength

0020H

Meaning
9 bytes
Configuration descriptor
Total length (32 bytes) which each descriptor of both
configuration descriptor, interface
and endpoint is added.

bNumInterfaces

01H

There is one interface.

bConfigurationValue

01H

Configuration number 1

iConfiguration

00H

Index value of string descriptor indicating
configuration name (Not in use)

bmAttributes

80H

Bus power

MaxPower

31H

Maximum power consumption (49 mA)

InterfaceDescriptor
Field Name

Value

Meaning

bLength

09H

9 bytes

bDescriptorType

04H

Interface descriptor

bInterfaceNumber

00H

Interface number 0

bAlternateSetting

00H

Alternate setting number 0

bNumEndpoints

02H

There are two endpoints.

bInterfaceClass

FFH

Specified device

bInterfaceSubClass

00H

bInterfaceProtocol

50H

Bulk only protocol

iIinterface

00H

Index value of string descriptor indicating interface
name (Not in use)

EndpointDescriptor
Field Name

Value

Meaning


blength

07H

7 bytes

bDescriptorType

05H

Endpoint descriptor

bEndpointAddress

01H

EP1= OUT

bmAttributes

02H

Bulk transfer

wMaxPacketSize

0040H

Payload 64 bytes

bInterval

00H

(Ignored for bulk transfer)

bLength

07H

7 bytes

bDescriptor

05H

bEndpointAddress

82H

EP2 = IN

bmAttributes

02H

Bulk transfer

wMaxPacketSize

0040H

Payload 64 bytes

bInterval

00H

(Ignored for bulk transfer)


Endpoint descriptor

92CZ26A-62

TMP92CZ26A

Table 3.4.19 Information Returned for the Microcontroller Information Command
Microcontroller Information
TMP92CZ26A

ASCII Code
54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20H, 20H, 20H, 20H

Table 3.4.20 Information Returned for the User Program Transfer Result Command
Transfer Result

Value

Error Conditions

No error

00H

User program not received

02H

The user program transfer result is received without the user program
transfer start command being received first.

Received file not in Intel Hex format

04H

The first data of a user program is not “:” (3AH).

User program size error

06H

The size of a received user program is larger than the value set in
wIndex of the user program transfer start command.

Download address error

08H

The specified user program download address is not in the designated
area.

Protocol error or other error

0AH

The user program transfer start or user program transfer result
command is received first.

The user program size is over 10 Kbytes.

A checksum error is detected in the Intel Hex file.
A record type error is detected in the Intel Hex file.
The length of an address record in the Intel Hex file is 3 or longer.
The length of an end record in the Intel Hex file is other than 0.

92CZ26A-63

TMP92CZ26A

(3) Description of the USB boot program operation
The boot program loads a user program in Intel Hex format sent from the PC into the
internal RAM. When the user program has been loaded successfully, the user program
starts executing from the first address received.
The boot program thus enables users to perform customized on-board programming.
a.

Operation procedure
1.

Connect the USB cable.

2.

Set the AM0 and AM1 pins to “1” and reset the microcontroller.

3.

After recognizing USB connection, the PC checks the information on the
connected device using the GET_DISCRIPTOR command.

4.

The PC sends the microcontroller information command by control transfer
(vendor request). After the setup stage is completed, the PC checks
microcontroller information data by bulk IN transfer.

5.

Upon receiving the microcontroller information command, the boot program
prepares microcontroller information in ASCII code.

6.

The PC prepares the user program to be loaded by converting an Intel Hex file
into binary format.

7.

The PC sends the user program transfer start command by control transfer
(vendor request). After the setup stage is completed, the PC transfers the user
program by bulk OUT transfer.

8.

After the user program has been transferred, the PC waits for about two
seconds and then sends the user program transfer result command by control
transfer (vendor request). After the setup stage is completed, the PC checks
the transfer result by bulk IN transfer.

9.

Upon receiving the user program transfer result command, the boot program
prepares the transfer result value to be returned.

10. If the transfer result is other than OK, the boot program enters the error
processing routine and will not automatically recover from it. In this case,
terminate the device driver on the PC and retry from step 2.

92CZ26A-64

TMP92CZ26A

b.

Notes on the user program format (binary)
1.

After receiving the checksum of a record, the boot program waits for the start
mark (3AH for “:”) of the next record. If data other than 3AH is received
between records, it is ignored.

2.

Since the address pointer is initially set to 00H, the record type to be
transferred first does not have to be an address record.

3.

Addresses 3000H to 497FFH (282 Kbytes) are allocated as the user program
download area. The user program should be contained within this area.

4.

A user program in Intel Hex format (normally written in ASCII code) must be
converted into binary data before it can be transferred. See the example
below for how to convert an Intel Hex file into binary format.
When a user program is downloaded via USB, the maximum allowed record
length is 250 bytes.
Example: Transfer data when writing 16-byte data in Intel Hex format from address 3000H
The following shows how an Intel Hex format file is displayed on a text editor.
: 103000000607F100030000F201030000B1F16010B7
: 00000001FF
However, the actual data consists of ASCII codes, as shown below.
3A3130333030303030303630374631303030333030303046323031303330303030
423146313630313042370D0A3A303030303030303146460D0A
Thus, the ASCII codes must be converted into binary data based on the conversion rules shown
in the table below.

ASCII Code

Binary Data

3A

3A (Only 3A remains the same.)

30~39

0~9

41 or 61

A

42 or 62

B

43 or 63

C

44 or 64

D

45 or 65

E

46 or 66

F

0D0A

Delete

The above Intel Hex file is converted into binary data as follows:
Data record

3A 10 3000 00 0607F100030000F201030000B1F16010 B7
Data
Record type
Address
Record length
: (Start mark\)

End record

3A 00 0000 01 FF
Checksum
Record type
Address
Record length
: (Start mark)

92CZ26A-65

Checksum

TMP92CZ26A

(4) Others
a)

USB connector
The USB connector must not be connected or disconnected while the boot
program is running.

b)

Software on the PC
To download a user program via USB, a USB device driver and special
application software are needed on the PC.

92CZ26A-66

TMP92CZ26A

3.5 Interrupts
Interrupts are controlled by the CPU Interrupt Mask Register  (bits 12 to 14
of the Status Register) and by the built-in interrupt controller.
TMP92CZ26A has a total of 56 interrupts divided into the following five types:
Interrupts generated by CPU: 9 sources
• Software interrupts: 8 sources
• Illegal Instruction interrupt: 1 source
Internal interrupts: 38 sources
• Internal I/O interrupts: 30 sources
• Micro DMA Transfer End interrupts /HDMA Transfer End interrupts: 6 sources
• Micro DMA Transfer End interrupts: 2 source
External interrupts: 9 sources
• Interrupts on external pins (INT0 to INT7, INTKEY)
A fixed individual interrupt vector number is assigned to each interrupt source. Any one of
seven levels of priority can also be assigned to each maskable interrupt. Non-maskable
interrupts have a fixed priority level of 7, the highest level.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
to the CPU. When more than one interrupt are generated simultaneously, the interrupt
controller sends the priority value of the interrupt with the highest priority to the CPU. (The
highest priority level is 7, the level used for non-maskable interrupts.)
The CPU compares the interrupt priority level which it receives with the value held in the
CPU interrupt mask register . If the priority level of the interrupt is greater than or
equal to the value in the interrupt mask register, the CPU accepts the interrupt.
However, software interrupts and illegal instruction interrupts generated by the CPU, and
are processed irrespective of the value in .
The value in the interrupt mask register  can be changed using the EI instruction
(EI num sets  to num). For example, the command EI3 enables the acceptance of all
non-maskable interrupts and of maskable interrupts whose priority level, as set in the
interrupt controller, is 3 or higher. The commands EI and EI0 enable the acceptance of all
non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence
both are equivalent to the command EI1).
The DI instruction (Sets  to 7) is exactly equivalent to the EI7 instruction. The DI
instruction is used to disable all maskable interrupts (since the priority level for maskable
interrupts ranges from 0 to 6). The EI instruction takes effect as soon as it is executed.
In addition to the general-purpose interrupt processing mode described above, there is also a
micro DMA processing mode that can transfer data to internal/external memory and built-in
I/O, and HDMA processing mode. In micro DMA mode the CPU, and in HDMA mode the DMA
controller automatically transfers data in 1byte, 2byte or 4byte blocks. HDMA mode allows
transfer faster than Micro DMA mode.
In addition, the TMP92CZ26A also has a software start function in which micro DMA and
HDMA processing is requested in software rather than by an interrupt. Figure 3.5.1 is a
flowchart showing overall interrupts processing.

92CZ26A-67

TMP92CZ26A

DMA soft start
request

Interrupt processing

Interrupt specified
by DMA
start vector ?

YES

Clear interrupt request flag
NO
Interrupt vector calue “V”
read interrupt request F/F clear

Start specified
by HDMA

General-purpose
interrupt
processing

YES

to HDMA processing flow

NO
PUSH
PC
PUSH
SR
SR ← Level of
accepted
interrupt + 1
INTNEST ← INTNEST + 1

Data transfer by micro
DMA
Micro DMA
processing

COUNT ← COUNT − 1
PC ← (FFFF00H + V)
COUNT = 0
NO

Interrupt processing
program

RETI instruction
POP SR
POP PC
INTNEST ← INTNEST − 1

End

Figure 3.5.1 Interrupt processing Sequence

92CZ26A-68

YES

Clear vector register
generating micro DMA
transfer end interrupt
(INTTC0)

TMP92CZ26A

3.5.1

General-purpose Interrupt Processing

When the CPU accepts an interrupt, it usually performs the following sequence of
operations. However, in the case of software interrupts and illegal instruction interrupts
generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and
(5).
(1) The CPU reads the interrupt vector from the interrupt controller. When more than one
interrupt with the same priority level have been generated simultaneously, the
interrupt controller generates an interrupt vector in accordance with the default
priority and clears the interrupt requests. (The default priority is determined as
follows: The smaller the vector value, the higher the priority.)
(2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the
stack (Pointed to by XSP).
(3) The CPU sets the value of the CPU’s interrupt mask register  to the priority
level for the accepted interrupt plus 1. However, if the priority level for the accepted
interrupt is 7, the register’s value is set to 7.
(4) The CPU increments the interrupt nesting counter INTNEST by 1.
(5) The CPU jumps to the address given by adding the contents of address FFFF00H + the
interrupt vector, then starts the interrupt processing routine.
On completion of interrupt processing, the RETI instruction is used to return control
to the main routine. RETI restores the contents of the program counter and the status
register from the stack and decrements the interrupt nesting counter INTNEST by 1.
Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts,
however, can be enabled or disabled by a user program. A program can set the priority
level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt
request.) If an interrupt request is received for an interrupt with a priority level equal to
or greater than the value set in the CPU interrupt mask register , the CPU will
accept the interrupt. The CPU interrupt mask register  is then set to the value
of the priority level for the accepted interrupt plus 1.
If during interrupt processing, an interrupt is generated with a higher priority than the
interrupt currently being processed, or if, during the processing of a non-maskable
interrupt processing, a non-maskable interrupt request is generated from another source,
the CPU will suspend the routine which it is currently executing and accept the new
interrupt. When processing of the new interrupt has been completed, the CPU will resume
processing of the suspended interrupt.
If the CPU receives another interrupt request while performing processing steps (1) to
(5), the new interrupt will be sampled immediately after execution of the first instruction
of its interrupt processing routine. Specifying DI as the start instruction disables nesting
of maskable interrupts.
After a reset, initializes the interrupt mask register  to 111, disabling all
maskable interrupts.
Table 3.5.1 shows the TMP92CZ26A interrupt vectors and micro DMA start vectors.
FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area.

92CZ26A-69

TMP92CZ26A
Table 3.5.1 TMP92CZ26A Interrupt Vectors and Micro DMA/HDMA Start Vectors
Default
Priority

Type

Interrupt Source and Source of
Micro DMA Request

Vector
Value

Micro DMA
Address Refer
/HDMA Start
to Vector
Vector

1

Reset or [SWI0] instruction

0000H

FFFF00H

2
3
4
5
6
7
8
9
10

[SWI1] instruction
Illegal instruction or [SWI2] instruction
[SWI3] instruction
[SWI4] instruction
[SWI5] instruction
[SWI6] instruction
[SWI7] instruction
(Reserved)
INTWD: Watchdog timer
Micro DMA (Note 2)
INT0: INT0 pin input
INT1: INT1 pin input
INT2: INT2 pin input
INT3: INT3 pin input
INT4: INT4 pin input (TSI)
INTALM: ALM(8KHz, 512Hz, 64Hz, 2Hz, 1Hz)
INTTA4: 8-bit timer 4
INTTA5: 8-bit timer 5
INTTA6: 8-bit timer 6
INTTA7: 8-bit timer 7
INTP0: Protect 0 (Write to SFR)
(Reserved)
INTTA0: 0
INTTA1: 8-bit timer 1
INTTA2: 8-bit timer 2
INTTA3: 8-bit timer 3
INTTB0: 16-bit timer 0
INTTB1: 16-bit timer 0
INTKEY: Key wakeup
INTRTC: RTC (Alarm interrupt)
(Reserved)
INTLCD: LCDC
INTRX: Serial receive end
INTTX: Serial transmission end
INTTB10: 16-bit timer 1
INTTB11: 16-bit timer 1
INT5: INT5 pin input
INT6: INT6 pin input
INT7: INT7 pin input
INTI2S0: I2S (Channel 0)
INTI2S1: I2S (Channel 1)
INTADM: AD Monitor function
INTSBI: SBI
INTSPIRX: SPIC receive
INTSPITX: SPIC transmission
INTRSC: NAND Flash controller
INTRDY: NAND Flash controller
INTUSB: USB
(Reserved)
(Reserved)

0004H
0008H
000CH
0010H
0014H
0018H
001CH
0020H
0024H

FFFF04H
FFFF08H
FFFF0CH
FFFF10H
FFFF14H
FFFF18H
FFFF1CH
FFFF20H
FFFF24H

−

−

−

0028H
002CH
0030H
0034H
0038H
003CH
0040H
0044H
0048H
004CH
0050H
0054H
0058H
005CH
0060H
0064H
0068H
006CH
0070H
0074H
0078H
007CH
0080H
0084H
0088H
008CH
0090H
0094H
0098H
009CH
00A0H
00A4H
00A8H
00ACH
00B0H

FFFF28H
FFFF2CH
FFFF30H
FFFF34H
FFFF38H
FFFF3CH
FFFF40H
FFFF44H
FFFF48H
FFFF4CH
FFFF50H
FFFF54H
FFFF58H
FFFF5CH
FFFF60H
FFFF64H
FFFF68H
FFFF6CH
FFFF70H
FFFF74H
FFFF78H
FFFF7CH
FFFF80H
FFFF84H
FFFF88H
FFFF8CH
FFFF90H
FFFF94H
FFFF98H
FFFF9CH
FFFFA0H
FFFFA4H
FFFFA8H
FFFFACH
FFFFB0H

0AH(Note 1)
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H (Note 1)
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH

00B4H
00B8H
00BCH
00C0H
00C4H

FFFFB4H
FFFFB8H
FFFFBCH
FFFFC0H
FFFFC4H

2DH
2EH
2FH
30H
31H

Non
maskable

−

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Maskable

92CZ26A-70

TMP92CZ26A

Default
Priority
51
52
53
54
55
56
57
58
59
60
−
to
−

Type

Maskable

Interrupt Source and Source of
Micro DMA Request
INTADHP: AD most priority conversion end
INTAD: AD conversion end
INTTC0/INTDMA0: Micro DMA0 /HDMA0 end
INTTC1/INTDMA1: Micro DMA1 /HDMA1 end
INTTC2/INTDMA2: Micro DMA2 /HDMA2 end
INTTC3/INTDMA3: Micro DMA3 /HDMA3 end
INTTC4/INTDMA4: Micro DMA4 /HDMA4 end
INTTC5/INTDMA5: Micro DMA5 /HDMA5 end
INTTC6
: Micro DMA6 end
INTTC7
: Micro DMA7 end
(Reserved)

Note 1: When standing-up micro DMA/HDMA , set at edge detect mode.
Note 2 : Micro DMA default priority.
Micro DMA stands up prior to other maskable interrupt.

92CZ26A-71

Vector
Value
00C8H
00CCH
00D0H
00D4H
00D8H
00DCH
00E0H
00E4H
00E8H
00ECH
00F0H
:
00FCH

Micro DMA
Address Refer
/HDMA Start
to Vector
Vector
FFFFC8H
FFFFCCH
FFFFD0H
FFFFD4H
FFFFD8H
FFFFDCH
FFFFE0H
FFFFE4H
FFFFE8H
FFFFECH
FFFFF0H
:
FFFFFCH

32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
−
to
−

TMP92CZ26A
3.5.2

Micro DMA processing

In addition to general-purpose interrupt processing, the TMP92CZ26A also includes a
micro DMA function and HDMA function. This section explains about Micro DMA function.
For the HDMA function, please refer 3.23 DMA controller.
Micro DMA processing for interrupt requests set by micro DMA is performed at the
highest priority level for maskable interrupts (Level 6), regardless of the priority level of
the interrupt source.
Because the micro DMA function has been implemented with the cooperative operation
of CPU, when CPU is a state of standby (IDLE2,IDLE1,STOP) by HALT instruction, the
requirement of micro DMA will be ignored (Pending).
Micro DMA is supported 8 channels and can be transferred continuously by specifying
the micro DMA burst function in the following.
Note: When using the micro DMA transfer end interrupt, always write “1” to bit 7 of SIMC register.

(1) Micro DMA operation
When an interrupt request is generated by an interrupt source that specified by the
micro DMA /HDMA start vector register, and Micro DMA start is specified by DMA
selection register, the micro DMA triggers a micro DMA request to the CPU at
interrupt priority level 6 and starts processing the request. When IFF = 7, Micro DMA
request cannot be accepted.
The 8 micro DMA channels allow micro DMA processing to be set for up to 8 types of
interrupt at once.
When micro DMA is accepted, the interrupt request flip-flop assigned to that
channel is cleared. Data in 1byte or 2byte or4byte blocks is automatically transferred
at once from the transfer source address to the transfer destination address set in the
control register, and the transfer counter is decremented by “1”. If the value of the
counter after it has been decremented is not “0”, DMA processing ends with no change
in the value of the micro DMA start vector register. If the value of the decremented
counter is “0”, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from
the CPU to the interrupt controller.
In addition, the micro DMA /HDMA start vector register is cleared to “0”, the next
micro DMA operation is disabled and micro DMA processing terminates.
If an interrupt request is triggered for the interrupt source in use during the
interval between the time at which the micro DMA /HDMA start vector is cleared and
the next setting, general-purpose interrupt processing is performed at the interrupt
level set. Therefore, if the interrupt is only being used to initiate micro DMA /HDMA
(and not as a general-purpose interrupt), the interrupt level should first be set to 0
(e.g., interrupt requests should be disabled).
If micro DMA and general-purpose interrupts are being used together as described
above, the level of the interrupt which is being used to initiate micro DMA processing
should first be set to a lower value than all the other interrupt levels. In this case,
edge-triggered interrupts are the only kinds of general interrupts which can be
accepted.

92CZ26A-72

TMP92CZ26A
If micro DMA requests are set simultaneously for more than one channel, priority is
not based on the interrupt priority level but on the channel number: The lower the
channel number, the higher the priority (Channel 0 thus has the highest priority and
channel 7 the lowest).
Note: Don’t start any micro DMAs by one interrupt. If any micro DMA are set by it, micro DMA that
channel number is biggest (priority is lowest) is not started.(Because interrupt flag is
cleared by micro DMA that priority is highest)
Although the control registers used for setting the transfer source and transfer
destination addresses are 32 bits wide, this type of register can only output 24-bit
addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a
32-bit address are not valid).
Three micro DMA transfer modes are supported: 1byte transfer, 2byte (One word)
transfers and 4byte transfers. After a transfer in any mode, the transfer source and
transfer destination addresses will either be incremented or decremented, or will
remain unchanged. This simplifies the transfer of data from memory to memory, from
I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various
transfer modes, see section 3.5.2 (4) “Detailed description of the transfer mode
register”.
Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing
operations can be performed per interrupt source (Provided that the transfer counter
for the source is initially set to 0000H).
Micro DMA processing can be initiated by any one of 48 different interrupts – the 47
interrupts shown in the micro DMA start vectors in Table 3.5.1 and a micro DMA soft
start.
Figure 3.5.2 shows a 2-byte transfer carried out using a micro DMA cycle in
Transfer Destination Address INC Mode (micro DMA transfers are the same in every
mode except Counter Mode). (The conditions for this cycle are as follows: both source
and destination memory are internal-RAM and multipled by 4 numbered source and
destination addresses).

1 state

(1)

(2)

(3)

(4)

src

dst

(5)

fSYS
A23 to 0

(Note) Actually, src and dst address are not outputted to A23-0 pins
because they are address of internal-RAM.

Figure 3.5.2 Timing for micro DMA cycle
States (1) and (2): Instruction fetch cycle (Prefetches the next instruction code)
State (3): Micro DMA read cycle.
State (4): Micro DMA write cycle.
State (5): (The same as in state (1), (2).)

92CZ26A-73

TMP92CZ26A
(2) Soft start function
The TMP92CZ26A can initiate micro DMA/HDMA either with an interrupt or by
using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is
initiated by a Write cycle which writes to the register DMAR.
Writing “1” to each bit of DMAR register causes micro DMA or HDMA to be
performed once. On completion of the transfer, the bits of DMAR for the completed
channel are automatically cleared to “0”.
When writing again “1” to it, soft start can execute continuously until the DMA
transfer counter (DMACn) or HDMA transfer counter B (HDMACBn) become “0”.
When a burst is specified by the register DMAB, data is transferred continuously
from the initiation of micro DMA until the value in the micro DMA transfer counter is
“0”.

Note1: If it is started by software, don’t set any channels to start in same time.
Note2: If be started sequentially, restart it after confirming micro DMA of all channels is completed
(all micro DMA are set to “0”).

Symbol

DMAR

NAME
DMA
Request

Address
109H
(Prohibit
RMW)

7

6

5

4

DREQ7

DREQ6

DREQ5

DREQ4

0

0

0

3

DREQ3
R/W
0
0
1: Start DMA

2

1

0

DREQ2

DREQ1

DREQ0

0

0

0

(3) Transfer control registers
The transfer source address and the transfer destination address are set in the following
registers. An instruction of the form LDC cr,r can be used to set these registers.

Channel 0
DMAS0

Micro DMA source address register 0

DMAD0

Micro DMA destination address register 0
DMAC0
DMAM0

Micro DMA counter register 0
Micro DMA mode register 0

Channel 7
DMAS7

Micro DMA source address register 7

DMAD7

Micro DMA destination address register 7
DMAC7
DMAM7

Micro DMA counter register 7
Micro DMA mode register 7

8 bits
16 bits
32 bits

92CZ26A-74

TMP92CZ26A
(4) Detailed description of the transfer mode register
0

0

0

Mode

DMAMn[4:0]
000zz

001zz

010zz

011zz

100zz

101zz

110zz

1 1 1 00

ZZ:

DMAM0 to 7

Mode Description
Destination INC mode
(DMADn +) ← (DMASn)
DMACn
← DMACn - 1
if DMACn = 0 then INTTCn

Execution Time

5 states

Destination DEC mode
(DMADn -) ← (DMASn)
DMACn
← DMACn - 1
if DMACn = 0 then INTTCn

5 states

Source INC mode
(DMADn) ← (DMASn +)
DMACn
← DMACn - 1
if DMACn = 0 then INTTCn

5 states

Source DEC mode
(DMADn) ← (DMASn -)
DMACn
← DMACn – 1
if DMACn = 0 then INTTCn

5 states

Source and destination INC mode
(DMADn +) ← (DMASn +)
DMACn
← DMACn – 1
If DMACn = 0 then INTTCn
Source and destination DEC mode
(DMADn -) ← (DMASn -)
DMACn ← DMACn – 1
If DMACn = 0 then INTTCn
Destination and fixed mode
(DMADn) ← (DMASn)
DMACn ← DMACn – 1
If DMACn = 0 then INTTCn
Counter mode
DMASn ← DMASn + 1
DMACn ← DMACn – 1
If DMACn = 0 then INTTCn

6 states

6 states

5 states

5 states

00 = 1-byte transfer
01 = 2-byte transfer
10 = 4-byte transfer
11 = Reserved

Note 1: n stands for the micro DMA channel number (0 to 7).
DMADn+/DMASn+: Post increment (Register value is incremented after transfer).
DMADn−/DMASn−: Post decrement (Register value is decremented after transfer).
“I/O” signifies fixed memory addresses; “memory” signifies incremented or decremented memory addresses.
Note 2: The transfer mode register should not be set to any value other than those listed above.
Note 3: The execution state number shows number of best case (1-state memory access).

92CZ26A-75

TMP92CZ26A

3.5.3

Interrupt Controller Operation

The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
For each of the 59 interrupts channels there is an interrupt request flag (consisting of a
flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector
register. The interrupt request flag latches interrupt requests from the peripherals.
The flag is cleared to “0” in the following cases: when a reset occurs, when the CPU reads
the channel vector of an interrupt it has received, when the CPU receives a micro DMA
request (when micro DMA is set), when the CPU receives a HDMA request (when HDMA is
set), when a micro DMA burst transfer is terminated, and when an instruction that clears
the interrupt for that channel is executed (by writing a micro DMA start vector to the
INTCLR register).
An interrupt priority can be set independently for each interrupt source by writing the
priority to the interrupt priority setting register (e.g., INTE0 or INTE12). Six interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source.
If more than one interrupt request with a given priority level are generated
simultaneously, the default priority (The interrupt with the lowest priority or, in other
words, the interrupt with the lowest vector value) is used to determine which interrupt
request is accepted first. The 3rd and 7th bits of the interrupt priority setting register
indicate the state of the interrupt request flag and thus whether an interrupt request for a
given channel has occurred.
If several interrupts are generated simultaneously, the interrupt controller sends the
interrupt request for the interrupt with the highest priority and the interrupt’s vector
address to the CPU. The CPU compares the mask value set in  of the status
register (SR) with the priority level of the requested interrupt; if the latter is higher, the
interrupt is accepted. Then the CPU sets SR to the priority level of the accepted
interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests
with a priority value equal to or higher than the value set in SR (e.g., interrupts
with a priority higher than the interrupt being processed) will be accepted.
When interrupt processing has been completed (e.g., after execution of a RETI instruction),
the CPU restores to SR the priority value which was saved on the stack before the
interrupt was generated.
The interrupt controller also includes eight registers which are used to store the micro
DMA /HDMA start vector. Writing the start vector of the interrupt source for the micro
DMA or /HDMA processing (See Table), enables the corresponding interrupt to be processed
by micro DMA or HDMA processing. The values must be set in the micro DMA parameter
registers (e.g., DMAS and DMAD) or HDMA parameter registers (e.g., HDMAS, and
HDMAD) prior to micro DMA or HDMA processing.

92CZ26A-76

Micro
DMA/HDMA
counter 0
interrupt

92CZ26A-77

INTTC4/INTDMA4
INTTC5/INTDMA5
INTTC6
INTTC7

INT1
INT2
INT3
INT4
INTALM
INTTA4
INTTA5

INT0

INTWD

Q

Q

Figure 3.5.3 Block Diagram of Interrupt Controller

Micro DMA/HDMA selection register

INTTC0/
INTDMA0

D
Q
CLR

RESET

D5
D4
D3
D2
D1
D0

Dn + 3
Interrupt request F/F

C

B

Y1
Y2
Y3
Y4
Y5
Y6

Decorder

6

51
Selector

S

V = E0H
V = E4H
V = E8H
V = ECH

V = 28H
V = 2CH
V = 30H
V = 34H
V = 38H
V = 3CH
V = 40H
V = 44H

6

V = 20H
V = 24H

DMA0V
DMA1V
DMA2V
DMA3V
DMA4V
DMA5V
DMA6V
DMA7V

Soft start

Interrupt vector read
Micro DMA acknowledge

S
R

Interrupt
request F/F

D
Q
CLR

A

Micro DMA/HDMA start vector setting register

Reset

Dn + 2

Dn + 1

Dn

Priority setting register

S
RESET
R
Interrupt vector
read

Interrupt request F/F

Interrupt controller

6

1

6

1
7

8

7

A
B
C

8 input OR

0
1
2

D2
D3
D4
D5
D6
D7

Interrupt vector
read

Interrupt vector
generator

D0
D1

3 INTRQ2 to 0

6

A
B
C
HDMA channel priority
encorder

5

0
1
2

6 input OR

Micro DMA channel priority
encorder

52

1
2 Highest A
priority
3 interrupt B
4 level selectC
5
6
7

signal to CPU

Priority encorderInterrupt request

3

3

Interrupt
mask
detect

HALT release

3

Micro DMA request

HDMA channel

HDMA request

Micro DMA channel
specification

HDMA

3

IFF＝7 then 0

During
STOP

During
IDLE1

Interrupt request
signal

EI 1 to 7
DI

INT0,1 to 4,INTKEY, INTRTC
INTALM

RESET

INTRQ2∼0 ≥ IFF
2∼0 then 1.

3

3

IFF2 to 0

Interrupt mask F/F RESET

CPU

TMP92CZ26A

TMP92CZ26A
(1) Interrupt priority setting registers
Symbol

Name

Address

7

6

F0H

−
R

−

5

4

3

−
R/W

−

I0C
R
0

−
INTE0

INT0
enable

Always write “0”.
INTE12

INTE34

INTE56

INT1 & INT2
enable

INT3 & INT4
enable

INT5 & INT6
enable

D0H

D1H

D2H

INT2
I2M2
I2M1
R/W
0
0

I2C
R
0

I2M0
0

INT4
I4M2
I4M1
R/W
0
0
INT6
I6M2
I6M1
R/W
0
0

I4C
R
0
I6C
R
0

I1C
R
0

I4M0

I3C
R
0

0
I6M0

I5C
R
0

0

−
INTE7

INT7
enable

D3H

−
R

−

−
R/W

−

I7C
R
0

Always write “0”.
INTETA01

INTETA23

INTETA45

INTETA67

INTTA0 &
INTTA1
enable

D4H

INTTA2 &
INTTA3
enable

D5H

INTTA4 &
INTTA5
enable

D6H

INTTA6 &
INTTA7
enable

D7H

Interrupt request flag

ITA1C
R
0
ITA3C
R
0
ITA5C
R
0
ITA7C
R
0

INTTA1 (TMRA1)
ITA1M2 ITA1M1
R/W
0
0
INTTA3 (TMRA3)
ITA3M2 ITA3M1
R/W
0
0
INTTA5 (TMRA5)
ITA5M2 ITA5M1
R/W
0
0
INTTA7 (TMRA7)
ITA7M2 ITA7M1
R/W
0
0

lxxM2
0
0
0
0
1
1
1
1

lxxM1
0
0
1
1
0
0
1
1

92CZ26A-78

ITA1M0
0
ITA3M0
0
ITA5M0
0
ITA7M0

lxxM0
0
1
0
1
0
1
0
1

0

ITA0C
R
0
ITA2C
R
0
ITA4C
R
0
ITA6C
R
0

2

1

INT0
I0M1
R/W
0
0
INT1
I1M2
I1M1
R/W
0
0
I0M2

INT3
I3M2
I3M1
R/W
0
0
INT5
I5M2
I5M1
R/W
0
0
INT7
I7M2
I7M1
R/W
0
0
INTTA0 (TMRA0)
ITA0M2 ITA0M1
R/W
0
0
INTTA2 (TMRA2)
ITA2M2 ITA2M1
R/W
0
0
INTTA4 (TMRA4)
ITA4M2 ITA4M1
R/W
0
0
INTTA6 (TMRA6)
ITA6M2 ITA6M1
R/W
0
0

Function (Write)
Disables interrupt requests
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests

0
I0M0
0
I1M0
0
I3M0
0
I5M0
0
I7M0
0
ITA0M0
0
ITA2M0
0
ITA4M0
0
ITA6M0
0

TMP92CZ26A

Symbol

Name

Address

INTTB00 &

INTETB0

INTTB01

D8H

enable

INTTB10 &

INTETB1

INTTB11

D9H

enable

INTRX0 &

INTES0

INTTX0

DBH

enable

INTSBI &

INTESBIADM INTADM

E0H

enable

INTESPI

INTSPI
enable

E1H

7

6

5

4

INTTB01 (TMRB0)
ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C
R
R/W
R
0
0
0
0
0
INTTB11 (TMRB1)
ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C
R
R/W
R
0
0
0
0
0

INTEUSB

enable

E3H

enable

E5H

0

0

−

−

0

0

−

−

−

−

−

−

Always write “0”.
−
INTERTC

INTRTC
enable

E8H

−

−

−

−

Always write “0”.

0

INTKEY
enable

E9H

0

−

−

−

−

Always write “0”.

Interrupt request flag

INTTB00 (TMRB0)
ITB00M2 ITB00M1 ITB00M0
R/W
0
0
0
INTTB10 (TMRB1)
ITB10M2 ITB10M1 ITB10M0
R/W
0
0
0

lxxM2
0
0
0
0
1
1
1
1

lxxM1
0
0
1
1
0
0
1
1

92CZ26A-79

IKC
R
0

lxxM0
0
1
0
1
0
1
0
1

0

0

0

INTUSB
IUSBC IUSBM2 IUSBM1 IUSBM0
R
R/W
0
0
0
0
INTALM
IALMC IALMM2 IALMM1 IALMM0
R
R/W
0
0
0
0
INTRTC
IRC
IRM2
IRM1
IRM0
R
R/W

−
INTEKEY

0

INTSPITX
INTSPIRX
ISPITC ISPITM2 ISPITM1 ISPITM0 ISPIRC ISPIRM2 ISPIRM1 ISPIRM0
R
R/W
R
R/W

−
INTEALM

1

INTTX0
INTRX0
ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0
R/W
R
R/W
0
0
0
0
0
0
0
INTADM
INTSBI
IADM0C IADMM2 IADMM1 IADMM0 ISBI0C ISBIM2 ISBIM1 ISBIM0
R
R/W
R
R/W
0
0
0
0
0
0
0
0

Always write “0”.
INTALM

2

ITX0C
R
0

−
INTUSB

3

0

0

INTKEY
IKM2
IKM1
R/W
0

0

IKM0

0

Function (Write)
Disables interrupt requests
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests

0

TMP92CZ26A

Symbol

Name

Address

7

6

5

4

3

2

1

0

−

INTELCD

INTLCD
enable

INTI2S0 &
INTEI2S01 INTI2S1
enable
INTRSC &
INTENDFC INTRDY
enable

INTEP0

0INTEAD

EAH

EBH

ECH

INTP0
enable

EEH

INTAD &
INTADHP
enable

EFH

Interrupt request flag

INTLCD
ILCD1C ILCDM2 ILCDM1 ILCDM0
R
R/W
Always write “0”.
0
0
0
0
INTI2S1
INTI2S0
II2S1C II2S1M2 II2S1M1 II2S1M0 I I2S0C II2S0M2 II2S0M1 II2S0M0
R
R/W
R/W
R/W
0
0
0
0
0
0
0
0
−

−

−

−

INTRSC
IRSCC IRSCM2 IRSCM1 IRSCM0 IRDYC
R
R/W
R
0
0
0
0
0
−
−
−
−
−
IP0C
R
R/W
R
Always write “0”.
0
INTADHP
IADHPC IADHPM2 IADHPM1 IADHPM0 IADC
R
R/W
R/W
0
0
0
0
0

lxxM2
0
0
0
0
1
1
1
1

lxxM1
0
0
1
1
0
0
1
1

92CZ26A-80

lxxM0
0
1
0
1
0
1
0
1

INTRDY
IRDYM2 IRDYM1 IRDYM0
R/W
0
0
0
INTP0
IP0M2
IP0M1
IP0M0
R/W
0
0
INTAD
IADM2 IADM1
IADM0
R/W
0
0
0

Function (Write)
Disables interrupt requests
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests

TMP92CZ26A

Symbol

Name

Address

7

6

5

4

3

2

ITC1M0

ITC0C

ITC0M2

INTTC1/INTDMA1
INTETC01
/INTEDMA01

INTETC23
/INTEDMA23

INTTC0/INTDMA0 &
INTTC1/INTDMA1

ITC1C

F1H

enable

INTTC3/INTDMA3

ITC3C

F2H

enable

ITC1M1

INTTC0/INTDMA0

R/W
0
0
INTTC3/INTDMA3
ITC3M2

ITC3M1

0

R
0

R
0

/INTEDMA45

INTETC67

INTTC4/INTDMA4 &
INTTC5/INTDMA5

ITC5C

F3H

enable

INTTC6 & INTTC7
enable

ITC3M0

ITC2C

R/W
0

0

0

R
0

INTWD
enable

F7H

ITC5M2

ITC5M1

ITC5M0

ITC7C

R
0

R/W
0
0
INTTC7 (DMA7)

ITC4C

ITC7M2

ITC7M1

0

R/W
0

0

R
0

ITC7M0

ITC6C

0

R
0

−
R

−

−
R/W

−

Always write “0”.

Interrupt request flag

R/W
0
0
INTTC2/INTDMA2
ITC2M2

ITC2M1

0
ITC2M0

0

R/W
0

0

INTTC4/INTDMA4

−
INTWDT

ITC0M0

ITC4M2

ITC4M1

ITC4M0

/IDMA5C /IDMA5M2 /IDMA5M1 /IDMA5M0 /IDMA4C /IDMA4M2 /IDMA4M1 /IDMA4M0

R
0

F4H

ITC0M1

/IDMA3C /IDMA3M2 /IDMA3M1 /IDMA3M0 /IDMA2C /IDMA2M2 /IDMA2M1 /IDMA2M0

INTTC5/INTDMA5
INTETC45

0

/IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0

R
0

INTTC2/INTDMA2 &

ITC1M2

1

lxxM2
0
0
0
0
1
1
1
1

lxxM1
0
0
1
1
0
0
1
1

92CZ26A-81

lxxM0
0
1
0
1
0
1
0
1

ITCWD
R
0

R/W
0
0
INTTC6 (DMA6)
ITC6M2

ITC6M1

0
ITC6M0

R/W
0
0
INTWD
−
−
−

−

Function (Write)
Disables interrupt requests
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests

0
−
−

TMP92CZ26A
(2)

Symbol

External interrupt control
Name

Address

Interrupt
IIMC0

7

6

5

4

3

2

1

0

I5EDGE

I4EDGE

I3EDGE

I2EDGE

I1EDGE

I0EDGE

I0LE

−

W

W

W

W

W

W

R/W

R/W

0

0

0

0

0

0

0

F6H

input mode

INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0

(Prohibit

control 0

RMW)

0: Rising

0: Rising

0: Rising

0: Rising

0: Rising

0: Rising

1: Falling

1: Falling

1: Falling

1: Falling

1: Falling

1: Falling

0: Edge

0
Always
write “0”.

mode
1: Level
mode

Interrupt
IIMC1

FAH

input mode

(Prohibit

control 0

I7EDGE

I6EDGE

W

W

0

0

INT7EDGE INT6EDGE

RMW)

0: Rising

0: Rising

1: Falling

1: Falling

Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense.
(change from “1” to “0”)
DI
LD

(IIMC0), XXXXXX0-B

; Switches from level to edge.

LD

(INTCLR), 0AH

; Clears interrupt request flag.

NOP
NOP
NOP
EI

; Wait EI execution

Note 2: X: Don’t care, –: No change
Note 3: See electrical characteristics in section 4 for external interrupt input pulse width.
Note 4: In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and
INT7 don’t depend on IIMC1 register setting. INT6 and INT7 operate by setting
TBnMOD.
Settings of External Interrupt Pin Function
Interrupt

Pin Name

INT0

PC0

Mode
Rising edge

INT1

PC1

INT2

PC2

INT3

PC3

INT4

P96

INT5
INT6
INT7

PP3
PP4
PP5

Setting Method
 = 0, = 0

Falling edge

 = 0,  = 1

High level

 = 1

Rising edge

 = 0

Falling edge

 = 0

Rising edge

 = 0

Falling edge

 = 1

Rising edge

 = 0

Falling edge

 = 1

Rising edge

 = 0

Falling edge

 = 1

Rising edge

 = 0

Falling edge

 = 1

Rising edge

 = 0

Falling edge

 = 1

Rising edge

 = 0

Falling edge

 = 1

92CZ26A-82

TMP92CZ26A
(3)
Symbol

SIO receive interrupt control
Name

SIO
SIMC

interrupt
mode
control

Address

7

6

5

4

3

2

1

0

−

−

IR0LE

W

W

W

0

0

1

F5H

Always

Always

0:INTRX0

(Prohibit

write “0”

write “0”

edge

RMW)

(Note)

mode
1:INTRX0
level
mode

Note: When using the micro DMA transfer end interrupt, always write “1”.

INTRX0 edge enable
0
Edge detect INTRX0
1
“H” level INTRX0

92CZ26A-83

TMP92CZ26A
(4) Interrupt request flag clear register
The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start
vector, as given in Table 3.5.1 to the register INTCLR.
For example, to clear the interrupt flag INT0, perform the following register operation after
execution of the DI instruction.
INTCLR

Symbol

INTCLR

Name

Address

Interrupt

F8H

clear

(Prohibit

control

RMW)

←

0AH

; Clears interrupt
flag INT0.

request

7

6

5

4

3

2

1

0

CLRV7

CLRV6

CLRV5

CLRV4

CLRV3

CLRV2

CLRV1

CLRV0

0

0

0

0

0

0

0

0

W
Interrupt vector

(5) Micro DMA start vector registers
These registers assign micro DMA /HDMA processing to sets which source corresponds to
DMA. The interrupt source whose micro DMA /HDMA start vector value matches the vector set
in one of these registers is designated as the micro DMA /HDMA start source.
When the micro DMA transfer counter (DMACn) or HDMA transfer counter B (HDMACBn)
value reaches “0”, the micro DMA /HDMA transfer end interrupt corresponding to the channel
is sent to the interrupt controller, the micro DMA /HDMA start vector register is cleared, and
the micro DMA /HDMA start source for the channel is cleared. Therefore, in order for micro
DMA /HDMA processing to continue, the micro DMA /HDMA start vector register must be set
again during processing of the micro DMA /HDMA transfer end interrupt.
If the same vector is set in the micro DMA /HDMA start vector registers of more than one
channel, the lowest numbered channel takes priority.
Accordingly, if the same vector is set in the micro DMA /HDMA start vector registers for two
different channels, the interrupt generated on the lower-numbered channel is executed until
micro DMA /HDMA transfer is complete. If the micro DMA /HDMA start vector for this channel
has not been set in the channel’s micro DMA /HDMA start vector register again, micro DMA
/HDMA transfer for the higher-numbered channel will be commenced. (This process is known
as micro DMA /HDMA chaining.)

92CZ26A-84

TMP92CZ26A

Symbol

Name

Address

7

6

DMA0
DMA0V

start

5

4

3

DMA0V5

DMA0V4

DMA0V3

2

1

0

DMA0V2

DMA0V1

DMA0V0

0

0

0

DMA1V2

DMA1V1

DMA1V0

0

0

0

DMA2V2

DMA2V1

DMA2V0

0

0

0

DMA3V2

DMA3V1

DMA3V0

0

0

0

DMA4V2

DMA4V1

DMA4V0

0

0

0

DMA5V2

DMA5V1

DMA5V0

0

0

0

DMA6V2

DMA6V1

DMA6V0

0

0

0

DMA7V2

DMA7V1

DMA7V0

0

0

0

R/W

100H

0

vector

0

0

DMA0 start vector
DMA1
DMA1V

start

DMA1V5

DMA1V4

DMA1V3

0

0

0

R/W

101H

vector

DMA1 start vector
DMA2
DMA2V

start

DMA2V5

DMA2V4

DMA2V3

0

0

0

R/W

102H

vector

DMA2 start vector
DMA3
DMA3V

start

DMA3V5

DMA3V4

DMA3V3

0

0

0

R/W

103H

vector

DMA3 start vector
DMA4V5

DMA4V4

DMA4V3

0

0

0

DMA5V5

DMA5V4

DMA5V3

DMA4
DMA4V

start

R/W

104H

vector

DMA4 start vector
DMA5
DMA5V

start

R/W

105H
0

vector

0

0

DMA5 start vector
DMA6V5

DMA6V4

DMA6V3

0

0

0

DMA7V5

DMA7V4

DMA7V3

DMA6
DMA6V

start

R/W

106H

vector

DMA6 start vector
DMA7
DMA7V

start

R/W

107H
0

vector

0

0

DMA7 start vector

(6) Micro DMA/HDMA select register
This register selectable that is started either Micro DMA or HDMA processing.
Micro DMA /HDMA start vector register (DMAnV) shared with both functions. When
interrupt which match with vector value that is set to DMA/HDMA start vector register
generated, use this register.

Symbol

NAME

Address

7

6

5
DMASEL5

4

3

DMA/HDMA
select

1

0

DMASEL4 DMASEL3 DMASEL2 DMASEL1 DMASEL0
R/W

Micro
DMASEL

2

10AH

0
0:Micro

0
0:Micro

0
0:Micro

0
0:Micro

DMA5

DMA4

DMA3

DMA2

1:HDMA5

1:HDMA4

1:HDMA3

1:HDMA2

92CZ26A-85

0
0:Micro
DMA1

0
0:Micro
DMA0

1:HDMA1 1:HDMA0

TMP92CZ26A
(7) Specification of a micro DMA burst
Specifying the micro DMA burst function causes micro DMA transfer, once started, to
continue until the value in the transfer counter register reaches “0”. Setting any of the bits in
the register DMAB which correspond to a micro DMA channel (as shown below) to “1” specifies
that any micro DMA transfer on that channel will be a burst transfer.

Symbol

DMAB

Name
DMA
burst

Address

108H

7

6

5

4

DBST7

DBST6

DBST5

DBST4

3

2

1

0

DBST3

DBST2

DBST1

DBST0

0

0

0

0

R/W
0

0

0

0

1: DMA request on Burst mode

92CZ26A-86

TMP92CZ26A
(8) Notes
The instruction execution unit and the bus interface unit in this CPU operate
independently. Therefore, if immediately before an interrupt is generated, the CPU fetches
an instruction which clears the corresponding interrupt request flag, the CPU may execute
this instruction in between accepting the interrupt and reading the interrupt vector. In this
case, the CPU will read the default vector 0004H and jump to interrupt vector address
FFFF04H.
To avoid this, an instruction which clears an interrupt request flag should always be
preceded by a DI instruction. And in the case of setting an interrupt enable again by EI
instruction after the execution of clearing instruction, execute EI instruction after clearing
and more than 3-instructions (e.g., “NOP” × 3 times). If placed EI instruction without
waiting NOP instruction after execution of clearing instruction, interrupt will be enable
before request flag is cleared.
In the case of changing the value of the interrupt mask register  by execution of
POP SR instruction, disable an interrupt by DI instruction before execution of POP SR
instruction.
In addition, please note that the following two circuits are exceptional and demand
special attention.

INT0 level mode

INTRX

In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the
interrupt request flip-flop for INT0 does not function. The peripheral interrupt
request passes through the S input of the flip-flop and becomes the Q output. If the
interrupt input mode is changed from edge mode to level mode, the interrupt
request flag is cleared automatically.
If the CPU enters the interrupt response sequence as a result of INT0 going from 0
to 1, INT0 must then be held at 1 until the interrupt response sequence has been
completed. If INT0 is set to level mode so as to release a halt state, INT0 must be
held at 1 from the time INT0 changes from 0 to 1 until the halt state is released.
(Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing
INT0 to revert to 0 before the halt state has been released.)
When the mode changes from level mode to edge mode, interrupt request flags
which were set in level mode will not be cleared. Interrupt request flags must be
cleared using the following sequence.
DI
LD (IIMC0), 00H
; Switches from level to edge.
LD (INTCLR), 0AH ; Clears interrupt request flag.
NOP
; Wait EI execution
NOP
NOP
EI
In level mode (The register SIMC set to “1”), the interrupt request flip-flop
can only be cleared by a reset or by reading the serial channel receive buffer. It
cannot be cleared by an instruction.

Note: The following instructions or pin input state changes are equivalent to instructions which
clear the interrupt request flag.
INT0: Instructions which switch to level mode after an interrupt request has been
generated in edge mode.
The pin input changes from high to low after an interrupt request has been
generated in level mode. (“H” → “L”)
INTRX: Instructions which read the receive buffer.

92CZ26A-87

TMP92CZ26A

3.6

DMAC (DMA Controller)

The TMP92CZ26A incorporates a DMA controller (DMAC) having six channels. This DMAC can
realize data transfer faster than the micro DMA function by the 900/H1 CPU.
The DMAC has the following features:
1) Six independent channels of DMA
2) Two types of transfer start requests
Hardware request (using an interrupt source connected with the INTC) or software
request can be selected for each channel.
3) Various source/destination combinations
The combination of transfer source and destination can be selected for each channel
from the following four types: memory to memory, memory to I/O, I/O to memory, I/O
to I/O.
4) Transfer address mode
Only the dual address mode is supported.
5) Dual-count mechanism and DMA end interrupt
Two count registers are provided to execute multiple DMA transfers by one DMA
request and to generate multiple DMA requests at a time. The DMA end interrupt
(INTDMA0 to INTDMA5) is also provided so that a general-purpose interrupt routine
can be used to prepare for the next processing.
6) Priorities among DMA channels (the same as the micro DMA acceptance specifications
of the INTC)
DMA requests are basically accepted in the order in which they are asserted. If more
than one request is asserted simultaneously or it looks as if two requests were
asserted simultaneously because one of the requests has been put on hold while other
processing was being performed, the smaller-numbered channel is given a higher
priority.
7) DMAC bus occupancy limiting function
The DMAC incorporates a special timer for limiting its bus occupancy time to avoid
excessive interference with the CPU or LCDC operation.
8) The DMAC can be used in HALT (IDLE2) mode.

92CZ26A-88

TMP92CZ26A

3.6.1 Block Diagram
Figure 3.6.1 shows an overall block diagram for the DMAC.

Bus
Multiplexer

Address Bus

SDRAM Controller

State

LCD Controller

Address Bus
Data Bus
State

Bus ACK
Bus REQ

CPU
Interrupt REQ
7

31

0

0

→Micro DMA source address setting

DMAR
Micro DMA REQ,
Micro DMA Channel

→Micro DMA burst setting
DMASEL

State

DMASn

→DMAC or micro DMA request
source setting

→DMAC or micro DMA soft start
setting
DMAB

Data Bus

Bus ACK

Bus REQ

INTC (Interrupt Controller)

DMAnV

Source Memory, I/O
Address Bus

Micro DMA ACK,
INTTCn

Destination Memory, I/O
Address Bus

DMADn
Data Bus
→Micro DMA destination address setting
State
15
0
DMACn

Address Bus
Data Bus
State

→Micro DMA transfer count setting
7
0
DMAMn
→Micro DMA mode setting

DMA ACK,
INTDMAn

Bus ACK

DMAC
DMA REQ,
DMA Channel

Bus REQ

→DMAC or micro DMA select
setting

31

0

Address Bus

HDMASn
State

→DMA source address setting

Data Bus

HDMADn
→DMA destination address setting
15
0
HDMACAn
→DMA transfer count A setting
HDMACBn
→DMA transfer count B setting
HDMAMn

7

0

→DMA mode setting
HDMAE
→DMA operation enable/disable
HDMATR
→DMA maximum bus occupancy
time setting, mode setting

Note: “n” denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5).

Figure 3.6.1 Overall Block Diagram

92CZ26A-89

TMP92CZ26A

3.6.2

SFRs

The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit
data bus.
(1) HDMASn (DMA Transfer Source Address Setting Register)
The HDMASn register is used to set the DMA transfer source address. When the source
address is updated by DMA execution, HDMASn is also updated.
HDMAS0 to HDMAS5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.

HDMASn Register
bit Symbol
HDMASn

7

6

5

4

DnSA7

DnSA6

DnSA5

DnSA4

Read/Write
After reset

Channel 1
Channel 2
Channel 3
Channel 4
Channel 5

DnSA2

DnSA1

DnSA0

0

0

0

0

15

14

13

0

12

11

10

9

8

DnSA15

DnSA14

DnSA13

DnSA12

DnSA11

DnSA10

DnSA9

DnSA8

0

0

0

0

0

0

0

19

18

17

16

DnSA19

DnSA18

DnSA17

DnSA16

0

0

0

Source address [7:0] for DMAn

R/W
0

Source address [15:8] for DMAn

23

22

21

20

DnSA23

DnSA22

DnSA21

DnSA20

R/W
0

0

Function

Channel 0

DnSA3

0

Read/Write
After reset

0

0

Function

bit Symbol

1

0

Read/Write
After reset

2

R/W

Function

bit Symbol

3

0

0

0

Source address [23:16] for DMAn

Source address

Source address

[23:16]

[15:8]

Source address
[7:0]
HDMAS0

(0902H)

(0901H)

(0900H)
HDMAS1

(0912H)

(0911H)

(0922H)

(0921H)

(0910H)
HDMAS2
(0920H)
HDMAS3

(0932H)

(0931H)

(0930H)
HDMAS4

(0942H)

(0941H)

(0940H)
HDMAS5

(0952H)

(0951H)

(0950H)

Note: Read-modify-write instructions can be used on all these registers.

Figure 3.6.2 HDMASn Register

92CZ26A-90

TMP92CZ26A

(2) HDMADn (DMA Transfer Destination Address Setting Register)
The HDMADn register is used to set the DMA transfer destination address. When the
destination address is updated by DMA execution, HDMADn is also updated.
HDMAD0 to HDMAD5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.

HDMADn

bit Symbol

HDMADn Register
5
4

7

6

DnDA7

DnDA6

DnDA5

DnDA4

0

0

0

0

15

14

13

12

DnDA15

DnDA14

DnDA13

DnDA12

0

0

0

0

Read/Write
After reset

23

22

21

20

DnDA23

DnDA22

DnDA21

DnDA20

Channel 1
Channel 2
Channel 3
Channel 4
Channel 5

0

0

0

11

10

9

8

DnDA11

DnDA10

DnDA9

DnDA8

0

0

0

0

19

18

17

16

DnDA19

DnDA18

DnDA17

DnDA16

0

0

0

0

R/W
0

0

Function

Channel 0

0

Destination address [15:8] for DMAn

Read/Write
After reset

0
DnDA0

R/W

Function

bit Symbol

1
DnDA1

Destination address [7:0] for DMAn

Read/Write
After reset

2
DnDA2

R/W

Function

bit Symbol

3
DnDA3

0

0

Destination address [23:16] for DMAn

Destination

Destination

Destination

address

address

address

[23: 16]

[15: 8]

[7: 0]
HDMAD0

(0906H)

(0905H)

(0904H)
HDMAD1

(0916H)

(0915H)

(0926H)

(0925H)

(0914H)
HDMAD2
(0924H)
HDMAD3

(0936H)

(0935H)

(0934H)
HDMAD4

(0946H)

(0945H)

(0944H)
HDMAD5

(0956H)

(0955H)

(0954H)

Note: Read-modify-write instructions can be used on all these registers.

Figure 3.6.3 HDMADn Register

92CZ26A-91

TMP92CZ26A

(3) HDMACAn (DMA Transfer Count A Setting Register)
The HDMACAn register is used to set the number of times a DMA transfer is to be
performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536
transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers). Even
when the transfer count A is updated by DMA execution, HDMACAn is not updated.
HDMACA0 to HDMACA5 have the same configuration.

HDMACAn

bit Symbol

HDMACAn Register
5
4
3

7

6

DnCA7

DnCA6

DnCA5

DnCA4

Read/Write
After reset

0

0

0

Channel 1
Channel 2
Channel 3
Channel 4
Channel 5

DnCA2

DnCA1

DnCA0

0

0

0

11

10

9

8

DnCA11

DnCA10

DnCA9

DnCA8

0

0

0

DnCA3

0

15

14

13

12

DnCA15

DnCA14

DnCA13

DnCA12

0

R/W
0

0

0

Function

Channel 0

0

Transfer count A [7:0] for DMAn

Read/Write
After reset

1

R/W

Function

bit Symbol

2

0

0

Transfer count A [15:8] for DMAn

Transfer count A

Transfer count A

[15: 8]

[7: 0]
HDMACA0

(0909H)

(0908H)
HDMACA1

(0919H)

(0918H)
HDMACA2

(0929H)

(0928H)
HDMACA3

(0939H)

(0938H)
HDMACA4

(0949H)

(0948H)
HDMACA5

(0959H)

(0958H)

Note: Read-modify-write instructions can be used on all these registers.

Figure 3.6.4 HDMACAn Register

92CZ26A-92

TMP92CZ26A

(4) HDMACBn (DMA Transfer Count B Setting Register)
The HDMACBn register is used to set the number of times a DMA request is to be made.
HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request,
FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count B is updated
by DMA execution, HDMACBn is also updated.
HDMACB0 to HDMACB5 have the same configuration.

HDMACBn

bit Symbol

HDMACBn Register
5
4
3

7

6

DnCB7

DnCB6

DnCB5

DnCB4

Read/Write
After reset

0

0

0

Channel 1
Channel 2
Channel 3
Channel 4
Channel 5

DnCB2

DnCB1

DnCB0

0

0

0

11

10

9

8

DnCB11

DnCB10

DnCB9

DnCB8

0

0

0

DnCB3

0

15

14

13

12

DnCB15

DnCB14

DnCB13

DnCB12

0

R/W
0

0

0

Function

Channel 0

0

Transfer count B [7:0] for DMAn

Read/Write
After reset

1

R/W

Function

bit Symbol

2

0

0

Transfer count B [15:8] for DMAn

Transfer count B

Transfer count B

[15: 8]

[7: 0]
HDMACB0

(090BH)

(090AH)
HDMACB1

(091BH)

(091AH)
HDMACB2

(092BH)

(092AH)
HDMACB3

(093BH)

(093AH)
HDMACB4

(094BH)

(094AH)
HDMACB5

(095BH)

(095AH)

Note: Read-modify-write instructions can be used on all these registers.

Figure 3.6.5 HDMACBn Register

92CZ26A-93

TMP92CZ26A

(5) HDMAMn (DMA Transfer Mode Setting Register)
The HDMAMn register is used to set the DMA transfer mode.
HDMAM0 to HDMAM5 have the same configuration.

7
HDMAMn

6

bit Symbol

HDMAMn Register
5
4
3

2

1

0

DnM4

DnM2

DnM1

DnM0

0

0

DnM3

Read/Write

R/W

After reset

0

0

0

DMA transfer mode

Transfer data size

000: Destination INC (I/O → MEM)

00: 1 byte

001: Destination DEC (I/O → MEM)

01: 2 bytes

010: Source INC (MEM → I/O)

10: 4 bytes

011: Source DEC (MEM → I/O)

11: Reserved

100: Source/destination INC

Function

(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

Transfer mode
[7: 0]
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5

HDMAM0
(090CH)
HDMAM1
(091CH)
HDMAM2
(092CH)
HDMAM3
(093CH)
HDMAM4
(094CH)
HDMAM5
(095CH)

Note 1: Read-modify-write instructions can be used on all these registers.
Note 2: INC: Post-increment
Dec: Post-decrement
I/O: Fixed memory address
MEM: Memory address to be incremented or decremented

Figure 3.6.6 HDMAMn Register

92CZ26A-94

(Note 2)

TMP92CZ26A

(6) HDMAE (DMA Operation Enable Register)
The HDMAE register is used to enable or disable the DMAC operation.
Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to “0”.

7
HDMAE
(097EH)

HDMAE Register
5
4

6

bit Symbol

3

2

1

0

DMAE5

DMAE4

DMAE3

DMAE2

DMAE1

DMAE0

0

0

0

0

0

Read/Write

R/W

After reset

0

DMA channel operation
Function

0: Disable
1: Enable

Note: Read-modify-write instructions can be used on this register.

Figure 3.6.7 HDMAE Register
(7) HDMATR (DMA Maximum Bus Occupancy Time Setting Register)
The HDMATR register is used to set the maximum duration of time the DMAC can
occupy the bus. The TMP92CZ26A does not have priority levels for bus arbitration.
Therefore, once the DMAC owns the bus, other masters (such as the LCDC) must wait until
the DMAC completes its transfer operation and releases the bus. This could lead to
problems in the system. For example, if the LCDC cannot own the bus as required, the LCD
display function may not work properly. To avoid such a situation, the DMAC limits the
duration of its bus occupancy by using this timer register. When the DMAC occupies the
bus for the duration of time set in this register, it releases the bus even if the specified DMA
operation has not been completed yet. After waiting for 16 states, the DMAC asserts a bus
request again to execute the rest of the DMA operation.
The DMAC counts the bus occupancy time regardless of which channel is occupying the
bus. To set the maximum bus occupancy time, ensure that the HDMAE register is set to
“00H” and set HDMATR to “1” and  to the desired value.
Note: In case of using S/W start with HDMA, transmission start is to set to "1" DMAR
register. However DMAR register can't be used to confirm flag of transmission end. DMAR
register reset to "0" when HDMA release bus occupation once with HDMATR function.
HDMATR Register
HDMATR
(097FH)
bit Symbol

7

6

5

4

DMATE

DMATR6

DMATR5

DMATR4

Read/Write
After reset

Function

3

2

1

0

DMATR3

DMATR2

DMATR1

DMATR0

0

0

0

R/W
0

0

0

0

0

Timer

Maximum bus occupancy time setting

operation
0: Disable

The value to be set in  should be obtained by
“maximum bus occupancy time / (256/fSYS)”.

1: Enable

“00H” cannot be set.

Note: Read-modify-write instructions can be used on this register.

Figure 3.6.8 HDMATR Register

92CZ26A-95

TMP92CZ26A

3.6.3

DMAC Operation Description

(1) Overall flowchart
Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is
requested.

Interrupt (DMA) request

No

Interrupt specified by
DMA start vector?

To general-purpose interrupt or
micro DMA processing flow

Yes
Interrupt request F/F clear
& bus REQ assert

No

Bus ACK?

Yes
Internal timer start

HDMASn read
HDMADn write

Timer match?

Yes

No
No

HDMACAn -1=0?

Yes
Bus REQ deassert

Yes
HDMACBn -1=0?

No

INTDMAn assert

END

Figure 3.6.9 Overall Flowchart

92CZ26A-96

TMP92CZ26A

(2) Bus arbitration
The TMP92CZ26A includes three controllers (DMA controller, LCD controller, SDRAM
controller) that function as bus masters apart from the CPU. These controllers operate
independently and assert a bus request as required. The controller that receives a bus
acknowledgement acts as the bus master. No priorities are assigned to these three
controllers, and bus requests are processed in the order in which they are asserted. Once
one of the controllers owns the bus, bus requests from other controllers are put on hold until
the bus is released again. While one of the controllers is occupying the bus, CPU processing
including non-maskable interrupt requests is also put on hold.
(3) Transfer source and destination memory setting
Either internal or external memory can be set as the source and destination memory or
I/O to be accessed by the DMAC. Even when the MMU is used in external memory, the
addresses to be accessed by the DMAC should be specified using logical addresses. The
DMAC accesses the specified source and destination addresses according to the bus width
and number of waits set in the memory controller and the bank settings made in the MMU.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
Table 3.6.1 Difference point of address setting between HDMA and micro DMA
Data Length

HDMA

1byte

No restriction

Source address

Destination address

Micro DMA

2byte

Even address

4byte

Address in multiples of 4

1byte

No restriction

2byte

Even address

4byte

Address in multiples of 4

No restriction

(4) Operation timing
The following diagram shows an example of operation timing for transferring 2 bytes
from 16-bit memory connected with the CS2 area to 8-bit memory connected with the CS1
area.
CPU execution cycle

DMAC/read

CPU execution
cycle

DMAC/write

SDCLK
int_xx
busrq
busak
CS2
CS1

A23 ∼ A0
RD

Undefined after interrupt
request is asserted until
DMAC read cycle is
started

800000H

400000H

400001H

SRWR
SRLUB
SRLLB

D15 ∼ D0

1234H

92CZ26A-97

ZZ34H

ZZ12H

TMP92CZ26A

3.6.4 Setting Example
This section explains how to set the DMAC using an example.
(1) Transferring music data from internal RAM to I2S by DMA transfer
The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be
transferred to FIFO-RAM via I2S. Each time an INTI2S request is asserted, 64 bytes (4
bytes x 16 times) shall be transferred to FIFO-RAM using DMAC channel 0. Since INTI2S
is an FIFO empty interrupt, the first data must be set in advance. Therefore, only the first
64 bytes shall be transferred by DMA soft start. After 32 Kbytes have been transferred, the
INTDMA0 interrupt routine shall be activated to prepare for the next processing.
(a) Main routine
No
1

Instruction
ldl

Comments

(hdmas0),2000H

; Source address = 2000H

2

ldl

(hdmad0),i2sbuf

; Destination address = i2sbuf

3

ldw

(hdmaca0),16

; Counter A = 16

4

ldw

(hdmacb0),512

; Counter B = 512 (32768/64)

5

ldb

(hdmam0),0AH

; Transfer mode = source INC, 4 bytes

6

set

0,(hdmae)

; Enable DMA channel 0.

7

ld

(dmar),01H

; Transfer the first 64 bytes by DMA soft start.

8

nop

;

9

ld

(dma0v),i2s_vector

10

ld

(intedma01),xxH

; INTI2S = DMA0
; INTDMA level = x

11

ldw

(i2sctl0),xxxxH

; Set operation mode for I2S.

12

ldw

(i2sctl1),xxxxH

; Start I2S transmission.

13

ei

xx

; Enable CPU interrupts.

(b) INTDMA0 interrupt routine
No

Instruction

1

res

2

:

3

:

4

:

5

:

0,(hdmae)

Comments
; Disable DMA channel 0.

6
7
8
9
10
11

reti

;

92CZ26A-98

TMP92CZ26A

3.6.5 Note
1. In case of using S/W start with HDMA, transmission start is to set to "1" DMAR
register. However DMAR register can't be used to confirm flag of transmission end.
DMAR register reset to "0" when HDMA release bus occupation once with HDMATR
function. We recommend to use HDMACBn register (counter value) to confirm flag of
transmission end.

92CZ26A-99

TMP92CZ26A

3.6.6 Considerations for Using More Than One Bus Master
In the TMP92CZ26A, the LCD controller, SDRAM controller, and DMA controller may act as
the bus master apart from the CPU. Therefore, care must be exercised to enable each of these
functions to operate smoothly.
To facilitate explanation of DMA operation performed by each bus master, the DMA transfer
operation performed by the DMA controller is defined as “HDMA”, the display RAM read
operation performed by the LCD controller as “LDMA”, and the SDRAM auto refresh operation
performed by the SDRAM controller as “ARDMA”.
The following explains various cases where two or more bus masters may operate at the
same time.
(1) CPU + HDMA
The DMA controller performs DMA transfer (HDMA) after issuing a bus request to the
CPU and getting a bus acknowledgement. The DMA controller may be active while the CPU
is in HALT mode (IDLE2 mode only), in which case HDMA does not interfere with the CPU
operation. However, if HDMA is started while the CPU is active, the CPU cannot execute
instructions while HDMA is being performed.
Before activating the DMA controller, therefore, it is necessary to estimate the CPU stop
time (defined as “tSTOP (HDMA)”) based on the transfer time, transfer start interval, and
number of channels to be used.
CPU bus stop rate = tSTOP (HDMA)[s] / HDMA start interval [s]
HDMA start interval [s] = HDMA start interrupt period [s]
Note: The HDMA start interval depends on the period of the HDMA start interrupt source. However, it is also
possible to start HDMA by software.

tSTOP (HDMA) [s] = (Source read time + Destination write time) × Transfer count + α
state/byte
Memory Type
Read / Write
Read
Write

Internal RAM

1/4

(Note 1)

External SDRAM

External SRAM

External SRAM

16-bit bus

16-bit bus

8-bit bus

Burst 1 / 2
1 word 6 / 2

1/4

Burst 1 / 2
1 word 3 / 2

(Note 2)
(Note 2)

2/2

(Note 3)

2/1

(Note 3)

(Note 2)
(Note 2)

2/2

(Note 3)

2/1

(Note 3)

Note 1: 2-1-1-1 access. Each consecutive address can be accessed in 1 state.
Note 2: The transfer speed varies depending on the combination of source and destination.
a) When the source or destination is internal RAM or internal I/O (SFR), burst access (6-1-1-1 access)
is possible. Only consecutive addresses on the same page can be accessed in 1 state. Additional 4
states are needed at the end of each burst access.
b) When the source or destination is other than internal RAM or internal I/O, 1-word access is used.
Note 3: In the case of 0 waits
state/byte
I/O Type
Read / Write

I2S

NANDF

USB

SPI

Read

−

2/2

2/2

2/4

Write

2/4

2/2

2/2

2/4

92CZ26A-100

TMP92CZ26A
Sample 1) Calculation example for CPU + HDMA

Conditions:

CPU operation speed (fSYS)

: 60 MHz

I2S sampling frequency

: 48 KHz (60 MHz/25/50 = 48 KHz)

I2S data transfer bit length

: 16 bits

DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S

Calculation example:

DMAC source data read time:
Internal RAM data read time = 1 state/4 bytes (However, the first 1 byte requires 2 states.)
DMAC destination write time:
I2S register write time = 2 states/4 bytes
Transfer count
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as follows:
5 Kbytes/4 bytes = 1280 [times]
Since I2S generates an interrupt for every 64 bytes, the DMAC’s counter A is set to 16 (64 bytes/4 bytes = 16
times) and counter B is set to 80.
* Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state)
occurs 80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead
time of 2 states is also needed for each interrupt request, requiring additional 160 states in total.

tSTOP (HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / fSYS [S] = 68 [μS]
HDMA start interval [s] = 1 / I2S sampling frequency [Hz] × (64 / 16 )
= 83.33 [mS]

CPU bus stop rate = tSTOP (HDMA) [s] / HDMA start interval [s]
= 68 [μS] / 83.33 [mS] = 0.08 [%]

92CZ26A-101

TMP92CZ26A

(2) CPU + LDMA
The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the
CPU and getting a bus acknowledgement.
If LDMA is not performed properly, the LCD display function cannot work properly.
Therefore, LDMA must have higher priority than the CPU. While LDMA is being
performed, the CPU cannot execute instructions.
To display data on the LCD using the LCD controller, it is necessary to estimate to what
degree LDMA would interfere with the CPU operation based on the display RAM type,
display RAM bus width, LCDD type, display pixel count, and display quality.
The time the CPU stops operation while the LCD controller transfers data for one line is
defined as “tSTOP (LDMA)”, which is calculated as shown below for each display mode.
tSTOP (LDMA) = (SegNum × K / 8) × tLRD
16-bit external SRAM

: tLRD = (2 + wait count) / fSYS [Hz] / 2

Internal RAM

: tLRD = 1 / fSYS [Hz] / 4

16-bit external SDRAM

:tLRD= 1 / fSYS [Hz] / 2

SegNum

: Number of segments to be displayed

K

: Number of bits needed for displaying 1 pixel
Monochrome

K=1

4 gray scales

K=2

16 gray scales

K=4

256 colors

K=8

4096 colors

K = 12

65536 colors

K = 16

262144/16777216 colors

K = 24

Note 1: When SDRAM is used, the overhead time is added as shown below.
tSTOP [s] = (SegNum × K/8) × tLRD + ((1/fSYS) × 8)
Note 2: When internal RAM is used, the overhead time is added as shown below.
tSTOP [s] = ( SegNum × K/8 )× tLRD + (1/fSYS)

The CPU bus stop rate indicates what proportion of the 1-line data update time
tLP is taken up by tSTOP(LDMA) and is calculated as follows:
CPU bus stop rate = tSTOP (LDMA) [s] / LHSYNC [period: s]

92CZ26A-102

TMP92CZ26A

Sample2) Calculation examples for CPU + LDMA

Conditions 1:

CPU operation speed (fSYS)

: 60 MHz

Display RAM

: Internal RAM

Display size

: QVGA (320seg × 240com)

Display quality

: 65536 colors (TFT)

Refresh rate

: 70 Hz (including 20 clocks of dummy cycles)

Calculation example 1:

tSTOP (LDMA)

= ((SegNum × K / 8) × tLRD) + (1 / fSYS [Hz])
= ((320 × 16 / 8) × 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz])
= ((640) × 16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]

LHSYNC [period: s] = 1/70 [Hz] /(COM+20=260) = 54.95 [μs]

CPU bus stop rate

= tSTOP (LCD)[s] / LHSYNC [period: s]
= 2.68 [μs] / 54.95 [μs] = 4.88 [%]

Conditions 2:

CPU operation speed (fSYS)

: 10 MHz

Display RAM

: 16-bit external SRAM (0 waits)

Display size

: QVGA (240seg × 320com)

Display quality

: 4096 colors (STN)

Refresh rate

: 100 Hz (0 dummy cycles)

Calculation example 2:

tSTOP (LDMA)

= (SegNum × K / 8) × tLRD
= (240 × 12 / 8) × ( 2 + wait count) / fSYS [Hz] / 2
= (360) × 200 [ns] / 2
= 36 [μs]

LHSYNC [period: s]

= 1/100 [Hz] / (COM = 240) = 41.67 [μs]

CPU bus stop rate

= tSTOP (LCD)[s] / LHSYNC [period: s]
= 36 [μs] / 41.67 [μs] = 86.40 [%]

92CZ26A-103

TMP92CZ26A

(3) CPU + LDMA + ARDMA
The SDRAM controller owns the bus not only when SDRAM is used as the LCD display
RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller
occupies the bus (ARDMA) while it refreshes SDRAM data by the auto refresh function.
No special consideration is needed for the ARDMA time normally as it ends within
several clocks per specified number of states. However, if the LCD controller occupies the
bus continuously, ARDMA cannot be executed at normal intervals and refresh data is
stored in a counter specifically provided in the SDRAM controller. In this case, ARDMA is
executed successively after the LCD controller releases the bus.
The priorities among the three bus masters should be set in the order of LCDC >
SDRAMC > CPU. The time the CPU stops operation while the LCD controller and SDRAM
controller are transferring data for one line is defined as “tSTOP (LDMA･ARDMA)”, which is
calculated as follows:
tSTOP (LDMA･ARDMA) = tSTOP (LDMA)[s] − (tSTOP (LDMA)[s] / AR interval [s] × 2 / fSYS [Hz])
CPU bus stop rate = tSTOP (LDMA･ARDMA)[s] / LHSYNC [period: s]
Auto Refresh Intervals
SRS2

SRS1

SRS0

Auto Refresh
Interval
(states)

0

0

0

47

0

0

1

78

13.0

7.8

3.9

1.95

1.30

0.98

0

1

0

156

26.0

15.6

7.8

3.90

2.60

1.95

0

1

1

312

52.0

31.2

15.6

7.80

5.20

3.90

1

0

0

468

78.0

46.8

23.4

11.70

7.80

5.85

1

0

1

624

104.0

62.4

31.2

15.60

10.40

7.80

1

1

0

936

156.0

93.6

46.8

23.40

15.60

11.70

1

1

1

1248

208.0

124.8

62.4

31.20

20.80

15.60

SDRCR

Frequency (System Clock)
6 MHz

10MHz

20MHz

40MHz

60MHz

80MHz

7.8

4.7

2.4

1.18

0.78

0.59

Unit: [μs]

92CZ26A-104

TMP92CZ26A
Sample3) Calculation example for CPU + LDMA + ARDMA

Conditions:

CPU operating speed(fSYS)

: 60 MHz

Display RAM

: 16-bit external SDRAM

Display size

: QVGA (320seg × 240com)

Display quality

: 65536 colors (TFT)

Refresh rate

: 70 Hz (including 20 clocks of dummy cycles)

SDRAM auto refresh

: Every 936 states (15.6 μs)

Calculation example:

tSTOP (LDMA)

=((SegNum × K / 8) × tLRD) + (8 / fSYS [Hz])
= ((320 ×16 / 8) × 1 / fSYS [Hz] / 2) + (8 / fSYS [Hz])
= ((640) × 16.67 [ns] / 2) + 133.33 [ns]
= 5.47 [μs]

LHSYNC [period:s]

= 1/70 [Hz] / (COM + 20 = 260) = 54.95 [μs]

Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
tSTOP (ARDMA)

= 2 / fSYS [Hz] = 33.33 [ns]

CPU bus stop rate

= tSTOP(LDMA･ARDMA) [s] / LHSYNC [period:s]
= (5.47 [μs] + 33.33 [ns]) / 54.95 [μs] = 10.01 [%]

92CZ26A-105

TMP92CZ26A

(4) CPU + LDMA+ ARDMA + HDMA
This is a case in which all the bus masters are active at the same time.
Since the LCD display function cannot work properly if the LCD controller cannot
perform LDMA properly, the priorities among the four bus masters should be set in the
order of LDMA > ARDMA > HDMA > CPU.
Before calculating the CPU bus stop rate, the conditions for proper LCD display shall be
considered first.
Setup time 1

LHSYNC
LCP0
LD-bus
LDMA1

Setup time 2

HDMA
(Worst case)
LDMA2

The above diagram shows the LHSYNC signal, LCP0 signal, and LD-bus signal for
transferring data from the LCD controller to the LCD driver, and the transfer operation
(LDMA1) for reading data from the display RAM into the FIFO buffer in the LCD
controller.
LDMA is started immediately after data has been transferred to the LCD driver. If
HDMA is started immediately before LDMA1 is started, LDMA must wait until HDMA
has finished before it can be started (LDMA2). LDMA2 must finish operation before the
LCD driver output for the next stage is started.
LHSYNC [period: s] − LCD driver data transfer time [s] − tSTOP(LCD) [s]
= HDMA continuous time [s] + CPU operation time [s]
In the case of STN display
LCD driver data transfer time [s] = SegNum/8×(1/fSYS) × (LD bus transfer speed)
In the case of TFT display
LCD driver data transfer time [s] = SegNum×(1/ fSYS) × (LD bus transfer speed)

92CZ26A-106

TMP92CZ26A
Sample 4) Calculation example for CPU + LDMA+ ARDMA + HDMA

Conditions:

CPU operation speed (fSYS)

: 60 MHz

Display RAM

: QVGA (320seg × 240com)

Display quality

: 65536 colors (TFT)

Refresh rate

: 70 Hz (including 20 clocks of dummy cycles)

SDRAM Auto Refresh

: Every 936 states (15.6 μs)

SDRAM

: 16-bit width

HDMA

: Transfers 5 Kbytes from internal RAM to I2S

Calculation example:

tSTOP (LDMA)

=((SegNum × K / 8) × tLRD) + (1 / fSYS [Hz])
= ((320 ×16 / 8) × 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz])
= ((640) ×16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]

LHSYNC [period: s]

= 1/70 [Hz] /(COM+20 = 260) = 54.95 [μs]

tSTOP (HDMA)

= (((1 + 2) × 16) × 80) + 80 + 160) / fSYS [s] = 68 [μs]

LCD driver data transfer time [s]
= SegNum × (1/fSYS) × (LD bus transfer speed)
= 320 × (1/60 MHz) × 16 = 85 [μs]

Since LHSYNC [period: s] < LCD driver data transfer time [s], this setting is not possible.
When the transfer speed is changed to x4, the LCD driver data transfer time is calculated as follows:
(The transfer speed should be adjusted according to the required specifications.)

LCD driver data transfer time [s]
= SegNum × (1/fSYS) × (LD bus transfer speed)
= 320 × (1 / 60MHz) × 4 = 21.3 [μs]

LHSYNC [period: s] − LCD driver data transfer time [s] − tSTOP(LDMA)
= 54.95 [μs] − 21.3 [μs] − 2.68 [μs] = 30.94 [μs]

To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time) must
be set to 30.92 [μS] or less. Although transferring all 5 Kbytes from the internal RAM to I2S requires tSTOP (HDMA) = 68
[μs], the maximum HDMA time should be limited by using the HDMATR register.

92CZ26A-107

TMP92CZ26A

HDMATR Register
HDMATR
(097FH)

bit Symbol

7

6

5

4

DMATE

DMATR6

DMATR5

DMATR4

Read/Write
After reset

2

1

0

DMATR3

DMATR2

DMATR1

DMATR0

0

0

0

R/W
0

0

0

0

Timer
Function

3

0

Maximum bus occupancy time setting

operation

The value to be set in  should be obtained by

0: Disable

“maximum bus occupancy time / (256/fSYS)”.

1: Enable

“00H” cannot be set.

Note: Read-modify-write instructions can be used on this register.

By writing “87H” to the HDMATR register, the maximum HDMA time is set to 29.9 [μs]
(256 × 7 × (1 / fSYS)). Since HDMA start interval [period:s] = 83.33 [ms] is longer than
LHSYNC [period:s] = 54.95 [μs], it is assumed that HDMA transfer occurs once during
LHSYNC [period:s].
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
tSTOP (ARDMA)

= 2 / fSYS [Hz] = 33.33 [ns]

The time LDMA, ARDMA, and HDMA all occupy the bus is defined as:
tSTOP(LDMA･ARDMA･HDMA)
Based on the above, the CPU bus stop rate is calculated as follows:
CPU bus stop rate

= tSTOP(LDMA･ARDMA･HDMA) [s] / LHSYNC [period:s]

= (5.47 [μs] + 33.33 [ns]+29.9 [μs]) / 54.95 [μs] = 64.42 [%]

Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
forcefully terminated at 29.9 [μs].

92CZ26A-108

TMP92CZ26A
Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA
at same time (Worst case)

Conditions:

CPU operation speed (fSYS)

: 80MHz

Display RAM

: Internal RAM

Display size

: QVGA (320seg × 240com)

Display quality

: 16777216 color (TFT)

Refresh rate

: 70Hz

HDMA

: Transfers 225 Kbytes from internal RAM to SDRAM

Calculation example:
= ((SegNum × K/8) × tLRD) + (1/fSYS [Hz])

tSTOP (LCD)

= ((320 × 24/8) × 1/fSYS [Hz]/4) + (1/fSYS [Hz])
= ((960) × 12.5 [nS]/4) + 12.5 [nS]
= 3.0125 [μS]

LHSYNC [period: S]

= 1/70 [Hz]/ (COM+20) = 54.9 [μS]

tSTOP (HDMA)

= (((2 + 1) × 4) × 57600) + 28800 + 14400)/fSYS [S] = 9180 [μS]

LCD driver data transfer time [S]
= SegNum × (1/fsys) × (LD bus transfer speed)
= 320 × (1/80MHz) × 8 = 32 [μS]

LHSYNC [cycle S] - LCD driver data transfer time [S] − tSTOP (LCD)
= 54.9 [μS] − 32 [μS] − 3.0125 [μS] = 19.8875 [μS]

To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time)
must be set to 19.8875 [μS] or less. Although transferring all 225 Kbytes from the internal RAM to SDRAM requires tSTOP
(HDMA) = 9180 [μs], the maximum HDMA time should be limited by using the HDMATR register.
HDMATR register

HDMATR
(097FH)

Bit Symbol

7

6

5

4

3

2

1

0

DMATE

DMATR6

DMATR5

DMATR4

DMATR3

DMATR2

DMATR1

DMATR0

0

0

0

Read/Write
After reset

Function

R/W
0
Timer
operation
0: Disable
1:Enable

0

0

0

0

Maximum bus occupancy time setting
The value to be set in  should be obtained by
“Maximum bus occupancy time / (256/fSYS)”.
“00H” cannot be set.

Note: Read-modify-write instructions can be used on this register.

By writing “86H” to the HDMATR register, the maximum HDMA time is set to 19.2[μs]
(256 × 6 × (1 / fSYS)).
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
forcefully terminated at 19.2 [μs].

92CZ26A-109

TMP92CZ26A

3.7 Function of ports
TMP92CZ26A has I/O port pins that are shown in Table 3.7.1 in addition to functioning as
general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table
3.7.2 lists I/O registers and their specifications.
Table 3.7.1 Port Functions (1/3) (R: PD= with programmable pull-down resistor, U= with pull-up resistor)
Port Name

Pin Name

Number of
Pins

I/O

R

I/O Setting

Pin Name for built-in
function

Port 1

P10 to P17

8

I/O

−

bit

Port 4

P40 to P47

8

Output

−

bit

A0 to A7

Port 5

P50 to P57

8

Output

−

bit

A8 to A15

Port 6

P60 to P67

8

I/O

−

bit

A16 to A23

Port 7

P70

1

Output

−

(Fixed)

P71

1

I/O

−

bit

P72

1

I/O

−

bit

WRLL , NDRE
WRLU , NDWE

P73

1

I/O

−

bit

EA24

P74

1

I/O

−

bit

EA25

P75

1

I/O

−

bit

R/ W , NDR/ B

P76

1

I/O

−

bit

P80

1

Output

−

(Fixed)

CS0

P81

1

Output

−

(Fixed)

CS1, SDCS

P82

1

Output

−

(Fixed)

CS2 , CSZA

P83

1

Output

−

(Fixed)

CS3 , CSXA

P84

1

Output

−

(Fixed)

CSZB

P85

1

Output

−

(Fixed)

CSZC

P86

1

Output

−

(Fixed)

CSZD , ND0CE

P87

1

Output

−

(Fixed)

CSXB , ND1CE

P90

1

I/O

−

bit

TXD0

P91

1

I/O

−

bit

P92

1

I/O

−

bit

RXD0
SCLK0, CTS0

P96

1

Input

PD

(Fixed)

INT4, PX
PY

Port 8

Port 9

D8 to D15

RD

WAIT

P97

1

Input

−

(Fixed)

Port A

PA0 to PA7

8

Input

U

(Fixed)

Port C

PC0

1

I/O

−

bit

INT0

PC1

1

I/O

−

bit

INT1, TA0IN

PC2

1

I/O

−

bit

INT2

PC3

1

I/O

−

bit

INT3, TA2IN

PC4

1

I/O

−

bit

EA26

PC5

1

I/O

−

bit

EA27

PC6

1

I/O

−

bit

EA28

PC7

1

I/O

−

bit

KO8

PF0

1

I/O

−

bit

I2S0CKO

PF1

1

I/O

−

bit

I2S0DO

PF2

1

I/O

−

bit

I2S0WS

PF3

1

I/O

−

bit

I2S1CKO

PF4

1

I/O

−

bit

I2S1DO

PF5

1

I/O

−

bit

I2S1WS

Port F

Port G

KI0 to KI7

PF7

1

Output

−

(Fixed)

SDCLK

PG0 to PG1

2

Input

−

(Fixed)

AN0 to AN1

PG2

1

Input

−

(Fixed)

AN2, MX

PG3

1

Input

−

(Fixed)

AN3, ADTRG , MY

PG4 to PG5

2

Input

−

(Fixed)

AN4 to AN5

92CZ26A-110

TMP92CZ26A

Table 3.7.1 Port Functions (2/3)
Port Name

Pin Name

Number of
Pins

I/O

R

I/O Setting

Pin Name for built-in
function

PJ0

1

Output

−

(Fixed)

PJ1

1

Output

−

(Fixed)

PJ2

1

Output

−

(Fixed)

SDWE , SRWR

PJ3

1

Output

−

(Fixed)

SDLLDQM

PJ4

1

Output

−

(Fixed)

SDLUDQM

PJ5

1

I/O

−

bit

NDALE

PJ6

1

I/O

−

bit

NDCLE

PJ7

1

Output

−

(Fixed)

SDCKE

PK0

1

Output

−

(Fixed)

LCP0

PK1

1

Output

−

(Fixed)

LLOAD

PK2

1

Output

−

(Fixed)

LFR

PK3

1

Output

−

(Fixed)

LVSYNC

PK4

1

Output

−

(Fixed)

LHSYNC

PK5

1

Output

−

(Fixed)

LGOE0

PK6

1

Output

−

(Fixed)

LGOE1

PK7

1

Output

−

(Fixed)

LGOE2

Port L

PL0 to PL7

8

Output

−

(Fixed)

LD0 to LD7

Port M

PM1

1

Output

−

(Fixed)

MLDALM, TA1OUT

PM2

1

Output

−

(Fixed)

ALARM , MLDALM

PM7

1

Output

−

(Fixed)

PWE

Port N

PN0 to PN7

8

I/O

−

bit

KO0 to KO7

Port P

PP1

1

I/O

−

bit

TA3OUT

PP2

1

I/O

−

bit

TA5OUT

PP3

1

I/O

−

bit

INT5, TA7OUT

PP4

1

I/O

−

bit

INT6, TB0IN0
INT7, TB1IN0

Port J

Port K

SDRAS , SRLLB
SDCAS , SRLUB

PP5

1

I/O

−

bit

PP6

1

Output

−

(Fixed)

PP7

1

Output

−

(Fixed)

PR0

1

I/O

−

bit

SPDI

PR1

1

I/O

−

bit

SPDO

PR2

1

I/O

−

bit

SPCS

PR3

1

I/O

−

bit

SPCLK

Port T

PT0 to PT7

8

I/O

−

bit

LD8 to LD15

Port U

PU0 to PU4

6

I/O

−

bit

LD16 to LD20 , LD22

Port R

,PU6

Port V

TB0OUT0
TB1OUT0

PU5

1

I/O

−

bit

LD21

PU7

1

I/O

−

bit

LD23, EO_TRGOUT

PV0

1

I/O

−

bit

SCLK0

PV1

1

I/O

−

bit

−

PV2

1

I/O

−

bit

−

PV3

1

Output

−

(Fixed)

−

PV4

1

Output

−

(Fixed)

PV6

1

I/O

−

bit

SDA

−

PV7

1

I/O

−

bit

SCL

Port W

PW0 to PW7

8

I/O

−

bit

−

Port X

PX4

1

Output

−

bit

CLKOUT, LDIV

PX5

1

I/O

−

bit

X1USB

PX7

1

I/O

−

bit

−

92CZ26A-111

TMP92CZ26A

Table 3.7.1 Port Functions (3/3)
Port Name
Port Z

Pin Name

Number of
Pins

I/O

R

I/O Setting

Pin Name for built-in
function

PZ0

1

I/O

−

bit

PZ1

1

I/O

−

bit

EI_SYNCLK

PZ2

1

I/O

−

bit

EI_PODREQ

PZ3

1

I/O

−

bit

EI_REFCLK

PZ4

1

I/O

−

bit

EI_TRGIN

PZ5

1

I/O

−

bit

EI_COMRESET

PZ6

1

I/O

−

bit

EO_MCUDATA

PZ7

1

I/O

−

bit

EO_MCUREQ

92CZ26A-112

EI_PODDATA

TMP92CZ26A

Table 3.7.2 I/O Port and Specifications (1/4)
Port
Port 1

Port 4
Port 5
Port 6

Port 7

Port 8

Pin name
P10 toP17

P40 to P47
P50 to P57
P60 to P67

Specification

X: Don’t care
I/O register
Pn

PnCR

Input port

X

0

Output port

X

1

PnFC
0

D8 to D15 bus

X

X

Output port

X

None

0

A0 to A7 Output

X

None

1

PnFC2
None

1

Output port

X

None

0

A8 to A15 Output

X

None

1

Input port

X

0

Output port

X

1

A16 to A23 Output

X

X

0

None
None

None

1

P70 to P76

Output port

X

1

0

P71 to P76

Input port

X

0

0

P70

RD Output

X

None

1

P71

WRLL Output

1
0

1

1

P72

NDRE Output
WRLU Output

1

NDWE Output

0

1

1

P73

EA24 Output

X

1

1

P74

EA25 Output

X

1

1

P75

R/ W Output

X

1

1

NDR/B Input

X

0

1

P76

WAIT Input

X

0

1

P80 to P87

Output port
CS0 Output

X

0

0

P80

X

1

None

P81

CS1 Output

X

1

0

SDCS Output

X

X

1

P82

P83

CS2 Output

X

1

0

CSZA Output

X

0

1

SDCS Output

X

1

1

CS3 Output

X

CSXA Output

X

None

1

0

X

1

P84

CSZB Output

X

1

P85

CSZC Output

X

1

P86
P87

None

None

CSZD Output

X

1

0

ND0CE Output

X

1

1

CSXB Output

X

1

0

ND1CE Output

X

1

1

92CZ26A-113

TMP92CZ26A

X: Don’t care

Table3.7.2 I I/O Port and Specifications (2/4)
Port
Port 9

Port A
Port C

Port F

Pin name

Specification

I/O register
Pn

PnCR

PnFC

PnFC2

P90, P92

Input port

X

0

0

None

P91

Input port, RXD0 Input

X

0

None

None

P96

Input port

X

None

0

None

P97

Input port

X

None

None

None

P90 to P92

Output port

X

1

0

0

P90

TXD0 Output

X

1

1

0

TXD0 Output (Open-drain)

X

1

1

1

P92

SCLK0 Output
SCLK0, CTS0 Input

X

1

1

0

X

0

0

0

P96

INT4 Input

X

None

1

None

PA0 to PA7

Input port

X

KI0 to KI7 Input

X

Input port

X

0

Output port

X

1

0

PC0

INT0 Input

X

0

1

PC1

INT1 Input

X

0

1

TA0IN Input

X

1

1

PC2

INT2 Input

X

0

1

PC3

INT3 Input

X

0

1

TA2IN Input

X

1

1

PC4

EA26 Output

X

0

1

PC5

EA27 Output

X

0

1

PC6

EA28 Output

X

0

1

PC7

KO8 Output (Open-drain)

X

1

1

PF0 to PF5

Input port

X

0

0

PC0 to PC7

None

0
1
0

PF0 to PF5

Output port

X

1

0

PF7

Output port

X

None

0

PF0

I2S0CKO Output

X

X

1

PF1

I2S0DO Output

X

X

1

PF2

I2S0WS Output

X

X

1

PF3

I2S1CKO Output

1

X

1

PF4

I2S1DO Output

X

X

1

PF5

I2S1WS Output

X

X

1

PF7

SDCLK Output

X

None

1

92CZ26A-114

None

None

None

TMP92CZ26A

Table3.7.2 I/O Port and Specifications (3/4)
Port
Port G

Port J

Pin name
PG0 to PG5

Input port

PG3

AN0 to AN5 Input
ADTRG Input

PG2

MX Output

Note:

PG3

MY Output

Note:

Port N

Port P

PnFC

X

None

1

X

0

0

X

1

0

Output port

X

None

0

SDRAS , SRLLB Output
SDCAS , SRLUB Output

X

PJ1
PJ2

SDWE , SRWR Output

X

PJ3

SDLLDQM Output

X

1

PJ4

SDLUDQM Output

X

1

PJ5

NDALE Output

X

PJ6

NDCLE Output

X

PJ7

SDCKE Output

X

PK0 to PK7

Output port

X

PK0

LCP0 output

X

1

PK1

LLOAD output

X

1

PK2

LFR output

X

PK3

LVSYNC output

X

PK4

LHSYNC output

X

1

PK5

LGOE0 output

X

1

PK6

LGOE1 output

X

1

PK7

LGOE2 output

X

1

PL0 to PL7

Output port

X

PL0 to PL7

LD0 to LD7 Output

X

PM1 to PM2

Output port

X

0

PM1

TA1OUTOutput

0

1

MLDALM Output

1

PM2

MLDALM Output
ALARM Output

0

1

1

1

PM7

PWE Output

X

PN0 to PN7

Input port

X

PJ4,

1

X

Output port (CMOS Output)

X

KO Output (Open-drain Output)

X

Input port

X

PP1 to PP5

Output port

PP6 to PP7

Output port

PP1

PP1 to PP5

1
None

1

1

1

None

1

1
None

None

None

1

0
1

1

1

None

0

None

1
1

0

X

None

0

TA3OUT output

X

1

1

PP2

TA5OUT output

X

1

1

PP3

INT5 input

X

0

TA7OUT output

X

1

INT6 input

X

0

TB0IN0 input

X

1

INT7 input

X

0

TB1IN0 input

X

1

PP6

TB0OUT0 output

X

PP7

TB1OUT1 output

X

92CZ26A-115

None

0

X

Note: Case of using touch screen

None

1
0

0

PP5

None

0

0

PP4

None

0

Input port

to

PnFC2

0

Output port

PJ0

Port M

PnCR

PJ5 to PJ6
PJ7

Port L

I/O register
Pn

PJ5 to PJ6
PJ0

Port K

Specification

X: Don’t care

None

1
1
1
1
1

None

TMP92CZ26A

Table 3.7.2 I/O Port and Specifications (4/4)
Port
Port R

Port T

Port U

Port V

Pin name

Port X

Port Z

I/O register
Pn

PnCR

PnFC

PR0 to PR3

Input port

X

0

0

PR0 to PR3

Output port

X

1

0

PR0

SPDI Input

X

0

1

PR1

SPDO Output

X

1

1

PR2

SPCS Output

X

1

1

PR3

SPCLK Output

X

1

1

PT0 to PT7

Input port

X

0

0

PT0 toPT7

Output port

X

1

0

PT0 to PT7

LD8 to LD15 Output

X

1

1

PU0 to PU7

Input port

X

0

0

PU0 to PU7

Output port

X

1

0

PU0 to PU7

X

1

1

PU7

LD16 to LD23 Output
EO_TRGOUT ( DBGE = “0”) Note:

X

X

X

PV0 to PV2

Input port

X

0

0

PV0 to PV4

Output port

X

1

0

PnFC2

None

None

None

None

PV6 to PV7

Input port

X

0

0

PV6 to PV7

Output port

X

1

0

PV6 to PV7

Output port (Open-drain)

X

1

0

1

PV0

SCLK0 Output

X

1

1

None

PV6

SDA I/O

X

1

1

0

SDA I/O (Open-drain)

X

1

1

1

SCL I/O

X

1

1

0

SCL I/O (Open-drain)

X

1

1

1

PW0 to PW7

Input port

X

0

0

PW0 to PW7

Output port

X

1

0

PX5, PX7

Input port

X

0

0

PX4

Output port

X

None

0

PX5, PX7

Output port

X

1

0

PX4

CLKOUT Output

0

LDIV Output

1

PX5

X1USB Input

X

0

1

PZ0 to PZ7

Input port

X

0

0

X

1

0

PZ0

Output port
EI_PODDATA ( DBGE = “0”) Note:

X

X

X

X

X

X

PZ2

EI_SYNCLK ( DBGE = “0”) Note:
EI_PODREQ ( DBGE = “0”) Note:

X

X

X

PZ3

EI_REFCLK ( DBGE = “0”) Note:

X

X

X

PZ4

EI_TRGIN ( DBGE = “0”) Note:

X

X

X

PZ5

EI_COMRESET ( DBGE = “0”) Note:

X

X

X

PZ6

EO_MCUDATA ( DBGE = “0”) Note:

X

X

X

PZ7

EO_MCUREQ ( DBGE = “0”) Note:

X

X

X

PV7
Port W

Specification

X: Don’t care

PZ1

Note: When Debug mode, it is set to the Debug pin regardless of port setting.

92CZ26A-116

None

1

0

None

None

1

None

None

TMP92CZ26A
3.7.1

Port 1 (P10 to P17)
Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or
outputs by control register P1CR and function register P1FC.
In addition to functioning as a general-purpose I/O port, port1 can also function as a data
bus (D8 to D15).
Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1
to the following function pins:
AM1
0
0
1
1

AM0
0
1
0
1

Function Setting after reset is released
Don’t use this setting
Data bus (D8 to D15)
Don’t use this setting
Input port (P10 to P17)

P1CR Register
P1FC Register
External write enable

P1 Register
S

0
1

D8 to D15

Selector

Port read data
D8 to D15

S

1
0

Selector

External read enable

Figure 3.7.1 Port1

92CZ26A-117

P10 to P17
(D8 to D15)

TMP92CZ26A

Port 1 register
P1
(0004H)

bit Symbol

7

6

5

4

3

2

1

0

P17

P16

P15

P14

P13

P12

P11

P10

Read/Write

R/W

After reset

Data from external port (Output latch register is cleared to “0”)
Port 1 Control register

P1CR
(0006H)

bit Symbol

7

6

5

4

3

2

1

0

P17C

P16C

P15C

P14C

P13C

P12C

P11C

P10C

0

0

0

0

0

0

0

0

2

1

0

Read/Write
After reset

W

Function

0: Input 1: Output
Port 1 Function register

7
P1FC
(0007H)

6

5

4

3

bit Symbol

P1F

Read/Write

W

After reset

0/1

Note2:

0: Port
1:Data bus
(D8 to D15)

Function
Port 1 Drive register
P1DR
(0081H)

bit Symbol

7

6

5

4

3

2

1

0

P17D

P16D

P15D

P14D

P13D

P12D

P11D

P10D

1

1

1

1

1

1

1

1

Read/Write
After reset
Function

R/W

Input/Output buffer drive register for standby mode

Note1: Read-modify-write is prohibited for P1CR, P1FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.

Figure 3.7.2 Register for Port1

92CZ26A-118

TMP92CZ26A

3.7.2

Port 4 (P40 to P47)
Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a
general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit
can be set individually for function. Setting the AM1 and AM0 pins as shown below and
resetting the device initialize port 4 to the following function pins:
AM1
0
0
1
1

AM0
0
1
0
1

Function Setting after reset is released
Don’t use this setting
Address bus (A0 to A7)
Don’t use this setting
Output port (P40 to 47)

P4FC Register

P4 Register
S

0
1
Selector

A0 to A7

Read data

Figure 3.7.3 Port4

92CZ26A-119

P40 to P47
(A0 to A7)

TMP92CZ26A

Port 4 register
P4
(0010H)

bit Symbol

7

6

5

4

3

2

1

0

P47

P46

P45

P44

P43

P42

P41

P40

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

P47F

P46F

P45F

P44F

P43F

P42F

P41F

P40F

0/1

0/1

0/1

0/1

Read/Write
After reset

R/W
Port 4 Function register

P4FC
(0013H)

bit Symbol
Read/Write
After reset

W
0/1

0/1

0/1

0/1

Note2:
0:Port

Function

1:Address bus (A0 to A7)

Port 4 Drive register
P4DR
(0084H)

bit Symbol

7

6

5

4

3

2

1

0

P47D

P46D

P45D

P44D

P43D

P42D

P41D

P40D

1

1

1

1

Read/Write
After reset
Function

R/W

1

1

1

1

Input/Output buffer drive register for standby mode

Note1: Read-modify-write is prohibited for P4FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.

Figure 3.7.4 Register for Port1r

92CZ26A-120

TMP92CZ26A

3.7.3

Port 5 (P50 to P57)
Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a
general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit
can be set individually for function. Setting the AM1 and AM0 pins as shown below and
resetting the device initialize port 5 to the following function pins:

AM1
0
0
1
1

AM0
0
1
0
1

Function Setting after reset is released
Don’t use this setting
Address bus (A8 ~ A15)
Don’t use this setting
Output port (P50 ~ P57)

P5FC Register

P5 Register
S

0
1
Selector

A8 to A15
Read data

Figure 3.7.5 Port5

92CZ26A-121

P50 to P57
(A8 to A15)

TMP92CZ26A

Port 5 register
P5
(0014H)

bit Symbol

7

6

5

4

3

2

1

0

P57

P56

P55

P54

P53

P52

P51

P50

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

P57F

P56F

P55F

P54F

P53F

P52F

P51F

P50F

0/1

0/1

0/1

0/1

Read/Write
After reset

R/W
Port 5 Function register

P5FC
(0017H)

bit Symbol
Read/Write
After reset

W
0/1

0/1

0/1

0/1

Note2:
0:Port

Function

1:Address bus (A8 to A15)

Port 5 Drive register

P5DR
(0085H)

bit Symbol

7

6

5

4

3

2

1

0

P57D

P56D

P55D

P54D

P53D

P52D

P51D

P50D

1

1

1

1

Read/Write
After reset
Function

R/W

1

1

1

1

Input/Output buffer drive register for standby mode

Note1: Read-modify-write is prohibited for P5FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.

Figure 3.7.6 Register for Port5

92CZ26A-122

TMP92CZ26A

3.7.4

Port 6 (P60 to P67)
Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs
or outputs and function by control register P6CR and function register P6FC.
In addition to functioning as a general-purpose I/O port, port6 can also function as an
address bus (A16 to A23). Setting the AM1 and AM0 pins as shown below and resetting the
device initialize port 6 to the following function pins:

AM1
0
0
1
1

AM0
0
1
0
1

Function Setting after reset is released
Don’t use this setting
Address bus(A16 ~ A23)
Don’t use this setting
Input port(P60 ~ P67)

P6CR Register
P6FC Register

P6 Register

0
1

A16 to A23

S

Selector
S

Read data

1
0

Selector

Figure 3.7.7 Port6

92CZ26A-123

P60 to P67
(A16 to A23)

TMP92CZ26A

Port 6 register
P6
(0018H)

bit Symbol

7

6

5

4

3

2

1

0

P67

P66

P65

P64

P63

P62

P61

P60

Read/Write

R/W

After reset

Data from external port (Output latch register is cleared to “0”)
Port 6 Control register

P6CR
(001AH)

bit Symbol

7

6

5

4

3

2

1

0

P67C

P66C

P65C

P64C

P63C

P62C

P61C

P60C

0

0

0

0

0

0

0

0

3

2

1

0

P63F

P62F

P61F

P60F

0/1

0/1

0/1

0/1

Read/Write
After reset

W

Function

0:Input 1:Output
Port 6 Function register

P6FC
(001BH)

bit Symbol

7

6

5

4

P67F

P66F

P65F

P64F

Read/Write
After reset

W
0/1

0/1

0/1

0/1

Note2:
0: Port 1:Address bus (A16 to A23)

Function

Port 6 Drive buffer register

P6DR
(0086H)

bit Symbol

7

6

5

4

3

2

1

0

P67D

P66D

P65D

P64D

P63D

P62D

P61D

P60D

1

1

1

1

1

1

1

1

Read/Write
After reset
Function

R/W

Input/Output buffer drive register for standby mode

Note: Read-modify-write is prohibited for P6CR, P6FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.

Figure 3.7.8 Register for Port6

92CZ26A-124

TMP92CZ26A

3.7.5

Port 7 (P70 to P76)
Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be
individually set as either inputs or outputs by control register P7CR and function register
P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also
function interface-pin for external memory.
A reset initializes P70 pin to output port mode, and P71 to P76 pins to input port mode.
Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 7
to the following function pins:
Initial setting of P70 pin
AM1
0
0
1
1

AM0
0
1
0
1

Function Setting after reset is released
Don’t use this setting
RD pin
Don’t use this setting
Output port (P70)

P7FC register

0S

P7 register

1

RD

P70 ( RD )

Selector

Port read data

P7CR register
P7FC register
0 S

P7 register
NDRE , NDWE

0 S

WRLL , WRLU

1

1
Selector

Selector

Port read data

S 1
0
Selector

Figure 3.7.9 Port7

92CZ26A-125

P71 ( WRLL , NDRE )
P72 ( WRLU , NDWE )

TMP92CZ26A

P7CR register
P7FC register
S

P7 register
EA24, EA25
S1

Read data

P73 (EA24)
P74 (EA25)

0
1
Selector

0
Selector

P7CR register
P7FC register
0 S

P7 register

1

R/W

P75(R/W, NDR /B )

Selector

S1

Port read data

0
Selector

NDR/ B

P7CR register
P7FC register
P76 ( WAIT )

P7 register
Port read data
WAIT

Figure 3.7.10 Port7

92CZ26A-126

TMP92CZ26A
Port 7 register

7
P7
(001CH)

bit Symbol

6

5

4

3

2

1

0

P76

P75

P74

P73

P72

P71

P70

Read/Write

R/W
Data from external port Data from external port

After reset

Data from external port

(Output latch register is (Output latch register is (Output latch register is
set to “1”)

cleared to “0”)

1

set to “1”)

Port 7 Control register

7
P7CR
bit Symbol
(001EH)
Read/Write

6

5

4

P76C

P75C

P74C

3

2

1

P73C

P72C

P71C

0

0

0

0

W

After reset

0

0

0

Function

0: Input 1: Output
Port 7 Function register

7
bit Symbol

P7FC
(001FH)

6

5

4

3

2

1

0

P76F

P75F

P74F

P73F

P72F

P71F

P70F

Read/Write

W

After reset

0
0:Port
1: WAIT

Function

0

0
0
Refer to following table

0

0

0:Port
1: NDWE at
=0
WRLU at
=1

0/1 Note3:
0:Port
1: RD

0:Port
1:
NDRE at
=0
WRLL at
=1

Port 7 Drive register

7
bit Symbol

P7DR
(0087H)

6

5

4

3

2

1

0

P76D

P75D

P74D

P73D

P72D

P71D

P70D

1

1

1

1

1

1

Read/Write

R/W

After reset

P72 setting

P73 setting

0

P71 setting

<


<


0

1

Input Port
Reserved

Output Port
EA24Output




>
0

1

Input Port
Reserved

Output Port
NDWE Output


0

1

P76 setting

P75 setting




0

(at =0)
WRLU Output
(at =1)

1

Input Port
WAIT Input

1

Input Port
Reserved

Output Port
NDRE Output
(at =0)
WRLL Output
(at =1)


0

Output Port
Reserved

1

P74 setting

1

0

0

1


0


0

1

Input/Output buffer drive register for standby mode

Function

Input Port
NDR/ B Input

1
Output Port
R/W Output


0

1

0

1

Input Port
Reserved

Output Port
EA25Output

1

Note1: Read-modify-write is prohibited for P7CR, P7FC.
Note2: When NDRE and NDWE are used, set registers by following order to avoid outputting negative glitch.
Order

Registser bit2

bit1

-----------------------------------------------------(1)

P7

0

0

(2)

P7FC

1

1

(3)

P7CR

1

1

Note3: Note2: It is set to “Port” or “Data bus” by AM pins state.

Figure 3.7.11 Register for Port7

92CZ26A-127

TMP92CZ26A
Port 8 (P80 to P87)
Port 80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to “0” and output
latches of P80 to P81, P83 to P87 to “1”. But if it is started at boot mode (AM [1:0]= “11”),
output latch of P82 is set to “1”.
Port 8 also function as interface-pin for external memory.
Writing “1” in the corresponding bit of P8FC, P8FC2 enables the respective functions.
Resetting resets P8FC to “0” and P8FC2 to “0”, sets all bits to output ports.

Reset

Function
control2

P8FC2 write

Internal data bus

3.7.6

Function
control

P8FC write
S
Output latch
Selector
P8 write

P80 ( CS0 )
P81 ( CS1, SDCS )
P82 ( CS2 , CSZA , SDCS )
P83 ( CS3 , CSXA )
P84 ( CSZB )
P85 ( CSZC )
P86 ( CSZD , ND0CE )
P87 ( CSXB , ND1CE )

CS0 , SDCS , SDCS , CSXA , CSZB , CSZC , ND0CE , ND1CE

P8 read

“1”, SDCS , CSZA , CSXA ,“1”, “1”, “1”, “1”
CS0 , CS1, CS2 , CS3 , CSZB , CSZC , CSZD , CSXB

Figure 3.7.12 Port 8

92CZ26A-128

TMP92CZ26A

Port 8 register

bit Symbol

P8
(0020H)

7

6

5

4

3

2

1

0

P87

P86

P85

P84

P83

P82

P81

P80

1

1

1

1

1

0 (Note3)

1

1

Read/Write

R/W

After reset

Port 8 Function register

7

6

5

4

3

2

1

0

P87F

P86F

P85F

P84F

P83F

P82F

P81F

P80F

0

0

0

0

0

0

0: Port
1: 

0: Port
1: 

bit Symbol

P8FC
(0023H)

Read/Write

W

After reset
Function

0: Port
1: CSZB

0: Port
1: CSZC

0

Refer to following table

0: Port
1: CS1

0
0: Port
1: CS0

Port 8 Function registers 2

bit Symbol

P8FC2
(0021H)

7

6

3

2

1

P87F2

P86F2

P83F2

P82F2

P81F2

0

0

Read/Write

5

4

W

After reset

W

0

Function

0

0

0

Refer to following table

0: CSXB

0: CSZD

1: ND1CE

1: ND0CE

0: 

1: SDCS

Port 8 Drive register

bit Symbol

P8DR
(0088H)

7

6

5

4

3

2

1

0

P87D

P86D

P85D

P84D

P83D

P82D

P81D

P80D

1

1

1

1

1

1

1

1

Read/Write

R/W

After reset

Input/Output buffer drive register for standby mode

Function

P83 setting

P86 setting


0

0

1

1

Output port
Don’t setting

CSZD Output

ND0CE
Output

0
1



1




0

P82 setting



0

1

Output port

CS2 Output

CSZA

SDCS
Output



Output
port

CS3

Output
CSXA Output

0
1

Output

P87 setting


0

1

0

Output port

CSXB Output

1

Don’t setting

ND1CE Output



Note1: Read-modify-write is prohibited for P8FC and P8FC2.
Note2: Don’t write “1” to P8- register before setting P82-pin to /CS2 or /CSZA because of P82-pin output “0” as /CE for
program memory by reset.
Note3: If it is started at boot mode (AM [1:0]= “11”), output latch of P82 is set to “1”.
Note4:

When ND0CE and ND1CE are used, set registers by following order.

Order

Registser bit2

bit1

-----------------------------------------------------(1)

P8

1

1

(2)

P8FC2

1

1

(3)

P8FC

1

1

Figure 3.7.13 Register for Port 8

92CZ26A-129

TMP92CZ26A
3.7.7

Port 9 (P90 to P92, P96, P97)
P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on bit basis using the
control register. Resetting sets P90 to P92 to input port and all bits of output latch to”1”.
P96 to P97 are 2-bit general-purpose input port.
Writing “1” in the corresponding bit of P9FC enables the respective functions.
Resetting resets the P9FC to “0”, and sets all bits to input ports.

(1) Port 90 (TXD0), Port 91 (RXD0), Port 92 (SCLK0, CTS0 )
Port 90 to 92 are general-purpose I/O port. They are also used either SIO0. Each pin
is below.

P90

P91

P92

SIO mode

UART, IrDA mode

(SIO0 module)

(SIO0 module)

TXD0

TXD0

(Data output)

(Data output)

RXD0

RXD0

(Data input)

(Data input)

SCLK0

CTS0

(Clock input or

(Clear to send)

output)

Reset
Direction
control
(on bit basis)
P9CR write

Internal data bus

Function
control
(on bit basis)
P9FC write
S
Output latch
P9 write
TXD0 output

A

S

Selector
B
S B
Selector

P9 read

A

Figure 3.7.14 P90

92CZ26A-130

P90 (TXD0)
Open-drain enable
P9FC2

TMP92CZ26A
Reset
Direction
control
(on bit basis)

Internal data bus

P9CRwrite
Function
control
(on bit basis)
P9FCwrite
S
Output latch

A

S

Selector
P9 write

P91(RXD0)
P92(SCLK0, CTS0 )

B

SCLK0 output

S B
Selector

P9 read

A
RXD0 input
SCLK0 input
CTS0 input

Figure 3.7.15 P91, 92

Internal data bus

Reset
Function
control

P9FC write

AVCC
TSICR0


Switch for TSI
typ.10Ω

TSICR0

P96 (INT4,PX)
P97 (PY)

P9 read

TSICR1

S
INT4

Rising/Falling
edge-ditection

A

Selector
B

IIMC

Only for P96

De-bounce
Circuit

TSICR0

TSICR0
TSICR0

Figure 3.7.16 Port 96,97

92CZ26A-131

Pull-down resistor
typ.50KΩ

TMP92CZ26A

Port 9 register

P9
(0024H)

bit Symbol
Read/Write

7

6

P97

P96

5

4

3

2

0

P91
P90
R/W
Data from external port (Output
latch register is set to “1”)

R
Data from external
port

After reset

1

P92

Port 9 control register

7
P9CR
(0026H)

6

5

4

3

bit Symbol
Read/Write
After reset
Function

2

1

0

P92C

P91C
W
0

P90C

0

0

Refer to following table

Port 9 function register

7
P9FC
(0027H)

6

bit Symbol
Read/Write
After reset

5

4

3

2

P96F
W
0
0: Input
port
1: INT4

Function

1

0

P92F
W
0

P90F
W
0

Refer to
following
table

Refer to
following
table

Port 9 Function registers 2

7
P9FC2
(0025H)

bit Symbol
Read/Write
After reset
Function

6

5

4

3

2

−
W
0
Always
write “0”

1

−
W
0
Always
write “0”

0
P90F2
W
0
0:CMOS
1:
open-drain

Port 9 drive register

P9DR
(0089H)

bit Symbol
Read/Write
After reset
Function

7

6

P97D

P96D

5

4

1

1



1

0
P90D

Input port,
CTS0 Input
Don’t setting

0
Input port
RXD0 Input

1

P90 setting




Input port,
CTS0 Input
Don’t setting

1
P91D
R/W
1

1
Input/Output buffer drive register for standby mode
P91 setting

P92 setting
0

2
P92D

R/W
1



0

3

1
Output port


0
1

0

1

Input port
Don’t
setting

Output port
TXD0
Output

Note 1: Read-modify-write is prohibited for P9CR, P9FC and P9FC2.
Note 2: When setting P96 pin to INT4 input, set P9DR to “0” (prohibit input), and when driving P96 pin to “0”, execute
HALT instruction. This setting generates INT4 inside. If don’t using external interrupt in HALT condition, set like an
interrupt don’t generated. (e.g. change port setting)

Figure 3.7.17 Register for Port 9

92CZ26A-132

TMP92CZ26A
Port A (PA0 to PA7)
Port A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to
functioning as general-purpose I/O ports, port A0 to A7 can also Key-on wake-up function
as Keyboard interface. The various functions can each be enabled by writing a “1” to the
corresponding bit of the Port A Function Register (PAFC).
Resetting resets all bits of the register PAFC to “0” and sets all pins to be input port.

INTKEY
Rising edge
-ditection
Internal data bus

3.7.8

PA0~PA7
8 input OR

Reset
KEY-ON
ENABLE
(on bit basis)

Pull-up resistor

PAFC write
PA0 to PA7
(KI0 to KI7)
PA read

Figure 3.7.18 Port A

When PAFC = “1”, if either of input of KI0-KI7 pins falls down, INTKEY interrupt is
generated. INTKEY interrupt can release all HALT mode.

92CZ26A-133

TMP92CZ26A

Port A register

PA
(0028H)

bit Symbol
Read/Write
After reset

7

6

5

4

3

2

1

0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

R
Data from external port
Port A Function register

bit Symbol
PAFC
(002BH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PA7F

PA6F

PA5F

PA4F

PA3F

PA2F

PA1F

PA0F

0

0

0
0: KEY IN disable

0

0
1: KEY IN enable

0

0

0

W

Port A Drive register

bit Symbol
PADR
(008AH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PA7D

PA6D

PA5D

PA4D

PA3D

PA2D

PA1D

PA0D

1

1

1

1

R/W
1
1
1
1
Input/Output buffer drive register for standby mode

Note 1: Read-modify-write is prohibited for PAFC.

Figure 3.7.19 Register for Port A

92CZ26A-134

TMP92CZ26A
Port C (PC0 to PC7)
PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input
or output. Resetting sets Port C to an input port. It also sets all bits of the output latch
register to “1”.
In addition to functioning as a general-purpose I/O port, Port C can also function as
input pin for timers (TA0IN, TA2IN), input pin for external interruption (INT0 to INT3),
Extension address function (EA26, EA27, EA28) and output pin for Key (KO8). Above
setting is used the function register PCFC. Edge select of external interruption establishes
it with IIMC register, which there is in interruption controller.
(1) PC0 (INT0), PC2 (INT2)
Reset

Direction control

PCCR write
Internal data bus

3.7.9

Function control

PCFC write
S
PC0 (INT0)
PC2(INT2)

Output latch

PCwrite
S
B
Selector
PC read
INT0
INT2

A
Level/edge selection
and
Rising/Falling selection
IIMC


Figure 3.7.20 Port C0, C2

92CZ26A-135

TMP92CZ26A
(2) PC1 (INT1, TA0IN), PC3 (INT3, TA2IN)
Reset

Direction control

Internal data bus

PCCR write

Function control

PCFCwrite
S
PC1 (INT1,TA0IN)
PC3 (INT3, TA2IN)

Output latch

PCwrite
S
B
Selector
A

PC read

Level/edge selection
and
Rising/Falling selection

INT1
INT3

IIMC

TA0IN
TA2IN

Figure 3.7.21 Port C1,C3

92CZ26A-136

TMP92CZ26A

(3) PC4 (EA26), PC5 (EA27), PC6 (EA28)
Reset

Direction
control
(on bit basis)
PCCRwrite

Internal data bus

Function
control
(on bit basis)
PCFC write
S
A
B Selector

S
Output latch
PC write

PC4(EA26)
PC5(EA27)
PC6(EA28)

C

EA26
EA27
EA28

S B
Selector

PC read

A

Figure 3.7.22 Port C4, C5, C6
(4) PC7 (KO8)

Reset
Direction
control
PCCR write
Function
control

Internal data bus

PCFC write
PC7(KO8)

S
Output latch

Open-drain enable

PC write
S B
Selector
PC read

A

Figure 3.7.23 Port C7

92CZ26A-137

TMP92CZ26A

Port C register

PC
(0030H)

bit Symbol
Read/Write
After reset

7

6

5

4

3

2

1

0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

R/W
Data from external port (Output latch register is set to “1”)
Port C control register

PCCR
(0032H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PC7C

PC6C

PC5C

PC4C

PC3C

PC2C

PC1C

PC0C

0

0

0

0

0

0

W
0
0
0: Input 1: Output

Port C function register

PCFC
(0033H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PC7F

PC6F

PC5F

PC4F

PC3F

PC2F

PC1F

PC0F

0

0

0

0

0

0

W
0
0
Refer to following table

Port C drive register

bit Symbol
PCDR
(008CH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PC7D

PC6D

PC5D

PC4D

PC3D

PC2D

PC1D

PC0D

1

1

1

1

R/W
1
1
1
1
Input/Output buffer drive register for standby mode
PC1 setting

PC2 setting


0
1

0

1

Input port
INT2

Output port
Don’t setting

0
1




0
1

PC5 setting

0

1

Input port
INT1

Output port
TA0IN input


0
1



0

1

Input port
EA27output

Output port
Reserved


0
1

0

1

Input port
EA26 output

Output port
Reserved


0
1

PC7 setting

0
1

1

Input port
INT0

Output port
Don’t setting



0

1

Input port
INT3

Output port
TA2IN input

PC6 setting




0

PC3 setting

PC4 setting




PC0 setting





0
Input port
Don’t
setting

1
Output port
KO8output
(Open-drain)


0
1

0

1

Input port
EA28output

Output port
Reserved

Note 1: Read-Modify-Write is prohibited for the registers PCCR, PCFC.
Note 2: When setting PC3-PC0 pins to INT3-INT0 input, set PCDR to “0000”(prohibit input), and when driving
PC3-PC0 pins to “0”, execute HALT instruction. This setting generates INT3-INT0 inside. If don’t use external interrupt
in HALT condition, set like an interrupt don’t generated. (e.g. change port setting)

Figure 3.7.24 Register for Port C

92CZ26A-138

TMP92CZ26A
3.7.10 Port F (PF0 to PF5, PF7)
Port F0 to F5 are 6-bit general-purpose I/O ports. Resetting sets PF0 to PF5 to be input
ports. It also sets all bits of the output latch register to “1”. In addition to functioning as
general-purpose I/O port pins, PF0 to PF5 can also function as the output for I2S0, I2S1. A
pin can be enabled for I/O by writing a “1” to the corresponding bit of the Port F Function
Register (PFFC).
Port F7 is 1-bit general-purpose output port. In addition to functioning as
general-purpose output port, PF7 can also function as the SDCLK output. Resetting sets
PF7 to be a SDCLK output port.

(1) Port F0 (I2S0CKO), Port F1 (I2S0DO), Port F2 (I2S0WS), Port F3 (I2S1CKO), Port F4
(I2S1DO), Port F5 (I2S1WS), Port F0 to F5 are general-purpose I/O port. They are also
used either I2S. Each pin is below.

I2Smode

I2Smode

(I2S0Module)
PF0

I2S0CKO

(I2S1Module)
PF4

(Clock output)
PF1

I2S0DO

(Clock output)
PF5

(Data output)
PF2

I2S0WS

I2S1CKO

I2S1DO
(Data output)

PF6

(Word-select
output)

92CZ26A-139

I2S1WS
(Word-select
output)

TMP92CZ26A
Reset
Direction
control
(on bit basis)

Internal data bus

PFCR write
Function
control
(on bit basis)
PFFC write
S
Output latch

S

A

Selector
PF write

B

I2S0CKO output
I2S1CKO/X1D4output

PF0 (I2S0CKO)
PF3 (I2S1CKO)

S B
Selector

PF read

A

Figure 3.7.25 Port F0, F3

Reset
Direction
control
(on bit basis)
PFCRwrite

Internal data bus

Function
control
(on bit basis)
PFFC write
S
Output latch

A

S

Selector
PF write
I2S0DO,I2S1DO output
I2S0WS,I2S1WS output

B
S B
Selector

PF read

A

Figure 3.7.26 Port F1, F2, F4, F5

92CZ26A-140

PF1(I2S0DO)
PF2(I2S0WS)
PF4(I2S1DO)
PF5(I2S1WS)

TMP92CZ26A

(2) Port F7 (SDCLK),
Port F7 is general-purpose output port. In addition to functioning as general-purpose
output port, PF7 can also function as the SDCLK output.

Internal data bus

Reset

Function
control
(on bit basis)
PFFC write
A S

S
Output latch
SDCLK

Selector
B

PF write

PF read

Figure 3.7.27 Port F7

92CZ26A-141

PF7(SDCLK)

TMP92CZ26A

Port F register

7
bit Symbol
PF
(003CH) Read/Write
After reset

6

PF7
R/W
1

5

4

3

2

1

0

PF5

PF4

PF3

PF2

PF1

PF0

R/W
Data from external port (Output latch register is set to “1”)
Port F control register

7

6

bit Symbol
PFCR
(003EH) Read/Write
After reset
Function

5

4

3

2

1

0

PF5C

PF4C

PF3C

PF2C

PF1C

PF0C

0

0

0

0

W
0
0
Refer to following table

Port F function register

7
bit Symbol
PFFC
(003FH) Read/Write
After reset

PF7F
W
1

Function

0: Port
1: SDCLK

6

5

4

3

2

1

0

PF5F

PF4F

PF3F

PF2F

PF1F

PF0F

0

0

0

0

W
0
0
Refer to following table

Port F drive register

bit Symbol
PFDR
(008FH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PF7D

PF6D

PF5D

PF4D

PF3D

PF2D

PF1D

PF0D

1

1

1

1

R/W
1
1
1
1
Input/Output buffer drive register for standby mode





0

1



Input port
Output port
I2S0WS output

1

1

Input port
Output port
I2S0DO output

1

1



1

PF3 setting


0

1



Input port
Output port
I2S1WS output

0
1

1

Input port
Output port
I2S0CKOoutput

0

PF4 setting


0

0


0

PF5 setting


1



0


0

0

PF0 setting

PF1 setting

PF2 setting

0

1



Input port
Output port
I2S1DO output

Note 1: Read-Modify-Write is prohibited for the registers PFCR, PFFC and PFFC2.

Figure 3.7.28 Register for Port F

92CZ26A-142

0
1

Input port
Output port
I2S1CKOoutput

TMP92CZ26A
3.7.11 Port G (PG0 to PG5)
PG0 to PG5 are 6-bit input port and can also be used as the analog input pins for the
internal AD converter. PG3 can also be used as ADTRG pin for the AD converter.
PG2, PG3 can also be used as MX, MY pin for Touch screen interface.
(PG) register is prohibited to access by byte. All the instruction (Arithmetic/Logical/
Bit operation and rotate/shift instruction) access by byte are prohibited. Word access is

Internal data bus

always needed.

Port G read

PG0(AN0),
PG1(AN1),
PG2(AN2,MX),
PG3(AN3,MY, ADTRG )
PG4(AN4)
PG5(AN5)

Conversion

AD read

Result
Register

AD

Channel

Converter

Selector

ADTRG
(for PG3 only)
(PG2,PG3 only)
TSICR0

Switch for TSI
Typ.10Ω

Figure 3.7.29 Port G

92CZ26A-143

TSICR0

TMP92CZ26A

Port G register

7
PG
(0040H)

6

Bit Symbol
Read/Write
After reset

5

4

3

2

1

0

PG5

PG4

PG3

PG2

PG1

PG0

R
Data from external port

Note: Selection of the input channel of AD converter and ADTRG input mode register is enabled by setting AD converter.
Port G Function register

7
PGFC
(0043H)

6

5

4

Bit Symbol
Read/Write
After reset
Function

3

2

1

0

3

2

1

0

PG3D

PG2D

PG3F
W
0
0: Input port
or AN3

1: ADTRG
Port G driver register

7
PGDR
(0090H)

6

5

4

Bit Symbol
Read/Write
After reset
Function

R/W
1
1
Input/Output buffer
drive register for
standby mode

Figure 3.7.30 Register for Port G
Note 1: Read-Modify-Write is prohibited for the registers PGFC.
Note 2: (PG) register is prohibited to access by byte. All the instruction (Arithmetic/ Logical/ Bit operation and rotate/ shift
instruction) access by byte are prohibited. Word access is always needed.
Example:

LD

wa, (PG)

: Using only “a” register data, and cancel “w” register data.

Note 3: Don’t use PG register at the state that mingles Analog input and Digital input.

92CZ26A-144

TMP92CZ26A

3.7.12 Port J (PJ0 to PJ7)
PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and
they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port,
Port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM,
SDLUDQM, and SDCKE), SRAM ( SRWR , SRLLB and SRLUB ) and NAND-Flash(NDALE
and NDCLE). Above setting is used the function register PJFC.
But Output signal either SDRAM or SRAM for PJ0 to PJ2 are selected automatically
according to the setting of memory controller.

Reset
Function
control2
(on bit basis)

Internal data bus

PJFC2 write
Function
control
(on bit basis)

S

PJFC write
Selector
Selector

PJ0( SDRAS , SRLLB )
PJ1 ( SDCAS , SRLUB )
PJ2( SDWE , SRWR )
PJ3(SDLLDQM)
PJ4(SDLUDQM)
PJ7(SDCKE)

PJ write
SRLLB , SRLUB , SRWR

PJ read

SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCKE

Figure 3.7.31 Port J0 to J4 and J7

92CZ26A-145

TMP92CZ26A
Reset
Direction
control
PJCR write

Internal data bus

Function
control
PJFC write
S
Output latch

A

S

Selector
PJ write
NDALE, NDCLE
output

B
S B
Selector

PJ read

A

Figure 3.7.32 Port J5,J6

92CZ26A-146

PJ5 (NDALE),
PJ6 (NDCLE)

TMP92CZ26A

Port J register

bit Symbol
PJ
(004CH) Read/Write

7

6

5

4

3

2

1

0

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

1

1

1

1

3

2

1

0

R/W
1

After reset

Data from external port
(Output latch register is
set to “1”)

1

Port J control register

7
bit Symbol
PJCR
(004EH) Read/Write
After reset
Function

6

5

PJ6C

PJ5C

4

W
0

0

0: Input, 1: Output

Port J function register

bit Symbol
PJFC
(004FH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PJ7F

PJ6F

PJ5F

PJ4F

PJ3F

PJ2F

PJ1F

PJ0F

0
0: Port
1: SDCKE

0
0: Port
1: NDCLE

0
0: Port
1: NDALE

0

0

0

W
0

0: Port
1:
SDLUDQM

0: Port
1:
SDLLDQM

0
0: Port
1: SDWE ,
SRWR

0: Port
0: Port
1: SDCAS , 1: SDRAS ,
SRLUB
SRLLB

Port J drive register

PJDR
(0093H)

bit Symbol

7

6

5

4

3

2

1

0

PJ7D

PJ6D

PJ5D

PJ4D

PJ3D

PJ2D

PJ1D

PJ0D

1

1

1

1

1

1

1

1

Read/Write
After reset
Function

R/W

Input/Output buffer drive register for standby mode

Note 1: Read-Modify-Write is prohibited for the registers PJCR and PJFC.

Figure 3.7.33 Register for Port J

92CZ26A-147

TMP92CZ26A

3.7.13 Port K (PK0 to PK7)
PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to
PK7 pins output “0”. In addition to functioning as output port function, Port K also
function as output pins for LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC, and
LGOE0 to LGOE2).
Above setting is used the function register PKFC.

Reset
Function control

PKFC write
S
A

Output latch

B

Selector

Internal data bus

(on bit basis)

Output buffer

PK0 (LCP0)
PK1 (LLOAD)
PK2 (LFR)
PK3 (LVSYNC)
PK4 (LHSYNC)
PK5 (LGOE0)
PK6 (LGOE1)
PK7 (LGOE2)

PK write
LCP0, LLOAD, LFR, LVSYNC,LHSYNC,LGOE0 to LGOE2
PK read

Figure 3.7.34 Port K0 to K7

92CZ26A-148

TMP92CZ26A

Port K register

PK
(0050H)

bit Symbol
Read/Write
After reset

7

6

5

4

3

2

1

0

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

0

0

0

0

0

0

0

0

R/W

Port K function register

PKFC
(0053H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PK7F

PK6F

PK5F

PK4F

PK3F

PK2F

PK1F

PK0F

0

0

0

0

0

0:Port
1: LHSYNC

0: Port
1: LVSYNC

W
0:Port
1:LGOE2

0:Port
1:LGOE1

0:Port
1:LGOE0

0
0: Port
1: LFR

0
0: Port
1: LLOAD

0
0: Port
1: LCP0

Port K drive register

PKDR
(0094H)

bit Symbol

7

6

5

4

3

2

1

0

PK7D

PK6D

PK5D

PK4D

PK3D

PK2D

PK1D

PK0D

1

1

1

1

1

1

1

1

Read/Write
After reset
Function

R/W

Input/Output buffer drive register for standby mode

Note 1: Read-Modify-Write is prohibited for the registers PKFC.

Figure 3.7.35 Register for Port K

92CZ26A-149

TMP92CZ26A

3.7.14 Port L (PL0 to PL7)
PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to
PL7 pins output “0”. In addition to functioning as a general-purpose output port, Port L
can also function as a data bus for LCD controller (LD0 to LD7). Above setting is used the
function register PLFC.

Reset

Internal data bus

Function
control
PLFC write
R
Output latch
PL write
LD0 to LD7

A

S

Selector
B

PL read

Figure 3.7.36 Port L0 to L7

92CZ26A-150

PL0 to PL7
(LD0 to LD7)

TMP92CZ26A

Port L register

PL
(0054H)

bit Symbol
Read/Write
After reset

7

6

5

4

3

2

1

0

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

0

0

0

0

0

0

0

0

R/W
Port L function register

PLFC
(0057H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PL7F

PL6F

PL5F

PL4F

PL3F

PL2F

PL1F

PL0F

0

0

0
0: Port

0

0

W
0
0
0
1: Data bus for LCDC (LD7 toLD0)

Port L drive register

PLDR
(0095H)

bit Symbol

7

6

5

4

3

2

1

0

PL7D

PL6D

PL5D

PL4D

PL3D

PL2D

PL1D

PL0D

1

1

1

1

1

1

1

1

Read/Write
After reset
Function

R/W

Input/Output buffer drive register for standby mode

Note 1: Read-Modify-Write is prohibited for the registers PLFC.

Figure 3.7.37 Register for Port L

92CZ26A-151

TMP92CZ26A

3.7.15 Port M (PM1, PM2, PM7)
PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and
PM1, PM2 and PM7 pins output “1”. In addition to functioning as output ports, Port M also
function as output pin for timers (TA1OUT), output pins for RTC alarm ( ALARM ), output
pin for melody/alarm generator (MLDALM, MLDALM ) and Power control pin (PWE).
Above setting is used the function register PMFC.
PM1 has two output function which MLDALM and TA1OUT, and PM2 has two output
function which ALARM and MLDALM . This selection is used PM, PM.

Reset
Function control

Internal data bus

PMFC write
S
Output latch

PM write

S
A
Y
Selector
B

PM Reset
TA1OUT

A

S

MLDALM

Y
Selector
B

Figure 3.7.38 Port M1

92CZ26A-152

PM1
(MLDALM,
TA1OUT)

TMP92CZ26A

Reset
Function control
(on bit basis)

Internal data bus

PMFC write
S
Output latch

S
A
Y
Selector
B

PM write

PM2
( ALARM ,
MLDALM )

PM read
MLDALM
ALARM

A

S

Y
Selector
B

Figure 3.7.39 Port M2

Reset
Function
control
(on bit basis)

Internal data bus

PMFC write
S
Output latch

PM write

S
A
Y
Selector
B

PM read
PWE

Figure 3.7.40 Port M7

92CZ26A-153

PM7 (PWE)

TMP92CZ26A

Port M register

7
PM
(0058H)

bit Symbol
Read/Write
After reset

6

5

4

3

PM7
R/W
1

2

1

PM2

PM1

0

R/W
1

1

Port M function register

7
bit Symbol
PMFC
(005BH) Read/Write
After reset

6

5

4

3

PM7F
W
0

2

1

PM2F

PM1F

0

W

0: Port
1: PWE

Function

0

0

0: Port
1: ALARM
at =1,
MLDALM
at =0

0: Port
1: MLDALM
at =1,
TA1OUT
at =0

Port M drive register

7
PMDR
(0096H)

bit Symbol
Read/Write
After reset

Function

6

5

4

3

PM7D

2

1

PM2D

PM1D

R/W

R/W

1

1

Input/Outp
ut buffer
drive
register for
standby
mode

1

Input/Output buffer
drive register for
standby mode

Note 1: Read-Modify-Write is prohibited for the registers PMFC.

Figure 3.7.41 Register for Port M

92CZ26A-154

0

TMP92CZ26A
3.7.16 Port N (PN0 to PN7)
PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input
or output. Resetting sets Port N to an input port. In addition to functioning as a
general-purpose I/O port, Port N can also function as interface pin for key-board (KO0 to
KO7). This function can set to open-drain type output buffer.

Reset
Direction
control
(on bit basis)

Internal data bus

PNCR write
Function
control
(on bit basis)
PNFC write
S
Output latch

PN0(KO0) to PN7(KO7)
Open-drain
enable

PN write
S B
Selector
PC read

A

Figure 3.7.42 Port N

92CZ26A-155

TMP92CZ26A

Port N register

bit Symbol
PN
(005CH) Read/Write
After reset

7

6

5

4

3

2

1

0

PN7

PN6

PN5

PN4

PN3

PN2

PN1

PN0

R/W
Data from external port (Output latch register is set to “1”)
Port N control register

bit Symbol
PNCR
(005EH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PN7C

PN6C

PN5C

PN4C

PN3C

PN2C

PN1C

PN0C

0

0

0

0
1: Output

0

0

0

W
0
0: Input

Port N function register

bit Symbol
PNFC
(005FH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PN7F

PN6F

PN5F

PN4F

PN3F

PN2F

PN1F

PN0F

0

0

0

0

W
0
0
0: CMOS output

0
0
1: Open-drain output

Port N drive register

PNDR
(0097H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PN7D

PN6D

PN5D

PN4D

PN3D

PN2D

PN1D

PN0D

1

1

1

1

R/W
1
1
1
1
Input/Output buffer drive register for standby mode

Note 1: Read-Modify-Write is prohibited for the registers PNCR and PNFC.

Figure 3.7.43 Register for Port N

92CZ26A-156

TMP92CZ26A
3.7.17 Port P (PP1 to PP7)
Port P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port P1 to P5 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, P0 to P5 can also function as
output pin for timers (TA3OUT, TA5OUT, TA7OUT), input pin for timers (TB0IN0,
TB1IN0), input pin for external interruption (INT5 to INT7).
Port P6 and P7 are 2-bit output port. Resetting sets output latch to “0”.In addition to
functioning as output port, PP6 and PP7 can also function as output pin for timers
(TB0OUT0, TB1OUT1).
Above setting is used the control register PPCR and function register PPFC.
Edge select of external interruption establishes it with IIMC register, which there is in
interruption controller.
In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and
INT7 don’t depend on IIMC1 register setting. INT6 and INT7 operate by setting
TBnMOD.
Reset
Direction
control
(on bit basis)

Internal data bus

PPCR write
Function
control
(on bit basis)
PPFC write
R
Output latch

A

S

Selector
PP write
TA3OUT output
TA5OUT output

B
S B
Selector

PP read

A

Figure 3.7.44 Port P1, P2

92CZ26A-157

PP1 (TA3OUT)
PP2 (TA5OUT)

TMP92CZ26A
Reset
Direction control
(on bit basis)
PPCR write

Internal data bus

Function
control
(on bit basis)
PPFC write
R
Output latch

A

S

Selector
B

PP write

PP3 (INT5, TA7OUT)

TA7OUT
S B
Selector
PP read

A
Level/edge selection
and
Rising/Falling selection

INT5

IIMC

Figure 3.7.45 Port P3
Reset

Direction control
(on bit basis)

Internal data bus

PPCR write
Function control
(on bit basis)

PPFC write
R
PP4 (INT6,TB0IN0)
PP5 (INT7, TB1IN0)

Output latch

PP write
S
B
Selector
PP read

A
Level/edge selection
and
Rising/Falling selection

INT6
INT7
(from TMRB0) INT6
(from TMRB1) INT7

IIMC


TB0IN0
TB1IN0

Figure 3.7.46 Port P4,P5

92CZ26A-158

TMP92CZ26A

Internal data bus

Reset
Function
control
(on bit basis)
PPFC write
R
Output latch

A

S

Selector
PP write

B

TB0OUT0 output
TB1OUT0 output

Figure 3.7.47 Port P6, P7

92CZ26A-159

PP6 (TB0OUT0)
PP7 (TB1OUT0)

TMP92CZ26A

Port P register

PP
(0060H)

bit Symbol
Read/Write
After reset

7

6

5

PP7

PP6

PP5

4

0

0

3

2

1

PP4
PP3
PP2
R/W
Data from external port
(Output latch register is cleared to “0”)

0

PP1

Port P control register

7

6

bit Symbol
PPCR
(0062H) Read/Write
After reset
Function

5

4

PP5C

PP4C

0

0

3

2

1

PP3C
PP2C
W
0
0
0: Input 1: Output

0

PP1C
0

Port P function register

PPFC
(0063H)

bit Symbol
Read/Write
After reset
Function

7

6

5

PP7F

PP6F

PP5F

4

0

0

0

0:Port
1:TB1OUT0

0:Port
1:TB0OUT0

3

2

1

PP4F
PP3F
PP2F
W
0
0
0
Refer to following table

0

PP1F
0

Port P drive register

PPDR
(0098H)

bit Symbol

7

6

5

4

3

2

1

PP7D

PP6D

PP5D

PP4D

PP3D

PP2D

PP1D

1

1

1

1

1

1

Read/Write
After reset

R/W

PP2 setting

PP3 setting

<


0
1

1

Input/Output buffer drive register for standby mode

Function



0

PP1 setting

>


>
0

1

Input port
INT5 input

Output port
TA7OUT output


0
1

0

1

Input port
Don’t setting

Output port
TA5OUT output

PP5 setting

0
1

0

1

Input port
Don’t setting

Output port
TA3OUT output

0

1

Input port
INT6 input

Output port
TB0IN0 input

PP4 setting




0

1


0
1




Input port
INT7 input

Output port
TB1IN0 input

0
1

Note1: Read-Modify-Write is prohibited for the registers PPCR, PPFC.
Note2: When setting PP5, PP4, PP3 pins to INT7,INT6,INT5 input, set PPDR to “0000” (prohibit input), and when
driving PP5,PP4,PP3 pins to “0”, execute HALT instruction. This setting generates INT7, INT6, and INT5 inside. If don’t using
external interrupt in HALT condition, set like an interrupt don’t generated.

Figure 3.7.48 Register for Port P

92CZ26A-160

TMP92CZ26A
3.7.18 Port R (R0 to R3)
Port R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port R0 to R3 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PR0 to PR3 can also function as
SPI controller pin (SPCLK, SPCS , SPDO and SPDI).
Above setting is used the control register PRCR and function register PRFC.

Reset
Direction
control
(on bit basis)

Internal data bus

PRCR write
Function
control
(on bit basis)
PRFC write
PR0(SPDI)

R
Output latch
PR write
S B
Selector
PR read

A

SPDI input

Figure 3.7.49 Port R0

92CZ26A-161

TMP92CZ26A

Reset
Direction
control
(on bit basis)

Internal data bus

PRCR write
Function
control
(on bit basis)
PRFC write
S
A
Selector
B

R
Output latch
PR write
SPDO,
SPCS ,
SPCLK
PR read

PR1(SPDO),
PR2( SPCS ),
PR3(SPCLK)
S B
Selector
A

Figure 3.7.50 Port R1 to R3

92CZ26A-162

TMP92CZ26A

Port R register

7
PR
(0064H)

6

5

4

bit Symbol
Read/Write

3

2

1

0

PR3

PR2

PR1

PR0

R/W
Data from external port

After reset

(Output latch register is cleared to “0”)
Port R control register

7
PRCR
(0066H)

6

5

4

bit Symbol
Read/Write
After reset
Function

3

2

1

0

PR3C

PR2C

PR1C

PR0C

W
0
0
0: Input, 1: Output

0

0

Port R function register

7
PRFC
(0067H)

6

5

4

bit Symbol
Read/Write
After reset

3

2

1

0

PR3F

PR2F

PR1F

PR0F

0

0

W
0: Port
1: SPCLK

Function
PR1 setting

0: Port
1: SPDI



0

1



0

1

Input port
SPDI input

Output port
(Reserved)



Input port
Output port
(Reserved) SPDO output

0
1

0
1

PR3setting

PR2 setting





0

1



1

0

0: Port
1: SPDO

PR0 setting



0

0

0: Port
1: SPCS

0

1

Input port
(Reserved)

Output port
SPCS Output



Input port
(Reserved)

Output port
SPCLK
output

0
1

Port R drive register

7
PRDR
(0099H)

6

5

4

bit Symbol

3

2

1

0

PR3D

PR2D

PR1D

PR0D

1

1

1

1

Read/Write

R/W

After reset

Input/Output buffer drive register
for standby mode

Function

Note: Read-Modify-Write is prohibited for the registers PRCR, PRFC.

Figure 3.7.51 Register for Port R

92CZ26A-163

TMP92CZ26A
3.7.19 Port T (PT0 to PT7)
Port T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port T0 to T7 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PT0 to PT7 can also function as
data bus pin for LCD controller (LD8 to LD15).
Above setting is used the control register PTCR and function register PTFC.
Reset
Direction
control
(on bit basis)

Internal data bus

PTCR write
Function
control
(on bit basis)
PTFC write
S
Output latch
PT write
LD8 to LD15

A

S

Selector
B

S B
Selector
PT read

A

Figure 3.7.52 Port T0 to T7

92CZ26A-164

PT0 to PT7
(LD8 to LD15)

TMP92CZ26A

Port T register

bit Symbol
PT
(00A0H) Read/Write

7

6

5

4

3

2

1

0

PT7

PT6

PT5

PT4

PT3

PT2

PT1

PT0

R/W
Data from external port (Output latch register is cleared to “0”)

After reset

Port T control register

PTCR
(00A2H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PT7C

PT6C

PT5C

PT4C

PT3C

PT2C

PT1C

PT0C

0

0

0

0

0

0

W
0
0
0: Input 1: Output

Port T function register

PTFC
(00A3H)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PT7F

PT6F

PT5F

PT4F

PT3F

PT2F

PT1F

PT0F

0

0

0

0

0
0: Port

W
0
0
0
1: Data bus for LCDC (LD15 to LD8)

Port T drive register

bit Symbol
PTDR
(009BH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PT7D

PT6D

PT5D

PT4D

PT3D

PT2D

PT1D

PT0D

1

1

1

1

1

1

1

1

R/W

Input/Output buffer drive register for standby mode

Note1: Read-Modify-Write is prohibited for the registers PTCR, PTFC.
Note2: When PT is used as LD15 to LD8, set applicable PTnC to”1”.

Figure 3.7.53 Register for Port T

92CZ26A-165

TMP92CZ26A
3.7.20 Port U (PU0 to PU7)
Port U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port U0 to U7 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PU0 to PU7 can also function as
data bus pin for LCD controller (LD16 to LD23) and SDCLK input function.
Above setting is used the control register PUCR and function register PUFC.
In addition to functioning as above function, PU7 can also function as communication for
debug mode (EO_TRGOUT). These functions are operated when it is started in debug
mode. In this case, PU7 can not be used as LD23 function.

Reset

Debug mode

Direction
control
(on bit basis)

Internal data bus

PUCR write
Function
control
(on bit basis)
PUFC write
R
Output latch
PU write
LD16 to LD20, LD22,LD23
EO_TRGOUT

A

S

Selector
B
C

S B
Selector
PU read

A

Figure 3.7.54 Port U0 to U4 , U6 , U7

92CZ26A-166

PU0~PU4,PU6
(LD16 to LD20,LD22)
PU7
(LD23,EO_TRGOUT)

TMP92CZ26A

Reset
Direction
control
(on bit basis)
PUCR wirte

Internal data bus

Function
control
(on bit basis)
PUFC write
R
Output latch

A S
Selector
B

PU write
LD21

S B
Selector
PU read

A

Figure 3.7.55 Port U5

92CZ26A-167

PU5 (LD21)

TMP92CZ26A

Port U register
PU
(00A4H)

Bit Symbol
Read/Write
After reset

7

6

5

4

3

2

1

0

PU7

PU6

PU5

PU4

PU3

PU2

PU1

PU0

R/W
Data from external port (Output latch register is cleared to “0”)
Port U control register

PUCR
(00A6H)

Bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PU7C

PU6C

PU5C

PU4C

PU3C

PU2C

PU1C

PU0C

0

0

0

0

0

0

W
0
0
0: Input 1: Output

Port U function register

PUFC
(00A7H)

Bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PU7F

PU6F

PU5F

PU4F

PU3F

PU2F

PU1F

PU0F

0
0: Port
1: LD23

0
0: Port
1: LD22

0
0: Port
1: LD19

0
0: Port
1: LD18

0
0: Port
1: LD17

W
0
0: Port
1:
LD21@
=1

0
0: Port
1: LD20

0
0: Port
1: LD16

Note: When PU is used as LD23 to LD16, set applicable PUnC to “1”.
Port U drive register

PUDR
(009CH)

Bit Symbol

7

6

5

4

3

2

1

0

PU7D

PU6D

PU5D

PU4D

PU3D

PU2D

PU1D

PU0D

1

1

1

1

1

1

1

1

Read/Write
After reset
Function

R/W

Input/Output buffer drive register for standby mode

Note1: Read-Modify-Write is prohibited for the registers PUCR, PUFC.
Note2: When use PU as LD23 to LD16, set PUnC to “1”. When use PU5 as LD21, set PU5C to “1”.

Figure 3.7.56 Register for Port U

92CZ26A-168

TMP92CZ26A
3.7.21 Port V (PV0 to PV4, PV6, PV7)
Port V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set
individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and
output latch to “0”. In addition to functioning as general-purpose I/O port pins, PV can also
function as input or output pin for SBI (SDA, SCL) and output for SIO(SCLK0) (Note).
Above setting is used the control register PVCR and function register PVFC.
Port V3 and V4 are 2-bit general-purpose output ports. Resetting clear port V3 and V4 to
output latch to “0”.
Reset

Direction control
(on bit basis)

Internal data bus

PVCR write

Function control
(on bit basis)
PVFC write
R
Output latch

PV write

A

PV0 (SCLK0)
PV1
PV2

S

Selector
B

SCLK0 出力
B
Selector
A
PV read

Note: SIO function support function that input clock from SCLK0, basically. However, if setting to PV0 pin, this function supports only
the output function.

Figure 3.7.57 Port V0 to V2

92CZ26A-169

TMP92CZ26A

Internal data bus

Reset

R
Output latch

PV3
PV4

PV write
PV read

Figure 3.7.58 Port V3, V4

Reset
Direction
control
(on bit basis)

Internal data bus

PVCR write
Function
control
(on bit basis)
PVFC write
A

R
Output latch

S
PV6(SDA)

Selector

PV write

Open-drain enable
PVFC2

B

SDA,SCL output

S B
Selector

PV read

A

SDA,SCL input

Figure 3.7.59 Port V6, V7

92CZ26A-170

PV7(SCL)

TMP92CZ26A

Port V register

PV
(00A8H)

bit Symbol
Read/Write
After reset

7

6

PV7

PV6

5

4

3

2

1

0

PV4

PV3

PV2
R/W

PV1

PV0

R/W
Data from external port

Data from external port

(Output latch register is
cleared to “0”)

(Output latch register is cleared to “0”)
Port V control register

PVCR
(00AAH)

bit Symbol
Read/Write
After reset
Function

7

6

PV7C

PV6C

5

4

3

2
PV2C

0
0
0: Input 1: Output

0

1

0

PV1C
PV0C
W
0
0
0: Input 1: Output

Port V function register

PVFC
(00ABH)

bit Symbol
Read/Write
After reset
Function

7

6

PV7F

PV6F

5



0

1



Reserved

0



1



1

PV0 setting

PV1 setting

0
Input port

2

PV1F
PV0F
W
0
0
0
Refer to following table

W
0
0
Refer to following table



1

3

PV2F

PV2 setting

0

4

Output port

Input port

0

Reserved

0

1

Input port
Reserved

SCLK0 output



Reserved

1

Output port

0

Reserved

1

Output port

Note: SCLK0 is only output.
PV7 setting

PV6 setting





0

1


0
1

0

1
Output port



Input port
Reserved

Output port

0

SCL I/O

1

Input port
Reserved

3

2

1

4

3

2

PV4D

PV3D

SDA I/O

Port V function register 2

PVFC2
(00A9H)

7

6

bit Symbol
Read/Write
After reset

PV7F2
W
0

PV6F2
W
0

Function

0:CMOS
1:Open
-drain

0:CMOS
1:Open
-drain

5

4

0

Port V drive register

PVDR
(009DH)

bit Symbol
Read/Write
After reset
Function

7

6

PV7D

PV6D
R/W

1

1

5

PV2D
R/W
1
1
1
Input/Output buffer drive register for standby mode

Note: Read-Modify-Write is prohibited for the registers PVCR, PVFC and PVFC2.

Figure 3.7.60 Register for Port V

92CZ26A-171

1

0

PV1D

PV0D

1

1

TMP92CZ26A
3.7.22 Port W (PW0 to PW7)
Port W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port W0 to W7 to input port and output latch to “0”.
Above setting is used the control register PWCR and function register PWFC.

Reset
Direction
control
(on bit basis)

Internal data bus

PWCR write
Function
control
(on bit basis)
PWFC write
PW0 to PW7

R
Output latch
PW write
S B
Selector
PW read

A

Figure 3.7.61 Port W0 to W7

92CZ26A-172

TMP92CZ26A

Port W register

bit Symbol
PW
(00ACH) Read/Write

7

6

5

4

3

2

1

0

PW7

PW6

PW5

PW4

PW3

PW2

PW1

PW0

R/W
Data from external port (Output latch register is cleared to “0”)

After reset

Port W control register

PWCR
(00AEH)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PW7C

PW6C

PW5C

PW4C

PW3C

PW2C

PW1C

PW0C

0

0

0

0

0

0

W
0
0
0: Input 1: Output

Port W function register

PWFC
(00AFH)

bit Symbol
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PW7F

PW6F

PW5F

PW4F

PW3F

PW2F

PW1F

PW0F

0

0

0

0

0

0

W
0
0: Port

0
1: Reserved

Port W drive register

7

6

5

4

3

2

1

0

bit Symbol

PW7D

PW6D

PW5D

PW4D

PW3D

PW2D

PW1D

PW0D

After reset

1

1

1

1

1

1

1

1

PWDR
(009EH) Read/Write
Function

R/W

Input/Output buffer drive register for standby mode

Note1: Read-Modify-Write is prohibited for the registers PWCR, PWFC.

Figure 3.7.62 Register for Port W

92CZ26A-173

TMP92CZ26A
3.7.23 Port X (PX4, PX5 and PX7)
Port X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port X5 and X7 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PX5 and PX7 can also function as
USB clock input pin (X1USB).
Above setting is used the control register PXCR and function register PXFC.
Port X4 is 1-bit general-purpose output port. Resetting sets output latch to “0”. In
addition to functioning as general-purpose output port, PX4 can also function as system
clock output pin (CLKOUT) and output pin (LDIV). This setting is used the PX register
and function register PXFC.

Internal data bus

Reset
Function
control
(on bit basis)
PXFC write
R
Output latch
A
PX write

S

Selector
B

PX read
CLKOUT output

A

S

Selector
LDIV output

B

Figure 3.7.63 Port X4

92CZ26A-174

PX4 (CLKOUT)
(LDIV)

TMP92CZ26A
Reset
Direction
control
(on bit basis)
PXCR write

Internal data bus

Function
control
(on bit basis)
PXFC write
PX5 (X1USB)
PX7

R
Output latch
PX write
S B
Selector
PX read

A

X1USB input

Figure 3.7.64 Port X5, X7

92CZ26A-175

TMP92CZ26A

Port X register

7
bit Symbol
PX
(00B0H) Read/Write

6

PX7
R/W

5

4

PX5

PX4

3

2

1

0

3

2

1

0

3

2

1

0

3

2

1

0

R/W
Data from external port

After reset

(Output latch register is cleared to “0”)
Port W control register

7
bit Symbol
PXCR
(00B2H) Read/Write
After reset
Function

6

PX7C
W
0
0: Input
1: Output

5

4

PX5C
W
0
0: Input
1: Output
Port W function register

7
bit Symbol
PXFC
(00B3H) Read/Write
After reset

6

PX7F
W
0

5

4

PX5F

PX4F
W

0

0:Port
1: Reserved

0

0:Port
1:X1USB
input

Function

0:Port
1:CLKOUT
at  = 0
LDIV
at  = 1

Port W drive register

7
bit Symbol
PXDR
(009FH) Read/Write
After reset
Function

6

PXD7

5

4

PXD5

PXD4

R/W
1

R/W
1

1

Input/Output buffer drive register
for standby mode

Note: Read-Modify-Write is prohibited for the registers PWCR, PWFC.

Figure 3.7.65 Register for Port X

92CZ26A-176

TMP92CZ26A
3.7.24 Port Z (PZ0 to PZ7)
Port Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port Z0 to Z7 to input port and output latch to “0”.
In addition to functioning as general-purpose I/O port function, Port Z can also function
as

communication

for

debug

mode

(EI_PODDATA,

EI_SYNCLK,

EI_PODREQ,

EI_REFCLK, EI_TRGIN, EI_COMRESET, EO_MCUDATA and EO_MCUREQ). These
functions are operated when it is started in debug mode. (There is not Function register in
this port. When DBGE is set to “0”, this port set to debug communication function.)

Debug mode

Reset

Direction
control
(on bit basis)

Internal data bus

PZCR write

R
Output latch

PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3 (EI_REFCLK)
PZ4 (EI_TRGIN)
PZ5 (EI_COMRESET)

PZ write

S B
Selector
PZ read

A

EI_PODDATA
EI_SYNCLK
EI_PODREQ
EI_REFCLK
EI_TRGIN
EI_COMRESET

Figure 3.7.66 Port Z0 to Z5

92CZ26A-177

TMP92CZ26A

Reset

Debug mode
Direction
control
(on bit basis)

Internal data bus

PZCR write

R
Output latch

A

S
PZ6(EO_MCUDATA)
PZ7(EO_MCUREQ)

Selector
PZ write

B

EO_MCUDATA
EO_MCUREQ
S

B

Selector
PZ read

A

Figure 3.7.67 Port Z6 to Z7

92CZ26A-178

TMP92CZ26A

Port Z register

PZ
(0068H)

bit Symbol
Read/Write
After reset

7

6

5

4

3

2

1

0

PZ7

PZ6

PZ5

PZ4

PZ3

PZ2

PZ1

PZ0

R/W
Data from external port (Output latch register is cleared to “0”)
Port Z control register

bit Symbol
PZCR
(006AH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PZ7C

PZ6C

PZ5C

PZ4C

PZ3C

PZ2C

PZ1C

PZ0C

0

0

0

0

0

0

W
0
0
0: Input 1: Output
Port Z drive register

bit Symbol
PZDR
(009AH) Read/Write
After reset
Function

7

6

5

4

3

2

1

0

PZ7D

PZ6D

PZ5D

PZ4D

PZ3D

PZ2D

PZ1D

PZ0D

1

1

1

1

R/W
1
1
1
1
Input/Output buffer drive register for standby mode

Note: Read-Modify-Write is prohibited for the registers PZCR.

Figure 3.7.68 Register for Port Z

92CZ26A-179

TMP92CZ26A

3.8

Memory Controller (MEMC)
3.8.1

Functions

TMP92CZ26A has a memory controller with a variable 4-block address area that controls as
follows.
(1) 4-block address area support
Specifies a start address and a block size for 4-block address area (block0 to 3).
* SRAM or ROM

: All CS-blocks (CS0 to CS3) are supported.

* SDRAM

: Either CS1 or CS2-blocks is supported.

* Page-ROM

: Only CS2-blocks is supported.

* NAND-Flash

: CS setting is not needed. If using NAND-Flash, set
BROMCR to “1” as external area for avoiding
conflicting with other CS memory.

(2) Connecting memory specifications
Specifies SRAM, ROM, SDRAM as memories to connect with the selected address areas.
(3) Data bus width selection
Whether 8-bit or 16bit is selected as the data bus width of the respective block address areas.
(4) Wait control
Wait specification bit in the control register and WAIT input pin control the number of waits
in the external bus cycle. The number of waits of read cycle and write cycle can be specified
individually. The number of waits is controlled in 15 mode mentioned below.
0 to 10 wait, 12wait,
16 wait, 20 wait
4+N wait (controls with WAIT pin)

92CZ26A-180

TMP92CZ26A

3.8.2

Control register and Operation after reset release

This section describes the registers to control the memory controller, the state after reset
release and necessary settings.
(1) Control Register
The control registers of the memory controller are as follows and Table 3.8.1 to Table 3.8.2.
･ Control register: BnCSH/BnCSL(n=0 to 3, EX)
Sets the basic functions of the memory controller that is the connecting memory
type, the number of waits to be read and written.
･ Memory start address register: MSARn(n=0 to 3)
Sets a start address in the selected address areas.
･ Memory address mask register: MAMR (n=0 to 3)
Sets a block size in the selected address areas.
･ Page ROM control register: PMEMCR
Sets to control Page-ROM.
･ Adjust the timing of control signal register: CSTMGCR, WRTMGCR, RDTMGCRn
Adjust the timing of rising/falling edge of control signals.
･ Internal-Boot ROM control register: BROMCR
Sets to access Boot-ROM.

92CZ26A-181

TMP92CZ26A

Table 3.8.1 Control register
B0CSL
(0140H)

B0CSH
(0141H)

MAMR0
(0142H)

7

6

5

4

B0WW3

B0WW2

B0WW1

B0WW0

After Reset

0

0

1

0

0

0

1

0

Bit Symbol

B0E

B0REC

B0OM1

B0OM0

B0BUS1

B0BUS0

Read/Write

R/W

Bit symbol
Read/Write

B1CSH
(0145H)

MAMR1
(0146H)

MSAR1
(0147H)

After Reset

0

Bit Symbol

M0V20

M0V19

M0V18

M0V17

0

After Reset

1

1

1

1

B2CSH
(0149H)

Bit Symbol

M0S23

M0S22

M0S21

M0S20

MSAR2
(014BH)

B3CSL
(014CH)

B3CSH
(014DH)

MAMR3
(014EH)

MSAR3
(014FH)

0

0

0

0

M0V16

M0V15

M0V14-V9

M0V8

1

1

1

1

M0S19

M0S18

M0S17

M0S16

R/W

After Reset

1

1

1

1

1

1

1

1

Bit symbol

B1WW3

B1WW2

B1WW1

B1WW0

B1WR3

B1WR2

B1WR1

B1WR0

After Reset

0

0

1

0

0

0

1

0

Bit Symbol

B1E

B1REC

B1OM1

B1OM0

B1BUS1

B1BUS0

Read/Write

R/W

Read/Write

R/W

R/W

After Reset

0

Bit Symbol

M1V21

M1V20

M1V19

M1V18

0

After Reset

1

1

1

1

Bit Symbol

M1S23

M1S22

M1S21

M1S20

Read/Write

0

0

0

0

M1V17

M1V16

M1V15-V9

M1V8

1

1

1

1

M1S19

M1S18

M1S17

M1S16

R/W

R/W

After Reset

1

1

1

1

1

1

1

1

Bit symbol

B2WW3

B2WW2

B2WW1

B2WW0

B2WR3

B2WR2

B2WR1

B2WR0

After Reset

0

0

1

0

0

0

1

0

Bit Symbol

B2E

B2M

B2REC

B2OM1

B2OM0

B2BUS1

B2BUS0

Read/Write

R/W

Read/Write
MAMR2
(014AH)

0
B0WR0

R/W

Read/Write
B2CSL
(0148H)

1
B0WR1

R/W

Read/Write
B1CSL
(0144H)

2
B0WR2

R/W

Read/Write
MSAR0
(0143H)

3
B0WR3

R/W

R/W

After Reset

1

0

Bit Symbol

M2V22

M2V21

M2V20

M2V19

0

After Reset

1

1

1

1

Bit Symbol

M2S23

M2S22

M2S21

M2S20

Read/Write

0

0

0

0

M2V18

M2V17

M2V16

M2V15

1

1

1

1

M2S19

M2S18

M2S17

M2S16

R/W

Read/Write

R/W

After Reset

1

1

1

1

1

1

1

1

Bit symbol

B3WW3

B3WW2

B3WW1

B3WW0

B3WR3

B3WR2

B3WR1

B3WR0

After Reset

0

0

1

0

0

0

1

0

Bit Symbol

B3E

B3REC

B3OM1

B3OM0

B3BUS1

B3BUS0

Read/Write

R/W

Read/Write

R/W

R/W

After Reset

0

Bit Symbol

M3V22

M3V21

M3V20

M3V19

0

After Reset

1

1

1

1

Bit Symbol

M3S23

M3S22

M3S21

M3S20

Read/Write

0

0

0

M3V17

M3V16

M3V15

1

1

1

1

M3S19

M3S18

M3S17

M3S16

1

1

1

1

R/W

Read/Write
After Reset

0
M3V18

R/W
1

1

1

1

92CZ26A-182

TMP92CZ26A

Table 3.8.2 Control register
BEXCSL
(0159H)

Bit Symbol

6

5

4

BEXWW3

BEXWW2

BEXWW1

BEXWW0

Read/Write
After Reset

BEXCSH
(0158H)

7

3

2

1

0

BEXWR3

BEXWR2

BEXWR1

BEXWR0

R/W
0

0

1

Bit Symbol

0

0

0

1

0

BEXREC

BEXOM1

BEXOM0

BEXBUS1

BEXBUS0

Read/Write
PMEMCR
(0166H)

CSTMGCR
(0168H)

R/W

After Reset

0

0

0

0

0

Bit Symbol

OPGE

OPWR1

OPWR0

PR1

PR0

Read/Write

R/W

After Reset

0

0

1

0

TAC1

TAC0

Bit Symbol

TACSEL1

Read/Write
WRTMGCR
(0169H)

0

0

TCWSEL1

TCWSEL0

0
TCWS1

R/W
0
B1TCRS1

Read/Write

B1TCRS0

B1TCRH1

R/W

TCWS0
R/W

0

0

B1TCRH0

B0TCRS1

R/W

0

TCWH1

TCWH0
R/W

0

0

B0TCRS0

B0TCRH1

R/W

0
B0TCRH0

R/W

After Reset

0

0

0

0

0

0

0

0

Bit Symbol

B3TCRS1

B3TCRS0

B3TCRH1

B3TCRH0

B2TCRS1

B2TCRS0

B2TCRH1

B2TCRH0

Read/Write
After Reset
BROMCR
(016CH)

R/W

After Reset

After Reset

RDTMGCR1
(016BH)

TACSEL0

Bit Symbol

Bit Symbol

R/W

R/W

Read/Write
RDTMGCR0
(016AH)

R/W
0

R/W
0

R/W
0

0

R/W
0

Bit Symbol

0

R/W
0

0

0

CSDIS

ROMLESS

VACE

Read/Write

R/W

After Reset

1

0/1

1/0

RAMCR

Bit Symbol

-

(016DH)

Read/Write

R/W

After Reset

Always
write “1”

92CZ26A-183

TMP92CZ26A

(2) Operation after releasing reset
The data bus width at starting is determined depending on state of AM1/AM0 pins after
releasing reset. Then, the external memory access as follows;
AM1
0
0
1
1

AM0
0
1
0
1

Start Mode
Don’t use this setting
Start with 16-bit data bus (note)
Don’t use this setting
Start with BOOT(32-bit internal-MROM )

Note: A memory to be used to start after releasing reset is either NOR-Flash or Masked-ROM.NAND-Flash,
SDRAM can’t be used.

AM1/AM0 pins are valid only just after releasing reset. In other cases, the data bus width
is the value set in the control register .
After reset, only control register (B2CSH/B2CSL) of the block address area 2 is effective
automatically. (B2CSH is set to “1” by reset).
The data bus width which is specified by AM1/AM0 pin is loaded to the bit to specify the
bus width of the control register in the block address area 2.
The block address area 2 is set to address 000000H to FFFFFFH by reset
(B2CSH is reset to “0”) .
After releasing reset, the block address areas are specified by MSARn and MAMRn.
Then, set BnCS.
Set BnCSH to “1” in order to enable the setting.

92CZ26A-184

TMP92CZ26A

3.8.3 Basic functions and register setting
In this section, setting of the block address area, the connecting memory and the number
of waits out of the memory controller’s functions are described.
(1) Block address area specification
The block address areas of CS0 to CS3 are specified by MSAR0 to MSAR3 and MAMR0 to
MAMR3.
(a) Memory start address register
Figure 3.8.1 shows the memory start address registers. MSAR0 to MSAR3 set the start
addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of the start
address in . The lower 16 bits of the start address (A15 to A0) are permanently set
to 0. Accordingly, the start address can only be set in 64-Kbyte increments, starting from
000000H. Figure 3.8.2 shows the relationship between the start address and the start
address register value.

Memory Start Address Registers (for areas CS0 to CS3)
7
6
5
4
3
2
MSAR0
(0143H)

MSAR1
(0147H)

Bit symbol

MSAR2
(014BH)

MSAR3
(014FH)

After reset

S23

S22

S21

S20

Read/Write

1

0

S19

S18

S17

S16

1

1

1

1

R/W
1

1

1

Function

1

Determines A23 to A16 of start address
Sets start addresses for areas CS0 to CS3

Figure 3.8.1 Memory Start Address Register

Start Address
Address
000000H

64KByte

Value in start address register (MSAR0 to MSAR3)

000000H .................... 00H
010000H .................... 01H
020000H .................... 02H
030000H .................... 03H
040000H .................... 04H
050000H .................... 05H
060000H .................... 06H
to

to

FF0000H ................... FFH
FFFFFFH

Figure 3.8.2 Relationship between Start Address and Start Address Register Value

92CZ26A-185

TMP92CZ26A
(b) Memory address mask registers
Figure 3.8.3 shows the memory address mask registers. MAMR0 to MAMR3 are used to
set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set
in MAMR0 to MAMR3. The compare operation used to determine if an address is in the
CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in
these registers.
Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to
CS3 areas.
Block address area CS0 : A20 to A8
Block address area CS1 : A21 to A8
Block address area CS2 to CS3 : A22 to A15
Accordingly, the size that can be each area is different.
Note: After releasing reset, only the control register of the block address area 2 is valid. The control register of
the block address area 2 has  bit. Setting  bit to “0” sets the block address area 2 to
addresses 000000H to FFFFFFH. Setting  bit to “1” specifies the start address and the address
area size as it is in the other block address area.

Memory Address Mask Register ( for CS0 area)
7
6
5
4
3
MAMR0
(0142H)

Bit symbol

V20

V19

V18

V17

1

1

1

1

Read/Write
After reset

2

1

0

V16

V15

V14∼9

V8

1

1

1

1

R/W

Function

Sets size of CS0 area 0: Used for address compare

Range of possible settings for CS0 area size: 256Bytes to 2MBytes

Memory Address Mask Register ( for CS1 area)
7
6
5
4
3
MAMR1
(0146H)

Bit symbol

V21

V20

V19

V18

1

1

1

1

Read/Write
After reset

2

1

0

V17

V16

V15∼9

V8

1

1

1

1

R/W

Function

Sets size of CS1 area 0: Used for address compare

Range of possible settings for CS1 area size: 256Bytes to 4MBytes

Memory Address Mask Register ( for CS2,CS3 area)
7
6
5
4
3
MAMR2
(014AH)

MSAR3
(014FH)

Bit symbol

V22

V21

V20

V19

Read/Write
After reset
Function

2

1

0

V18

V17

V16

V15

1

1

1

1

R/W
1

1

1

1

Sets size of CS2 or CS3 area 0: Used for address compare

Range of possible settings for CS2 or CS3 area size: 32KBytes to 8MBytes

Figure 3.8.3 Memory Address Mask Registers

92CZ26A-186

TMP92CZ26A

(c) Setting memory start addresses and address areas
An example of specifying a 64-Kbyte address area starting from 010000H using the CS0
areas i describes.
Set 01H in MSAR0 (Corresponding to the upper 8 bits of the start address).
Next, calculate the difference between the start address and the anticipated end address
(01FFFFH) based on the size of the CS0 area. Bits 20 to 8 of the result correspond to the
mask value to be set for the CS0 area. Setting this value in MAMR0 sets the area
size. This example sets 07H in MAMR0 to specify a 64K-byte area.

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

F

1

1

1

1

F

1

1

1

1

F

1

1
H

F

Memory
end
address
CS0 area
size
(64 Kbytes)

S23 S22 S21 S20 S19 S18 S17 S16

MSAR0

0

0

0

0

0

0

0

0

Memory
start
address

1

1

H

V20 V19 V18 V17 V16 V15

MSMR0 0

0

0

0

0

0

0

0

1

V14 to V9

1

1

0

1
7

1

V8

1

1

1

1

1

1

H

1

1

1

1

1

Memory address
mask register
setting

Setting of 07H specifies a 64-Kbyte area.

(d) Address area size specification
Table 3.8.3 shows the relationship between CS area and area size. “Δ” indicates areas
that cannot be set by memory start address register and address mask register
combinations. When setting an area size using a combination indicated by “Δ”, set the start
address mask register in the desired steps starting from 000000H.
If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area
number has the higher priority.
Example: To set the area size for CS0 to 128 Kbytes:
a. Valid start addresses
000000H
020000H

128 Kbytes
128 Kbytes

Any of these addresses may be set as the start address.

040000H
060000H
:

128 Kbytes

b. Invalid start addresses
000000H
010000H

64 Kbytes
128 Kbytes

030000H
050000H
:

This is not an integer multiple of the desired area size setting.
Hence, none of these addresses can be set as the start address.

128 Kbytes

92CZ26A-187

TMP92CZ26A

Table 3.8.3 Valid Area Sizes for Each CS Area
Size
(Byte)

256

512

32 K

64 K

128 K

256 K

512 K

1M

2M

4M

8M

○
○

○
○

○

○
○
○
○

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

Δ

CS area

CS0
CS1
CS2
CS3

○
○

Note:“Δ” indicates areas that cannot be set by memory start address register and address mask
register combinations.

(e) Block address area Priority
When the set block address area overlaps with the built-in memory area, or both two
address areas overlap, the block address area is processed according to priority as follows.

Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3

(f) Wait control for outside the block address area of CS0 to CS3
Also, that any accessed areas outside the address spaces set by CS0 to CS3 are processed
as the CSEX space. Therefore, settings of CSEX (BEXCSH, L-register) apply for the control
of wait cycles, data bus width, etc,.

92CZ26A-188

TMP92CZ26A

(2) Connection Memory Specification
Setting BnCSH specifies the memory type to be connected with the block
address areas. The interface signal is output according to the set memory as follows;
BnCSH
BnOM1

BnOM0

Function

0

0

SRAM/ROM (Default)

0

1

(Reserved)

1

0

(Reserved)

1

1

SDRAM

Note1: SDRAM should be set only with CS1 or CS2 .

(3) Data Bus Width Specification
The data bus width is set for every block address area. The bus size is set by
BnCSH as follows;
BnCSH
 

Function

0

0

8-bit bus mode (Default)

0

1

16-bit bus mode

1

0

Reserved

1

1

Don’t use this setting

Note1: SDRAM should be set to “01”(16-bit bus).

This way of changing the data bus width depending on the address being accessed is
called “dynamic bus sizing”. The part where the data is output to is depended on the data
width, the bus width and the start address.
The number of external data bus pin in TMP92CZ26A are 16 pin. Therefore, please
ignore the bus width of memory = 32 bit in the table.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus
width are put in consecutive address, do not execute a access to both memories with one command.

92CZ26A-189

TMP92CZ26A
Operand Data
Size (bit)

Operand Start

Bus width of Mem ory

Address

(bit)

4n + 0

8/16/32
8
16/32
8/16
32
8
16
32

4n + 1
8

4n + 2
4n + 3

4n + 0

8
16/32
8

4n + 1

16
32

16

CPU Data
CPU Address

8
4n + 2

16
32
8

4n + 3

16
32

8
4n + 0
16
32

8
4n + 1
16

32
32
8
4n + 2
16
32

8
4n + 3
16

32

4n + 0
4n + 1
4n + 1
4n + 2
4n + 2
4n + 3
4n + 3
4n + 3
(1) 4n + 0
(2) 4n + 1
4n + 0
(1) 4n + 1
(2) 4n + 2
(1) 4n + 1
(2) 4n + 2
4n + 1
(1) 4n + 2
(2) 4n + 1
4n + 2
4n + 2
(1) 4n + 3
(2) 4n + 4
(1) 4n + 3
(2) 4n + 4
(1) 4n + 3
(2) 4n + 4
(1) 4n + 0
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
(1) 4n + 0
(2) 4n + 2
4n + 0
(1) 4n + 0
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
(1) 4n + 1
(2) 4n + 2
(3) 4n + 4
(1) 4n + 1
(2) 4n + 4
(1) 4n + 2
(2) 4n + 3
(3) 4n + 4
(4) 4n + 5
(1) 4n + 2
(2) 4n + 4
(1) 4n + 2
(2) 4n + 4
(1) 4n + 3
(2) 4n + 4
(3) 4n + 5
(4) 4n + 6
(1) 4n + 3
(2) 4n + 4
(3) 4n + 6
(1) 4n + 3
(2) 4n + 4

D31 to D24 D23 to D16

D15 to D8

D7 to D0

xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b31 to b24
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b23 to b16
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx

xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
b7 to b0
xxxxx
b7 to b0
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
b31 to b24
b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b23 to b16
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
b31 to b24
xxxxx
b31 to b24
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b23 to b16
xxxxx
xxxxx
b23 to b16

b7 to b0
b7 to b0
xxxxx
b7 to b0
xxxxx
b7 to b0
xxxxx
xxxxx
b7 to b0
b15 to b8
b7 to b0
b7 to b0
b15 to b8
xxxxx
b15 to b8
xxxxx
b7 to b0
b15 to b8
b7 to b0
xxxxx
b7 to b0
b15 to b8
xxxxx
b15 to b8
xxxxx
b15 to b8
b7 to b0
b15 to b8
b23 to b16
b31 to b24
b7 to b0
b23 to b16
b7 to b0
b7 to b0
b15 to b8
b23 to b16
b31 to b24
xxxxx
b15 to b8
b31 to b24
xxxxx
b31 to b24
b7 to b0
b15 to b8
b23 to b16
b31 to b24
b7 to b0
b23 to b16
xxxxx
b23 to b16
b7 to b0
b15 to b8
b23 to b16
b31 to b24
xxxxx
b15 to b8
b31 to b24
xxxxx
b15 to b8

xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b23 to b16
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b31 to b24

xxxxx: During read, input data to the bus is ignored. At write, the bus is high impedance and the write
strobe signal remains no-active.

92CZ26A-190

TMP92CZ26A
(4) Wait control
The external bus cycle completes for two states minimum(25 ns at fSYS = 80 MHz).
Setting the BnCSL specifies the number of waits in the write cycle, and
BnCSL specifies the number of waits in the read cycle.  is set with
the same method as  as follows;
BnCSL/
















0

0

0

1

2 states (0 waits) access fixed mode

0

0

1

0

3 states (1 wait) access fixed mode (Default)

0

1

0

1

4 states (2 waits) access fixed mode

0

1

1

0

5 states (3 waits) access fixed mode

0

1

1

1

6 states (4 waits) access fixed mode

1

0

0

0

7 states (5 waits) access fixed mode

1

0

0

1

8 states (6 waits) access fixed mode

1

0

1

0

9 states (7 waits) access fixed mode

1

0

1

1

10 states (8 waits) access fixed mode

1

1

0

0

11 states (9 waits) access fixed mode

1

1

0

1

12 states (10 waits) access fixed mode

1

1

1

0

14 states (12 waits) access fixed mode

1

1

1

1

18 states (16 waits) access fixed mode

0

1

0

0

22 states (20 waits) access fixed mode

0

0

1

1

6 states +

others

Function

WAIT

pin input mode

(Reserved)

Note 1:For SDRAM, above setting is ineffective. Refer to the section 3.18 SDRAM controller.
Note 2:For NAND flash, this setting is ineffective.

(i) Waits number fixed mode
The bus cycle is completed with the set states. The number of states is selected from 2
states (0 waits) to 12 states (10 waits), 14 states(12 waits), 18 states(16 waits) and 22
states(20 waits).
(ii) WAIT pin input mode
This mode samples the WAIT input pins. It continuously samples the WAIT pin state
and inserts a wait if the pin is active. The bus cycle is minimum 6 states. The bus cycle is
completed when the wait signal is non active (“High” level) at 6 states. The bus cycle is
extended as long as the wait signal is active in case more than 6 states.

92CZ26A-191

TMP92CZ26A

(5) Recovery (Data hold) cycle control
Some memory have an AC specification about data hold time from CE or OE for read
cycle and a data confliction problem may occur. To avoid this problem, 1-dummy cycle can
be inserted after CSm-block access cycle by setting “1” to BmCSH register.
This 1-dummy cycle is inserted when the next cycle is for another CS-block.
BnCSH
0

No dummy cycle is inserted (Default).

1

Dummy cycle is inserted.

When not inserting a dummy cycle (0 waits)
SDCLK
A23 to A0
CSm

CSn
RD

When inserting a dummy cycle (0 waits)
Dummy
SDCLK
A23 to A0
CSm

CSn
RD

92CZ26A-192

TMP92CZ26A

(6) Adjust Function for the timing of control signal
This function can change the timing of CSn , CSZx , CSXx ,R/ W , RD , WRxx , SRWR and SRxxB
signals and adjust the timing according to the set-up/hold time of the memories.
As for the CSn , CSZx , CSXx ,R/ W and WRxx , SRWR , SRxxB (at write cycle), it can be changed
for only 1 CS area. While for RD and SRxxB (at read cycle), it can be changed for all CS
areas. As for CS area and EX area which is not set this function, it operates with base bus
timing (Refer to (7)).
This can not be used together with BnCSH function.
For control signal of SDRAM, it can be adjusted in SDRAM controller.
CSTMGCR, WRTMGCR
00

Change the timing of CS0 area

01

Change the timing of CS1 area

10

Change the timing of CS2 area

11

Change the timing of CS3 area

CSTMGCR
00

TAC = 0 × fSYS (Default)

01

TAC = 1 × fSYS

10

TAC = 2 × fSYS

11

(Reserved)

TAC:The delay from (A23-0) to (CSn, CSZx, CSXx, R/W).

WRTMGCR
00

TCWS/H = 0.5 × fSYS (Default)

01

TCWS/H = 1.5 × fSYS

10

TCWS/H = 2.5 × fSYS

11

TCWS/H = 3.5 × fSYS

TCWS:The delay from (CSn) to (WRxx,SRWR,SRxxB).
TCWH:The delay from (WRxx,SRWR,SRxxB) to (CSn).

RDTMGCR0/1
00

TCRH = 0 × fSYS (Default)

01

TCRH = 1 × fSYS

10

TCRH = 2 × fSYS

11

TCRH = 3 × fSYS

TCRH:The delay from (RD,SRxxB) to (CSn).

92CZ26A-193

TMP92CZ26A

RDTMGCR0/1
00

TCRS = 0.5 × fSYS (Default)

01

TCRS = 1.5 × fSYS

10

TCRS = 2.5 × fSYS

11

TCRS = 3.5 × fSYS

TCRS:The delay from (CSn) to (RD,SRxxB).

T1

T2

T3

TW

Tn-2

Tn-1

Tn

SDCLK
(80MHz)
A23 to 0

CSn
R/ W

TAC
TAC

RD
Read

cycle

SRxxB

TCRS

TCRH
Input

D15 to 0

WRxx
Write

cycle

SRWR

TCWH

TCWS

SRxxB
D15 to 0

Output
TCWS

Note: TW cycle is inserted by setting BnCSL register. If it is set to 0-Wait, TW cycle is not inserted.

92CZ26A-194

Output

TMP92CZ26A

(7) Basic bus timing
(a) External read/write cycle (0 waits)

SDCLK
(60 MHz)

T1

T2

CSn

A23 to A0
RD , SRxxB

Read
D15 to D0

Input

SRWR , SRxxB

Write

WRxx

D15 to D0

Output

(b) External read/write cycle (1 wait)
SDCLK
(60 MHz)

T1

TW

T2

CSn

A23 to A0

RD , SRxxB

Read
D15 to D0

Input

SRWR , SRxxB

Write

WRxx

D15 to D0

Output

92CZ26A-195

TMP92CZ26A

(c) External read bus cycle (1 wait + TAC: 1fSYS + TCRS: 1.5fSYS + TCRH: 1fSYS)
External write bus cycle (1 wait + TAC: 1fSYS + TCWS/H: 1.5fSYS)
T1

T2

T3

T4

T6

T5

SDCLK
(80 MHz)
CSn

TAC

TAC

A23 to 0

RD SRxxB

TCRS

TCRH

D15 to 0

Read

Input

SRWR , SRxxB

TCWS

TCWH

Write

WRxx

TCWS

TCWH

D15 to 0

Output

WAIT

(d) External read/write cycle (4 waits + WAIT pin input mode)
T1

T2

T3

T4

T5

T6

SDCLK
(80 MHz)
CSn
A23 to 0

RD SRxxB

Read
D15 to 0

Input

SRWR , SRxxB

Write

WRxx

D15 to 0

Output

WAIT

Sampling

92CZ26A-196

TMP92CZ26A

(e) External read/write cycle (4 waits + WAIT pin input mode)
T1

T2

T3

T4

T5

T6

TW

SDCLK
(80 MHz)
CSn
A23 to 0

RD SRxxB

Read
D15 to 0

Input

SRWR , SRxxB
Write

WRxx

D15 to 0

Output

WAIT
Sampling

(f)

Sampling

External read bus cycle (4 waits + WAIT pin input mode +TAC: 1fSYS + TCRS: 1.5fSYS
+ TCRH: 1fSYS)
External write bus cycle (4 waits + WAIT pin input mode + TAC: 1fSYS
+ TCWS/H: 1.5fSYS)
T1

T2

T3

T4∼T7

TW

T8

T9

T10

SDCLK
(80 MHz)
CSn
A23 to 0

RD SRxxB

Read
D15 to 0

Input

SRWR , SRxxB
WRxx

Write
TCWS

D15 to 0

Output
TCWS

WAIT
Sampling

Sampling

92CZ26A-197

TMP92CZ26A

(8) Connecting to external memory
Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR
flash to the TMP92CZ26A.
TMP92CZ26A

16-bit SRAM

RD

OE

SRLLB

LDS

SRLUB

UDS

SRWR

R/W

CS0

D [15:0]

CE

Not connect

I/O [16:1]

A0
A1

A0

A2

A1

A3

A2

16-bit NOR flash
OE
WE
CS2

CE

DQ [15:0]
A0
A1
A2

Figure 3.8.4 Example of External 16-Bit SRAM and NOR Flash Connection

92CZ26A-198

TMP92CZ26A

3.8.4 ROM Page mode Access Control
This section describes ROM page mode accessing and how to set registers. ROM page mode
is set by PMEMCR.
(1)

Operation and how to set the registers
TMP92CZ26A supports ROM access with the page mode. The ROM access with the page
mode is specified only in CS2.
Setting PMEMCR to “1” sets the memory access of CS2 to ROM page mode access.
The number of read cycles is set by the PMEMCR.
PMEMCR
 

Number of Cycle in a Page

0

0

1 state (n-1-1-1 mode) (n ≥ 2)

0

1

2 state (n-2-2-2 mode) (n ≥ 3)

1

0

3 state (n-3-3-3 mode) (n ≥ 4)

1

1

4 state (n-4-4-4 mode) (n ≥ 5)

Note: Set the number of waits “n” to the control register (BnCSL) in each block address area.

The page size (the number of bytes) of ROM in the CPU size is set to PMEMCR.
When data is read out until a border of the set page, the controller completes the page reading
operation. The start data of the next page is read in the normal cycle. The following data is set
to page read again.
PMEMCR




ROM Page Size

0

0

64 bytes

0

1

32 bytes

1

0

16 bytes (Default)

1

1

8 bytes

SDCLK
tCYC
A2~A23

+0

A0~A1

+1

+2

+3

CS2

tAD3

tAD2

tAD2

tAD2

tHA

tHA

tHA

tHA

RD

tRD3
D0~D15

Input
Data

Input
Data

Input
Data

Figure 3.8.5 Page mode access Timing

92CZ26A-199

tHR
Input
Data

TMP92CZ26A

3.8.5

Internal Boot ROM Control
This section describes about built-in boot ROM.
For the specification of S/W in boot ROM, refer to the section 3.4 boot ROM.
(1) BOOT mode
BOOT mode is started by following AM1 and AM0 pins condition with reset.

AM1

AM0

Start mode

0

0

Don’t use this setting

0

1

Start with 16-bit data bus

1

0

Don’t use this setting

1

1

Start with boot (32-bit internal MROM)

(2) Boot ROM memory map
Boot ROM is consist of 8-Kbyte masked ROM and assigned 3FE000H to 3FFFFFH
address.
000000H
Internal I/O , RAM
04A000H
3FE000H
Internal boot ROM
(8 Kbytes)
3FFF00H
(B) Reset/Interrupt
Vector area
(256 bytes)

400000H

FFFF00H

(A) Reset/Interrupt
Vector area
(256 bytes)

(3) Reset/interrupt address conversion circuit
Originally, reset/interrupt vector area is assigned FFFF00H to FFFFEFH ((A) area) in
TLCS-900/H1.
But because boot ROM is assigned to another area, reset/interrupt vector address
conversion circuit is prepared.
In BOOT mode, reset/interrupt vector area is assigned 3FFF00H to 3FFFEFH ((B) area)
area by it. And after boot sequence, its area can be changed to (A) area by setting
BROMCR to “0”. So, (A) area can be used only for application system program.
This BROMCR is initialized to “1” in BOOT mode. At another starting mode,
this register has no meaning.
Note: The last 16-byte area (FFFFF0H to FFFFFFH) is reserved for an emulator. So, this area is not changed
by  register.

92CZ26A-200

TMP92CZ26A

(4) Disappearing boot ROM
After boot sequence in BOOT mode, an application system program may continue to run
without reset asserting. In this case, an external memory which is mapped 3FE000H to
3FFFFFH address can not be accessed because of boot ROM is assigned.
To solve it, internal boot ROM can be disappered by setting BROMCR to
“1”.
This  is initialized to “0” in BOOT mode. At another starting mode, this bit
is initialized to “1”.
If this bit has been set to “1”, writing “0” is disabled.

7

6

5

4

BROMCR Bit symbol
(016CH)

3

2

1

0

CSDIS

ROMLESS

VACE

Read/Write

R/W

After Reset

1

0/1 (note)

Nand_Flash Boot ROM

Function

area

0: use

address

CS output

1: not use

conversion

0: Enable

0: Disable

1: Disable

1: Enable

Note: The value after reset release is depending on start mode.

92CZ26A-201

1/0 (note)
Vector

TMP92CZ26A

3.8.6 Cautions
(1) Note the timing between CS and RD
If the load capacitance of the RD (Read signal) is greater than that of the CS (Chip
select signal), it is possible that an unintended read cycle occurs due to a delay in the read
signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure
3.8.6.
SDCLK
(60 MHz)
A23 to A0
CSm

CSn
RD

(a)

Figure 3.8.6 Read Signal Delay Read Cycle

Example: When using an externally connected NOR flash which users JEDEC standard
commands, note that the toggle bit may not be read out correctly. If the read signal in the
cycle immediately preceding the access to the NOR flash does not go high in time, as
shown in Figure 3.8.7, an unintended read cycle like the one shown in (b) may occur.
Toggle bit RD cycle

Memory access
SDCLK
(60 MHz)
A23 to A0
NOR flash
chip select
RD

Toggle bit
(b)

Figure 3.8.7 NOR Flash Toggle Bit Read Cycle
When the toggle bit reverse with this unexpected read cycle, CPU always reads same
value of the toggle bit, and cannot read the toggle bit correctly.
To avoid this phenomenon, the data polling function control is recommended. Or use the
adjust timing function for rising edge of RD (RDTMGCRn) in order to avoid
generating this phenomenon.

92CZ26A-202

TMP92CZ26A
(2) Note the NAND flash area setting
Figure 3.8.8 shows a memory map for NAND flash.
And since CS3 area is recommended to assign address from 000000H to 3FFFFFH, this
case is explained.
In this case, “NAND flash” and CS3 area are overlapped. But CS3 pin don’t become
active by setting BROMCR to “1”. And also CS0 to CS3 , SDCS , CSXA to CSXB ,
CSZA to CSZD pins don’t become to active.
Note1: In this case, the address from 000000H to 049FFFH of 296 Kbytes in CS3’s memory can’t be used.
Note2: 16 byte area (001FF0H to 001FFFH) for NAND Flash are fixed like a following without relationship to
setting CS bock. Therefore, NAND flash area don’t according to CS3 area setting.
(NAND-Flash area specification)
1. bus width

: Depend on NDFMCR1 in NAND Flash controller.

2.WAIT control

: Depend on NDFMCR, in NAND Flash controller

000000H
Internal I/O
001FF0H
NAND flash
(16 bytes)

All CS pins become to unactibe
by BROMCR =”1”

002000H

Internal RAM
(288 Kbytes)

04A000H

COMMON X
(2 Mbytes)

CS3 area setting
000000H to 3FFFFFH (4 Mbytes)

200000H

LOCAL X
(2 Mbytes)

400000H

Figure 3.8.8 Recommended CS3 setting

92CZ26A-203

TMP92CZ26A

3.9 External Memory Extension Function (MMU)
This is MMU function which can expand program/data area to 3.1G bytes by having 4-type
local area.
The recommendation address memory map is shown in Figure 3.9.1.
However, when total capacity of used memory is less than 16M bytes, please refer to section of
Memory controller. Setting of register in MMU is not necessary.
An area which can be set as BANK is called LOCAL-area. Since the address for LOCAL area
is fixed, it cannot be changed.
And, area that cannot be set as BANK is called COMMON-area.
Basically one series of program should be closed within one bank. Please don’t jump to the
same LOCAL-area in the different bank directly by JP instruction and so on. Refer to the
examples as follows.
TMP92CZ26A has following external pins to connect external memory-LSI.
Address bus

: EA28, EA27, EA26, EA25, EA24 and A23 to A0

Chip Select

: CS0 to CS3 , CSXA to CSXB , CSZA to CSXD , SDCS ,
ND0CE

Data bus

3.9.1

and ND1CE

: D15 to D0

Recommended memory map
Figure 3.9.1 shows one of recommendation address memory map. It can be expanded to

maximum memory size.
Figure 3.9.3 also shows one of recommendation address memory map. It’s for a simple
memory system like internal Boot-ROM with NAND-Flash and SDRAM.

92CZ26A-204

TMP92CZ26A

ND 0 CE

Memory controller
setting

pin (512MB)

Address memory map
ND1CE

000000H

pin (512MB)

Internal I/O, RAM

COMMON-X
(2MB)

CSXA

CSXB

512MB(2MB× 256)

512MB(2MB× 256)
CS3-area
4MB

200000H
LOCAL-X
(2MB)

Bank 0

1

2

3

・ ・・ 15

LOCAL-Y
(2MB)

Bank 0

1

2

3

・ ・・ 15

・ ・・

255 256 ・ ・

511

400000H
・ ・・

63
CS1-area
4MB

600000H
COMMON-Y
(2MB)

SDCS : 64MB*(SDRAM case 2MB× 32) or CS1 pin: 128MB (2MB× 64)

800000H

LOCAL-Z
(4MB)

Bank 0

1

2

3

・ ・・ 127 128 ・ ・・ 255 ・ ・・ 384 ・ ・・ 511

CS2-area
8MB

C00000H
COMMON-Z
(4MB)

FFFF00H
FFFFFFH

CSZA pin (Note)
512MB(4MB× 128)

:

Vector area

CSZB pin

・ ・・

CSZD

pin

Internal area

: Overlapped with CO MMON-Area and disabled setting as LOCAL-area.

Note1: CSZA is a chip-select for not only bank0 to 127 of LOCAL-Z but also COMMON-Z.
Note2: In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum

Figure 3.9.1Recommendation memory map for maximum specification (Logical address)

92CZ26A-205

TMP92CZ26A

92CZ26A

LOCAL-X
CSXA to CSXB ,
EA24 to 28
512MB×2=1024MB

LOCAL-Y
SDCS or CS1
128MB or
*64MB

CSXA

000000H

Bank0

LOCAL-Z
CSZA to CSZD ,
EA24 to 28
512MB×4=2048MB
CSZA

CSZD

Bank0
Bank0

Bank384

127

511

Internal-I/O and
Internal RAM
63

255
CSXB

CSZB

Bank256
Bank128

255
511
CSZC

Bank256

383

Note: In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum

Figure 3.9.2 Recommendation memory map for maximum specification (Physical address)

92CZ26A-206

TMP92CZ26A

ND 0 CE

pin (512MB)

ND1CE

pin (512MB)

Memory controller
setting

Address memory map
000000H

Internal-I/O, RAM

COMMON-X
(2MB)
200000H

LOCAL-X
(2MB)
Internal Boot-ROM (8KB)

3FE000H
400000H
LOCAL-Y
(2MB)
600000H
COMMON-Y
(2MB)
800000H

LOCAL-Z
(4MB)

Bank 0

1

2

3

・・・ 15

CS2-area
8MB

C00000H
COMMON-Z
(4MB)

FFFF00H
FFFFFFH

SDCS pin

64MB(4MB×16)

Vector area
:Internal

area

: Overlapped with COMMON-Area and disabled setting as LOCAL-area.

Note: In case of connect SDRAM to Z-area, 64MB (4MB×16) is maximum

Figure 3.9.3Recommendation memory map for simple system (Logical address)
92CZ26A

LOCAL-Z
SDCS
4MB×16=64MB
SDCS

000000H
Bank 0
Internal-I/O
and RAM
3FE000H
Internal Boot-ROM

15

Note: In case of connect SDRAM to Z-area, 64MB(4MB×16) is maximum

Figure 3.9.4 Recommendation memory map for simple system (Physical address)

92CZ26A-207

TMP92CZ26A
3.9.2

Control register

There are 24-registers for MMU. They are prepared for 8-purpose using (as Program,
read-data, write-data and LCDC-display-data, source-data for odd/even number channel DMA,
destination-data for odd/even number channel DMA), and 3-local area (LOCAL-X, Y and Z).
These 8-purpose registers can access a data accessed easily.
(How to use)
At first, set enable register and using bank-number of each LOCAL register. In that case,
set a combination pin and memory setting to the Ports and Memory controller. After that, if
CPU or LCDC access to logical address of the local area, MMU converts logical address to
physical address according to the bank number, and output it. The physical address is
output to the external address bus pin. By this operation, accessing to external memory
becomes possible. And, if accessed same logical address, physical address is changed by
bank that be set to register in program, and enable accessing that memory of other bank.
Note:
1) When set the bank page, it inhibit to set overlapped area with common area ( because Local area
and common area shows same physical address)
2) In the LOCAL-area, changing Program bank number (LOCALPX, Y or Z) is disabled. Program bank
setting of each local area must change in common area. (But bank setting of data-Read, data-Write
and LCDC-display data can change also in local area.)
3) After data bank number (LOCALRn, LOCALWn or LOCALLn, LOCALEDn, LOCALSn, LOCALODn;
“n” means X, Y or Z) register is set by an instruction, don’t access its memory by next instruction
because of some clocks are needed to be effective MMU setting. In this case, insert dummy
instruction which accesses SFR or another memory between them like following example.
(Example)

ld

xix, 200000h

;

ldw

(localrx), 8001h

; read-data bank number is set

ldw

wa, (localrx)

; <---- Inserted Dummy instruction which accesses SFR

ldw

wa, (xix)

; instruction which reads bank1 of local-X area.

4) When LOCAL-Z area is used, Chip select signal CSZA should be assigned to P82-pin.
In this case, CSZA works as chip select signal for not only bank0 to 15 but also COMMON-Z.
But for it, following setting after reset is needed before P82 setting.
ldw

(localpz), 8000h

; LOCAL-Z Bank enable for program

ldw

(localrz), 8000h

; LOCAL-Z Bank enable for data read

ldw

(localwz), 8000h

; LOCAL-Z Bank enable for data write

ldw

(locallz), 8000h

; LOCAL-Z Bank enable for LCD display memory (*2)

ld
ld

(p8fc), -----0--B
(p8fc2), -----1--B

; Assign P82 to CSZA
;

(*1) If COMMON-Z area is not used as data write memory, this setting is not needed.
(*2) If COMMON-Z area is not used as LCD display memory, this setting is not needed.

92CZ26A-208

(*1)

TMP92CZ26A

3.9.2.1

Program bank register

The bank number used as program memory is set to these registers. In certain bank, cannot
diverge directly to different bank of same local area. To change program bank number in the
same local area is disable.
LOCAL-X register for Program

LOCALPX
(880H)

bit Symbol

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

0

0

0

0

0

0

0

0

Read/Write
After reset

R/W
Set BANK number for LOCAL-X

Function

(“0” is disabled because of overlapped with Common-area.)

15
(881H)

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0

0

BANK for
Function

Set BANK number for LOCAL-X

LOCALX

X8-X0 setting and CS

0: Disable

000000000 to 011111111 CSXA

1: Enable

100000000 to 111111111 CSXB
LOCAL-Y register for Program

7
LOCALPY
(882H)

6

bit Symbol

5

4

3

Y5

Y4

Y3

Read/Write
0

0

Y2

Y1

Y0

0

0

0

0

0

Set BANK number for LOCAL-Y

Function

(“3” is disabled because of overlapped with Common-area.)

15
bit Symbol

LYE

Read/Write

R/W

After reset

1

R/W

After reset

(883H)

2

14

13

12

11

10

9

8

0
BANK for

Function

LOCALY
0: Disable
1: Enable
LOCAL-Z register for Program

LOCALPZ
(884H)

bit Symbol

7

6

5

4

3

2

1

0

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

Read/Write
After reset

R/W
0

0

0

Set BANK number for LOCAL-Z

Function

(“3” is disabled because of overlapped with Common-area.)

15
(885H)

0

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0
BANK for

Function

LOCALZ

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-209

TMP92CZ26A
3.9.2.2

LCD display bank register

The bank page used as LCD display memory is set to these registers. Since the bank register
for CPU and LCDC are prepared independently, the bank page for CPU (Program, Read-data,
write-data) can change during LCD display on.
LOCAL-X register for LCD

bit Symbol
LOCALLX
(888H)

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

0

0

0

0

0

0

0

0

Read/Write
After reset
Function

R/W
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15
(889H)

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

Set BANK number for LOCAL-X

LOCALX
0: Disable

X8-X0 setting and CS
000000000∼011111111 CSXA

1: Enable

100000000∼111111111 CSXB

LOCAL-Y register for LCD

7
LOCALLY
(88AH)

6

bit Symbol

5

4

3

2

1

0

Y5

Y4

Y3

Y2

Y1

Y0

0

0

0

0

0

0

Read/Write

R/W

After reset

Set BANK number for LOCAL-Y

Function

(“3” is disabled because of overlapped with Common-area.)

15
(88BH)

bit Symbol

LYE

Read/Write

R/W

After reset

13

12

11

10

9

8

3

2

1

0

Z3

Z2

Z1

Z0

0

0

0

0

0
BANK

Function

14

for

LOCALY
0: Disable
1: Enable

LOCAL-Z register for LCD

LOCALLZ
(88CH)

bit Symbol

7

6

5

4

Z7

Z6

Z5

Z4

Read/Write
After reset
Function

R/W
0

0

15
(88DH)

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

LOCALZ

Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-210

TMP92CZ26A
3.9.2.3

Read-data bank register

The bank number used as read-data memory is set to these registers. The following is an
example which read data bank register of LOCAL-X is set to “1”. When “ldw wa, (xix)”
instruction is executed, the bank becomes effective at only read data (operand) for xix address.
(Example)
ld
ld
ldw
ldw

xix, 200000h
(localrx), 8001h
wa,(localrx)
wa, (xix)

;
; Set Read data bank.
; <----Insert dummy instruction that access to SFR
; Read bank1 of LOCAL-X area

LOCAL-X register for read

bit Symbol
LOCALRX
(890H)

7

6

5

4

X7

X6

X5

X4

Read/Write
After reset
Function

2

1

0

X3

X2

X1

X0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15
(891H)

3

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0
BANK for
LOCALX
0: Disable
1: Enable

Function

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for read

7
LOCALRY
(892H)

6

bit Symbol

5

4

3

2

1

0

Y5

Y4

Y3

Y2

Y1

Y0

0

0

0

0

0

0

Read/Write

R/W

After reset

Set BANK number for LOCAL-Y

Function

(“3” is disabled because of overlapped with Common-area.)

15
(893H)

bit Symbol

LYE

Read/Write

R/W

After reset

0
BANK for
LOCALY
0: Disable
1: Enable

Function

14

13

12

11

10

9

8

LOCAL-Z register for read

bit Symbol
LOCALRZ
(894H)

7

6

5

4

3

2

1

0

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

Read/Write
After reset
Function

R/W
0

15
(895H)

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0
BANK for
LOCALZ
0: Disable
1: Enable

Function

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000 to 001111111 CSZA
100000000 to 101111111 CSZC
010000000 to 011111111 CSZB
110000000 to 111111111 CSZD

92CZ26A-211

TMP92CZ26A
3.9.2.4

Write-data bank register

The bank number used as write data memory is set to these registers. The following is an
example which data bank register of LOCAL-X is set to “1”. When “ldw (xix), wa” instruction is
extended, the bank becomes effective at only cycle for xix address.
(Example)
ld
ld
ldw
ldw

xix, 200000h
(localwx), 8001h
wa, (localwx)
(xix), wa

;
; Set Write data bank.
; <----Insert dummy instruction that access to SFR
; Write to bank1 of LOCAL-X area

LOCAL-X register for write

bit Symbol
LOCALWX
(898H)

7

6

5

4

X7

X6

X5

X4

Read/Write
After reset
Function

2

1

0

X3

X2

X1

X0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15

(899H)

3

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0

0

BANK
Function

for

Set BANK number for LOCAL-X

LOCALX

X8-X0 setting and CS

0: Disable

000000000 to 011111111 CSXA

1: Enable

100000000 to 111111111 CSXB
LOCAL-Y register for write

7

6

LOCALWY bit Symbol
(89AH)
Read/Write

5

4

3

Y5

Y4

Y3

0

Y2

Y1

Y0

0

0

0

0

0

(“3” is disabled because of overlapped with Common-area.)

15
bit Symbol

LYE

Read/Write

R/W

14

13

12

11

10

9

8

0
BANK

Function

0

Set BANK number for LOCAL-Y

Function

After reset

1

R/W

After reset

(89BH)

2

for

LOCALY
0: Disable
1: Enable
LOCAL-Z register for write

bit Symbol
LOCALWZ
(89CH)

7

6

5

4

3

2

1

0

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

Read/Write
After reset
Function

R/W
0

0

15

(89DH)

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

LOCALZ

Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-212

TMP92CZ26A
3.9.2.5

DMA-function bank register

In addition to functioning as read/write function of CPU, this LSI can also function which
transfer data at high-speed by internal DMAC becoming bus master. (Please refer to DMAC
section)
In Bank for only DMA that different from Bank for CPU or LCDC display data, although
condition of program bank, read-bank and write-bank for CPU, bank of Source address and
Destination address are enable during operate DMA.
DMAC which assignment is possible in this LSI is 5-channel. But bank controller is 2-type.
Even-channel of DMA-channel 0, 2 and 4 become E-group (ES and ED group), odd-channel of
DMA-channel 1and 3 become O-group (OS and OD group). Assignment every channel is disable
in same group.
Following shows examples of setting bank for DMA_Source address to 1 in LOCALX area and
setting bank for DMA_Destination address to 2 in LOCALY area. If Source address which set to
XXX by using DMA function was set to LOCALX-area and Destination address was set to
LOCALY-area, when DMA of channel 0 is start, LOCALX bank1 is set to source and LOCALY
bank2 is set to destination.
(Example)
ldw

(localesx), 8001h ; Set DMA source bank for channel 0

ldw

(localedy), 8002h ; Set DMA destination bank for channel 0

DMA channel 0 start

92CZ26A-213

TMP92CZ26A
LOCAL-X register for even-group DMA source

bit Symbol
LOCALESX
(8A0H)

7

6

5

4

X7

X6

X5

X4

Read/Write
After reset
Function

2

1

0

X3

X2

X1

X0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15

(8A1H)

3

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0

0

BANK
Function

for

Set BANK number for LOCAL-X

LOCALX

X8-X0 setting and CS

0: Disable

000000000 to 011111111 CSXA

1: Enable

100000000 to 111111111 CSXB

LOCAL-Y register for even-group DMA source

7

6

bit Symbol
LOCALESY
(8A2H)

5

4

3

2

1

0

Y5

Y4

Y3

Y2

Y1

Y0

0

0

0

Read/Write

R/W

After reset

0

(“3” is disabled because of overlapped with Common-area.)

15
bit Symbol

LYE

Read/Write

R/W

After reset

0
BANK

Function

0

Set BANK number for LOCAL-Y

Function

(8A3H)

0

14

13

12

11

10

9

8

3

2

1

0

Z3

Z2

Z1

Z0

0

0

0

0

for

LOCALY
0: Disable
1: Enable

LOCAL-Z register for even-group DMA source

bit Symbol
LOCALESZ Read/Write
(8A4H)
After reset
Function

7

6

5

4

Z7

Z6

Z5

Z4
R/W

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

15

(8A5H)

0

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0

0

BANK for
Function

LOCALZ

Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-214

TMP92CZ26A
LOCAL-X register for even-group DMA destination

bit Symbol
LOCALEDX
(8A8H)

7

6

5

4

X7

X6

X5

X4

Read/Write
After reset
Function

2

1

0

X3

X2

X1

X0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15

(8A9H)

3

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

Set BANK number for LOCAL-X

LOCALX

X8-X0 setting and CS

0: Disable

000000000 to 011111111 CSXA

1: Enable

100000000 to 111111111 CSXB

LOCAL-Y register for even-group DMA destination

7

6

bit Symbol
LOCALEDY Read/Write
(8AAH)
After reset

5

4

3

Y5

Y4

Y3

0

Y2

Y1

Y0

0

0

0

0

0

(“3” is disabled because of overlapped with Common-area.)

15
LYE

Read/Write

R/W

14

13

12

11

10

9

8

3

2

1

0

Z3

Z2

Z1

Z0

0

0

0

0

0
BANK

Function

0

Set BANK number for LOCAL-Y

bit Symbol
After reset

1

R/W

Function

(8ABH)

2

for

LOCALY
0: Disable
1: Enable

LOCAL-Z register for even-group DMA destination

bit Symbol
LOCALEDZ Read/Write
(8ACH)
After reset
Function

7

6

5

4

Z7

Z6

Z5

Z4
R/W

0

0

15

(8ADH)

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

LOCALZ

Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-215

TMP92CZ26A

LOCAL-X register for odd-group DMA source

bit Symbol
LOCALOSX
Read/Write
(8B0H)
After reset
Function

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

0

0

0

0

0

0

0

0

R/W
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15

(8B1H)

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0

0

BANK
Function

for

Set BANK number for LOCAL-X

LOCALX

X8-X0 setting and CS

0: Disable

000000000 to 011111111 CSXA

1: Enable

100000000 to 111111111 CSXB

LOCAL-Y register for odd-group DMA source

7

6

bit Symbol
LOCALOSY Read/Write
(8B2H)
After reset

5

4

3

Y5

Y4

Y3

0

Y2

Y1

Y0

0

0

0

0

0

Set BANK number for LOCAL-Y

15
LYE

Read/Write

R/W

14

13

12

11

10

9

8

3

2

1

0

Z3

Z2

Z1

Z0

0

0

0

0

0
BANK

Function

0

(“3” is disabled because of overlapped with Common-area.)

bit Symbol
After reset

1

R/W

Function

(8B3H)

2

for

LOCALY
0: Disable
1: Enable

LOCAL-Z register for odd-group DMA source

LOCALOSZ
(8B4H)

bit Symbol

7

6

5

4

Z7

Z6

Z5

Z4

Read/Write
After reset
Function

R/W
0

0

15

(8B5H)

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0

0

BANK
Function

for

LOCALZ

Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-216

TMP92CZ26A
LOCAL-X register for odd-group DMA destination

LOCALODX
(8B8H)

bit Symbol

7

6

5

4

X7

X6

X5

X4

Read/Write
After reset
Function

2

1

0

X3

X2

X1

X0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)

15
(8B9H)

3

14

13

12

11

10

9

8

bit Symbol

LXE

X8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

Set BANK number for LOCAL-X

LOCALX

X8-X0 setting and CS

0: Disable

000000000 to 011111111 CSXA

1: Enable

100000000 to 111111111 CSXB

LOCAL-Y register for odd-group DMA destination

7

6

LOCALODY bit Symbol
Read/Write
(8BAH)

5

4

3

Y5

Y4

Y3

0

Y2

Y1

Y0

0

0

0

0

0

(“3” is disabled because of overlapped with Common-area.)

15
bit Symbol

LYE

Read/Write

R/W

14

13

12

11

10

9

8

3

2

1

0

Z3

Z2

Z1

Z0

0

0

0

0

0
BANK

Function

0

Set BANK number for LOCAL-Y

Function

After reset

1

R/W

After reset

(8BBH)

2

for

LOCALY
0: Disable
1: Enable

LOCAL-Z register for odd-group DMA destination

LOCALODZ bit Symbol
Read/Write
(8BCH)
After reset
Function

7

6

5

4

Z7

Z6

Z5

Z4
R/W

0

0

15
(8BDH)

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

14

13

12

11

10

9

8

bit Symbol

LZE

Z8

Read/Write

R/W

R/W

After reset

0
BANK

Function

0
for

LOCALZ

Set BANK number for LOCAL-Z
Z8-Z0 setting and CS

0: Disable

000000000 to 001111111 CSZA

100000000 to 101111111 CSZC

1: Enable

010000000 to 011111111 CSZB

110000000 to 111111111 CSZD

92CZ26A-217

TMP92CZ26A
3.9.3

Setting example
This is in case of using like following condition.

No.

Used as

Memory

Setting

MMU-area

(a)

Main
Routine
CharacterROM
Sub
Routine
LCD
Display-RAM
StackRAM

NOR-Flash
(16MB, 1pcs)

CSZA ,

COMMON-Z

(b)
(c)
(d)
(e)

32bit,
1wait

SRAM
(16MB, 1pcs)

Internal-RAM
(288KB)

CS1 ,

16bit,
0wait
---(32bit,
2-1-1-1clk)

Bank0 in
LOCAL-Z
Bank0 in
LOCAL-Y
Bank1 in
LOCAL-Y
Bank2 in
LOCAL-Y

Logical
Physical
address
address
C00000H to
FFFFFFH
800000H to 000000H to
BFFFFFH
3FFFFFH
400000H to 000000H to
5FFFFFH
1FFFFFH
200000H to
3FFFFFH
002000H to
049FFFH

(a) Main routine (COMMON-Z)
Logical

Physical

Address

Address

No

Instruction

Comment

1

org

C00000H

;

C00000H

<-(Same)

2

ldw

(mamr2),80FFH

; CS2 800000-ffffff/8MB

C000xxH

<-

3

ldw

(b2csl), C222H

; CS2 32bit ROM, 1wait

4

ldw

(mamr1),40FFH

; CS1 400000-7fffff/4MB

5

ldw

(b1csl), 8111H

; CS1 16bit RAM, 0wait

5.1

ldw

(localpz),8000H

; Enable LOCAL-Z Bank for program

5.2

; Enable LOCAL-Z Bank for read-data

ldw

(localrz),8000H

6

ld

(p8fc), 02H

;

7

ld

(p8fc2), 04H

;

xsp,48000H

9

ld

10

ldw

11

:

(localpy),8000H

; Stack Pointer = 48000H
; Bank0 in LOCAL-Y is set as Program bank
for sub routine

C000yyH

<-

;

12

call

13

:

400000H

;

; Call Sub routine

14

:

;

15

:

;

・

From No.2 to No.8 instructions are setting of Ports and Memory controller.

・

No.9 is a setting for stack pointer. It is assigned to internal-RAM.

・

No.10 is a setting to execute for No.12’s instruction.

・

No.12 is an instruction to call sub routine. When CPU outputs 400000H address, MMU will convert and output 000000H
physical address to external address bus: A23 to A0. And CS1 for SRAM will be asserted because of logical address is
in an area for CS1 at the same time. By these instructions, CPU cans brunch to sub-routine.
(Note: This example is based on sub routine program is already written on SRAM.)

92CZ26A-218

TMP92CZ26A

(b) Sub routine (Bank-0 in LOCAL-Y)
Logical

Physical

address

address

400000H

000000H

4000xxH

0000xxH

No

Instruction

16
17

org
ldw

400000H
(localwy),8001H

18
19

ldw
ldw

(locally), 8001H
(localrz), 8001H

20

ld

xiy,800000H

21

ld

Comment
;
; Bank1 in LOCAL-Y is set to write-data for LCD
Display RAM
; Bank1 in LOCAL-Y is set as LCD display RAM
; Bank0 in LOCAL-Z is set as read-data
for Character-RAM

22

5000yyH

1000yyH

wa,(xiy)
:

23
24

ld
ld

(localpy), 82H
xix, 400000H

25
26
27
28
29
30
31
32

ld
:
:
ld
ld
ld
:
ret

(xix), bc

xiz, 400000H
(lsarcl), xiz
(lcdctl0),01H

; Index address register for read
Character-ROM
; Read Character-ROM
; Convert it to display-data
;
; Index address register for write LCD
Display data
; Write LCD Display data
; Set LCD Controller
;
; Set LCD Start address to LCDC
;
; Start LCD Display operation
;
;

・No.17 and No.18 are setting for Bank-1 of LOCAL-Y. In this case, LCD Display data is written to SRAM by CPU.

So, (LOCALWY) and (LOCALLY) should be set to same bank-1.
・No.19 is a setting for Bank-0 of LOCAL-Z to read data from character-ROM.
・No.20 and No.21 are instructions to read data from character-ROM. When CPU outputs 800000H address, this MMU will

convert and output 000000H address to external address bus: A23 to A0. And /CSZA for NOR-Flash will be asserted
because of logical address is in an area for CS2 at the same time.
By these instructions, CPU can read data from character ROM.
・No.23 is an instruction which changes Program bank number in the LOCAL-area. This setting is disabled.
・No.24 and No.25 are instructions to write data to SRAM. When CPU outputs 400000H address, this MMU will convert and

output 200000H address to external address bus: A23 to A0. And /CS1 for SRAM will be asserted because of logical
address is in an area for CS1 at the same time.
By these instructions, CPU can write data to SRAM.
・No.28 and No.29 are setting to set LCD starting address to LCD Controller.

When LCDC outputs 400000H address in

DMA-cycle, this MMU will convert and output 200000H address to external address bus: A23 to A0. And /CS1 for SRAM
will be asserted because of logical address is in an area for CS1 at the same time.
By these instructions, LCDC can read data from SRAM.
・No.30 is an instruction to start LCD display operation.

92CZ26A-219

TMP92CZ26A

3.10 SDRAM Controller (SDRAMC)
The TMP92CZ26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that can
be used as data memory, program memory, or display memory.
The SDRAMC has the following features:
(1) Supported SDRAM
Data rate type
Memory capacity
Number of banks

: SDR (single data rate) type only
: 16 / 64 / 128 / 256 / 512 Mbits
: 2 banks / 4 banks

Data bus width
Read burst length
Write mode

: 16 bits
: 1 word / full page
: Single mode / Burst mode

(2) Supported initialization sequence commands
Precharge All command
Eight Auto Refresh commands
Mode Register Set command
(3) Access mode

Burst length
Addressing mode
CAS latency (clock)
Write mode

(4) Access cycles
CPU access cycles
Read cycle
Write cycle
Data size
HDMA access cycles
Read cycle
Write cycle
Data size

CPU Cycle

HDMA Cycle

LCDC Cycle

1 word

1 word or full page selectable

Full page

Sequential

Sequential

Sequential

2

2

2

Single

Single or burst selectable

: 1 word, 4-3-3-3 states (minimum)
: Single, 3-2-2-2 states (minimum)
: 1 byte / 1 word / 1 long-word

: 1 word, 4-3-3-3 states / full page, 4-1-1-1 states (minimum)
: Single, 3-2-2-2 states (minimum) / burst, 2-1-1-1 states (minimum)
: 1 byte / 1 word / 1 long-word

LCDC access cycles
Read cycle
Data size

: Full page, 4-1-1-1 states (minimum)
: 1 word

(5) Auto generation of refresh cycles
• Auto Refresh is performed while the SDRAM is not being accessed.
• The Auto Refresh interval is programmable.
• The Self Refresh function is also supported.
Note: The SDRAM address area is determined by the CS1 or CS2 setting of the memory controller. However, the number of
bus cycle states is controlled by the SDRAMC.

92CZ26A-220

TMP92CZ26A
3.10.1 Control Registers
The SDRAMC has the following control registers.

SDACR
(0250H)

Bit symbol
Read/Write
After reset

7
SRDS
1
Read data

0
Always

SDRAM Access Control Register
5
4
3
SMUXW1 SMUXW0
SPRE
R/W
0
0
0
Address multiplex type

write “0”

shift

Function

6
–

2

1

0
SMAC
R/W
0

Read/Write

SDRAM

commands

controller

0: Without

0: Disable

function

00: Type A (A9- )

0: Disable

01: Type B (A10- )

1: Enable

10: Type C (A11- )

auto pre-

11: Reserved

charge

1: Enable

1: With auto
precharge

7
SDCISR
(0251H)

Bit symbol
Read/Write
After reset

Function

SDRCR
(0252H)

Bit symbol
Read/Write
After reset

Function

7
−
R/W
0
Always
write “0”

SDRAM Command Interval Setting Register
6
5
4
3
2
1
0
STMRD
STWR
STRP
STRCD
STRC2
STRC1
STRC0
R/W
1
1
1
1
1
0
0
TMRD
TWR
TRP
TRCD
TRC
000: 1 CLK 100: 5 CLK
0: 1 CLK
0: 1 CLK
0: 1 CLK
0: 1 CLK
001: 2 CLK 101: 6 CLK
1: 2 CLK
1: 2 CLK
1: 2 CLK
1: 2 CLK
010: 3 CLK 110: 7 CLK
011: 4 CLK 111: 8 CLK

6

SDRAM Refresh Control Register
5
4
3
SSAE
SRS2
1
Self
Refresh
auto exit
function
0:Disable
1:Enable

92CZ26A-221

2
1
SRS1
SRS0
R/W
0
0
0
Refresh interval
000: 47 states 100: 468 states
001: 78 states 101: 624 states
010: 156 states 110: 936 states
011: 312 states 111: 1248 states

0
SRC
0
Auto
Refresh
0:Disable
1:Enable

TMP92CZ26A

7
SDCMM
(0253H)

6

SDRAM Command Register
5
4
3

Bit symbol
Read/Write
After reset

Function

2
SCMM2

1
0
SCMM1
SCMM0
R/W
0
0
0
Command issue (Note 1) (Note 2)
000: Don’t care
001: Initialization sequence
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved

Note 1:  is automatically cleared to “000” after the specified command is issued. Before writing the next
command, make sure that  is “000”. In the case of the Self Refresh Entry command, however,
 is not cleared to “000” by execution of this command. Thus, this register can be used as a flag for
checking whether or not Self Refresh is being performed.
Note 2: The Self Refresh Exit command can only be specified while Self Refresh is being performed.

7
SDBLS
(0254H)

Bit symbol
Read/Write
After reset

SDRAM HDMA Burst Length Select Register
6
5
4
3
2
SDBL5
SDBL4
SDBLS
SDBL2
R/W
0
0
0
0

1
SDBL1

0
SDBL0

0

0

For HDMA5 For HDMA4 For HDMA3 For HDMA2 For HDMA1 For HDMA0

Function

HDMA burst length
0: 1 Word read / Single write
1: Full page read / Burst write

Figure 3.10.1 Control Registers

92CZ26A-222

TMP92CZ26A

3.10.2 Operation Description
(1) Memory access control
The SDRAMC is enabled by setting SDACR to “1”.
When one of the bus masters (CPU, LCDC, DMAC) generates a cycle to access the SDRAM
address area, the SDRAMC outputs SDRAM control signals.
Figure3.10.2 to Figure3.10.5 shows the timing for accessing the SDRAM. The number of
SDRAM access cycles is controlled by the SDRAMC and does not depend on the number of
waits controlled by the memory controller.
(a)

Command issue function
The SDRAMC issues commands as specified by the SDCMM register. The SDRAMC also
issues commands automatically for each SDRAM access cycle generated by each bus
master.
Table 3.10.1 shows the commands that are issued by the SDRAMC.
Table 3.10.1 Commands Issued by the SDRAMC
CKEn-1

CKEn

SDxxDQM

A10

A15-11
A9-0

SDCS

Bank Activate

H

H

H

RA

RA

L

L

H

H

Precharge All

H

H

H

H

X

L

L

H

L

Read

H

H

L

L

CA

L

H

L

H

Read with Auto Precharge

H

H

L

H

CA

L

H

L

H

Write

H

H

L

L

CA

L

H

L

L

Write with Auto Precharge

H

H

L

H

CA

L

H

L

L

Mode Register Set

H

H

H

L

M

L

L

L

L

Burst Stop

H

H

H

X

X

L

H

H

L

Auto Refresh

H

H

H

X

X

L

L

L

H

Self Refresh Entry

H

L

H

X

X

L

L

L

H

Self Refresh Exit

L

H

H

X

X

H

H

H

H

Command

SDRAS SDCAS

SDWE

Note 1: H = High level, L = Low level, RA = Row address, CA = Column address, M = Mode data, X = Don’t care
Note 2: CKEn = CKE level in the command input cycle
CKEn-1 = CKE level in a cycle immediately before the command input cycle

92CZ26A-223

TMP92CZ26A

(b)

Address multiplex function
In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The
multiplex width is set by SDACR. Table3.10.2 shows the relationship
between the multiplex width and low/column addresses.
Table3.10.2 Address Multiplex
SDRAM Access Cycle Address
92CZ26A Pin

Row Address

Name

Column Address

Type A

Type B

Type C

 = 00

 = 01

 = 10

A0

A9

A10

A11

A1

A1

A10

A11

A12

A2

A2

A11

A12

A13

A3

A3

A12

A13

A14

A4

A4

A13

A14

A15

A5

A5

A14

A15

A16

A6

A6

A15

A16

A17

A7

A7

A16

A17

A18

A8

A8

A17

A18

A19

A9

A9

A18

A19

A20

A10
AP *

A10

A19

A20

A21

A11

A20

A21

A22

A12

A21

A22

A23

A13

A22

A23

EA24

A14

A23

EA24

EA25

A15

EA24

EA25

EA26

Row Address

*AP: Auto Precharge

(c)

Burst length
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write.
When the LCDC accesses the SDRAM, the burst length is fixed to full page.
The burst length can be selected for SDRAM read and write accesses by HDMA if the
following conditions are satisfied:
• The HDMA transfer mode is an increment mode.
• Transfers are made between the SDRAM and internal RAM or internal I/O.
In other cases, HDMA operation can only be performed in 1-word read/single write mode.
Use SDBLS to set the burst length for each HDMA channel.

92CZ26A-224

TMP92CZ26A

4CLK

3CLK

3CLK

CA (n+2)

CA (n+4)

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE

A10

RA

A15-A0

RA

CA (n)

D15-D0

D (n)
tRCD=
1CLK

Bank
Active

D (n+2)

CAS Latency=2CLK

D (n+4)

CAS Latency=2CLK

Read

CAS Latency=2CLK

Read

Read

Figure3.10.2 1-Word Read Cycle Timing

4CLK

1CLK

1CLK

Burst Stop Cycle 2CLK

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE

A10

RA

A15-A0

RA

A10
CA (n)

D15-D0

A15-0
D (n)

tRCD=
1CLK

Bank
Active

D (n+2)

D (n+4)

D(dmy)

D (dmy)

CAS Latency=2CLK

Burst Stop

Read

Figure3.10.3 Full-Page Read Cycle Timing

92CZ26A-225

TMP92CZ26A

3CLK

2CLK

2CLK

CA (n+2)

CA (n+4)

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE

A10

RA

A15-A0

RA

D15-D0

CA (n)
D (n)

D (n+2)

tRCD=
1CLK

Bank
Active

tWR=
1CLK

D (n+4)

tWR=
1CLK

Write

tWR=
1CLK

Write

Write

Figure3.10.4 Single Write Cycle Timing

2CLK

1CLK

1CLK

Burst Stop Cycle 2CLK

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE

A10

RA

A15-A0

RA

D15-D0

A10
CA(n)
D(n)

CA(n)
D(n+2)

D(n+4)

D(n+6)

A15-0

D(end)

tRCD=
1CLK

Bank
Active

Burst
Stop

Write

Figure3.10.5 Burst Write Cycle Timing

92CZ26A-226

TMP92CZ26A
(2) Execution of instructions on SDRAM
The CPU can execute instructions that are stored in the SDRAM. However, the following
operations cannot be performed.
a) Executing the HALT instruction
b) Changing the clock gear setting
c) Changing the settings in the SDACR, SDCMM, and SDCISR registers
These operations, if needed, must be executed by branching to other memory such as
internal RAM.
(3) Command interval adjustment function
Command execution intervals can be adjusted for each command. This function enables the
SDRAM to be accessed at optimum cycles even if the operationg frequency is changed by clock
gear.
Command intervals should be set in the SDCISR register according to the operating
frequency of the TMP92CZ26A and the AC specifications of the SDRAM.
The SDCICR register must not be changed while the SDRAM is being accessed.
The timing waveforms for various cases are shown below.
(a) Mode Register Set command
SDCLK
COMMAND NOP

MRS

NOP

Next
Command

NOP

TMRD

*TMRD=2CLK (SDCISR=”1”)
(b) Auto Refresh command
SDCLK
COMMAND NOP

AUTO
REFRESH

NOP

NOP

NOP

NOP

Next
Command

TRC

*TRC=5CLK (SDCISR=”100”)
(c) Self Refresh Exit
SDCLK
SDCKE
COMMAND XXX

NOP

NOP

NOP

NOP

NOP

TRC
*TRC=5CLK (SDCISR= “100”)
Exit Self Refresh

92CZ26A-227

Next
Command

TMP92CZ26A

(d) Precharge command
SDCLK
PRECHARGE

COMMAND NOP

NOP

Next
Command

NOP

TRP

*TRP=2CLK (SDCISR= “1”)

(e) Read cycle
SDCLK
COMMAND NOP

ACTIVE
Row Address

A15-A0

NOP

READ

Column Address

NOP

NOP

Non MUX-address

NOP

ACTIVE

Row Address

DIN

D15-D0
TRCD
TRC

*TRCD=2CLK (SDCISR= “1”)
*TRC=6CLK (SDCISR= “101”)
(f)

Write cycle

SDCLK
COMMAND
A15-A0

NOP

ACTIVE
Row Address

NOP

WRITE

Column Address

NOP

PRECHARG

Non MUX-address

NOP

Row Address

DOUT

D15-D0
TRCD

TWR
TRC

*TRCD=2CLK (SDCISR= “1”)
*TWR=2CLK (SDCISR= “1”)
*TRP=2CLK (SDCISR= “1”)
*TRC=6CLK (SDCISR= “101”)

92CZ26A-228

ACTIVE

TRP

TMP92CZ26A

(4) Read data shift function
If the AC specifications of the SDRAM cannot be satisfied when data is read from the
SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in
the next state. When this read data shift function is used, the read cycle requires additional
one state. The write cycle is not affected. The timing waveforms for various cases are shown
below.
(a) 1-word read, the read data shift function disabled (SDACR = “0”)
SDCLK
COMMAND

A15-A0

NOP

ACTIVE
Row Address

READ

NOP

NOP

ColumnAddress

ACTIVE

READ

Row Address

Column
Address

DIN1

D15-D0
Internal system
clock

DIN1

Internal dat bus

CPU data read
(b) 1-word read, the read data shift function enabled (SDACR = “1”,
=”0”)

SDCLK
COMMAND NOP
A15-A0

ACTIVE
Row Address

READ

NOP

NOP

NOP

ColumnAddress

ACTIVE
Row Address

DIN1

D15-D0
Internal system
clock
ク
ク
Internal data bus

DIN1
External data latch

92CZ26A-229

CPU data read

TMP92CZ26A

(c) Full-page read, the read data shift function enabled (SDACR = “1”,
 = “0”)
SDCLK
COMMAND NOP
A15-A0

ACTIVE

READ

NOP

Row Address

NOP

NOP

NOP

ColumnAddress
DIN1

D15-D0

DIN2

DIN3

Internal system
clock

DIN1

Internal data bus

External data latch

DIN2

DIN3

CPU data read

(5) Read/Write commands
The Read/Write commands to be used in 1-word read/single write mode can be specified by
using SDACR.
When SDACR is set to “1”, the Read/Write commands are executed with Auto
Precharge. When Auto Precharge is enabled, the SDRAM is automatically precharged
internally at every access cycle. Thus, the SDRAM is always in a “bank idle” state while it is
not being accessed. This helps reduce the power consumption of the SDRAM but at the cost of
degradation in performance as the Bank Active command is needed at every access cycle.
When SDACR is set to “0”, the Read/Write commands are executed without Auto
Precharge. In this case, the SDRAM is not precharged at every access cycle and is always in a
“bank active” state. This increases the power consumption of the SDRAM, but improves
performance as there is no need to issue the Bank Active command at every access cycle. If an
access is made to outside the SDRAM page boundaries or if the Auto Refresh command is
issued, the SDRAMC automatically issues the Precharge All command.

92CZ26A-230

TMP92CZ26A

(6) Refresh control
The TMP92CZ26A supports two kinds of refresh commands: Auto Refresh and Self Refresh.
(a) Auto Refresh
When SDRCR is set to “1”, the Auto Refresh command is automatically issued at
intervals specified by SDRCR. The Auto Refresh interval can be specified in a
range of 47 states to 1248 states (0.78 μs to 20.8 μs at f SYS = 60 MHz).
The CPU operation (instruction fetch and execution) is halted while the Auto Refresh
command is being executed. Figure3.10.6 shows the Auto Refresh cycle timing, and
Table3.10.3 shows the Auto Refresh interval settings. The Auto Refresh function cannot be
used in IDLE1 and STOP modes. In these modes, use the Self Refresh function to be
explained next.
Note: A system reset disables the Auto Refresh function.

2 states
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE

Auto Refresh

Figure3.10.6 Auto Refresh Cycle Timing

Table3.10.3 Auto Refresh Intervals
Unit [μs]

SDRCR
SRS2

SRS1

SRS0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Auto
Refresh
Interval
(states)
47
78
156
312
468
624
936
1248

Frequency (System Clock)
6 MHz

10 MHz

20 MHz

40 MHz

60 MHz

80 MHz

7.8
13.0
26.0
52.0
78.0
104.0
156.0
208.0

4.7
7.8
15.6
31.2
46.8
62.4
93.6
124.8

2.4
3.9
7.8
15.6
23.4
31.2
46.8
62.4

1.18
1.95
3.90
7.80
11.70
15.60
23.40
31.20

0.78
1.30
2.60
5.20
7.80
10.40
15.60
20.80

0.59
0.98
1.95
3.90
5.85
7.80
11.70
15.60

92CZ26A-231

TMP92CZ26A
(b) Self Refresh
The Self Refresh Entry command is issued by setting SDCMM to “101”.
Figure3.10.7 shows the Self Refresh cycle timing. Once Self Refresh is started, the SDRAM
is refreshed internally without the need to issue the Auto Refresh command.
Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is
exited. Note that the Auto Refresh function is also disabled at this time.
Note 2: The SDRAM cannot be accessed while it is in the Self Refresh state.
Note 3: To execute the HALT instruction after the Self Refresh Entry command, insert at least 10 bytes of NOP or other
instructions between the instruction to set SDCMM to “101” and the HALT instruction.

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS

SDRAS
SDCAS

SDWE
Self Refresh Entry

Self Refresh Exit

Figure3.10.7 Self Refresh Cycle Timing

92CZ26A-232

Auto Refresh Mode
Set

TMP92CZ26A

The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh
Exit command is executed when SDCMM is set to “110”. It is also executed
automatically in synchronization with HALT mode release. In either of these two cases,
Auto Refresh is performed immediately after the Self Refresh state is exited. Then, Auto
Refresh is executed at specified intervals. Exiting the Self Refresh state clears
SDCMM to “000”.
Setting SDRCR to “0” disables automatic execution of the Self Refresh Exit
command in synchronization with HALT release. The auto exit function should also be
disabled in cases where the SDRAM operation requirements cannot be met as the operation
clock frequency is reduced by clock gear down, as shown in Figure3.10.8.

Gear down

Gear up

fSYS
60MHz
｜
｜
625 KHz (10MHz/16)

Interrupt

CPU
Auto-EXIT
disable

SR
ENTRY

CLK
change

HALT

CLK
change

SR
EXIT

Auto-EXIT
enable

HALT mode
SDRAM controller
internal state
Auto Exit
enable

Auto Exit
disable

Auto Exit
enable

SDRAM state
Auto Refresh

Self Refresh

Auto Refresh

Figure3.10.8 Execution Flow for Executing HALT Instruction after Clock Gear Down

92CZ26A-233

TMP92CZ26A

(7) SDRAM initialization sequence
After reset release, the following sequence of commands can be executed to initialize the
SDRAM.
1. Precharge All command
2. Eight Auto Refresh commands
3. Mode Register Set command
The above commands are issued by setting SDCMM to “001”. While these
commands are issued, the CPU operation (instruction fetch, execution) is halted. Before
executing the initialization sequence, appropriate port settings must be made to enable the
SDRAM control signals and address signals (A0 to A15).
After the initialization sequence is completed, SDCMM is automatically
cleared to “000”.

Eight Auto Refresh commands

SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS

SDCAS
SDWE

A10
A15-A0

627

Precharge All

227

Auto Refresh

Auto Refresh

Auto Refresh

Auto Refresh

Figure3.10.9 Initialization Sequence Timing

92CZ26A-234

Auto Refresh

Mode Register
Set

TMP92CZ26A
(8) Connection example
Figure3.10.10 shows an example of connections between the TMP92CZ26A and SDRAM.
Table3.10.4 Pin Connections
SDRAM Pin Name

92CZ26A

Data Bus Width 16 bits

Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

16M

64M

128M

256M

512M

A0

A0

A0

A0

A0

A1

A1

A1

A1

A1

A2

A2

A2

A2

A2

A3

A3

A3

A3

A3

A4

A4

A4

A4

A4

A5

A5

A5

A5

A5

A6

A6

A6

A6

A6

A7

A7

A7

A7

A7

A8

A8

A8

A8

A8

A9

A9

A9

A9

A9

A10

A10

A10

A10

A10

BS

A11

A11

A11

A11

−

BS0

BS0

A12

A12

BS1

BS1

BS0

BS0

−
−

−
−

BS1

BS1

−

−

−
−
−

SDCS

CS

CS

CS

CS

CS

SDLUDQM

UDQM

UDQM

UDQM

UDQM

UDQM

SDLLDQM

LDQM

LDQM

LDQM

LDQM

LDQM

SDRAS

RAS

RAS

RAS

RAS

RAS

SDCAS

CAS

CAS

CAS

CAS

CAS

SDWE

WE

WE

WE

WE

WE

SDCKE

CKE

CKE

CKE

CKE

CKE

SDCLK

CLK

CLK

CLK

CLK

CLK

SDACR


00:

00:

01:

01:

10:

TypeA

TypeA

TypeB

TypeB

TypeC

: Command address pin of SDRAM

TMP92CZ26A
SDCLK
SDCKE

CLK
CKE

A13
A12

BS1
BS0

A11-A0

A11-A0

D15-D0

D15-D0

SDRAS
SDCAS
SDWE
SDCS

RAS
CAS
WE
CS

SDLUDQM
SDLLDQM

UDQM
LDQM
1 Mword x 4 banks x 16 bits

Figure3.10.10 An Example of Connections between TMP92CZ26A and SDRAM

92CZ26A-235

TMP92CZ26A

3.10.3 An Example of Calculating HDMA Transfer Time
The following shows an example of calculating the HDMA transfer time when SDRAM is used as
the transfer source.

1) Transfer from SDRAM to internal SRAM
Conditions:
System clock (fSYS)
SDRAM read cycle
SDRAM Auto Refresh interval
Internal RAM write cycle
Number of bytes to transfer

: 60 MHz
: Full page (5-1-1-1), 16-bit data bus
16-bit data bus
: 936 states (15.6 μs)
: 1 state, 32-bit data bus
: 512 bytes

Calculation example:
Transfer time = (SDRAM read time + SRAM write time) × transfer count
+ (SDRAM burst start + stop time)
+ (Precharge time + Auto Refresh time) × Auto Refresh count
(a) Read/write time
(SDRAM read 1 state × 2 + Internal RAM write 1 state) × 512 bytes/4 bytes
= 384 states × 1/60 MHz
= 6.4 μs
(b) Burst start/stop time
Start (TRCD: 2CLK) 5 states + Stop 2 states
= 7states/60 MHz
= 0.117 μs
(c) Auto Refresh time
Based on the above (a), Auto Refresh occurs once or zero times in 384 states. It is
assumed that Auto Refresh occurs once here.
(Precharge (TRP: 2CLK) 2 states + AREF (TRC: 5CLK) 5 states) ×AREF once
= 7 states × 1/60 MHz
= 0.117 μs
Total transfer time = (a) + (b) + (c)
= 6.4 μs + 0.117 μs + 0.117 μs
= 6.634 μs

92CZ26A-236

TMP92CZ26A
3.10.4 Considerations for Using the SDRAMC
This section describes the points that must be taken into account when using the SDRAMC.
Please carefully read the following to ensure proper use of the SDRAMC.
1) WAIT access
When SDRAM is used, the following restriction applies to memory access to other than
the SDRAM.
In the external WAIT pin input setting of the memory controller, the maximum external
WAIT period that can be set is limited to “Auto Refresh interval × 8190”.
2) Execution of the Self Refresh Entry, Initialization Sequence, or Precharge All command
before the HALT instruction
Execution of the commands issued by the SDRAMC (Self Refresh Entry, Initialization
Sequence, Precharge All) requires several states after the SDCMM register is set.
Therefore, to execute the HALT instruction after one of these commands, be sure to insert
at least 10 bytes of NOP or other instructions.
3) Auto Refresh interval setting
When SDRAM is used, the system clock frequency must be set to satisfy the minimum
operation frequency and minimum Auto Refresh interval of the SDRAM to be used.
In a system in which SDRAM is used and the clock is geared up and down, the Auto
Refresh interval must be set carefully.
Before changing the Auto Refresh interval, ensure that SDRCR is set to “0” to
disable the Auto Refresh function.
4) Changing SFR settings
Before changing the settings of the SDACR and SDCISR registers, ensure that
the SDRAMC is disabled (SDACR =“0”).
5) Disabling the SDRAMC
Set the following procedure, when disable the SDRAMC.

LOOP:

LD
LD
CP

(SDCMM),0x02
A,(SDCMM)
A,0x00

;
;
;

JP
LD

NZ,LOOP
(SDACR),0x00

;
;

Issue to All Bank Precharge
Read SDCMM
Palling it until the All Bank Precharge command
finished
Stop the SDRAM controller

92CZ26A-237

is

TMP92CZ26A

3.11 NAND Flash Controller (NDFC)
3.11.1

Features

The NAND Flash Controller (NDFC) is provided with dedicated pins for connecting with
NAND Flash memory.
The NDFC also has an ECC calculation function for error correction and supports two types
of ECC calculation methods. The ECC calculation method using Hamming codes can be used for
NAND Flash memory of SLC (Single Level Cell) type and is capable of detecting a single-bit
error for every 256 bytes. The ECC calculation method using Reed-Solomon codes can be used
for NAND Flash memory of MLC (Multi Level Cell) type and is capable of detecting four error
addresses for every 518 bytes.
Although the NDFC has two channels (channel 0, channel 1), all pins except for Chip Enable
are shared between the two channels. Only the operation of channel 0 is explained here.
The NDFC has the following features:
1) Controls the NAND Flash memory interface through registers.
2) Supports 8-bit and 16-bit NAND Flash memory devices.
3) Supports page sizes of 512 bytes and 2048 bytes.
4) Supports large-capacity block sizes over 256 Kbytes.
5) Includes an ECC generation circuit using Hamming codes (for SLC type).
6) Includes a 4-address (4-byte) error detection circuit using Reed-Solomon coding/
encoding techniques (for MLC type).

Note 1: The WP (Write Protect) pin of NAND Flash is not supported. If this function is needed, prepare it on an
external circuit.
Note 2: The two channels cannot be accessed simultaneously. It is necessary to switch between the two channels.

92CZ26A-238

TMP92CZ26A

3.11.1

Block Diagram
NAND Flash Controller Channel 0 (NDFC0)

ND_CE*

Hamming
ECC
Generator

ND_ALE
ND_CLE

ECC
Code

ND_RE*

Internal Data Bus

Timing
Generator

ND0CE
NDCLE,
NDALE,

NDRE ,

ND WE*

NDWE ,

ND_RB*

D15~ D0

RS ECC Write
Control
Register

Reed-Solomon
ECC
Generator
DATA_OUT[15:0]
DATA_IN[15:0]

F/F 80-bit
Address
Data

Reed-Solomon
ECC
Calculator

Figure 3.11.1 Block Diagram for NAND Flash Controller

92CZ26A-239

D15~D0,
NDR/B

TMP92CZ26A

3.11.2

Operation Description

3.11.2.1 Accessing NAND Flash Memory
The NDFC accesses data on NAND Flash memory indirectly through its internal
registers. This section explains the operations for accessing the NAND Flash.
Since no dedicated sequencer is provided for generating commands to the NAND Flash,
the levels of the NDCLE, NDALE, and NDCE pins must be controlled by software.

NDCLE

NDALE

NDCE

NDRE
NDWE

NDR/B

D15∼D0

NDFMCR0 = 1

NDFMCR0 = 0
NDFMCR0 = 1

NDFMCR0 = 1

Figure 3.11.2 Basic Timing for Accessing NAND Flash

92CZ26A-240

ND0FMCR = 0

TMP92CZ26A

The NDRE and NDWE signals are explained next. Write and read operations to and from
the NAND Flash are performed through the ND0FDTR register. The actual write operation
completes not when the ND0FDTR register is written to but when the data is written to the
external NAND Flash. Likewise, the actual read operation completes not when the
ND0FDTR register is read but when the data is read from the external NAND Flash.
At this time, the Low and High widths of NDRE and NDWE can be adjusted according to
the CPU operating speed (fSYS) and the access time of the NAND Flash. (For details, refer to
the electrical characteristics.)
The following shows an example of accessing the NAND Flash in 6 clocks by setting
NDFMCR0=2 and NDFMCR0=2. (In write cycles, the data drive
time also becomes longer.)
Program Memory Read (1wait)

Program Memory Read (1 wait)

NAND Flash Read

fSYS
A23∼A0

FF1234H

FF1238H

001FF0H

CS2

RD
SRWR
2clk

NDCLE
NDALE

NDCE
2clk

NDRE

NDWE
NDR/B
D15 ∼ D0

IN (Program)

Program Memory Read (1 wait)

IN (NAND Flash)

IN (Program)

Program Memory Read (1 wait)

NAND Flash Write

fSYS
A23∼A0

FF1234H

001FF0H

FF1238H

CS2

RD
SRWR
2clk

NDCLE
NDALE

NDCE
NDRE
2clk

NDWE
NDR/B
D15 ∼ D0

IN (Program)

OUT (NAND Flash)

Figure 3.11.3 Read/Write Access to NAND Flash

92CZ26A-241

IN (Program)

TMP92CZ26A

3.11.3

ECC Control

NAND Flash memory devices may inherently include error bits. It is therefore necessary to
implement the error correction processing using ECC (Error Correction Code).
Figure 3.11.4 shows a basic flowchart for ECC control.

Data Write

Data Read

Valid data write to
NAND Flash

Valid data read from
NAND Flash

Valid data write to
ECC generator

Valid data write to
ECC generator

ECC read
from ECC generator

ECC read from
NAND Flash

Write ECC to
NAND Flash

ECC read from
ECC circuit

END

Yes
Is there error?

Error correction
process

No

END

Figure 3.11.4 Basic Flow of ECC Control

Write:
1. When data is written to the actual NAND Flash memory, the ECC generator in
the NDFC simultaneously generates ECC for the written data.
2. The ECC is written to the redundant area in the NAND Flash separately from
the valid data.
Read:
1. When data is read from the actual NAND Flash memory, the ECC generator in
the NDFC simultaneously generates ECC for the read data.
2. The ECC for the written data and the ECC for the read data are compared to
detect and correct error bits.

92CZ26A-242

TMP92CZ26A

3.11.3.1 Differences between Hamming Codes and Reed-Solomon Codes
The NDFC includes an ECC generator supporting NAND Flash memory devices of SLC
(or 2LC: two states) type and MLC (or 4LC: four states) type.
The ECC calculation using Hamming codes (supporting SLC) generates 22 bits of ECC
for every 256 bytes of valid data and is capable of detecting and correcting a single-bit error
for every 256 bytes. Error bit detection calculation and correction must be implemented by
software. When using SmartMedia™, Hamming codes should be used.
The ECC calculation using Reed-Solomon codes (supporting MLC) generates 80 bits of
ECC for every 1 byte to 518 bytes of valid data and is capable of detecting and correcting
error bits at four addresses for every 518 bytes. When using Reed-Solomon codes, error bit
detection calculation is supported by hardware and only error bit correction needs to be
implemented by software.
The differences between Hamming codes and Reed-Solomon codes are summarized in
Table 3.11.1.
Table 3.11.1 Differences between Hamming Codes and Reed-Solomon Codes
Hamming
Maximum number of
correctable errors

Reed-Solomon

1 bit

4 addresses
(All the 8 bits at one address are correctable.)

Number of ECC bits

22 bits/256 bytes

80 bits/up to 518 bytes

Error bit detection
method

Software

Hardware

Error bit correction
method

Software

Software

Error bit detection time

Depends on the software to be used.

See the table below.

Others

Supports SmartMedia™.

-

Number of

Reed-Solomon Error Bit

Error Bits

Detection Time (Unit: Clocks)

4

813 (max)

3

648 (max)

2

358 (max)

1

219 (max)

0

1

Notes

These values indicate the total number of clocks for
detecting error bit(s) not including the register read/write
time by the CPU.

92CZ26A-243

TMP92CZ26A
3.11.3.2 Error Correction Methods
Hamming ECC
•

The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error
correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how
to implement error correction on 256 bytes of valid data using 22 bits of ECC.

•

If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction
process must be repeated several times to cover the entire page.

1) The calculated ECC and the ECC in the redundant area are rearranged, respectively,
so that the lower 2 bytes represent line parity (LPR15:0) and the upper 1 byte (of which
the upper 6 bits are valid) represents column parity (CPR7:2).
2) The two rearranged ECCs are XORed.
3) If the XOR result is 0 indicating an ECC match, the error correction process ends
normally (no error). If the XOR result is other than 0, it is checked whether or not the
error data can be corrected.
4) If the XOR result contains only one ON bit, it is determined that a single-bit error
exists in the ECC data itself and the error correction process terminates here (error not
correctable).
5) If each pair of bits 0 to 21 of the XOR result is either 01B or 10B, it is determined that
the error data is correctable and error correction is performed accordingly. If the XOR
result contains either 00B or 11B, it is determined that the error data is not correctable
and the error correction process terminates here.
An Example of Correctable

An Example of Uncorrectable

XOR Result

XOR Result

26a65a

2ea65a

Hexadecimal
Binary

10 01 10 00 Column parity

10 11 10 00

Column parity

10 10 01 10

10 10 01 10

Line parity

Line parity

01 01 10 10

01 01 10 10

6) The line and bit positions of the error are detected using the line parity and column
parity of the XOR result, respectively. The error bit thus detected is then inverted. This
completes the error correction process.

Example: When the XOR result is 26a65aH
Convert two bytes of line parity into one byte (10→1, 01→0).
Convert six bits of column parity into three bits (10→1、01→0).
Line parity:

10 10 01 10 01 01 10 10
1 1 0 1 0 0 1 1 = 212

Column parity:

*Error at address 212

10 01 10
1 0 1 =5

*Error in bit 5

Based on the above, error correction is performed by inverting the data in bit 5 at address 212.

92CZ26A-244

TMP92CZ26A

Reed-Solomon ECC
•

The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be
used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated
several times to cover the entire page.

•

Basically no calculation is needed for error correction. If error detection is performed properly, the NDFC
only needs to refer to the error address and error bit. However, it may be necessary to convert the error
address, as explained below.

1) If the error address indicated by the NDRSCAn register is in the range of 000H to
007H, this error exists in the ECC area and no correction is needed in this case.
(It is not able to correct the error in the ECC area. However, if the error exists in the
ECC area, only 4symbol (include the error in the ECC area) can correct the error to this
LSI. Please be careful.)
2) If the error address indicated by the NDRSCAn register is in the range of 008H to
20DH, the actual error address is obtained by subtracting this address from 20 DH.
(If the valid data is processed as 512 byte, the actual error address is obtained by
subtracting this address from 207H when the error address in the range of 008H to
207H.)
Example 1:
NDRSCAn = 005H, NDRSCDn = 04H = 00000100B
As the error address (005H) is in the range of 000H to 007H, no correction is needed.
(Although an error exists in bit 2, no correction is needed.)
Example 2:
NDRSCAn = 083H, NDRSCDn = 81H = 10000001B
The actual error address is obtained by subtracting 083H from 20DH. Thus, the error correction process inverts
the data in bits 7 and 0 at address 18AH.
(If the valid data is 512 byte, the actual error address is obtained by subtracting 083H from 207H. Thus, the error
correction process inverts the data in bits 7 and 0 at address 184H.)

Note:

If the error address (after converted) is in the range of 000H to 007H, it indicates that an error bit exists in
redundant area (ECC). In this case, no error correction is needed. If the number of error bits is not more
than 4 symbols, Reed-Solomon codes calculate each error bit precisely even if it is the redundant area
(ECC).

92CZ26A-245

TMP92CZ26A
3.11.4

Description of Registers
NAND Flash Control 0 Register
7

6

5

4

3

2

1

0

NDFMCR0
(08C0H)

bit Symbol

WE

ALE

CLE

CE0

CE1

ECCE

BUSY

ECCRST

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R

W

Read-modifywrite
instructions
cannot be
used.

After reset

0
WE
enable

0
ALE
control

0
CLE
control

0
CE0
control

0
CE1
control

0

0: Disable
1: Enable

0: “L” out
1: “H” out

0: “L” out
1: “H” out

0: “H” out
1: “L” out

0: “H” out
1: “L” out

0
NAND
Flash
state
1: Busy
0: Ready

(08C1H)

Function

bit Symbol

Read-modifywrite
instructions
cannot be
used.

15

14

13

SPLW1

SPLW0

SPHW1

Read/Write
After reset

Function

ECC circuit
control
0: Disable
1: Enable

0
ECC
reset
control
0: −
1: Reset
*Always
read as
“0”.

12

11

10

9

8

SPHW0

RSECCL

RSEDN

RSESTA

RSECGW

W

R/W

R/W
0
0
0
0
0
Strobe pulse width
Strobe pulse width
Reed(Low width of NDRE , (High width of NDRE ,
Solomon
NDWE )
NDWE )
ECC
latch
Inserted width
Inserted width
= (fSYS) × (set value)
= (fSYS) × (set value)
0: Disable
1: Enable

0

0

0

ReedSolomon
operation
0: Encode
(Write)
1: Decode
(Read)

ReedSolomon
error
calculation
start
0: −
1: Start
*Always
read as
“0”.

ReedSolomon
ECC
generator
write
control
0: Disable
1: Enable

Figure 3.11.5 NAND Flash Mode Control 0 Register
(a) 
The  bit is used for both Hamming and Reed-Solomon codes.
When NDFMCR1=“0”, setting this bit to “1” clears the Hamming ECC in the
ECC generator. When NDFMCR1=“1”, setting this bit to “1” clears the
Reed-Solomon ECC. Note that this bit is ineffective when NDFMCR0=“0”. Before
writing to this bit, ensure that NDFMCR0=“1”.
(b) 
The  bit is used for both Hamming and Reed-Solomon codes.
This bit is used to check the state of the NAND Flash memory (NDR/B pin). It is set to “1”
when the NAND Flash is “busy” and to “0” when it is “ready”.
Since the NDFC incorporates a noise filter of several states, a change in the NDR/B pin
state is reflected on the  flag after some delay. It is therefore necessary to inert a
delay time by software (e.g. ten NOP instructions) before checking this flag.
Read
command

Address input

Delay
time

NDWE pin
NDCLE pin
NDALE pin
NDR/B pin
 flag

92CZ26A-246

Sensing  flag

TMP92CZ26A

(c) 
The  bit is used for both Hamming and Reed-Solomon codes.
This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC
generator (to set  to “1”), the ECC generator must be enabled ( = “1”).
(d) , , 
The , , and  bits are used for both Hamming and Reed-Solomon
codes to control the pins of the NAND Flash memory.
(e) 
The  bit is used for both Hamming and Reed-Solomon codes to enable or disable
write operations.
(f)



The  bit is used only for Reed-Solomon codes. When Hamming codes are used,
this bit should be set to “0”.
Since valid data and ECC are processed differently, the NDFC needs to know whether
valid data or ECC is to be read. This control is implemented by software using this bit.
To read valid data from the NAND Flash, set  to “0”. To read ECC written in
the redundant area in the NAND Flash, set  to “1”.

Note 1:

Valid data and ECC cannot be read continuously by DMA transfer. After valid data has been read, DMA
transfer should be stopped once to change the  bit from “0” to “1” before ECC can be read.

Note 2:

Immediately after ECC is read from the NAND Flash, the NAND Flash access operation or error bit
calculation cannot be performed for a duration of 20 system clocks (fSYS). It is necessary to insert 20 NOP
instructions or the like.

(g) 
The  bit is used only for Reed-Solomon codes.
The error address and error bit position are calculated using an intermediate code
generated from the ECC for written data and the ECC for read data. Setting  to
“1” starts this calculation.
(h) 
The  bit is used only for Reed-Solomon codes. When using Hamming codes, this
bit should be set to “0”.
For a write operation, this bit should be set to “0” (encode) to generate ECC. The ECC
read from the NDECCRDn register is written to the redundant area in the NAND Flash.
For a read operation, this bit should be set to “1” (decode). In this case, valid data is read
from the NAND Flash and the ECC written in the redundant area is also read to generate
an intermediate code for calculating the error address and error bit position.

92CZ26A-247

TMP92CZ26A

(i)



The  bit is used only for Reed-Solomon codes. When using Hamming codes,
this bit should be set to “0”.
The Reed-Solomon processing unit is comprised of two elements: an ECC generator and
an ECC calculator. The latter is used to calculate the error address and error bit position.
The error address and error bit position are calculated using an intermediate code
generated from the ECC for written data and the ECC for read data. At this time, no special
care is needed if ECC generation and error calculation are performed serially. If these
operations need to be performed parallely, the intermediate code used for error calculation
must be latched while the calculation is being performed. The  bit is provided to
enable this latch operation.
When  is set to “1”, the intermediate code is latched so that the ECC
generator can generate the ECC for another page without problem while the ECC
calculator is calculating the error address and error bit position. At this time, the ECC
generator can perform both encode (write) and decode (read) operations.
When  is set to “0”, the latch is released and the contents of the ECC
calculator are updated as the data in the ECC generator is updated.

Reed-Solomon
ECC
Generator

NDECCRDn
Register

Flow of data
F/F 80bit

=1 Latch_ON
=0 Latch_OFF

Reed-Solomon
ECC
Calculator

(j)



The  bits are used for both Hamming and Reed-Solomon codes.
These bits are used to specify the High width of the NDRE and NDWE signals. The High
width to be inserted is obtained by multiplying the value set in these bits by f SYS.
(k) 
The  bits are used for both Hamming and Reed-Solomon codes.
These bits are used to specify the Low width of the NDRE and NDWE signals. The Low
width to be inserted is obtained by multiplying the value set in these bits by fSYS.

92CZ26A-248

TMP92CZ26A
NAND Flash Control 1 Register
NDFMCR1
(08C2H)

7

6

bit Symbol

INTERDY

Read/Write

R/W

After reset

0
Ready
interrupt
0: Disable
1: Enable

Function

(08C3H)

bit Symbol

5

2

1

0

INTRSC

BUSW

ECCS

SYSCKE

R/W

R/W

R/W

R/W

0
ReedSolomon
calculation
end
interrupt
0: Disable
1: Enable

0
Data bus
width

0

0
Clock
ECC
control
calculation

0: 8-bit
1: 16-bit

0: Disable
0:Hamming 1: Enable
1: ReedSolomon

15

14

13

STATE3

STATE2

STATE1

Read/Write

4

3

12

11

10

STATE0

SEER1

SEER0

0

Undefined

Undefined

9

8

R

After reset

0

0

Function

0

Status read (See the table below.)

Table 3.11.2 Reed-Solomon Calculation Result Status Table
STATE<3:0>

Meaning

0000

Calculation ended 0 (No error)

0001

Calculation ended 1(5 or more symbols in error; not correctable)

0010

Calculation ended 2 (Error found)

0011
0100~1111

Calculation in progress

Note: The  value becomes effective after the calculation has started.
SEER<1:0>

Meaning

00

1-address error

01

2-address error

10

3-address error

11

4-address error

Note: The  value becomes effective after the calculation has ended.

(a) 
The  bit is used for both Hamming and Reed-Solomon codes.
When using the NDFC, this bit must be set to “1” to enable the system clock. When not
using the NDFC, power consumption can be reduced by setting this bit to “0”.
(b) 
The  bit is used to select whether to use Hamming codes or Reed-Solomon codes.
This bit is set to “0” for using Hamming codes and to “1” for using Reed-Solomon codes. It
is also necessary to set this bit for clearing ECC.
(c) 
The  bit is used for both Hamming and Reed-Solomon codes.
This bit specifies the bus width of the NAND Flash to be accessed (“0” = 8 bits, “1” = 16
bits). No other setting is required in the memory controller.
(d) 
The  bit is used only for Reed-Solomon codes. When using Hamming codes,
this bit should be set to “0”.

92CZ26A-249

TMP92CZ26A
This bit is used to enable or disable the interrupt to be generated when the calculation of
error address and error bit position has ended.
The interrupt is enabled when this bit is set to “1” and disabled when “0”.
(e) 
The  bit is used for both Hamming and Reed-Solomon codes.
This bit is used to enable or disable the interrupt to be generated when the status of the
NDR/B pin of the NAND Flash changes from “busy” (0) to “ready” (1). The interrupt is
enabled when this bit is set to “1” and disabled when “0”.
(f)

、

The  and  bits are used only for Reed-Solomon codes. When using
Hamming codes, they have no meaning.
These bits are used as flags to indicate the result of error address and error bit
calculation. For details, see Table 3.11.2.

92CZ26A-250

TMP92CZ26A

NDFDTR0
(1FF0H)

bit Symbol

7

NAND Flash Data Register 0
6
5
4
3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

15

14

13

12

11

10

9

8

D15

D14

D13

D12

D11

D10

D9

D8

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Read/Write
After reset

R/W

Function

(1FF1H)

bit Symbol

NAND Flash Data Register (7-0)

Read/Write
After reset

R/W

Function

NDFDTR1
(1FF2H)

bit Symbol

NAND Flash Data Register (15-8)

7

NAND Flash Data Register 1
6
5
4
3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

15

14

13

12

11

10

9

8

D15

D14

D13

D12

D11

D10

D9

D8

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Read/Write
After reset

R/W

Function

(1FF3H)

bit Symbol

NAND Flash Data Register (7-0)

Read/Write
After reset
Function

R/W
NAND Flash Data Register (15-8)

Note: Although these registers allow both read and write operations, no flip-flop is incorporated. Since write and
read operations are performed in different manners, it is not possible to read out the data that has been just
written.

Figure 3.11.6 NAND Flash Data Registers (NDFDTR0, NDFDTR1)
Write and read operations to and from the NAND Flash memory are performed by
accessing the NDFDTR0 register. When you write to this register, the data is written to the
NAND Flash. When you read from this register, the data is read from the NAND Flash.
The NDFDTR0 register is used for both channel 0 and channel 1.
A total of 4 bytes are provided as data registers to enable 4-byte DMA transfer. For
example, 4 bytes of data can be transferred from 32-bit internal RAM to 8-bit NAND Flash
memory by DMA operation by setting the destination address as NDFDTR0. (NDFDTR1
cannot be set as the destination address.) The actual DMA operation is performed by first
reading 4 bytes from the internal RAM and then writing 1 byte to the NAND Flash four
times from the lowest address.
To access data in the NAND Flash, be sure to access NDFDTR0 (at address 1FF0). For
details, see Table 3.11.3.

92CZ26A-251

TMP92CZ26A

Table 3.11.3 How to Access the NAND Flash Data Register
Write
Access Data Size

1-byte access

Example of instruction

ld (0x1FF0),a

8-bit NAND Flash

16-bit NAND Flash

Supported

Not supported

2-byte access

ld (0x1FF0),wa

Supported

Supported

4-byte access

ld (0x1FF0),xwa

Supported

Supported

8-bit NAND Flash

16-bit NAND Flash

ld a,(0x1FF0)

Supported

Not supported

2-byte access

ld wa,(0x1FF0)

Supported

Supported

4-byte access

ld xwa,(0x1FF0)

Supported

Supported

Read
Access Data Size

1-byte access

Example of instruction

92CZ26A-252

TMP92CZ26A
NAND Flash ECC Register 0
6
5
4
3

7
NDECCRD0
(08C4H)

(08C5H)

NDECCRD1
(08C6H)

(08C7H)

NDECCRD2
(08C8H)

(08C9H)

NDECCRD3
(08CAH)

(08CBH)

NDECCRD4
(08CCH)

(08CDH)

ECCD4

ECCD3

2

1

0

ECCD2

ECCD1

ECCD0

0

0

bit Symbol
Read/Write
After reset
Function

ECCD7

ECCD6

ECCD5

0

0

0

15

14

13

12

11

10

9

8

bit Symbol
Read/Write
After reset
Function

ECCD15

ECCD14

ECCD13

ECCD12

ECCD11

ECCD10

ECCD9

ECCD8

0

0

0

0

0

7

NAND Flash ECC Register 1
6
5
4
3

R
0
0
0
NAND Flash ECC Register (7-0)

R
0
0
0
NAND Flash ECC Register (15-8)

ECCD4

ECCD3

2

1

0

ECCD2

ECCD1

ECCD0

0

0

bit Symbol
Read/Write
After reset
Function

ECCD7

ECCD6

ECCD5

0

0

0

15

14

13

12

11

10

9

8

bit Symbol
Read/Write
After reset
Function

ECCD15

ECCD14

ECCD13

ECCD12

ECCD11

ECCD10

ECCD9

ECCD8

0

0

0

0

0

7

NAND Flash ECC Register 2
6
5
4
3

R
0
0
0
NAND Flash ECC Register (7-0)

R
0
0
0
NAND Flash ECC Register (15-8)

ECCD4

ECCD3

2

1

0

ECCD2

ECCD1

ECCD0

0

0

bit Symbol
Read/Write
After reset
Function

ECCD7

ECCD6

ECCD5

0

0

0

15

14

13

12

11

10

9

8

bit Symbol
Read/Write
After reset
Function

ECCD15

ECCD14

ECCD13

ECCD12

ECCD11

ECCD10

ECCD9

ECCD8

0

0

0

0

0

7

NAND Flash ECC Register 3
6
5
4
3

R
0
0
0
NAND Flash ECC Register (7-0)

R
0
0
0
NAND Flash ECC Register (15-8)

ECCD4

2

1

0

ECCD1

ECCD0

0

0

ECCD7

ECCD6

ECCD5

0

0

0

15

14

13

12

11

10

9

8

bit Symbol
Read/Write
After reset
Function

ECCD15

ECCD14

ECCD13

ECCD12

ECCD11

ECCD10

ECCD9

ECCD8

0

0

0

0

0

7

NAND Flash ECC Register 4
6
5
4
3

R
0
0
0
NAND Flash ECC Register (7-0)

R
0
0
0
NAND Flash ECC Register (15-8)

bit Symbol

ECCD7

ECCD6

ECCD5

Read/Write
After reset
Function

0

0

0

15

14

13

12

ECCD15

ECCD14

ECCD13

ECCD12

bit Symbol
Read/Write
After reset
Function

ECCD3

ECCD2

bit Symbol
Read/Write
After reset
Function

ECCD4

ECCD3

2

1

0

ECCD2

ECCD1

ECCD0

0

0

R
0
0
0
NAND Flash ECC Register (7-0)

11

10

9

8

ECCD11

ECCD10

ECCD9

ECCD8

0

0

R
0

0

0

0
0
0
NAND Flash ECC Register (15-8)

Figure 3.11.7 NAND Flash ECC Registers

92CZ26A-253

TMP92CZ26A
The NAND Flash ECC register is used to read ECC generated by the ECC generator.
After valid data has been written to or read from the NAND Flash, setting
NDFMCR0 to “0” causes the corresponding ECC to be set in this register. (The
ECC in this register is updated when NDFMCR0 changes from “1” to “0”.)
When Hamming codes are used, 22 bits of ECC are generated for up to 256 bytes of valid
data. In the case of Reed-Solomon codes, 80 bits of ECC are generated for up to 518 bytes of
valid data. A total of 80 bits of registers are provided, arranged as five 16-bit registers.
These registers must be read in 16-bit units and cannot be accessed in 32-bit units.
After ECC calculation has completed, in the case of Hamming codes, the 16-bit line
parity for the first 256 bytes is stored in the NDECCRD0 register, the 6-bit column parity
for the first 256 bytes in the NDECCRD1 register (), the 16-bit line parity for
the second 256 bytes in the NDECCRD2 register, and the 6-bit column parity for the second
256 bytes in the NDECCRD3 register (). In this case, the NDECCRD4 register
is not used.
In the case of Reed-Solomon codes, 80 bits of ECC are stored in the NDECCRD0,
NDECCRD1, NDECCRD2, NDECCRD3 and NDECCRD4 registers.
Note: Before reading ECC from the NAND Flash ECC register, be sure to set NDFMCR0 to “0”.
The ECC in the NAND Flash ECC register is updated when NDFMCR0 changes from “1” to
“0”. Also note that when the ECC in the ECC generator is reset by NDFMCR0, the
contents of this register are not reset.
Register Name

Hamming

Reed-Solomon

NDECCRD0

[15:0] Line parity
(for the first 256 bytes)

[15:0]
Reed-Solomon ECC code 79:64

NDECCRD1

[7:2] Column parity
(for the first 256 bytes)

[15:0]
Reed-Solomon ECC code 63:48

NDECCRD2

[15:0] Line parity
(for the second 256 bytes)

[15:0]
Reed-Solomon ECC code 47:32

NDECCRD3

[7:2] Column parity
(for the second 256 bytes)

[15:0]
Reed-Solomon ECC code 31:16

NDECCRD4

Not in use

[15:0]
Reed-Solomon ECC code 15:0

The table below shows an example of how ECC is written to the redundant area in the
NAND Flash memory when using Reed-Solomon codes.
When using Hamming codes with SmartMedia™, the addresses of the redundant area
are specified by the physical format of SmartMedia™. For details, refer to the
SmartMedia™ Physical Format Specifications.
Register Name

Reed-Solomon

NAND Flash Address

NDECCRD0

[15:0]
Reed-Solomon ECC code 79:64

Upper 8 bits [79:72]→ address 518
Lower 8 bits [71:64] → address 519

NDECCRD1

[15:0]
Reed-Solomon ECC code 63:48

Upper 8 bits [63:56] → address 520
Upper 8 bits [55:48] → address 521

NDECCRD2

[15:0]
Reed-Solomon ECC code 47:32

Upper 8 bits [47:40] → address 522
Lower 8 bits [39:32] → address 523

NDECCRD3

[15:0]
Reed-Solomon ECC code 31:16

Upper 8 bits [31:24] → address 524
Lower 8 bits [23:16] → address 525

NDECCRD4

[15:0]
Reed-Solomon ECC code 15:0

Upper 8 bits [15:8] → address 526
Lower 8 bits [7:0] → address 527

92CZ26A-254

TMP92CZ26A

NAND Flash Reed-Solomon Calculation Result Address Register
7
6
5
4
3
2
NDRSCA0
(08D0H)

bit Symbol

RS0A7

RS0A6

RS0A5

RS0A4

0

0

0

0

Read/Write
After reset

0

RS0A2

RS0A1

RS0A0

0

0

0

0

R

Function

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)

15
(08D1H)

1

RS0A3

14

13

12

11

10

bit Symbol

9

8

RS0A9

RS0A8

Read/Write

R

After reset

0

Function

NDRSCA1
(08D4H)

bit Symbol

7

6

5

4

RS1A7

RS1A6

RS1A5

RS1A4

Read/Write
After reset

3

2

1

0

RS1A3

RS1A2

RS1A1

RS1A0

0

0

0

0

R
0

Function

0

0

0

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)

15
(08D5H)

14

13

12

11

10

bit Symbol

9

0

7

6

5

4

3

2

1

0

RS2A7

RS2A6

RS2A5

RS2A4

RS2A3

RS2A2

RS2A1

RS2A0

0

0

0

0

0

0

0

0

Read/Write

R

Function

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)

15
(08D9H)

14

13

12

11

10

bit Symbol

9

0

7

6

5

4

3

2

1

0

RS3A7

RS3A6

RS3A5

RS3A4

RS3A3

RS3A2

RS3A1

RS3A0

0

0

0

0

0

0

0

0

Read/Write

R

Function

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)

15
(08DDH)

0

NAND Flash ReedSolomon Calculation
Result Address
Register (9-8)

Function

After reset

RS2A8
R

After reset

bit Symbol

8

RS2A9

Read/Write

NDRSCA3
(08DCH)

0

NAND Flash ReedSolomon Calculation
Result Address
Register (9-8)

Function

After reset

RS1A8
R

After reset

bit Symbol

8

RS1A9

Read/Write

NDRSCA2
(08D8H)

0

NAND Flash
Reed-Solomon
Calculation Result
Address Register (9-8)

14

13

12

bit Symbol

11

10

9

8

RS3A9

RS3A8

Read/Write

R

After reset

0

0

NAND Flash ReedSolomon Calculation
Result Address
Register (9-8)

Function

Figure 3.11.8 NAND Flash Reed-Solomon Calculation Result Address Register

92CZ26A-255

TMP92CZ26A

If error is found at only one address, the error address is stored in the NDRSCA0 register.
If error is found at two addresses, the NDRSCA0 and NDRSCA1 registers are used to store
the error addresses. In this manner, up to four error addresses can be stored in the
NDRSCA0 to NDRSCA3 registers.
The number of error addresses can be checked by NDFMCR1.

NAND Flash Reed-Solomon Calculation Result Data Register
NDRSCD0
(08D2H)

bit Symbol

7

6

5

4

3

2

1

0

RS0D7

RS0D6

RS0D5

RS0D4

RS0D3

RS0D2

RS0D1

RS0D0

0

0

0

0

Read/Write
After reset

R
0

Function
NDRSCD1
(08D6H)

bit Symbol

0

7

6

5

4

RS1D7

RS1D6

RS1D5

RS1D4

bit Symbol

0

0

0

0

7

6

5

4

RS2D7

RS2D6

RS2D5

RS2D4

0

Function

0

RS1D3

RS1D2

RS1D1

RS1D0

0

0

0

0

3

2

1

0

RS2D3

RS2D2

RS2D1

RS2D0

0

0

0

0

0

0

0

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)

7

6

5

4

3

2

1

0

RS3D7

RS3D6

RS3D5

RS3D4

RS3D3

RS3D2

RS3D1

RS3D0

0

0

0

0

Read/Write
After reset

1

R

Function
bit Symbol

2

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)

Read/Write
After reset

3
R

Function

NDRSCD3
(08DEH)

0

Read/Write
After reset

NDRSCD2
(08DAH)

0

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)

R
0

0

0

0

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)

Figure 3.11.9 NAND Flash Reed-Solomon Calculation Result Data Register
If error is found at only one address, the error data is stored in the NDRSCD0 register. If error
is found at two addresses, the NDRSCD0 and NDRSCD1 registers are used to store the error
data. In this manner, the error data at up to four addresses can be stored in the NDRSCD0 to
NDRSCD3 registers.
The number of error addresses can be checked by NDFMCR1.

92CZ26A-256

TMP92CZ26A
3.11.5

An Example of Accessing NAND Flash of SLC Type
1.

Initialization
;
; ***** Initialize NDFC *****
;
Conditions: 8-bit bus, CE0, SLC, 512 (528) bytes/page, Hamming codes
;
ld
ld

2.

(ndfmcr1),0001h ; 8-bit bus, Hamming ECC, SYSCK-ON
(ndfmcr0),2000h ; SPLW1:0=0, SPHW1:0=2

Write
Writing valid data
; ***** Write valid data*****
;
ldw
ldw
ld

(ndfmcr0),2010h ; CE0 enable
(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),80h
; Serial input command

ldw
ld
ldw

(ndfmcr0),20D0h ; ALE enable
(ndfdtr0),xxh
; Address write (3 or 4 times)
(ndfmcr0),2095h ; Reset ECC, ECCE enable, CE0 enable

ld

(ndfdtr0),xxh

; Data write (512 times)

Generating ECC → Reading ECC
; ***** Read ECC *****
;
ldw

(ndfmcr0),2010h ; ECC circuit disable

ldw

xxxx,(ndeccrd0)

; Read ECC from internal circuit

ldw

1’st Read:
xxxx,(ndeccrd1)

D15-0 > LPR15:0
For first 256 bytes
; Read ECC from internal circuit

2’nd Read:

D15-0 > FFh+CPR5:0+11b For first 256 bytes

ldw

xxxx,(ndeccrd0)

; Read ECC from internal circuit

ldw

3’rd Read:
xxxx,(ndeccrd1)

D15-0 > LPR15:0
For second 256 bytes
; Read ECC from internal circuit

4’th Read:

D15-0 > FFh+CPR5:0+11b For second 256 bytes

;
;
;
;

Writing ECC to NAND Flash
; ***** Write dummy data & ECC*****
;
ldw
(ndfmcr0),2090h ; ECC circuit disable, data write mode
ld

(ndfdtr0),xxh

; Redundancy area data write (16 times)

;

Write to D520:

LPR7:0

> D7-0

For second 256 bytes

;

Write to D521:

LPR15:8

> D7-0

For second 256 bytes

;

Write to D522:

CPR5:0+11b

> D7-0

For second 256 bytes

;

Write to D525:

LPR7:0

> D7-0

For first 256 bytes

;

Write to D526:

LPR15:8

> D7-0

For first 256 bytes

;

Write to D527:

CPR5:0+11b

> D7-0

For first 256 bytes

92CZ26A-257

TMP92CZ26A
Executing page program
; ***** Set auto page program*****
;

;
;

ldw
ld

(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),10h
; Auto page program command

ldw

(ndfmcr0),2010h ; WE disable, CLE disable

Wait setup time (from Busy to Ready)

;
;
;

1. Flag polling
2. Interrupt

Reading status
; ***** Read Status*****
;
ldw
ld

(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),70h
; Status read command

ldw
ld

(ndfmcr0),2010h ; WE disable, CLE disable
xx,(ndfdtr0)
; Status read

92CZ26A-258

TMP92CZ26A
3.

Read
Reading valid data
; ***** Read valid data*****
;
ldw
(ndfmcr0),2010h ; CE0 enable

;
;

ldw
ld
ldw

(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),00h
; Read command
(ndfmcr0),20D0h ; ALE enable

ld

(ndfdtr0),xxh

; Address write (3 or 4 times)

Wait setup time (from Busy to Ready)

;
;
;

1. Flag polling
2. Interrupt
ldw
ld
ldw

(ndfmcr0),2015h ; Reset ECC, ECCE enable, CE0 enable
xx,(ndfdtr0)
; Data read (512 times)
(ndfmcr0),2010h ; ECC circuit disable

ld
ld
ld

xx,(ndfdtr0)
xx,(ndfdtr0)
xx,(ndfdtr0)

; Redundancy data read (8 times)
; ECC data read (3 times)
; Redundancy data read (2 times)

ld

xx,(ndfdtr0)

; ECC data read (3 times)

Generating ECC → Reading ECC
; ***** Read ECC *****
;
ldw
(ndfmcr0),2010h ; ECC circuit disable
ldw

xxxx,(ndeccrd0)

; Read ECC from internal circuit

ldw

1’st Read:
xxxx,(ndeccrd1)

D15-0 > LPR15:0
For first 256 bytes
; Read ECC from internal circuit

ldw

2’nd Read:
xxxx,(ndeccrd0)

D15-0 > FFh+CPR5:0+11b For first 256 bytes
; Read ECC from internal circuit

3’rd Read:

D15-0 > LPR15:0

ldw

xxxx,(ndeccrd1)

; Read ECC from internal circuit

4’th Read:

D15-0 > FFh+CPR5:0+11b For second 256 bytes

;
;
;
;

For second 256 bytes

Software processing
The ECC data generated for the read operation and the ECC in the
redundant area in the NAND Flash are compared. If any error is found, the
error processing routine is performed to correct the error data. For details,
see 3.11.3.2 “Error Correction Methods”.

92CZ26A-259

TMP92CZ26A
4.

ID Read
The ID read routine is as follows:
ldw
ld
ldw

(ndfmcr0),20B0h ; WE Enable, CLE enable
(ndfdtr0),90h
; Write ID read command
(ndfmcr0),20D0h ; ALE enable, CLE disable

ld
ldw
ld

(ndfdtr0),00h
; Write 00
(ndfmcr0),2010h ; WE disable, CLE disable
xx,(ndfdtr0)
; Read 1'st ID maker code

ld

xx,(ndfdtr0)

; Read 2'nd ID device code

92CZ26A-260

TMP92CZ26A
3.11.6

An Example of Accessing NAND Flash of MLC Type (When the valid data is processed
as 518byte)
1.

Initialization
;
; ***** Initialize NDFC *****
;
;

2.

Conditions: 16-bit bus, CE1, MLC, 2048 (2112) bytes/page, Reed-Solomon codes
ld

(ndfmcr1),0007h ; 16-bit bus, Reed-Solomon ECC, SYSCK-ON

ld

(ndfmcr0),5000h ; SPLW1:0=1, SPHW1:0=1

Write
Writing valid data
; ***** Write valid data*****
;
ldw
ldw
ldw

(ndfmcr0),5008h ; CE1 enable
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0080h ; serial input command

ldw
ldw
ldw

(ndfmcr0),50C8h ; ALE enable
(ndfdtr0),00xxh ; Address write ( 4 or 5 times)
(ndfmcr0),508Dh ; Reset ECC code, ECCE enable

ldw

(ndfdtr0),xxxxh

; Data write (259-times/:518byte)
(256-times/512byte)

Generating ECC → Reading ECC
; ***** Read ECC *****
;
ldw
(ndfmcr0),5008h ; ECC circuit disable
ldw
ldw
ldw

(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0080h ; serial input command
(ndfmcr0),50C8h ; ALE enable

ldw

(ndfdtr0),00xxh

; Address write ( 4 or 5 times)

ldw

xxxx,(ndeccrd0)

; Read ECC from internal circuit

ldw

Read:
D79-64
xxxx,(ndeccrd1) ; Read ECC from internal circuit

;
;

Read:
ldw

xxxx,(ndeccrd2)

ldw

Read:
D47-32
xxxx,(ndeccrd3) ; Read ECC from internal circuit

ldw

Read:
D31-16
xxxx,(ndeccrd4) ; Read ECC from internal circuit

;
;
;

D63-48

Read:

; Read ECC from internal circuit

D15-0

92CZ26A-261

TMP92CZ26A

Writing ECC to NAND Flash
; ***** Write dummy data & ECC *****
;
ldw
(ndfmcr0),5088h ; ECC circuit disable, data write mode
ldw

(ndfdtr0),xxxxh

ldw

Write to 207-206hex address:
> D79-64
(ndfdtr1),xxxxh ; Redundancy area data write

ldw

Write to 209-208hex address:
> D63-48
(ndfdtr0),xxxxh ; Redundancy area data write

;
;
;

; Redundancy area data write

Write to 20B-20Ahex address:

> D47-32

ldw

(ndfdtr1),xxxxh

ldw

Write to 20D-20Chex address:
> D31-16
(ndfdtr0),xxxxh ; Redundancy area data write

;
;

; Redundancy area data write

Write to 20F-20Ehex address:

> D15-0

;
;

The write operation is repeated four times to write 2112 bytes.

Executing page program
; ***** Set auto page program*****
;

;
;

ldw
ldw

(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0010h ; Auto page program command

ldw

(ndfmcr0),5008h ; WE disable, CLE disable

Wait set up time (from Busy to Ready)

;
;

1. Flag polling
2. Interrupt
※

In case of LB type NANDF, programming page size is normally each 2112
bytes and ECC calculation is processed each 518 (512) bytes. Please take care
of programming flow. In details, refer the NANDF memory specifications.

Reading status
; ***** Read status*****
;
ldw
(ndfmcr0),50A8h ; WE enable, CLE enable
ldw
ldw
ldw

(ndfdtr0),0070h ; Status read command
(ndfmcr0),5008h ; WE disable, CLE disable
xxxx,(ndfdtr0)
; Status read

92CZ26A-262

TMP92CZ26A
3.

Read (including ECC data read)
Reading valid data
; ***** Read valid data*****
;

;
;

ldw
ldw
ldw

(ndfmcr0),5008h ; CE1 enable
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0000h ; Read command 1

ldw
ldw
ldw

(ndfmcr0),50C8h ; ALE enable
(ndfdtr0),00xxh ; Address write (4 or 5 times)
(ndfmcr0),50A8h ; WE enable, CLE enable

ldw

(ndfdtr0),0030h

; Read command 2

Wait set up time (from Busy to Ready)

;
;
;

1. Flag polling
2. Interrupt
ldw
ldw

(ndfmcr0),540Dh ; ECC reset, ECC circuit enable, decode mode
xxxx,(ndfdtr0)
; Data read (259 times: 518 bytes)
(256-times:512byte)

ldw
ldw

(ndfmcr0),550Ch ; RSECGW enable
xxxx,(ndfdtr0)
; Read ECC (5 times: 80 bits)

;
;
;

Wait set up time (20 system clocks)

(1) Error bit calculation
ldw
ldw

(ndfmcr1),0047h ; Error bit calculation interrupt enable
(ndfmcr0),560Ch ; Error bit calculation circuit start

;
;
;
;

Wait set up time
Interrupt routine (End of calculation for Reed-Solomon Error bit)

INT:
;

ldw

;
;
;

If error is found, the error processing routine is performed to
correct the error data. For details see 3.11.3.2 “Error Correction
Methods”.

xxxx,(ndfmcr1)

; Check error status ”STATE3:0, SEER1:0”

;
;

The read operation is repeated four times to read 2112 bytes.

;

92CZ26A-263

TMP92CZ26A
4.

ID Read
The ID read routine is as follows:
ldw
ldw

(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0090h ; Write ID read command

ldw
ldw
ldw

(ndfmcr0),50C8h ; ALE enable, CLE disable
(ndfdtr0),0000h ; Write 00
(ndfmcr0),5008h ; WE disable, CLE disable

ldw
ldw

xxxx,(ndfdtr0)
xxxx,(ndfdtr1)

; Read 1'st ID maker code
; Read 2'ndID device code

92CZ26A-264

TMP92CZ26A

3.11.7

An Example of Connections with NAND Flash

TMP92CZ26A

100KΩ

NAND Flash 0

NAND Flash 1

NDCLE
NDALE

CLE
ALE

CLE
ALE

NDRE
NDWE

RE
WE

RE
WE

R/B (open drain)

R/B (open drain)

I/O[15:0]

I/O[7:0]

2KΩ
NDR/B
D[15:0]

CE

WP

CE

WP

ND0CE
ND1CE

External circuits for Write Protect

Note 1: A reset sets the NDRE and NDWE pins as input ports, so pull-up resistors are needed.
Note 2: The pull-up resistor value for the NDR/B pin must be set appropriately according to the NAND Flash memory to be used and the
capacity of the board (typical: 2 KΩ).
Note 3: The

WP

(Write Protect) pin of NAND Flash is not supported. When this function is needed, prepare it on an external circuit.

Figure 3.11.10 An Example of Connections with NAND Flash

92CZ26A-265

TMP92CZ26A

3.12

8 Bit Timer (TMRA)
The TMP92CZ26A features 8 channel (TMRA0 to TMRA7) built-in 8-bit timers.

These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each
module consists of 2 channels and can operate in any of the following 4 operating modes.
•

8-bit interval timer mode

•

16-bit interval timer mode

•

8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle
with variable period)

•

8-bit pulse width modulation output mode (PWM – Variable duty cycle with constant
period)

Figure 3.12.1 to Figure 3.12.4 show block diagrams for TMRA01 to TMRA67.
Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register.
In addition, a timer flip-flop and a prescaler are provided for each pair of channels.
The operation mode and timer flip-flops are controlled by 5bytes registers SFRs
(Special-function registers).
Each of the 4 modules (TMRA01 to TMRA67) can be operated independently. All modules
operate in the same manner; hence only the operation of TMRA01 is explained here.
The contents of this chapter are as follows.

Table 3.12.1 Registers and Pins for Each Module
Module
Specification
Input pin for external
External

clock

pin

Output pin for timer
flip-flop
Timer run register

SFR
(Address)

Timer register
Timer mode register
Timer flip-flop
control register

TMRA01

TMRA23

TMRA45

TMRA67
Low-frequency clock

TA0IN

TA2IN

Low-frequency clock

(Shared with PC1)

(Shared with PC3)

fs

fs

TA1OUT

TA3OUT

TA5OUT

TA7OUT

(Shared with PM1)

(Shared with PP1)

(Shared with PP2)

(Shared with PP3)

TA01RUN (1100H)

TA23RUN (1108H)

TA45RUN (1110H)

TA67RUN (1118H)

TA0REG (1102H)

TA2REG (110AH)

TA4REG (1112H)

TA6REG (111AH)

TA1REG (1103H)

TA3REG (110BH)

TA5REG (1113H)

TA7REG (111BH)

TA01MOD (1104H)

TA23MOD (110CH)

TA45MOD (1114H)

TA67MOD (111CH)

TA1FFCR (1105H)

TA3FFCR (110DH)

TA5FFCR (1115H)

TA7FFCR (111DH)

92CZ26A-266

External input
clock: TA0IN

Prescaler
clock
φT0TMR

φT4

8

Selector

4

Figure 3.12.1 TMRA01 Block Diagram

92CZ26A-267

TA01RUN


φT256

8-bit timer register
TA0REG

8-bit up counter
(CP0)

Internaldata bus

Register
buffer 0

n

2
Over
flow

Run/clear

TMRA0
Interrupt output:
INTTA0

8-bit timer
register
TA1REG

8-bit comparator
(CP1)

8-bit up counter
(UC1)

TA01RUN

TMRA0
Internal data bus
Interrupt output:
TA0TRG

TA01MOD


TA0TRG

Selector

TA01MOD


φT1
φT16
φT256

TA01RUN


Match detect

TA01MOD


8-bit up counter
(UC0)

TA01RUN

φT16

16 32 64 128 256 512

TA01MOD


φT1
φT4
φT16

φT1

2

Prescaler

TMRA1
Interrupt output:
INTTA1

Match
detect

TA1FFCR

Timer
flip-flop
TA1FF

Timer flip-flop
output: TA1OUT

TMP92CZ26A

3.12.1 Block Diagram

External input
clock: TA2IN

Prescaler
clock
φT0TMR
φT4

8

Selector

4

Figure 3.12.2 TMRA23 Block Diagram

92CZ26A-268

TA23RUN


φT256

8-bit timer register
TA2REG

8-bit comparator
(CP2)

Internal data bus

Register
buffer 2

n

2
Over
flow

Run/clear

TMRA2
Interrupt output:
INTTA2

TMRA2
Internal data bus
Interrupt output:
TA2TRG

8-bit timer
register
TA3REG

8-bit comparator
(CP3)

8-bit
up comparator
(UC3)

TA3FFCR

Timer
flip-flop
TA3FF

TMRA3
Interrupt output:
INTTA3

Match
detect

TA23RUN

TA23MOD


Selector

TA23MOD


TA2TRG

φT1
φT16
φT256

TA23RUN


Match detect

TA23MOD


8-bit up counter
(UC2)

TA23RUN

φT16

16 32 64 128 256 512

TA23MOD


φT1
φT4
φT16

φT1

2

Prescaler

Timer flip-flop
output: TA3OUT

TMP92CZ26A

Lowfrequency
clock (fs)

Prescaler
clock
φT0TMR
φT4

8

Selector

4

Figure 3.12.3 TMRA45 Block Diagram

92CZ26A-269

TA45RUN


φT256

8-bit timer register
TA4REG

8-bit comparator
(CP4)

Internal data bus

Register
buffer 4

n

2
Over
flow

Run/clear

TMRA4
Interrupt output:
INTTA4

TMRA4
Internal data bus
Interrupt output:
TA4TRG

8-bit timer
register
TA5REG

8-bit comparator
(CP5)

8-bit
up comparator
(UC5)

TA5FFCR

Timer
flip-flop
TA5FF

TMRA5
Interrupt output:
INTTA5

Match
detect

TA45RUN

TA45MOD


Selector

TA45MOD


TA4TRG

φT1
φT16
φT256

TA45RUN


Match detect

TA45MOD


8-bit up counter
(UC4)

TA45RUN

φT16

16 32 64 128 256 512

TA45MOD


φT1
φT4
φT16

φT1

2

Prescaler

Timer flip-flop
output: TA5OUT

TMP92CZ26A

Lowfrequency
clock (fs)

Prescaler
clock
φT0TMR

φT4

8

Selector

4

Figure 3.12.4 TMRA67 Block Diagram

92CZ26A-270

TA67RUN


φT256

8-bit timer register
TA6REG

8-bit comparator
(CP6)

Internal data bus

Register
buffer 6

n

2
Over
flow

Run/clear

TMRA6
Interrupt output:
INTTA6

TMRA6
Internal data bus
Interrupt output:
TA6TRG

8-bit timer
register
TA7REG

8-bit comparator
(CP7)

8-bit
up comparator
(UC7)

TA7FFCR

Timer
flip-flop
TA7FF

TMRA7
Interrupt output:
INTTA7

Match
detect

TA67RUN

TA67MOD


Selector

TA67MOD


TA6TRG

φT1
φT16
φT256

TA67RUN


Match detect

TA67MOD


8-bit up counter
(UC6)

TA67RUN

φT16

16 32 64 128 256 512

TA67MOD


φT1
φT4
φT16

φT1

2

Prescaler

Timer flip-flop
output: TA7OUT

TMP92CZ26A

TMP92CZ26A

3.12.2 Operation of Each Circuit
(1) Prescaler
A 9-bit prescaler generates the input clock to TMRA01.The clock φT0 is selected
using the prescaler clock selection register SYSCR0.
The prescaler operation can be controlled using TA01RUN in the timer
control register. Setting  to 1 starts the count; setting  to 0
clears the prescaler to 0 and stops operation. Table shows the various prescaler output
clock resolutions.
(Although the prescaler and the timer counter can be started separately, the timer
counter’s operation depends on the prescaler’s input timing.)

Table 3.12.2 Prescaler Output Clock Resolution
Clock gear

Prescaler of

selection

clock gear

SYSCR1

SYSCR0





Prescaler of TMRA

−

TAxxMOD
φT1(1/2)

φT4(1/8)

φT16(1/32)

φT256(1/512)

000(1/1)

fc/8

fc/32

fc/128

fc/2048

001(1/2)

fc/16

fc/64

fc/256

fc/4096

fc/32

fc/128

fc/512

fc/8192

011(1/8)

fc/64

fc/256

fc/1024

fc/16384

100(1/16)

fc/128

fc/512

fc/2048

fc/32768

000(1/1)

fc/32

fc/128

fc/512

fc/8192

001(1/2)

fc/64

fc/256

fc/1024

fc/16384

010(1/4)

fc

Timer counter input clock

010(1/4)

0(1/2)

1/2

1(1/8)

fc/128

fc/512

fc/2048

fc/32768

011(1/8)

fc/256

fc/1024

fc/4096

fc/65536

100(1/16)

fc/512

fc/2048

fc/8192

fc/131072

(2) Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock
specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (The match detection signal) from
TMRA0.
For each interval timer the timer operation control register bits TA01RUN
 and TA01RUN can be used to stop and clear the up counters
and to control their count. A reset clears both up counters, stopping the timers.

Note: TMR45 and TMR67 can select low-frequency clock(fs) instead of external clock input.

92CZ26A-271

TMP92CZ26A
(3) Timer registers (TA0REG and TA1REG)
These are 8-bit registers, which can be used to set a time interval. When the value
set in the timer register TA0REG or TA1REG matches the value in the corresponding
up counter, the comparator match detect signal goes active. If the value set in the
timer register is 00H, the signal goes active when the up counter overflows.
The TA0REG are double buffer structure, each of which makes a pair with register
buffer.
The setting of the bit TA01RUN determines whether TA0REG’s double
buffer structure is enabled or disabled. It is disabled if  = 0 and enabled if
 = 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when a 2n overflow occurs in PWM mode, or at the start of the PPG cycle
in PPG mode. Hence the double buffer cannot be used in timer mode.
(When using the double buffer, method of renewing timer register is only overflow in
PWM mode or frequency agreement in PPG mode.)
A reset initializes  to 0, disabling the double buffer. To use the double
buffer, write data to the timer register, set  to 1, and write the following
data to the register buffer. Figure 3.12.5 shows the configuration of TA0REG.

Timer registers 0 (TA0REG)
B
Shift trigger
Register buffer 0

Matching detection PPG cycle
n
2 overflow of PWM

Selector
S

A

Write to TA0REG

Write
Internal data bus

TA01RUN

Figure 3.12.5 Configuration of timer register (TA0REG)
Note: The same memory address is allocated to the timer register and the register buffer 0. When
 = 0, the same value is written to the register buffer 0 and the timer register;
when  = 1, only the register buffer 0 is written to.

92CZ26A-272

TMP92CZ26A
(4) Comparator (CP0, CP1)
The comparator compares the value in an up counter with the value set in a timer
register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0
or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is
inverted at the same time.
Note: If a value smaller than the up-counter value is written to the timer register while the timer is counting up, this will
cause the timer to overflow and an interrupt cannot be generated at the expected time. (The value in the timer
register canbe changed without any problem if the new value is larger than the up-counter value.) In 16-bit
interval timer mode, be sure to write to both TA0REG and TA1REG in this order (16 bits in total), The compare
circuit will not function if only the lower 8 bits are set.

(5) Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit
comparator output) of each interval timer.
Whether inversion is enabled or disabled is determined by the setting of the bit
TA1FFCR in the timer flip-flops control register. A reset clears the value
of TA1FF to 0. Writing 01 or 10 to TA1FFCR sets TA1FF to 0 or 1.
Writing 00 to these bits inverts the value of TA1FF. (This is known as software
inversion.)
The TA1FF signal is output via the TA1OUT pin. When this pin is used as the timer
output, the timer flip-flop should be set beforehand using the port function registers.
The condition for TA1FF inversion varies with mode as shown below
8-bit interval timer mode

: UC0 matches TA0REG or UC1 matches TA1REG

16-bit interval timer mode
80bit PWM mode

: UC0 matches TA0REG or UC1 matches TA1REG
n
: UC0 matches TA0REG or a 2 overflow occurs

8-bit PPG mode

: UC0 matches TA0REG or UC0 matches TA1REG

(Select either one of the two)

Note: If an inversion by the match-detect signal and a setting change via the TMRA1 flip-flopcontrol register occur
simultaneously, the resultant operation varies depending on the situation, as shown below.
・ If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the
flip-flop will be inverted only once.
・

If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur
simultaneously, the timer flip-flop will be set to 1.

・

If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur
simultaneously the flip-flop will be cleared to 1.

Be sure to stop the timer before changing the flip-flop incersion setting.
If the setting is chaged while the timer is counting, proper operation cannot be obtained.

92CZ26A-273

TMP92CZ26A

3.12.3 SFR
TMRA01 RUN Register

7

6

5

4

TA0RDE
TA01RUN Bit symbol
Read/Write
R/W
(1100H)
After Reset
0
Function
Double

3
I2TA01
0
In IDLE2

buffer

mode

0: Disable
1: Enable

0: Stop
1: Operate

2

1

TA01PRUN
TA1RUN
R/W
0
0
TMRA01
Up counter
prescaler
(UC1)

0
TA0RUN
0
Up counter
(UC0)

0: Stop and clear
1: Run (Count up)

TA0REG double buffer control
0
Disable
1
Enable

Count control
0
Stop and clear
1
Run (Count up)

Note: The values of bits 4 to 6 of TA01RUN are “1” when read.

TMRA23 RUN Register

7

6

5

4

TA2RDE
TA23RUN Bit symbol
Read/Write
R/W
(1108H)
After Reset
0
Function
Double

3
I2TA23
0
In IDLE2

buffer

mode

0: Disable
1: Enable

0: Stop
1: Operate

TA3REG double buffer control
0
Disable
1
Enable

2

1

TA23PRUN
TA3RUN
R/W
0
0
TMRA23
Up counter
prescaler
(UC3)

0
TA2RUN
0
Up counter
(UC2)

0: Stop and clear
1: Run (Count up)

Count control
0
Stop and clear
1
Run (Count up)

Note: The values of bits 4 to 6 of TA23RUN are “1” when read.

Figure 3.12.6 Register for TMRA (1)

92CZ26A-274

TMP92CZ26A

TMRA45 RUN Register

7

6

5

4

TA4RDE
TA45RUN Bit symbol
Read/Write
R/W
(1110H)
After Reset
0
Function
Double

3
I2TA45
0
In IDLE2

buffer

mode

0: Disable
1: Enable

0: Stop
1: Operate

2

1

TA45PRUN TA5RUN
R/W
0
0
TMRA45
Up counter
prescaler
(UC5)

0
TA4RUN
0
Up counter
(UC4)

0: Stop and clear
1: Run (Count up)

TA4REG double buffer control
0
Disable
1
Enable

Count control
0
Stop and clear
1
Run (Count up)

Note: The values of bits 4 to 6 of TA45RUN are “1” when read.
TMRA67RUN Register

7

6

5

4

TA6RDE
TA67RUN Bit symbol
Read/Write
R/W
(1118H)
After Reset
0
Function
Double

3
I2TA67
0
In IDLE2

buffer

mode

0: Disable
1: Enable

0: Stop
1: Operate

TA6REG double buffer control
0
Disable
1
enable

2

1

TA67PRUN TA7RUN
R/W
0
0
TMRA67
Up counter
prescaler
(UC7)

0
TA6RUN
0
Up counter
(UC6)

0: Stop and clear
1: Run (Count up)

Count control
0
Stop and clear
1
Run (Count up)

Note: The values of bits 4 to 6 of TA67RUN are “1” when read.

Figure 3.12.7 Register for TMRA (2)

92CZ26A-275

TMP92CZ26A
TMRA01 Mode Register

TA01MOD Bit symbol
(1104H)
Read/Write
After reset
Function

7

6

5

4

TA01M1

TA01M0

PWM01

PWM00

3

2

1

0

TA1CLK1

TA1CLK0

TA0CLK1

TA0CLK0

0

0

0

R/W
0

0

0

0

0

Operation mode

PWM cycle

Source clock for TMRA1

Source clock for TMRA0

00: 8-bit timer mode

00: Reserved

00: TA0TRG

00: TA0IN pin

01: 16-bit timer mode

01: 2

6

01: φT1

01: φT1

10: 8-bit PPG mode

10: 2

7

10: φT16

10: φT4

11: 8-bit PWM mode

11: 2

8

11: φT256

11: φT16

TMRA0 input clock



00

TA0IN (External input)

01

φT1

10

φT4

11

φT16

00

Comparator output

TMRA1 input clock
TA01MOD≠01

TA01MOD=01

from TMRA0


φT1

01
10

φT16

11

φT256

Overflow output from TMRA0
(16-bit timer mode)

PWM cycle selection



00

Reserved

01

2 × Clock source

10

2 × Clock source

11

2 × Clock source

6
7
8

TMRA01 operation mode selection



00

8 timer × 2ch

01

16-bit timer

10

8-bit PPG

11

8-bit PWM (TMRA0),
8-bit timer (TMRA1)

Figure 3.12.8 Register for TMRA (4)

92CZ26A-276

TMP92CZ26A
TMRA23 Mode Register

TA23MOD Bit symbol
(110CH)
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

TA23M1

TA23M0

PWM21

PWM20

TA3CLK1

TA3CLK0

TA2CLK1

TA2CLK0

0

0

0

0

0

0

R/W
0

0

Operation mode

PWM cycle

TMRA3 clock for TMRA3

TMRA2 clock for TMRA2

00: 8-bit timer mode

00: Reserved

01: 16-bit timer mode

01: 2

10: 8-bit PPG mode

10: 2

11: 8-bit PWM mode

11: 2

00: TA2TRG

00: TA2IN pin

6

01: φT1

01: φT1

7

10: φT16

10: φT4

8

11: φT256

11: φT16

TMRA2 input clock



00

TA2IN (External input)

01

φT1

10

φT4

11

φT16

00

Comparator output

TMRA3 input clock
TA23MOD≠01

TA23MOD=01

from TMRA2


φT1

01
10

φT16

11

φT256

Overflow output from TMRA2
(16-bit timer mode)

PWM cycle selection



00

Reserved

01

2 × Clock source

10

2 × Clock source

11

2 × Clock source

6
7
8

TMRA23 operation mode selection



00

8 timer × 2ch

01

16-bit timer

10

8-bit PPG

11

8-bit PWM (TMRA2),
8-bit timer (TMRA3)

Figure 3.12.9 Register for TMRA (5)

92CZ26A-277

TMP92CZ26A
TMRA45 Mode Register

TA45MOD Bit symbol
(1114H)
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

TA45M1

TA45M0

PWM41

PWM40

TA5CLK1

TA5CLK0

TA4CLK1

TA4CLK0

0

0

0

0

0

0

R/W
0

0

Operation mode

PWM cycle

TMRA5 clock for TMRA5

TMRA4 clock for TMRA4

00: 8-bit timer mode

00: Reserved

01: 16-bit timer mode

01: 2

10: 8-bit PPG mode

10: 2

11: 8-bit PWM mode

11: 2

00: TA4TRG

00: low-frequency clock

6

01: φT1

01: φT1

7

10: φT16

10: φT4

8

11: φT256

11: φT16

TMRA4 input clock



00

low-frequency clock(fs)

01

φT1

10

φT4

11

φT16

00

Comparator output

TMRA5 input clock
TA45MOD≠01

TA45MOD=01

from TMRA4


φT1

01
10

φT16

11

φT256

Overflow output from TMRA4
(16-bit timer mode)

PWM cycle selection



00

Reserved

01

2 × Clock source

10

2 × Clock source

11

2 × Clock source

6
7
8

TMRA45 operation mode selection



00

8 timer × 2ch

01

16-bit timer

10

8-bit PPG

11

8-bit PWM (TMRA4),
8-bit timer (TMRA5)

Figure 3.12.10 Register for TMRA (6)

92CZ26A-278

TMP92CZ26A
TMRA67 Mode Register

TA67MOD Bit symbol
(111CH)
Read/Write
After reset
Function

7

6

5

4

3

2

1

0

TA67M1

TA67M0

PWM61

PWM60

TA7CLK1

TA7CLK0

TA6CLK1

TA6CLK0

0

0

0

0

0

0

R/W
0

0

Operation mode

PWM cycle

TMRA7 clock for TMRA7

TMRA6 clock for TMRA6

00: 8-bit timer mode

00: Reserved

01: 16-bit timer mode

01: 2

10: 8-bit PPG mode

10: 2

11: 8-bit PWM mode

11: 2

00: TA6TRG

00: low-frequency clock

6

01: φT1

01: φT1

7

10: φT16

10: φT4

8

11: φT256

11: φT16

TMRA6 input clock



00

low-frequency clock(fs)

01

φT1

10

φT4

11

φT16

00

Comparator output

TMRA1 input clock
TA67MOD≠01

TA67MOD=01

from TMRA6


φT1

01
10

φT16

11

φT256

Overflow output from TMRA6
(16-bit timer mode)

PWM cycle selection



00

Reserved

01

2 × Clock source

10

2 × Clock source

11

2 × Clock source

6
7
8

TMRA67 operation mode selection



00

8 timer × 2ch

01

16-bit timer

10

8-bit PPG

11

8-bit PWM (TMRA6),
8-bit timer (TMRA7)

Figure 3.12.11 Register for TMRA (7)

92CZ26A-279

TMP92CZ26A
TMRA1 Flip-Flop Control Register

7
TA1FFCR
(1105H)

6

5

4

Bit symbol

3

2

1

0

TA1FFC1

TA1FFC0

TA1FFIE

TA1FFIS

Read/Write

R/W

After reset

1

Function
Readmodifywrite
instructions
are
prohibited.

R/W
1

0
TA1FF

TA1FF

01: Set TA1FF

control for

inversion

10: Clear TA1FF

inversion

select

11: Don’t care

0: Disable

0: TMRA0

1: Enable

1: TMRA1

Inversion signal for timer flip-flop 1 (TA1FF)
(Don’t care except in 8-bit timer mode)
TA1FFIS

0

Inversion by TMRA0

1

Inversion by TMRA1

Inversion of TA1FF
TA1FFIE

0

Disabled

1

Enabled

Control of TA1FF



0

00: Invert TA1FF

00

Inverts the value of TA1FF (Software inversion)

01

Sets TA1FF to “1”

10

Clears TA1FF to “0”

11

Don’t care

Note: The values of bits 4 to 6 of TA1FFCR are “1” when read.

Figure 3.12.12 Register for TMRA (8)

92CZ26A-280

TMP92CZ26A
TMRA3 Flip-Flop Control Register

7
TA3FFCR
(110DH)

Bit symbol

Readmodifywrite
instructions
are
prohibited.

After reset

6

5

4

3

2

1

0

TA3FFC1

TA3FFC0

TA3FFIE

TA3FFIS

Read/Write

R/W
1

Function

R/W
1

0
TA3FF

TA3FF

01: Set TA3FF

control for

inversion

10: Clear TA3FF

inversion

select

11: Don’t care

0: Disable

0: TMRA2

1: Enable

1: TMRA3

Inversion signal for timer flip-flop 3 (TA3FF)
(Don’t care except in 8-bit timer mode)
TA3FFIS

0

Inversion by TMRA2

1

Inversion by TMRA3

Inversion of TA3FF
TA3FFIE

0

Disabled

1

Enabled

Control of TA3FF



0

00: Invert TA3FF

00

Inverts the value of TA3FF (Software inversion)

01

Sets TA3FF to “1”

10

Clears TA3FF to “0”

11

Don’t care

Note: The values of bits 4 to 6 of TA3FFCR are “1” when read.

Figure 3.12.13 Register for TMRA (9)

92CZ26A-281

TMP92CZ26A
TMRA5 Flip-Flop Control Register

7
TA5FFCR
(1115H)

6

5

4

Bit symbol

3

2

1

0

TA5FFC1

TA5FFC0

TA5FFIE

TA5FFIS

Read/Write

R/W

After reset

1

Function
Readmodifywrite
instructions
are
prohibited.

R/W
1

0
TA5FF

TA5FF

01: Set TA5FF

control for

inversion

10: Clear TA5FF

inversion

select

11: Don’t care

0: Disable

0: TMRA4

1: Enable

1: TMRA5

Inversion signal for timer flip-flop 5 (TA5FF)
(Don’t care except in 8-bit timer mode)
TA5FFIS

0

Inversion by TMRA4

1

Inversion by TMRA5

Inversion of TA5FF
TA5FFIE

0

Disabled

1

Enabled

Control of TA5FF



0

00: Invert TA5FF

00

Inverts the value of TA5FF (Software inversion)

01

Sets TA5FF to “1”

10

Clears TA5FF to “0”

11

Don’t care

Note: The values of bits 4 to 6 of TA5FFCR are “1” when read.

Figure 3.12.14 Register for TMRA (10)

92CZ26A-282

TMP92CZ26A
TMRA7 Flip-Flop Control Register

7
TA7FFCR
(111DH)

6

5

4

Bit symbol

3

2

1

0

TA7FFC1

TA7FFC0

TA7FFIE

TA7FFIS

Read/Write

R/W

After reset

1

Function
Readmodifywrite
instructions
are
prohibited.

R/W
1

0
TA7FF

TA7FF

01: Set TA7FF

control for

inversion

10: Clear TA7FF

inversion

select

11: Don’t care

0: Disable

0: TMRA6

1: Enable

1: TMRA7

Inversion signal for timer flip-flop 7 (TA7FF)
(Don’t care except in 8-bit timer mode)
TA7FFIS

0

Inversion by TMRA6

1

Inversion by TMRA7

Inversion of TA7FF
TA7FFIE

0

Disabled

1

Enabled

Control of TA7FF



0

00: Invert TA7FF

00

Inverts the value of TA7FF (Software inversion)

01

Sets TA7FF to “1”

10

Clears TA7FF to “0”

11

Don’t care

Note: The values of bits 4 to 6 of TA7FFCR are “1” when read.

Figure 3.12.15 Register for TMRA (11)

92CZ26A-283

TMP92CZ26A

Timer Registers

TA0REG
(1102H)

TA1REG
(1103H)

TA2REG
(110AH)

TA3REG
(110BH)

TA4REG
(1112H)

TA5REG
(1113H)

TA6REG
(111AH)

TA7REG
(111BH)

bit Symbol

7

6

5

4

−

−

−

−

Read/Write

3

2

1

0

−

−

−

−

0

0

0

0

−

−

−

−

W

After reset

0

0

0

0

bit Symbol

−

−

−

−

Read/Write

W

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

Read/Write

W

Read/Write

W

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

0

0

0

0

−

−

−

−

Read/Write

W

After reset

0

0

0

0

bit Symbol

−

−

−

−

Read/Write

W

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

0

0

0

0

Read/Write

W

Read/Write
After reset

W
0

0

0

0

Note: All registers are prohibited to execute read-modify-write instruction.

Figure 3.12.16 TMRA Registers

92CZ26A-284

TMP92CZ26A

3.12.4 Operation in Each Mode
(1) 8-bit timer mode
Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers.
a. Generating interrupts at a fixed interval (Using TMRA1)
To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop
TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and
TA1REG register respectively. Then, enable the interrupt INTTA1 and start TMRA1
counting.
Example: To generate an INTTA1 interrupt every 20 us at fc = 50 MHz, set each register as
follows;

* Clock state

Clcok gear :

1/1

Prescaler of clock gear : 1/2

MSB

LSB
7

6

5

4

3

2

1

0

TA01RUN

←

–

X

X

X

–

–

0

–

TA01MOD

←

0

0

X

X

0

1

X

X

Stop TMRA1 and clear it to 0.
Select 8-bit timer mode and select φT1 (0.16 μs at fC = 50

TA1REG

←

0

1

1

1

1

1

0

1

Set TA1REG to 20 μs ÷ φT1 = 125(7DH)

INTETA1

←

X

1

0

1

X

–

–

–

Enable INTTA1 and set it to level 5.

TA01RUN

←

–

X

X

X

–

1

1

–

Start TMRA1 counting.

MHz) as the input clock.

X: Don't Care、−: No change

Note:

Select the input clock using Table 3.12.2.
The input clocks for TMRA0 and TMRA1 are different from as follows.
TMRA0: TA0IN input, φT1, φT4 or φT16.
TMRA1: Match output of TMRA0, φT1, φT16, and φT256.

92CZ26A-285

TMP92CZ26A
b.

Generating a 50% duty ratio square wave pulse
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its
status output via the timer output pin (TA1OUT).

Example: To output a 3.2μs square wave pulse from the TA1OUT pin at fC= 50 MHz,
use the following procedure to make the appropriate register settings. This
example uses TMRA1; however, either TMRA0 or TMRA1 may be used.
* Clock state

Clcok gear :

1/1

Prescaler of clock gear : 1/2

7

6

5

4

3

2

1

0

← −
← 0

X

X

X

X

X

−
1

0

0

−
0

X

−
X

Select 8-bit timer mode and select φT1 (0.16 μs at fC = 50

0

0

0

1

0

1

0

Set the timer register to 3.2 μs ÷ φT1 ÷ 2 = 0AH

TA1FFCR

← 0
← X

X

X

X

1

0

1

1

Clear TA1FF to “0” and set it to invert on the match detect

PM

← −

X

X

X

X

−

0

X

PMFC

← −

X

X

X

X

1

X

TA01RUN
← − X X
X: Don’t care, −: No change

X

−

−
1

1

−

TA01RUN
TA01MOD

Stop TMRA1 and clear it to “0”.
MHz) as the input clock.

TA1REG

signal from TMRA1.
Set PM1 to function as the TA1OUT pin.
Start TMRA1 counting.

φT1
TA01RUN

Bit7 to Bit2
Up
counter

Bit1
Bit0

0

1

2

3

0

1

2

3

0

1

Comparator
timing
Comparator output
(Match detect)
INTTA1
UC1 clear
TA1FF
TA1OUT
1.6 μs at fC = 50 MHz

Figure 3.12.17 Square Wave Output Timing Chart (50% duty)

92CZ26A-286

2

3

0

TMP92CZ26A
c.

Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the
input clock to TMRA1.

Comparator output
(TMRA0 match)
TMRA0 up counter
(when TA0REG = 5)
TMRA1 up counter
(when TA1REG = 2)

1

2

3

4

5

1

1

2

3

4

2

5

1

2

3
1

TMRA1 match output

Figure 3.12.18 TMRA1 Count Up on Signal from TMRA0
(2) 16 bit timer mode
Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer.
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
set TA01MOD to 01.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
TMRA1, regardless of the value set in TA01MOD. Table 3.12.2shows
the relationship between the timer (Interrupt) cycle and the input clock selection.

Example: To generate an INTTA1 interrupt every 0.13 s at fSYS = 50 MHz, set the timer registers
TA0REG and TA1REG as follows:

* Clock state

Clcok gear :

1/1

Prescaler of clock gear : 1/2

If φT16 (2.6 μs at fSYS = 50 MHz) is used as the input clock for counting, set the following
value in the registers: 0.13 s ÷ 2.6 μs = 50000 = C350H; e.g. set TA1REG to C3H and
TA0REG to 50H.

92CZ26A-287

TMP92CZ26A
The comparator match signal is output from TMRA0 each time the up counter UC0
matches TA0REG, though the up counter UC0 is not be cleared.
In the case of the TMRA1 comparator, the match detect signal is output on each
comparator pulse on which the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparator
TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
Value of up counter
(UC1, UC0)
TMRA0 comparator
match detect signal
TMRA1 comparator
match detect signal

0080H

0180H

0280H

0380H

0480H

0080H

Interrupt INTTA0
Interrupt INTTA1
Inversion

Timer output TA1OUT

Figure 3.12.19 Timer Output by 16-Bit Timer Mode
(3) 8-bit PPG (Programmable pulse generation) output mode
Square wave pulses can be generated at any frequency and duty ratio by TMRA0.
The output pulses may be active-low or active-high. In this mode TMRA1 cannot be
used.
TMRA0 outputs pulses on the TA1OUT pin.
tH

tL

 = “10”
t
tL

tH

 = “01”
t
Example:  = “01”
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interrupt INTTA1)
TA1OUT
TA0REG
TA1REG

Figure 3.12.20 8-Bit PPG Output Waveforms

92CZ26A-288

TMP92CZ26A

In this mode a programmable square wave is generated by inverting the timer
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
TA01RUN should be set to 1 so that UC1 is set for counting.
Figure 3.12.21 shows a block diagram representing this mode.
TA01RUN
TA0IN
φT1
φT4
φT16

TA1OUT

Selector
8-bit
up counter
(UC0)

TA1FFCR

TA1FF

Inversion

TA01MOD

INTTA0
Comparator

Selector

INTTA1

Comparator

TA0REG
Shift trigger

TA0REG-WR
TA01RUN

Register buffer

TA1REG

Internal data bus

Figure 3.12.21 Block Diagram of 8-Bit PPG Output Mode
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
will be shifted into TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is
varied).
Match with TA0REG
and up counter

(Up counter = Q1)

(Up counter = Q2)

Match with TA1REG
TA0REG
(Value to be compared)
Register buffer

Shift from register buffer
Q1

Q2
Q2

Q3
TA0REG (Register buffer)
write

Figure 3.12.22 Operation of Register Buffer
Note: The values that can be set in TAxREG renge from 01h to 00h (equivalent to 100h). If the maximum value 00h
is set , the match-detect signal goes active when the up-counter overfolws.

92CZ26A-289

TMP92CZ26A

Example:

To generate 1/4 duty 31.25 kHz pulses (at fC= 50 MHz)

32 μs
* Clock state

Clcok gear :

1/1

Prescaler of clock gear : 1/2
Calculate the value which should be set in the timer register.
To obtain a frequency of 31.25 kHz, the pulse cycle t should be: t = 1/31.25kHz = 32 μs
φT1 = 0.16 μs (at 50 MHz);
32 μs ÷ 0.16 μs = 200
Therefore set TA1REG to 200 (C8H)
The duty is to be set to 1/4: t × 1/4 = 32 μs × 1/4 = 8 μs
8 μs ÷ 0.16 μs = 50
Therefore, set TA0REG = 50 = 32H.
7

6

5

4

3

2

1

← −
← 1

X

X

X

0

Stop TMRA0 and TMRA1 and clear it to “0”.

X

X

−
X

0

0

−
X

0

1

Set the 8-bit PPG mode, and select φT1 as input clock.

← 0
← 1

0

0

0

1

0

1

0

Write 32H.

TA1REG

1

0

0

1

0

0

0

Write C8H.

TA1FFCR

← X

X

X

X

0

1

1

X

Set TA1FF, enabling both inversion and the double buffer.

PM

← −

X

X

X

X

−

0

X

PMFC

← −
← 1

X

X

X

X

1

X

X

X

X

−

−
1

1

1

TA01RUN
TA01MOD
TA0REG

0

Writing 10 provides negative logic pulse.

TA01RUN

Set PM1 as the TA1OUT pin.
Start TMRA0 and TMRA1 counting.

X: Don't care, −: No change

92CZ26A-290

TMP92CZ26A
(4) 8-bit PWM (Pulse width modulation) output mode
This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum
resolution of 8 bits can be output.
When TMRA0 is used the PWM pulse is output on the TA1OUT pin (Shared with
PM1). TMRA1 can also be used as an 8-bit timer.
The timer output is inverted when the up counter (UC0) matches the value set in
the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as
specified by TA01MOD). The up counter UC0 is cleared when 2n counter
overflow occurs.
The following conditions must be satisfied before this PWM mode can be used.
Value set in TA0REG < Value set for 2n counter overflow
Value set in TA0REG ≠ 0
TA0REG and
UC0 match
n

2
overflow
(INTTA0 interrupt)

TA1OUT
tPWM
(PWM cycle)

Figure 3.12.23 8-Bit PWM Waveforms
Figure 3.12.24 shows a block diagram representing this mode.
TA01RUN
TA0IN
φT1
φT4
φT16

8-bit up counter
(UC0)

Selector

TA1OUT

TA1FF

Clear

TA1FFCR


Inversion

TA01MOD

n

2 overflow
control

Comparator

TA01MOD


Overflow

INTTA0
TA0REG
Selector

Shift trigger

TA0REG-WR
TA01RUN

Register buffer

Internal data bus

Figure 3.12.24 Block Diagram of 8-Bit PWM Mode

92CZ26A-291

TMP92CZ26A
In this mode the value of the register buffer will be shifted into TA0REG if 2n
overflow is detected when the TA0REG double buffer is enabled.
Use of the double buffer facilitates the handling of low duty ratio waves.

Match with TA0REG
Up counter = Q1

Up counter = Q2

n

2 overflow
Shift into TA0REG
TA0REG
(Value to be compared)

Q1

Q2
Q2

Register buffer

Q3
TA0REG (Register buffer)
write

Figure 3.12.25 Register Buffer Operation
Example: To output the following PWM waves on the TA1OUT pin (at fC = 50 MHz).

16.0 μs
20.48 μs
* Clock state

Clcok gear :

1/1

Prescaler of clock gear : 1/2

To achieve a 20.48μs PWM cycle by setting φT1 to 0.16 μs (at fC = 50 MHz):
20.48 μs ÷ 0.16 μs = 128
2 = 128
n

Therefore n should be set to 7.
Since the low level period is 16.0 μs when φT1 = 0.16 μs,
set the following value for TAREG:
16.0 μs ÷ 0.16 μs = 100 = 64H
MSB

LSB

7

6

5

4

3

2

1

0

← −
← 1

X

X

X
0

−
0

Stop TMRA0 and clear it to 0

1

−
X

0

1

−
X

1

Select 8-bit PWM mode (cycle: 2 ) and select φT1 as the

1

1

0

0

1

0

0

Write 64H.

TA1FFCR

← 0
← X

X

X

X

1

0

1

X

Clear TA1FF to 0, enable the inversion and double buffer.

PM

← −

X

X

X

X

−

0

0

PMFC

← −
← 1

X

X

X

X

1

X

X

X

X

−

−
1

−

1

TA01RUN
TA01MOD

7

input clock.
TA0REG

TA01RUN

Set PM1 as the TA1OUT pin.
Start TMRA0 counting.

X: Don't care, −: No change

92CZ26A-292

TMP92CZ26A
Table 3.12.3 PWM Cycle
Clock gear

Prescaler of

PWM cycle

selection

clock gear

TAxxMOD

SYSCR1

SYSCR0





6

φT4(x8)

8

2 (x128)

TAxxMOD
φT1(x2)

2 (x256)

TAxxMOD

φT16(x32)

φT1(x2)

φT4(x8)

TAxxMOD

φT16(x32)

φT1(x2)

φT4(x8)

φT16(x32)
32768/fc

000(x1)

512/fc

2048/fc

8192/fc

1024/fc

4096/fc

16384/fc

2048/fc

8192/fc

001(x2)

1024/fc

4096/fc

16384/fc

2048/fc

8192/fc

32768/fc

4096/fc

16384/fc

65536/fc

2048/fc

8192/fc

32768/fc

4096/fc

16384/fc

65536/fc

8192/fc

32768/fc

131072/fc

4096/fc

16384/fc

65536/fc

8192/fc

32768/fc

131072/fc

16384/fc

65536/fc

262144/fc

8192/fc

32768/fc

131072/fc

16384/fc

65536/fc

262144/fc

32768/fc

131072/fc

524288/fc

2048/fc

8192/fc

32768/fc

4096/fc

16384/fc

65536/fc

8192/fc

32768/fc

131072/fc

4096/fc

16384/fc

65536/fc

8192/fc

32768/fc

131072/fc

16384/fc

65536/fc

262144/fc

0(x2)

010(x4)
011(x8)
1/fc

7

2 (x64)

100(x16)

x2

000(x1)
001(x2)
1(x8)

010(x4)

8192/fc

32768/fc

131072/fc

16384/fc

65536/fc

262144/fc

32768/fc

131072/fc

524288/fc

011(x8)

16384/fc

65536/fc

262144/fc

32768/fc

131072/fc

524288/fc

65536/fc

262144/fc

1048576/fc

100(x16)

32768/fc

131072/fc

524288/fc

65536/fc

262144/fc

1048576/fc

131072/fc

524288/fc

2097152/fc

(5) Settings for each mode
Table 3.12.4 shows the SFR settings for each mode.

Table 3.12.4 Timer Mode Setting Registers
Register Name

TA01MOD







Function

Timer Mode

PWM Cycle

TA1FFCR





TA1FFIS

Upper Timer Input

Lower Timer

Timer F/F Invert Signal

Clock

Input Clock

Select

Lower timer
8-bit timer × 2 channels

match

−

00

φT1, φT16, φT256
(00, 01, 10, 11)

External clock
φT1, φT4, φT16
(00, 01, 10, 11)

0: Lower timer output
1: Upper timer output

External clock
16-bit timer mode

−

01

−

φT1, φT4, φT16

−

(00, 01, 10, 11)
External clock
8-bit PPG × 1 channel

−

10

−

φT1, φT4, φT16

−

(00, 01, 10, 11)
6

8-bit PWM × 1 channel

8-bit timer × 1 channel

11

11

7

External clock

8

2 ,2 ,2

−

(01, 10, 11)
−

φT1, φT4, φT16

−

(00, 01, 10, 11)
φT1, φT16, φT256
(01, 10, 11)

−: Don’t care

92CZ26A-293

−

Output disabled

TMP92CZ26A

3.13 16 bit timer / Event counter (TMRB)
The TMP92CZ26A incorporates two multifunctional 16-bit timer/event counter (TMRB0,
TMRB1) which have the following operation modes:
•

16 bit interval timer mode

•

16 bit event counter mode

•

16 bit programmable pulse generation mode (PPG)
Can be used following operation modes by capture function.

•

Frequency measurement mode

•

Pulse width measurement mode

Timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (One of them
with a double-buffer structure), a 16-bit capture registers, two comparators, a capture input
controller, a timer flip-flop and a control circuit.
Timer/event counter is controlled by an 11-byte control SFR.Each channel(TMRB0,TMRB1)
operate independently.In this section, the explanation describes only for TMRB0 because each
channel is identical operation except for the difference as follows;

Table 3.13.1 Difference between TMRB0 and TMRB1
Channel

TMRB0

TMRB1

External clock/
capture trigger input pins

TB0IN0
(Shared with PP4)

TB1IN0
(Shared with PP5)

Timer flip-flop output pins

TB0OUT0
(Shared with PP6)
TB0RUN (1180H)
TB0MOD (1182H)

TB1OUT0
(Shared with PP7)
TB1RUN (1190H)
TB1MOD (1192H)

TB0FFCR (1183H)

TB1FFCR (1193H)

TB0RG0L (1188H)
TB0RG0H (1189H)
TB0RG1L (118AH)
TB0RG1H (118BH)
TB0CP0L (118CH)
TB0CP0H (118DH)
TB0CP1L (118EH)
TB0CP1H (118FH)

TB1RG0L (1198H)
TB1RG0H (1199H)
TB1RG1L (119AH)
TB1RG1H (119BH)
TB1CP0L (119CH)
TB1CP0H (119DH)
TB1CP1L (119EH)
TB1CP1H (119FH)

Specification
External
pins

Timer run register
Timer mode register
Timer flip-flop
control register
SFR
(Address)

Timer register

Capture register

92CZ26A-294

(from TMRA01)
TB0IN0

TA1OUT

External INT
input INT6

Prescaler
clock
φT0TMR

4

φT4

8

TB0RUN


Count
clock

Slelector

92CZ26A-295

Figure 3.13.1 Block diagram of TMRB0
Internal data bus

Register buffer 10

16-bit timer register
TB0RG0H/L

16-bit comparator
(CP10)

TB0MOD

φT1
φT4
φT16

TB1MOD


16-bit up counter
(UC10)

Match
detection

Capture register 0
TB0CP0H/L

TB0RUN


TB0MOD


φT16

16 32

Capture,
external interrupt
input control

φT1

2

Run/
clear

Internal data bus

Intenal data bus

16-bit time register
TB0RG1H/L

16-bit comparator
(CP11)

TB0MOD

TB0RUN

Caputure register 1
TB0CP1H/L

Internal data bus

Match detection

control

flip-flop

Timer

Interrupt output
register 0 register 1
INTTB00
INTTB01

TB0FF0

Timer
flip-flop

TB0OUT0

Timer flip-flop
output

TMP92CZ26A

3.13.1 Block diagram

(from TMRA01)
TB1IN0

TA3OUT

External INT
input INT7

Prescaler
clock
φT0TMR

4

φT4

8

TB1RUN


Count
clock

Slelector

92CZ26A-296

Figure 3.13.2 Block diagram of TMRB1
Internal data bus

Register buffer 12

16-bit timer register
TB1RG0H/L

16-bit comparator
(CP12)

16-bit up counter
(UC12)

Match
detection

Capture register 0
TB1CP0H/L

TB1RUN


TB1MOD

φT1
φT4
φT16

TB1MOD


Run/
clear

TB1MOD


φT16

16 32

Capture,
external interrupt
input control

φT1

2

Internal data bus

Intenal data bus

16-bit time register
TB1RG1H/L

16-bit comparator
(CP13)

TB1MOD

TB1RUN

Caputure register 1
TB1CP1H/L

Internal data bus

Match detection

control

flip-flop

Timer

Interrupt output
register 0 register 1
INTTB10
INTTB11

TB1FF0

Timer
flip-flop

TB1OUT0

Timer flip-flop
output

TMP92CZ26A

TMP92CZ26A

3.13.2 Operation
(1) Prescaler
The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0)
is selected by the register SYSCR0 of clock gear. This prescaler can be
started or stopped using TB0RUN. Counting starts when  is
set to “1”; the prescaler is cleared to “0” and stops operation when  is
cleared to “0”.
The resolution of prescaler is showed in the Table 3.13.2.
Table 3.13.2 Prescaler Clock Resolution
Clock gear

Prescaler of

selection

clock gear

SYSCR1

SYSCR0





Timer counter input clock

1/1
1/2

TBxMOD
φT1(1/2)

φT4(1/8)

φT16(1/32)

fc/8

fc/32

fc/128

fc/16

fc/64

fc/256

fc/32

fc/128

fc/512

1/8

fc/64

fc/256

fc/1024

1/16

fc/128

fc/512

fc/2048

fc/32

fc/128

fc/512

1/4

fc

Prescaler of TMRB

−

1/2

1/2

1/1
1/2

fc/64

fc/256

fc/1024

fc/128

fc/512

fc/2048

1/8

fc/256

fc/1024

fc/4096

1/16

fc/512

fc/2048

fc/8192

1/4

1/8

(2) Up counter (UC10)
UC10 is a 16-bit binary counter which counts up pulses input from the clock
specified by TB0MOD.
Any one of the prescaler internal clocks φT1, φTB0 and φT16 or an external clock
input via the TB0IN0 pin can be selected as the input clock. Counting or stopping and
clearing of the counter is controlled by TB0RUN.
When clearing is enabled, the up counter UC10 will be cleared to zero each time its
value matches the value in the timer register TB0RG1H/L. Clearing can be enabled or
disabled using TB0MOD.
If clearing is disabled, the counter operates as a free running counter.

92CZ26A-297

TMP92CZ26A
(3) Timer registers (TB0RG0H/L, TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the
up counter UC10 matches the value set in this timer register, the comparator match
detect signal will go active.
Setting data for both upper and lower timer registers is needed. For example, using
2-byte data transfer instruction or using 1-byte data transfer instruction twice for
lower 8 bits and upper 8 bits in order.
(The compare circuit will not operate if only the lower 8 bits are written. Be sure to
write to both timer registers (16 bits) from the lower 8 bits followed by the upper 8
bits.)
The TB0RG0H/L timer register has a double-buffer structure, which is paired with
register buffer 10. The value set in TB0RUN determines whether the
double-buffer structure is enabled or disabled: it is disabled when  = “0”,
and enabled when  = “1”.
When the double buffer is enabled, data is transferred from the register buffer 10 to
the timer register when the values in the up counter (UC10) and the timer register
TB0RG1H/L match.
The double buffer circuit incorporates two flags to indicate whether or not data is
written to the lower 8 bits and the upper 8 bits of the register buffer, respectively.
Only when both flags are set can data be transferred from the register buffer to the
timer register by a match between the up-counter UC10 and the timer register
TB0RG1. This data transfer is performed so long as 16-bit data is written in the
register buffer regardless of the register buffer to the timer register unexpectedly as
explained below.
For example, let us assume that an interrupt occurs when only the lower 8 bits (L1)
of the register buffer data (H1L1) have been written and the interrupt routine
includes writes to all 16 bits in the register buffer and a transfer of the data to the
timer register. In this case, if the higher 8 bits (H1) are written after the interrupt
routine is completed, only the flag for the higher 8 bits will be set, the flag for the
lower 8 bits having been cleared in the interrupt routine. Therefore, even if a match
occurs between UC10 and TB0RG1, no data transfer will be performed.
Then, in an attempt to set the next set of data (H2L2) in the register buffer, when
the lower 8 bits (L2) are written, this will cause the flag for the lower 8 bits to be set as
well as the flag for the higher 8 bits which has been set by writing the previous data
(H1). If a match between UC10 and TB0RG1 occurs before the higher 8 bits (H2) are
written, this will cause unexpected data (H1L2) to be sent to the timer register instead
of the intended data (H2L2).
To avoid such transfer timing problems due to interrupts, the DI instruction
(disable interrupts) and the EI (enable interrupts) can be executed before and after
setting data in the register buffer, respectively.
After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to
be used after a reset, data should be written to it beforehand.
On a reset  is initialized to “0”, disabling the double buffer. To use the
double buffer, write data to the timer register, set  to “1”, then write data
to the register buffer 10 as shown below.

92CZ26A-298

TMP92CZ26A
TB0RG0H/L and the register buffer 10 both have the same memory addresses
(1188H and 1189H) allocated to them. If  = “0”, the value is written to both
the timer register and the register buffer 10. If  = “1”, the value is written
to the register buffer 10 only.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0H/L

TB0RG1 H/L

Upper 8 bits
(TB0RG0H)

Lower 8 bits
(TB0RG0L)

Upper 8 bits
(TB0RG1H)

Lower 8 bits
(TB0RG1L)

1189H

1188H

118BH

118AH

TMRB1
TB1RG0 H/L

TB1RG1 H/L

Upper 8 bits
(TB1RG0H)

Lower 8 bits
(TB1RG0L)

Upper 8 bits
(TB1RG1H)

Lower 8 bits
(TB1RG1L)

1199H

1198H

119BH

119AH

The timer registers are write-only registers and thus cannot be read.

92CZ26A-299

TMP92CZ26A
(4) Capture registers (TB0CP0H/L, TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counter (UC10).
Data in the capture registers should be read all 16 bits. For example, using a 2-byte
data load instruction or two 1-byte data load instructions. The least significant byte is
read first, followed by the most significant byte.
(during capture is read, capture operation is prohibited. In that case, the lower 8
bits should be read first, followed by the 8 bits.)
The addresses of the capture registers are as follows;
TMRB0
TB0CP0H/L

TB0CP1H/L

Upper 8 bits
(TB0CP0H)

Lower 8 bits
(TB0CP0L)

Upper 8 bits
(TB0CP1H)

Lower 8 bits
(TB0CP1L)

118DH

118CH

118FH

118EH

Upper 8 bits
(TB1CP0H)

Lower 8 bits
(TB1CP0L)

Upper 8 bits
(TB1CP1H)

Lower 8 bits
(TB1CP1L)

119DH

119CH

119FH

119EH

TMRB1
TB1CP0H/L

TB1CP1H/L

The capture registers are read-only registers and thus cannot be written to.

(5) Capture input and external interrupt control
This circuit controls the timing to latch the value of up-counter UC10 into
TB0CP0H/L and TB0CP1H/L, and generates external interrupt.The latch timing of
capture register and selection of edge for external interrupt is controlled by
TB0MOD.
The value in the up-counter (UC10) can be loaded into a capture register by
software. Whenever 0 is written to TB0MOD, the current value in the up
counter (UC10) is loaded into capture register TB0CP0H/L. It is necessary to keep the
prescaler in RUN mode (e.g., TB0RUN must be held at a value of 1).

92CZ26A-300

TMP92CZ26A
(6) Comparators (CP10, CP11)
CP10 and CP11 are 16-bit comparators which compare the value in the up counter
UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect
a match. If a match is detected, the comparator generates an interrupt (INTTB00 or
INTTB01 respectively).
(7) Timer flip-flops (TB0FF0, TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR.
After a reset the value of TB0FF0 is undefined. If “00” is written to TB0FFCR
 or , TB0FF0 will be inverted. If “01” is written to the
capture registers, the value of TB0FF0 will be set to “1”. If “10” is written to the
capture registers, the value of TB0FF0 will be set to “0”.
Note: If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs
simultaneously, the resultant operation varies depending on the situation, as shown below.
•

If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the
flip-flop will be inverted only once.

•

If an inversion by the match-detect siganl and an attempt to set the flip-flop to 1 via the register occur
simultaneously, the flip-flop will be set to 1.

•

If an inversion by the match-detect signal and an attmept to cleare the flip-flop to 0 via the register
occur simultanerously, the flip-flop will be cleared to 0.

If an inversion by match-detect signal and inversion disable setting occur
simultaneously, two case (it is inverted and it is not inverted) are occurred. Therefore,
if changing inversion control (inversion enable/disable), stop timer operation
beforehand.
The values of TB0FF0 and TB0FF1 can be output via the timer output pins
TB0OUT0 (which is shared with PP6) and TB0OUT1 (which is shared with PP7).
Timer output should be specified using the port P function register.

92CZ26A-301

TMP92CZ26A

3.13.3 SFR
TMRB0 RUN Register

TB0RUN
(1180H)

Bit symbol
Read/Write
After Reset

Function

7

6

TB0RDE
R/W
0

−
R/W
0

5

4

3

2

I2TB0
R/W
0

TB0PRUN
R/W
0

1

0
TB0RUN
R/W
0

Double

Always

In IDLE2

TMRB0

Up counter

buffer

write “0”

mode

prescaler
0: Stop and clear
1: Run (Count up)

(UC10)

0: disable

0: Stop

1: enable

1: Operate

Count operation
, 

0

Stop and clear

1

Count up

Note: The 1, 4 and 5 of TB0RUN are read as “1” value.
TMRB1 RUN Register

TB1RUN
(1190H)

Bit symbol
Read/Write
After Reset

Function

7

6

TB1RDE
R/W
0

−
R/W
0

5

4

3

2

I2TB1
R/W
0

TB1PRUN
R/W
0

1

0
TB1RUN
R/W
0

Double

Always

In IDLE2

TMRB1

Up counter

buffer

write “0”

mode

prescaler

(UC12)

0: disable

0: Stop

0: Stop and clear

1: enable

1: Operate

1: Run (Count up)

Count operation
, 

0

Stop and clear

1

Count up

Note: The 1, 4 and 5 of TB1RUN are read as “1” value.

Figure 3.13.3 Register for TMRB (1)

92CZ26A-302

TMP92CZ26A

TMRB0 Mode Register

TB0MOD
(1182H)

Bit symbol

6

5

−

−

TB0CP0I

Read/Write
After Reset

Prohibit
readmodifywrite

7

Function

4

3

TB0CPM1 TB0CPM0

2

1

0

TB0CLE

TB0CLK1

TB0CLK0

0

0

W*

R/W
0

0

Always write “0”.

R/W

1

0

0

Capture timing
capture control 00:Disable
INT6 occurs at
0: Execute
rising edge
1: Undefined
01:TB0IN0 ↑
INT6 occurs at
rising edge
10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at
falling edge
11: TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge
Software

0
Control
Up counter
0:Disable
1: Enable

TMRB0 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16

TMRB0 source clock



00

TB0IN0 pin input

01

φT1

10

φT4

11

φT16

Control clearing for up counter (UC10)


0

Disable

1

Enable clearing by match with TB0RG1

00

Disable

INT6 occurs at the rising

01

Capture to TB0CP0H/L at rising edge of TB0IN0

edge of TB0IN0

Capture to TB0CP0H/L at rising edge of TB0IN0

INT6 occurs at the rising

Capture/interrupt timing
Capture control



10

Capture to TB0CP1H/L at falling edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TA1OUT

11

Capture to TB0CP1H/L at falling edge of TA1OUT

INT6 control

edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0

Software capture


0

The value of up counter is captured to TB0CP0H/L

1

Undefined

Figure 3.13.4 Register for TMRB (2)

92CZ26A-303

TMP92CZ26A
TMRB1 Mode Register

TB1MOD
(1192H)

Bit symbol

6

5

−

−

TB1CP0I

Read/Write
After Reset

Prohibit
readmodifywrite

7

Function

4

3

TB1CPM1 TB1CPM0

2

1

0

TB1CLE

TB1CLK1

TB1CLK0

0

0

W*

R/W
0

0

Always write “0”.

R/W

1

0

0

Capture timing
capture control 00:Disable
INT7 occurs at
0: Execute
rising edge
1: Undefined
01:TB1IN0 ↑
INT7 occurs at
rising edge
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at
falling edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
Software

0
Control
Up counter
0:Disable
1: Enable

TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16

TMRB1 source clock



00

TB1IN0 pin input

01

φT1

10

φT4

11

φT16

Control clearing for up counter (UC12)
0


1

Disable
Enable clearing by match with
TB1RG1H/L

Capture/interrupt timing
Capture control



INT7 control

00

Disable

INT7 occurs at the rising

01

Capture to TB1CP0H/L at rising edge of TB1IN0

edge of TB1IN0

Capture to TB1CP0H/L at rising edge of TB1IN0

INT7 occurs at the rising

10

Capture to TB1CP1H/L at falling edge of TB1IN0
Capture to TB1CP0H/L at rising edge of TA3OUT

11

Capture to TB1CP1H/L at falling edge of TA3OUT

edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0

Software capture


0

The value of up counter is captured to TB1CP0H/L

1

Undefined (Note)

Figure 3.13.5 Register for TMRB (3)

92CZ26A-304

TMP92CZ26A

TMRB0 Flip-Flop Control Register

7
TB0FFCR
(1183H)

Bit symbol

Prohibit
readmodifywrite

Function

5

4

−

TB0C1T1

TB0C0T1

−
W*

Read/Write
After Reset

6

3

2

1

TB0E1T1

TB0E0T1

TB0FF0C1

R/W

1

1

Always write “11”

0

0

0
TB0FF0C0

W*
0

0

1

TB0FF0 inversion trigger

Control TB0FF0

0: Disable trigger

00: Invert

1: Enable trigger

01: Set

1

10: Clear
*Always read as “11”.

When
capture
UC10 to
TB0CP1H/L

When
capture
UC10 to
TB0CP0H/L

When UC10
matches
with
TB0RG1H/L

Timer flip-flop control(TB0FF0)



00

Invert

01

Set to “11”

10

Clear to “00”

11

Undefined (Always read as “11”)

TB0FF0 control
Inverted when UC10 value matches the valued in TB0RG0H/L


0

Disable trigger

1

Enable trigger

TB0FF0 control
Inverted when UC10 value matches the valued in TB0RG1H/L


0

Disable trigger

1

Enable trigger

TB0FF0 control
Inverted when UC10 value is captured into TB0CP0H/L


0

Disable trigger

1

Enable trigger

TB0FF0 control
Inverted when UC10 value is captured into TB0CP1H/L


0

Disable trigger

1

Enable trigger

Figure 3.13.6 Register for TMRB (4)

92CZ26A-305

11: Undefined

When UC10
matches
with
*Always read as “11”.
TB0RG0H/L

TMP92CZ26A

TMRB1 Flip-Flop Control Register

7
TB1FFCR
(1193H)

Bit symbol

Prohibit
readmodifywrite

Function

5

4

−

TB1C1T1

TB1C0T1

−
W*

Read/Write
After Reset

6

3

2

1

TB1E1T1

TB1E0T1

TB1FF0C1

1

Always write “11”

0

0

TB1FF0C0

W*

R/W

1

0

0

0

1

TB1FF0 inversion trigger

Control TB1FF0

0: Disable trigger

00: Invert

1: Enable trigger

01: Set

1

10: Clear
*Always read as “11”.

When
capture
UC12 to
TB1CP1H/L

When
capture
UC12 to
TB1CP0H/L

When UC12
matches
with
TB1RG1H/L

Timer flip-flop control(TB1FF0)



00

Invert

01

Set to “11”

10

Clear to “00”

11

Don’t care

TB1FF0 control
Inverted when UC12 value matches the valued in TB1RG0H/L


0

Disable trigger

1

Enable trigger

TB1FF0 control
Inverted when UC12 value matches the valued in TB1RG1H/L


0

Disable trigger

1

Enable trigger

TB1FF0 control
Inverted when UC12 value is captured into TB1CP0H/L


0

Disable trigger

1

Enable trigger

TB1FF0 control
Inverted when UC12 value is captured into TB1CP1H/L


0

Disable trigger

1

Enable trigger

Figure 3.13.7 Register for TMRB (5)

92CZ26A-306

11: Don’t care

When UC12
matches
with
*Always read as “11”.
TB1RG0H/L

TMP92CZ26A

TB0RG0L
(1188H)

bit Symbol
After reset

4

−

−

−

−

3

2

1

0

−

−

−

−

0

0

0

0

−

−

−

−

W
0

0

0

0

−

−

−

−
W

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

0

0

0

0

0

0

0

0

−

−

−

−

−

−

−

−

Read/Write

TB0RG1H bit Symbol
(118BH)
Read/Write

W

W

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

0

0

0

0

−

−

−

−

Read/Write
After reset

TB1RG0H bit Symbol
(1199H)
Read/Write
TB1RG1L
(119AH)

5

After reset

After reset

TB1RG0L
(1198H)

6

Read/Write

TB0RG0H bit Symbol
(1189H)
Read/Write
TB0RG1L
(118AH)

7

W
0

0

0

0

−

−

−

−
W

After reset

0

0

0

0

0

0

0

0

bit Symbol

−

−

−

−

−

−

−

−

0

0

0

0

0

0

0

0

−

−

−

−

−

−

−

−

0

0

0

0

Read/Write
After reset

TB1RG1H bit Symbol
(119BH)
Read/Write
After reset

W

W
0

0

0

0

Note: All registers are prohibited to execute read-modify-write instruction.

Figure 3.13.8 Register for TMRB (6)

92CZ26A-307

TMP92CZ26A

3.13.4 Operation in Each Mode
(1) 16 bit timer mode
Generating interrupts at fixed intervals
In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The
interval time is set in the timer register TB0RG1H/L.
7

6

5

4

3

2

1

0

TB0RUN

←

–

0

X

X

–

–

X

0

Stop TMRB0

INTETB0

←

X

1

0

0

X

0

0

0

Enable INTTB01and set interrupt level 4.

TB0FFCR

←

1

1

0

0

0

0

1

1

Disable the trigger

TB0MOD

←

0

0

1

0

0

1

*

*

Select internal clock for input and

Disable INTTB00

(** = 01, 10, 11)

disable the capture function.

TB0RG1

←

*
*

*

*

*

*

*

*

*

(16 bits).

TB0RUN

←

–

0

X

X

–

1

X

1

Start TMRB0.

*

*

*

*

*

*

*

Set the interval time

X: Don't care, −: No change
(2) 16 bit event counter mode
In 16 bit timer mode as described in above, the timer can be used as an event
counter by selecting the external clock (TB0IN0 pin input) as the input clock. Up
counter (UC10) counts up at the rising edge of TB0IN0 input. To read the value of
the counter, first perform “software capture” once and read the captured value.
7

6

5

4

3

2

1

0

TB0RUN

←

–

0

X

X

–

–

X

0

Stop TMRB0

PPCR

←

X

X

–

1

–

–

–

X

Set PP4 to input mode for TB0IN0

PPFC

←

–

–

–

1

–

–

–

X

INTETB0

←

X

1

0

0

X

0

0

0

Enable INTTB01 and sets interrupt level 4

TB0FFCR

←

1

1

0

0

0

0

1

1

Disable trigger

TB0MOD

←

0

0

1

0

0

1

0

0

Select TB0IN0 as the input clock

TB0RG1

←

*

*

*

*

*

*

*

*

Set the number of counts

*

*

*

*

*

*

*

*

(16 bit)

–

0

X

X

–

1

X

1

Start TMRB0

Disable INTTB00

TB0RUN

←

X: Don't care, −: No change
When used as an event counter, set the prescaler in RUN mode.
(TB0RUN  = “1”)

92CZ26A-308

TMP92CZ26A
(3) 16-bit programmable pulse generation (PPG) output mode
Square wave pulses can be generated at any frequency and duty ratio. The output
pulse may be either low active or high active.
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be
enabled by the match of the up counter UC10 with timer register TB0RG0H/L or
TB0RG1H/L and to be output to TB0OUT0. In this mode the following conditions
must be satisfied.
(Value set in TB0RG0) < (Value set in TB0RG1)
Match with TB0RG0
(INTTB00 interrupt)
Match with TB0RG1
(INTTB01 interrupt)
TB0OUT0 pin

Figure 3.13.9 Programmable Pulse Generation (PPG) Output Waveforms
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
facilitates the handling of low-duty waves.

Match with TB0RG0H/L
Up conter = Q1

Up counter = Q2

Match with TB0RG1H/L
Shift into the TB0RG1H/L
TB0RG0H/L
(Value to be compared)
Register buffer 10

Q1

Q2
Q2

Q3
Write into the TB0RG0H/L

Figure 3.13.10 Operation of double buffer
Note: The values that can be set in TBxRGx range from 0001h to 0000h (equivalent to 10000h). If the maximum
value 000h is set, the match-detect signal goes active when the up-counter overflows.

92CZ26A-309

TMP92CZ26A
The following block diagram illustrates this mode.
TB0RUN TB0OUT0 (PPG output)
Selector
TB0IN0
φT1
φT4
φT16

16-bit up counter
UC10

16-bit comparator

Selector

Match

Clear

F/F
(TB0FF0)

16-bit comparator

TB0RG0H/L

TB0RG0-WR
TB0RUN

Register buffer 0

TB0RG1H/L

Internal data bus

Figure 3.13.11 Block Diagram of 16-Bit Mode
The following example shows how to set 16-bit PPG output mode:

7

6

5

4

3

2

1

0

TB0RUN

←

0

0

X

X

–

–

X

0

TB0RG0

←

*

*

*

*

*

*

*

*

Set the duty ratio

*

*

*

*

*

*

*

*

(16 bit)

TB0RG1
TB0RUN

←
←

Disable the TB0RG0 double buffer and stop TMRB0.

*

*

*

*

*

*

*

*

Set the frequency

*

*

*

*

*

*

*

*

(16 bit)

1

0

X

X

–

0

X

0

Enable the TB0RG0H/L double buffer.
(The duty and frequency are changed on an INTTB01
interrupt.)

TB0FFCR

←

X

X

0

0

1

1

1

0

Set the mode to invert TB0FF0 at the match with
TB0RG0H/L/TB0RG1H/L. Set TB0FF0 to 0.

TB0MOD

←

0

0

1

0

0

1

*

*

(** = 01, 10, 11)
PPFC

←

–

1

–

–

–

–

–

X

TB0RUN

←

1

0

X

X

–

1

X

1

Select the internal clock as the input clock and disable
the capture function.
Set PP6 to function as TB0OUT0
Start TMRB0.

X: Don't care, −: No change

92CZ26A-310

TMP92CZ26A
(4) Application examples of capture function
Used capture function, they can be applied in many ways, for example;
1.

One-shot pulse output from external trigger pulse

2.

Frequency measurement

3.

Pulse width measurement

1.

One-shot pulse output from external trigger pulse
Set the up counter UC10 in free-running mode with the internal input clock,
input the external trigger pulse from TB0IN0 pin, and load the value of up
counter into capture register TB0CP0H/L at the rising edge of the TB0IN0 pin.
When the interrupt INT6 is generated at the rising edge of TB0IN0 input, set
the TB0CP0H/L value (c) plus a delay time (d) to TB0RG0H/L (=c+d), and set the
above set value (c+d) plus a one-shot pulse width (p) to TB0RG1H/L (=c+d+p).
The TB0FFCR register should be set “11” and that the
TB0FF0 inversion is enabled only when the up counter value matches
TB0RG0H/L or TB0RG1H/L. When interrupt INTTB01 occurs, this inversion will
be disabled after one-shot pulse is output.
The (c), (d) and (p) correspond to c, d, and p in the Figure 3.13.12.

Set the counter in free-running mode.
Count clock
(Prescaler output clock)
TB0IN0 pin input
(External trigger pulse)

c+d+p

c+d

c

Load to capture registesr 0 (TB0CP0H/L)
INT6 occured

Match with TB0RG0H/L

Match with TB0RG1H/L

Inversion
enable
Disable inversion

Timer output pin TB0OUT0

caused by loading into
TB0CP0H/L

INTTB01 occured
Inversion
enable

Delay time

Pulse width

(d)

(p)

Figure 3.13.12 One-shot Pulse Output (with delay)

92CZ26A-311

TMP92CZ26A
Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to
TB0IN0pin
*Clock state
System clock :

fSYS

Prescaler clock :

fSYS/4

Main setting
Free-running
Count with φT1
TB0MOD

←

X

X

1

0

1

0

0

1

TB0FFCR

←

X

X

0

0

0

0

1

0

Load to TB0CP0H/L at the rising edge of TB0IN0
Clear TB0FF0 to “0”
Disable TB0FF0 inversion
←

PPFC

–

1

–

–

–

–

–

X

Select PP6 as TB0OUT0 pin (port setting)

INTE56

←

X

1

0

0

X

–

–

–

Enable INT6

INTETB0

←

X

0

0

0

X

0

0

0

Disable INTTB00, INTTB01

TB0RUN

←

–

0

X

X

–

1

X

1

Start TMRB0

1

–

–

Setting in INT6 routine

TB0RG1

← TB0CP0 + 3ms/φT1
← TB0RG0 + 2ms/φT1

TB0FFCR

←

TB0RG0

X

X

–

–

1

Enable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
INTETB0

←

X

1

0

0

X

0

0

0

–

–

0

0

–

–

Enable INTTB01

Setting in INTTB01 routine
TB0FFCR

←

X

X

Disable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
INTETB0

←

X

0

0

0

X

0

0

0

Disable INTTB01

X: Don't care, −: No change
When delay time is unnecessary, invert timer flip-flop TB0FF0 when the up counter
value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c)
plus the one –shot pulse width (p) to TB0RG1H/L when the interrupt INT6 occurs.
The TB0FF0 inversion should be enabled when the up counter (UC10) value matched
TB0RG1H/L, and disabled when generating the interrupt INTTB01.

92CZ26A-312

TMP92CZ26A
Count clock
(Prescaler output clock )

c+p

c
TB0IN0 iput
(External trigger pulse)

Load into capture register 0 (TB0CP0H/L)
INT6 occured

Load into capture register 1 (TB0CP1H/L)

INTTB01 occured
Match with TB0RG1H/L
Inversion enable
Timer output pin TB0OUT0
Pulse width
Enable inversioncaused by
loading to TB0CP0H/L

Disable inversion caused by loading into
TB0CP1H/L

(p)

Figure 3.13.13 One-shot Pulse Output (without delay)
2.

Frequency measurement
The frequency of the external clock can be measured in this mode. The clock is
input through the TB0IN0 pin, and its frequency is measured by the 8 bit timers
TMRA01 and the 16 bit timer/event counter (TMRB0).
The TB0IN0 pin input should be selected for the input clock of TMRB0. Set to
TB0MOD=”11”. The value of the up counter is loaded into the
capture register TB0CP0H/L at the rising edge of the timer flip-flop TA1FF of
8bit timers (TMRA01), and TB0CP1H/L at its falling edge.
The frequency is calculated by the difference between the loaded values in
TB0CP0H/L and TB0CP1H/L when the interrupt (INTTA0 or INTTA1) is
generated by either 8 bit timer.

Count clock
(TB0IN0 pin input)

C1

C2

TA1FF
Loading to TB0CP0H/L
Loading to TB0CP1H/L

C1

C1
C2

C2

INTTA0/INTTA1

Figure 3.13.14 Frequency Measurement
For example, if the value for the level 1 width of TA1FF of the 8 bit timer is set
to 0.5[s] and the difference between TB0CP0H/L and TB0CP1H/L is 100, the
frequency will be 100/0.5[s] =200[Hz].
Note: The frequency in this examole is calculated with 50% duty.

92CZ26A-313

TMP92CZ26A
3.

Pulse width measurement
This mode allows measuring the H level width of an external pulse. While
keeping the 16 bit timer/event counter counting (free-running) with the
internal clock input, the external pulse is input through the TB0IN0 pin. Then
the capture function is used to load the UC10 values into TB0CP0H/L and
TB0CP1H/L at the rising edge and falling edge of the external trigger pulse
respectively. The interrupt INT6 occurs at the falling edge of TB0IN0.
The pulse width is obtained from the difference between the values of
TB0CP0H/L and TB0CP1H/L and the internal clock cycle.
For example, if the internal clock is 0.8[us] and the difference between
TB0CP0H/L and TB0CP1H/L is 100, the pulse width will be 100 × 0.8[us] =80us
Additionally, the pulse width which is over the UC10 maximum count time
specified by the clock source can be measured by changing software.

Count clock
(Prescaler ouptut clock)
TB0IN0 pin input
(External pulse)
Loading to TB0CP0H/L

C2

C1

C1

C1
C2

C2

Loading to TB0CP1H/L
INT6

Figure 3.13.15 Pulse Width Measurement

Note: Only in this pulse width measuring mode(TB0MOD “10”), external interrupt INT6 occurs at the
falling edge of TB0IN0 pin input. In other modes, it occurs at the rising edge.

The width of L level can be measured by multiplying the difference between the
first C1 and the second C0 at the second INT6 interrupt and the internal
clock cycle together.

92CZ26A-314

TMP92CZ26A

3.14

Serial Channels (SIO)

TMP92CZ26A includes 1 serial I/O channel (SIO0). For both channels either UART mode
(Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected.
And, SIO0 includes data modulator that supports the IrDA 1.0 infrared data communication
specification.

• I/O interface mode

Mode 0:

• UART mode

Mode 1:
Mode 2:
Mode 3:

For transmitting and receiving I/O data using
the synchronizing signal SCLK for extending
7-bit data
8-bit data
9-bit data

In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wakeup function for making
the master controller start slave controllers via a serial link (A multi-controller system).
Figure 3.14.1 is block diagrams for each channel.
SIO0 is compounded mainly prescaler, serial clock generation circuit, receiving buffer and
control circuit, transmission buffer and control circuit.
•

Mode 0 (I/O interface mode)
Bit0

1

2

3

4

5

6

7

Transfer direction
•

•

Mode 1 (7-bit UART mode)
No parity

Start

Bit0

1

2

3

4

5

6

Stop

Parity

Start

Bit0

1

2

3

4

5

6

Parity Stop

Start

Bit0

1

2

3

4

5

6

7

Stop

Start

Bit0

1

2

3

4

5

6

7

Parity Stop

Start

Bit0

1

2

3

4

5

6

7

8

Stop

Start

Bit0

1

2

3

4

5

6

7

Bit8

Stop

Mode 2 (8-bit UART mode)
No parity
Parity

•

Mode 3 (9-bit UART mode)

Wakeup

When bit8 = 1, Address (Select code) is denoted.
When bit8 = 0, Data is denoted.

Figure 3.14.1 Data Formats

92CZ26A-315

TMP92CZ26A

3.14.1 Block Diagram

Prescaler
φT0

2 4 8 16 32 64
φT2

φT8

φT32

Serial clock generation circuit
BR0CR

TA0TRG
(from TMRA0)

BR0CR
BR0ADD
 

BR0CR

Baud rate generator

SC0MOD0


fIO

÷2
SCLK0

SCLK0

(UART only ÷ 16)

SC0MOD0


I/O interface mode

INT request
INTRX0
INTTX0
SC0MOD0


Transmision
counter

Serial channel
interrupt control

(UART only ÷ 16)

TXDCLK

RXDCLK
SC0MOD0


Receive
control

Transmission
control
SC0CR



RXD0

Receive buffer 1 (Shift register)

RB8

SIOCLK

SC0CR


I/O interface mode

Receive counter

UART
mode

Selector

φT8
φT32

Selector

φT2

Selector

Selector

Prescaler

φT0

Receive buffer 2 (SC0BUF)

CTS0

SC0MOD0


Parity control

Error flag

SC0CR
  
Internal data bus

Figure 3.14.2 Block Diagram

92CZ26A-316

TB8

Transmission buffer (SC0BUF)

TXD0

TMP92CZ26A

3.14.2 Operation of Each Circuit
(1) Prescaler
There is a 6-bit prescaler for generating a clock to SIO0. The prescaler can be run by
selecting the baud rate generator as the serial transfer clock.
Table 3.14.1 shows prescaler clock resolution into the baud rate generator.

Table 3.14.1 Prescaler Clock Resolution to Baud Rate Generator
-

fc

Clock gear
SYSCR1


Clock Resolution
-

φT0

φT2

φT8

φT32

000(1/1)

fSYS/4

fSYS/16

fSYS/64

fSYS/256

001(1/2)

fSYS/8

fSYS/32

fSYS/128

fSYS/512

010(1/4)

fSYS/16

fSYS/64

fSYS/256

fSYS/1024

011(1/8)

fSYS/32

fSYS/128

fSYS/512

fSYS/2048

100(1/16)

fSYS/64

fSYS/256

fSYS/1024

fSYS/4096

1/4

XXX:Don’t care

The baud rate generator selects between 4-clock inputs: φT0, φT2, φT8, and φT32
among the prescaler outputs.

92CZ26A-317

TMP92CZ26A

(2) Baud rate generator
The baud rate generator is the circuit which generates transmission/receiving clock
and determines the transfer rate of the serial channels.
The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by
the 6-bit prescaler which is shared by the timers. One of these input clocks is selected
using the BR0CR field in the baud rate generator control register.
The baud rate generator includes a frequency divider, which divides the frequency
by 1 or N + (16 − K)/16 to 16 values, determining the transfer rate.
The transfer rate is determined by the settings of BR0CR
and BR0ADD.
• In UART mode
When BR0CR = 0
The settings BR0ADD are ignored. The baud rate generator divides
the selected prescaler clock by N, which is set in BR0CK. (N = 1, 2, 3 ...
16)
When BR0CR = 1
The N + (16 − K)/16 division function is enabled. The baud rate generator
divides the selected prescaler clock by N + (16 – K)/16 using the value of N set in
BR0CR (N = 2, 3 ... 15) and the value of K set in BR0ADD
(K = 1, 2, 3 ... 15)
Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Clear
BR0CR to 0.
• In I/O interface mode
The N + (16 − K)/16 division function is not available in I/O interface mode. Clear
BR0CR to 0 before dividing by N.
The method for calculating the transfer rate when the baud rate generator is used is
explained below.
•

In UART mode
Baud rate =

•

Input clock of baud rate generator
Frequency divider for baud rate generator

In I/O interface mode
Input clock of baud rate generator
Baud rate =
Frequency divider for baud rate generator

92CZ26A-318

÷ 16

÷2

TMP92CZ26A

• Integer divider (N divider)
For example, when the source clock frequency (fc) is 19.6608 MHz, the input
clock is φT2, the frequency divider N (BR0CR) = 8, and
BR0CR = 0, the baud rate in UART Mode is as follows:
*Clock state

Baud Rate =

System clock
Prescaler clock

:
:

1/1
1/2

fC/16
÷ 16 = 19.6608106 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps)
8

Note: The N + (16 – K) / 16 division function is disabled and setting BR0ADD
 is invalid.
• N+(16-K)/16 divider (UART Mode only)
Accordingly, when the source clock frequency (fc) = 15.9744 MHz, the input
clock is φT2, the frequency divider N (BR0CR) = 6, K
(BR0ADD) = 8, and BR0CR  = 1, the baud rate in UART
Mode is as follows:
*Clock state

Baud Rate =

System clock
Prescaler clock
fC /16
(16 – 8)
6+
16

:
:

1/1
1/2

÷ 16 = 15.9744 × 106 ÷ 16÷ (6 +
= 9600 (bps)

8
) ÷ 16
16

Table 3.14.2 show examples of UART Mode transfer rates.
Additionally, the external clock input is available in the serial clock. (Serial
Channel 0). The method for calculating the baud rate is explained below:
• In UART Mode
Baud rate = external clock input frequency ÷ 16
It is necessary to satisfy (external clock input cycle) ≥ 4/fSYS
• In I/O Interface Mode
Baud rate = external clock input frequency
It is necessary to satisfy (external clock input cycle) ≥ 16/fSYS

92CZ26A-319

TMP92CZ26A

Table 3.14.2 Transfer Rate Selection

Unit (kbps)

(When baud rate generator is used and BR0CR = 0)
fSYS [MHz]

Input Clock
Frequency Divider N

φT0
(fSYS/4)

φT2
( fSYS/16)

φT8
(fSYS/64)

φT32
(fSYS/256)

7.3728

1

115.200

28.800

7.200

1.800

↑

3

38.400

9.600

2.400

0.600

↑

6

19.200

4.800

1.200

0.300

↑

A

11.520

2.880

0.720

0.180

↑

C

9.600

2.400

0.600

0.150

↑

F

7.680

1.920

0.480

0.120

9.8304

1

153.600

38.400

9.600

2.400

↑

2

76.800

19.200

4.800

1.200

↑

4

38.400

9.600

2.400

0.600

↑

5

30.720

7.680

1.920

0.480

↑

8

19.200

4.800

1.200

0.300

↑

0

9.600

2.400

0.600

0.150

44.2368

6

115.20

28.800

7.200

1.800

↑

9

76.800

19.200

4.800

1.200

58.9824

2

460.800

115.200

28.800

7.200

↑

3

307.200

76.800

19.200

4.800

↑

5

184.320

46.080

11.520

2.880

↑

6

153.600

38.400

9.600

2.400

↑

8

115.200

28.800

7.200

1.800

↑

C

76.800

19.200

4.800

1.200

↑

F

61.440

15.360

3.840

0.960

73.728

1

1152.000

288.000

72.000

18.000

↑

3

384.000

96.000

24.000

6.000

↑

6

192.000

48.000

12.000

3.000

↑

A

115.200

28.800

7.200

1.800

↑

C

96.000

24.000

6.000

1.500

↑

F

76.800

19.200

4.800

1.200

Note: Transfer rates in I/O interface mode are eight times faster than the values given above.

Timer out clock (TA0TRG) can be used for source clock of UART mode only.

Calculation method the frequency of TA0TRG
Frequency of TA0TRG =

Baud rate × 16

Note: In case of I/O interface mode, prohibit to use TA0TRG for source clock.

92CZ26A-320

TMP92CZ26A

(3) Serial clock generation circuit
This circuit generates the basic clock for transmitting and receiving data.
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR = 0, the basic clock is
generated by dividing the output of the baud rate generator by 2, as described
previously.
In SCLK Input Mode with the setting SC0CR = 1, the rising edge or falling edge
will be detected according to the setting of the SC0CR register to generate
the basic clock.
• In UART Mode
The SC0MOD0  setting determines whether the baud rate generator clock,
the internal clock fIO, the match detect signal from timer TMRA0 or the external clock
(SCLK0) is used to generate the basic clock SIOCLK.
(4) Receiving counter
The receiving counter is a 4-bit binary counter used in UART Mode, which counts up
the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data;
each data bit is sampled three times - on the 7th, 8th and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority
rule.
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
(5) Receiving control
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR = 0, the RXD0 signal is
sampled on the rising or falling edge of the shift clock which is output on the SCLK0
pin, according to the SC0CR setting.
In SCLK Input Mode with the setting SC0CR = 1, the RXD0 signal is sampled
on the rising or falling edge of the SCLK0 input, according to the SC0CR
setting
• In UART Mode
The receiving control block has a circuit, which detects a start bit using the majority
rule. Received bits are sampled three times; when two or more out of three samples
are 0, the bit is recognized as the start bit and the receiving operation commences.
The values of the data bits that are received are also determined using the majority
rule.

92CZ26A-321

TMP92CZ26A

(6) The Receiving Buffers
To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer
structure.
Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift
register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored
data is transferred to Receiving Buffer 2 (SC0BUF); these causes an INTRX0
interrupt to be generated. The CPU only reads Receiving Buffer 2 (SC0BUF). Even
before the CPU reads receiving Buffer 2 (SC0BUF), the received data can be stored in
Receiving Buffer 1. However, unless Receiving Buffer 2 (SC0BUF) is read before all
bits of the next data are received by Receiving Buffer 1, an overrun error occurs. If an
Overrun error occurs, the contents of Receiving Buffer 1 will be lost, although the
contents of Receiving Buffer 2 and SC0CR will be preserved.
SC0CR is used to store either the parity bit - added in 8-Bit UART Mode - or
the most significant bit (MSB) - in 9-Bit UART Mode.
In 9-Bit UART Mode the wake-up function for the slave controller is enabled by
setting SC0MOD0 to 1; in this mode INTRX0 interrupts occur only when the
value of SC0CR is 1.
SIO interrupt mode is selectable by the register SIMC.
Note1: The double buffer structure does not support SC0CR.
Note2: If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2,
the data may not be read properly. To avoid this situation, a read of receive buffer 2 should be triggered by
a receive interrupt.

(7) Notes for Using Receive Interrupts
• Receive interrupts can be detected either in level or edge mode. For details, see the
description of the SIO/SEI receive interrupt mode select register SIMC in the
section on interrupts.
• When receive interrupts are set to level mode, once an interrupt occurs, the same
interrupt will occur repeatedly even after control has jumped to the interrupt
routine unless interrupts are disabled.
(8) Transmission counters
The transmission counter is a 4-bit binary counter which is used in UART Mode and
which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is
generated every 16 SIOCLK clock pulses.
SIOCLK
15

16

1

2

3

4

5

6

7

8

9

10

11

12

TXDCLK

Figure 3.14.3 Generation of the transmission clock

92CZ26A-322

13

14

15

16

1

2

TMP92CZ26A

(8) Transmission controller
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR = 0, the data in the
Transmission Buffer is output one bit at a time to the TXD0 pin on the rising edge or
falling of the shift clock which is output on the SCLK0 pin, according to the
SC0CR setting.
In SCLK Input Mode with the setting SC0CR = 1, the data in the Transmission
Buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the
SCLK0 input, according to the SC0CR setting.
• In UART Mode
When transmission data sent from the CPU is written to the Transmission Buffer,
transmission starts on the rising edge of the next TXDCLK.

92CZ26A-323

TMP92CZ26A
Handshake function
Serial Channels 0 has a CTS0 pin. Use of this pin allows data can be sent in units of
one frame; thus, Overrun errors can be avoided. The handshake functions is enabled
or disabled by the SC0MOD  setting.
When the CTS0 pin goes High on completion of the current data send, data
transmission is halted until the CTS0 pin goes Low again. However, the INTTX0
Interrupt is generated, it requests the next data send to the CPU. The next data is
written in the Transmission Buffer and data sending is halted.
Though there is no RTS pin, a handshake function can be easily configured by setting
any port assigned to be the RTS function. The RTS should be output "High" to request
send data halt after data receive is completed by software in the RXD interrupt
routine.

TMP92CZ26A

TMP92CZ26A

TXD

RXD

CTS0

RTS (Any port)

Sender

Receiver

Figure 3.14.4 Handshake function
Timing to writing to the
transmission buffer
CTS0

Send is suspended
(1) from (1) and (2) (2)
13

14

15

16

1

2

3

14

15

16

1

2

3

SIOCLK
TXDCLK
Start bit

TXD

bit0

Note 1: (1) If the CTS 0 signal goes High during transmission, no more data will be sent after completion of the
current transmission.
Note 2: (2) Transmission starts on the first falling edge of the TXDCLK clock after the CTS0 signal has fallen.

Figure 3.14.5 CTS0 (Clear to send) Timing

92CZ26A-324

TMP92CZ26A

(9) Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data
written from the CPU form the least significant bit (LSB) in order. When all the bits
are shifted out, the transmission buffer becomes empty and generates an INTTX0
interrupt.
(10) Parity control circuit
When SC0CR in the serial channel control register is set to 1, it is possible to
transmit and receive data with parity. However, parity can be added only in 7-bit
UART mode or 8-bit UART mode. The SC0CR field in the serial channel
control register allows either even or odd parity to be selected.
In the case of transmission, parity is automatically generated when data is written
to the transmission buffer SC0BUF. The data is transmitted after the parity bit has
been stored in SC0BUF in 7-bit UART mode or in SC0MOD0 in 8-bit
UART mode. SC0CR and SC0CR must be set before the transmission
data is written to the transmission buffer.
In the case of receiving, data is shifted into receiving buffer 1, and the parity is
added after the data has been transferred to receiving buffer 2 (SC0BUF), and then
compared with SC0BUF in 7-bit UART mode or with SC0CR in 8-bit
UART mode. If they are not equal, a parity error is generated and the SC0CR
flag is set.
(11) Error flags
Three error flags are provided to increase the reliability of data reception.
1.

Overrun error 
If all the bits of the next data item have been received in receiving buffer 1
while valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun
error is generated.
The below is a recommended flow when the overrun error is generated.
(INTRX interrupt routine)
1) Read receiving buffer
2) Read error flag
3) If  = 1
then
a) Set to disable receiving (Write 0 to SC0MOD0)
b) Wait to terminate current frame
c) Read receiving buffer
d) Read error flag
e) Set to enable receiving (Write 1 to SC0MOD0)
f) Request to transmit again
4) Others

Note: Overrun errors are generated only with regard to receive buffer 2 (SC0BUF). Thus, if SC0CR is not
read, no overrun error will occur.

92CZ26A-325

TMP92CZ26A

2.

Parity error 
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
compared with the parity bit received via the RXD pin. If they are not equal, a
parity error is generated.

Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in
succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not
been cleared. To avoid this situation, a read of the parity error flag should be riggered by a receive interrupt.

3.

Framing error 
The stop bit for the received data is sampled three times around the center. If
the majority of the samples are 0, a Framing error is generated.

92CZ26A-326

TMP92CZ26A

(12) Timing generation
a.

In UART Mode

Receiving
Mode
Interrupt timing
Framing error timing

Center of last bit

Center of last bit

(bit 8)

(parity bit)

Center of stop bit

Center of stop bit

Parity error timing
Overrun error timing

8-Bit + Parity
(Note)

9-Bit
(Note)

Center of last bit

―

(parity bit)

Center of last bit

Center of last bit

(bit 8)

(parity bit)

8-Bit, 7-Bit + Parity, 7-Bit

Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit

Note1: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be
transferred) to allow checking for a framing error.
Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.

Transmitting
Mode
Interrupt timing

b.

9-Bit

8-Bit + Parity

8-Bit, 7-Bit + Parity, 7-Bit

Just before stop bit is

Just before stop bit is

Just

transmitted

transmitted

transmitted

before

stop

bit

is

I/O interface

Transmission

SCLK Output Mode

Immediately after last bit. (See Figure 3.14.13.)

Interrupt

SCLK Input Mode

Immediately after rise of last SCLK signal Rising Mode, or

SCLK Output Mode

Timing used to transfer received to data Receive Buffer 2 (SC0BUF)

timing
Receiving

immediately after fall in Falling Mode. (See Figure 3.14.14.)
(i.e. immediately after last SCLK). (See Figure 3.14.15.)

Interrupt
timing

SCLK Input Mode

Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.16.)

92CZ26A-327

TMP92CZ26A

3.14.3 SFR

Bit symbol
SC0MOD0
Read/Write
(1202H)
After Reset

7

6

5

4

3

2

1

0

TB8

CTSE

RXE

WU

SM1

SM0

SC1

SC0

0
Transfer
data bit 8

0
Hand shake
0: CTS
disable

Function

1: CTS
enable

0
Receive
function
0: Receive
disable
1: Receive
enable

R/W
0
0
0
Serial Transmission
Wake up
Mode
function
00: I/O interface Mode
0: disable
01: 7-bit UART Mode
1: enable
10: 8-bit UART Mode
11: 9-bit UART Mode

0
0
Serial transmission clock
(UART)
00: TMRA0 trigger
01: Baud rate
generator
10: Internal clock fIO
11: External clcok
(SCLK0 input)

Serial transmission clock source (UART)
00
01
10
11

TMRA0 match detect signal
Baud rate generator
Internal clock fIO
External clock (SCLK0 input)

Note: The clock selection for the I/O
interface mode is controlled by the
serial bontrol register (SC0CR).
Serial Transmission Mode
00
01
10
11

I/O Interface Mode
7-bit mode
UART mode 8-bit mode
9-bit mode

Wake-up function
9-Bit UART
Other Modes
Interrupt generated
0
whenever data is received
Don’t care
Interrupt generated only
1
when RB8 = 1
Receiving Function
0
1

Receive disabled
Receive enabled

Handshake function (/CTS pin)
0
1

Disabled (always transferable)
Enabled

Transmission data bit 8

Figure 3.14.6 Serial Mode Control Register (channel 0, SC0MOD0)

92CZ26A-328

TMP92CZ26A

7
SC0CR
(1201H)

Prohibit
to Read
modify
Write

bit Symbol
Read/Write
After Reset

Function

6

5

4

RB8
EVEN
PE
R
R/W
Undefined
0
0
Received
Parity
Parity
data bit 8
0: odd
addition
1: even
0: disable
1: enable

3

2

1

OERR
PERR
FERR
R (cleared to 0 when read)
0
0
0

0

SCLKS
IOC
R/W
0
0
0: SCLK0 0: baud rate

1: error

generator
1: SCLK0

Overrun

Parity

Framing

1: SCLK0

pin input

I/O interface input clock selection
0
1

Baud rate generator
SCLK0 pin input

Edge selection for SCLK pin (Input / Output Mode)
Transmits and receivers
data on rising edge of SCLK0.
Transmits and receivers
data on falling edge SCLK0.

0
1

Framing Error flag
Parity Error flag
Overrun Error flag

Cleared to 0
when read

Parity addition enables
0
1

Disabled
Enabled

Even parity addition/check
0
1

Odd parity
Even parity

Received data 8

Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing
instruction.

Figure 3.14.7 Serial Control Register (channel 0, SC0CR)

92CZ26A-329

TMP92CZ26A

Bit symbol

BR0CR
(1203H)

7

6

5

4

3

2

1

0

−

BR0ADDE

BR0CK1

BR0CK0

BR0S3

BR0S2

BR0S1

BR0S0

0

0

0

0

0

0

0

0

Read/Write

R/W

After Reset

Always
write “0”
Function

+(16−K)/16
division
0: Disable
1: Enable

00: φT0
01: φT2
10: φT8
11: φT32

Divided frequency setting

+(16−K)/16 division enable

Setting the input clock of baud rate generator

0

Disable

00

Internal clock φT0

1

Enable

01

Internal clock φT2

10

Internal clock φT8

11

Internal clock φT32

7

6

5

4

bit Symbol
Read/Write
BR0ADD
(1204H) After reset

3

2

1

0

BR0K3

BR0K2

BR0K1

BR0K0

0

0

0

0

R/W

Sets frequency divisor “K”
(divided by N + (16-K) / 16)

Function

Sets baud rate generator frequency divisor
BR0CR = 1
BR0CR
0000(N = 16)

or
BR0ADD
0001 (N = 1)


BR0CR = 0

0010 (N = 2)
to
1111 (N = 15)

0000

Disable

Disable

0001(K = 1)
to
1111(K = 15)

Disable

Divided by
N + (16-K) /16

0001 (N = 1) (UART only)
to
1111(N = 15)
0000(N = 16)
Divided by N

Note1:Availability of +(16-K)/16 division function
N

UART mode

I/O mode

2 to 15

○

×

1 , 16

×

×

The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in I/O
interface mode.
Note2:Set BR0CR  to 1 after setting K (K = 1 to 15) to BR0ADD when +(16-K)/16 division function is
used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is read from these
unused bits.

Figure 3.14.8 Baud rate generator control (channel 0, BR0CR, BR0ADD)

92CZ26A-330

TMP92CZ26A

7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0

7

6

5

4

3

2

1

0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

(Transmission)

SC0BUF
(1200H)
(Receiving)

Note: Prohibit read modify write for SC0BUF.

Figure 3.14.9 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF)

SC0MOD1
(1205H)

7

6

Bit symbol

I2S0

FDPX0

Read/Write

R/W

R/W

After Reset

0

Function

5

4

3

2

0

IDLE2

duplex

0: Stop

0: half

1: Run

1: full

Figure 3.14.10 Serial Mode Control Register 1 (channel 0, SC0MOD1)

92CZ26A-331

1

0

TMP92CZ26A

3.14.4

Operation in each mode
(1) Mode 0 (I/O Interface Mode)
This mode allows an increase in the number of I/O pins available for transmitting
data to or receiving data from an external shift register.
This mode includes the SCLK output mode to output synchronous clock SCLK and
SCLK input mode to input external synchronous clock SCLK.

Output extension
TMP92CZ26A

Input extension
Shift register

A

TMP92CZ26A

Shift register

B
TXD

SI

B

C

RXD

QH

C

D
SCLK

SCK

D

E

SCLK

CLOCK

E

S/ L

G
H

F
Port

RCK

A

F

G
H

Port

TC74HC595 or equivalent

TC74HC165 or equivalent

Figure 3.14.11 SCLK Output Mode connection example
Output extension

Input extension

TMP92CZ26A

Shift register

A

TMP92CZ26A

Shift register

B
TXD

SI

C

B
RXD

QH

D
SCLK

SCK

E

RCK

G
H

TC74HC595 or equivalent
External clock

CLOCK

E

S/ L

G
H

F
Port

TC74HC165 or equivalent
External clock

Figure 3.14.12 Example of SCLK Input Mode Connection

92CZ26A-332

C
D

SCLK

F
Port

A

TMP92CZ26A

a.

Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and
SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer.
When all data is output, INTES0  will be set to generate the INTTX0 interrupt.

Timing to write
transmisison data
SCLK0 output
( = 0:
rising edge mode)

(Internal clock
timing)

SCLK0 output
( = 1:
falling edge mode)
TXD0

Bit0

Bit1

Bit6

Bit7

ITX0C
(INTTX0 interrupt
request)

Figure 3.14.13 Transmitting Operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input Mode, 8-bit data is output on the TXD0 pin when the SCLK0 input
becomes active after the data has been written to the Transmission Buffer by the
CPU.
When all data is output, INTES0  will be set to generate INTTX0
interrupt.
SCLK0 input
( = 0:
rising edge mode)
SCLK0 input
( = 1:
falling edge mode)
TXD0

Bit0

Bit1

Bit5

Bit6

Bit7

ITX0C
(INTTX0 intterrupt
reqest)

Figure 3.14.14 Transmitting Operation in I/O Interface Mode (SCLK0 Input Mode)

92CZ26A-333

TMP92CZ26A

b.

Receiving
In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the
data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag
INTES0 is cleared as the received data is read. When 8-bit data is received,
the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown
below and INTES0 is set to 1 again, causing an INTRX0 interrupt to be
generated.
Setting SC0MOD0 to 1 initiates SCLK0 output.

IRX0C
(INTRX0 interrupt
request)
SCLK0 output
( = 0:
rising edge mode)
SCLK0 output
( = 1:
falling edge mode)
RXD0

Bit0

Bit1

Bit6

Bit7

Figure 3.14.15 Receiving operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input Mode the data is shifted to Receiving Buffer 1 when the SCLK input
goes active. The SCLK input goes active when the Receive Interrupt flag INTES0
 is cleared as the received data is read. When 8-bit data is received, the data
is shifted to Receiving Buffer 2 (SC0BUF) following the timing shown below and
INTES0  is set to 1 again, causing an INTRX0 interrupt to be generated.

SCLK0 input
( = 0:
rising edge mode)
SCLK0 input
( = 1:
falling edge mode)
RXD1

Bit

Bit1

Bit5

Bit6

Bit7

IRX0C
(INTRX0 interrupt request)

Figure 3.14.16 Receiving Operation in I/O interface Mode (SCLK0 Input Mode)
Note: The system must be put in the Receive Enable state (SC0MOD0 = 1) before data can be received.

92CZ26A-334

TMP92CZ26A

c.

Transmission and Receiving (Full Duplex Mode)
When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable
the level of transmit interrupt(1 to 6). Ensure that the program which transmits the
interrupt reads the receiving buffer before setting the next transmit data.
The following is an example of this:
Example:

Channel 0, SCLK output
Baud rate = 9600 bps
fsys = 2.4576 MHz

Main routine
7

6

5

4

3

2

1

0

INTES0

X

0

0

1

X

0

0

0

P9CR

X

X

X

X

X

1

0

1

Set P90, P91 and P92 to function as the TXD0,

P9FC

−

−

X

X

X

1

X

1

RXD0 and SCLK0 pins respectively.

SC0MOD0

−

−
X

0

−

−
X

0

SC0MOD1

−
1

X

X

−
X

−
X

Select full duplex mode.

SC0CR

−
0

−
0

−
0

−
1

−
1

−
0

0

0

SCLK0 output mode, select rising edge

0

0

Baud rate = 9600 bps.

−
*

−
*

1
*

−
*

−
*

−
*

−
*

−
*

Set the transmit data and start.

*

*

*

*

*

Set the next transmit data.

Set the INTTX0 level to 1.
Set the INTRX0 level to 0.

BR0CR
SC0MOD0
SC0BUF

Select I/O interface mode.

Enable receiving.

INTTX0 interrupt routine
ACC
SC0BUF

← SC0BUF
*

*

*

Read the receiving buffer.

X: Don't care, −: No change

92CZ26A-335

TMP92CZ26A

(2) Mode 1 (7-bit UART Mode)
7-Bit UART Mode is selected by setting the Serial Channel Mode Register
SC0MOD0 field to 01.
In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the
setting of the Serial Channel Control Register SC0CR bit; whether even parity
or odd parity will be used is determined by the SC0CR setting when
SC0CR is set to 1 (enabled).
Setting example:

Start

When transmitting data of the following format, the control
registers should be set as described below.

Bit0

2

1

3

4

5

6

Even
parity

Transmission direction (Transmission rate: 2400 bps at fSYS = 19.6608 MHz)
7

6

5

4

3

2

1

0

P9CR

← X

X

X

X

X

−

1

P9FC

← −
← X

−
0

X

X

X

−
X

← −
← 0

1

−
1

0

1

Set P90 to function as the TXD0 pin.

X

0

−
1

0

1

Select 7-bit UART mode.

−
0

−
1

−
0

−
0

−
0

Set the transfer rate to 2400 bps.

← X 1 0 0
← * * * *
X: Don't care, −: No change

X
*

0
*

0
*

0
*

Set data for transmission.

SC0MOD0
SC0CR
BR0CR
INTES0

SC0BUF

1

Add even parity.
Enable the INTTX0 interrupt and set it to interrupt level 4.

(3) Mode 2 (8-Bit UART Mode)
8-Bit UART Mode is selected by setting SC0MOD0 to 10. In this mode a
parity bit can be added (use of a parity bit is enabled or disabled by the setting of
SC0CR); whether even parity or odd parity will be used is determined by the
SC0CR setting when SC0CR is set to 1 (enabled).

Setting example:

Start

Bit0

When receiving data of the following format, the control
registers should be set as described below.
1

2

3

4

5

6

7

Odd
parity

Stop

Transmission direction (Transmission rate: 9600 bps at fSYS = 19.6608 MHz)

92CZ26A-336

TMP92CZ26A

Main routine
7

6

5

4

3

2

1

P9CR

← X

X

X

X

X

−

0

0
−

Set P91 to function as the RXD0 pin.

P9FC

← −

−

X

X

X

X

SC0MOD0

← −

1

−

1

0

−
1

Enable receiving in 8-bit UART mode.

SC0CR

1

BR0CR

← −
← 0

−
0

−
0

0

0

−
1

−
1

−
0

−
0

−
0

Set the transfer rate to 9600 bps.

INTES0

← X

1

0

0

X

0

0

0

Enable the INTTX0 interrupt and set it to interrupt

Add odd parity.

level 4.
Interrupt routine
← SC0CR AND 00011100

ACC

Check for errors

if ACC ≠ 0 then ERROR
← SC0BUF

ACC

Read the received data

X: Don't care, −: No change

(4) Mode 3 (9-Bit UART Mode)
9-Bit UART Mode is selected by setting SC0MOD0 to 11. In this mode
parity bit cannot be added.
In the case of transmission the MSB (9th bit) is written to SC0MOD0. In the
case of receiving it is stored in SC0CR. When the buffer is written and read, the
MSB is read or written first, before the rest of the SC0BUF data.
Wake-up function
In 9-Bit UART Mode, the wake-up function for slave controllers is enabled by
setting SC0MOD0 to 1. The interrupt INTRX0 can only be generated
when = 1.

TXD

RXD

Master

TXD

RXD

Slave1

TXD

RXD

Slave 2

Note: The TXD pin of each slave controller must be in Open-Drain Output Mode.

Figure 3.14.17 Serial Link using Wake-up function

92CZ26A-337

TXD

RXD

Slave 3

TMP92CZ26A

Protocol
1.

Select 9-Bit UART Mode on the master and slave controllers.

2.

Set the SC0MOD0 bit on each slave controller to 1 to enable data receiving.

3.

The master controller transmits data one frame at a time. Each frame includes an 8-bit
select code which identifies a slave controller. The MSB (bit 8) of the data () is
set to 1.
Start

Bit0

1

2

3

4

5

6

7

Select code of slave controller

8

Stop

“1”

4.

Each slave controller receives the above frame. Each controller checks the above select
code against its own select code. The controller whose code matches clears its 
bit to 0.

5.

The master controller transmits data to the specified slave controller (the controller
whose SC0MOD0 bit has been cleared to 0). The MSB (bit 8) of the data
() is cleared to 0.

Start

Bit0

1

2

3

4

5

Data

6.

6

7

Bit8

Stop

“0”

The other slave controllers (whose  bits remain at 1) ignore the received data
because their MSBs (bit 8 or ) are set to 0, disabling INTRX0 interrupts.
The slave controller whose  bit = 0 can also transmit to the master controller. In
this way it can signal the master controller that the data transmission from the
master controller has been completed.

92CZ26A-338

TMP92CZ26A

Setting example: To link two slave controllers serially with the master controller using the
internal clock fIO as the transfer clock.

TXD

RXD

TXD

Master

RXD

TXD

RXD

Slave1

Slave 2

Select code
00000001

Select code 00001010

• Setting the master controller
Main routine

P9FC

← X X XX X − 0 1
← − − XX X − X 1

Set P90 and P91 to function as the TXD0 and RXD0 pins

INTES0

← X 1 0 0 X 1 0 1

Enable the INTTX0 interrupt and set it to Interrupt Level 4.

P9CR

respectively.
Enable the INTRX0 interrupt and set it to Interrupt Level 5.

SC0MOD0 ← 1 0 1 0 1 1 1 0
SC0BUF

← 0 0 0 0 0 0 0 1

Set fIO as the transmission clock for 9-Bit UART Mode.
Set the select code for slave controller 1.

Interrupt routine (INTTX0)
SC0MOD0 ← 0 − − − − − − −
SC0BUF
← * * * * * * * *

Set TB8 to 0.
Set data for transmission.

• Setting the slave controller
Main routine
P9CR
P9FC
P9FC2

← X X X X X − 0 1
← − − X X X − X 1
← X X X X X X X 1

← X 1 0 0 X 1 0 0
SC0MOD0 ← 0 0 1 1 1 1 1 0
INTES0

Select P91 and P90 to function as the RXD0 and TXD0 pins
respectively (open-drain output).
Enable INTRX0 and INTTX0.
Set  to 1 in 9-Bit UART Transmission Mode using fSYS as
the transfer clock.

Interrupt routine (INTRX0)
Acc ← SC0BUF
if Acc =Select code
Then SC0MOD0 ← − − − 0 − − − − Clear  to 0.

92CZ26A-339

TMP92CZ26A

3.14.5 Support for IrDA
SIO0 includes support for the IrDA 1.0 infrared data communication specification.
Figure 3.14.8 shows the block diagram.

Transmisison
data

SIO0

TXD0
IR modulator

IR transmitter & LED

IR output

Modem
Receive
data

IR demodulator

RXD0

IR receiver

IR input

TMP92CZ26A

Figure 3.14.18 Block Diagram
(1) Modulation of the transmission data
When the transmit data is 0, the modem outputs 1 to TXD0 pin with either 3/16 or
1/16 times for width of baud-rate. The pulse width is selected by the SIRCR.
When the transmit data is 1, the modem outputs 0.

Transmission
data

Start

0

1

0

0

1

1

0

0

Stop

TXD0 pin

Figure 3.14.19 Transmission example
(2) Modulation of the receive data
When the receive data is the effective width of pulse “1”, the modem outputs “0” to
SIO0. Otherwise the modem outputs “1” to SIO0. The effective pulse width is selected
by SIRCR.
RXD0 pin

Receive data

Start

1

0

0

1

0

Figure 3.14.20 Receiving example

92CZ26A-340

1

1

0

Stop

TMP92CZ26A

(3) Data format
The data format is fixed as follows:
• Data length:

8-bit

• Parity bits:

none

• Stop bits:

1bit

(4) SFR
Figure 3.14.21 shows the control register SIRCR. Set the data SIRCR during SIO0
is stopping. The following example describes how to set this register:
1) SIO setting

; Set the SIO to UART Mode.

↓
2) LD (SIRCR), 07H

; Set the receive data pulse width to 16×.

3) LD (SIRCR), 37H

; TXEN, RXEN Enable the Transmission and receiving.

↓
4) Start transmission

; The modem operates as follows:

and receiving for SIO0

y SIO0 starts transmitting.
y IR receiver starts receiving.

92CZ26A-341

TMP92CZ26A
(5) Notes
1. Baud rate for IrDA
When IrDA is operated, set 01 to SC0MOD0 to generate
baud-rate.
The setting except above (TA0TRG, fIO and SCLK0-input) cannot be used.
2. The pulse width for transmission
The IrDA 1.0 specification is defined in Table 3.14.3.

Table 3.14.3 Baud rate and pulse width specifications
Baud Rate

Modulation

Rate Tolerance

Pulse Width

Pulse Width

Pulse width

(% of rate)

(minimum)

(typical)

(maximum)
88.55 μs

2.4 kbps

RZI

±0.87

1.41 μs

78.13 μs

9.6 kbps

RZI

±0.87

1.41 μs

19.53 μs

22.13 μs

19.2 kbps

RZI

±0.87

1.41 μs

9.77 μs

11.07 μs

38.4 kbps

RZI

±0.87

1.41 μs

4.88 μs

5.96 μs

57.6 kbps

RZI

±0.87

1.41 μs

3.26 μs

4.34 μs

115.2 kbps

RZI

±0.87

1.41 μs

1.63 μs

2.23 μs

The infra-red pulse width is specified either baud rate T× 3/16 or 1.6 μs (1.6 μs is equal to
3/16 pulse width when baud rate is 115.2 kbps).
The TMP92CZ26A has the function selects the pulse width of Transmission either 3/16 or
1/16. But 1/16 pulse width can be selected when the baud rate is equal or less than 38.4
kbps.
As the same reason, + (16 − k)/16 division function in the baud rate generator of SIO0 can
not be used to generate 115.2 kbps baud rate.
Also when the 38.4 kbps and 1/16 pulse width, + (16-K)/16 division function can not be used.

Table 3.14.4 Baud rate and pulse width for (16 – K) / 16 division function
Baud Rate

Pulse Width
115.2 Kbps 57.6 Kbps

38.4 Kbps

19.2 Kbps

9.6 Kbps

2.4 Kbps

○
○

○
○

○
○

T × 3/16

× (Note)

○

○

T × 1/16

−

−

×

○: Can be used (16 − K)/16 division function
×: Cannot be used (16 − K)/16 division function
−: Cannot be set to 1/16 pulse width
Note: Can be used (16 − K)/16 division function at a special condition.

92CZ26A-342

TMP92CZ26A

SIRCR
(1207H)

Bit symbol

7

6

5

4

PLSEL

RXSEL

TXEN

RXEN

Read/Write

3

2

1

0

SIRWD3

SIRWD2

SIRWD1

SIRWD0

0

0

0

R/W

After reset

0

0

Function

Select
transmit
pulse width
0: 3/16
1: 1/16

Receive
data
0: “H” pulse
1: “L” pulse

0

0

Transmit
0: disable
1: enable

Receive
0: disable
1: enable

0

Select receive pulse width
Set effective pulse width for equal or more than 2x ×
(value + 1) + 100ns
Can be set
: 1 to 14
Can not be set : 0, 15

Select receive pulse width
Formula: Effective pulse width ≥ 2x × (value + 1) + 100ns
x = 1/fFPH
0000

Cannot be set

0001

Equal or more than 4x + 100ns

to
1110

Equal or more than 30x + 100ns

1111

Can not be set

Receive (recovery) operation
0

Disable receiving operation
(Received data is ignored)

1

Enabled receiving operation

Transmit (modulation) operation
0

Disabled transmission operation
(Input from SIO is ignored)

1

Enabled transmission operation

Select transmit pulse width
0

3/16 pulse width

1

1/16 pulse width

Figure 3.14.21 IrDA Control Register

92CZ26A-343

TMP92CZ26A

3.15 Serial Bus Interface (SBI)
The TMP92CZ26A has a 1-channel serial bus interface which an I2C bus mode. This circuit
supports only I2C bus mode (Multi master).
The serial bus interface is connected to an external device through PV6 (SDA) and PV7 (SCL)
in the I2C bus mode.
Each pin is specified as follows.

PVFC2
11

I2C bus mode

PVCR
11

PVFC
11

3.15.1 Configuration

INTSBI interrupt request
SCL
SCK
SIO
clock
control
Input/
output
control
fSYS/4

Divider

2

Noise
canceller

I C bus
clock
sync. +
control

SO

SIO
data control

Transfer
control
circuit

SI

PV7
(SCL)

2

Shift
register

I C bus
data control

SBICR2/
SBISR

I2CAR

SBIDBR

SBICR0, 1

SBI control
register 2/
SBI status
register

I C bus
address
register

2

SBI data
buffer
register

SBI control
register 0, 1

Noise
canceller

SBIBR0
SBI baud rate
register 0

Figure 3.15.1 Serial bus interface (SBI)

92CZ26A-344

PV6
(SDA)

SDA

TMP92CZ26A

3.15.2 Serial Bus Interface (SBI) Control
The following registers are used to control the serial bus interface and monitor the
operation status.
z

Serial bus interface control register 0 (SBICR0)

z

Serial bus interface control register 1 (SBICR1)

z

Serial bus interface control register 2 (SBICR2)

z

Serial bus interface data buffer register (SBIDBR)

z

I2C bus address register (I2CAR)

z

Serial bus interface status register (SBISR)

z

Serial bus interface baud rate register 0 (SBIBR0)

3.15.3 The Data Formats in the I2C Bus Mode
The data formats in the I2C bus mode is shown below.
(a) Addressing format
1

8 bits
S

Slave address

R A
/ C
W K

1 to 8 bits

1

1 to 8 bits

Data

A
C
K

Data

1

1
A
C P
K

1 or more

(b) Addressing format (with restart)
1

8 bits
S

1 to 8 bits

R A
/ C
W K

Slave address

A
C S
K

Data

1

1

8 bits

1

R A
/ C
W K

Slave address

1 or more

1

S

Data

1

1 to 8 bits

1

1 to 8 bits

A
C
K

Data

A
C
K

Data

1
S:

1
A
C P
K

1 or more
Start condition
R/ W :

Direction bit

ACK:

Acknowledge bit

P:

Stop condition

Figure 3.15.2 Data format in the I2C bus mode

92CZ26A-345

Data
1 or more

(c) Free data format (data transferred from master device to slave device)
8 bits

1 to 8 bits

1
A
C P
K

TMP92CZ26A

3.15.4 I2C Bus Mode Control Register
The following registers are used to control and monitor the operation status when using
the serial bus interface (SBI) in the I2C bus mode.

Serial Bus Interface Control Register 0

SBICR0
(1247H)
Prohibit
ReadmodifyWrite

7

6

5

4

3

2

1

0

Bit symbol

SBIEN

−

−

−

−

−

−

−

Read/Write

R/W

After Reset

0

0

0

0

0

0

0

Function

SBI

R
0

Always read “0”.

operation
0 : disable
1 : enable

 : When using SBI,  should be set “1” (SBI operation enable) before setting each register of SBI
module.

Figure 3.15.3 Registers for the I2C bus mode

92CZ26A-346

TMP92CZ26A
Serial Bus Interface Control Register 1
7
SBICR1
(1240H)

Bit symbol

BC2

Read/Write
Function

BC1

5
BC0

R/W

After Reset
Prohibit
Readmodifywrite

6

0

0

0

4

3

ACK

−

R/W

R

0

1

2
SCK2

1

0

SCK1

SCK0/
SWRMON

0

0/1(Note2)

R/W
0

R/W

Number of transferred bits

Acknowledge

Always

Internal serial clock selection and

(Note 1)

mode

read as

software reset monitor

specification “1”.
0: Not
generate
1: Generate

Internal serial clock selection  at write
fSYS=80MHz (Output to SCL pin), Clock gear = fc/1
000
−
n=4
001
−
n=5
010
−
n=6
System Clock: fSYS
(=80MHz)
011
−
n=7
Clock Gear : fc/1
100
68 kHz
n=8
fSYS/4
101
36 kHz
n=9
fscl = n
[Hz]
2
+ 35
110
18 kHz
n = 10
111 (Reserved) (Reserved)
Software reset state monitor  at read
0

During software reset

1

(Initial Data)

Acknowledge mode specification
0

Not generate clock pulse for acknowledge signal

1

Generate clock pulse for acknowledge signal

Number of bits transferred
 = 0


Number of

000
001
010
011
100
101
110
111

clock pulses
8
1
2
3
4
5
6
7

 = 1

Bits

Number of

Bits

8
1
2
3
4
5
6
7

clock pulses
9
2
3
4
5
6
7
8

8
1
2
3
4
5
6
7

Note1: For the frequency of the SCL line clock, see 3.15.5 (3) Serial clock.
Note2: The initial data of SCK0 is “0”, the initialdata of SWRMON is “1” if SBI operation is enable
(SBICR0=“1”). If SBI operation is disable (SBICR0=“0”), the initialdata of SWRMON is “0”.
2

2

Note3: This I C bus circuit does not support Fast-mode, it supports the Standard mode only. Although the I C bus
2

circuit itself allows the setting of a baud rate over 100kbps, the compliance with the I C specification is not
guaranteed in that case.

Figure 3.15.4 Registers for the I2C bus mode

92CZ26A-347

TMP92CZ26A
Serial Bus Interface Control Register 1
SBICR2

Bit symbol

(1243H)

Read/Write
After reset

Prohibit

Function

7

6

MST

TRX

5

4

3

BB

PIN

SBIM1

W
0

0

selection

modifywrite

1

SBIM0

SWRST1

W (Note 1)
0

1

Master/Slave Transmitter Start/Stop

Read-

2

0

0
SWRST0

W (Note 1)
0

0

0

Software reset generate

Cancel

Serial bus interface

INTSBI

Generation interrupt

operating mode selection write “10” and “01”, then
an internal reset signal is
(Note 2)

0:Generate request

00: Port mode

/Receiver

condition

0:Slave

selection

1:Master

0:Receiver

generated.

stop

0:Don’t care 01: (Reserved)
2
condition 1:Cancel
10: I C Bus mode

1:Transmitter

1:Generate
start

interrupt

11: (Reserved)

request

condition

Serial bus interface operating mode selection (Note2)
00

Port Mode (Serial Bus Interface output disabled)

01

Reserved

10

I C Bus Mode

11

Reserved

2

Note 1: Reading this register functions as SBISR register.
Note 2: Switch a mode to port mode after confirming that the bus is free.
2

Switch a mode between I C bus mode and port mode after confirming that input signals via port are
high-level.

Figure 3.15.5 Registers for the I2C bus mode

Table 3.15.1Resolution of base clock
@fSYS = 80MHz

Clock Gear


Base Clock
Resolution

000(fc)

fSYS/2 (50ns)

001(fc/2)

fSYS/2 (0.1us)

010(fc/4)

fSYS/2 (0.2us)

011(fc/8)

fSYS/2 (0.4us)

100(fc/16)

fSYS/2 (0.8us)

2

3

4

5

92CZ26A-348

6

TMP92CZ26A
Serial Bus Interface Status Register
SBISR

Bit symbol

(1243H)

Read/Write
After reset

Prohibit

7

6

5

4

MST

TRX

BB

PIN

3

2

1

0

AL

AAS

AD0

LRB

0

0

0

0

R
0

0

0

1

Transmitter/ I C bus

2

INTSBI

Arbitration

Slave

GENERAL Last

Read-modif

Slave status Receiver

status

interrupt

lost

address

CALL

received bit

y-write

monitor

status

monitor

request

detection

match

detection

monitor

0:Slave

monitor

0:Free

monitor

monitor

detection

monitor

0: 0

1:Master

0:Receiver

1:Busy

0: Interrupt 0: −

monitor

0: Undetected 1: 1

Function

Master/

requested 1: Detected 0: Undetected 1: Detected
1: Detected

1:Tranmitter

1: Interrupt

canceled

Last received bit monitor
0

Last received bit was 0

1

Last received bit was 1

GENERAL CALL detection monitor
0

Undetected

1

GENERAL CALL detected

Slave address match detection monitor
0
1

Slave address don’t match or Undetected

Slave address match or GENERAL
CALL detected

Arbitration lost detection monitor
−

0
1

Arbitration lost

Note1: Writing in this register functions as SBICR2.
Note2: The initialdata SBISR is “1” if SBI operation is enable (SBICR0=“1”). If SBI operation is disable
(SBICR0=“0”), the initialdata of SBISR is “0”.

Figure 3.15.6 Registers for the I2C bus mode

92CZ26A-349

TMP92CZ26A
Serial Bus Interface Baud Rate Register 0
7

6

5

4

−

−

SBIBR0

Bit symbol

−

I2SBI

(1244H)

Read/Write

W

R/W

Prohibit

After reset

0

0

Read-modify

Function

-write

Always

IDLE2

read “0”

0: Stop

3

2

1

−

−

−

0
−

R
1

1

R/W

1

1

1

0

Always read as “1”

Always
write “0”.

1: Run
Operation during IDLE 2 mode
0

Stop

1

Operation

Serial Bus Interface Data Buffer Register
SBIDBR

Bit symbol

(1241H)

Read/Write

Prohibit

After reset

7

6

5

DB7

DB6

DB5

4

3

2

1

0

DB4

DB3

DB2

DB1

DB0

R (received)/W (transfer)

Read-modify

Undefined

-write
Note1: When writing transmitted data, start from the MSB (bit 7).Receiving data is placed from LSB(bit0).
Note2: SBIDBR can’t be read the written data because of it has buffer for writing and buffer for reading
individually.Therefore Read modify write instruction (e.g.“BIT” instruction ) is prohibitted.
Note3:Written data to SBIDBR is cleared by INTSBI signal.

I2C Bus Address Register
I2CAR

Bit symbol

(1242H)

Read/Write

Prohibit

After reset

Read-modify Function
-write

7

6

5

4

SA6

SA5

SA4

SA3

3

2

1

0

SA2

SA1

SA0

ALS

0

0

0

R/W
0

0

0

0

Slave address selection for when device is operating as slave device

0
Address
recognition
mode
specification

Address recognition mode specification
0

Slave address recognition

1

Non slave address recognition

Figure 3.15.7 Registers for the I2C bus mode

92CZ26A-350

TMP92CZ26A

3.15.5 Control in I2C Bus Mode
(1)

Acknowledge Mode Specification
When slave address is matched or detecting GENERAL CALL, and set the
SBICR1 to “1”, TMP92CZ26A operates in the acknowledge mode. The
TMP92CZ26A generates an additional clock pulse for an Acknowledge signal when
operating in Master Mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In
the receiver mode during the clock pulse cycle, the SDA pin is set to the Low in order
to generate the acknowledge signal.
Clear the  to “0” for operation in the Non-Acknowledge Mode; The
TMP92CZ26A does not generate a clock pulse for the Acknowledge signal when
operating in the Master Mode.

(2)

Number of transfer bits
The SBICR1 is used to select a number of bits for next transmitting and
receiving data.
Since the  is cleared to 000 as a start condition, a slave address and direction
bit transmission are executed in 8 bits. Other than these, the  retains a
specified value.

(3)

Serial clock
a. Clock source
The SBICR1  is used to select a maximum transfer frequency outputted
on the SCL pin in Master Mode. Set the baud rates, which have been calculated
according to the formula below, to meet the specifications of the I2C bus, such as the
smallest pulse width of tLOW,
tHIGH

tLOW

tLOW = (2 + 29)/(fSYS/4)
n-1

n−1

tHIGH = (2

+ 6)/(fSYS/4)

fscl = 1/(tLOW + tHIGH)
=

fSYS/4

1/fscl

SBICR1
000
001
010
011
100
101
110

n

2 + 35

Figure 3.15.8 Clock source

92CZ26A-351

n
4
5
6
7
8
9
10

TMP92CZ26A
b. Clock synchronization
In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down
a clock line to low-level, in the first place, invalidate a clock pulse of another master
device which generates a high-level clock pulse. The master device with a high-level
clock pulse needs to detect the situation and implement the following procedure.
The TMP92CZ26A has a clock synchronization function for normal data transfer even
when more than one master exists on the bus.
The example explains the clock synchronization procedures when two masters
simultaneously exist on a bus.
Wait counting high-level
width of a clock pulse
Start counting high-level width of a clock pulse
Internal SCL output
(Master A)
Internal SCL output
(Master B)

Reset a counting of
high-level width of a
clock pulse

SCL pin
a

b

c

Figure 3.15.9 Clock synchronization

As Master A pulls down the internal SCL output to the Low level at point “a”,
the SCL line of the bus becomes the Low-level. After detecting this situation,
Master B resets a counter of High-level width of an own clock pulse and sets the
internal SCL output to the Low-level.
Master A finishes counting Low-level width of an own clock pulse at point “b” and
sets the internal SCL output to the High-level. Since Master B holds the SCL line
of the bus at the Low-level, Master A wait for counting high-level width of an own
clock pulse. After Master B finishes counting low-level width of an own clock
pulse at point “c” and Master A detects the SCL line of the bus at the High-level,
and starts counting High-level of an own clock pulse. The clock pulse on the bus is
determined by the master device with the shortest High-level width and the
master device with the longest Low-level width from among those master devices
connected to the bus.

(4)

Slave address and address recognition mode specification
When the TMP92CZ26A is used as a slave device, set the slave address  and
 to the I2CAR. Clear the  to “0” for the address recognition mode.

(5)

Master/Slave selection
Set the SBICR2 to “1” for operating the TMP92CZ26A as a master device.
Clear the SBICR2 to “0” for operation as a slave device. The  is cleared
to “0” by the hardware after a stop condition on the bus is detected or arbitration is
lost.

92CZ26A-352

TMP92CZ26A
(6)

Transmitter/Receiver selection
Set the SBICR2 to “1” for operating the TMP92CZ26A as a transmitter.
Clear the  to “0” for operation as a receiver.
In Slave Mode,
z

Data with an addressing format is transferred

z

A slave address with the same value that an I2CAR

z

A GENERAL CALL is received (all 8-bit data are “0” after a start condition)

The  is set to “1” by the hardware if the direction bit ( R/ W ) sent from the
master device is “1”, and is cleared to “0” by the hardware if the bit is “0”.
In the Master Mode, after an Acknowledge signal is returned from the slave device,
the  is cleared to “0” by the hardware if a transmitted direction bit is “1”, and is
set to “1” by the hardware if it is “0”. When an Acknowledge signal is not returned, the
current condition is maintained.
The  is cleared to “0” by the hardware after a stop condition on the I2C bus is
detected or arbitration is lost.
(7)

Start/Stop condition generation
When the SBISR is “0”, slave address and direction bit which are set to
SBIDBR are output on a bus after generating a start condition by writing “1” to the
SBICR2 . It is necessary to set transmitted data to the data
buffer register (SBIDBR) and set “1” to  beforehand.

SCL pin

1

2

3

4

5

6

7

8

SDA pin

A6

A5

A4

A3

A2

A1

A0

R/ W

Start condition

Slave address and the direction bit

9

Acknowledge
signal

Figure 3.15.10 Start condition generation and slave address generation
When the  is “1”, a sequence of generating a stop condition is started by
writing “1” to the , and “0” to the . Do not modify the contents
of  until a stop condition is generated on a bus.

SCL pin
SDA pin
Stop condition

Figure 3.15.11 Stop condition generation
The state of the bus can be ascertained by reading the contents of SBISR.
SBISR will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.

92CZ26A-353

TMP92CZ26A

(8)

Interrupt service requests and interrupt cancellation
When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 
is cleared to “0”. During the time that the SBICR2 is “0”, the SCL line is pulled
down to the Low level.
The  is cleared to “0” when a 1-word of data is transmitted or received. Either
writing/reading data to/from SBIDBR sets the  to “1”.
The time from the  being set to “1” until the SCL line is released takes tLOW.
In the address recognition mode ( = “0”),  is cleared to “0” when the
received slave address is the same as the value set at the I2CAR or when a GENERAL
CALL is received (all 8-bit data are “0” after a start condition). Although
SBICR2 can be set to “1” by the program, the  is not clear it to “0” when it
is written “0”.

(9)

Serial bus interface operation mode selection
SBICR2 is used to specify the serial bus interface operation mode. Set
SBICR2< SBIM1:0> to “10” when the device is to be used in I2C Bus Mode after
confirming pin condition of serial bus interface to “H”.
Switch a mode to port after confirming a bus is free.

(10)

Arbitration lost detection monitor
Since more than one master device can exist simultaneously on the bus in I2C Bus
Mode, a bus arbitration procedure has been implemented in order to guarantee the
integrity of transferred data.
In case set start condition bit with bus is busy, start condition is not output on SCL
and SDA pin, but arbitration lost is generated.
Data on the SDA line is used for I2C bus arbitration.
The following shows an example of a bus arbitration procedure when two master
devices exist simultaneously on the bus. Master A and Master B output the same data
until point “a”. After Master A outputs “L” and Master B, “H”, the SDA line of the bus
is wire-AND and the SDA line is pulled down to the Low-level by Master A. When the
SCL line of the bus is pulled up at point b, the slave device reads the data on the SDA
line, that is, data in Master A. A data transmitted from Master B becomes invalid. The
state in Master B is called “ARBITRATION LOST”. Master B device which loses
arbitration releases the internal SDA output in order not to affect data transmitted
from other masters with arbitration. When more than one master sends the same data
at the first word, arbitration occurs continuously after the second word.
Figure 3.15.12 Arbitration lost

SCL pin
Internal SDA output
(Master A)
Internal SDA output
(Master B)

Internal SDA output becomes 1 after arbitration has been lost.

SDA pin
a

b

The TMP92CZ26A compares the levels on the bus’s SDA line with those of the internal
SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is

92CZ26A-354

TMP92CZ26A
lost and SBISR is set to “1”.
When SBISR is set to “1”, SBISR are cleared to “00” and the mode is
switched to Slave Receiver Mode. Thus, clock output is stopped in data transfer after
setting =“1”.
SBISR is cleared to “0” when data is written to or read from SBIDBR or when
data is written to SBICR2.

Master
A

1

Internal
SCL output
Internal
SDA output

D7A

2

3

4

5

6

7

8

D6A

D5A

D4A

D3A

D2A

D1A

D0A

9

1

2

3

4

D7A’ D6A’ D5A’ D4A’

Stop the clock pulse
Master
B

Internal
SCL output

1

2

Internal
SDA output

D7B

D6B

3

4

Keep Internal SDA output to high-level as losing arbitration






Accessed to
SBIDBR or SBICR2

Figure 3.15.13 Example of when TMP92CZ26A is a master device B
(D7A = D7B, D6A = D6B)
(11)

Slave address match detection monitor
SBISR is set to “1” in Slave Mode, in Address Recognition Mode (i.e. when
I2CAR = “0”), when a GENERAL CALL is received, or when a slave address
matches the value set in I2CAR. When I2CAR = “1”, SBISR is set to “1”
after the first word of data has been received. SBISR is cleared to “0” when
data is written to or read from the data buffer register SBIDBR.

(12)

GENERAL CALL detection monitor
SBISR is set to “1” in Slave Mode, when a GENERAL CALL is received (all
8-bit received data is “0”, after a start condition). SBISR is cleared to “0” when
a start condition or stop condition is detected on the bus.

(13)

Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the
SBISR. In the acknowledge mode, immediately after an INTSBI interrupt
request is generated, an acknowledge signal is read by reading the contents of the
SBISR.

92CZ26A-355

TMP92CZ26A
(14)

Software Reset function
The software Reset function is used to initialize the SBI circuit, when SBI is rocked
by external noises, etc.
An internal Reset signal pulse can be generated by setting SBICR2 to
“10” and “01”. This initializes the SBI circuit internally. All command registers and
status registers are initialized as well.
SBICR1is automatically set to “1” after the SBI circuit has been
initialized.
Note: If the software reset is executied , operation selection is reset, and its mode is set to port mode from I2C
mode.

(15)

Serial Bus Interface Data Buffer Register (SBIDBR)
The received data can be read and transferred data can be written by reading or
writing the SBIDBR.
In the master mode, after the start condition is generated the slave address and the
direction bit are set in this register.

(16)

I2CBUS Address Register (I2CAR)
I2CAR is used to set the slave address when the TMP92CZ26A functions as
a slave device.
The slave address output from the master device is recognized by setting the
I2CAR to “0”. The data format is the addressing format. When the slave
address is not recognized at the  = “1”, the data format is the free data format.

(17)

Setting register for IDLE2 mode operation (SBIBR0)
SBIBR0 is the register setting operation/stop during IDLE2-mode.
Therefore, setting  is necessary before the HALT instruction is executed.

92CZ26A-356

TMP92CZ26A
3.15.6 Data Transfer in I2C Bus Mode
(1) Device initialization
Set the SBICR1, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the
SBICR1 to “0”.
Set a slave address  and the  ( = “0” when an addressing format)
to the I2CAR.
For specifying the default setting to a slave receiver mode, clear “0” to the  and set “1” to the , “10” to the .
7 6 5 4 3 2 1 0
SBICR1
I2CAR

← 0 0 0 X 0 X X X
← X X X X X X X X

← 0 0 0 1 1 0 0 0
Note: X: Don’t care
SBICR2

Set acknowledge and SCL clock.
Set slave address and address recognition mode.
Set to slave receiver mode.

(2) Start condition and slave address generation
a. Master Mode
In the Master Mode, the start condition and the slave address are generated as
follows.
Check a bus free status (when  = “0”).
Set the SBICR1 to “1” (Acknowledge Mode) and specify a slave address
and a direction bit to be transmitted to the SBIDBR.
When SBICR2 = “0”, the start condition are generated by writing “1111” to
SBICR2. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address and
the direction bit which are set to the SBIDBR. At the 9th clock, the SDA line is
released and the acknowledge signal is received from the slave device.
An INTSBI interrupt request occurs at the falling edge of the 9th clock. The
 is cleared to “0”. In the Master Mode, the SCL pin is pulled down to the
Low-level while  is “0”. When an interrupt request occurs, the  is
changed according to the direction bit only when an acknowledge signal is
returned from the slave device.

Setting in main routine
7 6 5 4 3 2 1 0
Reg.

← SBISR
← Reg. e 0x20

if Reg.

≠ 0x00

Reg.

Wait until bus is free.

Then
← X X X 1 X X X X
SBIDBR1 ← X X X X X X X X
SBICR2 ← 1 1 1 1 1 0 0 0
SBICR1

Set to acknowledgement mode.
Set slave address and direction bit.
Generate start condition.

In INTSBI interrupt routine
INTCLR ← 0X2a

Clear the interrupt request

Process
End of interrupt

92CZ26A-357

TMP92CZ26A

b. Slave Mode
z

In the Slave Mode, the start condition and the slave address are received.
After the start condition is received from the master device, while eight clocks are
output from the SCL pin, the slave address and the direction bit that are output
from the master device are received.
When a GENERAL CALL or the same address as the slave address set in I2CAR
is received, the SDA line is pulled down to the Low-level at the 9th clock, and the
acknowledge signal is output.
An INTSBI interrupt request occurs on the falling edge of the 9th clock. The
 is cleared to “0”. In Slave Mode the SCL line is pulled down to the
Low-level while the  = “0”.

SCL pin

1

2

3

4

5

6

7

8

SDA pin

A6

A5

A4

A3

A2

A1

A0

R/ W

Start condition

Slave address + Direction bit


INTSBI
interrupt request
Output of master
Output of slave

Figure 3.15.14 Start condition generation and slave address transfer

92CZ26A-358

9
ACK
Acknowledge
signal from a
slave device

TMP92CZ26A

(3) 1-word Data Transfer
Check the  by the INTSBI interrupt process after the 1-word data transfer is
completed, and determine whether the mode is a master or slave.
a. If  = “1” (Master Mode)
Check the  and determine whether the mode is a transmitter or
receiver.
When the  = “1” (Transmitter mode)
Check the . When  is “1”, a receiver does not request data.
Implement the process to generate a stop condition (Refer to 3.15.6 (4)) and
terminate data transfer.
When the  is “0”, the receiver is requests new data. When the next
transmitted data is 8 bits, write the transmitted data to SBIDBR. When the next
transmitted data is other than 8 bits, set the   and write the
transmitted data to SBIDBR. After written the data,  becomes “1”, a serial
clock pulse is generated for transferring a new 1-word of data from the SCL pin,
and then the 1-word data is transmitted. After the data is transmitted, an
INTSBI interrupt request occurs. The  becomes “0” and the SCL line is
pulled down to the Low-level. If the data to be transferred is more than one word
in length, repeat the procedure from the  checking above.
INTSBI interrupt
if MST = 0
Then shift to the process when slave mode
if TRX = 0
Then shift to the process when receiver mode.
if LRB = 0
Then shift to the process that generates stop condition.
7 6 5 4 3 2 1 0
SBICR1
SBIDBR

← X X X X X X X X
← X X X X X X X X

Set the bit number of transmit and ACK.
Write the transmit data.

End of interrupt
Note: X: Don’t care

SCL

1

2

3

4

5

6

7

8

D5

D4

D3

D2

D1

D0

9

Write to SBIDBR
SDA

D7

D6

ACK
Acknowledge
signal from a
receiver


INTSBI
interrupt request
Output from master
Output from slave

Figure 3.15.15 Example in which  = “000” and  = “1” in transmitter mode

92CZ26A-359

TMP92CZ26A
When the  is “0” (Receiver mode)
When the next transmitted data is other than 8 bits, set   and
read the received data from SBIDBR to release the SCL line (data which is read
immediately after a slave address is sent is undefined). After the data is read,
 becomes “1”.
Serial clock pulse for transferring new 1 word of data is defined SCL and
outputs “L” level from SDA pin with acknowledge timing.
An INTSBI interrupt request then occurs and the  becomes “0”, Then the
TMP92CZ26A pulls down the SCL pin to the Low-level. The TMP92CZ26A
outputs a clock pulse for 1-word of data transfer and the acknowledge signal each
time that received data is read from the SBIDBR.
Read SBIDBR
SCL pin

1

2

3

4

5

6

7

8

SDA pin

D7

D6

D5

D4

D3

D2

D1

D0

9

ACK

New D7
Acknowledge signal
to a transmitter



INTSBI
interrupt request

Output from Master
Output from Slave

Figure 3.15.16 Example of when  = “000”,  = “1” in receiver mode
In order to terminate the transmission of data to a transmitter, clear  to
“0” before reading data which is 1-word before the last data to be received. The
last data word does not generate a clock pulse as the Acknowledge signal. After
the data has been transmitted and an interrupt request has been generated, set
 to “001” and read the data. The TMP92CZ26A generates a clock pulse
for a 1-bit data transfer. Since the master device is a receiver, the SDA line on the
bus remains High. The transmitter interprets the High signal as an ACK signal.
The receiver indicates to the transmitter that data transfer is complete.
After the one data bit has been received and an interrupt request been generated,
the TMP92CZ26A generates a stop condition (see Section 3.15.6 (4) Stop
condition generation) and terminates data transfer.

SCL pin

1

2

3

4

5

6

7

8

SDA pin

D7

D6

D5

D4

D3

D2

D1

D0

1

Acknowledge signal
sent to a transmitter



INTSBI
interrupt request

“0” → 
Read SBIDBR

“001” → 
Read SBIDBR
Output of Master
Output of Slave

Figure 3.15.17 Termination of data transfer in master receiver mode

92CZ26A-360

TMP92CZ26A
Example: In case receive data N times
INTSBI interrupt (After transmitting data)
7 6 5 4 3 2 1 0
SBICR1
Reg.

← X X X X X X X X
← SBIDBR

Set the bit number of receive data and ACK.
Load the dummy data.

End of interrupt

INTSBI interrupt (Receive data of 1st to (N−2) th)
7 6 5 4 3 2 1 0
← SBIDBR
End of interrupt

Load the data of 1st to (N−2)th.

Reg.

INTSBI interrupt ((N−1) th Receive data)
7 6 5 4 3 2 1 0
SBICR1
Reg.

← X X X 0 0 X X X
← SBIDBR

Not generate acknowledge signal
Load the data of (N−1)th

End of interrupt

INTSBI interrupt (Nth Receive data)
7 6 5 4 3 2 1 0
SBICR1
Reg.

← 0 0 1 0 0 X X X
← SBIDBR

Generate the clock for 1bit transmit
Receive the data of Nth.

End of interrupt

INTSBI interrupt (After receiving data)
The process of generating stop condition

Finish the transmit of data

End of interrupt

Note: X: Don’t care

92CZ26A-361

TMP92CZ26A
b. If  = 0 (Slave Mode)
In the slave mode the TMP92CZ26A operates either in normal slave mode or in
slave mode after losing arbitration.
In the slave mode, an INTSBI interrupt request occurs when the TMP92CZ26A
receives a slave address or a GENERAL CALL from the master device, or when a
GENERAL CALL is received and data transfer is complete, or after matching
received address. In the master mode, the TMP92CZ26A operates in a slave mode
if it losing arbitration. An INTSBI interrupt request occurs when a word data
transfer terminates after losing arbitration. When an INTSBI interrupt request
occurs the  is cleared to “0” and the SCL pin is pulled down to the Low-level.
Either reading/writing from/to the SBIDBR or setting the  to “1” will
release the SCL pin after taking tLOW time.
Check the SBISR, , , and  and implements processes
according to conditions listed in the next table.

Example: In case matching slave address in slave receive mode, direction bit is “1”.
INTSBI interrupt
if TRX = 0
Then shift to other process
if AL = 1
Then shift to other process
if AAS = 0
Then shift to other process
7 6 5 4 3 2 1 0
SBICR1
SBIDBR

← X X X 1 X X X X
← X X X X X X X X

Set the bit number of transmit.
Set the data of transmit.

Note: X: Don’t care

92CZ26A-362

TMP92CZ26A

Table 3.15.2 Operation in the slave mode




1

 

1

0

Conditions

Process

The TMP92CZ26A loses arbitration

Set the number of bits a word in

when transmitting a slave address and

 and write the transmitted data

receives a slave address for which the

to SBIDBR

value of the direction bit sent from
another master is “1”.
In Salve Receiver Mode, the
1

0

TMP92CZ26A receives a slave address
for which the value of the direction bit
sent from the master is “1”.

1

Check the  setting. If  is
set to “1”, set  to “1” since the
0

receiver win no request the data which
0

0

In Salve Transmitter Mode, a single
word of is transmitted.

follows. Then, clear  to “0” to
release the bus. If  is cleared to
“0”, set  to the number of bits in
a word and write the transmitted data to
SBIDBR since the receiver requests
next data.

The TMP92CZ26A loses arbitration
when transmitting a slave address and
1

1/0

receives a slave address or GENERAL
CALL for which the value of the direction

1

bit sent from another master is “0”.
0

0

0

The TMP92CZ26A loses arbitration

Read the SBIDBR for setting the 

when transmitting a slave address or

to “1” (reading dummy data) or set the

data and terminates word data transfer.

 to “1”.

In Slave Receiver Mode, the
TMP92CZ26A receives a slave address
1

1/0

or GENERAL CALL for which the value
of the direction bit sent from the master

0

is “0”.
0

1/0

In Slave Receiver Mode, the

Set  to the number of bits in a

TMP92CZ26A terminates receiving

word and read the received data from

word data.

SBIDBR.

92CZ26A-363

TMP92CZ26A

(4) Stop condition generation
When SBISR = “1”, the sequence for generating a stop condition start by
writing “1” to SBICR2 and “0” to SBICR2. Do not modify the
contents of SBICR2 until a stop condition has been generated
on the bus. When the bus’s SCL line has been pulled Low by another device, the
TMP92CZ26A generates a stop condition when the other device has released the SCL
line and SDA pin rising.

7 6 5 4 3 2 1 0
SBICR2

← 1 1 0 1 1 0 0 0

Generate stop condition.

“1” → 
“1” → 
“0” → 
“1” → 

Stop condition

Internal SCL

SCL pin

SDA Pin


 (Read)

Figure 3.15.18 Stop condition generation (Single master)

“1” → 
“1” → 
“0” → 
“1” → 

Stop condition

Internal SCL
The case of pulled low
by another device

SCL Pin

SDA Pin



 (Read)

Figure 3.15.19 Stop condition generation (Multi master)

92CZ26A-364

TMP92CZ26A
(5) Restart
Restart is used during data transfer between a master device and a slave device to
change the data transfer direction.
The following description explains how to restart when the TMP92CZ26A is in
Master Mode.
Clear SBICR2 to 0 and set SBICR2 to 1 to release the
bus. The SDA line remains High and the SCL pin is released. Since a stop condition
has not been generated on the bus, other devices assume the bus to be in busy state.
And confirm SCL pin, that SCL pin is released and become bus-free state by
SBISR = “0” or signal level “1” of SCL pin in port mode. Check the  until it
becomes 1 to check that the SCL line on a bus is not pulled down to the low-level by
other devices. After confirming that the bus remains in a free state, generate a start
condition using the procedure described in (2).
In order to satisfy the set-up time requirements when restarting, take at least 4.7 μs of
waiting time by software from the time of restarting to confirm that the bus is free
until the time to generate the start condition.

7 6 5 4 3 2 1 0
← 0 0 0 1 1 0 0 0
if SBISR ≠ 0
SBICR2

Release the bus
Check if SCL pin is released.

Then
if SBISR ≠ 1

Check if SCL pin of other device is “L” level.

Then
4.7 μs Wait
SBIDBR

← X X X 1 X X X X
← X X X X X X X X

Set the slave address and direction bit.

SBICR2

← 1 1 1 1 1 0 0 0

Generate start condition.

SBICR1

Set acknowledgement mode.

Note: X: Don’t care

“0” → 
“0” → 
“0” → 
“1” → 

“1” → 
“1” → 
“1” → 
“1” → 
4.7 μs (Min)

SCL line
Internal SCL
output

9

SDA line




Figure 3.15.20 Timing chart for generate restart
Note: Don’t write  = “0”, when  = “0” condition. (Cannot be restarted)

92CZ26A-365

Start condition

TMP92CZ26A

3.16 USB Controller
3.16.1

Outline
This USB controller (UDC) is designed for various serial links to construct USB system.
The outline is as follows:
(1) Compliant with USB rev1.1
(2) Full-speed: 12 Mbps (Not supported low-speed (1.5 Mbps))
(3) Auto bus enumeration with 384-byte descriptor RAM
(4) Supported 3 kinds of transfer type: Control, interrupt and bulk
Endpoint 0:

Control

64 bytes × 1-FIFO

Endpoint 1:

BULK (out)

64 bytes × 2-FIFO

Endpoint 2:

BULK (in)

64 bytes × 2-FIFO

Endpoint 3:

Interrupt (in)

8 bytes × 1-FIFO

(5) Built-in DPLL which generates sampling clock for receive data
(6) Detecting and generating SOP, EOP, RESUME, RESET and TIMEOUT
(7) Encoding and decoding NRZI data
(8) Inserting and discarding stuffed bit
(9) Detecting and checking CRC
(10) Generating and decoding packet ID
(11) Built-in power management function
(12) Supported dual packet mode
Note1:TMP92CZ26A don’t have special terminal that control pull-up resister for D+pin. So, need to add external
switch and control it.
Note2:There are some difference between our specification and USB 1.1. Refer and check “3.16.11 Notice and
restrictions at first”.

92CZ26A-366

TMP92CZ26A
3.16.1.1 System Configuration
The USB controller (UDC) is consisted of following 3 blocks.
1. 900/H1 CPU I/F
2.

UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM
and 4 endpoint FIFO

3.

USB transceiver
About above “1.” is explained at 3.16.2, and “2.” is 3.16.3.

UDC
Descriptor RAM
384 bytes

Request controller

ADDRESS
900/H1 CPU
interface

WR
RD

UDC core
Endpoint 0:
FIFO (64 bytes × 1)
I/F
PWM
Endpoint 1:
FIFO (64 bytes × 2)
FIFO
manager

DPLL
IFM

Endpoint 2:
FIFO (64 bytes × 2)

USB
transceiver

SIE
Endpoint 3:
FIFO (8 bytes × 1)

Figure 3.16.1 UDC Block Diagram

92CZ26A-367

D+
D−

TMP92CZ26A
3.16.1.2 Example
USB host

USB device

USB host

TMP92CZ26A
USB
USB
Connector Connector

VCC

GND
VBUS

INTx (detect rising)
R6

R7

USB
cable

X2
10MHz

PorTXX
X1USB

R1
R2

R8

R9

X1

VSS

R4

OFF at
“H”

R5

R3

48MHz

D+

D−

OFF at
"H"

If using USB controller in TMP92CZ26A, above setting is needed.
1) Pull-up of D+ pin
・ In the USB standard, in Full Speed connection, D+ pin must be set to pull-up.
And this pull-up is needed ON/OFF control by S/W.
Recommendation value: R1=1.5kΩ
2) Add cascade resistor of D+, D-signal
・ In the USB standard, in D+, D- signal, cascade resistor must be added to each
signal. Recommendation value : R2=27Ω, R3=27Ω
3) Flow current provision of the Connector connection and D+ pin, D- pin
・ In D+, D- pin of TMP92CZ26A, level must be fixed for flow current provision
when not using (it is not connect to host). In this case, it is showed that method of
controlling the pull-down resistor for fixed level by using detection signal of
connector connection.
Recommendation value: R4=10kΩ, R5=10kΩ
・ It is showed as example of the connector connection detection that method of
detecting by using VBUS (5V voltage).
Note: If rising of waveform is solw, recommned that likely baffering for waveform.

Recommendation value: R6=60kΩ, R7=100kΩ
(VBUS reducing current when suspend<500μA)
4) Connect oscillator of 10MHz to X1,X2, or input 48MHz clock to X1USB
・ If using USB by using the combination external 10MHz oscillator and internal,
Stage of external hub which can be used is restricted by the precision of internal
(Max 3 stages).
・ If 5 stages connection is needed for external hub, it is needed that input 48MHz
clock from X1USB pin (Restriction ≤±2500ppm.)
5) HOST side pull-down resistor
・ In the USB regulation, set pull-down D+ pin and D- signal at USB_HOST side.
Recommendation value: R8=15kΩ, R9=15kΩ
Note: Above connection and resistor etc, is example. Operation is not guranteed. Please confirm the
newest USB standar and the operation on your setting.

92CZ26A-368

TMP92CZ26A
3.16.2

900/H1 CPU I/F
The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works
following operations.
•

INTUSB (interrupt from UDC) generation

•

A bridge for SFR

•

USB clock control (48 MHz)

3.16.2.1 SFRs
The 900/H1 CPU I/F have following SFRs to control UDC and USB transceiver.
• USB control
USBCR1

(USB control register 1)

• USB interrupt control
USBINTFR1

(USB interrupt flag register 1)

USBINTFR2

(USB interrupt flag register 2)

USBINTFR3

(USB interrupt flag register 3)

USBINTFR4

(USB interrupt flag register 4)

USBINTMR1

(USB interrupt mask register 1)

USBINTMR2

(USB interrupt mask register 2)

USBINTMR3

(USB interrupt mask register 3)

USBINTMR4

(USB interrupt mask register 4)

Figure 3.16.2 900/H1 CPU I/F SFR
Address

Read/Write

SFR Symbol

07F0H

R/W

USBINTFR1

07F1H

R/W

USBINTFR2

07F2H

R/W

USBINTFR3

07F3H

R/W

USBINTFR4

07F4H

R/W

USBINTMR1

07F5H

R/W

USBINTMR2

07F6H

R/W

USBINTMR3

07F7H

R/W

USBINTMR4

07F8H

R/W

USBCR1

92CZ26A-369

TMP92CZ26A
3.16.2.2 USBCR1 Register
This register is used to set USB clock enables, transceiver enable etc.

USBCR1
(07F8H)

7

6

1

0

bit Symbol

TRNS_USE

WAKEUP

5

4

3

2

SPEED

USBCLKE

Read/Write

R/W

R/W

R/W

R/W

After reset

0

0

1

0

Function

•

TRNS_USE

(Bit7)

0: Disable USB transceiver
1: Enable USB transceiver

Set to “1” for TMP92CZ26A.
•

WAKEUP

(Bit6)

0: −
1: Start remote-wakeup-function

When the remote-wakeup-function is needed, at first check the
Current_Config.
If the  = “1” (means SUSPEND-status), write “1”,
and “0” to  after checking by this, remote-wakeup-function will be
started.
If the  = “0” or EP0, 1, 2, 3_STATUS =
“0”, don’t write “1” to .
•

SPEED

(Bit1)

1: Full speed (12 MHz)
0: Reserved

This bit selects USB speed.
Set to “1” for TMP92CZ26A.
•

USBCLKE

(Bit0)

0: Disable USB clock
1: Enable USB clock

This bit controls to supply USB clock.
The USB clock (named “fUSB”: 48MHz) is generated by an internal PLL.
When the USB is started to use, write “1” to  after confirmed the
lock up of PLL is terminated.
And when the PLL is stopped, stop PLL after writing “0” to .

92CZ26A-370

TMP92CZ26A
3.16.2.3 USBINTFRn, MRn Register
These SFRs control to generate INTUSB (only one interrupt to CPU) because the
UDC outputs 23 interrupt source.
The USBINTMRn are mask registers and the USBINTFRn are flag registers. In
the INTUSB routine, execute operations according to generated interrupt source after
checking USBINTFRn.
The below is the common specification for all MASK and FLAG registers.

(Common

spec for all mask and flag registers.)

Mask register
Interrupt source
(Set by rising edge)
Flag register
Writing “0” to flag register
A

B

C

D

A: The flag register is not set because mask register = “1”.
B: The flag register is not set because interrupt souce changes “1” → “0”.
C: The flag register is set because mask register = “0” and interrupt souce changes “0” → “1”.
D: The flag register is reset to “0” by writing “0” to flag register.

Note 1: Both “INTUSB generated number” and “bit number which is set to flag register” are not always equal. In the
INTUSB interrupt routine, clear FLAG register (USBINTFRn) after checking it. The interrupt request flag, which
is occurred between jump to the INTUSB interrupt routine and read flag register (USBINTFRn), is kept in
interrupt controller.
Therefore, after returning from the interrupt routine, CPU jumps to INTUSB interrupt routine again. And
when read the flag register (USBINTFRn), none of the bits are set to “1”. For this case, special software is
needed in order not to finish as error routine.
Note 2: When USBINTMRn or USBINTFRn is written, disable INTUSB (write 00H to INTEUSB register) before it.

92CZ26A-371

TMP92CZ26A

7

6

5

4

3

2

USBINTFR1
(07F0H)

bit Symbol

INT_URST_STR

INT_URST_END

INT_SUS

INT_RESUME

INT_CLKSTOP

INT_CLKON

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

Prohibit
to read
modify
write

After reset

0

0

0

0

0

0

Function

When read 0: Not generate interrupt

When write

1

0

0: Clear flag
1: −

1: Generate interrupt

Note: Above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode can not be released)
*Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, the system of low power
dissipation can be built. However, the way of use is limited as below.
Shift to IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
Release from IDLE1 mode :
Release Halt state by the request of INT_RESUME or INT_CLKON ( request of release SUSPEND )
Release Halt state by the request of INT_URST_STR or INT_URST_END ( request of RESET )

•

INT_URST_STR (Bit7)
This is a flag for INT_URST_STR (“USB reset” start - interrupt).
This is set to “1” when the UDC started to receive “USB reset” signal from
USB-host.
An application program has to initialize whole UDC by this interrupt.

•

INT_URST_END (Bit6)
This is a flag for INT_URST_END (“USB reset” end - interrupt).
This is set to “1” when the UDC receive “USB reset end” signal from
USB-host.

•

INT_SUS (Bit5)
This is a flag for INT_SUS (suspend - interrupt).
This is set to “1” when USB change to “suspend status”.

•

INT_RESUME (Bit4)
This is a flag for INT_RESUME (resume - interrupt).
This is set to “1” when USB change to “resume status”.

•

INT_CLKSTOP (Bit3)
This is a flag for INT_CLKSTOP (enable stopping clock supply - interrupt).
This is set to “1” when USB enable stopping clock supply after changing to
“suspend status”.

•

INT_CLKON (Bit2)
This is a flag for INT_CLKON (enabled starting clock supply - interrupt).
This is set to “1” when USB enable starting clock supply after change to
“resume status”.

92CZ26A-372

TMP92CZ26A

USBINTFR2
(07F1H)
Prohibit
to read
modify
write

7

6

5

4

3

2

1

0

bit Symbol

EP1_FULL_A

EP1_Empty_A

EP1_FULL_B

EP1_Empty_B

EP2_FULL_A

EP2_Empty_A

EP2_FULL_B

EP2_Empty_B

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Function

When read 0: Not generate interrupt

When write 0: Clear flag
1: −

1: Generate interrupt

Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)

USBINTFR3 bit Symbol
(07F2H)
Read/Write
Prohibit
to read
modify
write

After reset
Function

7

6

5

4

EP3_FULL_A

EP3_Empty_A

EP3_FULL_B

EP3_Empty_B

R/W

R/W

R/W

R/W

0

0

0

0

When read

0: Not generate interrupt

When write

0: Clear flag

3

2

1

0

1: Generate interrupt

1: −
Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)

•

EPx_FULL_A/B:
(When transmitting)
This is set to “1” when CPU full write data to FIFO_A/B.
(When receiving)
This is set to “1” when UDC full receive data to FIFO_A/B.

•

EPx_Empty_A/B:
(When transmitting)
This is set to “1” when FIFO become empty after transmission.
(When receiving)
This is set to “1” when FIFO become empty after CPU read all data from FIFO.

Note: The flag of EPx_FULL_A/B and EPx_Empty_A/B are not status flag. Therefore, check DATASET
register if the FIFO-status is needed.

92CZ26A-373

TMP92CZ26A

7

6

5

4

3

2

1

USBINTFR4
(07F3H)

bit Symbol

INT_SETUP

INT_EP0

INT_STAS

INT_STASN

INT_EP1N

INT_EP2N

INT_EP3N

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Prohibit
to read
modify
write

After reset

0

0

0

0

0

0

0

Function

When read

0: Not generate interrupt

0

When write 0: Clear flag

1: Generate interrupt

1: −

Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)

•

INT_SETUP (Bit7)
This is a flag for INT_SETUP (setup - interrupt).
This is set to “1” when the UDC receive request that S/W (software) control
is needed from USB host.
By S/W (INT_SETUP routine), at first, read device request of 8-bytes from
UDC and execute operation according to each request.

•

INT_EP0 (Bit6)
This is a flag for INT_EP0 (received data of the data phase for Control
transfer type - interrupt).
This is set to “1” when the UDC receive data of the data phase for Control
transfer type. At the Control write transfer, data reading from FIFO is needed
if this interrupt occur. At the Control read transfer, transmission data writing
to FIFO is needed if this interrupts occurred.
By host may don’t assert “ACK” of last packet in the data stage. In that case,
this interrupt cannot be generated. So, ignore this interrupt of after last
packet data was written in the data stage because the transmission data
number is specified by the host, or it depends on the capacity of the device.

•

INT_STAS (Bit5)
This is a flag for INT_STAS (status stage end - interrupt).
This is set to “1” when the status stage end.
If this interrupt is generated, it means that request ended normally.
If this interrupt is not generated and INT_SETUP is generated,
EP0_STATUS  is set to “1” and it means that request didn’t
end normally.

92CZ26A-374

TMP92CZ26A

•

INT_STASN (Bit4)
This is a flag for INT_STASN (change host status stage - interrupt).
This is set to “1” when the USB host change to status stage at the Control
read transfer type. This interrupt is needed if data length is less than
wLength (specified by the host).
But if the USB host change to status stage, this interrupt is always
generated because of this signal is designed by using NAK of first packet. So,
to avoid that this interrupt always generate, use mask register USBINTMRn.
Disable this interrupt before data of last payload is written.

•

INT_EPxN (Bit3, 2, 1)
This is a flag for INT_EPxN (NAK acknowledge to the USB host interrupt).
This is set to “1” when the Endpoint1, 2 and 3 transmit NAK.

92CZ26A-375

TMP92CZ26A

USBINTMR1 bit Symbol
(07F4H)
Read/Write
After reset

7

6

5

4

3

2

MSK_URST_STR

MSK_URST_END

MSK_SUS

MSK_RESUME

MSK_CLKSTOP

MSK_CLKON

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

Function

0: Be not masked 1: Be masked

•

MSK_URST_STR (Bit7)
This is a mask register for USBINTFR1.

•

MSK_URST_END (Bit6)
This is a mask register for USBINTFR1.

•

MSK_SUS (Bit5)
This is a mask register for USBINTFR1.

•

MSK_RESUME (Bit4)
This is a mask register for USBINTFR1.

•

MSK_CLKSTOP (Bit3)
This is a mask register for USBINTFR1.

•

MSK_CLKON (Bit2)
This is a mask register for USBINTFR1.

92CZ26A-376

1

0

TMP92CZ26A

USBINTMR2
(07F5H)

7

6

5

4

3

2

1

0

bit Symbol

EP1_MSK_FA

EP1_MSK_EA

EP1_MSK_FB

EP1_MSK_EB

EP2_MSK_FA

EP2_MSK_EA

EP2_MSK_FB

EP2_MSK_EB

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

1

1

1

1

1

1

1

1

Function

0: Be not masked 1: Be masked

•

EP1/2_MSK_FA/FB/EA/EB
This is a mask register for USBINTFR2 or
.

USBINTMR3 bit Symbol
(07F6H)
Read/Write
After reset
Function

7

6

EP3_MSK_FA

EP3_MSK_EA

R/W

R/W

1

1

5

4

3

2

1

0: Be not masked
1: Be masked

•

EP3_MSK_FA/FB/EA/EB:
This is a mask register for USBINTFR3 or
.

92CZ26A-377

0

TMP92CZ26A

USBINTMR4 bit Symbol
(07F7H)
Read/Write
After reset

7

6

5

4

3

2

1

MSK_SETUP

MSK_EP0

MSK_STAS

MSK_STASN

MSK_EP1N

MSK_EP2N

MSK_EP3N

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

1

Function

0: Be not masked
1: Be masked

•

MSK_SETUP (Bit7)
This is a mask register for USBINTFR4.

•

MSK_EP0 (Bit6)
This is a mask register for USBINTFR4.

•

MSK_STAS (Bit5)
This is a mask register for USBINTFR4.

•

MSK_STASN (Bit4)
This is a mask register for USBINTFR4.

•

MSK_EP1N (Bit3)
This is a mask register for USBINTFR4.

•

MSK_EP2N (Bit2)
This is a mask register for USBINTFR4.

•

MSK_EP3N (Bit1)
This is a mask register for USBINTFR4.

92CZ26A-378

0

TMP92CZ26A
3.16.3

UDC CORE

3.16.3.1 SFRs
The UDC CORE has following SFRs to control UDC and USB transceiver.
a)

FIFO
Endpoint 0 to 3 FIFO register

b)

c)

d)

e)

f)

Device request
bmRequestType

register

bRequest

register

wValue_L

register

wValue_H

register

wIndex_L

register

wIndex_H

register

wLength_L

register

wLength_H

register

Status
Current_Config

register

USB_STATE

register

StandardRequest

register

Request

register

EPx_STATUS

register

Setup
EPx_BCS

register

EPx_SINGLE

register

Standard Request Mode

register

Request Mode

register

Descriptor RAM

register

PortStatus

register

register

Control
EPx_MODE

register

EOP

COMMAND

register

INT_ Control

register

Setup Received

register

USBREADY

register

ADDRESS

register

DATASET

register

EPx_SIZE_L_A

register

EPx_SIZE_H_A

register

EPx_SIZE_L_B

register

EPx_SIZE_H_B

register

FRAME_L

register

FRAME_H

register

USBBUFF TEST

register

Others

92CZ26A-379

TMP92CZ26A
Figure 3.16.3 UDC CORE SFRs (1/3)
Address

Read/Write

SFR Symbol

0500H

R/W

Descriptor RAM0

0501H

R/W

Descriptor RAM1

0502H

R/W

Descriptor RAM2

0503H

R/W

Descriptor RAM3

067DH

R/W

Descriptor RAM381

067EH

R/W

Descriptor RAM382

067FH

R/W

Descriptor RAM383

0780H

R/W

ENDPOINT0

0781H

R/W

ENDPOINT1

0782H

R/W

ENDPOINT2

0783H

R/W

ENDPOINT3

*0784H

R/W

ENDPOINT4

*0785H

R/W

ENDPOINT5

*0786H

R/W

ENDPOINT6

*0787H

R/W

ENDPOINT7

*0788H

–

0789H

R/W

EP1_MODE

078AH

R/W

EP2_MODE

Reserved

078BH

R/W

EP3_MODE

*078CH

R/W

EP4_MODE

*078DH

R/W

EP5_MODE

*078EH

R/W

EP6_MODE

*078FH

R/W

0790H

R

EP0_STATUS

0791H

R

EP1_STATUS

0792H

R

EP2_STATUS

EP7_MODE

0793H

R

EP3_STATUS

*0794H

R

EP4_STATUS

*0795H

R

EP5_STATUS

*0796H

R

EP6_STATUS

*0797H

R

EP7_STATUS

0798H

R

EP0_SIZE_L_A

0799H

R

EP1_SIZE_L_A

079AH

R

EP2_SIZE_L_A

079BH

R

EP3_SIZE_L_A

*079CH

R

EP4_SIZE_L_A

*079DH

R

EP5_SIZE_L_A

*079EH

R

EP6_SIZE_L_A

*079FH

R

EP7_SIZE_L_A

07A1H

R

EP1_SIZE_L_B

07A2H

R

EP2_SIZE_L_B

07A3H

R

EP3_SIZE_L_B

*07A4H

R

EP4_SIZE_L_B

*07A5H

R

EP5_SIZE_L_B

*07A6H

R

EP6_SIZE_L_B

*07A7H

R

EP7_SIZE_L_B

–

Reserved

*07A8H

Note: “*” is not used at TMP92CZ26A.

92CZ26A-380

TMP92CZ26A

Figure 3.16.4 UDC CORE SFRs (2/3)
Address

Read/Write

SFR Symbol

07A9H

R

EP1_SIZE_H_A

07AAH

R

EP2_SIZE_H_A

07ABH

R

EP3_SIZE_H_A

*07ACH

R

EP4_SIZE_H_A

*07ADH

R

EP5_SIZE_H_A

*07AEH

R

EP6_SIZE_H_A

*07AFH

R

EP7_SIZE_H_A

07B1H

R

EP1_SIZE_H_B

07B2H

R

EP2_SIZE_H_B

07B3H

R

EP3_SIZE_H_B

*07B4H

R

EP4_SIZE_H_B

*07B5H

R

EP5_SIZE_H_B

*07B6H

R

EP6_SIZE_H_B

*07B7H

R

EP7_SIZE_H_B

07C0H

R

bmRequestType

07C1H

R

bRequest

07C2H

R

wValue_L

07C3H

R

wValue_H

07C4H

R

wIndex_L

07C5H

R

wIndex_H

07C6H

R

wLength_L

07C7H

R

wLength_H

07C8H

W

Setup Received

07C9H

R

Current_Config

07CAH

R

Standard Request

07CBH

R

Request

07CCH

R

DATASET1

07CDH

R

DATASET2

07CEH

R

USB_STATE

07CFH

W

EOP

07D0H

W

COMMAND

07D1H

R/W

EPx_SINGLE1

*07D1H

R/W

EPx_SINGLE2

07D3H

R/W

EPx_BCS1

*07D4H

R/W

EPx_BCS2

*07D5H

R/W

Reserved

07D6H

R/W

INT_Control

*07D7H

R/W

Reserved

07D8H

R/W

Standard Request Mode

07D9H

R/W

Request Mode

*07DAH

R/W

Reserved

*07DBH

R/W

Reserved

*07DCH

R/W

Reserved

*07DDH

R/W

Reserved

07DEH

W

ID_CONTROL

07DFH

R

ID_STATE

Note: “*” is not used at TMP92CZ26A.

92CZ26A-381

TMP92CZ26A

Figure 3.16.5 UDC CORE SFRs (3/3)
Address

Read/Write

07E0H

R/W

SFR Symbol

07E1H

R

FRAME_L

07E2H

R

FRAME_H

07E3H

R

ADDRESS

*07E4H

–

Reserved

*07E5H

–

Reserved

Port_Status

07E6H

R/W

*07E7H

–

Reserved

USBREADY

07E8H

W

Set Descriptor STALL

Note: “*” is not used at TMP92CZ26A.

92CZ26A-382

TMP92CZ26A
3.16.3.2 EPx_FIFO Register (x: 0 to 3)
This register is prepared for each endpoint independently.
This is the window register from or to FIFO RAM.
In the auto bus enumeration, the request controller in UDC set mode, which is
defined at endpoint descriptor for each endpoint automatically. By this, each endpoint
is set to voluntary direction.

Endpoint0
(0780H)

Endpoint1
(0781H)

Endpoint2
(0782H)

Endpoint3
(0783H)

bit Symbol

7

6

5

4

3

2

1

0

EP0_DATA7

EP0_DATA6

EP0_DATA5

EP0_DATA4

EP0_DATA3

EP0_DATA2

EP0_DATA1

EP0_DATA0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

7

6

5

4

3

2

1

0

bit Symbol

EP1_DATA7

EP1_DATA6

EP1_DATA5

EP1_DATA4

EP1_DATA3

EP1_DATA2

EP1_DATA1

EP1_DATA0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

7

6

5

4

3

2

1

0

bit Symbol

EP2_DATA7

EP2_DATA6

EP2_DATA5

EP2_DATA4

EP2_DATA3

EP2_DATA2

EP2_DATA1

EP2_DATA0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

7

6

5

4

3

2

1

0

bit Symbol

EP3_DATA7

EP3_DATA6

EP3_DATA5

EP3_DATA4

EP3_DATA3

EP3_DATA2

EP3_DATA1

EP3_DATA0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Note: Read or write these window registers by using load instruction of 1 byte because of each register have only 1
byte address. Don’t use load instruction of 2 bytes or 4 bytes.

The device request that received from the USB host is stored to following 8-byte
registers.
The 8-byte registers are bmRequestType, bRequest, wValue_L, wValue_H,
wIndex_L, wIndex_H, wLength_L and wLength_H. They are updated whenever new
SETUP token is received from host...
When the UDC receive without error, INT_SETUP interrupt is asserted and it
means the new device request has been received.
And there is a request which is operated automatically by UDC. It depends on
received request.
In that case, the UDC don’t assert INT_SETUP interrupt. A request which the UDC
is operating now can be checked by reading STANDARD_REQUEST_FLAG and
REQUEST_FLAG.

92CZ26A-383

TMP92CZ26A
3.16.3.3 bmRequestType Register
This register shows the bmRequestType field of device request.

bmRequestType
(07C0H)

7

6

5

4

3

2

1

0

bit Symbol

DIRECTION

REQ_TYPE1

REQ_TYPE0

RECIPIENT4

RECIPIENT3

RECIPIENT2

RECIPIENT1

RECIPIENT0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

DIRECTION (Bit7)

0: from host to device
1: from device to host

REQ_TYPE [1:0] (Bit6 to bit5)

00: Standard
01: Class
10: Vendor
11: (Reserved)

RECEIPIENT [4:0] (Bit4 to bit0)

00000: Device
00001: Interface
00010: Endpoint
00011: etc.
Others: (Reserved)

3.16.3.4 bRequest Register
This register shows the bRequest field of device request.

bRequest
(07C1H)

7

6

5

4

3

2

1

0

bit Symbol

REQUEST7

REQUEST6

REQUEST5

REQUEST4

REQUEST3

REQUEST2

REQUEST1

REQUEST0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

(Standard)

(Printer class)

00000000: GET_STATUS

00000000: GET_DEVICE_ID

00000001: CLEAR_FEATURE

00000001: GET_PORT_STATUS

00000010: Reserved

00000010: SOFT_RESET

00000011: SET_FEATURE
00000100: Reserved
00000101: SET_ADDRESS
00000110: GET_DESCRIPTOR
00000111: SET_DESCRIPTOR
00001000: GET_CONFIGURATION
00001001: SET_CONFIGURATION
00001010: GET_INTERFACE
00001011: SET_INTERFACE
00001100: SYNCH_FRAME

92CZ26A-384

TMP92CZ26A
3.16.3.5 wValue Register
There are 2 registers; the wValue_L register and wValue_H register. wValue_L
shows the lower-byte of wValue field of device request and wValue_H register shows
upper byte.

wValue_L
(07C2H)

wValue_H
(07C3H)

7

6

5

4

3

2

1

0

bit Symbol

VALUE_L7

VALUE_L6

VALUE_L5

VALUE_L4

VALUE_L3

VALUE_L2

VALUE_L1

VALUE_L0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

VALUE_H7

VALUE_H6

VALUE_H5

VALUE_H4

VALUE_H3

VALUE_H2

VALUE_H1

VALUE_H0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

3.16.3.6 wIndex Register
There are 2 registers, the wIndex_L register and wIndex_H register. the wIndex_L
register shows the lower byte of wIndex field of device request and wIndex_H register
shows upper byte.
These are usually used to transfer index or offset.

wIndex_L
(07C4H)

wIndex_H
(07C5H)

7

6

5

4

3

2

1

0

bit Symbol

INDEX_L7

INDEX_L6

INDEX_L5

INDEX_L4

INDEX_L3

INDEX_L2

INDEX_L1

INDEX_L0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

INDEX_H7

INDEX_H6

INDEX_H5

INDEX_H4

INDEX_H3

INDEX_H2

INDEX_H1

INDEX_H0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

3.16.3.7 wLength Register
There are 2 registers, the wLength_L register and wLength_H register. the
wLength_L register shows the lower-byte of wLength field of device request and
wLength_H register shows upper byte.
In case of data phase, these registers show byte number to transfer.

wLength_L
(07C6H)

wLength_H
(07C7H)

7

6

5

4

3

2

1

0

bit Symbol

LENGTH_L7

LENGTH_L6

LENGTH_L5

LENGTH_L4

LENGTH_L3

LENGTH_L2

LENGTH_L1

LENGTH_L0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

LENGTH_H7

LENGTH_H6

LENGTH_H5

LENGTH_H4

LENGTH_H3

LENGTH_H2

LENGTH_H1

LENGTH_H0

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

92CZ26A-385

TMP92CZ26A

3.16.3.8 Setup Received Register
This register informs for the UDC that an application program recognized
INT_SETUP interrupt.

SetupReceived
(07C8H)

7

6

5

4

3

2

1

0

bit Symbol

D7

D6

D5

D4

D3

D2

D1

D0

Read/Write

W

W

W

W

W

W

W

W

After reset

0

0

0

0

0

0

0

0

If this register is accessed by an application program, the UDC release to disabling
access to EP0’s FIFO RAM because the UDC recognized the device request is received.
This is to protect data stored in EP0 in the time from continuous request has been
asserted to an application program recognized INT_SETUP interrupt.
Therefore, write “00H” to this register when the device request in INT_SETUP
routine is recognized.
Note : When EP0_FIFO is accessed register after wrote to this register, the recovery time of 2clock at 12MHz is
needed.

3.16.3.9 Current_Config Register
This register shows the present value that is set by SET_CONFIGURATION and
SET_INTERFACE.
7
Current_Config
(07C9H)

5

4

3

2

1

0

bit Symbol

REMOTEWAKEUP

6

ALTERNATE[1]

ALTERNATE[0]

INTERFACE[1]

INTERFACE[0]

CONFIG[1]

CONFIG[0]

Read/Write

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

CONFIG[1:0] (Bit1 to bit0)
00: UNCONFIGURED

Set to UNCONFIGURED by the host.

01: CONFIGURED1

Set to CONFIGURED 1 by the host.

10: CONFIGURED2

Set to CONFIGURED 2 by the host.

INTERFACE[1:0] (Bit3 to bit2)
00: INTERFACE0

Set to INTERFACE 0 by the host.

01: INTERFACE1

Set to INTERFACE 1 by the host.

10: INTERFACE2

Set to INTERFACE 2 by the host.

ALTERNATE[1:0] (Bit5 to bit4)
00: ALTERNATE0

Set to ALTERNATE 0 by the host.

01: ALTERNATE1

Set to ALTERNATE 1 by the host.

10: ALTERNATE2

Set to ALTERNATE 2 by the host.

REMOTE WAKEUP (Bit7)
0: Disable

Disabled remote wakeup by the host.

1: Enable

Enabled remote wakeup by the host.

Note1: Config, INTERFACE and ALTERNATE each support 3 kinds (0,1 and 2).
Note2: If each request is controlled by S/W, this register is not set.

92CZ26A-386

TMP92CZ26A
3.16.3.10 Standard Request Register
This register shows the standard request that is executing now.
A bit which is set to “1” shows present executing request.
7
Standard Recuest

(07CAH)

bit Symbol

6

S_INTERFACE G_INTERFACE

5

4

S_CONFIG

G_CONFIG

3

2

G_DESCRIPT S_FEATURE

1

0

C_FEATURE

G_STATUS

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

S_INTERFACE
G_INTERFACE
S_CONFIG
G_CONFIG
G_DESCRIPT
S_FEATURE
C_FEATURE
G_STATUS

(Bit 7) : SET_INTERFACE
(Bit 6) : GET_INTERFACE
(Bit 5) : SET_CONFIGRATION
(Bit 4) : GET_CONFIGRATION
(Bit 3) : GET_DESCRIPTOR
(Bit 2) : SET_FEATURE
(Bit 1) : CLEAR_FEATURE
(Bit 0) : GET_STATUS

3.16.3.11 Request Register
This register shows the device request that is executing now.
A bit which is set to “1” shows present executing request.
7
Request
(07CBH)

6

5

bit Symbol

SOFT_RESET

Read/Write

R

R

After reset

0

0

SOFT_RESET
G_PORT_STS
G_DEVICE_ID
VENDOR
CLASS
ExSTANDARD
STANDARD

4

3

2

1

0

VENDOR

CLASS

ExSTANDARD

STANDARD

R

R

R

R

R

0

0

0

0

0

G_PORT_STS G_DEVICE_ID

(Bit 6) : SOFT_RESET
(Bit 5) : GET_PORT_STATUS
(Bit 4) : GET_DEVICE_ID
(Bit 3) : Vender class request
(Bit 2) : Class request
(Bit 1) : Not support auto Bus Enumeration
(SET_DESCRIPTOR, SYNCH_FRAME)
(Bit 0) : Standard request

92CZ26A-387

TMP92CZ26A
3.16.3.12 DATASET Register
This register shows whether FIFO has data or not.
The application program can be checked it by accessing this register that whether
FIFO has data or not.
In the receiving status, when valid data transfer from USB host finished, bit which
correspond to applicable endpoint is set to “1” and generate interrupt. And, when
application read data of 1-packet, this bit is cleared to “0”. In the transmitting status,
when it terminated that 1-packet data transfer to FIFO, this bit is set to “1”. And when
valid data is transferred to USB host, this bit is cleared to “0” and generates interrupt.

7
DATASET1
(07CCH)

DATASET2
(07CDH)

bit Symbol

6

EP3_DSET_B EP3_DSET_A

5
EP2_DSET_B

4

3

2

1

EP2_DSET_A EP1_DSET_B EP1_DSET_A

0
EP0_DSET_A

Read/Write

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

7

6

4

3

2

bit Symbol

EP7_DSET_B EP7_DSET_A

5
EP6_DSET_B

1

0

EP6_DSET_A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

Note: DATASET1, DATASET2 registers are not used at TMP92CZ26A.

•

Single packet mode
(DATASET1: Bit0, bit2, bit4 and bit6

DATASET2: Bit0, bit2, bit4 and bit6)

These bits show whether FIFO of applicable endpoint has data or not.
In endpoint of receiving mode, if bit 1 of applicable endpoint is “1”, data that
should be read exist to FIFO. Access EPx_SIZE register, and grasp size of data
that should be read, and read data of its size. When this bit is “0”, data that
should be read does not exist.
In endpoint of transmitting mode, if bit of applicable endpoint is “0”, CPU can
be transferred data under the payload. If its bit is “1”, because of FIFO have
transfer waiting data, transfer data to FIFO in UDC after applicable bit was
cleared to “0”. When short-packet is transferred, access EOP register after
writing transmission data to applicable endpoint.
•

Dual packet mode
(DATASET1: Bit3, bit5 and bit7

DATASET2: Bit1, bit3 bit5 and bit7)

These bits become effective in the dual packet mode. This mode has FIFO of
2-packets.
Each packet (called packet-A, packet-B) has DATASET-bit.
In isochroous transfer, it shows data transfer that can access in present frame
the packet. This is different from above one. In this case, the bit that whether A
or B is set to “1”, it is renewed according as shifting flame.

92CZ26A-388

TMP92CZ26A
Note1: In the receiving mode, if bits that A-packet and B-packet of applicable endpoint are “1”, read data that
packet-number should be received, after checking DATASIZE.
Note2: In the transmitting mode, if the both A and B bits are not “1”, it means that there are space in FIFO. So, write
data for payload or less to FIFO. If transmission become short-packet, write “0” to EOP after
writing data to the FIFO. The maximum size that can be written to A or B packet is same with maximum
payload size. If the both A and B bits are “0”, continuous writing of double maximum payload size are available.
Note3: In the dual packet transmitting mode, if both A and B packet are empty and EOP is written “0”,
the NULL-data is set to FIFO. In the single mode, the NULL-data is also set to FIFO if the above operation is
executed by A packet don’t have data state.

92CZ26A-389

TMP92CZ26A

3.16.3.13 EPx_STATUS Register (x: 0 to 7)
These registers are status registers for each endpoint. The  is common
for all endpoint.
7
6
5
4
3
2
1
0
EP0_STATUS
(0790H)

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

After reset

0

0

1

1

1

0

0

6

5

4

3

2

1

0

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

7
EP1_STATUS
(0791H)

After reset

0

0

1

1

1

0

0

6

5

4

3

2

1

0

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

7
EP2_STATUS
(0792H)

After reset

7
EP3_STATUS
(0793H)

1

0

0

2

1

0

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

R

R

R

R

R

R

R

After reset

0

0

1

1

1

0

0

6

5

4

3

2

1

0

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

After reset

0

0

1

1

1

0

0

6

5

4

3

2

1

0

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

After reset

0

0

1

1

1

0

0

6

5

4

3

2

1

0

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

After reset

0

0

1

1

1

0

0

7
EP7_STATUS
(0797H)

1

3

TOGGLE

7
EP6_STATUS
(0796H)

1

4

bit Symbol

7
EP5_STATUS
(0795H)

0

5

Read/Write

7
EP4_STATUS
(0794H)

0

6

6

5

4

3

2

1

0

bit Symbol

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

FIFO_DISABLE

STAGE_ERR

Read/Write

R

R

R

R

R

R

R

After reset

0

0

1

1

1

0

0

Note: EP4, 5, 6 and 7_STATUS registers are not used TMP92CZ26A.

TOGGLE Bit (Bit6)
0: TOGGLE

Bit0

1: TOGGLE

Bit1

SUSPEND (Bit5)
0: RESUME
1: SUSPEND

This bit shows status of toggle sequence bit.

This bit shows status of power management of UDC.
In the SUSPEND status, some limitation about accessing to
UDC is needed.
For the detail, refer 3.10.9.

92CZ26A-390

TMP92CZ26A

STATUS [2:0]
(Bit4 to bit2)

These bits show status of endpoint of UDC.
The status show whether transfer it or not, or show result of
transfer. . These are depending on transfer type.
(For the Isochronous transfer type, refer 3.10.6.)

000: READY

Receiving:

Device can be received.
In the endpoint 1 to 7, this register is initialized to “READY” by setting transfer type at
SET_CONFIGURATION.
In the endpoint 0, this register is initialized to “READY” by detecting USB reset from
the host.
This is initialized to “READY” by terminating the status stage without error.

Transmitting:

Basically, this is same with “Receiving”.
But in transmitting, when data for transmission is set to FIFO and answer to token
from host and transfer data to host collect and received ACK, status register is not
change, and it keeps “READY”. In this case, EPx_Empty_A or EPx_Empty_B
interrupt show terminates transfer correctly.

001: DATAIN

UDC set to DATAIN and generates EPx_FULL_A or EPx_FULL_B interrupt when
data is received from the host without error.

010: FULL

Refer 3.10.8 (2) Details for the STATUS register.

011: TX_ERR

After transfer data to IN token from host, UDC set TX-ER to status register when it is
not received “ACK” from host. In this case, an interrupt is not generated. The hosts
re-try and transfer IN token to this.

100: RX_ERR

UDC set RX_ERR to status register without transmitting “ACK” to host when an error
(like a CRC-error) is detected in data of received token. In this case, an interrupt is
not generated. The hosts re-try and transfer IN token to this.

101: BUSY

This status is used only for the control transfer type and it is set when a token of
status-stage is received from the host after terminated data-stage.
When status-stage can be finished, terminate correctly and returns to READY. This is
not used in the Bulk and interrupts transfer type.

110: STALL

This status shows that applicable endpoint is STALL status.
This status, return STALL-handshake except SETUP-token. In the control endpoint,
returns to READY from stall condition when SETUP-token is received.
In the other endpoint, returns to READY when initialization command of FIFO is
received.
(Note) In Automatically answer of Set_Interface request, request to interface 4 to 6
may not become to request error. If this is problem, in Set_Interface request answer,
set Standard Request Mode  to “1” and use software.

111: INVALID

This status shows that applicable endpoint is UNCONFIGURED status.
In this status, the UDC has no reaction when token is received from the host.
By reset, all endpoint set to INVALID status. Only endpoint 0 returns to READY by
receiving USB-reset. Applicable endpoint returns to READY by configured.

92CZ26A-391

TMP92CZ26A

FIFO_DISABLE (Bit1)
0: FIFO enabled
1: FIFO disabled

STAGE_ERROR (Bit0)
0: SUCCESS
1: ERROR

This bit symbol shows FIFO status except EP0.
If the FIFO is set to disabled, the UDC transmits NAK
handshake forcibly for the all transfer. Disabled or enabled is set
by COMMAND register. This bit is cleared to “0” when transfer
type is changed.
This bit symbol shows that status stage is not terminated
correctly. ERROR is set when a status stage is not terminated
correctly and new SETUP token is received.
When this bit is “1”, this bit is cleared to “0” by read
EP0_STATUS register. This bit is not cleared even if normal
control transfer or other transfer is executed after. To clear, read
this bit. When software transaction is finished and UDC writes
EOP register, UDC shifts to status register and
waits
termination of status stage. In this case, if software is needed to
confirm that status stage is terminated correctly, when a new
request flag is received, it can be confirmed that whether last
request terminate correctly or not. And during request routine in
software, when new request flag is asserted, it can be confirmed
that whether last request is canceled or not halfway.

92CZ26A-392

TMP92CZ26A
3.16.3.14 EPx_SIZE Register (x: 0 to 7)
These registers have following function.
a) In the receiving, showing data number for 1 packet which was received correctly.
b) In the transmitting, it shows payload size. But it shows length value when short
packet is transferred.
This register is not needed to read when it is transmitting.
c)

Showing dual packet mode and effective packet.

Each endpoint has H (High)-register that shows upper bit 9 to bit7 of data size and L
(Low) register which shows lower bit 6 to bit0 and control bit of FIFO.
And each H/L register has 2-set for dual-packet mode.
By reset, these are initialized to maximum payload size.

EP0_SIZE_L_A
(0798H)

EP1_SIZE_L_A
(0799H)

EP2_SIZE_L_A
(079AH)

EP3_SIZE_L_A
(079BH)

EP4_SIZE_L_A
(079CH)

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

EP5_SIZE_L_A
(079DH)

EP6_SIZE_L_A
(079EH)

EP7_SIZE_L_A
(079FH)

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

7

6

5

4

3

2

1

0

bit Symbol

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

Read/Write

R

R

R

R

R

R

R

R

After reset

1

0

0

0

1

0

0

0

Note EP4,5,6,7_SIZE_L_A registers are not used at TMP92CZ26A.

92CZ26A-393

TMP92CZ26A

7
EP1_SIZE_L_B
(07A1H)

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

7
EP2_SIZE_L_B
(07A2H)

EP3_SIZE_L_B
(07A3H)

1

0

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

EP5_SIZE_L_B
(07A5H)

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

7
EP6_SIZE_L_B
(07A6H)

6

6

5

5

4

3

bit Symbol

7

5

4

3

bit Symbol

6

5

4

3

2

6

5

4

DATASIZE9

7

6

5

bit Symbol

7
EP4_SIZE_L_B
(07A4H)

6

4

4

3

3

3

After reset

7
EP7_SIZE_L_B
(07A7H)

6

5

4

3

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

Note EP3,4,5,6,7_SIZE_L_B registers are not used at TMP92CZ26A.

92CZ26A-394

TMP92CZ26A

7
EP1_SIZE_H_A
(07A9H)

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

7
EP2_SIZE_H_A
(07AAH)

1

0

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

EP5_SIZE_H_A
(07ADH)

Read/Write

R

R

R

After reset

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

7
EP6_SIZE_H_A
(07AEH)

6

5

5

4

4

3

3

3

After reset

7

EP7_SIZE_H_A
(07AFH)

6

4

3

bit Symbol

7

5

4

3

bit Symbol

6

5

4

3

2

6

5

4

DATASIZE9

7
EP4_SIZE_H_A
(07ACH)

6

5

bit Symbol

7
EP3_SIZE_H_A
(07ABH)

6

6

5

4

3

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

Note EP4,5,6,7_SIZE_H_A registers are not used at TMP92CZ26A.

92CZ26A-395

TMP92CZ26A

EP1_SIZE_H_B
(07B1H)

EP2_SIZE_H_B
(07B2H)

EP3_SIZE_H_B
(07B3H)

2

1

0

bit Symbol

7

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

7

1

0

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

6

5

4

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

6

5

4

3

bit Symbol

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

6

5

6

5

4

3

bit Symbol

7
EP6_SIZE_H_B
(07B6H)

5

3

2

7

6

4

DATASIZE9

7
EP5_SIZE_H_B
(07B5H)

5

bit Symbol

7
EP4_SIZE_H_B
(07B4H)

6

4

4

3

3

3

After reset

7
EP7_SIZE_H_B
(07B7H)

6

5

4

3

0

0

0

2

1

0

bit Symbol

DATASIZE9

DATASIZE8

DATASIZE7

Read/Write

R

R

R

After reset

0

0

0

Note EP3,4,5,6,7_SIZE_H_B registers are not used at TMP92CZ26A.

DATASIZE[9:7] (H register: Bit2 to bit0)
DATASIZE[6:0] (L register: Bit6 to bit0)

In receiving, data number that 1 packet received
from the host is shown. This is renewed when a data
from the host is received with no error.

PKT_ACTIVE (L register: Bit7)

When dual-packet mode is selected, this bit show
packet that can be accessed. In this case, the UDC
accesses packets that divide FIFO (Packet A and
Packet B) mutually. When FIFO in UDC is accessed by
CPU, refer to this bit. If receiving endpoint, start
reading from packet that this bit is “1”. In single-packet
mode, this bit is no meaning because of the packet-A is
always used.

1: OUT_ENABLE
0: OUT_DISABLE

92CZ26A-396

TMP92CZ26A
3.16.3.15 FRAME Register
This register shows frame number which is issued with SOF token from the host
and is used for Isochronous transfer type.
Each HIGH and LOW registers show upper and lower bits.

FRAME_L
(07E1H)

FRAME_H
(07E2H)

7

6

5

4

3

2

1

0

bit Symbol

−

T[6]

T[5]

T[4]

T[3]

T[2]

T[1]

T[0]

Read/Write

R

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

0

7

6

5

4

3

1

0

bit Symbol

T[10]

T[9]

T[8]

T[7]

CREATE

Read/Write

R

R

R

R

R

R

R

After reset

0

0

0

0

0

1

0

2

FRAME_STS1 FRAME_STS0

T[10:7] (H register: Bit7 to bit4)
T[6:0] (L register: Bit6 to bit0)

These bits are renewed when SOF-token is received.
And it shows frame-number.

CREATE (H register: Bit2)

These bits show enable function that generate SOF
SOF automatically from UDC. This is used for the case of
receiving error of SOF token.

0: DISABLE
1: ENABLE

This function is set by accessing COMMAND register.
By reset, this bit is initialized to “0”.
FRAME STS[1:0]
(H register: Bit1 and bit0)
0: BEFORE
1: VALID

These bits show the status whether a frame number
that is shown FRAME register is correct or not. At the
LOST status, a correct frame number is undefined.
If this register is “VALID”, number that is shown to
FRAME register is correct.

2: LOST

If this register is “BEFORE”, when SOF auto
generation, BEFORE condition shows it from USB host
controller inside that from SOF generation time to receive
SOF token. Correct value as frame-number is value that is
selected from FRAME register value.
3.16.3.16 ADDRESS Register
This register shows device address which is specified by the host in bus
enumeration.
By reading this register, a present address can be confirmed.
7
ADDRESS
(07E3H)

6

5

4

3

2

1

0

bit Symbol

A6

A5

A4

A3

A2

A1

A0

Read/Write

R

R

R

R

R

R

R

After reset

0

0

0

0

0

0

0

ADDRESS [6:0] (Bit6 to bit0)

The UDC compares this register and address in all packet
ID, and UDC judges whether it is an effective transaction or
not.
This is initialized to “00H” by USB reset.

92CZ26A-397

TMP92CZ26A
3.16.3.17 EOP Register
This register is used when a dataphase of control transfer type terminate or when a
short packet is transmitting of bulk-IN, interrupt-IN.

EOP
(07CFH)

7

6

5

4

3

2

1

0

bit Symbol

EP7_EOPB

EP6_EOPB

EP5_EOPB

EP4_EOPB

EP3_EOPB

EP2_EOPB

EP1_EOPB

EP0_EOPB

Read/Write

W

W

W

W

W

W

W

W

After reset

1

1

1

1

1

1

1

1

Note: EOP registers are not used at TMP92CZ26A.

In a dataphase of control transfer type, write “0” to  when all
transmission data is written to the FIFO, or read all receiving data from the FIFO.
UDC is terminated status stage by this signal.
When short packet is transmitted by using bulk-IN or interrupt-IN endpoint, use
this for terminate writing transmission data. In this case, write “0” to  of
writing endpoint. Write “1” to another bit.

92CZ26A-398

TMP92CZ26A
3.16.3.18 Port Status Register
This register is used when a request of printer class is received.
In case of request of GET_PORT_STATUS, the UDC operates automatically by
using this data.

Port Status
(07E0H)

7

6

5

4

3

2

1

0

bit Symbol

Reserved7

Reserved6

PaperError

Select

NotError

Reserved2

Reserved1

Reserved0

Read/Write

W

W

W

W

W

W

W

W

After reset

0

0

0

1

1

0

0

0

Note: TMP92CZ26A don’t use this register because of not support to printer-class.

The data should be written before receiving request.
Write “0” to  bit of this register. This register is initialized to “18H” by
reset.
3.16.3.19 Standard Request Mode Register
This register set answer for Standard Request either answer automatically in
Hardware or control in software. Each bit mean kind of request.
When this register is set applicable bit to “0”, answer is executed automatically by
hardware. When this register is set applicable bit to “1”, answer is controlled by
software. If request is received during hardware control, interrupt signal (INT_SETUP,
INT_EP0, INT_STAS, INT_STAN) is set to disable. If request is received during
software control, interrupt signal is asserted, and it is controlled by software.
7

6

5

4

3

2

1

0

Standard Request Mode

bit Symbol

S_Interface

G_Interface

S_Config

G_Config

G_Descript

S_Feature

C_Feature

G_Status

(07D8H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

S_Intetface
G_Interface
S_Config
G_Config
G_Descript
S_Feature
C_Feature
G_Status

(Bit 7) : SET_INTERFACE
(Bit 6) : GET_INTERFACE
(Bit 5) : SET_CONFIGRATION
(Bit 4) : GET_CONFIGRATION
(Bit 3) : GET_DESCRIPTOR
(Bit 2) : SET_FEATURE
(Bit 1) : CLEAR_FEATURE
(Bit 0) : GET_STATUS

92CZ26A-399

TMP92CZ26A
3.16.3.20 Request Mode Register
This register set answer for Class Request either answer automatically in Hardware
or control in software. Each bit mean kind of request.
When this register is set applicable bit to “0”, answer is executed automatically by
hardware. When this register is set applicable bit to “1”, answer is controlled by
software. If request is received during hardware control, interrupt signal (INT_SETUP,
INT_EP0, INT_STAS, INT_STATUSN) is set to disable. If request is received during
software control, interrupt signal is asserted, and it is controlled by software.
7
Request Mode
(07D9H)

6

5

4

bit Symbol

Soft_Reset

G_Port_Sts

G_DeviceId

Read/Write

R/W

R/W

R/W

After reset

0

0

0

3

2

1

Note: TMP92CZ26A don’t use this register because of printer-class is not support automatic answer.

Soft_Reset
G_Port_Sts
G_Config
G_Descript

(Bit 7)
: Reserved
(Bit 6)
: SOFT_RESET
(Bit 5)
: GET_PORT_STATUS
(Bit 4)
: GET_DEVICE_ID
(Bit 3 to 0) : Reserved

Note1: SET_ADDRESS request is supported by only auto-answer .
Note2: SET_DESCRIPTOR and SYNCH_FRAME are controlled by only software .
Note3: Vendor Request and Class Request (Printer Class and so on) are controlled by only software.
Note4: INT_SETUP, EP0, STAS and STASN interrupts assert only when it is software-control.

92CZ26A-400

0

TMP92CZ26A
3.16.3.21 COMMAND Register
This register sets COMMAND at each endpoint. This register can be set selection of
endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0.
COMMAND for endpoint that is supported is ignored.
7
COMMAND
(07D0H)

6

5

4

3

2

1

0

bit Symbol

EP[2]

EP[1]

EP[0]

Command[3]

Command[2]

Command[1]

Command[0]

Read/Write

W

W

W

W

W

W

W

After reset

0

0

0

0

0

0

0

Note: When writing to this register, the recovery time of 2clock at 12MHz is needed. If writing continuously, insert
dummy instruction more than 250 ns.

EP [2:0] (Bit6 to bit4)
000: Select endpoint 0
001: Select endpoint 1
010: Select endpoint 2
011: Select endpoint 3

COMMAND [3:0] (Bit3 to bit0)
0000: Reserved
0001: Reserved
0010: SET_DATA0

This COMMAND clear toggle sequence bit of applicable endpoint (EP0 to EP3).
If this COMMAND is inputted, it set toggle sequence bit of applicable endpoint to “0”
compulsively. Data toggle for transfer is renewed automatically by UDC. However, if
setting toggle sequence bit of endpoint to “0” compulsively, this COMMAND execution
need. If control transfer type and Isochronous transfer type, execution this COMMND
don’t need because of controlling in hardware.

0011: RESET

This COMMAND reset applicable endpoint (EP0 to EP3).
If this COMMAND is inputted, applicable endpoint is initialized. CLEAR_FEATURE
request stall endpoint. When this stall is cleared, execute this COMMAND. (This
command doesn’t affect to transfer mode.)
This command Initialize following item.
・Clear toggle sequence bit of applicable endpoint.
・Clear STALL of applicable endpoint.
・Set to FIFO_ENABLE condition.

0100: STALL

This COMMAND set applicable endpoint to STALL (EP0 to EP3).
If STALL handshake must be return as answer for device request, execute this
command.

0101: INVALID

This COMMAND set condition to prohibition using applicable endpoint (EP1 to EP3).
If UDC detect USB_RESET signal from USB host, it set all endpoint (except endpoint 0)
to prohibition using it automatically. If Config and Interface are changed by device
request, set endpoint that is not used to prohibit using.

0110: CREATE_SOF

This COMMAND set quasi-SOF generation function to enable (EP0).
Default is set to disable, it need using for Isochronous transfer.

0111: FIFO_DISABLE

This COMMAND set FIFO of applicable endpoint to disable (EP1 to EP3).
If this command is set from external, all of transfer for applicable endpoint returns NAK.
When it is set from external if during receiving packet, this becomes valid from next
token. This command doesn’t affect packet that is transferring.

92CZ26A-401

TMP92CZ26A

1000: FIFO_ENABLE

This COMMAND set FIFO of applicable endpoint to enable (EP1 to EP3).
If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for
release disable condition. If during receiving packet, this becomes valid from next token.
If USB_RESET is detected from host and RESET COMMAND execute and transfer
mode is set by using SET_CONFIG and SET_INTERFACE request, applicable
endpoint become FIFO_ENABLE condition.

1001: INIT_DESCRIPTOR

This COMMAND is used if descriptor RAM is rewritten during operates system (EP0).
If UDC detect USB_RESET from host controller, it read content of descriptor RAM
automatically, and it set various setting.
If descriptor RAM is changed during operates system, it must read setting again.
Therefore, execute this command. Case of connects to USB host, this function start
reading automatically. Therefore, don’t have to execute this command.

1010: FIFO_CLEA

This COMMAND initializes FIFO of applicable endpoint (EP1 to EP3).
However, EPx_STATUS is not initialized.
If resetting by software, execute this COMMAND.
This command Initialize following item.
・Clear STALL of applicable endpoint.
・Set to FIFO_ENABLE condition.

1011: STAL_CLEAR

This COMMAND clear STALL of applicable endpoint (EP1 to EP3).
If clearing only STALL of endpoint, execute this COMMAND.

92CZ26A-402

TMP92CZ26A
3.16.3.22 INT_Control Register
INT_STASN interrupt is disabled and enabled by value that is written to this
register.
This is initialized to disable by external reset. When setup packet is received, it
becomes to disable.
7
INT_Control
(07D6H)

6

5

4

3

2

1

0

bit Symbol

Status_nak

Read/Write

R/W

After reset

0

In control read transfer, if host terminate dataphase in small data length (smaller
than data length that is specified to wLength by host), device side and stage
management cannot be synchronized. Therefore, INT_STASN interrupt inform that
shift to status stage.
If this interrupt don’t need, it can set to disable because of this interrupt is asserted
every status stage.
STATUS_NAK (Bit0)
0: INT_STATSN interrupt disable
1: INT_STATSN interrupt enable

3.16.3.23 USB STATE Register
This register shows device state of present for connection with USB host.
7
USB STATE
(07CEH)

2

1

0

bit Symbol

6

5

4

3

Configured

Addressed

Default

Read/Write

R/W

R

R

After reset

0

0

1

Inside UDC, answer for each Device Request is managed by referring this bits
(Configured, Addressed and Default). If transaction for SET_CONFIG request is
executed by using software, write present state to this register. If host appointconfig0,
this becomes Unconfigured. And returning to Addressed state is needed. Therefore, if
host appoint config0, write bit2 to “0”.
When Configured bit (Bit2) is written “0”, Addressed bit (bit 1) is set automatically
by hardware. When host appoint config value that supported by device, device must
execute mode setting of each endpoint by using value that is appointed by
endpoint-descriptor in the config-descriptor. After finish mode setting, set Configured
bit (Bit2) to “1” before access EOP register. When this bit is set to “1”, Addressed bit
(Bit1) is set to “0” automatically.

Bit2 to bit0
000: Default
010: Addressed
100: Configured

92CZ26A-403

TMP92CZ26A
3.16.3.24 EPx_MODE Register (x: 1 to 3)
This register sets transfer mode of endpoint (EP1 to EP3).
If transaction of SET_CONFIG and SET_INTERFACE are set to software control,
this control must use appointed config or interface. When it is setting mode, access
this register.
7
EP1_MODE
(0789H)

5

4

3

2

1

0

bit Symbol

6

Payload[2]

Payload[1]

Payload[0]

Mode[1]

Mode[0]

Direction

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

7
EP2_MODE
(078AH)

5

4

3

2

1

0

bit Symbol

6

Payload[2]

Payload[1]

Payload[0]

Mode[1]

Mode[0]

Direction

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

7
EP3_MODE
(078BH)

5

4

3

2

1

0

bit Symbol

6

Payload[2]

Payload[1]

Payload[0]

Mode[1]

Mode[0]

Direction

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

There is limitation to timing that can be written.
If transaction for SET_CONFIG and SET_INTERFACE are set to software control,
after received INT_SETUP interrupt, finish writing before access EOP register. This
register prohibits writing when it is other timing, and it is ignored.
DIRECTION (Bit0)
0: OUT

Direction of from host to device

1: IN

Direction of from device to host

MODE [1:0] (Bit2 and bit1)
00: Control transfer type
01: Isochronous transfer type
10: Bulk transfer type or interrupt transfer type
11: Interrupt (No toggle)
Note: If setting endpoint that is set to Isochronous transfer mode to “no use”, after changed to
Isochronous mode, set to “no use” by COMMAND register.

PAYLOAD [2:0] (Bit3, bit4 and bit5)
000:

8 bytes

001:

16 bytes

010:

32 bytes

011:

64 bytes

0100:128 bytes
0101:256 bytes
0110:512 bytes
0111:1023 bytes (Note1, 2)

Note1: Max packet size of Isochronous transfer type is 1023 bytes.
Note2: If except 8, 16, ..., 1023 was set to wMaxPacketSize of descriptor, Payload
more than descriptor value is set by auto-answer of Set_Configration and
Set_Interface.
Others (Bit6 and bit7) Reserved

92CZ26A-404

TMP92CZ26A
3.16.3.25 EPx_SINGLE Register
This register sets mode of FIFO in each endpoint (SINGLE/DUAL).
EPx_SINGLE1
(07D1H)

7
bit Symbol

6

5

4

EP3_SELECT EP2_SELECT EP1_SELECT

3

2

1

0

EP3_SINGLE EP2_SINGLE EP1_SINGLE

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A.
Bit number
0: No use
1: EP1_SINGLE
2: EP2_SINGLE
3: EP3_SINGLE
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
When EPx_SELECT bit is “1”, EPx_SINGLE bit become valid in following content.
0: DUAL mode

1: SINGLE mode

If set ting content of EPx_SINGLE bit to valid, set EPx_SELECT bit to “1”.
0: Invalid

1: Valid

3.16.3.26 EPx_BCS Register
This register set mode that access to FIFO in each endpoint.
7
EPx_BCS1
(07D3H)

bit Symbol

6

5

4

EP3_SELECT EP2_SELECT EP1_SELECT

3

2

1

EP3_BCS

EP2_BCS

EP1_BCS

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

Bit number
0: No use
1: EP1_BCS
2: EP2_BCS
3: EP3_BCS
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
Always write “1” to EPx_BCS bit.
0: Reserved

1: CPU access

If setting content of EPx_BCS bit to valid, set EPx_SELECT bit to “1”.
0: Invalid

1: Valid

92CZ26A-405

0

TMP92CZ26A
3.16.3.27 USBREADY Register
This register informs finishing writing data to descriptor RAM on UDC.
After assigned data to descriptor RAM, write “0” to bit0.
7
USBREADY
(07E6H)

6

5

4

3

2

1

0

bit Symbol

USBREADY

Read/Write

R/W

After reset

0

USBREADY (Bit0)
0: Writing to descriptor RAM was finished.
1: Writing to descriptor RAM is enable.
(However, when during connecting to host, writing to descriptor RAM is prohibited.)

USB host

TMP92CZ26A
VCC
GND

VSS

CPU

PortXX
R1 = 1.5 kΩ
D+
15 kΩ

R2

15 kΩ

R3

UDC
D−

VDD
INTXX
PortXX
(Pull-up on/off)
Write signal
Descriptor RAM access
Device ID RAM
Register in USB

USBREADY registera access

Detect level of VDD signal from USB cable, and execute initialize sequence. In this
case, UDC disable detecting USB_RESET signal until USBREADY register is written
“0” after released USB_RESET.
If pull-up resister on D+ signal is controlled by using control signal, when pull-up
resister is connected to host in OFF condition, this condition is equivalent condition
with USB_RESET signal by pull-down resister in host side. Therefore UDC isn’t
detected in USB_RESET until write “0” to USBREADY register
Note1: Pull-up resister and control switch are needed at external of TMP92CZ26A.
Note2: Above setting is example when communication. It is needed special circuit for prevent flow current at
connector connect detection , no-use, no connection.

92CZ26A-406

TMP92CZ26A
3.16.3.28 Set Descriptor STALL Register
This register sets whether returns STALL automatically in data stage or status
stage for Set Descriptor Request.
7
Set Descriptor STALL

(07E8H)

6

5

4

3

2

1

0

bit Symbol

S_D_STALL

Read/Write

W

After reset

0

Bit0: S_D_STALL
0: Software control (Default)
1: Automatically STALL

3.16.3.29 Descriptor RAM Register
This register is used for store descriptor to RAM. Size of descriptor is 384 bytes.
However, when storing descriptor, write according to descriptor RAM structure
sample.
7

6

5

4

3

2

1

0

bit Symbol

D7

D6

D5

D4

D3

D2

D1

D0

~

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

(067FH)

After reset

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Descriptor RAM

(0500H)

This register can Read/Write only following timing; before detect USB_RESET,
during processing SET_DESCRIPTOR request.
SET_DESCRIPTOR request processes from INT_SETUP assert until access EOP
register.
If there is rewriting request of descriptor in SET_DESCRIPTOR, process request
following sequence.
1) Read descriptor that is transferred by SET_DESCRIPTOR requests every packet.
2)

When reading descriptor number of last packet finished, write all descriptors to
RAM for descriptor.

3)

When writing finished, execute INIT_DESCRIPTOR of COMMAND register.

4)

When all process finished, access EOP register, and finish status stage.

5)

When INT_STAS is received, it shows normal finish of status stage.

If USB_RESET is detected, it starts reading automatically. Therefore, when it
connect to host, executing of INIT_DESCRIPTOR command is not needed.

92CZ26A-407

TMP92CZ26A
3.16.4

Descriptor RAM
This area stores descriptor that is defined in USB. Device, Config, Interface, Endpoint
and String descriptor must set to RAM by using following format.

Device descriptor
18 bytes

Config 1 descriptor
(Interfaces, endpoints)
Under 255 bytes

Config 2 descriptor
(Interfaces, ENDPOINT)
Under 255 bytes
String0 length

1 byte

String1 length

1 byte

String2 length

1 byte

String3 length

1 byte

String0 descriptor
Under 63 bytes
String1 descriptor
Under 63 bytes
String2 descriptor
Under 63 bytes
String3 descriptor
Under 63 bytes

Note 1: If String Descriptor is supported, set StringxLength area to size0. No support String Dedcriptor
is returned STALL.
Note 2: Config Descriptior refers to descriptor sample.
Note 3: Sequencer in UDC decides Config number, Interface number and Endpoint number. Therefore,
if supporting Endpoint number is small, assign address according as priority.
Note 4: This function become effective only case of store descriptor as RAM.
Note 5: RAM size is total 384 bytes.
Note 6: Possible timing in RD/WR of descriptor RAM is only before detect USB_RESET and processing
SET_DESCRIPTOR request. (Prohibit access except this timing.)
Writing must finish before connect to USB host and processing SET_DESCRIPTOR request.
SET_DESCRIPTOR request processes from INT_SETUP assert until access EOP register.

92CZ26A-408

TMP92CZ26A
Descriptor RAM setting example:
Address

Data

Description

Description

Device Descriptor
500H

12H

bLength

501H

01H

bDescriptorType

Device Descriptor

502H

00H

bcdUSB (L)

USB Spec 1.00

503H

01H

bcdUSB (H)

IFC’s specify own

504H

00H

bDeviceClass

505H

00H

bDeviceSubClass

506H

00H

bDeviceProtocol

507H

08H

bMaxPacketSize0

508H

6CH

bVendor (L)

509H

04H

bVendor (H)

50AH

01H

IdProduct (L)
IdProduct (H)

Toshiba

50BH

10H

50CH

00H

bcdDevice (L)

50DH

01H

bcdDevice (H)

50EH

00H

bManufacture

Release 1.00

50FH

00H

IProduct

510H

00H

bSerialNumber

511H

01H

bNumConfiguration

Config1 Descriptor
512H

09H

BLength

513H

02H

bDescriptorType

Config Descriptor

514H

4EH

wtotalLength (L)

78 bytes

515H

00H

wtotalLength (H)

516H

01H

bNumInterfaces

517H

01H

bConfigurationValue

518H

00H

iConfiguration

519H

A0H

bmAttributes

Bus powered-remote wakeup

51AH

31H

MaxPower

98 mA

Interface0 Descriptor AlternateSetting0
51BH

09H

bLength

51CH

04H

bDescriptorType

51DH

00H

bInterfaceNumber

51EH

00H

bAlternateSetting

51FH

01H

bNumEndpoint

520H

07H

bInterfaceClass

521H

01H

bInterfaceSubClass

522H

01H

bInterfaceProtocol

523H

00H

iInterface

Interface Descriptor
AlternateSetting0

Endpoint1 Descriptor
524H

07H

bLength

525H

05H

bDescriptorType

Endpoint Descriptor

526H

01H

bEndpointAddress

OUT

527H

02H

bmAttributes

BULK

528H

40H

wMaxPacketSize (L)

64 bytes

529H

00H

wMaxPacketSize (H)

52AH

00H

bInterval

92CZ26A-409

TMP92CZ26A

Address

Data

Description

Description

Interface0 Descriptor AlternateSetting1
52BH

09H

52CH

04H

bLength
bDescriptorType

52DH

00H

bInterfaceNumber

52EH

01H

bAlternateSetting

52FH

02H

bNumEndpoints

530H

07H

bInterfaceClass

531H

01H

bInterfaceSubClass

532H

02H

bInterfaceProtocol

533H

00H

iInterface

Interface Descriptor
AlternateSetting1

Endoint1 Descriptor
534H

07H

bLength

535H

05H

bDescriptorType

Endpoint Descriptor

536H

01H

bEndpointAddress

OUT

537H

02H

bmAttributes

BULK

538H

40H

wMaxPacketSize (L)

64 bytes

539H

00H

wMaxPacketSize (H)

53AH

00H

bInterval

Endpoint2 Descriptor
53BH

07H

bLength

53CH

05H

bDescriptorType

Endpoint Descriptor
IN

53DH

82H

bEndpointAddress

53EH

02H

bmAttributes

BULK

53FH

40H

wMaxPacketSize (L)

64 bytes

540H

00H

wMaxPacketSize (H)

541H

00H

bInterval

Interface0 Descriptor AlternateSetting2
542H

09H

bLength

543H

04H

bDescriptorType

544H

00H

bInterfaceNumber

545H

02H

bAlternateSetting

546H

03H

bNumEndpoints

547H

FFH

bInterfaceClass

548H

00H

bInterfaceSubClass

549H

FFH

bInterfaceProtocol

54AH

00H

iInterface

Interface Descriptor
AlternateSetting2

Endpoint1 Descriptor
54BH

07H

bLength

54CH

05H

bDescriptorType

Endpoint Descriptor

54DH

01H

bEndpointAddress

OUT

54EH

02H

bmAttributes

BULK

54FH

40H

wMaxPacketSize (L)

64 bytes

550H

00H

wMaxPacketSize (H)

551H

00H

bInterval

Endpoint2 Descriptor
552H

07H

bLength

553H

05H

bDescriptorType

Endpoint Descriptor

554H

82H

bEndpointAddress

IN

555H

02H

bmAttributes

BULK

556H

40H

wMaxPacketSize (L)

64 bytes

557H

00H

wMaxPacketSize (H)

558H

00H

bInterval

92CZ26A-410

TMP92CZ26A

Address

DATA

Description

Description

Endpoint3 Descriptor
559H

07H

bLength

55AH

05H

bDescriptorType

Endpoint Descriptor

55BH

83H

bEndpointAddress

IN

55CH

03H

bmAttributes

Interrupt
8 bytes

55DH

08H

wMaxPacketSize (L)

55EH

00H

wMaxPacketSize (H)

55FH

01H

bInterval

1 ms

String Descriptor Length Setup Area
560H

04H

bLength

Length of String Descriptor0

561H

10H

bLength

Length of String Descriptor1

562H

00H

bLength

Length of String Descriptor2

563H

00H

bLength

Length of String Descriptor3

String Descriptor0
564H

04H

bLength

565H

03H

bDescriptorType

String Descriptor

566H

09H

bString

Language ID 0x0409

567H

04H

bString

String Descriptor1
568H

10H

bLength

569H

03H

bDescriptorType

String Descriptor

56AH

00H

bString

(Toshiba)

56BH

54H

bString

T

56CH

00H

bString

56DH

6FH

bString

56EH

00H

bString

56FH

73H

bString

570H

00H

bString

571H

68H

bString

572H

00H

bString

573H

69H

bString

574H

00H

bString

575H

62H

bString

576H

00H

bString

577H

61H

bString

o
s
h
i
b
a

String Descriptor2
String Descriptor3

92CZ26A-411

TMP92CZ26A
3.16.5

Device Request

3.16.5.1 Standard request
UDC support automatically answer in standard request.
(1) GET_STATUS Request
This request returns status that is appointed of receive side, automatically.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

10000000B

GET_STATUS

0

0

2

Device, interface or
endpoint status

10000001B

Interface

10000010B

endpoint

Request to device returns following information according to priority of little
endian.
D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

Remote
wakeup

Self
power

D15

D14

D13

D12

D11

D10

D9

D8

0

0

0

0

0

0

0

0

• Remote wakeup

It returns present remote wakeup setting.
This bit is set or reset by SET_FEATURE or
CLEAR_FEATURE request. Default is value that is set to
bmAttributes field in Config descriptor.

• Self power

It returns present power supply setting. This bit return Self
or Bus Power according to value that is set to bmAttributes
field in Config descriptor.

Request to interface returns 00H of number of 2 bytes.
Request to endpoint returns in according to priority of little endian following
information.
D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

HALT

D15

D14

D13

D12

D11

D10

D9

D8

0

0

0

0

0

0

0

0

• HALT

It return halts status of endpoint that is selected.

92CZ26A-412

TMP92CZ26A
(2) CLEAR_FEATURE request
This request clears or disables particular function.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

00000000B

CLEAR_
FEATURE

Feature
selector

0
Interface
endpoint

0

None

00000001B
00000010B

• Reception side device
Feature selector: 1

Present remote wakeup setting is disabled.

Feature selector: except 1

STALL state

• Reception side interface
STALL state

• Reception side end point
Feature selector: 0

Halt of applicable endpoint is cleared.

Feature selector: except 0

STALL state

Note: If it request to endpoint that is not exist, it stall.

(3) SET_FEATURE request
This request set or enables particular function.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

00000000B

SET_
FEATURE

Feature
selector

0
Interface
endpoint

0

None

00000001B
00000010B

• Reception side device
Feature selector: 1

Present remote wakeup setting is disabled.

Feature selector: except 1

STALL state

• Reception side interface
STALL state

• Reception side end point
Feature selector: 0

Halt of applicable endpoint

Feature selector: except 0

STALL state

Note: If it request to endpoint that is not exist, it stall.

92CZ26A-413

TMP92CZ26A
(4) SET_ADDRESS request
This request set device address. Following request answer by using this device
address.
Answer of request is used present device address until status stage of this
request finish normally.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

00000000B

SET_ADDRESS

Device Address

0

0

None

(5) GET_DESCRIPTOR request
This request returns appointed descriptor.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

10000000B

GET_
DESCRIPTOR

Descriptor type
and Descriptor
index

0

Descriptor
length

Descriptor

or

• Device
• Config

Language ID

Device transmits device descriptor that is stored to descriptor RAM.
Config transmits config descriptor that is stored to descriptor RAM.
At this point, it transmits not only config descriptor but also
interface and endpoint descriptor.

• String

String transmits string descriptor of index that is appointed lower
byte of wValue field.

Note: Decriptor of short data length in wLength and descriptor length is transmitted by automatically answer of
Get_Descriptor.

92CZ26A-414

TMP92CZ26A
(6) SET_DESCRIPTOR request
This request sets or enables particular function.
bmRequestType
00000000B

bRequest

wValue

wIndex

wLength

Data

SET_
Descriptor

Descriptor type

0

Descriptor

Descriptor

and

or

length

Descriptor index

Language ID

Automatically answer of this request does not support.
According to INT_SETUP interrupt, if receiving request was discerned as
SET_DESCRIPTOR request, take back data after it confirmed EP0_DSET_A bit
of DATASET register is “1”. When finishing, access EOP register, and write “0” to
EP0_EOPB bit. Therefore, status stage finish. Transaction is same with vendor
request.
Pleas refer to vendor request section.
(7) GET_CONFIGURATION request
This request returns configuration value of present device.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

10000000B

GET_
CONFIG

0

0

1

Configuration
value

If it is not configured, it returns “0”. If configuration, it returns configuration
value.
(8) SET_CONFIGURATION request
This request sets device configuration.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

00000000B

SET_
CONFIG

Configuration

0

0

None

value

It configured in value that is appointed by using lower byte of wValue field.
When this value is “0”, it is not configured.

92CZ26A-415

TMP92CZ26A
(9) GET_INTERFACE request
This request returns AlternateSetting value that is set by appointed interface.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

10000001B

GET_
INTERFACE

0

Interface

1

Alternate
setting

If there is not appointed interface, it become to STALL state.
(10) SET_INTERFACE request
This request selects AlternateSetting in appointed interface.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

00000001B

SET_
INTERFACE

Alternate
setting

Interface

0

None

If there is not appointed interface, it become STALL state.
(11) SYNCH_FRAME request
This request transmits synchronous frame of endpoint.
bmRequestType

bRequest

wValue

wIndex

wLength

Data

10000010B

SYNCH_FRAME

0

Endpoint

2

Frame No.

Automatically answer of this request does not support.
According to INT_SETUP interrupt, if receiving request was discerned as
SYNCH_FRAME request, write data of 2byte in Frame No after it confirmed
EP0_DSET_A bit of DATASET register is “0”. When finishing, access EOP register,
and write “0” to EP0_EOPB bit. Therefore, status stage finish. It can be used only
in case of endpoint support isochronous transfer type and support this request.
Transaction is same with vendor request.
Pleas refer to vendor request section.

92CZ26A-416

TMP92CZ26A
3.16.5.2 Printer Class Request
UDC does not support “Automatic answer” of printer class request.
Transaction for Class request is the same as vendor request; answering to
INT_SETUP interrupt.
3.16.5.3 Vendor request (Class request)
UDC doesn’t support “Automatic answer” of Vendor request.
According to INT_SETUP interrupt, access register that device request is stored,
and discern receiving request. If this request is vendor request, control UDC from
external, and execute transaction for Vendor request.
Below is explanation for case of data phase is transmitting (Control read), and
case of data phase is receiving (Control write).
(a) Control Read request
bmRequestType

bRequest

wValue

wIndex

wLength

Data

110000xxB

Vender peculiar

Vender peculiar

Vender peculiar

Vender peculiar
(Expire 0)

Vendor data

When INT_SETUP is received, judge contents of receiving request by
bmRequestType, bRequest, wValue, wIndex and wLength registers. And execute
transaction for each request. As application, access Setup_Received register after
request was judged. And it must inform that INT_SETUP interrupt was
recognized to UDC.
After transmitting data prepared in application, access DATASET register, and
confirm EP0_DSET_A bit is “0”. After confirming, write data FIFO of endpoint 0.
If transmitting data more than payload, write data after it confirmed whether a
bit of EP0_DSET_A in DATASET register is “0”. (INT_ENDPOINT0 interrupt is
can be used.) If writing all data finished, write “0” to EP0 bit of EOP register.
When UDC receive it, status stage finish automatically.
And when UDC finish status stage normally, INT_STATUS interrupt is
asserted. If finishing status stage normally is recognized to external application,
manage this stage by using this interrupt signal. If status stage cannot be
finished normally and during status stage, maybe new SETUP token is received.
In this case, when INT_SETUP interrupt signal is asserted, “1” is set to
STAGE_ERROR bit of EP0_STATUS register. And it informs it to external that
status stage cannot be finished normally.
And maybe dataphase finish in data number that is short than value showed
to wLength by protocol of control read transfer type in USB. If application
program is configured by using only wLength value, transaction for it cannot be
when host shift to status stage without arriving at expecting data number. At this
point, shifting to status stage can be confirmed by using INT_STATUSNAK
interrupt signal. (However, releasing mask of STATUS_NAK bit by using
interrupt control register is needed.) In Vendor Request, this problem will not
generate because of receiving buffer size is set to host controller by driver,
actually.
Note: In every host, data (data that is transmitted from device by payload of 8 bytes) may be
recognized to short packet until confirming payload size of device side. And it may become to above
case on the exterior. Therefore, if controlling standard request by using software, be careful.)

92CZ26A-417

TMP92CZ26A
(b) Control write/request
There is no dataphase
bmRequestType

bRequest

wValue

wIndex

wLength

Data

010000xxB

Vendor peculiar

Vendor peculiar

Vendor peculiar

0

None

When INT_SETUP is received, judge contents of receiving request by
bmRequestType, bRequest, wValue, wIndex, wLength registers. And execute
transaction for each request. As application, access Setup_Received register
after request was judged. And it must inform that INT_SETUP interrupt was
recognized to UDC. If transaction of application finished, write “0” to EP0 bit
of EOP register. When UDC receive it, status stage finish automatically.
There is dataphase
bmRequestType

bRequest

wValue

wIndex

wLength

Data

010000xxB

Vendor peculiar

Vendor peculiar

Vendor peculiar

Vendor peculiar
(Except for 0)

Vendor data

When INT_SETUP is received, judge contents of receiving device request
by bmRequestType, bRequest, wValue, wIndex, wLength registers. And
execute transaction for each request. As application, access Setup_Received
register after request was judged. And it must inform that INT_SETUP
interrupt was recognized to UDC.
After receiving data prepared in application, access DATASET register, and
confirm EP0_DSET is “1”. After confirming, read data FIFO of endpoint 0. If
receiving data more than payload, write data after it confirmed whether a bit
of EP0_DSET_A in DATASET register is “1”. (INT_ENDPOINT0 interrupt is
can be used.) If reading all data finish, write “0” to EP0 bit of EOP register.
When UDC receive it, status stage finished automatically.
And when UDC finish status stage normally, INT_STATUS interrupt is
asserted. If finishing status stage normally is recognized to external
application, manage this stage by using this interrupt signal. If status stage
cannot be finished normally and during status stage, maybe new SETUP
token is received. In this case, when INT_SETUP interrupt signal is asserted,
“1” is set to STAGE_ERROR bit of EP0_STATUS register. And it informs it to
external that status stage cannot be finished normally.

92CZ26A-418

TMP92CZ26A
Below is control flow in UDC watch from application.
Start up

Setting each EP mode
in Set_Config (Interface)

IDLE

Standard request
Printerclass request

Enumeration
Judge request RD
Access to SetupReceived register
Control RD transfer

EP0 bit = 1

Control WR transfer

Get_Vendor_Request
transaction

Check
DATASET
register

EP0 bit = 0

Transmit
judgement
Total_Length

Total ≥ payload
WR number of payload
to EP0_FIFO register
Total = Total − payload

EP0 bit = 0
Check
DATASET
register

EP0 bit = 1

Receive
judgement
Total_Length

Total < payload

Total > payload

Total ≤ payload

WR number of rest data
to EP0_FIFO
Total = 0

RD number of payload
from EP0_FIFO register
Total = Total − payload

RD number of rest data
from EP0_FIFO
Total = 0

Receive
except
INT_STATUS
Abnormal
finish

Set_Vendor_Request
transaction

WR “0” only EP0 bit0 of
EOP register

Status finish
transacrion in UDC

Normal
finish
Receive
INT_STAS

Figure 3.16.6 Control Flow in UDC Watch from Application
Note 1: There is not special case in this flow such as overlap receive SETUP packet.
Please refer to chaptor 4.5.2.3.
Note 2: This flow shows various request. However, transaction can be divided every each interrupt.

92CZ26A-419

Total = 0
Not
transaction
Total = 0

TMP92CZ26A
3.16.6

Transfer mode and Protocol Transaction
UDC perform automatically in hardware as follows;
• Receive packet
•

Judge address endpoint transfer mode

•

Error process

•

Confirm toggle bit CRC of data receiving packet

•

Generate including toggle bit CRC of data transmitting packet

•

Handshake answer

(1) Protocol outline
Format of USB packet is showed to below. This is processed during transmission and
receiving by hardware into UDC.
•

SYNC field
This field always exists first of each packet, and input data and internal CLK is
synchronized in UDC.

•

Packet identification field (PID)
This field follows on SYNC field at every USB packet. UDC judge PID type and
judge transfer type by decoding this cord.

•

Address field
UDC confirms whether this function was appointed or not from host by using
this field. UDC compares with address that was set to ADDRESS register. If an
address accords with it, UDC continues process. If an address doesn’t accord, UDC
ignores this token.

•

Endpoint field
If sub-channels more than two is needed in field of 4 bits, it decides it function.
UDC can be supported endpoint except for control endpoint (max 7 endpoint).
Token for endpoint that is permitted is ignored.

•

Frame number field
Field of 11 bits is added +1 at every frame by host. This field follows to SOF token
that is transmitted in first of each frame, and frame number is appointed. UDC
reads content of this field when SOF token is received, and it sets frame number to
FRAME register.

•

Data field
This field is data of unit byte in 0 to 1023 bytes. When receiving it, UDC
transfers only part of this data to FIFO, after CRC was confirmed, interrupt signal
is asserted. And UDC informs finishing transferring data to FIFO. When
transmitting, following IN token, data of FIFO is transferred. Finally, data CRC
field is attached.

•

CRC function
Token is attached 5 bits, data is attached CRC of 15 bits. UDC compares CRC of
received data with attached CRC automatically. When transmission, CRC is
generated automatically and it is transmitted. This function may be compared by
various transfer modes.

92CZ26A-420

TMP92CZ26A
(2) Transfer mode
UDC support transfer mode in FULL speed.
•

FULL speed device
Control transfer type
Interrupt transfer type
Bulk transfer type
Isochronous transfer type
Following is explanation of UDC operation in each transfer mode.
Explanation of data flow is explanation until FIFO.

(a) Bulk transfer type
Bulk transfer type warrants transferring no error between host and function by
using detect error and retry. Basically, 3 phases (token, data and handshake are
used) are used. However, if flow control and STALL condition, data phase is
changed to hand shake phase, and it become to 2 phases. UDC holds status of
every each endpoint, and it control flow control in hardware. Each endpoint
condition can be confirmed by using EPx_STATUS register.

92CZ26A-421

TMP92CZ26A
(a-1) Transmission bulk mode
Below is transaction format of bulk transfer during transmitting.
•
•
•

Token: IN
Data: DATA0/DATA1, NAK, STALL
Handshake: ACK

Control flow
Below is control-flow when UDC receive IN token.
1.

Token packet is received and address endpoint number error is confirmed, and it
checks whether conform applicable endpoint transfer mode with IN token. If it
doesn’t conform, state return to IDLE.

2.

Condition of EPx_STATUS register is confirmed.
•
INVALI condition: State return to IDLE.
•
STAL condition: Stall handshake is returned and state return to IDLE.
FIFO condition is confirmed, if data number of 1 packet is not prepared, NAK
handshake is returned, and state return to IDLE.
If data number of 1 packet is prepared to FIFO, it shifts to 3.

3.

Data packet is generated.
Data packet generated by using toggle bit register in UDC.
Next, it transfers data from FIFO of internal UDC to SIE, and data packet is
generated. At this point, it confirms transferred data number. And if there is more
than max payload size of each endpoint, bit stuff error is generated, and finish
transfer. And STATUS becomes to STALL.

4.

CRC bit (counted transfer data of FIFO from first to last) is attached to last.

5.

When ACK handshake from host is received,
•

Clear FIFO.

•

Clear DATASET register.

•

Renew toggle bit, and prepare for next.

•

Set STATUS to READY.

UDC finishes normally. FIFO can be received next data.
If it is time out without receiving ACK from host,
•

Set STATUS to TX_ERR.

•

Put back addles pointer of FIFO.

Execute above setting. And wait next retry keeping FIFO data.
This flow is Figure 3.16.7.

92CZ26A-422

TMP92CZ26A

IDLE
Receive IN token

Error

ConfirmToken packet
• PID
• Address
• Endpoint
• Transfer mode
• Error

Invalid

OK
Confirm Handshake answer
• Confirm STATUS register (Status)
• Confirm DATASET register

Stall
FIFO empty

OK
More than MAX
payload

Generate DATA PID
• Attach DATA0/DATA1
• Confirm Datasize register

Transmit NAK

Transmit STALL

OK
Transmit data

Bit stuff error
Set STATUS at STALL

OK
Attach CRC
OK

Time out
• Set STATUS to TX_ERR
• Put back addless pointer of FIFO

Wait ACK
to host
Receive ACK

Normal finish transaction
• Clear FIFO
• Clear DATASET register
• Renew toggle bit
• Set STATUS to READY

Figure 3.16.7 Control Flow in UDC (Bulk transfer type (transmission)/Interrupt transfer type (transmission))

92CZ26A-423

TMP92CZ26A
(a-2) Receiving bulk mode
Below is transaction format receiving bulk transfer type. It has to follow below.
•

Token: OUT

•

Data: DATA0/DATA1

•

Handshake: ACK, NAK, STALL

Control flow
Below is control-flow when UDC receive IN token.
1.

Token packet is received and address endpoint number error is confirmed, and it
checks whether conform applicable endpoint transfer mode with OUT token. If it
doesn’t conform, state return to IDLE.

2.

Condition of status register is confirmed.
•

INVALID condition: State return to IDLE.

•

STALL condition: When dataphase finish, stall handshake is returned
and state return to IDLE, and data is canceled.
FIFO condition is confirmed, if data number of 1 packet is not prepared, present
transferred data is canceled, NAK handshake is returned after dataphase, and
state return to IDLE.
3.

Data packet is received.
Data is transferred from SIE of internal UDC to FIFO. At this point, it confirms
transferred data number. And if there is more than max payload size of each
endpoint, STATUS become to STALL and state return to IDLE. ACK handshake
doesn’t return.

4.

After last data was transferred, and compare counted CRC with transferred CRC.
If it doesn’t conform, it sets STATUS to RX_ERR and state return to IDLE. At this
point it doesn’t return ACK.
After retry, when next data is received normally, STATUS changes to DATIN. If it
doesn’t accord data toggle, it was judged don’t take ACK in last loading. And now
loading is regarded retry of last loading and data cancel. Set STATUS as RX_ERR,
return to host and return IDLE. FIFO address pointer returns. And it can be
received next data.

5.

If CRC compare with toggle and it finished normally, ACK handshake is returned.
Bellow is process in UDC.
•

Set transfer data number to DATASIZE register.

•

Set DATASET register.

•

Renew toggle bit, and prepare for next.

•

Set STATUS to READY.

UDC finishes normally.
This flow is Figure 3.16.8.

92CZ26A-424

TMP92CZ26A

IDLE
Receive OUT token

Error

Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error

Invalid

OK
Confirm Status
• Confirm STATUS register (status)
• Confirm FIFO’s condition

Stall
FIFO empty
Error transaction
• Set STATUS at
RX_ERR
• Put back FIFO
address pointer

OK
Except data PID
Time out

Generate DATA PID
• DATA0/DATA1
• Time out
• Toggle check
OK

Toggle error
• Set STATU Sat RX_ERR
• Put back FIFO address
pointer
• Retry recognition clean
data
Receive data
• Error
• Confirm receiving data
number

Cancel data

Cancel data
Error
transaction
• Set status to
stall

Data communication of
more than payload

OK

Transmit ACK

OK

Transmit NAK

Transmit STALL

Retry transaction

Normal finish transaction
• Set transfer data number to DATASIZE
register
• Set DATASET register
• Renew toggle bit
• Set STATUS to DATAIN

Figure 3.16.8 Control Flow in UDC (Bulk transfer type (Receiving))

92CZ26A-425

TMP92CZ26A
(b) Interrupt transfer type
Interrupt transfer type use transaction format same with transmission bulk
transfer.
When transmission by using toggle bit, hardware setting and answer in UDC
are same with transmission bulk transfer. Interrupt transfer can be transferred
without using toggle bit. In this case, if ACK handshake from host is not received,
toggle bit is renewed, and finish normally. UDC clears FIFO for next transfer.
(b-1) Interrupt transmitting mode (Toggle mode)
UDC operation is same with bulk transmission mode. Please refer to section
(a).
(b-2) Interrupt transmission mode (Not toggle mode)
This is same bulk transmission mode basically. However, if ACK handshake
from host is not received, transaction is different.
After transmit data packet,
When ACK handshake from host is received,
•

Clear FIFO.

•

Clear DATASET register.

•

Renew toggle bit and prepare for next.

•

Set STATUS to READY.

UDC finishes normally by above transaction. FIFO can be received next data.
If it is time out without receiving ACK from host,
•

Clear FIFO.

•

Clear DATASET register.

•

Renew toggle bit and prepare for next.

•

Set STATUS to TX_ERR.

Execute above setting. This setting is same with except STATUS.

92CZ26A-426

TMP92CZ26A
(c) Control transfer type
Control transfer type is configured in below three stages.
•

Setup stage

•

Data stage

•

Status stage

Data stage is skipped sometimes. Each stage is configured in one or plural
transaction. UDC executes each transaction while managing of three stages in
hardware. Control transfer type has below 3 type by whether there is data stage
or not, or direction.
•

Control read transfer type

•

Control write transfer type

•

Control write transfer type (Not data stage)

3-transfer sequences are shown in Figure 3.16.10, Figure 3.16.11 and Figure
3.16.12.
UDC answers automatically about standard request in hardware. Class request,
vendor request have to intervening CPU on controlling UDC.
Below is control flow in UDC and control flow in intervening CPU.
(c-1) Setup stage
Setup stage is same with transmission bulk transaction except case of token ID
become to SETUP.
However, control flow in UDC differ it.
•

Token: SETUP

•

Data: DATA 0

•

Handshake: ACK

Control flow
Below is control flow in UDC when SETUP token is received.
1.

SETUP token packet is received and address, endpoint number and error
are confirmed. And it checks whether applicable endpoint is the control
transfer mode.

2.

STATUS register state is confirmed.

State return to IDLE only it is INVALID state.
In bulk transfer mode, receiving data is enabled by STATUS registers value
and FIFO condition. However, in SETUP stage, STATUS is returned to
READY and accessing from CPU to FIFO is prohibited always, and internal
FIFO of endpoint 0 is cleared. And it prepares for following dataphase.
If CPU accesses Setup Received registers in UDC, it recognizes as Device
request is received, and accessing from CPU to EP0 is enabled.
There is this function for receiving it if new request is received in during
present device request is not finishing normally.

92CZ26A-427

TMP92CZ26A
3.

Data packet is received.
Device request of 8 bytes from SIE in UDC is transferred to below
request register.
•

bmRequestType register

•

bmRequest register

•

wValue register

•

wIndex register

•

wLength register

4.

After last data was transferred, and compare counted CRC with
transferred CRC. If it doesn’t conform, it sets STATUS to RX_ERR and
state return to IDLE. At this point it doesn’t return ACK, and host retry.

5.

If CRC compare with toggle and it finish normally, ACK handshake is
returned to host. Bellow is process in UDC.
•

Receiving device request is judged whether software control or
hardware control, if request need control in software, request is
informed receiving to external by asserting INT_SETUP interrupt.
If using hardware, INT_SETUP interrupt is not asserted.

•

According to stage control flow, prepare for next stage.

•

Set STATUS to DATAIN.

•

Set toggle bit to “1”.

Setup stage finishes by above.
This flow is Figure 3.16.6.
8-byte data that is transferred by this SETUP stage is device request.
CPU must process correspond it device request.
UDC detects following contents only from data of 8 bytes, and it manages
stage in hardware.
•

There is data stage or not

•

Data stage direction

It judges control read transfer type, control write transfer type, control
write transfer type (not data phase) by them.

92CZ26A-428

TMP92CZ26A

IDLE
Receive SETUP token

Error

Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error

Invalid

OK

Error transaction
• Set STATUS to RX_ERR
• Put back FIFO address point

Confirm Status
• Confirmation STATUS register (Status)
OK
Confirm DATA PID
• DATA0
• Time out

Except DATA0 PID
Time out

OK
Error, more than payload data comunication
Receive data
• Error
• Confirm receving data
number
OK

Transmit ACK
OK

Normal finish transaction
• Set DATASET register
• Assert INT_SETUP and request flag
• According to stage flow, prepare for next stage
• Set STATUS to DATAIN
• Set toggle bit to 1

Figure 3.16.9 Control Flow in UDC (Setup stage)

92CZ26A-429

TMP92CZ26A
(c-2) Data stage
Data stage is configured by one or plural transaction base on toggle sequence.
Transaction is same with format transmission or receiving bulk transaction.
However, below is difference.
•

Toggle bit start from “1” by SETUP stage.

•

It judges whether right or not by comparing IN and OUT token with
direction bit of device request. If token that direction is reverse was
received, it is recognized as status stage.

•

INT_ENDPOINT0 interrupt is asserted.

(c-3) Status stage
Status stage is configured 0-data-length packet with DATA1’s PID and
handshake behinds IN or OUT token. It uses transaction that direction different
with preceding stage.
Combination is below.
•

Control read transfer type: OUT

•

Control write transfer type: IN

•

Control write transfer type (not dataphase): IN

UDC processes status stage base of control flow in control transfer type. At this
point, CPU must write “0” to EP0 bit of EOP register in last transaction for status
stage finish normally.
Below is detail of status stage.
(c-3-1) IN status stage
Below is IN status stage transaction format.
•

Token: IN

•

Data: DATA1 (0 data length), NAK, STALL

•

Handshake: ACK

Control flow
Below is transaction flow of IN status stage in UDC.
1.

Token packet is received and address, endpoint number and error are
confirmed. If it doesn’t conform, state return to IDLE. If status stage
is enabled base on stage control flow in UDC, advance next stage.

2.

STATUS register state is confirmed.
•

INVALID condition: State return to IDLE.

•

STALL condition: Stall handshake is returned and state return
to IDLE.
It confirm whether EOP register is accessed or not by external. If it
is not accessing, NAK handshake is returned for continue control
transfer. And state return to IDLE.

3.

If EOP register is accessed was confirmed, 0-data-length data packet
and CRC are transmitted.

92CZ26A-430

TMP92CZ26A
4.

If ACK handshake from host is received,
•

Set STATU to READY.

•

Assert INT_STATUS interrupt.

It finishes normally by above transaction.
If it is time out without receiving ACK from host,
•

Set STATUS register to TX_ERR and state return IDLE. And wait
restring status stage.

At this point, if new SETUP stage is started without status stage finish
normally, UDC sets error to STATUS register.
(c-3-2) OUT status stage
Below is transaction format of OUT status stage.
•

Token: OUT

•

Data: DATA1 (0 data length)

•

Handshake: ACK, NAK, STALL

Control flow
Below is transaction flow of OUT status stage in UDC.
1.

Token packet is received and address, endpoint number and error are
confirmed. If it doesn’t conform, state return to IDLE. If status stage
is enabled base on stage control flow in UDC, advance next stage.

2.

STATUS register state is confirmed.
•

INVALID condition: State return to IDLE.

•

STALL condition: Data is cleared, stall handshake is returned,
and state return to IDLE.

It confirm whether EOP register is accessed or not by external. If it is
not accessing, NAK handshake is returned for continue control
transfer. And state return to IDLE.
3.

If EOP register is accessed was confirmed, 0-data-length data packet
and CRC are received.

4.

If there is not error in data, ACK handshake is transmitted to host.
•

Set STATUS to READY.

•

Assert INT_STATUS interrupt.

It finishes normally by above transaction.
If there is error in data, ACK handshake is not returned.
•

Set RX_ERR to STATUS register and return to IDLE. It waits retrying
status stage.

At this point, if new SETUP stage is started without status stage finish
normally, UDC sets error to STATUS register. Sequence of this protocol refers
to section supplement.

92CZ26A-431

TMP92CZ26A
(c-4) Stage management
UDC manages each stage of control transfer by hardware.
Each stage is changed by receiving token from USB host, or CPU accesses
register. Each stage in control transfer type has to process combination software.
UDC detect following contents from 8-byte data in SETUP stage. (It contents is
showed to following.) And, stage is managed by judging control transfer type.
•

There is data stage or not

•

Data stage direction

Control read transfer type is jugged control write transfer type, control write
transfer type (No data stage) by them.
Below are various conditions for changing stage in control transfer.
If receiving token for next stage from host before switching next stage from
state of internal UDC, NAK handshake is returned and BUSY is informed to USB
host. In all control transfer type, if SETUP token is received from host always,
present transaction is stopped, and it switches SETUP stage in UDC. CPU receive
new INT_SETUP even if it is processing previous control transfer.

92CZ26A-432

TMP92CZ26A
Stage change condition of control read transfer type
1.

2.

3.

Receive SETUP token from host
•

Start setup stage in UDC.

•

Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.

•

Change data stage into the UDC.

Receive IN token from host
•

CPU receive request from request register every INT_SETUP
interrupt.

•

Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.

•

According to Device request, monitor EP0 bit of DATASET register,
and write data to FIFO.

•

If UDC is set data of payload to FIFO or CPU set short packet
transfer in EOP register, EP0 bit of DATASET register is set.

•

UDC transfers data that is set to FIFO to host by IN token interrupts.

•

When CPU finish transaction, it writes “0” to EP0 bit of EOP register.

•

Change status stage in UDC.

Receive OUT token from host.
•

Return ACK to OUT token, and state change to IDLE in UDC.

•

Assert INT_STATUS interrupt to external.

These changing conditions are shown in Figure 3.16.10.
SETUP DATA0 ACK

IN

NAK

IN

DATA1 ACK

IN

DATA0 ACK

OUT DATA1 ACK

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR

bmRequestType register
bRequest register
wValue register
wIndex register
wLength register

EP0_FIFO (Rest data)

Setup Received register

EP0_FIFO (WR of payload)

Figure 3.16.10 The Control Flow in UDC (Control Read Transfer Type)

92CZ26A-433

EOP register

TMP92CZ26A
Stage change condition of control write transfer type
1.

2.

3.

Receive SETUP token from host.
•

Start setup stage in UDC.

•

Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.

•

Change data stage in UDC.

Receive OUT token from host.
•

CPU receive request from request register every INT_SETUP
interrupt.

•

Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.

•

Receive dataphase data normally, and set EP0 bit of DATASET
register.

•

CPU receives data in FIFO by setting DATASET.

•

CPU process receiving data by device request.

•

When CPU finish transaction, it writes “0” to EP0 bit of EOP register.

•

Change status stage in UDC.

Receive IN token from host.
•

Return data packet of 0 data to IN token, and state change to IDLE in
UDC.

•

Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.

These changing conditions are shown in Figure 3.16.11.
SETUP DATA0 ACK

OUT DATA1 ACK

OUT DATA0 NAK

OUT DATA0 ACK

IN

NAK

IN

DATA1 ACK

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR

bmRequestType register
bRequest register
wValue register
wIndex register
wLength register

EP0_FIFO (Rest data)

Setup Received register

EOP register

EP0_FIFO (RD of payload)

Figure 3.16.11 The Control Flow in UDC (Control Write Transfer Type)
In control read transfer type, transaction number of data stage do not always
accord with data number that is apppointed by device request. Therefore, CPU
can be processd by using INT_STATUSNAK interrupt. However, when class and
vendor request is used, be accord wLength value with data transfer number in
data phase. By this setting, using this interrupt is not need. Data stage data can
be confirmed by accessing DATASIZE register.

92CZ26A-434

TMP92CZ26A
Stage change condition of control write (no data stage) transfer type
1.

2.

Receive SETUP token from host
•

Start setup stage in UDC.

•

Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.

•

Change data stage in UDC.

Receive IN token from host
•

CPU receive request from request register every INT_SETUP
interrupt.

•

Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.

•

CPU process receiving data by device request.

•

When CPU finish transaction, it writes “0” to EP0 bit of EOP register.

•

Change status stage in UDC.

•

Return data packet of 0 data to IN token, and state change to IDLE in
UDC.

•

Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.

These change condition is Figure 3.16.12.
SETUP DATA0 ACK

IN

NAK

IN

DATA1 ACK

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR

bmRequestType register
bRequest register
wValue register
wINdex register
wLength register

Setup Received register

EOP register

Figure 3.16.12 The Control Flow in UDC (Control Write Transfer Type not Dataphase)

92CZ26A-435

TMP92CZ26A
(d) Isochronous transfer type
Isochronous transfer type is guaranteed transfer by data number that is limited
every each frame.
However, this transfer don’t retry when error occurs. Therefore, Isochronous
transfer type transfer only 2 phases (token, data) and it doesn’t use handshake
phase. And data PID for data phase is DATA0 always because of this transaction
doesn’t support toggle sequence. Therefore, UDC doesn’t confirm when data PID
is receiving mode.
Isochronous transfer type process data every frame. Therefore, all transaction
for finish transfer use receiving SOF token. UDC use FIFO that is divided into
two in Isochronous transfer type.
(d-1) Isochronous transmission mode
Isochronous transfer type format in transmitting is below transaction format.
•

Token: IN

•

Data: DATA0

Control flow
Isochronous transfer type is frame management. And data that write to
FIFO in endpoint is transmitted by IN token in next frame.
Below are two conditions in FIFO of Isochronous transmission mode
transferring.
X. FIFO for storing data that transmits to host in present frame
(DATASET register bit = 1)
Y. FIFO for storing data for transmitting host in next frame
(DATASET register bit = 0)
FIFO that is divided into two (packet A and packet B) conditions is whether
X condition or Y condition. Below flow is explained as X Condition (packet A),
Y Condition (packet B) in present frame.
X and Y conditions change one after the other by receiving SOF.
Below is control flow in UDC when receiving IN token.
1. Token packet is received and address endpoint number error is confirmed,
and it checks whether conform applicable endpoint transfer mode with
IN token. If it doesn’t conform, state return to IDLE.
2.

Condition of status register is confirmed.
•

3.

INVALID condition: State return to IDLE.

Data packet is generated.
Data packet is generated. At this point, data PID attach DATA0
always. Next, data is transferred from FIFO (X condition) of packet A in
UDC to SIE. And it generate DATA packet.

4.

CRC bit (counted transfer data of FIFO from first to last) is attached to
last.

92CZ26A-436

TMP92CZ26A
5.

Below is transaction when SOF token from host is received.
•

Change the packet A’s FIFO from X Condition to Y Condition. And
clear data.

•

Change the packet B from Y Condition to X Condition.

•

Set frame number to frame register.

•

Assert SOF and inform that frame is incremented to external.

•

DATASET register clears packet A bit and it sets packet B bit
arrangement loading in present frame.

•

Set STATUS to READY.

UDC finishes normally by above transaction.
Packet A’s FIFO can be received next data.
In renewed frame, Packet A’s FIFO interchange packet B’s FIFO, and
transaction is used same flow.
If SOF token is not received by error and so on, this data is lost because of
frame is not renewed. Nothing problem in receiving PID and if frame data is
received with CRC error, USB sets LOST to STATUS on FRAME register, and
frame number is not renewed. However, in this case, SOF is asserted and
FIFO condition is renewed. If SOF token is received without transmit and
transfer Isochronous in frame, UDC clears FIFO (X Condition) and sets
STATUS to FULL.

92CZ26A-437

TMP92CZ26A

IDLE
Receive IN token
Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error

Error

OK
Confirm Status
• Confirm STATUS register (status)

Invalid

OK
Generate DATA PID
• Attach DATA0
• Confirm DATASIZE register
OK

Receive SOF
without transmitting data

Clear X condition (A)
Set FULL to STATUS

Transmit data
Error transaction Set LOST to FRAME register
Not renew FRAME number
Assert SOF
Attach CRC

IDLE
ReceiveSOF
• FRAME noread
• BANK shift
Shift FIFO BANKs
every receive SOF

Not receive SOF
Not renewal frame number
loss data

BANK B transaction
• Assert SOF
• Clear transmitting FIFO BANK A in preceding frame
• Clear DATASET register’s BANK A bit
• Set DATASET register’s BANK B bit
(Finish a write in previous frame)
• Set STATUS to READY
• Wait data for transmitting next frame (BANK A)

BANK A transaction
• Assert SOF
• Clear transmitting FIFO BANK B in preceding
frame
• Clear DATASET register’s BANK B bit
• Set DATASET register’s BANK A bit
(Finish a write in previous frame)
• Set STATUS to READY

Figure 3.16.13 Control Flow in UDC (Isochronous transfer type (Transmission))

92CZ26A-438

TMP92CZ26A
(d-2) Isochronous receiving mode
Isochronous transfer type format in receiving is below transaction format.
•

Token: OUT

•

Data: DATA0

Control flow
Isochronous transfer type is frame management. And data that is written to
FIFO by OUT token is received to CPU in next frame.
Below are two conditions in FIFO of Isochronous receiving mode
transferring
X. FIFO for storing data that received from host in present frame
(DATASET register bit = 0)
Y. FIFO for storing data for transmitting host in previous frame
(DATASET register bit = 1)
FIFO that is divided into two (packet A and packet B) conditions is whether
X condition or Y condition. Below flow is explained as X Condition (packet A),
Y Condition (packet B) in present frame.
X and Y conditions change one after the other by receiving SOF.
Below is control flow in UDC when receiving OUT token.
All transaction is processed by hardware.
1.

Token packet is received and address endpoint number error is confirmed,
and it checks whether conform applicable endpoint transfer mode with
OUT token. If it doesn’t conform, state return to IDLE.

2.

Condition of status register is confirmed.
•

INVALID condition: State return to IDLE.

3.

Data packet is received.
Data is transferred from SIE into the UDC to packet A’s FIFO (X
Condition).

4.

After last data was transferred, and compare counted CRC with
transferred CRC. When transfer finish, result is reflected to STATUS.
However, data is stored FIFO, data number that packet A is received is
set to DATASIZE register of packet A.

5.

Below is transaction when SOF token from host is received.
•

Change the packet A’s FIFO from X Condition to Y Condition.

•

Change the packet B from Y Condition to X Condition, and clear data.
Prepare for next transfer.

•

Set frame number to frame register.

•

Assert SOF and inform that frame is incremented to external.

•

DATASET register set packet A bit and it clear packet B bit
arrangement loading in present frame.

•

If CRC comparison result agree it, DATAIN is set to STATUS. If
result doesn’t agree, RX_ERR is set to STATUS.

UDC finishes normally by above transaction.
CPU takes back packet A’s data.

92CZ26A-439

TMP92CZ26A
In renewed frame, Packet A’s FIFO interchange packet B’s FIFO, and
transaction is used same flow.
If SOF token is not received by error and so on, this data is lost because of
frame is not renewed. Nothing problem in receiving PID and if frame data is
received with CRC error, USB sets LOST to STATUS on FRAME register, and
frame number is not renewed. However, in this case, SOF is asserted and
FIFO condition is renewed. If SOF token is received without transmit and
transfer Isochronous in frame, UDC clears FIFO (X Condition) and sets
STATUS to FULL.
These are shown in Figure 3.16.14.

92CZ26A-440

TMP92CZ26A

IDLE
Receive OUT token
Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error

Error

OK
Invalid

Confirm Status
Confirming STATUS register (status)
OK
Confirm DATA PID
• Time out
• Error
OK

Error, time out exept data PID

Receive SOF nothing
transmitting data

Clear X Condition (A)

Error, receiving data more than payload.
Receiving data
• Error
• Receive receiving data
Error transaction
Set STATUS to RX ERR
BANK B transaction
• Assert SOF

IDLE

•
Receive SOF
• Frame no read
• Shift BANK

Set data size received preceding frame to
DATASIZE register in BANK A

•

Set BANK A bit in DATASET register

•

Clear BANK B bit in DATASET register

Shift FIFO BANK
every receive SOF

•

Set STATUS to DATAIN
(But if error generate, set RX_ERR)

Not receive SOF
Not renew frame number
loss data

BANK A transaction
• Assert SOF
•

Set data size received preceding frame to
DATASIZE register in BANK B

•

Set BANK B bit in DATASET register

•

Clear BANK A bit in DATASET register

•

Set STATUS to DATAIN
(But if error generate, set RX_ERR)

Figure 3.16.14 Control Flow in UDC (Isochronous transfer type (Receiving))

92CZ26A-441

TMP92CZ26A
3.16.7

Bus Interface and Access to FIFO
(1) CPU bus interface
UDC prepares two types of FIFO access, single packet and dual packet. In single
packet mode, FIFO capacity that is implemented by hardware is used as big FIFO. In
dual packet mode, FIFO capacity that is divided into two is used as two FIFOs. And it
uses as independent FIFO. Even if UDC is transmitting and receiving to USB host, it
can be used bus efficient by to possible load to FIFO.
But control transfer type receives only single packet mode.
Epx_SINGLE signal in dual packet mode must be fixed to “0”. If this signal is fixed to
“0”, FIFO register runs in single mode.
Sample: If you use endpoint 1 to dual packet of payload 64 bytes.
EP1_FIFO size

:

Prepare 128 bytes

EP1_SINGLE signal

:

Hold 0

EP1 Descriptor setting
Direction

:

Optional

Max payload size

:

64 bytes

Transfer mode

:

Optional

92CZ26A-442

TMP92CZ26A

(a) Single packet mode
This is data sequence of single packet mode when CPU bus interface is used.
Figure 3.16.15 is receiving sequence. Figure 3.16.16 is transmitting sequence.
Main of this chapter is access to FIFO. Data sequence with USB host refer to
chapter 5.
Endpoint 0 can’t be changed mode for exclusive single packet mode. Single
packet and dual packet of endpoint 1 to 3 can change by setting Epx_SINGLE
register. When transferring, don’t change packet.

Wait receiving data
IDLE
Receive valid data

DATASET = 0

DATASET register
• Set bit of EPx_D SET_A
• Assert EPx_DATASET signal
Interrupt by EPx_FULLA
Check DATASET register
DATASET register
• Check bit of EPx_DSET_A

DATASET = 1
SIZE register
• Size of SIZE_A_L confirmation

• Size of SIZE_A_H confirmation

RD receiving data of size in
appricable endpoint

• Clear receiving data in FIFO
• Clear applicable bit of DATASET
register

Figure 3.16.15 Receiving Sequence in Single Packet Mode

92CZ26A-443

TMP92CZ26A

Below is transmitting sequence in single packet mode.
Wait transmission event
IDLE
Transmission event
DATASET = 0
DATASET register
• Check bit of EPx_DSET_A
DATASET = 1
Distinction
transmitting

Wait transmitting
rest data
Transmitting number > payload

Transmitting number < payload

• WR of payload to applicable endpoint
• Total = Total − payload

• WR of transmitting number applicable endpoint
• Total = 0

If transmitting number reach to
payload, applicable bit of
DATASET register is set 1

If transmitting finish normally,
it clears applicable bit of DATASET.

EOP register
WR 0 to only bit of applicable endpoint

Wait transmitting
Wait IN token

Finish
transmitting

• Must access to EOP register in transmitting
short packet.
• This is used showing to the closing control
transfer type.
If you access to endpoint 0, you must to
access in closing control transfer type.

Figure 3.16.16 Transmitting Sequence in Single Packet Mode

92CZ26A-444

TMP92CZ26A

(b) Dual packet mode
In dual packet mode, FIFO is divided into A and B packet, it is controlled
according to priority in hardware. It can be performed at once, transmitting and
receiving data to USB host and exchanges to external of UDC. When it reads out
data from FIFO for receiving, confirm condition of two packets, and consider the
order of priority. If it has received data to two packets, UDC outputs from first
receiving data by FIFO that can be accessed are common in two packets.
DATASIZE register is prepared every packet A and packet B. First, CPU must
recognize data number of first receiving packet by PACKET_ACTIVE bit. If
PACKET_ACTIVE bit was set to 1, that packet is received, first. Packet A and
packet B set data turn about always.
Below is this sequence.

Wait receiving data
IDLE
Receiving valid data

DATASET register
• Set bit of EPx_DSET_A (B)
• Assert EPx_DATASET signal
DATASET = 0
Interrupt by EPx_FULL_A (B)
Check DATASET register
DATASET register
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
DATASET = 1
SIZE register
• Confirm Size of SIZE_A_L
• Confirm Size of SIZE_A_H
• Confirm Size of SIZE_B_L
• Confirm Size of SIZE_B_H

• Read size of receiving data from applicable endpoint
• There is below 3 cases by setting bit of DATASET
Only A: Read number of sizeA register
Only B: Read number of sizeB register
Both of A and B: Read number of sizeA + B register

• Clear receiving data in FIFO
• Clear applicable bit in DATASET register

Figure 3.16.17 Receiving Sequence in Dual Packet Mode

92CZ26A-445

TMP92CZ26A

When it writes data to FIFO in transmitting, confirm condition of two packets,
and consider the order of priority. When transfer data number is set, set to which
packet A and packet B, judge by PACKET_ACTIVE bit. Packet that bit is set to 0 is
bit that transfer now.
In transmitting and receiving, logic of PACKET_ACTIVE bit is reversed.
Therefore, please caution in transmitting.
Below is this sequence.
Wait transmitting event

IDLE
Interrupt by EPx_EMPTY_A (B)
Check DATASET register

Transmitting event

DATASET = 0

DATASETregister
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B

DATASET = 1
Transmittind
data distinction

Wait
transmitting
rest data

Transmitting number > payload × 2
• Write number of payload × 2 in
applicable endpoint
• Total = Total − payload × 2

EOP register

If transmitting number reach to
payload, DATASET set 1 to
applicable bit of register

If transmitting finish normally,
It clears applicable
bit of DATASET.

Transmitting number < payload × 2
• Write number of transmitting
number
• Total = 0

Write 0 to only bit of applicable
endpoint

Wait transmitting
Wait IN token

• Accessing to EOP register is needed in
transmitting short packet
• Control transfer type is only single mode

Finish
transmitting

Figure 3.16.18 Transmitting Sequence in Dual Packet Mode

92CZ26A-446

TMP92CZ26A

(c) Issuance of NULL packet
If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0
length is set to FIFO, and it can be transferred NULL packet to IN token.
But if it set NULL data to FIFO, it is valid only case of SET signal is L level
condition (case of FIFO is empty). If it answer to receiving IN token by using NULL
packet in a certain period, it is answered by keeping EPx_EOPB signal to L level.
However, if mode is dual packet mode, EPx_DATASET signal assert L level for
showing space of data. Therefore, data condition (both data have not data) cannot
be confirmed from external.
Note: NULL packet can be set also accessing EOP register.

Example:
NULL packet
completion of
transmitting

DATASET_A
DATASET_B
EPx_EOPB
NULL Neglect
A

NULL

NULL

NULL

NULL

B

A

B

A

(2) Interrupt control
Interrupt signal is prepared. This function use adept system.
Detail refers to 3.10.2 900/H1 CPU I/F.

92CZ26A-447

TMP92CZ26A
3.16.8

USB Device answer
USB controller (UDC) sets various register and initialization in UDC in detecting of
hardware reset, detecting of USB bus reset, and enumeration answer.
Below is explaining about each condition.
(1) Condition in detect in bus reset.
When UDC detects bus reset on USB signal line, it initializes internal register, and it
prepares enumeration operation from USB host. After detect in USB reset, UDC sets
ENDPOINT0 to control transfer type 8-byte payload and default address for using
default pipe. And endpoint except for it is prohibited.
Register name
ENDPOINT STATUS

Initial value
EP0

40H

Except for EP0

5CH

(2) Detail of STATUS register
Status register that was prepared every endpoint shows condition of every endpoint
in UDC.
Each condition affects transfer various USB. Condition changing in each transfer
type refers to chapter 5.
EPx_STATUS register value is 0 to 3, and it shows conditions of below. 0 to 4 are
result of various transfers. It can be confirmed previous result that is transferred to
endpoint by confirming from external of UDC.
0

READY

1

DATAIN

2

FULL

3

TX_ERR

4

RX_ERR

These conditions mean that endpoint operate normally. Meaning that is showed is
different every transfer mode. Therefore, please refer to below each transfer mode
column.

92CZ26A-448

TMP92CZ26A

ISO transfer mode
Below is transfer condition of frame before one. Receiving SOF renews this.
OUT (RX)

IN (TX)

Initial

READY

READY

Not transfer

READY

FULL

Finish normally

DATAIN

READY

Detect in error

RXERR

TXERR

Transfer mode of except ISO transfer
This is result previous transfer. When transfer finish, this is renewed.
OUT, SETUP

IN

Initial

READY

READY

Transfer finish normally

DATAIN

READY

Status stage finish

READY

READY

Transfer error

RXERR

TXERR

“Initial” is that renew RESET, USB reset, Current_Config register. In detect error, it
doesn’t generate EPx_DATASET except toggle transfer mode and Isochronous transfer
mode of interrupt.
5 to 7 in showing of status register mean that endpoint is special condition.
5

BUSY

BUSY generate only endpoint of control transfer. If UDC transfer in control writes transfer,
when CPU isn’t finishing enumeration transaction, and if it receive ID of status stage from
USB host, BUZY is set. STATUS is BUZY until CPU finishes enumeration transaction and
EP0 bit of EOP register is written 0 in UDC. If CPU enumeration transaction finishes and
EP0 bit of EOP register is written 0 and status stage from USB host finish normally, it
displays READY.
Please refer to 5.2.3 in chapter 5.

6

STALL

STALL show that endpoint is STALL condition.
This condition generate if it violates protocol or error in bus enumeration. If return endpoint
to condition that transfer can normally, device request of USB is needed. This request
returns condition normally. But control endpoint returns to condition normally by receiving
SETUP token. And it become to SETUP stage.

7

INVALID

This condition shows condition that endpoint can’t be used. UDC sets condition that isn’t
appointed in ENDPOINT to INVALID condition, and it ignores all of token for this endpoint.
In initializing, this condition generate always. When UDC detects hardware reset, it sets all
endpoint to INVALID condition. Next, if USB reset is received, endpoint 0 only is renewed to
READY. Other endpoint that is defined on disruptor, is renewed if SET_CONFIG request
finish normally.

92CZ26A-449

TMP92CZ26A
3.16.9

Power Management
USB controller (UDC) can be switched from optional resume condition (turn on the power
supply condition) to suspend (Suspension) condition, and it can be returned from suspends
condition to turn on the power supply condition.
This function can be set to low electricity consumption by operating CLK supplying for
UDC.
(1) Switch to suspend condition
USB host can be set USB device to suspend condition by keeping on IDLE state.
UDC switches to suspend condition by below process.
•

UDC switches to suspend condition if it detect IDLE state of more than 3 ms on
USB signal. At this point, set SUSPEND bit of STATUS register to “1”.

•

After switch to suspend condition, if besides pass away 2 ms, UDC renews
USBINTFR1 from “0” to “1”. After USBINTFR1
was renewed from “0” to “1”, set USBCR1 to “0”, and be stopped
supply of CLK (USB_CLK).
In this condition, all register value into the UDC is kept. However, accessing from
external can’t be accessed except reading of STATUS register, Current_Config
register, and USBINTFR1, USBINTFR2, USBINTMR1, USBINTMR2 and
USBCR1

(2) Return from suspend condition by host resume
Way to UDC change from suspend condition to resume condition have two type;
resume condition output from USB host and remote wakeup.
When activity of bus on USB signal restore by resume condition output from USB,
UDC reset SUSPEND output from “1” to “0”, and it resets SUSPEND bit of STATUS
register from “0”. And it resumed system. Resume condition output from this host keep
on no less than during 10 ms. Therefore effective protocol occurring on USB signal line
is after pass away this time.
(3) Return from suspend condition by remote wakeup
Remote wakeup is system for prompt resume from suspending USB device to USB
host. Remote wakeup isn’t supported by condition. And remote wakeup is limited using
from USB host by bus enumeration.
Function of remote wakeup in UDC can be used when it is permitted.
Setting remote wakeup by bus can be confirmed bit7 of Current_Config register.
When this bit is “1”, remote wakeup can be used. Remote wakeup doesn’t disable in
this bit. Therefore, if this bit show disable, must not set remote wakeup. If it fill the
conditions, output resume condition output to USB host by writing
USBCR1 from “1” to “0” of UDC in suspend condition. And it prompts
resume from UDC to host. After UDC changes to suspend condition, during 2 ms ignore
WAKEUP
input.
Therefore,
remote
wakeup
become
effective
by
USBINTFR1 was set to “1”.

92CZ26A-450

TMP92CZ26A
(4) Low power consumption by control of CLK input signal
When UDC switches to suspend condition, it stops CLK and switches to low power
consumption condition. But as system, this function enables besides low power
consumption by stopping source of CLK that is supplied from external. CLK that
supply to UDC can be controlled clock supply to USB by using
USBINTFR1 and .
If UDC switches to suspend condition, USBINTFR1 is set to “1”, and
 is set to “1”. After confirmation, stop supply CLK (USBCLK) by
setting “0” to USBCR1. If SUSPEND signal is set to “0” by resuming from
host, supply normal CLK to UDC within 3 ms.
When it uses remote wakeup, supplying stable CLK to UDC before using is needed.
When it uses doublers circuit as generation source, above control is needed.

92CZ26A-451

TMP92CZ26A
3.16.10 Supplement
(1) External access flow to USB communication
a)
SETUP DATA0 ACK

Normally movement
IN

NAK

IN

DATA1 ACK

IN

DATA0 ACK

OUT DATA1 ACK

IN

DATA1 ACK

IN

DATA0 ACK

SETUP DATA0 ACK

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
EP0 FIFO access
Request access
Setup Received access
EOP register access

b)
SETUP DATA0 ACK

Stage error
IN

NAK

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
EP0 FIFO access
Request access
Setup Received access
EOP register access
Stage error bit

Normal

Stage error

STATUS register read

92CZ26A-452

Normal

TMP92CZ26A

(2) Register beginning value
Register Name

Beginning Value Beginning Value
OUTSIDE Reset

USB_RESET

bmRequestType

0x00

0x00

bRequest

0x00

0x00

wValue_L

0x00

wValue_H

0x00

wIndex_L

0x00

wIndex_H

0x00

wLength_L

0x00

wLength_H

0x00

0x00

Register Name

Beginning Value Beginning Value
OUTSIDE Reset

USB_RESET

INT control

0x00

0x00

USBBUFF_TEST

0x00

Hold

0x00

USB state

0x01

0x01

0x00

EPx_MODE

0x00

0x00

0x00

EPx_STATUS

0x1C

0x1C

0x00

EPx_SIZE_L_A

0x88

0x88

0x00

EPx_SIZE _L_B

0x08

0x08

EPx_SIZE_H_A

0x00

0x00

Current_Config

0x00

0x00

EPx_SIZE_H_B

0x00

0x00

Standard request

0x00

0x00

FRAME_L

0x00

0x00

Request

0x00

0x00

FRAME_H

0x02

0x02

DATASET

0x00

0x00

ADRESS

0x00

0x00

Port Status

0x18

Hold

EPx_SINGLE

0x00

Hold

Standard request mode

0x00

Hold

EPx_BCS

0x00

Hold

Request mode

0x00

Hold

ID_STATE

0x01

0x00

Note 1: Above initial value is value that is initialized by external reset, USB_RESET. This value may differs display
value by various condition.
Please refer to register configure of chapter 2.
Note 2: Initial value of EPx_SIZE_L_A, EPx_SIZE_L_B, EPx_SIZE_H_A, EPx_SIZE_H_B registers differ by size of
FIFO.
EP0_STATUS register is initialized to 0x00 after received USB_RESET.
Note 3: Initial value of ID_STATE register is initialized by external reset, BRESET. When USB_RESET signal is
received from host, it isinitialized to 0x00.

92CZ26A-453

TMP92CZ26A

(3) USB control flow chart
(a) Transaction for standard request (Outline flowchart (Example))
USB interrupt

Call USBINT0 function

Judge Interrupt

SETUP
transaction

ENDPOINT 0
transaction

STATUS
transaction

92CZ26A-454

STATUS NAK
transaction

ENDPOINT 1
transaction

TMP92CZ26A

(b) Condition change

Turn on power supply

Initialization transaction

Normal finish/No transaction
Waiting USB
interrupt condition

Transmit Request
error/
S

Receive USB token

Transaction error/
Transmit STALL
Request
transaction
condition

92CZ26A-455

TMP92CZ26A

(c) Device request and various request judgment
Start

Get request data

Judge Request

Standard request
CLEAR_FEATURE
SET_FEATURE
GET_STATUS
SET_ADDRESS
SET_CONFIGURATION
GET_CONFIGURATION
SET_INTERFACE
GET_INTERFACE
SYNCH_FRAME
GET_DESCRIPTOR

Class request
* Error for not
support

Vendor request
* Error for not
support

End

92CZ26A-456

Error transaction

TMP92CZ26A

(c-1)

CLEAR_FEATURE request transaction
Start

No
Is request right？
Yes
Judge Recipient

Device
Disable remote
wakeup setting

Endpoint
Clear stall setting

Finish transaction

End

92CZ26A-457

Error transaction

TMP92CZ26A

(c-2)

SET_FEATURE request transaction

Start

No
Is request right?
Yes
Judge Recipient

Device
Enable remote
wakeup setting

Endpoint
Set stall

Finish transaction

End

92CZ26A-458

Error transaction

TMP92CZ26A

(c-3)

GET_STATUS request transaction
Start

No
Is request right?
Yes
Judge Recipient

Device
Set self power
supply information

Interface
Set 0 x 0 0 data of
2 bytes

Endpoint
Set stall information

Finish transaction

End

92CZ26A-459

Error transaction

TMP92CZ26A

(c-4)

SET_CONFIGRATION request transaction
Start

No
Is request right？
Yes
No
Is EP0 stall？
Yes
Is assignment
value valid？

No

Yes
No
Is state valid？
Yes
Set assignment
configuration value

Clear stall flag

Finish transaction

End

92CZ26A-460

Error transaction

TMP92CZ26A

(c-5)

GET_CONFIGRATION request transaction

Start

No
Is request right?
Yes
No
Is state valid?
Yes
Set present configuraion
value

Finish transaction

End

92CZ26A-461

Error transaction

TMP92CZ26A

(c-6)

SET_INTERFACE request transaction
Start

No
Is request right?
Yes
No
Is EP0 stall?
Yes
Is assignment
value valid?

No

Yes
No
Is state valid?
Yes
Set each endpoint to
assignmented configuration
value.

Finish transaction

End

92CZ26A-462

Error transaction

TMP92CZ26A

(c-7)

SYNCH_FRAME request transaction

Start

No
Is request right?
Yes
No
Is EP0 stall?
Yes
Is assignment
value valid?

No

Yes
No
Is state valid?
Yes
Set altrenate setting value
to present transmitting data.

Finish transaction

End

92CZ26A-463

Error transaction

TMP92CZ26A

(c-8)

SYNCH_FRAME request transaction
Start

No
Is request right?
Yes
Error transaction

Finish transaction

End

(c-9)

SET_DESCRIPTOR request transaction
Start

No
Is request right?
Yes
Finish transaction

End

92CZ26A-464

Error transaction

TMP92CZ26A

(c-10) GET_DESCRIPTOR request transaction
Start

No
Is request right?
Yes
No
Is EP0 stall?
Yes
Is assignment
value valid?

No

Yes
No
Is state valid?
Yes

Device
Set device
descriptor
information.

Config
Set config
descriptor
information.

Write information to
FIFO[EP0_fifowrite ( )]

End

92CZ26A-465

String
Set string
descriptor
information.

Error transaction

TMP92CZ26A

(c-11) Data read transaction to FIFO by EP0
Start

No
Is request right?
Yes
Stage information = data stage

Read data from FIFO

STATUS_NAK interrupt enable

STATUS_NAK interrupt disable

Data read from FIFO

Stage information = stataus stage

All data number
renew transfer address

Finish transaction

End

92CZ26A-466

TMP92CZ26A

(c-12) Data write transaction to FIFO by EP0
Start

No
Is request right?
Yes

Set transmitting size to SIZE
register

Stage information = data stage
Write data to FIFO
STATUS_NAK interrupt enable
Is data number decided
time of payload size?
Set data size to SIZE register
Yes
STATUS_ NAK interrupt disable
Write data to FIFO
Stage information = status stage
All data number
renew former transfer address

End

92CZ26A-467

Finish transaction

No

TMP92CZ26A

(c-13) Beginning setting transaction of microcontroller
Start

Interrupt disable

Set Stack point

Set Various interrupt

Clear vRAM

UDC initialization[UDC_INIT]

USB farm initialization[USB_INIT]

Interrupt enable

Main transaction[main ( )]

(c-14) Begining setting transaction of UDC
Start

USBC reset transaction

End

92CZ26A-468

TMP92CZ26A

(c-15) Beginning transaction of USB farm changing number
Start

Renew stage information
Renew current information
Renew support information

Invalid EP except EP0

Various flag Intialization

End

(c-16) Set DEVICE_ID data to DEVICE_ID of UDC
Start

Set DEVICE_ID data to
DEVICE_ID_RAM area.

End

92CZ26A-469

TMP92CZ26A

(c-17) Descriptor data set transaction
Start

Set descriptor data to
DESC_RAM area.

End

(c-18) USB interrupt transaction
Start

Read INT register

Judge Interrupt

Setup interrupt
transaction
[Proc_SETUPINT]

Endpoint 0 interrupt
[Proc_ ENDPOINT]

Status_NAK interrupt
[Proc_STATUSNAKINT]

Judge Request transaction
[STATUS_judge]

End

92CZ26A-470

Status_interrupt
[Proc_STATUSINT]

Others
Error
transaction

TMP92CZ26A

(c-19) Dummy function for not using maskable interrupts.
•

Transaction performs nothing, therefore outline flow is skipping.

(c-20) Request judgment transaction. If transaction result is error, it puts STALL
command.

Start

No
Is request right?
Yes

Error transaction

End

(c-21) SETUP stage transaction
Start

No
Is request right?
Yes
Stage information = SETUP stage

Request transaction

End

92CZ26A-471

TMP92CZ26A

(c-22) Perform endpoint 0 transaction in except for SETUP stage.
Start

Judge Stage

Data stage
GET system request
[EP0_fifowrite]
SET system request
[EP0_fiforead]

Status stage
Finish normally

Others
Error transaction

End

(c-23) Status stage interrupt transaction
Start

No
Status stage?
Yes
Normal finish
transaction

End

92CZ26A-472

Error transaction

TMP92CZ26A

(c-24) STATUS_NAK interrupt transaction
Start

Data stage?

No

Yes
Normal finish
transaction

Error transaction

End

(c-25) This transaction is no transaction by USB transaction perform in
interrupts.

Start

92CZ26A-473

TMP92CZ26A

(c-26) Getting descriptor information (reration of standard request)

Start

Get device information
on descriptor

Is config within
support?

No

Yes
Get config information
on descriptor

Interface is within
support in config present.

Yes
Get device information on
descriptor

Increment count to next config
information

End

92CZ26A-474

No

TMP92CZ26A
3.16.11 Points to Note and Restrictions
1.

Limitation of writing to COMMAND register in special timing
When “STALL” command is issued, ENDPOINT status might be shift to “INVALID”.
To avoid this problem, keep the below routine.
a.

BULK (IN/OUT)
In case issue STALL command to endpoint in BULK transfer, be sure to issue
STALL command after stop RD/WR accessing to endpoint; that is UDC returns
NAK in the response of token from host. INT_EPxNAK should be used to detect
NAK transmit.

b.

CONTROL OUT with data stage (software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, access to SetupReceived register. After that, issue STALL
command after detecting INT_ENDPOINT0 interrupt.

c.

CONTROL OUT without data stage (software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, issue STALL command before access to eop register.

d.

CONTROL IN(software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, issue STALL command before set the first transmit data
to host.

2.

Limitation of EPx_STATUS when execute USB_RESET command
EPx_STATUS may indicates different condition, if execute
USB_RESET command to the endpoint in the process of token. To avoid this
phenomenon, do not RESET the endpoint in transferring. (It is available in the process
of request that needs USB_RESET to that endpoint.)

92CZ26A-475

TMP92CZ26A

3.

When generating toggle error of device controller
a.

UDC operation
If USB host fail to receive ACK transmitted from UDC in OUT transfer, USB
host transmits the same data to UDC again. When the FIFO is available to receive,
UDC detects toggle error because of detecting the same data(having the same
toggle as the data which is received just before) and returns ACK. UDC rejects it
because the data have already received normally. While, if FIFO is not available,
UDC returns NAK and informs USB host that is unable to receive.

4.

If using USB device controller in TMP92CZ26A, the crystal oscillator (USB standard ≤
10 MHz±2500ppm) is recommended. And in this case, the stage of external hub can be
used until max 3 stages by the precision of this USB device controller and the internal
clock. If USB compliance (USB logo) is needed, the 5 stages connection is needed for
external hub. And it is needed that input 48MHz clock from X1USB pin (USB standard
≤ ±2500ppm.)

92CZ26A-476

TMP92CZ26A

3.17

SPIC (SPI Controller)
SPIC is a Serial Peripheral Interface Controller that supports only master mode.
It can be connected to SD card, MMC (Multi Media Card) etc. in SPI mode.
The features are as follows;
1) 32 byte –FIFO (Transmit / Receive)
2) Generate CRC7 and CRC16 (Transmit / Receive data)
3) Baud Rate: 20Mbps max
4) Connect several SD cards and MMC. (Use other output port for /SPCS pin as /CS)
5) Use as general clock synchronous SIO.
MSB/LSB-first, 8/16bit data length, rising/falling edge
6) 2 Interrupts: INTSPITX (Trans interruption), INTSPIRX (receive interruption)
Select Read/Mask for interrupts: RFUL, TEMP, REND and TEND

92CZ26A-477

TMP92CZ26A

3.17.1 Block diagram
It shows block diagram and connection to SD card in Figure 3.17.1.
SD Card

SPIC (SPI Controller)
SPCLK 100KΩ

Baud rate
Generator

16bit

16bit

8×32

TX shift register

8×32

RX shift register

Transmitt,Receive ontroller

TX FIFO

CS

RX FIFO

SPIMD/CT
SPITD

16bit

100KΩ

SPDO

SPDI

100KΩ
DI

100KΩ
DO

SPIIE

16bit

SPCS

SPICR

Internal data bus

16bit

SPIRD

16bit

SCLK

SPIST

fSYS

Port

INTSPI

WP (Write Protect)
INTn

CD (Card Detect)

Note1: SPCLK, SPCS , SPDO and SPDI pins are set to input port (Port PR3, PR2, PR1, PR0) by reset.
These signals are needed pull-up resister to fix voltage level, could you adjust resistance value for your final
set.
Note2: Please use general input port or interrupt signal for WP (Write Protect) and CD (Card Detect).

Figure 3.17.1 Block diagram and Connection example

92CZ26A-478

TMP92CZ26A

3.17.2 SFR
SFR of SPIC are as follows.These area connected to CPU with 16 bit data bus.
(1) SPIMD(SPI Mode setting register)
SPIMD register is for operation mode or clock etc.
SPIMD Register

7
bit Symbol
SPIMD
(820H) Read/Write
After Reset
Prohibit to
Read
Modify
Write

SWRST

XEN

W

R/W

0

0

5

4

3

Reset
Function

CLKSEL2

CLKSEL1

CLKSEL0

15

14

13

LOOPBACK

MSB1ST

DOSTAT

12

11

10

TCPOL

RCPOL

R/W
0

0

001: fSYS/2
010: fSYS/3
011: fSYS/4

0: don’t care 1: enable

0

101: fSYS/16
110: fSYS/64
111: fSYS/256

9

8

TDINV

RDINV

0

0

R/W

1

1

0

0

Invert data

LOOPBACK

Start bit for

SPDO pin

Synchronous Synchronous Invert data

Test mode

Transmit /

state

clock edge

clock edge

During

During

(no transmit)

during

during

transmitting

receiving

0:LSB

0:fixed to ”0”

transmitting

receiving

0: disable

0: disable

1:MSB

1:fixed to ”1”

0: fall

0: fall

1: enable

1: enable

1: rise

1: rise

0:disbale

Function

0

Select Baud Rate(Note1)
000:Reserved
100:fSYS/8

1: Reset

After Reset

1

1

0: disable

Read/Write

2

R/W

Software SYSCK

bit Symbol
(821H)

6

1:enable

Receive

Note: Maximum speed of this SD card is 20Mbps in SD card SPI mode.
When setting the baud rates, select less than 20Mbps according to the operation speed of CPU (fSYS).

Figure 3.17.2 SPIMD register
(a) 
Because Internal SPDO can be input to internal SPDI, it can be used as test.
Set =1 and =1, outputs clock from SPCLK pin regardless of
operation of transmit/receive.
Please change the setting when transmitting/receiving is not in operation.
SPDO pin

Transmitting data

B
Receiving data

Y

A

SPDI pin

SPIMD

Figure 3.17.3  Function

(b) 
Select the start bit of transmit/receive data
Please don't change the setting of this register when transmitting/receiving is in
operation.

92CZ26A-479

TMP92CZ26A
(c) 
Set the status of SPDO pin when data communication is not operating (after
transmitting or during receiving).
Please don't change the setting of this register when transmitting/receiving is in
operation.
(d) 
Select the edge of synchronous clock.
Please change the setting when bit is “0”. And set the same value as .

SPCLK pin ( = “0”)
SPCLK pin (= “1”)
SPDO pin

MSB

LSB
Bit0

Bit1

Bit2

Bit3 Bit4

Bit7

Figure 3.17.4  Register Function
(e) 
Select the edge of synchronous clock during receiving.
Please change the setting during SPIMD= “0”. And set the same value as
.

SPCLK pin (=”0”)
SPCLK pin (=”1”)
SPDI pin

MSB

LSB
Bit0

Bit1

Bit2

Bit3 Bit4

Figure 3.17.5 Register Function
(f) 
Select logical invert/no invert when outputs transmitted data from SPDO pin.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(g) 
Select logical invert/no invert for received data from SPDI pin.
Please don't change the setting of this register when transmitting/receiving is in
operation.

92CZ26A-480

TMP92CZ26A
(h) 
This bit is for Software reset of transmit/receive FIFO pointer. Write SPICT to
“0” at ="1", and stop transmitting. After that, by writing  to “1”, the
read/write pointer of transmit/receive FIFO are initialized.
When writing SPICT to “0”, stops transmission after the UNIT data in
transmitting is transmitted. Write  to“1”, the data in the transmit FIFO
becomes to invalid.
The data in the transmit shift register is cleared simultaneously. Therefore, the data is
not output if transmit is restarted after executed software reset.
Please do not write  to “1” during transmission. In case of receiving, the
received data in the receive FIFO buffer becomes invalid. However, the UNIT data in
receiving is loaded to receive FIFO as valid data.
In case of sequential receive, receiving operates sequentially even if the data of receive
buffer becomes invalid. Therefore, stops receive operation by writing
SPICT=“0”after finishing to receive all the data in receiving. And all the receive
operation is stopped by writing =“1”after checking no UNIT data in receiving
(namely after REND interrupt or the time to receive 1UNIT).
During receiving, do not write =“1”.
Software reset can be executed by 1 shot operation; writing =“1” (needless to
write =“0”). Writing =“1”and =“1”simultaneously is permitted.
(i) 
Enable/disable control of root clock this SPI controller.
(j) 
Select baud rate. Baud rate is created from fSYS and settings are in under table.
Please change the setting when transmitting/receiving are not in operation.

Note: When setting the baud rates, select less than 20Mbps according to the operation speed of CPU (fSYS).

Table 3.17.1 Example of Baud Rate
Baud Rate [Mbps]
fSYS =60MHz

fSYS =80MHz

fSYS/2

−

−

fSYS /3

20

−

fSYS /4

15

20

fSYS /8

7.5

10

fSYS /16

3.75

5



fSYS /64

0.9375

1.25

fSYS /256

0.234375

0.3125

92CZ26A-481

TMP92CZ26A

(2) SPICT(SPI Control Register)
SPICT register is for data length or CRC etc.
SPICT Register

SPICT
(822H)

bit Symbol

7

6

5

4

3

2

1

0

CEN

SPCS_B

UNIT16

TXMOD

TXE

FDPXE

RXMOD

RXE

R/W

R/W

R/W

R/W

R/W

0

0

0

0

Read/Write
After Reset

R/W
0

1

communication /SPCS pin

Function

0
Data length

control

0: output “0” 0: 8bit

0: disable

1: output “1” 1: 16bit

1: enable

Receive

control
0: disable

0: disable

0: disable

Transmit

mode
0: UNIT

1:Sequential 1: enable

15
(823H)

14

13

bit Symbol

CRC16_7_B CRCRX_TX_B CRCRESET_B

Read/Write

R/W

After Reset

0

0
CRC data

CRC

0: CRC7

0: Transmit

calculate

1: CRC16

1: receive

register

Function

12

11

0

CRC select

0

Alignment in Receive
Full duplex
Mode

Transmit

0:Reset
1:Release
Reset

Figure 3.17.6 SPICT Register
(a) 
Select CRC7 or CRC16 to calculate.
(b) 
Select input data to CRC calculation circuit.
(c) 
Initialize CRC calculate register.

92CZ26A-482

1: enable

10

0: UNIT

control

1:Sequential 1: enable

9

8

TMP92CZ26A

The process that calculating CRC16 of transmits data and sending CRC next to
transmit data is explained as follows.
(1) Set SPICT  to select CRC7 or CRC16 and  to select
calculating data.
(2) To reset SPICR register, write “1” after write to "0".
(3) Write transmit data to SPITD register, and wait for finish transmission all data.
(4) Read SPICR register, and obtain the result of CRC calculation.
(5) Transmit CRC which is obtained in (4) by the same way as (3).
CRC calculation of receive data is the same process.

Start

="1",
="0"

="0"→"1"

Transmit all data

Read CRC from SPICR
Write CRC in SPITD and send

Finish

Figure 3.17.7 Flow chart of CRC calculation process

92CZ26A-483

TMP92CZ26A

(d) 
Select enable/disable of the pin for SD card or MMC.
When the card isn’t inserted or no-power supply to DVcc, penetrated current is flowed
because SPDI pin becomes floating. In addition, current is flowed to the card
because SPCS , SPCLK and SPDO pin output “1”. This register can avoid these matters.

If write  to “0” with PRCR and PRFC selecting SPCS , SPCLK, SPDO and SPDI
signal, SPDI pin is prohibited to input (avoiding penetrated current) and SPCS , SPCLK,
SPDO pin become high impedance.
Please write =“1” after card is inserted, supply power to Vcc of card and supply
clock to this circuit (SPIMD=“1”).
(e) 
Set the value that outputs to SPCS pin.
(f) 
Select the length of transmit/receive data. Data length is described as UNIT downward.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(g) 
Select whether using alignment function for transmit/receive per UNIT during full
duplex.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(h)
Select UNIT/Sequential transmission. During transmission, it is prohibited to change
the transmission mode; Sequential→UNIT, UNIT → Sequential.
For UNIT transmit, the data in transmit FIFO is invalid. TEMP interrupt generates
when the data is shifted from transmit data register (SPITD) to transmit buffer.
For sequential transmit, 32 bytes of the data in FIFO is valid. TEMP interrupt
generates when the space of the FIFO becomes 16 bytes size and 32 bytes.
(i)
Set enable/disable of transmit. Transmission starts when set to “1”after writing
transmit data to transmit FIFO or set to “1” before writing transmit data to transmit
FIFO. During transmission, it is possible to change enable/disable. If cleared to “0” during
transmission, transmission is stopped after finishing transmitting the UNIT data in
transmitting.
(j)
Select UNIT/Sequential receives. During receiving, it is prohibited to change receiving
mode; Sequential→UNIT, UNIT → Sequential
In UNIT receive mode, receive FIFO is invalid and RFUL interrupt generates when the
received data is shifted from receive buffer to receive data register (SPIRD).
In sequential receive mode, receive FIFO is valid and RFUL interrupt generates when
16 and 32 bytes of the data is loaded to the FIFO.

92CZ26A-484

TMP92CZ26A
(k) 
In UNIT receive mode, receives only 1 UNIT data by writing “1”.
When reading receive data register (SPIRD) with the condition “1”, receives one time
additionally.
In sequential mode, receiving is kept sequentially until FIFO becomes full by writing
“1”. During receiving, it is possible to change enable/disable. If writing “0”during
receiving, receiving is stopped after finishing receiving the UNIT data in receiving.
[Transmit/Receive operation mode]
This SPI Controller supports 6 operations as below.
These are selected in , , , ,  registers.

Table 3.17.2 Transmit/Receive operation mode
Operation mode

Register setting

Description

    
(1) UNIT transmit

0

0

1

x

x

Transmit written data per UNIT

(2) Sequential transmit

0

1

1

x

x

Transmit written data in FIFO sequentially

(3) UNIT receive

0

x

x

0

1

Receive only 1 UNIT of data

(4) Sequential receive

0

x

x

1

1

Receive automatically if buffer has space

(5) UNIT transmit/receive

1

0

1

0

1

Transmit/receive 1 UNIT of data with aligning

(6)Sequential transmit/receive

1

1

1

1

1

transmit/receive data per each UNIT
Transmit/receive

sequentially with

transmit/receive data per each UNIT

x: don’t care

92CZ26A-485

aligning

TMP92CZ26A

Difference points between UNIT transmission and Sequential transmission
UNIT transmit mode can be selected by writing SPICT= “0”.
The transmit FIFO is invalid in UNIT transmit mode. The UNIT transmit starts when writing
UNIT data with the condition SPICT= “1” or writing SPICT= “1” after writing
1UNIT data in the transmit buffer. During transmission, it is prohibited to change the
transmission mode;
For UNIT transmit, TEMP interrupt generates when the data is shifted from transmit data
register (SPITD) to transmit buffer. TEND interrupt generates when the UNIT transmit is
finished.
Sequential transmit mode can be selected by writing SPICT= “1”. 32bytes of the
FIFO becomes valid in sequential transmit mode. Writing data in transmit FIFO every 16
bytes is always needed. If writing other than 16 bytes, TEMP interrupt does not generate
normally.
The written transmit data is shifted by turn with the condition SPICT= “1”. Or shifted
by turn when writing SPICT= “1” after writing data in transmit FIFO.
The transmission is kept executing as long as data exists. Therefore the transmission can be
kept sequentially while the transmit FIFO (32 bytes size) has no space. During transmission,
it is prohibited to change;
Sequential transmit→UNIT transmit
UNIT transmit → Sequential transmit
During transmission, it is possible to change enable/disable. If writing SPICT= “0”
during transmission, transmission is stopped after finishing to transmit the UNIT data in
transmitting.
TEMP interrupt generates when the space of FIFO becomes 16 and 32 bytes size. TEND
interrupt generates when the UNIT transmit is finished.

92CZ26A-486

TMP92CZ26A

Difference points between UNIT receive and Sequential receive
UNIT receive is the mode that receiving only 1 UNIT data. UNIT receive mode can be
selected by writing SPICT= “0”.
The receive FIFO is invalid in the UNIT receive mode. By writing SPICT= “1”,
receives 1UNIT data, loads received data in receive data register (SPIRD) and then stop
receiving. Reading (SPIRD) register should be executed after writing SPICT= “0”. If
reading (SPIRD) register with the condition SPICT= “1” 1 UNIT data is received again.
During receiving, it is prohibited to change;
Sequential receive→UNIT receive
UNIT receive → Sequential receive
RFUL and REND interrupts generate when UNIT receiving is finished.
Sequential receive is the mode that receiving the data sequentially and automatically when
receive FIFO has space. Sequential receive is selected by writing SPICT= “1”.
The 32 bytes size of receive FIFO becomes valid in sequential receive mode. Reading the data
in receive FIFO every 16 bytes is always needed. If reading other than 16 bytes, RFUL
interrupt does not generate normally.
Received data is loaded to receive FIFO by writing SPICT= “1”.
Receiving next data is kept automatically unless data receive FIFO becomes full (32bytes).
Therefore receiving is not stopped every UNIT but kept sequentially. During receiving, it is
prohibited to change receiving mode;
If writing SPICT= “0” during receiving, receiving is stopped after finishing to receive
the UNIT data in receiving.
RFUL interrupt generates when 16 and 32 bytes of the data is loaded to the FIFO. REND
interrupt generates when receiving 32 bytes size of the data is finished.

92CZ26A-487

TMP92CZ26A
Transmit/Receive
When transmitting or receiving, write = “1”
Writing = “1” first, and SPICT= “1” and keep waiting state for starting
UNIT receiving. When writing SPICT= “1”after = “1”, receiving does not
start right away. This is because the data to transmit at the same time has not been prepared.
Transmit/receive start when writing the data to (SPITD) register with the condition =
“1”.
The waveform of each transmit/receive operation is as follows;

Start
receiving

Start
transmitting

Transmitter
SPCLK output
SPDI input

LS
Bit1

Bit2

Bit1

Bit2

Bit4

Receiver
SPCLK output
SPDO output

LSB
Bit0

Bit3

Bit4

Bit5

Bit6

Bit7

Note: If transmit/receive are not operated simultaneously, please communicate with the condition =”0”.

Figure 3.17.8 Transmit/Receive

92CZ26A-488

TMP92CZ26A

(3) Interrupt
In INTC (interrupt controller), interrupt is divided roughly into 2 kinds; transmit interrupt
(INTSPITX) and receive interrupt (INTSPIRX). Besides in this SPI circuit, there are 4 kinds of
interrupts; 2 transmit interrupts 2 receive interrupts.
・ Transmit interrupt

TEMP (Empty interrupt of transmit FIFO) and TEND (End interrupt of transmit).
As for TEMP interrupt, the timing of generation differs according to transmit mode;
UNIT/sequential.
If transmit is sequencial, writing the data to transmit FIFO every 16 bytes is always needed. If
writing other than 16 bytes, TEMP interrupt does not generate normally.
UNIT transmit mode
TEMP interrupt generates when the data is shift from transmit data register (SPITD) to
transmit buffer since transmit FIFO is invalid.
TEND interrupt generates when the last UNIT transmit is finished (the falling edge of the
last bit clock) with the FIFO empty.
Sequential transmit mode
TEMP interrupt generates from 2 phenomenon. One is when the space of FIFO becomes 16
bytes size and the other 32 bytes size.
TEND interrupt generates when the last UNIT transmit is finished (the falling edge of the
last bit clock) with the FIFO empty.
・ Receive interrupt

RFUL (Receive FIFO interrupt) and REND (Receive finish interrupt).
As for RFUL interrupt, the timing of generation differs according to receive mode;
UNIT/sequential.
If transmit is sequencial, reading the data from receive FIFO every 16 bytes is always needed.
If reading other than 16 bytes, RFUL interrupt does not generate normally.
UNIT receive
RFUL interrupt generates the same timing as REND since the receive FIFO becomes invalid.
RFUL and REND interrupt generate when the data is shifted from receive buffer to receive data
register (SPIRD).
Sequential receive
RFUL interrupt generates from 2 phenomenon. One is when 16 bytes size of data is loaded to
receive FIFO and the other 32 bytes size of data.
REND interrupt generates when the receive FIFO becomes full (32bytes).

92CZ26A-489

TMP92CZ26A

(3-1) SPIST (SPI Status Register)
SPIST shows 4 statuses.
SPIST Register

7
SPIST
(824H)

6

5

4

3

bit Symbol

TEMP

Read/Write

R

After reset

2

1

0

TEND

REND
R

1

Function

1

0

Transmit FIFO

Transmit

Receive

Status

Status

Status

0: during

0: during

0: no space

transmission

receiving

1: having

or having

or not having

transmission

receiving

space

data

data

1: finish

1: finish or not
having space

15

14

13

12

11

10

9

8

bit Symbol
(825H)

Read/Write
After reset

Function

Figure 3.17.9 SPIST Register

(a) 
For UNIT transmission, it is cleared to “0” when valid data exists in transmit register
(SPITD). It is set to “1” when no valid data exists.
For Sequential transmission, it is set to “1” when no valid data exists in transmit buffer.
(b) 
This bit is cleared to “0” when valid data to transmit exists in the shift register/FIFO buffer
or when transmission. It is set to “1” when no valid data exists in the transmit data
register/FIFO buffer and finish transmitting all the data.
(c) 
For UNIT receiving, it is set to “1” when finish receiving and valid data was loaded to
receive data register (when valid data exists). It is cleared to “0” when no valid data exists
in receive register (SPIRD). It is set to “1” when no valid data exists or during receiving.
For Sequential receiving, it is set to “1” when valid data of 32 bytes exist in receive FIFO
after finish receiving last data. It is cleared to “0” even if having space of 1byte.
RFUL flag does not exist because meaning is the same with REND flag.

92CZ26A-490

TMP92CZ26A

(3-2) SPIIE(SPI Interrupt Enable Register)
SPIIE register is for enable 4 interrupts.
SPIIE Register

7

6

5

4

SPIIE
bit Symbol
(82CH)
Read/Write

2

1

0

RFULIE

TENDIE

RENDIE

R/W

After Reset

0

Function

15
(82DH)

3
TEMPIE

14

13

12

0

0

TEMP

RFUL

TEND

REND

interrupt

interrupt

interrupt

interrupt

0:enable

0:enable

0:enable

0:enable

1:disable

1:disable

1:disable

1:disable

11

0

10

9

8

bit Symbol
Read/Write
After Reset

Function

Figure 3.17.10 SPIIE Register

(a) 
Set enable/disable of TEMP interrupt.
(b)
Set enable/disable of RFUL interrupt.
(c)
Set enable/disable of TEND interrupt.
(d)
Set enable/disable of REND interrupt.

Note: As for 4 interrupts; 2 transmit interrupts (INTSPITX; TEMP, TEND) and 2 receive interrupts (INTSPIRX; RFUL,
REND), it should be selected one from TEMP and TEND, one from RFUL and REND when using
simultaneously. (Please do not select TEMP and TEND simultaneously. Or RFUL and REND simultaneously.)

92CZ26A-491

TMP92CZ26A

(4) SPICR (SPI CRC Register)
CRC result of Transmit/Receive data is set to SPICR register.
SPICR Register
SPICR
(826H)

bit Symbol

7

6

5

4

3

2

1

0

CRCD7

CRCD6

CRCD5

CRCD4

CRCD3

CRCD2

CRCD1

CRCD0

0

0

0

11

10

9

8

CRCD11

CRCD10

CRCD9

CRCD8

0

0

0

0

Read/Write

R

After Reset

0

0

0

0
0
CRC result register [7:0]

15

14

13

12

CRCD15

CRCD14

CRCD13

CRCD12

Function

bit Symbol
Read/Write

R

After Reset

0

0

0

0

CRC result register [15:8]
Function

Figure 3.17.11 SPICR Register

(a) 
The result which is calculated according to the setting; SPICT,
 and , are loaded to this register.
In case CRC16, all bits are valid.
In case CRC7, lower 7 bits are valid.
The flow will be showed to calculate CRC16 of received data for instance by flowchart.
Firstly, initialize CRC calculation register by writing = “1” after
setting = “1”, =”0”, = “0”.
Next, finish transmitting all bits to calculate CRC by writing data in SPITD register.
Please sense SPIST to confirm whether receiving is finished.
If read SPICR register after finishing, CRC16 of received data can be read.
Note: CRC is generated in I/O point. Please take care soft ware process to compare the CRC when
used FIFO.

8×32

TX shft register

8×32

RX shift register

SPI slave
Transmitt,Receive ontroller

TX FIFO

16bit

RX FIFO

Internal data bus

16bit

SPITD

TMP92CZ26A

SPIRD

(827H)

SPDO

SPDI

100KΩ
DI

100KΩ
DO

CRC generation point

92CZ26A-492

TMP92CZ26A

(5) SPITD (SPI Transmit Data Register)
SPITD0, SPITD1 registers are for writing transmitted data.
SPITD0 Register

SPITD0
(830H)

bit Symbol

7

6

5

4

TXD7

TXD6

TXD5

TXD4

Read/Write
After reset

3

2

1

0

TXD3

TXD2

TXD1

TXD0

0

0

0

11

10

9

8

TXD11

TXD10

TXD9

TXD8

0

0

0

0

3

2

1

0

TXD3

TXD2

TXD1

TXD0

0

0

0

11

10

9

8

TXD11

TXD10

TXD9

TXD8

0

0

0

0

R/W
0

0

0

0
0
Transmit data register [7:0]

15

14

13

12

TXD15

TXD14

TXD13

TXD12

Function

bit Symbol
(831H)

Read/Write
After reset

R/W
0

0

0

0

Transmit data register [15:8]
Function

SPITD1 Register

SPITD1
(832H)

bit Symbol

7

6

5

4

TXD7

TXD6

TXD5

TXD4

Read/Write
After reset

R/W
0

0

0

0
0
Transmit data register [7:0]

15

14

13

12

TXD15

TXD14

TXD13

TXD12

Function

bit Symbol
(833H)

Read/Write
After reset

R/W
0

0

0

0

Transmit data register [15:8]
Function

Figure 3.17.12 SPITD Register

This bit is for writing transmitted data. When read, the last written data is read. The data is
overwritten if write next data with transmit FIFO is not empty.
Transmit register exist 4bytes. Therefore, it is possible writing by using 4byte instruction
(use DMA together it etc.)
However, when write data (Destination address), writing the data from 830 addresses is
always needed.
Method of writing data (instruction) is restricted. Please refer to following table.
Transmit
data
write size

1byte write
2byte write
4byte write

Instruction
example

ld (0x830),a
ld (0x830),wa
ld (0x830),xwa

UNIT transmission
(No using FIFO)
2 byte
1byte
transmission
transmission
=1
=0
○
×
×
○
×
×

Sequential transmission
(Using FIFO)
2 byte
1 byte
transmission transmission
=1
=0
×
Prohibit
○
○
○
○

○: All data that written by CPU is transmitted
×: Invalid data that except for written by CPU is transmitted

92CZ26A-493

TMP92CZ26A

(6) SPIRD (SPI Receive Data Register)
SPIRD0, SPIRD1 registers are for reading received data.
SPIRD0 Register
SPIRD0
(834H)

bit Symbol

7

6

5

4

RXD7

RXD6

RXD5

RXD4

Read/Write
After reset

bit Symbol

0

0

0

0

15

14

13

1

0

RXD3

RXD2

RXD1

RXD0

0

0

0

0

12

11

10

9

8

RXD15

RXD14

RXD13

RXD12

RXD11

RXD10

RXD9

RXD8

0

0

0

0

3

2

1

0

RXD3

RXD2

RXD1

RXD0

0

0

0

11

10

9

8

RXD11

RXD10

RXD9

RXD8

0

0

0

0

Receive data register [7:0]

Read/Write
After reset

2

R

Function

(835H)

3

R
0

0

0

0

Function

Receive data register [15:8]
SPIRD1 Register

SPIRD1
(836H)

bit Symbol

7

6

5

4

RXD7

RXD6

RXD5

RXD4

Read/Write
After reset

R
0

0

0

0
0
Receive data register [7:0]

15

14

13

12

RXD15

RXD14

RXD13

RXD12

Function

bit Symbol
(837H)

Read/Write
After reset

R
0

0

Function

0

0

Receive data register [15:8]

Figure 3.17.13 SPIRD register

This bit is for reading received data. When read, read it after confirming status of RFUL or
REND. The data is overwritten if write next data with transmit FIFO is not empty.
Receive register exist 4bytes. Therefore, it is possible reading by using 4byte instruction (use
DMA together it etc.)
However, when read data basically, read the data from 834 addresses. (There is exception)
Method of reading data (instruction) is restricted. Please refer to following table.
Receive
data
read size

Instruction
example

UNIT receiving
Sequential receiving
(No using FIFO)
(Using FIFO)
2 byte
1 byte
2 byte
1byte
receiving
receiving
receiving
receiving
=1
=0
=1
=0
○
○
1byte read
ld a,(0x834)
Prohibit
Prohibit
×
○
ld a,(0x835)
Prohibit
Prohibit
△*1
○
○
○
2 byte read
ld wa,(0x834)
△*2
△*3
○
○
4 byte read
ld xwa,(0x834)
○: Read only valid data when CPU is reading.
△: Read valid data + invalid data when CPU is reading. Invalid data must be deleted after read.
×: Read only invalid data when CPU is reading.
*1: 834 address = valid data, 835 address = Invalid data,
*2: 834 address = valid data, 835 address = Invalid data, 836 address = Invalid data, 837 address = Invalid data
*3: 834 address = valid data, 835 address = valid data, 836 address = Invalid data, 837 address = Invalid data

92CZ26A-494

TMP92CZ26A

•

Note of FIFO buffer
There are following notes in this SPIC.
1) Transmit
・ Data is overwritten if write data with condition transmit FIFO buffer is FULL.
Interrupt and transmission are not executed normally because write-pointer in FIFO
becomes abnormal condition. Therefore, manage number of writing by using software.
・ If transmit is sequential, writing the data to transmit FIFO every 16 bytes is always
needed. If writing other than 16 bytes, TEMP interrupt does not generate normally.
Note: If transmitting it by except 16 byte, use UNIT transmitting.

2) Receive
・ If read data with condition receive FIFO is empty, undefined data is read. Interrupt
and receiving are not executed normally because read-pointer in FIFO becomes
abnormal condition. Therefore, manage number of reading by using software.

・ If receive is sequential, reading the data from receive FIFO every 16 bytes is always
needed. If reading other than 16 bytes, RFUL interrupt does not generate normally.
Note: If transmitting it by except 16 byte, use UNIT receiving.

3) CRC
CRC is generated in I/O point. Please take care soft ware process to compare the CRC when used FIFO.
Ex. Sequential receive
1.

Start sequential receive

2.

finish valid data receive (FIFO_Full)

3.

disable receive

4.

valid data read from FIFO to temporary buffer(internal RAM)

5.

CRC1 read from CRC generator in SPI circuit

6.

CRC2 receive (enable UNIT receive from SD-CARD)

7.

compare CRC1 and CRC2

Note: Above 2 to 4 process can be used DMAC, however it must stop sequential receive (process 3)
before to get CRC2 form SD-CARD.

92CZ26A-495

TMP92CZ26A

3.18 I2S (Inter-IC Sound)
The TMP92CZ26A incorporates serial output circuitry that is compliant with the I2S format.
This function enables the TMP92CZ26A to be used for digital audio systems by connecting an
LSI for audio output such as a DA converter.
The I2S unit has the following features:

Table 3.18.1 I2S Operation Features
Item

Description

Number of Channels

2 channels

Format

I S-format compliant

2

Right-justified and left-justified formats supported
Stereo / monaural
Master transmission only
Pins used

1. I2SnCKO (clock output)
2. I2SnDO (output)
3. I2SnWS (Word Select output)

WS frequency
Data transfer rate

Refer to “Setting the transfer clock generator and Word Select signal”.

Transmission buffer

64 bytes x 2

Direction of data

MSB-first or LSB-first selectable

Data length

8 bits or 16 bits

Clock edge

Rising edge or falling edge

Interrupt

INTI2Sn
(64-byte FIFO empty interrupt)

92CZ26A-496

TMP92CZ26A

3.18.1

Block Diagram

The I2S unit contains two channels: channel 0 and channel 1. Each channel can be controlled
and made to output independently.
Figure 3.18.1 shows a block diagram for I2S channel 0.
I2S0CTL

fSYS

8-bit
Counter

fI2S

I2SCKO
Control

I2S0C


I2S0CKO

I2S0CTL

6-bit
Counter

I2SWS
Control

I2S0C


I2S0WS

I2S0CTL


Clock Generator

INTI2S0
I2S0CTL

0 1

31

64-byte FIFO0
(2 bytes×32)

0 1

31

Data Selector

64-byte FIFO1
(2 bytes×32)

Interrupt

Shifter

Internal Data Bus

32bit

I2SBUF0



Control

I2S0DO
FIFO Control

Write Pointer

I2S0CTL

Read Pointer





Request Signal Output to ADC
(Supported in channel 0 only)

Figure 3.18.1 I2S Block Diagram

92CZ26A-497

TMP92CZ26A

3.18.2

SFRs

The I2S unit is provided with the following registers. These registers are connected to the
CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be accessed
using 4-byte load instructions.
I2S0 Control Register
I2S0CTL
(1808H)

7

6

bit Symbol

TXE0

Read/Write

R/W
0

0

After reset

5

4

3

2

1

0

*CNTE0

DIR0

BIT0

DTFMT01

DTFMT00

SYSCKE0

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

Transmission Counter

Function

(1809H)

Transmissio Bit length

0
System

Output format

control

n start bit

0: Stop

0: Clear

0:MSB

0: 8 bits

00: I S 10: Right

1: Start

1: Start

1:LSB

1: 16 bits

01: Left 11: Reserved

15

14

13

2

clock
0: Disable
1: Enable

12

11

10

9

8

bit Symbol

CLKS0

FSEL0

TEMP0

WLVL0

EDGE0

CLKE0

Read/Write

R/W

R/W

R

R/W

R/W

R/W

After reset

0

0

1

0

0

0

Source

Stereo

clock

Transmissio WS level

/monaural n FIFO state

Data output Clock
clock edge operation

0: Low left
Function

0: fSYS

0: Stereo

1: fPLL

1: Monaural 1: No data

0: Data

(after

1: High left 0: Falling
1: Rising

transmission)
0: Enable
1: Disable

I2S0 Divider Value Setting Register

I2S0C
(180AH)

7

6

5

4

3

2

1

0

bit Symbol

CK07

CK06

CK05

CK04

CK03

CK02

CK01

CK00

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

15

14

Function

(180BH)

Divider value for CK signal (8-bit counter)

13

12

11

10

9

8

Bit symbol

WS05

WS04

WS03

WS02

WS01

WS00

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

Function

Divider value for WS signal (6-bit counter)

I2S0 Buffer Register
I2S0BUF
(1800H)

bit Symbol

15

14

13

12

11

10

9

8

B015

B014

B013

B012

B011

B010

B009

B008

Read/Write
Read-modifywrite
instructions
cannot be
used.

7

6

5

4

3

2

1

0

B007

B006

B005

B004

B003

B002

B001

B000

W

After reset

Undefined

Function

Transmission buffer register (FIFO)

bit Symbol

31

30

29

28

27

26

25

24

B031

B030

B09

B028

B027

B026

B025

B024

23

22

21

20

19

18

17

16

B023

B022

B021

B020

B019

B018

B017

B016

Read/Write

W

After reset

Undefined

Function

Transmission buffer register (FIFO)
2

Figure 3.18.2 I S Channel 0 Control Registers

92CZ26A-498

TMP92CZ26A

I2S1 Control Register

I2S1CTL
(1818H)

7

6

bit Symbol

TXE1

Read/Write

R/W

After reset

0

5

4

3

2

1

0

*CNTE1

DIR1

BIT1

DTFMT11

DTFMT10

SYSCKE1

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

Transmission Counter

control
Function

Output format

0: MSB

0: 8 bits

00: I S

1: LSB

1:16 bits

01: Left

start bit

0: Stop
1: Start

Bit length

Transmission

0: Clear

2

0
System

clock
0: Disable
11: Reserved 1: Enable

10: Right

1: Start
15

(1819H)

14

13

12

11

10

9

8

bit Symbol

CLKS1

FSEL1

TEMP1

WLVL1

EDGE1

CLKE1

Read/Write

R/W

R/W

R

R/W

R/W

R/W

After reset

0

0

1

0

0

0

Source

Stereo

clock
Function

/monaural

Transmission WS level

Data output Clock

FIFO state

clock edge operation

0: fSYS

0: Stereo

0: Data

1: fPLL

1: Monaural

1: No data

0: Low left 0: Falling

(after

1: High left 1: Rising

transmission)
0: Enable
1: Disable

I2S1 Divider Value Setting Register

I2S1C
(181AH)

7

6

5

4

3

2

1

0

bit Symbol

CK17

CK16

CK15

CK14

CK13

CK12

CK11

CK10

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Function

Divider value for CK signal (8-bit counter)
15

(181BH)

13

12

11

10

9

8

Bit symbol

14

WS15

WS14

WS13

WS12

WS11

WS10

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

Function

Divider value for WS signal (6-bit counter)

I2S1 Buffer Register
I2S1BUF
(1810H)

bit Symbol

15

14

13

12

11

10

9

8

B115

B114

B113

B112

B111

B110

B109

B108

Read/Write
Read-modifywrite
instructions
cannot be
used.

7

6

5

4

3

2

1

0

B107

B106

B105

B104

B103

B102

B101

B100

W

After reset

Undefined

Function

Transmission buffer register (FIFO)

bit Symbol
Read/Write

31

30

29

28

27

26

25

24

B131

B130

B129

B128

B127

B126

B125

B124

23

22

21

20

19

18

17

16

B123

B122

B121

B120

B119

B118

B117

B116

W

After reset

Undefined

Function

Transmission buffer register (FIFO)

Figure 3.18.3 I2S Channel 1 Control Registers

92CZ26A-499

TMP92CZ26A
3.18.3

Description of Operation
(1) Settings the transfer clock generator and Word Select signal
In the I2S unit, the clock frequencies for the I2SnCKO and I2SnWS signals are
generated using the system clock (fSYS) as a source clock. The system clock is divided
by a prescaler and a dedicated clock generator to set the transfer clock and sampling
frequency.
The counters are started by setting I2SnCTL to “1” and are stopped and
cleared by setting  to “0”.
A) Clock generator
・ 8-bit counter
This is an 8-bit counter that generates the I2SnCKO signal by dividing the clock
selected by I2SnCTL.
・ 6-bit counter
This is a 6-bit counter that generates the I2SnWS signal by dividing the
I2SnCKO signal.
B) Word Select
・ Word Select signal (I2SnWS)
The I2SnWS signal is used to distinguish the position of valid data and whether
left data or right data is being transmitted in the I2S format. This signal is clocked
out in synchronization with the data transfer clock. In only channel 0, this signal
can be used as an AD conversion trigger signal for the ADC. How valid data is to
be output in relation to the WS signal can be specified as I2S format, left-justified,
or right-justified. In only channel 0, an interrupt request can be output to the ADC
on the rising edge of the WS signal. (This is controlled by the ADC’s control
register.)
(2) Data format
This circuit support I2S format, left justify and right justify format by setting
I2SnCTL register. And support stereo and monaural both, controlled
by I2SnCTL register.

92CZ26A-500

TMP92CZ26A

Left Data

Right Data

I2SnWS
I2SnCKO

I2S format
I2SnDO
Stereo

LSB

MSB

LSB

MSB

Valid data
Monaural

LSB

MSB

LSB

Valid Data
LSB

MSB

MSB

Valid Data

Left justify
I2SnDO
Stereo

LSB

MSB

MSB

Valid Data
Monaural

MSB

LSB

Valid Data
LSB

MSB

MSB

Valid Data
Right justify
I2SnDO
Stereo

LSB

MSB

LSB

Valid Data
Monaural

LSB

MSB

MSB

LSB

Valid Data
LSB

Valid Data

Figure 3.18.4 Output Format

92CZ26A-501

TMP92CZ26A

(2) Setting example for the clock generator (8-bit counter/6-bit counter)
The clock generator generates the reference clock for setting the data transfer speed
and sampling frequency.

I2S0C
(180AH)

7

6

5

4

3

2

1

0

bit Symbol

CK07

CK06

CK05

CK04

CK03

CK02

CK01

CK00

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

15

14

Function

(180BH)

Divider value for CK signal (8-bit counter)
13

12

11

10

9

8

Bit symbol

WS05

WS04

WS03

WS02

WS01

WS00

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

Function

Divider value for WS signal (6-bit counter)

• Setting the transfer clock I2SnCKO
The transfer clock is generated by dividing the clock selected by I2SnCTL
. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
Note:

The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is set to within 10
MHz by an appropriate combination of source clock frequency and divider value.

8-bit counter set value
00000000
00000001
11111111

Divider value
256
1
255

When fSYS = 60 MHz and I2SnC = 150, the data transfer speed is set as follows:
I2SnCKO = fSYS/150
= 60 [MHz]/150 = 400 [kbps]
Note: It is recommended that the value to be set in I2SnC be an even number. Although it is possible to
set an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes
the High width of the I2SnCK0 signal to become longer by one fsys or fPLL pulse than the Low width. (When
 = 0, the Low width becomes longer than the High width.)

• Setting the sampling frequency WS
The sampling frequency is set by dividing the transfer clock (CK) described above.
A 6-bit counter is provided to divide the transfer clock by 16 to 64. (The divider
value cannot be set to 1 to 15.)
6-bit counter set value
000000
000001
111111

Divider value
64
1
63

When fSYS = 60 MHz, I2SnC = 150, and I2SnC = 50, the sampling frequency is set as
follows:
I2SnCKO = fSYS / 150 / 50
= 60 [MHz] / 150 / 50 = 8 [kHz]
Based on the above, the transfer clock is set to 400 kbps, and the sampling frequency is set to 8 kHz in this
example.

92CZ26A-502

TMP92CZ26A

Note 1: The value to be set in I2SnC must be 16 or larger (18 or larger for I2S transfer) when the data
length is 8 bits and 32 or larger (34 or larger for I2S transfer) when the data length is 16 bits.
Note 2: It is recommended that the value to be set in I2SnC be an even number. Although it is
possible to set an odd number, the clock duty of the WS signal does not become 50%. Setting an odd
number causes the High width of the WS signal to become longer by one I2SnCK0 pulse than the Low
width.

• Special function
As a special function available only in channel 0, the rising edge of the WS signal
can be used as an AD conversion start trigger for the AD converter in this LSI.
Setting I2S0CTL=1 and I2S0CTL=1 enables the WS signal to
be sent to the AD converter. This can be done regardless of the setting of
I2S0CTL.
For details about AD conversion using the WS signal, refer to the chapter on the
AD converter.
(3) FIFO buffer and data format
The I2S unit is provided with a 128-byte FIFO buffer (32-bit wide x 32-entry). The data
written to the 4 bytes (32 bits) of the I2SnBUF register is written to this FIFO buffer. This
FIFO must be written in units of 4 bytes. It is also necessary to consider the output order
and to distinguish between right data and left data.
To write data to the I2SnBUF register, be sure to use a 4-byte load instruction. If a
1-byte load instruction is used, invalid data will be transmitted. In case of using 1-byte or
2-byte transmission instruction, FIFO buffer isn't renewed and transmission isn't started.
And window addresses are 1800H (channel 0) and 1810H (channel1).

Write Data Size

Example instruction

8-bit width

16-bit width

1-byte access

ld (0x1800),a

Not allowed

Not allowed

2-byte access

ld (0x1800),wa

Not allowed

Not allowed

4-byte access

ld (0x1800),xwa

OK

OK

Also note that data must be written in units of 64 bytes using the following sequence:
4-byte load instruction × 16 times = 64-byte data write
If data is not written in units of 64 bytes, interrupts cannot be generated at the normal
timing.
The I2SnCTL flag is set to “1” when the FIFO buffer for each channel contains
no valid data. If there is even one byte of valid data in the FIFO, the flag is cleared to “0”.
(The  flag is set to “1” as soon as the last valid data in the FIFO is sent to the
transmission shift register.)

92CZ26A-503

TMP92CZ26A

The following shows how written data is output under various conditions.

When I2SnCTL = 0
I2SnBUF register
Output order

MSB-first 16 bits

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2’nd Data
4’th Data

3’rd Data
4’th Data

LSB-first 8 bits
15

MSB-first 16 bits

14

13

12

11

10

9

3’rd Data
8

7

6

5

4

3

2

1

0

1’st Data
1’st Data

LSB-first 16 bits
MSB-first 8 bits

16

2’nd Data

LSB-first 16 bits
MSB-first 8 bits

17

2’nd Data

1’st Data

LSB-first 8 bits

2’nd Data

1’st Data

When I2SnCTL = 1
I2SnBUF register
Output order

MSB-first 16 bits

31

30

29

28

27

26

25

24

23

22

21

20

19

18

1’st Data
3’rd Data

4’th Data
4’th Data

3’rd Data

LSB-first 8 bits
15

MSB-first 16 bits

14

13

12

11

10

9

8

7

6

LSB-first 8 bits

5

4

3

2

1

0

2’nd Data

LSB-first 16 bits
MSB-first 8 bits

16

1’st Data

LSB-first 16 bits
MSB-first 8 bits

17

2’nd Data
1’st Data

2’nd Data
1’st Data

2’nd Data

Note: In case of using monaural setting, and change right / left: I2SnCTL, data output order change
off 1'st data and 2'nd data.

92CZ26A-504

TMP92CZ26A

3.18.4

Detailed Description of Operation

(1) Connection example
Figure 3.18.5 shows an example of connections between the TMP92CZ26A and an
external LSI (DA converter) using channel 0.
TMP92CZ26A
(Transmit)

(Receive)

PF2/I2S0WS

WS

PF0/I2SCKO

CK

PF1/I2SDO

DATA

Example: DA converter
Note:

After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor
as necessary.

Figure 3.18.5 Connection Example between the TMP92CZ26A and an External LSI
(2) Operation procedure
The I2S unit incorporates a 128-byte FIFO buffer that is divided into two 64-byte units.
Whenever each 64-byte buffer space becomes empty, an INTI2Sn interrupt is generated.
The next data to be transmitted should be written to the FIFO in the interrupt routine.
Example settings and timing diagram are shown below.
(Example settings) I2S0WS = 8 KHz, I2SnCKO = 400 kHz, data transmission on the rising edge (at fSYS = 50 MHz)
(Main routine)
7

6

5

4

3

2

1

0

INTEI2S01

X

−

−

X

0

0

1

Set interrupt level.

PFCR

X

−
X

−

−

−

−
1

X

−
1

−
0

−
1

0

−
0

−
1

Set pins: PF0 (I2S0CKO), PF1 (I2S0DO), PF2 (I2S0WS)

PFFC

−
1
1

1

0

Divider value N=150

X

X

1

1

0

0

1

0

Divider value K=50

I2S0CTL

0

0

X

0

1

0

0

1

Set transmit mode (I S mode, MSB-first, 16-bit).

0
*

X
*

X
*

X
*

X
*

0
*

0
*

0
*

Falling edge, WS=0 Left, clock stop.

I2S0BUF

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

1

0

X

0

1

0

0

1

0

X

X

X

X

0

0

0

(INTI2S Interrupt Routine)
* *
I2S0BUF

I2S0SC

I2S0CTL

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

2

Write left and right data to FIFO (4 bytes x 32 = 128 bytes).

Start transmission.

Write left and right data to FIFO (4 bytes x 16 = 64 bytes).

X: Don't care, −: No change

92CZ26A-505

TMP92CZ26A

FIFO write

1

2

3

4

31

32

33

I2SnWS pin
I2SnCKO pin
I2SnDO pin

INTI2Sn

Overall Timing Diagram
I2SnWS pin

400kHz

I2SnCKO pin
I2SnDO pin

LSB

MSB

LSB

MSB

LSB

Bit15 Bit14

Bit0

Bit15 Bit14

Bit0

MSB
Bit15

Detailed Timing Diagram

Figure 3.18.6 Timing Diagrams (I2S FMT/Stereo/16bit/MSB first)
(3) Considerations for using the I2S unit
1) INTI2Sn generation timing
Every 4bytes data trance from FIFO buffer to shift register per one time.
An INTI2Sn interrupt is generated under two conditions. One is when there are 64
bytes of empty space in the FIFO (after 61- 64th byte has been transferred to the shift
register). The other is when the FIFO becomes completely empty (after 125 - 128th
byte has been transferred to the shift register). Therefore, INTI2Sn indicates that
there are 64 bytes or 128 bytes of empty space in the FIFO, enabling the next data to
be written.
The FIFO must be written in units of 64 bytes. Since the FIFO can contain 128 bytes
of data, I2S output can be performed continuously as long as there are 64 bytes of data
in the FIFO. It is also possible to check the FIFO state by using the
I2SnCTL flag.
2) I2SnCTL
Transmission is started by setting I2SnCTL  to “1”. Once  is set to
“1”, transmission is continued automatically as long as the FIFO contains the data to
be transmitted. While  is set to “1” (transmission in progress), the other bits in
the I2SnCTL register must not be changed.
To stop transmission, make sure that the FIFO is empty by checking the
I2SnCTL flag. Then, after waiting for two periods of the I2SWS signal (after
all the data has been transmitted), set  to “0”. In case monaural setting, make
sure that the FIFO is empty by checking the I2SnCTL flag. Then, after
waiting for four periods of the I2SWS signal (after all the data has been transmitted),
set  to “0”.
If  is set to “0” while data is being transmitted, the transmission is stopped

92CZ26A-506

TMP92CZ26A
immediately. At the same time, the read and write pointers of the FIFO, the data in
the output shift register and the clock generator are all cleared. (However, when
I2SnCTL=1, the clock generator is not cleared. To clear the clock generator,
I2SnCTL must be set to “0”). Therefore, if transmission is stopped and then
resumed, no data will be output.
The WS signal stops at Low level and the CK signal stops at Low level when the
rising edge is selected and at High level when the falling edge is selected.
3) I2SnCTL
I2SnCTL is used to control the clock generator (8-bit counter, 6-bit
counter) for generating the I2SnCKO and I2SnWSOsignals.
Setting I2SnCTL to “1” starts the counters, and setting this bit to “0”
stops the counters. Normally, I2S data transmission is executed by setting both
I2SnCTL and  to “1”. When transmission is stopped by setting
I2SnCTL to “0” with I2SnCTL=1, the clock generator is not cleared.
To clear the clock generator, I2SnCTL must be set to “0”.
4) FIFO buffer
The I2S unit is provided with a 128-byte FIFO. Although it is not necessary to use all
128 bytes in the FIFO, data should basically be written in units of 64 bytes using an
INTI2Sn interrupt as a trigger. If data is written to the FIFO without waiting for an
INTI2Sn interrupt or in units other than 64 bytes, interrupts cannot be generated
properly.
If the last set of data, for which an interrupt is not needed, contains less than 64
bytes, set I2SnCTL to “0” to stop the transmission after writing the data, then
checking that the  flag is set to “1”, and waiting for two I2SWS periods (i.e.,
after all the data has been transmitted). In case monaural setting, make sure that the
FIFO is empty by checking the I2SnCTL flag. Then, after waiting for four
periods of the I2SWS signal (after all the data has been transmitted), set  to
“0”.
5) I2SnBUF
When writing data to the I2SnBUF register, be sure to use long-word data load
instructions. Word data load or byte data load instructions cannot be used.

Examples)
ld

(I2SnBUF), xwa;

OK

ld

(I2SnBUF), wa;

NG

ld

(I2SnBUF), a;

NG

92CZ26A-507

TMP92CZ26A

3.19 LCD Controller (LCDC)
The TMP92CZ26A incorporates an LCD controller (LCDC) for controlling an LCD driver
LSI (LCD module). This LCDC supports display sizes from 64 × 64 to 640 × 480 dots for
monochrome, grayscale, and 4096-color display and from 64 × 64 to 320 × 320 dots for color
display using 65536 or more colors. The supported LCD driver (LCD module) types are
STN (Super Twisted Nematic) and digital RGB input TFT (Thin Film Transistor).
•

STN support

With LCD drivers supporting STN, an 8-bit data interface is used to realize monochrome,
4-graysale, 16-grayscale, 64-grayscale, 256-color, 4096-color display.
After required settings such as the operation mode, display RAM start address, and LCD
size (common, segment) are made in the I/O registers, the start register is set to enable the
LCDC. The LCDC outputs a bus request to the CPU, reads data from the display RAM,
converts the data as necessary, and writes it to a dedicated FIFO buffer.
•

TFT support

With LCD drivers supporting digital RGB input TFT, an 8- to 24-bit data interface is
used to realize 4096-color, 65536-color, 262144-color, and 16777216-color display. The data
transfer method is the same as in the case of STN.
The LCDC controls LCD display operations using 8-bit RGB (R3:G3:B2), 12-bit RGB
(R4:G4:B4), 16-bit RGB (R5:G6:B5), 18-bit RGB (R6:G6:B6), or 24-bit RGB (R8:G8:B8)
display data, the shift clock LCP0 for capturing data, the frame signal LFR, the data load
signal LLOAD, and the LDIV signal for indicating the inversion of data output. The LDIV
signal can be used effectively in reducing noise and power consumption.
The LCDC also has horizontal synchronization signal LHSYNC and vertical
synchronization signal LVSYNC for controlling gate drivers, and three programmable OE
pins for supporting various signals of the TFT driver to be used.

92CZ26A-508

TMP92CZ26A

3.19.1 LCDC Features according to LCD Driver Type

Table 3.19.1 LCDC Features according to LCD Driver Type
(This table assumes the connection with a TOSHIBA-made LCD driver.)
Shift Register Type
LCD Driver
TFT
Display colors

Number of pixels that can be
displayed

256/4096/65536/262144/16777216 colors
For 65536 colors or less
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 128, 160, 240, 320, 640
For 65536 colors or more
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 128, 160, 240, 320

LCD driver data bus:
LD23 to LD0 pins

16 bits (32 bits: internal RAM)

8 to 24 bits

8 bits

4.17 ns/byte at internal RAM
To be connected to LCD driver data bus.
・ 8-bit mode: LD7 to LD0
・TFT mode: LD23 to LD0
Data shift clock for TFT source driver

External Pins

Vertical shift clock for TFT gate driver
LHSYNC pin

LGOE0 to LGOE2
pins
LFR pin
LVSYNC pin

LDIV pin

–

16 bits (32 bits: internal RAM)

LCP0 pin

LLOAD pin

Rows (Commons):
64, 96, 120, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 120, 128, 160, 240, 320, 480, 640

Horizontal flip, vertical flip, horizontal and vertical flip, 90-degree rotation
(supported for QVGA size, 65536 colors only)
A sub window can be inserted.

Data rotation function
PIP function support
Source data bus width
(SRAM, SDRAM)
Destination data bus width
(LCD driver)
Maximum transfer rate
(VRAM read)
(at fSYS = 80 MHz)

STN
Monochrome, 4/16/64 grayscale levels
256/4096 colors

Enable signal for TFT source driver to load data
to TFT panel
Adjustment signal for TFT gate driver’s gate
control signal
LCD alternate signal output pin. To be connected
to column/row driver’s FR pin.
This signal indicates the start of shift clock
capture by TFT gate driver.
This signal indicates the inversion of data. To be
connected to TFT source driver having the data
inversion function.

92CZ26A-509

Shift clock pulse output pin 0. To be connected to
column driver’s CP pin. The LCD driver latches the
data bus value on the falling edge of this pin.
Latch pulse output pin. To be connected to the LCD
driver’s LP pin. The display data in the LCD driver’s
output line register is updated on the rising edge of
this pin.
N/A
N/A
LCD alternate signal output pin. To be connected to
column/row driver’s FR pin.
Frequency that sets LCD refresh rate

N/A

TMP92CZ26A
3.19.2 SFRs
LCDMODE0 Register

7

6

5

4

3

2

1

0

LCDMODE0

bit Symbol

RAMTYPE1

RAMTYPE0

SCPW1

SCPW0

MODE3

MODE2

MODE1

MODE0

(0280H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

1

1

0

0

0

0

Display RAM

LD bus transfer speed
SCPW2= 0
00: 2-clk
01: 4-clk
10: 8-clk
11: 16-clk
SCPW2= 1
00: 6-clk
01: 12-clk

00: Internal RAM
01: External SRAM
Function

10: SDRAM
11: Reserved

Mode selection
0000: Reserved

1000: Reserved

0001: SR (mono)

1001: Reserved

0010: SR (4-gray)

1010: TFT (256-color)

0011: Reserved

1011: TFT (4096-color)

0100: SR (16-gray)

1100: TFT (64K-color)

0101: SR (64-gray) 1101:TFT(256K-,16M-color)
0110: STN (256-color) 1110 : Reserved

10: 24-clk

0111:STN (4096-color)1111: Reserved

11: 48-clk

Note: When SDRAM is used as the LCDC’s display RAM, it can only be accessed by “burst 1-clock access”.
LCDMODE1 Register

7

6

5

4

3

2

1

0

LCDMODE1

bit Symbol

LDC2

LDC1

LDC0

LDINV

AUTOINV

INTMODE

FREDGE

SCPW2

(0281H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

W

W

0

0

0

After reset

0

0

0

LD bus

Auto bus

Interrupt

(Supported for 64K-color: 16bps

inversion

inversion

selection

only)
Function

0

Data rotation function

0: Disable

000: Normal

100: 90-degree

001: Horizontal flip 101: Reserved
010: Vertical flip

0

LFR edge

LD bus
Trance

0: LHSYNC Speed

0: Normal

1: Enable

0:LLOAD

1: Invert

(Valid only

1:LVSYNC 1:LHSYNC 0: normal

110: Reserved

for TFT)

Front Edge
Rear Edge 1: 1/3

011: Horizontal & vertical flip
111: Reserved
Note: =1 inverts all output data on the LD bus. However, the LDIV signal that indicates the inversion of
output data by auto bus inversion remains unchanged.
LCD Size Setting Register
7

6

5

4

3

2

1

0

LCDSIZE

bit Symbol

COM3

COM2

COM1

COM0

SEG3

SEG2

SEG1

SEG0

(0284H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Common setting

Function

Note:

Segment setting

0000: Reserved

1000: 320

0000: Reserved

1000: Reserved

0001: 64

1001: 480

0001: 64

1001: Reserved

0010: 96

1010: Reserved

0010: 128

1010: Reserved

0011: 120

1011: Reserved

0011: 160

1011: Reserved

0100: 128

1100: Reserved

0100: 240

1100: Reserved

0101: 160

1101: Reserved

0101: 320

1101: Reserved

0110: 200

1110: Reserved

0110: 480

1110: Reserved

0111: 240

1111: Reserved

0111: 640

1111: Reserved

Although the TMP92CZ26A contains 288 Kbytes of RAM that can be used as display RAM, it may not be
enough depending on display size and color mode.

92CZ26A-510

TMP92CZ26A

LCD Control 0 Register
7

6

5

4

2

1

0

LCDCTL0

bit Symbol

PIPE

ALL0

FRMON

–

3

DLS

LCP0OC

START

(0285H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

PIP

Segment

FR divide

Always

FR signal

function

data

setting

write “0”

LCP0/Line

0:Disable

0: Normal

0: Disable

1:Enable

1: Always

1: Enable

selection

Function

output
1: At valid
data only

0:Line

output “0”

LCP0(Note LCDC
0: Always operation
0: Stop
1: Start

LLOAD

1:LCP0

width
0: At setting
in register
1: At valid
data only
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of  bit.

LCD Control 1 Register
7

6

5

4

3

2

1

0

LCDCTL1

bit Symbol

LCP0P

LHSP

LVSP

LLDP

LVSW1

LVSW0

(0286H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

1

0

1

0

0

0

Function

LCP0

LHSYNC

LVSYNC

LLOAD

LVSYNC

phase

phase

phase

phase

enable time control

0: Rising

0: Rising

0: Rising

0: Rising

01: 2 clocks of LHSYNC

1: Falling

1: Falling

1: Falling

1: Falling

10: 3 clocks of LHSYNC

00: 1 clock of LHSYNC

11: Reserved

LCD Control 2 Register

LCDCTL2
(0287H)

7

6

5

bit Symbol

LGOE2P

LGOE1P

LGOE0P

Read/Write

R/W

R/W

R/W

After reset

0

0

LGOE2

LGOE1

LGOE0

phase

phase

phase

0: Rising

0: Rising

0: Rising

1: Falling

1: Falling

1: Falling

4

3

2

1

0

0

Function

Divide FRM 0 Register

LCDDVM0

bit Symbol

(0283H)

Read/Write
After reset

7

6

5

4

3

2

1

0

FMP3

FMP2

FMP1

FMP0

FML3

FML2

FML1

FML0

0

0

0

0

0

0

0

R/W

Function

0

LCP0 DVM (bits 3-0)

LHSYNC DVM (bits 3-0)

Divide FRM 1 Register

LCDDVM1

bit Symbol

(0288H)

Read/Write
After reset
Function

7

6

5

4

3

2

1

0

FMP7

FMP6

FMP5

FMP4

FML7

FML6

FML5

FML4

0

0

0

R/W
0

0

0

0

LCP0 DVM (bits 7-4)

92CZ26A-511

0

LHSYNC DVM (bit 7-4)

TMP92CZ26A

LCD LHSYNC Pulse Register

LCDHSP

bit Symbol

(028AH)

Read/Write
After reset

7

6

5

4

3

2

1

0

LH7

LH6

LH5

LH4

LH3

LH2

LH1

LH0

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

LH15

LH14

LH13

LH12

LH11

LH10

LH9

LH8

0

0

0

0

0

0

0

0

W

Function
bit Symbol
(028BH)

LHSYNC period (bits 7–0)

Read/Write
After reset

W

Function

LHSYNC period (bits 15-8)
LCD V SYNC Pulse Register

LCDVSP
(028CH)

bit Symbol

7

6

5

4

3

2

1

0

LVP7

LVP6

LVP5

LVP4

LVP3

LVP2

LVP1

LVP0

0

0

0

0

0

0

0

0

7

6

5

Read/Write
After reset

W

Function

LVSYNC period (bits 7-0)

4

3

2

bit Symbol
(028DH)

1

0

LVP9

LVP8

Read/Write

W

After reset

0

0

LVSYNC period

Function

(bits 9-8)
LCD LVSYNC Pre Pulse Register

7
LCDPRVSP

bit Symbol

(028EH)

Read/Write
After reset
Function

6

5

4

3

2

1

0

PLV6

PLV5

PLV4

PLV3

PLV2

PLV1

PLV0

0

0

0

0

0

0

W
0

Front dummy LVSYNC (bits 6-0)

92CZ26A-512

TMP92CZ26A

7
LCDHSDLY

bit Symbol

(028FH)

Read/Write

6

5

4

3

2

1

0

HSD6

HSD5

HSD4

HSD3

HSD2

HSD1

HSD0

0

0

0

0

0

0

W

After reset
Function

0

LHSYNC delay (bits 6-0)

7

6

5

4

3

2

1

0

LDD6

LDD5

LDD4

LDD3

LDD2

LDD1

LDD0

0

0

0

LCDLDDLY

bit Symbol

PDT

(0290H)

Read/Write

R/W

After reset

0

W
0

0

0

0
LLOAD delay (bits 6-0)

Data output
timing

Function

0: Sync with
LLOAD
1: 1 clock later
than LLOAD

7
LCDO0DLY

bit Symbol

(0291H)

Read/Write

6

5

4

3

2

1

0

OE0D6

OE0D5

OE0D4

OE0D3

OE0D2

OE0D1

OE0D0

0

0

0

0

0

0

W

After reset
Function

7
LCDO1DLY

bit Symbol

(0292H)

Read/Write

6

5

4

3

2

1

0

OE1D6

OE1D5

OE1D4

OE1D3

OE1D2

OE1D1

OE1D0

0

0

0

W

After reset

0

0

0

Function

bit Symbol

(0293H)

Read/Write
After reset
Function

0
OE1 delay (bits 6-0)

7
LCDO2DLY

0
OE0 delay (bits 6-0)

6

5

4

3

2

1

0

OE2D6

OE2D5

OE2D4

OE2D3

OE2D2

OE2D1

OE2D0

0

0

0

W
0

0

0

0
OE2 delay (bits 6-0)

92CZ26A-513

TMP92CZ26A

LCDHSW

bit Symbol

(0294H)

Read/Write
After reset

7

6

5

4

3

2

1

0

HSW7

HSW6

HSW5

HSW4

HSW3

HSW2

HSW1

HSW0

0

0

0

0

0

0

0

0

3

2

1

0

LDW3

LDW2

LDW1

LDW0

0

0

0

0

W

Function

LCDLDW

bit Symbol

(0295H)

Read/Write
After reset

LHSYNC width (bits 7-0)

7

6

5

4

LDW7

LDW6

LDW5

LDW4
W

0

0

0

Function

LCDHO0W

bit Symbol

(0296H)

Read/Write
After reset

7

6

5

4

3

2

1

0

O0W7

O0W6

O0W5

O0W4

O0W3

O0W2

O0W1

O0W0

0

0

0

0

0

0

0

0

W

Function

LCDHO1W

bit Symbol

(0297H)

Read/Write
After reset

LGOE0 width (bits 7-0)

7

6

5

4

3

2

1

0

O1W7

O1W6

O1W5

O1W4

O1W3

O1W2

O1W1

O1W0

0

0

0

0

3

2

1

0

O2W3

O2W2

O2W1

O2W0

0

0

0

0

3

2

1

0

O0W8

LDW9

LDW8

HSW8

0

0

W
0

0

0

Function

LCDHO2W

bit Symbol

(0298H)

Read/Write
After reset

bit Symbol

(0299H)

Read/Write
After reset
Function

0

LGOE1 width (bits 7-0)

7

6

5

4

O2W7

O2W6

O2W5

O2W4
W

0

0

0

Function

LCDHWB8

0

LLOAD width (bits 7-0)

0

LGOE2 width (bits 7-0)

7

6

5

4

O2W9

O2W8

O1W9

O1W8
W

0

0

LGOE2 width (bits 9-8)

0

0

LGOE1 width (bits 9-8)

0
LGOE0
width (bit 8)

92CZ26A-514

LLOAD width (bits 9-8)

0
LHSYNC
width (bit 8)

TMP92CZ26A

LCD Main Area Start Address Register

LSAML
(02A0H)

7

6

5

4

3

2

1

bit Symbol

LMSA7

LMSA6

LMSA5

LMSA4

LMSA3

LMSA2

LMSA1

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

Function

LSAMM
(02A1H)

LCD main area start address (A7-A1)
7

6

5

4

3

2

1

0

bit Symbol

LMSA15

LMSA14

LMSA13

LMSA12

LMSA11

LMSA10

LMSA9

LMSA8

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

After reset
Function

LSAMH
(02A2H)

0

LCD main area start address (A15-A8)
7

6

5

4

3

2

1

0

bit Symbol

LMSA23

LMSA22

LMSA21

LMSA20

LMSA19

LMSA18

LMSA17

LMSA16

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

1

0

0

0

0

0

0

After reset
Function

LCD main area start address (A23-A16)

Note: When assigned internal RAM as VRAM, A1 signal cannot be used. Every 4bytes setting is needed.
LCD Sub Area Start Address Register

LSASL
(02A4H)

bit Symbol

7
LSSA7

6
LSSA6

5
LSSA5

4
LSSA4

3
LSSA3

2
LSSA2

1
LSSA1

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

Function

LSASM
(02A5H)

LCD sub area start address (A7-A1)
7

6

5

4

3

2

1

0

bit Symbol

LSSA15

LSSA14

LSSA13

LSSA12

LSSA11

LSSA10

LSSA9

LSSA8

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Function

LSASH
(02A6H)

0

LCD sub area start address (A15-A8)
7

6

5

4

3

2

1

0

bit Symbol

LSSA23

LSSA22

LSSA21

LSSA20

LSSA19

LSSA18

LSSA17

LSSA16

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

1

0

0

0

0

0

0

Function

LCD sub area start address (A23-A16)

Note: When assigned internal RAM as VRAM, A1 signal cannot be used. Every 4bytes setting is needed.

92CZ26A-515

TMP92CZ26A
LCD Sub Area HOT Point Register (X-dir)

LSAHX
(02A8H)

7

6

5

4

3

2

1

0

bit Symbol

SAHX7

SAHX6

SAHX5

SAHX4

SAHX3

SAHX2

SAHX1

SAHX0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

7

6

5

Function

(02A9H)

LCD sub area HOT point (7-0)

1

0

bit Symbol

4

3

2

SAHX9

SAHX8

Read/Write

R/W

R/W

After reset

0

0

LCD sub area HOT

Function

point (9-8)
LCD Sub Area HOT Point Register (Y-dir)

LSAHY
(02AAH)

7

6

5

4

3

2

1

0

bit Symbol

SAHY7

SAHY6

SAHY5

SAHY4

SAHY3

SAHY2

SAHY1

SAHY0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

7

6

5

2

1

Function

(02ABH)

LCD sub area HOT point (7-0)

4

3

0

bit Symbol

SAHY8

Read/Write

R/W

After reset

0
LCD sub
area HOT
point (8)

Function

LCD Sub Area Display Segment Size Register

7

6

5

4

3

2

1

0

LSASS

bit Symbol

SAS7

SAS6

SAS5

SAS4

SAS3

SAS2

SAS1

SAS0

(02ACH)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

2

1

0

bit Symbol

SAS9

SAS8

Read/Write

R/W

R/W

Function

LCD sub area segment size (7-0)

7
(02ADH)

6

5

4

3

After reset

0
0
LCD sub area segment
size (9-8)

Function

LCD Sub Area Display Common Size Register

7

6

5

4

3

2

1

0

LSACS

bit Symbol

SAC7

SAC6

SAC5

SAC4

SAC3

SAC2

SAC1

SAC0

(02AEH)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

2

1

0

Function

LCD sub area common size (7-0)

7
(02AFH)

6

5

4

3

bit Symbol

SAC8

Read/Write

R/W

After reset

0

Function

LCD sub area common size (8)

92CZ26A-516

TMP92CZ26A

3.19.3 Description of Operation
3.19.3.1

Outline

After the required settings such as the operation mode, display data memory address,
color mode, and LCD size are specified, the start register is set to start the LCDC
operation.
The LCDC issues a bus request to the CPU. When the bus is granted, the LCDC
reads data of the display size from the display RAM, stores the data in the FIFO
buffer in the LCDC, and then returns the bus to the CPU.
The display data in the FIFO buffer is transferred to the LCD driver via a dedicated
bus (LD pin). At this time, control pins (such as LCP0) that are connected to the LCD
driver also output specified waveforms in synchronization with the transfer of display
data.
Note:

While display RAM data is being read, the CPU operation is halted by the internal BUSREQ signal.
Therefore, the CPU stop time must be taken into account in programming.

External SDRAM, SRAM, or internal RAM (288 Kbytes) can be used as the display
RAM. Since the internal RAM allows very fast accesses (32-bit bus, 2-1-1-1 read/write),
it enables data transfer to the LCD driver (DMA operation) with the minimum CPU
stop time. Using the internal RAM also greatly reduces power consumption during
LCD display.
3.19.3.2

Display Memory Mapping

Since the number of bits needed to display one pixel varies even for the same display
size depending on the selected color mode, the required display RAM size also varies
with each color mode. (The color mode can be selected from a range of monochrome to
16777216 colors.)
In monochrome mode, one pixel of display data corresponds to one bit of display RAM
data. Likewise, the number of display RAM data used for displaying one pixel in each
color mode is as follows:
4-grayscale

1 pixel = 2 bits

16-grayscale

1 pixel = 4 bits

64-grayscale

1 pixel = 6 bits

STN 256-color

1 pixel = 8 bits

STN 4096-color

1 pixel = 12 bits

STN 65536-color

1 pixel = 16 bits

STN 256K-color

1 pixel = 16 bits (not 18 bits)

STN 16M-color

1 pixel = 24 bits

For example, a 320-segment x 240-common display in 4-grayscale mode requires
19200 bytes of display RAM space (320 × 240 × 2 = 152600 bits = 19200 bytes).
For details, refer to “Memory Map Image and Data Output in Each Display Mode”
later in this chapter.

92CZ26A-517

TMP92CZ26A

3.19.3.3

Basic Operation

The following diagram shows the basic timings of the waveforms generated by the
LCDC and adjustable elements. The adjustable elements for each signal include enable
time, phase, and delay time.
The signals used and their connections and settings vary with the LCD driver type
(STN/TFT) and specifications to be used.
Signal Name

Frame period (Refresh rate)

LVSYNC signal
(Enable width control)
(Phase control)

(Enable width control)

(Phase control)

(Enable width control)
LHSYNC signal
(Phase control)

LLOAD signal
LGOEn signal
(Enable width control)
(Phase control)
(Delay control)

LFR signal (FREDGE=0)

(Delay control)

(Line divide)

(Frame divide control)

(Dot divide)

(Line)
(Dot)

LFR signal (FREDGE=1)
(Line divide)
(Dot divide)

DLS=0 (Line inversion)

LLOAD signal

LLOAD signal details
(Valid data output)
LCP0 signal
(Only at valid data output)
(Always output)
(Phase control)

LD23-LD0 signal
LDINV signal

92CZ26A-518

TMP92CZ26A

3.19.3.4

Reference Clock LCP0

LCP0 is used as the reference clock for all the signals in the LCDC.
This section explains how to set the frequency (period) of the LCP0 signal.
The LCP0 clock speed (LD bus transfer speed) is determined by selecting TFT or STN
and setting LCDMODE0 and LCDMODE1. The clock speed should
be selected to meet the characteristics of the LCD driver to be used.
The LCP0 period can be selected from four types: fSYS/2, fSYS/4, fSYS/8, fSYS/16, fSYS/24 and
fSYS/48.
Internal signal (fsys)
LCP0
fsys / 2
LD23-LD0
LCP0
fsys / 4
LD23-LD0

LCP0

fsys /48

LD23-LD0

Figure 3.19.1 LCP Frequency Selection
Minimum speed
The LCP0 period needs to be short enough to prevent the next line signal from
overlapping the current line signal.
The transfer speed of display data must be set to suit the refresh rate; otherwise data
cannot be transferred properly. Set the data transfer speed so that each transfer
completes within the LHSYNC period.
STN monochrome/grayscale

:

Segment size / 8 × LCP0 [s: period] < LHSYNC [s: period] STN color

STN color

:

Segment size × 3 / 8 LCP0 [s: period] < LHSYNC [s: period]

TFT

:

Segment size × LCP0 [s: period] < LHSYNC [s: period]

Maximum speed
If the LCP0 period is too short, the data to be transferred to the LCD driver cannot be
prepared in time, causing wrong data to be transferred. The maximum transfer speed
is limited by the operation mode and display RAM type (bus width, wait condition, and
so on). If the data rotation function is used, the transfer speed must be slower.

92CZ26A-519

TMP92CZ26A

LCP0 Setting Range Table
Conditions
fSYS
: 60 MHz
Display size (color)
: up to 320 × 320
Display size (monochrome/grayscale) : up to 640 × 480
Note:

This table shows the range of LCP0 settings that can be made under the conditions shown above. If the
CPU clock speed, display size, or refresh rate is changed, the LCP0 range also changes.
Display RAM
Internal RAM

External
SRAM
(0 waits)

SDRAM

Display Mode
STN monochrome
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

STN 4-grayscale
Refresh cycle = 70 Hz
STN 16-grayscale
Refresh cycle = 140 Hz
STN 64-grayscale
Refresh cycle = 200 Hz
STN 256-color
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16
fSYS/2
to fSYS/8

fSYS/2
to fSYS/16
fSYS/2
to fSYS/8

fSYS/2
to fSYS/16
fSYS/4
to fSYS/8

fSYS/4

fSYS/4

fSYS/4

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/4
to fSYS/16

STN 4K-color
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/4
to fSYS/16

TFT 4K-color
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16

fSYS/2
To fSYS/16

fSYS/2
to fSYS/16

TFT 64K-color
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

TFT 64K-color
+ rotation operation

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

TFT 256K-color
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/4
to fSYS/16

TFT 16M-color
Refresh cycle = 70 Hz

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

fSYS/2
to fSYS/16

92CZ26A-520

External SRAM
(N waits)
fSYS/4 tofSYS/16 (up to 2 waits)
fSYS/8 to fSYS/16 (up to 6 waits)
fSYS/16 (up to 14 waits)
fSYS/4 to fSYS/8 (up to 2 waits)
fSYS/8 (up to 6 waits)
fSYS/8 to fSYS/16 (up to 2 waits)
fSYS/16 (up to 6 waits)
fSYS/4 (up to 1 wait)
fSYS/8 to fSYS/16 (up to 2 waits)
fSYS/16 (up to 6 waits)
fSYS/4 to fSYS/16 (up to 2 waits)
fSYS/8 to fSYS/16 (up to 6 waits)
fSYS/16 (up to 14 waits)
fSYS/4 to fSYS/16 (up to 2 waits)
fSYS/8 to fSYS/16 (up to 6 waits)
fSYS/16 (up to 14 waits)
fSYS/4 to fSYS/16 (up to 2 waits)
fSYS/8 to fSYS/16 (up to 6 waits)
fSYS/16 (up to 14 waits)
fSYS/4 to fSYS/16 (up to 2 waits)
fSYS/8 to fSYS/16 (up to 6 waits)
fSYS/16 (up to 14 waits)
fSYS/8 to fSYS/16 (up to 2 waits)
fSYS/16 (up to 2 waits)
fSYS/4 to fSYS/16 (up to 2 waits)
fSYS/8 to fSYS/16 (up to 2 waits)
fSYS/16 (up to 2 waits)

TMP92CZ26A

Example 1: When fSYS = 10 MHz, STN mode, LCDMODE0 = 01
Internal reference clock LCP0 = fSYS / 8 = 10 MHz / 8 = 1.25 [MHz]
LCP0 period = 1 / 1.25 [MHz] = 0.8 [μS]
Example 2: when fSYS = 60 MHz, TFT mode, LCDMODE0 = 11
Internal reference clock LCP0 = fSYS / 16 = 60 MHz / 16 = 3.75 [MHz]
LCP0 period = 1 / 3.75 [MHz] = 266 [nS]

LCDMODE0 Register
7
bit Symbol
LCDMODE0
(0280H)

6

5

4

3

2

1

0

SCPW1

SCPW0

MODE3

MODE2

MODE1

MODE0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

1

1

0

0

0

0

RAMTYPE1 RAMTYPE0

Display RAM

LD bus transfer speed

Mode selection
0000: Reserved

00: Internal RAM
(32-bit)
01: External SRAM
Function

10: SDRAM
11: Reserved

SCPW2= 0
00: 2-clk
01: 4-clk
10: 8-clk
11: 16-clk
SCPW2= 1
00: 6-clk
01: 12-clk

1000: Reserved

0001: SR (mono)

1001: Reserved

0010: SR (4-gray)

1010: TFT (256-color)

0011: Reserved

1011: TFT (4096-color)

0100: SR (16-gray)
0101: SR (64-gray)

1100: TFT (64K-color)
1101: TFT(256K-,16M-color)

0110: STN (256-color) 1110: Reserved
0111: STN (4096-color) 1111: Reserved

10: 24-clk
11: 48-clk

92CZ26A-521

TMP92CZ26A

LCDCTL0  is used to control the output timing of the LCP0 signal. When
=0, the LCP0 signal is always output. When =1, the LCP0
signal is output only when valid data is output.

LCP0 signal LCP0OC=1
LCP0 signal LCP0OC=0

LCD Control 0 Register
7

6

5

4

2

1

0

LCDCTL0

bit Symbol

PIPE

ALL0

FRMON

–

DLS

LCP0OC

START

(0285H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

After reset

0
PIP function

0
Segment

Frame divide Always

data

setting

3

0

write “0”

0: Disable
1: Enable

Function

FR signal

LCP0 (Note) LCDC

LCP0/Line

0: Always

selection
0: Normal

0: Disable

1: Always

1: Enable

1: At valid
0: Line

output “0”

1: LCP0

operation

output
data only

0: Stop
1: Start

LLOAD
width
0: At setting
in register
1: At valid
data only

Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of  bit.

The phase of the LCP0 signal can be inverted by the setting of LCDCTL1.

LVSYNC
LHSYNC
LLOAD
LGOEn
LFR
All signal changes
LCP0P=0

LCP0

LCP0P=1

LCP0
LD23-LD0
LCD Control 1 Register

LCDCTL1
(0286H)

7

6

5

4

1

0

bit Symbol

LCP0P

LHSP

LVSP

LLDP

LVSW1

LVSW0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

1

0

1

0

0

0

Function

3

2

LCP0

LHSYNC

LVSYNC

LLOAD

LVSYNC

phase

phase

phase

phase

enable time control

0: Rising

0: Rising

0: Rising

0: Rising

01 : 2 clocks of LHSYNC

1: Falling

1: Falling

1: Falling

1: Falling

10 : 3 clocks of LHSYNC

00 : 1 clock of LHSYNC

11 : Reserved

92CZ26A-522

TMP92CZ26A

3.19.3.5

Refresh Rate

The period of the horizontal synchronization signal LHSYNC is defined as the
product of the value set in LCDHSP and the LCP0 clock period.
The value to be set in LCDHSP is obtained as follows:
TFT
Segment size + number of dummy clocks (*)
STN
Monochrome/grayscale : (Segment size / 8) + number of dummy clocks (*)
Color
: (Segment size × 3 / 8) + number of dummy clocks (*)
LHSYNC [s: period] = LCP0 [s: period] × ( + 1)
LCD LHSYNC Pulse Register

LCDHSP

bit Symbol

(028AH)

Read/Write
After reset

7

6

5

4

LH7

LH6

LH5

LH4

2

1

0

LH3

LH2

LH1

LH0

0

0

0

0

W
0

0

0

Function
(028BH)

3

0

LHSYNC period (bits 7–0)

bit Symbol

7

6

5

4

3

2

1

0

LH15

LH14

LH13

LH12

LH11

LH10

LH9

LH8

0

0

0

0

0

0

0

0

Read/Write
After reset

W

Function

LHSYNC period (bits 15-8)

The period of the vertical synchronization signal LVSYNC is defined as the product of
the value set in LCDVSP and the LHSYNC period.
The value to be set in LCDVSP is obtained as follows:
TFT
Common size + number of dummy clocks (*)
STN
Common size + number of dummy clocks (*)
(A minimum of one dummy clock must be inserted in the back
porch.)
LVSYNC [s: period] = LHSYNC [s: period] × ( + 1)
= LCP0 [s: period] × ( + 1) × ( + 1)
LCD V SYNC Pulse Register

LCDVSP

bit Symbol

(028CH)

Read/Write
After reset

7

6

5

4

LVP7

LVP6

LVP5

LVP4

2

1

0

LVP3

LVP2

LVP1

LVP0

0

0

0

0

W
0

0

0

Function

0

LVSYNC period (bits 7-0)
7

(028DH)

3

6

5

4

3

bit Symbol

2

1

0

LVP9

LVP8

Read/Write

W

After reset
Function

0
LVSYNC period (bits 9-8)

92CZ26A-523

0

TMP92CZ26A

• Insertion of dummy clocks

Note: At least two LCP0 pulses
must be inserted.

Reference LHSYNC
(Delay=0)
LVSYNC
LHSYNC
(with delay)

LCP0
LD23-0

Vertical Front Porch

Horizontal Front
Porch

Horizontal back
Porch

Vertical back Porch

The above is a conceptual diagram showing the data (LD23-0), shift clock (LCP0),
horizontal synchronization signal (LHSYNC), and vertical synchronization signal
(LVSYNC) on the LCD panel.
The front porch and back porch as shown above should be taken into consideration in
setting LCDHSP and LCDVSP explained earlier.
Note 1: The horizontal back porch must be set so that “data transfer” plus “LCP0 × 2 clocks” are completed
within one period of the reference clock LHSYNC (with 0 delay), as defined by the following equation:
Delay time (LLOAD) + number of data transfer times + 2 < LHSYNC (LCP0 pulse count)
Note 2: The vertical back porch must have a minimum of one dummy clock.

(*) TFT driver
The recommended number of dummy clocks is specified by each TFT driver (or LCD module). Refer to the
specifications of the TFT driver (LCD module) to be used.
(*) STN driver
For an STN driver, the refresh rate can be set accurately by adjusting the value of the horizontal back porch. If the
desired refresh rate cannot be obtained by the horizontal back porch, it can be further adjusted by the vertical back porch.
For details, refer to the setting example to be described later in this section.

92CZ26A-524

TMP92CZ26A
•

Setting method
The front dummy LHSYNC (vertical front porch) not accompanied by valid data in
the total of LHSYNC period in the LVSYNC period is defined by the value set in
LCDPRVSP.
Front dummy LHSYNC (vertical front porch) = 
The back dummy LHSYNC (vertical back porch) is defined as follows:
( + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC:
)
The vertical back porch must have a minimum of one dummy clock.
The front dummy LCP0 (horizontal front porch) not accompanied by valid data in the
total number of LCP0 clocks in the LHSYNC period is defined by the value set in
LCDLDDLY.
Front dummy LCP0 (horizontal front porch) = 
The back dummy LCP0 (horizontal back porch) is defined as follows:
( + 1) − (valid LCP0: segment size) − (front dummy LCP0: )
Note 1:

The back dummy LCP0 (horizontal back porch) must have a minimum of two LCP0 clocks.

Note 2:

The delay time that is set in LCDLDDLY is counted based on LHSYNC (with 0 delay).

7

6

5

4

3

2

1

0

LCDLDDLY

bit Symbol

PDT

LDD6

LDD5

LDD4

LDD3

LDD2

LDD1

LDD0

(0290H)

Read/Write

R/W

0

0

0

After reset

0

Function

Data output
timing
0: Sync with
LLOAD
1: 1 clock later
than LLOAD

W
0

0

0

0
LLOAD delay (bits 6-0)

Example 1) Setting the refresh rate to 200 Hz under the following conditions:
fSYS = 30 MHz, STN mode, 320-segment × 240-common, 4096-color display,
LCDMODE0 = 00
Internal reference clock LCP0 = fSYS / 4 = 30 [MHz] / 4 = 7.5 [MHz]
Therefore, LCP0 period = 1 / 7.5 [MHz] = 0.133 [μS]
Condition 1: Refresh rate = 200 Hz, Refresh cycle = 5 [ms
Condition 2: LH =  ≥ (320×3/8) − 1 = 119
Condition 3: LV =  ≥ 240 − 1
When  = 239 (minimum value):
LVSYNC [s: period]

= LHSYNC [s: period] × ( + 1)
= LCP0 [s: period] × ( + 1) × ( + 1)

5 [ms]

= (1 / 7.5 [MHz]) × (LH + 1) ×240

LH + 1

= (5 × 10 ) × (7.5 × 10 ) / 240
-3

6

= 156.25

92CZ26A-525

TMP92CZ26A

3.19.3.6

Signal Settings

Signal Name
LCP0 signal

LVSYNC signal

Front dummy LHSYNC
(Vertical front porch)

Valid LHSYNC

Back dummy LHSYNC

(Common size)

(Vertical back porch)

LHSYNC signal
LGOEn signal

FR signal

LLOAD signal

LLOAD signal
LCP0 signal
LD23-LD0 signal
LDINV signal

The above diagram shows the typical timings of the signals controlled by the LCDC.
This section explains how to control each of these signals.

92CZ26A-526

TMP92CZ26A

1. LVSYNC Signal
The period of the vertical synchronization signal LVSYNC indicates the time for each
screen update (refresh rate). The LVSYNC period is defined as an integral multiple of
the period of the horizontal synchronization signal LHSYNC.
The LVSYNC period is calculated as the product of the value set in LCDVSP
and the LHSYNC period. The value to be set in LCDVSP should be “common
size + number of dummy clocks” or larger for TFT and STN.
= LHSYNC [s: period] × ( + 1)
= LCP0 [s: period] × ( + 1) × ( + 1)

LVSYNC [s: period]

LCD V SYNC Pulse Register
LCDVSP

bit Symbol

(028CH)

Read/Write
After reset

7

6

5

4

LVP7

LVP6

LVP5

LVP4

2

1

0

LVP3

LVP2

LVP1

LVP0

0

0

0

0

W
0

0

0

0

Function

LVSYNC period (bits 7-0)
7

(028DH)

3

6

5

4

3

2

bit Symbol

1

0

LVP9

LVP8

Read/Write

W

After reset

0

0

LVSYNC period

Function

(bits 9-8)

The enable width of the LVSYNC signal can be specified as 1 clock, 2 clocks, or 3
clocks of LHSYNC in LCDCTL1.
The phase of the LVSYNC signal can be inverted by the setting of LCDCTL1
.
Refresh rate
(Enable width control)
LVSP=0
(Phase control)
LVSP=1
LVSYNC signal

LCD Control 1 Register

LCDCTL1
(0286H)

7

6

5

4

1

0

bit Symbol

LCP0P

LHSP

LVSP

LLDP

LVSW1

LVSW0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

1

0

1

0

0

0

Function

3

2

LCP0

LHSYNC

LVSYNC

LLOAD

LVSYNC

phase

phase

phase

phase

enable time control

0: Rising

0: Rising

0: Rising

0: Rising

01 : 2 clocks of LHSYNC

1: Falling

1: Falling

1: Falling

1: Falling

10 : 3 clocks of LHSYNC

00 : 1 clock of LHSYNC

11 : Reserved

92CZ26A-527

TMP92CZ26A

2. LHSYNC Signal
The period of the horizontal synchronization signal LHSYNC corresponds to one line
of display. The LHSYNC period is defined as an integral multiple of the reference
clock signal LCP0.
The LHSYNC period is defined as the product of the value set in LCDHSP
and the LCP0 clock period. The value to be set in LCDHSP should be
“segment size + number of dummy clocks” or larger for TFT. In the case of STN, the
minimum value of LCDHSP is:
: (Segment size / 8) + number of dummy clocks
: (Segment size × 3 / 8) + number of dummy clocks

Monochrome/grayscale
Color

LHSYNC [s: period] = LCP0 [s: period] × ( + 1)
LCD LHSYNC Pulse Register
LCDHSP

bit Symbol

(028AH)

Read/Write
After reset

7

6

5

4

3

2

1

0

LH7

LH6

LH5

LH4

LH3

LH2

LH1

LH0

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

LH15

LH14

LH13

LH12

LH11

LH10

LH9

LH8

0

0

0

0

0

0

0

0

W

Function

(028BH)

LHSYNC period (bits 7-0)

bit Symbol
Read/Write
After reset

W

Function

LHSYNC period (bits 15-8)

The enable width of the LHSYNC signal can be specified by LCDHSW. It
is also possible to set the delay time for the LVSYNC signal in units of LCP0 pulses.
LHSYNC signal
(Enable width control)

(Phase control)

(Delay control)

92CZ26A-528

TMP92CZ26A

The enable width of the LHSYNC signal is set using LCDHSW. It can be
specified in a range of 1 to 512 pulses of the LCP0 clock.
The enable width is represented by the following equation:
Enable width =  + 1
Thus, when LCDHSW is set to “0”, the enable width is set as one pulse of
the LCP0 clock.
Signal Name
LCP0

LHSYNC signal

High width setting
LCP0 clock = 1, 2, 3 … 512 pulses

LCDHSW Register

LCDHSW

bit Symbol

(0294H)

Read/Write
After reset

7

6

5

4

3

2

1

0

HSW7

HSW6

HSW5

HSW4

HSW3

HSW2

HSW1

HSW0

0

0

0

0

0

0

0

0

W

Function

LCDHWB8

bit Symbol

(0299H)

Read/Write
After reset
Function

LHSYNC width (bits 7-0)

7

6

5

4

3

2

1

0

O2W9

O2W8

O1W9

O1W8

O0W8

LDW9

LDW8

HSW8

0

0

0

0

0

0

0

0

W
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)

LGOE0
width (bit 8)

92CZ26A-529

LLOAD width (bits 9-8)

LHSYNC
width (bit 8)

TMP92CZ26A
As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
inserted in the LHSYNC signal.
Delay time = 
Signal Name
LCP0 signal

LVSYNC signal

Reference LHSYNC
(with 0 delay)
LHSYNC signal
Delay control 1
LCDHSDLY Register
7
LCDHSDLY

bit Symbol

(028FH)

Read/Write

6

5

4

3

2

1

0

HSD6

HSD5

HSD4

HSD3

HSD2

HSD1

HSD0

0

0

0

0

0

0

W

After reset
Function

0

LHSYNC delay (bits 6-0)

The phase of the LHSYNC signal can be inverted by the setting of LCDCTL1
.
LHSYNC period
LHSYNC signal
(Enable width control)
LHSP=0
(Phase control)
LHSP=1

LCD Control 1 Register
7

6

5

4

1

0

LCDCTL1

bit Symbol

LCP0P

LHSP

LVSP

LLDP

LVSW1

LVSW0

(0286H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

0

0

After reset

Function

1

0

1

0

3

2

LCP0

LHSYNC

LVSYNC

LLOAD

LVSYNC

phase

phase

phase

phase

enable time control

0: Rising

0: Rising

0: Rising

0: Rising

01 : 2 clocks of LHSYNC

1: Falling

1: Falling

1: Falling

1: Falling

10 : 3 clocks of LHSYNC

00 : 1 clock of LHSYNC

11 : Reserved

92CZ26A-530

TMP92CZ26A

3. LLOAD Signal
The LLOAD signal is used to control the timing for the LCD driver to receive display
data. The period of the LLOAD signal synchronizes to one line of display. It is defined
as an integral multiple of the reference clock LCP0.
Refresh rate
Front dummy LHSYNC
(Vertical front porch)

LLOAD: Common size
(Valid data)

Back dummy LHSYNC
(Vertical back porch)

LVSYNC signal

LHSYNC signal

LLOAD signal

LD23-LD0 signal
LLOAD signal
LLOAD signal LCDLDDLY = 1
LCP0 signal
LD23-LD0 signal
LDINV signal

The LHSYNC signal and LLOAD signal differs in that the LHSYNC signal is output
all the time whereas the LLOAD signal is output only at valid data lines (commons).
Display data is output in synchronization with the LLOAD signal. Therefore, if a
delay is inserted in the LLOAD signal through the LCDLDDLY register, data output
is also delayed.
Also note that when LCDLDDLY=1 , data is output one LCP0 clock later than
the LLOAD signal.
LCDLDDLY=0: Data is output in synchronization with the LLOAD signal.
LCDLDDLY=1: Data is output one LCP0 clock later than the LLOAD signal.
The delay time for the LLOAD signal is controlled based on LCDLDDLY=1.
Therefore, even if the delay time is set to “0” with LCDLDDLY=0, the LLOAD
signal is output with a delay of one LCP0 clock. Be careful about this point.

92CZ26A-531

TMP92CZ26A

The number of pulses in the front dummy LHSYNC (vertical front porch) is specified
by LCDPRVSP. This delay time can be set in a range of 0 to 127 pulses of
the LCP0 clock.
Front dummy LHSYNC = 
LCD LVSYNC Pre Pulse Register

7
LCDPRVSP

bit Symbol

(028EH)

Read/Write

6

5

4

3

2

1

0

PLV6

PLV5

PLV4

PLV3

PLV2

PLV1

PLV0

0

0

0

W

After reset

0

0

0

Function

0

Front dummy LVSYNC (bits 6-0)

The back dummy LHSYNC (vertical back porch) is defined as follows:
( + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC:
)
Signal Name
LCP0

LLOAD signal

High width setting
LCP0 clock = 1, 2, 3 … 1023 pulses (=0) / 1024 pulses (=1)
Note: The vertical back porch must be set to “1” or longer in all the cases (STN/TFT).

The enable width of the LLOAD signal is determined depending on the
LCDCTL0 setting, as shown below.
LCDCTL0 = 0 : Output at setting value in (LCDDLW) 
LCDCTL0 = 1 : Output at valid data
LCD Control 0 Register
7

6

5

4

2

1

0

LCDCTL0

bit Symbol

PIPE

ALL0

FRMON

–

DLS

LCP0OC

START

(0285H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

After reset

0
PIP function

0
Segment

Frame divide Always

data

setting

write “0”

0: Disable
1: Enable

Function

3

0
FR signal

LCP0 (Note) LCDC

LCP0/Line

0: Always

selection
0: Normal

0: Disable

1: Always

1: Enable

output “0”

1: At valid
0: Line
1: LCP0

data only
LLOAD
width
0: At setting
in register
1: At valid
data only

Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of  bit.

92CZ26A-532

operation

output
0: Stop
1: Start

TMP92CZ26A

The enable width of the LLOAD signal is specified using LCDLDW. It can
be set in a range of 0 to 1024 pulses of the LCP0 clock.
The actual enable width is determined depending on the LCDLDDLY setting,
as shown below.
Enable width =  + 1 (when  = 1, =0 is prohibited)
Enable width = 
(when  = 0)
LCDLDW Register
LCDLDW

bit Symbol

(0295H)

Read/Write
After reset

7

6

5

4

3

2

1

0

LDW7

LDW6

LDW5

LDW4

LDW3

LDW2

LDW1

LDW0

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

O2W9

O2W8

O1W9

O1W8

O0W8

LDW9

LDW8

HSW8

0

0

0

0

0

0

W

Function
LCDHWB8

bit Symbol

(0299H)

Read/Write
After reset

LLOAD width (bits 7-0)

W
LGOE2 width (bits 9-8)

LGOE1 width (bits 9-8)

0
LGOE0

Function

LLOAD width (bits 9-8)

0
LHSYNC

width

width

(bit 8)

(bit 8)

When LCDCTL0=1, the enable width of the LLOAD signal is shown
below.

LLOAD

LCDLDDLY = 0

LLOAD

LCDLDDLY = 1

LCP0
LD23-LD0

92CZ26A-533

TMP92CZ26A

As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
inserted in the LLOAD signal.
Delay time = 
Signal Name
LCP0 signal

LLVSYNC signal

LHSYNC signal
(Internal reference signal)
LLOAD signal
Delay control

Note:

The delay time for the LLOAD signal is controlled based on LCDLDDLY=1. Therefore, even if the
delay time is set to”0” with LCDLDDLY=0, the LLOAD signal is output with a delay of one LCP0
clock. Be careful about this point.
LCDLDDLY Register

LCDLDDLY bit Symbol
(0290H)

Read/Write

7

6

5

4

3

2

1

0

PDT

LDD6

LDD5

LDD4

LDD3

LDD2

LDD1

LDD0

0

0

0

R/W

After reset

0

Function

Data output
timing
0: Sync with
LLOAD
1: 1 clock later
than LLOAD

W
0

0

0

0
LLOAD delay (bits 6-0)

The phase of the LLOAD signal can be inverted by the setting of LCDCTL1 .
LLOAD period
(Enable width control)
LLDP=0
(Phase control)
LLDP=1
LLOAD signal
LCD Control 1 Register
LCDCTL1 bit Symbol
(0286H)

7

6

5

4

3

2

1

0

LCP0P

LHSP

LVSP

LLDP

LVSW1

LVSW0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

After reset

1

0

1

0

0

0

Function

LCP0

LHSYNC

LVSYNC

LLOAD

LVSYNC

phase

phase

phase

phase

enable time control

0: Rising

0: Rising

0: Rising

0: Rising

01 : 2 clocks of LHSYNC

1: Falling

1: Falling

1: Falling

1: Falling

10 : 3 clocks of LHSYNC

00 : 1 clock of LHSYNC

11 : Reserved

92CZ26A-534

TMP92CZ26A

4. LGOE0 to LGOE2 Signals
The LCDC has three signals (LGOE0 to LGOE2) that can be controlled like the
LHSYNC signal. For these signals, the enable width, delay time, and phase timing can
be adjusted as shown below.
Signal Name
LCP0

LGOE0 signal
LGOE1 signal
LGOE2 signal
High width setting
LGOE0: LCP0 clock = 1, 2, 3 … 512 pulses
LGOE1: LCP0 clock = 1, 2, 3 … 1024 pulses
LGOE2: LCP0 clock = 1, 2, 3 … 1024 pulses

LCDHO0W

bit Symbol

(0296H)

Read/Write
After reset

7

6

5

4

O0W7

O0W6

O0W5

O0W4

LCDHO1W
(0297H)

Read/Write
After reset

0

0

0

LCDHO2W
(0298H)

Read/Write
After reset

0

bit Symbol

(0299H)

Read/Write
After reset

0

O0W3

O0W2

O0W1

O0W0

0

0

0

0

7

6

5

4

3

2

1

0

O1W7

O1W6

O1W5

O1W4

O1W3

O1W2

O1W1

O1W0

0

0

0

0

0

0

0

0

W
LGOE1 width (bits 7-0)
7

6

5

4

3

2

1

0

O2W7

O2W6

O2W5

O2W4

O2W3

O2W2

O2W1

O2W0

0

0

0

0

0

0

0

0

3

2

1

0

O0W8

LDW9

LDW8

HSW8

0

0

W

Function

LCDHWB8

1

LGOE0 width (bits 7-0)

Function

bit Symbol

2

W

Function

bit Symbol

3

LGOE2 width (bits 7-0)
7

6

5

4

O2W9

O2W8

O1W9

O1W8
W

0

0

LGOE2 width (bits 9-8)

0

0

LGOE1 width (bits 9-8)

Function

92CZ26A-535

0
LGOE0

LLOAD width (bits 9-8)

0
LHSYNC

width

width

(bit 8)

(bit 8)

TMP92CZ26A
Signal Name
LCP0 signal

LVSYNC signal

LHSYNC signal
(Internal reference signal)
LGOE0 signal
Delay control

7
LCDO0DLY bit Symbol
(0291H)
Read/Write

6

5

4

3

2

1

0

OE0D6

OE0D5

OE0D4

OE0D3

OE0D2

OE0D1

OE0D0

0

0

0

0

0

0

W

After reset
Function
7
LCDO1DLY bit Symbol
(0292H)

0
OE0 delay (bits 6-0)

6

5

4

3

2

1

0

OE1D6

OE1D5

OE1D4

OE1D3

OE1D2

OE1D1

OE1D0

0

0

0

Read/Write

W

After reset

0

0

0

Function
7
LCDO2DLY bit Symbol
(0293H)
Read/Write
After reset
Function

0
OE1 delay (bits 6-0)

6

5

4

3

2

1

0

OE2D6

OE2D5

OE2D4

OE2D3

OE2D2

OE2D1

OE2D0

0

0

0

W
0

0

0

0
OE2 delay (bits 6-0)

92CZ26A-536

TMP92CZ26A
LGOEn signal
LGOEnP=0
(Phase control)
LGOEnP=1
LCD Control 2 Register
LCDCTL2
(0287H)

7

6

5

bit Symbol

LGOE2P

LGOE1P

LGOE0P

Read/Write

R/W

R/W

R/W

After reset

0

0

0

Function

LGOE2

LGOE1

LGOE0

phase

phase

phase

0: Rising

0: Rising

0: Rising

1: Falling

1: Falling

1: Falling

4

92CZ26A-537

3

2

1

0

TMP92CZ26A

5. LFR Signal
The LFR (frame) signal is used to control the direction of bias the LCD driver applies
on liquid crystal cells. With small screens in monochrome mode, the polarity of the LFR
signal is normally inverted in synchronization with each screen display. With large
screens or when grayscale or color mode is used, the polarity is inverted at shorter
intervals to adjust the display quality.
When LCDCTL0=“1” and LCDCTL0 = “0”, the LFR signal is
inverted at intervals of “LHSYNC x N” (LHSYNC: internal reference signal with 0
delays). The “N” value is specified in LCDDVM0 and LCDDVM1.
When ="0" and =0, LFR signal synchronous with front edge of
LHSYNC signal, and when ="0" and =1, LFR signal synchronous
with rear edge of LHSYNC signal.
When LCDCTL0 is set to “0” to disable the frame divide function, the LFR
signal is inverted in synchronization with the LVSYNC period.
Enabling this function does not affect the waveform and timing of the LVSYNC
signal. (The refresh rate is not changed.)
Note1: The effect of this function varies with the characteristics of the LCD driver and LCD panel to be used.
Note2: LFR signal delaies synchronous with LHSYNC signal.
Generally, setting a prime number (3, 5, 7, 11, 13 and so on) as the “N” value produces better results.

LVSYNC

LFR
=0
 = 0
N

N

LHSYNC
LFR
=0
= 1
 = N
 = any
 = 0
LFR
=1
 = 0

LFR
=1
= 1
 = N
 = any
 = 0

92CZ26A-538

TMP92CZ26A

When LCDCTL0=1 and LCDCTL0=1, frame output is inverted at
intervals set in LCDDVM0 and the LFR signal is inverted at intervals of
“LCP0 × M”. The “M” value is specified in LCDDVM0.
When ="1" LFR signal synchronous with front edge of LHSYNC signal.
So, prohibit to set =1, always need to set =0.

LVSYNC

N
LHSYNC

LHSYNC (Expansion)
M

M

LCP0
LFR
=0
 = 1
 = N
 = M
 = 1

Note

prohibit to set =1, always need to set =0.

92CZ26A-539

TMP92CZ26A

LCD Control 0 Register
7

6

5

4

2

1

0

LCDCTL0

bit Symbol

PIPE

ALL0

FRMON

–

DLS

LCP0OC

START

(0285H)

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

3

0

0

PIP

Segment

Frame

Always

LFR signal

LCP0 (Note)

LCDC

function

data

divide

write “0”

LCP0/line

0: Always

operation

setting

setting

selection

output

0:Disable

0: Normal

1:Enable

1: Always

0: Disable

output “0”

1: Enable

Function

0

0:Line
1:LCP0

1: At valid
data only

0

0: Stop
1: Start

LLOAD
width
0: At setting
in register
1: At valid
data only

Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of  bit.

Divide FRM 0 Register

LCDDVM0

bit Symbol

(0283H)

Read/Write
After reset

7

6

5

4

3

2

1

0

FMP3

FMP2

FMP1

FMP0

FML3

FML2

FML1

FML0

0

0

0

0

0

0

0

0

R/W

Function

LCDDVM1

bit Symbol

(0284H)

Read/Write
After reset
Function

LCP0 DVM (bits 3-0) (M)

LHSYNC DVM (bits 3-0) (N)

7

6

5

4

FMP7

FMP6

FMP5

FMP4

3

2

1

0

FML7

FML6

FML5

FML4

0

0

0

R/W
0

0

0

0

LCP0 DVM (bits7-4) (M)

92CZ26A-540

0

LHSYNC DVM (bits 7-4) (N)

TMP92CZ26A

6. LD Bus
The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to
LD0). The output format can be selected according to the input method of the LCD
driver to be used.
The LCDC reads data of the size corresponding to the specified LCD size from the
display RAM and transfers it to the external LCD driver via the data bus pin dedicated
to the LCD. Thus, the LCDC automatically issues a bus request to the CPU (to stop
CPU operation) when it needs to read data from the display RAM. The bus occupancy
rate of the LCDC varies depending on the display mode and the speed at which data is
read from the display RAM.

Valid Data Read Time

Valid Data Read Time

Display RAM

Bus Width

External SRAM

16-bit

(2 + number of waits) / 2

16.6

Internal RAM

32-bit

**1/4

**4.16

External SDRAM

16-bit

*1/2

*8.33

(fSYS clocks/bytes)

tLRD(ns/bytes)
at fSYS = 60 MHz

Note: When SDRAM is used, additional 9 clocks are needed as overhead time for reading each common (line)
data. When internal RAM is used, additional 1 clock is needed as overhead time for reading each common
(line) data. Additional 1 clock of overhead time is also needed when a change of blocks occur in the
internal RAM even if the common (line) remains the same.

The time the CPU stops operating while data for one common (line) is being
transferred is defined as tSTOP, which is represented by the following equation:
tSTOP = (SegNum × K / 8) × tLRD
SegNum : Number of display segments
K
: Number of bits needed for displaying one pixel
Monochrome display
K=1
4-grayscale display
K=2
16-grayscale display
K=4
256-color display
K=8
4096-color display
K=12
65536-color display
K=16
262144-/16777216-color display
K=24
Note: When SDRAM is used, overhead time is added as follows:
tSTOP [S] = ( SegNum × K / 8 ) × tLRD + ((1 / fSYS ) × 8 )
The bus occupancy rate indicates the proportion of the one common (line) update time tLP occupied by tSTOP and
is calculated by the following equation:

CPU bus occupancy rate = tSTOP [s] / LHSYNC [s: period]

92CZ26A-541

TMP92CZ26A

•

Memory Map Image and Data Output in Each Display Mode

STN monochrome (1-pixel display data = 1-bit memory data)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

2 3

4 5 6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

LD Bus Output
8-bit type
LD0 0 → 8 …
LD1 1 → 9 …
LD2 2 → 10 …
LD3 3 → 11 …
LD4 4 → 12 …
LD5 5 → 13 …
LD6 6 → 14 …
LD7 7 → 15 …
Note: When setting 240 segment, 256 segment size of data is required.

●STN 4-grayscale (1-pixel display data = 2-bit memory data)
Display Memory
Address 0

Address 1

Address 2

LSB
D0
0

Address 3
MSB
D31

1

2 3

4 5 6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

LD Bus Output
8-bit type
LD0
1 - 0 → 17-16 …
LD1
3 - 2 → 19-18 …
LD2
5 - 4 → 21-20 …
LD3
7- 6 → 23-22 …
LD4
9- 8 → 25-24 …
LD5 11-10 → 27-26 …
LD6 13-12 → 29-28 …
LD7 15-14 → 31-30 …
Figure 3.19.2 Memory Map Image and Data Output in STN Monochrome/4-Grayscale Mode

92CZ26A-542

TMP92CZ26A

STN 16-grayscale (1-pixel display data = 4-bit memory data)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

2 3

4 5 6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Address 4

Address 5

Address 6

LSB
D0

Address 7
MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

LD Bus Output
8-bit type
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7

3-0 → 35-32 …
7-4 → 39-36 …
11-8 → 43-40 …
15-12 → 47-44 …
19-16 → 51-48 …
23-20 → 55-52 …
27-24 → 59-56 …
31-28 → 63-60 …

Figure 3.19.3 Memory Map Image and Data Output in STN 8-/16-Grayscale Mode

92CZ26A-543

TMP92CZ26A

STN 64-grayscale (1-pixel display data = 6-bit memory data)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

2 3

4 5 6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Address 4

Address 5

Address 6

Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Address 8

Address 9

Address 10

LSB
D0

Address 11
MSB
D31

64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

LD Bus Output
8-bit type
LD0
5-0
LD1
11-6
LD2
17-12
LD3
23-18
LD4
29-24
LD5
35-30
LD6
41-36
LD7
47-42

→
→
→
→
→
→
→
→

53-48
59-54
65-60
71-66
77-72
83-78
89-84
95-90

Figure 3.19.4 Memory Map Image and Data Output in STN 64-Grayscale Mode

92CZ26A-544

TMP92CZ26A

STN 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits))
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

R0

2 3

4 5 6
G0

7

B0

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R1

Address 4

G1

B1

R2

Address 5

G2

B2

R3

Address 6

G3

B3

Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R4

G4

B4

R5

G5

B5

R6

G6

B6

R7

G7

B7

LD Bus Output
8-bit type
LD0 2-0(R0) → 23-22(B2) …
LD1 5-3(G0) → 26-24(R3) …
LD2 7-6(B0) → 29-27(G3) …
LD3 10-8(R1) → 31-30(B3) …
LD4 13-11(G1) → 34-32(R4) …
LD5 15-14(B1) → 37-35(G4) …
LD6 18-16(R2) → 39-38(B4) …
LD7 21-19(G2) → 42-40(R5) …

Figure 3.19.5 Memory Map Image and Data Output in STN 256-Color Mode

92CZ26A-545

TMP92CZ26A

STN 4096-color (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1
R0

2 3

4 5 6
G0

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B0

Address 4

R1

G1

Address 5

B1

R2

Address 6

G2
Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
B2

R3

G3

B3

R4

G4

B4

R5

LD Bus Output
8-bit type
LD0 3-0(R0) → 35-32(B2)…
LD1 7-4(G0) → 39-36(R3)…
LD2 11-8(B0) → 43-40(G3)…
LD3 15-12(R1) → 47-44(B3)…
LD4 19-16(G1) → 51-48(R4)…
LD5 23-20(B1) → 55-52(G4)…
LD6 27-24(R2) → 59-56(B4)…
LD7 31-28(G2) → 63-60(R5)…

Figure 3.19.6 Memory Map Image and Data Output in STN 4096-Color Mode

92CZ26A-546

TMP92CZ26A

TFT 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

R0

2 3

4 5 6
G0

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

B0

R1

Address 4

G1

B1

R2

Address 5

G2

B2

R3

Address 6

G3

B3

Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R4

G4

12bit (TFT)
LD0
0(R0)
LD1
1(R0)
LD2
2(R0)
LD3
3(G0)
LD4
4(G0)
LD5
5(G0)
LD6
6(B0)
LD7
7(B0)

B4

→
→
→
→
→
→
→
→

R5

12(R1)
13(R1)
14(R1)
15(G1)
16(G1)
17(G1)
18(B1)
19(B1)

G5

B5

R6

G6

B6

R7

G7

B7

…
…
…
…
…
…
…
…

Figure 3.19.7 Memory Map Image and Data Output in TFT 256-Color Mode

92CZ26A-547

TMP92CZ26A

TFT 4096-color (1-pixel display data = 12-bit memory data (R: 4 bits, G: 4 bits, B: 4 bits)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

2 3
R0

4 5 6
G0

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B0

Address 4

R1

G1

Address 5

B1

R2

Address 6

G2
Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
B2

R3

G3

B3

R4

G4

B4

R5

12-bit TFT
LD0 0(R0) → 12(R1) …
LD1 1(R0) → 13(R1) …
LD2 2(R0) → 14(R1) …
LD3 3(R0) → 15(R1) …
LD4 4(G0) → 16(G1) …
LD5 5(G0) → 17(G1) …
LD6 6(G0) → 18(G1) …
LD7 7(G0) → 19(G1) …
LD8 8(B0) → 20(B1) …
LD9 9(B0) → 21(B1) …
LD10 10(B0) → 22(B1) …
LD11 11(B0) → 23(B1) …

Figure 3.19.8 Memory Map Image and Data Output in TFT 4096-Color Mode

92CZ26A-548

TMP92CZ26A

TFT 65536-color (16 bpp: R: 5 bits, G: 6 bits, B: 5 bits)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

2 3

4 5 6

R0

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
G0

Address 4

B0

R1

Address 5

G1
Address 6

B1
Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R2

G2

B2

R3

G3

B3

16-bit TFT
LD0 0(R0) → 16(R1) …
LD1 1(R0) → 17(R1) …
LD2 2(R0) → 18(R1) …
LD3 3(R0) → 19(R1) …
LD4 4(R0) → 20(R1) …
LD5 5(G0) → 21(G1) …
LD6 6(G0) → 22(G1) …
LD7 7(G0) → 23(G1) …
LD8 8(G0) → 24(G1) …
LD9 9(G0) → 25(G1) …
LD10 10(G0) → 26(G1) …
LD11 11(B0) → 27(B1) …
LD12 12(B0) → 28(B1) …
LD13 13(B0) → 29(B1) …
LD14 14(B0) → 31(B1) …
LD15 15(B0) → 32(B1) …
Figure 3.19.9 Memory Map Image and Data Output in TFT 65536-Color Mode

92CZ26A-549

TMP92CZ26A

TFT 262144-/16777216-color (24 bpp: R: 8 bits, G: 8 bits, B: 8 bits)
Display Memory
Address 0

Address 1

Address 2

Address 3

LSB
D0
0

MSB
D31
1

2 3

4 5 6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0
Address 4

G0

B0

Address 5

R1

Address 6

Address 7

LSB
D0

MSB
D31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

G2

B2

24-bit TFT
LD18 0(R0) → 24(R1) …
LD19 1(R0) → 25(R1) …
LD0 2(R0) → 26(R1) …
LD1 3(R0) → 27(R1) …
LD2 4(R0) → 28(R1) …
LD3 5(R0) → 29(R1) …
LD4 6(R0) → 30(R1) …
LD5 7(R0) → 31(R1) …
LD20 8(G0) → 32(G1) …
LD21 9(G0) → 33(G1) …
LD6 10(G0) → 34(G1) …
LD7 11(G0) → 35(G1) …
LD8 12(G0) → 36(G1) …
LD9 13(G0) → 37(G1) …
LD10 14(G0) → 38(G1) …
LD11 15(G0) → 39(G1) …
LD22 16(B0) → 40(B1) …
LD23 17(B0) → 41(B1) …
LD12 18(B0) → 42(B1) …
LD13 19(B0) → 43(B1) …
LD14 20(B0) → 44(B1) …
LD15 21(B0) → 45(B1) …
LD16 22(B0) → 46(B1) …
LD17 23(B0) → 47(B1) …

R3

G3

18-bit TFT

→ 26(R1) …
→ 27(R1) …
→ 28(R1) …
→ 29(R1) …
→ 30(R1) …
→ 31(R1) …

LD0
LD1
LD2
LD3
LD4
LD5

2(R0)
3(R0)
4(R0)
5(R0)
6(R0)
7(R0)

LD6
LD7
LD8
LD9
LD10
LD11

10(G0)
11(G0)
12(G0)
13(G0)
14(G0)
15(G0)

→ 34(G1) …
→ 35(G1) …
→ 36(G1) …
→ 37(G1) …
→ 38(G1) …
→ 39(G1) …

LD12
LD13
LD14
LD15
LD16
LD17

18(B0)
19(B0)
20(B0)
21(B0)
22(B0)
23(B0)

→ 42(B1) …
→ 43(B1) …
→ 44(B1) …
→ 45(B1) …
→ 46(B1) …
→ 47(B1) …

Note: The display RAM data format for 18 bpp is the same as that for 24 bpp. When 18 bpp is used, the least significant
bit should be disabled by port setting.

Figure 3.19.10 Memory Map Image and Data Output in TFT 262144-/16777216-Color Mode

92CZ26A-550

TMP92CZ26A

7. LDIV Signal
The  and  bits of the LCDMODE1 register are used to control
the LDIV signal as well as data output. The LDIV signal indicates the inversion of all
the LD bus signals.
When LCDMODE1=1, all display data is forcefully inverted and the LDIV
signal is also driven high. When LCDMODE1=1, the data that has just
been transferred and the data to be transferred next are compared. If there are more
changed bits than unchanged bits (for example, 7 or more bits are changed when using
a 12-bit bus, and 5 or more bits are changed when using a 8-bit bus), the data is
inverted and the LDIV signal is also driven high. This function can be used with TFT
source drivers having the data inversion function to reduce radiated noise and power
consumption due to high-speed data inversion.
If  and  are both set to “1” at the same time,  is given
priority and  is disabled.

92CZ26A-551

TMP92CZ26A

3.19.4 Interrupt Function
The LCDC has two types of interrupts.
One is generated synchronous with the LLOAD signal and the other is generated
synchronous with the LLOAD signal that is output immediately after the LVSYNC
signal.
LCDMODE1 is used to switch between these two types of interrupts.

LVSYNC

LHSYNC

LLOAD
D15-0(VRAM Read)
Interrupt request
LCDMODE1=0

Interrupt request
LCDMODE1=1

When LCDMODE1=0, an interrupt request is generated at the start of
each VRAM read before the LLOAD generates (once in each LLOAD period).
When LCDMODE1=1, an interrupt request is generated at the start of
VRAM read before the first LLOAD generates (once in each LVSYNC period).
**The interrupt request generates when reading the data from VRAM at once. Since
reading from VRAM is executed by DMA with bus request to the CPU, DMA operation
is given priority. Thus CPU accepts interrupt immediately after reading the data from
VRAM.
LCDMODE1 Register

LCDMODE1
(0281H)

7

6

5

4

3

2

1

0

bit Symbol

LDC2

LDC1

LDC0

LDINV

AUTOINV

INTMODE

FREDGE

SCPW2

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

W

W

After reset

0

0

0

0

0

0

0

0

Data rotation function

LD bus

Auto bus

Interrupt

(Supported for 64K-color: 16 bps

inversion

inversion

selection

only)
Function

LFR edge

LD bus
Trance

0: LHSYNC Speed

000: Normal

100: 90-degree

001: Horizontal flip 101: Reserved

0: Normal

0: Disable

0:LLOAD

1: Invert

1: Enable

1:LVSYNC 1:LHSYNC

010: Vertical flip

110: Reserved

(Valid only

011: Vertical &

111: Reserved

for TFT)

Front Edge
0: normal

Rear Edge 1: 1/3

horizontal flip

Note:

The LCDMODE1 setting must not be changed while the LCDC is operating. Be sure to set
LCDCTL0 to “0” to stop the LCDC operation before changing the interrupt setting.

92CZ26A-552

TMP92CZ26A
3.19.5 Special Functions
3.19.5.1

PIP (Picture in Picture) Function

The TMP92CZ26A includes a PIP (Picture in Picture) function that allows a different
screen to be displayed over the screen currently being displayed on the LCD.
The PIP function manages the address space of display memory by dividing it into
“main screen” and “sub screen”. For the main screen, the display size and start address
are specified as in the case of the normal screen display. For the sub screen, the display
size and start address are also specified for determining the position and size of the sub
screen.
When the HOT point (upper-left corner) and segment/common size are set for the sub
screen and the PIP function is enabled by setting LCDCTL0  to “1”, the sub
screen is displayed over the main screen.

HOT Point

LCD Panel (PIP OFF)

LCD Panel (PIP ON)

Main Area
Start Address

Note: This is just an image of
memory map and doesn’t describe
the image of bit map.

Sub Area
Start Address

VRAM Memory Map

92CZ26A-553

TMP92CZ26A

The table below shows the HOT point locations that can be specified.
*VRAM Access
Monochrome display
4-grayscale display
16-grayscale display
64-grayscale display
256-color display
4K-color display
64K-color display

HOT_Point(Y_dir)

16bit

In units of 16 dots

32bit

In units of 32 dots

16bit

In units of 8 dots

32bit

In units of 16 dots

16bit

In units of 4 dots

32bit

In units of 8 dots

16bit

In units of 8 dots

32bit

In units of 16 dots

HOT_Point(X_dir)

16bit

In units of 2 dots

In units of

32bit

In units of 4 dots

1 line

16bit

In units of 4 dots

32bit

In units of 8 dots

16bit

In units of 1 dots

32bit

In units of 2 dots

STN

16bit

In units of 8 dots

256K-color display

32bit

In units of 16 dots

TFT

16bit

In units of 2 dots

256k/16M-color display

32bit

In units of 4 dots

Note 1: The “VRAM Access” colomn shows the bus size for accessing the display RAM. When external RAM is
used, the bus size depends on the bit width of the external RAM to be used. When the internal RAM is
used VRAM is always accessed via a 32-bit bus.
Note 2: The same RAM must be used for both the main and sub areas.

The table below shows the HOT point segment and common sizes that can be
specified.
*VRAM Access

Segment size

Common size

Minimum size

units

16bit

32 dots

In units of 16 dots

32bit

64 dots

In units of 32 dots

16bit

16 dots

In units of 8 dots

32bit

32 dots

In units of 16 dots

16bit

8 dots

In units of 4 dots

32bit

16 dots

In units of 8 dots

64-grayscale display

16bit

16 dots

In units of 8 dots

32bit

32 dots

In units of 16 dots

256-color display

16bit

4 dots

In units of 2 dots

In units of

32bit

8 dots

In units of 4 dots

1 line

16bit

8 dots

In units of 4 dots

32bit

16 dots

In units of 8 dots

64K-color display

16bit

2 dots

In units of 1 dots

32bit

4 dots

In units of 2 dots

STN

16bit

16 dots

In units of 8 dots

256K-color display

32bit

32 dots

In units of 16 dots

TFT

16bit

4 dots

In units of 2 dots

256k/16M-color display

32bit

8 dots

In units of 4 dots

Monochrome display
4-grayscale display
16-grayscale display

4K-color display

92CZ26A-554

TMP92CZ26A

LCD Main Area Start Address Register
LSAML
(02A0H)

7

6

5

4

3

2

1

bit Symbol

LMSA7

LMSA6

LMSA5

LMSA4

LMSA3

LMSA2

LMSA1

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

Function

LSAMM
(02A1H)

LCD main area start address (A7-A0)

7

6

5

4

3

2

1

0

bit Symbol

LMSA15

LMSA14

LMSA13

LMSA12

LMSA11

LMSA10

LMSA9

LMSA8

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Function

LSAMH
(02A2H)

0

LCD main area start address (A15-A8)

7

6

5

4

3

2

1

0

bit Symbol

LMSA23

LMSA22

LMSA21

LMSA20

LMSA19

LMSA18

LMSA17

LMSA16

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

1

0

0

0

0

0

0

0

Function

LCD main area start address (A23-A16)

LCD Sub Area Start Address Register
LSASL
(02A4H)

7

6

5

4

3

2

1

bit Symbol

LSSA7

LSSA6

LSSA5

LSSA4

LSSA3

LSSA2

LSSA1

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

Function

LSASM
(02A5H)

LCD sub area start address (A7-A1)

7

6

5

4

3

2

1

0

bit Symbol

LSSA15

LSSA14

LSSA13

LSSA12

LSSA11

LSSA10

LSSA9

LSSA8

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Function

LSASH
(02A6H)

LCD sub area start address (A15-A8)

7

6

5

4

3

2

1

0

bit Symbol

LSSA23

LSSA22

LSSA21

LSSA20

LSSA19

LSSA18

LSSA17

LSSA16

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

1

0

0

0

0

0

0

Function

LCD sub area start address (A23-A16)

92CZ26A-555

TMP92CZ26A
LCD Sub Area HOT Point Register (X-dir)
LSAHX
(02A8H)

7

6

5

4

3

2

1

0

bit Symbol

SAH7

SAH6

SAH5

SAH4

SAH3

SAH2

SAH1

SAH0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

7

6

5

Function
(02A9H)

LCD sub area HOT point (7-0)
1

0

bit Symbol

4

SAH9

SAH8

Read/Write

R/W

R/W

After reset

0

0

Function

3

2

LCD sub area HOT point (9-8)
LCD Sub Area HOT Point Register (Y-dir)

LSAHY
(02AAH)

7

6

5

4

3

2

1

0

bit Symbol

SAHY7

SAHY6

SAHY5

SAHY4

SAHY3

SAHY2

SAHY1

SAHY0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

7

6

5

2

1

Function
(02ABH)

LCD sub area HOT point (7-0)
4

3

0

bit Symbol

SAHY8

Read/Write

R/W

After reset

0
LCD sub
area HOT

Function

point
(9-8)

Note: The HOT point should be set in units of the specified number of dots, which is determined by the display
color mode and display RAM access data bus width.
LCD Sub Area Display Segment Size Register
LSASS
(02ACH)

7

6

5

4

3

2

1

0

bit Symbol

SAS7

SAS6

SAS5

SAS4

SAS3

SAS2

SAS1

SAS0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

Function

LCD sub area segment size (7-0)
7

(02ADH)

1

0

bit Symbol

6

5

4

3

SAS9

SAS8

Read/Write

R/W

R/W

0

0

After reset
Function

2

LCD sub area segment size (9-8)

Note: The segment size should be set in units of the specified number of dots, which is determined by the display
color mode and display RAM access data bus width.

92CZ26A-556

TMP92CZ26A

LCD Sub Area Display Common Size Register
LSACS
(02AEH)

7

6

5

4

3

2

1

0

bit Symbol

SAC7

SAC6

SAC5

SAC4

SAC3

SAC2

SAC1

SAC0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

2

1

Function

LCD sub area common size (7-0)
7

(02AFH)

6

5

4

3

0

bit Symbol

SAC8

Read/Write

R/W

After reset

0

Function

LCD sub area common size (8)

Note: The common size should be set in units of 1 line.

92CZ26A-557

TMP92CZ26A

3.19.5.2

Display Data Rotation Function

When display RAM data is output to the LCD driver (LCDD), the data output
direction can be automatically rotated by hardware to meet the specifications of the
LCDD (or LCD module) to be used.
Table 3.19.2 Operation Conditions
Item

Vertical/Horizontal Flip Function

90-Degree Rotation Function

Display size

320 × 240

320×240 → 240 × 320

Color mode

64K colors (16 bpp)

64K colors (16 bpp)

Supported LCDD

TFT, STN

TFT, STN

Display RAM

Internal RAM, external SRAM

Internal RAM, external SRAM

1. Horizontal and Vertical Flip Function

Display RAM image

Normal display

Vertically flipped

Horizontally flipped

Horizontally and vertically flipped

The display RAM image shown above uses the data scan method for the normal
display screen so that data is read from the display RAM and written to the LCDD from
left to right and top to bottom.
The data on the LCD screen appears as “horizontally flipped” if data is read from the
display RAM from left to right and top to bottom and written to the LCDD from right to
left and top to bottom.
Likewise, the data on the LCD screen appears as “vertically flipped” if data is written
to the LCDD from left to right and bottom to top, or as “horizontally and vertically
flipped” if the data is written to the LCDD from right to left and bottom to top.
The horizontal and vertical flip function enables the output of display data to meet
the specifications of each LCDD without the need to rearrange the display RAM data.
In other words, the screen display can be flipped horizontally and vertically without

92CZ26A-558

TMP92CZ26A
the need to rewrite the display RAM data.

2. 90-Degree Rotation Function

Display RAM Image (QVGA 320×240)

QVGA (320×240)

Portrait-type QVGA (240×320)
(when this function is used)

The display RAM image above shows typical data of QVGA size (320 segments × 240
commons: landscape type). If the LCDD to be used is of landscape type, the data can be
written to the LCDD without any problem.
If the LCDD to be used is of portrait type (240 segments × 320 commons), the data
cannot be displayed properly.
This function enables the orientation of each display image to be rotated 90 degrees
without the need to change the display RAM data.

92CZ26A-559

TMP92CZ26A

3. Setting Method
The  bits in the LCDMODE1 register are used to set the display data
rotation function.
LCDMODE1 Register

LCDMODE1
(0281H)

7

6

5

4

3

2

1

0

bit Symbol

LDC2

LDC1

LDC0

LDINV

AUTOINV

INTMODE

FREDGE

SCPW2

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

W

W

After reset

0

0

0

0

0

0

0

Data rotation function

LD bus

Auto bus

Interrupt

(Supported for 64K-color: 16 bps

inversion

inversion

selection

only)
Function

LFR edge

0
LD bus
Trance

0: LHSYNC Speed

000: Normal

100: 90-degree

001: Horizontal flip 101: Reserved

0: Normal

0: Disable

0:LLOAD

1: Invert

1: Enable

1:LVSYNC 1:LHSYNC 0: normal

010: Vertical flip 110: Reserved

(Valid for

011: Horizontal and vertical flip

TFT only)

Front Edge
Rear Edge 1: 1/3

111: Reserved
Note: The  setting must not be changed while the LCDC is operating. Be sure to set
LCDCTL0 to “0” to stop the LCDC operation before changing .

When the horizontal and vertical flip function or 90-degree rotation function is used,
the display RAM start address of main/sub area should be set differently from when
in normal mode, as shown in the table below.
Mode

Setting Point

Display RAM Start Address
Setting Example

Normal

Point A

00000h

90-degree rotation

Point B

257FEh

Horizontal flip

Point A

00000h

Vertical flip

Point B

257FEh

Horizontal and vertical flip

Point B

257FEh

How to calculate the point B address:
(320×240×16/8)- 2 = 153600 - 2
= 153598 [decimal]
= 257FE [hex]
Point A

Point B

Display RAM Image (QVGA 320 × 240)

92CZ26A-560

TMP92CZ26A
3.19.5.3

Considerations for Using the LCDC

1． If the operation mode is changed while the LCDC is operating, a maximum of
one frame may not be displayed properly. Although this degree of disturbance
does not normally pose any problem (e.g. no response on LCD, display not
visible to human eyes), the actual operation largely depends on the conditions
such as the LCD driver, LCD panel, and frame frequency to be used. It is
therefore recommended that operation checks be performed under the actual
conditions.
2． The LCDMODE1 setting must not be changed while the LCDC is
operating. Be sure to set LCDCTL0 to “0” to stop the LCDC operation
before changing .
3． The LCDC obtains the bus from the CPU when it has some operation to
perform. Since the TMP92CZ26A includes other units that act as bus masters
such as HDMA and SDRAMC, it is necessary to estimate the bus occupancy
rate of each bus master in advance. For details, see the chapter on HDMA.

92CZ26A-561

TMP92CZ26A

3.19.6 Setting Example
•

STN

CO M001

VDD

O001

SCP
LP

SEG240

COM240

SEG001

O 240

O001

240CO M × 240SEG
LCD (M onochrom e Panel)

VSS

VDD
VSS

T6C13B
(240-colum n D river)
Note: The LCD drive power for LCD display must be supplied from an external circuit.

Figure 3.19.11 STN-Type LCD Driver Connection Example

92CZ26A-562

,V5LR

VSSLR,V3LR

,V0LR,V2LR,

VCCLR

open

TEST
DUAL

LD7∼ LD0

FR
/DSPOF
DI7∼ DI0
EIO 1
EIO2

VSS

LCP0
LHSYNC
LFR
port

O240

LP

/DSPOF
FR

EIO2
EIO1

open

VSS

SEG001

COM001

VSS
DIR
TEST
Di7-Di0
DUAL
SCP
S/C
VCCL/R, V0L/R,
V1L/R, V4L/R,
V5L/R

DIR
VDD
S/C

VDD

LVSYNC

CO M240

T6C13B
(240-row Driver)

TM P92CZ26

SEG240

240COM × 80SEG
LCD (Color Panel)

TMP92CZ26A

•

TFT
JB T 6L78-AS
(162-gate D riv e r)

92C Z26

VDD

VD D
U /D
T E ST 1
T E ST 2
V SS

V SS

LG O E 2-0

G1

G1

160 SE G × 3(R G B )× 162C O M
LC D

O E3-1
G 162

SC160

SB160

SA160

SC81

SB81

SA81

SC80

SB80

SA80

SC1

SB1

SA1

CPV

DO/I

D O /I

SC80

SB80

SA80

SC1

SB1

DC1-0

DB1-0

DA1-0

VSS

U/D
VDD

DC1-0

DB-1-0

DA1-0

VSS

D A5-2
D B5-2
D C 5-2

Control Signal

D15∼D0

D O /I

D I/O

D A5-0

D C 5-0

Axx∼Axx

C PH
LO AD

D B5-0
U/D
VDD

C ontrol S ignal
D 15∼ D 0
A 0∼ A 23

SA1

SC80

SB80

SA80

SC1

C PH
LO AD
D I/O

LC P 0
LLO A D
LF R
LH SY N C
LD 23~LD 0

SB1

LVS YN C

SA1

open

DI/O

G 162

D ispla y M em ory
(SD R AM or S R AM )

VDD
V SS

JB T 6L77-AS × 2
(80× R G B S ource D riv er)

N ote: T he LC D drive power for LC D display m ust be supplied from and external circuit.

Figure 3.19.12 TFT-Type LCD Driver Connection Example

92CZ26A-563

open

TMP92CZ26A

3.20 Touch Screen Interface (TSI)
The TMP92CZ26A has an interface for 4-terminal resistor network touch-screen.
This interface supports two procedures: an X/Y position measurement and touch detection.
Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and
using an internal AD converter.

3.20.1

Touch-Screen Interface Module Internal/External Connection
TMP92CZ26A
YMY
X+

Touch
Screen

MX

X-

PY
PX
Y+

External Capacitors

Figure 3.20.1External connection of TSI
Touch screen control
AVCC
PXEN
SPY

SPX

Dec.

P97
(PY)

PYEN
MXEN

INT4

MYEN

PTST

INT4

P96/INT4

TSI7

(PX)
PXD (typ.50kΩ)

AD converter

PG3/AN3
(MY)

AN3

PG2/AN2

AN2

(MX)
SMX

SMY

VREFH

AVCC
AVSS
VREFH
VREFL

VREFL

Figure 3.20.2 Internal block diagram of TSI

92CZ26A-564

Internal data bus

AVSS

TMP92CZ26A

3.20.2

Touch Screen Interface (TSI) Control Register
TSI control register

TSICR0
(01F0H)

7

6

5

4

3

2

1

0

bit Symbol

TSI7

INGE

PTST

TWIEN

PYEN

PXEN

MYEN

MXEN

Read/Write

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

0: Disable

Input gate

Detection

INT4

SPY

SPX

SMY

SMX

1: Enable

control of

condition

Function

interrupt

0 : OFF

0 : OFF

0 : OFF

0 : OFF

Port 96,97 0: no

control

1 : ON

1 : ON

1 : ON

1 : ON

0: Enable

touch

0: Disable

1: Disable

1: touch

1: Enable

PXD (internal pull-down resistor) ON/OFF setting


0



1

0

OFF

OFF

1

ON

OFF

De-bounce time setting register

TSICR1
(01F1H)

7

6

5

4

3

2

1

0

bit Symbol

DBC7

DB1024

DB256

DB64

DB8

DB4

DB2

DB1

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

After reset

0

0

0

0

0

0

0

0

0: Disable

1024

256

64

8

4

2

1

Function

1: Enable

De-bounce time is set by “(N*64-16) / fSYS”-formula.
“N” is sum of number which is set to “1” in bit6 to bit 0. Note3:

Note1: Since an internal clock is used for de-bounce circuit, when IDLE1, STOP mode or PCM condition, the de-bounce
circuit don’t operate and also interrupt which through this circuit is not generated. When IDLE1, STOP mode or PCM
condition, set this circuit to disable (Write “0” to TSICR1) before entering HALT state.If de-bounce time is set
to “0”, signal is received after counting the 6-system clock (fSYS) from the condition that this circuit is set to disable.
Note2: During converting the analog input-data by using AD converter, the current flow to the normal C-MOS input-gate.
Therefore, provide its current by setting TSICR0.If the middle voltage is inputted, cut the input-signal to
C-MOS logic (P96,P97) by settig this bit.
Note3: TSICR0 is that confirming initial pen-touch. When the input-signal to C-MOS logic is blocked by
TSICR0, this bit is always “1”. Please be careful.
Ex:
TSICR1=95H →N = 64 + 4 + 1 = 69

92CZ26A-565

TMP92CZ26A

3.20.3

Touch detection procedure

A Touch detection procedure shows procedure until a pen is touched by the screen and it is
detected.
By touching, TSI generates interrupt (INT4) and this procedure will terminate. After an X/Y
position measuring procedure is terminated, return to this procedure and wait for next touch.
When touch is waiting, set SPY-switch to ON, and set other 3 switches (SMY, SPX and SMX)
to OFF. The pull-down resistor that is connected to P96/INT4/PX pin is set to ON.
During waiting a touch, the internal resistors of X and Y-direction are not connected.
Therefore, P96/INT4/PX pin’s level is set to Low by internal pull-down register (PXD) and INT4
isn’t generated.
When pen was touched, the internal resistors of X and Y-direction are connected. Therefore,
P96/INT4/PX pin’s level is set to High by internal pull-down register (PXD) and INT4 is
generated.
And the de-bounce-circuit is prepared for avoiding that INT4 of plural times generate by
one-time touch. When de-bounce-time is set to TSICR1 register, the pulse of time less than its
time is ignored.
The circuit detects the rising of signal, counts-up the time of the counter which is set, after
count, receive the signal internal. During counting, when the signal is set to Low, counter is
cleared. And the state become to state of waiting a rising edge.

TSICR1

TSICR0, IIMC, P9FC

De-bounce circuit
P96/INT4 pin

Enables INT4,
And select the Rising
or Falling of INT4

F/F

Figure 3.20.3 Block diagram of de-bounce circuit

92CZ26A-566

INT4

TSICR0


TMP92CZ26A

P96/INT4 pin

Reset the counter for de-bounce time
Start the counter for de-bounce time

de-bounce time

de-bounce time

de-bounce time

INT4

INT4 is generated by matching counter and
specified de-bounce time.

After pen is de-touched, INT4 can be issued
again.

INT4 isn’t generated by matching counter and specified
de-bounce time because of it is an edge-type interrupt.

Figure 3.20.4 Timing diagram of de-bounce circuit

92CZ26A-567

TMP92CZ26A
3.20.4

X/Y position measuring procedure
In the INT4 routine, execute an X/Y position measuring procedure like below.

At first, set both SPX, SMX-switches to ON, and set SPY, SMY-switches to OFF.

By this setting, analog-voltage which shows the X-position will be inputted to PG3/MY/AN3
pin.
The X-position can be measured by converting this voltage to digital code with AD converter.

Next, set both SPY, SMY-switches to ON, and set SPX, SMX-switches to OFF.
By this setting, analog-voltage that shows the Y-position will be inputted to PG2/MX/AN2
pin.
The Y-position can be measured by converting this voltage to digital code with AD converter.
The above analog-voltage that is inputted to AN3 or AN2-pin can be calculated. It is a ratio
between resistance-value in TMP92CZ26A and resistance-value in touch screen shown in
Figure 3.20.5.
Therefore, if the pen touches a corner area on touch screen, analog-voltage will not be to 3.3V
or 0.0V. As a notice, since each resistor has an uneven, consider about it. And it is recommended
that an average code among a few times AD conversion will be adopted as a correct code.

[Calculation for analog input voltage to AN2 or AN3-pin : (E1)]
AVCC=3.3V

E1 = ((R2+Rmy) / (Rpy+Rty+Rmy)) × AVCC [V]

SPY (SPX)
ON-resistor: Rpy (Rpx)
typ.10Ω

Touch screen resistor
: Rty (Rtx)
A value depends on
a touch screen.

Ex.) The case of AVCC=3.3V, Rpy=Rmy=10Ω, R1=400Ω and
R2=100Ω
E1 = ((100+10) / (10+400+100+10) × 3.3
= 0.698V

R1
AN2 (AN3)-pin
R2

Note1: A Y-position can be calculated in the same way though above
formula is for X-position.
Note2: Rty = R1+R2.

Touch-point
SMY (SMX)
ON-resistor: Rmy (Rmx)
typ.10Ω

Figure 3.20.5 Calculation analog voltage

92CZ26A-568

TMP92CZ26A
3.20.5

Flow chart for TSI

(1) Touch Detection Procedure

(2) X/Y Position
Measurement Procedure

Main Routine:

INT4 Routine:

TSICR0←98H
TSICR1←XXH (voluntary) (a)

Execute Main Routine


･TSICR0←C5H
･AD conversion for AN3
･Store the result

(b)


･TSICR0←CAH
･AD conversion for AN2
･Store the result

(c)

Execute an operation
By using X/Y-position

Yes
Still touched?
TSICR0 = 1?

No
Return to Main Routine

Figure 3.20.6 Flow chart for TSI
Following pages explain each circuit condition of (a), (b) and (c) in above flow chart.

92CZ26A-569

TMP92CZ26A
(a) Main routine (condition of waiting INT4 interrupt)
(p9fc), = “1”

:

Set P96 to int4/PX, set P97 to PY

(inte34)

:

Set interrupt level of INT4

(tsicr0)=98h

:

Pull-down resistor on, SPY on, Interrupt-set

ei

:

Enable interrupt

TMP92CZ26A
Touch screen control

AVCC

PXEN

ON
SPY

SPX

PYEN
MXEN
MYEN

Y+
Touch
Screen

(PX/P96/INT4)

INT4
ON
TSI7

X+
(MY/PG3)

PXD (typ.50kΩ)
AD Converter

Y-

AN3
(MX/PG2)
AN2
SMX

SMY

AVCC
AVSS

VREFH

VREFH

VREFL

VREFL

AVSS

92CZ26A-570

PTST

Internal data bus

(PY/P97)

X-

Dec.

TMP92CZ26A

(b) X position measurement (Start AD conversion)
(tsicr0)=c5h

:

Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF.

(admod1)=b0h

:

Set to AN3.

(admod0)=08h

:

Start AD conversion.

TMP92CZ26A
Touch screen control

AVCC

PXEN

ON
SPX

SPY

Dec.

PYEN
MXEN

(PY/P97)
INT4

Touch
Screen

(PX/P96/INT4)

X-

TSI7

X+
(MY/PG3)

PXD (typ.50kΩ)
AD Converter

Y-

AN3
(MX/PG2)
AN2
SMX

SMY

AVCC
AVSS

ON
VREFH

VREFH

VREFL

VREFL

AVSS

92CZ26A-571

PTST

Internal data bus

MYEN

Y+

TMP92CZ26A

(c) Y position measurement(Start AD conversion)
(tsicr0)=cah

:

(admod1)=a0h

:

Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF.
Set to AN2.

(admod0)=08h

:

Start AD conversion.

TMP92CZ26A
Touch screen control

AVCC

PXEN

ON
SPY

Dec.

SPX

PYEN
MXEN

(PY/P97)

Touch
Screen

INT4

(PX/P96/INT4)

TSI7

X-

X+
(MY/PG3)

PXD (typ.50kΩ)
AD Converter
AN3

Y(MX/PG2)

AN2
SMX

SMY

AVCC
ON

AVSS

VREFH

VREFH

VREFL

VREFL

AVSS

92CZ26A-572

PTST

Internal data bus

MYEN

Y+

TMP92CZ26A

3.20.6
1.

Note

De-bounce circuit
The system clock of CPU is used in de-bounce circuit. Therefore, de-bounce circuit is not
operated when clock is not supplied to CPU (IDLE1, STOP mode or PCM mode). And, an
interrupt which through the de-bounce circuit is not generated.
When started from IDLE1, STOP or PCM mode by using TSI, set the de-bounce circuit to
disable before a condition become to HALT or PCM mode. (TSICR1="0")

2.

Port setting
During conversion the middle voltage of 0V~AVcc by using AD converter, the middle
voltage is inputted to a normal C-MOS input-gate (P96 and P97), too.
Therefore, provide the flow current for P96 and P97 by using TSICR0. In this case
(TSICR0="1"), when the input to C-MOS logic is cut, TSICR0 for confirming
a first pen touch is always set to “1”. Please be careful.

92CZ26A-573

TMP92CZ26A

3.21 Real time clock (RTC)
3.21.1

Function description for RTC

1)

Clock function (hour, minute, second)

2)

Calendar function (month and day, day of the week, and leap year)

3)

24 or 12-hour (AM/PM) clock function

4)

+/- 30 second adjustment function (by software)

5)

Alarm function (Alarm output)

6)

Alarm interrupt generate

3.21.2

Block diagram
16 Hz Clock

32 KHz
Clock

Divider
1 Hz Clock
Alarm Register

Carry hold

Alarm
Selector

Comparator

(1s)

ALARM

INTRTC

ALARM

Clock

Address
Bus
Adjust
RD WR

Internal data bus

R/W Control
D0~D7

Address

Figure 3.21.1 RTC block diagram
Note1: The Christian era year column:
This product has year column toward only lower two columns. Therefore the next year
in 99 works as 00 years. In system to use it, please manage upper two columns with
the system side when handle year column in the Christian era.
Note2: Leap year:
A leap year is the year, which is divisible with 4, but the year, which there is exception,
and is divisible with 100, is not a leap year. However, the year is divisible with 400, is a
leap year. But there is not this product for the correspondence to the above exception.
Because there are only with the year that is divisible with 4 as a leap year, please cope
with the system side if this function is problem.

92CZ26A-574

TMP92CZ26A
3.21.3

Control registers
Table 3.21.1 PAGE 0 (Timer function) registers

Symbol

Address

Bit7

Bit6

Bit5

SECR

1320H

40 sec

20 sec

10 sec

8 sec

4 sec

MINR

1321H

40 min

20 min

10 min

8 min

4 min

HOURR

1322H

10 hours

8 hours

4 hours

20 hours/
PM/AM

DAYR

1323H

DATER

1324H

Day 20

MONTHR 1325H
YEARR

1326H

PAGER

1327H Interrupt
enable

RESTR

Note:

1328H

Year 80 Year 40 Year 20

1Hz

16Hz

enable

enable

Clock
reset

Bit4

Bit3

Bit2

Bit1

Bit0

Function

Read/Write

2 sec

1 sec

Second column

R/W

2 min

1 min

Minute column

R/W

2 hours

1 hour

Hour column

W2

W1

W0

Day of the week
column

R/W

R/W

Day 10

Day 8

Day 4

Day 2

Day 1

Day column

R/W

Oct.

Aug.

Apr.

Feb.

Jan.

Month column
Year column
(Lower two columns)

R/W

PAGE register

W, R/W

Year 10

Year 8

Year 4

Adjustment Clock
function
enable

Alarm
enable

Alarm
reset

Year 2

Year 1
PAGE

R/W

setting

Always write “0”

Reset register

W only

As for SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE0, current state is read read it.

Table 3.21.2 PAGE1 (Alarm function) registers
Symbol

Address

SECR

1320H

MINR

1321H

HOURR

1322H

Bit7

Bit6

Bit5

1323H

DATER

1324H

Bit3

Bit2

Bit1

40 min

20 min
20 hours/

Day 20

YEARR

1326H

PAGER

1327H Interrupt
enable

Note:

1328H

Function

Read/Write

10 min

8 min

4 min

2 min

1 min

Minute column

10 hours

8 hours

4 hours

2 hours

1 hour

Hour column

W2

W1

W0

Day of the week
column

R/W

Day 4

Day 2

Day 1

Day column

R/W

24/12
LEAP0

24-hour clock mode
Leap-year mode

R/W

PAGE

PAGE register

W, R/W

Day 10

Day 8

MONTHR 1325H

RESTR

Bit0

R/W

PM/AM

DAYR

Bit4

LEAP1
Adjustment Clock
function
enable

1Hz

16Hz

enable

enable

Clock
reset

Alarm
reset

Alarm
enable
Always write “0”

R/W

R/W

setting
Reset register

As for SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE1, current state is read read it.

92CZ26A-575

R/W

W only

TMP92CZ26A
3.21.4

Detailed explanation of control register
RTC is not initialized by reset. Therefore, all registers must be initialized at the
beginning of the program.
(1) Second column register (for PAGE0 only)
7

SECR
(1320H)

Bit symbol

6

5

4

SE6

SE5

SE4

Read/Write

2

1

0

SE3

SE2

SE1

SE0

4 sec.
column

2 sec.
column

1 sec.
column

R/W

After reset
Function

3

Undefined
"0" is read.

40 sec.
column

20 sec.
column

10 sec.
column

8 sec.
column

0

0

0

0

0

0

0

0 sec

0

0

0

0

0

0

1

1 sec

0

0

0

0

0

1

0

2 sec

0

0

0

0

0

1

1

3 sec

0

0

0

0

1

0

0

4 sec

0

0

0

0

1

0

1

5 sec

0

0

0

0

1

1

0

6 sec

0

0

0

0

1

1

1

7 sec

0

0

0

1

0

0

0

8 sec

0

0

0

1

0

0

1

9 sec

0

0

1

0

0

0

0

10 sec

0

0

1

1

0

0

1

19 sec

0

1

0

0

0

0

0

20 sec

:

:
0

1

0

1

0

0

1

29 sec

0

1

1

0

0

0

0

30 sec

0

1

1

1

0

0

1

39 sec

1

0

0

0

0

0

0

40 sec

0

0

1

49 sec

0

0

0

50 sec

0

0

1

59 sec

:

:
1

0

0

1

1

0

1

0

:
1

0

1

1

Note: Do not set the data other than showing above.

92CZ26A-576

TMP92CZ26A

(2) Minute column register (for PAGE0/1)
7
MINR
(1321H)

Bit symbol

6

5

4

MI6

MI5

MI4

Read/Write

2

1

0

MI3

MI2

MI1

MI0

4 min,
column

2 min,
column

1 min,
column

R/W

After reset
Function

3

Undefined
"0" is read.

40 min,
column

20 min,
column

10 min,
column

8 min,
column

0

0

0

0

0

0

0

0 min

0

0

0

0

0

0

1

1 min

0

0

0

0

0

1

0

2 min

0

0

0

0

0

1

1

3 min

0

0

0

0

1

0

0

4 min

0

0

0

0

1

0

1

5 min

0

0

0

0

1

1

0

6 min

0

0

0

0

1

1

1

7 min

0

0

0

1

0

0

0

8 min

0

0

0

1

0

0

1

9 min

0

0

1

0

0

0

0

10 min

0

0

1

1

0

0

1

19 min

0

1

0

0

0

0

0

20 min

:

:
0

1

0

1

0

0

1

29 min

0

1

1

0

0

0

0

30 min

0

1

1

1

0

0

1

39 min

1

0

0

0

0

0

0

40 min

:

:
1

0

0

1

0

0

1

49 min

1

0

1

0

0

0

0

50 min

1

0

1

1

0

0

1

59 min

:
Note: Do not set the data other than showing above.

92CZ26A-577

TMP92CZ26A

(3) Hour column register (for PAGE0/1)
1.

In case of 24-hour clock mode (MONTHR= “1”)
7

HOURR
(1322H)

6

Bit symbol

5

4

3

HO5

HO4

HO3

Read/Write

2

1

0

HO2

HO1

HO0

2 hour
column

1 hour
column

R/W

After reset

Undefined

Function

"0" is read.

20 hour
column

10 hour
column

8 hour
column

4 hour
column

0

0

0

0

0

0

0 o’clock

0

0

0

0

0

1

1 o’clock

0

0

0

0

1

0

2 o’clock

:
0

0

1

0

0

0

8 o’clock

0

0

1

0

0

1

9 o’clock

0

1

0

0

0

0

10 o’clock

:
0

1

1

0

0

1

19 o’clock

1

0

0

0

0

0

20 o’clock

1

0

0

0

1

1

23 時

:
Note: Do not set the data other than showing above.

2.

In case of 24-hour clock mode (MONTHR= “0”)
7

HOURR
(1322H)

6

Bit symbol

5

4

3

2

1

0

HO5

HO4

HO3

HO2

HO1

HO0

2 hour
column

1 hour
column

Read/Write

R/W

After reset
Function

Undefined
"0" is read.

PM/AM

10 hour
column

8 hour
column

4 hour
column

0

0

0

0

0

0

0 o’clock
(AM)

0

0

0

0

0

1

1 o’clock

0

0

0

0

1

0

2 o’clock

:
0

0

1

0

0

1

9 o’clock

0

1

0

0

0

0

10 o’clock

0

1

0

0

0

1

11 o’clock

1

0

0

0

0

0

0 o’clock
(PM)

1

0

0

0

0

1

1 o’clock

Note: Do not set the data other than showing above.

92CZ26A-578

TMP92CZ26A

(4) Day of the week column register (for PAGE0/1)
7
DAYR
(1323H)

6

5

4

3

Bit symbol

2

1

0

WE2

WE1

WE0

Read/Write

R/W

After reset

Undefined

Function

"0" is read.

W2

W1

W0

0

0

0

Sunday

0

0

1

Monday

0

1

0

Tuesday

0

1

1

Wednesday

1

0

0

Thursday

1

0

1

Friday

1

1

0

Saturday

Note: Do not set the data other than showing
above.

(5) 日桁レジスタ (PAGE0/1)
7
DATER
(1324H)

6

Bit symbol

5

4

3

DA5

DA4

DA3

Read/Write

1

0

DA2

DA1

DA0

Day 2

Day 1

R/W

After reset
Function

2

Undefined
"0" is read.

Day 20

Day 10

Day 8

Day 4

0

0

0

0

0

0

0

0

0

0

0

0

1

1st day

0

0

0

0

1

0

2nd day

0

0

0

0

1

1

3rd day

0

0

0

1

0

0

4th day

:
0

0

1

0

0

1

9th day

0

1

0

0

0

0

10th day

0

1

0

0

0

1

11th day

0

1

1

0

0

1

19th day

1

0

0

0

0

0

20th day

:

:
1

0

1

0

0

1

29th day

1

1

0

0

0

0

30th day

1

1

0

0

0

1

31st day

Note1: Do not set the data other than showing above.
th

Note2: Do not set the day which is not existed. (ex: 30 Feb)

92CZ26A-579

TMP92CZ26A

(6) Month column register (for PAGE0 only)
7
MONTHR
(1325H)

6

5

Bit symbol

4

3

2

1

0

MO4

MO4

MO2

MO1

MO0

2 months

1 month

Read/Write

R/W

After reset

Undefined

Function

"0" is read.

10 months

8 months

4 months

0

0

0

0

1

January

0

0

0

1

0

February

0

0

0

1

1

March

0

0

1

0

0

April

0

0

1

0

1

May

0

0

1

1

0

June

0

0

1

1

1

July

0

1

0

0

0

August

0

1

0

0

1

September

1

0

0

0

0

October

1

0

0

0

1

November

1

0

0

1

0

December

Note: Do not set the data other than showing above.

(7) Select 24-hour clock or 12-hour clock (for PAGE1 only)
7
MONTHR
(1325H)

6

5

4

3

2

1

0

Bit symbol

MO0

Read/Write

R/W

After reset
Function

Undefined
"0" is read.

92CZ26A-580

1: 24-hour
0: 12-hour

TMP92CZ26A

(8) Year column register (for PAGE0 only)

YEARR
(1326H)

Bit symbol

7

6

5

4

YE7

YE6

YE5

YE4

Read/Write

2

1

0

YE3

YE2

YE1

YE0

4 Years

2 Years

1 Year

R/W

After reset
Function

3

Undefined
80 Years

40 Years

20 Years

10 Years

8 Years

1

0

0

1

1

0

0

1

99 years

0

0

0

0

0

0

0

0

00 years

0

0

0

0

0

0

0

1

01 years

0

0

0

0

0

0

1

0

02 years

0

0

0

0

0

0

1

1

03 years

0

0

0

0

0

1

0

0

04 years

0

0

0

0

0

1

0

1

05 years

0

0

1

99 years

:
1

0

0

1

1

Note: Do not set the data other than showing above.

(9) Leap-year register (for PAGE1 only)
7
YEARR
(1326H)

6

5

4

3

2

Bit symbol

1

0

LEAP1

Read/Write

LEAP0
R/W

After reset

Undefined

Function

00: leap-year
01: one year after leap-year

"0" is read.

10: two years after leap-year
11: three years after leap-year

92CZ26A-581

0

0

Current year is leap-year

0

1

Current is next year of a leap
year

1

0

Current is two years of a leap
year

1

1

Current is three years of a
leap year

TMP92CZ26A

(10) PAGE register (for PAGE0/1)
7
PAGER
(1327H)

6

5

4

3

2

ENATMR

1

Bit symbol

INTENA

ADJUST

Read/Write

R/W

W

R/W

R/W

After reset

0

Undefined

Undefined

Undefined

Read-modify Function
write
instruction
are
prohibited

Note:

(Note)
Interrupt

1: Adjust

“0” is read.

1: Enable

ENAALM

0

TIMER

ALARM

1: Enable

1: Enable

0: Disable

0: Disable

PAGE

“0” is read.

PAGE
selection

0: Disable

Pleas keep the setting order below and don’t set same time.
(Set difference time to Clock/Alarm setting and interrupt setting)

(Example) Clock setting/Alarm setting
ld

(pager), 0ch

:

Clock, Alarm enable

ld

(pager), 8ch

:

Interrupt enable

PAGE

0

Select Page0

1

Select Page1

0

Don’t care

1

Adjust sec. counter.
When set this bit to “1” the sec. counter become
to “0” when the value of sec. counter is 0 – 29.
And in case that value of sec. counter is 30-59,
min. counter is carried and become sec.
counter to "0". Output Adjust signal during 1
cycle of fSYS. After being adjusted once, Adjust
is released automatically.

ADJUST

(PAGE0 only)

(11) Reset register (for PAGE0/1)

RESTR
(1328H)

Bit symbol

7

6

5

4

DIS1Hz

DIS16Hz

RSTTMR

RSTALM

3

2

1

0

RE3

RE2

RE1

RE0

Read/Write

W

After reset

Undefined

Read-modify Function
write
instruction
are
prohibited

0: 1 Hz

RSTALM

RSTTMR

0: 16 Hz

1:Clock
reset

1: Alarm
reset

0

Unused

1

Reset alarm register

0

Unused

1

Reset timer register





1

1

Always write “0”

(PAGER)

1

Source signal
Alarm

0

1

0

1Hz

1

0

0

16Hz

Others

92CZ26A-582

Output “0”

TMP92CZ26A

3.21.5

Operational description
(1) Reading timer data
There is the case, which reads wrong data when carry of the inside counter happens
during the operation which clock data reads. Therefore please read two times with the
following way for reading correct data.
Start

PAGER = “0” ,
Select PAGE0

Read the clock data
(1st)

Read the clock data
(2nd)

NO
1st data = 2nd data
YES
END

Figure 3.21.2 Flowchart of timer data read

92CZ26A-583

TMP92CZ26A

(2) Timing of INTRTC and Clock data
When time is read by interrupt, read clock data within 0.5s(s) after generating
interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse
cycle.

ALARM
INTRTC
1s counter
(Internal signal)

56

57

58

59

0

1

2

1s count UP
(Internal signal)

Figure 3.21.3 Timing of INTRTC and Clock data

92CZ26A-584

3

4

TMP92CZ26A

(3) Writing timer data
When there is carry on the way of write operation, expecting data can not be wrote
exactly. Therefore, in order to write in data exactly please follow the below way.
1.

Resetting a divider
In RTC inside, there are 15-stage dividers, which generates 1Hz clock from
32,768 KHz. Carry of a timer is not done for one second when reset this divider. So
write in data at this interval.
Start

PAGER = “0”
Select PAGE0

RESTR = “1”
Divider reset

Write the clock data

End

Figure 3.21.4 Flowchart of data write

92CZ26A-585

Note)
This period is within
0.5 secound.

TMP92CZ26A

2.

Disabling the timer
Carry of a timer is prohibited when write “0” to PAGER and can
prevent malfunction by 1s Carry hold circuit. During a timer prohibited, 1s Carry
hold circuit holds one sec. carry signal, which is generated from divider. After
becoming timer enable state, output the carry signal to timer and revise time and
continue operation. However, timer is late when timer-disabling state continues
for one second or more. During timer disabling, pay attention with system power
is downed. In this case the timer is stopped and time is delayed.
Start

Disable the clock

Read the clock data

Enable the clock

End

Figure 3.21.5 Flowchart of Clock disable

92CZ26A-586

Note:
This period is within
0.5 secound.

TMP92CZ26A
3.21.6

Explanation of the interrupt signal and alarm signal
Can use alarm function by setting of register of PAGE1 and output either of three signals
from ALARM pin as follows by write “1” to PAGER. INTRTC outputs 1shot pulse
when the falling edge is detected. RTC is not initializes by RESET. Therefore, when clock or
alarm function is used, clear interrupt request flag in INTC (interrupt controller).
(1) In accordance of alarm register and the timer, output “0”.
(2) Output clock of 1Hz.
(3) Output clock of 16Hz.

(1) In accordance with alarm register and a clock, output “0”
When value of a clock of PAGE0 accorded with alarm register of PAGE1 with a state
of PAGER= “1”, output “0” to ALARM pin and occur INTRTC.
Follows are ways using alarm.
Initialization of alarm is done by writing in “1” at RESTR, setting value
of all alarm becomes don’t care. In this case, always accorded with value of a clock and
request INTRTC interrupt if PAGER is “1”.
Setting alarm min., alarm hour, alarm day and alarm the day week are done by
writing in data at each register of PAGE1.
When all setting contents accorded, RTC generates INTRTC interrupt, if
PAGER is “1”. However, contents (don't care state) which does
not set it up is considered to always accord.
The contents, which set it up once, cannot be returned to don't care state in
independence. Initialization of alarm and resetting of alarm register set to don’t care.
The following is an example program for outputting alarm from ALARM -pin at noon
(PM12:00) every day.
LD

(PAGER), 09H

;

Alarm disable, setting PAGE1

LD

(RESTR), D0H

;

Alarm initialize

LD

(DAYR), 01H

;

LD

(DATAR),01H

W0
1 day

LD

(HOURR), 12H

;

LD

(MINR), 00H

;

Setting 12 o’clock
Setting 00 min

;

Set up time 31 μs (Note)

LD

(PAGER), 0CH

;

Alarm enable

( LD

(PAGER), 8CH

;

Interrupt enable )

When CPU is operated by high frequency oscillation, it may take a maximum of one
clock at 32 kHz (about 30us) for the time register setting to become valid. In the above
example, it is necessary to set 31us of set up time between setting the time register and
enabling the alarm register.
Note:

This set up time is unnecessary when you use only internal interruption.

92CZ26A-587

TMP92CZ26A

(2) When output clock of 1Hz
RTC outputs clock of 1Hz to ALARM pin by setting up PAGER= “0”,
RESTR= “0”, = “1”. And RTC generates INTRC interrupt by
falling edge of the clock.
(3) When output clock of 16Hz
RTC outputs clock of 16Hz to ALARM pin by setting up PAGER= “0”,
RESTR= “1”, = “0”. And RTC generates INTRC interrupt by
falling edge of the clock.

92CZ26A-588

TMP92CZ26A

3.22 Melody / Alarm generator (MLD)
TMP92CZ26A contains melody function and alarm function, both of which are output from
the MLDALM pin. Five kind of fixed cycles interrupt is generate by using 15bit counter, which
is used for alarm generator.
Features are as follows.
1) Melody generator
The Melody function generates signals of any frequency (4Hz- 5461Hz) based on low-speed
clock (32.768 KHz) and outputs the signals from the MLDALM pin.
By connecting a loud speaker outside, Melody tone can easily sound.
2) Alarm generator
The Alarm function generates eight kinds of alarm waveform having a modulation frequency
(4096Hz) determined by the low-speed clock (32.768 KHz). And this waveform is able to invert
by setting a value to a register.
By connecting a loud speaker outside, Alarm tone can easily sound.
Five kinds of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) INTERRUPT are generated by
using a counter that is used for alarm generator.

This section is constituted as follows.
3.22.1 Block diagram
3.22.2 Control registers
3.22.3 Operational Description
3.22.3.1 Melody generator
3.22.3.2 Alarm generator

92CZ26A-589

TMP92CZ26A
3.22.1

Block Diagram
Reset

[Melody Generator]

Internal data bus

MELFH, MELFL register
MELOUT
Invert

MELFH


Comparator (CP0)

F/F

Stop and Clear
Clear
Low-speed
clock

12bit counter (UC0)

INTALM0 (8192Hz)
INTALM1 (512 Hz)
Edge
detectior

INTALM2 (64 Hz)

INTALM

INTALM3 (2 Hz)
INTALM4 (1 Hz)
15bit conter (UC1)

ALMINT


4096 Hz
MELALMC

8bit counter
(UC2)
MELOUT
Selector

Alarm wave form
generator

Invert
ALMOUT
MELALMC


ALM register

[Alarm Generator]

Internal data bus

Reset

Figure 3.22.1MLD Block Diagram

92CZ26A-590

MELALMC


MLDALM pin

TMP92CZ26A
3.22.2

ALM
(1330H)

Control registers

bit Symbol

ALM register
5
4

7

6

AL8

AL7

AL6

AL5

0

0

0

0

Read/Write
Function

bit Symbol

1

0

AL2

AL1

0

0

0

0

Setting alarm pattern

7

6

FC1

FC0

Read/Write

MELALMC register
5
4

3

2

1

0

ALMINV

−

−

−

−

MELALM

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

R/W

After reset

0

0

Free-run counter
control
Function

2
AL3

R/W

After reset

MELALMC
(1331H)

3
AL4

Always write “0”

Alarm

00: Hold

Wavefor
m invert

01: Restart

1:INVERT

Select
Output
Wavefor
m

10: Clear

0: Alarm

11: Clear & Start

1: Melody

Note1: MELALMC is read always “0”.
Note2: When setting MELALMC register except  during the free-run counter is running,  is kept “01”.

MELFL
(1332H)

bit Symbol

6

5

ML7

ML6

ML5

ML4

Read/Write
After reset

0

2

1

0

ML3

ML2

ML1

ML0

0

0

0

0

0

0

0

Setting melody frequency (lower 8bit)

7
bit Symbol

MELON

Read/Write

R/W

After reset

0

6

MELFH register
5
4

3

2

1

0

ML11

ML10

ML9

ML8

0

0

0

0

R/W

Control
melody
counter
Function

3

R/W

Function

MELFH
(1333H)

MELFL register
4

7

Setting melody frequency(upper 4bit)

0: Stop &
Clear
1: Start

7
ALMINT
(1334H)

6

ALMINT register
5
4

3

2

1

0

IALM3E

IALM2E

IALM1E

IALM0E

0

0

0

1:INTALM3

1:INTALM2

1:INTALM1

1:INTALM0

(2Hz)
enable

(64Hz)
enable

(512Hz)
enable

(8192Hz)
enable

bit Symbol

−

Read/Write

R/W

After reset

0

0

0

Always
write “0”

1:INTALM4

Function

(1Hz)
enable

IALM4E

R/W

Note: INTALM0 to INTALM4 prohibit that set to enable at same time. If setting to enable, set only 1.

92CZ26A-591

TMP92CZ26A

3.22.3

Operational Description

3.22.3.1

Melody generator

The Melody function generates signals of any frequency (4Hz-5461Hz) based on
low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin.
By connecting a loud speaker outside, Melody tone can easily sound.
(Operation)
At first, MELALMC have to be set as “1” in order to select melody waveform
as output waveform from MLDALM. Then melody output frequency has to be set to 12-bit
register MELFH, MELFL.
Followings are setting example and calculation of melody output frequency.
(Formula for calculating of melody waveform frequency)
@fs = 32.768 [kHz]
Melody output waveform

fMLD[Hz] = 32768/ (2 × N + 4)

Setting value for melody

N = (16384/ fMLD) − 2

(Note: N = 1~4095 (001H~FFFH), 0 is not acceptable)

(Example program)
In case of outputting “A” musical scale (440Hz)
LD

(MELALMC), −−XXXXX1B

; Select melody waveform

LD

(MELFL), 23H

; N = 16384/440 − 2 = 35.2 = 023H

LD

(MELFH), 80H

; Start to generate waveform

(Refer: Basic musical scale setting table)
Scale

Frequency

Register

[Hz]

Value: N

C

264

03CH

D

297

035H

E

330

030H

F

352

02DH

G

396

027H

A

440

023H

B

495

01FH

C

528

01DH

92CZ26A-592

TMP92CZ26A
3.22.3.2

Alarm generator

The Alarm function generates eight kinds of alarm waveform having a modulation
frequency 4096Hz determined by the low-speed clock (32.768 KHz). And this waveform is
reversible by setting a value to a register.
By connecting a loud speaker outside, Alarm tone can easily sound.
Five kind of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) interrupt be generate by using
a counter which is used for alarm generator.
(Operation)
At first, MELALMC have to be set as “0” in order to select alarm waveform
as output waveform from MLDALM. Then “10” be set on MELALMC register, and
clear internal counter. Finally alarm pattern has to be set on 8-bit register of ALM. If it is
inverted output-data, set  as invert.
Followings are example program, setting value of alarm pattern and waveform of each
setting value.

(Setting value of alarm pattern)
Setting value
for ALM
register

Alarm waveform

00H

“0” fixed

01H

AL1 pattern

02H

AL2 pattern

04H

AL3 pattern

08H

AL4 pattern

10H

AL5 pattern

20H

AL6pattern

40H

AL7 pattern

80H

AL8 pattern

Other

Undefined
(Do not set)

(Example program)
In case of outputting AL2 pattern (31.25ms/8 times/1sec)
LD

(MELALMC), C0H

; Set output alarm waveform
; Free-run counter start

LD

(ALM), 02H

92CZ26A-593

; Set AL2 pattern, start

TMP92CZ26A

Example: Waveform of alarm pattern for each setting value: not invert)
AL1 pattern
(Continuous output)

Modulation frequency (4096 Hz)
1

2

8

1

AL2 pattern
(8 times/1 sec)
31.25 ms

1秒

1
AL3 pattern
(once)
500 ms
1

2

1

AL4 pattern
(Twice/1 sec)
62.5 ms
1

1 sec
2

3

1

AL5 pattern
(3 times/1 sec)
62.5 ms

AL6 pattern
(1 times)

1 sec

1

62.5 ms
AL7 pattern
(Twice)

1

2

62.5 ms
AL8 pattern
(Once)
250 ms

92CZ26A-594

TMP92CZ26A

3.23 Analog-Digital Converter (ADC)
This LSI has a 6-channel, multiplexed-input, 10-bit successive-approximation Analog-Digital
converter (ADC).
Figure 3.23.1 shows a block diagram of the AD converter.
The 6-analog input channels (AN0-AN5) can be used as general-purpose inputs.
Note1: Ensure that the AD converter has halted before executing HALT instruction to place the
TMP92CZ26A in IDLE2, IDLE1, STOP or PCM mode to reduce power consumption current.
Otherwise, the TMP92CZ26A might go into a standby mode while the internal analog
comparator is still enable state.
Note2: The power consumption current is reduced by setting ADMOD1 to “0” in the ADC
has been stopped.

Internal data bus

ADS

ADMOD1

ADMOD0

ADMOD2

ADMOD4/5

ADMOD3

HTSEL/HHTRGE

ITM/LAT

TSEL/HTRGE
Scan
repeat

Channel
selection
control circuit
End Busy

Start

AD Monitor
Function control

AD Monitor function interrupt
INTADM
AD start control

End

Busy

Start
ADTRG

Normal AD
Converter Control
Circuit

High-Priority AD
Converter Control

AN2 (PG2)
AN1 (PG1)
AN0 (PG0)

Compare register
1 and 2

Sample
Hold

+
−
Comparator

Compare circuit
1&2

A / D Conversion
Result Register
ADREG0L~5L
ADREG0H~5H
High-Priority AD
Conversion
Result Register
ADREGSPH/L

VREF
VREFH
VREFL

D/A Converter

Figure 3.23.1 ADC Block Diagram

92CZ26A-595

Internal data bus

AN4 (PG4)
ADTRG, AN3 (PG3)

Multiplexer

AN5 (PG5)

TRMB/ I2S
Complete interrupt AD
INTADHP
Normal AD Conversion
complete interrupt
INTAD

TMP92CZ26A
3.23.1

Control register
The AD converter has 6-mode control registers (ADMOD0, ADMOD1, ADMOD2,
ADMOD3, ADMOD4 and ADMOD5) and 6-conversion result high/low register pairs
(ADREG0H/L ∼ ADREG5H/L). The results of high-priority AD conversion are stored in the
ADREGSPH/L.
Figure 3.23.2 to Figure 3.23.11 show the registers available in the AD converter.
AD Mode Control Register 0 (Normal conversion control)

ADMOD0
(12B8H)

7

6

bit Symbol

EOS

BUSY

Read/Write

R

R

After reset
Function

0

5

4

3

2

1

0

I2AD

ADS

HTRGE

TSEL1

TSEL0

0

0

R/W

0

0

0

0

Normal AD

Normal AD

AD

Start Normal

Normal AD

conversion

conversion

conversion

AD conversion

conversion at

end flag

BUSY Flag

when

0: Don’t Care

Hard ware

00: INTTB00 interrupt

trigger

01: Reserved

0: Disable

10: ADTRG

1: Enable

11: Reserved

0:During
conversion
sequence
or before
starting

IDLE2 mode 1:Start
0:Stop
conversion
1:During

AD conversion
0: Stop
1: Operate

conversion

Always read
as”0”.

1:Complete
conversion
sequence

Figure 3.23.2 AD Conversion Registers

92CZ26A-596

Select Hard ware trigger

TMP92CZ26A
AD Mode Control Register 1 (Normal conversion control)

ADMOD1
(12B9H)

bit Symbol

7

6

5

4

3

2

1

0

DACON

ADCH2

ADCH1

ADCH0

LAT

ITM

REPEAT

SCAN

0

0

0

0

Read/Write
After reset

Function

R/W
DAC
and Analog input channel select
VREF
application
control

0
Latency
0: No Wait
1:Start after
reading
conversion
result store
Register of
last channel

0

0

0

Interrupt
specification
when
conversion
channel fixed
repeat mode

Repeat mode
specification
0: Single
conversion
1: Repeat
conversion

Scan mode
specification
0: Channel
fixed mode
1: Channel
scan mode

Specify AD conversion interrupt for Channel Fixed
Repeat Conversion mode
Channel Fixed Repeat Conversion Mode
 = “0”,  = “1”
0 Generates interrupt every conversion
1 Generated interrupt every fourth conversion
Next SCAN start timing control for the channel
scan repeat mode
Channel Scan Repeat mode
( = 1,  = 1)
0 No Wait
1 Start after read last of conversion result
store Register
Analog input channel select

0:
Channel

fixed
000
AN0
001
AN1
010
AN2
011
AN3(note)
100
AN4
101
AN5
110
Reserved
111
Reserved

1:
Channel scanned
AN0
AN0→AN1
AN0→AN1→AN2
AN0→AN1→AN2→AN3 (note)
AN0→AN1→AN2→AN3→AN4 (note)
AN0→AN1→AN2→AN3→AN4→AN5 (note)

Note: When using PG3 pin as ADTRG , it cannot be set.
DAC & VREF application control
0 DAC & VREF off
(Set before into STOP mode)
1 DAC & VREF on
(Set to “1” before starting conversion)

Figure 3.23.3 AD Converter Related Register

92CZ26A-597

TMP92CZ26A

AD Mode Control Register 2 (High-priority conversion control)
ADMOD2
(12BAH)

7

6

bit Symbol

HEOS

HBUSY

Read/Write

R

R

0

0

After reset
Function

5

4

conversion
sequence
or before
starting
1: Complete
conversion
sequence

2

HADS

HHTRGE

1

0

HTSEL1

HTSEL0

0

0

R/W
0

High-priority
High-priority
AD conversion AD conversion
sequence
BUSY Flag
FLAG
0: During

3

0

Start
High-priority
AD conversion
0: Don’t Care
1: Start AD
conversion

0:Stop
conversion
1:During
conversion

High-priority
AD conversion
at Hard ware
trigger
0: Disable
1: Enable

Select Hard ware trigger
00: INTTB10 interrupt
01: Reserved
10: ADTRG
11: I2S Sampling Counter
Output

Always read
as”0”.

AD Mode Control Register 3 (High-priority conversion control)

ADMOD3
(12BBH)

7

6

5

4

bit Symbol

−

HADCH2

HADCH1

HADCH0

Read/Write

R/W

After reset
Function

0
Always write
“0”.

3

2

0

0
−

R/W
0

1

R/W
0

0

High-priority analog input channel select

Always write
“0”.

Analog input channel select
Analog input
channel when
High-priority


000
001
010
011
100
101
110
111

conversion

AN0
AN1
AN2
AN3(note)
AN4
AN5
Reserved
Reserved

Note: When using PG3 pin as ADTRG , it cannot be set.

Figure 3.23.4 AD Conversion Registers

92CZ26A-598

TMP92CZ26A
AD Mode Control Register 4 (AD Monitor function control)
ADMOD4
(12BCH)

7

6

5

4

3

2

1

0

bit Symbol

CMEN1

CMEN0

CMP1C

CMP0C

IRQEN1

IRQEN0

CMPINT1

CMPINT0

Read/Write

R/W

R/W

R

R

After reset

0

0

0

0

Function

R/W
0

0

0

0

AD Monitor

AD Monitor

Generation

Generation

AD monitor

AD monitor

Status of

Status of

function1

function0

condition of

condition of

function

function

AD monitor

AD monitor

0: Disable

0: Disable

AD monitor

AD monitor

interrupt 1

interrupt 0

function

function

1: Enable

1: Enable

function

function

0: Disable

0: Disable

interrupt 1

interrupt 0

interrupt 1

interrupt 0

1: Enable

1: Enable

0: No

0: No

0: less than

0: less than

(Note)

(Note)

generation

generation

1: Greater

1: Greater

1: Generation

1: Generation

than or Equal

than or Equal

Note: When AD monitor function interrupts generate, it is cleared automatically and it is set to
disable condition.

AD Mode Control Register 5 (AD Monitor function control)
7
ADMOD5
(12BDH)

bit Symbol

6

5

4

CMCH2

CM1CH1

CM1CH0

Read/Write
After reset
Function

3

2

1

0

CM0CH2

CM0CH1

CM0CH0

R/W
0

0

R/W
0

0

0

0

Select analog channel for AD monitor function 1

Select analog channel for AD monitor function 0

000: AIN0

100: AN4

000: AIN0

100: AN4

001: AIN1

101: AN5

001: AIN1

101: AN5

010: AIN2

110: Reserved

010: AIN2

110: Reserved

011: AN3

111: Reserved

011: AN3

111: Reserved

Note1: When converting AD in hard ware trigger by setting  and to “1”, set
PGFC to “1” (as ADTRG) in case of external TRG before enabling it. When using
an INTTBx0 of 16-bit timer, first set the  or  bit to “00” when the
timer is not operating. Then, set the  and  to “1” and enable trigger
operation. Finally, operate the timer so that AD conversion will be initiated at constant
intervals.
Note 2: When disabling an external trigger ( ADTRG ) for AD conversion, first clear the  or
 bit to “0”, and clear the PGFC to “0”, thus configuring port G as a
general-purpose port.
Note 3: When starting AD by using external trigger (ADTRG), it can be started after enabling
( = “1” or  = “1”) and 3 clock at fSYS was executed. AD is not started
when before that time.
Note 4: When chaging compare register value of AD Monitor function, change it after setting AD
Monitor function to disable(ADMOD4=”0”).

Figure 3.23.5 AD Conversion Registers

92CZ26A-599

TMP92CZ26A
AD Conversion Result Register 0 Low
ADREG0L
(12A0H)

bit Symbol

7

6

ADR01

ADR00

Read/Write
After reset
Function

5

4

3

2

R
0

0

1

0

OVR0

ADR0RF

R

R

0

0

Overrun flag

Store Lower 2 bits of
AN0 AD conversion

0:No generate
1: Generate

result

AD conversion
result store
flag
1: Stored

AD Conversion Result Register 0 High
bit Symbol

ADREG0H
(12A1H)

7

6

5

4

3

2

1

0

ADR09

ADR08

ADR07

ADR06

ADR05

ADR04

ADR03

ADR02

0

0

0

0

1

0

OVR1

ADR1RF

R

R

Read/Write
After reset

R
0

0

0

Function

0

Store Upper 8 bits of AN0 AD conversion result

AD Conversion Result Register 1 Low
7
bit Symbol

ADREG1L
(12A2H)

6

ADR11

Read/Write
After reset
Function

5

4

3

2

ADR10
R

0

0

0

0

Overrun flag

Store Lower 2 bits of
AN1 AD conversion

0:No generate
1: Generate

result

AD conversion
result store
flag
1: Stored

AD Conversion Result Register 1 High
bit Symbol

ADREG1H
(12A3H)

7

6

5

4

ADR19

ADR18

ADR17

ADR16

Read/Write
After reset

3

2

1

0

ADR15

ADR14

ADR13

ADR12

0

0

0

0

R
0

0

0

Function

0

Store Upper 8 bits of AN1 AD conversion result
9

8

7

6

ADREGxH
7 6 5

4

5

4

3

2

1

0

7

6

Channel X conversion result

•
•
•

3

2

1

0

5

4

3

2

ADREGxL
1 0

Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag . When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
Bit 1 is the Overrun flag . This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.

Figure 3.23.6 AD Conversion Registers

92CZ26A-600

TMP92CZ26A
AD Conversion Result Register 2 Low
ADREG2L
(12A4H)

bit Symbol

7

6

ADR21

ADR20

Read/Write
After reset
Function

5

4

3

2

R
0

0

1

0

OVR2

ADR2RF

R

R

0

0

Overrun flag

AD conversion
result store
0:No generate flag
1: Generate
1: Stored

Store Lower 2 bits of
AN2 AD conversion
result

AD Conversion Result Register 1 High
ADREG2H
(12A5H)

bit Symbol

7

6

5

4

ADR29

ADR28

ADR27

ADR26

Read/Write
After reset

3

2

1

0

ADR25

ADR24

ADR23

ADR22

0

0

0

0

R
0

0

0

Function

0

Store Upper 8 bits of AN2 AD conversion result

AD Conversion Result Register 3 Low
ADREG3L
(12A6H)

bit Symbol

7

6

ADR31

ADR30

Read/Write
After reset
Function

5

4

3

2

R
0

0

1

0

OVR3

ADR3RF

R

R

0

0

Overrun flag

AD conversion
result store
0:No generate flag
1: Generate
1: Stored

Store Lower 2 bits of
AN3 AD conversion
result

AD Conversion Result Register 3 High
ADREG3H
(12A7H)

bit Symbol

7

6

5

4

3

2

1

0

ADR39

ADR38

ADR37

ADR36

ADR35

ADR34

ADR33

ADR32

0

0

0

0

0

0

0

0

Read/Write
After reset

R

Function

Store Upper 8 bits of AN3 AD conversion result
9

8

7

6

ADREGxH
7 6 5

4

5

4

3

2

1

0

7

6

Channel X conversion result

•
•
•

3

2

1

0

5

4

3

2

ADREGxL
1 0

Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag . When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
Bit 1 is the Overrun flag . This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.

Figure 3.23.7 AD Conversion Registers

92CZ26A-601

TMP92CZ26A
AD Conversion Result Register 4 Low
ADREG4L
(12A8H)

bit Symbol

7

6

ADR41

ADR40

Read/Write
After reset
Function

5

4

3

2

R
0

0

1

0

OVR4

ADR4RF

R

R

0

0

Overrun flag

AD conversion
result store
0:No generate flag
1: Generate
1: Stored

Store Lower 2 bits of
AN4 AD conversion
result

AD Conversion Result Register 4 High
ADREG4H
(12A9H)

bit Symbol

7

6

5

4

ADR49

ADR48

ADR47

ADR46

Read/Write
After reset

3

2

1

0

ADR45

ADR44

ADR43

ADR42

0

0

0

0

R
0

0

0

Function

0

Store Upper 8 bits of AN4 AD conversion result

AD Conversion Result Register 5 Low
ADREG5L
(12AAH)

bit Symbol

7

6

ADR51

ADR50

Read/Write
After reset
Function

5

4

3

2

R
0

0

1

0

OVR5

ADR5RF

R

R

0

0

Overrun flag

AD conversion
result store
0:No generate flag
1: Generate
1: Stored

Store Lower 2 bits of
AN5 AD conversion
result

AD Conversion Result Register 5 High
ADREG5H
(12ABH)

bit Symbol

7

6

5

4

3

2

1

0

ADR59

ADR58

ADR57

ADR56

ADR55

ADR54

ADR53

ADR52

0

0

0

0

Read/Write
After reset

R
0

0

0

Function

0

Store Upper 8 bits of AN5 AD conversion result
9

8

7

6

ADREGxH
7 6 5

4

5

4

3

2

1

0

7

6

Channel X conversion result

•
•
•

3

2

1

0

5

4

3

2

ADREGxL
1 0

Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag . When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
Bit 1 is the Overrun flag . This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.

Figure 3.23.8 AD Conversion Registers

92CZ26A-602

TMP92CZ26A
High-priority AD Conversion Result Register SP Low
ADREGSPL
(12B0H)

bit Symbol

7

6

ADRSP1

ADRSP0

Read/Write
After reset
Function

5

4

3

2

R
0

0

1

0

OVSRP

ADRSPRF

R

R

0

0

Overrun flag

AD conversion
result store
0:No generate flag
1: Generate
1: Stored

Store Lower 2 bits of an
AD conversion result

High-priority AD Conversion Result Register SP High
ADREGSPH
(12B1H)

bit Symbol

7

6

5

4

3

2

1

0

ADRSP9

ADRSP8

ADRSP7

ADRSP6

ADRSP5

ADRSP4

ADRSP3

ADRSP2

0

0

0

0

Read/Write
After reset

R
0

0

0

Function

0

Store Upper 8 bits of an AD conversion result
9

8

7

6

ADREGxH
7 6 5

4

5

4

3

2

1

0

7

6

Channel X conversion result

•
•
•

3

2

1

0

5

4

3

2

ADREGxL
1 0

Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag . When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
Bit 1 is the Overrun flag . This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.

Figure 3.23.9 AD Conversion Registers

92CZ26A-603

TMP92CZ26A
AD Conversion Result Compare Criterion Register 0 Low
ADCM0REGL
(12B4H)

bit Symbol

7

6

ADR21

ADR20

Read/Write
After reset
Function

5

4

3

2

1

0

R/W
0

0

Store Lower 2 bits of an
AD conversion result
compare criterion

AD Conversion Result Compare Criterion Register 0 High
ADCM0REGH
(12B5H)

bit Symbol

7

6

5

4

ADR29

ADR28

ADR27

ADR26

Read/Write
After reset

3

2

1

0

ADR25

ADR24

ADR23

ADR22

0

0

0

0

R/W
0

0

Function

0

0

Store Upper 8 bits of an AD conversion result compare criterion

AD Conversion Result Compare Criterion Register 1 Low
ADCM1REGL
(12B6H)

bit Symbol

7

6

ADR21

ADR20

Read/Write
After reset
Function

5

4

3

2

1

0

R/W
0

0

Store Lower 2 bits of an
AD conversion result
compare criterion

AD Conversion Result Compare Criterion Register 1 High
ADCM1REGH
(12B7H)

bit Symbol

7

6

5

4

3

2

1

0

ADR29

ADR28

ADR27

ADR26

ADR25

ADR24

ADR23

ADR22

0

0

0

0

0

0

0

0

Read/Write
After reset
Function

R/W
Store Upper 8 bits of an AD conversion result compare criterion

Note: Disable the AD monitor function (ADMOD4 = “0”) before attempting to set or modify
the value of these registers.

Figure 3.23.10 AD Conversion Registers

92CZ26A-604

TMP92CZ26A
AD Conversion Clock Setting Register
7
ADCCLK
(12BFH)

3

2

1

0

bit Symbol

6

5

4

−

ADCLK2

ADCLK1

ADCLK0

Read/Write

R/W

R/W

R/W

R/W

After reset

0
Always
write “0”

Function

0
0
0
Select clock for AD conversion
000 : Reserved 100 : fIO/4
101 : fIO/5
001 : fIO/1
110 : fIO/6
010 : fIO/2
011 : fIO/3
111 : fIO/7

Note1: AD conversion is executed at the clock frequency selected in the above register. To assure
conversion accuracy, however, the conversion clock frequency must not exceed 12MHz
MHz.
Note2: Don ‘t change the clock frequency while AD conversion is in progress.

Figure 3.23.11 AD Conversion Registers


÷1 ∼ ÷7

fSYS

ADCLK

fIO(fSYS/2)
40MHz
30MHz



ADCLK

100(fIO/4)

10.0MHZ

AD conversion
speed
12 μsec

101(fIO/5)
011(fIO/3)

8MHZ
10.0MHZ

15 μsec
12 μsec

100(fIO/4)

7.5MHZ

16 μsec

AD conversion speed can be calculated by following.
Conversion speed = 120 × (1/ADCLK)

92CZ26A-605

TMP92CZ26A

3.23.2

Operation

3.23.2.1

Analog Reference Voltages
The VREFH and VREFL pins provide the analog reference voltages for the ADC.

3.23.2.2

Analog Input Channel(s) selection
The Analog input channels used for AD conversion are selected as follows:

(1)

Normal AD conversion
• Analog Input Channel Fixed mode (ADMOD1 = “0”)
Setting ADMOD1 selects one of the input pins AN0 to AN5 as the input
channel.
• Analog Input Channel Scan Mode (ADMOD1 = “1”)
Setting ADMOD1 selects one of the six scan modes.

(2)

High-priority AD conversion
Setting ADMOD3 selects one of the eight input pins AN0 ∼ AN5.
On a Reset, ADMOD1 is set to “0”, and ADMOD1 is initialized
to “000”. Thus pin AN0 is selected as the fixed input channel. Pins that are not used as
analog input channels can be used as standard input port pins.
If a high-priority AD conversion is triggered while a normal AD conversion is in
progress, the normal AD conversion sequence is suspended after converting data for
the current channel, to perform a high-priority AD conversion. After a high-priority
AD conversion is performed, the normal AD conversion sequence is resumed with that
channel.

92CZ26A-606

TMP92CZ26A

3.23.2.3

Starting an AD Conversion
The ADC supports two types of AD conversion: normal AD conversion and
high-priority AD conversion. The ADC initiates a normal AD conversion by software
when the ADMOD0 is set to “1”. It initiates a high-priority AD conversion by
software when the ADMOD2 is set to “1”. For a normal AD conversion,
ADMOD1 select one of four conversion modes. For a high-priority
AD conversion, the ADC only supports Fixed-Channel Single Conversion mode.
The ADMOD0 and ADMOD2 enable a hardware trigger for
a normal and high-priority AD conversion, respectively. When these bits are set to “10”,
a normal or high-priority AD conversion is triggered by a falling edge applied to
ADTRG pin. When ADMOD0 is set to “00”, a normal AD conversion is
triggered by INTTB00 of 16-Bit Timer interrupt. When ADMOD2 is set
to “00”, a high-priority AD conversion is triggered by INTTB10 of 16-Bit Timer
interrupt. If this bit is “11”, it is triggered by I2S sampling block. Even when a
hardware trigger is enabled, software starting can be used.
When a normal AD conversion starts, the Busy flag (ADMOD0) is set to “1”.
When a high-priority AD conversion starts, the high-priority AD conversion busy flag
(ADMOD2) is set to “1”. During a normal AD conversion, if a high-priority
AD conversion start, ADMOD0 holds “1”.
When an AD conversion complete, ADMOD0 and ADMOD2 is set to
“1”. These flags are cleared to “0” by reading these flags only.
During a normal AD conversion, writing a “1” to ADMOD0 causes the ADC
to abort any ongoing conversion immediately, and restart.
During a normal AD conversion, if normal AD conversion starting is enabled by
hard ware trigger, normal AD conversion is restarted when start condition from hard
ware trigger is satisfied. When restart is set, normal AD conversion is aborted
immediately.
During a normal AD conversion, if a high-priority AD conversion starts(writing a “1”
to ADMOD2 or a hard ware trigger occurs), the ADC aborts any ongoing
conversion immediately, and then start a high-priority AD conversion for the channel
specified by ADMOD3. Upon the completion of the high-priority
conversion, the ADC stores the conversion result to ADREGSPH/L, and then resumes
the suspended normal conversion with that channel.

Note: It cannot overlap with three or more AD conversions.
Prohibition example 1 : In FIRST normal AD conversion
Æ (Before finished FIRST normal AD conversion) Started SECOND normal AD conversion
Æ (Before finished SECOND normal AD conversion) Started THIRD normal AD conversion
Prohibition example 2 : In FIRST normal AD conversion
Æ (Before finished FIRST normal AD conversion) Started SECOND normal AD conversion
Æ (Before finished SECOND normal AD conversion) Started THIRD high-priority AD conversion

92CZ26A-607

TMP92CZ26A

3.23.2.4

AD Conversion Modes and AD Conversion-End Interrupts
The ADC supports the following four conversion modes. For a normal AD conversion,
ADMOD0<1:0> select one of the four conversion modes. For a high-priority AD
conversion, the ADC only supports Channel Fixed Single Conversion mode.
a. Channel Fixed Single Conversion mode
b. Channel Scan Single Conversion mode
c.

Channel Fixed Repeat Conversion mode

d. Channel Scan Repeat Conversion mode
(1)

Normal AD conversion
ADMOD0 select the conversion mode. Once a conversion is
started, the ADMOD0 is set to “1”. The ADC generates the AD Conversion
End interrupt (INTAD) and sets the ADMOD0 to “1” at the end of the specified
conversion process.
a. Channel Fixed Single Conversion mode
This mode is selected by programming ADMOD0 to “00”.
In this mode, the ADC performs a single conversion on a single selected
channel. When a conversion is completed, the ADC sets the ADMOD0,
and generates the INTAD interrupt. ADMOD0 is cleared to “0” when it is
read.
b. Channel Scan Single Conversion mode
This mode is selected by programming ADMOD0 to “01”. In
this mode, the ADC performs a single conversion on each of a selected group of
channels. When a single conversion sequence is completed, ADMOD0 is
set to “1”, and generates the INTAD interrupt. ADMOD0 is cleared to “0”
by reading this bit only.
c. Channel Fixed Repeat Conversion mode
This mode is selected by programming ADMOD0 to “10”. In
this mode, the ADC repeatedly converts a single selected channel. When a
conversion process is completed, ADMOD0 is set to “1”.
ADMOD1 control INTAD interrupts generation in this mode. The
timing when ADMOD0 is set also depends on the ADMOD1. The
EOCF bit is cleared when it is read. ADMOD0 is cleared to “0” by reading
this bit only.
If ADMOD1 is set to “0”, the ADC generates an interrupt after each
conversion. The results of conversion are always stored in the ADREGxH/L
register. The ADMOD0 is set to “1” when the ADC stores the results to the
ADREGxH/L.

92CZ26A-608

TMP92CZ26A
If ADMOD1 is set to “1”, the ADC generates an interrupt after every
four conversions. The results of conversions are sequentially stored in the
ADREG0H/L to ADREG3H/L registers, in that order. The ADMOD0 is set
to “1” when the ADC stores the results in the ADREG3H/L. The next conversion
results are again stored in the ADREG0, and so on. The ADMOD0 is
cleared to “0” by reading this bit only.

d. Channel Scan Repeat Conversion mode
This mode is selected by programming ADMOD0  to “11”. In
this mode, the ADC repeatedly converts the selected group of channels. When a
single conversion sequence is completed, the ADC sets ADMOD0 to “1”,
and generates the INTAD interrupt. ADMOD0 is cleared to “0” by reading
this bit only.
In continuous conversion modes (3) and 4)), clearing the ADMOD1
stops the conversion sequence after the ongoing scan conversion process is
completed.
Shift to a standby mode (IDLE2 Mode with ADMOD0 = “0”, IDLE1
Mode or STOP Mode) immediately stops operation of the AD converter even if AD
conversion is still in progress. Therefore, ADC may consume current even if
operation is stopped, depending on stop condition of ADC that switches to
standby mode. For avoiding this problem, Stop ADC before switching to standby
mode.

(2)

High-priority AD conversion
For a high-priority AD conversion, the ADC only supports Channel Fixed Single
Conversion mode, regardless of the settings of ADMOD1.
When a conversion start condition is satisfied, the ADC performs a single conversion
on a single selected channel, which is specified with the ADMOD3.
When a conversion is completed, the ADC sets ADMOD2to “1”. HEOS Flag is
cleared to “0” by reading this bit only.

92CZ26A-609

TMP92CZ26A

Interrupt Generation Timing and Flag Setting in Each AD Conversion Mode
Conversion mode

Interrupt
Generation
Timing

EOS set timing
(Note)

ADMOD1
ITM

REPEAT

SCAN

−

0

0

1

0

Channel Fixed
Single Conversion
Mode

After a
conversion

After a
conversion

Channel Fixed
Repeat
Conversion Mode

After every
conversion

After every
conversion

After every
four
conversions

After every
four
conversions

1

Channel Scan
Single Conversion
Mode

After a scan
conversion
sequence

After a scan
conversion
sequence

−

0

1

Channel Repeat
Single Conversion
Mode

After each
scan
conversion
sequence

After each
scan
conversion
sequence

−

1

1

0

Note: EOS is cleared to “0” by reading this bit only.

92CZ26A-610

TMP92CZ26A
3.23.2.5

High-Priority Conversion Mode
The ADC can perform a high-priority AD conversion while it is performing a normal
AD conversion sequence. A high-priority AD conversion can be started at software by
setting the ADMOD2 to “1”. It is also triggered by a hardware trigger if so
enabled using ADMOD2. If a high-priority AD conversion is triggered
during a normal AD conversion, the ADC aborts any ongoing conversion immediately,
and then begins a single high-priority AD conversion for the channel specified with the
ADMOD3. Upon the completion of the high-priority AD conversion, the
ADC stores the results of the conversion in the ADREGSPH/L, generates the
high-priority AD conversion interrupt (INTADHP), and then resumes the suspended
normal conversion with that channel. While a high-priority conversion is being
performed, a trigger for another high-priority conversion is ignored.

Example: In the case of a high-priority AD conversion for AN5 (ADMOD3=”101”) is started durring a
normal AD conversion in channel scan repeat mode for AN0 to AN3 (ADMOD1 = “11”、
ADMOD1 = “011”)
High-priority AD
conversion start trigger
Conversion channel

AN0

AN1

AN2

AN5

AN2

Abort conversion

conversion for AN2

for AN2

again

AN3

AN0

Start conversion for AN5

3.23.2.6

AD Monitor Function
When ADMOD4 is set to “1”, the AD monitor function is enabled. This
function generates an interrupt depending on condition of IRQEN1:0, when the
finished AD conversion of the channel which specified with the ADMOD5 register, if
the value of the AD conversion result register pair is greater or less (specified with
CMP1C:0C) than the value of the compare criterion register 0/1(ADCMxREGH/L).
The ADC performs this comparison each times it stores results to the specified AD
conversion result register and generate interrupt (INTADM) when condition is
satisfied. The conversion result register used for the AD monitor function is usually
not read in the program, so mind that its overrun flag  and conversion result
store flag  are always set.
If these are assigned to different channel, 2-analog channel can monitor “less” or
“grater”. And if these are assigned same analog channel, the watch that sets the range
of the voltage is possible.

3.23.2.7

AD Conversion Time
AD conversion of one time is 120 clocks that include sampling clock. The AD
conversion clock can be selected from 1/1 to 1/7 of fIO by ADCLK. To
assure conversion accuracy, the AD conversion clock frequency need to select 12 MHz
and under, i.e., AD conversion time need to select 10 µs and over.

92CZ26A-611

TMP92CZ26A

3.23.2.8

Storing and Reading the AD Conversion Result
Conversion results are stored into AD conversion result high/low register
(ADREG0H/L to ADREG5H/L).
In Channel Fixed Repeat Conversion mode, conversion results are stored into the
ADREG0H/L to ADREG3H/L sequentially.
In other modes, the AD conversion result of channel AN0, AN1, AN2, AN3, AN4, and
AN5 is stored in ADREG0H/L, ADREG1H/L, ADREG2H/L, ADREG3H/L,
ADREG4H/L, and ADREG5H/L respectively.
Table 3.23.1 shows the relationships between the analog input channels and the AD
conversion result registers.

92CZ26A-612

TMP92CZ26A

Table 3.23.1 Relationships between Analog Input Channels and AD Conversion Result Registers
AD Conversion Result Registers
Analog Input Channel
(Port G)

Conversion Modes
other than at right

AN0

ADREG0H/L

AN1

ADREG1H/L

AN2

ADREG2H/L

AN3

ADREG3H/L

AN4

ADREG4H/L

AN5

ADREG5H/L

Channel Fixed Repeat
Conversion Mode
(every fourth conversion)
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L

Note: For detect a overrun error thoroughly, read the AD conversion result register high at first and
read the AD conversion result register low at second. If OVRn=”0” and ADRnRF=”1”, a
correct conversion result was obtained.

3.23.2.9

Data Polling
When the results of AD conversion are processed by means of data polling without
using interrupts, ADMOD0 should be polled. After confirming ADMOD0
=”1”, read the AD conversion result register.

92CZ26A-613

TMP92CZ26A

Setting example:
1.

Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD
interrupt(INTAD) processing routine.

Main routine
7

6

5

4

3

2

1

0

INTEAD

←

1

1

0

0

←

1

1

0

0

−
0

−
1

−
1

Enable INTAD and set it to interrupt level 4.

ADMOD1

−
0

← X X 0 0 0
Interrupt routine processing example

0

0

1

Start conversion in channel fixed single conversion mode.

ADMOD0

← ADREG3

WA

Set pin AN3 to be the analog input channel.

Read value of ADREG3L and ADREG3H into 16-bits
general-purpose register WA.

← >>6

WA

Shift contents read into WA six times to right and zero fill
upper bits.

(2800H)
2.

← WA

Write contents of WA to memory address 2800H.

This example repeatedly converts the analog input voltages on the three pins AN0, AN1 and AN2, using channel
scan repeat conversion mode.

INTEAD

←

1

0

0

0

←

1

1

0

0

−
0

−
0

−
1

−
0

Disable INTAD.

ADMOD1
ADMOD0

← X

X

0

0

0

1

1

1

Start conversion in channel scan repeat conversion mode.

Set pins AN0 to AN2 to be the analog input channels.

3. Convert the analog input voltage on the AN2 pin as a high-priority AD conversion, and write the result to memory
address 2A00H using the High-priority AD interrupt(INTADHP) processing routine.
Main routine
INTEAD

←

1

1

0

1

ADMOD1

←

1

0

0

0

−
0

−
0

−
0

−
0

DAC On.

ADMOD3

←

0

0

1

0

0

0

0

0

Set pin AN2 to be the analog input channel.

← 0 0 0 0 1
Interrupt routine processing example

0

0

0

Start a high-priority AD conversion by software.

ADMOD2

← ADREGSP

WA

Enable INTADHP and set it to interrupt level 6.

Read value of ADREGSPL and ADREGSPH into 16-bits
general-purpose register WA.

← >>6

WA

Shift contents read into WA six times to right and zero fill
upper bits.

(2A00H)

← WA

Write contents of WA to memory address 2A00H.

4. Convert the analog input voltage on the AN4 pin as a normal AD conversion of a channel fixed single conversion
mode. And then if its conversion result is greater or equal than the value of (ADCM0REGL/H), write the result to
memory address 2C00H using the AD monitor function interrupt (INTADM) processing routine.
Main routine
INTEAD

←

−
0

−
0

−
0

0

1

1

←

−
0

1

ADMOD5

1

0

0

0

Set the analog input channel AN4 for AD monitor function 0.

ADMOD4

←

0

0

1

0

0

0

0

0

Enable the AD monitor function0 and AD monitor function

Enable INTAD and set it to interrupt level 3.

interrupt 0. Set “a conversion result ≥ AD conversion result
compare criterion register” for generation condition of monitor
function interrupt 0.
ADMOD1

←

1

0

1

0

0

0

0

Set pin AN4 to be the analog input channel.

← 0 0 0 0 1
Interrupt routine processing example

0

0

0

Start a normal AD conversion by software.

ADMOD0
WA

← ADREG4

0

Read value of ADREG4L and ADREG4H into 16-bits
general-purpose register WA.

WA

← >>6

Shift contents read into WA six times to right and zero fill
upper bits.

← WA
X : Don't care, − : No change

(2C00H)

Write contents of WA to memory address 2C00H.

92CZ26A-614

TMP92CZ26A

3.24 Watchdog Timer (Runaway detection timer)
The TMP92CZ26A contains a watchdog timer of runaway detecting.
The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that
the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
Connecting the watchdog timer output to the reset pin internally forces a reset.
(The level of external RESET pin is not changed.)

3.24.1

Configuration
Figure 3.24.1 is a block diagram of the watchdog timer (WDT).

WDMOD
RESET pin

Reset control

Internal reset

INTWD interrupt

WDMOD


Selector
2

15

2

17

2

19

2

21

Q

Binary counter
(22 stages)

fIO

R

S

Reset

Internal reset
Write
4EH

Write
B1H

WDMOD


WDT control register WDCR

Internal data bus

Figure 3.24.1 Block Diagram of Watchdog Timer
Note: It needs to care designing the total machine set, because Watchdog timer can’t operate completely by
external noise.

92CZ26A-615

TMP92CZ26A
3.24.2

Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD has elapsed. The watchdog timer must be cleared “0” in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-malfunction
program.
The watchdog timer begins operating immediately on release of the watchdog timer
reset.
The watchdog timer is halted in IDLE1 or STOP mode. The watchdog timer counter
continues counting during bus release (when BUSAK goes low).
When the device is in IDLE2 mode, the operation of WDT depends on the
WDMOD setting. Ensure that WDMOD is set before the device enters
IDLE2 mode.
The watchdog timer consists of a 22-stage binary counter which uses the clock (fIO) as the
input clock. The binary counter can output 215/ fIO, 217/ fIO, 219/fIO and 221/ fIO. Selecting one
of the outputs using WDMOD generates a watchdog timer interrupt when an
overflow occurs.

WDT counter

Overflow

n

0

WDT interrupt
Write clear code
WDT clear
(Soft ware)

Figure 3.24.2 Normal Mode
The runaway detection result can also be connected to the reset pin internally.
In this case, the reset time will be 32 clocks (102.4 μs at fOSCH = 10 MHz) as shown in
Figure 3.24.3. After a reset, the clock fIO is divided fSYS by two, where fSYS is generated by
dividing the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function

Overflow
WDT counter

n

WDT interrupt
Internal reset
32 clocks (102.4 μs at fOSCH = 10 MHz)

Figure 3.24.3 Reset Mode

92CZ26A-616

TMP92CZ26A
3.24.3

Control Registers
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode registers (WDMOD)
1.

Setting the detection time for the watchdog timer in 
This 2-bit register is used for setting the watchdog timer interrupt time used
when detecting runaway.
On a reset this register is initialized to WDMOD = 00.
The detection time for WDT is 215/fIO [s]. (The number of system clocks is
approximately 65, 536.)

2.

Watchdog timer enable/disable control register 
At reset, the WDMOD is initialized to “1”, enabling the watchdog
timer.
To disable the watchdog timer, it is necessary to clear this bit to “0” and to write
the disable code (B1H) to the watchdog timer control register (WDCR). This
makes it difficult for the watchdog timer to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to
the enabled state merely by setting  to “1”.

3.

Watchdog timer out reset connection 
This register is used to connect the output of the watchdog timer with the
RESET terminal internally. Since WDMOD is initialized to 0 at reset, a
reset by the watchdog timer will not be performed.

(2) Watchdog timer control registers (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
•

Disable control
The watchdog timer can be disabled by clearing WDMOD to 0 and then
writing the disable code (B1H) to the WDCR register.

•

WDCR

←

0

1

0

0

1

1

1

0

WDMOD

←

0

−

−

X

X

−

−

0

Clear WDMOD  to “0”.

WDCR

←

1

0

1

1

0

0

0

1

Write the disable code (B1H).

Write the clear code (4EH).

Enable control
Set WDMOD to “1”.

•

Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code
(4EH) to the WDCR register.
WDCR

←

0

1

0

0

1

1

1

0

Write the clear code (4EH).

Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please
refer to setting example.)
Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once.

92CZ26A-617

TMP92CZ26A

WDMOD
(1300H)

Bit symbol

7

6

5

WDTE

WDTP1

WDTP0

Read/Write
After reset
Function

4

3

2

1

0

I2WDT

RESCR

−

R/W
1

0

R/W
0

0

WDT control Select detecting time
1: Enable

IDLE2

15

0: Stop

17

1: Operate

00: 2 /fIO
01: 2 /fIO
19

10: 2 /fIO
21

0
1: Internally
connects
WDT out
to the
reset pin

0
Always
write “0”

11: 2 /fIO

Watchdog timer out control
0

−

1

Connects WDT out to a reset

IDLE2 control
0

Stop

1

Operation

Watchdog timer detection time
00

2 /fIO (Approximately 819.2 μs at fIO = 40 MHz)

01

2 /fIO (Approximately 3.276 ms at fIO = 40 MHz)

10

2 /fIO (Approximately 13.107 ms at fIO = 40 MHz)

11

2 /fIO (Approximately 52.428 ms at fIO = 40 MHz)

15
17
19
21

Watchdog timer enable/disable control
0

Disabled

1

Enabled

Figure 3.24.4 Watchdog Timer Mode Register

7

6

5

4

3

WDCR
(1301H)

Bit symbol

−

Read/Write

W

Read
-modify
-write
instruction is
prohibited

After reset

−

Function

2

1

B1H: WDT disable code
4EH: WDT clear code

WDT disable/clear control
B1H

Disable code

4EH

Clear code

Others

Don’t care

Figure 3.24.5 Watchdog Timer Control Register

92CZ26A-618

0

TMP92CZ26A

3.25

Power Management Circuit (PMC)

The TMP92CZ26A incorporates a power management circuit (PMC) for managing power
supply in standby state as protective measures against leak current in fine-process products.
The following six power supply rails are available.
: AVCC & AVSS (for ADC)
･Analog power supply
: DVCC3A, 3B & DVSSCOM (for general pins)
･3V-A, 3V-B digital I/O power supply
･1.5V-A digital internal power supply : DVCC1A & DVSSCOM (for general circuits)
･1.5V-B digital internal power supply : DVCC1B & DVSSCOM (for RTC, PMC)
: DVCC1C & DVSS1C
･1.5V-C oscillation power supply
(for high-frequency oscillator, PLL)

Each power supply rail is independent of one another (VSS is partially shared).
Of the six power supply rails, those that are supplied in Power Cut Mode are the power
supply rail for external pins (DVCC-3A, DVCC-3B), the power supply rail for ADC (AVCC),
and the power supply rail for RTC and backup RAM (DVCC-1B). DVCC1A and DVCC1C
power supply rails are isolated internally with their signals cut off so that no flow-through
current will be generated in the LSI when the power is turned off.
• DVCC-3A, DVCC-3B
This 3V rail supplies power for holding external pins, controlling ON/OFF of external power
supplies, and interrupt input to release standby state.
• AVCC
This 3V rail supplies power in the touch panel interface for interrupt input to release
standby state.
• DVCC-1B
This 1.5V rail supplies power to the RTC, 16 Kbytes of RAM, and PMC.

AVCC

DVCC-1C

DVCC-1A

DVCC-1B

DVCC-3A,3B

TMP92CZ26A

INT
Port
Others
RAM 16KB
ADC
Control

HighOSC

RTC

CPU, Other logic
& RAM 272 KB

I/O
Reg
PMC

Low-OSC

AVSS

DVSS-1C

DVSS-COM

XT1

Figure 3.25.1 Power Supply System

92CZ26A-619

XT2

I/O

TMP92CZ26A
3.25.1 SFR
7
PMCCTL
(02F0H)

2

1

0

bit symbol

PCM_ON

6

5

4

3

−

WUTM1

WUTM0

Read/Write

R/W

W

R/W

R/W

0

0

0

0

Data

−

After
system
reset
After hot
reset

retained

Data

Data

retained

retained

Power

Always

Warm-up time

Cut Mode

write “0”

00: 29 (15.625 ms)

0: Disable

Always

10: 211 (62.5 ms)

1: Enable

read as “0”

11: 212 (125 ms)

Function

01: 210 (31.25 ms)

Note: After wake-up interruption, internal wake-up timer count setting register value:, and after about
77us, external PWE terminal change from low level to high level. Additionally after more about 92us, internal
reset signal will be released. We recommend to confirm actual performance on final set, because the time to
be stable all voltage level and power supply circuit are difference characteristics every final set.

The following operations are affected by the setting of the  bit.
PCM_ON = 1
PCM_ON = 0
No interrupt

External interrupt input

Interrupt

HOT_RESET signal assert

Startup depending on the AM1

−

Operation after reset

and AM0 pins

Startup from boot ROM regardless
Operation after hot reset

of the AM1 and AM0 pins and

−

jump to internal RAM area.
A change in the PWE pin level is
Warm-up counter

used as a trigger to start counting
the

low-frequency

clock

for

releasing HOT_RESET.

92CZ26A-620

Counter stopped

TMP92CZ26A

3.25.2 Detailed Description of Operation
This section explains the procedures for entering and exiting the Power Cut Mode.
• Entering the Power Cut Mode
When to enter the Power Cut Mode, the CPU needs to be operating in the internal RAM.
Low frequency clock (XT) must be enable condition.
It is also necessary to disable interrupt requests, stop DMA operations, WDT and AD
converter. Next, set the output pins to function as ports through the Pn, PnCR and PnDR
registers. At this time, PM7 should be set as PWE. Of the external interrupt pins, those to be
used for waking up from the Power Cut Mode should be set as input pins with interrupt
enabled.
About trigger of interruption, only rising edges are effective among selectable interruption
pins. When INT4 is used as TSI, the de-bounce circuit should be disabled.
Then, set the warm-up time for waking up from Power Cut Mode in PMCCTL.
Write the wake-up program at addresses from 46000H to 49FFFH in the internal RAM.
Should be written all initialize sequence including WDT in this program.
Finally, stop the PLL and set PMCCTL to “1” to enter the Power Cut Mode.
At this time, the RESET (HOT_RESET) signal is asserted for all the circuits excluding
external I/O and PMC.
Note: As soon as PMCCTL is set to “1”, the power management signal (PWE) changes from “1” to “0”
and external power supplies are turned off.

92CZ26A-621

TMP92CZ26A

1. Prepare to shift Power Cut Mode
(1) Set the warm-up time: PMCCTL
After wake-up interruption, internal wake-up timer count setting register
value:, and after about 77us, external PWE terminal change from low
level to high level. Additionally after more about 92us, internal reset signal will be
released. We recommend to confirm actual performance on final set, because the
time to be stable all voltage level and power supply circuit are difference
characteristics every final set.
Warm-up time can be selected among 15.625ms, 31.25ms, 62,5ms and 125ms.
(2) Prepare the initial program after Warm-up (46000H∼49FFFH)
After wake-up, jump to Boot ROM, and Boot ROM process distinguish only bit 7
of PMCCTL register. All initialize setting including WDT setting must be written
in fixed RAM area (46000H∼49FFFH).
(3) Control of low frequency clock (XT)
Power Management Circuit operates by low frequency clock. Low frequency
clock (XT) must be enable condition
2. Operation Sequence
(1) Execution area of program must shift to internal RAM area.
Before shifting Power Cut Mode, it must stop all the source which might be
disturbed to shift Power Cut Mode.
a. Disable Watch Dog Timer operation
b. Disable A/D converter operation
c.

Disable all DMA function
• Disable LCDC
• Auto refresh of SDRAM (We recommend to use self refresh mode)
• Disable DMAC

(2) Fix to port condition (Pn, PnCR, PnFC,PnDR)
Fix port condition and set external interrupt mode to wake-up trigger.
When INT4 is used as TSI, the de-bounce circuit should be disabled.
(3) Disable interruption (DI)
(4) Stop PLL operation
(5) Shift to Power Cut Mode (PMCCTL= “1”)

92CZ26A-622

TMP92CZ26A
• Exiting the Power Cut Mode
The Power Cut Mode can be exited by external or internal interruption. (It inhibits to exit
the Power Cut Mode by reset when DVCC1A is cut off. Reset must be asserted after supplying
power to DVCC1A and waiting for its voltage to fully stabilize.) The interrupts that can be
used to exit the Power Cut Mode are RTC interrupt, INT0 to INT7 (TSI interrupt) and
INTKEY interrupt.
Table 3.25.1 Wake-up triggers

Source

Symbol

RTC

INTRTC

Note

INT0

Only support "Rising Edge"

INT1

Only support "Rising Edge"

INT2

Only support "Rising Edge"

INT3
External

Only support "Rising Edge"
When TSI, need to disable de-bounce circuit

INT4

Key

Only support "Rising Edge"

INT5

Only support "Rising Edge"

INT6

Only support "Rising Edge"

INT7

Only support "Rising Edge"
KI0~KI8

INTKEY

Only support "Falling Edge"

When an interrupt request is accepted, the power management signals (PWE) changes from
“0” to “1” and power is supplied to each block that has been cut off. After the warm-up time set
in PMCCTL has elapsed, HOT_RESET is automatically released and the CPU
starts up from the internal boot ROM regardless of the external AM pin state. All external
ports retain the state before entering the Power Cut Mode except for the PnDR setting which
is released upon release of HOT_RESET.
* Output pin Hi-Z state
* Input pin input gate OFF

→
→

“1” or “0” output
Input pin input gate ON

The internal boot ROM first checks the PMCCTL  bit in the PMC. If this bit is
set to “1”, execution jumps to address 46000H in the internal RAM before making all initial
settings. The  bit in the PMC is cleared to “0” by software.
Note 1: The interrupt that released the Power Cut Mode, whichever it is, does not activate any interrupt operation. Nor
is it possible to identify which interrupt released the Power Cut Mode.
Note 2: Once the PMCCTL bit is set to “1”, it remains in this state. To re-enter the Power Cut Mode, it is
necessary to set this bit to “0” once and then to “1” again. At this time, a minimum of 31 us must be inserted
between setting  to “0” and “1”.
Note 3: Since the Power Cut Mode is exited using the boot ROM, some settings must be made by software. Be
careful about this point.

7

6

5

4

BROMCR Bit symbol
(016CH)

3

2

1

0

CSDIS

ROMLESS

VACE

Read/Write

R/W

After reset

1
NAND Flash
area CS
output
0: Enable
1: Disable

Function

92CZ26A-623

0
Boot ROM
0: Used
1: Not used

1
Vector
address
conversion
0: Disable
1: Enable

TMP92CZ26A
3.25.3 Detailed Description of Timing
1. A maximum of 3 clocks (92 μs)
are needed for entering PCM.

CPU state transition

Normal

2. A maximum of 2.5 clocks (77 μs)
are needed from interrupt request.

Power Cut Mode (PCM)

3. A minimum of 1 clock (31 μs) is
needed for entering PCM again.

Warm-up

3CLK

Normal

XT2
PMCCTL
PWE pin

INTRTC
INT0-7, INTKEY
Interrupt enabled period

Internal HOT_RESET
Drive register active period

Port state

5. The drive register setting is
1. This interrupt is
ignored.

4. These interrupts
are ignored.

released a maximum of 1 clocks
(31 μs) after the end of warm-up.

Internal HOT_RESET assert to dead circuit only. (DVCC1A &DVCC1C circuit)
1.

If it is set PMCCTL=“1”, shift the Power Cut Mode, however, it spends
3-clock times maximum (around 92μS) to shift from normal mode to Power Cut Mode.
And the wake-up triggers during this 3-clock times, are ignored.

2.

It spends 2.5-clock times maximum (around 77μS) from the trigger to wake-up to rise-up
the PWE terminal.

3.

After wake-up from Power Cut Mode, reset to "0" the PMCCTL bit by soft
ware. If you want to shift Power Cut Mode again, need to wait 1-clock time minimum
(around 31μS).

4.

The wake-up triggers during waking-up, are ignored.

5.

After Warm-up count, and spend 1-clock time (around 31μS), release the DRV setting of
every ports. After that, spends 2-clock time (around 62μS), release internal RESET
(Hot_Reset).

92CZ26A-624

TMP92CZ26A
Regulator

Regulator

1.5V

3.0V

SW en

Delay Circuit
SW en

SW en
0
S 1

TMP92CZ26A

AVCC

DVCC-1C DVCC-1A

DVCC-1B

DVCC-3A,3B
Power On

RTC
CPU

ADC

AVSS

Other Logic
High_OSC

DVSS-1C

RESET

LOW_OSC
RAM16kB
PMC

DVSS-COM

XT1

XT2

Power management

I/O

signal (PWE)

External interrupt
INT0-7
(INT4 also supports TSI.)
INTKEY

Main
Power

Figure3.25.2 Example External Circuitry for Using the PMC
Figure3.25.2 shows an example of external circuitry for using the PMC.
In normal mode, the power management pin (PWE) outputs “1” and power is supplied to all
the blocks in the TMP92CZ26A.
In the Power Cut Mode, the power management pin (PWE) outputs “0” and power is cut off for
the internal circuitry excluding the CPU, part of internal RAM, AD converter and RTC to
reduce leak current. In the Power Cut Mode, power is supplied to only the I/O (including the AD
pins), TSI circuit, 16 Kbytes of internal RAM, low-frequency oscillation circuit, RTC and PMC.

92CZ26A-625

TMP92CZ26A
3.25.4 Notes of Power sequence
•

Power ON/Power OFF Sequence (Initial Power ON/Complete Power OFF)

In the power ON sequence (initial power ON), power must be supplied to internal circuits
first and then to external circuits, as shown below. In the power OFF sequence (complete
power OFF), power must be turned off from external circuits so that internal circuits are
turned off last.
Power ON
(DVCC1A, DVCC1B, DVCC1C) → (DVCC3A, DVCC3B, AVCC)
Power OFF
(AVCC, DVCC3A, DVCC3B) → (DVCC1C, DVCC1B, DVCC1A)

Power on

Power Cut Mode (PMC)

Power off

DVCC1A
DVCC1B
DVCC1C

Power increases and
stabilizes within 100 ms.

1.5V rails should be

Power decreases and
stabilizes within 100 ms.

turned on first, followed

3.0V rails should be
turned off first, followed by
1.5V rails.

by 3.0V rails.

DVCC3A

DVCC3B

AVCC
Oscillator Wake-up time to be stable
＋20 system clock

RESET

PWE terminal

Note1: Although it is possible to turn on or off 1.5V and 3.0V rails simultaneously, external pins may temporarily
become unstable in this case. Therefore, if there is any possibility that this would affect external devices
connected with the TMP92CZ26A, external power supplies should be turned on or off while internal power
supplies are stable, as shown in the diagram above.
Note2: In the power ON sequence, 3V rails must not be turned on before 1.5V rails. In the power OFF sequence, 3V
rails must not be turned off after 1.5V rails.

92CZ26A-626

TMP92CZ26A
3.25.5 Setting Example

Condition: Wake-up trigger=INT4(TSI)
org

002000h

ld

(syscr0),40h

;

Enable low frequency clock

ldw

(wdmod),0b100h

;

Disable WDT

ldw

(admod0),0000h

;

ldw

(admod2),0000h

;

Disable AD converter

ldw
ld

(admod4),0000h
(lcdctl0),00h

;
;

Disable DMA operation

ld

(pmfc),80h

;

Set PM7 port to PWE function

ld

(p9fc),40h

;

ld

(inte34),50h

;

ld

(tsicr1),00h

;

Disable de-bounce circuit

ld

(pllcr0), 00h

;

Change CPU clock from PLL to fOSCH

ld

(pllcr1), 00h

;

Stop the PLL circuit

ld

(pmcctl),00h

;

Set Warm-up time

di
ld

Set INT4 and set level

;
(pmcctl),80h

;

Enable  = 1
Shift to Power Cut Mode

; After Wake-up
org

046000h

ld

(pmcctl),00h

;

Disable  = 0

92CZ26A-627

TMP92CZ26A

3.26 Multiply and Accumulate Calculation Unit (MAC)
The TMP92CZ26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit
arithmetic operations at high speed. The MAC has the following features:
・One-cycle execution for all MAC operations (excluding register access time)
・Three operation modes : 1) 64-bit + 32-bit × 32-bit
2) 64-bit − 32-bit × 32-bit
3) 32-bit × 32-bit − 64-bit
・Support for signed/unsigned operations
・Support for integer operations only

3.26.1 Registers
The MAC in the TMP92CZ26A has one control register and three data registers. These
registers are connected to the CPU via a 32-bit bus and can be accessed in one system clock
(fSYS).

3.26.1.1

Control Register
The control register is used to control the operation of the MAC.
MAC Control Register

MACCR
(1BFCH)

7

6

5

4

3

2

1

0

bit Symbol

MOVF

MOPST

MSTTG2

MSTTG1

MSTTG0

MSGMD

MOPMD1

MOPMD0

Read/Write

R/W

W

After reset

0

0

Prohibit
Read-modify
-write

Function

R/W
0

0

R/W
0

0

R/W
0

Overflow

Calculation

flag

soft start

0: No

0:Don’t care

overflow

1:Start

010: Write to MACMOR<7:0>

10: 32×32 − 64

1: Overflow

calculation

011: Write to MACMOR<39:32>

11: Reserved

occurred

Calculation start trigger

Sign mode

Calculation mode

000: Write to MACMA<7:0>

0: Unsigned

00: 64 + 32×32

001: Write to MACMB<7:0>

1: Signed

01: 64 − 32×32

1xx: Write of “1” to 

Note 1:  is write-only and it is read as “0”.
Note 2: Writing “1xx” to  and writing “1” to  can be executed in the same write cycle.
Note 3:  is fixed two system clocks (fSYS) after calculation is started.

92CZ26A-628

0

TMP92CZ26A
3.26.1.2

Data Registers
The data registers are arranged as shown below.
Data Registers

Bits<63:56>

Bits<55:48>

Bits<47:40>

Bits<39:32>

Bits<31:24>

Bits<23:16>

Bits<15:8>

Bits<7:0>

(1BE3H)

(1BE2H)

(1BE1H)

(1BE0H)

(1BE7H)

(1BE6H)

(1BE5H)

(1BE4H)

(1BEBH)

(1BEAH)

(1BE9H)

Multiplier A

MACMA

Register
Multiplier B

MACMB

Register
MAC

MACORH

Register

(1BEFH)

(1BEEH)

(1BEDH)

(1BECH)

MACORL
(1BE8H)

Note 1: After reset, all the registers are cleared to “0”.
Note 2: Read-modify-write instructions can be used on all the registers.
Note 3: All the registers can be accessed in long word, word, or byte units.
Note 4: When MACCR is set to “0”, “001”, “010” or “011” and the registers are written in word or byte units, the
<7:0> bits of each register must be written last.
Note 5: The MACORL register is fixed one system clock (fSYS) after calculation is started, and the MACORH register is fixed
two system clocks (fSYS) after calculation is started. Therefore, to read the MACOR register immediately after
calculation, be sure to read the MACORL register first.

92CZ26A-629

TMP92CZ26A

3.26.2 Description of Operation
(1)

Calculation mode
The MAC has the following three types of calculation mode. The calculation mode to be used
is specified in MACCR. MACCR is used to select unsigned or signed
mode. The operation of each calculation mode is explained below.

(a) 64 + 32 × 32 mode
In this mode, the contents of the MACMA register and the MACMB register are
multiplied and the result is added to the contents of the MACOR register. Then, the result
is stored back in the MACOR register.
63

0

31

+

MACOR

31

0

×

MACMA

63
MACMB

0
MACOR

(b) 64 − 32 × 32 mode
In this mode, the contents of the MACMA register and the MACMB register are
multiplied and the result is subtracted from the contents of the MACOR register. Then, the
result is stored back in the MACOR register.
63

0

31

−

MACOR

31

0
MACMA

×

63
MACMB

0
MACOR

(c) 32 × 32 − 64 mode
In this mode, the contents of the MACMA register and the MACMB register are
multiplied and the contents of the MACOR register are subtracted from the result. Then,
the result is stored back in the MACOR register.

31

31

0
MACMA

×

0
MACMB

63

−

0
MACOR

92CZ26A-630

63

0
MACOR

TMP92CZ26A
(d) Sign mode
Both multiply-accumulate and multiply-subtract operations can be executed in unsigned
or signed mode.
In signed mode, the MACMA, MACMB, and MACOR registers become signed registers,
and the most significant bit is treated as the sign bit and the data set in each register is
treated as a two’s complement value. Table 3.26.1 shows the range of values that can be
represented in each sign mode.
Table 3.26.1 Data Range in Unsigned/Signed Mode
MACMA, MACMB Registers

MACOR Register

Unsigned

0 ∼ 2 −1

0 ∼ 2 −1

Signed

−2 ∼ +2 -1

−2 ∼ +2 −1

32

31

64

31

63

63

Use signed mode when the values to be set in the MACMA and MACMB registers are
signed (two’s complement) data. Even in unsigned mode it is possible to set signed (two’s
complement) data in the MACOR register to perform additions and subtractions in signed
mode.

(2)

Calculation start trigger
As a trigger to start calculation, writing to the MACMA, MACMB or MACOR register or

soft start (MACCR=1) can be selected in MACCR.

(3)

Overflow flag
When an overflow occurs in the calculation result (see Table 3.26.2), MACCR is set
to “1”. Once an overflow occurs, MACCR is held at “1” regardless of subsequent
calculation results. Since the overflow flag is not automatically cleared by a read operation, it
is necessary to write “0” to clear this flag.

Table 3.26.2 Overflow Definitions
Calculation Result
Sign Mode

MACCR
(MACOR register value)
MACOR > 2 −1

1

0 ≤ MACOR ≤ 2 −1

0

MACOR < 0

1

64

Signed

64

MACOR > 2 −1

1

−2 ≤ MACOR ≤2 −1

0

63

Unsigned

63

63

MACOR < −2

63

92CZ26A-631

1

TMP92CZ26A
3.26.3 Operation Examples
(1) Unsigned multiply-accumulate operation
The following shows a setting example for calculating “33333333 + 11111111 × 22222222”:
ld

(MACCR), 0x08

ld

xde, 0x00000000

ld

xhl, 0x33333333

; Unsigned multiply-accumulate mode
Start calculation by write to MACMB.

ld

xix, 0x11111111

ld

xiy, 0x22222222

ld

(MACORL), xhl

; Write 33333333 to MACORL.

ld

(MACORH), xde

; Clear MACORH.

ld

(MACMA), xix

; Write 11111111 to MACMA.

ld

(MACMB), xiy

; Write 22222222 to MACMB.

ld

xhl, (MACORL)

; Read lower result 0x41FDB975.

Calculation start

bit

7, (MACCR)

jp

nz, ERROR

; Go to error routine, if there is over-flow error

; Check over-flow error

ld

xde, (MACORH)

; Read upper result 0x02468ACF.

(2) Signed multiply-subtract operation
The following shows a setting example for calculating “33333333 − 11111111 × −22222222”:
ld

(MACCR), 0x25

ld

xde, 0x00000000

ld

xhl, 0x33333333

; Signed multiply-subtract mode
Start calculation by write of “1” to .

ld

xix, 0x11111111

ld

xiy, 0xDDDDDDDE

ld

(MACORL), xhl

; Write 33333333 to MACORL.

ld

(MACORH), xde

; Clear MACORH.

ld

(MACMA), xix

; Write 11111111 to MACMA.

ld

(MACMB), xiy

; Write −22222222 to MACMB.

set

5, (MACCR)

ld

xhl, (MACORL)

; −22222222

;

Calculation start

; Read lower result 0x41FDB975.

bit

7, (MACCR)

jp

nz, ERROR

; Go to error routine, if there is over-flow error

; Check over-flow error

ld

xde, (MACORH)

; Read upper result 0x02468ACF.

(3) Unsigned multiply-accumulate operation (two multiply-accumulate operations)
The following shows a setting example for calculating “(33333333 + 11111111 × 22222222) +
(11111111 × 44444444)”:
ld

(MACCR), 0x08

ld

xde, 0x00000000

ld

xhl, 0x33333333

; Unsigned multiply-accumulate mode
Start calculation by write to MACMB.

ld

xix, 0x11111111

ld

xiy, 0x22222222

ld

xiz, 0x44444444

ld

(MACORL), xhl

; Write 33333333 to MACORL.

ld

(MACORH), xde

; Clear MACORH.

ld

(MACMA), xix

; Write 11111111 to MACMA.

ld

(MACMB), xiy

; Write 22222222 to MACMB.

Calculation start

ld

(MACMB), xiz

; Write 44444444 to MACMB.

Calculation start

ld

xhl, (MACORL)

; Read lower result 0x5F92C5F9.

bit

7, (MACCR)

jp

nz, ERROR

; Go to error routine, if there is over-flow error

; Check over-flow error

ld

xde, (MACORH)

; Read upper result 0x06D3A06D.

92CZ26A-632

TMP92CZ26A

3.27 Debug Mode
The TMP92CZ26A includes a debug support unit (DSU) for enabling on-board debugging.
The DSU has 9 debug pins for interfacing with an external emulator via a DSU connector to be
mounted on the target board and a DSU connecting cable. For details about debugging, please
refer to the instruction manual of the emulation pod to be used.
This section provides product-specific explanations related to debug mode.
(1)

Connection method

TMP92CZ26A

Target Board

DSU Connecting
Cable

EI_PODDATA
EI_SYNCLK
EI_PODREQ
EI_REFCLK
EI_TRGIN

DSU
Connector

Emulation
Pod

Controller

PC

EI_COMRESET
EO_MCUDATA
EO_MCUREQ
EO_TRGOUT

DBGE

Note: When connecting the TMP92CZ26A and an emulator in debug mode, place the DSU connector on the target
board as near (less than 5cm) to the TMP92CZ26A as possible. It is desirable that all the signals are same
length.
Recommend connector:

(2)

SAMTEC

FTSH-110-01-DV-EJ

How to enter debug mode
Debug mode can be entered by setting the DBGE pin to Low. To return to normal mode from
debug mode, be sure to set the DBGE pin to High and then reset the system using the RESET
pin. In details of debus mode, refer the manual of emulation POD.

92CZ26A-633

TMP92CZ26A
(3)

Limitations in debug mode
Debug mode has the following limitations:
1) Target reset
While debugging is being performed, the system reset ( RESET pin) of the target
(microcontroller) must not be used to reset the controller and microcontroller. Instead,
reset should be performed from the controller. (For details, please refer to the instruction
manual of the emulation pod to be used.)

* If reset from the microcontroller by the RESET pin may clash the register information
and internal RAM data in the CPU, including not only programs but also breakpoint
and trace information.

92CZ26A-634

TMP92CZ26A

2) Pins
In debug mode, a total of 9 pins (PZ0 to PZ7 in Port Z and PU7 in Port U) are used to
connect the TMP92CZ26A with an emulator via a DSU probe for communicating with the
controller. For this reason, these 9 pins cannot be debugged. Therefore, if the port control
register of each pin is changed in debug mode, the register contents are changed but the
function of each pin remains the same.

Port Z Register
PZ
(0068H)

bit Symbol

7

6

5

4

3

2

1

0

PZ7

PZ6

PZ5

PZ4

PZ3

PZ2

PZ1

PZ0

Read/Write

R/W

After reset

External pin data (Output latch is reset to “0”.)

Port Z Control Register
PZCR
(006AH)

bit Symbol

7

6

5

4

PZ7C

PZ6C

PZ5C

PZ4C

Read/Write
After reset

3

2

1

0

PZ3C

PZ2C

PZ1C

PZ0C

0

0

0

0

W
0

0

0

0

Function

0: Input

1: Output

Port Z Function Register
PZFC
(006BH)

bit Symbol

7

6

5

4

3

2

1

0

PZ7F

PZ6F

PZ5F

PZ4F

PZ3F

PZ2F

PZ1F

PZ0F

0

0

0

0

0

0

0

0

Read/Write
After reset

W

Function

0: Port

Port Z Drive Register
PZDR
(009AH)

bit Symbol

7

6

5

4

3

2

1

0

PZ7D

PZ6D

PZ5D

PZ4D

PZ3D

PZ2D

PZ1D

PZ0D

1

1

1

1

1

1

1

1

Read/Write
After reset

R/W

Function

Input/output buffer drive register for standby mode

Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication function is
given a higher priority).

92CZ26A-635

TMP92CZ26A

Port U Register
PU
(00A4H)

PUCR
(00A6H)

Bit Symbol

7

6

5

4

PU7

PU6

PU5

PU4

3

2

1

0

PU3

PU2

PU1

PU0

Read/Write

R/W

After reset

External pin data (Output latch is reset to “0”.)

Bit Symbol

7

6

PU7C

PU6C

Port U Control Register
5
4
3
PU5C

PU4C

PU3C

Read/Write
After reset

2

1

0

PU2C

PU1C

PU0C

0

0

0

W
0

0

0

0

Function

0

0: Input 1: Output

Port U Function Register

PUFC
(00A7H)

Bit Symbol

7

6

5

4

3

2

1

0

PU7F

PU6F

PU5F

PU4F

PU3F

PU2F

PU1F

PU0F

0

0

0

0

0

0

0

Read/Write
After reset

W

Function

0

0: Port 1: Data bus for LCDC (LD23 to LD16)
Note: When LD23 to LD16 are used, set  to “1”.

Port U Drive Register

PUDR
(009CH)

Bit Symbol

7

6

5

4

3

2

1

0

PU7D

PU6D

PU5D

PU4D

PU3D

PU2D

PU1D

PU0D

1

1

1

Read/Write
After reset

R/W
1

Function

1

1

1

1

Input/output buffer drive register for standby mode

Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication function is
given a higher priority).

92CZ26A-636

TMP92CZ26A

3) Boot function
In this LSI, we support boot function, however, this boot function is not available in
debug mode. (It is inhibit to set DBGE =“0”, AM0=“1” and AM1=“1” at the same time.)
4) PMC function
In debug mode, the PMC function for cutting off the power supply to internal circuitry
and reducing standby current is not also available.

BROMCR Register Specifications in Debug Mode
7

6

5

4

3

BROMCR Bit symbol
(016CH)
Read/Write

2

1

0

CSDIS

ROMLESS

VACE

R/W

After reset

1

Function

NAND
Flash area
CS output

7
PMCCTL
(02F0H)

4

3

1: Not used

0: Enable

0: Disable

1: Disable

1: Enable

2

1

0

PCM_ON

−

WUTM1

WUTM0

Read/Write

R/W

W

R/W

R/W

0

0

0

0

Data
retained

−

−

−

Power Cut
Mode

Always write
“0”.

After hot
reset

5

0: Used

Vector
address
conversion

bit symbol
After
system
reset

6

1/0

1*

Boot ROM

Warm-up time
9

00: 2 (15.625 ms)
10

01: 2 (31.25 ms)

Function
Always read
ad “0”.

0: Disable
1: Enable

11

10: 2 (62.5 ms)
12

11: 2 (125 ms)

Note: Even if the  bit is set to “1”, the Power Cut Mode cannot be entered (the external PWE pin is not set to “0”).

92CZ26A-637

TMP92CZ26A

5) Data bus occupancy
The TMP92CZ26A includes three controllers (LCD controller, SDRAM controller and
DMAC) that function as bus masters apart from the CPU. Therefore, it is necessary to
estimate the bus occupancy time of each bus master and control each function accordingly
to ensure proper operation of each function. (For details, please refer to the chapter on the
DMA controller.)
In debug mode, in addition to the operations of these bus masters, a steal program that
runs in the background must also be taken into account in programming. When the
program stops at a breakpoint (including step execution), the CPU operation is halted but
the LCD controller, SDRAM controller and DMA controller remain active. At this time, the
steal program also runs in the background. Once the steal program obtains the bus, it
occupies the bus for 80 times of debug transmission clock (LH_SYNCLK) maximum.
Therefore, in some cases, other DMA operations (LCD display, DMAC data transfer,
SDRAM refresh) may not be performed at desired timing.

Setup time 1

LHSYNC
LCP0
LD-bus
LCD DMA operation 1

HDMA operation
(Worst case)

2
Setup time 2

1

LCD DMA operation 2

Figure 3.27.1 Example of Data Bus Occupancy Timing in Non-Debug Mode

Figure 3.27.1 shows an example of data bus occupancy timing in non-debug mode,
depicting the LHSYNC signal, LCP0 signal, and LD-bus signal for transferring data from
the LCD controller to the LCD driver, and the LCD DMA operation timing for reading
data from the display RAM.
If HDMA is asserted immediately before the DMA operation for the LCD (LCD DMA
operation 1) is started, this operation must wait until HDMA is finished before it can be
performed (LCD DMA operation 2).
Taking the above into account, it is necessary to ensure that each LCD DMA operation is
finished before the next LCD driver output is started.

92CZ26A-638

TMP92CZ26A

Setup time 1

LHSYNC
LCP0
LD-bus
LCD DMA operation 1

3
Setup time 2

HDMA operation 1
(Worst case)

2

Steal operation
(Worst case)

1

LCD DMA operation 2

HDMA operation 2

Figure 3.27.2 Example of Data Bus Occupancy Timing in Debug Mode

Figure 3.27.2 shows an example of data bus occupancy timing in debug mode. If the steal
program issues a wait request immediately before the DMA operation for the LCD (LCD
DMA operation 1) and HDMA (HDMA operation 1) are asserted, these operations must
wait until the steal program is finished before they can be performed. (LCD DMA is given a
higher priority than HDMA in bus arbitration. This means that bus requests is
sued for LCD DMA and HDMA while the steal program is running are processed in the
order of LCD and HDMA (LCD DMA operation 2 → HDMA operation 2) regardless of the
order in which they are issued. )
Taking the above into account, it is necessary to ensure that each LCD DMA or HDMA
operation is finished before the next LCD driver output is started.
In other words, to avoid abnormal operation in debug mode, the maximum duration of
HDMA operation time must be set so that it does not interfere with LCD DMA operation.
Alternatively, the LHSYNC period should be adjusted to accommodate a wait request by
the steal program (80 times of transmission for debug clock: LH_SYNCLK), although this
slightly reduces the LCD display quality.

92CZ26A-639

TMP92CZ26A

4.

Electrical Characteristics (Tentative)

4.1 Maximum Ratings
Symbol

Contents

Rating

DVCC3A

-0.3 to 3.9

DVCC3B
DVCC1A
DVCC1B

Unit

Power Supply Voltage

V

-0.3 to 3.0

DVCC1C
AVCC

-0.3 to 3.9

VIN

Input Voltage

-0.3 ∼DVCC3A/3B+0.3 (Note1)

V

-0.3 to AVCC + 0.3 (Note2)

IOL

Output Current (1pin)

15

mA

IOH

Output Current (1pin)

-15

mA

ΣIOL

Output Current (total)

80

mA

ΣIOH

Output Current (total)

-50

mA

Power Dissipation (Ta = 85°C)

600

mW

Soldering Temperature (10s)

260

°C

-65 to 150

°C

-0 to 70

°C

-0 to 50

°C

PD
TSOLDER
TSTG

Storage Temperature

TOPR

Operation Temperature

TOPR

Operation Temperature
(80MHz)

Note1: If setting it, don’t exceed the Maximum Ratings of DVCC3A (PV port and PW port are DVCC3B).
Note2: In PG0 to PG5, P96,P97,VREFH,VREFL maximum ratings for AVCC is applied.
Note3: The maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any
one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its
performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products that include this device, ensure that no maximum rating value will ever be exceeded.

Point of note about solderability of lead free products (attach “G” to package name)
Test
parameter
Solderability

Test condition

Note

Solder bath temperature = 230°C, Dipping time = 5 seconds

Pass:

The number of times = one, Use of R-type flux

solderability rate until forming

Solder bath temperature =245°C, Dipping time = 5 seconds

≥ 95%

The number of times = one, Use of R-type flux (use of lead free)

92CZ26A-640

TMP92CZ26A

4.2 DC Electrical Characteristics
Symbol

Parameter

Min

Typ.

Max

Unit

3.0

3.3

3.6

V

Condition

General I/O
DVCC
3A

Power Supply Voltage
(DVCC=AVCC)
(DVSSCOM=AVSS=0V)

DVCC
1A
DVCC
1B
DVCC
1C

X1=6 to
10MHz

Internal Power A

CPU CLK

XT1=30

(60MHz)

to 34KHz

CPU CLK
Internal Power B

1.4

1.5

1.6

−

0.3×DVCC3A

–

0.3×DVCC3B

V

(80MHz)

High CLK oscillator and PLL Power

Input Low Voltage for
D0 to D7
P10 to P17 (D8 to 15), P60 to P67
P71 to P76, P90

VIL0

PC4 to PC7, PF0 to PF5

3.0≦DVCC3A≦3.6

PG0 to PG5, PJ5 to PJ6
PN0 to PN7, PP1 to PP2
PR0 to PR3, PT0 to PT7
PU0 to PU7, PX5, PX7

VIL1

Input Low Voltage for
PV0 to PV2, PV6 to PV7, PW0 to PW7

-0.3

V

3.0≦DVCC3B≦3.6

Input Low Voltage for
VIL2

P91 to P92, P96 to P97, PA0 to PA7
PC0 to PC3, PP3 to PP5, PZ0 to PZ7,

–

0.25×
DVCC3A

3.0≦DVCC3A≦3.6

RESET

VIL3
VIL4
VIL5

Input Low Voltage for
AM0 to AM1, DBGE

–

0.1×DVCC3A

3.0≦DVCC3A≦3.6

Input Low Voltage for

–

0.1×DVCC1C

1.4≦DVCC1C≦1.6

–

0.15 ×DVCC3A

3.0≦DVCC3A≦3.6

X1
Input Low Voltage for
XT1

Note: Above power supply range is premised that all power supply of same system is equal.

(DVCC1A = DVCC1B = DVCC1C or DVCC3A = DVCC3B=AVCC)

92CZ26A-641

TMP92CZ26A

Symbol

Parameter

Min

Typ.

Max

Unit

Condition

–

DVCC3A + 0.3

–

DVCC3B + 0.3

–

DVCC3A + 0.3

3.0≦DVCC3A≦3.6

–

DVCC3A + 0.3

3.0≦DVCC3A≦3.6

0.9×DVCC1C

–

DVCC1C + 0.3

1.4≦DVCC1C≦1.6

0.85×

–

DVCC3A + 0.3

3.0≦DVCC3A≦3.6

Input High Voltage for
D0 to D7
P10 to P17 (D8 to 15), P60 to P67
P71 to P76, P90

VIH0

PC4 to PC7, PF0 to PF5
PG0 to PG5, PJ5 to PJ6

0.7 ×
DVCC3A

3.0≦DVCC3A≦3.6

PN0 to PN7, PP1 to PP2
PR0 to PR3, PT0 to PT7
PU0 to PU7, PX5, PX7

VIH1

Input High Voltage for
PV0 to PV2, PV6 to PV7, PW0 to PW7

0.7 ×
DVCC3B

V

3.0≦DVCC3B≦3.6

Input High Voltage for
VIH2

P91 to P92, P96 to P97, PA0 to PA7
PC0 to PC3, PP3 to PP5, PZ0 to PZ7,

0.75×
DVCC3A

RESET

VIH3
VIH4
VIH5

Input High Voltage for
AM0 to AM1 , DBGE
Input High Voltage for
X1
Input High Voltage for
XT1

0.9×
DVCC3A

DVCC3A

92CZ26A-642

TMP92CZ26A

Symbol

VOL1

Parameter
Output Low Voltage1
P90 to P92,
PC0 to PC3, PC7
PF0 to PF5, PK1 to PK7
PM1 to PM2, PM7
PN0 to PN7, PP1 to PP7
PV0 to PV7, PW0 to PW7,
PX5, PX7

VOL2

Output Low Voltage2
Except VOL1 output pin

VOH1

Output High Voltage1
P90 to P92,
PC0 to PC3, PC7
PF0 to PF7, PK1 to PK7
PM1 to PM2, PM7
PN0 to PN7, PP1 to PP7
PV0 to PV7, PW0 to PW7
PX5, PX7

VOH2
VOL(T)
VOH(T)
ILI
ILO
RRST
CIO

VTH

Output High Voltage2
Except VOL1 output pin
Output Low Voltage for
P96(PX), P97(PY)-pins
Output High Voltage for
P96(PX), P97(PY)-pins
Input Leakage Current
Output Leakage Current
Pull Up/Down Resistor for
RESET , PA0 to PA7, P96
Pin Capacitance
Schmitt Width for
P91 to P92, P96 to P97,

Min

Typ.

Max

–

–

0.4

Unit

Condition

IOL = 0.5mA, 3.0≦DVCC3A

IOL = 2mA, 3.0≦DVCC3A

V
IOH = -0.5mA, 3.0≦DVCC3A
2.4

–

–

IOH = -2mA, 3.0≦DVCC3A
–

–

0.2

IOL(T)=6.6mA

VCC-0.2

–

–

IOH(T)=-6.6mA

–
–

0.02
0.05

±5
±10

μA
μA

30

50

70

KΩ

–

–

10

pF

fc=1MHz

0.6

0.8

1.0

V

3.0≦DVCC3A≦3.6

3.0≦DVCC3A≦3.6
0.0 ≦ Vin ≦ DVCC3A
0.2 ≦ Vin ≦ DVCC3A-0.2V

PA0 to PA7, PC0 to PC3, PP3 to PP5,
PZ0 to PZ7, RESET

Note1 : Typical values are value that when Ta = 25°C and Vcc = 3.3 V unless otherwise noted.
Note2 : This data shows exept "debug mode"

92CZ26A-643

TMP92CZ26A

Symbol

Parameter
NORMAL (note2)

Min

Typ.

Max

−

15
45
0.5
28
12
34
0.4
21

30
60
1
45
23
45
0.8
34

mA

12

45

μA

200

3200

PLL_OFF
fSYS =10MHz

35

Ta ≦ 70℃

30

Ta ≦ 50℃

50

Ta ≦ 70℃

−

IDLE2
NORMAL (note2)

−
−

IDLE2

−

IDLE1

Unit

Condition
DVCC3A,3B = 3.6V
PLL_ON
fSYS=80MHz

Power Cut Mode
(WITH PMC function )

DVCC3A,3B = 3.6V
PLL_ON
fSYS=60MHz

−

Ta ≦ 50℃

35
μA
35

Ta ≦ 70℃

30

Ta ≦ 50℃

800

Ta ≦ 70℃

600

Ta ≦ 50℃

6
−

DVCC1A,1B,1C = 1.6V
DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V

2

STOP

DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V

6
ICC

DVCC1A,1B,1C = 1.6V

200

DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V

DVCC3A=3.6V
DVCC3B=3.6V
AVCC=3.6V
DVCC1A=0V
DVCC1B=1.6V
DVCC1C=0V
XT=32KHz
X=OFF
DVCC3A=3.6V
DVCC3B=3.6V
AVCC3.6V
DVCC1A=1.6V
DVCC1B=1.6V
DVCC1C=1.6V
XT=OFF
X=OFF

Note1 : Typical values are value that when Ta = 25°C and Vcc = 3.3 V unless otherwise noted.
Note2 : ICC measurement conditions (NORMAL, SLOW):
All functions are operational; output pins except bus pin are open, and input pins are fixed. Bus pin CL=50pF
(Access toexternal memory at 8-waitsetting )
Note3: This data shows exept "debug mode"

92CZ26A-644

TMP92CZ26A

4.3

AC Characteristics

The Following all AC regulation is the measurement result in following condition, if unless otherwise noted.
AC measuring condition
Clock of top column in above table shows system clock frequency, and “T” shows system
clock period [ns].

•

•

Output level: High = 0.7×3AVCC, Low = 0.3×3AVCC

•

Input level: High = 0.9×3AVCC, Low = 0.1×3AVCC

Note: In table, “Variable” shows the regulation at DVCC3A=3.0V~3.6V, DVCC1A=DVCC1B=DVCC1C=1.4~1.6V.

4.3.1

Basic Bus Cycle
Read cycle

No.

Parameter

Variable

Symbol

1 OSC period (X1/X2)

tOSC

2 System clock period ( = T)

80 MHz 60 MHz

Min

Max

100

166.6

−

−

266.6

12.5

16.6

tCYC

12.5

3 SDCLK low width

tCL

0.5T − 3

3.25

5.3

4 SDCLK high width

tCH

0.5T − 3

3.25

5.3

7

15.3

5-1
5-2

A0 ~ A23 valid → D0 ~ D15 input at 0
waits
A0 ~ A23 valid
→ D0 ~ D15 input at 4 waits/6 waits

6-1 RD falling →
6-2

D0 ~ D15 input at 0 waits

RD falling

→ D0 ~ D15 input at 4 waits/6waits

tAD

2.0T − 18.0

tAD6

6.0T − 18.0

−

82

tAD7

8.0T - 18.0

82

−

tRD

1.5T − 18.0

−

7

tRD

1.5T − 18.0

0.75

−

tRD6

5.5T − 18.0

−

73.6

tRD7

5.5T − 18.0

50.75

−

7-1 RD low width at 0 waits

tRR

1.5T − 10

8.75

14.9

7-2 RD low width at 4 waits

tRR6

5.5T − 10

58.75

81.3

8 A0 ~ A23 valid → RD falling

tAR

0.5T − 5

1.25

3.3

9 RD falling → SDCLK rising

tRK

0.5T − 5

1.25

3.3

10 A0 ~ A23 valid → D0 ~ D15 hold

tHA

0

0

0

11 RD rising → D0 ~ D15 hold

tHR

0

0

0

tTK

3

3

5

tKT

2

12

WAIT setup time

13

WAIT hold time

14 Data byte control access time

tSBA

15 RD high width

tRRH

1.5T − 18.0
0.5T − 5

2

3

0.75

7

1.25

3.3

Unit

AC measuring condition
• Data_bus, Address_bus, various function control signal capacitance CL = 50 pF
Note: The operation guarantee temprature: 80MHz: Ta=0∼50°C, less than 60MHz: Ta=0∼70°C

92CZ26A-645

ns

TMP92CZ26A

Write cycle
No.

Parameter

Symbol

Variable
Min

16-1

D0 ~ D15 valid
→ WR xx rising at 0 waits

D0 ~ D15 valid
16-2
→ WR xx rising at 2 waits/4 waits
17-1 WR xx low width at 0 waits
17-2

WR xx low width at 2 waits/4 waits

18 A0 ~ A23 valid →

WR falling

80MHz 60MHz

1.0T − 10.0

−

tDW

1.0T − 6.0

6.5

−

tDW4

3.0T − 10.0

−

39.8

tDW6

5.0T − 6.0

56.5

−

tWW

1.0T − 7.0

−

9.6

tWW

1.0T − 4.0

8.5

−

tDW

6.6

tWW4

3.0T − 7.0

−

42.8

tWW6

5.0T − 4.0

58.5

−

tAW

0.5T − 5.0

1.25

3.3

tWK

0.5T − 5.0

1.25

3.3
3.3

19

WR xx falling → SDCLK rising

20

WR xx rising

→ A0 ~ A23 hold

tWA

0.5T − 5.0

1.25

WR xx rising

→ D0 ~ D15 hold

tWD

0.5T − 5.0

1.25

3.3

RD rising

→ D0 ~ D15 output

tRDO

0.5T − 2.0

−

6.3

tRDO

0.5T − 1.0

5.25

−
22.9

21
22-1

22-2 RD rising

→ D0 ~ D15 output

23 Write width for SRAM
24

tRDO

1.5T − 2.0

−

tRDO

2.5T − 1.0

30.25

−

tSWP

1.0T − 7.0

−

9.6

tSWP

1.0T − 4.0

8.5

−

Data byte control ~ end of write

tSBW

1.0T − 7.0

−

9.6

for SRAM

tSBW

1.0T − 4.0

8.5

−

25 Address setup time for SRAM

tSAS

0.5T − 5.0

1.25

3.3

26 Write recovery time for SRAM

tSWR

0.5T − 5.0

1.25

3.3

tSDS

1.0T − 10.0

−

6.6

tSDS

1.0T − 6.0

6.5

−

tSDH

0.5T − 5.0

1.25

3.3

27 Data setup time for SRAM
28 Data hold time for SRAM

AC measuring condition
Note: The operation guarantee Temperature: 80MHz: Ta=0∼50°C, less than 60MHz: Ta=0∼70°C

92CZ26A-646

Unit

Max

ns

TMP92CZ26A

(1) Read cycle (0 waits)
tOSC
X1
tCYC
tCL

tCH

SDCLK

tTK

tKT

WAIT

A0~A23

tAD
CSn

tHA
R/ W
tAR

tRK

tHR

RD

tRRH

tRR
tRD

D0~D15

Data input

tSBA
SRxxB

SRWR

Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing. The CSn , R/ W , RD , WRxx , SRxxB , SRWR
pins timing can be adjusted by memory controller timing adjust function.

92CZ26A-647

TMP92CZ26A

(2) Write cycle (0 waits)
tOSC
X1
tCYC
tCL

tCH

SDCLK

tTK

tKT

WAIT

A0~A23

CSn

R/ W
tAW

tWA

tWK

WRxx

tWW
tDW
D0~D15

tSWR
tWD

Data output

tRDO
RD

tSDH
tSBW
SRxxB

tSDS
tSAS
tSWP
SRWR

Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing. The CSn , R/ W , RD , WRxx , SRxxB , SRWR

pins timing can be adjusted by memory controller timing adjust function.

92CZ26A-648

TMP92CZ26A

(3) Read cycle (1 wait)
SDCLK

WAIT

A0~A23
tAD3
CSn

R/ W

RD

tRR3
tRD3
D0~D15

Data input

(4) Write cycle (1 wait)

SDCLK

WAIT

A0~A23

CSn

R/ W

WRxx

tWW3
tDW3
D0~D15

Data output
tRDO

RD

92CZ26A-649

TMP92CZ26A
4.3.2

Page ROM Read Cycle
(1) 3-2-2-2 mode
Variable
Parameter

Symbol

80 MHz 60 MHz
Min

1 System clock period ( = T)
2 A0, A1

tCYC

→ D0 ~ D15 input

12.5

266.6

12.5

tAD2

2.0T − 18

7

15.2

19.5

31.8

13

24

3 A2 ~ A23

→ D0 ~ D15 input

tAD3

3.0T − 18

4 RD falling

→ D0 ~ D15 input

tRD3

2.5T − 18

16.6

5 A0 ~ A23 Invalid → D0 ~ D15 hold

tHA

0

0

0

→ D0 ~ D15 hold

tHR

0

0

0

6 RD rising

Unit

Max

ns

AC measuring condition
Note: The (a), (b) and (c) of “Symbol” in above table depend on the falling timing of RD pin. The falling timing of
RD pin is set by MEMCR0 in memory controller. If MEMCR0 is set to “00”, it

correspond with (a) in above table, and “01” is (b), “10” is (c).

SDCLK
tCYC
A2~A23

+0

A0~A1

+1

+2

+3

CS2

tAD3

tAD2

tAD2

tAD2

tHA

tHA

tHA

tHA

RD

tRD3
D0~D15

Data
input

Data
input

92CZ26A-650

Data
input

tHR
Data
input

TMP92CZ26A
4.3.3

SDRAM controller AC Characteristics
Variable
Parameter

Symbol

80 MHz 60 MHz
Min

1
2

Ref/Active to ref/active
command period

=000

Active to precharge
command period

=000

tRC

=110

Active to read/write
command delay time

T

12.5

16.6

7T

87.5

116.2

2T

tRAS

=110

25.0

33.2

7T

12210

87.5

116.2
16.6

T

12.5

=1

2T

25.0

33.2

Precharge to active
4
command period

=0

T

12.5

16.6

2T

25.0

33.2

Active to active
command period

=000

3T

37.5

49.8

7T

87.5

116.2
16.6

3

5

=0

tRCD
tRP

=1

tRRD

=110
=0

6 Write recovery time

T

12.5

2T

25.0

33.2

T

12.5

16.6

0.5T − 5

−

3.3

0.5T − 3

3.25

−

0.5T − 5

−

3.3

tWR

=1

7 CLK cycle time

tCK

8 CLK high level width

tCH
tCL

9 CLK low level width
10-1a Access time from CLK(CL* =2)
10-1b =0(Read data shift OFF)
10-2a Access time from CLK(CL* =2)
10-2b =1(Read data shift ON)

12 Data-in set-up time

0.5T − 3

tAC
tAC

3.25

−

T − 16

−

0.6

T − 16

- 3.5

−

T − 6.5

−

10.1

T − 6.5

6

−

tOH

0

0

0

1Word/Single

tDS

0.5T − 4

2.25

3.3

Burst

tDS

0.5T − 4

2.25

3.3

1Word/Single

tDH

2.5

6.6
2.3

11 Output data hold time

T −

10

tDH

0.5T − 6

−

tDH

0.5T − 4

2.25

−

14 Address set-up time

tAS

0.5T − 4

2.25

4.3

15 Address hold time

tAH

2.3

13 Data-in hold time

Burst

16 CKE set-up time
17 Command set-up time

tCKS
tCMS

18 Command hold time

tCMH

19 Mode register set cycle time

tRSC

Unit

Max

0.5T − 6

−

0.5T − 4

2.25

−

0.5T − 5

−

3.3

0.5T − 3

3.25

−

0.5T − 5

−

3.3

0.5T − 3

3.25

−

0.5T − 6

−

2.3

0.5T − 4

2.25

−

T

12.5

16.6

*CL: CAS latency
AC measuring condition
SDCLK pin CL = 30 pF, Other pins CL = 50 pF

92CZ26A-651

ns

TMP92CZ26A

(1) SDRAM read timing (1Word length read mode, =1)
tCK
SDCLK
tCH

tRCD

tCL

tRAS

tRP

SDxxDQM
tCMS

tCMS tCMH

SDCS

tCMH
SDRAS

tRRD
SDCAS

SDWE

tAS
A0~A9

tAH

Row

Column
tAS

A10

Row

A11~A15

Row

tAH

tAC
D0~D15

tOH
Data input

92CZ26A-652

TMP92CZ26A

(2) SDRAM write timing (Single write mode, =1)
tCK
SDCLK
tCH

tRCD
tCMS

tCL

tWR

SDxxDQM
tCMS

tRRD

SDCS

tCMH
SDRAS

tCMH
SDCAS

tRAS
SDWE

tAS
A0~A9

tAH

Row

Column
tAS

A10

Row

A11~A15

Row

tAH

tDS
D0~D15

tDH
Data output

92CZ26A-653

tRP

TMP92CZ26A

(3) SDRAM burst read timing (Start burst cycle)
tCK
SDCLK
tCMS
SDxxDQM
tMRD

tRCD

SDCS

tCMS

tCMH

SDRAS

tCMS tCMH
SDCAS

tCMH
SDWE

tAH

tAS
A0~A9

027

tAS

Row

Column

Row

A10

A11~A15

tAH

tAS

0

Row
tAC

D0~D15

tAC
Data input
tOH

92CZ26A-654

tAC
Data input
tOH

Data
input

TMP92CZ26A

(4) SDRAM burst read timing (End burst timing)
tCK
SDCLK
tCMH

tCMS

tRP

SDxxDQM
tCMS

tCMS

tCMH

tCMH

SDCS

SDRAS

SDCAS

SDWE

A0~A9

Column
tAS

A10

A11~A15

Row
tAC

D0~D15

Data input
tOH

Data input
tOH

92CZ26A-655

TMP92CZ26A

(5) SDRAM initializes timing
tCK
SDCLK
tRC
SDxxDQM
tCMS
SDCS

SDRAS

tCMS

tCMH

tCMS

tCMH

tCMH

tCMS

SDCAS

tCMH
SDWE

A0~A9

220
tAS

tAH

A10

A11~A15

0

92CZ26A-656

TMP92CZ26A

(6) SDRAM refreshes timing
tCK
SDCLK
tRC
SDxxDQM
tCMS

tCMH

SDCS

SDRAS

SDCAS

SDWE

(7) SDRAM self refresh timing
tCK
SDCLK
tCKS

tCKS
SDCKE

SDxxDQM
tCMS

tCMH

SDCS

SDRAS

SDCAS

SDWE

92CZ26A-657

tRC

TMP92CZ26A
4.3.4

NAND Flash Controller AC Characteristics
80 MHz 60 MHz

Variable
No. Symbol

Parameter
Min

Max

(n=3)

(n=3)

(m=3)

(m=3)

1

tNC

Access cycle

(2 + n + m ) T

100

132

2

tRP

NDRE low level width

(1.5+ n) T − 12

45

63

3

tREA

NDRE data access time

41

60

4

tOH

Read data hold time

0

0

0

5

tWP

NDWE low level width

(1.0 + n) T − 20

30

47

6

tDS

Write data setup time

(1.0 + n) T − 20

30

47

7

tDH

Write data hold time

(0.5 + m) T − 2

42

56

(1.5 + n) T − 15

Unit

ns

AC measuring condition

Note1: The “n” in “Variable” means wait-number which is set to NDFMCR0, and “m” means number which is
set to NDFMCR0.
Example: If NDFMCR0 is set to “01”, n=1, tRP = (1.5 + n) T − 12 = 2.5T − 12
Note2: In above variable, the setting that result is minus can not use.
tCYC
SPLW1:0="01"

SPHW1:0="01"

SDCLK

A0~A23
tRP
NDRE

Read
cycle

NDWE

tREA
tOH
Data input

D0~D7
D0~D15

NDRE

tWP
Write
cycle

NDWE

tDS
D0~D7
D0~D15

Data output

92CZ26A-658

tDH

TMP92CZ26A
4.3.5

Serial channel timing
(1) SCLK input mode (I/O interface mode)
Parameter

Variable

Symbol

80 MHz 60 MHz Unit

Min

Max

SCLK cycle

tSCY

16T

200

266

Output data → SCLK rising/ falling

tOSS

tSCY/2 − 4T − 30

20

36.4

SCLK rising/ falling → Output data hold

tOHS

tSCY/2 + 2T -20

105

146

SCLK rising/ falling → Input data hold

tHSR

2T + 10

35

43

SCLK rising/ falling → Input data valid

tSRD

180

246

Input data valid → SCLK rising/ falling

tRDS

20

20

tSCY − 20
20

ns

(2) SCLK output mode (I/O interface mode)
Parameter
SCLK cycle (Programmable)

Variable

Symbol
tSCY

80 MHz 60 MHz Unit

Min

Max

16T

8192T

200

266

Output data → SCLK rising/ falling

tOSS

tSCY/2 − 40

60

93

SCLK rising/ falling → Output data hold

tOHS

tSCY/2 − 40

60

93

SCLK rising/ falling → Input data hold

tHSR

0

0

0

137.5

199

62.5

66

SCLK rising/ falling → Input data valid

tSRD

Input data valid → SCLK rising/ falling

tRDS

tSCY − 1T − 50
1T + 50

ns

tSCY
SCLK
Output mode/
Input mode
SCLK
(Input mode)
tOSS
Output data
TXD

tOHS
0

1
tSRD

Input data
RXD

2

3

tRDS
tHSR

0

1

2

3

Valid

Valid

Valid

Valid

92CZ26A-659

TMP92CZ26A

4.3.6

Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0)
Parameter

Variable

Symbol
Min

80 MHz 60 MHz Unit
Max

Clock cycle

tVCK

8T+100

200

234

Low level pulse width

tVCKL

4T + 40

90

107

High level pulse width

tVCKH

4T + 40

90

107

4.3.7

Interrupt Operation
Parameter

Variable

Symbol
Min

80 MHz 60 MHz Unit
Max

INT0~INT7 low width

tINTAL

2T + 40

65

74

INT0~INT7 high width

tINTAH

2T + 40

65

74

4.3.8

USB Timing (Full-speed)
VCC = 3.3 ± 0.3 V/fUSB = 48 MHz/Ta = 0 ~ 70°C

Parameter

Symbol

Min

Max

D+, D− rising time

tR

4

20

D+, D− falling time

tF

4

20

VCRS

1.3

2.0

Output signal crossover voltage

AC measuring condition
Measuring
positoin

TMP92CZ26A
D+
D−

VCC
R3 = 1.5 kΩ

R1 = 27 Ω
R1 = 27 Ω

R2 = 15 kΩ
CL = 50 pF

D+, D−

ns

VCRS

90%

90%

10%

tR

10%

tF

92CZ26A-660

Unit
ns
V

ns

TMP92CZ26A

4.3.9

LCD Controller
Parameter

Variable

Symbol
Min

LCP0 clock period

Max

80 MHz

60 MHz

(n=0)

(n=0)

tCW

2T(n+1)

25

33.3

LCP0 high width
(Include phase inversion)

tCWH

T(n+1) − 5

7.5

11.6

LCP0 low width
(Include phase inversion)

tCWL

T(n+1) − 5

7.5

11.6

Data valid → LCP0 falling
(Include phase inversion)

tDSU

T(n+1) − 7.5

5

9.1

LCP0 falling → Data hold
(Include phase inversion)

tDHD

T(n+1) − 7.5

5

9.1

Signal delay from LCP0 basic
changing point
(Include phase inversion)

tGDL

-20

±20

±20

20

tCW
LCP0

LD0~LD23

tCWH

tCWL

tDSU

tDHD

LD0~LD23 out

LDINV

LVSYNC
LHSYNC
FR
LLOAD
LGOE0
LGOE1
LGOE2

LDINV

tGDL

AC measuring condition
• CL = 50 pF (LCP0 only CL = 30 pF)

Note: The “n” in “Variable” show value that is set to LCDMODE0.
Example: If LCDMODE0 = “01”, n=1, tRWP= 2T(n+1) = 2T

92CZ26A-661

Unit

ns

TMP92CZ26A
I2S Timing

4.3.10

Parameter

Variable

Symbol
Min

80 MHz 60 MHz Unit

Max

I2SCKO clock period

tCR

tIC

100

100

I2SCKO high width

tHB

0.5 tCR − 15

35

35

I2SCKO low width

tLB

0.5 tCR − 15

35

35

I2SDO, I2SWS setup time

tSD

0.5 tCR − 15

35

35

I2SDO, I2SWS hold time

tHD

0.5 tCR − 8

42

42

ns

tCR
tLB

tHB

I2SCKO
tHD

tSD

tHD

I2SDO

I2SWS

Note: The Maximum operation frequency of I2SCKO in I2S circuit is 10MHz. Don’t set I2SCKO to value more than 10MHz.

AC measuring condition
• I2SCKO, I2SDO and I2SWS pins CL =

30

pF

92CZ26A-662

TMP92CZ26A

4.3.11

SPI Controller

Parameter

Variable

Symbol
Min

SPCLK frequency ( = 1/S)

80MHz 60 MHz

Unit

Max

fPP

20

20

15

SPCLK rising time

tr

6

6

6

SPCLK falling time

tf

6

6

6

SPCLK low width

tWL

0.5S − 6

19

28

SPCLK high width

tWH

0.5S − 6

19

28

Output data valid → SPCLK rising

tODS

0.5S − 18

7

15

SPCLK rising/ falling
→ Output data hold

tODH

0.5S − 10

15

23.4

Input data valid
→ SPCLK rising/ falling

tIDS

5

5

5

SPCLK rising/ falling
→ Input data valid

tIDH

5

5

5

MHz

ns

AC measuring condition
• Clock of top column in above table shows system clock frequency, and “S” in “Variable” show
SPCLK clock cycle [ns].
• CL = 25 pF

fPP
SPCLK Output

0.7 VCC

(at SPIMD= “11”)

SPCLK Output
(at SPIMD= “00”)

tf

tWL

tWH

0.2VCC

tr

tODS

tODH

tIDS

tIDH

SPDO Output

SPDI Input

92CZ26A-663

TMP92CZ26A

4.4

AD Conversion Characteristics
Parameter

Symbol

Condition

Min

Typ.

Max

Analog reference voltage (+)

VREFH

AVCC − 0.2

AVCC

AVCC

Analog reference voltage (−)

VREFL

DVSS

DVSS

DVSS + 0.2

AD converter power supply
voltage

AVCC

DVCC3A/3B

DVCC3A/3B

DVCC3A/3B

AD converter ground

AVSS

DVSS

DVSS

Analog input voltage

AVIN

VREFL

Analog current for
reference voltage

analog

Total error
(Quantize error of ±0.5 LSB is
included)

Unit

V

DVSS
VREFH

IREFON

 = 1

0.38

0.45

mA

IREFOFF

 = 0

1

5

μA

ET

Conversion speed at 12uS

±2.0

±4.0

LSB

Note1: 1 LSB = (VREFH − VREFL)/1024[V]
Note2: Minimum frequency for operation
Minimum clock for AD converter operate is 3MHz. (Clock frequency that is seleted by Clock gear ≥ fSYS = 3MHz)
Note3: The power supply current from AVCC pin is included in the power supply current of VCC pin (ICC).

92CZ26A-664

TMP92CZ26A

5.

Table of Special function registers (SFRs)
The SFRs include the I/O ports and peripheral control registers allocated to the 8-Kbyte address
space from 000000H to 001FF0H.

(1) I/O Port

(13) Clock gear, PLL

(2) Interrupt control

(14) 8-bit timer

(3) Memory controller

(15) 16-bit timer

(4) TSI(Touch screen I/F)

(16) SIO

(5) SDRAM controller

(17) SBI

(6) LCD controller

(18) AD converter

(7) PMC

(19) Watchdog timer

(8) USB controller

(20)RTC(Real time clock)

(9) SPI controller

(21)MLD(Melody/alarm generator)

(10) MMU

(22)I2S

(11) NAND-Flash controller

(23) MAC

(12) DMA controller

Table layout
Symbol

Name

Address

7

6

1

0
Bit Symbol
Read/Write
Initial value after reset
Remarks

Note: “Prohibit RMW” in the table means that you cannot use RMW instructions on these register.
Example: When setting bit0 only of the register PxCR, the instruction “SET 0, (PxCR)” cannot be
used. The LD (transfer) instruction must be used to write all eight bits.

Read/Write
R/W:
R:
W:
W*:
Prohibit RMW:

R/W*:

Both read and write are possible.
Only read is possible.
Only write is possible.
Both read and write are possible (when this bit is read as1)
Read modify write instructions are prohibited. (The EX, ADD, ADC, BUS,
SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC,
RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are read
modify write instructions.)
Read modify write is prohibited when controlling the pull-up resistor.

92CZ26A-665

TMP92CZ26A

Table 5.1 I/O Register Address Map
[1] Port (1/2)
Address

Name

0000H

Address

Name

0010H P4

Address

Name

0020H P8

Address

Name

0030H PC

1H

1H

1H P8FC2

1H

2H

2H

2H

2H PCCR

3H

3H P4FC

3H P8FC

3H PCFC

4H P1

4H P5

4H P9

4H

5H

5H

5H P9FC2

5H

6H P1CR

6H

6H P9CR

6H

7H P1FC

7H P5FC

7H P9FC

7H

8H

8H P6

8H PA

8H

9H

9H

9H

9H

AH

AH P6CR

AH

AH

BH

BH P6FC

BH PAFC

BH

CH

CH P7

CH

CH PF

DH

DH

DH

DH

EH

EH P7CR

EH

EH PFCR

FH

FH P7FC

FH

FH PFFC

Address

Name

0040H PG

Address

Name

Address

Name

Address

Name

0050H PK

0060H PP

0070H Reserved

1H

1H

1H

1H Reserved

2H

2H

2H PPCR

2H Reserved

3H PGFC

3H PKFC

3H PPFC

3H Reserved

4H

4H PL

4H PR

4H Reserved

5H

5H

5H

5H Reserved

6H

6H

6H PRCR

6H Reserved

7H

7H PLFC

7H PRFC

7H Reserved

8H

8H PM

8H PZ

8H Reserved

9H

9H

9H

9H Reserved

AH

AH

AH PZCR

AH Reserved

BH

BH PMFC

BH

BH Reserved

CH PJ

CH PN

CH

CH Reserved

DH

DH

DH

DH Reserved

EH PJCR

EH PNCR

EH

EH Reserved

FH PJFC

FH PNFC

FH

FH Reserved

92CZ26A-666

TMP92CZ26A
[1] Port (2/2)
Address

Name

0080H

Address

Name

Address

0090H PGDR

Name

Address

00A0H PT

00B0H PX

Name

1H P1DR

1H

1H

1H

2H

2H

2H PTCR

2H PXCR

3H

3H PJDR

3H PTFC

3H PXFC

4H P4DR

4H PKDR

4H PU

4H

5H P5DR

5H PLDR

5H

5H

6H P6DR

6H PMDR

6H PUCR

6H

7H P7DR

7H PNDR

7H PUFC

7H

8H P8DR

8H PPDR

8H PV

8H

9H P9DR

9H PRDR

9H PVFC2

9H

AH PADR

AH PZDR

AH PVCR

AH

BH

BH PTDR

BH PVFC

BH

CH PCDR

CH PUDR

CH PW

CH

DH

DH PVDR

DH

DH

EH

EH PWDR

EH PWCR

EH

FH PFDR

FH PXDR

FH PWFC

FH

Note: Do not access no allocated name address.

92CZ26A-667

TMP92CZ26A

[2] INTC
Address

Name

00D0H INTE12
1H INTE34

Address

Name

Address

00E0H INTESBIADM

Name

00F0H INTE0

1H INTESPI

1H INTETC01

Address

Name

0100H DMA0V
1H DMA1V

/INTEDMA01
2H INTE56

2H Reserved

2H INTETC23

2H DMA2V

/INTEDMA23
3H INTE7

3H INTEUSB

3H INTETC45

3H DMA3V

/INTEDMA45
4H INTETA01

4H Reserved

4H INTETC67

4H DMA4V

5H INTETA23

5H INTEALM

5H SIMC

5H DMA5V

6H INTETA45

6H Reserved

6H IIMC0

6H DMA6V

7H INTETA67

7H

7H INTWDT

7H DMA7V

8H INTETB0

8H INTERTC

8H INTCLR

8H DMAB

9H INTETB1

9H INTEKEY

9H

9H DMAR

AH

AH INTELCD

AH IIMC1

AH DMASEL

BH INTES0

BH INTEI2S01

BH

BH

CH

CH INTENDFC

CH

CH

DH

DH Reserved

DH

DH

EH

EH INTEP0

EH

EH

FH

FH INTEAD

FH Reserved

FH

[3] MEMC
Address

[4] TSI
Name

Address

Name

Address

Name

Address

Name

0140H B0CSL

0150H

0160H

01F0H TSICR0

1H B0CSH

1H

1H

1H TSICR1

2H MAMR0

2H

2H

2H Reserved

3H MSAR0

3H

3H

3H

4H B1CSL

4H

4H

4H

5H B1CSH

5H

5H

5H
6H

6H MAMR1

6H

6H PMEMCR

7H MSAR1

7H

7H

7H

8H B2CSL

8H BEXCSL

8H CSTMGCR

8H

9H B2CSH

9H BEXCSH

9H WRTMGCR

9H

AH MAMR2

AH

AH RDTMGCR0

AH

BH MSAR2

BH

BH RDTMGCR1

BH

CH B3CSL

CH

CH BROMCR

CH

DH B3CSH

DH

DH RAMCR

DH

EH MAMR3

EH

EH

EH

FH MSAR3

FH

FH

FH

Note: Do not access no allocated name address.

92CZ26A-668

TMP92CZ26A
[5] SDRAMC
Address

Name

0250H SDACR
1H SDCISR
2H SDRCR
3H SDCMM
4H SDBLS
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH

[6] LCDC
Address

[7] PMC
Name

Address

Name

Address

Name

Address

0280H LCDMODE0

0290H LCDHSDLY

02A0H LSAML

1H LCDMODE1

1H LCDO0DLY

1H LSAMM

1H

2H

2H LCDO1DLY

2H LSAMH

2H

3H LCDDVM0

3H LCDO2DLY

3H

3H

4H LCDSIZE

4H LCDHSW

4H LSASL

4H

5H LCDCTL0

5H LCDLDW

5H LSASM

5H

6H LCDCTL1

6H LCDHO0W

6H LSASH

6H

7H LCDCTL2

7H LCDHO1W

7H

7H

8H LCDDVM1

8H LCDHO2SW

8H LSAHX

8H

9H

9H LCDHWB8

9H LSAHX

9H

AH LCDHSP

AH

AH LSAHY

AH

BH LCDHSP

BH

BH LSAHY

BH

CH LCDVSP

CH

CH LSASS

CH

DH LCDVSP

DH

DH LSASS

DH

EH LCDPRVSP

EH

EH LSACS

EH

FH LCDHSDLY

FH

FH LSACS

FH

Note: Do not access no allocated name address.

92CZ26A-669

Name

02F0H PMCCTL

TMP92CZ26A
[8] USBC (1/2)
Address

Name

0500H Descriptor
to

RAM

067FH (384 byte)

Address

Name

07B0H

Address

Name

Address

Name

Address

Name

0780H ENDPOINT0

0790H EP0_STATUS

07A0H

1H ENDPOINT1

1H EP1_STATUS

1H EP1_SIZE_L_B

2H ENDPOINT2

2H EP2_STATUS

2H EP2_SIZE_L_B

3H ENDPOINT3

3H EP3_STATUS

3H EP3_SIZE_L_B

4H

4H

4H

5H

5H

5H

6H

6H

6H

7H

7H

7H

8H

8H EP0_SIZE_L_A

8H

9H EP1_MODE

9H EP1_SIZE_L_A

9H EP1_SIZE_H_A

AH EP2_MODE

AH EP2_SIZE_L_A

AH EP2_SIZE_H_A

BH EP3_MODE

BH EP3_SIZE_L_A

BH EP3_SIZE_H_A

CH

CH

CH

DH

DH

DH

EH

EH

EH

FH

FH

FH

Address

Name

07C0H bmRequestType

Address

Name

07D0H COMMAND

1H EP1_SIZE_H_B

1H bRequest

2H EP2_SIZE_H_B

2H wValue_L

1H EPx_SINGLE1
2H Reserved

3H EP3_SIZE_H_B

3H wValue_H

3H EPx_BCS1

4H

4H wIndex_L

4H Reserved

5H

5H wIndex_H

5H

6H

6H wLength_L

6H INT_Control

7H

7H wLength_H

7H

8H

8H SetupReceived

8H Standard Request Mode

9H

9H Current_Config

9H Request Mode

AH

AH Standard Request

AH

BH

BH Request

BH

CH

CH DATASET1

CH

DH

DH DATASET2

DH

EH

EH USB STATE

EH ID_CONTROL

FH

FH EOP

FH ID_STATE

Note: Do not access no allocated name address.

92CZ26A-670

TMP92CZ26A
[8] USBC (2/2)
Address

Name

07E0H Port Status
1H FRAME_L

Address

Name

07F0H USBINTFR1
1H USBINTFR2

2H FRAME_H

2H USBINTFR3

3H ADDRESS

3H USBINTFR4

4H

4H USBINTMR1

5H

5H USBINTMR2

6H USBREADY

6H USBINTMR3

7H

7H USBINTMR4

8H Set Descriptor STALL

8H USBCR1

9H

9H

AH

AH

BH

BH

CH

CH

DH

DH

EH

EH

FH

FH

Note: Do not access no allocated name address.

92CZ26A-671

TMP92CZ26A
[9] SPIC
Address

Name

Address

Name

0820H SPIMD

0830H SPITD0

1H SPIMD

1H SPITD0

2H SPICT

2H SPITD1

3H SPICT

3H SPITD1

4H SPIST

4H SPIRD0

5H SPIST

5H SPIRD0

6H SPICR

6H SPIRD1

7H SPICR

7H SPIRD1

8H

8H

9H

9H

AH

AH

BH

BH

CH SPIIE

CH

DH SPIIE

DH

EH

EH

FH

FH

[10] MMU
Address

Name

Address

Name

Address

Name

08A0H LOCALESX

Address

Name

0880H LOCALPX

0890H LOCALRX

08B0H LOCALOSX

1H LOCALPX

1H LOCALRX

1H LOCALESX

1H LOCALOSX

2H LOCALPY

2H LOCALRY

2H LOCALESY

2H LOCALOSY

3H LOCALPY

3H LOCALRY

3H LOCALESY

3H LOCALOSY

4H LOCALPZ

4H LOCALRZ

4H LOCALESZ

4H LOCALOSZ

5H LOCALPZ

5H LOCALRZ

5H LOCALESZ

5H LOCALOSZ

6H

6H

6H

6H

7H

7H

7H

7H

8H LOCALLX

8H LOCALWX

8H LOCALEDX

8H LOCALODX

9H LOCALLX

9H LOCALWX

9H LOCALEDX

9H LOCALODX

AH LOCALLY

AH LOCALWY

AH LOCALEDY

AH LOCALODY

BH LOCALLY

BH LOCALWY

BH LOCALEDY

BH LOCALODY

CH LOCALLZ

CH LOCALWZ

CH LOCALEDZ

CH LOCALODZ

DH LOCALLZ

DH LOCALWZ

DH LOCALEDZ

DH LOCALODZ

EH

EH

EH

EH

FH

FH

FH

FH

Note: Do not access no allocated name address.

92CZ26A-672

TMP92CZ26A

[11] NAND-Flash controller
Address

Name

08C0H NDFMCR0

Address

Name

Address

Name

08D0H NDRSCA0

1FF0H NDFDTR0

1H NDFMCR0

1H NDRSCA0

1H NDFDTR0

2H NDFMCR1

2H NDRSCD0

2H NDFDTR1

3H NDFMCR1

3H

3H NDFDTR1

4H NDECCRD0

4H NDRSCA1

4H

5H NDECCRD0

5H NDRSCA1

5H

6H NDECCRD1

6H NDRSCD1

6H

7H NDECCRD1

7H

7H

8H NDECCRD2

8H NDRSCA2

8H

9H NDECCRD2

9H NDRSCA2

9H

AH NDECCRD3

AH NDRSCD2

AH

BH NDECCRD3

BH

BH

CH NDECCRD4

CH NDRSCA3

CH

DH NDECCRD4

DH NDRSCA3

DH

EH

EH NDRSCD3

EH

FH

FH

FH

92CZ26A-673

TMP92CZ26A

[12] DMAC
Address

Name

Address

Name

Address

Name

Address

Name

0900H HDMAS0

0910H HDMAS1

0920H HDMAS2

0930H HDMAS3

1H HDMAS0

1H HDMAS1

1H HDMAS2

1H HDMAS3

2H HDMAS0

2H HDMAS1

2H HDMAS2

2H HDMAS3

3H

3H

3H

3H

4H HDMAD0

4H HDMAD1

4H HDMAD2

4H HDMAD3

5H HDMAD0

5H HDMAD1

5H HDMAD2

5H HDMAD3

6H HDMAD0

6H HDMAD1

6H HDMAD2

6H HDMAD3

7H

7H

7H

7H

8H HDMACA0

8H HDMACA1

8H HDMACA2

8H HDMACA3

9H HDMACA0

9H HDMACA1

9H HDMACA2

9H HDMACA3

AH HDMACB0

AH HDMACB1

AH HDMACB2

AH HDMACB3

BH HDMACB0

BH HDMACB1

BH HDMACB2

BH HDMACB3

CH HDMAM0

CH HDMAM1

CH HDMAM2

CH HDMAM3

DH

DH

DH

DH

EH

EH

EH

EH

FH

FH

FH

FH

Address

Name

Address

Name

Address

0940H HDMAS4

0950H HDMAS5

0970H

1H HDMAS4

1H HDMAS5

1H

2H HDMAS4

2H HDMAS5

2H

3H

3H

3H

4H HDMAD4

4H HDMAD5

4H

5H HDMAD4

5H HDMAD5

5H

6H HDMAD4

6H HDMAD5

6H

7H

7H

7H

8H HDMACA4

8H HDMACA5

8H

9H HDMACA4

9H HDMACA5

9H

AH HDMACB4

AH HDMACB5

AH

Name

BH HDMACB4

BH HDMACB5

BH

CH HDMAM4

CH HDMAM5

CH Reserved

DH

DH

DH Reserved

EH

EH

EH HDMAE

FH

FH

FH HDMATR

92CZ26A-674

TMP92CZ26A

[13] CGEAR, PLL
Address

Name

10E0H SYSCR0

[14] 8-bit timer
Address

Name

Address

1100H TA01RUN

Name

1110H TA45RUN

1H SYSCR1

1H

2H SYSCR2

2H TA0REG

1H
2H TA4REG

3H EMCCR0

3H TA1REG

3H TA5REG

4H EMCCR1

4H TA01MOD

4H TA45MOD

5H EMCCR2

5H TA1FFCR

5H TA5FFCR

6H Reserved

6H

6H

7H

7H

7H

8H PLLCR0

8H TA23RUN

8H TA67RUN

9H PLLCR1

9H

9H

AH

AH TA2REG

AH TA6REG

BH

BH TA3REG

BH TA7REG

CH

CH TA23MOD

CH TA67MOD

DH

DH TA3FFCR

DH TA7FFCR

EH

EH

EH

FH

FH

FH

[15] 16-bit timer
Address

Name

1180H TB0RUN

[16] SIO
Address

Name

Address

1190H TB1RUN

[17] SBI
Name

1200H SC0BUF

Address

Name

1240H SBI0CR1

1H

1H

1H SC0CR

1H SBI0DBR

2H TB0MOD

2H TB1MOD

2H SC0MOD0

2H I2C0AR

3H TB0FFCR

3H TB1FFCR

3H BR0CR

3H SBI0CR2/SBI0SR

4H

4H

4H BR0ADD

4H SBI0BR0

5H

5H

5H SC0MOD1

5H

6H

6H

6H

6H

7H

7H

7H SIRCR

7H SBI0CR0

8H TB0RG0L

8H TB1RG0L

8H

8H

9H TB0RG0H

9H TB1RG0H

9H

9H

AH TB0RG1L

AH TB1RG1L

AH

AH

BH TB0RG1H

BH TB1RG1H

BH

BH

CH TB0CP0L

CH TB1CP0L

CH

CH

DH TB0CP0H

DH TB1CP0H

DH

DH

EH TB0CP1L

EH TB1CP1L

EH

EH

FH TB0CP1H

FH TB1CP1H

FH

FH

Note: Do not access no allocated name address.

92CZ26A-675

TMP92CZ26A

[18] 10-bit ADC
Address

Name

[19] WDT
Address

Name

Address

12A0H ADREG0L

12B0H ADREGSPL

1H ADREG0H

1H ADREGSPH

2H ADREG1L

2H Reserved

2H

3H ADREG1H

3H Reserved

3H

1H WDCR

4H ADREG2L

4H ADCM0REGL

4H

5H ADREG2H

5H ADCM0REGH

5H

6H ADREG3L

6H ADCM1REGL

6H

7H ADREG3H

7H ADCM1REGH

7H

8H ADREG4L

8H ADMOD0

8H

9H ADREG4H

9H ADMOD1

9H

AH ADREG5L

AH ADMOD2

AH

BH ADREG5H

BH ADMOD3

BH

CH Reserved

CH ADMOD4

CH

DH Reserved

DH ADMOD5

DH

EH Reserved

EH

EH

FH Reserved

FH ADCCLK

FH

[20] RTC
Address

[21] MLD
Name

1320H SECR
1H MINR

Address

Name

1330H ALM
1H MELALMC

2H HOURR

2H MELFL

3H DAYR

3H MELFH

4H DATER

4H ALMINT

5H MONTHR

5H

6H YEARR

6H

7H PAGER

7H

8H RESTR

8H

9H

9H

AH

AH

BH

BH

CH

CH

DH

DH

EH

EH

FH

FH

Name

1300H WDMOD

Note: Do not access no allocated name address.

92CZ26A-676

TMP92CZ26A
[22] I2S
Address

[23] MAC
Name

1800H I2S0BUF

Address

Name

Address

1810H I2S1BUF

Name

Address

1BE0H MACMA

1BF0H

1H

1H

1H MACMA

1H

2H

2H

2H MACMA

2H

3H

3H

3H MACMA

3H

4H

4H

4H MACMB

4H

5H

5H

5H MACMB

5H

6H

6H

6H MACMB

6H

7H

7H

7H MACMB

7H

8H I2S0CTL

8H I2S1CTL

8H MACORL

8H

9H I2S0CTL

9H I2S1CTL

9H MACORL

9H

AH I2S0C

AH I2S1C

AH MACORL

AH

Name

BH I2S0C

BH I2S1C

BH MACORL

BH

CH

CH

CH MACORH

CH MACCR

DH

DH

DH MACORH

DH

EH

EH

EH MACORH

EH

FH

FH

FH MACORH

FH

Note: Do not access no allocated name address.

92CZ26A-677

TMP92CZ26A
(1) I/O ports (1/11)
Symbol

Name

Address

P1

PORT1

0004H

P4

PORT4

0010H

P5

PORT5

0014H

P6

PORT6

0018H

P7

PORT7

001CH

P8

PORT8

0020H

P9

PORT9

0024H

PA

PORTA

0028H

PC

PORTC

0030H

PF

PORTF

003CH

7

6

5

4

3

2

1

0

P17

P16

P15

P14

P13

P12

P11

P10

R/W
Data from external port (Output latch register is cleared to “0”)
P47
P46
P45
P44
P43
P42
P41
P40
R/W
0
0
0
0
0
0
0
0
P57
P56
P55
P54
P53
P52
P51
P50
R/W
0
0
0
0
0
0
0
0
P67
P66
P65
P64
P63
P62
P61
P60
R/W
Data from external port (Output latch register is cleared to “0”)
P76
P75
P74
P73
P72
P71
P70
R/W
Data from external Data from external port Data from external port
port (Output latch
(Output latch register is (Output latch register is
1
register is set to “1”)
cleared to “0”)
set to “1”)
P87
P86
P85
P84
P83
P82
P81
P80
R/W
1
1
1
1
1
0
1
1
P97
P96
P92
P91
P90
R
R/W
Data from external port
Data from external port
(Output latch register is set to “1”)
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
R
Data from external port
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
R/W
Data from external port (Output latch register is set to “1”)
PF7
PF5
PF4
PF3
PF2
PF1
PF0
R/W
R/W
1

PG

PORTG

0040H
PJ7

PJ

PORTJ

004CH
1
PK7

PK

PORTK

0050H
0
PL7

PL

PORTL

0054H

PM

PORTM

0058H

PN

PORTN

005CH

PP

PORTP

0060H

0
PM7
R/W
1
PN7

PP7
0

Data from external port (Output latch register is set to “1”)
PG5
PG4
PG3
PG2
PG1
PG0
R
Data from external port
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
R/W
Data from external port
(Output latch register is
1
1
1
1
1
set to “1”)
PK6
PK5
PK4
PK3
PK2
PK1
PK0
R/W
0
0
0
0
0
0
0
PL6
PL5
PL4
PL3
PL2
PL1
PL0
R/W
0
0
0
0
0
0
0
PM2
PM1
R/W
1
1
PN6
PN5
PN4
PN3
PN2
PN1
PN0
R/W
Data from external port (Output latch register is cleared to “1”)
PP6
PP5
PP4
PP3
PP2
PP1
R/W
Data from external port
0
(Output latch register is cleared to “0”)

92CZ26A-678

TMP92CZ26A
(1) I/O ports (2/11)
Symbol

Name

Address

PR

PORTR

0064H

PT

PORTT

00A0H

PU

PORTU

00A4H

7

PT7

PV

PORTV

00A8H

PW

PORTW

00ACH

PX

PORTX

00B0H

PZ

PORTZ

0068H

6

PT6

5

PT5

4

PT4

3

2

1

0

PR3

PR2

PR1

PR0

R/W
Data from external port
(Output latch register is cleared to “0”)
PT3
PT2
PT1
PT0

R/W
Data from external port (Output latch register is cleared to “0”)
PU7
PU6
PU5
PU4
PU3
PU2
PU1
R/W
Data from external port (Output latch register is cleared to “0”)
PV7
PV6
PV4
PV3
PV2
PV1
R/W
R/W
Data from external port
Data from external port
(Output latch register is
(Output latch register is cleared to “0”)
cleared to “0”)
PW7
PW6
PW5
PW4
PW3
PW2
PW1
R/W
Data from external port (Output latch register is cleared to “0”)
PX7
PX5
PX4
R/W
R/W
Data from external port
(Output latch register is cleared to “0”)
PZ7
PZ6
PZ5
PZ4
PZ3
PZ2
PZ1
R/W
Data from external port (Output latch register is cleared to “0”)

92CZ26A-679

PU0

PV0

PW0

PZ0

TMP92CZ26A

(1) I/O ports (3/11)
Symbol
P1CR

Name
PORT1
control
register

Address
0006H
(Prohibit
RMW)

P1FC

PORT1
function
register

0007H
(Prohibit
RMW)

P4FC

PORT4
function
register

0013H
(Prohibit
RMW)

7

6

5

4

3

2

1

0

P17C

P16C

P15C

P14C

P13C

P12C

P11C

P10C

0

0

0

0
0: Input

0
1:Output

0

0

0

W

P47F

P46F

P45F

P44F

P5FC

0017H
(Prohibit
RMW)

0/1

0/1

0/1

P57F

P56F

P55F

0/1

P6CR

001AH
(Prohibit
RMW)

0/1

0/1

0/1

P67C

P66C

P65C

P6FC

0

0

0/1

P7CR

001EH

control
register

(Prohibit
RMW)

0/1

0/1

P53F

P52F

P51F

P50F

0/1

0/1

0/1

0/1

1: Address bus (A8~A15)
P64C

0

P66F

P63C

P62C

P61C

P60C

0

0

0

0

0

P65F

P63F

P62F

P61F

P60F

0/1

0/1

0/1

0/1

1: Output

P64F
W

0/1

0/1

0/1

0/1

0: Port

1: Address bus (A16~A23)

P76C

P75C

P74C

P73C

P72C

P71C

W

W

W

W

W

W

0

0

0

0
PORT7

0/1

W

P67F
001BH
(Prohibit
RMW)

0/1

W

0: Input
PORT6
function
register

P41F

1: Address bus (A0~A7)
P54F

0: Port
PORT6
control
register

P42F

W
0: Port

PORT5
function
register

P43F

P1F
W
0/1
0: Port
1: Data
bus
(D8~D15)
P40F

0

0: Input
port,
WAIT
1:Output
port

0: Input
port,
NDR/ B
1: Output
port,
R/ W

0: Input
0: Input
0: Input
port
port
port
1: Output
1: Output
1: Output
port,
port,
port,
EA25
EA24
NDWE @
 = 0,
WRLU @
 = 1

P76F

P75F

P74F

P73F

0

0

0

0

P72F

0
0: Input
port
1: Output
port,
NDRE @
 = 0,
WRLL @
 = 1

P71F

P70F

0

0

W
P7FC

PORT7
function
register

001FH
(Prohibit
RMW)

0: Port
1: WAIT

0: Port
0:Port
1:NDR/ B , 1: EA25
R/ W

92CZ26A-680

0:Port
1: EA24

0
0: Port
1: NDWE @
 = 0,
WRLU @
 = 1

0: Port
0: Port
1: NDRE @ 1: RD
 = 0,
WRLL @
 = 1

TMP92CZ26A

(1) I/O ports (4/11)
Symbol

Name

Address

7

6

5

4

3

2

1

0

P87F

P86F

P85F

P84F

P83F

P82F

P81F

P80F

0
0: Port
1:  1:  1: CSZC

0
0: Port
1: CSZB

0
0: Port
1: CS3 ,

0
0: Port,

W
P8FC

PORT8
function
register

0023H
(Prohibit
RMW)

0
0: Port

0
0: Port

CSXA

CSZA

0
0: Port
1: CS1

0
0: Port
1: CS0

1: CS2 ,
SDCS

P87F2

P86F2

P84F2

W

P8FC2

PORT8
function
fegister2

0021H
(Prohibit
RMW)

0
0: CSXB
1: ND1CE

P82F2

0
0: CSZD
1: ND0CE

0
0: Port,
CS3

1: CSXA

0
0: Output
port,
CS2
1: CSZA ,
SDCS

P92C

P9CR

P9FC

PORT9
control
register

PORT9
function
register

0

0026H
(Prohibit
RMW)

0 Input
port,
CTS 0
1: Output
port,
SCLK0

P96F
W

0027H
(Prohibit
RMW)

P92F
W

0
0: Input
port,
1:INT4
–

P9FC2

PORT9
function
register2

0025H
(Prohibit
RMW)

P81F2

W

0
0:Port,
CTS 0

W
0
Always
write “0”

92CZ26A-681

P91C
W
0
0: Input
port,
RXD0
1: Output
port,

P90C
0
0: Input
port,
1: Output
port,
TXD0

P90F
W
0
0:Port
1:TXD0

1:SCLK0
–

W
0
Always
write “0”

0
0: 
1: SDCS

P90FC2
W
0
0: CMOS
1:Open
-Drain

TMP92CZ26A

(1) I/O ports (5/11)
Symbol
PAFC

Name
PORTA
function
register

Address
002BH
(Prohibit
RMW)

7

6

5

4

3

2

1

0

PA7F

PA6F

PA5F

PA4F

PA3F

PA2F

PA1F

PA0F

0

0

0

0

0

0

0

0

PC1C

PC0C

W
0: Key-in disable
PC7C

PC6C

PC5C

1: Key-in enable

PC4C

PC3C

PC2C

W

PCCR

PORTC
control
register

0
0032H
(Prohibit
RMW)

0

0: Input
0: Input
port,
port,
1: Output
EA28
port, 1: Output
KO output
port
(Open
-drain)

PC7F

PC6F

0
0: Input
port,
EA27
1: Output
port

PC5F

0
0: Input
port,
EA26
1: Output
port

0
0: Input
port,
INT3
1: Output
port,
TA2IN

PC4F

0
0: Input
port,
INT2
1: Output
port,

PC3F

PC2F

0
0: Input
port,
INT1
1: Output
port,
TA0IN

PC1F

0
0: Input
port,
INT0
1: Output
port,

PC0F

W

PCFC

PORTC
function
register

0033H
(Prohibit
RMW)

0

0

0

0

0: Port

0: Port

0:Port

0:Port

0:Port

1:KO

1:EA28,

1:EA27

1:EA26

1:INT3,

output

0

0

0

0

0: Port

0: Port

0: Port

1: INT1,

1:INT0

1: INT2

TA0IN

TA2IN

(Open
-Drain)

PF5C
PFCR

PORTF
control
register

PF4C

PF3C

003EH

PF2C

PF1C

PF0C

0

0

0

PF1F

PF0F

W

(Prohibit
RMW)

0

0

0

PF5F

PF4F

PF3F

0

0

0

0

0

0

0:Port

0:Port

0:Port

0:Port

0:Port

0:Port

1:I2S0WS

1:I2S0DO

1:I2S1CKO

0: Input, 1: Output
PF7F

PFFC

PORTF
function
register

003FH

W

(Prohibit
RMW)

1
0: Output
port,
1: SDCLK

PF2F
W

1:I2S1WS 1:I2S1DO 1:I2S1CKO

92CZ26A-682

TMP92CZ26A

(1) I/O ports (6/11)
Symbol

Name

Address

7

6

5

4

3

2

1

0

PF2F

PF1F

PF0F

PG3F
W
PGFC

PORTG
function
register

0043H

0

(Prohibit
RMW)

0:Input
port,
AN3
1: ADTRG

PJCR

PORTJ
control
register

PJ6C

004EH
(Prohibit
RMW)

0
0:Input
PF7F

PJFC

PORTJ
function
register

004FH
(Prohibit
RMW)

PKFC

PLFC

PMFC

PORTL
function
register

PORTM
function
register

PF6F

0
1: Output
PF5F

PF4F

0

0

0

0

0

0

0

0

0: Port

0: Port

0: Port

0: Port

0: Port

0: Port

0: Port

0: Port

1: SDCKE

1:NDCLE

1: NDALE

1:

1:
SDLLDQM

1: SDWE ,

1: SDCAS , 1: SDRAS ,

SDLUDQM

SRWR

SRLUB

PK4F

PK3F

PK2F

0

0

PK6F

PK5F

0053H
(Prohibit
RMW)

0057H
(Prohibit
RMW)

005BH
(Prohibit
RMW)

PF3F
W

PK7F
PORTK
function
register

PJ5C
W

SRLLB

PK1F

PK0F

0

0

W
0

0

0

0

0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
1: LGOE2 1: LGOE1 1: LGOE0 1: LHSYNC 1: LVSYNC 1: LFR
PL7F

PL6F

PL5F

PL4F

PL3F

PL2F

0: Port
0: Port
1: LLOAD 1: LCP0
PL1F

PL0F

0

0

W
0

0

0
0: Port

0
0
0
1: Data bus for LCDC (LD7~LD0)

PM7F

PM2F

PM1F

W
0

W
0

W
0

0: Port
0: Port
1: ALARM , 1:MLDALM

0: Port
1:PWE

MLDALM

92CZ26A-683

,TA1OUT

TMP92CZ26A

(1) I/O ports (7/11)
Symbol
PNCR

Name
PORTN
control
register

Address
005EH
(Prohibit
RMW)

7

6

5

4

3

2

1

0

PN7C

PN6C

PN5C

PN4C

PN3C

PN2C

PN1C

PN0C

0

0

0

0

0

0

0

0

PN3F

PN2F

PN1F

PN0F

0

0

0

0

W
0: Input 1: Output

PNFC

PORTN
function
register

005FH
(Prohibit
RMW)

PN7F

PN6F

PN5F

PN4F
W

0

0

0

0

0:CMOS output 1:Open-Drain output
PP5C
PPCR

PORTP
control
register

PP4C

PP3C

0062H

PP2C

PP1C

0

0

PP2F

PP1F

W

(Prohibit
RMW)

0

0

0
0: Input 1: Output

PP7F

PPFC

PORTP
function
register

PRCR

PORTR
control
register

0063H
(Prohibit
RMW)

0
0: Port
1:
TB1OUT0

PP6F
0
0: Port
1:
TB0OUT0

PP5F

PP4F

0

W
0

PP3F
0

0

0

0: Port
1:
TB1IN0@
=1
INT7@
=0

0: Port
1:
TB0IN0@
=1
INT6@
=0

0: Port
1:
TA7OUT@
=1
INT5@
=0

0: Port
1: TA5OUT

0: Port
1: TA3OUT

PR3C

PR2C

0066H
(Prohibit
RMW)

0
PR3F

PRFC

PTCR

(Prohibit
RMW)

PORTT
control
register

00A2H
(Prohibit
RMW)

PTFC

00A3H
(Prohibit
RMW)

PR0C

PR2F

PR1F

0
PR0F

W
0

PT7C

PT6C

PT5C

0

0

0

PT7F
PORTT
function
register

0
0
0: Input, 1: Output

0067H

PORTR
function
register

PR1C
W

PT6F

PT5F

0

0: Port
0: Port
1: SPCLK 1: SPCS
PT4C
PT3C
PT2C
W
0

0

0: Input

1: Output

PT4F

0
0: Port
1: SPDO
PT1C

0
0: Port
1: SPDI
PT0C

0

0

0

PT3F

PT2F

PT1F

PT0F

0

0

0

0

W
0

0

0

0

0: Port 1: Data bus for LCDC (LD15~LD8)

92CZ26A-684

TMP92CZ26A
(1) I/O ports (8/11)
Symbol
PUCR

Name
PORTU
control
register

Address
00A6H
(Prohibit
RMW)

7

6

5

4

3

2

1

0

PU7C

PU6C

PU5C

PU4C

PU3C

PU2C

PU1C

PU0C

0

0

0

0

0

0

PU7F

PU6F

PU5F

0
1: Output
PU3F

PU2F

PU1F

PU0F

W
0
0: Input
PU4F
W

PUFC

PORTU
function
register

00A7H
(Prohibit
RMW)

0

0

0

0

0

0

0: Port

0: Port

0: Port

0: Port

0

0: Port

0

0: Port

0: Port

0: Port

1: LD23

1: LD22

1: LD21@

1: LD20

1: LD19

1: LD18

1: LD17

1: LD16

=1

PV7C
PVCR

PORTV

00AAH

control
register

(Prohibit
RMW)

PV6C

PV2C

0

0

W
0: Input 1: Output

0
0: Input

PV2F

PV6F
W

PORTV
function
register

00ABH
(Prohibit
RMW)

PV0C

W

0
PV7F

PVFC

PV1C

0
1: Output

PV1F

PV0F

W

0

0

0

0

0

0: Port

0: Port

0: Port

0: Port

0: Port

1: SCL

1: SDA

1:Reserved

1:Reserved

1: SCLK0@

PW2C

PW1C

PW0C

0

0

0

PW2F

PW1F

PW0F

0

0

0

PZ2C

PZ1C

PZ0C

0

0

0

=1

PWCR

PWFC

PXCR

PORTW

00AEH

control
register

(Prohibit
RMW)

PORTW
function
register

00AFH
(Prohibit
RMW)

PORTX

00B2H

control
register

(Prohibit
RMW)

PW7C

PW6C

PXFC

PW4C

PW3C
W

0

0

0

PW7F

PW6F

PW5F

0
0: Input

0
1: Output

PW4F

PW3F
W

0

0

0

PX7C

PX5C

W

W
0

0
0: Input

PORTX
function
register

PW5C

0
0
0: Port 1: Reserved

1: Output

PX7F

PX5F

PX4F

W

W

W

0

0

00B3H
0:Port
(Prohibit
RMW) 1:Reserved

0

0:Port

0:Port

1: X1USB

1: CLKOUT

input

@=0
LDIV
@=1

PZCR

PORTZ

006AH

control
register

(Prohibit
RMW)

PZ7C

PZ6C

PZ5C

PZ4C

PZ3C
W

0

0

0

0
0: Input

92CZ26A-685

0
1: Output

TMP92CZ26A

(1) I/O ports (9/11)
Symbol

Name

Address

P1DR

PORT1
drive
register

P2DR

PORT2
drive
register

P3DR

PORT3
drive
register

0083H

P4DR

PORT4
drive
register

0084H

P5DR

PORT5
drive
register

0085H

P6DR

PORT6
drive
register

0086H

P7DR

PORT7
drive
register

0087H

P8DR

PORT8
drive
register

0088H

P9DR

PORT9
drive
register

0089H

PADR

PORTA
drive
register

008AH

0081H

7

6

5

P17D

P16D

P15D

1
P27D

0082H

1
P37D

4

3

2

1

P14D
P13D
P12D
P11D
R/W
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P26D
P25D
P24D
P23D
P22D
P21D
R/W
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P36D
P35D
P34D
P33D
P32D
P31D
R/W

1

1

1

1

PC7D

PC6D

1

1

0
P10D
1
P20D
1
P30D

1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P47D
P46D
P45D
P44D
P43D
P42D
P41D
P40D
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P57D
P56D
P55D
P54D
P53D
P52D
P51D
P50D
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P67D
P66D
P65D
P64D
P63D
P62D
P61D
P60D
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P76D
P75D
P74D
P73D
P72D
P71D
P70D
R/W
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P87D
P86D
P85D
P84D
P83D
P82D
P81D
P80D
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P97D
P96D
P92D
P91D
P90D
R/W
R/W
1
1
1
1
1
Input/Output buffer
Input/Output buffer drive register
drive register for
for standby mode
standby mode
PA7D
PA6D
PA5D
PA4D
PA3D
PA2D
PA1D
PA0D
R/W
1

1

1

1

1

1

PC2D

PC1D

PC0D

1

1

1

PF1D

PF0D

1

1

Input/Output buffer drive register for standby mode

PCDR

PORTC
drive
register

008CH

PC5D
1

PC4D
PC3D
R/W
1

1

Input/Output buffer drive register for standby mode

PFDR

PORTF
drive
register

008FH

PF7D
R/W
1

PF5D

PF4D

1

1

PF3D
PF2D
R/W
1

1

Input/Output buffer drive register for standby mode

92CZ26A-686

TMP92CZ26A
(1) I/O ports (10/11)
Symbol

PGDR

Name

PORTG
drive
register

Address

7

6

PJDR

4

3

2

PG3D

PG2D

1

0

R/W
1

0090H

1

Input/Output buffer
drive register for
standby mode
PJ7D

PORTJ
drive
register

5

0093H

PJ6D

PJ5D

PJ4D

PJ3D

PJ2D

PJ1D

PJ0D

1

1

1

1

R/W
1

1

1

1

Input/Output buffer drive register for standby mode
PK7D

PK6D

PK5D

PK4D

1

1

1

1

PORTK
PKDR

drive
register

PK3D

PK2D

PK1D

PK0D

1

1

1

1

R/W

0094H

Input/Output buffer drive register for standby mode
PL7D
PLDR

PORTL
drive
register

PL6D

PL5D

PL4D

PL3D

PL2D

PL1D

PL0D

1

1

1

1

R/W

0095H
1

1

1

1

Input/Output buffer drive register for standby mode
PM7D
PMDR

PORTM
drive
register

0096H

PM2D

R/W

PM1D
R/W

1

1

1

Input/Output buffer drive register for standby mode
PN7D
PNDR

PORTN
drive
register

0097H

PN6D

PN5D

PN4D

PN3D

PN2D

PN1D

PN0D

1

1

1

1

R/W
1

1

1

1

Input/Output buffer drive register for standby mode
PP7D
PPDR

PORTP
drive
register

0098H

PP6D

PP5D

PP4D

PP3D

PP2D

PP1D

1

1

1

R/W
1

1

1

1

Input/Output buffer drive register for standby mode
PR3D
PRDR

PORTR
drive
register

PTDR

PR1D

PR0D

1

1

R/W
0099H

1

1

Input/Output buffer drive register for
standby mode
PT7D

PORTT
drive
register

PR2D

009BH

PT6D

PT5D

PT4D

PT3D

PT2D

PT1D

PT0D

1

1

1

1

R/W
1

1

1

PU7D

PU6D

1

Input/Output buffer drive register for standby mode

PUDR

PORTU
drive
register

009CH

PU5D

PU4D

PU3D

PU2D

PU1D

PU0D

1

1

1

1

PV1D

PV0D

1

1

R/W
1

1

1

1

Input/Output buffer drive register for standby mode
PV7D
PVDR

PORTV
drive
register

009DH

PV6D

PV4D

PV3D

R/W
1

PV2D
R/W

1

1

1

1

Input/Output buffer drive register for standby mode

92CZ26A-687

TMP92CZ26A
(1) I/O ports (11/11)
Symbol

PWDR

Name
PORTW
drive
register

Address

009EH

7

6

5

4

3

2

1

0

PW7D

PW6D

PW5D

PW4D

PW3D

PW2D

PW1D

PW0D

1

1

1

1

R/W
1

1

1

1

Input/Output buffer drive register for standby mode
PX7D
drive
register

PX4D

1

1

R/W

PORTX
PXDR

PX5D

009FH

1

Input/Output buffer drive register
for standby mode
PZ7D

PZDR

PORTZ
drive
register

PZ6D

PZ5D

PZ4D

PZ3D

PZ2D

PZ1D

PZ0D

1

1

1

1

R/W

009AH
1

1

1

1

Input/Output buffer drive register for standby mode

92CZ26A-688

TMP92CZ26A

(2) Interrupt control (1/4)
Symbol

Name

Address

7

6

5

4

3

2

−
INTE0

INT0 enable

00F0H

−

−

−

−

−

−

I0C

I0M2

00D0H

I2C
R
0

0

INT3 & INT4
enable

00D1H

I4C
R
0

0

I2M2

I2M1
R/W
0

0
I4M2

I2M0
0

I1C
R
0

I1M2
0

INT5 & INT6
enable

00D2H

I6C
R
0

I6M2

I4M0
0

I3C
R
0

I3M2
0

I6M0
0

I5C
R
0

I5M2
0

−
INTE7

INTETA01

INTETA23

INTETA45

INTETA67

INTETB0

INT7
enable

INTTA0 &
INTTA1
enable
INTTA2 &
INTTA3
enable

00D3H

00D4H

00D5H

INTTA4 &
INTTA5
enable

00D6H

INTTA6 &
INTTA7
enable

00D7H

INTTB00 &
INTTB01
enable

00D8H

−
−

ITA1C
R
0
ITA3C
R
0
ITA5C
R
0
ITA7C
R
0
ITB01C
R
0

INTES0

INTTB10 &
INTTB11
enable

INTRX0 &
INTTX0
enable

00D9H

00DBH

−

−
−
Always write “0”
INTTA1 (TMRA1)
ITA1M2
ITA1M1
R/W
0
0
INTTA3 (TMRA3)
ITA3M2
ITA3M1
R/W
0
0
INTTA5 (TMRA5)
ITA5M2
ITA5M1
R/W
0
0
INTTA7 (TMRA7)
ITA7M2
ITA7M1
R/W
0
0
INTTB01 (TMRB0)
ITB01M2 ITB01M1
R/W
0
0

−

ITA1M0
0
ITA3M0
0
ITA5M0
0
ITA7M0
0
ITB01M0
0

I7C
R
0

00E0H

ITA0C
R
0
ITA2C
R
0
ITA4C
R
0
ITA6C
R
0
ITB00C
R
0

I7M1
R/W
0
0
INTTA0 (TMRA0)
ITA0M2
ITA0M1
R/W
0
0
INTTA2 (TMRA2)
ITA2M2
ITA2M1
R/W
0
0
INTTA4 (TMRA4)
ITA4M2
ITA4M1
R/W
0
0
INTTA6 (TMRA6)
ITA6M2
ITA6M1
R/W
0
0
INTTB00 (TMRB0)
ITB00M2 ITB00M1
R/W
0
0

00E1H

0
I7M0
0
ITA0M0
0
ITA2M0
0
ITA4M0
0
ITA6M0
0
ITB00M0
0

INTTB10 (TMRB1)

ITB11M1
R/W

ITB11M0

ITB10C
R

ITB10M2

ITB10M1
R/W

ITB10M0

0

0

0

0

0

0

0

0

ITX0C
R

INTTX0
ITX0M2
ITX0M1
R/W
0

ITX0M0

IRX0C
R

0

0

0

INTRX0
IRX0M2
IRX0M1
R/W
0

IADM0C

IADMM2

R

IADMM1

IADMM0

R/W
0

ISPITC
R
0

ISBI0C

ISBIM2

R

0

ISPITM2
0

IRX0M0

0

0

ISBIM1

ISBIM0

INTSBI

0

0

R/W
0

INTSPITX
INTSPI
enable

I5M0

0

ITB11M2

0

INTESPI

I5M1
R/W
0

I7M2

INTADM
INTSBI &
INTADM
enable

I3M0

ITB11C
R

0
INTESBI
ADM

I3M1
R/W
0

0

INT7

INTTB11 (TMRB1)
INTETB1

I1M0

INT5
I6M1
R/W
0

0

I1M1
R/W
0
INT3

I4M1
R/W
0

0

0

INT1

INT6
INTE56

I0M0

0

INT4
INTE34

I0M1
R/W

INT2
INT1 & INT2
enable

0

R

Always write “0”

INTE12

1
INT0

ISPITM1
R/W
0

0

0

ISPIRM1
R/W
0

ISPIRM0

INTSPIRX
ISPITM0

92CZ26A-689

0

ISPIRC
R
0

ISPIRM2
0

0

TMP92CZ26A
(2) Interrupt control (2/4)
Symbol

Name

Address

7

6

5

4

3

2

−
INTEUSB

INTUSB
enable

00E3H

−
−

−

−
−
Always write “0”

−

IUSBC
R
0

−
INTEALM

INTERTC

INTEKEY

INTELCD

INTEI2S01

INTENDFC

INTEP0

INTEAD

INTALM
enable

INTRTC
enable

INTKEY
enable

INTLCD
enable

00E5H

00E8H

00E9H

00EAH

INTI2S0 &
INTI2S1
enable

00EBH

INTRSC &
INTRDY
enable

00ECH

INTP0
enable

00EEH

INTAD &
INTADHP
enable

00EFH

−
−

−
−

−
−

−
−

II2S1C
R
0
IRSCC
R
0
−
−

IADHPC
R
0

−

1

0

IUSBM1
R/W
0

IUSBM0

INTUSB
IUSBM2
0

0

INTALM
−

−
Always write “0”
−
−
−
−
Always write “0”
−
−
−
−
Always write “0”
−
−
−
−
Always write “0”
INTI2S1
II2S1M2
II2S1M1
R/W
0
0
INTRSC
IRSCM2
IRSCM1
R/W
0
0
−
−
−
−
Always write “0”
INTADHP
IADHPM2 IADHPM1
R/W
0
0

−

IALMC
R
0

−

−

−

II2S1M0
0
IRSCM0
0
−

IADHPM0

0

92CZ26A-690

IRC
R
0
IKC
R
0
ILCD1C
R
0
II2S0C
R
0
IRDYC
R
0
IP0C
R
0
IADC
R
0

IALMM2

IALMM1

R/W
0
0
INTRTC
IRM2
IRM1
R/W
0
0
INTKEY
IKM2
IKM1
R/W
0
0
INTLCD
ILCDM2
ILCDM1
R/W
0
0
INTI2S0
II2S0M2
II2S0M1
R/W
0
0
INTRDY
IRDYM2
IRDYM1
R/W
0
0
INTP0
IP0M2
IP0M1
R/W
0
0
INTAD
IADM2
IADM1
R/W
0
0

IALMM0
0
IRM0
0
IKM0
0
ILCDM0
0
II2S0M0
0
IRDYM0
0
IP0M0
0
IADM0
0

TMP92CZ26A

(2) Interrupt control (3/4)
Symbol

Name

7

Address

INTTC0/INTDMA0 &
INTETC01
INTTC1/INTDMA1 00F1H
/INTEDMA01
enable

6

0
INTTC2/INTDMA2 &
INTETC23
INTTC3/INTDMA3 00F2H
/INTEDMA23
enable

4

3

0

0

0

0

0

0

SIMC

IIMC0

SIO
interrupt mode
control

00F4H

0

0

0

0

0

enable

0

INTCLR

ITC6C
R

ITC6M2

ITC6M1
R/W

0

0

0

0

0

0

0

0

I0LE
R/W
0

IR0LE
W
1
0: INTRX0
edge
mode
1: INTRX0
level
mode
−
R/W
0
write “0”

I5EDGE
W
0

I4EDGE
W
0

(Prohibit
RMW)

0

ITC7M0

−
W
0
Always
write “0”

00F8H

0

ITC7M1
R/W

I3EDGE
W
0

I2EDGE
W
0

I1EDGE
W
0

I0EDGE
W
0

INT4
edge

INT3
edge

INT2
edge

INT1
edge

INT0
edge

0: INT0
edge mode

0: Rising

0: Rising

0: Rising

0: Rising

0: Rising

0: Rising

1: Falling

1: Falling

1: Falling

1: Falling

1: Falling

1: Falling

1:INT0
level mode

−

−

−
CLRV7

−

−
CLRV6

ITC6M0

Always

INTWD
−

Always write “0”
Interrupt
clear control

0

ITC7M2

−
W
0
00F5H
Always
(Prohibit write “0”
RMW)

00F7H

0

INTTC6 (DMA6)

−
INTWDT

0

ITC7C
R

00F6H
Interrupt
(Prohibit INT5
input mode control 0
RMW) edge

INTWD

0

0

0

0

0

INTTC7 (DMA7)
INTTC6 & INTTC7
enable

1

INTTC5/INTDMA5
INTTC4/INTDMA4
ITC5C
ITC5M2
ITC5M1
ITC5M0
ITC4C
ITC4M2
ITC4M1
ITC4M0
/IDMA5C /IDMA5M2 /IDMA5M1 /IDMA5M0 /IDMA4C /IDMA4M2 /IDMA4M1 /IDMA4M0
R
R
R/W
R/W
0

INTETC67

2

INTTC3/INTDMA3
INTTC2/INTDMA2
ITC3C
ITC3M2
ITC3M1
ITC3M0
ITC2C
ITC2M2
ITC2M1
ITC2M0
/IDMA3C /IDMA3M2 /IDMA3M1 /IDMA3M0 /IDMA2C /IDMA2M2 /IDMA2M1 /IDMA2M0
R
R
R/W
R/W
0

INTTC4/INTDMA4 &
INTETC45
INTTC5/INTDMA5 00F3H
/INTEDMA45
enable

5

INTTC1/INTDMA1
INTTC0/INTDMA0
ITC1C
ITC1M2
ITC1M1
ITC1M0
ITC0C
ITC0M2
ITC0M1
ITC0M0
/IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0
R
R
R/W
R/W

CLRV5

CLRV4

ITCWD

−

−

R

−

−

−
−

0

−

−

−

CLRV3

CLRV2

CLRV1

CLRV0

0

0

0

0

I7EDGE

I6EDGE

W

W

W
0

0

0

0

Interrupt vector

00FAH

IIMC1

0

Interrupt
input mode control 1 (Prohibit
RMW)

92CZ26A-691

0

INT7
edge

INT6
edge

0: Rising

0: Rising

1: Falling

1: Falling

TMP92CZ26A

(2) Interrupt control (4/4)
Symbol

Name

DMA0V

DMA0
start
vector

DMA1V

DMA1
start
vector

DMA2V

DMA2
start
vector

DMA3V

DMA3
start
vector

DMA4V

DMA4
start
vector

DMA5V

DMA5
start
vector

DMA6V

DMA6
start
vector

DMA7V

DMA7
start
vector

DMAB

DMAR

Address

7

6

0100H

0101H

0103H

0104H

0105H

0106H

0107H

0108H

DMA
request

0109H
(Prohibit
RMW)

4
DMA0V4

1

0

DMA0V3 DMA0V2
R/W
0
0
DMA0 start vector

3

0

0

DMA1V5

DMA1V4

0

0

DMA2V5

DMA2V4

2

DMA0V1

DMA0V0

0

0

DMA1V3 DMA1V2
R/W
0
0
DMA1 start vector

DMA1V1

DMA1V0

0

0

DMA2V3

DMA2V1

DMA2V0

0

0

DMA3V3 DMA3V2
R/W
0
0
0
0
DMA3 start vector
DMA4V5 DMA4V4 DMA4V3 DMA4V2
R/W
0
0
0
0
DMA4 start vector
DMA5V5 DMA5V4 DMA5V3 DMA5V2
R/W
0
0
0
0
DMA5 start vector
DMA6V5 DMA6V4 DMA6V3 DMA6V2
R/W
0
0
0
0
DMA6 start vector
DMA7V5 DMA7V4 DMA7V3 DMA7V2
R/W
0
0
0
0
DMA7 start vector
DBST5
DBST4
DBST3
DBST2
R/W
0
0
0
0
1: DMA request on burst mode

DMA3V1

DMA3V0

0

0

DMA4V1

DMA4V0

0

0

DMA5V1

DMA5V0

0

0

DMA6V1

DMA6V0

0

0

DMA7V1

DMA7V0

0

0

DBST1

DBST0

0

0

DREQ3

DREQ2

DREQ1

0

0

0

DMASEL2

DMASEL1

DMASEL0

DMA2V2

R/W

0102H

DMA burst

5
DMA0V5

0

0

DMA3V5

DMA3V4

DBST7

DBST6

0

0

DREQ7

DREQ6

DREQ5

0

0

0

0
0
DMA2 start vector

DREQ5

DREQ4
R/W

DMASEL5

0
0
1: DMA request in software
DMASEL4

DMASEL3

R/W
DMASEL

Micro
DMA/HDMA
Select

010AH

0
0:Micro
DMA5
1:HDMA5

0

0

0

0: Micro

0: Micro

0: Micro

DMA4

DMA3

DMA2

1:HDMA4 1:HDMA3 1:HDMA2

92CZ26A-692

0
0: Micro

0
0: Micro

DMA1

DMA0

1:HDMA1

1:HDMA0

TMP92CZ26A

(3) Memory controller (1/4)
Symbol

B0CSL

B0CSH

B1CSL

B1CSH

B2CSL

Name

BLOCK0
CS/WAIT
control
register
low

BLOCK0
CS/WAIT
control
register
high

BLOCK1
CS/WAIT
control
register
low

BLOCK1
CS/WAIT
control
register
high

BLOCK2
CS/WAIT
control
register
low

Address

0140H
(Prohibit
RMW)

0141H
(Prohibit
RMW)

0144H
(Prohibit
RMW)

0145H
(Prohibit
RMW)

0148H
(Prohibit
RMW)

7

6

5

B0WW3

B0WW2

B0WW1

0

0

1

4

0
B0WR0

0

1

0

0001: 0 waits
0010: 1 wait
0101: 2 waits
0110: 3 waits
0111: 4 waits
1000: 5 waits
1001: 6 waits
1010: 7 waits
1011: 8 waits
1100: 9 waits
1101: 10 waits
1110: 12 waits
1111: 16 waits
0100: 20 waits
0011: 6 states + WAIT pin input mode
Others: Reserved

0001: 0 waits
0010: 1 wait
0101: 2 waits
0110: 3 waits
0111: 4 waits
1000: 5 waits
1001: 6 waits
1010: 7 waits
1011: 8 waits
1100: 9 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states + WAIT pin input mode
Others: Reserved

B0E
R/W
0
CS select
0: Disable
1: Enable

B0REC

B0OM0
R/W
0
0
0
Dummy
00: ROM/SRAM
cycle
01: Reserved
0:No insert 10: Reserved
1: Insert
11: Reserved

B1WW3

B1WW2

B1WW1

0

0

1

0

Write waits
0001: 0 waits
0010: 1 waits
0101: 2 waits
0110: 3 waits
0111: 4 waits
1000: 5 waits
1001: 6 waits
1010: 7 waits
1011: 8 waits
1100: 9 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states + WAIT pin input mode
Others: Reserved

B1E
R/W
0
CS select
0: Disable
1: Enable

B2WW2

B2WW1

0

0

1

B1WR2

0

0

B0BUS1

B0BUS0

0
0
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B1WR1
B1WR0
1

0

Read waits
0001: 0 waits
0010: 1 waits
0101: 2 waits
0110: 3 waits
0111: 4 waits
1000: 5 waits
1001: 6 waits
1010: 7 waits
1011: 8 waits
1100: 9 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states + WAIT pin input mode
Others: Reserved

B1REC

B2WW3

B0OM1

B1WW0
B1WR3
R/W

B1OM1

B1OM0
R/W
0
0
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM

0
Dummy
cycle
0:No
insert
1: Insert
B2WW0
B2WR3
R/W
0

Write waits
0001: 0 waits
0010: 1 waits
0101: 2 waits
0110: 3 waits
0111: 4 waits
1000: 5 waits
1001: 6 waits
1010: 7 waits
1011: 8 waits
1100: 9 waits
1101: 10 waits
1110: 12 waits
1111: 16 waits
0100: 20 waits
0011: 6 states + WAIT pin input mode

B2WR2

0

0

B1BUS1

B1BUS0

0
0
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B2WR1
B2WR0
1

0

Read waits
0001: 0 waits
0010: 1 waits
0101: 2 waits
0110: 3 waits
0111: 4 waits
1000: 5 waits
1001: 6 waits
1010: 7 waits
1011: 8 waits
1100: 9 waits
1101: 10 waits
1110: 12 waits
1111: 16 waits
0100: 20 waits
0011: 6 states + WAIT pin input mode
Others: Reserved

B2M

B2REC

R/W
0149H
(Prohibit
RMW)

1
B0WR1

Read waits

B2E

B2CSH

2
B0WR2

Write waits

Others: Reserved

BLOCK2
CS/WAIT
control
register
high

3

B0WW0
B0WR3
R/W
0
0

B2OM1

B2OM0

B2BUS1

B2BUS0

R/W

1
0
CS select 0: 16 MB
0: Disable 1: Sets
1: Enable
area

0
Dummy
cycle
0:No
insert
1: Insert

92CZ26A-693

0
0
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM

0
1
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set

TMP92CZ26A
(3) Memory controller (2/4)
Symbol

Name

Address

7

6

5

B3WW3

B3WW2

B3WW1

0

0

1

4

Write waits

B3CSL

B3CSH

BLOCK3
CS/WAIT
control
register
low

BLOCK3
CS/WAIT
control
register
high

0001: 0

waits
waits
waits
waits
1011: 8 waits
1101: 10 waits
1111: 16 waits

014CH 0101: 2
(Prohibit 0111: 4
RMW) 1001: 6

014DH
(Prohibit
RMW)

BEXCSL

0010: 1
0110: 3
1000: 5
1010: 7
1100: 9
1110: 12
0100: 20

0001: 0
0101: 2
0111: 4
1001: 6
1011: 8
1101: 10
1111: 16

waits
waits
waits
waits
waits
waits
waits

BEXCSH

0
B3WR0

0

1

0

waits
waits
waits
waits
waits
waits
waits

0010: 1
0110: 3
1000: 5
1010: 7
1100: 9
1110: 12
0100: 20

waits
waits
waits
waits
waits
waits
waits

0011: 6 states + WAIT pin input mode

Others: Reserved

Others: Reserved

B3E
R/W
0
CS select
0: Disable
1: Enable

B3REC

B3OM1

B3OM0
R/W
0
0
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved

0
Dummy
cycle
0:No
insert
1: Insert
BEXWW3 BEXWW2 BEXWW1 BEXWW0 BEXWR3
R/W
0
0
1
0
0

0001: 0

waits
waits
waits
waits
1011: 8 waits
1101: 10 waits
1111: 16 waits

0158H 0101: 2
(Prohibit 0111: 4
RMW) 1001: 6

0159H
(Prohibit
RMW)

1
B3WR1

0011: 6 states + WAIT pin input mode

B3BUS1

B3BUS0

0
0
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
BEXWR2 BEXWR1 BEXWR0
0

1

0

Read waits
0010: 1
0110: 3
1000: 5
1010: 7
1100: 9
1110: 12
0100: 20

0001: 0
0101: 2
0111: 4
1001: 6
1011: 8
1101: 10
1111: 16

waits
waits
waits
waits
waits
waits
waits

waits
waits
waits
waits
waits
waits
waits

0010: 1
0110: 3
1000: 5
1010: 7
1100: 9
1110: 12
0100: 20

waits
waits
waits
waits
waits
waits
waits

0011: 6 states + WAIT pin input mode

0011: 6 states + WAIT pin input mode

Others: Reserved

Others: Reserved

BEXREC
BLOCK EX
CS/WAIT
control
register
high

2
B3WR2

Read waits

Write waits

BLOCK EX
CS/WAIT
control
register
low

3

B3WW0
B3WR3
R/W
0
0

0
Dummy
cycle
0:No
insert
1: Insert

92CZ26A-694

BEXOM1

BEXOM0
R/W
0
0
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved

BEXBUS1 BEXBUS0
0
0
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set

TMP92CZ26A

(3) Memory controller (3/4)
Symbol

Name

MAMR0

Memory
address
mask
register 0

MSAR0

Memory
start
address
register 0

MAMR1

Memory
address
mask
register 1

MSAR1

Memory
start
address
register 1

MAMR2

Memory
address
mask
register 2

MSAR2

Memory
start
address
register 2

MAMR3

Memory
address
mask
register 3

MSAR3

Memory
start
address
register 3

Address
0142H

0143H

0146H

0147H

014AH

014BH

014EH

014FH

7

6

5

4

3

2

1

0

M0V20

M0V19

M0V18

M0V17

M0V16

M0V15

M0V14-9

M0V8

1

1

1

1

M0S23

M0S22

M0S17

M0S16

1

1

1

1

M1V21

M1V20

MV15-9

M1V8

1

1

1

1

M1S23

M1S22

M1S17

M1S16

1

1

1

1

M2V22

M2V21

M2V16

M2V15

1

1

1

1

M2S23

M2S22

M2S17

M2S16

1

1

1

1

M3V22

M3V21

M3V16

M3V15

1

1

1

1

M3S23

M3S22

M3S17

M3S16

1

1

1

1

R/W
1
1
1
1
0: Compare enable
1: Compare disable
M0S21
M0S20
M0S19
M0S18
R/W
1
1
1
1
Set start address A23 to A16
M1V19
M1V18
M1V17
M1V16
R/W
1
1
1
1
0: Compare enable
1: Compare disable
M1S21
M1S20
M1S19
M1S18
R/W
1
1
1
1
Set start address A23 to A16
M2V20
M2V19
M2V18
M2V17
R/W
1
1
1
1
0: Compare enable
1: Compare disable
M2S21
M2S20
M2S19
M2S18
R/W
1
1
1
1
Set start address A23 to A16
M3V20
M3V19
M3V18
M3V17
R/W
1
1
1
1
0: Compare enable
1: Compare disable
M3S21
M3S20
M3S19
M3S18
R/W
1
1
1
1
Set start address A23 to A16

92CZ26A-695

TMP92CZ26A
(3) Memory controller (4/4)
Symbol

PMEMCR

CSTMGC

Name
Page
ROM
control
register

Adjust for
Timing of
control
signal

Address

7

6

5

0166H

4

3

2

1

0

OPGE
R/W
0
ROM
page
access
0: Disable
1: Enable

OPWR1

OPWR0

PR1

PR0

WRTMGCRR

00: 1 CLK (n-1-1-1 mode)
01: 2 CLK (n-2-2-2 mode)
10: 3 CLK (n-3-3-3 mode)
11: Reserved

TACSEL1 TACSEL0
R/W
0
0
Select area to
change timing
00:CS0
01:CS1
10:CS2
11:CS3

0168H

TCWSEL1 TCWSEL0
Adjust for
Timing of
control
signal

0
0
Wait number on page

0
0
Select area to
change timing
00:CS0
01:CS1
10:CS2
11:CS3

0169H

B1TCRS1

B1TCRS0

B1TCRH1

TAC1

TAC0
R/W

0

0

Select delay time(TAC)
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:Reserved

TCWS1
0

TCWS0
R/W
0

Select delay time(TCWS)
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS

B1TCRH0

1
0
Byte number in a page
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes

B0TCRS1

B0TCRS0

TCWH1

TCWH0

0

0

Select delay time(TCWH)
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS
B0TCRH1

B0TCRH0

0

0

R/W
RDTMGCR0

Adjust for
Timing of
control
signal

0
016AH

0

0

0

0

0

Select delay time(TCRS)
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS

Select delay time(TCRH)
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS

Select delay time(TCRS)
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS

Select delay time(TCRH)
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS

B3TCRS1

B3TCRH1

B2TCRS1

B2TCRH1

B3TCRS0

B3TCRH0

B2TCRS0

B2TCRH0

R/W
RDTMGCR1

Adjust for
Timing of
control
signal

0
016BH

0

0

Select delay time(TCRS)
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS

0

Select delay time(TCRH)
00:0 x× fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS

0

0

Select delay time(TCRS)
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS

CSDIS

BROMCR

Boot Rom
Control
register

RAMCR

RAM
Control
register

0

ROMLESS
R/W
1
0/1
Nand-Flash Boot
Area CS
ROM
Output
0: Use
0:enable 1: No use
1:disable

016CH

0

Select delay time(TCRH)
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS

VACE
1/0
Vector
address
0: Disable
1: Enable
−
R/W

016DH

1
Always
write “1”

92CZ26A-696

TMP92CZ26A

(4) TSI
Symbol

TSICR0

Name

TSI
control
register0

Address

01F0H

7

6

5

4

3

2

1

0

TSI7

INGE

PTST

TWIEN

PYEN

PXEN

MYEN

MXEN

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0: Disable Input gate Detection
1: Enable control of condition
Port
0: no
96,97
touch
0: Enable 1: touch

INT4
interrupt
control

0

SPY

SPX

SMY

SMX

0 : OFF

0 : OFF

0 : OFF

0 : OFF

1 : ON

1 : ON

1 : ON

1 : ON

0: Disable
1: Enable

1: Disable
DBC7

DB1024

DB256

DB64

DB8

DB4

DB2

DB1

R/W
TSICR1

TSI
control
register1

01F1H

0

0

0

0

0

0

0

0

0: Disable

1024

256

64

8

4

2

1

1: Enable

De-bounce time is set by “(N*64-16) / fSYS”-formula.
“N” is sum of number which is set to “1” in bit6 to bit 0.

92CZ26A-697

TMP92CZ26A

(5) SDRAM controller
Symbol

Name

Address

7

6

SRDS

−

1

0

5

4

SMUXW1 SMUXW0

3

2

1

SPRE

0
SMAC

R/W

SDACR

SDRAM
access
control
register

0250H

Read
data shift
function

R/W

0

Always
write “0”

0

Address multiplex
type

0

0
SDRAM

Read/Write
commands

controller

00: Type A (A9- )

0: Disable

01: Type B (A10- )

1: Enable

10: Type C (A11- )
11: Reserved

0: Without
auto precharge

0: Disable
1: Enable

1: With auto
precharge

SDCISR

SDRAM
Command
Interval
Setting
Register

STMRD

STWR

STRP

STRCD

STRC2

STRC1

STRC0

1

1

1

TMRD

TWR

TRP

1

1

0

0

TRCD

TRC
000: 1 CLK

100: 5 CLK

0: 1 CLK

0: 1 CLK

0: 1 CLK

0: 1 CLK

001: 2 CLK

101: 6 CLK

1: 2 CLK

1: 2 CLK

1: 2 CLK

1: 2 CLK

010: 3 CLK

110: 7 CLK

R/W

0251H

011: 4 CLK

SDRCR

SDRAM
refresh
control
register

0252H

−
R/W
0
Always
write “0”

SSAE
1
Self

SRS2

SRS1
R/W
0
0
Refresh interval

111: 8 CLK
SRS0
0

Refresh
auto

000: 47 states

100: 468 states

001: 78 states

101: 624 states

exit
function

010: 156 states 110: 936 states
011: 312 states

SRC
0
Auto
Refresh
0:Disable

111: 1248 states 1:Enable

0:Disable
1:Enable
SCMM2

SCMM1
R/W
0
0
Command issue

SCMM0
0

000: Don’t care
001: Initialization sequence
SDCMM

SDRAM
command
register

a. Precharge All command

0253H

b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
SDBL5

SDBLS

SDRAM
HDRAM
burst length
register

SDBL4

0
0254H

For
HDMA5

0
For
HDMA4

SDBL3
0
For
HDMA3

HDMA burst length
0:1 Word Read / Single Write
1:Full Page Read / Burst Write

92CZ26A-698

SDBL2
0
For
HDMA2

SDBL1
0
For
HDMA1

SDBL0
0
For
HDMA0

TMP92CZ26A
(6) LCD controller (1/6)
Symbol

Name

Address

7

6

RAMTYPE1 RAMTYPE0

0
Display RAM

LCD
MODE0

LCD
mode0
register

0

00: Internal RAM
0280H

01: External SRAM
10: SDRAM
11: Reserved

LDC2

5

4

3

2

1

0

SCPW1

SCPW0

MODE3

MODE2

MODE1

MODE0

0

0

R/W
1
1
0
0
LD bus transfer speed Mode setting
SCPW2= 0
0000 : Reserved
00: 2-clock
0001 : SR (mono)
01: 4-clock
0010 : SR (4Gray)
10: 8-clock
0011 : Reserved
11: 16-clock
SCPW2= 1
00: 6-clock
01: 12-clock
10: 24-clock
11: 48-clock

LDC1

LDC0

1000 : Reserved
1001 : Reserved
1010 : TFT (256 color)
1011 : TFT (4096 color)

0100 : SR (16Gray)

1100 : TFT (64k color)

0101 : SR (64Gray)

1101 : TFT256k,16M
(color)
1110 : Reserved

0110 : STN (256 color)
0111 : STN
(4096 color)
LDINV

AUTOINV

1111 : Reserved

INTMODE

FREDGE

SCPW2

0

W
0

W
0

R/W
0
LCD
MODE1

LCD
mode1
register

0281H

0

0

Data rotation function

0
LD bus

0
Auto bus

(Supported for 64K-color: 16bps only)

Inversion

inversion

001: Horizontal flip 101: Reserved
110: Reserved

010: Vertical flip

FR edge

0:LLOAD

1:LHSYNC

0: Normal

1: enable

1: Inversion

back edge
(Valid only 1:LVSYNC
for TFT)

111: Reserved

LD bus
transfer
speed

0: LHSYNC
front edge

0: Disable

100: 90-degree

000: Normal

Interrupt
selection

0: normal
1: 1/3

011: Horizontal & vertical flip

LCDDVM0

LCDDVM1

LCD
divide
frame0
register
LCD
divide
frame1
register

FMP3
0283H

FMP2

FMP1

FMP0

FML3

0

0

0

0

0

LCP0 DVM (bits 3-0)
FMP7
0288H

FML2

FML1

FML0

0

0

0

R/W

FMP6

LHSYNC DVM (bits 3-0)

FMP5

FMP4

FML7

FML6

FML5

FML4

0

0

0

R/W
0

0

0

0

0

LCP0 DVM (bits 7-4)
COM3

COM2

LHSYNC DVM (bit 7-4)

COM1

COM0

SEG3

SEG2

R/W
0

LCDSIZE

LCD size
register

0284H

0

PIPE

LCD
control0
register

0285H

0

1000 : 320
1001 : 480
1010 : Reserved
1011 : Reserved
1100 : Reserved
1101 : Reserved
1110 : Reserved
1111 : Reserved

ALL0

0

LCDCTL0

0

Common setting
0000 : reserved
0001 : 64
0010 : 96
0011 : 120
0100 : 128
0101 : 160
0110 : 200
0111 : 240

0

SEG1

SEG0

0

0

R/W

FRMON
R/W
0

PIP
function

Segment

FR divide

Data

setting

0:Disable

0:Normal

1:Enable

1: Always 0: Disable
output “0” 1: Enable

–
0
Always
write “0”

0
0
Segment setting
0000 : Reserved
0001 : 64
0010 : 128
0011 : 160
0100 : 240
0101 : 320
0110 : 480
0111 : 640
DLS
0

1000 : Reserved
1001 : Reserved
1010 : Reserved
1011 : Reserved
1100 : Reserved
1101 : Reserved
1110 : Reserved
1111 : Reserved
LCP0OC
R/W
0

0
LCDC

FR signal

LCP0

LCP0/Line

0: Always
output

operation

1: At valid
data only

0: Stop

selection
0:Line
1:LCP0

LLOAD
width
0: At setting
in register
1: At valid
data only

92CZ26A-699

START

1: Start

TMP92CZ26A

(6) LCD controller (2/6)
Symbol

LCDCTL1

Name

LCD
control1
register

Address

0286H

6

5

LCP0P
R/W
1
LCP0

7

LHSP
R/W
0
LHSYNC

LVSP
R/W
1
LVSYNC

LLDP
R/W
0
LLOAD

4

3

2

1

0

LVSW1
R/W
0

LVSW0
R/W
0

LVSYNC

phase

phase

phase

phase

enable time control

0:Rising

0:Rising

0:Rising

0:Rising

00: 1 clock of LHSYNC

1:Falling

1: Falling

1: Falling

1: Falling

01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved

LGOE2P

LCDCTL2

LCDHSP

LCD
control2
register

LHSYNC
Pulse
register

0287H

0
LGOE2

LGOE1P
R/W
0
LGOE1

0
LGOE0

phase

phase

phase

0: Rising

0: Rising

0: Rising

1: Falling

1: Falling

1: Falling

LH7

LH6

LGOE0P

LH5

LH4

LH3

LH2

LH1

LH0

0

0

0

0

LH11

LH10

LH9

LH8

0

0

0

0

LVP3

LVP2

LVP1

LVP0

0

0

0

0

LVP9

LVP8

W

028AH

0

0

0

0

LHSYNC period (bits 7-0)
LH15
LCDHSP

LHSYNC
Pulse
register

LH14

LH13

LH12
W

028BH

0

0

0

0

LHSYNC period (bits 15-8)
LVP7
LCDVSP

LVSYNC
Pulse
register

LVP6

LVP5

LVP4
W

028CH

0

0

0

0

LVSYNC period (bits 7-0)

LCDVSP

LVSYNC
Pulse
register

W
028DH

0

0

LVSYNC period
(bits 9-8)
PLV6

LCDPRVSP

LVSYNC
Pre Pulse
register

PLV5

PLV4

PLV3

PLV2

PLV1

PLV0

0

0

0

HSD2

HSD1

HSD0

0

0

0

LDD2

LDD1

LDD0

0

0

0

W

028EH

0

0

0

0

Front dummy LVSYNC (bits 6-0)

LCDHSDLY

LHSYNC
Delay
register

HSD6

HSD5

HSD4

0

0

0

HSD3
W

028FH

0

LHSYNC delay (bits 6-0)
PDT

LDD6

LDD5

LDD4

0

0

0

R/W
0
LCDLDDLY

LLOAD
Delay
register

LDD3
W
0

Data output

0290H

timing
0: Sync with

LLOAD delay (bits 6-0)

LLOAD
1: 1 clock
later than
LLOAD

92CZ26A-700

TMP92CZ26A

(6) LCD controller (3/6)
Symbol
LCDO0DLY

LCDO1DLY

LCDO2DLY

LCDHSW

Name
LGOE0
Delay
register

LGOE1
Delay
register

LGOE2
Delay
register

LHSYNC
Width

Address

7

6

5

4

3

2

1

0

OE0D6

OE0D5

OE0D4

OE0D3

OE0D2

OE0D1

OE0D0

0

0

0

0

0

OE1D6

OE1D5

OE1D4

OE1D1

OE1D0

0

0

OE2D1

OE2D0

0

0

W

0291H

0
0
OE0 delay (bits 6-0)
OE1D3

0292H
0

0

0

0
0
OE1 delay (bits 6-0)

OE2D6

OE2D5

OE2D4

OE2D3

OE2D2

W

0293H
0

0

0

0
0
OE2 delay (bits 6-0)

HSW7

HSW6

HSW5

HSW4

0

0

0

0

HSW3

HSW2

HSW1

HSW0

0

0

0

0

LDW3

LDW2

LDW1

LDW0

0

0

0

0

O0W3

O0W2

O0W1

O0W0

0

0

0

0

O1W3

O1W2

O1W1

O1W0

0

0

0

0

O2W3

O2W2

O2W1

O2W0

0

0

0

0

LDW9

LDW8

HSW8

0

0

W

0294H

register

OE1D2

W

Setting bit7-0 for LHSYNC Width

LCDLDW

LLOAD
width
register

LDW7

LDW6

LDW5

LDW4

0

0

0

0

O0W7

O0W6

O0W5

W

0295H

LHSYNC width (bits 7-0)

LCDHO0W

LGOE0
width
register

O0W4
W

0296H
0

0

0

0

LLOAD width (bits 7-0)

LCDHO1W

LGOE1
width
register

0297H

O1W7

O1W6

O1W5

O1W4

0

0

0

0

W
LGOE1 width (bits 7-0)

LCDHO2W

LGOE2
width
register

0298H

O2W7

O2W6

O2W5

O2W4

0

0

0

0

W
LGOE2 width (bits 7-0)

LCDHWB8

Bit8,9
for signal
width
register

O2W9

O2W8

O1W9

O1W8

0

0

0

0

O0W8
W

0299H

LGOE2 width

LGOE1 width

(bits 9-8)

(bits 9-8)

0
LGOE0
width
(bit 8)

92CZ26A-701

LLOAD width (bits 9-8)

0
LHSYNC
width
(bit 8)

TMP92CZ26A
(6) LCD controller (4/6)
Symbol

Name

LSAML

Start
address
register
LCD main-L

LSAMM

Start
address
register
LCD main-M

LSAMH

Start
address
register
LCD main-H

LSASL

Start
address
register
LCD sub-L

LSASM

Start
address
register
LCD sub -M

LSASH

Start
address
register
LCD sub -H

LSAHX

Hot point
register
LCD sub -X

LSAHX

Hot point
register
LCD sub -X

LSAHY

Hot point
register
LCD sub -Y

Address
02A0H

02A1H

02A2H

02A4H

02A5H

02A6H

02A8H

7

6

5

LMSA7

LMSA6

LMSA5

4

0

0

LMSA15

LMSA14

0

0

LMSA23

LMSA22

0

1

LSSA7

LSSA6

0

0

LSSA15

LSSA14

0

0

LSSA23

LSSA22

0

1

SAHX7

SAHX6

0

0

3

2

LMSA4
LMSA3
LMSA2
R/W
0
0
0
0
LCD main area start address (A7-A1)
LMSA13
LMSA12
LMSA11
LMSA10
R/W
0
0
0
0
LCD main area start address (A15-A8)
LMSA21
LMSA20
LMSA19
LMSA18
R/W
0
0
0
0
LCD main area start address (A23-A16)
LSSA5
LSSA4
LSSA3
LSSA2
R/W
0
0
0
0
LCD sub area start address (A7-A1)
LSSA13
LSSA12
LSSA11
LSSA10
R/W
0
0
0
0
LCD sub area start address (A15-A8)
LSSA21
LSSA20
LSSA19
LSSA18
R/W
0
0
0
0
LCD sub area start address (A23-A16)
SAHX5
SAHX4
SAHX3
SAHX2
R/W
0
0
0
0
LCD sub area HOT point (7-0)

1

0

LMSA1
0
LMA9

LMSA8

0

0

LMSA17

LMSA16

0

0

LSSA1
0
LSSA9

LSSA8

0

0

LSSA17

LSSA16

0

0

SAHX1

SAHX0

0

0

SAHX9

LSAHY

Hot point
register
LCD sub -Y

LSASS

Segment
size
register
LCD sub

LSASS

Segment
size
register
LCD sub

LSACS

Common
size
register
LCD sub

LSACS

Common
size
register
LCD sub

SAHX8
R/W

02A9H

SAHY7
02AAH

SAHY6

SAHY5

SAHY4

SAHY3

SAHY2

0
0
LCD sub area HOT
point (9-8)
SAHY1
SAHY0

R/W
0

0

0

0
0
LCD sub area HOT point (7-0)

0

0

0

SAS1

SAHY8
R/W
0
LCD sub
area HOT
point (9-8)
SAS0

0

0

02ABH

SAS7
02ACH

SAS6

SAS5

SAS4

SAS3

SAS2

R/W
0

0

0

0
0
0
LCD sub area segment size (7-0)

SAS9

SAS8
R/W

02ADH

SAC7
02AEH

SAC6

SAC5

SAC4

SAC3

SAC2

0
0
LCD sub area
segment size (9-8)
SAC1
SAC0

R/W
0

0

0

0
0
0
LCD sub area common size (7-0)

0

0
SAC8
R/W
0
LCD sub
area
common
size (8)

02AFH

92CZ26A-702

TMP92CZ26A
(7) PMC
Symbol Name

Address
02A0H

PMCCTL

PMC
Control
Register

2

1

0

PCM_ON

7

6

5

4

3

−

WUTM1

WUTM0

R/W

W

R/W

R/W

After system
reset

0

0

0

0

After Hot
reset

Data
retained

−

Data
retained

Data
retained

Power
Cut Mode

Always
write “0”

0: Disable

Always
read as
“0”

Warm-up time
00: 29 (15.625 ms)
01: 210 (31.25 ms)

1: Enable

92CZ26A-703

10: 211 (62.5 ms)
11: 212 (125 ms)

TMP92CZ26A
(8) USB controller (1/6)
Symbol

Name

Address

Descriptor
RAM 0
register

0500H

Descriptor RAM1

Descriptor
RAM 1
register

0501H

Descriptor RAM2

Descriptor
RAM 2
register

Descriptor RAM3

Descriptor
RAM 3
register

0503H

:
:

:
:

:
:

Descriptor RAM381

Descriptor
RAM 381
register

067DH

Descriptor RAM0

Descriptor
Descriptor RAM382 RAM 382
register

Descriptor RAM383

Endpoint0

Endpoint1

Endpoint2

Endpoint3

Descriptor
RAM 383
register
Endpoint 0
register
Endpoint 1
register

6

5

4

3

2

1

0

D6

D5

D4

D3

D2

D1

D0

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

D7

D6

D5

D4

D3

D2

D1

D0

R/W

R/W
Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

D7

D6

D5

D4

D3

D2

D1

D0

0502H

R/W
Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

D7

D6

D5

D4

D3

D2

D1

D0

Undefined

Undefined

Undefined

Undefined

D3

D2

D1

D0

R/W
Undefined

Undefined

Undefined

Undefined

:
:
D7

D6

D5

D4
R/W

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

D7

D6

D5

D4

D3

D2

D1

D0

067EH

R/W
Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

D7

D6

D5

D4

D3

D2

D1

D0

Undefined

Undefined

Undefined

Undefined

067FH

R/W
Undefined

Undefined

Undefined

Undefined

EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0

R/W

0780H
Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DATA1 EP1_DATA0

R/W

0781H
Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

EP2_DATA7 EP2_DATA6 EP2_DATA5 EP2_DATA4 EP2_DATA3 EP2_DATA2 EP2_DATA1 EP2_DATA0

Endpoint 2
register

0782H

Endpoint 3
register

0783H

R/W
Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0

R/W
Undefined

EP1_MODE

Endpoint 1
mode
register

0789H

EP2_MODE

Endpoint 2
mode
register

078AH

Endpoint 3
mode
register

078BH

EP3_MODE

7
D7

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Payload[2] Payload[1] Payload[0] Mode[1]
R/W
0
0
0
0
Payload[2] Payload[1] Payload[0] Mode[1]
R/W
0
0
0
0
Payload[2] Payload[1] Payload[0] Mode[1]

Undefined

Mode[0]

Direction

0
Mode[0]

0
Direction

0
Mode[0]

0
Direction

0

0

R/W
0

92CZ26A-704

0

0

0

TMP92CZ26A
(8) USB controller (2/6)
Symbol
EP0_STATUS

EP1_STATUS

EP2_STATUS

EP3_STATUS

EP0_SIZE_L_A

EP1_SIZE_L_A

EP2_SIZE_L_A

EP3_SIZE_L_A

EP1_SIZE_L_B

EP2_SIZE_L_B

EP3_SIZE_L_B

EP1_SIZE_H_A

EP2_SIZE_H_A

EP3_SIZE_H_A

Name
Endpoint 0
status
register
Endpoint 1
status
register
Endpoint 2
status
register
Endpoint 3
status
register
Endpoint 0
size
register
Low A
Endpoint 0
size
register
Low A
Endpoint 2
size
register
Low A
Endpoint 3
size
register
Low A
Endpoint 1
size
register
Low B
Endpoint 2
size
register
Low B
Endpoint 3
size
register
Low B
Endpoint 1
size
register
High A
Endpoint 2
size
register
High A
Endpoint 3
size
register
HighA

Address

7

6

5

4

3

2

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

0

0

1

1

1

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

0

0

1

1

1

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

0

0

1

1

1

TOGGLE

SUSPEND

STATUS[2]

STATUS[1]

STATUS[0]

1

0

FIFO_DISABLE STAGE_ERR

R

0790H

0791H

0

0

FIFO_DISABLE STAGE_ERR

R

0792H

0

0

FIFO_DISABLE STAGE_ERR

R

0793H

0

0

FIFO_DISABLE STAGE_ERR

R
0

0

1

1

1

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

1

0

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

DATASIZE3

DATASIZE2

DATASIZE1

DATASIZE0

1

0

0

0

DATASIZE9

DATASIZE8

DATASIZE7

R

0798H

R

0799H
1

0

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

R

079AH
1

0

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

R

079BH
1

0

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

R

07A1H
0

0

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

R

07A2H
0

0

0

0

PKT_ACTIVE

DATASIZE6

DATASIZE5

DATASIZE4

R

07A3H
0

0

0

0

R

07A9H
0

0

0

DATASIZE9

DATASIZE8

DATASIZE7

0

R
0

0

DATASIZE9

DATASIZE8

DATASIZE7

0

R
0

0

07AAH

07ABH

92CZ26A-705

TMP92CZ26A
(8) USB controller (3/6)
Symbol

Name

Endpoint 1
size
EP1_SIZE_H_B
register
High B
Endpoint 2
size
EP2_SIZE_H_B
register
High B
Endpoint 0
size
EP3_SIZE_H_B
register
High B
bmRequestType

bRequest

wValue_L

wValue_H

wIndex_L

wIndex_H

wLength_L

wLength_H

bmRequestType
register

bRequest
register
wValue
register
Low
wValue
register
High
wIndex
register
Low

Address

6

5

4

3

2

1

0

DATASIZE9

DATASIZE8

DATASIZE7

R

07B1H
0

0

0

DATASIZE9

DATASIZE8

DATASIZE7

R

07B2H
0

0

0

DATASIZE9

DATASIZE8

DATASIZE7

R

07B3H

DIRECTION

REQ_TYPE1

REQ_TYPE0

RECIPIENT4

RECIPIENT2

RECIPIENT1

RECIPIENT0

0

0

0

0

0

0

0

REQUEST6

REQUEST5

REQUEST4

REQUEST3

REQUEST2

REQUEST1

REQUEST0

0

0

0

0

0

0

0

0

VALUE_L7

VALUE_L6

VALUE_L5

VALUE_L4

VALUE_L3

VALUE_L2

VALUE_L1

VALUE_L0

0

0

0

0

0

0

0

0

VALUE_H7

VALUE_H6

VALUE_H5

VALUE_H4

VALUE_H3

VALUE_H2

VALUE_H1

VALUE_H0

0

0

0

0

0

0

0

0

INDEX_L7

INDEX_L6

INDEX_L5

INDEX_L4

INDEX_L3

INDEX_L2

INDEX_L1

INDEX_L0

R

R

R

07C3H

R

07C4H

07C6H

0

0

07C2H

wLength
register
Low

0

REQUEST7

07C1H

07C5H

RECIPIENT3

0

R

07C0H

wIndex
register
High

wLength
register
High

7

0

0

0

0

0

0

0

0

INDEX_H7

INDEX_H6

INDEX_H5

INDEX_H4

INDEX_H3

INDEX_H2

INDEX_H1

INDEX_H0

0

0

0

0

0

0

0

0

LENGTH_L7

LENGTH_L6

LENGTH_L5

LENGTH_L4

LENGTH_L3

LENGTH_L2

LENGTH_L1

LENGTH_L0

R

R
0

0

0

0

0

0

0

0

LENGTH_H7

LENGTH_H6

LENGTH_H5

LENGTH_H4

LENGTH_H3

LENGTH_H2

LENGTH_H1

LENGTH_H0

0

0

0

0

0

0

0

0

R

07C7H

92CZ26A-706

TMP92CZ26A

(8) USB controller (4/6)
Symbol
SetupReceived

Current_Config

Standard Request

Name
SetupReceived register

Current_
Config
register

Address

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

07C8H

W

REMOTEWAKEUP

07C9H

ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0]

R

07CAH

Request
register

07CBH

0

0

0

0

0

0

S_INTERFACE

G_INTERFACE

S_CONFIG

G_CONFIG

G_DESCRIPT

S_FEATURE

C_FEATURE

G_STATUS

0

0

0

0

0

0

0

0

VENDOR

CLASS

ExSTANDARD

STANDARD

0

R

SOFT_RESET G_PORT_STS G_DEVICE_ID

Request

R

EP3_DSET_B

DATASET1

DATASET2

USB_STATE

DATASET 1
register

DATASET 2
register

USB state
register

EOP
register

EPx_SINGLE1

EPx_BCS1

INT_Control

Command
register
Endpoint 1
single
register

0

0

0

EP2_DSET_A

EP1_DSET_B

EP1_DSET_A

0

0

0

0

0

0

EP7_DSET_B

EP7_DSET_A

EP6_DSET_B

EP6_DSET_A

EP5_DSET_B

EP5_DSET_A

0

0

0

0

0

EP6_EOPB

EP5_EOPB

EP4_EOPB

0

0

Addressed

Default

R

0

0

1

EP3_EOPB

EP2_EOPB

EP1_EOPB

EP0_EOPB

1

1

1

EP[2]

EP[1]

EP[0]

1

1

1

1

0

0

0

Command[3] Command[2] Command[1] Command[0]

W
EP3_SELECT

0

EP2_SELECT EP1_SELECT

0
EP3_SELECT

0

0

EP2_SELECT EP1_SELECT

0

0

0

R/W
0

0

0

EP3_BCS

EP2_BCS

EP1_BCS

R/W
0

0

EP3_SINGLE EP2_SINGLE EP1_SINGLE

R/W

07D1H

07D6H

0

W

07D0H

Interrupt
control
register

EP4_DSET_A

Configured

R/W

07CFH

07D3H

0
EP4_DSET_B

R

07CEH

Endpoint 1
BCS
register

0
EP0_DSET_A

R

07CDH

R/W
0

0

0

0
Status_nak

R/W
0
S_Interface

Standard
Standard Request Request
Mode
mode
register

07D8H

Request
mode
register

07D9H

Request Mode

0
EP2_DSET_B

R

1
COMMAND

0
EP3_DSET_A

07CCH

EP7_EOPB
EOP

0
CONFIG[0]

R

0

StandardRequest
register

0
CONFIG[1]

G_Interface

S_Config

G_Config

G_Descript

S_Feature

C_Feature

G_Status

0

0

0

0

R/W
0

0

0

0

Soft_Reset

G_Port_Sts

G_DeviceId

R/W
0

0

92CZ26A-707

0

TMP92CZ26A

(8) USB controller (5/6)
Symbol
Port Status

FRAME_L

FRAME_H

Name
Port
status
register
Frame
register
Low
Frame
register H

ADDRESS

Address
register

USBREADY

USB
ready
register

Address

7

6

5

4

3

2

1

0

Reserved7

Reserved6

PaperError

Select

NotError

Reserved2

Reserved1

Reserved0

W

07E0H
0

0

0

1

1

0

0

0

−

T[6]

T[5]

T[4]

T[3]

T[2]

T[1]

T[0]

0

0

07E1H

R
0

0

0

0

T[10]

T[9]

T[8]

T[7]

CREATE

0

0

0

0

0

1

0

A6

A5

A4

A2

A1

A0

0

0

A3

07E3H

R
0

0

0

R/W

07E6H

0
S_D_STALL

W

07E8H

0
INT_SUS

(Prohibit
RMW)

INT_RESUME INT_CLKSTOP

0

0

0

0

0

When read 0: Not generate interrupt When write
EP1_Empty_A

EP1_FULL_B

0

0: Clear flag
1: −

EP1_Empty_B

EP2_FULL_A

EP2_Empty_A

EP2_FULL_B

EP2_Empty_B

0

0

0

R/W

07F1H
(Prohibit
RMW)

INT_CLKON

R/W

07F0H

EP1_FULL_A

0

0

0

0

0

When read 0: Not generate interrupt When write 0: Clear flag
1: −

1: Generate interrupt
EP3_FULL_A

EP3_Empty_A

0

0

EP3_FULL_B

EP3_Empty_B

R/W
USB
interrupt
USBINTFR3
flag
register 3

07F2H
(Prohibit
RMW)

When read

0

0

0:Not generate interrupt
1:Generate interrupt

When write

0: Clear flag
1: −

INT_SETUP

USB
interrupt
USBINTFR4
flag
register 4

0
USBREADY

1: Generate interrupt
USB
interrupt
USBINTFR2
flag
register 2

FRAME_STS1 FRAME_STS0

R

INT_URST_STR INT_URST_END

USB
interrupt
USBINTFR1
flag
register 1

0

R

07E2H

0

SetSet Descriptor Descriptor
STALL
stall
register

0

INT_EP0

INT_STAS

INT_STASN

(Prohibit
RMW)

INT_EP1N

INT_EP2N

INT_EP3N

0

0

R/W

07F3H
0

0

0

0

When read 0: Not generate interrupt
1: Generate interrupt

92CZ26A-708

0
When write

0: Clear flag
1: −

TMP92CZ26A

(8) USB controller (6/6)
Symbol

Name

USB
interrupt
USBINTMR1
mask
register 1
USB
interrupt
USBINTMR2
mask
register 2

Address

7

6

5

MSK_URST_STR MSK_URST_END

07F4H

4

MSK_SUS

3

MSK_RESUME MSK_CLKSTOP

2

1

0

MSK_CLKON

R/W
1

1

1

1

1

1

EP2_MSK_FA

EP2_MSK_EA

EP2_MSK_FB

EP2_MSK_EB

1

1

1

1

MSK_EP1N

MSK_EP2N

MSK_EP3N

1

1

1

0: Be not masked 1: Be masked

07F5H

EP1_MSK_FA

EP1_MSK_EA

EP1_MSK_FB

EP1_MSK_EB

1

1

1

1

R/W
0: Be not masked 1: Be masked
EP3_MSK_FA

EP3_MSK_EA

R/W
USB
interrupt
USBINTMR3
mask
register 3

USB
interrupt
USBINTMR4
mask
register 4

1
07F6H

1

0: Be not masked
1: Be masked

MSK_SETUP

MSK_EP0

MSK_STAS

MSK_STASN

R/W

07F7H
1

1

1

1

0: Be not masked 1: Be masked
TRNS_USE

WAKEUP

SPEED

USBCR1

USB
control
register 1

07F8H

0
Transceiver

USBCLKE

R/W

R/W

1

0
Wake up

0:disable

0: −

1:enble

1:Start

92CZ26A-709

0

TMP92CZ26A
(9)
Symbol

SPIC (1/2)
Name

Address

0820H
(Prohibit
RMW)

SPIMD

SPI Mode
Setting
register

7

6

SWRST

XEN

W

R/W

0

0

Software
reset
0: don’t
care
1: Reset
LOOPBACK

5

4

3

2

SYSCK
0: disable
1: enable

MSB1ST

0
1
0821H
LOOPBACK Start bit for
(Prohibit
Test mode Transmit /
RMW)

CEN

Receive
0:LSB
1:MSB

SPCS_B

0

R/W
1

0

0

Select Baud Rate
000:Reserved 100: fSYS/8
001: fSYS/2
101: fSYS/16
010: fSYS/3
110: fSYS/64
111: fSYS/256
011: fSYS/4

DOSTAT

TCPOL

RCPOL

R/W

0:disbale
1:enable

1

CLKSEL2 CLKSEL1 CLKSEL0

TDINV

RDINV

R/W
1

0

0

0

SPDO pin
state
(no transmit)
0:fixed to ”0”
1:fixed to ”1”

Synchronous
clock edge
during
transmitting
0: fall
1: rise

Synchronou
s clock edge
during
receiving
0: fall
1: rise

Invert data
During
transmitting
0: disable
1: enable

TXE

FDPXE

RXMOD

UNIT16

TXMOD

0
Invert data
During
receiving
0: disable
1: enable

RXE

R/W
0
0822H

SPICT

SPI
Control
register

1

communica SPCS pin
tion
0: output
control
“0”
0: disable
1: enable
1: output

0

0

Data length
0: 8bit
1: 16bit

Transmit
mode
0: UNIT
1:
Sequential

0
Transmit
control
0: disable
1: enable

0

0

Alignment
in
Full duplex
0: disable
1: enable

Receive
Mode
0: UNIT
1:
Sequential

0
Receive
control
0: disable
1: enable

“1”
CRC16_7_B CRCRX_TX_B CRCRESET_B

R/W

0823H

0

0

CRC select
0: CRC7
1: CRC16

CRC data
0: Transmit
1: receive

0
CRC
calculate
register
0:Reset
1:Release
Reset

TEMP

TEND

R
1
Transmit
FIFO
Status

0824H
SPIST

SPI
Status
register

REND
R

0: no space
1: having
space

1

0

Transmit
Status
0: during
transmission
or having
transmission
data
1: finish

Receive
Status
0: during
receiving
or not having
receiving data
1: finish or not
having space

TENDIE

RENDIE

0825H

TEMPIE

RFULIE

R/W
0

082CH
SPIIE

TEMP
interrupt
0:enable
1:disable

SPI
Interrupt
enable
register
082DH

92CZ26A-710

0
RFUL
interrupt
0:enable
1:disable

0
TEND
interrupt
0:enable
1:disable

0
REND
interrupt
0:enable
1:disable

TMP92CZ26A
(9) SPIC (2/2)
Symbol

Name

Address

0826H
SPICR

SPI
CRC
register

7

6

5

4

3

2

1

0

CRCD7

CRCD6

CRCD5

CRCD4

CRCD3

CRCD2

CRCD1

CRCD0

0

0

0

0

0

0

0

0

CRCD11

CRCD10

CRCD9

CRCD8

0

0

0

0

TXD2

TXD1

TXD0

0

0

TXD9

TXD8

0

0

0

TXD3

TXD2

TXD1

TXD0

0

0

0

0

TXD11

TXD10

TXD9

TXD8

0

0

0

0

RXD3

RXD2

RXD1

RXD0

0

0

0

0

RXD11

RXD10

RXD9

RXD8

0

0

0

0

RXD3

RXD2

RXD1

RXD0

0

0

0

0

RXD11

RXD10

RXD9

RXD8

0

0

0

0

R
CRC result register [7:0]
CRCD15

0827H

CRCD14

CRCD13

CRCD12
R

0

0

0

0

CRC result register [15:8]
TXD7

TXD6

TXD5

TXD4

0830H
SPITD0

SPI
transmission
data0
register

0831H

TXD3
R/W

0

0

0

TXD15

TXD14

0

0

0
0
0
Transmit data register [7:0]
TXD13
TXD12
TXD11
TXD10
R/W
0

0

0

Transmit data register [15:8]
TXD7
0832H
SPITD1

SPI
transmission
data1
register

TXD6

TXD5

TXD4
R/W

0

0

0

0

Transmit data register [7:0]
TXD15
0833H

TXD14

TXD13

TXD12
R/W

0

0

0

RXD7

RXD6

RXD5

0

Transmit data register [15:8]

0834H
SPIRD0

SPI
receive
data0
register

RXD4
R

0

0

0

RXD15

RXD14

RXD13

0

Receive data register [7:0]

0835H

RXD12
R

0

0

0

RXD7

RXD6

RXD5

0

Receive data register [15:8]

0836H
SPIRD1

SPI
receive
data1
register

RXD4
R

0

0

0

RXD15

RXD14

RXD13

0

Receive data register [7:0]

0837H

RXD12
R

0

0

0

0

Receive data register [15:8]

92CZ26A-711

TMP92CZ26A
(10) MMU (1/8)
Symbol

LOCALPX

Name
LOCALX
register
for
program

Address

0880H

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

0

0

R/W
0
0
0
0
Set BANK number for LOCAL-X
(“0” is disabled because of overlapped with Common-area.)
0

LXE
R/W
LOCALPX

LOCALPY

LOCALX
register
for
program

LOCALY
register
for
program

0881H

0

X8
R/W

0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

Y4

Y3

Y2

Y1

Y0

R/W
0882H

0

0

0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)

Z5

Z4

LYE

LOCALPY

LOCALY
register
for
program

LOCALPZ

LOCALZ
register
for
program

LOCALPZ

LOCALZ
register
for
program

R/W
0883H

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z3

Z2

Z1

Z0

R/W
0884H

0885H

0

0

0

0
0
0
0
Set BANK number for LOCAL-Z
(“3” is disabled because of overlapped with Common-area.)

0

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-712

TMP92CZ26A

(10) MMU (2/8)
Symbol

Name

LOCALLX

LOCALX
register
for
LCD

0888H

LOCALLX

LOCALX
register
for
LCD

0889H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALLY

LOCALY
register
for
LCD

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
088AH

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALLY

LOCALY
register
for
LCD

LOCALLZ

LOCALZ
register
for
LCD

LOCALLZ

LOCALZ
register
for
LCD

R/W
088BH

088CH

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

088DH

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-713

TMP92CZ26A

(10) MMU (3/8)
Symbol

Name

LOCALRX

LOCALX
register
for
read

0890H

LOCALRX

LOCALX
register
for
read

0891H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALRY

LOCALY
register
for
read

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
0892H

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALRY

LOCALY
register
for
read

LOCALRZ

LOCALZ
register
for
read

LOCALRZ

LOCALZ
register
for
read

R/W
0893H

0894H

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

0895H

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-714

TMP92CZ26A

(10) MMU (4/8)
Symbol

Name

LOCALWX

LOCALX
register
for
write

0898H

LOCALWX

LOCALX
register
for
write

0899H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALWY

LOCALY
register
for
write

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
089AH

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALWY

LOCALY
register
for
write

LOCALWZ

LOCALZ
register
for
write

LOCALWZ

LOCALZ
register
for
write

R/W
089BH

089CH

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

089DH

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-715

TMP92CZ26A

(10) MMU (5/8)
Symbol

Name

LOCALESX

LOCALX
register
for DMA
source

08A0H

LOCALESX

LOCALX
register
for DMA
source

08A1H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALESY

LOCALY
register
for DMA
source

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
08A2H

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALESY

LOCALY
register
for DMA
source

LOCALESZ

LOCALZ
register
for DMA
source

LOCALESZ

LOCALZ
register
for DMA
source

R/W
08A3H

08A4H

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

08A5H

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-716

TMP92CZ26A

(10) MMU (6/8)
Symbol

Name

LOCALEDX

LOCALX
register
for DMA
destination

08A8H

LOCALEDX

LOCALX
register
for DMA
destination

08A9H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALEDY

LOCALY
register
for DMA
destination

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
08AAH

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALEDY

LOCALY
register
for DMA
destination

LOCALEDZ

LOCALZ
register
for DMA
destination

LOCALEDZ

LOCALZ
register
for DMA
destination

R/W
08ABH

08ACH

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

08ADH

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-717

TMP92CZ26A

(10) MMU (7/8)
Symbol

Name

LOCALOSX

LOCALX
register
for DMA
source

08B0H

LOCALOSX

LOCALX
register
for DMA
source

08B1H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALOSY

LOCALY
register
for DMA
source

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
08B2H

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALOSY

LOCALY
register
for DMA
source

LOCALOSZ

LOCALZ
register
for DMA
source

LOCALOSZ

LOCALZ
register
for DMA
source

R/W
08B3H

08B4H

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

08B5H

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-718

TMP92CZ26A

(10) MMU (8/8)
Symbol

Name

LOCALODX

LOCALX
register
for DMA
destination

08B8H

LOCALODX

LOCALX
register
for DMA
destination

08B9H

Address

7

6

5

4

3

2

1

0

X7

X6

X5

X4

X3

X2

X1

X0

R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
X8
R/W
R/W
0
LOCALX
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-X
X8-X0 setting and CS
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5

LOCALODY

LOCALY
register
for DMA
destination

Y4

Y3

Y2

Y1

Y0

0

0

0

R/W
08BAH

0

0

0

Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE

LOCALODY

LOCALY
register
for DMA
destination

LOCALODZ

LOCALZ
register
for DMA
destination

LOCALODZ

LOCALZ
register
for DMA
destination

R/W
08BBH

08BCH

0
LOCALY
BANK
0:disable
1:enable
Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

0

0

R/W
0

0

0

0

Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)

08BDH

LZE

Z8

R/W

R/W

0
LOCALZ
BANK
0:disable
1:enable

0
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA

100000000∼101111111 CSZC

010000000∼011111111 CSZB

110000000∼111111111 CSZD

92CZ26A-719

TMP92CZ26A

(11) NAND-Flash controller (1/4)
Symbol

Name

7

6

5

4

3

2

1

0

WE

ALE

CLE

CE0

CE1

ECCE

BUSY

ECCRST

0

0

0

Address

R/W
WE

ALE

08C0H enable
control
(Prohibit 0: Disable 0: “L” out
RMW)
1: Enable 1: “H” out

NDFMCR0

CLE

0
CE0

0
CE1

control

control

control

0: “L” out

0: “H” out

0: “H” out

1: “H” out

1: “L” out

1: “L” out

0
NAND
Flash

state

0: Disable 1: Busy
1: Enable 0: Ready

0
ECC

reset
control
0: −
1: Reset
*Always
read as
“0”.

NANDF
Control0
Register

SPLW1

SPLW0

SPHW1

SPHW0

RSECCL

RSEDN

RSESTA

RSECGW

0

W
0

R/W
0

R/W
0

0

0

Strobe pulse width

08C1H (Low width of NDRE ,
(Prohibit NDWE )

0

0

Strobe pulse width

Reed-

(High width of NDRE ,
NDWE )

Solomon

ReedSolomon

ReedSolomon

ReedSolomon

ECC

operation

latch

error
calculation
start

ECC

0: Encode

RMW)

08C2H
NDFMCR1

0
ECC
circuit
control

NANDF
Control1
Register

Inserted width

Inserted width

(Write)

= (fSYS) × (set value)

= (fSYS) × (set value)

0: Disable

1: Decode

1: Enable

(Read)

0: −

generator
write
control

1: Start

0: Disable
*Always
1: Enable
read as “0”.

INTERDY

INTRSC

BUSW

ECCS

SYSCKE

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

Ready
interrupt

0: Disable
1: Enable

Reed-

Data bus

Solomon

width

calculation
end
interrupt

0: 8-bit
1: 16-bit

0: Disable

ECC
calculation

Clock
control

0:Hamming 0: Disable
1: Reed1: Enable
Solomon

1: Enable

STATE3
08C3H

STATE2

STATE1

STATE0

SEER1

SEER0

R
0

0

0

0

Undefined Undefined

Status read (See the table below.)
ECCD7

ECCD6

ECCD5

ECCD4

08C4H
NANDF
NDECCRD0 Code ECC
Register0

0

0

ECCD2

0
0
0
0
NAND Flash ECC Register (7-0) (7-0)

ECCD15

ECCD14

ECCD13

ECCD12

ECCD1

ECCD0

0

0

ECCD11

ECCD10

ECCD9

ECCD8

0

0

ECCD1

ECCD0

0

0

ECCD9

ECCD8

0

0

R

08C5H
0

0

0
0
0
0
NAND Flash ECC Register (7-0) (15-8)

ECCD7

ECCD6

ECCD5

ECCD4

ECCD3

ECCD2

R

08C6H
NANDF
NDECCRD1 Code ECC
Register1

ECCD3
R

0

0

0
0
0
0
NAND Flash ECC Register (7-0) (7-0)

ECCD15

ECCD14

ECCD13

ECCD12

ECCD11

ECCD10

R

08C7H
0

0

0
0
0
0
NAND Flash ECC Register (7-0) (15-8)

92CZ26A-720

TMP92CZ26A

(11) NAND-Flash controller (2/4)
Symbol

Name

Address

7

6

5

4

3

2

1

0

ECCD7

ECCD6

ECCD5

ECCD4

ECCD3

ECCD2

ECCD1

ECCD0

0

0

0

0

0

ECCD15

ECCD14

ECCD13

ECCD9

ECCD8

0

0

ECCD1

ECCD0

0

0

ECCD9

ECCD8

0

0

ECCD1

ECCD0

0

0

ECCD9

ECCD8

0

0

R

08C8H
NANDF
NDECCRD2 Code ECC
Register2

0
0
0
NAND Flash ECC Register (7-0)
ECCD12

08C9H
0

0

0

ECCD7

ECCD6

ECCD5

ECCD4

ECCD3

ECCD2

R
0

0

0

0
0
0
NAND Flash ECC Register (7-0)

ECCD15

ECCD14

ECCD13

0

0

0

ECCD7

ECCD6

ECCD5

ECCD12

ECCD11

ECCD10

R

08CBH

0
0
0
NAND Flash ECC Register (15-8)
ECCD4

ECCD3

ECCD2

R

08CCH
NANDF
NDECCRD4 Code ECC
Register4

ECCD10

0
0
0
NAND Flash ECC Register (15-8)

08CAH
NANDF
NDECCRD3 Code ECC
Register3

ECCD11
R

0

0

0

0
0
0
NAND Flash ECC Register (7-0)

ECCD15

ECCD14

ECCD13

ECCD12

ECCD11

ECCD10

R

08CDH
0

0

0

0
0
0
NAND Flash ECC Register (15-8)

92CZ26A-721

TMP92CZ26A
(11) NAND-Flash controller (3/4)
Symbol

Name

Address

08D0H

NDRSCA0

NDRSCD0

NANDF
read solomon
Result
address
Register0

NANDF
read solomon
Result data
Register0

7

6

5

4

3

2

1

0

RS0A7

RS0A6

RS0A5

RS0A4

RS0A3

RS0A2

RS0A1

RS0A0

0

0

0

0

0

0

0

0

R
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS0A9
R
0

08D1H

RS0D7
08D2H

NDRSCD1

NANDF
read solomon
Result data
Register1

RS0D6

RS0D5

RS0D4

0

0

0

0

RS1A6

RS1A5

RS1A4

0

RS0D0

0

0

0

0

RS1A3

RS1A2

RS1A1

RS1A0

0

0

0

0

0

0

0

RS1A9

RS1A8
R

0
08D5H

RS1D7
08D6H

0

NAND Flash ReedSolomon Calculation
Result Address
Register (9-8)
RS1D6

RS1D5

RS1D4

RS1D3

RS1D2

RS1D1

RS1D0

0

0

0

0

R
0

0

0

0

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
RS2A6

RS2A5

RS2A4

RS2A3

RS2A2

RS2A1

RS2A0

0

0

0

0

R
0

NDRSCD2

RS0D1

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)

08D8H

NDRSCA2

RS0D2

R

RS2A7

NANDF
read solomon
Result
address
Register2

RS0D3
R

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)

08D4H

NDRSCA1

0

NAND Flash
Reed-Solomon
Calculation Result
Address Register (9-8)

RS1A7

NANDF
read solomon
Result
address
Register1

RS0A8

0

0

0

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS2A9

RS2A8
R

0
08D9H

NANDF
read solomon
08DAH
Result data
Register2

0

NAND Flash ReedSolomon Calculation
Result Address
Register (9-8)
RS2D7

RS2D6

RS2D5

RS2D4

RS2D3

RS2D2

RS2D1

RS2D0

0

0

0

0

R
0

0

0

0

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)

92CZ26A-722

TMP92CZ26A

(11) NAND-Flash controller (4/4)
Symbol

Name

Address

7

6

5

4

3

2

1

0

RS3A7

RS3A6

RS3A5

RS3A4

RS3A3

RS3A2

RS3A1

RS3A0

0

0

0

0

0

0

0

0

R

08DCH

NDRSCA3

NDRSCD3

NANDF
read
solomon
Result
address
Register3

NANDF
read
solomon
Result data
Register3

NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS3A9
0

08DDH

0

NAND Flash ReedSolomon Calculation
Result Address
Register (9-8)
RS2D7

RS2D6

RS2D5

RS2D4

RS2D3

RS2D2

RS2D1

RS2D0

0

0

0

0

R

08DEH
0

0

0

0

NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
D7

D6

D5

D4

D3

D2

D1

D0

R/W

1FF0H
NDFDTR0

RS3A8
R

Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

NANDF
Data
Register0

NAND-Flash Data Register (7-0)
D15
1FF1H

D14

D13

D12

D11

D10

D9

D8

R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (15-8)
D7

1FF2H
NDFDTR1

NANDF
Data
Register1

D6

D5

D4

D3

D2

D1

D0

R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (7-0)
D15

1FF3H

D14

D13

D12

D11

D10

D9

D8

R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (15-8)

92CZ26A-723

TMP92CZ26A
(12) DMAC (1/7)
Symbol

Name

Address

0900H

7

6

5

4

3

2

1

0

D0SA7

D0SA6

D0SA5

D0SA4

D0SA3

D0SA2

D0SA1

D0SA0

0

0

0

0

0

0

0

0

D0SA10

D0SA9

D0SA8

0

0

0

D0SA18

D0SA17

D0SA16

0

0

0

D0DA3

D0DA2

D0DA1

D0DA0

0

0

0

0

D0DA10

D0DA9

D0DA8

0

0

0

D0DA18

D0DA17

D0DA16

0

0

0

R/W
Source address for DMA0 (7:0)

HDMAS0

DMA
source
address
Register0

0901H

D0SA15

D0SA14

D0SA13

D0SA12

0

0

0

0

D0SA11

R/W
0

Source address for DMA0 (15:8)
D0SA23
0902H

D0SA22

D0SA21

D0SA20

D0SA19

R/W
0

0

0

0

0

Source address for DMA0 (23:16)
D0DA7
0904H

D0DA6

D0DA5

D0DA4
R/W

0

0

0

0

Destination address for DMA0 (7:0)

HDMAD0

DMA
destination
address
Register0

D0DA15
0905H

D0DA14

D0DA13

D0DA12

D0DA11

R/W
0

0

0

0

0

Destination address for DMA0 (15:8)
D0DA23
0906H

D0DA22

D0DA21

D0DA20

D0DA19

R/W
0

0

0

0

D0CA7

D0CA6

D0CA5

0

Destination address for DMA0 (23:16)

HDMACA0

DMA
Transfer
count
number A
Register0

0908H

D0CA4

D0CA3

D0CA2

D0CA1

D0CA0

0

0

0

0

D0CA10

D0CA9

D0CA8

0

0

0

D0CB3

D0CB2

D0CB1

D0CB0

0

0

0

0

D0CB10

D0CB9

D0CB8

0

0

0

D0M2

D0M1

D0M0

0

0

R/W
0

0

0

0

D0CA15

D0CA14

D0CA13

Transfer count A [7:0] for DMA0

0909H

D0CA12

D0CA11

R/W
0

0

0

0

D0CB7

D0CB6

D0CB5

0

Transfer count A [15:8] for DMA0

HDMACB0

DMA
Transfer
count
number B
Register0

090AH

D0CB4
R/W

0

0

0

0

Transfer count B [7:0] for DMA0
D0CB15
090BH

D0CB14

D0CB13

D0CB12

D0CB11

R/W
0

0

0

0

0

Transfer count B [15:8] for DMA0
D0M4

D0M3

R/W
0

HDMAM0

DMA
transfer
Mode
Register0

090CH

0

0

DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

92CZ26A-724

Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved

TMP92CZ26A
(12) DMAC (2/7)
Symbol

Name

Address

0910H

7

6

5

4

3

2

1

0

D1SA7

D1SA6

D1SA5

D1SA4

D1SA3

D1SA2

D1SA1

D1SA0

0

0

0

0

0

0

0

0

D1SA10

D1SA9

D1SA8

0

0

0

D1SA18

D1SA17

D1SA16

0

0

0

R/W
Set source address for DMA1 (7:0)

HDMAS1

DMA
source
address
Register1

0911H

D1SA15

D1SA14

D1SA13

D1SA12

0

0

0

0

D1SA11

R/W
0

Set source address for DMA1 (15:8)
D1SA23
0912H

D1SA22

D1SA21

D1SA20

D1SA19

R/W
0

0

0

0

0

Set source address for DMA1 (23:16)
D1DA7
0914H

D1DA6

D1DA5

D1DA4

D1DA3

D1DA2

D1DA1

D1DA0

0

0

0

0

D1DA10

D1DA9

D1DA8

0

0

0

D1DA18

D1DA17

D1DA16

0

0

0

R/W
0

0

0

0

Set destination address for DMA1 (7:0)

HDMAD1

DMA
destination
address
Register1

D1DA15
0915H

D1DA14

D1DA13

D1DA12

D1DA11

R/W
0

0

0

0

0

Set destination address for DMA1 (15:8)
D1DA23
0916H

D1DA22

D1DA21

D1DA20

D1DA19

R/W
0

0

0

D1CA7

D1CA6

D1CA5

0

0

Set destination address for DMA1 (23:16)

HDMACA1

DMA
Transfer
count
number A
Register1

0918H

D1CA4

D1CA3

D1CA2

D1CA1

D1CA0

0

0

0

0

D1CA10

D1CA9

D1CA8

0

0

0

R/W
0

0

0

D1CA15

D1CA14

D1CA13

0

Set transfer-count-number A for DMA1 (7:0)

0919H

D1CA12

D1CA11

R/W
0

0

0

D1CB7

D1CB6

0

0

Set transfer-count-number A for DMA1 (15:8)

HDMACB1

DMA
Transfer
count
number B
Register1

091AH

D1CB5

D1CB4

D1CB3

D1CB2

D1CB1

D1CB0

0

0

0

0

D0CB10

D0CB9

D0CB8

0

0

0

D1M1

D1M0

0

0

R/W
0

0

0

0

Set transfer-count-number B for DMA1 (7:0)
D0CB15
091BH

D0CB14

D0CB13

D0CB12

D0CB11

R/W
0

0

0

0

0

Set transfer-count-number B for DMA1 (15:8)
D1M4

D1M3

D1M2
R/W

0

HDMAM1

DMA
transfer
Mode
Register1

091CH

0

0

DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

92CZ26A-725

Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved

TMP92CZ26A
(12) DMAC (3/7)
Symbol

Name

Address

0920H

7

6

5

4

3

2

1

0

D2SA7

D2SA6

D2SA5

D2SA4

D2SA3

D2SA2

D2SA1

D2SA0

0

0

0

0

0

0

0

0

D2SA10

D2SA9

D2SA8

0

0

0

D2SA18

D2SA17

D2SA16

0

0

0

D2DA3

D2DA2

D2DA1

D2DA0

0

0

0

0

D2DA10

D2DA9

D2DA8

0

0

0

D2DA18

D2DA17

D2DA16

0

0

0

R/W
Source address for DMA2 (7:0)

HDMAS2

DMA
source
address
Register2

0921H

D2SA15

D2SA14

D2SA13

D2SA12

0

0

0

0

D2SA11

R/W
0

Source address for DMA2 (15:8)
D2SA23
0922H

D2SA22

D2SA21

D2SA20

D2SA19

R/W
0

0

0

0

0

Source address for DMA2 (23:16)
D2DA7
0924H

D2DA6

D2DA5

D2DA4
R/W

0

0

0

0

Destination address for DMA2 (7:0)

HDMAD2

DMA
destination
address
Register2

D2DA15
0925H

D2DA14

D2DA13

D2DA12

D2DA11

R/W
0

0

0

0

0

Destination address for DMA2 (15:8)
D2DA23
0926H

D2DA22

D2DA21

D2DA20

D2DA19

R/W
0

0

0

0

D2CA7

D2CA6

D2CA5

0

Destination address for DMA2 (23:16)

HDMACA2

DMA
Transfer
count
number A
Register2

0928H

D2CA4

D2CA3

D2CA2

D2CA1

D2CA0

0

0

0

0

D2CA10

D2CA9

D2CA8

0

0

0

D2CB3

D2CB2

D2CB1

D2CB0

0

0

0

0

D2CB10

D2CB9

D2CB8

0

0

0

D2M2

D2M1

D2M0

0

0

R/W
0

0

0

0

D2CA15

D2CA14

D2CA13

Transfer count A [7:0] for DMA2

0929H

D2CA12

D2CA11

R/W
0

0

0

0

D2CB7

D2CB6

D2CB5

0

Transfer count A [15:8] for DMA2

HDMACB2

DMA
Transfer
count
number B
Register2

092AH

D2CB4
R/W

0

0

0

0

Transfer count B [7:0] for DMA2
D2CB15
092BH

D2CB14

D2CB13

D2CB12

D2CB11

R/W
0

0

0

0

0

Transfer count A [15:8] for DMA2
D2M4

D2M3

R/W
0

HDMAM2

DMA
transfer
Mode
Register2

092CH

0

0

DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

92CZ26A-726

Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved

TMP92CZ26A
(12) DMAC (4/7)
Symbol

Name

Address

0930H

7

6

5

4

3

2

1

0

D3SA7

D3SA6

D3SA5

D3SA4

D3SA3

D3SA2

D3SA1

D3SA0

0

0

0

0

0

0

0

0

D3SA10

D3SA9

D3SA8

0

0

0

D3SA18

D3SA17

D3SA16

0

0

0

R/W
Set source address for DMA3 (7:0)

HDMAS3

DMA
source
address
Register3

0931H

D3SA15

D3SA14

D3SA13

D3SA12

0

0

0

0

D3SA11

R/W
0

Set source address for DMA3 (15:8)
D3SA23
0932H

D3SA22

D3SA21

D3SA20

D3SA19

R/W
0

0

0

0

0

Set source address for DMA3 (23:16)
D3DA7
0934H

D3DA6

D3DA5

D3DA4

D3DA3

D3DA2

D3DA1

D3DA0

0

0

0

0

D3DA10

D3DA9

D3DA8

0

0

0

D3DA18

D3DA17

D3DA16

0

0

0

R/W
0

0

0

0

Set destination address for DMA3 (7:0)

HDMAD3

DMA
destination
address
Register3

D3DA15
0935H

D3DA14

D3DA13

D3DA12

D3DA11

R/W
0

0

0

0

0

Set destination address for DMA3 (15:8)
D3DA23
0936H

D3DA22

D3DA21

D3DA20

D3DA19

R/W
0

0

0

0

D3CA7

D3CA6

D3CA5

0

Set destination address for DMA3 (23:16)

HDMACA3

DMA
Transfer
count
number A
Register3

0938H

D3CA4

D3CA3

D3CA2

D3CA1

D3CA0

0

0

0

0

D3CA10

D3CA9

D3CA8

0

0

0

D3CB3

D3CB2

D3CB1

D3CB0

0

0

0

0

D3CB10

D3CB9

D3CB8

0

0

0

D3M2

D3M1

D3M0

0

0

R/W
0

0

0

0

D3CA15

D3CA14

D3CA13

Transfer count A [7:0] for DMA3

0939H

D3CA12

D3CA11

R/W
0

0

0

0

D3CB7

D3CB6

D3CB5

0

Transfer count A [15:8] for DMA3

HDMACB3

DMA
Transfer
count
number B
Register3

093AH

D3CB4
R/W

0

0

0

0

Transfer count B [7:0] for DMA3
D3CB15
093BH

D3CB14

D3CB13

D3CB12

D3CB11

R/W
0

0

0

0

0

Transfer count B [15:8] for DMA3
D3M4

D3M3

R/W
0

HDMAM3

DMA
transfer
Mode
Register3

093CH

0

0

DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

92CZ26A-727

Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved

TMP92CZ26A
(12) DMAC (5/7)
Symbol

Name

Address

0940H

7

6

5

4

3

2

1

0

D4SA7

D4SA6

D4SA5

D4SA4

D4SA3

D4SA2

D4SA1

D4SA0

0

0

0

0

0

0

0

0

D4SA10

D4SA9

D4SA8

0

0

0

D4SA18

D4SA17

D4SA16

0

0

0

D4DA3

D4DA2

D4DA1

D4DA0

0

0

0

0

D4DA10

D4DA9

D4DA8

0

0

0

D4DA18

D4DA17

D4DA16

0

0

0

R/W
Source address for DMA4 (7:0)

HDMAS4

DMA
source
address
Register4

0941H

D4SA15

D4SA14

D4SA13

D4SA12

0

0

0

0

D4SA11

R/W
0

Source address for DMA4 (15:8)
D4SA23
0942H

D4SA22

D4SA21

D4SA20

D4SA19

R/W
0

0

0

0

0

Source address for DMA4 (23:16)
D4DA7
0944H

D4DA6

D4DA5

D4DA4
R/W

0

0

0

0

Destination address for DMA4 (7:0)

HDMAD4

DMA
destination
address
Register4

D4DA15
0945H

D4DA14

D4DA13

D4DA12

D4DA11

R/W
0

0

0

0

0

Destination address for DMA4 (15:8)
D4DA23
0946H

D4DA22

D4DA21

D4DA20

D4DA19

R/W
0

0

0

0

D4CA7

D4CA6

D4CA5

0

Destination address for DMA4 (23:16)

HDMACA4

DMA
Transfer
count
number A
Register4

0948H

D4CA4

D4CA3

D4CA2

D4CA1

D4CA0

0

0

0

0

D4CA10

D4CA9

D4CA8

0

0

0

D4CB3

D4CB2

D4CB1

D4CB0

0

0

0

0

D4CB10

D4CB9

D4CB8

0

0

0

D4M2

D4M1

D4M0

0

0

R/W
0

0

0

0

D4CA15

D4CA14

D4CA13

Transfer count A [15:8] for DMA4

0949H

D4CA12

D4CA11

R/W
0

0

0

0

D4CB7

D4CB6

D4CB5

0

Transfer count A [15:8] for DMA4

HDMACB4

DMA
Transfer
count
number B
Register4

094AH

D4CB4
R/W

0

0

0

0

Transfer count B [7:0] for DMA4
D4CB15
094BH

D4CB14

D4CB13

D4CB12

D4CB11

R/W
0

0

0

0

0

Transfer count B [15:8] for DMA4
D4M4

D4M3

R/W
0

HDMAM4

DMA
transfer
Mode
Register4

094CH

0

0

DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

92CZ26A-728

Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved

TMP92CZ26A
(12) DMAC (6/7)
Symbol

Name

Address

0950H

7

6

5

4

3

2

1

0

D5SA7

D5SA6

D5SA5

D5SA4

D5SA3

D5SA2

D5SA1

D5SA0

0

0

0

0

0

0

0

0

D5SA10

D5SA9

D5SA8

0

0

0

D5SA18

D5SA17

D5SA16

0

0

0

D5DA3

D5DA2

D5DA1

D5DA0

0

0

0

0

D5DA10

D5DA9

D5DA8

0

0

0

D5DA18

D5DA17

D5DA16

0

0

0

R/W
Source address for DMA5 (7:0)

HDMAS5

DMA
source
address
Register5

0951H

D5SA15

D5SA14

D5SA13

D5SA12

0

0

0

0

D5SA11

R/W
0

Source address for DMA5 (15:8)
D5SA23
0952H

D5SA22

D5SA21

D5SA20

D5SA19

R/W
0

0

0

0

0

Source address for DMA5 (23:16)
D5DA7
0954H

D5DA6

D5DA5

D5DA4
R/W

0

0

0

0

Destination address for DMA5 (7:0)

HDMAD5

DMA
destination
address
Register5

D5DA15
0955H

D5DA14

D5DA13

D5DA12

D5DA11

R/W
0

0

0

0

0

Destination address for DMA5 (15:8)
D5DA23
0956H

D5DA22

D5DA21

D5DA20

D5DA19

R/W
0

0

0

0

D5CA7

D5CA6

D5CA5

0

Destination address for DMA5 (23:16)

HDMACA5

DMA
Transfer
count
number A
Register5

0958H

D5CA4

D5CA3

D5CA2

D54CA1

D5CA0

0

0

0

0

D5CA10

D5CA9

D5CA8

0

0

0

D5CB3

D5CB2

D5CB1

D5CB0

0

0

0

0

D5CB10

D5CB9

D5CB8

0

0

0

D5M2

D5M1

D5M0

0

0

R/W
0

0

0

0

D5CA15

D5CA14

D5CA13

Transfer count A [7:0] for DMA5

0959H

D5CA12

D5CA11

R/W
0

0

0

0

D5CB7

D5CB6

D5CB5

0

Transfer count A [15:8] for DMA5

HDMACB5

DMA
Transfer
count
number B
Register5

095AH

D5CB4
R/W

0

0

0

0

Transfer count B [7:0] for DMA5
D5CB15
095BH

D5CB14

D5CB13

D5CB12

D5CB11

R/W
0

0

0

0

0

Transfer count B [15:8] for DMA5
D5M4

D5M3

R/W
0

HDMAM5

DMA
transfer
Mode
Register5

095CH

0

0

DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved

92CZ26A-729

Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved

TMP92CZ26A
(12) DMAC (7/7)
Symbol

HDMAE

Name
DMA
enable
Register

Address

7

6

5

4

3

2

1

0

DMAE5

DMAE4

DMAE3

DMAE2

DMAE1

DMAE0

0

0

0

0

0

R/W
097EH

0

DMA channel operation
DMATE

DMATR6

DMATR5

DMATR4

0: Disable

1: Enable

DMATR3

DMATR2

DMATR1

DMATR0

0

0

0

R/W
HDMATR

DMA
timer
Register

0
097FH Timer

0

0

0

0

0: Disable

Maximum bus occupancy time setting
The value to be set in  should be obtained by
“Maximum bus occupancy time / (256/fSYS)”.

1: Enable

“00H” cannot be set.

operation

92CZ26A-730

TMP92CZ26A

(13) Clock gear, PLL
Symbol

SYSCR0

Name

System
clock
control
register0

Address

7

6

5

4

XTEN

USBCLK1

USBCLK0

1

R/W
0

0

Low
-frequency
oscillator
circuit (fs)

10E0H

0: Stop
1:
Oscillation

3

2

1

WUEF
R/W
0

Select the clock of
USB(fUSB)

0
PRCK
R/W
0

Warm-up
timer

Select
Prescaler

00: Disable

clock

01: Reserved

0: fSYS/2

10: X1USB

1: fSYS/8

11: fPLLUSB

GEAR2

SYSCR1

System
clock
control
register1

GEAR1
GEAR0
R/W
1
0
0
Select gear value of high
frequency (fc)
000: fc
101: (Reserved)
001: fc/2
110: (Reserved)
010: fc/4
111: (Reserved)
011: fc/8
100: fc/16

10E1H

−

SYSCR2

System
clock
control
register2

CKOSEL

0
10E2H

Always
write “0”.

0

WUPTM1 WUPTM0
R/W
1
0

HALTM1

HALTM0

1

1

Select
CLKOUT

Warm-Up Timer

HALT mode

00: Reserved

00: Reserved

0: fSYS

01: 28/inputted frequency

01: STOP mode

1: fs

10:214/inputted frequency 10: IDLE1 mode
11:216/inputted frequency 11: IDLE2 mode

−
R/W
0

PROTECT

EMCCR0

EMC
control
register0

R
0
10E3H Protect flag

Always
write “0”.

0: OFF

EXTIN
R/W
0

DRVOSCH

DRVOSCL

R/W
1

R/W
1

1: External

fc oscillator

fs oscillator

clock

drive ability

drive ability

1: NORMAL 1: NORMAL

1: ON

0: WEAK

EMCCR1

EMCCR2

PLLCR0

EMC
control
register1
EMC
control
register2

PLL
control
register0

10E4H

st

10E5H

FCSEL
R/W
0
10E8H

LUPFG
R
0

Select fc
clock
0 : fOSCH
1 : fPLL

Lock-up
timer
Status flag
0 : not end
1 : end

PLL1

LUPSEL

R/W
0
PLL
control
register1

10E9H

nd

Switching the protect ON/OFF by write to following 1 -KEY,2 -KEY
st
1 -KEY: EMCCR1=5AH,EMCCR2=A5H in succession write
nd
2 -KEY: EMCCR1=A5H,EMCCR2=5AH in succession write

PLL0

PLLCR1

0: WEAK

0

PLLTIMES

R/W
0

PLL0 for
CPU

PLL1 for
USB

0: Off

0: Off

1: On

1: On

0
Select the

Select
stage of
Lock up
counter

number of

0: 12 stage
(for PLL0)

1: ×16

1:13 stage
(for PLL1)

92CZ26A-731

PLL
0: ×12

TMP92CZ26A

(14) 8-bit timer (1/2)
Symbol

TA01RUN

Name

TMRA01
RUN
register

Address

7

6

5

4

3

TA0RDE
R/W
0
1100H

I2TA01
0

8-bit timer
register 0

1102H
(Prohibit
RMW)

TA1REG

8-bit timer
register 1

1103H
(Prohibit
RMW)

TA01MOD

TA1FFCR

TA23RUN

TMRA1
Flip-Flop
control
register

TMRA23
RUN
register

1104H

Up counter

Up counter

buffer

0: Stop

prescaler

(UC1)

(UC0)

0: Disable

1: Operate

0: Stop and clear
1: Run (Count up)

−
W
0
−
W
0

TA01M0

0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode

PWM01

PWM00 TA1CLK1 TA1CLK0
R/W
0
0
0

TA0CLK1 TA0CLK0

Source clock for TMRA1

Source clock for TMRA0

00: TA0TRG
01: φT1
10: φT16
11: φT256

00: TA0IN pin
01: φT1
10: φT4
11: φT16

TA1FFC1 TA1FFC0
W
1
1
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care

TA1FFIE TA1FFIS
R/W
0
0
TA1FF
TA1FF
control for inversion
inversion select

0
PWM cycle
00: Reserved
6
01: 2
7
10: 2
8
11: 2

TA2RDE
R/W
0

I2TA23
0

8-bit timer
register 2

110AH
(Prohibit
RMW)

TA3REG

8-bit timer
register 3

110BH
(Prohibit
RMW)

TA23MOD

TA3FFCR

TMRA3
Flip-Flop
control
register

110CH

0

0: Disable 0: TMRA0
1: Enable 1: TMRA1

TA23PRUN TA3RUN
R/W
0
0

TA2RUN
0

IDLE2

TMRA23

Up counter

Up counter

buffer

0: Stop

prescaler

(UC3)

(UC2)

0: Disable

1: Operate

0: Stop and clear
1: Run (Count up)

−
W
0
−
W
0

TA23M1

TMRA23
MODE
register

0

Double

1: Enable

TA2REG

0

TMRA01

1105H
(Prohibit
RMW)

1108H

0
TA0RUN

IDLE2

TA01M1

TMRA01
MODE
register

1

Double

1: Enable

TA0REG

2

TA01PRUN TA1RUN
R/W
0
0

TA23M0

0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode

PWM21

PWM20 TA3CLK1 TA3CLK0
R/W
0
0
0

TA2CLK1 TA2CLK0

Source clock for TMRA3

Source clock for TMRA2

00: TA2TRG
01: φT1
10: φT16
11: φT256

00: Reserved
01: φT1
10: φT4
11: φT16

TA3FFC1 TA3FFC0
W
1
1
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care

TA3FFIE TA3FFIS
R/W
0
0
TA3FF
TA3FF
control for inversion
inversion select
0: Disable 0: TMRA2
1: Enable 1: TMRA3

0
PWM cycle
00: Reserved
6
01: 2
7
10: 2
8
11: 2

110DH
(Prohibit
RMW)

92CZ26A-732

0

0

TMP92CZ26A

(14) 8-bit timer (1/2)
Symbol

TA45RUN

Name

TMRA45
RUN
register

Address

7

6

5

4

3

TA4RDE
R/W
0
1110H

I2TA45
0

8-bit timer
register 4

1112H
(Prohibit
RMW)

TA5REG

8-bit timer
register 5

1113H
(Prohibit
RMW)

TA45MOD

TA5FFCR

TA67RUN

TMRA5
Flip-Flop
control
register

TMRA67
RUN
register

1114H

Up counter

Up counter

buffer

0: Stop

prescaler

(UC5)

(UC4)

0: Disable

1: Operate

0: Stop and clear
1: Run (Count up)

−
W
0
−
W
0

TA45M0

0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode

PWM41

PWM40 TA5CLK1 TA5CLK0
R/W
0
0
0

TA4CLK1 TA4CLK0

Source clock for TMRA5

Source clock for TMRA4

00: TA4TRG
01: φT1
10: φT16
11: φT256

00: 32KHz clock
01: φT1
10: φT4
11: φT16

TA5FFC1 TA5FFC0
W
1
1
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care

TA5FFIE TA5FFIS
R/W
0
0
TA5FF
TA5FF
control for inversion
inversion select

0
PWM cycle
00: Reserved
6
01: 2
7
10: 2
8
11: 2

TA6RDE
R/W
0

I2TA67
0

TA6REG

8-bit timer
register 2

TA7REG

8-bit timer
register 3

111BH
(Prohibit
RMW)

TA67MOD

TA7FFCR

TMRA7
Flip-Flop
control
register

111CH

0

0: Disable 0: TMRA4
1: Enable 1: TMRA5

TA67PRUN TA7RUN
R/W
0
0

TA6RUN
0

IDLE2

TMRA67

Up counter

Up counter

buffer

0: Stop

prescaler

(UC7)

(UC6)

0: Disable

1: Operate

0: Stop and clear
1: Run (Count up)

−
W
0
−
W
0

TA67M1

TMRA67
MODE
register

0

Double

1: Enable

111AH
(Prohibit
RMW)

0

TMRA45

1115H
(Prohibit
RMW)

1118H

0
TA4RUN

IDLE2

TA45M1

TMRA45
MODE
register

1

Double

1: Enable

TA4REG

2

TA45PRUN TA5RUN
R/W
0
0

TA67M0

0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode

PWM61

PWM60 TA7CLK1 TA7CLK0
R/W
0
0
0

TA6CLK1 TA6CLK0

Source clock for TMRA7

Source clock for TMRA6

00: TA6TRG
01: φT1
10: φT16
11: φT256

00: 32KHz clock
01: φT1
10: φT4
11: φT16

TA7FFC1 TA7FFC0
W
1
1
00: Invert TA7FF
01: Set TA7FF
10: Clear TA7FF
11: Don’t care

TA7FFIE TA7FFIS
R/W
0
0
TA7FF
TA7FF
control for inversion
inversion select
0: Disable 0: TMRA6
1: Enable 1: TMRA7

0
PWM cycle
00: Reserved
6
01: 2
7
10: 2
8
11: 2

111DH
(Prohibit
RMW)

92CZ26A-733

0

0

TMP92CZ26A

(15) 16-bit timer (1/2)
Symbol

TB0RUN

Name

TMRB0
RUN
register

Address

1180H

7

6

TB0RDE
R/W
0
Double
buffer
0: disable
1: enable

−
R/W
0
Always
write “0”.

−

−

3

2

I2TB0
R/W
0

TB0PRUN
R/W
0
TMRB0
prescaler

IDLE2
0: Stop

1

0
TB0RUN
R/W
0
Up
counter
(UC10)

0: Stop and clear
1: Run (Count up)

0
0
Always write “00”.

TMRB0
MODE
register

4

1: Operate

R/W

TB0MOD

5

1182H
(Prohibit
RMW)

TB0CP0I TB0CPM1 TB0CPM0 TB0CLE
W*
R/W
1
0
0
0
Control
Software Capture timing
Up
capture
00: Disable
control
INT6 occurs at rising counter
0: Execute
0:Clear
edge
1: Undefined
Disable
01: TB0IN0 ↑
1:Clear
INT6 occurs at rising
Enable

TB0CLK1

TB0CLK0

0

0

TMRB1 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16

edge

10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at falling
edge
11: TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge

−

−

TB0CT1

TB0C0T1 TB0E1T1
R/W
1
1
0
0
0
Always write “11”.
TB1FF0 inversion trigger
0: Disable trigger
*Always read as “11”.
1: Enable trigger
W*

TMRB0
Flip-Flop
control
register

1183H
(Prohibit
RMW)

TB0RG0L

16 bit timer
register 0
low

1188H
(Prohibit
RMW)

TB0RG0H

16 bit timer
register 0
high

1189H
(Prohibit
RMW)

TB0RG1L

16 bit timer
register low

118AH
(Prohibit
RMW)

TB0RG1H

16 bit timer
register 1
high

118BH
(Prohibit
RMW)

TB0CP0L

Capture
register 0
low

118CH

TB0CP0H

Capture
register 0
high

118DH

TB0CP1L

Capture
register 1
low

118EH

TB0CP1H

Capture
register 1
high

118FH

TB0FFCR

When
capture
UC10 to
TB0CP1H/L

TB0E0T1 TB0FF0C1 TB0FF0C0
W*
0
1
1
Control TB1FF0
00: Invert
01: Set
10: Clear
When UC10 When UC10 11: Don’t care

When
matches
matches
capture
with
with
UC10 to
* Always read as “11”.
TB0CP0H/L TB0RG1H/L TB0RG0H/L

−
W
0
−
W
0
−
W
0
−
W
0
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined

92CZ26A-734

TMP92CZ26A

(15) 16-bit timer (2/2)
Symbol

TB1RUN

Name

TMRB1
RUN
register

Address

1190H

7

6

TB1RDE
R/W
0
Double
buffer
0: disable
1: enable
−

3

2

I2TB1
R/W
0

TB1PRUN
R/W
0
TMRB0
prescaler

IDLE2
0: Stop

1

0
TB1RUN
R/W
0
Up
counter
(UC12)

0: Stop and clear
1: Run (Count up)
−

0
0
Always write “00”.

TMRB1
MODE
register

4

1: Operate

R/W

TB1MOD

5

−
R/W
0
Always
write “0”.

1192H
(Prohibit
RMW)

TB1CP0I TB1CPM1 TB1CPM0 TB1CLE
W*
R/W
1
0
0
0
Control
Software Capture timing
Up
capture
00: Disable
control
INT7 occurs at rising counter
0: Execute
0:Clear
edge
1:
Disable
01: TB1IN0 ↑
Undefined
1:Clear
INT7 occurs at rising
Enable

TB1CLK1

TB1CLK0

0

0

TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16

edge

10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at falling
edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge

−

−

TB1CT1

TB1C0T1 TB1E1T1 TB1E0T1 TB1FF0C1 TB1FF0C0
R/W
W*
1
1
0
0
0
0
1
1
Control TB1FF0
Always write “11”.
TB1FF0 inversion trigger
00: Invert
0: Disable trigger
*Always read as “11”.
01: Set
1: Enable trigger
10: Clear
When UC12 When UC12 11: Don’t care
When
When
matches
matches
capture
capture
* Always read as “11”.
W*

TB1FFCR

TMRB1
Flip-Flop
control
register

1193H
(Prohibit
RMW)

with
with
UC12 to
UC12 to
TB1CP1H/L TB0CP0H/L TB1RG1H/L TB1RG0H/L

TB1RG0L

16 bit timer
register 0
low

1198H
(Prohibit
RMW)

TB1RG0H

16 bit timer
register 0
high

1199H
(Prohibit
RMW)

TB1RG1L

16 bit timer
register low

119AH
(Prohibit
RMW)

TB1RG1H

16 bit timer
register 1
high

119BH
(Prohibit
RMW)

TB1CP0L

Capture
register 0
low

119CH

TB1CP0H

Capture
register 0
high

119DH

TB1CP1L

Capture
register 1
low

119EH

TB1CP1H

Capture
register 1
high

119FH

−
W
0
−
W
0
−
W
0
−
W
0
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined

92CZ26A-735

TMP92CZ26A

(16) UART/Serial channels
Symbol

Name

SC0BUF

Serial
channel 0
buffer
register

SC0CR

Serial
channel 0
control
register

Address
1200H
(Prohibit
RMW)

1201H
(Prohibit
RMW)

7

6

5

RB7
TB7

RB6
TB6

RB5
TB5

4

3

2

RB4
RB3
RB2
TB4
TB3
TB2
R (Receive) /W (Transmission)
Undefined
RB8
EVEN
PE
OERR
PERR
FERR
R
R/W
R (Cleared to 0 when read)
Undefined
0
0
0
0
0
1: Error
Received Parity
Parity
data bit8
addition
Overrun
Parity
Framing
0: Odd
0: Disable
1: Even
1: Enable
TB8

CTSE

RXE

WU

SM1

SM0

1

0

RB1
TB1

RB0
TB0

SCLKS

IOC
R/W

0
0
0: SCLK0↑ 0:baud
1: SCLK0↓ rate
generator
1: SCLK0
pin input
SC1

SC0

R/W

SC0MOD0

Serial
channel 0
mode 0
register

1202H

0
0
Transfer 0: CTS
data bit 8
disable
1: CTS
enable

−

BR0CR

Serial
channel 0
baud rate
control
register

BR0ADD

Serial
channel 0
K setting
register

SC0MOD1

Serial
channel 0
mode 1
register

1203H

0
Always
write “0”.

BR0K3

BR0K1
BR0K0
R/W
0
0
0
0
Sets frequency divisor “K” (1~F)

1204H

1205H

I2S0
R/W
0
IDLE2
0: Stop
1: Run
PLSEL

SIRCR

IrDA
control
register

0
0
0
0
0
0
Receive
Wake up 00: I/O interface Mode 00: TA0TRG
function
0: Disable 01: 7-bit UART Mode 01: Baud rate generator
0: Receive 1: Enable 10: 8-bit UART Mode 10: Internal clock φ1
disable
11: 9-bit UART Mode 11: External clock
(SCLK0 input)
1: Receive
enable
BR0ADDE BR0CK1 BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
R/W
0
0
0
0
0
0
0
(16−K) /16 00: φT0
Divided frequency “N” setting
division
01: φT2
0~F
0: Disable 10: φT8
1: Enable 11: φT32

1207H

0
Select
transmit
pulse
width
0: 3/16
1: 1/16

BR0K2

FDPX0
R/W
0
Duplex
0: Half
1: Full
RXSEL

TXEN

SIRWD3 SIRWD2 SIRWD1
SIRWD0
R/W
0
0
0
0
0
0
0
Receive
Transmit Receive
Select receive pulse width
data
0: Disable 0: Disable Set the valid SIRR×D pulse width for equal or
0:“H” pulse 1: Enable 1: Enable more than
2x × (setting value + 1) + 100ns
1: “L” pulse
Can be set: 1~14
Can not be set: 0, 15

92CZ26A-736

RXEN

TMP92CZ26A
(17) SBI
Symbol

Name

Address

7

6

BC2

SBICR1

SBIDBR

Serial bus
interface
control
register 1

SBI
buffer
register

5

BC1

4

BC0

R/W
1240H
(Prohibit
RMW)

1241H
(Prohibit
RMW)

0

0

0

DB6

ACK

−

R/W

R

0

1

2
SCK2

1

0

SCK1

SCK0
/SWRMON

R/W
0

R/W
0

0/1

Acknowledge Always
Setting for the divisor value “n”
read as “1”.
mode
(When writing)
specification
000: 4
001: 5
010: 6

Number of transfer bits
000: 8
001: 1
010: 2
011: 3
100: 4
101: 5
110: 6
111: 7
DB7

3

0: Disable
1: Enable

DB5

011: 7
110: 10

DB4

DB3

100:8
101: 9
111: (Reserved)

DB2

DB1

DB0

SA2

SA1

SA0

ALS

0

0

0

R (receive)/W (Transmit)
Undefined
SA6

SA5

SA4

SA3
R/W

I2CAR

I2C BUS
Address
register

1242H
(Prohibit
RMW)

0

0

0

0

0
Address
recognition

Slave Address setting

0: Enable
1: Disable

SBISR
When
read

Serial bus
interface
status
register
1243H
(Prohibit
RMW)

MST

TRX

BB

PIN

R/W

R/W

R/W

R/W

R/W

0

0

0

1

0

SBIBR0

SBICR0

Serial bus
interface
control
register 0

0: Receiver

1: Busy

1: Cancel

Start/Stop
condition

Cancel
INTSBI
interrupt
request

Serial bus interface
operation mode selection

0:Don’t care

10: I2C bus mode

1:Cancel
interrupt
request

11: (Reserved)

1:Master

Arbitration
Slave
lost detection Address
monitor
match
detection
0: −
monitor
1: Detected
0: Undetected

1:

−

I2SBI

W

R/W
0

−

−

00: Port mode
01: (Reserved)

−

−

Software reset generate
write “10” and “01”, then an
internal reset signal is
generated.

−

R
1

1

IDLE2
0: Stop
1: Operate

−

0: “0”
0: Undetected 1: “1”
1: Detected

1: Detected

1

−

−

−

−
R/W

1

1

Always read as “1”.

R/W
0

Last receive
bit monitor

0: Request

1: Busy
condition

1247H
(Prohibit
RMW)

0

General call
detection
monitor

0: Free

0:Slave

SBIEN

R/W

0

monitor

/ Receiver

monitor

0
Always
read “0”

R/W

0

status

Slave status

0: Stop
condition

1244H
(Prohibit
RMW)

R/W

INTSBI
request
monitor

Transmitter

Serial bus
interface
control
register 2

Serial bus
interface
baud rate
register 0

LRB/
SWRST0

I C bus
status
monitor

Master/

Transmitter

SBICR2
When
write

2

AD0/
SWRST1

AL/SBIM1 AAS/SBIM0

0
Always
write “0”.

−

−

−

0

0

0

R
0

0

0

SBI
operation
0:disable
1:enable

0
Always read as “0”.

92CZ26A-737

TMP92CZ26A
(18) AD converter (1/3)
Symbol

ADREG0L

Name
AD
conversion
result
register 0 low

AD
conversion
ADREG0H
result
register 0 high

Address

12A0H

12A1H

7

6

ADR01

ADR00

R
0
0
Store Lower 2 bits of
AN0 AD conversion
result
ADR09
ADR08

ADREG1L

AD
conversion
ADREG1H
result
register 1 high

0

0

ADREG2L

AD
conversion
ADREG2H
result
register 2 high

ADREG3L

AD
conversion
ADREG3H
result
register 3 high

ADREG4L

AD
conversion
result
register 4
low

AD
conversion
ADREG4H
result
register 4high

12A2H

12A3H

ADREG5L

AD
conversion
ADREG5H
result
register 5 high

ADR07

ADR06

ADR05

ADR04

12A5H

ADR17

ADR16

0

0

ADR15

ADR14

0
0
0
0
Store Upper 8 bits of an AN1 conversion result

ADR20

0
0
Store Lower 2 bits of
AN2 AD conversion
result
ADR29
ADR28
0

0

ADR27

ADR26

ADR25

ADR24

0
0
0
0
Store Upper 8 bits of an AN2 conversion result

0
0
Store Lower 2 bits of
AN3 AD conversion
result

12ABH

OVR1
R
0

ADR1RF
R
0

ADR13

ADR12

0

0

OVR2
R
0

ADR2RF
R
0

ADR23

ADR22

0

0

OVR3
R
0

ADR3RF
R
0

ADR38

AD conversion
result store flag

0:No generate
1: Generate
1: Stored

ADR37

ADR36

ADR35

ADR34

ADR33

ADR32

0

0

OVR4
R
0

ADR4F
R
0

R
0

0

0
0
0
0
Store Upper 8 bits of an AN3 conversion result

ADR4

0
0
Store Lower 2 bits of
AN4 AD conversion
result
ADR49
ADR48

Overrun flag
0:No generate
1: Generate

ADR47

ADR46

ADR45

ADR44

AD conversion
result store flag
1: Stored

ADR43

ADR42

0

0

OVR5
R
0

ADR5F
R
0

R
0

0

0
0
0
0
Store Upper 8 bits of an AN4 conversion result

ADR5
R

12AAH

0

Overrun flag

R

12A9H

0

Overrun flag
AD conversion
0:No generate result store flag
1: Generate
1: Stored

ADR30

ADR4
12A8H

ADR02

R

ADR39
12A7H

ADR03

R

R
12A6H

0
ADR0RF
R
0

Overrun flag
AD conversion
0:No generate result store flag
1: Generate
1: Stored

R
12A4H

1
OVR0
R
0

Overrun flag
AD conversion
0:No generate result store flag
1: Generate
1: Stored

0
0
0
0
Store Upper 8 bits of an AN0 conversion result

0
0
Store Lower 2 bits of
AN1 AD conversion
result
ADR19
ADR18

ADR5
AD
conversion
result
register 5 low

2

ADR10

ADR31
AD
conversion
result
register 3 low

3

R

ADR21
AD
conversion
result
register 2 low

4

R

ADR11
AD
conversion
result
register 1 low

5

0
0
Store Lower 2 bits of
AN5 AD conversion
result
ADR59
ADR58

Overrun flag
0:No generate
1: Generate

ADR57

ADR56

ADR55

ADR54

AD conversion
result store flag
1: Stored

ADR53

ADR52

0

0

R
0

0

0
0
0
0
Store Upper 8 bits of an AN5 conversion result

92CZ26A-738

TMP92CZ26A
(18) AD converter (2/3)
Symbol

ADREGSPL

ADREGSPH

ADCM0REGL

Name
High priority
Conversion
Register SP
low

High priority
Conversion
Register SP
high
AD
Conversion
Result
Compare
Criterion
Register 0
Low

AD
Conversion
Result
ADCM0REGH Compare
Criterion
Register 0
High

ADCM1REGL

AD
Conversion
Result
Compare
Criterion
Register 1
Low

AD
Conversion
Result
Compare
ADCM1REGH
Criterion
Register 1
High

ADCCLK

AD
Conversion
Clock
Setting
Register

Address

7

6

ADRSP1

ADRSP0

5

4

3

2

R
12B0H

0

0

0
ADRSPRF

R

R

0
Overrun
1: Generate

Store Lower 2 bits of an
AD conversion result

ADRSP9

1
OVSRP

ADRSP8

ADRSP7

ADRSP6

0
AD conversion
result store flag
1: Stored

ADRSP5

ADRSP4

ADRSP3

ADRSP2

0

0

0

0

R

12B1H
0

0

0

0

Store Upper 8 bits of an AD conversion result
ADR21

ADR20
R/W

12B4H

0

0

Store Lower 2 bits of an
AD conversion result
compare criterion

ADR29

ADR28

ADR27

ADR26

ADR25

ADR24

ADR23

ADR22

0

0

0

0

R/W
12B5H

0

0

0

0

Store Upper 8 bits of an AD conversion result compare criterion
ADR21

ADR20
R/W

0

0

12B6H
Store Lower 2 bits of an
AD conversion result
compare criterion

ADR29

ADR28

ADR27

ADR26

ADR25

ADR24

ADR23

ADR22

0

0

0

0

R/W
0

0

0

0

12B7H
Store Upper 8 bits of an AD conversion result compare criterion

−

ADCLK2

ADCLK1

ADCLK0

R/W

R/W

R/W

R/W

0

0

0

0

Always
write “0”

12BFH

92CZ26A-739

Select clock for AD conversion
000 : Reserved 100 : fIO/4
101 : fIO/5
001 : fIO/1
110 : fIO/6
010 : fIO/2
111 : fIO/7
011 : fIO/3

TMP92CZ26A
(18) AD converter (3/3)
Symbol

Name

Address

7

6

4

3

2

1

0

EOS

BUSY

5

I2AD

ADS

HTRGE

TSEL1

TSEL0

0

0

0

0

0

R
0

ADMOD0

AD mode
control
register 0

12B8H

Normal AD
conversion
end flag
0:During
conversion
sequence
or before
starting
1:Complete
conversion
sequence

R/W

Normal AD
conversion
BUSY Flag

AD conversion Start Normal
when
AD conversion
IDLE2 mode 0: Don’t Care
1:Start
0: Stop
AD conversion
1: Operate
Always read
as”0”.

0:Stop
conversion
1:During
conversion

DACON

ADCH2

ADCH1

ADCH0

0

0

0

0

LAT

0
Normal AD
conversion at
Hard ware
trigger
0: Disable
1: Enable

ITM

Select Hard ware trigger
00: INTTB00 interrupt
01: Reserved
10: ADTRG
11: Reserved

REPEAT

SCAN

R/W

ADMOD1

AD mode
control
register 1

12B9H

DAC and VREF Analog input channel select
application
control

HEOS

0
Latency
0: No Wait
1:Start after
reading
conversion
result store
Register of
last channel

0

HBUSY

HADS

HHTRGE

0

0

0

0

High-priority
AD conversion
sequence
FLAG
0: During
conversion
sequence
or before
starting
1: Complete
conversion
sequence

High-priority AD
conversion
BUSY Flag

Start
High-priority
AD conversion
0: Don’t Care
1: Start AD
conversion

High-priority
AD conversion
at Hard ware
trigger
0: Disable
1: Enable

−

HADCH2

0

0

R

ADMOD2

ADMOD3

AD mode
control
register 2

AD mode
control
register 3

12BAH

0

Interrupt
specification
when
conversion
channel fixed
repeat mode

0

Repeat mode
specification
0: Single
conversion
1: Repeat
conversion

HTSEL1

Always
write “0”.

CMEN1

HTSEL0

R/W

0:Stop
conversion
1:During
conversion

0

0

Select Hard ware trigger
00: INTTB10 interrupt
01: Reserved
10: ADTRG
11: I2S Sampling Counter
Output

Always read
as”0”.

HADCH1

−

HADCH0

R/W
12BBH

Scan mode
specification
0: Channel
fixed mode
1: Channel
scan mode

R/W
0

0

High-priority analog input channel
select
CMEN0

CMP1C

CMP0C

Always
write “0”.

IRQEN1

IRQEN0

0

0

CMPINT1 CMPINT0

R/W
0

ADMOD4

AD mode
control
register 4

12BCH

0

0

0

Generation

Generation

AD monitor

AD monitor

Status of

function0

condition of

condition of

function

function

monitor

monitor

0: Disable

0: Disable

AD monitor

AD monitor

interrupt 1

interrupt 0

function

function

1: Enable

1: Enable

function

function

0: Disable

0: Disable

interrupt 1

interrupt 0

interrupt 1

interrupt 0

1: Enable

1: Enable

0: No

0: No

0: less than

0: less than

(Note)

(Note)

generation

generation

1: Generation

1: Generation

CM0CH1

CM0CH0

CMCH2

CM1CH1

AD

or Equal

CM1CH0

CM0CH2

0

0

R/W
0
12BDH

AD Status of

AD Monitor

function1

or Equal

ADMOD5

0

AD Monitor

1: Greater than 1: Greater than

AD mode
control
register 5

0

0

R/W

Select analog channel for AD monitor function 1
000: AIN0
100: AN4
001: AIN1
101: AN5
010: AIN2
110: Reserved
011: AN3
111: Reserved

92CZ26A-740

0

0

Select analog channel for AD monitor function
1
000: AIN0
100: AN4
001: AIN1
101: AN5
010: AIN2
110: Reserved
011: AN3
111: Reserved

TMP92CZ26A

(19) Watchdog timer
Symbol

Name

Address

7

6

5

WDTE

WDTP1

WDTP0

4

3

2

1

0

I2WDT

RESCR

−

R/W
WDMOD

WDCR

WDT
mode
register

WDT
control
register

1300H

1301H
(Prohibit
RMW)

1
WDT
control
1: Enable

R/W

0
0
Select detecting time
15
00: 2 /fIO
17
01: 2 /fIO
19
10: 2 /fIO
21
11: 2 /fIO
−
W
−
B1H: WDT disable code

92CZ26A-741

0
IDLE2
0: Stop
1: Operate

4E: WDT clear code

0
1:Internally
connects
WDT out to
the reset pin

0
Always
write “0”.

TMP92CZ26A

(20) RTC (Real-Time Clock)
Symbol
SECR

MINR

HOURR

Name
Second
register

Minute
register

Hour
register

Address

7

6

5

4

SE6

SE5

SE4

“0” is read

40 sec.
MI6

20 sec.
MI5

10 sec.
MI4

“0” is read

40 min.

20 min.
HO5

10 min.
HO4

20 hours
(PM/AM)

10 hours

1320H

1321H

1322H
“0” is read

DAYR

Day
register

Date
register

DA4

1324H
“0” is read

20 days

10 days
MO4

1325H

MONTHR

Month
register

PAGE0
PAGE1

“0” is read

YE7

YE6

PAGER

Year
register

Page
register

PAGE0
PAGE1

80 years

40 years

10 month
“0” is read

YE5

1326H

YEARR

1327H
(Prohibit
Interrupt
RMW)

DIS1HZ
1328H
(Prohibit
RMW)

0: 1 Hz

DA3

1

0

SE1

SE0

2 sec.
MI1

1 sec.
MI0

2 min.
HO1

1 min.
HO0

4 hours

2 hours

1 hour

WE2

WE1
R/W
Undefined
W1
DA1

WE0

2 days
MO1

1 day
MO0

W2
DA2

R/W
Undefined
8 days
4 days
MO3
MO2
R/W
Undefined
8 month
4 month

YE2

4 years

ADJUST ENATMR ENAALM
W
R/W
Undefined
Undefined
“0” is read

1: Adjust

DIS16HZ

RSTTMR

0: 16 Hz

1:Clock
reset

RSTALM

TIMER

ALARM

1: Enable

1: Enable

0: Disable

0: Disable

RE3
W
Undefined
1: Alarm
reset

92CZ26A-742

2 month

W0
DA0

1 month
0: Indicator
for 12
hours
1: Indicator
for 24
hours

YE4

0: Disable

RESTR

8 hours

YE3
R/W
Undefined
20 years 10 years
8 years
“0” is read

INTENA
R/W
0

1: Enable

Reset
register

2

1323H
“0” is read
DA5

DATER

3

SE3
SE2
R/W
Undefined
8 sec.
4 sec.
MI3
MI2
R/W
Undefined
8 min.
4 min.
HO3
HO2
R/W
Undefined

RE2

YE1

YE0

2 years
1 year
Leap year setting
00: Leap year
01: One year after
10: Two years after
11: Three years after
PAGE
R/W
Undefined
“0” is
read.
RE1

Always write “0”

PAGE
selection

RE0

TMP92CZ26A

(21) Melody/alarm generator
Symbol
ALM

Name
Alarmpattern
register

Address

1330H

7

6

5

4

3

2

1

0

AL8

AL7

AL6

AL5

AL4

AL3

AL2

AL1

0

0

0

0

0

0

0

0

−

−

−

MELALM

0

0

0

0
Output
frequency
0: Alarm
1: Melody

ML1

ML0

0

0

ML9

ML8

0

0

R/W
Alarm pattern setting
FC1

FC0

−

ALMINV

R/W

MELALMC

MELFL

Melody/
alarm
control
register

Melody
frequency
L-register

1331H

1332H

0
0
Free run counter
control
00: Hold
01: Restart
10: Clear
11: Clear and start
ML7
ML6

0
Alarm
frequency
invert
1: Invert

0

ML5

ML4

MELFH

1333H

0

0

0

ALMINT

1334H

ML2

0
0
0
Melody frequency set (Low 8bit)
ML11
ML10
R/W

0
Melody
counter
control
0: Stop
and
clear
1: Start

0

0

Melody frequency set (Upper 4 bits)

−

Alarm
interrupt
enable
register

ML3
R/W

MELON
R/W
Melody
frequency
H-register

Always write “0”.

0
Always
write “0”.

IALM4E

IALM3E
IALM2E
R/W

IALM1E

IALM0E

0

0

0

0

0

1:INTALM4

1:INTALM3

1:INTALM2

1:INTALM1

1:INTALM0

(1Hz)

(2Hz)

(64Hz)

(512Hz)

(8192Hz)

enable

enable

enable

enable

enable

92CZ26A-743

TMP92CZ26A
(22) I2S (1/2)
Symbol

Name

Address

15

14

13

12

11

10

9

8

B015

B014

B013

B012

B011

B010

B009

B008

7

6

5

4

3

2

1

0

B007

B006

B005

B004

B003

B002

B001

B000

W
Undefined
I2S

I2S0BUF

Transmission
Buffer

Transmission buffer register (FIFO)

1800H

(Prohibit
RMW)

Register0

31

30

29

28

27

26

25

24

B031

B030

B09

B028

B027

B026

B025

B024

23

22

21

20

19

18

17

16

B023

B022

B021

B020

B019

B018

B017

B016

W
Undefined
Transmission buffer register (FIFO)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

B115

B114

B113

B112

B111

B110

B109

B108

B107

B106

B105

B104

B103

B102

B101

B100

W
Undefined

I2S

I2S1BUF

Transmission
Buffer
Register1

1810H

(Prohibit
RMW)

Transmission buffer register (FIFO)

31

30

29

28 27

26

25

24

23

22

21

20

19

18

17

16

B131

B130

B129

B128

B126

B125

B124

B123

B122

B121

B120

B119

B118

B117

B116

B127

W
Undefined
Transmission buffer register (FIFO)

92CZ26A-744

TMP92CZ26A

(22) I2S (2/2)
Symbol

Name

Address

1808H

I2S0CTL

I2S
Control
Register0

1809H

7

6

4

3

TXE0

*CNTE0

DIR0

BIT0

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

Transmit
0: Stop
1: Start

I2S0C

180AH

1819H

I2S1C

0
System
clock
0:Disable
1:Enable

TEMP0

WLVL0

EDGE0

CLKE0

R

R/W

R/W

R/W

0

0

1

0

0

Stereo
Condition of WS level
/monaural transmission
FIFO
0: Stereo
0:low left
0: data
1: Monaural
1:high left
1: None
data

Source
clock
0: fSYS
1: fPLL

CK06

CK05

CK04

CK03

CK02

Clock
edge for
data
output
0:Rising
1:Falling

0
Clock
enable
(After transmission)
0:Operate
1:Stop

CK01

CK00

0

0

WS01

WS00

R/W
0

0

0
0
0
0
Divider value for CK signal (8-bit counter)
WS04

WS03

WS02
R/W

0

0
0
0
0
Divider value for WS signal (6-bit counter)

TXE1

*CNTE1

DIR1

BIT1

R/W

R/W

R/W

R/W

0

0

Transmit
0: Stop
1: Start

0
Counter
control
0: Clear
1: Start

0

DTFMT11 DTFMT10 SYSCKE1

Transmis Bit length
sion start
BIT
0: 8 bits
0:MSB
1:16 bits
1:LSB

R/W

R/W

0

0

Output format
00: I2S
10:
Right
01: Left
11:Reserved

R/W
0
System
clock
0:Disable
1:Enable

CLKS1

FSEL1

TEMP1

WLVL1

EDGE1

CLKE1

R/W

R/W

R

R/W

R/W

R/W

0

0

1

0

0

0

Condition of WS level
Stereo
/monaural transmission
FIFO
0:low left
0: Stereo
1:high left
1: Monaural 0: data
1: None
data

Source
clock
0: fSYS
1: fPLL

CK16

CK15

CK14

CK13

CK12

Clock
edge for
data
output
0:Rising
1:Falling

Clock
enable
(After transmission)
0:Operate
1:Stop

CK11

CK10

0

0

WS11

WS10

R/W
0

0

0
0
0
0
Set divide frequency for CK signal (8-bit counter)
WS15

181BH

Output format
00: I2S
10: Right
01: Left
11:Reserved

R/W

R/W

CK17
181AH

0

FSEL0

180BH

I2S
Control
Register1

1

R/W

0

I2S1
Divider
Value
Setting
Register

Transmis Bit length
sion start
BIT
0: 8 bits
0:MSB
1:16 bits
1:LSB

WS05

1818H

I2S1CTL

Counter
control
0: Clear
1: Start

2

DTFMT01 DTFMT00 SYSCKE0

CLKS0

CK07
I2S0
Divider
Value
Setting
Register

5

WS14

WS13

WS12
R/W

0

0
0
0
0
Set divided frequency for WS signal (6-bit counter)

92CZ26A-745

0

TMP92CZ26A
(23) MAC (1/2)
Symbol
MACMA_LL

MACMA_LH

MACMA_HL

MACMA_HH

MACMB_LL

MACMB_LH

MACMB_HL

MACMB_HH

Name
Data
register
Multiplier
A-LL
Data
register
Multiplier
A-LH
Data
register
Multiplier
A-HL
Data
register
Multiplier
A-HH
Data
register
Multiplier
B-LL
Data
register
Multiplier
B-LH
Data
register
Multiplier
B-HL
Data
register
Multiplier
B-HH

Address

Multiply and
Accumulate

6

5

4

3

2

1

0

MA6

MA5

MA4

MA3

MA2

MA1

MA0

MA10

MA9

MA8

MA17

MA16

MA25

MA24

MB2

MB1

MB0

MB10

MB9

MB8

MB17

MB16

MB25

MB24

OR1

OR0

OR9

OR8

OR17

OR16

OR25

OR24

R/W

1BE0H

Undefined
Multiplier A data register [7:0]
MA15

MA14

Accumulate

Multiplier A data register [15:8]
MA22

Accumulate

Accumulate
-LHH

MA18

Undefined
MA31

MA30

MA29

MA28

MA27

MA26

R/W

1BE3H

Undefined
Multiplier A data register [31:24]
MB7

MB6

MB5

MB4

MB3
R/W

1BE4H

Undefined
Multiplier B data register [7:0]
MB15

MB14

MB13

MB12

MB11
R/W

1BE5H

Undefined
Multiplier B data register [15:8]
MB23

MB22

MB21

MB20

MB19

MB18

R/W

1BE6H

Undefined
Multiplier B data register [23:16]
MB31

MB30

MB29

MB28

MB27

MB26

R/W

1BE7H

Undefined
Multiplier B data register [31:24]
OR7

OR6

OR5

OR4

OR3

OR2

R/W

1BE8H

Undefined
Multiply and Accumulate data register [7:0]
OR15

OR14

OR13

OR12

OR11

OR10

R/W

1BE9H

Undefined
Multiply and Accumulate data register [15:8]
OR23

OR22

OR21

OR20

OR19

OR18

R/W

1BEAH

Undefined
Multiply and Accumulate data register [23:16]
OR31

Data register
Multiply and

MA19

Multiplier A data register [23:16]

-LGL

MACOR_LHH

MA20

1BE2H

Data register

MACOR_LHL

MA21

R/W

-LLH

Multiply and

MA11
R/W

MA23

Data register
Multiply and

MA12

Undefined

-LLL

MACOR_LLH

MA13

1BE1H

Data register

MACOR_LLL

7
MA7

1BEBH

OR30

OR29

OR28

OR27
OR26
R/W
Undefined
Multiply and Accumulate data register [31:24]

92CZ26A-746

TMP92CZ26A
(23) MAC (2/2)
Symbol

Name
Data register

MACOR_HLL

Multiply and
Accumulate

7

6

5

4

3

2

1

0

OR39

OR38

OR37

OR36

OR35

OR34

OR33

OR32

OR41

OR40

OR49

OR48

OR57

OR56

Address

R/W

1BECH

Undefined

-HLL

Multiply and Accumulate data register [39:32]
OR47

Data register

MACOR_HLH

Multiply and
Accumulate

OR46

Accumulate

Multiply and Accumulate data register [47:40]
OR54

Accumulate

MACCR

OR52

OR51

OR50

R/W
Undefined
Multiply and Accumulate data register [55:48]
OR63

OR62

MOVF

MOPST

R/W
0

W
0

Over flow

Select the trigger of start calculation

Sign

Calculation

flag

Start
calculation

000: Write to MACMA[7:0]

mode

Mode

0:no

control

001: Write to MACMB[7:0]

0:Unsigned

00: 64 + 32 × 32

over flow

1:Signed

01: 64 − 32 × 32

1:generate

0:don’t care 010: Write to MACMOR[7:0]
1: Start
011: Write to MACMOR[39:32]

over flow

calculation

1BEFH

-HHH

MAC
Control
Register

OR53

1BEEH

Data register

MACOR_HHH

OR42

R/W

-HHL

Multiply and

OR43

Undefined
OR55

Data register

MACOR_HHL

OR44

1BEDH

-HLH

Multiply and

OR45

1BFCH

OR61

OR60

OR59
OR58
R/W
Undefined
Multiply and Accumulate data register [63:56]
MSTTG2

MSTTG1

0

1xx: Write “1” to 

92CZ26A-747

MSTTG0

MSGMD

0

R/W
0

R/W
0

MOPMD1 MOPMD0
R/W
0

10: 32 × 32 − 64
11: Reserved

0

TMP92CZ26A

6.

Package
P-FBGA228-1515-0.80A5

TOP VIEW

BOTTOM VIEW

92CZ26A-748
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : Yes
Encryption                      : Standard V1.2 (40-bit)
User Access                     : Print, Copy, Fill forms, Extract, Assemble, Print high-res
XMP Toolkit                     : 3.1-702
Modify Date                     : 2005:12:12 10:05:32+09:00
Create Date                     : 2005:12:09 13:16:22+09:00
Metadata Date                   : 2005:12:12 10:05:32+09:00
Creator Tool                    : Word 用 Acrobat PDFMaker 7.0.5
Format                          : application/pdf
Title                           : TMP92CZ26AXBG_ETD_rev0.2.pdf
Creator                         : TOSHIBA CORPORATION Semiconductor Company
Document ID                     : uuid:cffc1ff4-5569-44de-bc17-d57e72caabed
Instance ID                     : uuid:524ece3e-0f8f-4726-8fd2-0968bccb9711
Producer                        : Acrobat Distiller 7.0.5 (Windows)
Page Count                      : 751
Author                          : TOSHIBA CORPORATION Semiconductor Company
EXIF Metadata provided by EXIF.tools

Navigation menu