Toshiba Tlp510E Technical Training Manual TLP511

TLP511E 9b1e6ba1-369d-4426-ae4e-9fa939baf5c1

2014-12-13

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FILE NO. 336-9707

TECHNICAL TRAINING MANUAL

3 LCD DATA PROJECTOR

TLP511U
TLP510U
TLP511E
TLP510E

PRINTED IN JAPAN, Nov., 1997 S

CONTENTS
1. MAIN POWER SUPPLY
CIRCUIT ..................................... 1-1
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.

6. DIGITAL CIRCUIT ................... 6-1
6-1. Outline ........................................................ 6-1
6-2. Each IC Description .................................. 6-3

Description ................................................. 1-1
Output Control .......................................... 1-1
Voltage Switching ...................................... 1-1
Over-voltage Protection ............................ 1-1
Over-current Protection ........................... 1-2
Overheat Protection .................................. 1-2

7. VIDEO SIGNAL PROCESS
CIRCUIT ..................................... 7-1
7-1.
7-2.
7-3.
7-4.
7-5.

2. LAMP POWER SUPPLY
CIRCUIT (LAMP DRIVER) ..... 2-1

Circuit Component .................................... 7-1
Input Signal Switch Section ...................... 7-3
Video Demodulation Block ....................... 7-5
RGB Signal Amplification Section ......... 7-12
Microprocessor Interface ....................... 7-14

2-1. Configuration ............................................. 2-1

3. OPTICAL SYSTEM ................... 3-1

8. CCD CAMERA CIRCUIT
(For TLP511) ............................... 8-1

3-1. Configuration ............................................. 3-1

8-1. Outline ........................................................ 8-1

4. R.G.B. DRIVE CIRCUIT ........... 4-1
4-1. Outline ........................................................ 4-1
4-2. Operation Description .............................. 4-3

9. FLUORESCENT LAMP
INVERTER CIRCUIT
(For TLP511) ............................... 9-1

5. MICROPROCESSOR ................ 5-1

9-1. Operation Description .............................. 9-1
9-2. Troubleshooting ......................................... 9-2
9-3. Circuit Diagram......................................... 9-3

5-1.
5-2.
5-3.
5-4.
5-5.
5-6.

System Outline ........................................... 5-1
System Microprocessor ............................. 5-3
Power Supply Reset Process ..................... 5-4
Non-volatile Memory Process .................. 5-4
Remote Control Reception Process.......... 5-4
RS-232C Transmission/
Reception Process ...................................... 5-4
5-7. Status Read Process .................................. 5-4
5-8. Status Display Process .............................. 5-5
5-9. On-screen Display Process ........................ 5-5
5-10. Video System Control Process .................. 5-6
5-11. Panel System Control Process .................. 5-6
5-12. Drive System Control Process .................. 5-7
5-13. Various Display Modes ............................. 5-7
5-14. Applicable Signal ....................................... 5-8
5-15. RS-232C Control Method ......................... 5-9

1. MAIN POWER SUPPLY CIRCUIT

1-3. Voltage Switching

1-1. Description

When the voltage switching terminal of connector C
opens, pin 1 develops low, since the pin 2 of IC401 is 6V,
higher than pin 2 (3V), the voltage adjusted to 16.3V is
directly developed from IC201, since the status of Q205
turns off. When the voltage switching terminal develops
ground potential, since pin 2 of IC401 develops 0V and
the voltage of pin 2 develops low, pin 1 develops high,
Q205 turns on, voltage-set-up resistor of R201 is shortcircuited and the voltage of IC201 rises from 16.3V to
18.0V.

This power supply boosts up at boost-up-converter just
after bridge-rectifying AC input voltage, supplies the
voltage smoothed to DC 350V to the lamp output. Then
current resonance DC-DC converter which uses the DC
350V as an input converts the voltage and supplies S6V,
+6V, +10V, +13V, +15.5V and –12V.
The boost-up-converter control IC, IC301, stabilizes AC
rectified voltage to DC 350V. The current resonance DCDC converter, IC303, turns FET Q102 and Q103 “ON/
OFF” alternately using the drive transformer T103 and
converts the voltage to secondary side through the
converter transformer T101. At this time, the voltage of
S6V at the secondary side is detected by IC402, the
negative feedback to IC303 is carried out at photo
coupler PH301 and then the voltage is stabilized. Other
outputs are determined by the turn ratio of secondary
side of T101, and the voltage rectified, smoothed, but not
stabilized are stabilized through the series regulator.
(+10V is stabilized at IC203, +13V at IC202, +15.5V at
IC201.)

1-4. Over-voltage Protection
When the negative feedback circuit of current resonance
DC-DC converter is shut down, the secondary side
voltage control is unable to operate, the voltage begins to
develop high without any restriction. At this time, when
the voltage of S6V and +6V exceeds 8.5V, the base of
transistor Q401 is biased through the zener diode D201,
and turns on, and then the voltage higher than 7V is
added to pin 6 (OVP) of IC303 through the photo coupler
PH302. When the voltage higher than 7V is added to pin
6, IC303 is latched, all outputs are shut down. ( Boostup-converter stops simultaneously, too.)

The voltage rectified and smoothed by D105 and C113 at
primary winding of T101 is supplied as a VCC voltage of
IC301, IC302 and IC303 on primary side ICs, and also
the voltage rectified and smoothed by D106 and C114 is
supplied as a gate bias voltage of D306 TRIAC (triode
AC switch) which short-circuits the inrush current
limiting resistor R305. Therefore, when the electric
current resonance DC-DC converter stops to oscillate, the
VCC voltage is not supplied so that the boost-upconverter stops to operate.

When the voltage is added to +10V, +13V, +15.5V lines
from external side, (exceeding +15V for +10V line, 13V
for +13 line and 20V for +15.5V line), on each line
respectively through the zener diodes D202, D203 and
D204, the base voltage of Q401 is biased passing, IC303
is latched in the same way as the above-mentioned, all
outputs are shut down. When releasing the latch operation, stop to supply the commercial power supply and
then re-supply the commercial power after more than
approx. 120 seconds.

1-2. Output Control
When the output control 1 and 2 of connector A develops
low, the voltage of approx. 14V is added to Q203 gate
and pins 4 of IC203, IC201, and IC202 through R205
and R206 respectively, since the transistors Q201 and
Q202 turn off. In this case, Q204, IC201, IC202 and
IC203 turn off, the voltages of +6V, +10V, +15.5V and
+13V are not developed.
When the output control 1 and 2 develop high, the
transistors Q201 and Q202 turn on, so no voltage is
added to the gate Q203, IC201, IC202 and IC203,
described above, and the voltage of +6V, +10V, –15.5V
and +13V are developed.

1-1

1-5. Over-current Protection

In S6V and +6V lines, the voltage drop owing to the
current flowing in L203 is detected by pins 5 and 6 of
IC401, when the total current amount exceeds 8A, pin 7
develops high and the voltage biasses the base voltage of
transistor Q401 passing through the zener diode D402
and diode D401. In the same way as described in the
item of the over-voltage protection, IC303 is latched and
all outputs are shutdown. The method to release the latch
operation is the same as the item of the over-voltage
protection.

The over-current protection for lamp output detects the
voltage drop of the current detection resistor R113 at
between pins 9 and 10 of IC302. When voltage switching
terminal of connector C opens (at 16.3V), the photo
coupler PH303 turns off since pin 1 of IC401 develops
low and the voltage of drop voltage at R113 is directly
compared at pin 10 of IC302. When the lamp output
current is from 0.7 to 0.9A, pin 8 develops high and the
voltage higher than 7V is added to pin 6 of IC303. Then
IC303 is latched and all outputs are shut down.

Over-current protection at +10V, +13V, +15.5V lines are
carried out by the over-current protection characteristic
provided with the series regulator ICs (IC203, IC202 and
IC201). Refer to Fig. 1-5-1.

When the voltage switching terminal of connector C
develops the ground potential (at 18.0V), pin 1 of IC401
develops high, PH303 turns on and the voltage of drop
voltage at R113 and the voltage divided by R317 and
R327 are compared at pin 10 of IC302. When the lamp
output is from 1.05 to 1.35A, pin 8 of IC302 develops
high, IC303 is latched and all outputs are shut down. The
method to release the latch operation is the same as the
over-voltage protection description.

In this case, as only the line short-circuiting or overloading is protected, no effect appears on other outputs. The
protection is released by removing the over current
flowing condition.
When short-circuiting or overloading continues, the IC
overheats and the overheat protection circuit inside the
IC works to shut down the output voltage. In this case,
the overheat protection is released by unloading the
current and removing the overheat of IC.

1-6. Overheat Protection
As an overheat protection of the power supply, the
temperature of switching FET Q301 of the boost-upconverter is detected. Positive characteristic thermistor
TH301 for temperature detection is attached on the heat
sink of Q301. When Q301 is overheated owing to the
overload and/or defect of cooling fan, etc., the resistor
value of TH301 increases abruptly, while the surface
temperature exceeds approx. 120°C. Then the transistor
Q302 turns on, the voltage higher than 7V is added to the
pin 6 (OVP) of IC303, IC303 is latched and all outputs
are shut down.

Relative output voltage (%)

100

80
60
40
20
0

1.0
2.0
3.0
Output current Io (A)

When releasing the latch operation, stop to supply the
commercial power by canceling, cool enough after more
than approx. 120 seconds, and then re-supply the
commercial power.

4.0

Fig. 1-5-1

1-2

2. LAMP POWER SUPPLY CIRCUIT
(LAMP DRIVER)
2-1. Configuration
The lamp power supply cicrcuit receives a DC220 to
390V (primary side) from the system power supply and
provides a AC voltage (70 to 100VAC at ever turning on
the lamp) to turn on the lamp. Fig. 2-1-1 shows the block
diagram.
Lamp Driver
L1

L1
Commutator

Power
input

Stabilizer
R1

Igniter
L2

C1
Lamp
C2
Control

I122

I121

100nF

CB3
EMC GND
(optional)

Mains
isolated

CB2-1
SCI

CB2-2
Common

Flag

Fig. 2-1-1
The DC voltage is supplied to CB1 from the main power
supply unit through an interlock switch. This voltage
becomes AC input x 2Ö2 (= 340V for AC120V input)
when the lamp is off. CB2 is a connector for the lamp on
control signal input (SCI) and lamp off control signal
output (FLAG). When +5V is applied to SCI (CB2-1) in
the standby on, I122 FET transistor turns on, the igniter
develops a high voltage pulse (5 to 25 kV), and the lamp
starts to light up.

The pulse normally continues to be developed until the
lamp turns on (for max. 3s.). But if the lamp does not
turn on, I121 does not turn on, the voltage of CB2-3
develops high. I121 turns on and develops low after the
lamp turned on, the igniter circuit stops the operation.
Then the AC70 to 100V is applied to the lamp.

2-1

3. OPTICAL SYSTEM
3-1. Configuration
No.

Lamp
unit

Mirror
box
unit

UHP lamp

Light source of the optical system. AC lighting system 120W, arc length 1.3 mm.
As the arc length is shorter than the conventional metal halide lamp, the light source
operates as an ideal light point source and this improves the light convergence factor.
Also, the color temperature gets higher and this allows to reproduce more natural
white color.

Parabolic
reflector

Parabolic reflector converges light emitted from the UHP lamp forward in approximate
parallel light beams and illuminates the liquid crystal panel.

UV IR filter

Optical filter to pass necessary visible rays and cut unnecessary ultraviolet rays and
infrared rays among light emitted from the UHP lamp.

Multi-lenses
A, B

Two multi-lenses A and B allow a circular beam light emitted from the light source to
illuminate the square liquid crystal panel evenly, thus providing projected pictures
with less brightness variation.

Polarization
light beam
splitter (PBS)

Separates the illuminating light from the light source into P polarization light and S
polarization light and leads both light to the multi-lens B with a little angle.

Phase
difference
plate

Converts the polarization direction of incident light via the multi-lens B into another
direction. Here, P polarization light waveform separated by PBS is converted into
another S polarization light waveform.

Condenser
lens

Converges the illuminating light emitted from the light source into the liquid crystal
panel.

Dichroic
mirror

Separates the white light emitted from the light source into RGB three primary colors.
The white light emitted from the light source reflects B light using a dichroic mirror 1
and the RG lights pass through the dichroic mirror 1. Of the RG lights passed, G light
is reflected by the dichroic mirror 2 and R light passes.

Full reflection
mirror

Reflection mirror to lead the R and B lights separated by the dichroic mirrors 1 and 2
to the liquid crystal panel.

Field lens

Light transmitted through liquid crystal panel is converged in direction of focal point
and effectively entered entrance pupil of the projection lens.

Relay lens

In the R axis optical path which is longer than those of G, B, the relay lens works as
a correction lens to arrange the illumination distribution of the liquid crystal panel
surface with that of other liquid crystal panel.

Incident side
polarized
plate/Phase
difference
plate

The illumination lights separated into RGB have the S polarizing waveform component in processing the PBS and phase difference plate operation previously described.
The incident side polarized plate arranges the illumination light more effective direct
polarizing waveform. The phase difference plate used works to converge the S
polarizing waveform into the P polarizing waveform which fits to the transparent axis
of the liquid crystal panel.
Since the phase difference plate possesses the wavelength characteristics for light,
each RGB axis employs exclusive phase difference plate. These polarizing plates
and difference plates are constructed in one plate by attaching each other, and put
on a glass plate.
To increase the color purity ratio of three primary colors, the glass plate possess the
dichroic filter characteristics for RG axis.

Liquid crystal
panel

Light exit side polarized plate is put on the light exit plane. When no signal voltage is
applied, the polarization direction of transmission light rotates by 90 degrees. When a
voltage is applied, the polarization direction is controlled owing to the voltage
applied. That is, the liquid crystal panel employs such general TN type liquid crystal.
In this model, the incidence/exit polarization plate is placed (in normally white mode)
so that the light transmission amount becomes maximum (white) when no voltage is
added and the light transmission amount becomes minimum (black) when maximum
voltage is added.
According to the liquid crystal panel specification, exclusive panel for each RGB axis
is employed and shown by identification seals.

Cross prism

Works to mix RGB lights passed through the liquid crystal panel.

Projection
lens

Demodulated by the video signal on the liquid crystal panel and projects pictures
displayed on the liquid crystal at a screen. Light axis of the projection lens is set at
upper side of center of the liquid crystal panel and this realizes easy viewing of the
panel because the projected screen position is upper than the unit position. The
projected light shows S polarizing waveform and is compatible with the polarizing
screen.
The projection lens employs the zoom & focus system and allows to project enlarging
a picture upto maximum approx. 300 inch.

Prism
unit

Projection
lens

Description

Name

3-1

XGA 1.3 inch 3 plates system

14
1

-3

(120W)

UHP

-1

10
13
12

10
5

-2

11
8

-1

Fig. 3-1-1 Optical configuration diagram

3-2

4. R.G.B. DRIVE CIRCUIT
4-1. Outline
The outline of RGB drive circuit is described below
using the G process of the RGB drive circuit as an
example.

Odd number
pixel memory

SW1
1

Normal
amp.1

Q502
DAC1

Q514
1 SW3

Amp.
Q508,Q509,Q510

Inverted
amp.1

Q515
1SW5

Q511,Q512,Q513
Even number
pixel memory

Normal
amp.2

Q504

1
DAC2

Amp.
Q523,Q524,Q510

2
SW2

Q514

1 Q515

SW4

2 SW6

Inverted
amp.2

Panel
VIDEO
input

1
2
3
4
5

Sample hold
&
6-Phase decomposite

Q505,Q506,Q507

Sample hold
&
6-Phase decomposite

Exclusive for odd number pixel
Q516

7
8
9
10
11
12

2
Q517

Line inverted

Exclusive for
even number pixel

Frame inverted

12-phase composite
(12-phase collectively input)
12-phase decomposite

Digital PC board

Drive PC board

Fig. 4-1-1
In the panel, 1024 pixels are arranged in a horizontal
direction and 768 lines of the pixels are in a vertical as
shown in Fig. 4-1-2.

1024 pixels
1

1022 1023 1024
1st line

As an H inverted drive system is employed, the panel
input signal waveform is as shown in Fig. 4-1-3.
768 lines

Black level

768th line
White level
Center voltage
1st line

2nd line
White level

Black level
1st frame

1st line
2nd line

Fig. 4-1-2
2nd frame

Fig. 4-1-3

4-1

The signal as shown in Fig. 4-1-1 is separated into the
odd and even pixels at the digital PC board. After the
signal process is carried out in the drive PC board, the
odd and even pixel signals are synthesized to
decomposite the signal on the panel.

3) the signal passing through DAC2 ® Q504 ® Normal
amp. 1 ® SW41 ® SW6 ® Q517 to the positive
phase 2 and
4) the signal passing through DAC2 ® Q504 ® inverted
amp. 2 ® SW42 ® SW6 ® Q517 to inverted phase
2,

Referring to Fig. 4-1-1, the operation principle is
described.
When assuming;

the AC and DC levels of the positive phases 1, 2 and the
inverted phases 1, 2 are expected to be the same.

1) the signal passing through DAC1 ® Q502 ® Normal
amp. 1 ® SW31 ® SW5 ® Q516 to the positive
phase 1,

However, each voltage will vary slightly owing to the
adjustment variation. In this case, each frame signal is
assumed as follows.

2) the signal passing through DAC1 ® Q502 ® inverted
amp. 1 ® SW32 ® SW5 ® Q516 to the inverted
phase 1,
<1st frame>
1

10 11 12

Pixel

Inverted phase
2 voltage
Inverted phase
1 voltage

2nd line

Center voltage

1 2 3 4 5 6 7 8 9 10 11 12 Pixel

Normal phase 1
voltage
Normal phase 2
voltage

1st line

<2nd line>
Inverted phase 2
voltage
Inverted phase 1
voltage
Center voltage

9 10 11 12 Pixel

2nd line
1st line

Normal phase 1
voltage
Normal phase 2
voltage

3 4

9 10 11 12 Pixel

Fig. 4-1-4
variation of the same line between each frame and
inverting the pixel voltage of the adjacent lines (1st line
and 2nd line) between each frame.

As shown in Fig. 4-1-4, even if a slight level difference
occurs among the positive phases 1, 2 and inverted
phases 1, 2 signals (approx. 100 mV), the level difference will be decreased visually by reducing the level

4-2

4-2. Operation Description

4-2-1. Outline of Liquid Crystal Panel

The video signal of the odd number pixel (even number
pixel) is sent to Q501 (Q503) base and supplied to pin 16
of Q502 (Q504), LM1201M. The signal is clamped at
pin 16 and the pedestal voltage is adjusted at pin 6 after
the DC level is stabilized and then AC level is adjusted at
pin 3.

The liquid crystal panel module is an active matrix panel
with a built-in driver of multi-crystal silicon. The liquid
crystal panel module is designed for use of color projectors in combination with an enlargement projection
system and dichroic mirror.

The signal is developed from pin 8, supplied to the buffer
circuits of Q505 – Q507 and Q511 – Q513, and supplied
to the inverted circuits of Q508, Q509, Q510, Q523,
Q525 and Q510. These signals are supplied to pins 5, 6,
8, 13, 15 and 16 of 12 phases development IC.
CXA2504N, Q516 and Q517 of sample-and-hold passing
through the SW circuit composed of Q514 and Q515.
The signals are developed from pins 37, 35, 33, 25 and
23 for each input.

(1)

Screen size

26.624 (W) x 19.968 (H)

(2)

Pixel number

1024 (W) x 768 (H)

(3)

Applicable to XGA

(4)

Monochrome panel

(5)

Drive system

H inverted drive

(6)

Dot clock

65 MHz

(7)

Inverted function for UP/DOWN/LEFT/RIGHT directions

The signals at pins 4, 7, 14 are used as bias input and the
bias inputs set the center DC voltage of output equal to
the bias voltage.
Q519 works to suppress the noise occurred at 12 phases
collective input process of the panel.

4-2-2. Basic Component
Table 4-2-1 Terminal description
Pin No.

Name

Pin No.

Name

Pin No.

Name

Pin No.

Name

VID7

DIRX

VID10

CLY

VID5

DIRX

VID12

CLY

VID3

ENB2

LCCOM

VDDY

VID1

ENB1

N.C.

NRS2

VSSX

NRG

NRS1

CLX

VID2

LCCOM

CLX

VID4

DIRY

VID11

VID6

DIRY

VID9

VDDX

VID8

VSSY

4-3

Table 4-2-2 Input terminal function description
Name

Function

Start pulse input terminal of X shift register composing X driver.

CLX, CLX

Transfer clock input terminal X shift register composing X driver

DIRX, DIRX

X driver driving direction switch input terminal (DIRX = H R shift, DIRX = L L shift)

ENB1 – ENB2

X driver enable pulse input terminal

VID1 – VID12

X driver video signal input terminal

DY
CLY, CLY
DIRY, DIRY
LCCOM

Start pulse input terminal of Y shift register composing Y driver.
Transfer clock input terminal of Y shift register composing Y driver.
Transfer clock input terminal of Y shift register composing Y driver. (DIRX = H Down shift,
DIRX = L Up shift)
Diagonal electrode potential input terminal of liquid crystal panel

VDDX

X driver positive power supply input terminal

VDDY

Y driver positive power supply input terminal

VSSX

X driver negative power supply input terminal

VSSY

Y driver negative power supply input terminal

NRG

Drive signal input terminal for auxiliary signal circuit

NRS1 – NRS2

Auxiliary signal input terminal

4-4

5. MICROPROCESSOR

5-1-3. Adjustment Control
•

Video controls (high & low brightness ratio,
brightness, color density, tint, sharpness)

The system microprocessor has features as shown below.

•

In considering easy maintenance for specification
modification, etc., the program content is written in the
built-in non-volatile memory.

Panel adjustments (V position, H position,
phase, clock, user registration, user read-out)

•

Mode adjustments (Wide, MIC, OSD mute,
projection)

•

Language adjustments (English, Japanese,
French, German, Spanish, Italian)

5-1. System Outline

The program is also developed in considering use of
structured notation, parts modularity, and multi filling
system.

5-1-4. Adjustment Control at Factory Delivery

Major functions of the system microprocessor are as
follows.
5-1-1. System Control
•

Microprocessor program write process

•

Non-volatile memory control process

•

Remote control reception process

•

RS-232C transmission/reception process

•

Status read process

•

On-screen display process

Power

ON/OFF
(Main/Fan/Lamp)

•

Input switch

(RGB/Video/Camera)

•

Sound volume control

UP/DOWN

•

Adjust

(Up/Down/Left/Right)

•

All mute

ON/OFF

•

Audio mute

ON/OFF

•

Display

ON/OFF

•

Freeze

ON/OFF

•

Resize

ON/OFF

•

Focus

UP/DOWN
(at camera use)

•

Zoom

UP/DOWN
(at camera use)

Video sub adjustments (RGB gain, sub-bright)

•

Drive adjustments (each item for panel controls,
RGB trimming)

Fig. 5-1-1 shows the system block diagram.

5-1-2. Normal Control
•

•

5-1

PL010

PL004

PL001
2
/

PL001
HC125
2
/

2
/
QL012
HC125

77 76 75 74 72 71 70 69 68 67 66 65 64 63 62 61 60 59 49 55 54
58
57

QL005
HC14

5-2

53
52
51

QL002
HD64F3337YF16

QL003
PQ20VZ1U

2
QL010
HC165
3
/

5
/

SENSOR

48
16 17

PL006

DRIVE

PL003

7 5 4 78 79 11 10

3
/

21 22 23 24 25 26 27 28

39 40 41 42 43 44

QL004
RN5VD27A

PL009

HC541
QL007

PL002

CAT24C16J
SW

QL006

Fig. 5-1-1 System block diagram

LED

5-2. System Microprocessor

Using an exclusive data-writer allows easy maintenance
of the system microprocessor when specification modification, bug correction, etc. will occur.

The system microprocessor QL002 employs an 8 bit
micro-controller (HD64F3337YF16).

Table 5-2-1 shows the terminal functions of the system
microprocessor.

In this system microprocessor, a program area is provided inside the non-volatile memory.

Table 5-2-1 Terminal functions of the system microprocessor
Pin No.

Name

Function

I/O

Pin No.

Name

Function

I/O

RES

Reset input

LED2

LED data 2

XTAL

Clock input for oscillation

LED3

LED data 3

EXTAL

Clock output for oscillation

LED4

LED data 4

MD1

Mode 1

LED5

LED data 5

MD0

Mode 2

MAIN. PW

Main power supply swtich

NMI

Priority interruption

FAN. PW

Fan power supply switch

FVPF

Memory write voltage

VCC2

VCC1

Digital power supply

LAMP. PW

WDT

Not used

RXD0

RS-232C reception for camera

TXD0

RS-232C transfer for camera

GND1

Digital ground

SDA

15
16

Lamp power supply switch

OSDL

OSD load

DDCV

Not used

SENL

Sensor load

SENC

Used for sensor

I/O

SEND

Used for sensor

Oscillation clock

VD0C

Video I2C clock

SEL

Remote controller selection

VD0D

Video I2C data

I/O

EEPCK

Non-volatile memory clock

GND2

Digital ground

I 2C

EEPDT

REMOCON

AUX

21
22

Not used

Digital power supply

Non-volatile memory data

I/O

DRVC

Drive

DRVD

Drive I2C data

Remote controller reception

OSDC

OSD clock

Not used

OSDD

OSD data

KEY0

Key input 0

PLLU

PLL enable

KEY1

Key input 1

SYGL

SYG load

KEY2

Key input 2

SYGC

SYG clock

KEY3

Key input 3

SYGD

SYG data

I/O

KEY4

Key input 4

T-FORC data 0

KEY5

Key input 5

T-FORC data 1

KEY6

Key input 6

T-FORC data 2

KEY7

Key input 7

T-FORC data 3

AVCC

Analog power supply

T-FORC data 4

AD0

Not used

T-FORC data 5

AD1

Not used

T-FORC data 6

AD2

Not used

T-FORC data 7

AD3

Not used

GND3

Digital ground

AD4

Not used

CLK

T-FORC clock

AD5

Not used

R/W

T-FORC read/write

AD6

Not used

ENB

T-FORC enable

AD7

Not used

RST

T-FORC reset

AGND

Analog ground

TXD1

RS-232C transfer for control

LED0

LED data 0

RXD1

RS-232C reception for control

LED1

LED data 1

SCL

Not used

5-3

clock

5-3. Power Supply Reset Process

5-5. Remote Control Reception Process

In the power supply reset process, power supply reset IC
(RN5VD27A), QL004 is employed.

In the remote control reception process, a remote control
unit (CT-9925) connected to the remote control terminal
emits a remote control signal and a remote control signal
receive section on the front panel, the rear panel or the
camera arm (for TLP511) decodes the signal.

The reset IC,QL004, develops the reset signal when the
power supply voltage for the microprocessor varies and
becomes lower than the specified voltage, and sends the
signal to the reset terminal of the system microprocessor
(QL002).

The remote control signals for rear panel and camera
section (for TLP511) are selected by QL012 buffer
(TC74HC125AF). Then both signals are mixed with the
remote control signal for front panel through QL005
buffer (74HC14AF).

5-4. Non-volatile Memory Control Process
In the non-volatile memory process, data reading and
saving for various adjustments are carried out on the
non-volatile memory, QL006 (CAT24C16J).

Finally, the signal mixed is supplied to the remote control
terminal of the system microprocessor (QL002).

When the power (AC) is on, all the adjustment data are
read out by the system microprocessor (QL002), then the
previous status is realized.

5-6. RS-232C Transmission/Reception
Process
In the RS-232C transmission/reception process, an RS232C signal entered through the RS-232C connector (DSUB 9P) is decoded in the RS-232C interface
(mPD4721), and fed to RXD1 terminal of the system
microprocessor (QL002).

When saving the data, all the adjustment data are written
by the system microprocessor (QL002), then the current
status is preserved.
However, if a failure (such as power interruption due to
lightning, etc.) occurs during the adjustment data writing,
a data error may occur. If the data is determined as
incorrect, the initial data memorized on the system
microprocessor (QL002) is read out and stored on the
non-volatile memory.

In the RS-232C transmission process, RS-232C signal
developed from TXD0 terminal of the system microprocessor (QL002) is decoded in the RS-232C interface
(mPD4721) and fed to the camera microprocessor
section.

5-7. Status Read Process
In the status read process, the following status shown in
the table below are read by QL010 (74HC165AF) and
the error process corresponding to each status is carried
out.
Table 5-7-1 shows the contents of the status read signals
and the logic.

Table 5-7-1 The contents of the status read signals and the logic
Signal name

D
14

Pin No.

QL010

FAN1. ER

FAN1. SW

FAN2. ER

TEMP1. ER

LAMP. ER

MAIN. ER

(L)

Abnormal

Normal

Abnormal

Normal

Abnormal

(H)

Normal

Abnormal

Normal

Abnormal

Normal

5-4

5-8. Status Display Process

5-9. On-screen Display Process

In the status display process, two-color lighting LEDs of
DL037, DL038 and DL039 turn ON for each kind of
status shown in the table below by using LED0 to LED5
terminal output of the microprocessor.

In the on-screen display process, control signals are
supplied to the OSD display IC QX003 (CD0016AM),
and the OSD display IC generates character display
signals at the timing determined by VD, HD and clock
supplied to the IC separately.

Table 5-8-1 Contents of the status display signals and the logic
ON

LAMP

TEMP

Function

Status

Countermeasure

Green

Red

Orange

Stand-by

At power off

Normal

Green

Lamp ON

At power on

Normal

Green

(Green)

Lamp Heat-up

At power on

Normal

Green

Lamp Lighting

During power on

Normal

Green

Lamp OFF

At power off

Normal

Orange

(Green)

Lamp cool-down

At power off

Normal

At power On/During

Repair

At power On/During

Repair or preparation failure

Stand-by power supply
abnormality

At AC cord plugged

Repair

Green

Non-volatile memory OK

At AC cord plugged

Normal

Red

Non-volatile memory NG

At AC cord plugged

At initial time

Red

Main power supply
abnormality

Red

Lamp no-lighting

Red

Orange

Lamp lighting-lifetime

At power on

Operates after approx. 2500 H
operation

Red

(Red)

Suction fan stop

At power on

Repair

Red

(Orange)

Exhaust fan stop

At power on

Repair

Red

(Green)

Fan filter open

Ever

Temperature sensor
abnormality

Ever

Lower internal temperature of
the unit.

Red

X: Lighting OFF
( ): Blinking

5-5

5-10. Video System Control Process

5-11. Panel System Control Process

In the video system control process, control signals are
supplied to various video system process ICs shown in
the table below. Table 5-10-1 shows the I2C control for
each kind of video system.

The panel system control process supplies various
control signals to the panel system control ICs shown in
the table below.
Table 5-11-1 shows the IC control for each kind of panel
system.

Table 5-10-1 I2C control for each kind of video system
Part No.

Type name

Process

QV001

CXA1855Q
(Custom: $90)

I/O SW process

QV002

TC9090N
(Custom: $B2)

Color signal process (3D Y/C separation)

QV005

TDA9141
(Custom: $8A)

Sync detection process (Custom: $8B)
Signal kinds identification (NTSC/PAL/SECAM, etc.)

QV008

TDA4780
(Custom: $88)

Video control (Density, hue)

QV007

TDA4672
(Custom: $88)

Video control (Sharpness control)

QV045

CXA1315M
(Custom: $40)

Input SW, MIC SW
Volume, mute, MIC gain

QB025

CXA1315M
(Custom: $44)

Brightness, contrast, RGB gain
Sync information

QV057

M62320FP
(Custom: $71)

Camera ON/OFF (for TLP511), focus, zoom reading
Fan switch open

Table 5-11-1 IC control for each kind of panel system
Part No.

Process

Type name

QX004

SYG
(TC160G54AF1137)

Various kinds of screen display process (position, picture frame,
property)
Screen position control (Vertical position, horizontal position)

QX007

CXA3106

Screen position control (sampling phase, sampling frequency)

QX204
QX404
QX604

TFORC
(TC203E2651AF-01)

Picture frame control (R)
Picture frame control (G)
Picture frame control (B)

QX001

M62320FP
(Custom: $78)

Panel mode control
A/D sample phase (R)

QX002

M62320FP
(Custom: $7A)

A/D sample phase (G)
A/D sample phase (B)

5-6

5-12. Drive System Control Process

Table 5-12-1 shows each kind of the drive system IC
control.

In the drive system control process, the control signal is
supplied to each kind of drive system process ICs shown
in the the table below.

Table 5-12-1 Each kind of the drive system IC control
Part No.

Type name

Process

Q701

M62399FP
(Custom: $90)

Process relative to R drive

Q702

M62399FP
(Custom: $92)

Process relative to G drive

Q703

M62399FP
(Custom: $94)

Process relative to B drive

Q704

M62399FP
(Custom: $96)

Process relative to VCOM, NR

Q705

M62399FP
(Custom: $98)

Process relative to NR, Bias

5-13. Various Display Modes

(5)

In this system, various LED display patterns are provided
in relation to the display modes shown in Table 5-8-1.
Operation processes from the status of AC cord plugged
to that of power on and power off will be given below.

In the normal status, ON/STANDBY LED and the
LAMP LED are turned on in green, and the main
power and the lamp power are turned on.

(6)

When the power is turned off by pressing the ON/
STANDBY key, the unit enters the standby status in
passing through following processes.

(1)

(2)

(3)

Data of the non-volatile memory are checked when
the AC cord is plugged, and all the LED are turned
on in red in the initial use. In second or later use, all
the LEDs are turned on in green and the unit enters
the standby status.

1) When the lamp power is turned off, ON/
STANDBY LED turns on in orange.
2) The LAMP LED blinks in green for about 1
min. For this period the lamp can not be turned
on again by the ON/STANDBY key.

In the standby status, only the ON/STANDBY LED
is turned on in orange, and the main power is off
and the lamp power is also off.

3) When blinking of the LAMP LED stops, only
the ON/STANDBY LED turns on in orange.
After this, the lamp can be turned on again by
the ON/STANDBY key.

When the power is on by pressing the ON/
STANDBY key, the unit enters a normal status in
passing through following processes.

(7)

Moreover, the fan works for about 2 min. to lower
temperature of the unit. When the main power turns
off, the fan also stops and returns to the standby
status.

(8)

If an error occurs due to some causes, the ON/
STANDBY LED turns on in red, and the error
information is kept in the display status of the
LAMP and TEMP LEDs. When the error is
detected, the unit enters the standby status after
cooling down process for about 2 min. In this case,
if the error status continues, the error display is also
kept and any key entry is not accepted.

1) The main power is on, and ON/STANDBY LED
turns on in green.
2) The fan power is on, and the fan starts to rotate.
3) The lamp power is on, and LAMP LED blinks
in green for about 3s.
4) With the lamp turned on, LAMP LED turns on
in green and the unit enters the normal status.
(4)

If the lamp does not turn on, ON/STANDBY LED
turns on in orange, and the LAMP LED blinks in
green for about 1 min. and then the unit returns to
the standby status.

5-7

5-14. Applicable Signal

In other mode, the signal line number is detected to allow
the separate adjustment in the VGA system (basically
effective for line number of 480 lines), SVGA system
(basically effective for line number of 600 lines) and
XGA system (basically effective for line number of 768
lines).

Various kinds of signals are used as the applicable
signals in the preset mode (standard value) as shown in
Table 5-14-1. For the signals not fit to the preset modes,
a user mode is provided.
In the preset modes, the applicable signals are based on
the VESA standard, so the sample frequency (CLOCK
adjustment in the panel menu) is not used, but the
adjustment is allowed only in the user mode.

In the user mode of SGA system (900 line system and
1024 line system), the input signal is applicable to the
plain display mode. That is, the signal is displayed in
different two ways owing to the line number in vertical
direction.

Table 5-14-1 Applicable signal
Signal

Resolution

Frequency

All

Operation

Sync

Mode

Content

H (kHz)

V (Hz)

Clock
(MHz)

NTSC

664

484

15.734

59.940

12.590

800

525

N/N

Video input
Video input

H/V

Correspondence

Remarks

PAL

756

574

15.625

50.000

12.500

800

625

N/N

V60

VGA 60 Hz

640

480

31.470

59.940

25.175

800

525

N/N

V72

VGA 72 Hz

640

480

37.861

72.809

31,500

832

520

N/N

V75

VGA 75 Hz

640

480

37.500

75.000

31.500

840

500

N/N

V85

VGA 85 Hz

640

480

43.269

85.008

36.000

832

509

N/N

M13

MAC-13”

640

480

35.000

66.667

30.240

864

525

N/N

24K

PC98-STD

640

400

24.830

56.420

21.053

848

444

N/N

T70

VGA 70 Hz

720

350

31.470

70.020

28.322

900

450

P/N

T70

VGA 70 Hz

720

400

31.470

70.020

28.322

900

450

N/P

T70

VGA 70 Hz

640

350

31.470

70.020

28.322

800

450

P/N

T70

VGA 70 Hz

640

400

31.470

70.020

28.322

800

450

N/P

T85

VGA 85 Hz

640

350

37.861

85.080

31.500

832

445

P/N

T85

VGA 85 Hz

640

400

37.861

85.080

31.500

832

445

N/P

T85

VGA 85 Hz

720

400

37.927

85.039

35.500

936

446

N/P

S56

SVGA 56 Hz

800

600

35.156

56.250

36.000

1024

625

N/N

S60

SVGA 60 Hz

800

600

37.879

60.317

40.000

1056

628

N/N

S72

SVGA 72 Hz

800

600

48.077

72.188

50.000

1040

666

N/N

S75

SVGA 75 Hz

800

600

46.875

75.000

49.500

1056

625

N/N

S85

SVGA 85 Hz

800

600

53.674

85.061

56.250

1048

631

N/N

M16

MAC-16”

832

624

49.724

74.550

57.283

1152

667

N/N

X60

XGA 60 Hz

1024

768

48.363

60.004

65.000

1344

806

N/N

X70

XGA 70 Hz

1024

768

56.476

70.069

75.000

1328

806

N/N

X75

XGA 75 Hz

1024

768

60.023

75.029

78.750

1312

800

N/N

X85

XGA 85 Hz

1024

768

68.677

84.997

94.500

1376

808

N/N

M21

MAC-21”

1152

870

100.000

68.653

75.030

1456

915

N/N

Plain display

SXGA1 1152 system

1152

864

108.000

67.500

75.000

1600

900

N/N

Plain display

SXGA2 1280 system

1280

1024

135.000

79.976

75.025

1688

1066

N/N

Plain display

• In the operation column, O shows a standard mode, D
shows pull-in mode, X shows plain display mode.

• In the sync column of Table 3-14-1, P shows the positive polarity and N shows the negative polarity.

5-8

5-15. RS-232C Control Method

Table 5-15-1 RS-232C connection signals
Pin No. Signal name

Signals are connected to the RS-232C connector in a
straight format as shown in Table 5-15-1 RS-232C
connection signals. This is because a crossing connection is provided inside the unit. Communication conditions are set to meet the conditions given in Table 5-15-2.

Signal content

I/O

RXD

Receive data

TXD

Transmit data

DTR

Data terminal ready

S. G

Signal ground

Table 5-15-3 shows the command list of RS-232C.

DSR

Data set ready

When transmitting the command, be always sure to keep
100 ms interval between each command. Moreover, the
process time is required for a while when turning the
power ON/OFF and/or selecting the input mode. So in
such cases, also be always sure to keep enough intervals
between the commands.

RTS

Transmission request

CTS

Transmission enable

Table 5-15-2 RS-232C communication conditions
Item

Conditions

Communication system

Transmission speed 9600 baud, No parity, Data length 8 bit, Stop bit: 1 bit

Communication type

STX (1 byte) + CMD (3 byte) + ETX (1 byte) = 1 block
STX is 02h, ETX is 03h, CMD is command string (Uppercase character)

5-9

Table 5-15-3 RS-232C command list
Item

Command

Normal status

PON

Power supply ON

POF

RGB
Camera (for TLP511)

Common adjustment

Video

Content

Item

Command

Panel

PVP

Vertical position

Power supply OFF

PHP

Horizontal position

IN1

Video input

PPH

Sampling phase

IN2

RGB input

PCK

Sampling frequency

IN3

Camera input

PL0

VUP

Volume UP

PL1

VDW

Volume DOWN

PL2

DON

Display ON

PL3

DOF

Display OFF

PL4

MON

All Mute ON

PL5

MOF

All Mute OFF

PS0

AON

Audio Mute ON

PS1

AOF

Audio Mute OFF

PS2

FON

Freeze ON

PS3

Content

FOF

Freeze OFF

PS4

RON

Resize ON

PS5

ROF

Resize OFF

MW1

Wide ON

CFU

Focus UP

MW0

Wide OFF

CFD

Focus DOWN

MM1

MIC ON

CZU

Zoom UP

MM0

MIC OFF

CZD

Zoom DOWN

MO1

OSD mute ON

ALF

Menu left shift/
adjustment value
DOWN

MO0

OSD mute OFF

ARG

Menu right shift/
adjustment value UP

PJ0

Floor mounted front
projection

AUP

Menu up shift

PJ1

Ceiling mounted front
projection

ADW

Menu down shift

PJ2

Floor mounted rear
projection

RST

Standard setting for
each item

PJ3

Ceiling munted rear
projection

SAV

Adjustment value
storing

LEN

English display

VCN

Contrast

LJP

Japanese display

VBR

Bright

LFR

French display

VCL

Color

LGR

German display

VTN

Tint

LSP

Spanish display

VSH

Sharp

LIT

Italian display

Mode

Language

Camera

5-10

CSH

High sensitivity ON

CSL

High sensitivity OFF

SIR

Iris adjustment

6. DIGITAL CIRCUIT
6-1. Outline
A Configuration of digital circuit is shown in Fig. 6-1-1.
The functions of digital circuit are described on the
following pages.

QX202, 203, 205, 206
MB814265/HM514265
(MEMORY)

R signal
(2.0V - 4.0V)

QX201
CXA3026Q
(A/D CONV.)

QX204
TC203E2651AF-01
(T-FORC)

QX207
EPM7064LC68
(EXCHANGE)

QX208
MB40950
(D/A CONV.)

R signal
(3.0V - 5.0V)

1/2 CLK

R CHANNEL

G signal
(2.0V - 4.0V)

G CHANNEL (RX4**, CX4**, QX4**)

G signal
(3.0V - 5.0V)

B signal
(2.0V - 4.0V)

B CHANNEL (RX6**, CX6**, QX6**)

B signal
(3.0V - 5.0V)

42 MHz
System clock
for T-FORC

CLK (PECL)

ZX003
42 MHz
X'tal OSC

FREEZE
(MPU or camera)

VD
HD

QX003
ON SCREEN
DISPLAY

VD (INPUT)

VD (PANEL)

HD (INPUT)

HD (PANEL)

QX028
CXA3106Q
(PLL IC)

QX004
LCD panel
TC160G54AF1137
clock
(SYG)
1/2 CLK

Reference clock
for signal format
measurement

For RGB signal

Reference
clock for
LCD drive

ZX003
32.5 MHz
X'tal OSC

QX029
TLC2932
(PLL IC)
For VIDEO signal

Fig. 6-1-1

6-1

QX009
EMP7160ELC84
(TIMING)

QX008
TLC2932
(PLL IC)

Timing signals
for LCD drive

6-1-1. PLL Circuit

6-1-4. Gamma Correction Circuit

The PLL circuit develops the clock signal synchronized
with the horizontal sync signal, using the horizontal sync
signal entered.

The gamma correction is carried out in the digital circuit.
So the digital circuit develops the signal corrected in
gamma.

For RGB signals, a highly stable CXA3106 (QX028) is
used. For video signal, a highly traceable TLC2932
(QX029) is used.

The gamma correction circuit is built in the T-FORC
(QX207, QX407 and QX607) and the gamma correction
characteristics are set by the microprocessor using a bus.

6-1-2. Video Signal Format Conversion

6-1-5. Panel Driving Timing Signal Generation

The LCD panel used for the unit requires a non-interlace
signal of 65 Hz dot clock entered. Accordingly, all the
RGB signals are converted into XGA 60 Hz format (Dot
clock = 65 MHz). In the same way, the video signal
(interlace signal) is converted into a non-interlace signal
with 64 MHz dot clock in keeping the vertical sync
signal frequency. These processes are carried out by the
newly developed ICs T-FORC (QX207, QX407 and
QX607) and memories (QX202, QX203, QX205,
QX206, QX402, QX403, QX405, QX406, QX602,
QX603, QX605 and QX606).

The driving for LCD panel requires various kinds of
timing signals. These timing signals are generated in the
digital circuit and especially generated by the timing
generation PLD (QX009).

Furthermore, as the clock of XGA signal reaches approx.
80 MHz (max.), all signal processes are carried out in
parallel for even and odd pixels grouped. The video
signal entered is converted into the digital video signals
for two systems by the A/D converters (QX204, QX401
and QX601).

The RGB signals consist of various kinds of signal
formats, and the timing signal, enlargement ratio and etc.
must be switched corresponding to each signal format.

6-1-6. ON-SCREEN Character Generation
The ON-SCREEN character timing signal is generated
and superimposed inside the digital circuit. So the signal
composed of the ON-SCREEN character is developed
from the digital circuit.
6-1-7. Signal Format Measurement

For this purpose, the signal format identification is
carried out by measuring the HD signal frequency
entered and the line number per 1 frame. This circuit is
built in the SYG (QX004) and the processed result is
read by the microprocessor through the bus line.

The signals divided into two systems are processed in
parallel in stages after the digital circuit. In case of the
process carried out in parallel as described above, if the
characteristics between two systems differ, the vertical
stripes will appear on the screen. In order to reduce this
vertical stripes, the signal system used is exchanged for
every one line and one field by the EXCHANGE PLD
(QX207, QX407 and QX607). The signals exchanged are
returned to the original order just before reaching the
LCD panel.
6-1-3. Screen Size Enlargement and Reduction
The pixel number of the LCD panel used for the unit is
1024 x 768 pixels. As for a signal entered, various kinds
of signals are used ranging from 640 x 480 pixels of
VGA signal to 1280 x 1024 pixels of SXGA signal. In
this unit, these signals are displayed on the whole screen
by enlarging/reducing the signals. The enlargement/
reduction process are also carried out by the ICs T-FORC
(QX207, QX407 and QX607) and memories (QX202,
QX203, QX205, QX206, QX402, QX403, QX405,
QX406, QX602, QX603, QX605 and QX606).

6-2

6-2. Each IC Description

The VCO, phase comparator, loop filter and frequency
dividing circuit are built in the IC, so the IC can generate
the clock signal by itself.

6-2-1. PLL IC CXA3106Q (QX028) for RGB Signals
A configuration of CXA3106Q is shown in Fig. 6-2-1.
The PLL IC of CXA3106Q is an IC with high performance and low jitter, and can generate the clock signal
synchronized with the horizontal sync signal of max. 120
MHz.

RC 1

RC 2
1 bit
ON/OFF

VCO
(TTL)

1 - 4 CLK

TTLIN

COARSE
DELAY

LATCH
VCO
(PECL)

PECLIN
2 bits

SYNC
(PECL)

PECLOUT

DSYNC
(PECL)

1 bit
ON/OFF
TTLOUT

TTLIN

CLK
(TTL)

1 bit

POLARITY
1/16

PECLIN
PHASE
DETECTOR

1 bit

CHARGE
PUMP
2 bits

1 bit

ON/OFF

20/16 CLK

TTLOUT

FINE
DELAY

VCO

MUX
1 bit

5 bits
1/256

DIV
PECLOUT

2 bits

1/4096

TTLIN

NCLK
(TTL)
CLK
(PECL)

1 bit
ON/OFF

PROGRAMMABLE
COUNTER
HOLD
(TTL)

DSYNC
(TTL)

1 bit

LOGIC
SYNC
(TTL)

TTLOUT
POLARITY

TTLOUT

CLK/2
(TTL)

1 bit

12 bits

REST
1/2

ON/OFF
TTLOUT

NCLK/2
(TTL)

PECLOUT

CLK/2
(PECL)

1 bit
ON/OFF
UNLOCK
DETECT
1 bit

1 bit

ON/OFF
DAC

CONTROL REGISTER

SYNTHESIZER
POWER SAVE

ON/OFF

READ OUT
TTLOUT

TTLOUT

WHOLE CHIP
POWER WAVE

TTLIN
1 bit

1 REF
SENABLE

SCLK

SDATA

SEROUT

DIVOUT

Fig. 6-2-1

6-3

TLOAD

PECL

UNLOCK

VBB

6-2-2. PLL IC TLC2932 (QX029) for Video Signal

6-2-4. Timing Signal Generation PLD (QX009)

The PLL IC of TLC2932 is composed of a phase
comparator and a VCO. As a frequency dividing circuit is
not built in, so the IC works as a PLL circuit by connecting to the external VCO terminal of QX028 and using the
frequency dividing circuit of QX028.

A configuration of timing signal generation PLD is
shown in Fig. 6-2-3. The timing generation PLD generates the clock pulse and the timing signal to drive the
panel. As the signal timing and clock differ owing to the
inverted driving for top/bottom/left/right of panel and
kinds of input signals, the mode signal controls the
timing signal generation PLD.

6-2-3. Sync Process IC SYG (QX004)
A configuration of the SYG component is shown in Fig.
6-2-2. The SYG IC is used as a sync process IC and
composed of the timing generation circuit for 2 systems,
one for the input signal and the other is for the panel
display, and the input signal measurement circuit. The IC
supplies the HD/VD signal to each IC and the IC works
on the timing signal basis. Also, the field identification at
video signal is carried out by the IC. In the unit, as the
PLL circuit is independent from the SYG, the sync signal
(DSYNC) enters from the PLL circuit to pin 139. The pin
is connected to the reset terminal of the horizontal
counter (for input signal).

PLL IC
QX008

PLL
CIRCUIT

PCLK

SW
AD CLK/2
32.5 MHz
Mode

MODE
DECODER

PANEL TIMING
GENERATOR

CLK, HD, VD

Timing signals
for
LCD panel

Fig. 6-2-3
32.5 MHz

SIGNAL FORMAT
MEASUREMENT

HD, VD

6-2-5. A/D Converter CXA3026Q
(QX201, QX401 and QX601)

TIMING SIGNAL
GENERATOR 1

A configuration of CXA3026Q is shown in Fig. 6-2-4.
The max. conversion speed of 120 MHz is supported by
CXA3026Q, A/D converter.

TIMING SIGNAL
GENERATOR 2

A frequency dividing circuit is built in the A/D converter
and the converter develops the data for two systems. The
clock speed is fast, so that the clock signal to be entered
is a differential input of PECL level. The input level of
analog signal ranges from 2.0 to 4.0V.

BUS
INTERFACE

MPU

Fig. 6-2-2

6-4

INV
VRT

R1
R/2

(LSB)
P1D0

R
0

P1D1
1

6 bits

R
R

8 bits

63
64

TTLOUT

VRM3

LATCH A

P1D2

8 bits

VRM2
VIN

127
128

ENCODER

129

6 bits

6 bits LATCH + ENCODER

6 bits
126

P1D6
P1D7
(MSB)

(LSB)
P2D0
P2D1

P2D2
192
193

6 bits

TTLOUT

191

LATCH B

VRM1

8 bits

R
R
R/2

P2D3
P2D4
P2D5

254

P2D6

255

P2D7
(MSB)

VRB
R2
(ECL)
CLK
(TTL)

P1D4
P1D5

P1D3

DELAY

1/2

(ECL)
NRSET
(TTL)

SELECTOR

TTL
OUT

SELECT

Fig. 6-2-4

6-5

CLK OUT

OSD, OSDI, PBLK

6-2-6. Picture Size of View Conversion IC T-FORC
(QX204, QX404, QX604)
A configuration of T-FORC is shown in Fig. 6-2-5. The
T-FORC is a newly developed picture size conversion IC.

Video
signal

By using the IC, smooth picture enlargement and
reduction, and format conversion will be made. Also, a
gamma correction circuit is built in the IC.

Video
signal

Memory

SW
OSD SW
BLANKING SW
SW

Video
signal

SEL

From
timing PLD

Freeze

PANEL TIMING
TRIM

To LCD panel
(ENB, DX)

MPU
MEMORY
INTERFACE

FORMAT
CONVERTER

Fig. 6-2-6
GAMMA
(LOOK UP
TABLE)

MEMORY
INTERFACE

6-2-9. D/A Converter

OSD SW
BLK SW
(NOT USED)

BUS
INTERFACE

Input CLK
System CLK
(42 MHz)
Panel CLK
(32.5 MHz)

Memory

MPU

Fig. 6-2-5

6-2-7. Memory
The memory uses four general 4 M bits EDO-DRAMs
(256k x 16 bits) per 1 channel.
6-2-8. Exchange PLD
A configuration of timing signal generation PLD is
shown in Fig. 6-2-6. In the unit, the signal process is
carried out in parallel by dividing the process into two
systems. In order to reduce the characteristic difference
between these two systems, the signals of both systems
are switched for every 1 line and 1 frame. The PLD
carries out the process. Also, the ON-SCREEN display
signal superimposing, addition of non-display section for
top and bottom and left and right, etc. are carried out by
the PLD.

6-6

MB40950 is a 10 bits 3 channels D/A converter of which
max. conversion speed is 60 MHz. In order to reduce the
difference of two systems of each RGB channel, each
RGB channel possesses one IC respectively. So one
channel of 3 channels D/A converter built in the IC is not
used. The output signal level ranges from 3.0 to 5.0V.

7. VIDEO CIRCUIT

7-1-2. Video Demodulation Section
In the video demodulation section, the composite video
signal and Y/C signals are demodulated into the RGB
signals.

7-1. Circuit Component
The video circuit performs selection of input signals,
video signal (NTSC, PAL, SECAM) demodulation to
RGB signals, RGB input signal amplification and audio
signal amplification.

In the video/color process IC, the color demodulation is
carried out corresponding to the color mode of the video
signal entered. The applicable color modes are NTSC,
4.43 NTSC, PAL and SECAM.

Fig. 7-1-1 shows the block diagram.

The mode identification is automatically carried out by
the video/color process IC.

7-1-1. Input Signal SW Section

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