UBS Axcera 425A 500-watt solid state television transmitter User Manual Chapter 3

UBS-Axcera 500-watt solid state television transmitter Chapter 3

Chapter 3

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-1Chapter 3Circuit Descriptions3.1 (A4) High-Band VHF Exciter(1070901; Appendix C)3.1.1 (A4) Aural IF SynthesizerBoard, 4.5 MHz (1265-1303;Appendix D)The aural IF synthesizer board amplifieseach of the three possible audio inputsand the amplifier circuits that supply thesingle audio output. The balanced audioor the composite audio input is connectedto the board while the subcarrier audio(SCA) input can be connected at thesame time as either of the other twoinputs. The board has the 4.5-MHzvoltage-controlled oscillator (VCO) andthe aural modulation circuitry thatproduces the modulated 4.5-MHz output.The board also contains a phase lock loop(PLL) circuit that maintains the precise4.5-MHz separation between the aural(41.25 MHz) and the visual (45.75 MHz)IF frequencies.3.1.1.1 Balanced Audio InputThe first of the three possible basebandinputs to the board is a 600Ω-balancedaudio input (+10 dBm) that entersthrough jack J2, pins 1 (+), 2 (GND), and3 (-), and is buffered by U1B and U1C.Diodes CR1 to CR4 protect the inputstages of U1B and U1C if an excessivesignal level is present on the input leadsof jack J2. The outputs of U1B and U1Care applied to differential amplifier U1A;U1A eliminates the common modesignals (hum) on its input leads. Apre-emphasis of 75 ms is provided byR11, C11, and R10 and can be eliminatedby removing jumper W5 on J5. The signalis then applied to amplifier U1D whosegain is controlled by jumper W3 on J11.Jumper W3 on jack J11 is positionedaccording to the input level of the audiosignal (0 or +10 dBm). If the input levelis approximately 0 dBm, the mini-jumpershould be in the high gain positionbetween pins 1 and 2 of jack J11. If theinput level is approximately +10 dBm,the mini-jumper should be in low gainposition between pins 2 and 3 of jackJ11. The balanced audio is thenconnected to buffer amplifier U2A whoseinput level is determined by the setting ofbalanced audio gain pot R13. The outputof the amplifier stage is wired to thesumming point at U2D, pin 13.3.1.1.2 Composite Audio InputThe second possible audio input to theboard is the composite audio (stereo)input at BNC jacks J3 and J13. The twojacks are loop-through connected; as aresult, the audio can be used in anotherapplication by connecting the unusedjack and removing W4 from J12. JumperW4 on jack J12 provides a 75Ω-inputimpedance when the jumper is betweenpins 1 and 2 of jack J12 and a highimpedance when it is between pins 2 and3. Diodes CR9 to CR12 protect the inputstages of U6A and U6B if an excessivesignal level is applied to the board. Theoutputs of U6A and U6B are applied todifferential amplifier U2C, whicheliminates common mode signals (hum)on its input leads. The composite inputsignal is then applied to amplifier U2B;the gain of this amplifier is controlled bycomposite audio gain pot R17. Thecomposite audio signal is connected tothe summing point at U2D, pin 13.3.1.1.3 Subcarrier Audio InputThe third possible input to the board isthe SCA input at BNC jack J4. The SCAinput has an input impedance of 75Ω thatcan be eliminated by removing jumperW2 from pins 1 and 2 of J14. The SCAinput is bandpass filtered by C66, C14,R22, C15, C67, and R23 and is fed tobuffer amplifier U3A. The amplified signalis then applied though SCA gain pot R24to the summing point at pin 13 of U2D.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-23.1.1.4 Audio Modulation of the VCOThe balanced audio, or the compositeaudio and/or the SCA-buffered audiosignals, are fed to the common junctionof resistors R14, R20, and R27 thatconnect to pin 13 of amplifier U2D. Theoutput audio signal at pin 14 of U2D istypically .8 Vpk-pk at a ±25-kHzdeviation for balanced or .8 Vpk-pk at±75-kHz deviation for composite asmeasured at TP1. This signal is applied toVCO U10. A sample of the deviation levelis amplified, detected by U7A and U7B,and connected to J10 on the board. Thisaudio-deviation level is connected to thefront panel meter through the transmittercontrol board.The audio is connected to CR13 to CR16;these are varactor diodes that frequencymodulate the audio signal onto thegenerated 4.5-MHz signal in U10. U10 isthe 4.5-MHz VCO that generates the 4.5-MHz continuous wave (CW) signal. Theoutput frequency of this signal ismaintained and controlled by thecorrection voltage output of U5 PLL IC.The audio-modulated, 4.5-MHz signal isfed to amplifiers U11A and U11B. Theoutput of U11B is connected to the 4.5-MHz output jacks at J7 and J8.3.1.1.5 Phase Lock Loop (PLL) CircuitA sample of the signal from the 4.5-MHzaural VCO at the output of U11A isapplied to PLL IC U5 at the Finconnection. In U5, the signal is divideddown to 50 kHz and is compared to a 50-kHz reference signal. The referencesignal is a divided-down sample of thevisual IF, 45.75-MHz signal that isapplied to the oscillator-in connection onthe PLL chip through jack J6 on theboard. These two 50-kHz signals arecompared in the IC and the fV, and fR isapplied to the differential amplifier U3B.The output of U3B is fed back throughCR17 to the 4.5-MHz VCO IC U10; thissets up a PLL circuit. The 4.5-MHz VCOwill maintain the extremely accurate 4.5-MHz separation between the visual andaural IF signals; any change in frequencywill be corrected by the AFC errorvoltage.PLL chip U5 also contains an internal lockdetector that indicates the status of thePLL circuit. When U5 is in a "locked"state, pin 28 goes high and causes thegreen LED DS1 to illuminate. If the 4.5-MHz VCO and the 45.75-MHz oscillatorbecome "unlocked," out of the capturerange of the PLL circuit, pin 28 of U5 willgo to a logic low and cause the red LEDDS2 to light. A mute output signal fromQ3 (unlock mute) will be applied to jackJ9. This mute is connected to thetransmitter control board.3.1.1.6 Voltage RequirementsThe ±12 VDC needed for the operation ofthe board enters through jack J1. The+12 VDC is connected to J1-3 andfiltered by L2, C3, and C4 before it isconnected to the rest of the board. The-12 VDC is connected to J1-5 and filteredby L1, C1, and C2 before it is connectedto the rest of the board. +12 VDC isconnected to U8 and U9; these are 5-voltregulator ICs that provide the voltage tothe U10 and U5 ICs.3.1.2 (A5) Sync Tip Clamp/Modulator Board (1265-1302;Appendix D)The sync tip clamp/modulator board canbe divided into five circuits: the mainvideo circuit, the sync tip clamp circuit,the visual modulator circuit, the aural IFmixer circuit, and the diplexer circuit.The sync tip clamp/modulator boardtakes the baseband video or 4.5-MHzcomposite input that is connected to thevideo input jack (either J1 or J2, whichare loop-through connected), andproduces a modulated visual IF + auralIF output at output jack J20 on theboard. The clamp portion of the boardmaintains a constant peak of sync levelover varying average picture levels(APL). The modulator portion of the
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-3board contains the circuitry thatgenerates an amplitude-modulatedvestigial sideband visual IF signal outputthat is made up of the baseband videoinput signal (1 Vpk-pk) modulated ontoan externally generated 45.75-MHz IFcarrier frequency. The visual IF signaland the aural IF signal are thencombined in the diplexer circuit toproduce the visual IF + aural IF outputthat is connected to J20, the IF outputjack of the board.3.1.2.1 Main Video Signal Path (Part 1 of2)The baseband video or the 4.5-MHzcomposite input connects to the board atJ2. J2 is loop-through connected to J1and terminated to 75 watts if jumper W4is on jack J3. With jumper W4 removed,the input can be connected to anothertransmitter through J1; J1 is loop-through connected to J2.Test point TP1 is provided to monitor thelevel of the input. The input is fed to thenon-inverting and inverting inputs ofU1A, a differential amplifier thatminimizes any common-mode hum thatmay be present on the incoming signal.Diodes CR1 to CR4 form a voltage-limiternetwork in which, if the input voltagesexceed the supply voltages for U1A, thediodes conduct, preventing damage toU1A. CR1 and CR3 conduct if the inputvoltage exceeds the negative supply andCR2 and CR4 conduct if the input voltageexceeds the positive supply voltage.The video output of U1A is connected toJ22 on the board. Normally, the video atJ22 is jumpered to J27 on the board. Ifthe 4.5-MHz composite input kit ispurchased, the 4.5-MHz composite signalat J22 connects to the external composite4.5-MHz filter board and the 4.5-MHzbandpass filter board. These two boardsprovide the video-only signal to J27 andthe 4.5-MHz intercarrier signal to J28from the 4.5-MHz composite input. Thevideo through the video gain pot R12(adjusted for 1 Vpk-pk at TP2) connectsto amplifier U1B.The output of U1B, if the delay equalizerboard is present in the tray, connects thevideo from J6, pin 2, to the externaldelay equalizer board and back to thesync tip clamp/modulator board at J6,pin 4. If the delay equalizer is notpresent, the video connects throughjumper W1 on J5, pins 1 and 2. Thedelay equalizer board plugs directly to J6on the sync tip clamp/modulator board.The video from J6, pin 4, is thenconnected through jumper W1 on J5,pins 2 and 3, to the amplifier Q1. Theoutput of Q1 connects to Q2; the basevoltage of Q2 is set by the DC offsetvoltage output of the sync tip clampcircuit.3.1.2.2 Sync Tip Clamp CircuitThe automatic sync tip clamp circuit ismade up of U4A, Q7, U3B, andassociated components. The circuitbegins with a sample of the clampedvideo that is split off from the main videopath at the emitter of Q3. The videosample is buffered by U3A and connectedto U4A. The level at which the tip of syncis clamped, approximately -1.04 VDC asmeasured at TP2, is set by the voltage-divider network connected to U4A. If thevideo level changes, the sample appliedto U4A changes. If jumper W7 on J4 is inthe Clamp-On position, the voltage fromthe clamp circuit that is applied to thesumming circuit at the base of Q2 willchange; this will bring the sync tip levelback to approximately -1.04 VDC. Q7 willbe turned off and on according to thepeak of sync voltage level that is appliedto U4A. The capacitors C14, C51, C77,and C41 will charge or discharge to thenew voltage level, which biases U3Bmore or less, through jumper W7 on J4in the Auto Clamp-On position. U3 willincrease or decrease its output, asneeded, to bring the peak of sync back tothe correct level as set by R152 and R12.This voltage level is applied through U3Bto Q2. In the Manual position, jumper W7
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-4on J4 is in the Clamp-Off position,between pins 1 and 2, and adjustableresistor R41 provides the manual clampbias adjustment for the video thatconnects to Q2.Jumper W6 on jack J35 must be in theNormal position, between pins 2 and 3,for the clamp circuit to operate with anormal non-scrambled signal. If ascrambled signal is used, the tray isoperated with jumper W6 in the Encodedposition, connected between pins 1 and2. The clamp circuit is set by adjustingdepth of modulation pot R152 for thecorrect depth of modulation as measuredat TP2.Depending on the input video level, thewaveform as measured at TP2 may notbe 1 Vpk-pk. If W7 on J4 is moved to theClamp-Off (Manual) position, betweenpins 1 and 2, the clamp level is adjustedby R41 and will not automatically beclamped to the set level. The output ofbuffer amplifier U3A drives the sync tipclamp circuit consisting of differentialamplifier U4A, FET Q7, and bufferamplifier U3B. U4A is biased by R124,R125, R184, R152, and R126 so that theclamped voltage level at peak of sync isapproximately -1.04 VDC as measured atTP2.3.1.2.3 Main Video Signal Path (Part 2 of2)The clamped video from Q2 is connectedto white clipper circuit Q3. Q3 is adjustedwith R20 and set to prevent videotransients from overmodulating the videocarrier. The clamped video is connectedto sync clipper circuit Q4 (adjusted byR24); Q4 limits the sync to -40 IRE units.The corrected video connects to emitterfollower Q4 whose output is wired tounity gain amplifier U2A and provides alow-impedance, clamped video output atpin 1.3.1.2.4 Visual Modulator CircuitThe clamped video signal from U2A issplit. One part connects to a meteringcircuit, consisting of U20 and associatedcomponents, that produces a videooutput sample at J8-6 and connectsthrough the transmitter control board tothe front panel meter for monitoring. Theother clamped video path from U2A isthrough a sync-stretch circuit thatconsists of Q5 and Q6. The sync-stretchcircuit contains R48; R48 adjusts thesync stretch magnitude (amount) andR45 adjusts the cut-in. This sync-stretchadjustment should not be used to correctfor output sync problems, but it can beused for video input sync problems. Theoutput of the sync-stretch circuitconnects to pin 5, the I input of mixerZ1.The video signal is heterodyned in mixerZ1 with the visual IF CW signal (45.75MHz). The visual IF CW signal enters theboard at jack J15 and is connected to U9,where it is amplified and wired to pin 1,the L input of mixer Z1. The adjustablecapacitor C78 and resistor R53 are set upto add a small amount of incidentalcarrier phase modulation (ICPM)correction to the output of the mixerstage to compensate for any non-linearities generated by the mixer.The modulated 45.75-MHz RF output ofmixer Z1 is amplified by U5 and is fed todouble-sideband visual IF output jackJ18. The level of this output jack isadjusted by R70. J18 is the visual IFloop-through output jack that is normallyjumpered to J19 on the board. If theoptional visual IF loop-through kit ispurchased, the visual is connected out ofthe board to any external IF processortrays.After any external processing, themodulated visual IF, double-sidebandsignal re-enters the board through J19.The visual IF from J19 is amplified byU10 and U11 and routed through thevestigial sideband filter network,
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-5consisting of T1, FL1, and T2, andproduces a vestigial sideband visual IFsignal output. The filtered vestigialsideband visual IF is amplified by U7 andconnected to a T-type attenuator. R62can be adjusted to set the visual IF gain;this is the amount of visual IF signal thatis coupled to amplifier IC U8. R63 andC30 are adjusted for the best VSBFfrequency response. The amplified IFsignal is fed to the input of the diplexercircuit that consists of R76, L13, and L12.A detected voltage sample of the visualIF is available at test point TP5.3.1.2.5 41.25-MHz Aural IF CircuitOn this board, the 41.25-MHz aural IF iscreated by mixing the modulated 4.5-MHz aural intercarrier signal, producedby the aural IF synthesizer board or fromthe composite 4.5-MHz filter board, withthe 45.75-MHz CW signal produced bythe 45.75-MHz IF carrier oven oscillatorboard. The modulated 4.5-MHz auralintercarrier signal enters the board at J14or J28 and is connected to IF relay K1.Jumper W3 on J7 determines whetherthe 4.5-MHz used by the board isinternally generated or from an externalsource. With jumper W3 connectedbetween pins 2 and 3, the 4.5 MHz fromthe aural IF synthesizer board or fromthe 4.5-MHz composite input isconnected to mixer Z2. If an external4.5-MHz signal is used, it enters theboard at J12 and is fed through gain potR88 to amplifier IC U13A. The amplified4.5 MHz is then connected to J7 and, ifjumper W3 is between pins 1 and 2, the4.5-MHz signal from the external sourceis connected to the mixer. Mixer Z2heterodynes the aural-modulated, 4.5-MHz signal with the 45.75-MHz CW signalto produce the modulated 41.25-MHzaural IF signal.The output of the mixer is fed to abandpass filter that is tuned to pass onlythe modulated 41.25-MHz aural IF signalthat is fed to jack J16, the 41.25-MHzloop-through out jack of the board.For normal operation, the 41.25-MHzsignal is jumpered by a coaxial cablefrom J16 to J17 on the board. If the(optional) aural IF loop-through kit ispurchased, the 41.25-MHz signal isconnected to the rear of the tray, towhich any processing trays can beconnected, and then back to jack J17 onthe board. The modulated 41.25-MHzaural IF signal from J17 is connectedthrough amplifier ICs U15 and U16. Theamplified output is connected to theattenuator-matching circuit that isadjusted by R85. R85 increases ordecreases the level of the 41.25 MHz thatsets the A/V ratio for the diplexer circuit.The diplexer circuit takes the modulated45.75-MHz visual IF and the modulatedaural IF and combines them to producethe 45.75-MHz + 41.25-MHz IF output.The combined 45.75-MHz + 41.25-MHzIF signal is amplified by U12 andconnected to combined IF output jackJ20 on the board. A sample of thecombined IF output is provided at J21 onthe board. If a NICAM input is used, itconnects to J36 on the board. The levelof the NICAM signal is set by R109 beforeit is fed to the diplexer circuit consistingof L28, L29, and R115. This circuitcombines the NICAM signal with the45.75-MHz visual IF + 41.25-MHz auralIF signal.3.1.2.6 Operational VoltagesThe +12 VDC needed to operate thetransmitter control board enters theboard at J23, pin 3, and is filtered byL26, L33, and C73 before it is fed to therest of the board.The -12 VDC needed to operate theboard enters the board at J23, pin 5, andis filtered by L27 and C74 before beingfed to the rest of the board.3.1.3 (A6) Delay Equalizer Board(1227-1204; Appendix D)The delay equalizer board provides adelay to the video signal, correction to
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-6the frequency response, andamplification of the video signal.The video signal enters the board at J1-2and is connected to a pi-type, low-passfilter consisting of C16, L7, and C17. Thisfilter eliminates any unwanted higherfrequencies from entering the board. Theoutput of the filter is connected toamplifier stage U1; the gain is controlledby R29. The video output of the amplifierstage is wired to the first of four delay-equalizing circuits that shape the videosignal to the FCC specification for delayequalization or to the desired shapeneeded for the system. The board hasbeen factory-adjusted to this FCCspecification and should not bereadjusted without the properequipment.Resistors R7, R12, R17, and R22 adjustthe sharpness of the response curvewhile inductors L1, L2, L3, and L4 adjustthe position of the curve. With a delayequalizer test generator signal or a sinex/x video test pattern input, the resistorsand inductors can be adjusted, whilemonitoring a Tektronix VM700 testmeasurement set, until the desired FCCdelay equalization curve or system curveis attained. The delay-equalized videosignal is connected to J1-4, the videooutput of the board. A sample of thedelayed video signal is connected to J2on the board and can be used for testingpurposes.The ±12 VDC needed to operate theboard enters the board at J1. The +12VDC connects to J1-9, which is filtered byL5 and C11 before it is directed to therest of the board. The -12 VDC connectsto J1-6, which is filtered by L6 and C12before it is directed to the rest of theboard.3.1.4 (A7) IF Carrier Oven OscillatorBoard (1191-1404; Appendix D)The IF carrier oven oscillator boardgenerates the visual IF CW signal at45.75 MHz for NTSC system "M" usage.The +12 VDC is applied through jack J10to crystal oven HR1, which is preset tooperate at 60° C. The oven enclosescrystal Y1 and stabilizes the crystaltemperature. The crystal is the principaldevice that determines the operatingfrequency and is the most sensitive interms of temperature stability.Crystal Y1 operates in an oscillator circuitconsisting of transistor Q1 and itsassociated components. Feedback isprovided through a capacitor-voltagedivider, consisting of C5 and C6, thatoperates the crystal in a common-baseamplifier configuration using Q1. Theoperating frequency of the oscillator canbe adjusted by variable capacitor C17.The oscillator circuit around Q1 has aseparate regulated voltage, 6.8 VDC,which is produced by a combination ofdropping resistor R4 and zener diodeVR1. The output of the oscillator at thecollector of Q1 is capacitively coupledthrough C8 to the base of Q2. The smallvalue of C8, 10 pF, keeps the oscillatorfrom being loaded down by Q2.Q2 is operated as a common-emitteramplifier stage whose bias is providedthrough R8 from the +12 VDC line. Theoutput of Q2, at its collector, is splitbetween two emitter-follower transistorstages, Q3 and Q4. The output of Q3 istaken from its emitter through R11 toestablish an approximate 50-ohm sourceimpedance through C11 to J3, the mainoutput jack. This 45.75-MHz signal is atabout the +5 dBm power level. In mostsystems, this output is either directed toa visual modulator board or to somesplitting and amplifying arrangement thatdistributes the visual IF carrier for otherneeds. The second output from thecollector of Q2 is fed to the base of Q4,the emitter follower transistor.Q4 drives two different output circuits.One output is directed through voltagedividers R14 and R15 to jack J2 and ismeant to be fed to a frequency counter.While monitoring J2 the oscillator can beset exactly on the operating frequency
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-7(45.75 MHz) by adjusting C17. Theoutput at J2 is at a power level ofapproximately -2 dBm, which is sufficientto drive most frequency counters. Theother output of Q4 connects to prescalerchip U1, which divides the signal by 15.The output of U1 is applied to U2, aprogrammable divider IC. U2 isprogrammed through pins 11 to 20 todivide by 61. This results in a 50-kHzsignal at pin 9 that is available as anoutput at J1. The output of 50 kHz isgenerally used in systems where thevisual IF carrier oven oscillator is used asthe reference for a PLL circuit; anexample of this is when the PLL circuituses the aural IF synthesizer board andthe aural VCO. The 50-kHz CMOS outputat jack J1 is not capable of achievingenough drive level for a long coaxialcable length. As a result, when a longcoaxial cable is needed, the output atjack J5 is utilized. The push-pulltransistor stage Q5 and Q6, along withemitter resistor R18, provide a large-loadoutput capability at J5.The stages U1, U2, Q5, and Q6 arepowered by +5.1 VDC, which is obtainedby using the +12 VDC line voltage, andvoltage-dropping resistor R16 and zenerdiode VR2.The +12 VDC power is applied to theboard through jack J4, pin 3, and isisolated from the RF signals which mayoccur in the +12 VDC line through theuse of RF choke L2 and filter capacitorC10.3.1.5 (A8) ALC Board, NTSC (1265-1305; Appendix D)The automatic level control (ALC) boardprovides the ALC and amplitude linearitycorrection of the IF signal. The ALCadjusts the level of the IF signal throughthe board to control the output power ofthe transmitter.The visual + aural IF input (0 dBm)signal from the modulator enters theboard at modulator IF input jack J32. Ifthe (optional) receiver tray is present,the visual + aural IF input (0 dBm) fromthe receiver tray connects to receiver IFinput jack J1. The modulator IF inputconnects to relay K3 and the receiver IFinput connects to relay K4. The tworelays are controlled by the ModulatorSelect command that is connected to J30on the board. Modulator selectenable/disable jumper W11 on J29controls whether the Modulator Selectcommand at J30 controls the operation ofthe relays or not. With jumper W11 onJ29, pins 1 and 2, the Modulator Selectcommand at J30 controls the operation ofthe relays; with jumper W11 on J29, pins2 and 3, the modulator is selected all ofthe time.3.1.5.1 Modulator SelectedWith the modulator selected, J11-10 andJ11-28 on the rear of the UHF excitertray are connected together; this makesJ30 low and causes relays K3 and K4 tode-energize. When K4 is de-energized, itconnects the receiver IF input at J1, ifpresent, to 50 watts. When K3 is de-energized, it connects the modulator IFinput at J32 to the rest of the board;Modulator Enable LED DS5 will beilluminated.3.1.5.2 Receiver SelectedWith the receiver selected, which is J11-10 and J11-28 on the rear of the UHFexciter tray (connected to J30 on theboard) not connected together, relays K3and K4 are energized. When K4 isenergized, it connects the receiver IFinput at J1, if present, to the rest of theboard. When K3 is energized, it connectsto the modulator IF input at J32 to 50watts; Modulator Enable LED DS5 will beilluminated.3.1.5.3 Main IF Signal Path (Part 1 of 3)The selected visual + aural IF input (0dBm) signal is split, with one half of thesignal entering a bandpass filter thatconsists of L3, L4, C4, L5, and L6. This
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-8bandpass filter can be tuned with C4 andis substantially broader than the IF signalbandwidth. It is used to slightly steer thefrequency response of the IF to make upfor any small discrepancies in thefrequency response in the stages thatprecede this point. The filter also servesthe additional function of rejectingunwanted frequencies that may occur ifthe tray cover is off and the tray is in ahigh RF environment (if this is the case,the transmitter will have to be servicedwith the tray cover off in spite of thepresence of other RF signals). Thefiltered IF signal is fed through a pi-typematching pad consisting of R2, R3, andR4 to the pin-diode attenuator circuitconsisting of CR1, CR2, and CR3.3.1.5.4 Input Level Detector CircuitThe other part of the split IF input isconnected through L2 and C44 to U7; U7is an IC amplifier that is the input to theinput level detector circuit. The amplifiedIF is fed to T4; T4 is a step-uptransformer that feeds diode detectorCR14. The positive-going detected signalis then low-pass filtered by C49, L18, andC50. This allows only the video withpositive sync to be applied throughemitter follower Q1. The signal is thenconnected to detector CR15 to produce apeak-sync voltage that is applied to op-amp U9A. There is a test point at TP3that provides a voltage reference checkof the input level. The detector servesthe dual function of providing a referencethat determines the input IF signal levelto the board and also serves as an inputthreshold detector.The input threshold detector prevents theautomatic level control from reducing theattenuation of the pin-diode attenuator tominimum (the maximum signal) if the IFinput to the board is removed. The ALC,video loss cutback, and the thresholddetector circuits will only operate whenjumper W3 on jack J6 is in the Autoposition, between pins 1 and 2. Withoutthe threshold detector, and with the pin-diode attenuator at minimum, when thesignal is restored it will overdrive thestages following this board.As part of the threshold detectoroperation, the minimum IF input level atTP3 is fed through detector CR15 to op-amp IC U9A, pin 2. The reference voltagefor the op-amp is determined by thevoltage divider that consists of R50 andR51 (off the +12 VDC line). When thedetected-input signal level at U9A, pin 2,falls below this reference threshold(approximately 10 dB below the normalinput level), the output of U9A at pin 1goes to the +12 VDC rail. This high isconnected to the base of Q2. At thispoint, Q2 is forward biased and creates acurrent path from the -12 VDC line andthrough red LED DS1, the input levelfault indicator, which becomes lit, resistorR54, and transistor Q2 to +12 VDC. Thehigh from U9A also connects throughdiode CR16 to U9B, pin 5, whose outputat pin 7 goes high. The high connectsthrough range adjust pot R74 to J20,which connects to the front panel-mounted power adjust pot. This highconnects to U10A, pin 2, and causes it togo low at output U10A, pin 1. The low isapplied through jumper W3 on J6 to thepin-diode attenuator circuit that cutsback the IF level and, therefore, theoutput power level, to 0. When the inputsignal level increases above the thresholdlevel, the output power will raise, as theinput level increases, until normal outputpower is reached.The video input level at TP3 is also fed toa sync-separator circuit, consisting of ICU8, CR17, Q3, and associatedcomponents, and then to a comparatorcircuit made up of U9C and U9D. Thereference voltage for the comparators isdetermined by a voltage dividerconsisting of R129, R64, R65, R66, andR130 (off the -12 VDC line). When theinput signal level to the detector at TP3falls below this reference threshold,which acts as a loss of sync detectorcircuit, the output of U9C and U9D goestowards the -12 VDC rail and is split, withone part biasing on transistor Q5. A
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-9current path is then established from the+12 VDC line through Q5, the resistorsR69, R137, and the red LED DS3 (videoloss indicator), which becomes lit. WhenQ5 is on, it applies a high to the gates ofQ6 and Q7. This causes them to conductand apply video loss fault pull-downoutputs to J18, pins 5 and 2.The other low output of U9C and U9D isconnected through CR20 to jack J5.Jumper W2 on J5, in the Cutback Enableposition (between pins 2 and 3),connects the low to the base of theforward-biased Q4. If jumper W2 is inthe Disable position, between pins 1 and2, the auto cutback will not operate. WithQ4 biased on, a level determined by thesetting of cutback level pot R71, which isset at the factory to cut back the outputto approximately 25%, is applied to U9B,pin 5. The output of U9B at pin 7 goeslow and is applied through the poweradjust pot to U10A, pin 2, whose outputgoes low. This low is applied to the pin-diode attenuator to cut back the level ofthe output to approximately 25%.3.1.5.5 Pin-Diode Attenuator CircuitThe input IF signal is fed to a pin-diodeattenuator circuit that consists of CR1 toCR3. Each of the pin diodes contain awide intrinsic region; this makes thediodes function as voltage-variableresistors at this intermediate frequency.The value of the resistance is controlledby the DC bias supplied to the diode. Thepin diodes are configured in a pi-typeattenuator configuration where CR1 isthe first shunt element, CR3 is the serieselement, and CR2 is the second shuntelement. The control voltage, which canbe measured at TP1, originates eitherfrom the ALC circuit when jumper W3 onJ6 is in the ALC Auto position, betweenpins 1 and 2, or from pot R87 when thejumper is in the Manual Gain position.On the pin-diode attenuator circuit, acurrent path exists from J6 through R6and then through the diodes of the pinattenuator. Changing the amount ofcurrent through the diodes by forwardbiasing them changes the IF output levelof the board. There are two extremes ofattenuation ranges for the pin-diodeattenuators. In the minimum attenuationcase, the voltage, measured at TP1,approaches the +12 VDC line. There is acurrent path created through R6, throughseries diode CR3, and finally through R9to ground. This path forward biases CR3and causes it to act as a relatively low-value resistor. In addition, the largercurrent flow increases the voltage dropacross R9 that tends to turn off diodesCR1 and CR2 and causes them to act ashigh-value resistors. In this case, theshunt elements act as a high resistanceand the series element acts as a lowresistance to represent the minimum losscondition of the attenuator (maximumsignal output). The other extreme caseoccurs as the voltage at TP1 is reducedand goes towards ground or even slightlynegative. This tends to turn off (reversebias) diode CR3, the series element,causing it to act as a high-value resistor.An existing fixed current path from the+12 VDC line, and through R5, CR1,CR2, and R9, biases series element CR3off and shunt elements, diodes CR1 andCR2 on, causing them to act as relativelylow-value resistors. This represents themaximum attenuation case of the pinattenuator (minimum signal output). Bycontrolling the value of the voltageapplied to the pin diodes, the IF signallevel is maintained at the set level.3.1.5.6 Main IF Signal Path (Part 2 of 3)When the IF signal passes out of the pin-diode attenuator through C11, it isapplied to modular amplifier U1. Thisdevice includes within it the biasing andimpedance matching circuits that makesit operate as a wide-band IF amplifier.The output of U1 is available, as asample of the pre-correction IF fortroubleshooting purposes and systemsetup, at jack J2. The IF signal is thenconnected to the linearity correctorportion of the board.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-103.1.5.7 Linearity Corrector CircuitsThe linearity corrector circuits use threestages of correction to correct for anyamplitude non-linearities of the IF signal.Each stage has a variable thresholdcontrol adjustment, R34, R37, or R40,and a variable magnitude controladjustment, R13, R18, or R23. Thethreshold control determines the point atwhich the gain is changed and themagnitude control determines theamount of gain change that occurs oncethe breakpoint is reached. Two referencevoltages are needed for the operation ofthe corrector circuits. Zener diode VR1,with R33 and R135, provides a +6.8 VDCreference and the diodes CR11 and CR12provide a .9 VDC reference thattemperature compensates for the twodiodes in each corrector stage.For the linearity correctors to operate, anIF signal is applied to transformer T1,which doubles the voltage swing bymeans of a 1:4 impedancetransformation. Resistors R14, R15, andR16 form an L-pad that lowers the levelof the signal. The amount that the levelis lowered is adjusted by adding more orless resistance, using R13, in parallelwith the L-pad resistors. R13 is only inparallel when the signal reaches a levellarge enough to turn on the diodes CR4and CR5. When the diodes turn on,current flows through R13, putting it inparallel with the L-pad.When R13 is put in parallel with theresistors, the attenuation through theL-pad is lowered, causing signal stretch(the amount determined by theadjustment of R13). The signal is nextapplied to amplifier U2 to compensate forthe loss through the L-pad. Thebreakpoint, or cut-in point, for the firstcorrector is set by controlling where CR4and CR5 turn on. This is accomplished byadjusting cut-in resistor R34; R34 formsa voltage-divider network from +6.8 VDCto ground. The voltage at the wiper armof R34 is buffered by unity-gain amplifierU5D. This reference voltage is thenapplied to R35, R36, and C39 throughL12 to the CR4 diode. C39 keeps thereference from sagging during thevertical interval. The .9 VDC referencecreated by CR11 and CR12 is applied tounity-gain amplifier U5B. The referencevoltage is then connected to diode CR5through choke L11. The two chokes L11and L12 form a high impedance for RFthat serves to isolate the op-amp ICsfrom the IF.After the signal is amplified by U2, it isapplied to the second corrector stagethrough T2. This corrector and the thirdcorrector operate in the same fashion asthe first. All three corrector stages areindependent and do not interact witheach other.The correctors can be disabled by movingjumper W1 on J4 to the Disable position,between pins 2 and 3; this moves all ofthe breakpoints past the tip of sync sothat they will have no affect. The IFsignal exits the board at IF output jack J3after passing through the three correctorstages and is normally connected to anexternal IF phase corrector board.3.1.5.8 Main IF Signal Path (Part 3 of 3)After the IF signal passes through theexternal IF phase corrector board, itreturns to the ALC board at IF input jackJ7. The IF then passes through abandpass filter consisting of L20, C97,C62, L21, C63, L22, L23, C64, and C99.This bandpass filter is identical in bothform and function to the one described inSection 3.3 of this chapter. In this case,the filter is intended to make up for smallerrors in frequency response that areincurred by the signal while beingprocessed through the linearity andincidental phase correction circuits.Following the bandpass filter, the signalis split using L24, L25, and R89. Thesignal passing through L24 is the main IFpath through the board. A sample of thecorrected IF signal is split off andconnected to J10, the IF sample jack.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-11The IF connects to jacks J27 and J28.These jacks control whether a 6-dB padis included in the circuit by thepositioning of jumpers W9 and W10. The6-dB pad-in is when jumpers W9 andW10 are connected between pins 2 and 3on J27 and J28. The 6-dB pad-out iswhen jumpers W9 and W10 areconnected between pins 1 and 2 on J27and J28. Normally, the pad is out. The IFsignal is then applied to a two-stage,frequency-response corrector circuit thatis adjusted as needed.Variable resistors R103 and R106 adjustthe depth and gain of the notches andvariable caps C71 and C72 adjust thefrequency position of the notches. The IFsignal is amplified by U13 and U14 beforeit is connected to J12, the IF output jackof the board. R99 is an output leveladjustment that is set to provideapproximately 0 dBm of IF output at J12.A sample of the IF is fed to J11 toprovide an IF sample point that can bemonitored without breaking the signalpath and gives an indication of the IFsignal after the linearity and thefrequency-response correction takesplace.3.1.5.9 ALC CircuitThe other path of the corrected IF signalis used in the ALC circuit. The IF is wiredout of the splitter through L25 andconnects to op-amp U12. The output ofU12 is wired to jacks J8 and J9 on whichjumpers W4 and W8 control the normalor encoded operation of the ALC circuitry.For normal operation, jumper W4 on J8 isbetween pins 1 and 2 and jumper W8 onJ9 is between pins 1 and 2. The IF signalis applied to transformer T5; T5 doublesthe voltage swing by means of a 1:4impedance transformation before it isconnected to the ALC detector circuit onthe board and amplified by U10B.For normal operation, jumper W7 on J26is between pins 1 and 2 and jumper W5on J21 is between pins 1 and 2. Thedetected ALC voltage is wired to U10A,pin 2, where it is summed with the frontpanel power control setting. The outputpower adjustment for the transmitter isachieved, if the (optional) remote powerraise/lower kit (1227-1039) is purchased,by R75, a motor-driven pot controlled byswitch S1 on the board, or screwdriveradjust pot R1 on the front panel of theUHF exciter tray. An external powerraise/lower switch can be used byconnecting it to jack J10, at J10-11power raise, J10-13 power raise/lowerreturn, and J10-12 power lower, on therear of the UHF exciter tray. S1, or theremote switch, controls relays K1 and K2,which control motor M1 that movesvariable resistor R75. If the (optional)remote power raise/lower kit is notpurchased, the ALC voltage is controlledonly by screwdriver adjust pot R1 on thefront panel of the UHF exciter tray. TheALC voltage is set for .8 VDC at TP4 witha 0 dBm output at J12 of the board. Asample of the ALC at J19, pin 2, is wiredto the transmitter control board where itis used on the front panel meter and inthe AGC circuits.This ALC voltage, and the DC levelcorresponding to the IF level after signalcorrection, are fed to U10A, pin 2, whoseoutput at pin 1 connects to the ALC pin-diode attenuator circuit. If there is a lossof gain somewhere in an IF circuit, theoutput power of the transmitter will drop.The ALC circuit senses this drop at U10Aand automatically lowers the loss of thepin-diode attenuator circuit tocompensate by increasing the gain.The ALC action starts with the ALCdetector level that is monitored at TP4.The detector output at TP4 is nominally+.8 VDC and is applied through resistorR77 to a summing point at op-ampU10A, pin 2. The current available fromthe ALC detector is offset, orcomplemented, by current taken awayfrom the summing junction. In normaloperation, U10A, pin 2, is at 0 VDC whenthe loop is satisfied. If the recovered orpeak-detected IF signal at IF input jackJ7 of this board should drop in level,
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-12which normally means that the outputpower is decreasing, the null conditionwould no longer occur at U10A, pin 2.When the level drops, the output ofU10A, pin 1, will go more positive. Ifjumper W3 on J6 is in the Automaticposition, it will cause the ALC pin-diodeattenuators CR1, CR2, and CR3 to haveless attenuation and increase the IFlevel; this will act to compensate for thedecrease in level. If the ALC cannotincrease the input level enough to satisfythe ALC loop, due to there not beingenough range, an ALC fault will occur.The fault is generated because U10D, pin12, increases above the trip point set byR84 and R83 until it conducts. Thismakes U10D, pin 14, high and causes thered ALC Fault LED DS2 to light.3.1.5.10 Scrambled Operation withEncodingFor encoded, scrambled operation,jumper W4 on J8 must be connectedbetween pins 2 and 3, jumper W8 on J9must be between pins 3 and 2, jumperW7 on J26 must be between pins 2 and3, and jumper W5 on J21 must bebetween pins 2 and 3. The IF isconnected through W4 on J8 to the syncregeneration circuits.If this board is operated with scrambling,using suppressed sync, the ALC circuitoperates differently than described abovebecause there is no peak of sync presenton the IF input. A timing pulse from thescrambling encoder connects to theboard at J24. This timing pulse isconverted to sync pulses by U17A andU17B, which control the operation of Q8.The sync amplitude is controlled by R149and is then applied to U15A, where it isadded to the detected IF signal toproduce a peak of sync level. The outputof U15A is peak detected by CR26 andfed to U15B. If necessary, intercarriernotch L39 can be placed in the circuit byplacing W6 on J22. The intercarrier notchis adjusted to filter any aural and 4.5-MHz intercarrier frequencies. The peak ofsync signal is fed through R162, the ALCcalibration control, to amplifier U15C. Theamplified peak of sync output isconnected through J21, pins 2 and 3, toU10A, where it is used as the referencefor the ALC circuit and the AGC referenceto the transmitter control board. VoltageTP4 should be the same in either thenormal or the encoded video mode.Monitor J9, pins 3 and 4, with a spectrumanalyzer, check that the board is in theAGC mode, and tune C103 to notch-outthe aural IF carrier.3.1.5.11 Fault CommandThe ALC board also has circuitry for anexternal mute fault input at J19, pin 6.This is a Mute command and, in mostsystems, it is involved in the protectionof the circuits of high-gain outputamplifier devices. The Mute command isintended to protect the amplifier devicesagainst VSWR faults. In this case, theaction should occur faster than justpulling the ALC reference down. Twodifferent mechanisms are employed: oneis a very fast-acting circuit to increasethe attenuation of the pin-diodeattenuator, CR3, CR1, and CR2, and thesecond is the reference voltage beingpulled away from the ALC amplifierdevice. An external Mute is a pull-downapplied to J19, pin 6, to provide a currentpath from the +12 VDC line through R78and R139, the LED DS4 (Mute indicator),and the LED section of opto-isolator U11.These actions turn on the transistorsection of U11 that applies -12 VDCthrough CR21 to U10A, pin 3, and pullsdown the reference voltage. This is afairly slow action that is kept at this paceby the low-pass filter function of R81 andC61. When the transistor section of U11is on, -12 VDC is also connected throughCR22 to the pin-diode attenuator circuit.This establishes a very fast mutingaction, by reverse biasing CR3, in theevent of an external VSWR fault.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-133.1.5.12 ±12 VDC Needed to Operate theBoardThe ±12 VDC connects to the board atJ14. The +12 VDC connects to J14-3 andis filtered by L30, L41, and C80 before itis applied to the rest of the board. The-12 VDC connects to J14-5 and is filteredby L31 and C81 before it is applied to therest of the board.The +12 VDC also connects to U16, a 5-VDC regulator IC, that produces the +5VDC needed to operate timing IC U17.3.1.6 (A9) IF Phase Corrector Board(1227-1250; Appendix D)The IF phase corrector board hasadjustments that pre-correct for any IFphase modulation distortion that mayoccur in output amplifier devices such asKlystron power tubes and solid-stateamplifiers. Two separate, adjustable IFpaths are on the board: a quadrature IFpath and an in-phase IF path. Thequadrature IF is 90° out of phase andmuch larger in amplitude than the in-phase IF. When they are combined in Z1,it provides the required adjustable phasecorrection to the IF signal.The IF input signal enters at J1 and is ACcoupled to U1. U1 amplifies the IF beforeit is connected to Z1, a splitter thatcreates two equal IF outputs: IF output 1is connected to J2 and IF output 2 isconnected to J3. The IF output 1 at J2 isjumpered through coaxial cable W4 tojack J6, the quadrature input, on theboard. The IF output 2 at J3 is jumperedthrough coaxial cable W5 to jack J7, thein-phase input, on the board.3.1.6.1 Phase Corrector CircuitThe phase corrector circuit corrects forany amplitude nonlinearities of the IFsignal. It is designed to work at IF andhas three stages of correction. Eachstage has a variable threshold andmagnitude control. The threshold controldetermines the point at which the gain ischanged and the magnitude controldetermines the gain change once thebreakpoint is reached. The second stagehas a jumper that determines thedirection of correction, so that the gaincan increased either above or below thethreshold, and either black or whitestretch can be achieved.In the phase corrector circuit, the IFsignal from J6 is applied to transformerT1; T1 doubles the voltage swing using a1:4 impedance transformation. ResistorsR8, R61, R9, and R48 form an L-pad thatattenuates the signal. This attenuation isadjusted by adding R7, a variableresistor, in parallel with the L-pad. R7 isonly in parallel when the signal reaches alevel large enough to bias on CR1 andCR2 and allow current to flow throughR7. When R7 is put in parallel with the L-pad, the attenuation through the L-pad islowered, causing black stretch.Two reference voltages are utilized in thecorrector stages and both are derivedfrom the +12 VDC line. Zener diode VR1,with R46 as a dropping resistor, provides+6.8 VDC from the +12 VDC line. DiodesCR11 and CR12 provide a .9 VDCreference to temperature compensatethe corrector circuits from the effects ofthe two diodes in each corrector stage.The threshold for the first corrector stageis set by controlling where CR1 and CR2turn on. This is accomplished byadjusting R3 to form a voltage dividerfrom +6.8 VDC to ground. The voltage atthe wiper of R3 is buffered by U9C, aunity-gain amplifier, and applied to CR1.The .9 VDC reference is connected toU9D, a unity-gain amplifier, whoseoutput is wired to CR2. These tworeferences are connected to diodes CR1and CR2 through chokes L2 and L3. Thetwo chokes form a high impedance for RFto isolate the op-amps from the RF. Theadjusted signal is next applied toamplifier U2 to compensate for the lossthrough the L-pad. U2 is poweredthrough L4 and R10 from the +12 VDCline. After the signal is amplified by U2, it
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-14is applied to the second corrector stagethrough T2 and then to a third correctorstage through T3. The other twocorrector stages operate in the samemanner as the first; they areindependent and do not interact witheach other.When jumper W1 on J8 is connectedfrom center to ground, R15 is put inseries with ground. In this configuration,black stretch (white compression) isapplied to the IF signal by controlling theattenuation through the path. When W1is connected from the center pin to theend that connects to T2, R15 is put inparallel with the L-pad. In thisconfiguration, black compression (whitestretch) is applied to the IF signal bycontrolling the attenuation through thepath.The phase correctors can be bypassed bymoving jumper W2 on J9 to the Disableposition. This action will move all of thethreshold points past sync tip so thatthey will have no effect. R68 can beadjusted and set for the correction rangethat is needed. TP2 is a test point thatgives the operator a place to measurethe level of the quadrature IF signal thatis connected to pin 6 on combiner Z2.3.1.6.2 Amplitude Corrector CircuitThe amplitude corrector circuit uses onestage of correction to correct for anyamplitude nonlinearities of the IF signal.The stage has a variable thresholdcontrol, R31, and a variable magnitudecontrol, R35. The threshold controldetermines the point at which the gain ischanged and the magnitude controldetermines the amount of gain changeonce the breakpoint is reached.Two reference voltages are needed forthe operation of the corrector circuit.Zener diode VR1 with R46 provides +6.8VDC and the diodes CR11 and CR12provide a .9 VDC reference voltage totemperature compensate for the twodiodes in the corrector stage. In theamplitude corrector circuit, the IF signalfrom J7 is applied to transformer T4 todouble the voltage swing by means of a1:4 impedance transformation. ResistorsR36, R55, R56, and R37 form an L-padthat lowers the level of the signal. Theamount that the level is lowered isadjusted by adding more, or less,resistance, using R35 in parallel with theL-pad resistors. R35 is only in parallelwhen the signal reaches a level largeenough to turn on diodes CR8 and CR9.When the diodes turn on, current flowsthrough R35 and puts it in parallel withthe L-pad. When R35 is in parallel withthe resistors, the attenuation through theL-pad is lowered, causing signal stretch(the amount of stretch determined by theadjustment of R35).The signal is next applied to amplifier U5to compensate for the loss in levelthrough the L-pad. The breakpoint, orcut-in point, for the corrector stage is setby controlling where CR8 and CR9 turnon. This is achieved by adjusting cut-inresistor R31 to form a voltage dividerfrom +6.8 VDC to ground. The voltage atthe wiper arm of R31 is buffered byunity-gain amplifier U8B. This voltage isthen applied to R34 through L11 to theCR9 diode. The .9 VDC reference createdby CR11 and CR12 is applied to unity-gain amplifier U8A. C36 keeps thereference from sagging during thevertical interval. The reference voltage isthen connected to diode CR8 throughchoke L12. The two chokes L11 and L12form a high impedance for RF to isolatethe op-amp ICs from the IF.After the signal is amplified by U5, it isapplied to a second stage through T5.The transformer doubles the voltageswing by means of a 1:4 impedancetransformation. Resistors R39, R57, R58,and R40 form an L-pad that lowers thelevel of the signal. The signal is appliedto amplifier U6 to compensate for theloss in level through the L-pad. After thesignal is amplified by U6, it is applied to athird stage through T6. The transformerdoubles the voltage swing by means of a
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-151:4 impedance transformation. ResistorsR42, R59, R60, and R43 form an L-pad tolower the level of the signal. The signal isapplied to amplifier U7 to compensate forthe loss in level through the L-pad. TP1 isa test point that gives the operator aplace to measure the level of the in-phase IF signal that is connected tomixer stage Z2. The amplitude correctorcan be disabled by moving jumper W3 onJ10 to the Disable position; this will movethe breakpoint past sync tip and will haveno effect on the signal.3.1.6.3 Output CircuitThe phase-corrected signal from pin 1 oncombiner Z2 exits the board at IF outputjack J4 after passing through a matchingnetwork consisting of six resistors.3.1.7 (A11) VHF Mixer/AmplifierEnclosure Assembly (1088067;Appendix C)The VHF mixer/amplifier enclosureassembly is made up of the x4 multiplierboard, the VHF filter/mixer board, andthe high-band VHF filter/amplifier board.3.1.7.1 (A1) x4 Multiplier Board (1174-1112; Appendix D)The x4 multiplier board multiplies thefrequency of an RF input signal by afactor of four. The board is made up oftwo identical x2 broadband frequencydoublers.The input signal (+5 dBm) at thefundamental frequency enters throughSMA jack J1 and is fed through a 3-dBmatching pad, consisting of R1, R2, andR3, to amplifier IC U1. The output of theamplifier stage is directed through abandpass filter, consisting of L2 and C4,that is tuned to the fundamentalfrequency. The voltage measured at TP1is typically +0.6 VDC. The first doublerstage consists of Z1 with bandpass filterL3 and C6 tuned to the second harmonic.The harmonic is amplified by U2 and fedthrough a bandpass filter, consisting ofC10 and L5, also tuned to the secondharmonic frequency. The voltagemeasured at TP2 is typically +1.2 VDC.The next doubler stage consists of Z2with bandpass filter C12 and L6 tuned tothe fourth harmonic of the fundamentalfrequency. The fourth harmonic is thenamplified by U3 and fed to the SMAoutput jack of the board at J2. Thetypical LO signal output level is a nominal+15 dBm.The +12 VDC for the board entersthrough jack J3-3 and is filtered by L7and C16 before being distributed to thecircuits on the board.3.1.7.2 (A2) VHF Filter/Mixer Board(1150-1102; Appendix D)The VHF filter/mixer board is made up ofthree separate circuits: a filter andamplifier circuit for the LO input, a mixerstage, and a filter and amplifier for theRF output of the mixer. The board ismounted inside of (A11) the VHFmixer/amplifier enclosure assembly(1088067), an aluminum enclosure thatprovides RFI protection. Thefilter/amplifier board (1064252) is alsomounted inside the enclosure.The LO input (+5 dBm) connects to theboard at J3 and is fed to a filter circuit.The input to the filter consists of C11,C12, and L5, with C12 adjusted for thebest input loading. C13 and C17 areadjusted for the best frequency responseand C18 is adjusted for the best outputloading of the LO signal. Capacitor C15 isadjusted for the best coupling. Thefiltered LO is amplified by U2 andconnected to LO output jack J4. Typically,the output at jack J4 is jumpered by acoaxial jumper to jack J5 on the board.The LO at J5 connects to mixer Z1 at pin1 (+14 dBm).The IF input connects to the board at J7and is fed to mixer Z1 at pin 3 (-3 dBm).
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-16Mixer Z1 takes the LO input at pin 1 andthe IF input at pin 3 to produce an RFoutput at pin 8. The RF output at pin 8(-14 dBm) connects through a pi-typeattenuator, made up of R3, R4, and R5,before it is connected to RF output jackJ6. Normally, jack J6 is connected by acoaxial jumper to J1 on the board. J1connects to the input of a filter circuit,consisting of C25, C1, C23, C2, and L1,with C2 adjusted for the best inputloading. C3 and C6 are adjusted for thebest center frequency, C4 is adjusted forthe best coupling, and C7 is adjusted forthe best output loading of the RF signal.The filtered RF is amplified by U1 andconnected to the RF output jack for theboard at J2 (-2 dBm).The +12 VDC needed for the operation ofthe board is supplied by an externalpower supply in the tray. The +12 VDCenters the board at J8, pin 3, and isfiltered and isolated from the rest of thetray by L7 and C22 before being appliedto the board.3.1.7.3 (A3) High-Band VHF Filter/Amplifier Board (1064252; Appendix D)The VHF high-band filter/amplifier boardis made up of two separate circuits: afilter circuit and an amplifier with a gaincontrol circuit.The RF input connects to the board at J7and is fed through a channel filter circuit.The input to the filter consists of C27,C28, and C29, with C29 adjusted for thebest input loading. C23 and C26 areadjusted for center frequency, with C24adjusted for the best coupling, and C20 isadjusted for the best output loading ofthe RF signal. The filtered RF isconnected to RF output jack J6; J6 isusually jumpered to jack J1 on the board.The filtered RF at J1 connects through a7-dB pi-type attenuator, consisting of R1,R2, and R3, before it is wired to a pin-diode attenuator circuit. The pin-diodeattenuator circuit is made up of CR1,CR2, and CR3 and is controlled by thebias current applied through R5. Thediodes CR1, CR2, and CR3 are pin-typediodes with a broad intrinsic regionsandwiched inside the diode. This broadintrinsic region causes the pin diodes toact as variable resistors instead of asdetecting devices at the RF frequencies.The resistance values of the pin diodesare determined by the relative amount offorward bias that is applied to the diodes.Jumper W1 on J5 is set for manual gainor auto gain by its position on the jack.Between 1 and 2 is manual gain, whichuses pot R9 to set the output level;between 2 and 3 is auto gain, which usesthe external control voltage input to jackJ4 as the level control (this arrangementis not used in this configuration).The level-controlled RF is pre-amplifiedby U1 and connected to Q1, the outputamplifier for the board. C17 is used tomaximize the RF signal. The RF output isamplified by Q1 and applied to the RFoutput jack for the board at J2.The output from Q1 is first fed throughdirection coupler Z1 before exiting theboard at J2, the RF output. The RFsample derived from Z1 has twofunctions. The first function is to providean RF sample at J8 on the board which isfed to the front panel of the exciter traythrough a voltage divider consisting ofR19 and R18. The second function is toprovide a peak-detected voltage that isused by the exciter tray for meteringpurposes. The sample provided by Z1,pin 3, is first fed through a dB padconsisting of R20, R21, and R22. Thevoltage is stepped up by 1-to-4transformer T1. The signal is then peakdetected by C32 and C14 before beingbuffered and amplified by U2. The peak-detected voltage that is used formetering purposes is controlled by potR28 on the board.The +12 VDC needed for the operation ofthe board is supplied by an externalpower supply in the tray. The +12 VDCenters the board at J3, pin 3, and isfiltered and isolated from the rest of the
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-17tray by L5 and C19 before being appliedto the entire board. The –12 VDC entersthe board at J3, pin 5, and is filtered andisolated from the rest of the tray by L6and C35 before being applied to theentire board.3.1.8 (A17) Transmitter ControlBoard (1265-1311; Appendix D)The transmitter control board providesinformation on system control functionsand the operational LED indications;these can be viewed on the front panel ofthe transmitter. The main controlfunctions are for the Operate/Standbyand Auto/Manual selections. When thetransmitter is switched to Operate, theboard supplies the enables to anyexternal amplifier trays. The board alsoperforms the automatic switching of thetransmitter to Standby upon the loss ofthe video input when the transmitter is inAuto.The transmitter control board contains aVSWR cutback circuit. If the VSWR of thetransmitter increases above 20%, theVSWR cutback circuit will become activeand cut back the output level of thetransmitter, as needed, to maintain amaximum of 20% VSWR. An interlock(low) must be present at J8-24 for thetransmitter to be switched to Operateand, when the interlock is present, thegreen Interlock LED DS5 will be lit.3.1.8.1 Operate/Standby Switch S1K1 is a magnetic latching relay thatcontrols the switching of the transmitterfrom Operate and Standby. When theOperate/Standby switch S1, on the frontpanel of the tray, is moved to Operate,one coil of relay K1 energizes and causesthe contacts to close and apply a low toU4B-9. If the transmitter interlock ispresent, and there is no overtemperaturefault, lows will also be applied to U4B-10,U4B-11, and U4B-12.With all the low inputs to U4B, the outputat U4B-13 will be low. The low biases offQ1 and this turns off the amber StandbyLED DS1 on the front panel. In addition,this action applies a high to Q2 and turnson and lights the green Operate LED DS2(also on the front panel). When Q2 isbiased on, it connects a low to Q12 andbiases it off; this allows the ALC to beapplied to J1 and connect to any externalamplifier trays. The low from U4B-13 isalso applied to Q4 and Q24, which arebiased off, and removes the disablesfrom J1-4 and J18-1. The low from U4B-13 also connects to Q10, which is biasedon, and connects a high to Q6, Q7, Q8,and Q9; these are biased on and apply-12 VDC enables to J8-2, J8-3, J8-4, andJ8-5, which connect to any externalamplifier trays. The high applied to Q2 isalso connected to Q5 and Q26, which arebiased on, and apply a low enable to J1-3, which connects to a remote operateindicator. The transmitter is now in theOperate mode.When the Operate/Standby switch S1 ismoved to Standby, the other coil of relayK1 energizes, causing the contacts toopen and a high (+12 VDC) to be appliedto U4B-9. The high at the input causesthe output at U4B-13 to go high. Thehigh biases on Q1 and applies a low tothe amber Standby LED DS1, on thefront panel, and turns on and applies alow to Q2. This causes Q2 to turn off andextinguishes the green Operate LED DS2.When Q12 is biased on, the output fromU2C goes low and pulls the ALC voltagesat J1 low; this lowers the gain of theexternal amplifier trays. The high fromU4B-13 is applied to Q4 and Q24, whichare biased on, and applies disables at J1-4 and J18-1. The high from U4B-13connects to Q10, which is biased off. TheQ10 bias off removes the high from Q6,Q7, Q8, and Q9, which are biased off,and removes the -12 VDC enables at J8-2, J8-3, J8-4, and J8-5, which connect tothe external amplifier trays. The lowapplied to Q2 is also connected to Q5 andQ26, which are biased off, and removesthe remote enable at J1-3. Thetransmitter is now in the Standby mode.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-183.1.8.2 Automatic/Manual Switch S2K2 is a magnetic latching relay thatswitches the operation of the transmitterto Automatic or Manual using Auto/Manual switch S2 on the front panel ofthe tray.When S2 is set to the Auto position, theoperation of the transmitter is controlledby the fault circuits and will stay inOperate even if Operate/Standby switchS1 is moved to Standby. With S2 in Auto,a low is applied to one coil in the relayand this energizes and closes thecontacts. The closed contacts apply a lowto the green Automatic LED DS3; as aresult, DS3 is illuminated. The low fromthe relay connects to U5A, pin 2; U5D,pin 13; Q21; and Q23. When Q21 andQ23 are biased off, this causes theiroutputs to go high. The high from Q21connects to the amber Manual LED DS4,on the front panel, biasing it off, and toQ22, biasing it on. The drain of Q22 goeslow and is applied to J8-7; this enablesany remote auto indicator connected toJ8-7. The low to Q23 biases it off andremoves the enable to any remotemanual indicator connected to J8-6.When S2 is set to the Manual position,the operation of the transmitter is nolonger controlled by the fault circuits; it iscontrolled by Operate/Standby switch S1.With S2 in Manual, a low is applied to theother coil in the relay and this energizesand opens the contacts. The opencontacts remove the low from the greenAutomatic LED DS3 on the front paneland causes it to not light. The highconnects to U5A, pin 2; U5D, pin 13;Q21; and Q23. Q21 and Q23 are biasedon; this causes their outputs to go low.The low from Q21 connects to the amberManual LED DS4 on the front panel,biasing it on, and to Q22, biasing it off.The drain of Q22 goes high and is appliedto J8-7; this will disable any remote autoindicators connected to it J8-7. Q23 isbiased on and applies a low enable to anyremote manual indicator connected to J8-6.3.1.8.3 Automatic Turning On and Off ofthe Transmitter Using the Presence ofVideoThe transmitter control board also allowsthe transmitter to be turned on and offby the presence of video at thetransmitter when the transmitter is inAuto. When a video fault occurs due tothe loss of video, J7-5 goes low. The lowis applied through W1, on J10, to Q16,which is biased off, and to the red VideoLoss Fault LED DS9, on the front panel,which will light. The drain of Q16 goeshigh and connects to U5B, pin 5, causingthe output at pin 4 to go low. The lowconnects to Q18, which is biased off, andcauses the drain of Q18 to go high. Thehigh connects to U3D, pin 12, whoseoutput at pin 14 goes high. The highconnects to U5C, pins 8 and 9, causingits output at pin 10 to go low, and toU5A, pin 1, causing its output at pin 3 togo low.With S2 set to Automatic, a low is appliedto U5A, pin 2, and to U5D, pin 13. WhenU5A, pin 1, is high and U5A, pin 2, is low,it causes the output at pin 3 to go low.When U5D, pin 12, is low and U5D, pin13, is low, it causes its output to go high.When U5A, pin 3, is low, it biases off Q20and removes any pull down to theOperate switch. A high at U5D, pin 11,biases on Q19 and applies a low enableto the Standby switch that places thetransmitter in the Standby mode.When the video signal is returned, J7-5goes high. The high is applied to Q16,which is biased on, and to the red VideoFault LED DS9, which is extinguished.The output of Q16 goes low and connectsto U5B, pin 5. If there is no receiver ALCfault, U5B, pin 6, is also low; this causesthe output at pin 4 to go high. The highconnects to Q18, which is biased on, andcauses the drain of Q18 to go low. Thelow connects to U3D, pin 12, whoseoutput at pin 14 goes low. The lowconnects to U5C, pins 8 and 9, whichcauses its output at pin 10 to go high,and to U5A, pin 1. With Auto/Manual
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-19switch S2 in Auto, a low is applied toU5A, pin 2, and to U5D, pin 13. WhenU5A, pins 1 and 2, is low, its output atpin 3 goes high. When pin 12 of U5D ishigh, the output of U5D at pin 11 goeslow. When U5A, pin 3, is high, it biaseson Q20 and applies a pull-down enable tothe Operate switch. A low at U5D, pin 11,biases off Q19 and removes any pulldown to the Standby switch. As a resultof these actions, the transmitter isswitched to Operate.3.1.8.4 FaultsThere are four possible faults, video lossfault, VSWR cutback fault,overtemperature fault, and ALC fault,which may occur in the transmitter andare applied to the transmitter controlboard. During normal operation, no faultsare sent to the board. The receiver ALCfault circuit will only function if a receivertray is part of the system. Theovertemperature fault is only used with2-kW transmitters and is controlled bythe temperature of the reject load.3.1.8.5 Video Loss FaultIf a video loss occurs while thetransmitter is in Auto, the system willchange to the Standby mode until thevideo is returned; at that point, it willimmediately revert to Operate. A videoloss fault applies a low from the ALCboard to the video fault input atJ7-5 on the board.With jumper W1 in place on J10, thevideo fault is connected to LED DS9 andto Q16. The red Video Loss Fault LEDDS9 on the front panel will light. Q16 isbiased off and causes its drain to go high.The high is wired to U5B, pin 5, whoseoutput at U5B, pin 4, goes low. The lowis wired to Q18, which is biased off, andcauses the drain to go high. The high isconnected to U3D, pin 12, which causesits output at U3D, pin 14, to go high. Thehigh connects to U5A, pin 1, and, if thetransmitter is in Auto, pin 2 of U5A islow. When pin 1 is high and pin 2 is low,the output of U5A goes low and reversebiases Q20, shutting it off. The high atU5C, pins 8 and 9, causes its output atpin 10 to go low. This low is connected toU5D, pin 12, and, if the transmitter is inAuto, pin 13 of U5D is also low. The lowson pins 12 and 13 cause the output to gohigh and forward bias Q19. The drain ofQ19 goes low and connects the coil inrelay K1, causing it to switch to Standby.When the video returns, the video lossfault is removed from the video faultinput at J7-5. With jumper W1 in placeon J10, the base of Q16 goes high. Thered Video Loss Fault LED DS9 on thefront panel will be extinguished. Q16 isbiased on, which causes its drain to golow. The low is wired to U5B, pin 5; U5B,pin 6, will be low if no ALC fault occurs.The two lows at the inputs make theoutput at U5B, pin 4, go high. The high iswired to Q18, which is biased on, causingthe drain to go low. The low is connectedto U3D, pin 12, which causes its outputat U3D, pin 14, to go low. The lowconnects to U5A, pin 1, and, if thetransmitter is in Auto, pin 2 of U5A isalso low. With both inputs low, theoutput of U5A at pin 3 goes high. Thehigh forward biases Q20 and causes itsdrain to go low. The low connects to theoperate coil on relay K1 that switches thetransmitter to Operate. The low at U5C,pins 8 and 9, causes its output at pin 10to go high. This high is connected toU5D, pin 12, and, if the transmitter is inAuto, pin 13 of U5D is low. The high onpin 12 causes the output of U5D to golow and reverse bias Q19. The drain ofQ19 goes high and this removes the lowfrom the standby coil in relay K1.3.1.8.6 Overtemperature FaultIn the 1-kW transmitter, there is noconnection to the overtemperature circuiton the transmitter control board. In the2-kW transmitter, the thermal switch onthe output dummy load connects to J8-1on the board. In the 100-watttransmitter, the (A6) thermal switch on(A23) the 100-watt amplifier heatsink
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-20assembly connects to J12 on the board.If the temperature of the thermal switchraises above 170° F, it closes and appliesa low to J8-1 or to J12. The low connectsto Q3, which is biased off, and to the redOvertemperature LED DS6, which isbiased on. The drain of Q3 goes high andconnects to pins 11 and 12 of U4B. Thehigh at the input to U4B causes it to gohigh and switches the system toStandby; this removes the OperateEnable commands to any externalamplifier trays.3.1.8.7 VSWR Cutback FaultThe reflected power sample of the RFoutput of the transmitter is connected toJ2, pin 9, of the transmitter controlboard. The sample connects to op-ampU1B, pin 5, which buffers the signalbefore it is split. One of the split-reflectedsamples connects to J1-5 on the board;J1-5 is wired to J10-5 on the rear of thetray for remote monitoring. Another split-reflected sample connects to position 3on the front panel meter for the tray. Thefinal split remote-reflected sampleconnects to U2B, pin 5.If the reflected sample level increasesabove the level set by R22, the VSWRcutback pot, the output of U2B at pin 7,goes high. The high is connected to Q11through CR11, which is biased on,making U2C, pin 10, low and causingU2C, pin 8, to go low. This low is splitand fed out of the tray at J1-6, J1-7, J1-8, and J1-9. These are ALC outputs tothe amplifier trays that cut back theoutput power of the amplifier trays. Thelow from U2C, pin 8, is also fed throughcoaxial jumper W2 on J13 and J14 toR73. R73 is a bias-adjust pot that setsthe level of the pin attenuator biasavailable as an output at J16. The high atU2B, pin 7, is also fed to the base of Q14and Q13, which are forward biased. Thisproduces a low at the drains that connectto the front panel amber VSWR CutbackLED DS7, causing it to light and indicatethat the tray is in cutback, and to outputjack J8-37 for the connection to a remoteVSWR cutback indicator.3.1.8.8 Receiver ALC FaultIf a receiver tray is part of the system, asample of the ALC voltage from this trayis connected to J8-11 on the transmittercontrol board. If the receiver is operatingnormally, the ALC level that is applied toU3C, pin 9, remains below the trip levelset by R35; as a result, the output at pin13 stays high. The high is applied to thered ALC Fault LED DS8, which is off. Thehigh also connects to U3A, pin 2, and toQ15. Q15 is biased on and the draingoes low. The low connects to U5B, pin6. In addition, U5B normally has a lowthat is connected to U5B, pin 5, andproduces a high at output pin 4. The highis wired to Q18, which is biased on, andmakes its drain low. The low connects toU3D, pin 12, which, because the level isbelow the preset, the output at U3D, pin14, goes low. A low at this point indicatesa no-fault condition. The high that isconnected to U3A, pin 2, causes itsoutput to go low. The low is connected toQ25, which is biased off. The low isremoved from J8-12, which will not lightany remote receiver fault indicator that isconnected to it.If the receiver malfunctions, the ALClevel applied to U3C, pin 9, goes high.This is above the level set by R35 andcauses the output at pin 13 to go low.The low is applied to the red ALC FaultLED DS8, which lights. The low alsoconnects to U3A, pin 2, and to Q15. Q15is biased off and the drain goes high. Thehigh connects to U5B, pin 6, andproduces a low at output pin 4. The lowis wired to Q18, which is biased off, andthis makes its drain go high. The highconnects to U3D, pin 12 and, becausethe level is above the preset, the outputat U3D, pin 14, goes high. A high at thispoint indicates a fault condition thatswitches the transmitter to Standby. Thelow connected to U3A, pin 2, causes itsoutput to go high. The high is connectedto Q25, which is biased on, and causes
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-21the drain to go low. The low is connectedto J8-12, which can light any remotereceiver fault indicator that is connectedto it.3.1.8.9 MeteringThe front panel meter connects to J3-1(-) and J3-2 (+), the output of switch S3,on the transmitter control board. Thefront panel meter has seven meteringpositions which are controlled by S3:Audio, Video, % Aural Power, % VisualPower, % Reflected Power,% Exciter, and ALC. The video sampleconnects to the board at J5-4 and isconnected through video calibration potR20 to position 6 on front panel meterswitch S3. The audio sample enters theboard at J5-6 and is connected throughaudio calibration pot R19 to position 7 onfront panel meter switch S3.The reflected sample connects to theboard at J2-9 and is connected throughbuffer amplifier U1B and 100Ω resistorR84 to position 3 on front panel meterswitch S3. The visual sample connects tothe board at J2-5 and is connectedthrough buffer amplifier U1D and 100Ωresistor R86 to position 4 on front panelmeter switch S3. The aural sampleconnects to the board at J2-7 and isconnected through buffer amplifier U1Cand 100-watt resistor R85 to position 5on front panel meter switch S3. Theexciter sample connects to the board atJ2-3 and is connected through bufferamplifier U1A and 100Ω resistor R87 toposition 2 on front panel meter switchS3. The ALC sample connects to theboard at J6-1 and is connected throughbuffer amplifier U2C and ALC calibrationpot R15 (which adjusts the output ofU2A, pin 1) and through 100Ω resistorR18 to position 1 on front panel meterswitch S3. Typical readings on the meterare:• Video = 1 Vpk-pk at white• % Reflected = < 5%• % Visual power = 100%• % Aural power = 100%• % Exciter = The level on the meterneeded to attain 100% output powerfrom the transmitterRefer to the test specifications sheet forthe transmitter for the actual reading:• ALC = .8 VDC• Audio = ±25 kHz with a balancedaudio input or ±75 kHz with acomposite audio inputSamples are provided for the remotemetering of the exciter at J1-10, thevisual at J8-26, the aural at J8-27, andthe reflected at J1-5.U6 is a temperature-sensor IC that givesthe operator the ability to measure thetemperature inside the tray by measuringthe voltage at TP1. The sensor is set upfor +10 mV equals 1° F (for example,750 mV equals 75° F).3.1.8.10 Operational VoltagesThe +12 VDC needed for the operation ofthe transmitter control board enters theboard at jack J4, pin 3. C28, L1, and L3are for the filtering and isolation of the+12 VDC before it is split and applied tothe rest of the board. The -12 VDCneeded for the operation of the boardenters the board at jack J4, pin 5. C29and L2 are for the filtering and isolationof the -12 VDC before it is split andapplied to the rest of the board.The +12 VDC is split when it is connectedto the board. Four of the +12 VDCoutputs are fed out of the board at J8-16,J8-17, J8-18, and J8-19 through diodesCR7, CR8, CR9, or CR10 and resistorsR50, R51, R52, or R53 are fed to anyexternal amplifier trays for use in theirlogic circuits. The resistors are for currentlimiting and the diodes are to preventvoltage feedback from the externalamplifier trays.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-223.1.9 (A19) Visual/Aural MeteringBoard (1265-1309; Appendix D)The visual/aural metering board providesdetected outputs of the visual, aural, andreflected output samples that are usedfor monitoring on the front panel meter.The board also provides adjustments forthe calibration of the readings on themeter. These readings are attained fromsamples of the forward power andreflected power outputs of the tray.A forward power sample, visual + aural,is applied to SMA jack J1 on the board.The input signal is split, with one pathconnected to forward power sample SMAjack J2 for monitoring purposes. Theother path is connected through C1 toCR2, R4, R5, R6, C4, and CR1, whichmake up a detector circuit. The detectedvisual + aural signal is amplified by U6Band its output is split. One amplifiedoutput of U6B connects to the aural levelcircuit and the other output connects tothe visual level circuit.3.1.9.1 Aural Level CircuitOne of the detected visual + aural leveloutputs of U6B connects through C6 tothe intercarrier filter circuit that consistsof R13, R14, L1, C7, and C8; C8 and L1,the intercarrier filter, can be adjusted fora maximum aural reading. The filternotches out the video + aural and onlyleaves the 4.5-MHz difference frequencybetween the visual and aural, which is agood representation of the aural level.The 4.5-MHz signal is fed to bufferamplifier U6A. The output of U6A isdetected by diode detector CR3 and U1Aand then fed through aural calibrationcontrol R20 to amplifier U2D. Theamplified output of U2D is split, with themain output connected through R21 toJ6, pin 1, which supplies the aural leveloutput to the front panel meter formonitoring. The other output of U2D isconnected to aural null adjust R51 andoffset null adjust R48, which are adjustedto set up the visual power calibration.3.1.9.2 Visual Level CircuitThe other detected visual + aural leveloutput from U6B is connected to U1Cand, if there is no scrambling, connectsdirectly to intercarrier notch L3, which isadjusted to filter out the aural and the4.5-MHz intercarrier frequencies, leavingonly a visual-with-sync output. Thevisual-with-sync output is fed to a peak-detector circuit consisting of CR5 andU2A. The signal is then fed through visualcalibration control R28, which is adjustedfor a 100% visual reading with no aural,to amplifier U2B. The amplified visualpeak of sync output is connected tocomparator U2C. The other input to U2Cis the level set by aural null adjust R51,which is adjusted for 100% visual powerafter the aural is added and the peakpower is adjusted back to the referencelevel. Inputs to U2C also come fromoffset null adjust R48, which is adjustedfor 0% visual power with the transmitterin Standby. The adjusted output isamplified by U3D and connected to theother input of U2C. The output of U2Cconnects to J6, pins 2 and 3, whichsupply the peak of sync visual leveloutput to the front panel meter formonitoring.If this board is operated with scrambling,using suppressed sync, the visual levelcircuit operates differently than describedabove because there is no peak of syncpresent on the forward sample input. Forthe board to operate properly, a timingpulse from the scrambling encoder mustconnect to the board at J4. This timingpulse is converted to sync pulses by U4Aand U4B, which control the operation ofQ2. Intercarrier notch L2 is tuned toremove any visual + aural signal thatmay remain.The sync amplitude is controlled by gateamplitude adjust R25 and then applied tothe minus input of U1C. At this point, it isinserted into the visual + aural signalthat is connected to the plus input ofU1C, producing a peak of sync in thesignal. The output of U1C is connected to
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-23intercarrier notch L3, which is adjusted tofilter out the aural and the 4.5-MHzintercarrier frequencies. The visual-with-sync output is fed to a peak-detectorcircuit, consisting of CR5 and U2A, andthen fed through visual calibration controlR28 to amplifier U2B. The amplifiedvisual peak of sync output is connectedto J6, pins 2 and 3, that supply the peakof sync visual level output to the frontpanel meter for monitoring. R32 movesthe pulse to where the sync should beand R25 sets the visual meteringcalibration with no sync present.3.1.9.3 Reflected Level CircuitA reflected-power sample is applied to J3of the visual/aural metering board and isdetected by diode detector CR7 and U3B.The detected output is fed throughreflected calibration pot R39, which canbe adjusted to control the gain of U3C.The output of U3C connects to J6, pin 7,which supplies a reflected-power leveloutput to the front panel meter.3.1.9.4 Voltages for Circuit OperationThe ±12 VDC is applied to the board atJ5. The +12 VDC is connected to J5, pin3, and is isolated and filtered by L4 andC34 before it is connected to the rest ofthe board. The +12 VDC also connects toU5, a 5-VDC regulator that provides thevoltage needed to operate U4. The -12VDC is applied to J5, pin 1, and isisolated and filtered by L5 and C35before it is connected to the rest of theboard.3.1.10 (A4-A14) Channel OscillatorAssembly, Dual Oven (1145-1202;Appendix D)The channel oscillator assembly containsthe channel oscillator board (1145-1201)that generates a stable frequency-reference signal of approximately 100MHz. The channel oscillator assembly isan enclosure that provides temperaturestability for the crystal oscillator. An SMAoutput at jack J1 and an RF sample atBNC connector jack J2 are also part ofthe assembly.Adjustments can be made through accessholes in the top cover of the assembly.These adjustments are set at the factoryand should not be tampered with unlessit is absolutely necessary and the proper,calibrated equipment is available. R1 isthe temperature adjustment; C11 is thecourse-frequency adjustment; C9 is thefine-frequency adjustment; and C6, C18,L2, and L4 are adjusted for the maximumoutput of the frequency as measured atjack J1.The +12 VDC for the assembly entersthrough FL1 and the circuit-groundconnection is made at E1.3.1.11 (A4-A13) EEPROM FSKIdentifier Board (1265-1308;Appendix D)The FSK identifier board, with EEPROM,generates a morse code identification callsign by frequency-shift keying the VCXOoscillator in the upconverter or bysending a bias voltage to the IFattenuator board to amplitude modulatethe aural carrier. This gives the station ameans of automatically repeating itsidentification call sign, at a given timeinterval, to meet FCC requirements.The starting circuit is made up of U1Band U1D, which are connected as aflip-flop, with gate U1A used as the setflip-flop. U1A automatically starts theflip-flop each time U3 completes itstiming cycle. At the start of a cycle, U1Benables clock U2. U2 applies the clockpulses that set the speed, which isadjusted by R2, for when theidentification code is sent to 12-bit binarycounter U4. R2, fully clockwise (CW), isthe fastest pulse train and R2, fullycounter-clockwise (CCW), is the slowestpulse train. U4 provides binary outputsthat address EEPROM U5.The scans in U4 will continue until fieldeffect transistor (FET) Q1 is gated on.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-24The gate of Q1 is connected to pin 13 onU4, which is the maximum count used inthe EEPROM, and will provide a resetpulse each time the binary counter goeshigh on pin 13. The reset pulse, when thedrain of Q1 goes low, is applied to theflip-flop and the timer U3, whichdetermines the length of time betweenthe sending of the identification code.R14 is adjusted to set this time interval.R14, fully CW, is the longest intervalbetween identification calls,approximately eight minutes. R14, fullyCCW, is the shortest interval between thesending of the code (approximately 10seconds).U6B is an amplifier connected to theoutput of U5, which turns the LED DS1on and off at the rate set by R2. Thisgives the operator a visual indication thatthe FSK identifier board is operating andat the rate at which it is operating.The data output of U5, which is serial, isconnected to U6A, whose output shiftslow and high, and is applied to the VCXOboard, which shifts the frequencyaccording to the programming of U5. Thedeviation of the shift is adjusted by R4and is typically set at 1 kHz. Once R4 isset, R9 is re-adjusted to -1.5 VDC at J3-2.The +12 VDC from an external powersupply enters the board at J1, pin 3. Thevoltage is fed through RF choke L1 and isfiltered by C1 before being applied to therest of the tray. The +12 VDC is alsoapplied to U7, which is a voltageregulator that regulates its output at +5VDC. The +5 VDC is fed to the ICs on theboard. The -12 VDC from an externalpower supply enters the board at J1, pin5. The voltage is fed through RF choke L2and filtered by C2 before being applied tothe rest of the tray.3.1.12 (A4-A12) IF Attenuator Board(1150-1201; Appendix D)The IF attenuator board is operated withthe FSK identifier board to produce anamplitude-modulated aural IF signal forbroadcasting the required FCC stationidentification call sign at the proper timeintervals.The board contains a pin-diodeattenuation circuit that consists of CR1and the two resistors R2 and R3. Thebias output of the FSK identifier board isapplied to J3 of the IF attenuator board.As the bias applied to J3 increases anddecreases, the amplitude of the aural IFsignal, which enters the board at J1 andexits the board at J2, will increase anddecrease. This produces an amplitude-modulated IF signal at J2, the aural IFoutput jack of the board.3.2 (A6 and A7) 600-Watt High-BandVHF Amplifier Trays (1219-1100;Appendix C)The 600-watt high-band VHF amplifiertray (1219-1100) can be adjusted at thefactory for use as either a visual, a visual+ aural, or an aural RF amplifier tray. Asa visual amplifier, the tray hasapproximately 55 dB of gain at thefrequency of the VHF high-band channeland will take the typical +3 dBm inputand amplify it to an output level ofapproximately +58 dBm, 100%=600watts peak of sync. As an aural amplifier,the tray is calibrated for 400 watts equals100% output. As a visual + auralamplifier, the tray is calibrated for 300watts peak of sync visual plus –10 dB or–13 dB aural power (30 watts or 15watts).The tray is made up of the boards andassemblies listed in Table 3-1.
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-25Table 3-1. 600-Watt Amplifier Tray Boards and AssembliesMAJOR ASSEMBLYDESIGNATOR BOARD/ASSEMBLY NAME DRAWING NUMBERA1-A1 Phase shifter board(mounted in [A1] an RFenclosure assembly) 1198-1602A2-A1 Filter/amplifier board(mounted in [A2] an RFenclosure assembly) 1218-1104A2-A2 High band driver board(mounted in [A2] an RFenclosure assembly) 1219-1103A3-A1 Overdrive protection board(mounted in [A3] an RFenclosure assembly) 1198-1601A3-A2 High band VHF amplifierboard (mounted in [A3] anRF enclosure assembly) 1219-1114A3-A3 4-way splitter board(mounted in [A3] an RFenclosure assembly) 1219-1101A4-A1, A4-A2, A4-A3, andA4-A4Four high band VHFamplifier boards (mountedin [A4] an RF enclosureassembly)1218-1201A5-A1 4-way combiner board 1219-1102A13 AGC control board 1142-1601A8 Current metering board 1198-1609A10 +48 VDC switching powersupply assemblyThe on-channel visual RF or aural RFinput signal (+3 dBm) enters the rear ofthe tray at BNC jack J1 and is fedthrough J1 of the (A1) enclosureassembly to J1 of (A1-A1) the phaseshifter board (1198-1602). The boardprovides a phase shifter adjustment ofthe RF signal that is needed to providemaximum output during the combining ofmultiple 600-watt amplifier trays in anamplifier array. Front panel-mountedphase shift potentiometer R2 connects toJ3 on the board and controls the phase ofthe RF signal.If the input signal level to the phaseshifter board falls below a preset level, ahigh, which is an input fault, connectsfrom J5 of the board to J14 on the AGCcontrol board. When an input faultoccurs, the AGC control board generatesa fault output at J1, which is connectedto J4 on the filter/amplifier board. Thefault cuts back the RF signal level usingthe pin-diode attenuator circuit on thefilter/amplifier board.The phase-controlled output at J2 of thephase shifter board (+2 dBm) is directedto J7, the input jack of (A2-A1) the filteramplifier board (1218-1104) that is madeup of two circuits. The first circuit is achannel filter that is adjusted for thedesired channel frequency andbandwidth. The filtered output (+1 dBm)is connected to the second circuit; thiscircuit contains two amplifiers. The RFconnects through a pin-diode circuit toamplifier IC U1. The amplitude of the RFsignal through the pin-diode attenuator
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-26circuit is controlled by the voltage appliedto J4, the external control jack of theboard. Jumper W1 on J5 should bebetween pins 2 and 3; these pins provideexternal control, through J4, of the gainof the board as well as the output level ofthe tray.The front panel-mounted gain pot R3connects to the AGC control board and isused to adjust the AGC pin-attenuatorbias voltage that connects to J4 on thefilter/amplifier board. The RF signal, afterthe pin-attenuator circuit, is amplified bythe second amplifier stage Q1 to about+14 dBm; this signal is connected to theoutput of the board at J2. The RF outputof the filter/amplifier board connects toJ1 on (A2-A2) the high-band VHF driverboard (1219-1103). The board containsan RF power FET that has a gain of 20dB.The RF output of the board at J2 (+34dBm) connects to J2 of (A3) an RFenclosure that contains the overdriveprotection board, the high-band amplifierboard, and the 4-way splitter board. Thesignal is connected to J4 of (A3-A1) theoverdrive protection board (1198-1601).The RF signal is through-connecteddirectly to J5, the RF output jack of theboard. A sample of the RF on the board isapplied to a diode-detector circuit thatconsists of CR1 and U1A. The gain ofamplifier U1D is controlled by detectorgain pot R11, which is set to +.4 VDC asmeasured at TP1.The set output of U1D is connected tocomparator IC U1B. The trip point for thecomparator is adjusted by R12, typicallyto 110% output power, sync only. Whenthe signal reaches that level, theoverdrive protection board will cut backthe output power of the tray and the redOverdrive LED DS1 on the board and thered Overdrive LED DS1 mounted on thefront panel will be illuminated. Typically,the output power level will bounce downand then up and continue bouncing untilthe output level is lowered to the normaloperating level (100%). The redOverdrive LED DS1, the green ModuleLED DS3, and the Enable LED DS2 mayblink on and off during the bouncing ofthe output level; this is a normaloccurrence. The greater the output levelis above 110%, the larger the bounce willbe.The RF output of the overdrive protectionboard at J5 connects to J1 on (A3-A2)the high-band amplifier board (1219-1114) that amplifies the RF before it isconnected to J1 on (A3-A3) the 4-waysplitter board (1219-1101). The splitterboard takes the +34 dBm input andprovides four +30 dBm outputs at J1, J2,J3, and J4 of the (A3) amplifierenclosure.The four RF outputs connect to (A4) thefinal amplifier enclosure. This enclosurecontains four (A4-A1, A4-A2, A4-A3, andA4-A4) high-band amplifier boards(1218-1201). The RF signals connect toJ1 on each of the high-band amplifierboards. Each amplifier board providesapproximately 20 dB of gain.The RF signal inputs to the amplifierboards (+30 dBm) are amplified to+49.5 dBm outputs at J2. These outputsare connected to J1, J2, J3, and J4 on(A5-A1) a 4-way combiner board (1219-1102). The 4-way combiner takes thefour +49.5 dB inputs and combines themto form the 300-watt RF output at J5 ofthe combiner that connects to J2, the RFoutput jack of the tray.The 4-way combiner board provides aforward power sample at J9 and areflected output power sample at J11.The forward output power sampleconnects to J4 on (A13) the AGC controlboard (1142-1601). The reflected outputpower sample connects to J5 on (A13)the AGC control board (1142-1601). TheAGC control board contains two peak-detector networks that provide detectedoutputs that are used for front panel andremote meter indications of forward andreflected output power levels, the AGCdetector voltage level, and the VSWR
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-27cutback protection if the reflected powerlevel increases above the preset level.Two voltages, +48 VDC from the internalswitching power supply and +12 VDCfrom the exciter control panel, areneeded for the operation of the tray. The+12 VDC connects to J3-7 and J3-8 onthe rear of the tray; these are wired toJ8, pins 4 and 1, on (A13) the AGCcontrol board. The +12 VDC is connectedto U8, a +5 VDC regulator IC thatsupplies the +5 VDC needed for theoperation of the front panel-mountedLEDs.The (A10) +48 VDC switching powersupply provides the +48 VDC to (A8) thecurrent metering board (1198-1609). Thecurrent metering board distributes thevoltages through fuses to the amplifierdevices on the filter/amplifier, the high-band driver board, the high-bandamplifier board, and the four final high-band amplifier boards. The fuses F1, F2,F3, and F4 are 10-amp fuses; F5 is a 5-amp fuse; and F6 and F7 are 1-ampfuses. There are two spare fuses, one 1amp and one 10 amp, on the top, right-hand side of the tray. Fuse F1 protects(A4-A1) the high-band amplifier board;fuse F2 protects (A4-A2) the high-bandamplifier board; fuse F3 protects (A4-A3)the high-band amplifier board; fuse F4protects (A4-A4) the high-band amplifierboard; fuse F5 protects (A3-A2) the high-band amplifier board; and fuse F6protects (A2-A1) the filter/amplifierboard. Fuse F7 supplies +48 VDC to J8,pin 2, on the AGC control board. The +48VDC is connected to regulator IC U7 thattakes the +48 VDC and provides a +12VDC output. The +12 VDC is used for theoperation of the AGC control board. The+12 VDC is also connected through thecurrent metering board, jumpered fromTB1-5 to TB1-6, to the phase shifterboard, the filter/amplifier board, and theoverdrive protection board.The current metering board also suppliessample outputs of the operating currentsof the amplifier devices in the tray to thefront panel current meter. The meter inthe (I1) position reads the current for the(A4-A1) high-band amplifier board; themeter in the (I2) position reads thecurrent for (A4-A2) the high-bandamplifier board; the meter in the (I3)position reads the current for the (A4-A3)high-band amplifier board; and the meterin the (I4) position reads the current forthe (A4-A4) high-band amplifier board.To read the desired current, place switchS2 in the proper position, checking thatS1 is in the Current position. Thesecurrent readings can be used whensetting up the idling currents, no RF driveapplied, for the devices. (I1, I2, I3, and I4)are each set for 2 amps when the tray isa visual amplifier, or a visual + auralamplifier, and they are set for 1 ampwhen the tray is an aural amplifier.230 VAC is applied through jack J4 toterminal block TB1 in the tray. WhenCB1, the 15-amp, front panel-mountedcircuit breaker, is switched on, the 230VAC is distributed from TB1 to (A11 andA12) two cooling fans, which will begin tooperate, and to (A10) the switchingpower supply. There are two surgesuppressors, VR1 and VR2, mounted onTB1 that provide protection fromtransients or surges on the input AC line.There are two other surge suppressors,VR3 and VR4, mounted at the input tothe switching power supply from each ACline to ground, that provide protectionfrom transients or surges on the AC line.The switching power supply onlyoperates when the power supply enablecontrol line, jack J3, pins 9 and 10, onthe rear of the tray, is shorted. Theenable is generated by the control panelwhen the amplifier array is switched toOperate. The enable is applied to (A13)the AGC control board (1142-1601)which, if there is no thermal fault,connects the enable from J10, pins 6 and7, to J1-6 and J1-8 on the switchingpower supply assembly. The greenEnable LED DS2 on the front panel willlight, indicating that an enable is present.If the amplifier array is in Standby, or if a
500-Watt UHF Transmitter Chapter 3, Circuit Descriptions425A, Rev. 0 3-28thermal fault occurs, the AGC controlboard will not enable the switching powersupply. As a result, the +48 VDC will beremoved from the amplifier modules andthe front panel Enable and Module StatusLEDs will not be lit.The front panel meter (A9) uses the frontpanel Selector switch S1 to monitor theAGC Voltage, % Output Reflected Power,% Forward Power, and the SwitchingPower Supply Voltage (+48 VDC). Themeter in the AGC position will readanywhere from .5 volts to 3 volts. Themeter is calibrated in the Power Supplyposition using R86 on the AGC controlboard. The % Output Power is calibratedusing R44 and the % Reflected Power iscalibrated using R53 on the AGC controlboard. With S1 in the Current position,S2 can be switched to read the idlingcurrents, no RF drive applied, of thehigh-band amplifier boards. Typicalreadings are an idling current of 2 ampsvisual, or visual + aural, or 1 amp auralin the amplifier assembly I1, I2, I3, and I4positions.The reflected power sample from the 4-way combiner board is fed back to theAGC control board at J5. On the board,the reflected sample is connectedthrough the detector circuit to VSWRcutback circuit U13C. If the reflectedpower increases above 20%, the outputpower of the tray, as set by R60 (theVSWR cutback on the AGC controlboard), will be cut back to maintain a20% reflected output level.The red VSWR Cutback LED DS4 on thefront panel will remain lit until thereflected level drops below 20%.There are three thermal switches in thetray for overtemperature protection. Twoof the thermal switches (A4-A5 and A4-A6) are mounted on the rear of (A4) theheatsink for the high-band amplifierboards and the third thermal switch (A5-A2) is mounted on the heatsink for (A5-A1) the 4-way combiner board. Thethermal switches close when the heatsinkon which they are mounted reach atemperature of 175° F. The closedthermal switch causes the AGC controlboard to remove the enable to theswitching power supply. This eliminatesthe +48 VDC and lights the redOvertemperature LED DS5 on the frontpanel. The AGC control board willextinguish the Module Status LED DS3.3.3 (A9) Bandpass Filter Assembly(1067297; Appendix C)The RF input connects to the (A9)constant impedance bandpass filterassembly (1067318) at jack J1 of (A1) asplitter/combiner board (1092-1092).The splitter/combiner board divides thecombined RF signal into two signalsbefore feeding it to jack J1 of (A2 andA3) two 5-section bandpass filters withtraps. These filters screen the 6 MHz-wide signal and attenuate the –4.5-MHzand +9-MHz out-of-band products. Thesesignals connect to jacks J2 and J3 on(A4) the other splitter/combiner board(1092-1092), that recombines the twosignals before sending them on to jack J1of (A5) the directional coupler module(1092-1308). The directional couplermodule provides forward and reflectedsamples to the exciter tray for meteringpurposes.

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