Xilinx 8.2i ISE Development System Reference Guide User Manual To The 655d0d4f 48e4 4338 93fb 692ddea72099
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- Software Manuals
- Development System Reference Guide
- About This Guide
- Table of Contents
- 1 Introduction
- 2 Design Flow
- 3 Tcl
- Tcl Overview
- Xilinx Tcl Shell
- Tcl Fundamentals
- Xilinx Tcl Commands
- Tcl Commands for General Usage
- partition (support design preservation)
- process (run and manage project processes)
- project (create and manage projects)
- clean (remove system-generated project files)
- close (close the ISE project)
- get (get project properties)
- get_processes (get project processes)
- new (create a new ISE project)
- open (open an ISE project)
- properties (list project properties)
- set (set project properties, values, and options)
- set device (set device)
- set family (set device family)
- set package (set device package)
- set speed (set device speed)
- set top (set the top-level module/entity)
- timing_analysis (generate timing analysis reports)
- delete (delete timing analysis)
- disable_constraints (disable timing constraints)
- disable_cpt (disable components for path tracing control)
- enable_constraints (enable constraints for analysis)
- enable_cpt (enable components for path tracing control)
- get (get analysis property)
- new (new timing analysis)
- reset (reset path filters and constraints)
- run (run analysis)
- saveas (save analysis report)
- set (set analysis properties)
- set_constraint (set constraint for custom analysis)
- set_endpoints (set source and destination endpoints)
- set_filter (set filter for analysis)
- set_query (set up net or timegroup report)
- show_settings (generate settings report)
- xfile (manage project files)
- Tcl Commands for Advanced Scripting
- collection (create and manage a collection)
- append_to (add objects to a collection)
- copy (copy a collection)
- equal (compare two collections)
- foreach (iterate over elements in a collection)
- get (get collection property)
- index (extract a collection object)
- properties (list available collection properties)
- remove_from (remove objects from a collection)
- set (set the property for all collections)
- sizeof (show the number of objects in a collection)
- object (get object information)
- search (search and return matching objects)
- collection (create and manage a collection)
- Project Properties and Options
- Example Tcl Scripts
- 4 PARTGen
- 5 Logical Design Rule Check
- 6 NGDBuild
- NGDBuild Overview
- NGDBuild Syntax
- NGDBuild Input Files
- NGDBuild Output Files
- NGDBuild Intermediate Files
- NGDBuild Options
- –a (Add PADs to Top-Level Port Signals)
- –aul (Allow Unmatched LOCs)
- –bm (Specify BMM Files)
- –dd (Destination Directory)
- –f (Execute Commands File)
- –i (Ignore UCF File)
- –insert_keep_hierarchy
- –intstyle (Integration Style)
- –l (Libraries to Search)
- –modular assemble (Module Assembly)
- –modular initial (Initial Budgeting of Modular Design)
- –modular module (Active Module Implementation)
- –nt (Netlist Translation Type)
- –p (Part Number)
- –r (Ignore LOC Constraints)
- –sd (Search Specified Directory)
- –u (Allow Unexpanded Blocks)
- –uc (User Constraints File)
- –ur (Read User Rules File)
- –verbose (Report All Messages)
- 7 MAP
- MAP Overview
- MAP Syntax
- MAP Input Files
- MAP Output Files
- MAP Options
- –bp (Map Slice Logic)
- –c (Pack CLBs)
- –cm (Cover Mode)
- –detail (Write Out Detailed MAP Report)
- –equivalent_register_removal (Remove Redundant Registers)
- –f (Execute Commands File)
- –gf (Guide NCD File)
- –global_opt (Global Optimization)
- –gm (Guide Mode)
- –gm incremental (Guide Mode incremental)
- –ignore_keep_hierarchy (Ignore KEEP_HIERARCHY Properties)
- –intstyle (Integration Style)
- –ir (Do Not Use RLOCs to Generate RPMs)
- –ise (ISE Project File)
- –k (Map to Input Functions)
- –l (No logic replication)
- –o (Output File Name)
- –ol (Overall Effort Level)
- –p (Part Number)
- –pr (Pack Registers in I/O)
- –r (No Register Ordering)
- –register_duplication (Duplicate Registers)
- –retiming (Register Retiming During Global Optimization)
- –t (Start Placer Cost Table)
- –timing (Timing-Driven Packing and Placement)
- –tx (Transform Buses)
- –u (Do Not Remove Unused Logic)
- –xe (Extra Effort Level)
- MAP Process
- Register Ordering
- Guided Mapping
- Simulating Map Results
- MAP Report (MRP) File
- Halting MAP
- 8 Physical Design Rule Check
- 9 PAR
- Place and Route Overview
- PAR Process
- Guided PAR
- PAR Syntax
- PAR Input Files
- PAR Output Files
- PAR Options
- Detailed Listing of Options
- –f (Execute Commands File)
- –gf (Guide NCD File)
- –gm (Guide Mode)
- –intstyle (Integration Style)
- –k (Re-Entrant Routing)
- –m (Multi-Tasking Mode)
- –n (Number of PAR Iterations)
- –nopad (No Pad)
- –ol (Overall Effort Level)
- –p (No Placement)
- –pl (Placer Effort Level)
- –power (Power Aware PAR)
- –r (No Routing)
- –rl (Router Effort Level)
- –s (Number of Results to Save)
- –t (Starting Placer Cost Table)
- –ub (Use Bonded I/Os)
- –w (Overwrite Existing Files)
- –x (Performance Evaluation Mode)
- –xe (Extra Effort Level)
- Detailed Listing of Options
- PAR Reports
- Multi Pass Place and Route (MPPR)
- Xplorer
- ReportGen
- Turns Engine (PAR Multi-Tasking Option)
- Halting PAR
- 10 XPower
- 11 PIN2UCF
- 12 TRACE
- TRACE Overview
- TRACE Syntax
- TRACE Input Files
- TRACE Output Files
- TRACE Options
- –a (Advanced Analysis)
- –e (Generate an Error Report)
- –f (Execute Commands File)
- –fastpaths (Report Fastest Paths)
- –intstyle (Integration Style)
- –ise (ISE Project File)
- –l (Limit Timing Report)
- –nodatasheet (No Data Sheet)
- –o (Output Timing Report File Name)
- –run (Run Timing Analyzer Macro)
- –s (Change Speed)
- –skew (Analyze Clock Skew for All Clocks)
- –stamp (Generates STAMP timing model files)
- –u (Report Uncovered Paths)
- –v (Generate a Verbose Report)
- –xml (XML Output File Name)
- TRACE Command Line Examples
- TRACE Reports
- OFFSET Constraints
- PERIOD Constraints
- Halting TRACE
- 13 Speedprint
- 14 BitGen
- BitGen Overview
- BitGen Syntax
- BitGen Input Files
- BitGen Output Files
- BitGen Options
- –b (Create Rawbits File)
- –bd (Update Block Rams)
- –d (Do Not Run DRC)
- –f (Execute Commands File)
- –g (Set Configuration)
- –g (Set Configuration—Virtex/-E/-II/-II Pro/-4 and Spartan-II/-IIE/-3/-3E)
- ActivateGCLK
- ActiveReconfig
- Binary
- CclkPin
- Compress
- ConfigRate
- CRC
- DCIUpdateMode
- DCMShutdown
- DebugBitstream
- DisableBandgap
- DONE_cycle
- DonePin
- DonePipe
- DriveDone
- Encrypt
- Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3
- GSR_cycle
- GWE_cycle
- GTS_cycle
- HswapenPin
- Key0, Key1, Key2, Key3, Key4, Key5
- KeyFile
- Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5
- LCK_cycle
- M0Pin
- M1Pin
- M2Pin
- Match_cycle
- PartialGCLK
- PartialMask0, PartialMask1, PartialMask2
- PartialLeft
- PartialRight
- Persist
- PowerdownPin
- ProgPin
- ReadBack
- Security
- SEURepair
- StartCBC
- StartKey
- StartupClk
- TckPin
- TdiPin
- TdoPin
- TmsPin
- UnusedPin
- UserID
- –intstyle (Integration Style)
- –j (No BIT File)
- –l (Create a Logic Allocation File)
- –m (Generate a Mask File)
- –r (Create a Partial Bit File)
- –w (Overwrite Existing Output File)
- 15 BSDLAnno
- 16 PROMGen
- PROMGen Overview
- PROMGen Syntax
- PROMGen Input Files
- PROMGen Output Files
- PROMGen Options
- –b (Disable Bit Swapping—HEX Format Only)
- –c (Checksum)
- –d (Load Downward)
- –f (Execute Commands File)
- –i (Select Initial Version)
- –l (Disable Length Count)
- –n (Add BIT FIles)
- –o (Output File Name)
- –p (PROM Format)
- –r (Load PROM File)
- –s (PROM Size)
- –t (Template File)
- –u (Load Upward)
- –ver (Version)
- –w (Overwrite Existing Output File)
- –x (Specify Xilinx PROM)
- –z (Enable Compression)
- Bit Swapping in PROM Files
- PROMGen Examples
- 17 IBISWriter
- 18 CPLDfit
- CPLDfit Overview
- CPLDfit Syntax
- CPLDfit Input Files
- CPLDfit Output Files
- CPLDfit Options
- –blkfanin (Specify Maximum Fanin for Function Blocks)
- –exhaust (Enable Exhaustive Fitting)
- –ignoredatagate (Ignore DATA_GATE Attributes)
- –ignoretspec (Ignore Timing Specifications)
- –init (Set Power Up Value)
- –inputs (Number of Inputs to Use During Optimization)
- –iostd (Specify I/O Standard)
- –keepio (Prevent Optimization of Unused Inputs)
- –loc (Keep Specified Location Constraints)
- –localfbk (Use Local Feedback)
- –log (Specify Log File)
- –nofbnand (Disable Use of Foldback NANDS)
- –nogclkopt (Disable Global Clock Optimization)
- –nogsropt (Disable Global Set/Reset Optimization)
- –nogtsopt (Disable Global Output-Enable Optimization)
- –noisp (Turn Off Reserving ISP Pin)
- –nom1opt (Disable Multi-level Logic Optimization)
- –nouim (Disable FASTConnect/UIM Optimization)
- –ofmt (Specify Output Format)
- –optimize (Optimize Logic for Density or Speed)
- –p (Specify Xilinx Part)
- –pinfbk (Use Pin Feedback)
- –power (Set Power Mode)
- –pterms (Number of Pterms to Use During Optimization)
- –slew (Set Slew Rate)
- –terminate (Set to Termination Mode)
- –unused (Set Termination Mode of Unused I/Os)
- –wysiwyg (Do Not Perform Optimization)
- 19 TSIM
- 20 TAEngine
- 21 Hprep6
- 22 NetGen
- NetGen Overview
- NetGen Simulation Flow
- NetGen Functional Simulation Flow
- NetGen Timing Simulation Flow
- Syntax for NetGen Timing Simulation
- FPGA Timing Simulation
- Output files for FPGA Timing Simulation
- CPLD Timing Simulation
- Input files for CPLD Timing Simulation
- Output files for CPLD Timing Simulation
- Options for NetGen Simulation Flow
- –aka (Write Also-Known-As Names as Comments)
- –bd (Block RAM Data File)
- –dir (Directory Name)
- –fn (Control Flattening a Netlist)
- –gp (Bring Out Global Reset Net as Port)
- –insert_pp_buffers (Insert Path Pulse Buffers)
- –intstyle (Integration Style)
- –mhf (Multiple Hierarchical Files)
- –module (Simulation of Active Module)
- –ofmt (Output Format)
- –pcf (PCF File)
- –s (Change Speed)
- –sim (Generate Simulation Netlist)
- –tb (Generate Testbench Template File)
- –ti (Top Instance Name)
- –tm (Top Module Name)
- –tp (Bring Out Global 3-State Net as Port)
- –w (Overwrite Existing Files)
- Verilog-Specific Options for Functional and Timing Simulation
- –insert_glbl (Insert glbl.v Module)
- –ism (Include SimPrim Modules in Verilog File)
- –ne (No Name Escaping)
- –pf (Generate PIN File)
- –sdf_anno (Include $sdf_annotate)
- –sdf_path (Full Path to SDF File)
- –shm (Write $shm Statements in Test Fixture File)
- –ul (Write uselib Directive)
- –vcd (Write $dump Statements In Test Fixture File)
- VHDL-Specific Options for Functional and Timing Simulation
- NetGen Equivalence Checking Flow
- Syntax for NetGen Equivalence Checking.
- Input files for NetGen Equivalence Checking
- Output files for NetGen Equivalence Checking
- Options for NetGen Equivalence Checking Flow
- –aka (Write Also-Known-As Names as Comments)
- –bd (Block RAM Data File)
- –dir (Directory Name)
- –ecn (Equivalence Checking)
- –fn (Control Flattening a Netlist)
- –intstyle (Integration Style)
- –mhf (Multiple Hierarchical Files)
- –module (Verification of Active Module)
- –ne (No Name Escaping)
- –ngm (Design Correlation File)
- –tm (Top Module Name)
- –w (Overwrite Existing Files)
- NetGen Static Timing Analysis Flow
- Input files for Static Timing Analysis
- Output files for Static Timing Analysis
- Syntax for NetGen Static Timing Analysis
- Options for NetGen Static Timing Analysis Flow
- –aka (Write Also-Known-As Names as Comments)
- –bd (Block RAM Data File)
- –dir (Directory Name)
- –fn (Control Flattening a Netlist)
- –intstyle (Integration Style)
- –mhf (Multiple Hierarchical Files)
- –module (Simulation of Active Module)
- –ne (No Name Escaping)
- –pcf (PCF File)
- –s (Change Speed)
- –sta (Generate Static Timing Analysis Netlist)
- –tm (Top Module Name)
- –w (Overwrite Existing Files)
- Preserving and Writing Hierarchy Files
- Dedicated Global Signals in Back-Annotation Simulation
- 23 XFLOW
- XFLOW Overview
- XFLOW Syntax
- XFLOW Input Files
- XFLOW Output Files
- XFLOW Flow Types
- –assemble (Module Assembly)
- –config (Create a BIT File for FPGAs)
- –ecn (Create a File for Equivalence Checking)
- –fit (Fit a CPLD)
- –fsim (Create a File for Functional Simulation)
- –implement (Implement an FPGA)
- –initial (Initial Budgeting of Modular Design)
- –module (Active Module Implementation)
- –mppr (Multi-Pass Place and Route for FPGAs)
- –sta (Create a File for Static Timing Analysis)
- –synth
- –tsim (Create a File for Timing Simulation)
- Flow Files
- XFLOW Option Files
- XFLOW Options
- Running XFLOW
- 24 Data2MEM
- A Xilinx Development System Files
- B EDIF2NGD, and NGDBuild
- Glossary