CMT2380F32 Rev. 0.9 | 1/65 www.cmostek.com MCU Features 32 MHz Cortex-M0 32-bit CPU platform 32 kB Flash with erasing protection 4 kB RAM with parity to enhance system stability
CMT2380F32 | Micros
ISM modules / Communication Modules | Micros
CMT2380F32 CMT2380F32 Ultra Low Power Sub-1GHz Wireless MCU MCU Features SoC 32 MHz Cortex-M0+ 32-bit CPU platform 32 kB Flash with erasing protection 4 kB RAM with parity to enhance system stability 16 general purpose I/O interfaces available Flexible power management system - 0.5 uA @ 3 V(deep sleep mode): the power consumption when all clocks are off, power-on reset is active, I/O state is maintained, I/O interrupt is active and all registers, RAM, and CPU stay in data storage status - 0.8 uA @ 3 V (deep sleep mode): the power consumption when RTCs work - 150 uA/MHz @3 V @16 MHz: the power consumption when CPU and peripheral modules run with program Flash operating internally - 2 us: the chip's wakeup time from ultra-low power mode, the fast response enables mode switching more flexible and efficient RTC and crystal - External high speed crystal: 4 32 MHz - External low speed crystal: 32.768 kHz - Internal high speed clock: 4/8/16/22 and 24 MHz - Internal low speed clock: 32.8/38.4 kHz Timer and counter - 3 general purpose 16-bit timers/counters - A 16-bit timer/counter available in low power mode - 3 high performance 16-bit timers/counters capable for capture/compare and PWM output - One 20-bit programmable counter/watchdog circuit with built-in dedicated ultra-low power RC-OSC to perform WDT counting Communication interface - UART 0 and UART 1 standard communication interface - One ultra-low power UART(LPUART) supporting for low speed clock - Standard I2C and SPI communication interface One 12-bit 1 Msps SAR ADC 2 voltage comparators Low voltage detector (LVD), configurable 16-level comparison level, support for port voltage and supply voltage monitoring RF Features Frequency range: 127 1020 MHz Modem: FSK, GFSK, MSK, GMSK and OOK Data rate0.5 300 kbps Sensitivity: -121 dBm @ 434 MHz, FSK Receiving current: 8.5 mA @ 434 MHz, FSK Transmitting current: 72 mA @ 20 dBm, 434 MHz Configurable up to 64-byte FIFO System Features Supply voltage1.8 3.6 V Operating temperature: -40 85 QFN40 5x5 packaging Applications Smart grid and automatic meter reading Home security and building automation Wireless sensor networks and industrial monitoring ISM band data communication Descriptions Employed a 32-bit Cortex-M0+ CPU core and an ultra-low power RF transceiver, the CMT2380F32 is a FSK, GFSK, MSK, GMSK and OOK wireless MCU with high performance and ultra-low power applying to 127 to 1020 MHz band wireless applications. Operating with 1.8 to 3.6 V supply voltage, the CMT2380F32 consumes only 72 mA current while delivering up to 20 dBm power. As for the receiver, the Rev. 0.9 | 1/65 www.cmostek.com device consumes an ultra-low current of 8.5 mA with the sensitivity reaching -121 dBm. The device employs a wide range of peripherals like support of standard UART, I2C and SPI interfaces, up to 16 general-purpose I/Os, support of internal high-speed, low-speed, low-power RC oscillators and 32.768 kHz external crystal oscillators, flexible data handling and packet handler, up to 64-byte Tx/Rx FIFO, feature-enriched RF GPIO, multiple low-power modes and fast-start mechanisms, high-precision RSSI, manual fast frequency hopping, multi-channel input 12-bit high-speed ADC, etc. Leading the industry in the aspect of the smallest package size, the CMT2380F32 is ideal for size constraints due to a small form-factor, power-efficient IoT applications. CMT2380F32 Rev. 0.9 | 2/65 www.cmostek.com CMT2380F32 Table 1. The CMT2380F32 Resource List Memory Analog Peripherals Digital Peripherals Others CCP ROM RAM ADC VCMP LVD RTC WDT Timer UART LPUART SPI I2C PCA CRC GPIO PWM 12-bit 32 k 4 k 2 x9-ch 16-bit 16-bit 2 x6 x6-ch 1 1 1 16+1 Figure 1. Typical Application Schematic for the CMT2380F32 (20dBm Output Power with Antenna Switch) Table 2. Typical Application BOM (20 dBm Output Power with Antenna Switch) Label Description C1 ± 5%, 0402 NP0, 50 V C2 ± 5%, 0402 NP0, 50 V C3 ± 5%, 0402 NP0, 50 V C4 ± 5%, 0402 NP0, 50 V C5 ± 5%, 0402 NP0, 50 V C6 ± 5%, 0402 NP0, 50 V C7 ± 5%, 0402 NP0, 50 V Component Value 434 MHz 868/915 MHz 15 15 10 3.9 8.2 2.7 8.2 2.7 220 220 4.7 2 4.7 2 Unit pF pF pF pF pF pF pF Supplier - C8 ± 5%, 0402 NP0, 50 V 220 220 pF - C9 ± 5%, 0402 NP0, 50 V 220 220 pF - C12 ± 5%, 0402 NP0, 50 V C13 ± 20%, 0402 X7R, 25 V 470 pF - 2.2 nF - C14 ± 20%, 0603 X7R, 25 V 4.7 uF - Rev. 0.9 | 3/65 www.cmostek.com CMT2380F32 Label Description C15 ± 5%, 0402 NP0, 50 V C16 ± 5%, 0402 NP0, 50 V C17 ± 5%, 0402 NP0, 50 V C18 ± 5%, 0402 NP0, 50 V C19 ± 20%, 0402 X7R, 25 V C20 ± 20%, 0603 X7R, 25 V C21 ± 20%, 0402 X7R, 25 V C22 ± 5%, 0402 NP0, 50 V L1 ±10%, 0603multilayer chip inductor L2 ±10%, 0603 multilayer chip inductor L3 ±10%, 0603 multilayer chip inductor L4 ±10%, 0603 multilayer chip inductor L5 ±10%, 0603 multilayer chip inductor L6 ±10%, 0603 multilayer chip inductor L7 ±10%, 0603 multilayer chip inductor L8 ±10%, 0603 multilayer chip inductor Y1 ±10 ppm, SMD32*25 mm CMT2380F32, ultra-low power sub-1GHz U1 wireless MCU U2 AS179, PHEMT GaAs IC SPDT Switch R1 ± 5%, 0402 R2 ± 5%, 0402 Component Value 434 MHz 868/915 MHz 27 Unit pF 27 pF 10 pF 10 pF 100 nF 4.7 uF 100 nF 470 pF 180 100 nH 27 6.8 nH 18 12 nH 33 22 nH 15 10 nH 27 12 nH 27 12 nH 68 18 nH 26 MHz Supplier Sunlord SDCL Sunlord SDCL Sunlord SDCL Sunlord SDCL Sunlord SDCL Sunlord SDCL Sunlord SDCL Sunlord SDCL EPSON - - CMOSTEK - - SKYWORKS 2.2 k - 2.2 k - Rev. 0.9 | 4/65 www.cmostek.com Table of Contents CMT2380F32 1 Electrical Specifications ......................................................................................................................7 1.1 Recommended Operating Conditions................................................................................................................. 7 1.2 Absolute Maximum Ratings................................................................................................................................ 7 1.3 RF Power Consumption ..................................................................................................................................... 8 1.4 Receiver ............................................................................................................................................................. 9 1.5 Transmitter ....................................................................................................................................................... 11 1.6 RF Operating Mode Switching Time................................................................................................................. 12 1.7 RF Frequency Synthesizer ............................................................................................................................... 12 1.8 Requirement on Crystals for RF Section .......................................................................................................... 13 1.9 Controller Output Features ............................................................................................................................... 13 1.10 Controller Input FeaturesP0, P1, P2 and P3 Reset) ..................................................................................... 14 1.11 Port External Input Sampling Requirements (Timer Gate/Timer Clock) ........................................................... 14 1.12 Port Leakage Features (P0, P1, P2 and P3) .................................................................................................... 14 1.13 Controller Power Consumption Features.......................................................................................................... 15 1.14 POR/BOR Features.......................................................................................................................................... 18 1.15 Controller External XTH Oscillator.................................................................................................................... 18 1.16 Controller External 32.768 kHz Oscillator......................................................................................................... 19 1.17 Controller Internal RCH Oscillator .................................................................................................................... 19 1.18 Controller Internal RCL Oscillator ..................................................................................................................... 20 1.19 Controller Flash Features ................................................................................................................................. 20 1.20 Controller Low Power Mode Recover Time ...................................................................................................... 20 1.21 Controller ADC Features .................................................................................................................................. 21 1.22 Analog Voltage Comparator ............................................................................................................................. 23 1.23 Low Battery Detection Features ....................................................................................................................... 25 1.24 Receive Current and Supply Voltage Correlation ............................................................................................. 27 1.25 Correlation Among Receive Current, Supply Voltage and Temperature .......................................................... 27 1.26 Receive Sensitivity and Supply Voltage Correlation......................................................................................... 28 1.27 Receive Sensitivity and Temperature Correlation ............................................................................................ 29 1.28 Transmit Power and Supply Voltage Correlation.............................................................................................. 29 1.29 Phase Noise ..................................................................................................................................................... 30 2 Pin Description ...................................................................................................................................31 3 Chip Structure.....................................................................................................................................37 4 Sub-GHz Transceiver .........................................................................................................................39 4.1 Transmitter ....................................................................................................................................................... 39 4.2 Receiver ........................................................................................................................................................... 39 4.3 Transceiver Power-on Reset (POR)................................................................................................................. 39 4.4 Transceiver Crystal Oscillator........................................................................................................................... 40 4.5 Transceiver Built-in Low Frequency Oscillator (LPOSC) .................................................................................. 41 4.6 Transceiver Built-in Low Battery Detection....................................................................................................... 41 4.7 Receiver Signal Strength Indication (RSSI) ...................................................................................................... 41 4.8 Phase Jump Detector (PJD)............................................................................................................................. 42 4.9 Receiver Clock Data Recovery (CDR).............................................................................................................. 42 Rev. 0.9 | 5/65 www.cmostek.com CMT2380F32 4.10 Fast Manual Frequency Hopping ..................................................................................................................... 43 4.11 Transceiver Control Interface and Operating Mode.......................................................................................... 43 4.11.1 Transceiver SPI Interface Timing ............................................................................................................. 43 4.11.2 Transceiver FIFO Interface Timing........................................................................................................... 44 4.11.3 Transceiver Operating Status, Timing, and Power Consumption ............................................................. 45 4.11.4 Transceiver GPIO Function and Interrupt Mapping.................................................................................. 48 5 Controller function Introduction .......................................................................................................50 5.1 Cortex M0+ Core Function Description ............................................................................................................ 50 5.2 Memory ............................................................................................................................................................ 53 5.2.1 On-chip Program Memory Flash .............................................................................................................. 53 5.2.2 On-chip Data Memory Flash .................................................................................................................... 53 5.3 System Clock ................................................................................................................................................... 55 5.4 Operating Mode................................................................................................................................................ 55 5.5 RTC Hardware Real Time Clock RTC .............................................................................................................. 55 5.6 General Purpose IO Port .................................................................................................................................. 55 5.7 Interrupt Controller............................................................................................................................................ 55 5.8 Reset Controller ............................................................................................................................................... 57 5.9 Timer/Counter .................................................................................................................................................. 57 5.10 Watchdog WDT ................................................................................................................................................ 58 5.11 Universal Purpose Asynchronous Receiver UART0, UART1 and LPUART ..................................................... 58 5.12 Synchronous Serial Interface SPI..................................................................................................................... 59 5.13 I2C Bus............................................................................................................................................................. 59 5.14 Buzzer .............................................................................................................................................................. 59 5.15 Clock Calibration Circuit ................................................................................................................................... 59 5.16 Unique ID number ............................................................................................................................................ 59 5.17 CRC16 Hardware Cyclic Redundancy Check Code......................................................................................... 59 5.18 12-bit SARADC ................................................................................................................................................ 59 5.19 Voltage Comparator (VC) ................................................................................................................................. 59 5.20 LVD Low Voltage Detector (LVD)..................................................................................................................... 59 5.21 Embedded Debug System................................................................................................................................ 60 5.22 High Security .................................................................................................................................................... 60 6 Order Information ...............................................................................................................................61 7 Packaging Information .......................................................................................................................62 8 Top Marking.........................................................................................................................................63 9 Reference Documents........................................................................................................................64 10 Revise History.....................................................................................................................................64 11 Contacts ..............................................................................................................................................65 Rev. 0.9 | 6/65 www.cmostek.com CMT2380F32 1 Electrical Specifications VDD= 3.3 VTOP= 25 °CFRF = 433.92 MHz, sensitivity is measured by receiving a PN9 sequence and matching to 50 impedance, 0.1% BER if nothing else stated. All measurement results are obtained using the evaluation board CMT2380F32-EM if nothing else stated. 1.1 Recommended Operating Conditions Parameter Operating supply voltage Operating temperature Operating speed RF supply voltage slope Controller supply voltage SCloonpteroller power-on reset effective voltage Table 3. Recommended Operating Conditions Symbol VDD TOP VRF-PSR VMC U-PSR Condition CPU frequency range Min. Typ. 1.8 -40 256k 4M 1 50 VMC U-POR Max. 3.6 85 32 M 0.1 Unit V Hz mV/us mV/us V 1.2 Absolute Maximum Ratings Table 4. Absolute Maximum Ratings[1] Parameter Supply voltage Interface voltage Junction temperature Storage temperature Soldering temperature ESD rating[2] Latch-up current Symbol VDD VIN TJ TSTG TSDR Condition Lasts for at least 30 seconds HHuummaann bbooddyy mmooddeell ((HHBBMM)) @ 85 Min. -0.3 -0.3 -40 -50 -2 -100 Typ. 3.6 3.6 125 150 255 2 100 Max. V V kV mA Notes: [1]. Exceeding the Absolute Maximum Ratings may cause permanent damage to the equipment. This value is a pressure rating and does not imply that the function of the equipment is affected under this pressure condition, but if it is exposed to absolute maximum ratings for extended periods of time, it may affect equipment reliability. [2]. The CMT2380F32 is a high performance RF integrated circuit. The operation and assembly of this chip should only be performed on a workbench with good ESD protection. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent performance degradation or loss of functionality. Rev. 0.9 | 7/65 www.cmostek.com CMT2380F32 1.3 RF Power Consumption Parameter Sleep current Standby current RFS current TFS current FSK, RX current (high performance) FSK, RX current (low power mode) FSK, TX current Table 5. RF Power Consumption Symbol ISLEEP IStandby IRFS ITFS IRx-HP IRx-LP ITx Condition Sleep mode, sleep counter off Sleep mode ,sleep counter on Crystal oscillator on 433 MHz 868 MHz 915 MHz 433 MHz 868 MHz 915 MHz 433 MHz, 10 kbps,10 kHz FDEV 868 MHz, 10 kbps, 10 kHz FDEV 915 MHz, 10 kbps,10 kHz FDEV 433 MHz, 10 kbps, 10 kHz FDEV 868 MHz, 10 kbps, 10 kHz FDEV 915 MHz, 10 kbps, 10 kHz FDEV 433 MHz, +20 dBm (Direct-tie) 433 MHz, +20 dBm (With RF switch) 433 MHz, +13 dBm (Direct-tie) 433 MHz, +10 dBm (Direct-tie) 433 MHz, -10 dBm (Direct-tie) 868 MHz, +20dBm (Direct-tie) 868 MHz, +20dBm (With RF switch) 868 MHz, +13 dBm (Direct-tie) 868 MHz, +10 dBm (Direct-tie) 868 MHz, -10 dBm (Direct-tie) 915 MHz, +20 dBm (Direct-tie) 915 MHz, +20 dBm (Direct-tie) 915 MHz, +13 dBm (Direct-tie) 915 MHz, +10 dBm (Direct-tie) 915 MHz, +10 dBm (Direct-tie) Min. Typ. Max. Unit 300 nA 800 nA 1.45 mA 5.7 mA 5.8 mA 5.8 mA 5.6 mA 5.9 mA 5.9 mA 8.5 mA 8.6 mA 8.9 mA 7.2 mA 7.3 mA 7.6 mA 72 mA 77 mA 23 mA 18 mA 8 mA 87 mA 80 mA 27 mA 19 mA 8 mA 70 mA 75 mA 28 mA 19 mA 8 mA Rev. 0.9 | 8/65 www.cmostek.com CMT2380F32 1.4 Receiver Table 6. Receiver Specifications Parameter Data Rate Error Sensitivity @ 433 MHz Sensitivity @ 868 MHz Sensitivity @ 915 MHz Saturation Image rejection ratio Receive channel bandwidth Co-channel rejection Symbol DR FDEV S433-HP S868-HP S915-HP PLVL IMR BW CCR Condition OOK FSK and GFSK FSK and GFSK DR = 2.0 kbps, FDEV = 10 kHz DR = 10 kbps, FDEV = 10 kHz DR = 10 kbps, FDEV= 10 kHz (low power mode) DR = 20 kbps, FDEV = 20 kHz DR = 20 kbps, FDEV = 20 kHz (low power mode) DR = 50 kbps, FDEV = 25 kHz DR =100 kbps, FDEV = 50 kHz DR =200 kbps, FDEV = 100 kHz DR =300 kbps, FDEV = 100 kHz DR = 2 kbps, FDEV = 10 kHz DR = 10 kbps, FDEV = 10 kHz DR = 10 kbps, FDEV = 10 kHz (low power mode) DR = 20 kbps, FDEV = 20 kHz DR = 20 kbps, FDEV = 20 kHz (low power mode) DR = 50 kbps, FDEV = 25 kHz DR =100 kbps, FDEV = 50 kHz DR =200 kbps, FDEV = 100 kHz DR =300 kbps, FDEV = 100 kHz DR = 2 kbps, FDEV = 10 kHz DR = 10 kbps, FDEV = 10 kHz DR = 10 kbps, FDEV = 10 kHz(low power mode) DR = 20 kbps, FDEV = 20 kHz DR = 20 kbps, FDEV = 20 kHz (low power mode) DR = 50 kbps, FDEV = 25 kHz DR =100 kbps, FDEV = 50 kHz DR =200 kbps, FDEV = 100 kHz DR =300 kbps, FDEV = 100 kHz FRF = 433 MHz FRF = 868 MHz FRF = 915 MHz Receive channel bandwidth DR = 10 kbps, FDEV = 10 kHz Interference with the same modulation Rev. 0.9 | 9/65 Min. 0.5 0.5 2 50 Typ. -121 -116 -115 -113 -112 -111 -108 -105 -103 -119 -113 -111 -111 -109 -108 -105 -102 -99 -117 -113 -111 -111 -109 -109 -105 -102 -99 35 33 33 -7 Max. 40 300 200 20 500 Unit kbps kbps kHz dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBc dBc dBc kHz dBc www.cmostek.com CMT2380F32 Parameter Adjacent channel rejection Alternate channel rejection Blocking Input 3rd order intercept point RSSI range Sensitivity @ 433.92 MHz (typical configuration) Symbol ACR-I ACR-II BI IIP3 RSSI Condition DR = 10 kbps, FDEV = 10 kHz, BW = 100 kHz, 200 kHz channel spacing, interference with the same modulation DR = 10 kbps, FDEV = 10 kHz, BW=100kHz, 400 kHz channel spacing, interference with the same modulation DR = 10 kbps, FDEV = 10 kHz, ±1 MHz offset, continuous wave interference DR = 10 kbps, FDEV = 10 kHz, ±2 MHz offset, continuous wave interference DR = 10 kbps, FDEV = 10 kHz, ±10 MHz offset, continuous wave interference DR = 10 kbps, FDEV = 10 kHz, 1 MHz and 20 MHz offset two tone test, maximum system gain setting DR = 1.2 kbps, FDEV = 5 kHz DR = 1.2 kbps, FDEV = 10kHz DR = 1.2 kbps, FDEV = 20 kHz DR = 2.4 kbps, FDEV = 5 kHz DR = 2.4 kbps, FDEV = 10 kHz DR = 2.4 kbps, FDEV = 20 kHz DR = 9.6 kbps, FDEV = 9.6 kHz DR = 9.6 kbps, FDEV = 19.2 kHz DR = 20 kbps, FDEV = 10 kHz DR = 20 kbps, FDEV = 20 kHz DR = 50 kbps, FDEV= 25 kHz DR = 50 kbps, FDEV = 50 kHz DR = 100 kbps, FDEV = 50 kHz DR = 200 kbps, FDEV= 50 kHz DR = 200 kbps, FDEV = 100 kHz DR = 300 kbps, FDEV = 50 kHz DR = 300 kbps, FDEV = 150 kHz Min. -120 Typ. 30 Max. Unit dBc 45 dBc 70 dBc 72 dBc 75 dBc -25 dBm 20 dBm -122.9 dBm -121.8 dBm -119.5 dBm -120.6 dBm -120.3 dBm -119.7 dBm -116.0 dBm -116.1 dBm -114.2 dBm -113.0 dBm -110.6 dBm -109.0 dBm -107.8 dBm -103.5 dBm -104.3 dBm -98.0 dBm -101.6 dBm Rev. 0.9 | 10/65 www.cmostek.com CMT2380F32 1.5 Transmitter Table 7. Transmitter Specifications Parameter Output power Output power step GFSK (Gaussian filter coefficient) Output power change with different temperature Spurious emissions Harmonic output[1] for FRF= 433 MHz Harmonic output[1] for FRF= 868 MHz Harmonic output[1] for FRF= 915 MHz Harmonic output[1] for FRF= 433 MHz Harmonic output[1] for FRF= 868 MHz Harmonic output[1] for FRF= 915 MHz Symbol POUT PSTEP Condition Specific matching network is required for different frequency bands BT Min. -20 0.3 POUT-TOP Temperature range:-40 to + 85 C H2433 H3433 H2868 H3868 H2915 H3915 H2433 H3433 H2868 H3868 H2915 H3915 POUT = +13 dBm,433MHz, FRF<1 GHz 1 GHz to12.75 GHz, including harmonics 2nd harmonic,+20 dBm POUT 3nd harmonic,+20 dBm POUT 2nd harmonic,+20 dBm POUT 3nd harmonic,+20 dBm POUT 2nd harmonic,+20 dBm POUT 3nd harmonic,+20 dBm POUT 2nd harmonic,+13 dBm POUT 3nd harmonic,+13 dBm POUT 2nd harmonic,+13 dBm POUT 3nd harmonic,+13 dBm POUT 2nd harmonic,+13 dBm POUT 3nd harmonic,+13 dBm POUT Typ. 1 0.5 1 - 46 - 50 - 43 - 52 - 48 - 53 - 52 - 52 - 52 - 52 - 52 - 52 Max. +20 1.0 -54 -36 Unit dBm dB - dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm Notes: [1]. The harmonic level mainly depends on the matching network. Above parameters are measured based on the CMT2380F32-EM, users may get different results on their applications. Rev. 0.9 | 11/65 www.cmostek.com CMT2380F32 1.6 RF Operating Mode Switching Time Table 8. RF Operating Mode Switching Time Parameter RF operating mode switching time Symbol T [1] SLP-R X T [1] SLP- T X TSTB-R X TSTB-TX TRFS-R X TTFS-R X TT X-R X TR X-T X Condition From sleep to RX From sleep to TX From standby to RX From standby to TX From RFS to RX From TFS to TX From TX to RX (Needs 2Tsymbol to ramp down) From RX to TX Min. Typ. 1 1 350 350 20 20 2Tsymbol +350 350 Max. Units ms ms us us us us us us Notes: [1]. TSLP-RX and TSLP-TX are dominated by the crystal oscillator startup time, and the start-up time is to a large degree crystal dependent. 1.7 RF Frequency Synthesizer Parameter Frequency range Frequency resolution Frequency tuning time Phase noise @ 433 MHz Phase noise @ 868 MHz Phase noise @ 915 MHz Symbol FRF FRES tTUNE PN433 PN868 PN915 Table 9. RF Frequency Synthesizer Condition Min. 760 380 190 127 10 kHz deviation 100 kHz deviation 500 kHz deviation 1MHz deviation 10 MHz deviation 10 kHz deviation 100 kHz deviation 500 kHz deviation 1MHz deviation 10 MHz deviation 10 kHz deviation 100 kHz deviation 500 kHz deviation 1MHz deviation 10 MHz deviation Typ. Max. Unit 1020 MHz 510 MHz 340 MHz 170 MHz 25 Hz 150 us -94 dBc/Hz -99 dBc/Hz -118 dBc/Hz -127 dBc/Hz -134 dBc/Hz -92 dBc/Hz -95 dBc/Hz -114 dBc/Hz -121 dBc/Hz -130 dBc/Hz -89 dBc/Hz -92 dBc/Hz -111 dBc/Hz -121 dBc/Hz -130 dBc/Hz Rev. 0.9 | 12/65 www.cmostek.com CMT2380F32 1.8 Requirement on Crystals for RF Section Table 10. Requirement on Crystals for RF Section Parameter Crystal frequency[1] Crystal frequency tolerance[2] Load capacitance ESR Crystal startup time[3] Symbol FXTAL ppm CLO AD Rm tXTAL Condition Min. Typ. Max. Unit 26 MHz 20 ppm 15 pF 60 400 us Notes: [1]. An external 26 MHz reference clock can be used to drive the XI pin directly through a coupling capacitor if such a clock is available. The peak-to-peak level of the external reference clock is required between 0.3 and 0.7 V. [2]. It involves:(1) initial tolerance, (2) crystal loading, (3) aging, and (4) temperature changing. The acceptable crystal frequency tolerance is subject to the bandwidth of the receiver and the RF tolerance between the receiver and its paired transmitter. [3]. This parameter is to a large degree crystal dependent. 1.9 Controller Output Features Table 11. Controller Output Features Parameter Output high level Output low level Output high level (enhanced mode) Output low level (enhanced mode) Symbol VO H VOL VO HD VOLD Condition Sourcing 4 mA current, VDD = 3.3V Sourcing 6 mA current, VDD= 3.3V Sinking 4 mA current, VDD = 3.3V Sinking 6 mA current, VDD= 3.3V Sourcing 8 mA current, VDD = 3.3V Sourcing 12 mA current, VDD = 3.3V Sinking 8 mA current, VDD = 3.3V Sinking 12 mA current, VDD = 3.3V Min. VDD - 0.25 VDD - 0.60 VDD - 0.25 VDD - 0.60 Typ. Max. VDD + 0.25 VDD + 0.60 VDD + 0.25 VDD + 0.60 Unit V V V V V V V V Notes: 1. The maximum total current of IOH and IOL (sum of all pins) shall not exceed 40 mA to meet the specified maximum voltage drop. 2. The maximum total current of IOH and IOL (sum of all pins, enhanced mode) shall not exceed 100 mA to meet the specified maximum voltage drop. Rev. 0.9 | 13/65 www.cmostek.com Voltage (V) VOL @ VDD = 3.3 V Low drive High drive CMT2380F32 Voltage (V) VOH @ VDD = 3.3 V Low drive High drive Current (mA) Figure 2. Controller I/O Driving Ability 1.10 Controller Input FeaturesP0, P1, P2 and P3 Reset) Current (mA) Table 12. Controller Input FeaturesP0, P1, P2 and P3 Reset) Parameter Output high level Output low level Input hysteresis range (VIH-VIL) Pull-up resistor Input capacitance Symbol VIH VIL VHYS RPUP Condition VDD = 1.8 V VDD = 3.3 V VDD = 1.8 V VDD = 3.3 V VDD = 1.8 V VDD = 3.3 V Pull-up enabled Sinking 12 mA currentVDD = 3.3 V Min. 1 1.8 0.6 1.1 0.4 0.7 Typ. 1.1 2 0.7 1.3 0.4 0.7 80 5 Max. 1.2 2.2 0.8 1.5 0.4 0.7 Unit V V V V V V k pF 1.11 Port External Input Sampling Requirements (Timer Gate/Timer Clock) Table 13. Port External Input Sampling Requirements (Timer Gate/Timer Clock) Parameter External interrupt input pulse width Timer 4/5/6 capture pulse width (FSYS=4MHz) Timer 0/1/2/4/5/6 external clock input (FSYS=4MHz) PCA external input clock Notes: Symbol TINT TCAP TCLK TPCA Condition VDD = 1.8 V VDD = 3.3 V VDD = 1.8 V VDD = 3.3 V VDD = 1.8 V VDD = 3.3 V VDD = 1.8 V VDD = 3.3 V Min. 30[1] 30[1] 0.5 0.5 Typ. Max. PCLK/2 PCLK/2 PCLK/8 PCLK/8 Unit ns ns us us MHz MHz MHz MHz [1]. It's the minimum external interrupt input pulse width used in the practical test for triggering the interrupt. It can support triggering the interrupt with even shorter pulse width based on the chip capability. 1.12 Port Leakage Features (P0, P1, P2 and P3) Rev. 0.9 | 14/65 www.cmostek.com CMT2380F32 Table 14. Port Leakage Features (P0, P1, P2, and P3) Parameter Leakage current Symbol Ilkg(Px,y) Condition VDD: 1.8 to 3.6V Min. Typ. Max. Unit ± 50 nA Notes: [1]. Unless otherwise specified, the leakage current is measured with GND or VDD applied to the corresponding pin. [2]. The pin to be tested must be set to input mode. 1.13 Controller Power Consumption Features Table 15. Controller Power Consumption Features Parameter Symbol Condition Note 4 MHz Typ. Max. Unit 220 uA VCORE = 1.55 V, VDD = 3.3 V. All 8 MHz 400 uA Operating current peripheral clock sources are off. when program IDD-RAM Run While(1) in SRAM with RCH 16 MHz 740 uA running in SRAM as clock source. 24 MHz 1080 uA 32 MHz 1400 uA 4 MHz 670 uA Core mark operating current IDD-Mark VCORE = 1.55 V, VDD = 3.3 V. All peripheral clock sources are off. Run Core Mark in Flash with RCH as clock source VCORE = 1.55 V, VDD = 3.3 V. All peripheral clock sources are on. Run While(1) in Flash with RCH as clock source. 8 MHz 16 MHz 24 MHz 32 MHz Flash Wait=1 4 MHz 8 MHz 16 MHz 24 MHz 1300 uA 2380 uA 3410 uA 3530 uA 700 880 uA 1350 1600 uA 2500 3000 uA 3600 4300 uA Operating current Sleep current IRUN VCORE = 1.55 V, VDD = 3.3 V. All peripheral clock sources are off. Run While(1) in Flash with RCH as clock source. VCORE = 1.55 VVDD = 1.8~3.6 V. ISLP All peripheral clock sources are on with RCH as clock source. 4 MHz 8 MHz 16 MHz 24 MHz 32 MHz Flash Wait=1 4 MHz 8 MHz 16 MHz 550 750 uA 1050 1300 uA 1900 2400 uA 2700 3300 uA 2850 3000 uA 260 280 uA 500 520 uA 950 970 uA Rev. 0.9 | 15/65 www.cmostek.com CMT2380F32 Parameter Symbol Condition Note 24 MHz 4 MHz VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off. RCH clock source is used. 8 MHz 16 MHz 24 MHz LP operating current LP sleep current ILP-R UN ILP-R UN ILP-SLP ILP-SLP 32 MHz VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are on. Run While(1) in Flash with XTAL (32768Hz, Driver = 1) as clock source. TA = -40 ~ 25 TA = 50 TA = 85 VCORE = 1.55V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off. Run While(1) in Flash with XTAL (32768 Hz, Driver = 1) as clock source. TA = - 40 ~ 25 TA = 50 TA = 85 VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are on. Run While(1) in Flash with XTAL (32768 Hz, Driver = 1) as clock source. TA = - 40 ~ 25 TA = 50 TA = 85 VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off (except LPTimer and RTC). Run While(1) in Flash with XTAL (32768Hz, Driver = 1) as clock source. TA = - 40 ~ 25 TA = 50 TA = 85 VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off, except LPTimer, WDT and RTC. TA = - 40 ~ 25 TA = 50 TA = 85 Deep sleep current IDEEP-SLP VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off, except WDT. TA = - 40 ~ 25 TA = 50 TA = 85 VCORE = 1.55 V, VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off, except LPTimer. TA = - 40 ~ 25 TA = 50 TA = 85 VCORE = 1.55 V, VDD = 1.8~3.6V. All peripheral clock sources are off, except RTC. TA = - 40 ~ 25 TA = 50 Typ. Max. Unit 1400 1420 uA 110 125 uA 190 210 uA 330 360 uA 470 500 uA 580 610 uA 7 9 uA 7.3 9.2 uA 8.9 11.3 uA 6 8 uA 6.1 8.2 uA 7.7 10.1 uA 3.3 3.5 uA 3.6 3.8 uA 5.4 5.8 uA 2.2 2.4 uA 2.5 2.6 uA 4.2 4.6 uA 1.5 1.65 uA 1.85 2.2 uA 3.5 4.2 uA 1.2 1.3 uA 1.5 1.8 uA 3.1 3.7 uA 0.9 1 uA 1.1 1.3 uA 2.6 3 uA 1.0 1.1 uA 1.2 1.5 uA Rev. 0.9 | 16/65 www.cmostek.com CMT2380F32 Parameter Symbol Condition VCORE = 1.55 V,VDD = 1.8 ~ 3.6 V. All peripheral clock sources are off. Note TA = 85 TA = - 40 ~ 25 TA = 50 TA = 85 Typ. Max. Unit 2.6 3.4 uA 0.42 0.6 uA 0.75 0.95 uA 2.2 2.7 uA Rev. 0.9 | 17/65 www.cmostek.com CMT2380F32 1.14 POR/BOR Features VVCDCD VBOR_hys+ 1.65V VBOR_hys- 1.50v Vth ~0.8v BOR_5V unknown Treset Treset unknown Figure 3. POR/BOR Features Notes: 1. POR/BOR detects the VDD voltage. 2. It detects the threshold only instead of VDD power-up and power-down slew rate. 3. The detection threshold is the same no matter the VDD is powering on or off. A reset pulse is triggered when VDD is lower than the threshold. 4. In case a reset pulse is generated, the pulse duration will not be less than Treset to guarantee a complete system reset. Table 16. POR/BOR Features Parameter Symbol Condition Min. Typ. Max. Unit POR release voltage (power-up process)BOR detection voltage (power-down process) VPOR 1.45 1.50 1.65 V 1.15 Controller External XTH Oscillator Table 17. Controller External XTH Oscillator Parameter Crystal frequency Equivalent series resistance Load capacitance Duty cycle Current consumption[1] Startup time Symbol FFCLK ESRFCLK CFCLK DCFCLK IDD TFstart Condition 32 MHz crystal 4 MHz crystal The two pins of the crystal oscillator are connected separately. 32 MHz crystal, CFCLK= 12 pF, ESRFCLK = 30 4 MHz~32 MHz Notes: [1]. It is the current consumption when configure XTH_CR_Driver = 0b1110. Min. 4 12 40 200 Typ. 30 400 50 600 Max. 32 60 1500 24 60 400 Unit MHz pF % uA us Rev. 0.9 | 18/65 www.cmostek.com CMT2380F32 1.16 Controller External 32.768 kHz Oscillator Table 18. Controller External 32.768 kHz Oscillator Parameter Crystal frequency Equivalent series resistance Load capacitance Clock duty cycle Current consumption[1] Startup time Symbol FSCLK ESRSCLK CSCLK DCFCLK IDD Tstart Condition The two pins of the crystal oscillator are connected separately. CSCLK =12pF,ESRSCLK = 65k CSCLK =12pF,ESRSCLK = 65 k,40%~60% duty cycle Min. Typ. 32.768 65 Max. 85 0 12 40 50 60 0.6 1 500 Notes: [1]. The operating current is measured under the condition at XTL_CR_Driver = 0b0011 and ESR=65k. Unit kHz k pF % uA ms 1.17 Controller Internal RCH Oscillator Parameter Table 19. Controller Internal RCH Oscillator Symbol Condition Min. Internal high speed oscillating frequency FMCLK 4 FMCLK = 4 MHz Startup time (not including software calibration) TMstart FMCLK = 8 MHz FMCLK = 16 MHz FMCLK = 24 MHz FMCLK = 4 MHz Current consumption IMCLK FMCLK = 8 MHz FMCLK = 16 MHz FMCLK = 24 MHz Clock duty cycle Frequency tolerance DCMCLK 45 VDD = 1.8 ~ 3.6 V, TA = -40 ~ +85 -2.5 DEVMCLK VDD = 1.8 V ~ 3.6 V, TA = - 20 ~ + 50 -2.0 Typ. 4.0 8.0 16.0 22.12 24.0 6.0 4.0 3.0 2.5 80 100 120 140 50 Max. 32 55 +2.5 + 2.0 Unit MHz us us us us uA uA uA uA % % % Rev. 0.9 | 19/65 www.cmostek.com CMT2380F32 1.18 Controller Internal RCL Oscillator Parameter Internal high speed oscillating frequency Startup time Current consumption Clock duty cycle Frequency tolerance Table 20. Controller Internal RCL Oscillator Symbol FACLK Condition Min. Typ. 38.4 32.768 TACLK IACLK DCACLK DEVACLK VDD = 1.8 ~ 3.6V, TA = - 40 ~ + 85 VDD = 1.8 ~ 3.6V, TA = - 20 ~ + 50 100 0.25 25 50 -2.0 -1.5 Max. 75 +2.0 +1.5 Unit kHz us uA % % % 1.19 Controller Flash Features Parameter Sector endurance Byte Program Time Sector erase time Chip erase time Data retention Table 21. Controller Flash Features Symbol ECFlash TProg TErase Condition Min. 20 6 4 30 TA = +25 °C 20 RETFlas h TA = +85 °C 10 Typ. Max. 7.5 5 40 Unit kcycles us ms ms Year Year 1.20 Controller Low Power Mode Recover Time Table 22. Controller Low Power Mode Recover Time Parameter Symbol Condition Min. Regulated 1.5 V, TA = + 25°C, 4 MHz Typ. 4.0 Regulated 1.5 V, TA = + 25°C, 8 MHz 3.1 Return to active mode from TWakeup deep sleep mode Regulated 1.5 V, TA = + 25°C, 16 MHz 2.8 Regulated 1.5 V, TA = + 25°C, 24 MHz 2.7 Max. Unit us us us us Rev. 0.9 | 20/65 www.cmostek.com CMT2380F32 1.21 Controller ADC Features AIN0 ADC_CR0[10] ADC_CR0[12:11] ADC_CR0[1:0] AIN8 VCC/3 1.2V Refe1r.e2ncVeVolt age + - Temperature Sensor ADC_CR0[7:4] ADC_CR2[7:0] ADC_CR0[3:2] S&aHmopldle SARADC 1.5V 2.5V ExRef VCC ADCREF PCLK PCLK/2 PCLK/4 PCLK/8 ADCCLK ADC_CR0[9:8] ADC_Result ADC_Result0 ADC_Result8 ADC_ResultAcc Figure 4. Controller ADC Features Table 23. Controller ADC Features Parameter Input voltage range External input reference voltage Internal 2.5V reference voltage Internal 1.5 V reference voltage Operating current (including reference source and buffer) Operating current (not including reference source and buffer) Input capacitance ADC clock Startup time (ADC core and reference source) Conversion time Valid bit Symbol VADCin Condition Single-ended VADC_REF_IN VREF_25 TA = 25°C,VDD = 3.3 V VREF_15 TA = 25°C,VDD = 3.3 V IADC1 200 ksps IADC2 1000 ksps CADC _ IN FADC_C LK TADC_START TADC_CO NV ENOB 1 Msps @ VDD 2.7 V 500 ksps @ VDD 2.4 V 200 ksps @ VDD 1.8 V REF = EXREF(External Reference) 1 Msps @ VDD 2.7 V 500 ksps @ VDD 2.4 V 200 ksps @ VDD 1.8 V Rev. 0.9 | 21/65 Min. 0 0 2.475 1.485 20 Typ. Max. VA DC_ REF_ IN 3.6 Unit V V 2.5 2.525 V 1.5 1.515 V 2 mA 0.5 mA 16 19.2 pF 24 MHz 30 us 24 28 Cycles 10.3 bit 10.3 bit www.cmostek.com CMT2380F32 Parameter Signal to noise ratio Differential nonlinearity Integral nonlinearity Drift error Gain error Missing code Symbol SNR DNL INL Eoffset Egain MC Condition REF = VDD 200ksps @ VDD 1.8 V REF = Internal 1.5V 200ksps @ VDD 2.8 V REF = Internal 2.5 V 1 Msps @ VDD 2.7 V 500 ksps @ VDD 2.4 V 200 ksps @ VDD 1.8 V REF = EXREF(External Reference) 1 Msps @ VDD 2.7 V 500 ksps @ VDD 2.4 V 200 ksps @ VDD 1.8 V REF = VDD 200 ksps @ VDD 1.8 V REF = Internal 1.5V 200 ksps @ VDD 2.8 V REF = Internal 2.5V Min. Typ. 9.4 9.4 68.2 68.2 60 60 -1 -3 0 0 11.999 12 Max. +1 +3 Unit Bit Bit dB dB dB dB LSB LSB LSB LSB bit Rev. 0.9 | 22/65 www.cmostek.com CMT2380F32 1.22 Analog Voltage Comparator VC0_CR[3:1] VC0_CR[14:12] VCIN7 VCVICNI0N0 VcoreVcVoorlteage Temperature Sensor ADC ReferenAcDeCVoltage 1.2V Refere1n.c2eVVoltage VC_CR[7] VC0_CR[0] Trigger Policy Select ion VC_CR[11:8] VCIN7 VCIN0 - + VC0 VC0_CR[3:1] Digital Filtering VC0_CR[15] VC0_CR[11:8] ADC RefereAncDeCVoltage SupplyVoltage V1c.o2rVeVoltage TemperaAtuDrCeSensor ADC ReferenceVoltage 1.2V ReferenceVcVoorletage VVCCIINN00 VCIN7 RDeivsidisitnogr VC_CR[6:0] VC1_CR[3:1] VCIN0 VCIN7 VC1 + - VC1_CR[11:8] Digital Filtering VC1_CR[15] VC_CR[15:12] VC1_CR[0] Trigger Policy Select ion VC1_CR[3:1] VC1_CR[14:12] Figure 5. Analog Voltage Comparator VVCCO0Interrupt VVCC1OInterrupt Table 24. Analog Voltage Comparator Parameter Input voltage range Common-mode input range Input offset Internal 1.2 V reference voltage Comparator current Comparator response time Comparator startup time (data signal does not change when it is enabled) Symbol VIN VIN_CO M VOffset Condition Single-ended TA = 25°C, VDD = 3.3V V1P2_AT ICO MP TRESPO NSE TSetup VCx_BIAS_SEL = 00 VCx_BIAS_SEL = 01 VCx_BIAS_SEL = 10 VCx_BIAS_SEL = 11 VCx_BIAS_SEL = 00 VCx_BIAS_SEL = 01 VCx_BIAS_SEL = 10 VCx_BIAS_SEL = 11 VCx_BIAS_SEL = 00 VCx_BIAS_SEL = 01 VCx_BIAS_SEL = 10 VCx_BIAS_SEL = 11 Min. 0 0 -10 Typ. Max. 3.6 VDD - 0.2 +10 Unit V V mV 1.2 V 0.16 1.28 uA 10 20 20 5 us 1 0.2 20 5 us 1 0.2 Rev. 0.9 | 23/65 www.cmostek.com Parameter From main band gap being enabled to V1P2_AT being stable From 2.5V being enabled & BGR being enabled to V2P5 being stable V2P5 reference source current Digital filtering time Symbol TWarmup1 TWarmup2 IV2P5 TFilter Condition VC_debounce = 000 VC_debounce = 001 VC_debounce = 010 VC_debounce = 011 VC_debounce = 100 VC_debounce = 101 VC_debounce = 110 VC_debounce = 111 CMT2380F32 Min. Typ. 20 Max. Unit us 15 us 4 uA 25 50 100 400 us 1,600 6,000 25,000 100,000 Rev. 0.9 | 24/65 www.cmostek.com CMT2380F32 1.23 Low Battery Detection Features LVD_CR[3:2] VCC P03 P23 P25 LVD_CR[0] + LVD_CR[11:8] FDiltigeirtianlg LVD_CR[15] LVLVDDInterrupt tLhVrLeDVshDold LVD_CR[7:4] Trigger Policy Selection LVD_CR[14:12] LVD_CR[1] LLVVDDInterrupt Figure 6. Low Battery Detection Features Rev. 0.9 | 25/65 www.cmostek.com CMT2380F32 Table 25. Low Battery Detection Features Parameter External input voltage range VDD or VEX detection threshold Low battery detection operating current Low battery detection response time (when VDD or VEX falls below or rises above the thresholds) Startup time (when it is enabled, VDD or VEX does not change) Hysteresis voltage Digital filtering time Symbol VEX VLEVEL ILVD TResponse TSetup VHyste TFilter Condition Single-ended LVD_CR_VTDS = 0000 LVD_CR_VTDS = 0001 LVD_CR_VTDS = 0010 LVD_CR_VTDS = 0011 LVD_CR_VTDS = 0100 LVD_CR_VTDS = 0101 LVD_CR_VTDS = 0110 LVD_CR_VTDS = 0111 LVD_CR_VTDS = 1000 LVD_CR_VTDS = 1001 LVD_CR_VTDS = 1010 LVD_CR_VTDS = 1011 LVD_CR_VTDS = 1100 LVD_CR_VTDS = 1101 LVD_CR_VTDS = 1110 LVD_CR_VTDS = 1111 LVD_debounce = 000 LVD _debounce = 001 LVD _debounce = 010 LVD _debounce = 011 LVD _debounce = 100 LVD _debounce = 101 LVD _debounce = 110 LVD _debounce = 111 Min. Typ. Max. Unit 0 VDD V 1.86 1.96 2.07 2.17 2.27 2.38 2.48 2.58 V 2.69 2.79 2.89 3.00 3.10 3.20 3.31 3.41 0.12 uA 80 us 5 us 20 mV 30 40 50 130 us 480 1,800 7,300 29,000 Rev. 0.9 | 26/65 www.cmostek.com CMT2380F32 1.24 Receive Current and Supply Voltage Correlation Rx Current vs. Supply Voltage 434MHz 868MHz 8.80 Current Comsumption(mA) 8.60 8.40 8.20 8.00 7.80 7.60 7.40 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage(V) Test ConditionsFreq = 434 MHz & 868 MHz, FDEV = 10 kHz, BR = 10 kbps Figure 7. Rx Current vs. Supply Voltage 1.25 Correlation Among Receive Current, Supply Voltage and Temperature Rx Current vs. Volt-Temp Current Consumption(mA) 9.5 9.3 9.0 8.8 8.5 8.3 8.0 7.8 7.5 7.3 7.0 -40 25 Temperature() Test ConditionsFreq = 434 MHz, FDEV = 10 KHz, BR = 10 kbps Figure 8. Rx Current vs. Volt-Temp 3.3V 1.8V 3.6V 85 Rev. 0.9 | 27/65 www.cmostek.com CMT2380F32 Current Consumption(mA) Rx Current vs. Volt-Temp 3.3V 1.8V 3.6V 9.5 9.3 9.0 8.8 8.5 8.3 8.0 7.8 7.5 7.3 7.0 -40 25 85 Temperature() Test Conditions: Freq = 868 MHz, FDEV= 10 kHz, BR = 10 kbps Figure 9. Rx Current vs. Volt-Temp 1.26 Receive Sensitivity and Supply Voltage Correlation Sensitivity(dBm) -113.0 -113.5 -114.0 -114.5 -115.0 -115.5 -116.0 -116.5 -117.0 -117.5 1.8 Sensitivity vs. Voltage 2.1 2.4 2.8 3.0 Supply Voltage(V) Test Conditions: FSK modulation, FDEV = 10 kHz, BR = 10 kbps Figure 10. Sensitivity vs. Voltage 434MHz 868MHz 3.3 3.6 Rev. 0.9 | 28/65 www.cmostek.com 1.27 Receive Sensitivity and Temperature Correlation CMT2380F32 Sensitivity(dBm) -112.0 -113.0 -114.0 -115.0 -116.0 -117.0 -118.0 Sensitivity vs. Temperature -40 25 Temperature() Test ConditionsFSK modulation, FDEV = 10 kHz, BR = 10 kbps 434MHz 868MHz 85 Figure 11. Sensitivity vs. Temperature 1.28 Transmit Power and Supply Voltage Correlation Tx Power(dBm) Tx Power vs. Supply Voltage 20dBm 13dBm 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 10.0 1.8 1.9 2.0 2.1 2.2 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage(V) Test ConditionsFreq = 434 MHz, 20 dBm & 13 dBm matching network respectively Figure 12. Tx Power vs. Supply Voltage Rev. 0.9 | 29/65 www.cmostek.com CMT2380F32 Tx Power(dBm) Tx Power vs. Supply Voltage 13dBm 20dBm 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 10.0 9.0 1.8 1.9 2.0 2.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage(V) Test ConditionsFreq = 868MHz, 20dBm&13dBmmatching network respectively 1.29 Phase Noise Figure 13. Tx Power vs. Supply Voltage Power (dBm) 433.92 MHz Phase Noise 20 13.4dBm 0 -20 -40 -60 -80 -100 431.92 432.42 432.92 center 433.92MHz 433.42 433.92 434.42 (2000pts ) Res BW 1kHz 434.92 435.42 435.92 sweep 5s Figure 14. 433.92MHz Phase Noise Rev. 0.9 | 30/65 www.cmostek.com CMT2380F32 868 MHz Phase Noise 20 12.4dBm 0 Power (dBm) -20 -40 -60 -80 -100 866 866.5 867 867.5 868 868.5 869 869.5 870 center 868MHz sweep 5s (2000pts ) Res BW 1kHz Figure 15. 868 MHz Phase Noise 2 Pin Description Figure 16. The CMT2380F32 Pin Arrangement Diagram Rev. 0.9 | 31/65 www.cmostek.com CMT2380F32 Pin # 0 1 2 - 3 4 5 6 7 8[1] 9 10 11 12 13 14 Table 26. The CMT2380F32 Pin Description Pin Name GND NC RFIP/RFIN FRO RF-AVDD RF-DGND RF-DVDD GPIO3 P32 TIM3_TOGN PCA_CH2 TIM6_CHB VC1OUT UART1_TXD PCA_CH4 RTC_1HX AIN2/VC2 P33 UART2_RXD PCA_CH1 TIM5_CHB PCA_ECI UART1_RXD XTL_OUT TIM1_TOGN AIN3/VC3 NC NC NC P34 PCA_CH0 UART2_TXD TIM5_CHA TIM0_EXT TIM4_CHA RTC_1HZ TIM1_TOG AIN4/VC4 I/O Description I Chip substrate, must connect to ground - No connection I Differential RF signal input port O PA output I RF circuit VDD, requires to connect to a 1.8-3.6 V power supply I GND, must connect to ground I Digital VDD, requires to connect to a 1.8-3.6 V power supply IO Can be configured as: CLKO, DOUT/DIN, INT2 and DCLK (TX/RX) IO General purpose digital input/output pin O LPtimer inverted reversal output IO PCA capture input/compare output 2 IO Timer6 capture input/compare output B O VC1 output O UART1 TXD IO PCA capture input/compare output 4 O RTC1HZ output I Analog input IO General purpose digital input/output pin I UART2 RXD IO PCA capture input / compare output 1 IO Timer5 capture input / compare output B I PCA external clock I UART1 RXD O 32K Oscillating output O Timer1 inverted reversal output I Analog input - Not connect - Not connect - Not connect IO General purpose digital input/output pin IO PCA capture input / compare output 0 O UART2 TXD IO Timer5 capture input / compare output A I Timer0 external clock input IO Timer4 capture input / compare output A O RTC1HZ output O Timer1 inverted output I Analog input Rev. 0.9 | 32/65 www.cmostek.com CMT2380F32 Pin # 15 16 17 18 19 Pin Name P35 UART1_TXD TIM6_CHB UART0_TXD TIM0_GATE TIM4_CHB SPI_MISO I2C_SDA AIN5/VC5 P36 UART1_RXD TIM6_CHA UART0_RXD PCA_CH4 TIM5_CHA SPI_MOSI I2C_SCL AIN6/VC6/AVREF P00 ResetB P01 UART0_RXD I2C_SDA UART1_TXD TIM0_TOG TIM5_CHB SPI_SCK TIM2_EXT AIN7/VC7 XTHI P02 UART0_TXD I2C_SCL UART1_RXD TIM0_TOGN TIM6_CHA SPI_CS TIM2_GATE AIN8 XTHO I/O Description IO General purpose digital input/output pin O UART1 TXD IO Timer6 capture input / compare output B O UART0 TXD I Timer0 gating IO Timer4 capture input / compare output B I SPI Module master input slave output data signal IO I2Cdata I Analog input IO General purpose digital input/output pin UART1 RXD Timer6 capture input / compare output A UART0 RXD PCA capture input / compare output 4 Timer5 capture input / compare output A SPI module master output slave input data signal I I2C Clock O Analog input I Digital input I Reset input port, active low, chip reset IO General purpose digital input/output pin I UART0 RXD IO I2C data O UART1 TXD O Timer0 inverted output IO Timer5 capture input / compare output B O SPI clock O Timer2 external clock I Analog input I External XTH crystal oscillator clock input IO General purpose digital input/output pin O UART0 TXD O I2C clock I UART1 RXD O Timer0 inverted reversal output IO Timer6 capture input / compare outputA O SPI CS I Timer2 gating I Analog Input O External XTH crystal oscillator clock output Rev. 0.9 | 33/65 www.cmostek.com CMT2380F32 Pin # 20 21 22 23 24 25 26 27 Pin Name MCU-GND MCU-VCAP MCU-VDD P03 PCA_CH3 SPI_CS TIM6_CHB LPTIM_EXT RTC_1HZ PCA_ECI VC0_OUT LVDIN1 P15 I2C_SDA TIM2_TOG TIM4_CHB LPTIM_GATE SPI_SCK UART0_RXD LVD_OUT XTLO P14 I2C_SCL TIM2_TOGN ECI ADC_RDY SPI_CS UART0_TXD XTLI P23 TIM6_CHA TIM4_CHB TIM4_CHA PCA_CH0 SPI_MISO UART1_TXD IR_OUT LVDIN2/VC0 P24 TIM4_CHB I/O Description I Digital Ground O LDO core power supply output (internal circuit only, connect 4.7uF capacitor) I Digital Power Supply IO General purpose digital input/output pin O PCA capture input / compare output 3 O SPI CS IO Timer6 capture input / compare output B I LPTimer external clock input O RTC 1Hz output I PCA external clock input O VC0 output I Analog input IO General purpose digital input/output pin IO I2C data O Timer2 inverted output IO Timer4 capture input / compare output B I LPTimer gating O SPI clock I UART0 RXD O LVD output O External XTL crystal oscillator clock input IO General purpose digital input/output pin O I2C clock O Timer2 inverted reversal output I PCA external clock input O ADC ready O SPI CS O UART0 TXD I External XTL crystal oscillator clock input IO General purpose digital input/output pin IO Timer6 capture input / compare output A IO Timer4 capture input / compare output B IO Timer4 capture input / compare output A IO PCA capture input / compare output0 IO SPI Module master input slave output data signal O UART1 TXD O 38k carrier output I Analog input IO General purpose digital input/output pin IO Timer4 capture input / compare output B Rev. 0.9 | 34/65 www.cmostek.com CMT2380F32 Pin # 28 29 30 31 Pin Name TIM5_CHB HCLK_OUT PCA_CH1 SPI_MOSI UART1_RXD VC1_OUT AIN0 P25 SPI_SCK PCA_CH0 TIM5_CHA LVD_OUT UART2_RXD I2C_SDA TIM1_GATE LVDIN3/VC1 P26 SPI_MOSI TIM4_CHA TIM5_CHB PCA_CH2 UART2_TXD I2C_SCL TIM1_EXT AIN1 P27 SPI_MISO TIM5_CHA TIM6_CHA PCA_CH3 UART0_RXD RCH_OUT XTH_OUT SWDIO P31 TIM3_TOG PCA_ECI PCLK_OUT VC0OUT UART0_TXD I/O Description IO Timer5 capture input / compare output B O HCLK output IO PCA capture input / compare output 1 O SPI module master output slave input data signal I UART1 RXD O VC1 output I Analog input IO General purpose digital input/output pin O SPI Clock IO PCA capture input / compare output 0 IO Timer5 capture input / compare output A O LVD output I UART2 RXD IO I2C data I Timer1 gating I Analog input IO P26 general purpose digital input/output pin O SPI Module master output slave input data signal IO Timer4 capture input / compare output A IO Timer5 capture input / compare output B IO PCA capture input / compare output 2 O UART2 TXD O I2C Clock I Timer1 external clock input I Analog input IO General purpose digital input/output pin IO SPI Module master input slave output data signal IO Timer5 capture input / compare output A IO Timer6 capture input / compare output A IO PCA capture input / compare output 3 I UART0 RXD O 24 M oscillating output O 32 M oscillating output IO Debugging interface, SWDIO IO General purpose digital input/output pin O Timer 3 Inverted output I PCA external clock O PCLK output O VC0 output O UART0 TXD Rev. 0.9 | 35/65 www.cmostek.com CMT2380F32 Pin # 32 33 34 35 36 37 38 39 40 Pin Name RCL_OUT HCLK_OUT SWCLK SCLK SDA CSB FCSB NC XI XO GPIO2 GPIO1 I/O Description O RCL oscillating output O HCLK output I Debugging interface, SWCLK I RF SPI clock IO RF SPI data input/output, connect to 10 k pull-up resistor externally I RF SPI chip selection for register access I RF SPI chip selection for FIFO access - Not connect I 26 MHz crystal circuit input O 26 MHz crystal circuit output IO Can configure as: INT1,INT2,DOUT/DIN,DCLK (TX/RX),RF_SWT IO Can configure as: DOUT/DIN,INT1,INT2,DCLK (TX/RX),RF_SWT Notes: [1]. INT1 and INT2 refer to RF interrupts. DOUT refers to the demodulated data output. DIN refers to the modulation data input. DCLK refers to the modulation or demodulation data rate synchronous clock, which is switched automatically according to operation mode switch between TX and RX. Rev. 0.9 | 36/65 www.cmostek.com CMT2380F32 3 Chip Structure XIN XOUT PA RXIP RXIN SWDIO SWCLK VC0_OUT VCIN0~VCIN7 AIN0~AIN8 ADC_RDY VCO LOOP FILTER CP PFD 26 Mhz XO PA D- DIV M- DIV AFC LOOP LNA I LMT Q LMT SWD Cortex-M0+ CPU NVIC Temp. Sensor VC0 VC1 12-bit ADC LVD BGR Vref AHB 2 APB AHB Bus Matirx RSSI AGC LOOP ADC Flash 32KB SRAM 4KB CRC I2C SPI LP UART UART0 UART1 PCA Timer4 Timer5 Timer6 Timer0 Timer1 Timer2 LPTimer RTC LFOSC LDOs POR Bandgap Registers Radio Controller SPI, FIFO Interface MODEM Packet Handler FIFO IO Ctrl System Control XTL XTH POR BOR RCH RCL Power VDD to VCore P3 P2 P1 P0 VDD GND FCSB CSB SCLK SDA GPIO1 GPIO2 GPIO3 XTLI XTLO XTHI XTHO RESET MCU-VDD GND P0.0~P0.3 P1.4, P1.5 P2.3~P2.7 P3.1~P3.6 LPTIM_GATE LPTIM_EXT LPTIM_TOG LPTIM_TOGN TIMn_GATE TIMn_EXT TIMn_TOG TIMn_TOGN TIMn_CHA TIMn_CHB PCA_ECI PCA_CHn UARTn_TxD UARTn_RxD UART2_TxD UART2_RxD SPI_SCK SPI_CS SPI_MISO SPI_MOSI I2C_SDA I2C_SCL Figure 17. Functional System Block Diagram The CMT2380F32 is a microcontroller integrated with high-performance sub-GHz wireless transceiver. The internal system block diagram of the CMT2380F32 is shown in Figure 17. Low-power and High-performance Sub-GHz Transceiver With supports of 127 to 1020MHzfrequency range, modulation modes like OOK, (G)FSK, (G)MSK, etc., the sub-GHz wireless transceiver is remarkable for low-power and high performance features adapting to various wireless transceiver applications. The product is part of the CMOSTEK NextGenRFTM product family which covers a complete product line consisting of transmitters, receivers, transceiver, etc. High Performance Cortex-M0+ Microprocessor Embedded with high-performance Cortex-M0+ core microprocessor, the CMT2380F32 suits for portable measurement systems requiring ultra-low power consumption. Powered by built-in 12-bit high-precision and high-speed SAR ADC (sampling rate up to 1Msps), comparator, rich peripherals like multi-channel UART, SPI andI2C, the CMT2380F32 is remarkable for such features as high integration, strong anti-interference and high reliability. See below table for its rich peripherals. Rev. 0.9 | 37/65 www.cmostek.com CMT2380F32 Table 27. The CMT2380F32 Peripheral Resource List ROM RAM Name Peripheral Resource 32 kbytes Flash 4 kbytes Debug function Unique identification code Multi-function serial interface ADC Serial bus debug interface Support UART0/1 LPUART SPI I2C 12-bit1 Msps SAR Analog voltage comparator Real time clock VC0/1 1 IO port 16+1 Port interrupt 16 Buzzer 4-ch Flash security protection Available RAM parity Available Internal high speed oscillator IRC 4 / 8 / 16 / 22.12 / 24 MHz Internal low speed oscillator IRC 38.4 / 32.768 kHz External high speed crystal oscillator 4 / 8 / 16 / 32 MHz Internal low speed crystal oscillator 32.768 kHz Rev. 0.9 | 38/65 www.cmostek.com CMT2380F32 4 Sub-GHz Transceiver 4.1 Transmitter The CMT2380F32 transmitter is based on direct RF synthesizer. Its carrier frequency is generated by a low noise fractional frequency synthesizer. The modulated data is transmitted by an efficient single-ended power amplifier (PA). The output power can be read and written by registers, which is configurable ranging from -20dBm to +20dBm with 1dB step. When the PA switches quickly, its changed input impedance instantaneously interferes with the output frequency of the VCO. This effect becomes a VCO pull that produces spectral spurs and glitches near the target carrier. By ramping the PA output power, it can minimize the instantaneous glitch of the PA. The CMT2380F32 has a built-in ramping mechanism. When the PA ramp is enabled, the PA output power can be ramped to the required value by the configured speed in order to reduce the undesired spectral spectrum. In FSK mode, the transmitter supporting signal is transmitted after Gaussian filtering, meaning GFSK, to make the transmitting spectrum more concentrated. Users can design a PA matching network based on specific application requirements to optimize the transmission efficiency at the required output power. Typical application schematics and required BOMs are detailed above. For more application schematic details and layout guidelines, please refer toAN141 CMT2300A Schematic and PCB Layout Guide. The transmitter can work in pass-through mode and packet mode respectively. In pass-through mode, data is sent to the chip directly through the DIN pin of the chip and transmitted directly. In packet mode, data is preloaded into the FIFO of the chip in STBY status and transmitted then along with other packet elements. 4.2 Receiver An ultra-low power, high performance low IF OOK, FSK receiver is built in the CMT2380F32. It follows processing steps as: 1) The RF signal sensed by the antenna is amplified by the low noise amplifier. 2) The signal is down-converted to the intermediate frequency by the quadrature mixer and then filtered by the image rejection filter. 3) The signal is further amplified by the limiting amplifier. 4) The signal is sent to the digital domain for digital demodulation processing. Each analog module is calibrated to an internal reference voltage during power-on reset (POR). This allows the chip to perform better at different temperatures and voltages. Baseband filtering and demodulation is done by a digital demodulator. When the chip is working in an environment with strong out-of-band interference, the automatic gain control loop adjusts the gain of the system through the wideband power detector and attenuation network next to the LNA to achieve optimal system linearity, selectivity, sensitivity, etc. Following the low-power design techniques of CMOSTEK, an ultra-low power is consumed even when the receiver keeps operating for long period. Its periodic operating mode and air wakeup feature further reduce the average power consumption of the system, serving well in applications where power consumption is critical. Similar to the transmitter, the CMT2380F32 receiver can operate in pass-through mode and packet mode respectively. In the pass-through mode, the data output by the demodulator can be directly output through the DOUT pin of the chip. DOUT can be configured from GPIO1/2/3. In the packet mode, data processing follows steps as: 1)The data output of the demodulator is firstly sent to the packet processor for decoding. 2)The data is filled into the FIFO. 3)The controller portion of the CMT2380F32 reads the FIFO through the SPI interface. 4.3 Transceiver Power-on Reset (POR) The power-on reset circuit assists in power supply change detection and generates a corresponding reset signal to reset the entire RF system (the RF portion of the CMT2380F32). The CMT2380F32 controller can reinitialize the RF system after POR. The two cases for POR reset generation are as follows: 1. A rapid power supply mutation triggers POR reset under the condition that RF-VDD (RF system power supply, the Rev. 0.9 | 39/65 www.cmostek.com CMT2380F32 same below) drops 0.9V±20% (0.72V 1.08V) within less than 2 us. Note that it monitors RF-VDD decrease instead of its absolute value as shown inthe below figure. < 0.2 us RF-VDD 0.9 V x (1 +/- 20%) POR Figure 18. Rapid RF-VDD Drop Triggers POR Reset 2. A slow supply power drop triggers POR reset under the condition that RF-VDD drops to 1.45V±20% (1.16 1.74V) within less than 2 us. Note that it monitors the absolute value of RF-VDD instead of RF-VDD decrease as shown in the below figure. > 0.2 us VDD 1.45 V x (1 +/- 20%) POR Figure 19. Slow RF-VDD Drop Triggers POR Reset 4.4 Transceiver Crystal Oscillator The crystal oscillator provides both a reference clock for the phase-locked loop and a system clock for the digital part. The load capacitance depends on the crystal specified CL parameters. The total load capacitance between XI and XO should be equal to CL ensuring the crystal oscillates accurately at 26 MHz. = / + / + + . C15 and C16 are the load capacitances reside at both ends of the crystal. Cpar is the parasitic capacitance resides on the PCB. Each pin of the crystal has a 5pF parasitic capacitance inside, as an equivalence of 2.5pF altogether. The equivalent series resistance of the crystal should meet the specified specifications to ensure reliable crystal start-up. Alternatively the traditional crystal can be replaced with an external source connected to the XI pin. This clock signal is recommended to have a peak-to-peak level between 300 mV and 700 mV and be coupled to the XI pin with a coupling capacitor. Rev. 0.9 | 40/65 www.cmostek.com CMT2380F32 4.5 Transceiver Built-in Low Frequency Oscillator (LPOSC) The CMT2380F32 RF system integrates a sleep timer driven by a 32 kHz low power oscillator (LPOSC). When this function is enabled, the timer periodically wakes up the chip from sleep mode. Sleep time can be configured from 0.03125 ms to 41,922,560 ms when the chip is in periodical operating mode. Due to the low power oscillator frequency will change with the temperature and voltage drift, it will be automatically calibrated during power on and will be periodically calibrated since then. These calibrations will keep the oscillator's frequency tolerance within ± 1%. 4.6 Transceiver Built-in Low Battery Detection The chip is employed with low battery detection function which is performed each time when the frequency is tuned. Frequency tuning occurs when the chip transitions from the SLEEP/STBY state to the RFS/TFS/TX/RX state. The detection result can be read by the LBD_VALUE register. 4.7 Receiver Signal Strength Indication (RSSI) The RSSI is used to evaluate the strength of the signal within the tuned channel. The cascaded I/Q logarithmic amplifier amplifies the signal before it is sent to the demodulator. The receive signal indicators inside the logarithmic amplifiers ofI channel and Q channel produce DC voltage that is proportional to the input signal strength. The RSSI output is the sum of the two signal values, which extend a dynamic range of 80 dB based on the sensitivity. After the signal strength is sampled by the ADC, a smoother RSSI value is obtained through a SAR filter and a smoothing filter. The order of the smoothing filter can be set via RSSI_AVG_MODE<2:0>. After filtering, the code value is converted into a dBm value. Users can obtain either the RSSI code value (RSSI_CODE<7:0>) ordBm value (RSSI_DBM<7:0>) by reading the register. With configuring the value of RSSI_DET_SEL<1:0>, users can choose to either output the RSSI value in real time or store RSSI value at each stage during packet receiving. The CMT2380F32 supports users to set RSSI_TRIG_TH<7:0> threshold. After a comparison between the threshold value and detected RSSI value, the comparison outputs logic 1 if the RSSI detection value is more than the threshold value, otherwise it outputs logic 0. The comparison output can be output to the RSSI VLD interrupt or it can support the operation of the internal super-low power (SLP) mode. RSSI_AVG_MODE<2:0> RSSI_DET_SEL<1:0> LATCH RSSI_CODE<7:0> SAR ADC SAR FILTER RSSI AVG FILTER CODE to dBm CONVERT LATCH RSSI_DBM<7:0> RSSI_DET_SEL<1:0> COMPARE to RSSI_TRIG_TH<7:0> RESULT Figure 20. RSSI Measuring and Comparing Circuit Structure The CMT2380F32 offers RSSI to meet the qualitative analysis requirements of users generally. However more accurate RSSI measurement results are needed in case of quantitative analysis, therefore users need to perform production calibration based on actual solutions. Please refer to AN144- CMT2300A RSSI User Guide for details. Rev. 0.9 | 41/65 www.cmostek.com CMT2380F32 4.8 Phase Jump Detector (PJD) PJD refers to the phase jump detector. During the chip performing FSK demodulation, it can be used to identify useful signals from noise via observing the hopping characteristics of received signals. 2 2 1 1 1 1 SYM SYM SYM SYM SYM SYM Figure 21.Receive Signal Jump Diagram PJD identifies an input signal transition from 0 to 1 or from 1 to 0 as a phase jump. Users simply configure PJD_WIN_SEL<1:0> to indicate PJD how many signal transitions need to be detected before output the judgment result. As shown in above diagram, 6 phase jumps occurred among the total of 8 symbols received, meaning the jump number is not equal to the number of symbols. The jump count is equivalent to the number of symbols only if preamble is received. In general, the more signal transition detected, the more reliable the judgment is. The less, the faster the detection completes. If the receiving time window is small, the number of detections needs to be reduced to meet the window setting requirements. In general, 4 signal transitions detection can ensure reliable detection, that is, neither misjudging noise as a useful signal nor the detection failure of a useful signal will happen. Monitoring signal transitions is essentially monitoring whether the signal meets the expected data rate, meanwhile, the PJD also automatically monitors whether the error of the signal meets the agreed value of the valid signal and determines if the SNR exceeds 7 dB. It outputs 1 if it determines a reliable signal is received based on the combined data rate, error and SNR monitoring results, otherwise it outputs 0 if it determines the signal is noise or interference signal. This result can be output to the RSSI VLD interrupt or to the implementation instance of the internal assisting super-low power (SLP) receive mode. In the direct mode, the FSK demodulation output can also be muted through setting the DOUT_MUTE register bit to 1based on phase jump detect result. PJD is similar to traditional carrier sense(CS) technique, more reliable though. A combine of RSSI monitoring and PJD technique ensures accurate channel state identification. 4.9 Receiver Clock Data Recovery (CDR) CDR system is largely to recover the clock signal synchronized with the data rate while receiving data, either for decoding inside the chip or outputting to the GPIO for users to sample data. Error existing between the recovered clock frequency and the actual transmitted data rate will cause data acquisition errors, error codes and decoding errors during data reception. Therefore, CDR takes a simple but critical role. The CMT2380F32 receiver supports three CDR systems according to different application requirements: COUNTING system This system is designed for the case where the data rate is relatively accurate. If the data rate is 100% aligned, users can even receive unlimited lengths of 0 without error. TRACING system This system is designed for dealing with large data rate errors. It has a tracking function that automatically detects the data rate transmitted by TX and adjusts the RX local data rate promptly to minimize the error between them. This system leads the industry by supporting up to 15.6% error. MANCHESTER system This system comes from COUNTING system by inheriting its basic features except a difference on specific design for Rev. 0.9 | 42/65 www.cmostek.com CMT2380F32 Manchester codec, which performs special treatment in case of a sudden change in the TX data rate to identify the signal part with sudden changes. 4.10 Fast Manual Frequency Hopping Manual frequency hopping refers to switching an original basic frequency point obtained by RRPDK configuration, e.g. 433.92MHz,to another frequency point by simply setting 1 or 2 registers on MCU during the application, which simplify user's operation much for switching frequency points frequently in multi-channel applications. = + . × _ < : >× _ < : > General processing steps follow: 1) Set FH_OFFSET<7:0> during the initialization configuration of power-up. 2) Switch channels constantly as desired in the application by changing FH_CHANNEL<7:0>. When fast manual frequency hopping in the receiving mode is performed, it needs to have special process on AFC parameters. Please refer to AN197-CMT2300A-CMT2119B-CMT2219B Fast Manual Frequency Hopping and CMT2300as well as CMT2219B Frequency Hopping Calculation Table for more details. 4.11 Transceiver Control Interface and Operating Mode 4.11.1 Transceiver SPI Interface Timing The RF system of CMT2380F32 communicates with the controller section via a 4-wire SPI port (FCSB, CSB, SDA and SCLK). The low active CSB is the chip selection signal used to access the registers. The low active FCSB is the chip selection signal used to access the FIFO. The above two cannot be set to low both at the same time. SCLK is a serial clock with speed up to 5MHz.Data is sent on the falling edge of SCLK and collected on the rising edge for the chip itself or an external MCU. SDA is a bidirectional pin for inputting and outputting data. Both the address and data parts are transmitted from the MSB. The CSB is pulled low when registers are accessed. An R/W bit followed by a 7-bit register address is sent. After the controller pulls CSB low, it must wait for at least half a SCLK cycle before it can start transmitting R/W bits. After the controller sends the falling edge of the last SCLK, it must wait for at least half of the SCLK cycle before pulling CSB high. It should be noted that, as for read register operations, both the controller and the transceiver may generate a switch IO (SDA) port event among address 0 and data 7. At this point, SDA will switch the IO port from input to output, and the controller will switch the corresponding IO port from output to input. In the below figure, please notice the position of the dotted line in the middle, at this time, it is strongly recommended the controller switches the IO port to input before it sends the falling edge of SCLK. The transceiver will switch the IO to output after it receives the falling edge, which avoids situations where the both set SDA to output resulting in electrical conflicts. > 0.5 SCLK cycle > 0.5 SCLK cycle CSB FCSB SCLK SDA X7654321076543210X r/w = 1 register address register read data Figure 22. Transceiver SPI Read Register Timing Rev. 0.9 | 43/65 www.cmostek.com CMT2380F32 > 0.5 SCLK cycle > 0.5 SCLK cycle CSB FCSB SCLK SDA X7654321076543210X r/w = 0 register address register write data Figure 23. Transceiver SPI Write Register Timing 4.11.2 Transceiver FIFO Interface Timing By default, the transceiver provides two independent 32-byte FIFOs for RX and TX. The RX FIFO is used to store received data in RX mode, and the TX FIFO is to store data to be transmitted in TX mode. Users can set FIFO_MARGE_EN to 1 as well, thus the two FIFOs are combined into a 64-byte FIFO, available both in TX and RX. By configuring FIFO_RX_TX_SEL, it indicates whether TX or RX currently is used. In no-combine case, when 32-byte RX FIFO is filled in, to save system operation time, users can fill in the 32-byte TX FIFO simultaneously for the next transmission. The FIFO can be accessed via the SPI interface. Users can clear the FIFO by setting the FIFO_CLR_TX/FIFO_CLR_RX bit and transmit repeated data filled previously by setting FIFO_RESTORE, which avoids data refilling. When accessing the FIFO, users start from configuring a number of registers involving FIFO read/write mode and some operating modes settings, as well as some other working modes. Please see AN143-CMT2300A FIFO and Packet Format Usage Guide for more details. As shown in below timing diagram for reading and writing, it should be noted that the FCSB control and CSB control for register access are slightly different. At the beginning of the access, the FCSB pulls down one clock cycle before sending the rising edge of SCLK. After sending the falling edge of the last SCLK, it pulls up FCSB at least 2us later. The FCSB must keep pulled up for at least 4us between two consecutive read and write operations. When writing to the FIFO, the first bit of the data must be ready a half of clock cycle before the first rising edge of SCLK is sent. > 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us CSB FCSB SCLK SDA X76543210 X 76543210X FIFO read data FIFO read data Figure 24. SPI Read FIFO Timing Rev. 0.9 | 44/65 www.cmostek.com CMT2380F32 > 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us CSB FCSB SCLK SDA X76543210 X 76543210X FIFO write data FIFO write data Figure 25. SPI Write FIFO Timing The transceiver provides enriched FIFO-related interrupt sources helping for efficient operation of the chip. The Rx and Tx-related FIFO interrupt timing is shown in the figure below. RX DATA Noise Sync 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SYNC_OK RX_FIFO_WBYTE RX_FIFO_NMTY RX_FIFO_TH (FIFO_TH = 16) RX_FIFO_FULL RX_FIFO_OVF Noise RX FIFO ARRAY EMPTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL Figure 26 Transceiver RX FIFO Interrupt Timing Schematic TX DATA Prefix Pream Sync 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 TX_FIFO_NMTY TX_FIFO_TH (FIFO_TH = 16) TX_FIFO_FULL FIFO ARRAY EMPTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL Figure 27. Transceiver TX FIFO Interrupt Timing Schematic 4.11.3 Transceiver Operating Status, Timing, and Power Consumption Startup Timing After the transceiver is powered up on RF-VDD, generally it takes about 1 ms for POR release. The crystal starts after POR release. The startup time defaults to N ms depending on characteristics of the crystal itself. After startup, it needs to wait for a Rev. 0.9 | 45/65 www.cmostek.com CMT2380F32 period of time for crystal stabilization then to start working. The default stabilization time is set as 2.48ms by default. The time can be written later by writing XTAL_STB_TIME <2:0>. The chip stays in the IDLE state until the crystal is stable. After the crystal is stabilized, the chip will leave IDLE and begin calibration for each module. After calibration, the chip will stay at SLEEP, waiting for the user to do initialization configuration. The chip returns to IDLE and resume the power-on process any time when reset is performed. RF-VDD POR POR Release XTAL Start up XTAL Stablize <= 1 ms <= N ms <= 2.48 ms Block Calibrations <= 6.5 ms Enters the SLEEP State Ready for customer initializing Figure 28. Startup Timing Diagram The chip enters SLEEP mode after calibration completion. By now, the controller can switch the chip to different operating states by setting the register CHIP_MODE_SWT<7:0>. Transceiver Operating Status The transceiver has a total of 7 working status: IDLE, SLEEP, STBY, RFS, RX, TFS and TX, as listed in the below table. Status IDLE SLEEP STBY RFS TFS RX TX Table 28. Transceiver Status and Module Startup Table Binary Code 0000 Switch Command soft_rst SPI, POR Startup Module 0001 go_sleep SPI, POR, FIFO 0010 go_stby SPI, POR, XTAL, FIFO 0011 go_rfs SPI, POR, XTAL, PLL, FIFO 0100 go_tfs SPI, POR, XTAL, PLL, FIFO 0101 go_rx SPI, POR, XTAL, PLL, LNA+MIXER+IF, FIFO 0110 go_tx SPI, POR, XTAL, PLL, PA, FIFO Optional Startup Module NA LFOSC, sleep timer CLKO CLKO CLKO CLKO, RX timer CLKO Rev. 0.9 | 46/65 www.cmostek.com CMT2380F32 go_sleep go_tx go_tfs go_sleep IDLE 0000 Power up SLEEP 0001 go_stby go_sleep go_tx go_stby STBY 0010 go_gtfos_stby go_stgboy_rfs go_rx go_stby TFS 0100 RFS 0011 go_tfs go_tx go_rfs go_rx TX 0110 go_switch go_switch RX 0101 go_sleep go_rx go_rfs go_sleep Figure 29. Status Switch Diagram SLEEP Status The power consumption of the chip keeps the lowest in SLEEP mode with almost all modules disabled. The SPI is enabled, the registers in the configuration area and control area 1 can be accessed, and the contents previously filled in the FIFO is retained but the FIFO cannot be operated. If the periodical wake-up function is enabled, the LFOSC and sleep counters will start to work. The time period required for switching from IDLE to SLEEP is the power up processing time specified in above. Switching from the rest of the status to SLEEP is done immediately. STBY Status In STBY, the crystal is enabled and the LDO of the digital circuit is enabled as well. The current is slightly increased. The FIFO can be operated. Users can choose whether to output CLKO (system clock) to the GPIOn pin. As the crystal is enabled, the time required switching from STBY to transmit or receive is less than that in SLEEP status (switching from SLEEP to STBY requires more time to wait for the crystal startup and stabilizing for a while). Switching from other status to STBY will complete immediately. RFS Status RFS is transitional status before switching to RX. Except the receiver's RF module, all others are enabled and the current will be larger than that in STBY. As the PLL is already locked to the RX frequency point in RFS status, it cannot be switched to TX. Switching from STBY to RFS requires approximately 350us for PLL calibration and settling. Switching from SLEEP to RFS requires more time to wait for the crystal startup and stabilizing for a while. Switching from other status to RFS is done immediately. TFS Status TFS is transitional status before switching to TX. Except the transmitter's RF module, all other modules are enabled and the current will be larger than STBY. As the PLL is already locked to the frequency of the TX in TFS status, it cannot be switched to Rev. 0.9 | 47/65 www.cmostek.com CMT2380F32 RX. Switching from STBY to TFS requires approximately 350us for PLL calibration and settling. Switching from SLEEP to TFS requires more time to wait for the crystal startup and stabilizing for a while. Switching from other states to TFS is done immediately. RX Status All RX related modules on the receiver will be turned on. Switching from RFS to RX takes only 20us. Switching from STBY to RX requires a 350us for PLL calibration and settling. Switching from SLEEP to RX requires more time to wait for the crystal startup and stabilizing for a while. In TX, users can switch to RX in a prompt way by sending the go_switch command. No matter whether the frequency points set by TX and RX are the same, it needs to wait for 350us for PLL recalibration and settling to accomplish switch. TX Status All transmitter related modules will be turned on at TX. Switching from TFS to TX takes only 20us. Switching from STBY to TX requires 350us for PLL calibration and settling. Switching from SLEEP to TX requires more time to wait for the crystal startup and stabilizing for a while. In RX, users can switch to TX in a prompt way by sending the go_switch command. No matter whether the frequency points set by TX and RX are the same, it needs to wait for 350us for PLL recalibration and settling to complete switch. 4.11.4 Transceiver GPIO Function and Interrupt Mapping The three GPIOs employed in the transceiver are GPIO1, GPIO2, and GPIO3. Each GPIO can be configured with different input or output functions. The transceiver is employed with two interrupt ports, which can be configured to different GPIOs for mapping output. Pin# 48 47 9 Name GPIO1 GPIO2 GPIO3 Table 29. Transceiver GOIP Function I/O Function IO Can configure as: DOUT/DIN,INT1,INT2,DCLK (TX/RX),RF_SWT IO Can configure as:INT1,INT2,DOUT/DIN,DCLK (TX/RX),RF_SWT IO Can configure as: CLKO,DOUT/DIN,INT2,DCLK (TX/RX) The interrupt mapping table is given below. Mapping for INT1 and INT2 is the same. Take INT1 as an example as follows. Name RX_ACTIVE TX_ACTIVE RSSI_VLD PREAM_OK SYNC_OK NODE_OK CRC_OK PKT_OK SL_TMO RX_TMO Table 30. Transceiver Interrupt Mapping INT1_SEL Description 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 Indicates that the interrupt is ready to enter RX or has entered RX, which is 1 in the PLL calibration and RX status, otherwise 0. Indicates that the interrupt is ready to enter TX or has entered TX, which is 1 in the PLL calibration and RX status, otherwise 0. An interrupt Indicating whether the RSSI is valid An interrupt Indicating whether Preamble is received successfully. An interrupt Indicating whether Sync Word is received successfully. An interrupt Indicating whether Node ID is received successfully. An interrupt Indicating whether receive and pass CRC check successfully An interrupt indicating receive a packet completely An interrupt indicating SLEEP counter time out An interrupt indicating RX counter time out Clear Method Auto Auto Auto by MCU by MCU by MCU by MCU by MCU by MCU by MCU Rev. 0.9 | 48/65 www.cmostek.com CMT2380F32 Name INT1_SEL Description TX_DONE RX_FIFO_NMTY RX_FIFO_TH RX_FIFO_FULL RX_FIFO_WBYTE RX_FIFO_OVF TX_FIFO_NMTY TX_FIFO_TH TX_FIFO_FULL STATE_IS_STBY STATE_IS_FS STATE_IS_RX STATE_IS_TX LBD TRX_ACTIVE PKT_DONE 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 An interrupt indicating TX completion An interrupt indicating RX counter is not empty An interrupt indicating unread contents in RX FIFO exceed FIFO TH An interrupt indicating RX FIFO is full An interrupt indicating a BYTE is written in RX FIFO, which is a pulse An interrupt indicating RX FIFO overflow An interrupt indicating TX FIFO is not empty An interrupt indicating unread contents in TX FIFO exceed FIFO TH An interrupt indicating TX FIFO is full An interrupt indicating current status is STBY An interrupt indicating current status is RFS or TFS An interrupt indicating current status is RX An interrupt indicating current status TX An interrupt indicating that low battery detection is active (VDD is lower than the set TH) An interrupt indicating begin to enter RX or TX, already in RX or TX, which is 1 in PLL calibration, RX status or TX state, otherwise 0. Indicating that the current data packet has been received with 4 cases as below: 1. Receive the entire packet completely 2. Manchester decoding error, decoding circuit automatically restarts 3. NODE ID receives error, the decoding circuit automatically restarts 4. The signal conflict is found, the decoding circuit does not restart automatically, waiting for the MCU to process Clear Method by MCU Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto by MCU The interrupt is valid for value 1 by default. However value 0 becomes valid for all interrupts by setting the INT_POLAR register bit to 1. Still take INT1 as an example as shown in the below figure with the control and selection diagram of all interrupt sources shown. INT1 and INT2 are the same in control and mapping. Rev. 0.9 | 49/65 www.cmostek.com CMT2380F32 RX_ACTIVE RSSI_VLD_FLG Preamble OK Interrupt Source 0 PREAM_OK_CLR PREAM_OK_EN 0 D Q PREAM_OK_FLG 1 Sycn Word OK Interrupt Source 0 SYNC_OK_CLR SYNC_OK_EN 0 D Q SYNC_OK_FLG 1 Node ID OK Interrupt Source 0 NODE_OK_CLR NODE_OK_EN 0 D Q NODE_OK_FLG 1 CRC OK Interrupt Source 0 CRC_OK_CLR CRC_OK_EN 0 D Q CRC_OK_FLG 1 Packet OK Interrupt Source 0 PKT_DONE_CLR PKT_DONE_EN 0 D Q PKT_OK_FLG 1 Sleep Timeout Interrupt Source 0 SL_TMO_CLR SL_TMO_EN 0 D Q SL_TMO_FLG 1 Receive Timeout Interrupt Source 0 RX_TMO_CLR RX_TMO_EN 0 D Q RX_TMO_FLG 1 Transmit Done Interrupt Source 0 TX_DONE_CLR TX_DONE_EN 0 D Q RX_DONE_FLG 1 LBD Interrupt Source 0 RX_FIFO_NMTY_FLG RX_FIFO_TH_FLG RX_FIFO_FULL_FLG RX_FIFO_WBYTE_FLG RX_FIFO_OVF_FLG TX_FIFO_NMTY_FLG TX_FIFO_TH_FLG TX_FIFO_FULL_FLG STATE_IS_STBY STATE_IS_FS STATE_IS_RX LBD_CLR STATE_IS_TX 0 D Q LBD_FLG 1 RX_ACTIVE TX_ACTIVE TRX_ACTIVE INT1_CTL <4:0> 00000 0 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 0 INT_POLAR 0 INT1 1 Packet OK Interrupt Source Packet Err Interrupt Source Collision Err Interrupt Source PKT_DONE_CLR PKT_DONE_EN 0 D Q PKT_DONE_FLG 0 1 Figure 30. The CMT2300A INT1 Interrupt Map 5 Controller function Introduction GPO3_SEL <1:0> GPIO3 GPO2_SEL <1:0> GPIO2 GPO1_SEL <1:0> GPIO1 5.1 Cortex M0+ Core Function Description The ARM® Cortex®-M0+ processor is based on the Cortex-M0 and includes a 32-bit RISC processor with a computing power of 0.95 Dhrystone MIPS/MHz. At the same time, it is powered with a number of new designs, improved debugging and tracking capabilities, reducing the number of instruction cycles (IPC), improved two-stage pipeline for Flash access, etc. The Cortex-M0+ Rev. 0.9 | 50/65 www.cmostek.com CMT2380F32 processor fully supports the integrated Keil & IAR debugger. The Cortex-M0+ includes a hardware debug circuit that supports the 2-pin SWD debug interface. Table 31. ARM Cortex-M0+ Features CPU instruction set Assembly line Performance efficiency Performance efficiency Interrupt Interrupt priority Enhanced instruction Debugging Thumb/Thumb-2 2-stage pipeline 2.46CoreMark/ MHz 0.95 DMIPS/MHz in Dhrystone 32 fast interrupts Configurable 4-level interrupt priority Single cycle 32-bit multipliers Serial-wire debug port with 4 hard break points and 2 watch points Rev. 0.9 | 51/65 www.cmostek.com SWDI0 SWCLK CORTEX-M0 CPU Fmax=32MHz NVIC SWD P00,P01 P02,P03 P14 P15 P23,P24 P25,P26 P27 P31,P32 P33,P34 P35,P36 UART0_TXD UART0_RXD UART1_TXD UART1_RXD UART2_TXD UART2_RXD VC0_OUT VCIN0VCIN7 VC1_OUT VCIN0VCIN7 ADC_RDY AIN0-AIN8 LVD_OUT LVDIN1/2/3 GPIO port0 GPIO port1 GPIO port2 GPIO port3 U AR T0 U AR T1 LPUART VC0 VC1 BGR Vref Temp sensor 12-bit ADC LVD @VDDA AHB Bus matirx Flash 16/32 KB SRAM 2/4KB System control CRC AHB to APB brige WDT Clock Trimming CMT2380F32 POWER VOLT.REG VDD to Vcore @VDD POR/BOR RCH RCL @VDDA XTL XTH @VDD RTC Ti me r0 Ti me r1 Ti me r2 LPTimer PCA Ti me r4 Ti me r5 Ti me r6 SPI I2C VDD=1.8 to 5.5v VSS VDDA VSSA VDD RESET XTLO XTLI XTHO XTHI RTC_1Hz TIM0_GATE TIM0_EXT TIM0_TOG TIM0_TOGN TIM1_GATE TIM1_EXT TIM1_TOG TIM1_TOGN TIM2_GATE TIM2_EXT TIM2_TOG TIM2_TOGN LPTIM_GATE LPTIM_EXT LPTIM_TOG LPTIM_TOGN PCA_ECI PCA_CH0 PCA_CH1 PCA_CH2 PCA_CH3 PCA_CH4 TIM4_CHA TIM4_CHB TIM5_CHA TIM5_CHB TIM6_CHA TIM6_CHB SPI_SCK SPI_CS SPI_MISO SPI_MOSI I2C_SDA I2C_SCL Figure 31. Controller Functional Block Diagram Rev. 0.9 | 52/65 www.cmostek.com CMT2380F32 5.2 Memory 5.2.1 On-chip Program Memory Flash It's powered by fully built-in 32kbytesflash controller remarkable for no external high voltage input required, programming with high voltage generated by fully built-in circuits and support of ISP, IAP, ICP functions. 5.2.2 On-chip Data Memory Flash 4 kbytes RAM data is retained in various ultra-low power modes desired by customer. With hardware parity bit, if the data is accidentally destroyed, the hardware circuit will generate an interrupt immediately when the data is read, which helps ensure system reliability. Rev. 0.9 | 53/65 www.cmostek.com 0xFFFF_FFFF Reserved 0xE010_0000 Cortex-M0+ Specific 0xE000_0000 Peripheral resource area 0x4002_1000 Reserved AHB 0x4002_0000 CMT2380F32 0x4002_0c00 PORT CTRL 0x4002_0900 CRC 0x4002_0800 Reserved 0x4002_0400 RAM CTRL 0x4002_0000 flash CTRL Reserved Reserved Reserved 0x4000_4000 0x4000_0000 Peripheral resource area 0x2000_1000 Reserved SRAM 0x2000_0000 up t o 4KByt e) Main flash Reserved area 0x0000_8000 (32 k Main flash area Byte) (Up to 32KByte) 0x0000_0000 0x4000_3C00 Reserved 0x4000_3800 TIM6 0x4000_3400 TIM5 0x4000_3000 TIM4 0x4000_2C00 Reserved 0x4000_2800 Reserved 0x4000_2400 analog_ctrl 0x4000_2000 System_ctrl 0x4000_1C00 Reserved 0x4000_1800 CLKTRIM 0x4000_1400 RTC 0x4000_1000 PCA 0x4000_0C00 TIM 0x4000_0800 SPI 0x4000_0400 I2C 0x4000_0000 UART Figure 32. Memory Section Mapping Rev. 0.9 | 54/65 www.cmostek.com CMT2380F32 5.3 System Clock 1 high-precision internal clock RCH with a configurable frequency of 4~24MHz. The wake-up time from low-power mode to operating mode is 3 us at 16MHz configuration. Frequency tolerance over full temperature and voltage range is less than ±2.5%. No external expensive high-frequency crystal is required. 1 external crystal oscillator XTH with a frequency range of 4~32MHz. 1 external crystal oscillator XTL with a frequency of 32.768 kHz. 1 internal clock RCL with frequencies of 32.768/38.4 kHz. 5.4 Operating Mode Active mode Both CPU and the peripheral function modules are running. Sleep mode CPU stops running and the peripheral function modules are running. Deep sleep mode CPU stops running, the high-speed clock stops running, and the low-power function module is running. 5.5 RTC Hardware Real Time Clock RTC RTC (real time counter) is a register supporting BCD data, which uses a 32,768 Hz crystal oscillator as its clock to implement the perpetual calendar function. It supports interrupt period setting as year/month/day/hour/minute/second, 24/12 hour mode, automatic leap year calibration by hardware, precision compensation and the highest precision reaching 0.96ppm. The internal temperature sensor or external temperature sensor can be used for accuracy compensation. It supports adjusting the year/month/day/hour/minute/second by +1/-1 operation via software with a minimum adjustable precision of 1 second. When the MCU is reset caused by external factors, the RTC calendar recorder which indicates the time and date, does not clear the reserved value, which makes it the best choice for measuring instrumentation with the requirement of permanent high-precision and real-time clock. 5.6 General Purpose IO Port Up to 16 GPIO ports are available with some of them multiplexed with analog ports. Each port is controlled by an independent control register bit. It supports both edge-triggered interrupts and level-triggered interrupts, which wake up the MCU to operating mode from various ultra-low power modes. It supports both Push-Pull CMOS output and Open-Drain output. Built-in pull-up resistor, pull-down resistor and the function of Schmitt trigger input filtering are available. The output drive capability is configurable with up to 12mA of current drive capability. 16 general purpose IOs support external asynchronous interrupts. 5.7 Interrupt Controller The Cortex-M0+ processor provides a built-in Nested Vectored Interrupt Controller (NVIC) that supports up to 32 interrupt request (IRQ) inputs. It supports4 interrupt priorities to handle complex logic and enables real-time control and interrupt handling. The 32 interrupt entry vector addresses are listed in the below table. Rev. 0.9 | 55/65 www.cmostek.com Table 32. Interrupt Vector Address Table Interrupt Vector Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Interrupt Source GPIO_P0 GPIO_P1 GPIO_P2 GPIO_P3 UART0 UART1 UART2 SPI I2C Timer 0 Timer 1 Timer 2 LPTimer Timer 4 Timer 5 Timer 6 PCA WDT RTC ADC VC0 VC1 LVD RAM Flash fault Clock trim Rev. 0.9 | 56/65 CMT2380F32 www.cmostek.com CMT2380F32 5.8 Reset Controller This product has 7 reset signal sources. Each reset signal allows CPU resume to run, with most of the registers being reset and the program counter PC being reset and pointing to 00000000. Table 33. Reset Source Table No. Reset Source 0 Power-on and power-off reset POR BOR 1 External Reset Pin reset 2 WDT reset 3 PCA reset 4 Cortex-M0+ LOCKUP hardware reset 5 Cortex-M0+ SYSRESETREQ software reset 6 LVD reset 5.9 Timer/Counter Table 34. Timer Functionalities Table Function Category Timer Timer 0 Bit Width 16/32 Base timer Timer 1 16/32 LPTimer PCA Timer 2 LPTimer PCA 16/32 16 16 Timer 4 16 Advanced Timer 5 16 timer Timer 6 16 Pre-divided Frequency 1/2/4/8/16 32/64/256 1/2/4/8/16/ 32/64/256 1/2/4/8/16/ 32/64/256 NA 2/4/8/16/32 1/2/4/8/16/ 64/256/1024 1/2/4/8/16/ 64/256/1024 1/2/4/8/16/ 64/256/1024 Counting Direction Up-count PWM NA Capture NA Complementary O ut p ut NA Up-count NA NA NA Up-count NA NA NA Up-count NA NA NA Up-count 5 5 NA Up-count / down-count/ 2 2 1 up-down-count Up-count/ down-count/ 2 2 1 up-down-count Up-count/ down-count/ 2 2 1 up-down-count The Base Timer contains three timers, Timer 0/1/2, with the same functionality. Timer 0/1/2 is a synchronous timer/counter that can either be used as a 16-bit timer/counter with auto-reload function or as a 32-bit timer/counter with no auto-reload function. Timer 0/1/2 can count external pulses or perform system timing. Rev. 0.9 | 57/65 www.cmostek.com CMT2380F32 The LPTimer is an asynchronous 16-bit timer/counter that can still perform clock/count by internal low speed RC or external low speed crystal oscillator even the system clock is turned off. It provides the function to wake up the system in low power mode by interrupt as well. The PCA (programmable counter array) supports up to 5 16-bit capture/compare modules. The timer/counter can be used as the capture/compare function for general-purpose clock counter/event counter. Each module of the PCA can be independently programmed to provide input capture, output compare or pulse width modulation. In addition, module 4 supports an additional watchdog timer mode. The Advanced Timer consists of three timers, Timer 4/5/6, with the same functionalities, which are high-performance counters used to count different clock waveforms. Each timer can generate a pair of PWMs that complement each other or 2 separate PWM outputs that captures external inputs for pulse width or period measuring. The basic functions and features of the advanced timer are shown in the below table. Table 35. Advanced Timer Function Table Waveform mode Basic function Interrupt type Sawtooth wave, triangle wave Incrementing and decrementing counting directions Software synchronization Hardware synchronization Cache function Orthogonal coding count General purpose PWM output Protection mechanism AOS associated action Count comparison match interrupt Count cycle match interrupt Dead time error interrupt Short circuit monitoring interrupt 5.10 Watchdog WDT WDT (watch dog timer) is a configurable 20-bit timer that provides a reset in case of an MCU exception. A built-in 10k low-speed clock input is used as the counter clock. Users can choose to pause or keep it run in debug mode. WDT can be reset by writing a specific sequence. 5.11 Universal Purpose Asynchronous Receiver UART0, UART1 and LPUART 2 universal asynchronous receiver/transmitters One low power universal asynchronous receiver/transmitter available in low-power mode Rev. 0.9 | 58/65 www.cmostek.com CMT2380F32 5.12 Synchronous Serial Interface SPI One serial peripheral interface, supporting master-slave mode. 5.13 I2C Bus One I2C (inter-integrated circuit), supporting master-slave mode. With serial synchronous clock, data can be transmitted between devices at different rates. The serial 8-bit bidirectional data transmission can reach a maximum speed of 1Mbps. 5.14 Buzzer 3 base timers along with 1 LPTimer co-function to output buzzer providing programmable drive frequency for the buzzer. The buzzer port provides 16mA sink current, complementary output without additional transistors required. 5.15 Clock Calibration Circuit The built-in clock calibration circuit can be used to calibrate the internal RC clock with an external precision crystal oscillator. The internal RC clock can also be used to verify whether the external crystal clock is working properly. 5.16 Unique ID number Each chip has a unique 16-byte device identification number consisting of wafer lot information, chip coordinate information, etc. The ID address is 0X0010_0E70-0X0010_0E7F. 5.17 CRC16 Hardware Cyclic Redundancy Check Code It conforms to the polynomial given in ISO/IEC13239 :F(x) = X16 + X12 + X5 + 1. 5.18 12-bit SARADC The 12-bit successive approximation analog-to-digital converter, which is monotonous without loss of code, has a sampling rate of 1 Msps when operating with a 24M ADC clock. The reference voltage can be selected from the on-chip precision voltage (1.5V or 2.5V) or from an external input or supply voltage. The 12 input channels includes 9 external pin inputs, 1 internal temperature sensor voltage, one 1/3 supply voltage and 1 built-in BGR 1.2V voltage. A configurable input signal amplifier is built in to detect weak signals. 5.19 Voltage Comparator (VC) It's Chip pin voltage monitoring/comparison circuit. It provides 8 configurable positive/negative external input channels, 5 internal input channels including 1 internal temperature sensor voltage, 1 built-in BGR 2.5V reference voltage, 1 built-in BGR 1.2 V voltage and one 64-step resistor Partial pressure. The VC output can be used by Timer0/1/2, LPTimer, Advanced Timer, PCA capture with programmable count array, gating, and external count clocks. An asynchronous interrupt can be generated based on the rising/falling edge to wake up the MCU from low power mode. It supports configurable software anti-shake function as well. 5.20 LVD Low Voltage Detector (LVD) It detects the chip supply voltage or chip pin voltage with sixteen levels of voltage monitoring values (1.8 ~ 3.3 V). An asynchronous interrupt or reset can be generated based on the rising/falling edge. It provides hardware hysteresis circuit and Rev. 0.9 | 59/65 www.cmostek.com CMT2380F32 configurable software anti-shake function. 5.21 Embedded Debug System The embedded debugging solution provides a full-featured real-time debugger co-working with sophisticated debugging software such as Keil and IAR. It supports for 4 hard breakpoints and multiple soft breakpoints. 5.22 High Security It's powered with encrypted embedded debugging solution providing full-featured real-time debugger. Please refer to AN220 CMT2380F32 User's Manual (Microcontroller Section) for detailed instructions on using the CMT2380F32 microcontroller. Rev. 0.9 | 60/65 www.cmostek.com CMT2380F32 6 Order Information Table 36. The CMT2380F32 Order Information Model CMT2380F32-EQR[1] Description Packaging The CMT2380F32 ultra-low QFN40(5x5) power sub-1GHz wireless MCU Packaging Option Tape and tray Operating Condition 1.8 to 3.6 V, - 40 to 85 °C Minimum Order Quantity 3,000 Notes: [1]. E refers to extended Industrial product rating, which supports temperature range from -40 to +85 °C. Q refers to the package type QFN40. R refers to tape and tray type, and the minimum order quantity (MOQ) is 3,000 pieces. Please visit www.cmostek.com for more product/product line information. Please contact sales@cmostek.comor your local sales representative for sales or pricing requirements. Rev. 0.9 | 61/65 www.cmostek.com 7 Packaging Information The packaging information of the CMT2380F32 is shown in the below figure. D b 40 1 2 CMT2380F32 e 40 L 1 2 D2 Ne E2 E Top View K EXPOSED THERMAL PAD ZONE Nd Bottom View A A1 c Side View Figure 33. QFN405x5 Packaging Symbol A A1 b b1 C D D2 e Ne Nd E E2 L L1 K h Table 37. QFN405x5 Packaging Scale Min. Scale (mm) MaximumTyp. 0.70 0.75 0 0.02 0.15 0.20 0.14REF 0.18 0.20 4.90 5.00 3.60 3.70 0.40 BSC 3.60 BSC 3.60 BSC 4.90 5.00 3.60 3.70 0.35 0.40 0.10REF 0.20 - 0.30 0.35 Rev. 0.9 | 62/65 Max. 0.80 0.05 0.25 0.25 5.10 3.80 5.10 3.80 0.45 0.40 www.cmostek.com 8 Top Marking CMT2380F32 2380F32 E 9 Y WW Figure 34. The CMT2380F32 Top Marking Table 38. The CMT2380F32 Top Marking Information Marking Method Laser Pin 1 Mark Diameter of the circle = 0.3 mm Font Size 0.5 mm, align right Line 1 Marking 2380F32 referring to model CMT2380F32 Line 2 Marking Line 3 Marking E9 is internal tracing code The date code is assigned by the package factory. Y is the last digit of the year. WW is the working week. Rev. 0.9 | 63/65 www.cmostek.com CMT2380F32 9 Reference Documents Doc No. AN141 AN142 AN143 AN144 AN146 AN147 AN149 AN150 AN197 AN198 AN199 AN220 Table 39. Reference Documents Name CMT2300A Schematic and PCB Layout Guide CMT2300A Quick Start Guide CMT2300A FIFO and Packet Format Usage Guide CMT2300A RSSI User Guide CMT2300A Low Power Mode User Guide CMT2300A Features Usage Guide CMT2300A RF Parameter Configuration Guide CMT2300A Low Voltage Transmit Power Compensation CMT2300A-CMT2119B-CMT2219B Fast Manual Frequency Hopping CMT2300A-CMT2119B-CMT2219B Status Switching Precautions CMT2300A-CMT2119B-CMT2219B RF Frequency Calculation Guide CMT2380F32 User Manual (Microcontroller Section) Description CMT2380F32 RF matching design guidelines CMT2380F32 RF quick start CMT2380F32 RF transceiver message usage guide CMT2380F32 RF RSSI user guide CMT2380F32 RF Low power design guidelines CMT2380F32 RF features description CMT2380F32 RF Frequency matching parameters CMT2380F32 RF Low-voltage transmit power compensation instructions CMT2380F32 fast manual frequency hopping instructions CMT2380F32 RF status switching considerations CMT2380F32 RF frequency calculation instructions CMT2380F32 controller detailed instructions 10 Revise History Version No. 0.8 0.9 Chapter All 7 Table 40. Revise History Records Description Initial version Packaging diagram update Date 2018-04-22 2018-05-09 Rev. 0.9 | 64/65 www.cmostek.com CMT2380F32 11 Contacts CMOSTEK Microelectronics Co., Ltd. Shenzhen Branch Address: 2/F Building 3, Pingshan Private Enterprise S.T. Park, Xili, Nanshan District, Shenzhen, Guangdong, China Tel: Post Code: Sales: Supports: Website: +86-755-83231427 518057 sales@cmostek.com support@cmostek.com www.cmostek.com Copyright. CMOSTEK Microelectronics Co., Ltd. All rights are reserved. The information furnished by CMOSTEK is believed to be accurate and reliable. However, no responsibility is assumed for inaccuracies and specifications within this document are subject to change without notice. The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK. The CMOSTEK logo is a registered trademark of CMOSTEK Microelectronics Co., Ltd. All other names are the property of their respective owners. Rev. 0.9 | 65/65 www.cmostek.comMicrosoft Word 2013