7f313f714386c8343d4ddc865daa452d0bff69109a21439211a6d4de50476dae
SY27-2521-3 8130 8140 8101 Maintenance Information Volume 4 =-===-== - -- --_ -- --- _,_
------ -- - - - · - Maintenance Library
This edition includes REA 06-88481.
-----~ -~ ~ --- ------- ----~ -~ -----------~ ~ ----- Information System
== =-= = -= - --- - -- - - - = == == = --- -
=~ _-== =_ '=_-=-El=?-' ==_===:.=::: =~ _ -==: - =: - ==== -~= =-
Processors
=-~ --=-=--==-==---==--=-=
w
Storage and Input/Output Unit
Maintenance Information
(Volume 4 of 4)
SY27-2521-3
The following listing shows, by volume (binder) number, the basic contents of the 8100 Information System Maintenance Information Manual. The column not shaded indicates the volume you are using; the shaded columns indicate the contents of the other three volumes.
SY27-2521-3
ii
Volume 4 (Binder 4)
Disk Storage (FA) FA 100 General Information FA200 Offline Tests FA300 Intermittent Failure Repair Strategy FA400 Signal Paths and Detailed Operational Description FA500 Adjustment, Removal, and Replacement
Information
Power (PA) PA 100 General Information PA200 Offline Tests PA300 Intermittent Failure Repair Strategy PA400 Signal Paths and Detailed Operational Description PA500 Adjustment, Removal, and Replacement
Information PA600 Service Checks PA700 Locations
System Control Facility (SC) SC100 General Information SC200 Offline Tests SC300 Intermittent Failure Repair Strategy SC400 Signal Paths and Detailed Operational Description SC500 SCF System Test and Internal 1/0 Bus Cable
Change Procedures
Expanded Function Panel (SP) SP100 General Information SP200 Offline Tests SP300 Intermittent Failure Repair Strategy SP400 Signal Paths and Detailed Operational Description SP500 Adjustment, Removal, and Replacement
Information
Magnetic Tape Adapter (TA) TA 100 General Information TA200 Offline and Online Tests TA300 Intermittent Failure Repair Strategy TA400 Signal Paths and Detailed Operational Description TA500 Console Messages
Appendix A. Hexadecimal-to-Binary Conversion
Chapter 5. MAP Reference Information Disk Storage
(FA)
SY27·2521 ·3
5-FA·i
Introduction
This part of Chapter 5 provides maintenance information needed to service the disk storage unit in the 8130, 8140, or 8101. When used with the MAP Maintenance Package, the FA MAP diagnoses disk storage problems and refers you to this part of Chapter 5 for information such as hardware locations, actions, and wiring checks.
This part also contains maintenance information and action plans for diagnosing intermittent problems not found with the MAPs.
This part has five sections: 1. General Information (FA 100-FA131) - Contains information on FA configuration,
theory of operation, and repair strategy. 2. Offline Tests (FA200-FA250) - Contains disk storage test information, error
messages, and actions. 3. Intermittent Failure Repair Strategy, (FA300-FA350) - Contains System Error
Log information that you use to service intermittent failures. 4. Signal Paths and Detailed Operational Description (FA400-FA452) - Contains signal
path diagrams, wiring and signal paths, and net lists. 5. Adjustment, Removal, and Replacement Information (FA500-FA590} - Contains
disk storage service checks, and adjustment, removal, and replacement procedures.
SY27-2521-3
Contents
5-FA-ii
FA100 General Information · · · · · . · · · . · . . · · · . . . · . · · · · · · . · · · · · · FA110 Components and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FA111 Hardware Components . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . Disk Storage Adapter Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disk Storage Drive (DSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FA112 Addressing . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA113 Configuration Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA120 Basic Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA130 DSD Unique Repair Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA131 Disk Storage Unique Intermittent Repair Strategy . . . . . . . . . . . .
5-FA-1 5·F A-2 5·F A-2 5-FA-2 5-FA-4 5-FA-5 5-FA-5 5-F A·6 5-FA-8 5-FA-8
FA200 Offline Tests . . · . · · · · · · . . · . . · . . . · . · · . . . . . · . . · . . · . . · · FA210 Offline Test Routine Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
FA211 Adapter Logic Offline Test Routine Descriptions . . . . . . . . . . . . . FA212 Disk Drive Offline Test Routine Descriptions. . . . . . . . . . . . . . . . FA220 Not Used FA230 Test Message Formats and Status Information . . . . . . . . . . . . . . . . . FA231 Offline Adapter Test Message Formats . . . . . . . . . . . . . . . . . . . . FA232 Drive Test Message Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . FA233 Status and Sense Byte Formats . . . . . . . . . . . . . . . . . . . . . . . . .
File Status (FS) Byte (Tag 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Sense (AF) Byte 1 (Tag 101) and File Pulsing (AP} Byte 1 . . . . . . . File Sense (BF) Byte 2 (Tag 110} and File Pulsing (BP} Byte 2 . . . . . . . File Sense (CF) Byte 3(Tag111) and File Pulsing (CP) Byte 3 ....... Seek Status (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FCB Processor Extended Status (FE) . . . . . . . . . . . . . . . . . . . . . . . . Data Handler Basic Status (HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adapter Basic Status (BS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Handler Extended Status (HE) . . . . . . . . . . . . . . . . . . . . . . . . . FA240 Test Message, Error Number Descriptions, and Actions . . . . . . . . . . . FA241 Common Test Error Messages and Actions . . . . . . . . . . . . . . . . . FA242 Adapter Test Messages, Error Numbers, and Actions . . . . . . . . . . . FA243 Disk Logic Test Messages, Error Numbers, and Possible Causes . . . . FA250 Action Plan . . . . . . · . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . .
5-FA-9 5-FA-9 5-FA-10 5-FA-11
5-FA-13 5-FA-13 5-FA-13 5-F A-13 5-FA-13 5-FA-14 5-FA-15 5-FA-15 5-FA-16 5-FA-16 5-FA-17 5-FA-17 5-FA-17.1 5-FA-18 5-FA-19 5-F A-20 5-FA-22 5-F A·34
FA300 Intermittent Failure Repair Strategy . . · . . . · . . · . · . . . · . · . . . . . FA310 Adapter-Unique Intermittent Repair Strategy . . . . . . . . . . . . . . . . .
FA311 Looping with MAP Interaction to Determine Failures . . . . . . . . . . FA312 Using the System Error Log to Determine Failures . . . . . . . . . . . . FA313 Using the Free-Lance Utility to Determine Failures. . . . . . . . . . . . FA320 Not Used FA330 Error Log Formats and Meanings Used for the FA MAP. . . . . . . . . . . FA331 DPPX Error Log Formats and Meanings . . . . . . . . . . . . . . . . . . . FA332 DPCX Condition/Incident Log Formats and Meanings . . . . . . . . . . FA340 How to Use the Error Log . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . FA341 Using the DPPX Error Log . . . . . . . . . . . . . . . . . . . . . . . · . . . . FA342 Using the DPCX Condition/Incident Log . . . . . . . . . . . . . . . . . . FA350 Action Plan to Correct Intermittent Failures . . . . . . . . . . . . . . . . . .
5-FA·35 5-FA-35 5-FA-35 5-FA-35 5-FA-35
5-FA-35 5-FA-35 5-FA-38 5-FA-40 5-FA-40 5-FA-40 5-FA-40.1
FA400 Signal Paths and Detailed Operational Description ············.· 5-FA-41 FA410 Card Socket Wiring Charts ...·.··...··....·····.··...... 5-FA-41
FA1 FCB Processor Card . . . . . . . · · · . · . . . . . . . . . . . . . . · . . . . . . . 5-FA-41 FA2 Data Handler Card . . . . . . . · · . . · . . . . . . · · . . . . . · . . . . . . . . . 5-FA-41 FA3 Data Channel Card . . . . . . · · . . · . . . . · . . . . . · . . . · . . . · . . . . . 5-FA-42
FA4 Logic Card 1 . . . . . . . . . . · . . . . . . . . . . . . . . . . . . · . . . . . . . . .
FA5 Logic Card 2 . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . .
FA6 Servo Card 1 . · . . · . · . . . · . · . . · . . · . . . . . . . . . . . . · . . . . . . . FA7 Servo Card 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . _. . . . . . . . . . . FAS Voice Coil Motor (VCM) Drive Card · . . . . . . . . . . . . . . . . . . . . . . .
5-FA-42 5-FA-43 5-FA-43 5-FA-44 5-FA-44
FA9 Terminator Card.·.···.····..·.............··....·... Adapter to Drive Cables, (CC) and (DD) . . . . . . . . . . . . . . · . . . · . . . . . Drive Logic Board to DE Cables, (FA) and (MH) . . . . . . . . . . . . . . . · . . .
Top Card Connectors W, X, Y, and Z . . . . . . . . . . . . . . . . . . . . . . . . . .
5-FA-44 5-FA-45 5-FA-46 5-FA47
FA420 Adapter to Disk Drive Interface Description .................. . 5-FA-48
Control Bus (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-FA-48
Dedicated Cable (DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-FA48
Output Lines from DSD to System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-FA48
Individual Cabling Via Voltage Crossovers . . . . · . . . . . . . . . . . . . . . . . . . 5-FA49 FA430 Not Used
FA440 Jumpers ..........·............................... 5-FA-49 FA441 Board Jumpers ................................... . 5-FA-49 FA442 FA4 Logic Card 1 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-FA-49
FA443 FA5 Logic Card 2 Jumpers . . . . . . . . . . . . . . . . . . . . ....... . 5-FA-50
FA444 FA6 Servo Card 1 Jumpers · . . . . . . . . . . . . . . . . . . . . . . . . . . . FA450 Detailed Data Flow and Operational Theory . . . . . . . . . . . . . . . . . .
FA451 Data Flow Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA452 Detailed Operational Theory ·.........................
5-FA-50
5-FA-51 5-FA-51 5-FA-55
File Adapter ....................................... . 5-FA-55 Disk Enclosure (OE) .·.....·......... , ................ . 5-FA-55
Spindle/Brake ......·................................ 5-FA-56 Actuator .............·.·............·...·.·...·.... 5-FA-56
Read/Write Components ....·..........·.........·.....· 5-FA-56 DSD Data Formatting . . . . . . . . · . . . . . . . . · . . . . . . . · . . . . . . . . 5-FA-56
Seek . . . . . . . . . . . . . . . . . . · . . . . · . . . · . . . · . · . · . · . . . . . . . . 5-FA-59 Read/Write . . . . . . . . . . . . . . . . . · . . . . . . . . · . · . . . · . . . . . . . . 5-FA-60
Power Sequencing . . . . . . . . . . . . . . . . . . . . · . . . · . · . . . . . . . . . . 5-FA-62 Signal Bus Descriptions . . . . . · . . . . . . . . . . . . . . . . . . · . . . . . . . . 5-FA-63
Phase-Locked Oscillator (PLO) Loop . · · · . . . · . . . · . . . . . . . . . . . . 5-FA-64
Voltage Controller Oscillator (VCO) Control ·.·.·.·.·.·........
Recalibrate Issued by Processor or Storage and 1/0 Unit . . . . . . . . . . .
Access and Head Change . . · . · . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Safety Detection . . . · . . . . . . . . . . . . . ............... .
5-FA-65 5-FA-65 5-FA-66 5-FA-67
Sense/Status Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-FA-68
FA500 Adjustment, Removal, and Replacement Information ····...····· FA510 Scope Charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scope Chart 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Chart 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Chart 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Chart 4 . . . . . . . · . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . Scope Chart 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Chart 6 . . . . . . . . . . . . . . . ......................... .
Scope Chart 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-FA-69 5-FA-69 5-FA-69 5-FA-69 5-FA-69 5-FA-69 5-FA-70 5-FA-70 5-FA-70
Figures
SY27-2521-3
Scope Chart 8 . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Chart 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Chart 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA520 Adapter and DSD Cable and Card Continuity . . . . . . . . . . . . . . . . . FA521 Data Select Gate Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . FA522 Disk Adapter to DSD Continuity. . . . . . . . . . . . . . . . . . . . . . . . FA530 Not Used FA540 Disk Enclosure (OE) Removal and Replacement. . . . . . . . . . . . . . . . FA541 Shock Mount Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA550 Card Gate, Board, and VCM Driver Card Removal/Replacement . . . . . FA551 Card Gate Removal/Replacement . . . . . . . . . . . . . . . . . . . . . . . FA552 Board Removal/Replacement . . . . . . . . . . . . . . ~. . . . . . . . . . . FA553 Voice Coil Motor (VCM) Driver Card Removal/Replacement . . . . . FA560 Card Gate Fan Removal/Replacement . . . . . . . . . . . . . . . . . . . . . . FA570 Drive Motor and Drive Belt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA571 Drive Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drive Motor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive Motor Assembly Removal/Replacement . . . . . . . . . . . . . . . . . . FA572 Drive Belt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive Belt Tensioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive Belt Removal/Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . Antistatic Brushes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA580 Brake Assembly and Coil Removal, Adjustment, and Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FA590 Actuator Lock Knob and Lock/Operate Switch Adjustment . . . . . . . . Actuator Lock Lever Cable Adjustment . . . . . . . . . . . . . . . . . . . . . · . . Lock/Operate Switch Adjustment . . . . . . . . . . . . . . · . . . . . . . . . . · . ·
5-FA-70 5-FA-70 5-FA-70 5-FA-71 5-FA-71 5-FA-71
5-FA-72 5-FA-74 5-FA-75 5-FA-75 5-FA-76 5-FA-76 5-FA-76 5-FA-77 5-FA-77 5-FA-77 5-FA-78 5-FA-79 5-FA-79 5-FA-79 5-FA-79
5-F A-80 5-F A-81 5-FA-81 5-F A-81
FA 100-1. FA111-1. FA111-2. FA111-3. FA1114. FA111-5. FA111-6. FA120-1. FA240-1. FA451-1. FA451-2. FA451-3. FA451-4. FA452-1. FA452-2. FA452-3. FA452-4. FA452-5. FA452-6. FA452-7. FA452-8. FA452-9.
Disk Storage Drive Basic Diagram .···.·.·.·..·.·.·.·..· 5-FA-1 8130 Processor Adapter Card Locations. · · · . · · · . . . · · · . · · · 5-FA-2 8140 Processor Model AXX Adapter Card Locations ··.·.···· 5-FA-3 8140 Processor Model BXX Adapter Card Locations .·.·.···· 5-FA.J
8101 Storage and 1/0 Unit Card Locations ··.··...···..··· 5-FA-3
Disk Storage Drive ··..·.·.······.········.·.······ 5-FA4 Disk Storage Drive Logic Board and Card Gate .···.·.···.·· 5-FA-5 Data Flow in the Disk Storage Adapter and the DSD . . . . . . . . . . 5-FA-7 Pseudo Card and Cable Locations . . . . . . . . . . . . . . . . . . . . . 5-FA-18 Adapter Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . · 5-FA-51 Data Flow Diagram, Seek Operation . . . . . . . . . . . . . . . . . . . . 5-FA-52 Data Flow Diagram, Read/Write Operation ............... 5-FA-53 Data Flow Diagram, Error Detection and Safety Circuits ...... 5-FA-54 Disk Configurations ..... , .....................·.. 5-FA-55 Actuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · 5-FA-56 Data Surface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . 5-FA-57 Servo Surface . . . .... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-F A-57 Sector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . 5-FA-57 Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . 5-FA-58 Spiraling ·..................................... 5-FA-59 Example of Defective Sector Reassignment . . . . . . . . . . . . . . . 5-FA-59 Sector Scan . . . · · . · . . . . . . . . · . · . . . . . . . . . . . . . . . . . . 5-FA-61
5-FA-iii
FA452-10. FA452-11. FA452-12. FA452-13. FA452-14. FA452-15. FA452-16. FA452-17. FA452-18. FA452-19. FA541-1. FA541-2. FA541-3.
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-FA-62 Power-On Logic Sequence Timing . . . . . . . - - .......... . 5-FA-63 PLO Data Flow. . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-FA-64 PLO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ 5-FA-65 VCO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-FA-65 Recalibration Timing Chart . . . . . . . . . . . . . . . . . . . . . . . .. 5-FA-66 Access and Head Change Timing Chart . . . . . . . . . . . . . . . . . . 5-FA-66 Write Safety Detection Circuits ...................... . 5-FA-67 Transient Blanking Timing ......·................... 5-FA-67 Sense/Status Timing Chart . . . . . . . . · . . . . . . . . . . . . . . . . . 5-FA-68 Type A Shock Mount . . . · . . . . . . . . . . . . . . . . . . . ·....· 5-FA-74 Type B Shock Mount . . . . . . . . . . . . . . . · . . . . . . . ..... . 5-FA-74 Type B Shock Mount Access . . . . . . . . . . . . . . . . . . . . . . . .. 5-FA-74
SY27-2521-3
Abbreviations
ADWA AGC ARC CA (CC) CHCV CHIO CIL CNT COMPSTAT CPR CRC (DD)
DE DH
DPCX DPPX
DSD
OT
ECC FAX
adapter work area address automatic gain control adapter return code channel address pseudo for control cable channel control vector channel input output condition/incident log count completion status channel pointer register cyclic redundancy check pseudo for dedicated cable disk enclosure data handler Distributed Processing Control Executive Distributed Processing Programming Executive disk storage drive device type error correction code pseudo for disk storage card type
FCB FDM (FH) FRU FRWA GFI ID
1/0
IOEP LV MAP MD (MH) Ml OP PA PCI PES PIO PLO RES R/W rws SCA SCF
sex
SEQ NO TCC TCM UT VCM
w x
y
z
function control block function definition module pseudo for fixed head cable field replaceable unit function request work area address General Failure Index identification
input/output
1/0 interrupt entry point
level Maintenance Analysis Procedure Maintenance Device pseudo for moving head cable manual intervention option physical address program-controlled interrupt position error signals
programmed 1/0
phase locked oscillator reserved read/write read write storage secondary component address System Control Facility pseudo for system control facility card type sequence number top card connector test control monitor unit type voice coil motor pseudo for top card connector row 2 pseudo for top card connector row 3 pseudo for top card connector row 4 pseudo for top card connector row 5
S·FA-iv
FA100 General Information
The 8100 system disk storage drive (Figure FA100-1) consists of a disk enclosure (DE), a drive motor, and a card gate mounted on a subframe. The DE consists of a seated unit that houses the disks, the access mechanism, and some associated electronics. Three shock mounts inside the 8100 system units fasten the disk drive subframe to the 8130, 8140, or 8101 frame; the frame supplies ac and de power.
The DE uses either three or six disks stacked on a spindle, and resides within the frame in a horizontal position. These disks rotate at 3125 rpm and provide a 27-ms average access time. The DE provides various byte capacities by using a combination of fixed and movable heads. The DE has a filtered closed air circulation system to prevent read/write head contamination. A voice coil motor controls a pivoted arm actuator that allows read/write heads to be attached.
The DE cannot be repaired in the field, and must be replaced as a FRU. Defective DEs must be returned to the plant of manufacture with the cover seal intact to obtain the maximum credit value.
Subframe
Card Gate
Mounting Lugs (for shock mounts)
The following 8100 Information System units contain the disk storage drive (DSD) and adapter: · IBM 8130 Processor, Models A21-A24.
· IBM 8140 Processor, Models A31-A34, A41-A44, A51-A54, 851, B52, B61, 862, B71, and B72.
· IBM 8101 Storage and Input Output Unit, Models A11, A13, A23, and A25.
Disk storage is available in four configurations giving a storage capacity range from 23 to 64 million bytes of data, as follows:
Model* Disk Elements Moving Head Capacity Fixed Head Capacity
Ax1
3
29, 32.7, 360 bytes
Ax2
3
23, 461, 888 bytes
Ax3
6
64, 520, 192 bytes
Ax4
6
58, 654, 720 bytes
Ax5
6 (2 units)
64, 520, 192 bytes
*x = 1, 2, 3, 4, or 5. There is no model A12 or A14.
0 131,072
0 131,072
0
Model* Bx1 Bx2
·x = 5, 6, 7
Disk Elements Moving Head Capacity
6 6 (lower) 6 (upper)
58, 654, 720 bytes 58, 654, 720 bytes 64, 520, 192 bytes
Fixed Head Capacity
131,072 131,072
0
Actuator Coil Driver Card -----tt----.
Figure FA100-1. Disk Storage Drive Basic Diagram
Drive Motor
Disk Enclosure (DE) Sealed Plastic Cover The inside of the DE is not accessible to the CE.
SY27-2521-3
(FA100)
5-FA-1
FA110 Components and Addressing
FA 111 Hardware Components
Disk storage consists of two disk storage adapter cards that attach to the PIO bus and a disk storage drive (DSD).
Disk Storage Adapter Cards
Two logic cards attach the DSD to the processor through the SC card and the System Control Facility (SCF) bus. These cards plug into the 8130 A1 board, the 8140 A2 or 82 board, and the 8101 A2 board. Connections between the cards are through top card connectors (TCC) W, X, Y, Zand board wiring. Connections between the adapter cards and the DE are through the control cable (CC) and the dedicated cable (DD). See Figures FA111-1 through FA1114 for the locations of these cards and cables. The cards are:
· FA1 card - Function Control Block (FCB) Processor
· FA2 card - Data Handler (DH)
SY27-2521·3
Board 01A-A1
ll Control Cable (CC) to Drive ll
ll
Dedicated Cable (DD) to Drive
n
YJ
II
vs
V6
II II
0
,...-- ,__, .---. .--, ,--, ,--, .-- r-- ..--- ,.........., r - r-- ,....-- r-- ,.... ,.... ,.... r - r-- r -
Adapter Cards TCC
y
Notes:
1. 04 and 31 pins are ground.
z
2 TCC W, X, Y, and Z are interchangeable with
each other, but are not n1eessarily interchangeable
with those of other adapters. For part numbers, refer
to Chapter 3, Figures L T140-1, L T140-2, L T240-1,
L T240-2, L T240-3, L T240-4, and L T340-1.
2
l
13
2
l G and J ,. Socket 13
2
l
MandP Socket
13
2
t Sand U Socket 13
__ .....__. L.......,,j
....__. " - - ...._. .................................... L....... ...................... .___ ......................
Z1
Z2
Zl
Z4
Zb
26
II
II
II
II
II
..-- ..---
II
--
YJ
Y4
YS
Y6
II II II II
0
r-- r - r-- ..--- ,...-- r-- r - r - r - ,.... r-- ,.... ,.....- ..... ,.....-
SC
~-I ..__I_l.___I____.I.___!~l..._I____.I .__I_ _
Figure FA111-1. 8130 Processor Adapter Card Locations
5-FA-2
Board 01 A·A2
'E
'E
IU
0
l3
:I: Q
0 m 0
LL.
(I)
N <(
u..
<
LL.
.."O
IU
0 :I: 0
'E
«I
0 m
0u..
< N
c(
u.. u..
Dedicated Cable (DD) to Driw
Control Cable {CC) to Drive
-
........... ...........
--
Dedicated Cable {DD) to Drive
Control Cable (CC) to Drive
Models
Laations*
SC
FA1
FA2
{CC)
(DD)
A3X/A4X A5X
A2D2 A2D2
A2Q2 A2F2
A2P2 A2E2
A2Z6 A2Z3
A2Z5 A2z2·
Figura FA111-2. 8140 Processor Model AXX Adapter Card Locations
Board 01 A-82
Control Cable (CC) to Upper Drive
Board 01 A-A2
Control Cable (CC) to Upper Drive
Control Cable (CC) to Lower Drive
Cables to SC Card Located in 01A-A2A2
;:
...
aaCl..l
2
i:
!a.. 2
Cl)
~ 0
.:!
j
0 ..J
"E
IU
0 m C.J
LL
'E
«I
0 :I: Q
'E
IU
0
ca
C.J
LL
a'E
:I: 0
< N <(
:(
LL LI- u.
N c(
u.
Control Cable (CC) to Lower Drive
m:"I'
0
a:
e0 n
Dedicated Cable (DD) to Lower Drive
-.:
aaCl)..
2
"a.O..
m uC...J
...
aaCl)..
2 'E
IU
0 :I: 0
:(
N <(
u. u.
-...
Cll
...
~ 0
Cl)
~
.:!
0 ..J
... 'E
IU
0
"O
ca
m 0
uC..J
:I: Q
< N
u.
<(
u.
Dedicated Cable (DD) to Upper Drive
Figure FA111-3. 8140 Processor Model BXX Adapter Card Locations
Dedicated Cable (DD) to Upper Drive
Dedicated Cable (DD) to Lower Drive
Figure FA111-4. 8101 Storage and 1/0 Unit Card Locations
SY27-2521-3
(FA110, FA111)
5-FA-3
Disk Storage Drive (DSD)
SY27-2521-3
The DSD (Figure FA111-5) includes:
· Disk Enclosure (DE) - The actual storage device that contains the disks, R/W heads, and the access mechanism.
· Disk electronics - Six circuit cards plugged in the 01X-A1 board, that is hingemounted on the DSD subframe, and one circuit card that is mounted on the card gate. The cards on the A 1 board (Figure FA111-5 and FA111-6) are:
FA3 card - Data channel card
FA4 card - Logic 1 card
Drive Belt
FA5 card - Logic 2 card
FA6 card - Servo 1 card
FA7 card - Servo 2 card
FAS card - Voice coil motor (VCM) driver card. (Mounted on the card gate)
Belt Tensioner
FA9 card - Terminator card
Base Cesting The DE is assembled on this
Disk Enclosure (DE) DSD Subframe
Upper Shock Mount
Motor Lock
Spindle Brake Assembly The brake is applied when the ---------l!!!:-------....:::...~:--~~~""'-7"'":d'--:~~h-' power is off.
Drive Motor (50 or 60 Hz) A thermal cutout is fitted to 'sense' overheating. To reset the cutout, press the Thermal Reset Button.
Drive Motor Mounting Bracket Drive Motor
Figure FA111-5. Disk Storage Drive
Pivot of Drive Motor Mounting Bracket
Lower Shock Mount This shock mount is attached te; the subframe and bolts onto a frame in the using system or unit.
5-FA-4
Pulley The direction of rotation is shown by the arrow on the belt guard.
Caution: The heads on the actuator end the dilks might be damaged if the DE pulley Is turned counterclockwise.
Disk Electronics
Card Gate Assembly 01X·A1
Card Position
.Card Name
A 1·FA8
VCM Driver
A1-B2 (FA3)
Data Channel
A1-C2 (FA4)
Logic 1
A1·D2 (FAS)
Logic 2
A 1-E2 (FAS)
Servo 1
A1-F2(FA7)
Servo2
A 1-A4 (FA9)
Terminator
Cable Position A1-Y1 (FH) ~1-A2 (MH) A1-A3 (CC) A1-A5 (DD)
Cable Name Fixed Heads Moving Heads Control Cable Dedicated Cable
Card Size
4W,2H 4W,3H 4W,3H 2W,3H 4W,3H 1W, 1H
Belt Guard
Switching Relay Cooling Fan
Actuator Lock Knob This is on the DE casting below the gate.
Caution: The Lock/Operate Lever must be in the locked position when removing the disk enclosure (DE), or when moving the unit that houses the DE. (See FA540)
Board 01X-A1 I
~
~
To DE (For fixed heads only) (FH)
Spare
Y1
Y2
A
B c
D
E
F
l
(MH) to DE
2 2
Qcci sI:V.
(.)
·ug
.I.V..
IV
...J
v
0
<(
M
LL
<(
N
N
u "iii 0 ...J ID <(
u.
0 ~
eInD
.>0..
~
«>
<(
......
<(
LL
LL
~
d
:E
(.)
>
(CC) From
LL
co
<(
Adapter
LL
2
FA9
f
IV
eQn .
(DD) From Adapter
Z1
Z2
Spare
I I Spare
Figure FA111-6. Disk Storage Drive Logic Board and Card Gate
FA 112 Addressing
The only software addressing needed for the DSD is the physical address (PA) of the adapter cards. No logical address (LA) is necessary since only one device can be attached to a disk storage adapter. The disk storage PA consists of two hex characters. The first character, 1/0 group address, is determined by switch settings on the associated SCF card (see Chapter 2 for a detailed discussion of addressing) and is assigned according to the location of disk storage. The second character of the address, 0, is fixed by board wiring. For example, the processor disk storage PA is 80 and the first 8101 disk storage PA is 90.
FA 113 Configuration Table Entry
LV PA UTUT OPOP OPOP
LV
Level
01
PA
Physical Address
P = 1/0 Group address - set in the SCF switches
A = Fixed wiring on the board
Disk Storage Location
8130 8140 8140 Model BXX 1st 8101 2nd 8101 3rd 8101 (8140 only) 4th 8101 (8140 only)
PA
Lower Upper
80
-
80
-
84
85
90
91
AO
A1
BO
81
co
Cl
UTUT = Unit Type 0020
OPOP
Option 1000 2000 3000 4000
Disk Feature 29Meg 64Meg 23Meg 58Meg
OPOP 0000
Moving Heads 5
11 4 10
Fixed Heads 0 0 8 8
SY27-2521·3
(FA111 Cont-FA113)
5-FA-6
FA120 Basic Operational Description
The operation of the DSD can be divided into four broad categories: Seek: Positions selected heads over desired tracks. Read/Write:· Reads or writes data on selected head. Integrity: Checks device operation and ensures data integrity. Sense: Provides error and status information to the adapter.
Further categories can be defined for: Control: Defines signal bus operations between adapter cards and DSD. Power: Includes motor drive, braking, power on and off sequencing.
Operationally, these categories all interact and cannot normally be separated. However, they are treated separately in the descriptions found in FA450 "Detailed Data Flow".
Figure FA120-1 is a high-level diagram of the data flow in the disk storage adapter and the DSD.
SY27-2521-3
5-FA·6
SC
To Other Adapters
Gated Driver/Receiver
Board To
Board Wiring
TCC
w
CMD Decoder
Disk Storage Adapter
FCB Decoder
l..lllll TAC I""
_[1----
KA
Control Cable (CC)
Disk Electronics -")I.I Terminator JFA9
r "V[r--------.A1A4
:? Logic1 FA4 Card
'""·-------------N-o_t_e_2----------~------·A_1_c_2__--.___
_.
.,..
·~
FCB Buffer
Control
·
_· -_- - , ... A. K"'_~
Logic 2 FA5 Card A1D2
.,__ _ _s_p_in_d_le_B_r_a_k_e_____~, - - - - - - - - - - Note 3
Disk Enclosure -- - -
FA1 FCB
Card Processor
TCC
x
Note 1
TCC y
TCC
z
Data Handler Control
..,i
i...
~
SER DES/ Bit CTR
..WR·
i...._ RD
r-
Dedicated Cable (DD) Note 2
Data
(MH) - Moving Heads
)
Channel FA3 Card A1B2
f --;J (FH) - Fixed Heads
.,..._ _ _R_IW_H_e_a_d_s_ _ _.::J_ - - - - - - - - - - - - - -
Note 3
I
-y --~--~----...-
I
Jr
I
Servo 1 FA6 Card A1E2
Servo Head Note 3
,
1
I I I
I
I
Not·:
1. See FA t 11 for card /ocat/ons.
2. See FA420 for DSD signal connections. 3. See FA422 for DE llgnal connections.
Note 1
Servo 2 FA7 Card A1F2
I
l
VCM Driver
,________V_C_M_C__o_il______~_, --------.J
FAS Card
Note 3
Figure FA120-1. Data Flow in the Disk Storage Adapter and the DSD
SY27-2521-3
System Power Control
J .,..._____S_p_i_nd_l_e_M_o_to_r_____~ _ -- _ _ _ _ _ _ _ _ _ _ _ _ _
Note 3
(FA120)
5-FA-7
FA130 DSD Unique Repair Strategy
The General Failure Index (GFI) contained in Chapter 1 provides procedures for initial disk storage fault isolation. If the GF I isolates a problem to disk storage, it directs you to use the maintenance device (MD) to execute the FA MAP contained on test diskette 03 for problem resolution. The primary repair strategy for disk storage problems involves use of the FA MAP offline. If random or intermittent failures occur that cannot be resolved by the MAPs, the MD prompts you to use the intermittent repair strategies, or action plans, contained in FA350.
SV27-2521-3
FA 131 Disk Storage Unique Intermittent Repair Strategy
See FA300 for detailed information on intermittent failures. An intermittent failure can be defined as:
· An error occurring so infrequently that it is not detectable by looping the test. Go to FA350 "Action Plan to Correct Intermittent Failures".
· An error occurring at random times (different test error messages occur), thereby making the MAPs ineffective. After the MAPs detect three different test error messages, you are instructed to go to FA350.
· An error that is detected only after looping the diagnostics for more than 5 minutes. Record the test message error number and continue using the FA MAPs. In .this case, repair verification will again require looping.
5-FA-8
FA200 Offline Tests
Offline tests check the disk storage operation. They consist of 48 routines on maintenance diskette 03. The offHne tests are invoked using the maintenance device (MD), either by the FA MAP or the Free-Lance Option.
· When using the FA MAP, the MAPs invoke the tests as needed.
· Valid offline routines are: 01-47 and 50 (see FA210).
· When using the Free-Lance Option, the following test invocation message must be entered:
At 80BC, enter PAB.
At 80BC, enter SLRRB.
PA = Disk storage address (see FA 112)
S
Sense Option (one character)
0 = run disk storage adapter tests only
1 = run disk storage adapter and device tests
2 = not used by disk storage
L Loop Option (one character)
0 = run selected routines one time
1 = loop selected routines; stop on error
2 = loop selected routines; bypass error
RR Routine Number (two characters)
If 00 or no entry is made, all routines will run. If a routine number is entered, only that routine will run.
B
begin execution, enters the invoke message.
FA210 Offline Test Routine Descriptions
The offline disk storage tests consist of 48 routines arranged to test the functions within the disk storage in an order that isolates the problem to the most likely failing FRU(s). Routines 01-19 tests the adapter logic (see FA211), and Routines 20-47 and 50 test the drive (see FA212).
SY27-2521-3
Generally, the tests begin by checking the basic functions (for example, 1/0 instructions) and then progress to checking complex functions (for example, function definition module, FDM, interface).
All 1/0 instructions that are defined are executed with minimal setup to get predictable results from an 1/0 instruction. All accessible registers are set to values to verify that each latch of the register can be turned on and turned off.
Error generation tests are included to test the error detection logic. The objective is to have functional errors cause the various status bits (indicating the error) to be turned on. These routines require a somewhat more sophisticated use of an 1/0 sequence.
A functional exercise of the hardware is done by executing a random program of Seeks, Writing of data, Reading of data, and Reading of IDs. Any errors recorded during this exercise are considered potential solid failures.
All writing of data and IDs is confined to the test cylinder (cylinder 359). Reading data is also confined to the test cylinder and the fixed he.ad area. Reading IOs is unrestricted. There are cases in whic:;h the error is displayed while a bad ID exists (on the test track of head 1 only). A normal termination of the test (such as a FREE or BEGIN) clears the bad ID. Since the possibility of an abnormal end to a test exists (such as, loss of power), the Operational Format Utility must be used to restore the correct IDs. Errors that could cause a bad. ID condition are:
Routine
Error Numbers
27
13,14,15
29
16, 17, 18, 19, 1A, 18
30
13, 14, 15, 16, 17
--32---- -
- --1-J,-t4,- 15, 16, 17
33
13, 14, 15, 16, 17
34
13, 14, 15, 16, 17, 18, 19
35
13,14,15
36
13, 14, 15
46
10,11,12,13
50
11
Note: After FRU replacement, depending on the nature of the problem, the disk surface may contain bad data, thus preventing a good verification run. When this occurs, it may be advisable to run the Operational Format Utility.
Also, these failures may have resulted in bad data on the customer/user area, requiring re-creation of the data by the user and possibly reformat (IDs) of the defective area by use of the utilities. Affected areas are tracks 0, 1, and 128 of head 1, fixed heads, and the CE cylinder (359).
(FA130-FA210)
5-FA-9
SY27-2521-3
FA211 Adapter Logic Offline Test Routine Descriptions
Routine 01. Tests the adapter reset command by checking all registers reset by the command for correct reset values. The registers tested are: basic status, FCB processor status, seek status, burst register, first value register, next function request register, data CHCV, FCB CHCV, and seek register.
Routine 02. Tests the basic status register and the commands that modify the register (set/reset basic status under mask, read basic status).
Routine 03. Tests the next function request register. The register is reset and written to all 1'sand then all O's. The state of the NF R register is tested after each write.
Routine 04. Tests the seek register and the commands that modify the seek register. The seek register is reset then written with all 1's plus the recalibrate bit. It is then read for the correct state. Next the seek register is written with all O's and tested for the correct state.
Routine 05. Tests the FCB channel central vector and the commands that modify the CHCV. It is written first to all 1'sand then to all O's and tested for the correct state.
Routine 06. Tests the data channel control vector and the commands that modify the CHCV. It is written first to all 1's and then to all O's and tested for the correct state.
Routine 07. Tests the first value register and the commands that modify the register. It is written first to all 1's and then to all O's and tested for the correct state in each case.
Routine 08. Tests the initiate command and basic FCB operation. Prior to the first command being issued in this test, the PASO channel hang message is outputted on the invoking device. This message is overlaid by the test before it is seen unless a Channel Hang condition really exists. This precaution is necessary as this routine transfers data between the processor storage and the adapter. The test issues the initiate command with the adapter disabled and checks the CHCVs. The adapter is then enabled and an FCB of 'NO-OP' is processed. Again the CHCVs are tested.
Routine 09. Tests for an FCB timeout error. The error is generated in the routine. The test executes an FCB with channel request inhibited. Basic status and seek status are compared.
5-FA-10
Routine 10. Verifies that a program-controlled interrupt can be executed and that an interrupt is generated. The adapter is enabled and an FCB of 'NO-OP, PCI' is processed. Basic status is checked to ensure that an interrupt occurs.
Routine 11. Tests the store memory control FCB command. The adapter is enabled and an FCB is processed for the SMC subcommand. Basic status is checked as well as the appropriate channel pointer registers.
Routine 12. Is an extended test of a program-controlled interrupt. It insures that PCI alone sets the interrupt bit. The adapter is enabled but file interrupts are disabled. An FCB of 'PCl,NO-OP,SMC,NO-OP' is processed and basic status is checked for an interrupt.
Routine 13. Tests that interrupt is set when device error is set. The adapter is enabled with file interrupts disabled. The device error bit is set in basic status and the basic status register is checked for an interrupt.
Routine 14. Tests that all invalid PIO commands generate equipment checks. The adapter is enabled and each invalid command is issued. Basic status is then compared for the correct setting.
Routine 15. Tests the file reset command. A reset file command is issued and basic status is checked for all O's.
Routine 16. Tests the FDM initialization of the file. The FDM initialization function request is issued followed by a request to the FDM to read basic status. FDM return codes are checked after each function.
Routine 17. Tests the load burst count, store new track, and load sector count FCB commands. FCB's of 'SNT,LSC,LDburst' are processed. The residual count register, seek register, and burst register are read and tested for the appropriate status.
Routine 18. Tests the adapter data buffers for the ability to retain 1'sand O's. FCBs are processed to write and read both data buffers in the adapter and the data received is compared with what is expected.
Routine 19. Tests the adapter data buffer for parity check generation. A parity check is generated in the data buffer, and FCB is processed to write data into buffer 1 with odd parity, a second FCB is processed to read the data with even parity, and data handler basic status bit 1 (data handler error) is checked to see that it is set.
FA212 Disk Drive Offline Test Routine Descriptions
Routine 20. Tests the recalibrate FCB command and file recalibrate. The ability to read the file sense is also tested. FCBs are processed to recalibrate and to read file status; status is checked after each to ensure correct setting. This routine checks the control sample pulsing logic by issuing 32 requests for file sense. After each request, a check is made to ensure the index/sector bit is on. This routine also tests the file rotational speed bit in the adapter basic status. Bit 1 of the data handler extended status (file speed ok) is checked to ensure that it is on.
Routine 21. Tests the ability of the file to wrap data on the cable. FCBs are processed to recalibrate, read file status, and to perform file wrap. Status is checked after each to ensure correct setting.
Routine 22. Tests the read ID immediate command. FCBs are processed to perform recalibrate, read ID immediate, and to store new track (359) followed by a read ID immediate. Status is checked to ensure operations were performed correctly.
Routine 23. Tests the seek command and file arm movement. The test includes a seek from cylinder 0 to cylinder 1 to cylinder 0. The seek controls are tested. FCBs processed are: recalibrate; seek head 1, cylinder 001; read ID immediate; seek head 1, cylinder 000; file sense; and read ID immediate. Status is checked after each operation.
Routine 24. Tests servo calibration. FCBs processed are: recalibrate; seek head 1, cylinder 128; and recalibrate. Status is checked after each operation.
Routine 25. Tests write data, read data, and readback check FCB commands. FCBs processed are: recalibrate; seek head 1, cylinder 359; read ID immediate; write sector; read file status; read sector; read file status; (compare data); readback check. Status is checked after each operation. This routine performs 64 cycles of all operations excepting the initial recalibrate.
Routine 26. Tests the ability of the file control electronics to read the IDs of all heads according to model. A recalibrate is issued first: then each moving head that is installed (figured from Test Control Monitor (TCM) configuration option byte) is tested using a seek, read ID normal, and write sector. Each fixed head present is tested using a seek, SNT, and read ID normal.
The configuration definitions are (from TCM option byte):
Offline Use
Option Byte
Definition
10
5 moving heads
(29M)
20
11 moving heads
(64M)
30
4 moving heads and 8 fixed heads (23M)
40
10 moving heads and 8 fixed heads (58M)
SY27-2521·3
Routine 27. Tests sector ID flags. The following FCBs are processed: recalibrate; seek head 1, cylinder 359; read ID immediate;write,read ID; (set ID flag bit);write,read ID; and read residual count register. Status is checked after each operation.
Routine 28. Tests the multisector operation of the file. The file is exercised with skip factors of 1, 2, 4, and 8. For each skip factor, sector counts of 2, 4, 8, 16, 32 and 64 are used. The test proceeds as follows: recalibrate, seek (cylinder 359), read ID immediate, write sector, read sector, set skip factor and sector count, load sector count, read sector, test buffer areas for correct data. The test is looped until all of the combinations of sector count and skip factor have been tested. After each operation, status is checked to ensure all correct conditions exist.
Routine 29. Tests the format and retrieve FCB commands. This routine first performs a recalibrate, seek (359), and read ID immediate. The ID is saved. Next the routine performs a write sector, read sector, and retrieve. The retrieved data is then checked. A format (FFFF) is then performed on the sector. A read sector is performed and the data compared for hex FF. Next a format (0000) is performed. A read sector is executed and the data compared for hex 00. The ID is restored. Status fs checked after each operation.
Routine 30. Tests the read displaced ID and write displaced ID FCB commands. The test first does a recalibrate, seek (359), and a read ID immdediate. The ID is saved. Next, FCBs are issued to write displaced ID, read displaced ID, and read ID normal. The ID is restored. Status is checked after each operation. Reformatting is done to clean up the data file.
Routine 31. Performs extended testing of the recalibrate command. After a recalibrate and seek (359) is performed, a read ID immediate is performed. Status is checked after each operation.
Routine 32. Tests that the adapter can generate an ID error. The error is indicated in the basic status by attempting to write to a defective sector. First a recalibrate, seek (359), and read ID immediate are performed. The ID is saved. A write ID is performed to set defective sector. A write sector is then attempted and should fail. The proper error codes are checked. The ID is restored. Status is checked after each operation.
Routine 33. Tests that the adapter can generate an ID error by accessing a sector with an incorrect ID written on the file. The routine does a recalibrate, seek (359), and read ID immediate. The ID is saved. A write ID normal is done with a bad ID field. A read ID normal and read sector are issued. The appropriate error conditions are checked. Status is checked after all operations. The good ID is restored.
(FA211, FA212)
5-FA-11
Routine 34. Tests that the disk adapter can generate a data field error indication in the basic status. The error is generated by attempting to write data to a protected sector. FCBs are processed as follows: recalibrate, seek (359), read ID immediate. The ID is saved. Next, FCBs are processed for write sector, write ID (protected), read ID normal, write sector normal, and read sector normal. Proper status is checked after each operation. The good ID is restored.
Routine 35. Tests that the disk adapter can generate a CRC error and an ID error. This is done by reading an ID with bad CRC. The routine creates and restores the ID. FCBs are processed for recalibrate, seek (359), and read ID immediate. The ID is saved. The sector is formatted with the CRC bad for that ID. A read sector normal is performed. Proper status is checked after each operation. The good ID is restored.
Routine 36. Tests that the disk adapter generates a CRC error and a data field error in the basic status. This is done by reading data sector with bad CRC. This routine creates the bad CRC and restores a good CRC at completion. A recalibrate, seek (359), and read ID immediate are issued and the ID is saved. The sector is formatted with bad data CRC. A read sector FCB is processed. The original good ID is restored. Two write sectors are performed. Status is checked after each operation for the correct setting.
Routine 37. Tests that the disk adapter generates a sector not found error in the basic status. This is done by attempting to access sector numbers beyond the valid range. A recalibrate, seek (359), and read ID immediate are issued. Next, a readback check is issued for an invalid sector. The readback check is looped for sector addresses 42-7F.
Routine 38. Tests that the disk can generate a multisector error indication. This routine writes multiple sectors so that a count remains in the residual count register. A recalibrate, seek (359), read ID immediate, and write sector are issued. An FCB for load sector count and read multiple sector is issued. Status is checked after each operation.
Routine 39. Tests that the adapter can generate a file error indication in the basic status and FCB processor status. This is done by sending the file a control byte with even parity. A recalibrate, seek (359), and read ID immediate are issued. Next, an FCB is processed to send a control byte with even parity. Status is checked after each operation.
Routine 40. Tests that the disk adapter generates a file error indicated in the basic status and the FCB processor status. This is done by sending the file an address larger than the maximum for the file. A recalibrate, seek (359), and read ID immediate are issued. Next, a seek for cylinder 511 is issued. Status is checked after each operation.
Routine 41. Tests that the disk adapter can generate a control bus parity error in the basic status and the FCB processor status. This is done by writing a control byte to the file with odd parity and reading it back with even parity. One FCB is processed which writes the control byte odd and reads it back even. Status is checked for the error when the operation is completed.
Routine 42. Tests that the disk adapter can generate a command error indication in the basic status and the seek status register. This is done by issuing a diagnostic write.command when the FCB processor is busy. A recalibrate, seek (359), and read ID immediate are issued. An FCB is then processed with seek, PCI, seek, and SMC commands chained. The PCI causes an immediate return to the driver. At this time the diagnostic write is issued. Status is checked after each operation.
SY27-2521-3
REA 06-88481
5-FA-12
Routine 43. Tests the ability of the file control electronics to access random cylinders and heads, and to read the track IDs according to model. An FCB is processed to: issue recalibrate, seek (128), recalibrate, seek (359), and read ID immediate. Next, an FCB is processed to perform 73 random seeks followed by a read ID normal on different cylinders o.n all heads (1-4). Status is checked after each operation.
Routine 44. Performs a seek speed test by doing a recalibrate, a seek (359), and a read
ID normal (PSC =0). An FCB is then issued and timed while performing four seeks,
alternating between cylinder 0 and cylinder 359. The seek speed is checked for a ±15% tolerance. The speed constants are adjusted for each processor.
Routine 45. Tests the file rotational speed bit in the adapter basic status and then verifies that the speedbit functions correctly. The test issues a recalibrate, a seek (359), and a read ID normal (PSC = 0). The routine is then delayed about 10 ms (about 1/2 of a revolution). The routine then issues a read ID normal (PSC = O) and times the operation. The next time PSC 0 comes under the head should be near 9.2 ms-. One revolution takes exactly 19.2 ms. The speed is then checked for a+/- 10% tolerance. The speed constants are adjusted for each processor.
Routine 46. Ensu_res that a multisector write of IDs only writes requested IDs. The test performs a recalibrate and then a seek to head 1 of the CE track. The test then writes two IDs using a multisector write operation. The IDs are read and compared to ensure that the write worked. Next, all IDs on the disk are checked to ensure that only the requested writes were performed. Status is checked after each operation.
Routine 47. Ensures that a multisector read of 32 data sectors are processed within approximately 40-60 ms. The test first issues a recalibrate and then a seek to head 1 of the CE track. The test then reads 32 sectors using a multisector retrieve. The expired time is tested. Status is checked after each operation. Speed constants are adjusted for each processor.
Routine 48. Checks that the DSD subsystem can successfully process multisector write operations. The routine processes Recalibrate, Seek (cylinder 359), and Read ID Immediate FCBs. Next, the routine issues Multisector Writes for skip factors 1, 2, 4, and 8, with a count of 2. Finally, the routine loops 10 times issuing a Multisector Write for skip factor 2 with a count of 64. After each operation, status is checked to ensure all correct conditions exist.
Routine 50. Performs a checkout of the fixed heads. No data is written in the sector fields under a fixed head; however, the write circuitry of each fixed head is tested by writing IDs. These IDs are rewritten correctly by the test. If an error condition causes a bad ID to remain under a fixed head, reformatting of that track should resolve the problem. The customer data under a fixed head should then be available, as previously, to the test. This routine processes one FCB that performs seek, read ID, write ID (error), read ID (to test), and restore ID operations.
The configuration definitions are (from TCM option byte):
Offline Use
Option Byte
Definition
10
5 moving heads
(29M)
20
11 moving heads
(64M)
30
4 moving heads and 6 fixed heads (23M)
40
10 moving heads and 8 fixed heads (58M)
FA220 Not Used
FA230 Test Message Formats and Status Information
The formats of the output messages are:
Format Content
1
YYBC
2
PAZZ
3
PAXE RREN CCMO
4
PAXE RR EN RCVD EXPO
5
PAXE RREN FSTB AFAP BFBP CFCP SSFE HSBS HER1 R200
Bytes
02 02 06 08 20
Legend
yy
System message number
BC
Indicates a system error
PA
zz
x = 1
Disk storage physical address Ml number Indicates that PA is the adapter address
X=2 Indicates that PA is the device address
E=E Indicates that this is an error message
RR
Routine number
EN
Error number
CC
One byte of command code (current PIO operation)
MO
One byte of error modifier data defined by failure description
RCVD - Two bytes of received data defined by error description
EXPO Two bytes of expected data defined by error description
FS
One byte of fife status
TB
One byte of wrap fail status (00 =good, 80 =fail)
AF
One byte of file sense 1 (101)
AP
One byte of file pulsing 1 (101)
BF
One byte of file sense 2 (110)
BP - One byte of file pulsing 2 (110)
CF - One byte offile sense 3 (111)
CP - One byte of file pulsing 3 (111)
SS
One byte of seek status
FE - One byte of FCB processor extended status
HS
One byte of data handler basic status
BS - One byte of adapter basic status
HE - One byte of data handler extended status
R1 - One byte of next function request register, part 1
R2 - One byte of next function request register, part 2
00 - One byte of hex 00 for pad
Note: When enterlng test error messages (as in menu selection 'C'), spaces must not be entered as shown in the above format.
FA231 Offline Adapter Test Message Formats The adapter tests use only formats 1, 2, 3, and 4.
FA232 Drive Test Message Formats The disk drive tests use all the formats (1, 2, 3, 4, and 5)
FA233 Status and Sense Byte Formats
File Status (FS) Byte (Tag 100)
Bit Position
File Status (FS)
0
1
2
Fixed Head Not Selected
Brake Applied
*
Track Not Avail
*
3 Command Error
*
4
5
6
Data Seek Home Unsafe Inc
*
7 Not Ready
*
Note: The active condition of any bit is a 1.
*Bits with an asterisk indicate error conditions when they are set to a 1. Al I other bits indicate DSD status at the time the adapter sampled the status register.
Bit 0 - Fixed Head Not Selected. This bit is set to 1 at the conclusion of a seek, power-up, recalibrate or moving head select. This bit is set to 0 at the conclusion of a fixed head select operation, even if fixed heads are not present.
Bit 1 - Brake Applied. This bit is set if the brake coil is no longer energized and the brake is applied. It provides sense information for the fact that the dedicated line 'brake applied' was activated. The DSD powers down within 5 seconds of the brake applied line being active.
Bit 2 - Track Not Available. If a command requires the DSD to access an invalid cylinder (valid cyclinders are 0 to 359), then an interrupt is given and this sense bit set. The actuator will not move. This bit is reset after a seek tag sequence with a valid address.
Bit 3 - Command Error. This sense bit is set when the DSD detects a parity error on either the control bus or tag lines, or an invalid tag code. An interrupt is then generated. The resulting sense cycle clears the interrupt caused by a tag error. In this case, 'reset error' must be activated followed by a further sense command to clear the interrupt as tag parity error removes confidence in control and sense cycle communication. Correct parity is presented on the control bus by the DSD even after a 'command error' is detected. Cylinder and head address is checked after a command error before a write operation is performed.
Bit 4 - Data Unsafe. Certain conditions can occur during read/write operations which may change/risk customer data. A 'data unsafe' incident may result in loss of a maximum of one sector of customer information. These conditions are monitored by the DSD and their occurrence will result in an interrupt. Write current is immediately inhibited at source and all data heads are deselected by the DSD. All system commands except the sense command are ignored. The DSD adpater reselects the appropriate head after resetting an unsafe condition.
REA 06-88481
SY27-2521-3
(FA212 Cont-FA233)
5-FA-13
The following conditions result in 'data unsafe' being set: Write or read and multiple module selection error Write and data servo unsafe Write and no write transitions Not write and write current detected Write and not on track and moving head selected Write and read. If write and read commands overlap by 10 ns or more, 'data unsafe' is set. Write and head short circuit to ground indication Write and moving head selected during sector pulse. Can only write in the data areas. Write and 'not ready'
'Reset error' in all cases clears the 'unsafe condition'.
Bit 5 - Seek Incomplete. This sense bit is set when any access, recalibrate, or moving head select operation is in process. (This bit is not relevant to fixed head seeks.) This bit is also set by 'not ready'. A read, write, or moving head seek operation must not be attempted with the bit active. A sense cycle performed during an access will correctly indicate 'seek incomplete'. If this bit is still set after the access should have been completed, then a recalibrate may be performed.
Bit 6 - Home. This bit is set at the end of a successful power-up sequence or recalibrate operation; the actuator is at cylinder 0 with moving head '00001' selected. An interrupt is then issued and the resulting sense command indicates 'home'. A normal access to cylinder 0 will not cause a 'home' indication. If 'home' is not indicated after a powerup or a recalibrate, then a recalibrate should be performed.
'Home' is reset when the next tag code '001' is issued.
Bit 7 - Not Ready. The DSD indicates 'not ready' for any of the following reasons, and will issue an interrupt: · 'Seek' operation not completed within 1. 7 seconds. · 'Invalid move' is active. The internal DSD latch 'invalid move' detects actuator motion
which is not in response to an access command or an attempt to write on moving heads during an access operation. · The PLO is out of synchronization for any reason including loss of disk speed. · Disk not moving. · Oscillator not running. · Not 'power OK'. · Excessive noise on the +24V line. · Servo unsafe. · 'Power good' pulsing (should be a solid level). · The wires on the top right voltage connector on the C gate are pulled out or not making connection.
This bit is reset by a recalibrate operation. If 'brake applied' is on, do a power-down/ power-up sequence. If the recalibrate is successful, then a 'reset error' completes the error recovery.
SY27-2521·3
REA 06-88481
File Sense (AF) Byte 1 (Tag 101) and File Pulsing (AP) Byte 1
5-FA-14
Bit Position
File Sense 1 (AF)
0
1
2
3
4
5
On Track
Linear Ind/ Region Sect Pulse
Out Direct
Not Out Drive
Not In Drive
6
7
Tag Velocity Pty Profile Error Error
File Pulsing 1
(AP)
x x xx
x x xx
X = 0: Not pulsing = 1: Pulsing
Note: Active sense and pulsing bits are set to a 1. An active pulsing bit indicates that the associated sense bit changed state while it was being sampled 256 times. Thus, the sense bit is intermittent and not valid.
Bit description is the condition when an active (set to "1") pulsing bit indicates that, after being repetitively sampled 256 times, the associated sense bit has changed state (pulsing). Another way to state it is, if 'the pulsing bit is set, the condition of the associated sense bit has no valid meaning.
Bit 0 - On Track. Is normally set when the actuator is on track (within 10% of track center). It is reset if the actuator deviates from the center of the track by 10% (as defined by 'servo sample').
Bit 1 - Linear Region Normal and Even. Changes state when the actuator crosses a track. The level is +5V for an even track and OV for an odd track. The line normally pulses when on track.
Bit 2 - Index and Sector Pulses Missing. Is normally reset indicating that index and sector pulses are present.
Bit 3 - Out Direction. Indicates the direction of seek.
Bit 4 - Not Out Drive, Bit 5 - Not In Drive. These bits indicate the logic level of the voice coil drives respectively 'out' and 'in':
Bit4 Bit 5 Meaning
0
0
The actuator drive is turned off and the actuator is being pushed in
by return spring.
0
1
The actuator is being accelerated outwards.
0
The actuator is being accelerated inwards.
The actuator is either on track or setting on track at the end of an access.
Bit 6 -Tag Parity Error. Is set if the DSD receives other than tag codes '001' to '111' with correct parity. It is reset by 'reset error'.
Bit 7 - Velocity Profile Error. Is set by an internal test on the DSD circuits, which sets the instantaneous velocity of the actuator. It is reset by 'reset error'.
File Sense (BF) Byte 2 (Tag 110) and File Pulsing (BP) Byte 2
Bit Position 0
1
2 3
4
5
6
7
File Sense 2 (BF)
Behind Home
Miss- Not Coil ing Miss- Cur· Clocks ing rent 72 Clock Low
Error Latch
File Pulsing 2 x
(BP)
x x x
Miss· ing Servo Signal
Off Data Track
Not Missing Posi· ti on Error Signal
CTR 5 In Sync
x x x x
X = 0: Not pulsing = 1: Pulsing
Note: Active sense and pulsing bits are set to a 1. An active pulsing bit indicates that the associated sense bit changed state while it was being sampled 256 times. Thus, the sense bit is intermittent and not valid.
Bit description is the condition when an active (set to "1 ")pulsing bit indicates that, after being repetitively sampled 256 times, the associated sense bit has changed state (pulsing). Another way to s'tate it is, if the pulsing bit is set, the condition of the associ· ated sense bit has no valid meaning.
Bit 0 - Behind Home. Is set when the DSD actuator is over a cylinder between the land· ing zone and track 0. This bit is reset when the actuator is outside cylinder 0.
Bit 1 - Missing Clocks 7 2. Changes state every time a 'missing clock' is detected. Miss· ing clocks are used to code positional information on the director servo surface.
Bit 2 - Not Missing Clocks Error Latch. Is normally set. It is reset when six consecutive missing clocks are detected. It is set by 'reset error'.
Bit 3 - Coil Current Low. Is set when the coil current is below a threshold level. It is reset by 'recalibrate'.
Bit 4 - Missing Serve; Signal. Is set if the amplitude of the signal from the dedicated Servo Read is too small for the DSD electronics to use. The bit is reset by 'reset error'.
Bit 5 - Off Data Track. Indicates the servo is off track, as defined by the 'servo sample', by plus or minus 10%. Bit 5 is reset by 'recalibrate'.
Bit 6 - Not Missing Position Error Signals (PES). Indicates that the PES reference signals used by the actuator when accessing and following a track are correct. It is set by 'recalibrate'.
Bit 7 - Counter 5 In Sync. Indicates that the phase locked oscillator (PLO) in the DSD is in synchronism.
File Sense (CF) Byte 3 (Tag 111) and File Pulsing (CP) Byte 3
Bit Position 0
1
2
3
4
5
6
7
File Sense 3 (CF)
Not Shift
File Pulsing 3 x
(CP)
Not (Off Track and Write)
Inside AGC Win· dow
Not AGC Freeze
Demod Pulsing
Not (Read and Write)
Not (Servo Protect and Write)
Invalid Move
x xx x x x x
X = 0: Not pulsing = 1: Pulsing
Note: Active sense and pulsing bi'ts are set to a 1. An active pulsing bit indicates that the associated sense bit changed state while it was being sampled 256 times. Thus, the sense bit is intermittent and not valid.
Bit description is the condition when an active (set to "1") pulsing bit indicates that, after being repetitively sampled 256 times, the associated sense bit has changed state (pulsing). Another way to s'tate it is, if the pulsing bit is set, the condition of the associated sense bit has no valid meaning.
Bit 0 - Not Shift. Indicates that the position of the actuator agrees with the desired cylinder address given in the previous tag 2, tag 1 sequence. Indicates that a seek command is not in progress.
Bit 1 - Not (Off Track and Write). Indicates that the DSD is not trying (erroneously) to write when off track. The bit is set by 'reset error'.
Bit 2 - Inside AGC Window. Indicates that signal from the selected head is of suffi· cient amplitude to be used by the head-position control circuits. (Does not apply if non-existent head is selected.)
Bit 3 - Not AGC Freeze. Indicates that the AGC freeze line pulses correctly once per sector.
Bit 4 - Demod Pulsing. Indicates that part of the position-detection electronics is working correctly. This bit should normally be pulsing.
Bit 5 - Not (Read and Write). Indicates that the DSD is trying to read and write at the same time.
Bit 6 - Not fServo Protect and Write). Indicates that the DSD is trying to write between sectors.
Bit 7 - Invalid Move. Indicates that the servo head in the DSD has been offset by more than half a track from its normal position without a seek request. It is reset by 'recalibrate'.
REA 06-88481
SY27·2521·3
(FA233 Cont)
5-FA-15
Seek Status (SS)
Bit Position 0
1
2 3
4
5
6
7
Seek Status (SS)
Tag Seq Error
CMD Error
FCB FCB Proc Time Error Error
Cable Cont OK
Seek Status
Notes: 1. The status bits are set to 1 when active. 2. Bits 0, 1, and 2 are set to indicate errors that occur during an operation between the
adapter and the processor. Bit 3 is set to indicate an error that occurs during an operation between the adapter and the file.
Bit 0 - Tag Sequence Error. Indicates that the adapter received the improper interface sequence from the processor. This bit is set when: 1. Two adapters are addressed at the same time. 2. The file detects the TC tag. 3. An invalid tag sequence of the 1/0, TA, TD, and channel grant tags is detected.
SY27-2521-3
REA 06-88481
5-FA-16
5, 6, 7 0 10
Activity
FHS begun and not yet completed. NO MHS or RECAL in progress. (Not seek complete.) If FHS is not complete in 52 ms, 'seek incomplete' is set.
0 0
MHS begun and not yet completed. No FHS or RECAL in progress nor
begun after MHS. (Not seek complete.)
0
MHS begun then FHS begun. FHS completed and MHS not completed.
(Not seek complete.)
0
MHS begun then FHS begun. Neither completed. (Not seek complete.)
MHS begun then FHS begun. MHS completed and FHS not completed. No data is transferred until FHS is complete.
MHS
Moving Head Seek
FHS
Fixed Head Seek
RECAL
Recalibrate
FCB Processor Extended Status (FE)
Bit Position 0
1
2
3
4
5
6
7
This bit sets adapter basic status (BS) bits 5 and 7.
Bit 1 - Command Error. Indicates that the adapter received an invalid command or command parity error from the processor. This bit is set when: 1. The adapter receives an invalid command. 2. The adapter receives a valid command with bad parity. 3. An initiate signal is issued to the adapter and it is busy. 4. The adapter receives an invalid command when adapter basic status bit 3 (busy) is on.
This bit sets adapter basic status (BS) bits 5 and 7.
Bit 2 - FCB Processor Error. Indicates an internal parity error within the FCB processor card. This bit, which is set during TA or TD time of the 1/0 command, sets adapter basic status (BS) bits 1, 5, and 7.
Bit 3 - FCB Timeout Error. Indicates the adapter is busy and more than 2 seconds have elapsed between channel requests to the processor. The 6-1 /2 second single-shot has expired (this single-shot is started when the start signal is issued to the adapter). (This may not be an error if the system code has disabled interruptions.) This bit sets adapter basic status (BS) bits 1 and 7.
Bit 4 - Cable Continuity OK. Bit is set as long as continuity is complete through the adapter and drive cards; all must be properly seated. This line does not go through the file cards (see FA522). This line is +3V when good.
Bit 5, 6, 7 - Seek Status. Indicate seek status of file.
5, 6, 7 0 0 0 0 0
Activity No MHS, FHS, or RECAL in progress. RECAL begun and not yet completed. (Not seek complete.)
FCB Processor 0
0
Extended
Status
(FE)
FCB Processor Extended Status
2 3 4 5 6 7 (00) 0 0 0 0 0 0 (01) 0 0 0 0 0
(03) 0 0 0 0 (04) 0 0 0 0 0 (05) 0 0 0 0
(07) 0 0 0
(OF) 0 0
(11) 0 0 0 0
(27) 0 0 1 1
(2C) 0
0 0
Significance
Idle state
Adapter waiting to make channel request or continually servicing a hot file interrupt
Waiting for Channel Grant
Op decode state (interface hang condition).
Waiting for acknowledge signal from Data Handler (cannot communicate between FA1 and FA2 cards).
Waiting for proceed signal from Data Handler to enable next file operation.
Waiting for proceed signal from Data Handler (doing data transfer to/from storage).
Incomplete End Op processing. Decoding 'end-op' has not presented adapter basic status (BS) but is presenting an interruption. If a seek or data transfer command in the FCB precedes 'end-op', cannot get 'end-op complete' until those commands complete.
Incomplete PC I processing
Waiting for seek completion before processing Data Op. Will have a 'read' or 'write' in the next function request register. Must wait for 'seek complete' before any data transfer can be done.
2 3 4 5 6 7 (37) 1 0 1 1
(38)
0 0 0
(39)
0 0
(3A)
0 0
(38)
0
(3C)
0 0
(3D)
0
(3E)
0
(3F) 1 1 1 1 1 1
Significance
End op processing delayed by outstanding seek. There is no data transfer command in the FCB list. Need 'seek complete' before executing end-op.
Multisector transfer past sector 63. The number of sectors to transfer exceed the number of sectors remaining on the disk.
Data Handler error. The following conditions turn on this error: (1) data CRC, (2) ID error, (3) track does not compare, (4) something is wrong with the data the file presented to the data handler card (FA2 card). See data handler basic status and data handler extended status to determine the type of error. When this error occurs, the following is true: (1) seek was OK, (2) can transfer data, (3) alternate sector sets an FCB status of hex 39.
File error (non data); not doing a data transfer. In conjunction with this error, file status bits 1, 2, 3, 4, or 7 is on.
File error (data related); error during a read or write, not necessarily a data problem.
Data flow parity error. There is a parity error in the tags between the FA1 and FA2 cards. This is a control parity error, not a data parity error.
Control sample timeout. Sent 'control sample' to the file but did not get 'control sample' back within 1.8 µsec.
CHIO equipment check (file adapter check). The adapter connected to the processor by means of CH 10 and 'halt' became
is active. If data handler status bit 6 is off, the adapter doing
a control operation; if the bit is on, the adapter is doing an FCB operation.
Control bus parity error. The adapter detected bad parity during a sense operation to the file.
Data Handler Basic Status (HS)
Bit Position 0
1
2 3
4
5
6
7
Data Handler Basic Status (HS)
FCB Proc Error
DH Error
CRC ID Error Error
Data Field Error
Sector Not Found
Equip
Check
I
Halt
File Write Gate Error
Note: The status bits are set to a 1 when active.
Bit 0 - FCB Processor Error. Indicates Data Handler received bad parity from FCB Processor.
Bit 1 - Data Handler Error. Indicates error was detected internal to data handler card (FA2 card).
Bit 2 - CRC Error. Indicates that CRC received from file does not compare to CRC generated. See bits 3 and 4 to determine the Jype of CRC error.
Adapter Basic Status (BS)
REA 06-88481
SY27-2521-3
Bit 3 - ID Error. Indicates an ID error. This bit is set if the defective bit is on in the ID field on a read ID, read data, or write data command.
Bit 4 - Data Field Error. Indicates CRC error or write operation to a write protected field.
Bit 5 - Sector Not Found. Indicates that the sector cannot be found. Set if: 1. Sector search and two indexes are detected before the sector is found. 2. Not getting sector pulses (sector counter does not run). 3. Sync byte is not decoded in read ID (see if the NRZI line is, pulsing).
Bit 6 - Equip Check/Halt. Indicates that equipment check occurred after the data channel grant. Data transfer is halted. This bit sets adapter basic status bits 1, 5, and 7.
Bit 7 - File Write Gate Error. Indicates a miscompare between write gate to file and write gate return from file (Data Unsafe condition). Set if: 1. File was told to write, but no write gate was returned. 2. File was not told to write, but a write gate was returned.
If NFR equals write, this indicates a good write gate error. If NFR equals read or write, this indicates a multisector data transfer is in process and the write gate return should be active.
Bit Position
0
1
2
3
4
5
6
7
Adapter Basic PCI Device File Busy Chan Equip Req Int
Status
Error Int
Req Check Enab
(BS)
Disab
Frozen
Note: The status bits are set to a 1 when active.
Bit 0 - Program Controlled Interrupt (PCI). Indicates when the adapter decodes a PCI operation.
Bit 1 - Device Error. Indicates adapter has detected an error which was caused by the device. The 'file not ready' bit is set.
Bit 2 - File Interrupt Disabled. Set by program. Adapter ignores interrupts from file.
Bit 3 - Busy. Indicates that the adapter is processing FCBs.
Bit 4 - Channel Request Frozen. Set by program. Prevents adapter from requesting a new FCR operation. Allows the current data transfer to complete, then stops the adapter.
Bit 5 - Equipment Check. Indicates that this adapter has detected an error. The adapter is selected, but received halt tag on an internal check. This bit is also set by a parity error in the NFR. When this bit is on, 'file not ready' is set.
Bit 6 - Requests Enabled. Set by program. Enables adapter to make requests to the processor. If this bit is off, the adapter cannot perform CHIO operations.
Bit 7 - Interrupt. Set when adapter wants to interrupt processing. Occurs for normal reasons as well as error detection.
(FA233 Cont)
5-FA-17
Da18 Handler Extended Status (HE)
Bit Position 0
1
2 3
4
5
6
7
Data Handler BFRA Fife Wrt Wrt
Extended
to
Speed Prat Prat
Status (HE) File
Good 1
0
Sector Disp
Sector Sector Alt Reas- Defect Sector signed
SY27-2621-3
REA 06-88481
Note: The status bits are set to a 1 when active.
Bit 0 - Buffer A to File. Indicates buffer A connected to file. "O" indicates buffer B connected to file.
Bit 1 - File Speed Good. Indicates file speed tolerance is within 2-1/2% nominal. This bit is off if sector pulses are not detected every 600 ms.
Note: Bim 2-7 are valid only for the last good ID read. If the read was not successful, 'these bits are left over from the previous ID read.
Bit 2 -Write Protect 1. Indicates second half of sector is Write Protected.
Bit 3 - Write Protect 0. Indicates first half of sector is Write Protected.
Bit 4 - Sector Displaced. Indicates sector is displaced form normal position (pushed down).
Bit 5 - Sector Reassigned. Indicates sector is reassigned to an alternate sector.
Bit 6 - Sector Defective. Indicates a defective sector.
Bit 1 -Alternate Sector. Indicates that the sector is an alternate.
~FA-17.1
This page intentionally left blank.
REA 06-88481
SY27-2621-3
(fA233 Cont)
&·FA-17.2
FA240 Test Message, Error Number Descriptions, and Actions
SY27-2521-3
REA 06-88481
Use Figure FA240-1 to identify locations for sections FA241, FA242, and FA243.
Mach Type
Model
Gate 01A
Pseudo Card Locations Disk Storage Gate 01 C
SC
FA1 FA2 FA3 FA4 FA5 FAS FA7 FAS FA9
8130 A2x
A2G2 A1U2 A1T2 A182 A1C2 A1D2 A1E2 A1F2 VCM A1A4
8140
A3x/A4x A5x
A202 A202 A2P2 A182 A1C2 A1D2 A1E2 A1 F2 VCM A1A4 A2D2 A2F2 A2E2 A182 A1C2 A1D2 A1E2 A1F2 VCM A1A4
8140
Bxx (lower) A2A2 B2H2 B2J2 A182 A1C2 A102 A1E2 A1F2 VCM A1A4 Bx2 (upper) A2A2 B2F2 B2G2 A1B2 A1C2 A1D2 A1 E2 A1F2 VCM A1A4
8101
Axx (lower) A2A2 A2H2 A2J2 A1B2 A1C2 A102 A1 E2 A1F2 VCM A1A4 Axx (upper) A2A2 A2E2 A2F2 A182 A1C2 A1D2 A1E2 A1F2 VCM A1A4
A. Pseudo Card Locations
Adapter 01 A-XX Board
Mach
- - Type
8130 8140
8140
8101
Mach
- - Type
8130 8140
8140
8101
- - Model
A2x A3xlA4x A5x Bxx (lower) Bxx (upper) Axx (lower) Axx (upper)
Card
- - Socket
A1Y1 A2Z6 A2Z3 A2K4 A2Y3 A2Y3 A2Y2
- - Model
A2x A3x/A4x A5x Bxx(lower) Bxx (upper) Axx (lower) Axx (upper)
Card
- - Socket
A1Y2 A2Z5 A2Z2 A2K5 A2Z3 A2Z3 A2Z2
Disk Storage Drive Board 01X
Control (CC)
A1A3
A1A2
Dedicated (DD)
A1A5
A1Y1
Moving Head (MH)
Fixed Head (FH)
DE
Moving and Fixed Head Cables are a part of the DE.
B. Pseudo Cable Locations
Figure FA240-1. Pseudo Card and Cable Locations
Manual Intervention (Ml) or Operator Messages
5-FA-18
Msg No.
Message
Actions*
PAOO
Successful completion.
PASO
CH 10 hang, attempted data transfer.
1. Reseat or exchange FA 1, FA2, SC, and TCC W and X.
2. Check continuity in nets: FA1B08-SC 009 FA1G03-SC P02
PA84
CE cylinder degraded.
PAFO
Test in progress.
1. Run Surface Status and Format utility {see CP653) on cylinder 359.
2. Rerun FA MAP.
3. If same failure occurs, reseat or exchange FA1, FA2.
Note: If the problem still occurs, the CE cylinder has been degraded so that a Write Multisector (full track) operation can not be tested. All other diagnostic tests have completed successfully.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on o'tller adapters. See Chapter 3, Figures L T140-1 through L T140-3, LT240-1 through L T240-8, LT340-1 and L T340-2 for TCC locations and part numbers.
FA241 Common Test Error Messages and Actions
RREN
Failure Desription
Actions*
XX01
System check
1. Reseat or exchange FA 1, FA2, SC, FA4, FA3.
2. Check wiring on TCCs W, X, Y,Z.
3. Check continuity in the nets: · FA2B02-FA 1S02 · FA2B09-FA1009 e FA2B10-FA1B10 · FA2002-FA 1002 · FA2D06-FA 1006 · FA2007-FA 1D07 · FA2010-FA1010 e FA2D11-FA1011 · FA2012-FA1012 e FA2G09-SCG12 · FA2G12.:...FA 1J05 · FA2S10-FA1004FA1G09-FA 1J11 · FA1B02-FA1G05FA 1J13 · FA 1G02-SCD07 · FA 1J04-SCJ06 · FA1M08-SCG10 e FA1M10-SCP10 · FA 1P02-SCG02 · FA1P10-SCM12 · FA1S04-SCB02 e FA 1S05-SCG05 · FA1S07-SCD11 · FA1S08-SCM02
e FA 1510-SCB10
· FA 1512-SCP11 · FA1513-SCG09
e FA 1U02-SCD 13
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. rec W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures l T140-1 thro~gh l T140-3, l r240-1 through l r240-8, l r340-1 and l T340-2 for rec locations and part numbers.
REA 06-88481
SY27-2521·3
RREN
Failure Desription
Actions*
XX01 (cont)
3. (cont) · FA1U04-SCJ09 e FA 1U05-SCG04 · FA 1U07-SCP06 · FA1U10-SCJ07 e FA 1U 11-SCBOB e FA1U12-SCP13 · FA1U13-SCG08
XX04
Unexpected interrupt
1. Reseat or exchange FA5, FA7, FA4.
XX07
Initialize error.
1. Reseat or exchange FA 1, FA4, FA9, FA2, FA5, FA7.
2. Reseat or replace TCCs W, X.
3. Reset or replace cables (CC), (DD).
4. Check continuity in nets:
· TCCW24
· TCC X05 e TCC X24 · FA 1G 13-(CC)B04-
FA4P07-FA9804 e FA1B04-(CC)B12-
FA9B12-FA4P09
· FA 1B05-(DD)B04FA4D06
· FA1G07-(CC)B05FA4M08-FA9B05
e FA1G10-(CC)B03FA4M07-FA9803
· FA1G12-(CC)B02FA4M09-FA9802
e FA1J09-(CC)D05FA9D05-FA4P02
· FA1M12-(DD)B03FA4G09
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. rec W, X, Y, and Z are interchangeable with each other. However, they may be
different 'than those used on other adapters. See Chapter 3, Figures l T140-1 through l T140-3, L T240-1 through L T240-8, L r340-1 and l r340-2 for rec locations and part numbers.
(FA240, FA241)
5-FA-19
RREN
Failure Description
Actions*
XXOA
Save ID error.
1. Run Surface Status and Format Utility (CP653) on cylinder 359.
2. Rerun tests (even if utility failed).
XXOB
ID not stored.
xxoc
Restore ID error.
1. Run Surface Status and Format Utility (CP653) on cylinder 359.
2. Rerun tests (even if utility failed).
1. Run Surface Status and Format Utility (CP653) on cylinder 359.
2. Rerun tests (even if utility failed).
XXOF XX66
Internal equipment check.
CE cylinder in degraded state
Reseat or exchange FA1, FA2.
1. Run Surface Status and Format Utility (CP653) on cylinder 359, all heads.
2. Suspect DE; request aid.
XX77
Data handler basic status error.
1. Reseat or exchange FA2, FA1.
2. Check continuity in TCC Y and Z.
XX99
Adapter machine check.
1. Reseat or exchange FA2, FA1.
Notes:
2. Check continuity in nets:
· FA 1B10-FA2810 · FA1D02-FA2D02 · FA1D06-FA2006 · FA1D07-FA2D07 · FA 1 D09-FA2B09 · FA101O-FA2D10 · FA 1D11-FA2D11 · FA1D12-FA2012 · FA 1S02-FA2B02
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, l T240-1 through L T240-8, LT340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
5-FA-20
FA242 Adapter Test Messages, Error Numbers, and Actions
RREN 0110 0111 0112
Failure Description Residual count error. FCB processor error. Seek status error.
Actions*
Reseat or exchange FA 1, FA2.
Reseat or exchange FA 1, FA2.
1. Reseat or exchange FA 1. 2. Check continuity in nets:
· TCCY03 Wiring: See FA522
0113 0114
Burst reg error. First value reg error.
Restart or exchange FA 1, FA2.
1. Reseat or exchange FA 1, FA4, (DD).
2. Check continuity in nets:
· FA1B05-(DD)B04FA4D06
0115
0116 0117 0118 0210 0211 0212 0213 0214 0215 0310 0311 0315 0410
Next function request reg error. Data CHCV error. FCB CHCV error. Seek reg error. Set basic status error.
Reset basic status error.
Set basic status error. Reset basic status error. Write NFR reg error.
Reset NF R reg error. NFR reg error. (write NFR reg)
Reseat or exchange FA 1.
Reseat or exchange FA1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA 1, FA2, FA4, FA5. Reseat or exchange FA1, FA2.
Reseat or exchange FA 1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA 1.
Reseat or exchange FA 1. Reseat or exchange FA 1.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, LT240-1 through l T240-8, l T340-1 and LT340-2 for TCC locations and part numbers.
RREN
Failure Description
Actions*
0411
Seek reg error. (load NFR reg to seek reg)
Reseat or exchange FA 1.
0412
NFR reg error. (write NFR reg)
Reseat or exchange FA 1.
0413
Seek reg error. (load NFR reg to seek reg)
Reseat or exchange FA 1.
0414
NFR reg error. (write NFR reg)
Reseat or exchange FA 1.
0415
NFR reg error. (controller reset)
Reseat or exchange FA1.
0416
Seek reg error. (load NFR reg to seek reg)
Reseat or exchange FA 1.
0418
Seek reg error. (controller reset)
Reseat or exchange FA1.
0510 through 0517
FCB CHCV error.
Reset or exchange FA1, FA2.
0610 through 0618
Data CHCV error.
Reseat or exchange FA1, FA2.
0710
Set first value.
Reseat or exchange FA 1, FA2.
0711
Write first value.
Reseat or exchange FA 1, FA2.
0714
Reset first value.
Reseat or exchange FA1, FA2.
0816
FCB CHCV error. (using Initiate command)
Reseat or exchange FA 1, FA2.
0811
Basic status error. (after Initiate command)
- 1. Reseat or exchange FA 1, FA2.
2. Check continuity in TCCs W,X.
0812
Error in FCB channel pointer reg address. (using Initiate command)
Reseat or exchange FA1.
Notes:
7. *Use Figure FA240-1 to identify card and cable locations.
2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, 'they may be
different 'than those used on other adapters. See Chapter 3, Figures l T140-1 through L T140.:J, L T240-1 through l T240..IJ, L T340-1 and L T340-2 for TCC locations and part numbers.
REA 06-88481
SY27-2521-3
RREN
Failure Description
Actions*
0813 0814
Basic status error. (after Initiate command)
FCB CHCV error. (using Initiate command)
1. Reseat or exchange FA1, FA2,SC.
2. Check continuity in TCCs W,X.
3. Check continuity in net:
· FA1J02-SCJ02 · FA2G09-SCG12
Reseat or exchange FA1.
0910
Basic status error (during Initiate Timeout)
Reseat or exchange FA 1, FA2, FA4, FA5.
0911
Seek status error. (during Initiate Timeout)
Reseat or exchange FA 1, FA2, FA4, FA5, FA6.
1010
Basic status error. (on set PCI)
1. Reseat or exchange FA 1, FA2.
2. Check continuity in TCC W05.
1110
Basic status error. (after store memory control)
1. Reseat or exchange FA 1, FA2.
2. Check continuity in TCCs W,X.
1111
Data CHCV error. (after store memory control)
Reseat or exchange FA 1, FA2.
1112
FCB CHCV error. (after store memory control)
Reseat or exchange FA 1, FA2.
1113 1114
Error in address remaining in FCB CHCV. (after store memory control)
Reseat or exchange FA 1, FA2.
1210
Basic status error after PCI.
Reseat or exchange FA 1, FA2.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different 'than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240..IJ, LT340-1 and LT340-2 for TCC locations and part numbers.
(FA241 Cont, FA242)
5-FA-21
RREN
Failure Description
Actions*
1310
Basic status error after Set Basic Status Under Mask command.
Reseat or exchange FA1, FA2.
1410
Invalid PIO command failed to set equipment check.
Reseat or exchange FA1, FA2.
1519
Basic status error after File Reset P10 command.
1. Reseat or exchange FA4, FA2, (DD).
2. Check continuity in nets:
· FA2G13-(DD)D11FA4G12
1610
Basic status error during initialize function request.
Reseat or exchange FA2, FA 1.
1711
Failure in program function request block (FRB).
Reseat or exchange FA1, FA2, FA3.
1712
Residual count error
Reseat or exchange FA 1, FA2.
1713
Seek reg error
Reseat or exchange FA1, FA2.
1714
Burst reg error.
Reseat or exchange FA 1, FA2.
1715
FRB complete with error.
Reseat or exchange FA 1, FA2.
1716
Residual count error.
Reseat or exchange FA 1, FA2.
1717
Seek reg error.
Reseat or exchange FA 1, FA2.
1718
Burst reg error.
Reseat or exchange FA 1, FA2.
1811
Write buffer error.
1. Reseat or exchange FA 1, FA2.
2. Check continuity in TCCs
w.x.
1812
Read buffer error.
1. Reseat or exchange FA 1, FA2.
2. Check continuity in TCCs W, X,Y,Z.
1813
Data buffer error (0000.)
1. Reseat or exchange FA 1, FA2, SC.
2. Check continuity in TCC X.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards_when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different tha" those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
REA 06-88481
RREN
1814
1815 1816 1817 1818 1910 1911 1912
5-FA-22
Failure Description Data buffer error (F FF F).
Write buffer error. Read buffer error. Data error (FFFF). Data buffer error (0000). Write buffer error. Read buffer error. Basic status error after read buffer.
Actions* 1. Reseat or exchange FA1, FA2. 2. Check continuity in TCCs Y, Z. Reseat or exch~nge FA 1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA 1, FA2. Reseat or exchange FA1, FA2. Reseat or exchange FA 1, FA2.
FA243 Disk Logic Test Messages, Error Numbers, and Possible Causes
RREN
2010
Failure Description
Control sample not received.
Actions*
1. Reseat or exchange FA1, FA4, FA9, (CC).
2. Check whether jumper at C-A1A5B12 to 813 is properly installed and has good continuity.
3. Check continuity in nets:
· FA1804-(CC)B 12FA9B12-FA4P09
· FA1J06-FA2J12-(DD)B12FA4803
· FA7G1 O-(J1-2) · FA5G11-(J5-1)
4. Check power interface lines (see PA452):
· - Power good
· + Brake applied
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, LT340-1 and L T340-2 for TCC locations and part numbers.
RREN 2011
Failure Description
Seek timeout error (spindle turning and appears to be running normally)
Actions·
1. Reseat or exchange FA5, FA4, FA7, FA3, FAS, FA2, FAl, (DD).
2. Check drive power. 3. Check that actuator lock is
fully disengaged. (see FA590) 4. Check continuity in nets:
e FA4B06-FA5U10 e FA4D07-FA5S09 e FA4D11-FA5B03 e FA4D13-FA5U11 e FA4J07- FA5D06-FA7S13 e FA 1B05-(DD)B04-FA4D06 · FA3M05-FA4D09-FA5J04 · FA3P05-FA4P10 · FA3P06-FA4G02 e FA3P10-FA4J06 · FA4B13-FA5S04 e FA4M12-FA5P09 e FA4P11-FA5J13-FA7S07 e FA4S05-FA5D07 e FA4S06-FA5D05 e FA4S07-FA5M12 e FA4S08-FA5M07 e FA4U06-FA5B05 e FA5G04-FA7D09 e FA4M13-FA5S07-
FA7P11 e FA4U02-FA5U07-
FA7M13 e FA4U10-FA5G07 e FA5G02-FA7B09 e FA5G03-FA7B08 e FA5J06-FA7B10
Notes:
1. *Use Figure FA240-1 to identify card and cable locations.
2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 throu{Jh L T140-3, l T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
REA 06-88481
SY27-2521 ·3
RREN
2011 {cont)
Failure Description
Seek timeout error (spindle stops turning after 20 second power on delay)
Seek timeout error (spindle never starts turning at all)
Actions·
e FA5S13-(DD)D07FA2B03
e FA6D10-FA7D10, J10,
P10, U10
1. Check that spindle lock is fully disengaged (see FA590).
2. Reseat or exchange FAS, FA7, FA6, FA3, FA4.
3. Check continuity in nets: e FA3M10-FA6G12 e FA3U12-FA5J05 e FA4S03-FA5S08 e FA5B13-FA6G07 e FA5G05-FA7B04 e FA5J02-FA6J07 e FA7D05-(MH)D11 e FA7D06-(MH)D10 e FA7S04-(MH)B10, 812, D09, 013
4. Suspect DE; request aid.
1. Check that spindle lock is fully disengaged (see FA590).
2. Check belt, motor (see FA580, FA570)
3. Check ac to motor (see FA570)
4. Reseat or exchange FA4, FA5,FA7
5. Check continuity in nets:
· FA4S13-FA5U09FA7P02 · FA5M09-FA7P09-
B2A01 (J1-8)
Notes:
1. *use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
(FA242 Cont, FA243)
5-FA-23
RREN
Failure Description
Actions*
2012
Fi le sense not '82' after recal failure
1. Reseat or exchange FA4, FA9, FA1, FA5, FA3, FA7, FA2, FA6, (CC), (DD).
2. Check continuity in nets:
· TCC-W22
· FA1803-(CC)D06FA9D06-FA4M03
· FA1G08-(CC)D09FA9D09-FA4M05
· FA1G12-(CC)B02FA9B02-FA4P07
· FA 1J07-(CC)D07FA9D07-FA4M02
· FA1J09-(CC)D05FA9D05-FA4P02
· FA1J10-(CC)D04FA9004-FA4M04
· FA1J12-(CC)D13FA9013-FA4P04
· FA1M03-(CC)D11FA9011-F A4P05
Notes:
1. *Use Figure FA240-1 to identify card and cable locations.
2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different 'than those used on o'ther adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 'through L T240-8, L T340-1 and LT340-2 for TCC locations and part numbers.
SY27-2521-3
REA 06-88481
5-FA-24
RREN
Failure Description
Actions*
2012 (cont)
e FA1M04-(CC)D10FA9D10-FA4P06
e FA1P04-(CC)D12FA9D12-FA4M06
· FA2004-(DD)B05-FA5S10 e FA3B12-(MH)D03-(FH)A13
· FA3G10-FA4M11 e FA3M02-FAS11 e FA3M05-FA4D09-FA5J04 e FA4B08-FA5P07-FA7M02 · FA4S07-FA5M12 e FA4U07-FA5P10 · FA5B09-FA7S10 · FA5G02-FA7B09
e FA5S12-FA7D13
· FA5U04-FA7P07
3. Suspect DE; request aid.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 'through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
RREN
Failure Description
Actions*
2013 2014
File sense not '82' after successful sense operation
Control bus error
1. Reseat or exchange FA4, FA5, FA7
2. Check continuity in net:
· FA4B08-FA5P07-FA7M02
1. Reseat or exchange FA7, FA6, FA 1, FA9, FA3, FA4, FA5, FA2, (CC).
2. Check continuity in nets:
· FA 1B03-(CC)006FA9D06-FA4M03
· FA1G07-(CC)B05FA9B05-FA4M08
· FA1G10-(CC)B03FA9B03-FA4M07
· FA1J07-(CC)D07FA9007-FA4M02
· FA1J09-(CC)005FA9D05-FA4P02
· FA1J10-(CC)D04FA9D04-FA4M04
e FA4B08-FA5P07-FA7M02
· FA5B07-FA7011
e FA6B13-FA7P06 e FA6D10-FA7D10-
FA7J10-FA7P10FA7U10
e FA6D13-FA7D02
Notes:
1. *Use Figure FA240-1 to identify card and cable locations.
2. Unplug 11$SOCiated cards when chscking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures l T140r 1 through l T140-3, l T240-1 through l T240-8, l T340-1 and l T340-2 for TCC locations and part numbers.
SY27-2521-3
RREN
Failure Description
Actions*
2015
Recalibrate failure
1. Reseat or exchange FA5, FA4, FA7, FA3, FAS, FA2, FA1, (DD)
2. Check continuity in nets:
· FA5J06-FA7B10
e FA5U12-FA7M08
2016
Speed OK bit failure
1. Reseat or exchange FA2.
2017
Recal failure
1. Reseat or exchange FA5, FA7. 2. Check continuity of net:
e FA5U12-FA7M08 · FA6D13-FA7D02
2018
Control sample pulsing logic error
1. Reseat or exchange FA1, FA4.
2110
Recal failure
1. Reseat or exchange FA5, FA7, FA4, FA1.
2. Check continuity in net: e FA5J06-FA7810
2111
Control bus failure
1. Reseat or exchange FA4, FA9, FA1, (CC)
2. Check continuity of net:
· FA 1B03-(CC)006FA9D06-FA4M03
· FA1G08-(CC)D09FA9009-FA4M05
· FA1J09-(CC)D05FA9005-FA4P02
Notes:
1. *Use Figure FA240- 1 to identify card and cable locations.
2. Unplug associated cards when chscking continuity. 3. TCC W, X, Y, and Z are interchangeable wi'th each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140- r
through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
(F A243 Cont)
5-FA-25
RREN
Failure Description
Actions·
2112
Control bus parity error.
Reseat or exchange FA4.
2113
Control bus failure
1. Reseat or exchange FA4, FA9, FA1, (CC).
2114
FRB complete with control bus parity error.
1. Reseat or exchange FA4, FA 1, FA9, (CC).
2. Check continuity in nets:
· FA4P04-(CC)D13FA1J12-FA9D13
2115
FRB complete with error and no file error.
1. Reseat or exchange FA6, FA7. 2. Check wiring in net:
· FA6D10-FA7D10, J10, P10,U10
2116
FRB complete with control bus parity error.
Reseat or exchange FA 1, FA4, (CC).
2117
FRB complete with error and no file error.
Reseat or exchange FA 1, FA2, FA4.
2210
Recal failure.
Reseat or exchange FA4, FA5, FA7, FA1.
2212
FRB complete with error.
1. Run Surface Status and Format Utility (CP653) on track 0, head 1, then rerun diagnostic tests.
2. Reseat or exchange FA3, FA2, FA4, FA5, FA1, FA7, FA6.
3. Reseat or replace cables (DD), (FH), (MH), TCCs W, X, Y.
4. Check continuity in nets:
· FA1P06-(DD)D04FA4J13
· FA2B07-FA2B08
· FA2812-FA2D13FA2G02-FA2G03FA2J02
· FA2G07-(DD)D10FA3U07
· FA2G08-(DD)B08FA3S07
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different 'than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
5-FA-26
RREN
Failure Description
Actions·
2212 (cont)
4. (cont) · FA2J06-(00)012FA3U11 · FA2J07-(DO)D09-FA4J11 · FA2J09-(00)D05-FA3S02 · FA3804-FA4J02FA5G09 · FA3812-(MH)D03(FH) A1A13 · FA3J12-FA4J12 · FA3M04-(MH)B03(FH) A 1E13
· FA3M05-FA4D09FA5J04
e FA3M07-~FH) A1E11 · FA3M09-(MH)B02 e FA3P05-FA4P10 e FA3P09-(MH)B06 e FA3P10-FA4J06 e FA3U06-FA6G03 e FA4J07-FA5D06-FA7S13 5. See net in FA521. 6. Suspect OE; request aid.
2213
FRB complete without error after error test.
1. Run Surface Status and Format Utility (CP653) on track 0, head 1, then rerun diagnostic tests.
2. Reseat or exchange FA4, FA3, FA2, FA1, FA5
3. Check continuity in nets: · FA1P06-(DD)004-FA4J13 · FA2G08-(DD)B08-FA3S07 · FA2J07-(DO)D09-FA4J11 · FA3B04-FA4J02-FA5G09 · FA3J12-FA4J12
4. Suspect DE; request aid.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 'through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
RREN
Failure Description
Actions*
2214
Basic status not correct after error test.
Reseat or exchange FA1, FA2.
2310
Recalibrate error.
Reseat or exchange FA4, FA5, FA7,FA1.
2311
Seek to track 1 error.
2312
File status.error.
1. Reseat or exchange FA4, FA5, FA7, FA6, FA1, FA9, (CC).
2. Check continuity in nets:
· FA1J10-(CC)D04FA9D04-FA4M04
a FAJ05-FA5U02
· FA4M06-(CC)D12FA1P04-FA9D12
· FA4S07-FA5M12 · FA4S09-FA6J06-FA7803
· FA4U06-FA5B05 · FA5G03-FA7B08
· FA7S02-FA5J07 · FA1G13-(CC)B04-
FA9B04-FA4M09
· FA4B08-FA5P07-FA7M02
1. Reseat or exchange FA4, FA9, FA1, FA6, FA7, (CC).
2. Check continuity in nets:
· FA1B03-(CC)D06FA9D06-FA4M03
· FA 1G08-(CC)D09FA9D09-FA4M05
· FA4S09-FA6J06FA7803
2313
File status not= 80.
1. Reseat or exchange FA4, FA5. 2. Check continuity in nets:
· FA4G04-FA5P12
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
RREN
Failure Description
Actions*
2314
Read ID error,
1. Run Surface Status and Format Utility (CP653) on track 1, head 1, then rerun diagnostic tests.
2. Reseat or exchange FA5, FA4,
FA7.
3. Reseat or replace cable (DD).
4. Check continuity in nets:
· FA4G05-FA5M08 · FA5B09-FA7S10
5. See net in FA521
6. Suspect DE; request aid.
2315
Seek to track 0 error.
2316
File status error.
1. Reseat or exchange FA5, FA4, FA7.
2. Cheek continuity in nets:
· FA4J05-FA5U02 · FA5S12-FA7D13
Reseat or exchange FA4, FA 1, (CC).
2317
File status not= 80.
Reseat or exchange FA4, FA6, FA7, FA1.
2318
Read ID error.
Reseat or exchange FAS, FA7.
2410
Recalibrate error.
Reseat or exchange FA4, FA5, FA7,FA1.
2411
Seek to track 128 error.
1. Reseat or exchange FA7, FA5, FA4.
2. Check continuity in nets:
· FA4S06-FA5D05 · FA5D04-B1E4A14-(J9-3) · FA4S05-FA5D07 · FA5B07-FA7D11 · FA5J07-FA7S02
· FA5S12-FA7D13
Notes:
1. *Use Figure FA240-1 to identify card and cable locations.
2 Unplug associated cards when checking continuity.
3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, l T240-1 through l T240-8, LT340-1 and L T340-2 for TCC locations and part numbers.
(FA243 Cont)
5-FA-27
RREN
Failure Description
Actions*
2412 2510
Recalibrate error after 128.
Recalibrate error.
Reseat or exchange FA4, FA6, FA7, FA1.
Reseat or exchange FA4, FA6, FA7, FA1.
2511
Seek to track 359 error. (CE track)
1. Run Surface Status and Format Utility (CP653) on cylinder 359, then rerun diagnostic tests. (even if utility fails)
2. Reseat or exchange FA5, FA7.
3. Check continuity in net:
· FA4S05-FA5D07
4. Check that actuator lock is fully disengaged. (See FA590.)
5. Suspect DE; request aid.
2512
Read ID error.
1. Run Surface Status and Format Utility (CPS53) on cylinder 359, then rerun diagnostic tests. (even if utility fails)
2. Reseat or exchange FA4, FA7, FA5.
3. Check continuity in net:
· FA5B09-FA7S10
4. Suspect DE; request aid.
2513
Write data error.
1. Run Surface Status.and Format Utility (CP653) on cylinder 359, then rerun diagnostic tests. (even if utility fails)
2. Reseat or exchange FA6, FA3, FAS, FA2, FA1, FA4, FA7, FA8, (DD).
.
Notes:
3. Check continuity in nets:
· FA1M13-(DD)D06FA4S10-FA5P13
· FA2B03-(DD)D07FA5S13
· FA2D09-(DD)B09FA5G08
· FA2G13-(DD)D11FA4G12
· FA2M04-(DD)D03FA3J07
· FA3D05-(MH)D05
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. rec W, X, Y, and Z are interchangeable with each other. However, they may be
different "than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L r240-1 through L r240-8, L r340-1 and L r340-2 for rec locations and part numbers.
SY27-2521-3
REA 06-88481
5-FA-28
RREN
Failure Description
Actions*
2513 (cont)
3. (cont) · FA3D06-(MH)D04 · FA3D07-(MH)D07(FH)A1D11
· FA3D12-(J1-3)
e FA3G03-(MH)B08-
(FH)A1C13 · FA3G13-FA4U12 · FA3J06-F A4G 11 · FA3P11-FA6G08 · FA3S02-(DD)D05-
FA2J09 · FA3U06-FASG03 · FA4B12-FA6G13-
FA7G12 · FA4G10-FA5U06 · FA4G13-FA6J13 · FA4J11-(DD)D09-
FA2J07 · FA5G08-(DD)B09-
FA2009 · FA5J09-FASG10 · FA5J10-FASJ04 · FA5U 13-FA6G04 · FASB12-FASG05 4. Suspect DE, request aid.
2514
File status error.
Reseat or exchange FA4, FAS, FA7,FA1.
2515
Read sector error.
1. Reseat or exchange FA3, FA2, (DD).
2. Check continuity in nets:
· FA2J11-(DD)B10FA3U02
251S
File status error.
Reseat or exchange FA4, FAS, FA7, FA1.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. rec W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L r240-1 through L T240-8, L r340-1 and L r340-2 for rec locations and part numbers.
RREN 2517 2518
2519
Failure Description Readback check error.
Seek, write, read back, check error. Seek to track 0 error.
Actions*
Reseat or exchange FA4, FA3, FAS, FA1, FA2.
1. Reseat or exchange FA7, FAS, FA2. 2. Suspect DE, request aid.
1. Reseat or exchange FAS, FA4, FA7.
2. Check continuity in net: · FA4S05-FA5D07
2520
Sector ID error.
Reseat or exchange FA1, SC, FA2.
2610
2611 2613 2614 2615 2616
2617 2618
Recalibrate, seek (128), recalibrate.
Model invalid.
Seek moving heads 1-4 (model 30). Seek moving heads 0-4 (model 10). Seek moving heads 1-A (model 40). Seek moving heads 0-A (model 20).
Seek moving head 0 (model 30). Seek moving head 0 (model 40).
1. Run Surface Status and Format Utility (CP653) on track 128, head 1. Then rerun diagnostic tests.
2. Reseat or exchange FA4, FA5, FA7,FA1.
See FA113; model and/or configuration are not valid.
1. Run Surface Status and Format Utility (CP653) on cylinder 359, all heads. Then rerun diagnostic tests.
2. Reseat or exchange FA3, FA4, FA1, FA2.
3. Reseat cable (MH), TCC X. 4. Check continuity in nets:
· FA3M04-(MH)B03-(FH)A1E13
e FA3M09-(MH)B02 e FA3M11-(MH)B05 e FA3P09-(MH)B06
· FA3P07-FA4P12
e FA3P04-(MH)B04-(FH)A1C11
5. Possible defective head. Replace DE. Request aid.
See FA113; model and/Or configuration do not agree.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continui'ty. 3. TCC W, X, Y, and Z are interchangeable wi'th each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures t. T140-1
through LT140.:J, LT240-1 through L T240-8, L T340-1 and LT340-2 for TCC locations and part numbers.
REA 06-88481
SY27-2521-3
RREN 2619 261A 2618 261C 2610 261E
Failure Description
Seek moving heads 5 (model 10/30). Seek moving heads 6 (model 10/30). Seek moving heads 7 (model 10/30). Seek moving heads 8 (model 10/30). Seek moving heads 9 (model 10/30). Seek moving heads A (model 10/30).
Actions*
See FA 113; model and/or configuration do not agree.
2620 2621 2622 2623 2624 262S 2626 2627 2628 2629 262A
RD/WRT moving head 0. RD/WAT moving head 1. RD/WRT moving head 2. RD/WAT moving head 3. RD/WAT moving head 4. RD/WAT moving head 5. RD/WRT moving head 6. RD/WAT moving head 7. RD/WRT moving head 8. RD/WAT moving head 9. RD/WRT moving head A.
1. Run Surface Status and Format Utility (CP653) on cylinder 359, all heads. Then rerun diagnostic tests.
2. Reseat or exchange FA1, FA2.
3. Check +24 V ripple.
4. Suspect DE; request aid.
2630 2631 2632 2633 2634 263S 2636 2637
RD failure fixed head 0. RD failure fixed head 1. RD failure fixed head 2. RD failure fixed head 3. RD failure fixed head 4. RD failure fixed head S. RD failure fixed head 6. RD failure fixed head 7.
1. Run Surface Status and Format Utility (CP653) on all fixed heads.
2. Reseat or exchange FA3, FAS, FA6.
3. Rerun tests.
4. If failure persists, suspect DE; request aid.
2710
Recalibrate error.
Reseat or exchange FA4, FAS, FA7, FA1.
2711
Seek 'to CE track error.
Reseat or exchange FAS( FA7.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continui'ty. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140.:J, L T240-1 through L T240-8, LT340-1 and LT340-2 for TCC locations and part numbers.
(i=A243 Cont)
5-FA-29
RREN
Failure Description·
Actions*
2712
Read ID error.
Reseat or exchange FA4, FA6, FA7.
2713
Write ID error.
Reseat or exchange FA5,FA7.
2714
File status error.
Reseat or exchange FA4, FA6, FA7, FA 1, FA2.
2715
Sector flag error.
2810
Recalibrate error.
1. Reseat or exchange FA4, FA3, FA5, FA 1, FA2, (DD).
2. Check continuity in nets:
· TCC X32
· FA2G13-(DD)D11FA4G12
· FA1M13-(DD)D06FA4S10-FA5P13
· FA3G13-FA4U12
Reseat or exchange FA4, FA5, FA7, FA1.
2811
Seek to CE track error.
Reseat or exchange FA4, FA5.
2812
Read ID error.
Reseat or exchange FA4, FA6, FA7.
2813
Write data error.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA1.
2814
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
2815
Read data error.
Reseat or exchange FA1, FA3, FA2.
2816
Multisector error.
Reseat or exchange FA3, FA2, FA1.
2817
Data overrun.
Reseat or exchange FA2.
2910
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continulty. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
5-FA-30
RREN
,.
Failure Description
Actions*
2911
Seek to CE.track error.
Reseat or exchange FA4, FA5.
2912
Read ID error.
Reseat or exchange FA4, FA6, FA7.
2913
Write data error.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA 1.
2914
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
2915
Retrieve error.
Reseat or exchange FA2, FA 1.
2916
Format error.
Reseat or exchange FA2, FA 1.
2917
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
2918
Data does not compare.
Reseat or exchange FA3, FA6, FA2, FA7.
2919
Format error.
Reseat or exchange FA2, FA 1.
291A 2918
Read data error.
Reseat or exchange FA3, FAS, FA2, FA7.
3010
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
3011
Seek to CE track error.
Reseat or exchange FA4, FA5.
3012
Read ID error.
Reseat or exchange FA4, FAS, FA7.
3013
WRT ID displaced error.
Reseat or exchange FA5, FA7, FA1.
3014
RD ID displaced error.
Reseat or exchange FA3, FA6, FA2, FA7, FA1.
3015
Displaced ID error.
Reseat or exchange FA3, FAS, FA2, FA7, FA1.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, LT240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
RREN
Failure Description
Actions*
3016
RD ID error.
Reseat or exchange FA3, FA6, FA2, FA7, FA1.
3017
Restore ID error.
Reseat or exchange FA3, FA6, FA2, FA7, FA1.
3018
Format error.
Reseat or exchange FA 1, FA2.
3110
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
3111
Seek to CE track error.
Reseat or exchange FA4, FA5.
3112
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3210
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
3211
Seek to CE track error.
Reseat or exchange FA4, FA5.
3212
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3213
Write ID error.
Reseat or exchange FA5, FA7.
3214
Data error.
Reseat or exchange FA3, FA6, FA2, FA7.
3215
Write data error.
Reseat or exchange FA6, FA3, FA4, FA6, FA2, FA7, FA1.
3216
Basic status error.
Reseat or exchange FA 1, FA2, FA4, FA9.
3217
Residual count error.
Reseat or exchange FA2, FA 1.
3310
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
3311
Seek to CE track error.
Reseat or exchange FA4, FA5.
3312
Read ID error.
Reseat or exchange FA4, FA6, FA7.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable wi'th each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140.:J, LT240-1 through LT240:.S, L T340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
RREN
Failure Description
Actions*
3313
Write ID error.
Reseat or exchange FA3, FA6, FA2, FA7.
3314
Read ID normal error.
Reseat or exchange FA3, FA6, FA2, FA7.
3315
Basic status error.
Reseat or exchange FA 1, FA4, FA6, FA2, FA9.
3316
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
3317
Basic status error.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
3410
Recalibrate error.
Reseat or exchange FA4, FA6, FA7,FA1.
3411
Seek to CE track error.
Reseat or exchange FA4, FA5.
3412
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3413
Write data error.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA 1.
3414
Write ID error.
Reseat or exchange FA5, FA7.
3415
Protect bit error.
Reseat or exchange FA3, FA6, FA2, FA7.
3416
Write data error.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA1.
3417
Basic status error.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
3418
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
3419
Protect data error.
Reseat or exchange FA3, FA6, FA2, FA7.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
(FA243 Cont)
5-FA-31
RREN 3510
Failure Description Recalibrate error.
Actions*
Reseat or exchange FA4, FA5, FA7, FA1.
3511
Seek to CE track error.
Reseat or exchange FA4, FA5.
3512
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3513
Format error.
Reseat or exchange FA2, FA 1.
3514
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
3515
Basic status error.
Reseat or exchange FA 1, FA4 FA5, FA2, FA9.
3610
Recalibrate error.
Reseat or exchange FA4, FA5, FA7,FA1.
3611
Seek to CE track error.
Reseat or exchange FA4, FA5.
3612
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3613
Format error.
Reseat or exchange FA2, FA 1.
3614
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
3615
Basic status error.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
3616 3617
Write data error.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA1.
3710
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
3711
Seek to CE track error.
Reseat or exchange FA4, FA5.
3712
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3713
Readback check error.
Reseat or exchange FA3, FA6, FA2, FA7, FA1.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable wi'th each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140..:J, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
SY27-2521-3
5.-FA-32
RREN
Failure Description
Actions*
3714
Basic status error.
Reseat or exchange FA1, FA4, FA5, FA2, FA9.
3810
Recalibrate error.
Reseat or exchange FA4, FA5, FA7,FA1.
3811
Seek to CE track error.
Reseat or exchange FA4, FA5.
3812
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3813
Write data error.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA 1.
3814
Read data error.
Reseat or exchange FA3, FA6, FA2, FA7.
3815
Basic status error.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
3816
Extended status error.
Reseat or exchange FA2, FA4, FA5, FA 1, FA9.
3910
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
3911
Seek to CE track error.
Reseat or exchange FA4, FA5.
3912
Read ID error.
Reseat or exchange FA4, FA6, FA7.
3913
Control bus error.
Reseat or exchange FA3, FA 1.
3914
Basic status error.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
3915
Extended status error.
Reseat or exchange FA2, FA4, FA5, FA 1, FA9.
4010
Recalibrate error.
Reseat or exchange FA4, FA5, FA7, FA1.
4011
Seek to CE track error.
Reseat or exchange FA4, FA5.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through l T140..:J, L T240-1 through L T240-8, l T340-1 and l T340-2 for TCC locations and part numbers.
RREN 4012
4013 4014
4015
4113 4114
4115
4210
4211 4212
4213 4214 4215
4216
4310 4311
Failure Description Read ID error. Invalid seek address. Basic status error. Extended status error. Control bus error. Basic status error. Extended status error. Recalibrate error. Seek to CE track error. Read ID error. PCI error. Basic status error. Extended status error. Seek error.
Actions*
Reseat or exchange FA4, FA6, FA7.
Reseat or exchange FA3, FA 1.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
Reseat or exchange FA2, FA4, FA5, FA 1, FA9.
Reseat or exchange FA4, FA 1.
Reseat or exchange FA 1, FA4, FA5, FA2, FA9.
Reseat or exchange FA2, FA4, FA5, FA1, FA9.
Reseat or exchange FA4, FA5, FA7, FA1.
Reseat or exchange FA4, FA5.
Reseat or exchange FA4, FA6, FA7.
Reseat or exchange FA1, FA2.
Reseat or exchange FA1, FA4, FA5, FA2, FA9.
Reseat or exchange FA2, FA4, FA5, FA 1, FA9.
1. Reseat or exchange FA4, FA5, FA7.
2. Suspect DE; request aid.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2 Unplug associated cards when checking con'tinuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, LT240-1 through L T240-8, LT340-1 and L T340-2 for TCC locations and part numbers.
REA 06-88481
SY27-2521-3
RREN 4411
Failure Description Seek speed error.
4412
Seek timeout
4413
Control Ier error.
Actions*
1. Reseat or exchange FA4, FA5. 2. Check continuity in nets:
· FA4002-FA5B02 · FA4B02-FA5B08 3. Suspect DE; request aid.
1. Reseat or exchange FA4, FA5. 2. Check continuity in nets:
· FA4D02-FA5B02
· FA4B02-FA5808
3. Suspect DE; request aid.
Reseat or exchange FA 1, FA2.
4510
Seek speed bit error.
Reseat or exchange FA2.
4511 4512
Speed out of tolerance. Timeout.
Reseat or exchange FAS, FA7, FA4, FA6.
Reseat or exchange FA 1, FA2. FA2, FA4.
4513 4610
Error during FCB processing.
Multisector write ID operational error.
Reseat or exchange FA 1, FA2.
Reseat or exchange FA6, FA3, FA4, FA5, FA2, FA7, FA1.
4611
Write IOs not requested.
Reseat or exchange FA1, FA2.
4612 4613
Timeout occurred waiting for processing.
Error during FCB processing.
Reseat or exchange FA1. Reseat or exchange FA 1, FA2.
4711
Multisector read too slow.
1. Reseat or exchange FA1.
I 2. Run diagnostics on other
adapters and/or disconnect
other adapters located on the
same board as the disk in
question; repair failing adapter.
Notes:
Note: A channel grant problem in another adapter may be affecting the disk operation.
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, l T240-1 through LT240-8, LT340-1 and l T340-2 for TCC locations and part numbers.
(FA243 Cont)
5-FA-33
RREN 4713
4810 4811 4812 4813 4814
5010
Failure Description
Error during FCB processing.
Recalibrate error.
Seek to CE track error. Read ID error. Write multisector error (2 sectors). Write multisector error (full track).
Invalid model.
5011 5012
Fixed head write error. Fixed head read error.
Actions* Reseat or exchange FA1, FA2.
SV27-2621-3
REA 06..S8481
FA250 Action Plan
Reseat or exchange FA4, FA5, FA7,FA1. Reseat or exchange FA4, FA5. Reseat or exchange FA4, FA6, FA7. Reseat or exchange FA1, FA2.
Reseat or exchange FA1, FA2.
Correct configuration table to agree with DSD model. Note: After a configuration correction, the processor must be re-IPLed.
Suspect DE; request aid.
1. Run Surface Status and Format Utility (CP653) on all fixed heads.
2. Reseat or exchange FA3, FA5, FA6, (FH).
3. Rerun tests. 4. If failure persists, suspect DE;
request aid.
Notes:
1. *Use Figure FA240-1 to identify card and cable locations. 2. Unplug associated cards when checking continuity. 3. TCC W, X, Y, and Z are interchangeable with each other. However, they may be
different than those used on other adapters. See Chapter 3, Figures L T140-1 through L T140-3, L T240-1 through L T240-8, L T340-1 and L T340-2 for TCC locations and part numbers.
5-FA-34
1. If the unit is available, and the offline tests have not been run, do a power-on reset and run the tests.
2. Record the error message (R REN) for future reference. If there is no failure, go to step 8.
3. The unit must be released by the customer before replacing the FRU(s) indicated on the MD. Always power the unit down when instructed to reseat or replace a FRU, or check nets for continuity or shorts.
4. For multiple FRU callouts, replace them in the order shown on the MD display because they are listed in the order of failure probability. After replacing each FRU, key 'FWD' and the verification tests are automatically performed.
5. Check FA240 for the error number to be sure that all of the possible FRUs have been replaced. Only the most likely FRUs are listed on the MD display.
6. If replacing the FR Us does not correct the problem, check the continuity of the nets listed for the error number in FA240. Also check each net to ground, there should be no shorts. a. Open nets are field repairable by installing a BLU/WHT wire to complete the path. First use a test jumper to verify the fix. b. For a grounded net, check for foreign matter on the board in the area of the net pins. (For example, pieces of wire, nuts, screws, tight wire.)
7. If the failure still occurs, try this action plan one more time starting at step 1 before requesting assistance.
8. If the tests run without a failure, loop the tests for five passes (see FA311) or until there is a failure. · If a failure occurs, go to step 3. · If no failure occurs, terminate the test by entering an 'F' on the MD and then 'ENT'.
9. If the tests do not fail after five passes, go to FA350.
FA300 Intermittent Failure Repair Strategy
FA310 Adapter-Unique Intermittent Repair Strategy
Intermittent failures may be detected by looping the FA offline tests, or by examining the error log.
FA311
Looping with MAP Interaction to Determine Failures
To loop the disk storage tests, answer "YES" to the question: "Do you want to check for intermittent failure by looping FA test?" The test loops continuously until an error is detected or the test is terminated by entering an F on the MD keypad. While the test is looping, PAFO is displayed on the MD.
If an error is detected while looping, the MAP analyzes and directs repairs of the failure in the same manner as a solid failure. Once a repair action has been performed, the MAP loops the tests to verify the repair.
Note: If an error ls not detected after five passes while looping the tests, or if 'the error detected occurs randomly (test error messages vary), 'the MAP operation is ineffective and more information is required. Go to FA350.
Ano'ther option is 'the free-lance looping operation (see FA313).
FA312 Using the System Error Log to Determine Failures
DPPX and DPCX record in their error logs any DSD failure that occurs during system operation. The error log can be used to select specific failure types or all failures. Obtain all error log records associated with the DSD. Refer to Chapter 2 (CP700 for DPPX; CP800 for DPCX) for information on how to obtain the error log and to FA340 "How to Use the Error Log". Examine the log to determine the type of failure and go to FA350 to correct the failure.
FA313 Using the Free-Lance Utility to Determine Failures
The disk storage tests can be looped using the free-lance operation provided by the maintenance device (MD). The test invocation message is PAPN B - 118 (see FA210). The test loops continuously until an error is detected or the test is terminated by entering an F on the MD keyboard.
FA320 Not Used
If an error is detected while looping, the MD displays the test message error number. Record the number and go to FA240 to identify and repair the failure. Once a repair action has been taken, loop the disk storage tests for at least five passes to verify the repair.
FA330 Error Log Formats and Meanings Used for the FA MAP
The format of the error log depends upon whether the customer is using DPPX or DPCX. For DPPX formats, see FA331; for DPCX, see FA332.
FA331 DPPX Error Log Formats and Meanings
Disk storage failures are stored in the DPPX error log in the Type 5 record format. Only those fields necessary for the FA MAPs are identified. See Chapter 2 (CP700) for complete error log details.
The error log for Class 05, Subclass 01, consists of either Header I or 11 plus the main
body of the Record.
If bit 0 of the Option Mask (Option)= 1, then Header I is supplied with a time stamp.
If bit 0 of the Option Mask = 0, then Header 11 is supplied with a sequence number.
The BCLE is part of the record of bit 1 if the option Mask= 1.
DPPX Error Log Format
The D fields are variable by adapter type.
Header I CLASS 05 SUBCLASS 01 OPTION (5) DATE VY.DOD TIME HH/MM/SS
Header II CLASS 05 SUBCLASS 01 OPTION (5) DATE YY.DDD SEONO. (1)
Record PA (2) SCA (3) OT (4) CRC (7) COMPSTAT (8) ARC (9) DATA (11) RES (12) CNT (13) IOEP (14) ADWA (15) CA (16) CPR (17) FRWA (18) RES (19)
Extended Data 001 (24) (25) 005 (32) (33) 009 (40) (41) 013 (48) (49)
002 (26) (27) DOS (34) (35) 010 (42) (43)
D03 (28) (29) 007 (36) (37) 011 (44) (45)
004 (30) (31)
DOS (38) (39) 012 (46) (47)
SY27-2521-3
(FA243 Cont-FA331)
5-FA-35
Content M·ning
The following listing describes the error log records used for the FA MAPs:
( 1) SEO NO.
Sequence Number of the error log record. This part of the Header 11 format is provided through DISPLAY.ERR LOG
if bit 0 of the Option Mask (field 5) =0. If bit 0 = 1, then
Header I is provided with a time stamp. The format of the time
stamp is hour/minute/second.
With either header, a data field is provided consisting of the year and Julian date.
Date is only valid when the customer sets it after every IPL using the SET.DATE command. Time is only valid when the customer runs DPPX with Timer Management and sets the time after every IPL using the SET.TOD command.
( 2) PA
Physical Adapter Address - Byte 0 of the FRB byte.
( 3) SCA
Secondary Component Address - Bytes 26, 27 of the FRB -N/A
( 4) OT
Device Type - 4007
( 5) OPTION Option Mask - Byte 4 of DPPX Header:
Bit 0 -
Bit 1 Bit 2 Bit 3-7 -
1 time stamp (Header I) 0 sequence number (Header 11) 1 BCLE present 1 Extended data present Specifies format for extended data
( 7) CRC
FDM Request Code (in hex) - Byte 1 of the F RB:
00 Initialize OB Close 69 Diagnose 6A Low priority start 6C Restart 6E Hold 7A High priority start
( 8) COMPSTAT Completion Status - Byte 2 of the FRB. Byte 2 has the following meaning:
Bit 0 Error Record Indicator Bit 1 Reenter Bit 2 Reenter FRB Indicator Bit 3 Reserved Bit4 Complete Bit 5 Error Bit 6 Exception Bit 7 - Attention
( 9) ARC
Adapter Return Code (in hex) - Byte 3 of the FRB. Valid entries are:
00 Normal Completion 01 Program Controlled Interrupt 02 FRB Busy 04 Equipment Check 06 ECC SuccessfuI 10 - Program Check 11 FR B Program Check 19 - Record Not Found
SY27-2521-3
REA 06-88481
5-FA·36
1A - Multisector Count Error 1B - Write Protect Error 20 - Unexpected Interrupt 21 - Adapter Parity Error 2A - Adapter Timeout 28 - Seek Check
33 - Data CRC Error - Primary
39 - Data CRC Error - Alternate 3A - ID CRC Error - Primary 3B - ID CRC Error - Alternate 62 - File Not Ready 63 - Data Unsafe 68 - File Speed Not OK
Note: The values in fields 8 and 9 represent the status of the adapter when it terminated its activity (either successfully or with an error) and returned control to DPPX.
(11) DATA Bytes 4-7 of the FRB.
(12) RES
Reserved - Bytes 8, 9 of the FRB - N/A.
(13) CNT Count - Bytes 10, 11 of the FRB.
(14) IOEP 1/0 Interrupt Entry Point - Bytes 12-15 of the FRB.
(15) ADWA Adapter Work Area Address - Bytes 16-19 of the F RB.
(16) CA
Channel Address - Byte 24 of the FRB - N/A.
(17) CPR
Channel Pointer Register - Byte 25 of the F RB - N/A.
(18) FRWA Function Request Work Area Address - Bytes 20-23 of the FRB. Contains address of FDM error log.
(19) RES
Reserved - Bytes 28-31 of the FRB - N/A.
001 (24)
Error Record Flag_s - Byte 0 of the FRWA. Defined as:
Bits 0-1 Bit 2 Bits 3-7
Reserved Partial Log Indicator Reserved
Note: If bit 2 is set, then the information in fields 001 through D 13 are not complete and not correct
(25) 002 (26)
(27) D03 (28)
FRB Byte 1 (Retry Count) - The number of retries attempted on the following operation before successful recovery or termination with error.
FRB Byte 2 (completion status) as logged on the initial detection of an error.
F RB Byte 3 (ARC) as logged on the initial detection of an error.
Data handler extended status (see FA233):
Bit 0 - Buffer A to File Bit 1 - File Speed Good Bit 2 - Write Protect 1 Bit 3 - Write Protect 0 Bit4 - Sector Displaced Bit 5 - Sector Reassigned Bit 6 - Sector Defective Bit 7 - Alternate Sector
(29) D04 (30)
(31)
D05 (32) (33)
D06 (34)
Residual Sector Count - Residual count of the number of sectors remaining for a multisector operation that has been terminated with an error (Bits 10-15).
Data handler basic status (see FA233):
Bit 0 - FCB Processor Error Bit 1 - Data Handler Error Bit 2 - CRC Error Bit 3 - ID Error Bit 4 - Data Field Error Bit 5 - Sector Not Found
Bit 6 - Equip Check/Halt Bit 7 - File Write Gate Error
Seek status (see FA233):
Bit 0 Bit 1 Bit 2 Bit 3 Bit4 Bits 5-7
- Tag Sequence Error - Command Error - FCB Processor Error - FCB Timeout Error - Cable Continuity OK - Seek Status:
000 - No MHS, FHS, RECAL in progress 001 - RECAL begun 010- FHS begun 100 - MHS begun 101 - MHS begun, FHS done 110 - MHS begun. FHS begun 111 - MHS done, FHS begun
MHS
Moving Head Seek
FHS = Fixed Head Seek
RECAL = Recalibrate
Data handler basic status See D04 (30) above.
Basic status (see FA233):
BitO
Program Controlled Interrupt
Bit 1 Device Error
Bit 2
File Interrupt Disabled
Bit3
Busy
Bit4 - Channel Request Frozen
Bit 5
Equipment Check
Bit6 - Requests Enabled
Bit 7 - Interrupt
Data handler basic status See D04 (30) above.
SY27-2521-3
(35) D07 (36,37)
FCB Processor status (see FA233): Bit 0 - 0 Bit 1 - 0 Bits 2-7 (in hex):
00 01
03 04 05 07,0F 11 27 2C
37 38 39 3A 3B 3C 3D 3E 3F
Idle state. Adapter waiting to make channel request, or continually servicing a hot file interrupt. Waiting for Channel Grant. OP decode state. Waiting for acknowledge signal from Data Handler. Waiting for proceed signal from Data Handler. Incomplete End-Op processing. Incomplete PCI processing. Waiting for seek completion before processing Data Op. End-Op processing delayed by outstanding seek. Multisector error Data Handler error File error (non-data) File error (data related) Data flow parity error Control sample timeout CH 10 equipment check Control bus parity error
Next Function Request (in hex) - FCB operation being executed.
Code
0000 0800 0900 OAOX 1000 18XX 20XX 21XX 23XX 24XX 26XX 28XX 29XX 30XX 34XX 38XX 3CXX 4200 4XXO 5XOO 60XX
Command
End-Op No-Op PCI (Program-Controlled Interrupt) Load Burst Register TIC End-Op Load Sector Count Read ID Normal Read ID Displaced Read ID PSC - Normal Read ID Compare Read ID Immediate Write ID Write ID Displaced Read Sector Normal Read Sector Compare Write Sector Normal Write Sector Compare Recalibrate Control Bus - Bit 4 of byte 1 set Store Memory Control Read Back Check Normal
(FA331 Cont)
5-FA-37
D08 (38,39) D09 (40,41) D10 (42,43)
D11 (44,45)
64XX 6XOO 70XX 71XX 78XX
8YYY 9YYY AYYY CYYY DYYY EYYY
Read Back Check Compare Buffer Diagnostic - Bit 4 of byte 1 set Read CRC Retrieve Format
Seek (Moving Heads) Seek (Moving Heads) Seek (Fixed Heads) Store New Track (Moving Heads) Store New Track (Moving Heads) Store New Track (Fixed Heads)
YYY bit layout= BBFHHHHC CCCCCCCC
where: BB= 10 =seek 11 = store new track
F = 1 = fixed head select 0 = moving head select
HHHH = head address
CCCCCCCCC =cylinder address
Examples (in hex):
1. Seek to moving head 5, cylinder 10 0 0101 1 00101000 128
2. Seek to fixed head 3 (cylinder 10 1 0011 CCCCCCCC address not applicable)
3. Store new track moving head 2, 11 0 0010 1 01100111 cylinder 167
4. Store new track fixed head 7
1 1 0111 C CCCCCCCC
(cylinder address not applicable)
Seek Register:
Bit 0 Bits 1-5
Bit 6
Bits 7-15-
Reserved Head Address Reserved Cylinder Address
FDM Flags - Condition Flags set by FDM for internal use.
File Status (see FA233):
Byte 1:
Bit 0 Bit 1 Bit 2
Bit 3
Bit 4 Bit 5 Bit 6
Bit 7
Fixed Head Not Selected Brake Applied Track Not Available Command Error
Data Unsafe Seek Incomplete Home Not Ready
Byte 2 - Reserved
File Sense 1 (see FA233):
Byte 1:
Bit 0 Bit 1
On Track Linear Region Normal and Even
SY27-2521-3
REA 06-88481
012 (46,47) 13 (48,49)
5-FA-38
Bit 2 Bit 3 Bit 4
Bit 5
Bit 6 Bit 7
Index and Sector Pulses Missing Out Direction Not Out Drive Not In Drive Tag Parity Error Velocity Profile Error
Byte 2 - Pulsing Information (same bit definition as Byte 1)
File Sense 2 (see FA233):
Byte 1:
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Behind Home Missing Clocks+ 2 Not Missing Clocks Error Latch Coil Current Low Missing Servo Signal Off Data Track Not Missing Position Error Signals Counter 5 In Sync
Byte 2 - Pulsing Information (same bit definition as Byte 1)
File Sense 3 (see FA233):
Byte 1:
Bit 0 Bit 1 Bit 2 Bit 3 Bit4 Bit 5 Bit 6 Bit 7
Not Shift Not (Off Track and Write) Inside AGC Window Not AGC Freeze Demod Pulsing Not (Read and Write) Not (Servo Protect and Write) Invalid Move
Byte 2 - Pulsing Information (same bit definition as Byte 1)
FA332 DPCX Condition/Incident log Formats and Meanings
Disk storage failures are stored in the OPCX condition/incident log in the Type 5 record format. Only those fields necessary for the FA MAPs are identified. See Chapter 2 (CP800) for complete error log details.
Type 5 Record
(1) 5-TYPE I-REC
(2)
(3)
SEO-XXXX PA-XX LA-XX D1-XX 02-XX 03-XX 04-XX
(4) 05-PL
06-XX
(5) 010-HESC
07-XX 08-XX 09-XXXXXX
(6)
011-HSSS
(7)
D12-HSBS
(8) D13-HSFE
(9)
014-NANB
015-SKRG
D16-XXX
(10) 017-FSOO
( 11) D18-AFAP
( 12) D19-BFBP
(13) 020-CFCP
021-XXXX
D22-XXXX D25-XXXX D28-XXXX
D23-XXXX D26-XXXX D29-XXXX
D24-XXXX D27-XXXX 030-XXXX
Type 5 Record Description
(1) Type 5 Indicates an extended variable incident record.
(2) SEO
A four-digit decimal number (0001-4095). This number identifies the relative time the incident occurred.
(3) PA
A two-digit number indicating the physical address of the FA adapter/device. (See FA 113.)
LA
(4) D5
PL - Partial Logout Bits 0, 1, 3, 4, 5, 6, 7 - Reserved Bit 2 - 0 = Complete Logout 1 = Partial Logout
(5) 010 (6) 011
Byte 1 =Data-Handler Extended Status (HE) (see FA233):
Bit 0 Bit 1 Bit 2 Bit3 Bit4 Bit 5 Bit6 Bit 7
Buffer A to File File Speed Good Write Protect 1 Write Protect 0 Sector Displaced Sector Reassigned Sector Defective Alternate Sector
Byte 2 = Residual Sector Count
Residual Sector Count is not used for intermittent problem determination.
Bits 8-15 Equal the number of remaining sectors for a multisector operation that was terminated with an error.
eyte 1 =Data Handler Basic Status (HS) (see FA233):
Bit 0 Bit 1 Bit 2 Bit3 Bit4 Bit 6 Bit6 Bit 7
FCB Processor Error Data Handler Error CRC Error ID Error Data Field Error Sector Not Found Equip Check/Halt File Write Gate Error
Byte 2 =Seek Status (SS) (see FA233):
Bit 0 - Tag Sequence Error Bit 1 - Command Error Bit 2 - FCB Processor Error Bit 3 - FCB Timeout Error Bit 4 - Cable Continuity OK Bits 5-7- Seek Status:
000 - No MHS, FHS, RECAL in progress 001 - RECAL begun 010 - FHS begun
REA 06-88481
SY27-2521-3
(7) 012
(8) D13 (9) D14
100 - MHS begun 101 - MHS begun, FHS done 110 - MHS begun, FHS begun 111 - MHS done, FHS begun
MHS =Moving Head Seek FHS = Fixed Head Seek RECAL =Recalibrate
Byte 1 =Data Handler Basic Status (HS)
(See 011 field bits 0-7.)
Byte 2 =Basic Status (BS) (see FA233):
Bit 0 Bit 1
Program Controlled Interrupt Device error
Bit 2 Bit 3
File Interrupt Disabled Busy
Bit4
Channel Request Frozen
Bit 5
Equipment Check
Bit 6
Requests Enabled
Bit 7
Interrupt
Byte 1 = Data Handler Basic Status (HS)
(See 011 field bits 0-7.)
Byte 2 = FCB Processor Status (FE) (see FA233): BitO - 0 Bit 1 - 0 Bits 2-7 in hex:
38
Multisector error
39
Data Handler error
3A
File error (non-data)
3B
File eror (data related)
3C
Data flow parity error
3D
Control sample timeout
3E
CHIO equipment check
3F
Control bus parity error
Next Function Request (in hex)
Hold the FCB operation currently being executed.
Code
Command
0000 0800 0900 OAOX 1000 1800 20XX 21XX 23XX 24XX 26XX 28XX 29XX 30XX 34XX
End-Op No-Op PCI (Program Controlled Interrupt) Load Burst Register TIC End-Op Load Sector Count Read ID Normal Read ID Displaced Read ID PSC - Normal Read ID Compare Read ID Immediate Write ID Write ID Displaced Read Sector Normal Read Sector Compare
(FA331 Cont, FA332)
5-FA-39
D15 (10) D17
(11) D18
38XX 3CXX 4200 4XXO 5XOO 60XX 64XX 6XOO 71XX 78XX SYYY 9YYY AYYY CYYY DYYY EYYY
Write Sector Normal Write Sector Compare Recalibrate Control Bus - Bit 4 of byte 1 set Store Memory Control Read Back Check Normal Read Back Check Compare Buffer Diagnostic - Bit 4 of byte 1 set Retrieve Format Seek (Moving Heads) Seek (Moving Heads) Seek (Fixed Heads) Store New Track (Moving Heads) Store New Track (Moving Heads) Store New Track (Fixed Heads)
YYY bit layout= BBFHHHHC CCCCCCCC
where: BB= 10 =seek 11 = store new track
F = 1 = fixed head select
0 = moving head select
HHHH = head address
CCCCCCCCC =cylinder address
Examples (in hex):
1. Seek to moving head 5, cylinder 10 0 0101 1 00101000 128
2. Seek to fixed head 3 (cylinder address not applicable)
0 1 0011 C CCCCCCCC
3. Store new track moving head 2, cylinder 167
4. Store new track fixed head 7 (cylinder address not applicable)
11 0 0010 1 01100111
11 1 0111 c cccccccc
Seek Register:
Bit 0 - Reserved Bits 1-5 - Head Address Bit 6 - Reserved Bits 7-15- Cylinder Address Byte 1 =File Status (FS) - (in hex) (see FA233):
Bit 0 - Fixed Head Not Selected
80
Bit 1 - Brake Applied
40
Bit 2 - Track Not Available
20
Bit 3 - Command Error
10
Bit 4 - Data Unsafe
08
Bit 5 - Seek Incomplete
04
Bit 6 - Home
02
Bit 7 - Not Ready
01
Byte 2 = Reserved
Byte 1 =File Sense 1 (AF) - (in hex) (see FA233):
Bit 0 On Track
80
Bit 1 - Linear Region Normal and Even 40
SY27-2521-3
REA 06-88481
(12) D19 (13) D20
Bit 2 - Index and Sector Pulses Missing 20
Bit 3 - Out Direction
10
Bit 4 - Not Out Drive
08
Bit 5 - Not In Drive
04
Bit 6 - Tag Parity Error
02
Bit 7 - Velocity Profile Error
01
Byte 2 =Pulsing Sense 1 (AP) (same bit definition as Byte 1)
Byte 1 =File Sense 2 (BF) - (in hex) (see FA233):
Bit 0 Behind Home
80
Bit 1 Missing Clocks+ 2
40
Bit 2 Not Missing Clocks Error Latch 20
Bit3 Coil Current Low
10
Bit4 Missing Servo Signal
08
Bit 5 Off Data Track
04
Bit 6 - Not Missing Position Error Signals 02
Bit 7 - Counter 5 In Sync
01
Byte 2 =Pulsing Sense 2 (BP) (same bit definition as Byte 1)
Byte 1 =File Sense 3 (CF) (see FA233):
Bit 0 Bit 1 Bit 2 Bit3 Bit4 Bit 5 Bit6 Bit 7
Not Shift Not (Off Track and Write) Inside AGC Window Not AGC Freeze Demod Pulsing Not (Read and Write) Not (Servo Protect and Write) Invalid Move
Byte 2 = Pulsing Sense 3 (CP) (same bit definition as Byte 1)
5-FA-40
FA340 How to Use the Error Log
The procedure for examining the error log depends upon whether the customer is using DPPX or DPCX. For the DPPX operating system, see FA341; for DPCX, see FA342.
FA341 Using the DPPX Error Log
Examine the error log for the failing DSD. Using FA331 (DPPX Error Log Formats and Meanings) identify the latest error log with a complete logout of the most frequent failure type (Field D01 =hex OOXX for a complete logout and hex 20XX for a partial logout). Also a complete logout has valid pulsing bits in Fields 45, 47, and 49. If there are no complete logout records, use the latest partial logout record. When instructed to by the MD display, enter the requested data fields from this error tog. The MD will display the action plan. To verify the repair, return the system to the customer. Obtain a new error log after the customer has used the system. End the repair action when there are no FA failures in the error log.
FA342 Using the DPCX Condition/Incident Log
Examine the condition/incident log records for the failing DSD. Using FA332, identify the latest condition/incident log with a complete logout of the most frequent failure type (Field D5 =hex 00 for a complete logout and hex 20 for a partial logout). Also a complete logout has valid pulsing bits in Fields D18, D19 and D20. If there are no complete logout records, use the latest partial logout record. When instructed to by the MD display, enter the requested
data fields from this log record. The MD will display the action plan. To verify the repair, return the system to the customer. Obtain a new error log after the customer has used the system. End repair action when there are no FA failures in the error log.
FA350 Action Plan to Correct Intermittent Failures This procedure assumes that there is an intermittent hardware failure. It is also possible, however, that the problem may be a defective/intermittent ID or data field on the customer surface. Since the diagnostic tests utilize only the CE track (359), customer surface problems will not be detected. In such cases, it is recommended that the Surface Status and Format utility be run on the entire file (refer to CP653).
1. The offline tests should have been run. a. If they have not been run, go to FA250. b. If there were random errors, go to step 2. c. If the tests were looped without error for five passes, go to step 8.
2. Obtain the error log for failing DSD physical address (PA). Refer to Chapter 2 (CP700 for DPPX; CP800 for DPCX) for information on obtaining the error log.
3. Enter into the MD the information from the latest complete logout record of the most frequent type of failure (see FA340). If there are no complete logouts, use the latest partial logout.
4. The MD display recommends FRU replacements or possible causes of failure in the order of probable cause. Replace and record the FR Us. (If, after all recommended FRUs have been replaced, the problem still exists, request aid.)
5. Loop the tests for five passes. Enter "F" into the MD keyboard to end looping. If there is a failure, the MD will continue prompting.
6. Return the system to the customer. 7. End Repair action when there are no more DSD failures in the error log after a satisfactory
period. 8. If the drive has fixed heads installed, run Routine 50 in free-lance mode (this is a special
test for "write" capabilities of the fixed heads). If there are no fixed heads or Routine 50 runs without error, go to step 2.
REA 06-88481
SY27·2521-3
(FA332 Cont-FA350)
5-FA-40.1
SY27-2521-3
REA 06-88481
This Page Intentionally Left Blank
5-FA-40.2
FA400 Signal Paths and Detailed Operational Description
FA2 Data Handler Card
Th is section contains card socket wiring charts, board and card jumpers, and detailed operational description.
FA410 Card Socket Wiring Charts
This section shows the card pins and associated line names. Where possible, input/output directions are shown with arrows. See FAl 11 for card locations.
FA1 FCB Processor Card
5C5 5C5 5C5 5C5 5C5 5C5 SC5 SC5 SC5 SC5 5C5 5C5 5C5 5C5 5C5 5C5 5C5 5C5 SC5 SC5 SC5 SC5 5C5 5C5 FA2 FA2 FA2 FA2 FA2 FA2 FA2 FA2 FA2 FA2 FA2 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4
- data bit P (0-7) - data bit 0 -data bit 1 -data bit 2 -data bit 3 -data bit4 - data bit 5 - data bit6 - data bit 7 - data bit P (8-15) -data bit 8 - data bit 9 - data bit 10 - data bit 11 -data bit 12 -data bit 13 - data bit 14 - data bit 15 - ch grant low - system reset -TA tag - 1/0 tag - halt tag -TD tag - DH stat bit P - DH stat bit 0 - DH stat bit 1 - DH stat bit 2 - DH stat bit 3 - DH stat bit 4 - DH stat bit 5 - DH stat bit 6 - DH stat bit 7 +continuity to ctr1 ad - clock ring reset· - control bus bit P* - control bus bit O* - control bus bit 1* - control bus bit 2* - control bus bit 3 * - control bus bit 4* - control bus bit 5* - control bus bit 6* - control bus bit 7* -cntl sample recd - file interrupt
P10 504 U11 507 U05 U10 513 508 M10 U12 509 510 U02 505 U13 U04 U07 512 G03 M05 MOB D13 J04 P02 D07 D12 D10 D06 810 D11 502 D09 D02 M07 J05 J12 J10 J09 803 J07 GOS M04 M03 P04 804 805
812 - int/req/bus in 0 808 - end of chain 809 - IRR G02 - valid halfword D05 - parity valid
3 J02 - ch req low
D04 +9MHz G09 J11 813 - 4V reg JOO + file bus degate G07 - tag bit p G12 - tag bit 2 G10 - tag bit 1 G13 -tag bit 0 M12 - control sample POO - data select
3 M13 - reset error
G04 - ch grant low pass (TP)
802 +sample clock (TP) G05 J13 P05 ] + gate bus driver on (VE) U06 D08 ground 807 - tie down M02 M09 P09 P11 P12 P13 U09
5C5 SC5 5C5 5C5 SC5 FA2 FA2 FA2 FA2 FA2-FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4-FA5
Volts
PA +5 voe PA +a.5 voe
PA-5VDC PA Ground
*Bi-directional bus
(TP) = test point
Pins
003, J03, P03, U03 B11,G11,M11,511 800, GOO, M06, 506
008, JOB, P08, uoa
REA 06-88481
SV27-2521-3
5CF +gate bus driver on (VE) G10
5C5 - system reset
G09
SC5 - release
J13
FA1 -4V reg
813
FA1 +9 MHz
510
FA1 +file bus degate
J12
FA3 1F read clock
G07
FA3 1F write clock
JOO
FA3 + NRZ data
GOS
FA3 + write gate return
M04
FA5 - index
803
FA5 - sector
004
FA5 - sector pulses missing
009
+ write Ioad (TP)
[ 804
805
+gate P clock (TP)
[ 807
+select clock (TP)
r2808 013 G02
G03
J02
+byte start (TP)
[ J04
J10
Volts
PA +5 voe PA +a.5 voe PA-5 voe
PA Ground
(TP) =test point
Pins
003, J03, P03, U03 811,G11,M11,S11 800, GOG, MOS, 506 008, JOB, POS, UOB
007 - DH stat bit P
FA1
012 - DH stat bit 0
FA1
010 - DH stat bit 1
FA1
000 - DH stat bit 2
FA1
810 - DH stat bit 3
FA1
011 - DH stat bit 4
FA1
802 - DH stat bit 5
FA1
809 - DH stat bit 6
FA1
002 - DH stat bit 7
FA1
G12 - clock ring reset
FA1
M02 +continuity from cntl FA1
J09 - fast sync
FA3
J11 -write data
FA3
3G13 - write
J07 - read
008
g'ound
FA4 FA4
G05 - tie down
M03
U10
(FA400 - FA410)
5-FA-41
FA3 Data Channel Card
FA2 FA2 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA5 FA6 FA6 DE DE DE DE DE DE DE
- fast sync -write data - head select 1 - head select 2 - head select 4
- head select s
+ write select + read select - servo unsafe + common reset - fixed head select +write clock -AGC freeze
2F write clock + servo VCO inhibit
center taps actuator 1/0 line A actuator I/0 line 8 fixed head 1/0 line A fixed head 1/0 line 8 M safety
+ data select gated
- I write select (TP) - read actr (TP) - 1.32V int (TP)
+ 5.8V int (TP)
- read fixed heads (TP) - diff analog signal (TP)
write I def res (TP) diff analog signal (TP) AGC ref volt (TP) - multi module select (TP) + IW error squelch (TP) trans error (TP) - 1 .32V ref (TP) - sat squelch (TP) - heads grounded (TP) + write DC (TP) AGC control volt (TP) +inhibit trans error (TP)
S02 U02 P07 P05 P10 P06 G13 J12 M02 M03 M05 J06 804 M10 U06 G03 005 006 010 009 011 P12 805 807 808 809 810 813 004 013 G02 G04 G05 G07 GOS G09 G11 G12 J02 J04
Volts
PA + 5 voe PA + 12 voe
PA Ground
PA -4 voe PA -12 voe
(TP) = test point
Pins
003, JOO, P03, U03 811
DOS, J08, POS, uoa
806, GOS, M06, S06 012
507 J07 U07 U11 G10 U12 802 803 P11 812 M04 P04 P09 M11 M09 MOS M07 007 J05 J09 J10 J11 J13 M12 M13 P02 P13 503 504 505
soa
509 510 511 512 U04 U05 U09 U10 U13
+NAZ data +write gate return
1F read clock 1F write clock +data unsafe 1F wrt elk ungated to PLO - buffered analog data A - buffered analog data 8 data servo 2F burst - M positive supply head select A head select 8 - module select 1 - module select 2 - module select 3 - module select 4 - module select 5 write current - IW during read (TP) transient blanking (TP) - multi module sel error (TP) - head ground error (TP) shift reg shift pul (TP) - servo sample (TP) inhibit SS (TP) - operation (TP) data (TP) combined data (TP) OP ext (TP) tie up (-0.SV) (TP) test data l/P (TP) 1F read clock MST (TP) zener +2V (TP) increase (TP) decrease (TP) +gate test data (TP) internal fast sync (TP) high current (TP) data SS (TP)
veo error signal (TP)
FA2 FA2 FA2 FA2 FA4 FA5 FA6 FA6 FAS DE DE DE DE DE DE DE DE DE
SY27-2521-3
FA4 Logic Card 1
FA1 FA1 FA1 FA1 FA1 FA1 FA1 FA1 FA2 FA2 FA3 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FA5 FAS FAS FA7 FA7 FA7 FA7
+file bus degate - control sample - tag bit P - tag bit 0 - tag bit 1 -tag bit 2 - reset error - data select -write - read + data unsafe
profile gain voltage +half track (REL) - go home or P.O.F.L. + brake applied (logic)
missing clocks 2 - index sector pulses +servo protect
pulsing and O/P - in drive +missing servo sig latch +byte cntr bit 16 - count down 2 tracks - count up 2 tracks +not ready +quarter track (REL) + lin reg N of even trk + behind home - AGe freeze + out direction - missing elk err latch - seek complete - out drive +ROS DA error +move not valid - ABS track address 1 +home - cntr 5 out of sync + seek timeout - outside AGe window + off data track +on track +low coil current - power on delay - bad AGe level
803 G09 MOS P07 M07 M09 S10 J13 G12 J11 M11 802 804 806 BOS 810 GOS G10 M10 M13 S02 S03 505 506
sos
D04 D11 013 J02 J07 J09 P11 U02 U04 U05 U06 U07 U10 U13 G03 G13 812 G07 S13 U11
Volts
PA + 5 voe PA + 12 voe
PA Ground
PA -12 voe
*Bidirectional bus
Pins
D03, J03, P03, U03 811 DOS, JOB, POS, UOS 012
(TP) = test point
5-FA-42
P04 M04 P02 M03 M02 M05 P06 P05 M06 006 P09 P12 P10 J06 G02 G11 S11 J12 U12 U09 009 813 G04 G05 M12 S07 002 005 007 J05 509 512 805 807 809 D10 GOG J04 J10 P13 504
- control bus bit P*
FA 1
- control bus bit 0*
FA 1
- control bus bit 1*
FA 1
- control bus bit 2*
FA 1
- control bus bit 3*
FA1
- control bus bit 4*
FA 1
- control bus bit 5*
FA 1
-controlbusbit6*
FA1
- control bus bit 7*
FA 1
- file interrupt
FA 1
-cntlsamplerecd
FA1
- head select 1
FA3
- head select 2
FA3
- head select 4
F A3
- head select S
F A3
+write clock
FA3
- servo unsafe
FA3
+ read select
F A3
+ write select
F A3
+ common reset
F A3
- fixed head select
F A3
- shift
FA5
-gohomebtt
FA5
- calibration address
FA5
+ head 1 selected
F A5
- set seek
FA5
+desired velocity
FA5
- reset calibration
F A5
- tag 001 clock 2
FA5
+out
FA5
- even
FA6-FA7
+ data select gated
DE
- tag 010 CS (TP)
EMROS parity (TP)
- force DAC 0/P to 0 (TP)
+ rel trk addr 12S (TP)
- tag 001 CS no fxhd (TP)
+track unavailable (TP)
+ 1/2 TTG (TP)
+data 5110 (TP)
+common reset (TP)
FA5 Logic Card 2
FA1 FA3 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA7 FA7 FA7 FA7 FA7 FA7 FA7 FA7 FA7 DE DE
- reset error
P13
1F wrtcl k ungated to PLO J05
+desired velocity
802
- calibration address
MOS
- set seek
M12
- shift
S04
- tag 001 clock 2
S09
- fixed head select
J04
+ head 1 selected
P09
- reset calibration
P11
- go home bit
P12
+out
U02
- Q/2 error
807
coil current signal
809
+servo clock SS
G05
- power good delayed
M09
+ N/2 error
S12
+ Q/2 error
J07
- missing servo clock
P06
- power on delay
U09
- N/2 error
U12
compensation coil
004
compensation coil (GNO) POS
+ vel >profile (TP)
804
+counter 5 (TP)
812
+ (G + N) (TP)
G06
- common reset (TP)
G12
+ quad error (TP)
M05
-cntr4 (TP)
M06
rel track addr 128 (TP) M10
+ V timeout (TP)
M11
handover vel (TP)
503
dedicated ready (TP)
511
- hybrid velo (TP)
002
QSW (up open) (TP)
J11
NSW (up closed) (TP)
J12
+seek timeout SS (TP)
U05
Volts
PA +5VDC PA + 12 voe PA +24 voe PA Ground PA -12 voe
(TP) =test point
Pins
000 I JOO, P03' U03 811 $02 008, JOB, P08, UOS 012
GOB S10 S13 G09 803 805 808 810 G07 M02 M03 M04 M07 M13
sos
005 007 009 010 P02 P04 P05 P10 U06 U10 U11 S07 006 J13 P07 U07 813 013 J02 J09 J10 U1.3 G02 GOO J06 G04 G13 S05 011 U04 G10 G11
- sector pulses missing - sector -index -AGC freeze +fin reg Nor even track - ABS track address 1
profile gain voltage +quarter track (REL) -cntr 5 out of sync +missing servo sig latch - missing elk err latch
pulsing and 0/P +not ready + seek timeout +byte cntr bit 16 -count up 2 tracks -count down 2 tracks +ROS DA error +half track (REL)
missing clocks 2 + move not valid - index sector pulses +home + servo protect - go home or P.O. F. L. +behind home - in drive + out direction - seek complete +brake applied (logic) - out drive - osc early + head change gate - osc late +shift reg clock +enable servo sample +enable mark detect - select demod 02 -select demod 01 - select demod N2 - select demod N1 + normal error - select integrator +seek - sector integrator
brake coil 1 brake applied to power
FA2 FA2 FA2 FA3-FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4 FA4-FA7 FA4-FA7 FA4-FA7 FA4-FA7 FA4-FA7 FA6 FA6 FA6 FA6 FA6 FA6 FA7 FA7 FA7 FA7 FA7 FA7 FA7 FA7 DE PA
FA6 Servo Card 1
FA3 FA3 FA3 FA4 FA5 FA5 FA5 FA5 FA5 FA5 FA7 FA7 FA7 FA7
buffered analog data A 803
buffered analog data B 002
data servo 2F burst
GOB
- even
J06
+ enable mark detect
G04
- osc early
G07
+shift reg clock
G10
+ head change gate
011
+ enable servo sample
J04
- osc late
J07
VTP 1 ref
804
+on track
G13
- 7 volts
010
- dedicated SW PES
013
+ AGC control (TP)
802
veo (TP)
805
reset bucket
807
linear data sig (TP)
808
- reset cap (TP)
810
+ positive zero crossing (TP) [812
G05
Volts
PA +5VOe PA + 12 voe PA Ground PA -4VOe PA -12 voe
(TP) = test point
Pins
003, JOO 811 008, JOB 806, G06 012
GOO G12 009 J13 813 G02 G11 GOS 809 004 005 006 007 J02 J05 J09 J10 J11 J12
+servo VCO inhibit 2F write clock
- outside AGC window +off data track
data PES +select demod A (TP) -8 (TP) -0 (TP) -G (TP)
AGe ref (TP) + 6 volts (TP)
linear data signal (TP) +select gain adj (TP) + demod 8 (TP) - counter run (TP) - bit 0 (TP) + enable data (TP) - enable data (TP)
2F write clock (TP)
FA3 FA3 FA4 FA4 FA7
SY27-2521-3
(FA410 Cont)
5-FA-43
FA7 Servo Card 2
FA4 FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS DE DE PA
-even
803
- select demod 01
808
- select demod 02
809
- select dem ad N 1
009
- select demod N2
810
+normal
812
+brake applied (logic)
M02
- out drive
M13
- seek complete
S07
+seek
sos
+out direction
S13
- select integrator
POS
+select integrator
P07
- in drive
P11
data PES
P06
+ 24V common
S09
- servo preamp 0/P
DOS
+servo preamp 0/P
006
-power good
G10
tribits (TP)
802
hybrid PES Q (TP)
G04
on track threshold c ntl (TP) GOS
hybrid PES (TP)
(G09 J11
ret spring curr comp (TP) M03
integrator (TP)
M07
+ M servo clock (TP)
M09
notch filter amp 0/P (TP) M10
base 179 in (TP)
S03
+ NSW (TP)
512
+VGA (TP)
004
+ sw sequence (TP)
J02
hybrid PES N (TP)
J09
-comp I 0/P (TP)
J13
integrator O/P (TP)
P04
Volts
PA +5VDe PA + 12 voe PA +24 voe PA Ground PA -~voe PA -12 voe
(TP) = test point
Pins
003, JOO, P03
s 805I 811 , G 11 I M11, 11
G02 DOS, JOB, P08, U08 806, GOO, MOO, S06 D12,J12, P12, U12
G03 +low coil current
J04 - bad AGC level
G12 +on track
P02 - power on delay
804 +servo clock SS
G13 - missing servo clock
MOS - N/2 error
S02 + 0/2 error
S10
coil current signal
011 - 0/2 error
013 + N/2 error
P09 - power good delayed
807
VPT 1 ref
002 - dedicated SW PES
D10 -7volu
3 J10
P10 U10
M12
base PNP out
sos
CSR out
U02
base NPN out
U04
base NPN in
UOS
CSR in
U07 base PNP in
M04
VCM finish
M05
VCM start
S04
SPA -8V
J05
DE adj res B
JOB
DE adj res A
P13
base 179 out (TP)
U03 - servo offset inj (TP)
U09
driver preamp SS (TP)
U11
pre-driver 1/P (TP)
U13
servo offset (TP)
FA4 FA4 FA4-FA6 FA4-FA5 FA5 FAS FA5 FAS FAS FAS FAS FAS FA6 FAS FA6
FAS FAS FAS FAS FAS FAB FAS-DE FAB-DE DE DE DE
SY27-2521·3
FAB Voice Coil Motor (VCM) Drive Card
(Located on the side of the 01X-A1 Gate.)
Base PNP Out Base NPN In Base NPN Out Base PNP In
VCM Card
CSR In CSR Out
P7 1 2 3 4
PS 1 2
5-FA44
P Connector as viewed when plugged
VCM Start VCM Finish +24V Common +24V
P10 1 2 3 4
FA9 Terminator Card
+Tag 2 +Tag 1 +Tag 0 + Tag parity
+ SV
+ SV
+ SV
continuity check
B02 002
803 003 <E--1
B04 004 ~ 806 005 ~ 806 006 ~ 807 007 ~ 80S DOS ~ 809 009 EB10 010 ~ 811 011 ~ 812 012 ~ 813 013 ~
X-A1A4 Note: Numbers indicate common connections.
continuity check + SV + control bus 0 + control bus 1 + control bus 2 + control bus 3 +ground + control bus 4 + control bus 6 + control bus 6 + control bus 7 + control bus P
Adapter to Drive Cables, (CC) and (OD)
CONNECTIONS
The routing of this cable depends on the Unit 8130, 8140, or 8101
Brake Cable
24V} ++ 24V
+ 12V
From Power Supplies
+ 5V
-4V
-12V
J1-2 - Power Good - From power supply logic
Ground - From power supply logic
J5-1 - Brake Applied - To power supply logic
To the Drive Motor
:;if1'.
'~-:: ~
,- -,
: : .r...
I I l'\.J
I'--·I - - r - - ., ... -'
I I
I I A4
:
,_
-'I
-,.. -~
r...--~
To Cooling Fan
ac voltage
~This supply is independent of the motor supply so that the cards have cooling during servicing of the DSD.
(CC)
+tags bit 2
~ BQ2 0 0
+tags bit 1
~ 803 0 0
+tags bit 0
~ 804 0 0
+tags bit P
~ 805 0 0
806 0 0
807 0 0
808 0 0
809 0 0
810 0 0
811 0 0
+ control sample rcvd ~ 812 0 0
+ continuity
~ 813 0 0
D02--? +continuity to adapter
003004~ +control bus bit 0 D05~ + control bus bit 1 D06~ +control bus bit 2 007 ~ + control bus bit 3 D08~ +ground D09~ + control bus bit 4 010~ +control bus bit 5 D11 ~ + control bus bit 6 D12-e-- + control bus bit 7 D13~ +control bus bit P
Control Cable (CC) Dedicated Cable (DD)
+ continuity from adapter ~ 802 0
+ control sample
~ 803 0
+ disk interrupt
~ 804 0
- sector
~ 805 0
806 0
+ ground + NAZI data
~ 807 0 ~ 808 0
- sector pulse missing
~ 809 0
-write data
+ disk bus degate + ground
~ 810 0
811 0
~ 812 0
~ 813 0
0 D02~ +ground
0 003~ - write gate return 0 D04 E-- + data select
0 005 E-- - fast sync 0 006 E-- + reset error 0 D07~ - index 0 DOB E-- +ground
0 009~ - read select 0 010~ + read clock 0 011 E-- - write select 0 012~ + write clock
0 013 ----+ + continuity
;(DD)
REA 06-88481
SY27-2521-3
(FA410 Cont)
5-FA-45
Drive Logic Board to DE Cables, (FA) and (MH)
Pin connections and signal titles for both the fixed and moving head flat cables are shown.
Flat Cable
A1Y1 * (FH)
A1A2 (MH)
Card Gate with Cover Removed, Showing (MH) and (FH) Plug Positions
*(FH) is installed only when the fixed head feature is installed.
802
803
804
805
To
806 807
A1A2 808
809
810
811
812
813
D B ,.,
2 00
00
00 00 00 00 00
00 00
Oo 0 u
13 00 ....
002
003
004
005
006
To
007
A1A2 008
009
D10
D11
D12
D13
SY27-2521-3
Line Name
-Chip Select 3
Head Select A
Head Select B
-Chip Select 2
..
Chip Select 1 Mars Safety
Center Taps
Not Used
Servo Center Tap
-8 Volt (Servo Write Current)
B Volt (Servo Write Data A)·
+Data Select Gated
r0- -1
I
r---
Ir--
---- ---- ---
-
--- ··
I
I
I (MH)
I
I
L
_
I .....J
-- ----------·--
Through Base Casting
0
Line Name
To Moving
Heads
+ Data Select Gated
+6 Volts
Actuator 1/0 Line A
Actuator 1/0 Line B
4 Volts
Write Current
Ground
..
8 Volts +Servo Preamp Out
Servo Preamp Out
Ground
8 Volts (Servo Write Data B)
·p1ant use only
Line Name
Center Taps
Chip Select 4
Head Select A
Head Select B
Write Current + 6 Volts
Ground Fixed Head Input/Output Line A Fixed Head Input/Output Line B ~
Ground -4 Volts
Ground Chip Select 5
Unsafe
+Data Select Gated
+Data Select Gated
...
A1C13 A1811 A1E13 A1C11 A1011 B1A13 B1ABC11 81813 B1C13 B1ABC11 A1013 B1ABC11 A1E11 81011 A1813 C1C11
To A1Y1
olo oIo 0 0 0
00 0
0 0
13
oIo 1: Al
I
81
c 0 0 0
0 0
BcDE AB
0 0
D E
Cl
0 0
B c
11
To Fixed Heads
Through Base Casting
(FH)
5-FA-46
Top Card Connectors W, X, Y, and Z
- dh valid - dh eoc - sync cl k (c) + dflow bus bit 2 + spiral 1 + dflow bus bit 5 - gt in status - ctl csr - XXX clock + ground
+ dflow bus bit 6
+ dflow bus bit 1
+ dflow bus bit 0 - nfr sel - dhi 1 + dflow bus bit 3 - sync clock (p) + cs attached + XXX b clki + buffer rd - time out +ground - file window - XXX clock
reserved reserved - proc lo int 15
- PW proc lo
- RWS hi int 7 - proc lo int 13 - RWS lo int5 - RWS lo int 7 - RWS lo int6 +ground - proc hi int pO - proc hi int 5
- proc hi int 3 - proc lo int 10 - proc lo int 9 - proc lo int 8 - RWS hi int4 - proc hi int 0
+ burst reg bit 4
-RWS hi int 1 -RWShi into +ground -RWSlo int2 - proc hi int 2
<-- 1W22 W02
~ jvv23 W03
~ jw24 W04
--+ W25 W05 --+ IW26 W06
~ W27 W07
~ W28 wos
--+ W29 W09
--+ W30 W10
~ W31 W11 ~ W32 W12 ~ W33 W13
--+ X22 X02
-E-- X23 X03
~ X24 X04 ~ X25 X05
E--- X26 X06
--+ X27 X07
X28 X08
<E-- X29 X09
~ X30 X10 X31 X11
~ X32 X12 ~ X33 X13
Y22 Y02
Y23 Y03
-7 Y24 Y04 -E-- Y25 Y05 -E-- Y26 Y06 -7 Y27 Y07 -E-- Y28 Y08 <E-- Y29 Y09
~ Y30 Y10 Y31 Y11
~ Y32 Y12
---+ Y33 Y13
~ Z22
-7 Z23 -7 Z24
~ Z25 -E-- Z26
~ Z27 ~ Z28 ~ Z29
~ Z30
Z31 ~ Z32
~ Z33
Z02 ~ Z03 ~ Z04
Z05 ~ Z06 ~
Z07 -+
zos
Z09 ~ Z10 ~ Z11 ~ Z12 ~ Z13 E--
- dh csr - sync elk (b) +ground + dflow bus bit 7 - sampled td - td sync + spiral 2 - sync cl k (b) + dfl ow bus pty - sync clock (c)
+ gt dh X St
-dhi 0
+ dflow bus bit 4 + skip factor 1 +ground - dhctl/ops 0 + dflo sel - dhctl/ops 1 - proc window 1 - proc busy - XXX clock - equipment check + dfhi sel - proc window 2
+ burst reg bit 1 + cable continuity out +ground - pty proc hi - RWS hi int6 + burst reg bit 2 - reset - proc lo int 14 - RWS hi int 5 - proc hi int 7 - proc hi int 6 - proc lo int p1
- proc lo int 11 - proc hi int 4 +ground -RWSloint3 - RWS hi int3
- RWS hi int 2
reserved -RWS1oint4 -RWSlointO - RWS lo int 1 - proc lo int 12 - proc hi int 1
Top Card Connector (Pin Side)
·· --2
-13··.·······
2·
'I···-···331~······'···
········ 22 I·· 33
Each top card pin is connected to the corresponding pin on the other card.
Example:
FA 1 W02 to FA2 W02 FA1 X22 to FA2 X22 FA1 Y33 to FA2 Y33 FA1 Z13toFA2Z13
SY27-2521-3
(FA410 Cont)
5-FA-47
FA420 Adapter to Disk Drive Interface Description
Control Bus (CC)
Control Bus Bits 0-7 and Parity. This section of the control bus is used to transfer data to and from the DSD. The decode of the three tag bits determines the significance and direction of data flow. Parity is checked by the DSD for incoming data and generated for outgoing data.
Tag Bus Bits 0, 1, 2 and Parity. The three tag bus bits are decoded to eight control lines as shown in the table below:
Tag Bits
0
1
2
Meaning
0
0
0
Interrupt Control
0
0
1
Head Selection
0
1
0
Track Selection
0
1
1
Diagnostic Wrap
1
0
0
Sense
1
0
1
Diagnostic Sense 1
1
1
0
Diagnostic Sense 2
1
1
1
Diagnostic Sense 3
Tag 000 Interrupt Control. The 000 and bit 1 on the bus suppresses the '-seek complete' interrupt. Tag 000, and not bit 1, resets the condition. Any suppressed interrupt will now become active.
Tag 001 Head Selection (Seek Control). Tag 001 gates control bus bits 5-0 to the head address register. Bit 7 is gated to the desired address register bit 256. Bit 6 is unused.
Tag 010 Track Selection (Required Address). Tag 010 gates the control bus bits 7-0 into the desired address register bits 1-128 respectively.
Tag 011 Diagnostic Wrap Back. Tag 011 gates the low order bits (1-128) of the desired address register, back to the control bus for wrap around transmission back to the using system.
Tags 100, 101, 110 and 111. These tags gate sense and status information onto the control bus. ·For details of sense and status lines, see FA233.
'-Control Sample Received'. This line is activated by the DSD after it reads the tag lines and, if necessary, the control lines following a 'control sample' signal from the system controller.
SY27-2521-3
5-FA-48
Dedicated Cable (DD)
'-Control Sample' (Input to DSD from System). The control bus is looped through up to four DSDs and the information carried is available to them all. ' - Control sample' can only be active on one DSD at any time and is ANDed with the 001 or 010 tag decbdes to gate head or track selection into the correct DSD.
'-Control sample' also generates'+ enable bus' for any tag other than 001 or 010 which gates sense and status to the control bus.
'+ Interface Driver Degate'. This line disables the control bus, control bus parity, and control sample received.
'- Reset Error'. This line is used to reset the 'data unsafe' or 'command error' sense bits. It may also be used to clear an interrupt.
'-Write'. This line activates the 'write' circuits in the DSD. It causes the 'write' current source to be turned on.
'- Read'. This line with 'data select' causes the data separator to decode data read from the disk, and present it on the 'NAZI' data line.
Note: '-Write' and'- read' are mutually exclusive. An error interrupt occurs if they are both active at the same time.
'-Data Select'. This is only active in one DSD at any time. It is used to gate'- write' or '-read'.
'-Write Data'. This is serial binary data for writing to the disk. '-Write data' is synchronized with'- write clock'.
'- Fast Sync'. This line must be activated to synchronize the data separator: 1. Before Reading ID 2. Before Reading Data 3. For Displaced Sector ID
Output Lines from DSD to System '- 1F Write Clock'. Synchronized to servo clock, pulses from the servo surface'- 1F write clock' are used by the using system to synchronize write data.
'- Read Clock'. Derived from raw 'read' data by the data separator.
'+ NRZ Data' to System. This line is the output from the data separator denoting 1's by an up level, and O's by a down level.
'-System Index'. '-System Index' indicates the track start to the using system. It is derived from data in the dedicated servo area just prior to the start of the first sector on any track.
'-System Sector'. '-System Sector' is similar to '-system index' but indicates the start of all sectors after the first. It is derived from the dedicated servo area.
·-Sector Pulses Missing'. This indicates to the using system that the DSD failed to detect one or more sector or index pulses at the time that one was expected.
·-Interrupt'. An Interrupt is raised by any one of the following: · Seek Incomplete · Not Ready · Data Unsafe · Command Error · Brake Applied · Track Unavailable
'+Write Gate Return'. This indicates to the using system that the write current has been switched on.
'+Dedicated Ready'. This indicates to the system that the DSD is 'ready'.
Individual Cabling Via Voltage Crossovers ·-Power Good'. This is active only when all power lines are within tolerance. When inactive, it causes the DSD brake to be applied immediately.
·+Brake Applied'. This indicates to the system that the brake has been applied either due to an unsafe or error condition, or due to brake failure. The system will respond by removing ac power from the motor within 5 seconds of'+ brake applied' becoming active.
FA430 Not Used
FA440 Jumpers FA441 Board Jumpers
The only board jumper used is the file degate jumper from C-A 1A5812 to C-A 1A5B 13. This jumper must be installed for proper disk operation. However, the MD instructs you to remove it for certain tests.
FA442 FA4 Logic Card 1 Jumper
D
SY27 ·2521-3
Jumper A must be installed for proper operation. The FA4 Logic 1 card is located in 01X-A1C2.
( FA420-FA442)
5-FA-49
FA443 FA5 Logic Card 2 Jumpers
~
D D
6AO
6AO
D D
6AO <SA?> 6AO
6AO
6A06AO
D D "D fl
6AO 6AO
~
6AO
E
D D
Jumpers A must be installed for proper operation.
The FA5 Logic 2 card is located in 01X-A102.
SY27·2521·3 FA444 FA6 Servo Card 1 Jumpers
5-FA-50
Jumpers A must be installed for proper operation.
The FAS Servo 1 card is located in 01X-A1E2.
FA450 Detailed Data Flow and Operational Theory
FA451 Data Flow Diagrams
Figure FA451·1 shows the adapter data flow. Figures FA451·2, FA451-3, and FA451·4, respectively, show data flow for a seek operation, a read/write operation, and for error detection and safety circuits.
I
I
< SCF
Signal
Bus
~
I
I
I
~ -_..
Command Decoder
---
-FCB Decoder
b
,,
'~
-~
FCB Buffer
~ ~·
L
I
I
I ~ --
Data Buffers (2) 256 x9
I
I
L
Figure FA451·1. Adapter Data Flow Diagram
-
-...
--
Seq"ence
-
Control
I\
~ -
CRC/Byte
~ -
~ .....
Counter
FCB Processor Card (FA 1)
---
Physical Sector Counter
-~
SER DES/Bit
~ --
Counter
--
Data Handler Card (FA2)
SY27-2521-3
-----,
I
I
I
I I I
I
_J
_,..,, Drive
-- Seek/Sense Tags
- Drive Control
·~
Bus
I-.. I
I
I
I
_J
Index/Sector
--- Drive Data ·Control
--- Data to Drive Data from Drive
(FA443-FA451)
5-FA-51
SY27-2521-3
Data Channel Card (FA3)
------------,
-........
Safety CCTS
AS
_!
I I I I
~
.,
I 111 l
A4/A3
· 1~-~·.L~.L~~
.... JI
Servo Safety
---1I -- I
-.....
Head
Address
Reg
r--
I
~
- I
I
...
I
I
- CTL Bus., _l_ ~ I
---
J a
-........
I
~ ~
I I
--.:::::!-.
...... I
Status Bit
..~ ..... _,._ ~
l
Track Address Logic
·'I
,..
I I
.J.
ti
-t
I
I
I
..-..-
I
Assembly
I
Tag
I
l Tag Bus
................
I
Bit Reg/
t'- I
Decode
I
I
I
L,_ _____ - - - - - _ _J
Logic 1 Card (FA4)
, - - - - Disk Enclosure
1
I
I
Unsafe
Detection
Servo
...
HD/
5
P~amp
u
~ c: c:
u 0
.........
--1
,------------, Servo 2 Card (FA7)
I
I
Note: Shading shows circuits not used in seek operation.
I
I
I
I
I
I
I
I
l
-
A2/Y1 Conn
Driver Card
I
I
I
I
... J
-
l
l
I
Servo
...
Track Sensing
...... .
J
Access Control
L - - - 1- + - - - - 1-1- - _J
~~
...
-
[
L
sv .. CTR
I
I
2F OSC
I_.
......_, CTL
1"'"
...1 I
I
I
_l
I
___ J
Logic 2 Card (FA5)
Servo
CTL
__.,
(Fine)
I :::.
r
I ..
I I I
I
I
I
I
L ____________ _J
Servo 1 Csrd (FAS)
Figure FA451-2. Data Flow Diagram, Seek Operation
5·FA·52
A5
a
~
c c u 0
r-
1
I I I I I
I I
Data Channel Card (FA3)
Safety CCTS
, - - - - - Disk Enclosure
1
I
i--~--.~r----i A2/Y1
Unsafe Detection
Read Decode
AMPS
0 ~
Write
c c
Encode
u 0
R/W Clocks and CTLS
Head Address Decode
I __ _J
R/W Heads/ Preamps/ Drivers
L _____ _
A4/A3
Logic 1 Card (FA4)
F1gure FA451-3. Data Flow Diagram, Read/Write Operation
Logic 2 Card (FA5)
SY27-2521-3
Servo 2 Card (FA7)
Servo 1 Card (FA6)
(FA451 Cont)
5-FA-53
SY27-2521-3
r-
Data Channel Card (FA3)
Disk Enclosure.
i------
1
I I I I I
AS
Safety
CCTS
1
I
~--.--1~~---1 A2/Y1
Unsafe Detection
9
~
c: u 0
Servo 2 Card (FA7)
5-FA-54
Tag Bus
I I
L.1.-
Status Bit Assembly
Tag Bit Reg Decode
Logic 1 Card (FA4)
Figure FA451-4. Data Flow Diagram, Error Detection and Safety Circuits
Logic 2 Card (FAS)
Servo 1 Card (FA6)
FA452 Detailed Operational Theory
File Adapter
Function Definition Module (FOM). System code builds Functional Control Blocks (FCBs), which are queues of functions to be executed by the adapter. System code then requests the FDM to execute the FCB. The FDM issues the appropriate commands to the adapter hardware to cause it to fetch the enqueued functions from the FCB. The adapter hardware makes the necessary data transfers and interrupts back to the FDM when all functions in the FCB have been executed.
Function Control Block Processor Card (FA1). The FA1 card communicates with the FDM through commands and status. It also fetches operations from the FCB, controls seeking and sensing of the drive, causes the data handler to initiate data transfer operations, and maintains adapter status.
When an operation is fetched from the FCB, the FA 1 card decodes it and causes the necessary actions to occur to complete its execution. Once the action is initiated, the FA1 card may fetch the next FCB operation to allow overlapped operations (that is, fixed head data transfers and a moving head seek).
When the end of an FCB is reached or an error occurs, the FA1 card causes an interrupt back to the FDM.
Data Handler Card (FA2). When the FCB processor determines that data transfer to or from the drive is required, the FA2 card is activated. The FA2 card monitors the position of the head with respect to the disk. The Physical Sector Counter (PSC) in the FA2 card is able to predict the next physical sector on the track. The sequence control logic inspects the FCB operation and, at the correct sector count, verifies the ID (in the case of a read or write of a data field), and executes that read or write operation.
Two 256-byte data buffers reside in the FA2 card. While one buffer is receiving one data field from the drive (or processor), the other buffer may be transmitting to the processor (or drive). Within the FA2 card, Cyclic Redundancy Check (CRC) data is checked and generated and correct parity is maintained on the data.
When the transfer of one field is completed, the FA2 card requests the next function from the FCB processor. In this fashion, a read (or write) of all 64 data fields on a track may occur within one revolution.
Disk Enclosure (OE)
The DE is a sealed unit that contains the read/write components, actuator, spindle, and some of the DE electronics. This unit is available in 3- and 6-disk models as shown in Figure FA452-1. The DE drive motor, spindle brake, and the remainder of the electronics are attached to the DE base casting.
Six-Disk Model Actuator Arm
Read/Write Data Heads
10 9 8
7 6
5
Data
4
Surfaces
3
2
This surface is used
for one moving head
0
or eight fixed heads.
' - - - - - Servo Surface
Servo Head
Drive Belt
""---- Base Casting - - - - - - - - - Spindle
Three-Disk Model Actuator Arm
__ Read/Write Data Heads ......__ No data is stored on these surfaces.
Servo Head
Drive Belt
Pulley
Figure FA452-1. Disk Configurations
4
Data
3
Surfaces
2
1
This surface is used for one moving head or eight fixed heads.
0
'------ Servo Surface
Base Casting. Spindle
SY27-2521-3
(FA451 Cont, FA452)
5-FA-55
Spindle/Brake Actuator
SV27-2621-3
Depending on the type of DE, either three or six disks are clamped onto the spindle hub. A fourth (dummy) disk is fitted on the end of the three-disk spindle to assist the closed air circulation system.
The spindle is coupled to the drive motor by a belt that runs on the spindle and motor pulleys. If the DE is switched off or power fails, a mechanical drive brake operates against the spindle pulley to control deceleration of the disks. The brake also prevents disk rotation during transit.
The spindle and the conductive belt are grounded to the DE frame through antistatic brushes attached to the DE casting.
The moving heads are attached to the end of each arm of a pivoted arm actuator. See Figure FA452-2.
Because the head-to-disk spacing is small, contamination prevention is important. Therefore, a closed-air circulation is used in which blades on the spindle hub continually circulate air through an absolute filter. A breather filter controls air pressure during startup, and ambient temperature changes.
Pivot
Read/Write Components
Figure FA452-2. Actuator
DSD Data Formatting
5-.FA-56
A rectangular coil is attached on the opposite side of the actuator pivot within a twogap magnet, and current in the coil causes the heads to move in an arc across the disk surface.
Servo tracks on one disk surface are read continuously by the dedicated servo head and provide information to enable a closed loop servo system to be used for accessing.
Additional servo information is contained in each sector of the data tracks on all disk surfaces. This sampled servo information supplements the dedicated servo for fine control of the data head position when on track and during read or write operations.
Preamplifiers for servo and data heads and head section circuits are mounted on the actuator close to the heads, together with write driver circuits. During start and stop cycles, the actuator retracts the heads to the guard band area on the disk surfaces.
A retract spring pulls the heads to the landing zones if loss of disk speed occurs or if the actuator power supply fails. A magnetic catch on the actuator holds the heads over the landing zones in a normal power-off state.
A mechanical lock is provided for locking the actuator in the retracted position during removal and installation of the DE or transit of the DSD.
The disks rotate at a nominal 3125 revolutions per minute. A single head flies over each disk surface. To minimize wear of the disks and heads, the start and stop times are controlled by the drive motor and drive brake.
The disk surface nearest the base casting is dedicated to the servo head. The remaining surfaces each have a data head. Up to eight fixed heads can be fitted in place of the data head nearest the base casting. Each fixed head remains permanently over its own data track.
Note: Fixed heads land on the data track and, for this reason, it is recommended that any permanent data be rewritten by the customer after a maximum of 20 power on/ off cycles.
The DSD format is written so that there are two data records of 256 bytes.
Track Format. The number of tracks on each disk data surface is 376. The band of 16 tracks closest to the disk spindle forms the guard band, which is behind home. The cylinder home is defined as cylinder zero, and the remaining cylinders are numbered from this cylinder outwards.
Sector boundaries are derived from information permanently encoded within the dedicated servo pattern under the zero head. These boundaries are defined by pulses on the dedicated sector line.
Each track is divided into 33 sectors (0-32) of 600 bytes. Sector 32 is reserved as an alternate sector to provide backup for defective disk areas. Cylinder 64 is also reserved for alternate sector usage, and cylinder 359 is reserved for maintenance test purposes.
Data Surface. Each data surface (Figure FA452-3) has 360 concentric data tracks, each of which has 32 sectors. A factory-written sample servo used for track following is contained in each sector. Each track has a reserved sector to which failed sectors are reassigned.
When this alternative sector has been used, further reassignment is to track 64, which has been reserved as an alternative track.
Spindle
Data Surfaces
Figure FA452-3. Data Surface
Guard Band this band contains seek control information and is used as the landing zone for the moving heads when power is removed.
Servo Surface. The servo surface (Figure FA452-4) is used for seek operations. It has 360 concentric tracks, with index and sector coding that corresponds to the data tracks on the other surfaces. The guard band has 16 tracks without encoding.
Dedicated Servo Surface
Guard Band (Behind Home) Area: used for access and recalibrate control. This area has a minimum of 16 tracks.
Figure FA452-4. Servo Surface
Home Track 0
SY27·2521·3·
Sector Format. Each sector (see Figures FA452-5 and FA452-6) has a gross length of 600 bytes and is made up of three basic areas:
1. ID area, which contains flag byte, sector, head, track numbers, and cyclic check code.
2. Data area, which contains two 256-byte data fields. 3. Servo sample area, which is used by the DSD position servo to establish the data
head position over the track. This area is not available and is interlocked to prevent accidental erasure or overwriting.
As shown in Figure FA452-6, a two-byte CRC field is provided for each of the 256-byte data fields, and a four-byte ECC field is provided for each of the 256-byte data fields.
Sector numbers Field number
31
ID I 31
Index
32
t
00 "
01
100 132
Flag (1 byte)
Sector ID
Address (3 bytes)
ID CRC (2 bytes)
Field
Data 256 bytes)
Data CRC (2 bytes)
Figure FA452-5. Sector Format
Field
Data (256 bytes)
Data CRC (2 bytes)
(FA452 Cont)
5-FA-57
SY27-2521·3
.-- Sector Start
I I - 14 Bytes of 00 (settling time for write turn on, AGC Recovery, Sync, etc.)
- 1 Byte (Sync Byte) 01 (conditions controller circuits)
r- CRC Check bytes for previous ID bytes.
I I ,_ 16 (14) bytes of 00 as in fJ r- 1 byte 01 as in
5-FA-58
.-- Read circuit recovery time after write.
,, ·
1256 There are two possible
Bytes without ECC
sector formats, selected
14
11 3 2
256 bytes ~
2
16
256
· 7 bytes
22 bytes
by user system and/or customer option.
256 Bytes with ECC
(
____ \
14
11 3 2
14
256 bytes
4
14
256
4 7 bytes~
22 bytes
..__ _ _ _ _ _ _ _ ___,......_..___,,__,___ _ _ ___,..........__ _ _ _ _ _ _ ....... -+------t--'--~-----~-L
---------------~-1---'--_.
...J.,._ _ _ _ _ _ _ _~
0
256 data bytes -
·
2 bytes CRC _ _ _ _ ___,
J r 256 dato by ···
1
l
2bytesCRC~
Recovery Area including 12Y:i
4 bytes ECC - - - - - - - - - '
bytes of sample servo
16 (14) bytes 00 as in 11---------'
4 bytes ECC
1 byte 01 as in I I - - - - - - - - - - - - - -. . . . .
Flag Byte
Bit
Significance
0
Defective Field 2
1
Defective Field 1
2 Write Protect Field 2
3 Write Protect Field 1
4 Sector Displaced
5 Sector Re. .igned
6 Sector Defective
7 Alternate Sector
'-- Address Bytes
BYTEO
BYTE 1
BYTE 2
0
23456 70
2
3
4
5
6
7
0
2
3
4
5
6
7
x 32 16 8 4 2
x
x 16 8 4 2
x 256 128 64 32 16
8
4
2
Sector Address
Track (Head) Address
Cylinder Address
Figure FA452-6. Sector Organization
Spiraling. Large volumes of data are sometimes required to be read or written on sequential sectors and tracks. In these cases, after all remaining sectors on the first track have been written, the next sequential head is selected and writing continues on the next track. A maximum of eight sectors is required for the read/write circuit to stabilize after a head change; therefore to ensure that data transfer can continue with the minimum interruption, sector addresses on each succeeding track are displaced by eight sectors (see Figure FA452-7). This avoids the requirement to wait for a full disk rotation before restarting the read or write operation. Fixed heads do not follow this principle as they are not intended for use with bulk data.
Address cylinder XX head VY
Defective sector
\ Spare
0
2
3
4 I ((
.) )
'~' 23 24 25
28 29 30 31 27
32 Track with defective sector
0
2 3 4 rr1
23 24 25 !~! 26 27 28 29 30 31 Sector reassigned
.))
0
2 3 I 4((1
1.3-J 23 24 I 25
26 I._2]..J 20
29 30 31
Subsequent defective sector
.I)
Index Pulse
'/'4 . - - - - - -IRotation I ·~'-o1~~-L~~~~~................1...1._0~,~~_.__._......._......._.......__._~l~2~0,..__.__.__.__.__.__._...._....__.l3_0_,_____ HeadO
10,
Head 1
II I I . 12. 0.
30 I I
Figure FA452-7. Spiraling
Head 2
Defective Sector Handling. Occasionally, defects in the disk surface will cause a sector to be unusable for normal operations. These surface defects may occur at any time, although originally they are detected and flagged during the manufacturing process.
Section 32 on each track is reserved as an alternate for the first defective sector on that track. In addition, cylinder 64 is reserved as an alternate for any subsequent sector failures.
When the first defective sector is identified, the sector number in the address bytes is changed to 32 and the flag byte 6 is set. All subsequent sectors will be reassigned so that the defective sector will now occupy the space currently occupied by the next sequential sector, and sector 32 ~ili'be occupied by sector 31. Afl sectors that have been moved in this way have bit 4 set in the flag byte (Sector Displaced) and the sector address changed to show the new sector assignment.
Any subsequent defect on the same track will have bits 6, 5, and 4 set in the flag byte (Sector Defective, Reassigned, and Displaced respectively). Its address also is exchanged with that of the first available sector on cylinder 64 using the same head (see Figure FA452-8).
If the defect on any sector prevents reading of the ID field, then the whole ID field is rewritten 64 bytes later on the sector. If this ~rea is also defective, then provision is made for the ID field to be written 256 bytes later instead. Bits 5 and 7 are set in the flag byte (Sector Reassigned and Alternate Sector).
I 0 I 1 I 2 I 3 I 4(( I )/
I 1 23 1 24 2s
22 = First available sector on cylinder 64, head YY
I I I~ 20 1 29
30
31
Subsequent 1 defective sector
reassigned Address changed to cylinder 64,
head VY, sector 22
Figure FA452-8. Example of Defective Sector Reassignment
Flag Byte. Bits 4 through 7 have been described previously under Defective Sector Handling. Bits 0 and 1 (Defective Fields 2 and 1) indicate the location of a defect to the first or second data field in 256-bytff mode. Bits 2 and 3 (Write Protect Fields 2 and 1) directly identify sectors that contain protected data which must not be overwritten.
Seek
Access Positioning. A dedicated servo surface and read head control the primary access positioning and locate the access mechanism over a selected data cylinder. However, with dense packing of data tracks on each surface, any minor misalignment between data heads and data track cannot be tolerated.
Final access positioning, therefore, is controlled by short bursts of servo information written at the start of each sector. The servo head may therefore be marginally off track, but the data head is correctly aligned at all times.
The sample servo error signal is reset to zero at the end of each sector, and is set by the sample servo electronics to its required level every time a sector or index area passes under the selected read head.
Dedicated Servo. A seek operation is initiated by two commands on the logic card control bus. The adapter places the binary equivalent of the low-order eight bits of the desired address on the control bus, and encodes a tag of 010 to the tag bus.
SV27-2621·3
(FA452 Cont)
5-FA-59
After permitting the two buses to stabilize, the adapter activates the control sample, which permits the tag bus register to accept the tag code. The tag code is decoded and gates the control bus to the desired address register, bits 1-128. The high-order bit (256) of the address is provided in a similar manner by a tag decode of 001; this gates the head address data to the head addres~ register.
The desired address is compared with the current address position, stored in the absolute address accumulator by the subtractor. At the same time, the decode verifies the validity of the address required and raises track unavailable if the track requested is outside the usable track address. Track unavailable is combined with parity error to inhibit set seek, thereby preventing an attempt to seek under error conditions.
The desired and absolute addresses are compared in the subtractor. The lower of the two addresses is subtracted from the higher, and the difference count obtained. The count is equivalent to the number of tracks that have to be crossed for the access arm to arrive at the desired address.
Any output from the subtractor other than all zeros activates shift. This indicates to the access logic that the heads are not positioned at the required track.
Internal carry lines in the subtracter determine the direction of subtraction. If the absolute address is higher than the desired address, the subtraction is absolute address minus the desired address. The -carry 256 signal from the subtractor controls the direction of access motion.
To obtain the fastest possible movement of the access arm, the voice coil motor is driven at its maximum possible acceleration for as long as possible, then decelerated quickly to a stop immediately over the desired track without overshooting or undershooting. Because each successive access move can vary in length from 1 to 359 tracks, a very sophisticated servo control system is necessary.
For any access length, the actuator is driven at maximum acceleration until its velocity exceeds the velocity profile. From that point until the completion of the access, the actuator velocity is controlled to follow the profile. The velocity profile is stored as 512 words in a read-only storage (ROS) module.
At all times during the course of an access, the DSD calculates the distance of the actuator from the desired track by taking the difference between the absolute track address and the desired track address. This difference is updated at 1/4 track intervals and used to address the ROS. On long accesses, when the difference exceeds 512 quarter tracks (that is, 128 tracks), the ROS address is forced to 511.
The ROS output feeds a digital-to-analog converter so that, as the difference count decrements from 127 to 0, a graduated output is produced that corresponds to the desired velocity profile. To compensate for mechanical and electrical tolerances and for drift caused by environmental conditions, the graduated output of the acces; velocity generator is variable and controlled by the profile gain voltage.
SY27-2521-3 Read/Write
5-FA-60
Profile gain voltage is generated all the time that power is available to the DSD. The maximum access performance of the DSD is obtained by calibrating the profile gain voltage using the following sequence:
1. Recalibrate - This causes the DSD to access to the home position with head 1 selected.
2. Seek to track 128 with head 1 selected - During this 128-track seek, the velocity profile is compared with the true velocity of the access arm.
The counter increments until the velocity is not greater than profile or until the counter is full.
A compensation coil in the DE minimizes drift caused by temperature variations. The compensation coil is made of the same material as the voice coil motor windings. Therefore, any resistance changes in the compensation coil mirror those of the voice coil and provide corresponding compensation to the analog circuits.
One further offset to the desired velocity is provided by the handover velocity. The handover velocity is recalibrated automatically after a calibrate operation, and sets the slow seek timing for the last 1/4 track of a seek operation.
The access arm is forced to seek in two-track increments. The time taken is compared in a slope detector block against a reference voltage. If the time is less than 1.9 ms, the counter, previously preset to 7, is decremented, and the cycle repeated until the time is equal to or greater than 1.9 ms, or until the counter has reached 0.
When the access arm has reached the desired address,+ seek is deactivated and, after a suitable delay, seek complete is activated. This raises an interrupt that signals to the adapter that the operation is completed.
A prerequisite for any read/write operation is that one, and only one, read/write head must be selected.
Control bus bits 1 through 5 are gated into the head address register by a tag decode of 001. These five lines are then converted to five module-select lines by the head-select decode logic. Module-select lines 1 through 3 are routed directly to the DE logic circuits through the (MH) cabl"e.
Note: The DE contains up to five modules each capable of driving up to four heads.
When a module select line is activated, the positive supply is gated to the appropriate module. Decoding the head select pair then gates the selected head.
Each module contains the following: four write drives, four read preamplifiers, a common read output amplifier, head selection logic, read/write selection logic, and safety circuits.
The DE does not reject invalid codes. However, the safety circuits indicate an error condition if a write operation is attempted on an invalid head.
The read/write heads are center-tapped, and the center tap lines are connected together. A read or write operation is controlled by the center tap of the selected head. A plus level on the center tap line provides the current for writing; a zero level provides the necessary grounding for a differential output while reading.
Read and write signals pass to and from the module through the actuator 1/0 Iines (or fixed-head 1/0 lines on a fixed head DE).
Write Data. Write data from the dedicated cable enters a four-bit shift register and is clocked through the shift register by a clock pulse derived from the write clock. The four bits of the shift register are fed to a precompensation encoder where the bit pattern is encoded to become a modified frequency modulation (MFM) signal that, after feeding through the signal bus amplifier modules, is passed to the moving and fixed heads for writing by the selected head.
Precompensation in the encoder is a technique used to counteract timing errors that occur in the read signal caused by the high density of data on the disk surface. In principle, as the data flows through the shift register, bit 3 of the shift register is the bit being wrritten, bit 4 is the bit that was written previously, and bits 1 and 2 are yet to be written. The timing logic supplies the encoder with three clock lines at 2F frequency, 2F early, 2F on-time, and 2F late; early and late are approximately± 9 ns from the on-time signal.
The encoder examines the four bits in the shift register and, from the 16 possible bit combinations, decides whether bit 3 should be written on the disk on time, late, or early and uses one of the three 2F clocks to achieve this. Write data is also fed to the head circuits during a write operation for test purposes.
Read Data. Any time that a head is selected and not writing, it is reading data from the disk. Read data is amplified within the DE and passed by the actuator 1/0 line to the signal bus amplifier for further amplification. Two outputs are available from this stage: the first provides sample !.ervo input; the second is amplified again by a variable gain stage that provides a differential output at a constant level, regardless of the input variations.
Figure FA452-9 shows the expected output at this point 013 or 813. Synchronization is provided by the system sector line. The figure shows a full scan across one sector using a delayed 10: 1 sweep on a time base of 0.2 ms/division.
End of Preceding
Start of
Sector
Next Sector
\_ }_ _________________________
·
·
...,._Rotation
Figure FA452-9. Sector Scan
Sample Servo Area
SY27·2521·3
The data -V detector extracts timing information from the differential output of the amplifier by detecting the signal peaks. Each peak produces a pulse output that is fed to the voltage controlled oscillator (VCO) sync control logic. VCO sync logic controls the following operations:
1. The VCO is synchronized with the incoming data stream in frequency and phase. The phase discriminator detects differences in phase between the oscillator· and the data stream, and raises or lowers the control voltage to the oscillator, through the charge pump, to keep them in step. The servo inhibit VCO line stops the oscillator during the sample servo area. Rapid changes in operation cause the VCO to go out of sync; the controller, therefore, issues a fast sync command when changing from write to read, for example.
2. Fast sync momentarily stops the oscillator and restarts it in proper synchronism with the data stream so that control can be rapidly resumed.
3. The VCO output is used by the data separation circuits (MFM decoder and NRZ data generator) to time the extraction of data from the data stream. NRZ data is applied to the controller in the using system in serial mode together with a read clock to drive the deserializer.
Error Detection and Safety Circuits. Comprehensive error detection is provided by the DSD, and write operations are immediately inhibited if any unsafe condition is detected while writing. Recovery actions, however, must be handled by the adapter.
Thirty-two status and sense conditions are available to the 8100 system, in groups of eight. By selecting the appropriate tag (100, 101, 110, or 111 ), the 8100 system can gate the selected group in the control bus out register.
Provided that the degate bus and power-on delayed are not active, the contents of the register will be gated to the control bus.
Sense Cycle. Certain conditions will cause an interrupt to be raised. This interrupt may result from (1) the normal completion of an access, head select, recalibrate, or powerup sequence, or (2) alternatively, as a result of DSD error condiitions such as not ready, data unsafe, command error, track unavailable, or brake applied.
The issue of an interrupt by the DSD is serviced by a control bus sense cycle with tag code 100. Further sense cycles may then be initiated with tag codes 101, 110, and 111 to provide further sense information if the tag 100 sense indicated an error condition.
(FA452 Cont)
5-FA-61
Power Sequencing
SY27·2521·3
The 8130/8140 Processor or the 8101 Storage and 1/0 Unit supplies and sequences the ac and de power to the DSD. The basic sequence in Figure FA452-10 applies.
Power Down
DC Power (
to Gate ../1----
I
I
!See Note 1
AC Power (~__JWjW l·.A . .i(~J,·. . . .~W·AL_~(
to Gate Fan/
1
""./
)
I
I
DC~wer ~(_~_J'llllllfrlflllllll:Se~e~N~o~~j3(
to Brake .)
././
J
AC Power to(
Drive Motoi;.1r-----....
......._, c...1. .~,--~jjLC~
See Note 4 _,
I
:---· I 25 sec (max) (( ./.,/
See Note 5 (
)
1. The ac power to the gate cooling fan must be on any time that de power is supp/led to the logic cards to prevent overheating of the electronic components.
2. The brake is retracted when de power is applied and - power good is at de-ground level. This should occur within ±500 ms of ac power being applied to the drive motor.
If brake failure occurs, that is, the brake is released, ac power is removed from the motor within 5 seconds (maximum) by the 8130/8140 Processor or by the 8101 Storage and 1/0 Unit.
3. The ac power is not applied to the drive motor unless de power to the gate is on and within tolerance.
4. - Power good is applied to the DSD (VC-1) and indicates that the de voltages are within tolerance at the user system, and that ac power is applied to the DSD drive motor. When power good goes active (that is, to ground level), it provides the de ground for the brake electromagnet.
Power good must be active within ±500 ms of ac power being applied to the drive motor.
5. The DSD issues an interrupt within 25 seconds of power good being active. Power good is filtered by the DSD and used to hold the DSD reset for 17 seconds by - POD. At the end of the 17-second delay, the DSD effects a calibrate operation and raises the interrupt.
Figure FA452-10. Power Sequencing
5-FA-62
Power-On Logic Sequence (Figure FA452-11)
1. The ac and de power are applied to the DSD. 2. Brake applied remains essentially negative to provide a return path for brake
current which retracts the brake and permits the spindle to accelerate. 3. -Power good is raised by the processor when de voltages are within tolerance. 4. -POD becomes active for approximately 20 seconds to permit the disk speed to
stabilize at 3125 rpm. 5. CTR 4 comes into synchronization after -POD times out and triggers the kick SS.
If CTR 4 fails to come into sync before -POD and PLO holdover SS times out, brake applied will be raised, the brake will activate, and brake applied to the adapter will be raised. The ac and de power will then be switched off within 5 seconds. 6. -Kick SS applies maximum acceleration to the actuator arm for 10 ms to move the actuator arm into the data area. 7. During the initial access movement, CTR 5 comes into synchronization. 8. +Seek is raised with the kick SS cycle and is lowered when the actuator comes to rest. 9. -Seek complete initiates a recalibrate cycle. 10. At the completion of the recalibrate cycle, home and ready become active and an interrupt is raised. 11. During this recalibrate cycle, handover velocity (HV) is calibrated. This is an analog voltage that should set to a similar level each time the DSD is powered up.
Power Down. When the DSD is powered down normally, through software or an emergency, the moving heads are moved to the landing zone of the disks, and the motor brake is applied when its +24V holdoff voltage is removed.
If a de supply goes outside the specified limits, all ac and de voltages are removed within 5 seconds. This reduces the risk of possible loss of data.
DC Power from System
02 P07 '+ Brake Applied'
Brake Mechanical Action F2 G10 '-Pwr Good' F2 P02 '-POD' No pin out'+ CRT 4' in Sync 02 S06 '- Kick SS' (10 msecl 02 G07'+ CRT 5' in Sync. 02 011 '+ Seek' 02 J13 '-Seek Complete'
02 Ul 1 '+ Behind Home' 02 P10 '+ Home'
02 M07 '- Ready' C2 006 '- Interrupt' 02 SOJ 'HV Test Pt'
,,...- Brake is released
nxrxzXXXTT'm
~~~~~~~~~~~~~~~~~~~~~~~~~~~........,
. . . . . . . . . . . . . . . . ~~~--is·~~~~~~~~~~~~~_.
~~~~
______r--ir-~~~~~~~~~~. . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
~'-"~~~~~~~~~~~~------
_______r---j,--~~~~---~--~--~~--~--------...-~~~~~,
Note: This chart indicates the correct sequence of events. Actual times and wave forms will vary.
Figure FA452-11. Power-On Logic Sequence Timing
Power Interlocks. Power-failure detection is not provided by the DSD. However, failing conditions are indicated to the system.
Not-Ready Condition. A not-ready signal is issued and an interrupt is raised when: · The Phase Lock Oscillator (PLO) loses synchronization. This can be due to loss of
disk speed that can occur if the drive motor fails, ac power removed from the motor, or the brake fails. · The brake applied line is active due to failure of the brake drive. The line is reset when the power-down sequence of the 8130/8140 Processor or the 8101 Storage and 1/0 Unit is complete. · The invalid move line is active. This line is actuated either when actuator motion is not in response to an access command, or when writing is attempted during an access operation.
Recalibrate (see Figure FA452-15) resets not ready except when brake applied is active or when a power-down sequence is required. If recalibrate is not successful, reset error completes the recovery process.
Signal Bus Descriptions
Thermal Failure. A thermal cutout detects overheating in the drive motor. If the cutout operates, it can be reset manually only after the motor has cooled to within safe limits. After a thermal cutout trips, the PLO will go out of synchronization, thus activating brake-applied and initiating a power-off sequence in the 8130/8140 or the 8101.
Control Cable (CC)
Control Cable Bits 0-7 and Parity. This section of the control cable is used to transfer data to and from the DSD. The decode of the three tag bits determines the significance and direction of data flow. Parity is checked by the DSD for incoming data and generated for outgoing data.
Tag Bus Bits 0, 1, 2 and Parity. The three tag bus bits are decoded to seven conrol lines as shown in the following table:
Tag Bits
0 12
0 0 0 00 1 0 10 0 1 1 1 0 0 10 1 1 10 1 1 1
Meaning
Not Used Head Selection Track Selection Test Wrap Sense Test Sense 1 Test Sense 2 Test Sense 3
Tag 001 Head Selection. Tag 001 gates control bus bits 5-0 to the head address register. Bit 7 is gated to the desired address register bit 256. Bit 6 is unused.
Tag 010 Track Selection. Tag 010 gates the control bus bits 7-0 into the desired address register bit 1-128 respectively.
Tag 011 Test Wrap. Tag 011 gates the low order bits (1-128) of the desired address register, back to the controll bus for wrap around transmission back to the adapter.
Tags 100, 101, 110 and 111. These tags gate sense and status information onto the control bus.
-Control Sample Received. This indicates to the adapter that control sample has been received and responded to.
SY27-2521-3
(FA452 Cont)
5-FA-63
Dedicated Cable (DO) -Control Sample (input to DSD from the adapter). -Control sample and the 001 tags decode gate head or track selection. -Control sample also generates +enable bus for any tag other than 001 or 010 which gates sense and status to the control bus. +Oegate Bus. This line is normally held negative. When activated, it prevents sense and status information from being gated to the control bus. -Reset Error. This line is used to reset the data unsafe or command error sense bits. It may also be used to clear an interrupt.
-Write. This line activates the write circuits in the DSD. -Read. This line activates the read circuits in the DSD.
Note: -Write and -read are mutually exclusive. An error interrupt occurs if they are both active at the same time.
-Data Select. Data Select is used to gate -write or -read. -Write Data. This is serial binary data for writing to the disk. -Write data is synchronized with -write clock. -Fast Sync. This rapidly forces the read PLO into synchronization after any event that requires a long resync, using normal sync control. For example, after change from write to read.
Output Lines from DSD to the Adapter -1 F Write Clock. Synchronized to servo clock, pulses from the servo surface -1 F write clock are used by the adapter to synchronize write data. -Read Clock. Synchronized to data during read operations, -read clock is used by the adapter to clock read data into the deserializer. +NRZ Data to the Adapter. Serial data read from the disks. -System Index. -System index indicates the track start to the adapter. It is derived from data in the sample servo area just prior to start of first sector on any track. -System Sector. -System sector is similar to -system index but indicates the start of all sectors after the first. -Sector Pulses Missing. This indicates to the controller that the DSD failed to detect a sector pulse at the time one was expected. -Interrupt. An interrupt is generated for home and ready, after power up, for seek complete and some error conditions.
±Write Gate Return. This indicates to the controller that the write current to the DSD has been switched on.
Individual Cabling Through Voltage Crossovers -Power Good. This is active only when all de power lines are within tolerance at the 8130/8140 or the 8101. Its loss causes the DSD brake to be applied immediately. +Brake Applied. This indicates to the controller that the brake has been applied, either because of an unsafe or error condition or brake failure. The 8130/8140 or the 8101 will respond by removing ac power from the motor within 5 seconds of+ brake applied becoming active.
SY27-2521-3
5-FA-64
Phase-Locked Oscillator (PLO) Loop The PLO (Figure FA452-12) is synchronized in phase and frequency by the servo signal clock pulses as follows:
The voltage-controlled oscillator (VCO) runs at approximately 16.5 MHz. The output 2F is divided by 2 to give 1F write clock.
The 1F write clock drives a 5-bit counter (counter 4) whose output is 1/16th of the PLO frequency. The servo clock pulses trigger a single shot(+ servo clock SS 280 ns).
For the PLO to be in synchronization, the trailing edge of the servo clock SS must coincide with the midpoint of the negative level of the counter 4 signal.
A comparative circuit on the Logic 2 card looks for this coincidence and provides an output of oscillator early or late to the VCO to correct any misalignment.
During normal synchronous operation, narrow oscillator late and oscillator early signals are produced continuously as shown in Figure FA452-13.
The PLO is used by the processor to serialize write data.
r----.-+-C-o-un_t_e_r-5.-T-P_ _ _C_o-un_t_e_r4 - - - - - - - - - · t - - - - - - - - - - - - - - - - - - - - - - - - - - - - · - - -
Counter 5
Out of Sync
I - -o G01- Bi 2--Q- =M06 - - - - I
I ----I I---- I
I ~
l I
I
J02 Oscillator Late lJ07
I I
11
I
I 1F Write
J05 I I
'Power On Delay'
J.. U09
~-!---'
+ Co u n t e r !' 4-3:--
Comparator r-
1 1
I I
I I
VCO
G121 -v
'2F-~9
-;-2
l l Oscillator Early G07
I IM10
I Clock
i~I
__
U12--.
--------_ -v
I I G05
c~
l s13
I
I
:'_:A_'_D~I"._~!
I
I
I
I
I
I
L X-A2_E:!FA6~
I
I
I
I
I
Lx-A1B2 IFA:! ~
r-----,
1----,
I
I
I
I
I
I
I DOG
I D10 0--~~~~~---b-....r~~,
I Dedicated I Servo II Preamplifier
Detected Servo Signal
Servo Clock Detector
I
Servo
I
Clock
B04
I I
I
I
I
011 I
I
D05
I
IL D_isk_En_clos_ure_jI
L_ X-A2_F~FA7)J
Figure FA452-12. PLO Data Flow
Detected Servo Signal
Servo Clock SS
'Counter 4'
'Counter 5'
'Oscillator Late'
'Oscillator Early' '1 F Write Clock'
I
I
I
t
I
I
I
~1IlJUUU1JU1JUUlMJWlJlf1JUUUUUUU1111lflflJ1JUlJUUUUUlJUlIWlJ1IUl
I
I
I
I
Figure FA452-13. PLO Timing
Voltage Controller Oscillator (VCO) Control The VCO and associated control circuit (Figure FA452-14) form a phase-locked loop that tracks the frequency and average phase of the read input data signal, and corrects for any drift in these signal components.
Circuit Operation. The 2F clock applied to the data latch is compared with the data SS (single shot) for coincidence. If the data SS pulse is completed before the end of the corresponding data latch pulse, an increase line is activated. If the data SS pulse is completed after the end of the corresponding data latch pulse, a decrease line is activated. The combined output (an analog control voltage) is applied to the VCO to restore the correct coincidence of the data latch pulses with the data SS pulse.
Relatively large discontinuities of the data signal can cause loss of synchronization of the data latch and data SS signals. Therefore, when the source of the data signal changes, for example when changing from writing to reading, the VCO control circuit is switched momentarily to the fast synchronization state.
During fast synchronization, the VCO operates as previously described, except that the signals involved are much greater.
The fast sync signal applied to the fast sync logic can be in one of two phases, depending on the mode (read or write) in which the DSD is operating. The fast sync logic selects the appropriate fast sync input, that is, fast sync from the processor or internal fast sync.
The circuit is reset by the end of the inhibit SS pulse and the data pulses; the VCO is then restarted so that the data pulses and the VCO output are synchronized.
When the DSD is not under the control of the disk adapter, the VCO is synchronized with the write clock.
2F Read Clock
0 U10
Data SS
J12
U06 U04
Read Select Servo VCO Inhibit 1 F Write Clock
S04 (TP) U05 (TP)
S02
Operation Extend
Internal Fast Sync Fast Sync From FA2 J09
Data Latch
Fast Sync Logic
2 F Standardized Data
'---1 MFM Decoder
Figure FA452-14. VCO Control
---
VCO 16.5 MHz (2F)
2F
Data Servo 2
P11
High Current
U09 (TP)
Forces Phase to Standardized Data
Card C·A 182 (FA3)
Recalibrate Issued by Processor or Storage and 1/0 Unit Recalibrate sequence is as follows (see Figure FA452-15):
1. A recalibrate command issued by the processor is initiated by a tag code of 001 with bus bit 0 active (-).
2. Tag 001 CLK 2 with -go home bit sets -go home.
3. ·+Out direction drops and +seek is raised.
4. When the actuator arm arrives in the behind home position, seek drops and 4 ms later -seek complete is activated.
5. -Seek complete initiates a further seek with +out direction active to the home position.
6. 4 ms after the seek ends, -seek complete is activated again together with + home and an interrupt to signify completion of the recalibrate.
7. +Home is reset by the next seek operation and remains negative until a further calibrate command sets it again.
8. Handover velocity is not affected by a recalibrate command after the initial power-up sequence.
SY27 -2521-3
(FA452 Cont)
5-FA-65
SY27-2521·3
Bus Bit 0
FA4 007 Tag 001, CLK 2
'-Go Home' ('-Go Home' or 'POFL')
'+Out Direction' '+Seek' '- Seek Complete'
Depends on previous
f /Returns to original
72227222771/ operation ) '
-~-level
,
,
)
'+ Behind Home'
'+Home'
'-Interrupt'
Access and Head Change
Figure FA452-15. Recalibration Timing Chart
5·FA-66
Figure FA452-16 indicates the sequence of events for a seek to a higher number cylinder followed by a head change only operation. For a seek in the other direction (to a lower number cylinder), only+ out direction will show a different response.
8 A tag decode of 010 and -control sample reads the low-order bits (1-128) of the
desired address into the desired address register. If this address is different from the current address, -shift becomes active. +Out direction sets according to the dif· ferent count from the subtracter. (It may then switch to the opposite condition when the high-order bit 256 of the desired address is received in the next tag cycle.)
The subsequent decode of tag 001 with control sample sets the high-order bit 256 of the desired address. +out direction sets and+ seek are raised; -shift is deactivated when the desired address and absolute address are equal. This occurs at 1/4 track from the on-track position. + seek deactivates when on track and 4 ms later -seek complete is activated together with -interrupt.
·e The adapter performs a sense cycle which resets the interrupt. During a head change only operation, tags 010 and 001 are used in exactly the same way as for an access. - shift and+ out direction may show a response to tag 010 bus data if the low-order address bits differ from the absolute address. They will, however, return to the inactive state when the second tag cycle 001 is received. A seek complete interrupt occurs 4 ms after -control sample received.
- Tag 0 (100)
~ ..,.
+
e
With or without Head change
r 8 "t~--~----~---1~---------.++----I~
Sense Cycle
- - - - - - - Head Change Only _ _ _ _ _,..._Sense Cycle
- Tag 1 (010)
+
-Tag2(001)
+ - - - - - - - - - ........--~r---------~~----------........---------------j
-- Control Sample
- Control Sample Received
Data Set on Control Bus +Shift
+ Out Direction
~ Dependent on previous operation P~tce~e~aBieiS!d~~~:>K:~\\~\~\~,,~,~,,~,~\\~qr------j,r----------~~---~KDX~i~XICi~i~XiDR~i~i*~k~iZk*~iUI----------~---~·--?
+Seek
- Seek Complete - Interrupt
Figure FA452-16. Access and Head Change Timing Chart
Write Safety Detection
General. Write safety detection circuits (Figure FA452-17) on the data channel card check operation of the DSD that could affect data written on the disks or data being written.
812
Positive Supply (<-+5.5~)
I
Current
r-----------------~
I
Safety Condition Latches
I
I
Threshold
~n~
1M-u-lt-i--Ch-ip-S-e-le-ct-io-n-E-rr-o-r --I .----+--·
I
Latch
.L
T I
:
.--
I
I
I
Centre Taps
G03
I
I
I
I I
Current
I
I
--+--1---t- Threshold Head Grounded Error
I
Sense 1-----------rt-l
Latch
l
I
I
......_
I
I
I
SafetY
011
I
I
I
I I
I I
Current
I
Latch
l
Threshold 1------------1Tt----+--+--+---
Senff
I
I
I
+-
I
I
I
- Write Current when Not Writing
I
I
l
Current Threshold
Sense
I No Transition During Write
Latch
'--+--+--+--
I
I
I
I
,____
I
OR
l
Write Current
I
002 0
I I
Priority Inhibit
M03(TP)
L----------------~
Multi-Chip Select
J 11 - HD Ground Error
G07 Trcnsi ti on Error
G05
-0 Write Current Error
GlO + Data Unsafe
G13
+ Write Select
Date Channel Card FA3 (X-A1B2)
Logic 1 Card FA4 (X-A1C2) From servo unsafe latches
Safety Control Logic
Transient Blanking
r-
- - -'
+ Read . Write + Unready · Write + Servo Protect · Write + Off Track · Write
OR
N
J09 M02
Transient Blanking Test PT
~-Servo Unsafe 511
Figura FA452-17. Write Safety Detection Circuits
SY27-2521·3
These circuits check for the following unsafe conditions: · No transitions - that is, failure of write drivers to switch current in a head in write
mode. · Head grounded - this causes excessive current in the center-tap line. · Multimodule selection - this causes excessive current in the positive power supply
to the DE circuits. · Servo unsafe - logical or analog unsafe conditions external to the data channel. · Write current when not writing.
Each of the first four unsafe conditions listed above causes a latch to be set in the safety condition latches.
The latch outputs are connected with +servo unsafe to produce the line+ data unsafe.
No Transitions. Normally, when the current in a head is reversed during a write operation, voltage spikes are produced in the head winding. If these spikes are missing (that is, no transitions occur), either the head or the write driver has failed.
The voltage spikes caused by this failure and the - write gate produce the - no transitions during the writing signal. This signal sets the appropriate safety condition latch.
Head Grounded. A head-to-ground short circuit can cause current in the center-tap line to exceed the threshold set in the associated current threshold sense circuit; then a head grounded error signal is produced.
Multimodule Selection. If current in the positive supply to the DE exceeds the threshold set in the associated current threshold sense circuit, a multimodule selection error signal is produced.
Servo Unsafe. Unsafe logical or analog conditions cause the -servo unsafe signal to be applied to the write safety detection circuit. The -servo unsafe signal is connected with any of the unsafe conditions latched in the safety condition latches to produce + data unsafe.
Write Current When Not Writing. An error signal caused by write current flowing when not in writing mode is processed through the sense circuit and safety condition latches, and is then applied to the processor as a 1W error.
Priority Inhibit. Priority inhibit prevents any subsequent error from setting the safety condition latches so that only the first error condition is held in the latches.
Transient Blanking. Transient conditions that would otherwise set the safety condition latches are inhibited by transient blanking that gates off the latches. Transient blanking is provided in the unsafe detectors circuit. See Figure FA452-18.
X-A1B2G13 X-A1B2J09
+Write
I
Select I
,
;
,J.--_._________ + TBrlanksienngt /
-Jj -::j/;fJ.t_ _ _ _ _ _ _ _ __J_ _ _ _ _ _
10 µs
3 µs
Figure FA452-18. Transient Blanking Timing
(FA452 Cont)
5-FA-67
Sense/Status Cycle
SY27-2521-3
A sense or status cycle is initiated by the processor encoding a sense or status tag (tags 011-111) and raising -control sample (see Figure FA452-19). This may be in response to an interrupt or simply a normal housekeeping command.
The tag is decoded by the DSD. Control sample, control sample received, and tags 000, 001, or 010 are combined to raise the internal line enable bus.
Meanwhile, the tag decode has selected the appropriate sense or status bits for transmission to the adapter. Enable bus gates the selected bits to the bus out drivers and, provided that - POD and degate bus are inactive, the bits are transmitted to the using system.
- POD prevents the DSD from responding to a sense or status cycle during the powerup sequence.
- Data On Tag Bus I (Tags 011, 100, 101, 110, 111) )
- Control Sample - Decode Tag
- Control Sample-Read + Enable Bus - Data on Control Bus
Figure FA452-19. Sense/Status Timing Chart
cggggxggggxggggggggga
> I
k)tXXXgXX)fl
> (
5-FA-68
FA500 Adjustment. Removal, and Replacement Information
FA510 Scope Charts Scope Chart 1
The following scope charts were obtained using a Tektronic 453 and are to be used in conjunction with the FA MAP. See Scope Chart 1 for initial scope set up. Subsequent scope charts will only list the changes from the initial setup.
1. Use 1X scope probes. 2. Place oscilloscope Channel 1 probe on X-A 1D2J09 +SR Clock. 3. Place oscilloscope Channel 2 probe on X-A 1D2J1 O+Enable Servo Sample. 4. Place oscilloscope EXT TRIG probe on X-A 1D2S1 O. 5. Set oscilloscope controls as shown in the following table:
HORIZ DISPLAY MAG A SWEEP LENGTH A TIME BASE MODE TRIGGER SOURCE A SWEEP MODE A TRIG SLOPE A TRIG COUPLING TRIG A TRIG LEVEL A TRIG HF STAB INVERT
NORMAL TRIG OFF FULL 5 us/DIV ALT EXT NORMAL TRIG
AC NORMAL 0 0
6. Switch CHAN 1 INPUT to GND and adjust trace. 7. Position trace until the center line is ground. 8. Switch CHAN 1 INPUT to DC. 9. Switch CHAN 2 INPUT to GND and adjust trace. 10. Position trace until the center line is ground. 11. Switch CHAN 2 INPUT to DC. 12. Adjust A TRIG LEVEL to display trace. 13. Adjust a POSITION control to start trace at left-hand line.
SCOPE DI SPLAY
:I-
;s;:
.:i;.
"T
. .. .t
JT
rT
. .. . "
CT CT
X-A1D2J09 +SR Clock
~~
:~~
:~
~
J
X-A 1D2J10 + Enable Servo Sample
Scope Chart 2 Scope Chart 3 Scope Chart 4
SY27·2521·3
1. Move CHAN 2 probe to X-A1D2U13 (+Enable Mark Detect). 2. Switch MODE to CHAN 2.
SCOPE DISPLAY
. ~
LL LL __J__J__l I'
1:
. ~
~
...~.pm lll'" IUJ. I I I '·
["T "TT [TTTT [TT rT fTTT
I=
I=
~ t-
X-A 1D2U13 +Enable Mark
1. Move CHAN 1 probe to X-A 1E2B03 (Data A). 2. Set CHAN 1 V/DIV to 20 mV. 3. Switch CHAN 1 INPUT to AC. 4. Switch MODE to CHAN 1.
SCOPE DISPLAY
X-A1E2803 Data A
1. Move CHAN 2 probe to X-A1E2D02 (Data B). 2. Set CHAN 2 V/DIV to 20 mV. 3. Switch CHAN 2 INPUT to GND and adjust. 4. Position until the center line is ground. 5. Switch CHAN 2 INPUT to AC. 6. Switch MODE to CHAN 2. 7. Pull INVERT switch. SCOPE DISPLAY
X-A1 E2803 Data A
(FA452 Cont-FA510)
5-FA-69
Scope Chart 5 Scope Chart 6
1. Move CHAN 1 probe to X-A 1E2G03 (+Vco Inhibit). 2. Set MODE to CHAN 1. 3. Set CHAN 1 V/DIV to 1V.
SCOPE DISPLAY
I-
~
· ,, _.LLL _t_
_J_
]
.._ :i...t...u. ..J. I
-
+--;
+
..J..J...U.. .J.J...LL l.L.u...J.
"
X-A1E2G13+VCO Inhibit
SCOPE DISPLAY
Scope Chart 7
X-A1 E2G03 + VCO Inhibit
1. Move CHAN 1 probe to X-A 1E2J05 (-CRT RUN). SCOPE DISPLAY
~
__.._
_._ _._
·
TT1
I :r
1
.,
, ..1 I
..L
..LI...l.1. ..LL.LL Lu.. ...L
.:"· IT
I
Ill 111 I'
:
+
'j-
X-A1E2J05 - CTR Run
+
SY27-2521-3
Scope Chart 8
1. Move CHAN 1 probe to X-A1E2G08 (+2F Burst). SCOPE DISPLAY
5-FA-70
Scope Chart 9 Scope Chart 10
X-A 1E2G08 + 2F Burst
SCOPE DISPLAY= a valid MST 1 level (-0.8V to -1.SV)
1. Move CHAN 1 probe to X·A 1E2B13 (Data PES). 2. Set A TIME BASE to 2 ms. 3. Move EXT TRIG probe to X-A 1D2S13 - (System Index). 4. Adjust A TRIG LEVEL to display trace. SCOPE DISPLAY
~
- + +-_ ~- ...--~- j
r-· -- -- b-7... ~ _,__-
- lrTT nT·
f --.. "!
r - i F - -
LL l~.
t'.L~
II rTrT [Tia. rT
X-A1E2B13 Data PES
-
-~
FA520 Adapter and DSD Cable and Card Continuity
There are two separate areas for cable and card continuity: 1. Data Select Gate continuity checks the Moving Head (MH) cable X-A 1A2, the FA3
Data Channel card, and the FA4 Logic 1 card. 2. System continuity checks the Control cable (CC), Dedicated cable (DD), the FA1 and
FA2 adapter cards, the TCC Y03, and the FA9 terminator card.
FA521 Data Select Gate Continuity
X-A182
I0$0
I
FA3
I
P12 P12 + Data Select Gate
v
I
' -X-A1A2
-0
002 D02
X-A1C2
813 813
-0 "'
I
I
FA4
I
512 S12
-0 U"
+ Data Select Gate
I
(MH) Moving Head Cable
I -1
-0
~t - i
I
DE
__ J - o-I-"
I
L
FA522 Disk Adapter to DSD Continuity
(CC)*
"V ....,.
D02 002
A1 CARD**
r-o813 813
,.......
I,,)
M07
--- / ~ " \
Q
: Y03
)
, __ J Q
A2 CARD**
/
Q M02
l--0 ........,
U"
013 D13
802 802
...., 0
(DDl 0
Control Cable (CC)
X-A1A3
'V
0-t-
D02 002
813 813
.....
Term Card (FA9)
X-A1A4
·ro 0-t002 002
813 813
~
......
Dedicated Cable (DD)
X-A1A5
er-t-
013 013
802 802
-0 0-I-
I Mach Type
I I
I 8130 I 8140 I 8140 t 8101
I 8101 8140
I .8140
Model
Pseudo Card and Cable Locations
I A2X
A-A1U2' A-A1T2 A-A1Y1 A-A1Y2
I I I A3X/A4X A-A202 A-A2P2 A-A2Z6 A-A2Z5
A5X
I A-A2F2 A-A2E2 I A-A2Z3 I A-A2Z2
I f AXX (Low)I A-A2H2 I A-A2J2 A-A2Y3 A-A2Z3
I f AXX (Up) ' A-A2E2 A-A2F2 A-A2Y2 l A-A2Z2
I I f f BXX (Low) A-B2H2 A-B2J2 A-A2K4 A-A2K5
I BXX (Up) I A-B2F2 A-82G2 I A-A2Y3 I A-A2Z3
FA530 Not Used
SY27-2521-3
(FA510 Cont-FA522)
5-FA-71
FA540 Disk Enclosure (DE) Removal and Replacement
It is necessary to remove the DSD subframe from the unit to remove the DE. Removing the drive motor eliminates the need to remove the actuator lock lever bracket.
Cautions: 1. Do not remove the DE without requesting aid. 2. The DSD weighs 25kg (55 lb). The card gate may be removed to lighten the load
(see FA550). Also, in the case of the 8101 Mod A25, removal of the top DSD should require assistance due to weight and leverage constraints.
3. The heads on the actuator and the disks might be damaged if the DE pulley is turned counterclockwise.
DSD Subframe Removal 1. Switch off electrical power. 2. With the actuator lock lever in the Operate position, remove the spindle lock bracket (2 screws) from the subframe. Do not loosen or remove cable from the spindle lock bracket. 3. Remove the motor from the subframe. Do not disconnect the wires, but lay the motor on the unit frame floor until the new subframe is installed. (See FA570.) 4. If you want to lighten the load, remove the card gate (see FA551) and go to step 11. 5. If you have not removed the card gate, continue by disconnecting the DE ground. 6. Remove the card gate cover and cable retaining plate. 7. Loosen the card gate screw and swing the gate open. 8. Release the fan retainer at the rear of the card gate and withdraw the fan from the gate. 9. Unplug cabl~s Y1 (if fixed heads are installed), A2, A3, and A5.
10. Unplug cables J1, J2, J4, J5 and J9. (J9 also requires that both bottom board retainers be loosened in order to remove cable.)
11. Move the Operator/Lock Lever to the Lock position. 12. Remove the flat cable retaining straps.
Note: For 8101 Mod A25 units, it will also be necessary to remove the
OPERATE/LOCK lever plate.
13. Loosen the actuator lock cable retaining bracket. 14. Disconnect the actuator lock cable from the nylon actuator lock knob arm.
(See FA590.) 15. Disconnect the frame ground strap. 16. Loosen the three shock mounts, and remove the subframe by sliding it out of the
screws. (See FA541.) Stand the OSD on the DE cover on a clean surface.
SY27-2521·3
5-FA-72
DE Removal 1. Disconnect the slip-on terminals from the brake and the trimmer resistor. 2. Remove the nylon actuator lock knob bracket. 3. Unscrew the lower (long) DE mounting nut and the two upper DE mounting nuts. 4. Lift the subframe from the OE.
DE Replacement 1. To install the DE, reverse the removal procedure. 2. Adjust the belt tensioner and the brake as detailed in FA580 and FA572. 3. Insure that the actuator lock knob is turned fully counterclockwise (the Lock/
Operate lever is in the Operate position). 4. Run diagnostics. 5. Format OE using the format utility. (See CP650)
DSEpinGdrloeuLnodc-:-k--;---;:--~~-~~1i.,..J
Bracket
Upper Mounting Nut Gate Cover
X-A1A5
Long Nut
Actuator Lock Knob
Actuator Lock Knob Arm (shown in locked position)
Operate/Lock Lever Actuator Lock Lever Assembly
Pivot Nut P4
Board Retainers
SY27-2521-3
(FA540)
5-FA-73
FA541 Shock Mount Removal There are two types of shock mounts: A and 8. Determine if the shock mount is type A or type Band use the corresponding procedure.
Type A (Figure FA541·1) 1. Loosen the 1/4-20 UNC screws (hex head) to a point that allows the subframe to
slide out.
Type B (Figure FA541·2) 1. Loosen the 1/4-20 UNC screws (allen head) that attach the subframe to the two upper
shock mounts. 2. Insert a hex wrench through the access hole in the machine frame base and remove the
hex screw from the lower shock mount. See Figure FA541-3.
----Yr %20 UNC Screw
SY27 -2521-3
Figure FA541-2. Type B Shock Mount
Upper Shock Mount
Figure FA541-1. Type A Shock Mount
Lower Shock Mount Washer _ _ _ _ _ __,
% 20 UNC Screw - - - - '
Figure FA541-3. Type B Shock Mount Access
5-FA-74
FA550 Card Gate, Board, and VCM Driver Card Removal/Replacement
FA551 Card Gate Remo val/Replacement
Removal 1. Switch off electrical power. 2. Remove the card gate cable clamp screws, then remove the cable clamp and card cover. 3. Disconnect flat cable connectors (CC), (DO), (MH), (FH if installed), and terminator FA9 (A4). See Figure FA111-5. 4. Loosen the card gate screw and open the card gate. 5. If it is necessary to release the 8130, 8140, or 8101 flat cables, remove the cable straps to release the cables. 6. Disconnect voltage connectors J1 through J5, and J9. 7. Disconnect the ground connector from the gate casting. 8. Release the cables from under the board retainers by loosening the board retainer screws and lifting the retainers. 9. Disconnect the fan supply from terminal block TB2.
10. Unscrew the pivot nut from the upper pivot and lift the gate off both pivots.
Replacement Install the card gate in the reverse order to that used to remove it.
Note: If the 8130, 8140, or 8101 flat cables were released from the subframe cable clamp, rec/amp the cables with the rubber straps as shown.
Allow sufficient slack cable around the pivot area of the card gate (the length of cable should be approximately 240 mm (1 inch) from the cable clamp to the end of the socket.)
P1
D 2
P2
P.Connector
as viewed
P7
when plugged
P3
PS
Board Retainers 8130, 8140, or 8101 Flat Cables
SY27-2521·3
(FA541-FA551)
5-FA-75
FA552 Board Removal/Replacement
Removal 1. Switch off electrical power 2. Remove the cable clamp and the card cover. 3. Unplug the cards and the flat cable connectors. 4. Note card part numbers and locations. 5. Open the card gate. 6. Unplug the voltage connectors from the pin side of the A1 board. 7. Loosen four screws holding the board retainers and lift out.
Replacement 1. Install board A1 in the reverse order to that used to remove it.
FA553 Voice Coil Motor (VCM) Driver Card Removal/Replacement
The card is screwed to the inside of a plastic cover attached to the right-hand end of the card gate.
Removal 1. Unplug the voltage connectors J7, JS, and J 10. 2. Remove the cover screws and cover. 3. Remove card retaining screws and card.
Replacement 1. Install the VCM driver card in the reverse order to that used to remove it.
SY27-2521·3
5-FA-76
FA560 Card Gate Fan Removal/Replacement
Removal
Caution: Before removing the fan, note the 'direction-of-airflow' arrow to ensure that the fan can be refitted correctly.
1. Remove all power from DSD. 2. Disconnect the fan supply wires from terminal block TB2 and the adjacent ground
screw. 3. Loosen the card gate screw and open the card gate. 4. Release the fan retainer at the rear of the card gate and withdraw the fan from the
card gate.
Replacement 1. Install the card gate cooling fan in the reverse order to that used to remove it.
Fan Support
Terminal Block TB2 Fan Retainer
FA570 Drive Motor and Drive Belt
FA571 Drive Motor
Drive Motor Characteristics
The drive motor is fitted with a thermal cutout that prevents overheating of the motor. The thermal cutout will not reset until the motor has cooled.
Caution: Switch off all power to the DSD before pressing the Thermal Reset button.
60-Hz Motor (Early Style)
TB1 50-Hz Motor
Thermal Reset Button (Push to Reset)
Button
The following table shows the motor frequencies and voltage ranges:
Country U.S.
Hz
Nom Min
Max
60
120
104
127
Other than
60 100
U.S. & Canada
110
90
110
96.5 119
120 104
127
127 111
137
200 180
225
208 180
225
220 193
238
230 201
254
240 201
254
Other than
50 100
U.S. & Canada
110
90
110
96.5 119
200 180
220
220 193
238
230 202
249
240 210
259
Note: Drive motor input VAC may be measured at T81.
SY27·2521·3
(FA552-FA571)
5-FA-77
Drive Motor Assembly Removal/Replacement
Removal The drive motor assembly is a field replaceable unit (FRU) that consists of the motor, the motor bracket with pivots, and the driving pulley.
1. Switch off electrical power. 2. Remove the spindle lock bracket. 3. Disconnect operated lock mounting bracket from the frame. 4. If removing the motor for DE replacement, go to step 7. 5. Remove the motor terminal block TB1 cover. 6. Disconnect the wires from TB 1 and the adjacent ground screw. 7. Loosen the two belt guard screws and slide the belt guard off. 8. Push the motor against the belt tensioner and turn the tensioner shaft so that the
tensioner spring is held in compression. 9. Remove the tensioner mounting screws and remove the tensioner. Allow the belt to
support the weight of the motor. 10. Remove the retaining ring (C clip) from the motor pivot. 11. Supporting the weight of the motor, remove the belt, then move the motor toward
the rear until the pivots are clear of the holes.
Note: The motor pivot bushings might fall off as the motor is removed.
12. Remove the pivot bushings and inspect them carefully; if they are damaged, renew
them.
'Tensioner Mounting Screwsl
SY27·2621·3
REA 06-88481
Belt Tensioner
Spindle Lock Bracket Spindle Lock Bracket Screws
Belt Guard
Motor P11/J11
Belt Guard Screw
Bushing
Retaining Ring
Spindle Lock _ __ Bracket
5·FA·78
To left side Drive Motor---.3..
Operate - - - - . .
·
Switch
-----11----+1·
Assembly
Replacement 1. Install drive motor in the reverse order of removal. 2. Adjust the belt tensioner as detailed in FA572.
FA572 Drive Belt
Drive Belt Tensioner
1. Switch off all power to the DSD. 2. Pull the shaft and turn it through 90 degrees so that it locks in the 'out' Position. 3. Loosen the two mounting screws. 4. Allow the tensioner assembly to find its own position resting against the motor
bracket. 5. Retighten the two mounting screws. 6. Turn the shaft and release it so that it is pulled into the operating position.
Mounting Screws
, __Pull and__tu..rn to 'out' position
I
~~:=JJ
Spring
\ _ Shaft (Shown in operating position)
Drive Belt Removal/Replacement
Removal
Caution: Do not turn the DE spindle pulley counterclockwise as this may damage the heads and disks.
1. Switch off all power to the DSD. 2. Loosen the two belt guard screws and remove the belt guard. 3. Lift the motor against the force of the belt tensioner and lift off the belt. 4. Gently lower the motor till it rests on its stop.
Antistatic Brushes
Replacement Make sure that the belt to be fitted is clean, dry, and not frayed or otherwise damaged.
1. Push the motor against the tensioner and fit the belt centrally on the pulleys. Note: The smooth side of the belt should bear on the faces of the pulleys.
2. Allow the motor to be supported by the belt. Fit the belt guard and tighten the screws.
3. Adjust the tensioner. 4. Refit the belt guard.
Drive Belt Belt Guard Screw
Antistatic Brush
Antistatic Brush
The antistatic brushes are accessible when the belt guard is removed as described in the previous procedure. When fitting a new brush, ensure that the carbon brush is centered on the associated pulley. Refit the belt guard.
SV27·2521-3
(FA571 Cont, FA572)
5-FA-79
FA580 Brake Assembly and Coil Removal, Adjustment, and Replacement
SY27·2521·3
Removal
Caution: When the brake assembly has been removed, do not turn the DE spindle pulley counterclockwise as this may damage the heads and disks.
1. Switch off all power to the DSD. 2. Loosen the two belt guard screws and remove the belt guard. 3. Push the motor against the force of the belt tensioner and lift off the belt. 4. Disconnect wires 1 and 2 from the brake coil. 5. Remove the two screws that attach the brake assembly and lift out the brake
assembly complete with the antistatic arm.
Adjustment 1. Switch off all power to the DSD. 2. Remove the belt guard. 3. Check that there is a gap of 0.25 mm (0.010 in.) between the coil core on the base and the armature. If not, adjust the brake as follows: a. Insert a 0.25 mm (0.010 in.) feeler gauge between the coil core and the armature, and hold the two castings and the pulley together, as shown.
Note: Ensure that the feeler gauge is clear of the small coil spring (not illustrated) recessed in the armature.
b. Tighten the two mounting screws. c. Remove the feeler gauge. d. Recheck the adjustment.
Replacement 1. Attach the brake and coil loosely to the DE with the two brake mounting screws. 2. Attach the antistatic brush arm to the core casting with the brush arm screw. 3. Adjust the brake as follows: a. Insert a 0.25 mm (0.010 in.) feeler gauge between the core casting and the armature casting, and hold the two castings and the pulley together.
Note: Ensure that the feeler gauge is clear of the spring (not illustrated) recessed in armature.
b. Tighten the two brake mounting screws. c. Remove the feeler gauge.
Caution: The wires 1 and 2 must be connected to the correct terminals (marked 1 and 2) on the coil.
Belt Guard Screw Brake Assembly and Coil
5-FA-80
Belt Guard'
Motor
Antistatic Brush Arm
4. Connect wires 1 and 2 to their respective coil terminals marked 1 and 2. 5. If necessary, adjust the antistatic brush arm until the brush bears centrally on the DE
pulley spindle. 6. Lift the motor against the force of the belt tensioner and fit the drive belt. Ensure
that the smooth side of the belt bears on the pulleys. Allow the motor to be supported by the belt. 7. Fit the belt guard and tighten the belt guard screws.
Brake Mounting Screws
Feeler Gauge
0.25 mm (0.010 inch)
FA590 Actuator Lock Knob and Lock/Operate Switch Adjustment
Actuator Lock Lever Cable Adjustment 1. Position both Lock/Operate lever and Actuator Lock Knob Arm in the LOCK position. 2. If cable has been removed, insert control cable into levers. 3. Tighten cable clamps (see insert for correct position of the clamp). 4. Adjust outer sleeves of cables and tighten clamps as required to give satisfactory lockout operation. Provide full travel of the actuator lock arm on the DE in both lock and operate positions.
Use the following figure to locate and adjust the Lock/Operate lever cables. Lock/Operate Switch Adjustment
1. Place the Lock/Operate lever in the OPE RATE position slot. 2. Adjust the switch down, and rotate counterclockwise until the switch actuator over-
travel is taken up. 3. Tighten screws.
To right side Disk Drive Actuator Lock Knob
To left side
Note: The ACTUATOR LOCK KNOB ARM has been known, in some cases, to slip around the ACTUATOR LOCK KNOB. This could result in an improper unlocking condition, even though the ACTUATOR LOCK KNOB ARM is moving its full travel.
Visually inspect to see that the ACTUATOR LOCK KNOB turns with the full travel of the ACTUATOR LOCK KNOB ARM, while operating the LOCK/OPERA TE LEVER.
Operate - - - . . i
·
Lock/Operate Switch Assembly
Lock/Operate Lever
Spindle Lock _ _..,. Bracket
Shock Mount (Lower)
Long Nut
Actuator Locj(
Knob Arm
REA 06-88481
SY27·2521·3
Subframe
X-A1A5
(FA580. FA590)
5-FA-81
SY27-2521-3 This page intentionally left blank.
5-FA-82
Chapter 5. MAP Reference Information Power (PA)
SY27·2521-3
5-PA-i
Introduction
This part of Chapter 5 provides maintenance information to service the 8130/8140/ 8101 power. The PA MAP guides you in isolating power failures, and refers to this part of Chapter 5 for locations, adjustments, service checks, or replacement procedures.
This part has seven sections: 1. General Information (PA100-PA130): Contains information on PA configuration,
operation, and repair strategy. 2. Offline Tests (PA200-PA253): Contains test information and failure plans.
3. Intermittent Failure Repair Strategy (PA300-PA310): Contains information to repair intermittent failures.
4. Signal Paths (PA400-PA466): Contains figures and wiring charts which show wiring and signal paths.
5. Adjustment, Removal, and Replacement Information (PA500-PA540): Contains information for adjusting the plus 5 volt de and for removing the LED and BOP.
6. Service Checks (PA600-PA680): Contains information for checking transformers, diodes, and voltages.
7. Locations (PA700-PA760): Contains information for basic locations.
SY27-2521-3
Contents
5-PA-ii
PA100 General Information . . . . . . . . . · . PA110 Components . . . . . . . . . . PA120 Basic Operational Description .
PA121 PSCF Power Control Logic . 8130 PSCF Power Control Logic 8140 Models AXX PSCF Power Control Logic 8140 Models BXX PSCF Power Control Logic
PA122 Not Used PA123 Attached 8101 Power-On Control. . . . . PA 124 DC Overvoltage and Undervoltage Sensing PA130 Power-Unique Repair Strategy .
PA200 Offline Tests . . . . · . . . .. PA210 PA MAP Menu Options . . . .
PA211 PA MAP Options for 8130, 8140, and Undetermined Power Problems . . . . . . . . . . . . . . . . . .
PA212 PA MAP Options for 8101 Power Problems. PA250 Action Plans . . . . . . . . . . . . . . . . . .
PA251 Possible Causes of Failure - General . . . . PA252 Possible Causes of Failure Using the Status of 8101
Fuses and Indicators . . . . . . . . . . . . . . . . PA253 PC-2/PC-3 01C Disk Drive Power Fault Isolation
PA300 Intermittent Failure Repair Strategy. · . . . PA310 General Intermittent Failure Repair Strategy
PA400 Signal Paths and Detailed Operational Description. PA405 Safety Grounds . . . . . . . . . . . 8130/8140 Models AXX Safety Grounds . . . . . 8140 Models BXX Safety Grounds . . . . . . . . 8101 Models A1X, A20, and A23 Safety Grounds. 8101 Model A25 Safety Grounds . . . . . . .
PA410 60-Hz AC Power (U.S. and Canada) . . . . . PA411 8130 60-Hz AC Power (U.S. and Canada) PA412 8140 60-Hz AC Power (U.S. and Canada) 8140 Models AXX 60-Hz AC Power (U.S. and Canada). 8140 Models BXX 60-Hz AC Power (U.S. and Canada). PA413 8101 60-Hz AC Power (U. S. and Canada) . . . .. 8101 Models AlX, A20, and A23 60-Hz AC Power (U.S. and Canada) . . . . . . . . . . . . . . . . . . . . . 8101 Model A25 60-Hz AC Power (U.S. and Canada) .. .
PA420 60-Hz AC Power (Other Than U.S. and Canada) . . . . . PA421 8130 60-Hz AC Power (Other Than U.S. and Canada) . PA422 8140 60-Hz AC Power (Other Than U.S. and Canada) . 8140 Models AXX 60-Hz AC Power (Other Than U.S. and Canada) . . . . . . . . . . . . . . . . . . . . . 8140 Models BXX 60-Hz AC Power (Other Than U.S. and Canada) . . . . . . . . . . . . . . . . . . . . . PA423 8101 60-Hz AC Power (Other Than U.S. and Canada) . 8101 Models A 1X, A20, and A23 60-Hz AC Power (Other Than U.S. and Canada) . . . . . . . . . . . . . . . . . 8101 Model A25 60-Hz AC Power (Other Than U.S. and Canada) . . . . . . . . . . . . . . . . . . . . . . . . .
5-PA-1 5-PA-1 5·PA·3 5-PA-6 5-PA-6 5-PA-7 5-PA-8
5-PA-9 5-PA-10 5-PA-10
5-PA-11 5-PA-11
5-PA-11 5-PA-11 5-PA-12 5-PA-12
5-PA-12 5-PA-12
5-PA-13 5-PA-13
5-PA-15 5-PA-16 5-PA-16 5-PA-17 5-PA-18 5-PA-19 5-PA-20 5-PA-20 5-PA-21 5-PA-21 5-PA-22 5-PA-23
5-PA-23 5-PA-24 5-PA-25 5-PA-25 5-PA-26
5-PA-26
5-PA-27 5-PA-28
5-PA-28
5-PA-29
PA430 50-Hz AC Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · PA431 8130 50-Hz AC Power . . . . . . . . . . . . . . . . . . . . . . . . . . . PA432 8140 50-Hz AC Power . . . . . . . . . . . . . . . . . . . . . . . . . · · 8140 Models AXX 50-Hz AC Power . . . . . . . . . . . . . . . . . · . . . 8140 Models BXX 50-Hz AC Power. . . . . · . . . . . . . . . . . . · . . . PA433 8101 50-Hz AC Power . . . . . . . . . . . . . . . . . . . . . . . . . · . 8101 Models A1X, A20, and A23 50-Hz AC Power ......··... 8101 Model A25 50-Hz AC Power . . . . . . . . . . . . . . . . . . . . . . .
PA440 DC Power · . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . ...· · PA441 8130 DC Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . · . PA442 8140 DC Distribution . . . . . · . . . . . . . . . . . . . . . . . . · . . . PA443 8101 DC Distribution . . . . . . . . . . . . . . . . . . . . · . . . · . · .
PA450 Power Logic Interconnections .·.·..........·.....·... PA451 8130 Power Logic Interconnections . . . . . . . . . . . . . . . . . . . PA452 8140 Power Logic Interconnections ........·....·..... PA453 8101 Power Logic Interconnections. . . . . . . . . . . . . . . . . · .
PA460 Power Card Assemblies . . . . . . . . . . . . . . . . . . · . . . . . . . . · . PA461 PC-1 Power Card Assembly . . . . . . . . . . . . . . . . . . . . . . . . PA462 PC-2 First-Disk -4V Regulator and Sensing Logic Card ..... . PA463 PC-3 Power Sequence Card . . . . . . . . . . . . . . . . . . . . · . . . PA464 PC-4 8101 Power Sequence Card . . . . . . . . . . . . . . . . . . . . . PA465 PC-50 Second-Disk -4V Regulator Card . . . . . . . . . . . . . . . . PA466 PC-51 Second-Disk Control Card ...... : . . . . . . . . . . . . . .
5-PA·30 5-PA-30 5-PA-31 5-PA-31 5-PA-32 5-PA-33 5-PA-33 5-PA-34 5-PA-35 5-PA-43 5-PA-44 5-PA-48 5-PA-52 5-PA-52 5-PA-53 5-PA-55 5-PA-58 5-PA-58 5-PA-60 5-PA-61 5-PA-63 5-PA-64 5-PA-66
PA500 Adjustment, Removal, and Replacement Information ....··.·· PA510 +5V DC Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . · · · · . · PA520 LED Removal and Replacement Procedure . . . . . . . . . . . . . . . . PA530 BOP Adapter Card Removal and Replacement Procedure ...... . PA540 How to Gain Access to BOP Components . . . . . . . . . . . . . . . . . PA550 01G Gate Capacitor and Thermal Replacement Procedure1 · · · · ·
5-PA-67 5-PA-67 5-PA-68 5-PA-69 5-PA-69 5-PA-70
\
PA600 Service Checks ········.·······.····.···.······· · · 5-PA-71
\
PA610 AC Ripple Service Check ·........... ; ..........·.... 5-PA-71
PA620 8130/8140/8101 Indicator Check . . . . . . . . . . . . . . . . . . . . . . 5-PA-72
PA630 Capacitor Resistance Check . . . . . . . . . . . . . . . . . . . . . . . . . . 5-PA-72
PA640 Transformer Winding and Diode Service Checks . . . . . . . . . . . . . 5-PA-74
PA641 01G Gate T2 Transformer Winding and Diode Service
Check . . . . · . . · . . . . . . · . . . · . . . . . . . . . . . . . . . . . . . . . . . 5-PA-74
PA642 01G Gate Power Supply Diode Isolation . . . . . . . · . . . . . . . . 5-PA-74
PA643 Transistor Q1 and Q2 Check . . . . . . . . . . . . . . . . . . . . . . . 5-PA-75
PA650 Fuse and Voltage Distribution .............·.....·.·.. 5-PA-76
PA660 Voltage Verification ..............·.·..........·. PA661 System DC Voltage Verification ....·...·.......... PA662 PC-1 Card AC and DC Voltage Verification .·.·.·...·.. PA663 PC-2 Card DC Voltage Verification ...........·..··.·
PA670 Power Status Indicators and Their Meaning ...........·.· PA680 8140 Model BXX DC Parallel Wiring Check .·.........··.
5-PA-78 5-PA-78 5-PA-79 5-PA-80 5-PA-80 5-PA-81
PA700 locations .·....·.....·.·.·.·.·....··········· PA710 Gate and Other Subassembly Locations ...·...........·
PA711 8130 Gate and Other Subassembly Locations ........·.· PA712 8140 Gate and Other Subassembly Locations ......·.... PA713 8101 Gate and Other Subassembly Locations .......... . PA720 Operator Panel Component locations ........·.....·.. PA721 8130/8140 Basic Operator Panel Locations .·.......... PA722 8140 Expanded Function Operator Panel Locations ..... . PA723 8101 Operator Panel Locations ....·............·..
PA730 OH Gate (1/0 Panel) Locations ........·............. PA731 8130 OH Gate Locations . . . . . . . . . . . . . . . . . . . . . . . . PA732 8140 OH Gate Locations ..........·.·........... PA733 8101 OH Gate Locations . . . . . . . . . . . . . . . . . . . . . . . .
PA740 01G Gate Power Supply Component Locations .......... . PA741813001G Gate Power Supply Component Locations PA742 8140 01G Gate Power Supply Component Locations .·... PA743 8101 01G Gate Power Supply Component Locations .....
PA750 Board DC Voltage Distribution . . . . . . . . . . · . . . . . . . . . . . PA751 8130 Board Voltages . . · . . . . . . . . . . . . . . . . . . . . . . . . PA752 8140 Board Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . PA753 8101 Board Voltages ...............·.·...·.·... PA754 Disk Board Signal and Voltage Distribution 01C and 01 E Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PA755 Diskette Signal and Voltage Distribution (010 Gate) · · · · · ·
PA760 Board and Cable Connectors ........·.....·.·......
5-PA-83 5-PA-83 5-PA-83 5-PA-84 5-PA-89 5-PA-91 5-PA-91 5-PA-92 5-PA-93 5-PA-93 5-PA-93 5-PA-94 5-PA-95 5-PA-96 5-PA-96 5-PA-97 5-PA-98 5-PA-100 5-PA-100 5-PA-102 5-PA-104
5-PA-105 5-PA-106 5-PA-107
SY27-2521-3
5-PA·iii
Figures
PA110-1. 01G Power Gate Hardware Configuration, Rear View .. PA120-1. Power On/Off Sequence Timing. . . . . . . . . . . . . . PA120-2. Basic Power-On Logic for Machines with One Disk Drive . PA120-3. Basic Power Distribution . . . . . . . . . . . . . PA123-1. 8101 Unit Power-On Signal Sequence Timings .. PA124-1. DC Overvoltage/Undervoltage Sensing Summary .
PA253-1. PC-2 J16 Input/Output Levels . . . PA253-2. PC·3 Power Reset Line Distribution PA440-1. 8130 DC Power . . . . . . . . . . . PA440-2. 8140 Models AXX DC Power . . . . PA440-3. 8140 Models BXX DC Power (2 parts) PA440-4. 8101 Models A 1X, A20, and A23 DC Power . PA440-5. 8101 Model A25 DC Power . . . . . . . . . . PA442-1. 8140 Models AXX DC Distribution (2 parts) . PA442-2. 8140 Models BXX DC Distribution (2 parts) . PA443-1. 8101 Models A1X, A20, and A23 DC Distribution (2 parts) PA443-2. 8101 Model A25 DC Distribution (2 parts) . . . . PA452-1. 8140 Models AXX Power Logic Interconnections PA452-2. 8140 Models BXX Power Logic Interconnections PA453-1. 8101 Models A1X, A20, and A23 Power Logic
Interconnections . . . . . . . . . . . . . . .. PA453-2. 8101 Model A25 Power Logic Interconnections PA465-1. PC-50 Card Signals . . . . . . . . . . PA466-1. 8140 Models BXX PC-51 Card Signals PA466-2. 8140 Model A25 PC-51 Card Signals PA510-1. +5V DC Adjustment . . . . . . . . . PA520-1. LED Assembly . . . . . . . . . . . . PA530-1. Basic Operator Panel Adapter Card (01 B). PA540-1. BOP Frame Mounting. . . . . . . . . . PA641-1. 01G Transformer and Diode Locations .. PA642-1. Diode Check Wire Removal . . . . . . . . PA650-1. 8130 Fuse Specifications and Voltage Distribution Chart. PA650-2. 8140 Models AXX Fuse Specifications and Voltage
Distribution Chart . . . . . . . . . . . . . . . . . PA650-3. 8140 Models BXX ·Fuse Specifications and Voltage
Distribution Chart . . . . . . . . . . . . . . . . . PA650-4. 8101 Fuse. Specifications and Voltage Distribution Chart. PA662-1. PC-1 Connector Locations . . . . · . . . . . . . . · . . . . . PA663-1. PC-2 Connector Locations . · · . . . . . . . . . . . . . . PA712-1. 8140 Models AXX Gate and Other Subassembly Locations. PA712-2. 8140 Models BXX Gate and Other Subassembly
Locations (4 parts) . . . . . . . . . . . . . . . . . . . . . PA713-1. 8101 Models A1X, A20, and A23 Gate and Other Subassembly
Locations . . . . . . . . . . . . . . . . . . . . . . . . . PA713-2. 8101 Model A25 Gate and Other Subassembly Locations
PA732-1. 8140 Models AXX OH 1/0 Panel Locations . PA732-2. 8140 Models BXX OH 1/0 Panel Locations . . . . . . .
5-PA-2 5-PA-3 5-PA-4 5-PA-5 5-PA-9 5-PA-10 5-PA-12 5-PA-12 5-PA-35 5-PA-37 5-PA-38 5-PA-40 5-PA-41 5-PA-44 5-PA-46 5-PA-48 5-PA-50 5-PA-53 5-PA-54
5-PA-55 5-PA-57 5-PA-65 5-PA-66 5-PA-66 5-PA-67 5-PA-68 5-PA-69 5-PA-69 5-PA-74 5-PA-75 5-PA-76
5-PA-77
5-PA-77 5-PA-78 5-PA-79 5-PA-80 5-PA-84
5-PA-85
5-PA-89 5-PA-90 5-PA-94 5-PA-94
SY27-2521-3
Abbreviations
BOP CAP EFP FRU Hz IPL
LED MAP
av
PN POR PSCF SCF SCR SSCF TB UV
basic operator panel channel request priority expanded function operator panel field-replaceable unit Hertz initial program load light emitting diode maintenance analysis procedure overvoltage part number power-on reset Primary System Control Facility System Control Facility silicon-controlled rectifier Secondary System Control Facility terminal block undervoltage
5-PA-iv
PA100 General Information
DANGER With the power cord connected to the wall outlet, line voltage and the +5 and +24 control voltages are always present in all:
· 8130s, 8140 Models AXX, and 8101s. · 8140 Models BXX with the line voltage circuit breaker (CB1) on.
Before removing metal covers or internal power components (except for power control (PC) and logic cards), either (1) disconnect the power cord for all 8130s, 8140 Models AXX, and all 8101s, or (2) turn off,CB1 for 8140 Models BXX.
Note: If the +5V or +24V control voltage is missing, the 8130/8140/8101 will not power up.
Eight system voltages are developed from the 01G-T2 transformer windings: +5, +8.5, +12, +24, -5, -8.5, -4, and -12 volts. If the disk storage is not installed, only the -5 volts is sensed. If the -5 volts is not present, the 8130/8140/8101 will not power on. If the disk storage is connected, +12, +24, -4, -12 and one +5V supply are sensed to ensure that the voltages are present. See PA124 for more information on voltage sensing.
A thermal switch is located in the 01A gate, and manual reset thermal circuit breakers are located in the 01C and 01E gate disk drive motors. Excessive gate temperature will cause the 01 A gate thermal switch to open and the machine will power down. Excessive motor temperatures causes the disk drive thermal circuit breaker to open and turn off ac power to that disk drive motor. All other power remains on. If the disk storage is connected and the disk drive fails to get up to speed, the power to that disk drive motor drops in approximately 20 seconds. This 20-second time-out can also result from an open thermal switch in the motor, a broken or misaligned drive belt, a deenergized disk motor brake, or the lock-operate lever not in the operate position.
The 8130/8140/8101 can be connected to one of several different line voltage sources. The 01G gate power supply contains one of three types of ferro transformers in the line voltage circuit. Which type of transformer is installed depends upon the country and frequency of the source voltage. All of the transformers have the same output voltages and power controls; the only differences are the input voltages and frequency. The following table lists the transformer part number for the appropriate input voltages and frequencies:
Input Voltage
Frequency Phase Where Used
Transformer Part Number
120 Note 1
60 Hz
U.S. and Canada 7389040
208, 240
60 Hz
U.S. and Canada 7389042
100/110/115/120/127/ 200/208/220/230/240
60 Hz
Other than
7389042
U.S. and Canada
100/110/200 220/230/240
50 Hz
*The value of C12 must be 15 microfarads. **The value of C12 must be 18 microfarads.
Other than
7389041*
U.S. and Canada 7389297**
Note 1: Check all voltages with CE voltmeter (PN 1749231 or equivalent), using meter lead set PN 453697 and either probe set PN 453698 or probe PN 453718.
PA110 Components
The PA power is made up of a line cord, the basic power gate (01G) other power gates (8140 models BXX), and the distribution to other components. Mounted on the rear of the 01G gate are transformers 01G-T1and01G-T2, line filter (FL1) mounted on TB4, card PC1, and various capacitor, fuse, and diode modules. The PC3 and PC4 cards mount on the PC1 card. The PC2 card is part of the -4V supply for the first disk drive, and mounts on the front of the 01G power gate for 8130s, 8140 Models AXX, and 8101~ and on the M/N gate ofr 8140 Models BXX. The PC50 card is part of the -4V supply used for the second disk drive. See Figure PA110-1 and PA740 for 01G component locations.
You must know the unit model number to use this power section of the MIM. Always verify the model number.
Note: The 8101 does not have a convenience outlet or fuse F13.
REA 06-88481
SV27-2521-3
(PA100 - PA110)
5-PA-1
SY27-2521-3
REA 06-88481
0 (8130/8140 only)
Figure PA110-1. 01G Power Gate Hardware Configuration, Rear View
5-PA-2
PA120 Basic Operational Description
Line voltage is supplied to the system through the line filter, TB4, and fuse F11 to control voltage transformer 01G-T1. The secondary windings of T1 develop two control voltages that are present as long as the power cord is connected to the line voltage, except on 8140 Models BXX (see PA 100). These control voltages (+5V CTL and +24V CTL) are used to start the powerup sequence, and the absence of either voltage will prevent system power from cycling up.
When the main power switch is placed in the on position, K2 is picked and ac power is applied to transformer 01G-T2, the diskette drive motor, and all fans. After a time delay to permit the de voltages to stabilize, ac power is applied to the first disk drive motor through the points of contactor K1 (see Figure PA120-1) and approximately 5 seconds later, to the second disk drive motor (if installed) through K50.
The secondary windings of T2 develop the system voltages which are distributed to the 01A gate through 01G-TB1, 01A-TB1, and 01A-TB2. The system voltages are further distributed by jack connectors to the different functional components. See Figure PA 120-2 for basic power on logic, Figure PA 120-3 for the basic power distribution, and PA440 through PA443 for more detailed information on de distribution.
When 8101 units are attached to the 8130/8140, they are powered up using the following procedure:
1. Set the 8101 power control switch to Remote.
<I) 2. The main power switch should be set to the On position on all of the attached
8101s.
<I). 3. Set the 8130/8140 power switch to the Power On position
4. The system control facility (SCF) will then send a turn-on signal to each 8101 in a timed sequence.
If the 8130/8140 system is inoperable, an 8101 may be powered up by first setting the unit power control switch to Local and then set the 8101 power switch to On (I).
Power On
Power Off
y
,I...
+Switch On
+ 5V Cntl Measure at 01G-J8B15
... I
I
l
f
I
1. . .
I I I l
I
I
I
_l_
TD1 (PC3 Card): 215 to 430 ms
...,
I
J
I I
1
TD2 (PC3 Card): 330 to 710 ms
Pick K2 AC to Ferro
Down Level Measure at 01G-J13-2
Sys POR
Up Level Measure at 01M-J16B07
+ Pwr Good
Up Level Measure at 01N-J53-10
I
I
I
I
I I I
,,.l
. , I Note
I
I I
..L
I I I
T 1
I
TD4 115 to 280 ms
1.. I
_.1 I
I
I
I
J
- Pwr Good
Down Level Measure at 01C-J1-3
Pick K1 - Brk Off
Down Level Measure at 01C-J5-4
Internal Power Supply -POR
I Second Disk Delay I (PC51 Card)~ 5 sec
I~...
I
I
_l
... ,
I
I
+Start VE
Up Level Measure at 01G-J12B07
I
_l
I I
I
I I
T
I
I
TD3 (PC3 Card):
I
5.2 to 11.6 sec
1-1111
POR1
I
I
l
I
1. . . . . . . ,
l I
Note
1 I
I
I
. 'I
+VE
rI f
- Pwr Good
Pick K50 - Brk Off
... , -POR1
I I
(+VE)
I
~"'
Down Level i.L
Measure at
~
01 E-J1-3
0
N
-s
·~
Down Level
.~ c:
Measure at
:::>
01 E-J5-4
0
u.
Up Level Measure at 01A-A1Z1 805
\
For Units with 1 Disk File
Note: The disk determines the timing relationship between the Power Good and Brake On/Off signal.
I
~Note ~
I
I
I
I
I
I
I
~ _.,Note
I
I
I
I
Figure PA120-1. Power On/Off Sequence Timing
REA 06-88481
SV27-2521-3
(PA110 Cont - PA120)
5-PA-3
0 +24V Ctl
r_____ BOP Panel
[ K 1 Relay
( K2 Relay]
- V L >_-____.,.._+_24_V_C_tl_ _ _
Y;_+-)--tf.,__--t-¥'-ll(;._~~~~-
O +5V Ct_I
u
Main Povver Switch
+5V Ctl
(Present with the power cord connected.)
01C Gate
0.2V Ref
Power Good
.---+-"""'-H~--o-e_la_v_ _"'""S ~l--t--N_o_t_B_ra_k_e_A_P_P_h_·e_d_ _ _ _ ___,
SV27-2521-3
REA 06-88481
0.2V Ref
A
PC3 Card
Time Delay ~-------1 Driver
1
l_ _ _ _ _ _...o~DC
-eommon
-POR 1
~ TD2
TD3
-
-POR 2 -POR3
+ Loss of Voltage
PC2 Card
F
+5V
L----' TD4
-POR
+ Contacts Closed (K2 Aux NO)
+ Disk Drive lntlk Switch -POR
r--< OR A
--.____.._ _.s FL
~R
'------'
- File Fault
- Power Good +Power Good
PC4 Card 8101
8140 A2 Board
-Sys Off A
Unit Power Ctl Sw
-Unit PwrCtl -0~
- Remote On
8101 SC5 Card
8130 A 1 Board
-__ -POR 3
Note: For more detail see individual components; for machine with two disks, see PA40a Figure PA120-2. Basic Power-On Logic for Machines with One Disk Drive
5-PA-4
Input AC
Line Filter
01G-TB4
L-T1
D
Line Voltage
Circuit
Breaker
AC
(CB1)
II
Power On Control
Notes:
I I 8140 Models BXX Only t i 8101 Only I I 8101 Model A25 and 8140 Models BXX Only.
Figure PA120-3. Basic Power Distribution
Disk 2
K50
Motor
II
IJ
Disk 1
K1
Motor
Convenience Outlets
K2
Fans and Diskette Motor
AC
Power
DC
T2
Supplies
DC Dist
r---
PC3
AC T1
PC1 Sense
PC2 Sense
REA 06-88481
SV27-2521-3
PC50
PC51
ID
PC4
Bl
01C Gate (Disk 1)
01 E Gate (Disk 2)
IJ
(PA120 Cont)
5-PA-5
PA 121 PSCF Power Control Logic
8130 PSCF Power Control Logic
8101
r-1_,__
-POR1 (+VE)
~> J11D07 ~~, JB A15
~
PC3CARD
01A-A1 BOARD
TOK2 RELAY
_ll..,.~
L_f""
t
01H·S1 Remote/ Local Switch
-Sys Off
~*-1
J9B07
l
,___....f<(m..> S05 SC5
(A1A2)
.......... J12B13
+5V
[ l
r--A>i C-T-R-L-. U05
1
J12B02
[ J12D02 ~) J9B06
~A>l S04
Y03 .,...._
- X32 [..,...,.....
X33 VL..
X13 i.-...............,
X02 _,.,_.,..-...., X03 v.L.
01TAID3
,... - ..,
I
D03
L '""'
r - - B12
I "I
I
813
I ''I
I
D13
I
I
002
I 'I
I
003
..___,.~
+CRP=B +CRP=4 +CRP=2 +CRP=l +XMIT CONTROL +HOLD PWR ON
J12DDtG
PC4 CARD
,,,,, J12D13 ...
~..
J9B03
PC1 CARD
"---------~-.;·-.-----~U-J~J...LJA1oDn2
·
01T-
01A-A2 _ _ _ _T_..!_______
A 1E2
1 BOARD
SC5
r-
X03 t<'t..-....,.,J:E:"'"tt-t1H-t--:-,-<~;f-=D;.::0:,:3_______
~K4 ~ .....,..,,so4
l - 804
K4 ~>luos
005
!A2A2)
X02 ~~ X131.<¥ x33 i.....-......... ..... /
I _,.,,_ 002
I -.......--
1 /L D13 I -.......-
I _,...,... 813
4 '---K-Jc'L..-~>i 505
X32L(~
805
vo2i..-~
"------------~ ~
I /L 812
L:::~ r--< D03
I -.....-
L._,
01TA1E3
Notes:
D -SEQ COMP H6A04 (Z3802) A6D04 IZ1802)
f l -POR1 (+vE) H6804 (Z3803) A6E04 (Zl 803)
D +o0 HZ CONTROL A6D02 (Zl D02)
a SQUARE AC A6D04 (Z1B02)
I I -REMOTE PWR OFF A6E04 (Zl 803)
I I -PORll+VE)
86804 (21805)
MODE: LS A3X, A4X ASX A2X
MODELS A3X,A4X ASX A2X MODELS ~
MODELS ~
MODELS ~
MODELS ALL
I I +5V CTRL 86802 (Zl D05)
0 -TURN ON 86A04 IZ1804)
MODELS ~ MODELS ALL--
I I 810101A·A1 and01A·A2are feature boards.
To 8101 /8809 and ends with a terminator.
SY27-2521-3
REA 06-88481
01A-A2 BOARD
set
(A2G2)
Y22
8130
REMOTE PWR OFF
TO K2 RELAY
01T·
-A1E., 3
D03 _,,_..._I ~J
B12 i_.,._.,: 1
r""" I
813 :...,....,.. I I
D13 ~..... I
17"' I
· D02 ~.... I
D03 ' - ' I
...,...~J
01T-
A1E2
~1 Y03 ...,,....., X32 ~.... X33
~"" X13
X02 ~-..
~
7"'' X03
~:;j X03
~) X02
~>X13
~~X33 ~)X32
~)Y03
SC2 (A2F2) SC4 (A2D2)
SC5 (A2C2)
JBA16 -........-- J11 D04i<~
U04 ~
+60 Hz CONTROL
12 VAC
J13·6
Tl-7 ~f"+--J1-1-J-13-«!~i!=-..J
D U05 VL. ~
-POM (+VE)
PCJ SEO CARD
U04 ~D
I
t z 0 >I- ...J ffi ~
J11807r-~
J7 8
_. . _,.
f<..J 1~fl ~:r [ ' '
!%: :IE
J11B08 DC
~ r
.i7-lCOMMON
i'~ ::::> 0
15
""ID
·~ll
J8A 15
J 11 D07 l<L__f -
sos l<'...,.~.--+~_J
· -SEQ COMPLETE
PC1 CARD
J8A12 -..~
(( J 12808
5-PA-6
8140 Models AXX PSCF Power Control Logic
8101
-POR 1 (VE)
ey, ~ J11D07
!>'
J8 A15
PC3 CARD
G TOK2
RELAY
J11J10
t
01H-S1 Remote/ Local Switch
-Sys Off
~)~807
~f<<m» 505
....... J12B13
+5V
l
J . l __,,,_ J12802
CTRL
~
r-.A> U05
[~ J12D02 v
J12DoJ
J9B06 -TURN
i.-:A> 504
rN
01A-A2
BOARD
PC4 CARD
J12D13 -""-' J9803
PC1 CARD
r~ ...... ~... 504 K4 '-':~> U05 005
1-:~> sos
K4 805
SC5 (A1A2)
J_
' I
SC5 (A2A21
01A-AI BOARD
Y03 ~~
X32 ....
X33 ....
X13
1.--L............
X02 -'-"'-
I''-...,
·--- X03 "-"'-
01T-
AID3
- ,.. -
I
003
L_
r- - 812
I
I
813
I
I .... 013
I
I
002
I
- 003
I -·
on-'-
A102
X03 ..,......
X02 ..,...... X13 .....~ X33 c , . /
X32 i.....~
1-=~
Y02
OH· A1E2
r003
I
I .,,.. 002
~
I
I _.,..._ D13
I
I -·
I
I_,._.,
813 812
L r::-..-· D03
I
L-01T· A1E3
+CRP=B +CRP=4 +CRP=2 +CRP=1 +XMIT CONTROL +HOLD PWR ON
01A·A1 BOARD
8140
REMOTE
SC1 (A1A2)
U12 ra...-.. g~ -
P11 1.6 ..........
1 ~1]
P-W--R-O-.F.F
JBA10 SQUARE
Y22
Y12 PIO j<<IJ:>)t---i AC
J J
-POR (+VE)
500 ms RATE (2 Hz)
t i
TO K2 RELAY
1cO- ~
J11 G02
OlT·
-A1.E, 3
003 1-- I
B12
I==~
bh
,,,1~ I
813 ~.... I
I
D13 ~... I
I
D02 ~... I
I'' I
003 u..... I
L' : _ J
01T·
A1E2
003 D02 D13 813 812 803
01T-
A1D2
...~-,
~ I
I
I
I
I'' I
I b.
~,
I
!
"
I
r- --~.,
I'' I
_ .J
01TA1D3
01A-A2 BOARD
...... Y03
............
~,,
X32
....... X33
/ __,.,,... X13
r ..... X02
X03
..... X03
.....___ X02
................. X13
.................... X33
.................... X32
~--,, YOO
_t
~
Y22
Y12
SC2 (A2A2)
SC4 (A2C2l
SC5 (A2D2)
,,
......_
JBA16
J11 004 ~
U04 ~
+60 Hz CONTROL
12 VAC
JlJ-6
T1-7 ~
vL.
JI I J13 I''
U05
It'..:.
~.
-PoF (+VE)
t
"<'
~
,,
PC3 SEQ CARD
....
U04 illB
z 0 >z Z t-- ...J
wO
J11807 I'' J7 8
g:w~ ~(xJ [
a:
~tl w
:IiLi x"'
J11B08 JJ. CODMCMON
0 - .::,>"coo
15
JBA15 "
J11 D07
S05 _,
·-SEQ
COMPLETE
PC1 CARD
I<<
((
J8A12
J12B08
Notes:
D -SEQ COMP H8A04 (23802) A6D04 (Z1B02)
MODELS A3X,A4X ASX
f l -POR1 (Vi;I H6B04 (Z3803)
A6E04 lziBOOI E6A04 (Z2803)
I I +60 HZ CONTROL
a A6D02 (Z1 002) SQUARE AC A6004 IZ1B02l
I I -REMOTE PWR OFF A6E04 (Z1803)
I I -PORI (+VE)
86804 (Z1 805)
MODELS A3X,A4X ASX A6X,A7X
MODELS ~
m - MODELS
MODELS ALL
MODELS ALL
I I +5V CTRL 86802 (Z1 0051
MODELS ALL
a:. 11!111 -TURN ON B6A04 IZ1804)
MODELS ~
Ir.ti 8101s . I 01A-A1 and 01 A-A2 are
feature boards.
I
I
To 8101/8809 and ends To 8101/8809 and ends
with a terminator.
with a terminator.
REA 06-88481
SY27-2521-3
(PA 121)
5-PA-7
8140 Models BXX PSCF Power Control Logic 8101
D ~' -POR 1 (+Vel
c.,:111D07 ., J8 A15
·
PC3CARD
01AA1 BOARD
SY27-2521-3
REA 06-88481
8140
SC1 (A102)
---REMOTE
PWR OFF
TO K2 RELAY
TOK2 _][...., J11J10
1.___P"-
RELAY
01 H·S1 Remote/ Local Switch
Svs 011
~ J9807
01TAID3
.. _,~m~ ,.. 7Y" S05
SC5 (A1A2)
~"' J12813
+5V
l 1
C_TR__L ..
~A~ U05
"I _.._, J12B02
[~...... J12D02 ......,
J12D03
J9B06
-TURN
r~
Ji~ 504
-
01A-A2
·
$
T
r --
Y03 ~v~~::::::::::::::--t--'~~~0~03~---~-_.:..:+C~R~P~-~8-------~~~~--+---~J
...I
L '':
X32 rl(:~~~:::::::--tt-l°"r~:_~;,~B~12~______.:..:+C~R~P~==4-------~~f.;i~~-i_,::'.::::__~J
I ''
X33 ~v.L~::::::::::1H-t-~~I<~~B~13:.__~----+~C~R~P~=~2-----~-~~~~--l.~~~~J
I
I ..........
I
013
+CRP=l
I ,·
I
002
I -...-,,.
+XMIT CONTROL
01TA1E2
I
L~~ J9803
PC4CARD
PC1 CARD
BOARD
r·· ~ -*); 504 804
K4 k~> U05
D05
SC5 (A2A2)
X02 ,_,,./
X13 L,.,..,,/
X33 ,_,,_/
I
K4 f<~> 505
805
X32 i.,.,__ _ . . . /
~ Y02 ....,...
'--~~-------_J
I ,,_,, 002
I
013
I
813
I
I
812
L-r- - 003
L --1
01TA 1E3
~> X03
...,~.. >1 X02
A-'~> X13 ~~>1 X33
'~~~> X32 ~ ,..t~~~,i Y03
01T-
Notes:
I I -SEQ COMP H6A04 (Z3802) A6D04 (Z1802)
-POR1 (+Vel H6804(Z3i03) A6E04 (Z 18031 86804
MODELS A3X, A4X ASX. BXX
MQQlli A3X,A4X
ASX BXX
IJ -+«! HZ CONTROL A6D02 (Z10021
MODELS ALL
-POR 1(+Ve) 86804 (Z1805)
MODELS ALL
I I +5V CTRL 86802 (Z1005)
MODELS ALL
111!'11 -TURN ON Sil B6A04 (Z1B041
m - MODELS
1J s10101A-A1 and 01 A-A2 are feature boards.
r-A-1,02
003 __,.,._.....
I'' I
002
I
,, I
013 813
I
----,-,,
I
(..,...., I ,, I
812
I
803 Ir-...-_:::,.J, ,, I
~-.J
01T· A1D3
,...,,, X03
...___
..._7"'"! X02 X13
~-,-...,,. X33
'--"---.,.-..-,,, X32
Y03 ~.._.._
---,.
a SOUARE AC A6D04 (Z18021 B6A02
MODELS
ALL EXCEPT BXX BXX
11!1 A2 board is present if there are mora than four ports or, if an 8809 is attached, or 1f there 1s a display/printer adapter.
To 810118809 and ends with a terminator.
To 810118809 and ends with a terminator.
. . . -REMOTE PWR OFF MODELS . . A6E04 IZ1803)-- ALL -
Y12 SC2 (A1C2) SC4 (A1A2)
01A·C2 BOARD SC5 (C2A2l
01A·A2 BOARD SC5 (A2A2)
JBA16 ' J11 0041""
U04 ~
-t£0 Hz CONTROL
12 VAC
J13-6
Tl-] ~r-r--J,-1-J-13~'<~~....J
,..,. fl U05
-POJrn
(+Ve)
PC3 SEO CARO
U04~
t z
..,1
J118071'-~
0 >
I- .....
~ ~ J7 8
...,
L:..! :~a~E:I<~G
J11808 ---
~~-!CDOCMMON
S05 ~....
. ~J:A15:: ~Fl - J11 D07 ="'l__f
+ SEQ
CO ~PLETE
PC1 CARD
JBA 12 I'" J12808
Im
S05 le'<
5-PA-8
PA 122 Not Used
PA 123 Attached 8101 Power-On Control
A +5V control level (+5 Ctl) must be available at each 8101 as a prerequisite to power up. This voltage is required by the power control logic in each device and is furnished by the 8101 power supply (see PA440).
Note: When the 8130 with the System Expansion Feature or the 8140 is powered up, only the Power On indicator on the 8130/8140 operator panel is valid during the poweron signal sequence (approximately 73 seconds). All other indicators and hexadecimal displays are INVALID. This is because the 8130/8140 is held in a system-reset state until the 8101 unit power-on sequence is complete, at which time the IPL process begins.
Sequence Control
When the 8130/8140 is powered on, +5V Ctl is generated and 250 ms later -POR1 (+Ve) becomes active. The 8101 power-on signal sequencing starts when -POR1 (+VE) becomes active. The 8130/8140 remains in a system-reset state until the power-onsignal sequence is complete. In the PSCF -POR1 (VE) is sent to PSCF cards 2, 3, and 5 which control power-on signal sequencing. When the operation is complete -POR1 (Ve) is sent to the PSCF1 card which controls initialization reset functions.
The PSCF and SSCF -POR 1 (+VE), together with +5V ctl, control the POR signal.
Primarily, -POR1 (+VE) becomes active 5.2 to 11.6 seconds after the power switch is activated and provides the gating for the 1/0 drivers to ensure a noise-free environment when the drivers are turned on or off. The -POR1 (+VE) in both the PSCF and SSCF is deactivated before +5V Ctl, which generates a POR. This causes the 1/0 drivers to turn off before the loss of +5V Ctl.
8101 powe~·on signal sequencing is controlled by the PSCF using the channel request logic in the SSCFs, the channel request priority (CRP) bus between the PSCF and SSCFs, and the Transmit Control (Xmit Ctrl) line. When an SSCF is powered down, the Transmit Control line enables a comparison between its predetermined CAP value and the contents of the CRP bus. When the contents of the CRP bus are equal to or less than the SSCF's CRP value, the "sequence on" signal is activated.
The sequence in which the units are optioned to power up is determined by their CRP assignment. The unit with the highest CRP assignment is activated first, followed by the remaining units in descending order of CRP assignment. The PSCF controls this sequencing by using the 4-bit power-up sequence counter as the source for the value it places on the CAP bus. The counter is first reset and then set to a value of 8'1111' at the time the 8130/8140 is powered up. The PSCF places the value 8'1111' on the CAP bus and raises the Transmit Control line. At that time, all SSCFs compare their CRP value with the value 8' 1111' on the CRP bus. If an SSCF is assigned the CRP value 8 '1111 ', the unit to which it is attached is powered on. The PSCF waits 4 seconds, decrements the counter by 1, places the new value on the CRP bus, and raises the Transmit Control line. Again all SSCFs compare the CRP bus with their predetermined CRP value, and, if a comparison is made, the unit to which that SSCF is attached is powered up. This sequence continues until the counter value overflows from being decremented past the value 8'0000'. At this time, all attached 8101 units, )Nith their power control switch set to Remote, are powered up and the PSCF returns a Sequence Complete signal to the processor power control logic to show that the 8101 power-on signal sequencing is complete.
+5V Ctl In 8130/40
L
-POR1 (+VE) In 8130/8140
Figure PA123-1 shows the timings for the power-on signal sequence for the attached
8101 units. The 8130/8140 +5VCC signal initiates this sequence
(Refer to PA752-003 Pin)
,,..__.._L
5to11.6seconds
I
(Refer to PA752-A2H6B04 pin)
s..,___""".I.~__I ~~I Power-Off Sequence ----
5
* Power Hold
64 Seconds
Power Sequence Complete (Refer to PA451·D1G-J8-A12)
* System Reset
Power-On Sequence
~1 r
-
-
-
-
-
-
4
5,.._.... _
_
,__., , . . _ 8.5 - 10.5 ms
-~--,l___;s I
CRP Bus
t "I I'1 1 I IF Iel
98
I Al 1
65
1
4
3
1
2
1
1'
0
1_ _ __
4Sec--.I ~
CRP 1
CRP 2
CRP 4
CRPB *SCF signals. Refer to the Chapter 5 SC section for the complete SCF power sequence. Figure PA123-1. 8101 Unit Power-On Signal Sequence Timings
REA 06-88481
SY27-2521-3
(PA121 Cont- PA123t
5-PA-9
PA 124 DC Overvoltage and Undervoltage Sensing The 8100 power logic monitors certain de voltages for overvoltage (OV) and undervoltage (UV) conditions and, if detected, performs a machine power off. Refer to the following text and also to Figure PA124-1 to determine those machine voltages sensed for OV/UV conditions, and also for those de voltages not sensed.
Overvoltage Sensing
The 8100 senses only the -4V de for an overvoltage condition. The PC-2 and PC-50 logic cards generate and sense this voltage; PC-2 supplies the first disk drive and PC-50 supplies the second (if installed). When PC-2 or PC-50 detects a -4V de overvoltage after power is applied to the regulator, the PC card logic turns on a silicon-controlled rectifier (SCR) to remove the overvoltage. This condition opens fuse F14 (F50 on PC-50), which drops the --4V de and powers down the machine.
Undervoltage Sensing
The PC-2, PC-3, and PC-50 cards sense undervoltage conditions as follows:
· PC-2 senses the -4, -12, one +5, +12, and +24 de voltages at the load side of the fuse that corresponds to the voltage. (See Figure PA124-1). When PC-2 (PA462) detects an undervoltage condition for any of these voltages at any time except during a poweron or power-off operation, it:
- Powers down the machine - Turns on the disk storage fault indicator (DS4) - Turns on the Power/Thermal indicator (DS3) - Generates a machine turn-off signal
· PC-3 senses the -5V de voltage at 01A-TB1-8 for an 8130 (PA441 and PA451), at 01A-TB2-3 for an 8140 Model AXX and at 01A-TB2-7 for Model BXX (Figure PA440-3 and PA442 and PA452) and at 01A-TB2-3 for an 8101 (PA443 and PA453). When PC-3 detects a -5V undervoltage condition at any time (PA463) except during a power-on or power-off operation, it drops machine power.
· PC-50 senses the -4V de for the second disk drive (if installed). When this PC card detects a -4V undervoltage condition, it powers down the machine and turns on its disk storage fault indicator (DS50).
DC Voltage
ov
UV
Sensed By
Fused By
-4 **-4
-4 -4 +5 +5 +5 +5 ** +5
** +5 ** +5
* -5
-8.5 +8.5 -12 +12 +24
x x
x x
x x
x x
-
x
-
-
-
-
-
-
-
-
-
-
-
-
-
x
-
-
-
-
-
x
-
x
-
x
PC-2 PC-2
PC-50 PC-50 PC-2
--------
_______ .,.
.................
--------
---------------
PC-3
--------
...................
PC-2 PC-2 PC-2
01G-F14 01M-F14 01N-F50 01G-F50 01G-F3 01G-F4 01G-F5 01G-F6 01R-F1 01R-F2 01R-F3 01G-F8 01G-F7 01G-F2 01G-F1 01G-F10 01G-F9
Comments
1st disk drive 8140 1st disk drive 8140 2nd disk drive 8101 2nd disk drive
Not sensed Not sensed Not sensed Not sensed Not sensed Not sensed
Not sensed Not sensed
*An 8101 Model A 10 (no disk drive) senses only this voltage. **Present only on 8140 Models BXX.
Figure PA124-1. DC Overvoltage/Undervoltage Sensing Summary
SY27-2521-3
REA 06-88481
5-PA-10
Figure PA124-1 shows all 8100 de voltages and if they are sensed for either OV or UV conditions. It also shows the PC card that senses these voltages, which occurs at the load (output) side of the respective fuse. Refer to PA660 for a list of all system voltages, fusing, and test points.
PA130 Power-Unique Repair Strategy
Access to power components and test points normally requires removal of exterior covers over the area being checked.
You should perform all initial 8100 power fault isolation by using the maintenance device and the power (PA) MAPs located on MD diskette 01. · Use MD diskette 01 menu option 4 either for 8130/8140 power problems or if you
cannot determine the failing machine type. · Use MD diskette 01 menu option 5 if you know an 8101 failed but cannot determine
which one.
Always have the maintenance device plugged into the 8130/8140 01H gate convenience outlet unless you have either: · disconnected or plan to disconnect the power cord. · turned off the line voltage circuit breaker (CB 1) on 8140 Models BXX. · otherwise have no 01 H gate convenience outlet power because of a machine problem.
PA211 describes the PA MAP menu options and their meanings used for 8130, 8140, and undetermined power problem isolation; PA212 describes the PA MAP menu options available for an 8101.
When using PA211 or PA212, find the symptom meaning that most closely describes your failure and select the corresponding PA MAP option. If you isolate the problem to a field-replaceable unit (FRU), repair or exchange the FRU; for a problem other than a defective FRU, repair as necessary; if you cannot determine the problem, request aid.
If the Chapter 1 ,General Failure Index (GFI) directed you to the PA MAP, use MD diskette 01 menu option 4 or 5 as explained above. The PA MAP then directs you to either: · Exchange a FRU. · Locate opens by checking circuit continuity. · Locate shorts by unloading particular circuits. · Locate power control failures. · Verify correct power supply operation.
Intermittent failures make all MAPs ineffective. If either an intermittent power problem occurs or the PA MAP cannot isolate the failure, go to PA300.
PA200 OffIine Tests
To perform initial power problem fault isolation, you must obtain the entire system from the customer. As the PA MAPs are standalone programs and do not require system interaction, you do not need to plug the MD signal cable into the 8130/8140 01 H gate socket. You should, however, plug the MD power cable into an 01 H gate convenience outlet if power is available there. (See note after PA211 options). Power on the MD, load MD diskette 01, and use:
· MD diskette 01 menu option 4 either for 8130/8140 power problems or if you cannot determine the failing machine type.
· MD diskette 01 menu option 5 for 8101 power problems.
PA210 PA MAP Menu Options
PA211 PA MAP Options for 8130, 8140, and Undetermined Power Problems
The following lists and briefly describes the PA MAP options, symptoms, and meanings used for MD diskette 01 menu option 4. To use these options, find the symptom meaning that most closely describes your failure, then select the corresponding PA MAP option and symptom as displayed on the MD. If none of the meanings apply or you cannot determine the symptom, select option 09, UNKNOWN PROBLEM.
If you isolate the problem to a field-replaceable unit (FRU), repair or exchange the FRU; for a problem other than a defective FRU, repair as necessary; if you cannot determine the problem, request aid.
PA MAP Menu Option
Symptom
Meaning
01
SOUND; NO LIGHTS
After a power-up, fans and motors
run but no indicators are on.
02
NO POWER-UP
INDICATION
After attempting a power-up, no fans or motors run and all indicators are off.
03
VOLTAGE OUT OF
TOLERANCE
Voltage measurements indicate that one or more voltages are low.
04
1 VOLTAGE MISSING
You have determined that a voltage
AT LOAD POINT
is missing either at the 01A gate, a
disk drive, the diskette drive, or a fan.
05
DISKETTE DRIVE
MOTOR
You know or suspect that a diskette drive motor problem exists.
06
DISK DRIVE MOTOR
You know or suspect that a disk
drive motor problem exists. The disk
storage fault indicator on PC-2 or
PC-50 (if installed) could be on.
07
FAN NOT RUNNING
One or more fans do not run.
08
POWER/THERMAL CHECK The Power/Thermal Check indicator is
on and the system does not power up.
09
UNKNOWN PROBLEM
Use this option to begin PA MAP
fault isolation if you cannot determine
a symptom.
10
OPEN FUSE
You have exchanged a fuse and want to verify the repair. If the fuse again opens, the PA MAP provides fault isolation.
*11
CUSTOMER CB TRIPS
The customer's line voltage CB trips
either when connecting the power
cord or when powering up.
*12
8130/8140 AC OUTLET
No ac voltage at the 8130/8140
convenience outlet(s).
13
EXIT POWER MAP
Returns you to the MD diskette 01 menu.
14
POWER ON DISABLED
The Power On Disabled indicator is on
and the system does not power up.
15
MENU OPTIONS
Displays the PA MAP menu options.
*You cannot plug the MD into the 8130/8140 convenience outlet when selecting this option, as the outlet has no power.
PA212 PA MAP Options for 8101 Power Problems
The following lists and briefly describes the PA MAP options, symptoms, and meanings used for MD diskette 01 menu option 5.
· If the symptom meaning describes your failure, select the corresponding PA MAP option and symptom as displayed on the MD.
· If none of the meanings apply or you cannot determine the symptom, select option OC, POWER PROBLEM.
· For any 8101 symptom not listed, use MD diskette 01 option 4 and go to PA211.
Note: If a MAP step asks you to check a voltage that does not apply or an indicator that is not installed, reply as if the voltage or indicator were installed and good.
If you isolate the problem to a field-replaceable unit (FRU), repair or exchange the FRU;
for a problem other than a defective FRU, repair as necessary; if you cannot determine the problem, request aid.
REA 06-88481
SY27-2521-3
PA MAP Menu Option
QC
Symptom POWER PROBLEM
OD
SCF POWER SIGNALS
Meaning
Isolates a system power problem to a particular 8101.
An 8101 operates with the local/ remote switch set to Local but not when set to Remote.
(PA124 - PA212l_
6-PA-11
PA250 Action Plans
Use the information in this section to aid in fault isolation of solid power failures. For intermittent power problems, refer to PA300.
PA251 Possible Causes of Failure - General
· If all voltages appear momentarily but the 8130/8140/8101 does not power up, the PC-3 card could be defective.
· If the 8130/8140/8101 operates normally with the disk storage sensing logic disabled and fails when connected, the PC-2 sensing circuits could be defective.
PA252 Possible Causes of Failure Using the Status of 8101 Fuses and Indicators
Use the status of the following fuses and indicators to determine possible causes of power failures.
Fuse/Indicator
Status
Possible Cause
F14 or F50
Power/Thermal Check
D54 (on PC-2) and/or
D550 (on PC-50)
Open On
On
-4V undervoltage
F14 or F50
Power/Thermal Check
D54 (on PC-2) and/or
D550 (on PC-50)
Good On
On
· Disk drive interlock switch open
· Undervoltage condition on one or more de voltages (+5, +12, +24, -4, -12)
Power/Thermal Check On
D54 (on PC-2)
Off
D550 (on PC-50)
Off
· -5V undervoltage condition at the gate
· Power-up failed due to an open gate thermal
DS51 (on PC-51 )
On
01 E gate disk brake active
Any de fuse
Open
· Overcurrent condition due to circuit overload (PA650)
· Undervoltage condition
Any ac fuse
Open
· Overcurrent condition
· Wrong tap connected to 01G·T1 or T2 transformer primary (PA410·PA430)
All indicators
On
Open.ground condition
All indicators
Off
· Missing line voltage
· Open ac circuit (PA410-PA430)
· Defective 5SCF (SC5) card
· Remote on signal missing
· Line circuit breaker (C81) tripped (8140 Models 8XX only)
SY27-2521-3
REA 06-88481
5-PA-12
PA253 PC-2/PC-3/01C Disk Drive Power Fault Isolation
If PC-2, PC-3, or the 01C disk drive appears to cause a power on failure, use the following procedure to aid in fault isolation. See also PA450 through PA453 and PA460 through PA462.
Providing the disk storage fault indicator (DS-4) is on, disconnect J16/P16 on PC-2 and also disconnect the power plug (01C-J11/P11) to the 01C disk drive motor.
· If power remains on, either a PC-2 input or the PC-2 card caused the fault indication. Use Figure PA253-1.
· If the machine does not power up, either a PC-3 input or output caused the problem. Use Figure PA253-2 and PA453.
Figure PA253-1 describes the voltages expected at certain PC-2 J16 pins before and after a power up attempt.
J16
Voltage
Pin
Before
Voltage After
Comments
A03
0
A05
0
A06
0
A07
0
812
0
A12
0
A10
0
A01
0
807
0
811
0
A11
+5
806
+5
809
0
808
0
+24* +12* +5* -4* -12* 0 0 +24* +3.5
+5 +5
+5
0
+5
+5V after power up if the disk storage interlock switch or switch path is open. +24V path through the K2 relay indicating that the relay is picked. (PA440) Approximately 3.5V if the -POR signal is coming from PC-3 G10. (PA452, PA461, and PA462) -Sw Off signal. (PA450, PA461, and PA463) This point is also called -POR but comes from PC-3 G07 and indicates +24V ac from the T1 transformer. (PA461, PA463, PA410, and PA440) Disk Storage (File) Fault signal from PC-2 to PC-3. If measured when the fault occurs, the meter deflects lower, then returns to +5V. -Power Good signal to the disk drive logic that allows the K1 relay to pick, which starts the disk drive motor. During power up, this signal is +2V to +3V. +Power Good signal to the 01A gate and the SCF logic.
*If power remains up. Figure PA263-1. PC-2 J16 Input/Output Levels
Figure PA253-2 shows the signal path of certain PC-3 power reset lines used to determine fault isolation when using this action plan.
Line Name PC-3 Pin PC-1 Pin PC-2 Pin 01A Pin Disk Pin
-POR 1
D07
-POR 2
D13
-POR 3
809
-POR*
G05
-POR
G10
-Sw Off
G07
J8A15 J8809 J8810 J1A01 J1A06
J1A03
-
-
J16A 11 J16807, J16809 J16811
J12-3 J16-3 J16-6
-
-
-
01C J1-3
Figure PA253-2. PC-3 Power Reset Line Distribution
PA300 Intermittent Failure Repair Strategy
Use the information in this section to aid in fault isolation of either intermittent power problems or for those failures that the PA MAP could not isolate.
PA310 General Intermittent Failure Repair Strategy
Use the following general procedure to aid in isolating intermittent power failures: 1. Turn off machine power at the operator panel and either disconnect the power cord from the wall outlet on all 8130 and 8140 Models AXX, or turn off the line voltage circuit breaker (CB1) on 8140 Models BXX. 2. Disconnect all P/J connectors one at a time and inspect for cracked housings and loose or bent pins. Reconnect them if not defective, or repair or replace as necessary. See PA760 for connector part numbers. 3. Reseat all pluggable cards in the power supply gate(s) and all 01A logic gate cards. 4. Check all TBs and filter capacitors for loose screws. 5. Check power cables for possible chafing or pinching. 6. Check power cables and connections for opens or shorts. 1. Either connect the power cord to the wall outlet or turn on CB1 (8140 models BXX). DANGER With the power cord connected to the wall outlet, line voltage and the +5 and +24 control voltages are always present in all: · 8130s, 8140 Models AXX, and 8101s. · 8140 Models BXX with the line voltage circuit breaker (CB1) on. 8. Turn on machine power at the operator panel and check relay contactors for proper operation. 9. When powered up, vibrate the machine while visually checking for arcing or smoking.
10. Go to PA610 and perform the AC Ripple Service Check. 11. Check for extra or missing ac (PA405) and de (PA440) grounds.
REA 06-88481
SY27-2521·3
(PA260 - PA310)
5-PA-13
SY27-2521-3
REA 06-88481
This page intentionally left blank.
5-PA-14
PA400 Signal Paths and Detailed Operational Description
DANGER With the power cord connected to the wall outlet, line voltage and the +5 and +24 control voltages are always present in all:
· 8130s, 8140 Models AXX, and 8101s. · 8140 Models BXX with the line voltage circuit breaker (CB1) on.
The following summarizes PA400, the first five sections of which are grouped according to machine type, where:
x = 1 = 8130
x =2 =8140 x = 3 = 8101
· PA41 X contains the 60-Hz ac power logic for machines used in the United States and Canada.
· PA42X contains the 60-Hz ac power logic for machines used in countries other than the United States and Canada.
· PA43X contains the 50-Hz ac power logic. · PA44X contains the de power logic. · PA45X contains the power control (PC) card external logic connections. · PA460 contains PC card diagrams and internal logic connections sectionalized by PC
card type.
REA 06-88481
SY27-2521-3
(PA400)
5-PA-15
PA405 Safety Grounds 8130/8140 Models AXX Safety Grounds
3*
r--- --,
1·
I
G9
~G6
I
I
5*
- - \.._ -
_.)
14*
G11
BLK
Jumper
3·
l -°"' GN/YEL
__ G13 0
-
r-
'--
:-
l
-
./
4*
4·
3*
G14
2·
GN/YEL
! GN/YEL
GN/YEL
Jumper Jumper Jumper
· = Wire number in bundle
SV27-2621-3
REA 06-88481
5-PA-16
Rear Outlet Front Outlet
01U-J1-G PA412,PA422,PA432
01 H-J1-G PA412,PA422,PA432
Disk Fan 1 01 C Disk Drive 1 01 C (EMC) AC Filter
Fan Motor Case PA412,PA422,PA432
01C-J1-2 PA412,PA422,PA432
01G-TB4-3 PA412,PA422,PA432
Power Attachment Cord Service Ground PA412,PA422,PA432
OlG Power Gate to Frame
Gate Fans 1 and 2 01 A
01 A-J1 -2 PA412,PA422,PA432
Diskette Drive 01 D
01 D-J3-5 PA412,PA422,PA432
Front Cover Fan
01C-J2-2 PA412,PA422,PA432
Diskette Drive 01 D Disk 1 Fan 01 C Disk Drive 1 01 C
01 D Motor Case PA412,PA422,PA432
01 C Motor Case PA412,PA422,PA432
01 C Motor Case PA412,PA422,PA432
G1-G4 G5
G6-G9
0
Power Gate From Rear of Cabinet
D
G11 ---1.....;_';,___,
Power Gate Frame Ground (In Rear of Cabinet)
Cabinet
Diskette Frame Ground
Disk 1 Frame Ground
G12-G15 Along Side of Ferro-T2
8140 Mode's BXX Safety Grounds
01 L-E1
Convenience Outlet 01U
Building Ground
Line Cord
G10
Line
-I
Filter
- i Capacitors
01G-TB4-3
G1 G2
0 0
0 0
G3 G4
G9
01 L-TB1-8 01 L-T81-7
01 L-J7-2 ) UFrna;mt e :
r-----
t I ) 01C-J1-2 ) I
I
I :.01~E~ __ 0182~1-2)
<25} Disk 1
0
01C
e 01C Fan
01 L-J3-2 01 L-J4-2
. - - - - - - 0 01 B1/P1-2 )
010
- - Fan
01 E-E1 01 E-J1-2 )
~
Disk 2 01E
e 01 E-J6-2 )
L ----- ----
01 L-J2-2 )
) 01 D-P1-5 )
~
Diskette 01D
01 L-J1-2
01A-J1-2 ) 01A-J2-2 ) 01A-J3-2 )
0
e Logic Gate
0
Fans 01A
G9 G10 0
0 G11
0
G1 G2 G3 G4
G11
- Unit Frame
01L-J5-2
Op Panel 01F Disk 2 01E Disk 1 01C Diskette 01 D
01A-J4-2 ) 01 l-J6-2 (
0
01G Gate
0
(Power Wall) Fan (0183) (B3-J1)
Ferro 01R Ground
Signal Shields
01G-TB1-3
DC Return PA442
REA 06-88481
SY27-2521-3
(PA405)
5-PA-17
8101 Models A1X, A20, and A23 Safety Grounds
r-----'"'
7·
G9
' I
I I
I
t--lG6
I
I
5·
'------J
14*
r GN/YEL
G100
~ - -l- - ..
' - - - __ ..I
SY27·2521·3
REA 06-88481
Disk Fan 1 01C Disk Drive 1 01C (EMC) AC Filter
Fan Motor Case PA413,PA423,PA433
01C-J1-2 PA413,PA423,PA433
01G-TB4-3 PA413,PA423,PA433
Power Attachment Cord Service Ground PA413,PA423,PA433
BLK
J~mper
01 G Power Gate to Frame
G11o-------------------......:~------------------------------------------------~
! -l- -, 3·
G130----G-N--/Y--E-L------,-----_!"---_---_-..I...;.._______4_* ___________________G_a_t_e _F_an_s_1_a_n_d_2__0_1_A__ 0P1AA4-1J13-,2PA423,PA433
4·
r-
-,
3·
' - - __ ..I
G14 2·
Diskette Drive 01 D
01 D-J3-5 PA413,PA423,PA433
Front Cover Fan
01C-J2-2 PA413,PA423,PA433
GN/YEL GN/YEL
Jumper Jumper Jumper
· == Wire number in bundle
Diskette Drive 01 D Disk 1 Fan 01 C Disk Drive 1 01 C
01 D Motor Case PA413,PA423,PA433
01 C Motor Case PA413,PA423,PA433
01 C Motor Case PA413,PA423,PA433
Power Gate Frame Ground (In Rear of Cabinet)
G1-G4 G5
G6-G9
0
Power Gate From Rear of Cabinet
0
5-PA-18
Diskette Frame Ground
G12-G15 Along Side of Ferro-T2
Disk 1 Frame Ground
8101 Model A25 Safety Grounds
BLK
GBO>------------------~
____ ,"
j
___
,
..,/
6"
r-----, 1·
I
G9
~G6
____ I
5"
\...
)
14"
Disk Drive 2 and Fan Motor Case
Disk Fan 1 01C Disk Drive 1 01 C
(EMC) AC Filter
01 E-P2-6 PA413,PA423,PA433
Fan Motor Case 01C PA413,PA423,PA433
01C-J1-2 PA413,PA423,PA433
01G-TB4-3 PA413, PA423, PA433
r ,.- - =1-- -""\ G100~----.;:.;.;::.:G..N:./.Y.:E.:L......__~\...---.-------.,,/~----------------------P-o-w-e-r-A-t-ta-c-h-m-e-n-t-C-o-r-d-~
Service Ground PA413,PA423,PA433
BLK G11
Jumper
3"
G130
L GN/YEL
,.- ......... -,
'----"'
4"
GN/YEL
2"
G14
01 G Power Gate to Frame
-
Gate Fans 1 and 2 01 A
01A-J1-2 PA413, PA423, PA433
Front Cover Fan
01C-J2-2 PA413,PA423,PA433
GN/YEL
Jumper
Disk 1 Fan 01C
01 C Motor Case
PA413, PA423, PA433
-I-~..,;;G;;.;N..:/_Y_EL____J_um...;p_._, __________________D_is_k D_ri_ve_1 _0_1C____ P01AC41M3o,PtoAr4C2a3se,PA433
!~G~N~/YE~L------------------------D-is-k 2-F-an--01 -E ----0-1 -E M~o1tor~CMase~M~
.-_~G_N_1v_E__ L _ _J_u_mpe__ r _ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_is_k_D_r_ive_2__01_e_ _ _ 01 E Motor Case PA413,PA423,PA433
"=Wire number in bundle
Ground (In Rear of Cabinet)
REA 06-88481
SY27-2521-3
G1-G4 G5
G6-G9
Power Gate From Rear of Cabinet
0
G11---r·i
Ill
Front of Cabinet
Diskette Frame Ground
Disk 2 Frame Ground Disk 1 Frame Ground
G12-G15 Along Side of Ferro-T2
(PA405 Cont)
5-PA-19
PA410 60-Hz AC Power (U.S. and Canada) PA411 8130 60-Hz AC Power (U.S. and Canada)
Diskette Motor
___ 010 ..... PJr -iJ3 I 4f
I 51
120V 60Hz Single Phase
r Blk
I I
I I Grn/Yel
I I I I Wht
-
G10
Conv Outlet B
A F11 B
fl
SY27-2521-3
REA 06-88481
5-PA-20
Front Cover Fan
r - - 010-TB2
--,
p
2
r
01C
r--1
J
2
I r -2 e>--+-< - - - - - - - - - - - -
II I
I I I I
1L
I
1 e>-<...,_+-< _ ....,~ _.,.__ _ _ _ __
L---~
II
1111
I
4
220V
!!!! T2
120V
1 I
Com
L J ::f] II
01C Disk Motor
G9 09
r-51 01G-TB2
4 I
3
21
I 1I L _ _J
230/240V T1 6
200/208/220V
,. 7
120/127V
,. 8
100/110/115V ,. 9
Com
,. 10
":"
.- -,
I
01c- I 2 L
...J 1 I
TB2 L _ _- _- _ _J
01 C Logic Fan
I I +0.2V Ref
PA451 JS-4
+24V Ref I I P13-4
+24V Control
P13-10
I I +0.2V Ref
P13-2 } PA-
+24V Ref I I P13-5
18V AC Ref II P13-1
I I 10V AC Ref
P13-6
DC Common
P13-8
10V AC Ref 18V AC Ref
II II
P13-9
P13-7
PA440
Notes:
I I Typical value with system operating properly; for reference
only. Voltage measured with respect to DC common.
f l O:mnect this lead to T1 input tap corresponding to AC input
voltage.
I J Connect this lead to T2 input tap corresponding to AC input
voltage.
Ia DANGER High-voltage resonant circuit. Do not measure across C12
with power on.
I I Leads in P3 and J3 are connected to pins 4, 5, and 6 for
II· 100 to 127 volts and to pins 1, 5, and 3 for 200 to 240 volts.
See also Note
PA412 8140 60-Hz AC Power (U.S. and Canada)
8140 Models AXX 60-Hz AC Power (U.S. and Canada)
Front Convenience Outlet
01H-J21
I
B I I
__ J
Diskette Motor
( 1)
r
I
- - - - - :iG14
I -=-
Frame
G14
II
T2 230V
P3Lf6f_J 01A
JJ r: 3 2
01A Gate Fan #2
Fan #1 Blk
G10
A F11 B
11G13
I -=-
01A
G13
09
r - s i 01G-TB2
4
3
21 J 1I L _ _J
L j
01C Disk Motor
G9
Frame
II
+0.2V Ref
+24V Ref
+24V Control +0.2V Ref +24V Ref
01 C Logic Fan
·II
II
01C Disk PA451 J5-4
p~ P13-4
Pl 3-10
P13-2 }
II P13-5
18V AC Ref II
P13-1
lOV AC Ref II
P13-6
DC Common
P13-8
10V AC Ref
IIII 18V AC Ref
P13-9
P13-7
PA440
Notes:
I I Typical value with system operating properly; for reference
only. Voltage measured with respect to DC common.
f l Connect this lead to T1 input tap corresponding to AC input
voltage.
I J Connect this lead to T2 input tap corresponding to AC input
voltage.
11 DANGER
High-voltage resonant circuit. Do not measure across C12
1 with power on. I I Leads in P3 and J3 are connected to pins 4, 5, and 6 for 100 to IJ. 127 volts and to pins 1, 5, and 3 for 200 to 240 volts. See also Note I I All units built after EC 862592 have disk and dislct1tte doub/egrounded.
REA 06-88481
SY27-2521-3
(PA410 - PA412)
5-PA-21
8140 Models BXX 60-Hz AC Power (U.S. and Canada)
SY27-2521·3
REA 06-88481
5-PA-22
208V, 240V 60Hz Single-Phase
01G-
01R-
C81
20A
....------~~----~~--0~0------'~--~~l-----CI I 1A I 18 I Lin~ 1 Voltage
I Circuit
I I Breaker
I I ,11,
-1' -
0---~~+--~;µ...-----0
28
I I
: 01 L-Tl -TB2 I
115
VAC
;
~
iii
v;
01 H (Conv Outlet·
Notes:
D Connect this lead to input tap
corresponding to ac input voltage.
I I See PA440 for 01R-T1and01G-T2
secondaries.
II For additional wiring to K50,
see Figure PA442-2.
6
8
To 01G-J13
9
7
i01 G-,-T83 1 I
01L-T81
r,-,
r 01-L J-/P ,
I
I
01 E-J6-1
----,--1.-------o...ti_.,_____-< 5-1~-.........--------------------------------.
>------- I 2 I
~---...J1"--lillfl>~1-----~~------)~ 7-1
01C-Jl1-1
I I
3-1
IJ
0181-Jl-1
01C-T81-1
0182-Jl -1
---4-1
I
I 14
01 E-J11-1
01A-J1-1 01 A-J2-1
01 E-T82-1
F12
01 A-J3-1
01A-J4-1
2-1 )>------< 01D-J1-1
5
< .__...,__,__--.----i
7-4 6-1
>>-----------0-1-B3---J1--1--~---------4-9--- ----------+----+---------------------------.
u- 01 G-TB5-8 r - 24ov- - - ..,
24ov - - OIBl
'----t--;---------------0-1-::G:--T=-:8:-5:--6:-..!0~'u~2~0.:::_8V.::..(
I I 01A-T83-4 01 G I I 01R-T83-2
Tl ~I
6-3
-T2 I 1
208V
II I I 01R-TB3-1
_ j L _ _a_ ___ J _________...;::__::......;::.....~111-----1I--1
C4
0 I
I
I
0G1aGte Fan
01C 010 Logic Gate
01A 01A 01A 01A 01E 01E 01C Front 01C Logic Logic Logic Logic Logic Mot- Gate Cover Mot-
01E Gate
0183-Jl-3 ~---___;;_.;....;;....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Fan Motor Gate Gate Gate Gate Fan or Fan Fan or Fan
Fan Fan Fan Fan
01 A-J4-3
01A-J3-3
01A-J2-3
01 A-Jl-3
2-3)>-------c( 01 D-Jl -3
01 E-J6-3
>-------- __..._____ 7-3
>--------c '--------~ 3-3
01C-Jl1-3 0181-Jl-3
01C-TB1-2
0182-Jl-3
K50
OlE-TBl-2
4-3
-~ 01E-J11-3 ~....._------------------------------+--
6
4
01 E-TB2-2
L - _.......J
PA413 8101 60-Hz AC Power (U.S. and Canada) 8101 Models A1X, A20, and A23 60-Hz AC Power (U.S. and Canada)
Diskette Motor
I
1t--u-~~~~~--~:-:LG14 I -=
G14
!!!! T2 230V
01A
r: J3 3
2
P3f6f~
01A Gate Fan #2
r:01A
P1 11Jll"
11 I I I
------~2,,
G13
I
I
I
-=
G13
I
I
I
l
F12 B
G9
D9
A
F 11 B
01G-TB2
r-si
230/240V T1 6
4 I
200/208/220V
'" 7
3
120/127V
'" 8
100/110/115V .. 9
Com
.. 10
-
120V
I
I
1 I
Com
L J ;f]
01C Disk Motor
r-.,
01c- I 2 L _ _ -.J 1 II
G9
TB2 L ____ _J
Frame
II
+0.2V Ref
+24V Ref
+24V Control +0.2V Ref +24V Ref
01 C Logic Fan
D D
01C Disk P13-4
PA453 J5-4
D D
} P13-10
P13-2
PA440
P13-5
18V AC Ref 10V AC Ref DC Common 10V AC Ref 18V AC Ref
D. P13-1
·~ P13-6
, P13-8
DD-.' - P13 9
~ P13-7
PA440
Notes:
D TYpical value with system operatingproperly; for reference
only. Voltage measured with respect to DC common.
I I Connect this lead to T1 input tap corresponding to AC input
voltage.
I J Connect this lead to T2 input tap corresponding to AC input
Ia 110/tagB. DANGER
High-voltage resonant circuit. Do not measure across C12
with power on.
I I Leads in P3 and J3 are connected to pins 4, 5, and 6 for 100 I J to 127 llO/ts and to pins 1, 5. and 3 for 200 to 240 110lts..
See also Note
I J All units built after EC 862592 have disk and diskette doub/e-
grounded.
REA 06-88481
SY27-2521-3
(PA412 Cont- PA413)
5-PA-23
8101 Model A25 60-Hz AC Power (U.S. and Canada)
SY27-2521-3
REA 06-88481
5-PA-24
r0-1-E--T-B1-,
1 1 O-+-~--;...;..;+-~)-+;..;..;.+-~~~~----------~~,....~n-;"---'>-~------.r-t----......... Frame I r-
1 I
01E Disk I t
I
Motor I I
:
I :_ -
Frame
1 I
I 20..+-------t..,..,")-o!----+-.;-------....
L--- _J
p1 E Logic Fan
01rE--T-B22 -,
I r- _J
I I I
I LL--~
01A Gate Fan #2
010 G13
Blk
120V
60 Hz {
Grn/Yel
Single - - - - - -
Phase
G10
4·I
I
I
1 I
I
I
I
I
2 I
I 21
61
L ...J
01G-
TB3
T2
G14
r - , 01G-TB5
I
230V
UI
N g> Ie-;·~-
11: 41 120V
-o ~
<{
>.s.g.:_
I
a.. c
8 Cl)
1 : Com
~~
L _ I .~=
II
-
01C Disk Motor
G9
A F11
B
09
Frame -
01C TB2
01 C Logic Fan
+o.2V Ref +24V Ref +24V Control +0.2V Ref +24V Ref
01 C Disk J5-4 PA453
P13-4 } P13-10
PA440 P13-2 P13-5
-Pick K50
0--+----2-00~2/23-0-0/~28/4"0!"V'2_2_ _0_V-------.
T1 ~6--------------------------------------------~1~8V~A~C~R~e~f~
ij7
1OV AC Ref
120/127V
8
DC Common
100/110/115V Com
-=-9=10------------------------------~-----------------:,~a~v~A":1"0"V::AC~CR~Ree~ff-
01 E-J54-1 PA453
P13-1 }
:~~~ PA440
P13-9 P13-7
Notes:
I I Typical value with system operating properly; for refenmce
only. Voltage measured with respect to DC common.
f l Connect this lead to T1 input tsp corresponding to AC·
input voltage.
I I Connect this lead to T2 input tsp corresponding to AC
input voltage.
II DANGER
I
High-voltage resonant circuit. Do not measure across C12 with power on.
I I All units built after EC 862592 hal!O disk and diskette double-
grounded.
PA420 60-Hz AC Power (Other than U.S. and Canada) PA421 8130 60-Hz AC Power (Other Than U.S. and Canada)
Diskette Motor
100, 110, 115, 120, 127, 200, 208, 220, 230, 240V 60-Hz Single Phase
Blk Grn/yel Wht
0r1-G.-.T.B,4 1 I
Front
Cover
Fan
-T2
230/240V
r-51 01G-TB2
41
3
21
L _ _J
2 I .......i-------t-~ ........__ _ _ _ _ _ ___,r~-u
3 I
L -, I
----~~~I ~,~~~~--1
II II
01C Disk Motor
1 I
J I
J11L _ P11
L_1_ j
r -, 01C-TB1
09
.- -,
I 01 c- I 2 L _ _ ...J 1 I TB2 L ____ _J
01C Logic Fan
230/240V T1 6
200/208/220V
7
120/127V
8
100/110/115V
9
Com
10
+0.2'-' Ref +24V Ref
·II
P5-4 PA451 P13-4
+24V Control
+0.2V Ref II +24V Ref II
} P13-10
P13-2
PA440
P13-5
18V AC Ref I I P13-1
10V AC Ref I I P13-6
DC Common
P13-8
B 10V AC Ref
18V AC Ref II
P13-9 P13-7
PA440
-
REA 06-88481
SY27-2521-3
Notes:
U T}'pical value with system operating propsrly; for r11ft1rence
only. Voltage measured with f'llSpect to DC common.
E1-<»~n11ct this lead to T1 input tap corresponding to AC input
voltagtJ.
I J Connect this lead to T2 input tap corresponding to AC input
voltage for 100V and 110V. For all other input voltages,
connect this lead to TB5-5.
Ia DANGER High-voltage resonant circuit. Do not measure across C12
with power on.
I I Low-voltage convenience outlet l'flCtlptacle to bB connt1ered
for 100V and 110V inputs. High-voltage conveniflnce outlet
receptacle to bB connt1eted for 200V to 240V inpur.. Low-
voltage shown. High-voltll{/IJ outlet connections same as low
voltage.
I I Leach in P3 and J3 are connected to pins 4, 5, and 6 for 100 I J to 127 volr. and to pins 1, 5, and 3 for 200 to 240 volr..
See also Note
(PA413 Cont - PA421)
5-PA-25
PA422 8140 60-Hz AC Power (Other Than U.S. and Canada)
,-8140 Models AXX 60-Hz AC Power (Other Than U.S. and Canada) Front Convenience Outlet -o~H-1 J2
I
I' B
IL __
I
I
__ J
Diskette Motor
01A Gate Fan #2
01A
J3r:
2
P3~f6j£--J~
01A
Gate
Fan #1
I
100, 110,
Bik.
115, 120,
I
127, 200, 208. 220, 230, 240V 60 Hz
{
I Grn/Yel
I
I
l
Single
Phase
G10 G9
A F 11
,-5101G-TB2
B
41
3
21
I 1I L _ _J
SY27-2521-3
REA 06-88481
:iG14
G14
A
r
I
G9 GS
09
-= ":"
230/240V T1 6
200/208/220V
,. 7
120/127V
,. 8
100/110/115V ,. 9
Com
,. 10
-
3 2
P11
T2
230/240V
220V
200/208V
.,;
Cl
127V 115/120V
:c N C:
I.... c: ..0... ~ ·-
110V
~0 :;;>
100V Com
<{ "C
a.. c:
0 Q) CJ
~~
L
~ -
G9
Frame
II
+0.2V Ref +24V Ref +24V Control +0.2V Ref +24V Ref
18V AC Ref lOV AC Ref DC Common lOVACRef 18V AC Ref
01 C Logic Fan
a a a a
01C Disk PA451 J5-4
PA4~ P13-4
Pl 3-10 P13-2 }
P13-5
a P13-1
D P13-6
P13-8
D P13-9 II
P13-7
PA440
5-PA-26
Notes:
I I Typical value with system operating properly; for referenCB
only. Voltage measured with respect to DC common.
I I Connect this lead to TT input tap corresponding to AC input
voltage.
I I Connect this lead to T2 input tap corresponding to AC input
voltage.
11 DANGER
1
High-voltage resonant circuit. Do not measure across C12 with power on.
I I Low-voltage convenience outlet receptacle to be connected for
100V to 127V inputs. High-voltage convenience outlet
receptacle to be connected for 200V to 240V inputs. Low·
voltage shown. High-voltage outlet connections same as low
voltage.
I I Connect this lead to T2 input tap corresponding to AC input
voltage for 100, 110, 115, and 120V. For 127V input, con-
nect this lead to TB5-3. For 200, 208, 220, 230, and 240V
inputs, connect this lead to TB5-7.
IJI Leads in P3 and J3 are connected to pins 4, 5, and 6 for 100
I J I I . to 127 volts and to pins 1, 5, and 3 for 200 to 240 volts. See
also Notes and
liJ All units built after EC 862592 haVf1 disk and diskette double·
grounded.
8140 Models BXX 60-Hz AC Power (Other Than U.S. and Canada)
200/208V, 220V,240V 60-Hz Single-Phase
D
2oav
01L- 01R-
TB1 CB1
'f rn"" 20A
I ~0-----'~---4-H~----O
I 1A I 18 I Li~e 1 Voltage
I Circuit
I I Breaker
I I 1111
~ o----4....;..c~,....-~~.L..,_---Q
28
6
8
To 01G-J13
9
7
01G-TB3 01 L-TB1
01 L LIP
01E-J6-1
1 1 r Ir - - ,I I 1 I 11 ____ .__"""'11'J>-:----~_.._---.._
~
5-1~---f-------~~~~---------------------.
I I
I 2 I
----4.I-f-e-l --~.c&-11---~> 7-1 >--_ _ _ _.., 01C-J11-1
I I
3-1
01B1-J1-1
II
0182-J1-1
01C-TB1-1
01 E-J11-1
01 E-TB2-1
01 A-J1-1
01A-J2-1
F12
01A-J3-1
01A-J4-1
01 H (Conv Outlet),
Notes:
II Connect this lead to input tap
corresponding to ac input voltage.
fl See PA440 for 01R·T1and01G·T2
secondaries.
I I For additional wiring to K50,
see Figure PA442-2.
01G-TB5-8 01G-TB5-7 01G-TB5-6
6-3>-i
y
01B3-J1·3
1 - 3 8 01A-J4-3 01A-J3-3
01A-J2-3
01A-J1-3
2-3)------<( 01 D-J1 -3
01 E-J6-3
>---------4. ~'-----4~~7-3 ~----.... ....._____,. 3-3
01C-TB1-2
REA 06-88481
SY27-2521-3
II II
I
01G Gate Fan
01C 01D 01A Logic Gate Logic Fan Motor Gate
Fan
01A logic Gate Fan
01A Logic Gate Fan
01A Logic Gate Fan
01E 01E Logic MotFan or
01C Gate Fan
Front Cover Fan
01C Mot· or
01E Gate Fan
(PA422)
5-PA-27
PA423 810160-Hz AC Power (Other Than U.S. and Canada)
8101 Models A1X, A20, and A23 60-Hz AC Power (Other Than U.S. and Canada)
!itw3i-~ ~;w 01A
"'.;1
G13
'- -
- -~
01A 01~TB4
01 A Gate Fan #2
ri Gate
Fan #1
J n-Il...:-------------
Blk
100, 110, , , 5, { 120, 127,200,
208, 220,230. 240V60 Hz
Single Phase
-----_..._,__ _ _ _ _ _.__~+----o--+----'
G10 G9
A F 11 B
SY27-2521-3
REA 06-88481
Diskette Motor
------.-... P3r- 4 J3 I !1 l I I
)5j
I sI
f"::"G14
Frame
G14
01G-TB3
II
!!! T2
230/240V 220V
200/208V 127V
115/120V 110V 100V Com
01C Disk Motor
P11
G9 09
I-,
I
01c- I 2 L
_J 1 I
G9
TB2 L--- - - -~
Frame
01 C Logic Fan
II
PA4~ L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-+-0.-2-V-R-e-f +24V Ref
:
=DD-
t
01 C
Disk
PA453 J54
P13-4
+24V Control
+0.2V Ref +24V Ref
II D
P13-10 P13-2 }
P13-5
P13-6
PA440
5-PA-28
Notes:
I I Typical value with system operating properly; for reference
only. Vo/'tage measured with respect to DC common.
f l Connect this lead to T1 input tap correspqndlng to AC
input voltage.
I J Connect this lead to T2 input tap corresponding to AC
Ia input voltage. DANGER High·voltage resonant circuit. Do not measure across C12 with power on. I I Connect this lead to T2 input taP corresponding to AC input voltage for 100, 110, 775, and 120V. For 127V, connect this lead to TB5-3. For 200, 208, 220, 230 and 240V, connect this lead to TB5-7. D Leads in P3 and J3 are connected to pins 4, 5, and 6 for 100 I J g . to 127 volts and to pins 1, 5, and 3 for 200 to 240 volts. See also Notes and I I All units built after EC 862592 have disk and diskette doub/egrounded.
8101 Model A25 60-Hz AC Power (Other Than U.S. and Canada)
~~~~;··l ~ ~ <+ I. r0-1-E--T-B1-,
01E
P11r---1J11
,I .!.._
!£' 4t
I I I I I I
I I L..
-
Frame
I I
I
I I
I I
:_J I
L
_
_2_
_.._
... ~"-I
.__I
l.~--:.3J
T_T
r-_:K--50-5-1
--;r--- 1 01 E Logic Fan
~ ~ 01 E·TB2
Front Cover
: I ~ 3 TA~
_ _ _ _ _ _.,_...._-.c-c.-~~·"A- ~
I
·T
Frame - - - .,
Fan
I I
r-~; 4
---j-_J :: !:o.;. ~- FramLe_-<~>_JI 2
-
--"'o1-...l.I ~---1i~.f..1,
.c-.--i_--=
I I I
L
L
1
C)
-
1 J
Frame
- - _:. .:- - >
L _. - -
,·1~ -_ -_
- - ..J J2
-_
_ -
,
i.'
-- .·.·-- -v
=i-l CR50
.....................-----------~
-~--------
G14 O~G..:,T~5
I 010 P2ft~.~. ----------,~-- --~V;
,..81
T2 230/240V
=
h------.-:-_"T____ 1-. 1 '"' 1 --I-6i---_ c 1: ~!~~:.'t3:_~::_2~n ~---_-_=_=~ -------~--~l-~"~~s31~1i~·=i~'------~~+-A--~-B----:3-~ +--~+~~----~'~ 01A Gate
Fan #2
-
-
t
.rI-'.~.-..,.,
.
.
_
-
-
-
-
--~-::-I:.-g....,.-.:...~:~-~._,,_-_._
_ ....._.-..-...,...__
I I
T_T
r
- -+ - ~ 01A
01A
I J .~ A.2 1I'
J2 P2
:!. -: IJ PJ
r
.,I..
-:'11_Li-~ // 1' I
I I G13
TI "'"-I)',21I1I
I
i
":"
II
01A G13
J2 L-+ !. r-2~_5- - - - - - - -
~ 3-1 -
r6~7
,·....,.
220V 200/208V
,-.+.~-. -r-~.-.. ---y-
~~1·1 G9 ----~1--.... -l
I .-....,.5·':L.t 127V
.:ti
I I
~v 4_._
115/120V
*GB
.-----4~1----t------......;.'~-),;·3_..1_ _11_0V_ __,_
1 T "21 100V
l
( L _ I 71
Com
-
1--'
14
N I.-..
:.ga>
c:
0 ·-
-~o >3:a:
<( -0
a. c:
8 GI
~~
01A
~
Fan#1
r-1 01
1
1G0·T-B~T4-----------+---~:"""""C'.r.0;.1.G-_·K~v2--~ -y---~---:::::::~;:::===~~ ·~ ~-5~I11 -~~------~a
c12fj
-
I
I
100, 110,
115, 120, 127,200, 208, 220,
{-TLI~I:.,_._lI_--GB-rlkn-/Y-e-l------,~~._.I!_ ,_,..._.23 ,JII --:~-~~ .F~-LT1
230, 240V
60 Hz Single Phase
I~I I : Wht ':"
~C~)
G10
1 "' ! > I
C) Tl
I
~ 4
~
-~ ..J_
__J
~~ I
G9 I
51 !
~
l..- .J
1 ~ I
I
~
T ""/, 1
I "'"V I
I
I
I c- T
I
I
I
I "!.0 I Aux :
I " -v _l 0 _t
I I NC
I Com 1
I 1
I
I ('
2 J
L- ---~ ..J
~ 01G·K1
r 1----, I >-y. _3 I
----1-~l_o~Lr-;-.- +----+----------------------
TII-._....A..4.1.I.....,,...------+-----'!-',~~,---::~TJ~131~'r.-0.:.1,_C;.1,.,P..;.1..1.:..:--..~... -0-1-C2--TB-1,I
l -- ! : : ~ i~ j
' 6 _.
4 I
:
"' :
I ~2 I
I -. I -_. 1 I I I
I I
I
I
L -1 1
T ,.
I I
1 2,// :
T '"' 1
-\(
I
1
1 1
:
1 I
1 I
01C Disk Motor
c::J I 1
2:
--1---1-' -'--
::T L
j_
6I L+ - ___ J
.....IL. ~~-6..1J ----'
I
..I ;·~---·..LI._~1~,<.,..,.,J_1.t--+--+-Lr-0.-.....
_.J
1 -- _
.
I
I J
~
01G· TB3
f G9) GS ~ "="
G9i
09
r-1 llFrame -=
f;_, "='
01C TI ""2' I
I -1- I
T82 L__'- _- _- _- _- _.J _ .JI
( A
f11 c ~B
01C Logic Fan
+o.2V Ref 11 01C Disk J5-4
+24V Ref
PA453
+24V Control +o.2V Ref +24V Ref
PP1133-410 } P13-2 P13-5
PA440
----------1t--~i~~~~>--l~t-----~-O-~-:-~-~_:_:_:: ~~~ ll:J._~1-90 ~-~-~_:_m_:m_:_:"_:_ rs-, 01G·TB2
-Pick K50
1 _ s,,.._o-~~----2_3_0_12_4_o_v _______,T1 _s________________________________1_a_v_A_c_R_e_f_
_____
__________________________________
I~ 1
,
18V AC Ref
DI...,......-'.~ l_ ~ I I._:i _"".T.J
Com
010-J54-1 PA453
P13-1 }
:~:: PA440
P13-9 P13-7
REA 06-88481
SY27-2521·3
Notes:
I I Connect this lead to TT input tap corresponding to AC
input voltage.
I I Connect this lead to T2 input tap corresponding to AC
input voltage.
I J Typical value with system operating properly; for reference
only. Voltage measured with respect to DC common.
Il l DANGER High-voltage resonant circuit. Do not measure across C12
with power on.
I I All units built after EC 862592 have disk and diskette double·
grounded.
(PA423)
5.PA-29
PA430 50-Hz AC Power PA431 8130 50-Hz AC Power
100, 110, 200.220. 230,240V
50Hz
Single Phase
,.. Brn
: I
I I Grn/Yel
I I I I Blu
G10
A F 11 B
SY27-2521-3
REA 06-88481
5-PA-30
Diskette Motor
__ 010 r --, ...p..3;.1..:;.,_ 4 IJ3
I 51
Front Cover Fan
I
I
I L
01G-TB2
r-si
41 3 21
I 1I L _ _J
=
::!! T2
-
IJ
3 I
~I
2 I
I
J11L_ P11
G9
09
-=
240V
230V 220V
200V
110V
100V
Com
~ L J
-
II
.,;
Cl
NC
I.-.. :c0
0 ·-
-0~ 3.>.:.
a~ <..
m
1cJ
0
CD CJ
~~
-=
r-21
L -, I
I I
I I
J I
L _1_ j
r--, 01C-TB1
i--
OlC Disk Motor
230/240V T1 6
200/208/220V
> 7
120/127V
> 8
100/110/115V
~ 9
Com
~ 10
-=
-=
01 C Logic Fan
a +0.2V Ref a +24V Ref
+24V Control
D +0.2V Ref D +24V Ref
D 18V AC Ref
D 10V AC Ref
DC Common
D 10V AC Ref
a 18V AC Ref
PA451 P5-4
P13-4
} P13-10
P13-2
PA440
P13-5
Pl 3-1 P13-6 P13-8 P13-9 P13-7
PA440
Notes:
I I Typical value with system operating properly; for reference
only. Voltage measured with respect to DC common.
f l Connect this lead to T1 input tap corresponding to AC
input voltage.
I I Connect this lead to T2 input tap corresponding to AC
I a .
input voltage.
DANGER High-voltage resonant circuit. Do not measure across C12 with power on.
I I Low-voltage convenience outlet receptacle to be connected
for 100V-127V inputs. High-voltage convenience outlet
receptacle to be connected for 200V to 240V inputs. Low-
voltage shown. High-voltage outlet connections same as low
voltage.
Connect this lead to T2 input tap corresponding to AC input voltage 100/110/115/120V. For 127V input, connect this
lead to TB5·3. For all other input voltages (200/208/220/ 230/240V) connect this lead to T85-7.
I J Leads in P3 and J3 are connected to pins 4, 5, and 6 for 100
to 126 11olts and to pins 1. 5. and 3 for 200 to 240 volts.
I I I.I- See also Notes and
PA432 8140 50-Hz AC Power
8140 Models AXX 50-Hz AC Power
,B
A
I' B
I
L __ _j
r: 01A
J3 3 2
P3w~
01A Gate Fan #2
Gate Fan #1
Bk-Japan Bn·All Others
100. 110, 200, { 220, 230, 240V
50 Hz Single Phase
_ __.I.._G_rn/_Y_e_I I
A F11 B
Front Convenience Outlet
-01!il J2
Diskette Motor
B
fJ
iG14 G14
!!!! T2 240V
I G13
' i I1 I ":"
G13
01G·TB3
II
L
I
I
I L
01G-TB2
r-si
4 I
fJ
3
21
I 1I
L _ _J
II 2
01C Disk Motor
G9 09
230/240V T1 6
200/208/220V
7
120/127V
8
100/110/115V
9
Com
10
-
REA 06-88481
SV27-2521-3
.. ..,
I
01c- I 2 L
_J 1 I
G9
TB2 L _ _- _- _ _j
Frame
II
+o.2V Ref
+24V Ref
+24V Control +0.2V Ref +24V Ref
01 C Logic Fan
II II
II
01C Disk J5-4 PA451
PA~ P13·4
P13·10 P13·2 }
I I P13·5
D 18V AC Ref
P13-1
D 10V AC Ref
P13-6
DC Common 10V AC Ref 18V AC Ref
·II
P13-3 P13-9
P13·7
PA440
Notes:
D Typical value with system operating properly; for referenCtJ
only. Voltage measured with respect to DC common.
I I Connect this lead to T1 input tap corresponding to AC
input voltage.
I I Connect this lead to T2 input tap corresponding to AC
input voltage.
11 DANGER
High-voltage resonant circuit. Do not measure acroa C12
1 with power on. I I Low-voltage convenience outlet receptacle to be connected for 100V and 710V inputs. High-voltage convenienet1 outlet
receptacle to be connected for 200V and 240V inputs.
Low-voltage shown. High-voltage outlet connections same
as low voltage.
f l Leads in P3 and J3 are connected to pins 4, 5, and 6 for IJ. 100 or 770 volts and to pins 1, 5, and 3 for 200 to 240 volts.
SN also Note
I I Connect this lead to T2 input tsp corresponding to AC input for 100 or 110V.
El Tap1 2 and 3 on T2 primary are not brought out on transformer PN 7389297.
I J All units after EC 862592 have disk and diskette doublegroundlld.
(PA430 - PA432)
5-PA-31
8140 Models BXX 50-Hz AC Power
SY27-2521-3
REA 06-88481
5-PA-32
II
208V
>------< 6 >-------<.. 8
To 01G-J13
>------<.. 9
200V. 220V,
F 11
-------< 7
:::-F13
01G-TB3 01L-TB1
OlLJ/P . - - - -.."..'\ 01 E-J6-1 L~"---------------------------------------------
01L- OlRTB1 CB1
P/On 01
1 D ~ 'f lO""' 1 I
20A 0--"'""'"'4~-+-+~+---S-0::-I1:
~ 11p '\- 1I1Av Li~ n:e~e 18
I
I
.s..._r1.l-_1..l-._1.-.l-----'l""""_"r.'L_....1.._1._.11__
_
r
1
_
- L1
1
5-l '-
O-----'-1-It".2,". ~1I1 ----''I~e2 ~Il---'~71-1.
3
11_~1,,,. 1
III III _ r : 3 - 1
·.~/~>--=------,+.-_----~<-/#
01C-J11-1
0181-J1-1
01~~1-1
01C-TB1-1
/, - -_.- . . & - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -L----------+---------------------------------.
£_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
230V. 240V, 50 Hz Single-Phase
I I CBrirecaukietr
L~....;.;.;,..;.,;_--;.~F-----r~r--0-1-28
r - - - - _..J
I
A
I
01L-F1
I
I I
6 _L(""' 4
1 I
I I
I
J
1I 4
I
1
.L.:.._l_
~ A I" I
F12 (' I I
B i l_l_ 1,.,- I
I I
l~ I
II - I I I I I
II I
I : I 3 I
/ - ~ 41
5 - K50""~ "J7 01E-J11-1 '/0>1-E--T_.B.~_10l1-E1i-TlB2t-1--------+-----------------------------..
~
,-71-1,0lA-Jl-1
"~ -'----------+------------------------.
01A-J2-1 ~
l~_".. 2-l)
01A-J3-1 -' - - - - - - - - - + - - - - - - - - - - - - - - - - - - - -
< 2_ 01A-J4-1 - ) ---------+-----------------~ OlD-Jl-'lo- _l_C--T-B-2---1-----t-----------·-----.
I I
Othe' Count""4
I I
I I
I I
I I
100
I
VAC
Q>; I :.,:,:I
iij I cii
r=;c>v----, r 1_! I
--T 1
'---+TI-fl~11I---r--<-~""-6-~--. 7;-4s>------(
: :
0183-J1-· 1L'---------~---------.
01G-TB:7_
<>IB--rB3-:-~----1
I I
I
I
I
:I :I
I ..,-
01G-TB5-6Q I~ ~ 230V
II I
240V-:
: 01 R-TB3-4_
I I
230V-'.
I :
\
: 1
OlG-TBs-s..._. _22ov~
l ' t o1R-TB3-~ om
J ~--.'--r-l___________--;Ott17'G,-:;-Tn;B;c:5-;-4'---........!."""i..,-~2oo~v~ 01G ~ : 01 R~~i~ -T1
l r :-- " 8 J ' .I..::J___ 6
'""T f' ,---==:;___;._________J_____, l
'---l_-l--l~----L-----------0-1-G-.TB15·-1.
r-jI -4~ -
--- 5-3-------.
L..--7 6_3~ 1
I
.
.
.
1 ..-
.~ . ; _
l --
-fTJ2
I I
1 I
I 1
----u--.J_.L
200V~ 01R-TB3-1 :
~ ~-
; I
L
L __
~
01B3-J1-3~
fl I
I
M
M
M
I
01G Gate
Fan
01C 010 01A 01A 01A 01A 01E 01E 01C Front 01C Logic Gate· Logic Logic Logic Logic Logic Mot- Gate Cover MotFan Motor Gate Gate Gate Gate Fan or Fan Fan or
01E Gate Fan
01 H (Conv Outlet)
I
Fan Fan Fan Fan
:I ~1-38 01A-J4-3
01A-J3-3 Lt-----------------------+-----+------J
Notes:
I I Connect this lead to T2 input tap
I
I I
: L-72-3)
01A-J2-3 "L
2 01A-J1-3f''-\- . - - - - - - - - - - - - - - - - - - - - + - - - - + - - - - - - - - - - - '
< 01D-J1-3 ~.-------------------+---'
corresponding to ac input voltage.
f l See PA440 for 01 R-T1 and 01G-T2
secondaries.
B For additional wiring to K50.
see Figure PA442-2_
I
I
J.T5 lI
1: 01E-J6-3 ~L 01C~-T82-2
~
~
_: 01C-T81-2
73__33~.~._----7-+ 01C-J11-3 / ' ) - - - - t - ! ! t - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + - - + - - - t - - - - "
~- . - - - - - - - - )
00118812-~J1l-~3 L}~t-----------------------------------~----------------------------4--------4--~---~4~----'
K50'-----'\
'- 01E-TB1-2
4-3
1-~ 01E-J11-3 / ~
6
4
I
L _ _ _JI
"° - 01 E-T82-2
PA433 8101 50-Hz AC Power
8101 Models A1X, A20, and A23 50-Hz AC Power
P3Lw_J ,01A
J3r: 3
2
01A Gate Fan #2
Bk.Japan Bn-All Others
100, 110, 200, { 220, 230, 240V
50Hz Single Phase
____I _G_rn_l_Y_e1_ I
G10 G9
Wht-Japan Lt Blu-All Others
A F 11 B
Diskette Motor
G13
I' f-=
G13
fl
3
21 I 1I
L _ _J
i G14
G14
01G-TB3
II
r
I
09
230/240V Tl 6
200/208/220V
,. 7
120/127V 100/110/115V
Com
>- 8
,. 9
>~ 10
-=
T2
240V 230V 220V 200V 110V 100V Com
.,;
CD
N
I-
=Cc
..... c
..0... ·~-
0~ >.....
~ IQ
<( "C
Q. c
0
aa>>
0
Cl)
Cl) C/l
c12-f'l
ll__::L.-.3
3 2
P11
r-2-,
L -, I
I I I
J
OlC Disk Motor
,-,
I
01c- I 2 L
_J 1 I
G9
L TB2 _ _- _- _ _J
mFrame
OlC Logic Fan
+0.2V Ref +24V Ref +24V Control +0.2V Ref +24V Ref
D D
D
01C Disk J5-4 PA453
PM~ P13-4
P13-10 P13-2 }
D~ P13-5
18V AC Ref lOV AC Ref DC Common 10V AC Ref 18V AC Ref
D ...I. P13-1
·~. PlJ-6
_.. PlJ-8
DD . PlJ-9
-i Pl 3-7
PA440
REA 06-88481
SY27-2521-3
Notes:
D Typical value with system operating properly; for reference
only. Voltage measured with respect to DC common.
fJ Connect this lead to T1 input tap corresponding to AC
input voltage.
I J Connect this lead to T2 input tap corresponding to AC
input voltage.
DANGER High-voltage resonant circuit. Do not measure across C12 with power on.
Leads in P3 and J3 are connected to pins 4, 5, and 6 for 100
IJ. or 110 volts and to pins 1, 5, and 3 for 200 to 240 volts. See
also Note
Connect thi$ lead to T2 input tap corresponding to AC input for 100 and 110V. For 200, 220, 230, and 240V, connect this lead to TB5·6.
I J Taps 2 and 3 on T2 primary are not brought out on transformers PN 7389297.
mAll units built after EC 862592 have disk and diskette doublegrounded.
(PA432 Cont, PA433)
5-PA-33
8101 Model A25 50-Hz AC Power
SY27·2521~3
REA 06-88481
5-PA-34
r0-1-E--T-B-1 ,
- -:- 01 E Logic Fan 01E-TB2
I
I
r
-1
<>--+----+-~".l......-"'-~------------r--
a..-o--.;.....--..p.........._ _ _
Frame
r
I
-
r
-2 -
-,
e>--_.1
o
i--
.
01E Disk I I
I
Motor
I I I I
I I 2o-+-----t~>-.;....--+-r-----~
L--- _J
I I
IL-L-~-
G14
r - , 01G-TB5
= T2
01A Gate Fan #2
I
010
240V
.,;
230V
I
220V
:c N Cc:l
I..-.. c:
01A~f:f-:f!~
G13 _ GS
11:I
I
I
l..6-J
-= G13
L ..J
11
01A Gate Fa~#1
---------4-------... a r - 01G-TB4 l
r - - - - - - 01G-K2
1 ------~+--+-----+----~
1 I le>--t---------------+-----~I-r5"--
3
o-----+--+---------------'
Blk-Japan
I
200V 110V 100V
Com
C12~=
..0.. 3·-:
0 i ;>
<( ~
0... c:
Q> u0
cQn> cQn>
-
Brn-all others
I
FL 1
6
41
I
I 21
I
I
1 I
I
I
I
I 2 I
I 2 I
61
. .J
L .J
01G-TB3 G9
I I
I I I I
1 I
'--- _ _J
01C Disk Motor
G9
09
llFrame -
01C TB2
A F11
B
+o.2V Ref +24V Ref +24V Control +o.2V Ref +24V Ref
01C Logic Fan
01C Disk J5-4 PA453
PP1133-410 } P13-2 P13-5
PA440
230/240V
T1 6
200/208/220V 120/127V 100/110/115V
~~o
D
Com
18V AC Ref 10V AC Ref DC Common 10V AC Ref 18V AC Ref
01 E-J54-1 PA453 Pl 3-1
P13-6 P13-8 } PA440 P13-9 P13-7
Notes:
I I Connect this lead to TT input taP corresponding to AC
input voltage.
f l Connect this lead to T2 input tap corresponding to AC
input voltage.
I J Typical value with system operating properly; for reference
I a
only. Voltage measured with respect to DC common.
DANGER High-voltage resonant circuit. Do not measure across C12 with power on.
I I Taps 2 and 3 on T2 primary are not brought out on trans-
former PN 7389297.
I I All units built after EC 862692 have disk and diskette double·
grounded.
PA440 DC Power
T3
HS-2
m r
Bus.-.B...ar"W'- 6 01G-S1
JJ.
11
-r. 1r
~ 38 -
~
-
. __ "'\
_44_32+1i_ff__0B,;.1,:.2....-!11[+---l":..i.._oT....,..§..T..'_Ii~----'-~B.:::us~Blar
W5
1 ' 12
I _,_, I ~6 I
110 ®
~ 40 .i
j
13 ~
~
T3
TB6
33 34
441 45]
~_..4_311 --NVT'?J.?"""Iti
C9ll !L~_L1 V_'f D_B
I
_J
+I '..l..
l 1 w4D ___ ~ ~
IL
+-.L..c1+1~.1... c
...
10y
+ CB ........
,..........
W3 " - - - -
~ ~ ~_!_ 0 '~ 0 ~
J ~
Bus Bar
_/
Bus Bar
> 35 > 36
: T3
14 15
>16
17
1B
>
19
~
21
T2
·22
T3
25 37 27
01G
TB1 IJ
-"'>c12,..,..
E +5V
J7>.. 10-""'
A F4B
""" -cu
--.J"'....,.<~>---~ 1-+1-9'D--"-c"~u'
A F3 B
L'"o
t\8
__ia 7 J>.
ls:
~
~
~ -6~ -yq "'fQ
+5V +5V +B.5V
See PA441PA443 for DC distribution.
-12V
Gnd -5V
-5V
Com Com +8.5V +5V Com
-8.5V +24V Control -5V +12V 9.5V AC Ref 9.5V AC Ref 13V AC Ref 13V AC Ref 6V AC Ref
Com -5V
Com
+8.5V +5V
P7/J7
.---------------=~.-B;.5V__------------~<~'1<4
_ _ _ _ _ _ _ _ _ _ _ .-------------+~2~4~V,.+.2.4.V=C.o-n;tr.ol.._------------+-<~1- <3
,-------------___;-s~v.;,,,,;:_
--1~,1<5
,-------------.....:+~1=-2-V--------------'-~, 1(14
r-----------6-V.=...;A~C-R-ef_ll__.----------1~,l<2
r--------==--.:..~.:....:..:..:......__ _ _ _ _ _ _ _--1~,1<10
<11<12
.--------6-V'A-C-R-e~f "1"n19----------~i-{'<1<13
II
11--.....c=+-< .------·5~V,;.._-------------+-<~1<11 1(15 PC1 ~I( 8 Contains: ' Fuses
J J4/P4
1) 11"--
I/
2>1/>-1----' 3>:>>-+-----'
4 >I />-"------'
6)!/>-"-------'
~
~ I 1>' i~ '-/--> -1 +-2+ 4V - - - - - - -
} ,~ 2,.>:',,, I -5V
To 01D Diskette PA441-443
>J 3 /PJ
t1- -11-./.:, >----S+.-S=V=-=-=-~----
9.5V AC Ref 9.5V AC Ref 13V AC Ref 13V AC Ref 26V AC Ref
P10/J 10 F7 -B.5V 2)1) -5V
i< >:" ,---------i-<< 8 F8 -5V
} :---------1-<-<. 1< 9 F9 +24V
'-----------1-<, I< 1 F 10 +12V
3
-5V Sense
4 6
>>1">>
'
---5V-5V
+ 01-A--T-B-1Sense Ret
-
-
-
>: '-------------+-<,- 11(3
7 } > --5-V+01-A---TB-2- - - -
I> -< 1< 7 PC3 Sequence B)
-5V 01 A-TB2
To 01A Gate PA441-443
26V AC Ref El
( :< 6 Card (J 11) ~>--1-------
,....-------=---------+-<, i< 4
J6/P6
~ :;!~
} To01C
3> I ) > - + - - - - - - - -
t4-)-1-L +24V
Disk PA441-443
J13/P13 ~ T1-6
'
2 >: / K2-1
3 >1
KTAux Corn
4s>>:/I.).,__...__K2 _Au_x N_O __ To
6 )k T1-7
} Prime Power Box PA410
7 >:1; T1-10 ·· T1-8
s>I/ T1-9
9) I)>--+--------~: >--+--·_K_2.~-2'---~
.____ _ _ ___.._10---'-1- - '
24
6V AC Ref fJ
P14/Jlill-
J15/P15
Q6 l
26V AC Ref fl
11~218~~~1~~---~~-+-~----~----+-~~~--~--------l.~_!:.26~V!...!:A~C~R~e~f~fJI!!...~-
32
lll31t'ffi'----------t---------+--------------~f--__::-4~V~D~C~/9~.~5~-V4V~AD~CC/1~3R.5~VeAfC'.R.ef_
Com
-4V DC/13.5V AC Ref
'--------+--------'-----+--J J J
J
-4V DC/9.5V AC Ref -4VDC
-4V DC/9.5V AC Ref fl IU
I< 1
I "'I< <1<
3 4
5:~:
II
PC2 Contains: Fuse
30 29
-E
-4V DC 111 -4V DC/9.5V AC Ref 111
+24V
c13*.,.s+:v--<'<! 9 ~:<1
F14-4V
c~
II Bo-
-5V
,.P16/J16
Eo
I
Com
1 )I)
2>:,, 3>!>
4 >: >
Com -4V
-4V
}To 01C Disk PA441-443
I
'®,' m ,---::-...:
+4V DC
Ref 1f1
,\:
a2vHS·3
Com ~:----~1
Notes:
0 This jumper connects de common to frame ground.
IA12
'-----------~------------------------------~--~!--<._:_.(__.i...._._ _ _.....J
llfJ +1.5V DC Ref
f l Typical value with system operating properly; for reference only.
I J For additional wiring to TB 1, see PA441.
a For additional wiring to W3 and W4, see PA441.
For additional wiring to PC1, see PA441, PA451, and PA461. For additional wiring to PC2, see PA441, PA451, and PA462. Jumper present on 60-Hz machines only. For logic cable connections, see PA450.
Energized LED on PC2 indicates power fault associated with 01Cdisk. For adjustment of T3, see PA510. See PAl 10 for location and PA663 for connections.
Both AC and DC voltages on these lines simultaneously.
~ For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6,
llrl Pl/Jl, and P15/J15, see PA441.
ilJ For R1-R6values, see PA141.
Im R6 not connected for 768K and 1024K machines. IDJ Present with EC 321965 installed.
See PA710 for physical location of Q2.
Figure PA440-1. 8130 DC Power
REA 06-88481
SY27·2521-3
(PA433 Cont - PA440)
5-PA-35
SY27-2521-3 This page intentionally left blank.
5-PA-36
11 _... 38 _T_3_ 42 [Tf7J~2_~5 i
IEJ JBus -Ba-r W6 l
L o1G_iL'. ]
~ l r--../...,._ _ ___,
~ \
>- 12
40
n..l rti 43T I
_:;: 1..1 21
'~ ;:'.:':6T
441 __... I 117
I
I 1
Bus Bar 11~
J'C/
l ~ T0 /71>
W5 Y<71
~i.1l';-11~~ ~
L V'IT Ill '---<~~ -~-t1~l-. '~.J..::::::,:.·_~._---i1--<4~>5=-]+,-~..3...·,.-1~.....J
I
I
+ I
+ +
Rll5i0i~~ +
a .1--3-.:.3=3--+=-<T.-T3""B'~61_,.,,,_~___:;r~=rL·.;;.,~... L_D~_JrQ·} ~T.W.~.4L- .nc~.s.l~-TLc111~T.L~c100W3~
~
>~_.__
C8 '
7] 34
:-: 2 ~
·
Bus Bar
Bus Bar
~'-6r.~-----11"""1UJ>---~
A B
~...<.FO5=>----+-v>-U'I
~A F'4--a.A">----+~--<~
;A.""F-3'-B---o-~B-~---iiPl
)- 35 )- 36
~ 3 ~ ~ 4~
. T3
HS-1
F2
r~ --, -"
I """" I 1 D2 IA
B
1
L
I D4 I
I _lA
I
I r.r I
Fl
I l.
L _,....
~~ I~
I
I
I
I
I DJ I
I ~__.__.-4-4-T~1c:J-
L __ _J
7 W1
Cl '::f+
cs*+
-12V
Gnd
-5V
Com Com +8.5V +5V Com -8.5V +24V Control -5V +12V 9.5V AC Ref 9.5V AC Ref 1JV AC Ref 13V AC Ref
P7/J7 .-------------~~------------~~<;<4
. - - - - - - - - - - - - - - - - ' : : . . . . ; _ ; , _ : ;_ _ _ _ _ _ _ _ _ _ _ _+-<<1<3
,,( 5
,...--------------------------+-<,1(14 .-----------=--------------------1-<~I< 2 .--------=-=~=...:....:..::..:--1!!!....._ _ _ _ _ _ _ _~~,1(10
<:< 12
,..-----------'==-----------+-<<1<13
n....r----.1.r-+< PC1 .-----=-=----------------1-~,1<11 1(15 Contains:
-
~~<a Fuses
J J4/P4
1 >: >--
2 )I/.,.._.__ __,
>:3
/>--<>-----'
4 ) I /,__.....__ ___,
)! 6
/>--If-------'
I
J2/P2
1>: )_.__+2_4_V'----- }
1
2 >: /
-5V
J3/P3
1 >:>- -8.~______ ,
To 01 D Diskette PA441-443
9.5V AC Ref fl
P10/J10 T
9.5V AC Ref - - - - - - - - - + - < , 1< 8
_ _ _ ~-....____....._..
-=.13~V:....:....A~C=...:R~ef;....;_
,1<9
,......___...__ _ _~1~3V.:.....;.A~C~R~e.;_f 26V AC Ref
,----------+-<,I< 1
<1<
.{
i1<
3 7
<i< t i .---2-6V--A-C -R-ef""""'---------~~<1<46
F7 -8.5V F8 -5V F9 +24V FlO +12V
PC3 Sequence Card (J11)
2 )I) ·5V
n! > J>:>>---------
4 )I
·5V Sense
To 01A Gate
>
PA441-443
J5/P5
1>: l >1I> :r +12V
, ,
J6/P6
>--+--+_l'-"2:....:V,___ _ _
To 01 C
3 >I >--+--+_2_4_V____ Disk
4 ) I '>--.i--+_;2::-4:....:V,_____ PA441-443
I
>: J13/P13
,
l )>--+--T_1_-_6_ _ __
2
>1,>--...._K_2·_1_ _ __ I/
3 >I> K2 Aux Com
To
l4 >I )>--+--K-2_A_u_x--'-N-O-- Prime
5 >)>--+--T-1-_7-- - - - > Power
6)
1
I~'
Tl-10
Box PA410·
7s>>11/>>--T-l1--8--'-'-=----- 443
9>1'>--.i--T_1-~9_ _ __
.___ _ __._1_0_>~:>~-_:-K_2_·_ 2 _ _ _ 1
24
26
28 32 >- 31 30 29
-!:-
aNotes: This jumper connects de common to frame ground.
lfl Typical value with system operating properly; for reference
only.
I I For additional wiring to TB 1, see PA442. I I For additional wiring to W3 and W4, see PA442.
I I For additional wiring to PC1, .see PA442, PA452, and PA461.
Figure PA440-2. 8140 Models AXX DC Power
6V AC Ref
6V AC Ref fl 26V AC Ref I I
26V AC Ref f,I
-4V DC/13.5V AC Ref -4V DC/9.5V AC Ref
-4V DC I I
-4V DC/9.5V AC Ref I I
+24V ·5V
I J For additional wiring to PC2, see PA442, PA452, and PA462.
I J Jumper present on 60-Hz machines only.
EJ Far logic cable connections, see PA450. I I Ent1rgized LED on PC2 indicates power fault associated with
01Cdisk.
lliJ For adjustment of T3, see PA510.
P14/J14
J15/P15
Com
>-t------} -4V DC/13.5V AC Ref
I< I<
1 3
-4V DC/9.5V AC Ref -4 V DC
L/ I'
II<<
4
a 5llll nn , I 6
·4 V DC/9.5V AC Ref ... 111:.1 -.,,I(
! D ....__,_....;..:----1 v c13+_~rLa8.yLff--<<i<I(
9 7
r..
PC
S 2
.
Contains:
Fuse
1, Com
>:1
2 3 4
)I >~f--C_o__ m _ _ __
>>,i:·-))>>--+--<4-·v_f4-..-..-;_-V-_-_-_-_-_
To 01C
Disk PA441-443
F14-4V
C o--+----~·-----_..---
1
,
+4V DC Ref 11:9
UI
B __
HS-3
m P16/J16
E Com_\ 1
I
mR7 Is In Models A3X-A5X only.
A12 1 -~q<
...__~_....__ _ _~
\ - - _':_2..J
f l +1.5V DC Ref
lfJ See PA710 for location and PA663 for connections.
See PA710 for physical location of 02.
llJ Both AC and DC voltages on these lines simultaneously.
llJ On some special-feature machines, R50 replaces R4 and
RS by being wired directly across the C2 terminals, and the
I I For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6, and
P15/J15, St88 PA442.
Im For additional wiring to P5/J5, see PA442 and PA452.
C8 +end of the cable lead to J17-6 is disconnected and COVBred.
llJ For additional wiring to P16/J16, see PA452. Im Present with EC 867486 installed.
REA 06-88481
SY27-2521-3
(PA440 Cont)
5-PA-37
SY27-2521-3
m Bus BarW6
T3
TB7 HS-2
r "'"""-
G_G.st
l J
11 38 - - .__4_,_,2~,--<l-....:.1I+-l_':l_,__D.:.5_._1+-----+-l~~
~ ~U'21-+-t------~L
K. l
F6
01G
TB1 I I
\ Y \_
>>--
12 40
~
L
13 ~3
J 43 T
I
~ ~
2t
I
~ vi-06
441 _...31 07
J I
I
Bus Bar IJ~
~
~ l
W5
<?JI
T
~ __I::.!_ ~ ~I
A~l.......Q"'B--+~~1_2.n.'IV'.l
F5
j~ 11 "" +5V
45l~~l4'_v~o] ~Jt +:cs +: c1t:*c10
cs+~
~\.~ ...4........c,:.<B.~>r--------~--=+~-iso._L,A._~:1o_l,.tn>7.~ +5V
'->--~_:_-+-<!~~-~.(Dl--+----'lJ .------B-'--us'-B-~'-l+----~7J l ~ TB6
33
I I _.--.. 1 _n.
w4
[~ ~ ~ 0
t l - w3
0~ ® ©®
Bus Bar
A F3 B
~ ,z;1
L.__---OA_,.....,r"\'\\._,0-B--+J7A~7 .fl>.~
+5V
s
36 ; 4 ;
HS-1
F2
Busr+w2
I Bar
~ i
17.l_
r--
1./L '--------!-+--.
~~ +8.5V
-vu- --v
I:::;_--, _....
I _, T
I l l > - - - - , I D2 -1.
lIA
B -v(
+ i~2
I\
C6
~
''
R4
~ ~1 1..7..,l._vA-+C-,4nr, t·-{(?>-----1~-+-23.«/"'L,c--t--+-"-'fi.A'V2.~--e
See PA441. PA443 for DC
I 04 I
rf--0 I A. I
l r ,,,,,,~~-+-+-+-<l'l
I 1
~~
4-<f-
R3
F 1
-\0_../{"b8.-,
~IC~7+ ~
0-IU>-+---+-+~ R,~6 ~f-
~5
s;~ 5 'L
.----1-+-+---+--+-~~--+----"J\/'~,,,,.../"-~
_0_1--t-~:~ ~ >---I-+-+-"-:
;:.
p 17"'' J 17
_[
distribution. -12V Gnd
I
I
I 03 I
L
_ _ l ' , J
I
_J
\
W1
,..-rJ,fll"' '--'-+--~-H,__+___,.........,......-.L--.!+ !_P-_--~--~--'?>-~-,
Bus Bar
C3
I f/
Wl
>--+-+-+-+---+-----1>---+---+---------+-~_/c1~ cs~+
+
-5V
-5V Com
Com
+8.5V
REA 06-88481
Com
-5V
Com
+8.5V
+5V
P7/J7 ..--------------+-2_4_V_C_o-8_.n5V_t-ro_l_ _ _ _ _ _ _ ____....-<'1I < 4
.-------------+~2~4V-,-------------t'-(,f(3
-5V
'I< 5
.-----------+-1_2_V-------------+-<{1(14
.------------6-V_A_C_R-ef~--.:w---------r--<.~i< 2
a
.-------=--'-C--=-~---~-----------+-<1<10
I J4/P4
1 >:r+J
2>1>--~-3 ) : r>---+--~
>!4 ) I />--+---~
6 ,r>--+----~
6V AC Ref fl
<11< 12
.----------5-V---~C---------+-<,1<13
.-------------------1~,1<11
11~ 1 <15 PC1
J3/P3
~ ~< 8 Contains: Oi-,. - -8.5V
01A-TB1-7 }
P10/J10 Fuses
2 >!> +12V
01A-TB1-15
9.5V AC Ref fir---------+~./T( 8 F7 -8.5V 3 ) I r -5V
01 A-TB1 -9
9.5V AC Ref r--+----+--------1
.----+---+-1----13V AC Ref ..--+--+-<----1_3_V_A_C_R_ef_
~I
F8 -5V
< '
-
-
-
-
-
-
-
-
-
+
-
<
, I1<<
< :<
9 1 J
F9 +24V F10 +12V
4 ) II'r-
7 >, >
-5V Sense -5V Sense
Ret
OlA TB2 -
-7
26V AC Ref
<i< 7
fl .---2-6-V-A-C--Re~f------------+-<..-~-<·<-. -iI1<-<--46--<
PC3 Sequence Card(J11 l
PA442
P12/J12
01 N-J53-6 (PA452)f -Svs_Off .
';<' Bl 3
01 N-J53-1 (PA452)r -lnhib Oel!!Y < ;<so7
J13/P13
1 ) I
I
2 >1 /
T1-6 K2-1
To01G-T1 (PA412, PA422, PA423)
24
26
28 32 31 1[30 f29 ~
+5V Com -8.5V +24V Control -5V +12V 9.5V AC Ref 9.5V AC Ref 13V AC Ref 13V AC Ref r------------<>-----~
6V AC Ref J
6V AC Ref D 26V AC Ref fl
26V AC Ref I I
-4VDC/13.5V AC Ref -4VDC/9.5V AC Ref
-4VOC ti -4VDC/9.5V AC Ref fl
+24V -5V
l 3>1> K2AuxComm
4
5
)>I1,rr-<~K_2_A_ux""'""""N"""O_
6) i)>--t-T_l_-7_ _ _ _
7>1( i~~o
To01G-T1 (PA412,
189o>)>I:I)_">,->-t-----t'-"TK_""l"-2""--9'-_2..__ ____ ___
PA422, PA423)
To
P50/J50
J52/P5._2---~--~
--t<< TB1-4
-12V r
-
- --1.....-----.1-_
4 PC50
5
->lri:l-->1>-t-~~,-----.
>I .... ID PA443
i-<< 3
6
.,._ J. __
I - 2>!?!- Com
t<< 2
~< 1
Contains Fuse
3 1
>~~
>l>r,
r ;:::_,--, ---------.... F50-4V ~_?J~ +4V DC Ref ~ C
I l ~
+1.5V DC Ref_: 8
·9 It- 01 I
s-;r>l I Y~,.. I Com
E
J
3>fu L..:.:.·...J
...__ _ _ _ ____C..c.oo.~mm~ } Tpo 01 E Gate
J51/P51
----------4~-V4V- A441-PA443
Figure PA440-3 (Part 1 of 2). 8140 Models BXX DC Power
P14/J14
-4V
e -4V
ODCC//91.35.V5VAACCRRefeff flJl ll ~~ I<II~
~
4
-4V
lfl -4V
DC OC/9.5V
AC
Ref
fl
W
-<:<
r<' I<1<
6 8
9
:[aY" C13
!
II Aat~HSJ L.Lf-<1< 7
9 Im _j_
PC2 Contains: Fuse F14
See PA710 for physical location of 02.
-4V
c~o-~--~·-----.-~-~
B E
Co' ~l:
1
+4V DC Ref
\:,~:"DC fJ A·f
5-PA-38
-- -- ---- --- --- - -- -- -- -- --- -- --- --- ----
r-01R--
R3
R2
r - , -~ -~-----
1
4
5
6
7
L
-:1
~I
Ill
TB4
_ 9 _1J0
TB1
T1*
171
HS1
r-;~~~--,
I
I
I
I
I
I
CR2 A
I I
L-- - _J
+ + C1 C2 R1
r -TB12
F1 I I
I
I
I
I
I I
4 I
_J
l_ _ _ _ _ _ _ _ _ _ _ _ - - - _ _ _ _ _ _ _J *See PA412, PA422, and PA432 for 01R-T1 primary.
Figure PA440-3 (Part 2 of 2). 8140 Models BXX DC Power
REA 06-88481
SY27-2521-3
Notes:
D This jumper connacts de common to frame ground.
f J Typical value with system opBrating properly; for f'tlferencs
only.
I I For additional wiring to TB 1, 11t111 PA442. I I For additional wiring to PC1, see PA442, PA452, and PA461. I I For additional wiring to PC2, see PA442, PA452, and PA462.
IJI Jumper preStlnt on 60-Hz machines only.
B For logic cable connections, see PA450. I I Enef'(/izad LED on PC2 indicates power fault associated with
01Cdisk.
I I For adjustment of T3, 11t111 PA510. IDJ Set1 PA110 for location and PA663 for connt1etions. ID Both AC and DC 11oltag1JS on theStl lines simultaneously.
mFor additional wiring to P4/J4 and P15/J15, see PA442.
llJ Depending on the features installed, add and/or remove jumpers on
TB4 as follows:
Featurets, Installed
Add Jumper
Communications or Tape or Communications and Tape
3 to6
Communications and Floating-Point or Tape and Floating-Point or Communications and Tape
3 to6
Communications in C2 and 02 boards or Display /Printer
None
Floating-Point
None
Display/Printer and Floating-Point
None
Note: Connect removed jumpers between TB4-7 and TB4· 1a
llJ For additional wiring to PC50 and PC51, SH PA453. I I Present with EC862250 installt1d.
Remove Jumper 3 to 8 2 to 8 and 3 to 8
3 to8 2to8 2 to 8 and 3 to 8
(PA440 Cont)
5-PA-39
TJ
HS-2
:u 11 ~ 38 - ._ _42_.i.,_f'T-t~>-7-l~H_- ;:t-_,D.5...-1+------t----,
>- ~ "'\ 43 1
J v
I Bus Bar
l W5
>-1_2_ _ _ _ _'--1_~2-+l_v-1_-=D=6~~I
)- L ~ ~
441 45}
~31t
-;::
~7
J
T I
rr'i> ~ <b ~lJ l
13
T3
l~Ll.--1"D~J
TB6
33 34 35 36
C1 :::=: +
24 26
L 28 32 31 >-30 >- 29
-=
Notes:
D This jumper connects de common to frame ground. f l Typical value with system operating properly; for reference
only.
I J For additional wiring to TB 1, see PA443.
I I For additional wiring to W3 and W4, see PA443.
SV27-2521-3
REA 06-88481
-
01G II
U TB1 ~~:A.0>---+~_ni..~12_~VA} +5Vto
Com
A B
l l
A2 Bd
-5V Com
+5V to Bl Bd +5V to Al Bd +5V to Files
+8.5V
See PA441PA443 for DC distribution.
+8.5V
+5V
P7/J7
,--------------+=2~4~V-C-_8.o5V_n_t-ro-l-----------1r-<,,/ '< 4
r--------------=:....;_:-:-=-------------t-<-<1<3 r------------+~24~V-'---------------t-<~l<S
_ .-------------~s_v _ _ _ _ _ _ _ _ _ _ _ _--t-<~1<14
.-------~----------~6+V~.1.~::2.v.-.'..-.-:-.-.A-~-C="--'.-.'.R-~e-f-~-=-=t-l-----------r---~<+;-J<<I1<<120
,,_._--_ ---_-~_s6~Vv__A__C__R__e_t_-=_fJ_=-_-_--_--_--_--_+-~-t-<<<l.,1:<<<l11123
n__. _-.Jr-+< '< 15
PC1 Contains:
-
-L__f-< ~< 8 Fuses
1J4)/P:>4 -If-l
2 )I),__..._ _
>:3 )>--!"--------'
4)1/~~--~
6 >! >>--~-------
'
J2/P2
1>: >>-~+2;::_4_V;;__ __
>: } 2 '>--1---'-5'"-'V~-----
To 010 Diskette PA441-443
, J3/P3
1 ) 1I,,___,,__-_8_.5_V _ _ __ _
+ C5-f::
-12V
Gnd
-5V
-5V Com Com +8.5V +5V Com
fl P10/J10
,---+---+-l----~9~.~5~V9~.5AV~CA=-C:.R.e.fR~e-f-;;;;;r----------1--<,l1' (8
,------------4-<-< 1< 9
:<J 13V AC Ref :----------+-<.,_I( 1
13V AC Ref ---------~-<< .----=2~6V.:.....:.A~C=-:...R_e_f_..__ _ _ _ _ _ _ _+-<-<i< 7
26V AC Ref fl
( :< 6
r--------'='----------t-<.,1<4
F7 -8.5V F8 -5V F9 +24V FlO +12V
PC3 Sequence Card
PC4 Pwr Seq Card
>;2 )I)
3 >>--+--_"--5v-"--------
4 >j / -5v Sense
}'
To 01A Gate
7 >,)
PA441-443
J5/P5
1, +12V
>Ir :J
·/
J6/P6
} l ) 1I /,>--.,_+_+21_42_VV_ _ __
J ) 1/>---+--+-2_4_V_ _ __ 4)1/>---1---------
To OlC Disk PA441-443
1
' J13/P13
l ) 1'->--i"--T_1_-6_ _ __ 2> <>--l..__K_2_-_1_ _ __
Ir
-8.5V +24V Control -5V +12V 9.5V AC Ref 9.5V AC Ref 13V AC Ref 13V AC Re~----------+---6V AC Ref~
3 4
>>1i)>>-+--K-K2_2A_Auu_xx_NC_oO_m
_
!65>) I
)r--+-------)>-~T_l_-_ 7 _ _ __
>-
>i7
S
>I
>~i---...:T'--'1_-1,:_;0~-- >~,___,T...;1-::-8~---
g) l~-T_1-_9_ _ __
o> 1 I ,,.K~2-~ 2 -----
1
I
'------~--~
To Prime Power Box PA410443
P14/J14
J15/P15
6V AC Ref fJ
26V AC Ref fl
26V AC Ref fl
-4V DC/13.5V AC Ref -4V DC/9.5V AC Ref
-4V DC 6 -4V DC/9.5V AC Ref f l
+24V -5V
I I For additional wiring to PC1, see PA443, PA453, and PA461. I I For additional wiring to PC2, see PA443, PA453, and PA462. fJ Jumper present on 6().Hz machines only.
mFor logic cable connections, see PA450-
Com
Dt-<I< 1
-4V DC/13.5V AC Ref -4V DC/9.5V AC Ref
t-<k'< I<
3 4
-4V DC -4V DC/9.5V AC Ref
fl~ifJ'j < ')': (<986
C13 ~SYi !
+LJ...f-<__:< 7
Im For adjustment of T3, see PA510.
llJ See PA710 for location and PA663 for connections.
mBoth AC and DC voltages on these lines simultaneously.
llJ For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6,
P16/J16 A12
t < 1~
PC2
Contains: Fuse
1
Com
1
>,2
)I ) 1 -
>
- Co-mi
-
-
-
-
-
-
}>--1t---------
>: } 3 )~ >~1--4V--------
4 )>--1~-4_v_ _ _ __
To 01C Disk PA441-443
F14 -4V
I
+4V DC
l AYa2: m E~ Co~ II cB~o--+----'-'--:---.------~HS·3Ref fl
\~;-~:~c Rel fJ
See PA710 for physical location of 02.
I J Energized LED on PC2 indicates power fault associated with
01Cdisk.
P15/J15, and P16/J76, see PA443.
ilJ For additional wiring to P5/J5, see PA443 and PA453.
Figure PA440-4. 8101 Models A1X, A20, and A23 DC Power
5-PA-40
Im Bus BarW6
_____ ,.---,
T3
-os l 11
>
~ _.... 38 -
-
"'\.
HS-2
4432I_f~f811_}i
-
,,.....,.
J
I Bus Bar
·r,0 01 01 >-1_2_ _ _ _ __,_I_"__,21_..._...,.._,,o,........s+-+---,I
l a ~1-~~--4--04~_-1:::IL~u~u.~._.L,4__4_14_5-tq_:I-<~>-31-0r-71~ 1
'(
L~l__o~.J
J
+ r
}r..l.
TJ
W4
r
......_-;;: 01G-S1
l W5
~ ~ L1 ~ ~,2.f..7/,,X._._._4_-_--~lA~'-6...B.C'"'>---~1~ "~ 1.T0~1B12G1_~~E~ }ll
+SV to A2 Bd
+ +
+
~'-~_A">---~~n-10...~.r.&"l
n. C 9- '[- c 1 1 1 - ' - c 1 0 W3
ca....1...
~'A---F..4.CB">----Hi~f_)-9-1~_~ +5V to
mJ TB6
111 >,.-~33-43+--<1~ _1-!-.1-2<_>~,,.J~---.."
[~ 0 l0lii-l ~ ~~ 0 ~ ~ ~
Bus Bar
7
Bus Bar
l .___----O'AA. F'--3-"-"rB-B-~~,___1~.s..~0A
A1 Bd +5V to Files
35 ~3~ 36 ~4;:
"""'CU ~
., T3
..
~ 6 +8.5V
14 >IS
>16
17
>1_8
~
19 >20
> 21
T2 >22
>23"
25
See PA441PA443 for DC distribution.
-12V
Gnd
-5V Bus Bar
Com
-5V Corn
+8.5V
+5V
-+-<<;<4 P7/J7
.--------------~_.5_V_ _ _ _ _ _ _ _ _ _ _ _
. - - - - - - - - - - - - - - - -+-24-V -Co-nt-ro-l - - - - - + - < < 1 < 3
..-------------+~2~4~V-------------+-<,!<5
.------------- -5V-------------+~<1<-14
B. _ _ _ _ _ _ _ _ _ _ _+_1_2_v_ _ _ 6V AC Ref
- - - - - - - - - + - < < 1<<1(12Q
-<11<12
fl r------6-V-A-C-R- ef==----------+~<1<13
·5V
<1<11
·---.+< . ~~<8 lq5
P10/J10
----L-~---_.:...9·...:..5...:..V..:9...A5.V..:.A.Cc=-RR_ee_ft-'.fl=:--------+~, T1.< 8
13V AC Ref fl 13V AC Ref ~fJ
26V AC Ref Ka
<'',1I~i<<< 3197
< fl :< .
-
-
-
-2-6V-
-AC-
_Re_f
;
;
;
-
-
-
-
-
-
-
-
-
+
-
<
,
,
(
6 4
El
PC1 Contains: Fuses F7 -8.5V FS -5V F9 +24V F10 +12V
PC3 Sequence Card
J J4/P4
1 >: >--
2 )I)
43)>:1>>
s>!> I
J2/P2
1 >: >
2): / I
+24V -5V
J3/P3
1 >: >
2 )I'
>1"
3)1 4 )I)
7>! >-
-8.5V +12V -5V -5V Sense -5V Sense Ret
n:J6/P6 >
3>1>
+12V
+24V +24V
PC4 Pwr 4 >' /
I
37 27
-sv
Com Com +8.5V
To
P:o_1~_5__,o_ _ ___, J52/P52
--r- TB1-4 -12vr;< 4 PC50
PA443
;-(( 3 llJ
1--).,>-+-- - - - - ,
65 >1,(,'>-,----.
Seq Card
J13/P13 T1-6
21>>''~' K2-1
1"
+5V
Corn
·8.5V
+24V Control
-5V
+12V
9.5V AC Ref fl
_ _ ____,,___ _ _ _ _ _ _ _ ~---+-t
9.5V AC Ref ;....---------+----'
-+---------------------~
13V AC Ref
13V AC Ref
6V AC Ref
____c__- _-__. r Com
I ;-( (
2
I,< 1
Contains Fuse Fso-4v
~~ 2
3 1
)>) I1'>II +-~~ ....
..,
....
I.-- --, +4V DC Ref ~ c
fl]- I t-- l +1.5V DC Ref_: B
I I-- 01 I
E
I T7 I
L
lvvv-,
_ _ _,
c
om
i-;>-1r>11 3)J.~
Im J51/P51
3>, 4>i>
56)>1"~
I~ 7 >1 / 8)j)
9>!> 10>:>
K2 Aux Com K2 Aux NO
T1-7 T1-10 T1-8 T1-9 K2-2
CCoomm} -4V
To 01E Gate
-4V PA441-443
}To 01E Gate PA441-443
}To 01A Gate PA441-443
}To 01C Gate PA441-443
To Prime Power Box PA410-443
,
~
6VACR~6
l
26V AC Ref 6
26 "1
P14/J14
J15/P15
28
26V AC Ref I I
< ( .:.. n:1 I I 1
IJ
1
1 )I
.,C~o- m -----
32 31 >-30
r--~-2_9_
_
_
_
_
_
_
_
-4V DC/13.5V AC Ref
-4V DC/9.5V AC Ref
-4V DC 6
_t----------+-----------------+---4~V~D~C~/~9~.5~V..;,.;A~C.:::....:..R~e_f_..fl..___
_
_
_ _._ _
_
_
_
_
_- 4_
_
_
_
_
_
-4V _DC/13.5V AC Ref U IU _/I<
fJI -4V DC/9.5V AC Ref
lfJ--t-( l<
-4V DC
fl ·--f-<I<
_-4_V_D_C_/9_.5_V_A_C_R_e_f_fJlfJ
I(
3
4 s
S
PC2
>i2
J
)
1_)">--l_Co__ m _ _ __ 1)'>---'--4-'-V_ _ _ __
lFcuo~nFta1i4n-s4:Vt---4''>-:->-~'--4_V_ _ _ __
To 01C Gate } PA441-443
~
Notes:
I I This jumper connects de common to frame ground.
f l Typical value with system operating properly; for reference
only.
I J For additional wiring to TB 1, see PA443. IJ For additional wiring to W3 and W4, see PA443. I I For additional wiring to PC1, see PA443, PA453, and PA461. I I For additional wiring to PC2, see PA443, PA453, and PA462.
+24V -5V
! C13 ~r8-rVf-<"1 ( 9
fl L - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . Jumper present on 60-Hzmachinesonly.
I I m For logic cable connections, see PA450.
IJ Energi~ed liJ LED on PC2 indicates power fault associated with
Both AC and DC voltages on these lines simultaneously. For additional wiring to PC50 and PC51, see PA453.
+L..Lf-<1<1
P16/J16
1
~A
~<
12
II
+4V
CBv---"'-~~-11~:--;t-_--,1'.-i-1-?2~tl~3Ref
fDlC
E
C
o
m
\ : '57 ~- _
_
1
_J
II
\_ +1.5V DC Ref fl
01Cdtsk.
lliJ For adjustment of T3, $88 PA510.
mSee PA710 for location and PA663 for connections.
r_n... For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6, and
mP15/J15, see PA443. For additional wiring to P16/J16 and J51/P51, see PA453.
ID) Present with EC 867485 installed.
See PA710 for physical location of 02.
Figure PA440-5. 8101 Model A25 DC Power
REA 06-88481
SY27-2521-3
(PA440 Cont)
5-PA-41
SY27-2521-3 This page intentionally left blank.
6-PA-42
PA441 8130 DC Distribution
D OlG TB1
--,,.. 1 JOO. -5V ""' a2~
"1--
.n. 3 ,_.}-----f
-- -~
Ill.. 4 1"" -12V
......
lllll. 5 ..a. +8,5V
01G Gate DC Power Distribution to the 01A Logic Gate
I I 01A-A1
Board
+5V
+5V Com
-1<:< 4 J1
~
OlA TB1
_r;;-:-: m..
,..., -
1 ~..a:;:.------+--------, __.. ---+~5_ v _ _-+-------.
2 y
'-----C+5oVm---~~ ~ ~ J2 +5V
3 ~~~~'.-----------+----+-----.--,
,(4 J3
Com
~
-8.5V +5V Com
r-'"((3 -"(4 J4
.< ....5___
-B.5V +5V Com
..-----
--.(3 ,(4· J5
2/:(.5._· _
.",.",'10-""""' +5V
lllll.11 _,,,._ +5V
IL - .,., ..D.ll 12 _m.. ~
+5V
-5V Com +5V +8.5V
-5V
~-
,( 1
_/< 2 J7
-;:/( 5
..._( 6 '--
r_/-<- , -
01G-PC1
fl
J3/P3
1 );'
2 » 3 »
4~ /T
6,.-,.
-8.5V
-5V -5V Sense -5V
DC Common
Com +5V +B.5V
-5V Com +5V +8.5V
<<2 --.< 5 J9
.,_(_6 _
'J(1 <<2
<(5 JI 1
,(6
7 »
8 ).'
9 »
-5V Sense Ret -5V -5V
IJ
-W3
,..--
-
DC Common DC Common
I
._ t--
W6 I I IJ
r- r-
01A-TB2 _ ~+5::..:V _ _ _ _ _ _ _ _ __,
-- I J~-------,
01A-A2 Board
(¥'
~
-
2
.Q'~"A"-..-.!\:....:....:._=_+=_5V=_==_ =::-:+;----t+-;-=-t+:=-=-=,+=._=_===_=1_=iC++.-..85;o;-;..mV.5;-._V-~_~------1+"<~-,<<..('(<152
JI
..., 3 .A.> ,..+...:8;.;.;.5;...;V_ _+-__..
-- .,., 1i%t: :----+---+-t-t---t-,
-5V +8.5V
~ -"(6
,.---
-"(1
+5V
-·'( 2
Com
J3 ,(5
-5V
.,.(_6,
Ja.
-
.A>.
7 8
-8.5V
-n"-v"-~~V-----5--V-. .+.-. .+.-+---+i--- .+.-+++---' ........---~-+-.,__
+8.5V +5V
_-C"o=m;..
;
.
.
_-
;,__..
--.< 1
<(2
--K·«: 5
I
J5
_. - K'----+-+-.
l
5V
..,.(_6__
DA.
DC Common
~ 9 ,....L- ----+-+-++-t-'
-5V Com +5V +8.5V -8.5V -5V
r--1
-<< 1
-«<Os J2
2- ":(_6 . ,
r-;z:- ........ 1
~u4D07
Notes:
I I For additional wiring to 01G-TB 1, see PA440. f l For additional wiring to 01G-PC1, see PA440, PA451.
Com +5V +8.5V
-<< 2 J4
=<< 5
~ -"(. 6
I I For additional wiring to 01G-W3 and 01G-W4, see PA440. LC.D.Com::m:o.n.:.:..:..:.:.;.::::.:.+-t--------C--5o-mV--=~---;-,,-<."(-(21--.
I I For additional wiring to 01A-A 1 Board, see PA451.
+5V
-"< 5 J6
I I inc <<6 For additional wiring to Disk Drive, see PA451.
+8.5V
I I For additional wiring to 01G-PC2, see PA440, PA451.
I J For additional wiring to 01F-BOP, see PA451.
I I Present with EC321965 installed.
II
01G TB1
-5V
IL ~ ~ Olt.2~
DC Common
~
.......,..
3
- t-..:
~
~?\.
1'. -12V
1-[6~ 121. 5 ""' ,.,
..,
+8.5V +5V
DA. 7 ,,.,..,v
L'~ +5V
-..n.o,.. 8 ,_..., ').,_
.a.,. 9 .A>.
, +5V 1
"""'"10J~ 2L
.a 11 ,.._
+5V 1'
+5V ,
-- -1C12:
...,
J2/P2
OIG PCl
fl
I)>
2 »
f---J6/P6
f----
1 »
3),,
4 »
+24V -5V
+12V +24V +24V
J15/P15
» 01G PC2 1
Com
II 2»
Com
3))
-4V
-4V
4))
l
01G Gate DC Power Distribution to the Operator Panel, Disk, and Diskette
A3
1
+5V "'( 803
Com
808
"'< -5V
< 006
~
BOP Adapter
j< +5V
~ Cables
...1( 803
Com
808
·« +8.5V 011
Com +5V
J1
°"'(3
,(4
01F-A1A2 BOPIJ
Diskette Control A2 Card
;, +5V -"'(
+24V ,(
-<< -5V
..Com
-<<
003, J03 D10,J12 011, J13 DOB
01C-A1 Board
(Disk Drive)
J1 11
-12V I./, +12V ,( 1 B2E1
,(2 B1E14
See { -f<<J
PA453 ~
~
i<< Com
1 B3E1
+5V ,(2 B2E14
I
]
-4V Com
,(3 B3A1
,(4 B2A14
~
~
Com +5V -4V
lo(( 1 B5E1
-((2 84E14
l.((3 B5A1
Com ,(4 84A14
L.......-
Com +24V +24V
~
l..((1 -((2 l.((3
B6E1 BSA14 B6A1
Note: See PA140 through PA743 for locations.
REA 06-88481
SY27-2521-3
(PA441)
5-PA-43
SY27-2521-3
REA 06-88481
5-PA-44
PA442 8140 DC Distribution
01G-TB1 El
c~ :
..i..e
+8.SV
I~ - 5---
c:
- --- - 9---. +5V
- - -..10_ +5V
Ill
_ 11__.... +5V
- - 1c,2: +5V
Ill
01G Gate DC Power Distribution to the 01A Logic Gate
01A-TB1
- - ..a 1 ~
--_-. 2...llflo.. - .A. 3 _...
'!.
- ....... 4 _..Ii.
L.
~
- -r-- 6_.. - - 7 ....
~
- -. 8_..
~
- - :a. 9 .......
- ..... 10......
_I
l
lL:
+5V L{( II
l
l
D +5Vl l ( l'
+5VJ.1( l'
El
-5V .J( 1
. +8.5V
}(
r~
4
J1
J3
+8.5V_L,(
l'
4
~
D DC Com .J( ~
ml DC Com_.r..,( ~
01A-A1 Board
II
B3E01 B2A14
B4A14
m DC Com_u( L'
J3,'P3
» -8.SV
1
3)) -5V
01G PCl
4)) -5V Sense
II ~
,.
= 4 01 K-R2 ~m~
01K-R1 ~~
J5/P5
r,-y::J+12v
"' _J
m
·,,__
W3 1
DC Common
a 2111
3
-4 I-'
~--
f l W6
,.... .......
5d1. DC Common
W4
a 6 7
.8..___
Figure PA442-1 (Part 1 of 2). 8140 Models AXX DC Distribution
01A-TB2
- -...... 1.-.
- - -- 2 --- .A. 3 _.....
"[
..,4 ......
- i:.
- - ..... 5 .....
.Alo. 6_...
-..z..\
..... s .....
[-9~- -- 10_....
_I
l
i/
D
m
/._
~IE
l
+5V I (
~
II
01A·A2
Board
II
IJ +5V r:;-( "['
1 l l
+5V .1 i(
T'
l!I
J
-5V .1 ' ( 1
.. +8.5V
.)(
r~
4
B3E01 B2A14
+12V J4
+12V JS
+12V J6
-8.5V
H2D07
J3
+8.5V ~< 4
B4A14
::{{ 4
DC Com -<< II
{<-:!
DC Com ,( ml
U2A14 J3A14
~< 4
J4A14
DCCom~
01G Gate DC Power Distribution to the Operator Panel, Disk, and Diskette
5V
II
~DCCommoe
~' -*~
1r.-: ~ IL- 3 - "'
- ~ ..., 4 -A
+8.5V
~ ..... ...,
I~~ - 7
~
+5V
c:~ 2
J2/P2
OlG PCl
IJ
» 1
+24V
2).r
5V
t-----' J6/P6
t------1 1))- +12V
3))- +24V
4» +24V
J15/P15
PC2
m
1» Com 2)r Com
3» 4V
4» -4V
'--·
AJ
+5V -(( 803
Com << BOE:
-5V , ( D06
BOP
~
. - - - A4 Adapter Cables
+5V -( < 803
Com "'< soe
+8.5V -( (
D,,
Jl
Com ,(3
+5V -((4
01F-A1A2
BOP 1IiJ
J2
Com
·5V «1 01F-A1A3
.. sv
-((3 EFP
I
Com ~(4 Register
Com ~(5 Card
J2 r---
+5V
J'(4
01F-A1A1 EFP Mode
Card
+5V
A2
-((
·24V ·«
-5V ..,,.(
D03,J03 D10,J12 D11,J13
Diskette Control Card
~ < Jl
DOS
i
To PC2-J 16-809 f;
-12V ./( 1 B2E1
·12V ~(2 B1E14
.,_ ( 3
.-ll--
Com -< ( 1 B3E1
·5V -«2 B2E14 -4V ,(3 B3A1 Com ,(4 B2A14
.....__
01C·A1 Board (Disk Drive)
Im
Brake To PC2-J16-A12 ,
,.lL-
Com ,(1 B5E1
·5V {<2 B4E14
4V J'(3 B5A1 Com J(4 B4A14
.....__
. -J5- -
Com -< <. 1 B6E1
+24V ,\ 2 B5A14
+24V <3 B6A1
(4
Notes:
I I This wire in Model A31-34 & A41-44 only. B For additional wiring to 01G-TB1, ·e PA440. I I For additional wiring to 01G·PC· 1,,.,, PA440, PA452 I I For additional wiring to 01G·W3 and 01G·W4, Stl6 PA440. I I For additional wiring to 01A·A 1 and 01A·A2 Boards, see PA452
I I PIN
PIN
E1812 OR E1C12 E1012 E1E12 F1A12 F1812 F1C12 F1012 OR
(Y2C04) (Y2C05) (Y2C06) (Y2C07) (Y2C08l (Y2C09) (Y2C10l (Y2C11)
I I PIN
PIN
E6803 OR (Z2C04)
E6C03 E6003 E6E03 F6A03
I (Z2C05) (Z2C06) 1z2con (Z2C081
l F6803
F6C03
(Z2C091 (Z2C101
F6003 OR (Z2C11)
I I PIN
PIN
H1C12 OR H1012 H1E12 J1A12 J1812 J1C12 J1012 J1E12 OR
(Y3C04) (Y3C05) (Y3C06) (Y3C07) (Y3C08) (Y3C09) (Y3C10) (Y3C11)
mJ PIN
PIN
H6C03 OR (Z3C04)
H6003
(Z3C05)
H6E03
(Z3C06)
J6A03
(Z3C07)
J6803
(Z3C08l
J6C03
(Z3C09)
J6003
(Z3C10)
J6E03 OR (Z3C11)
I I PIN
PIN
M1A12 OR M1812 M1C12 M1012 M1E12 N1A12 N1812 N1C12 OR
(Y4C04) (Y4C05) (Y4C06) (Y4C07) (Y4C08) (Y4C09) (Y4C10) (Y4C11)
Ill PIN
PIN
M6A03 OR
M6803 .. , M6C03 M6003 M6E03 N6A03 N6803 N6C03 OR
(Z4C04) (Z4C05) (Z4C06) (Z4C07) (Z4C08) (Z4C09) (Z4C10) (Z4C11)
Figure PA442-1 (Part 2 of 2). 8140 Models AXX DC Distribution
mRequired for Models A61·A64 and A71·A14 only.
Ill On some special featured machines to reduce voltage drop to
match the 11f1W current loads, the position of the following leads are exchangsd:
Lead 1 at TB 1·9 reattached to TB 1-11
Lead 2 at TB1-10 reattached to TB1·12
Lead 16 at TB 1· 11 reattached to TB 1-9
Lead 15 at TB1·12 reattached to TB1-10
Ill For additional wiring to 01G·PC·2, .,,, PA440, PA452 I I For additional wiring to 01C Disk Drive, see PA452
mFor additional wiring to 01F, BOP Panel, see PA452
llJ For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6, and
P15/J15, see PA440.
llD For additional wiring to 1'1/J1, see PA452
fZ;J For additional wiring to P5/J5, ·e PA440 and PA452
mPresent with EC867486 installed.
REA 06-88481
SY27-2621-3
(PA442)
5-PA-45
D
-5V
01G-T81
DC Common
~
~ AA_ 2 ,,.
[[' -....,. 3 ....
- ""' 4,.,.
--::::: ~
""' ~
:C +8.5V
~
-.Al 8
- [ .., .., 7-
----=:::::
~
~
~
+5V
b 2
DC Distribution to Operator Panel, Diskette, and Disks
A3
+5V ,( 803
Com J( 808 -5V ,( DOG
....___ BOP
A4
Adapter
-<< r -
+5V
Cables
603
Com ,( BOS
+8.5V ,( 011
Jl Com
I I {(3 01F-A1A2
+SV ,( 4 BOP
J2
-<< +5V
+SV
1 01F-A1A3
{(3 EFP
Com ,( 4 Register
.< Com
5 Card
J2
+5V
01F-A1A1
~(4 EFP Mode
Card
1: -l 2V Sns->01M-J16-B12 (PA452)
~ +SV To 01C-EC1-8 (PA452)
Notes:
I I For additional wiring to 01G-TB1, see PA440. f l For additional wiring to 01G·PC1, see PA440, PA452, and PA461. I I For additional wiring to 01M·PC2, see PA440and PA452. I I For additional wiring to OP Panel, see PA452. I I For additional wiring to P2/J2, P4/J4, P6/J6, and P15/J15,
seePA440.
~ For additional wiring to PT /J1, see PA452.
For additional wiring to K50, see PA412, PA422 and PA432.
DmFor additional wiring to PC50, see PA440.
Figure PA442-2 (Part 1 of 2). 8140 Models BXX DC Distribution
SY27-2521-3
REA 06-88481
01G-PC1
fl
J2/P2
1)) 2))-
+24V -5V
Com
~ 3 ) '
J5/P5
~ ~
~
1 ),", +12V
+24V 3))
+24V 4))
J15/P15
01M-PC2
IJ
1 »
2)) 3)) 4))
Com Com -4V -4V
J
.....
Com
l
Com
l.
Com
J
.
To 01MPC2-J16-809 t
(PA452)
A2
+5V ,(
+24V -5V
:;?'
<<
;1,,·((
J1
D03,J03 010,J12 D11,J13 DOB
-12V ,( 1 B2E1
+12V ~(2 B1E14
;< - Pwr Good y 3
~
,...J--2---
-<< Com
1 B3E1
+5V
-<< -4V -<< Com
2 B2E14 3 B3A1
-<< ..._4 B2A14
J4
Comr.,.-..;z1- B5E1
+5V -4V Com
,(2 B4E14
.,..( 3 B5A1
-<< 4 B4A14
L---
JS
Com.---
-l-- +24V Brake +24V
01G-K2-2 ~ra~e
(PA440)
1
2 Applied
.~/( 1 B6E1
«,( 2 B5A14 3 B6A1
i<4
J1
- Pwr Good 01 N-J54-5 L (PA452) I
-<< -12V
+12V
<<1 B2E1 2 B1E14
~ ./( 3
J2 Com r - -
,( 1 B3E1 +5V
,(2 B2E14 -4V
,(3 B3A1
Com
......,__(__4_, B2A14
01NJ54-10 (PA452) +Brake Applied
01N J54·1 (PA452)-Pick K50
IJ
+24 P/On 01G-J8A08 L (PA452) I
1 1
- .K ri
01E/K50
.,...
J4
~
Com , ,( 1 B5E1
+5V _...( y 2 B4E14
4 -4V
Com
./(
~(
3
B5A1 B4A14
,___
JS
Com~
.-+24V 1+24V
.~/(( 1 B6E1
\~ B5A14
)( B6A1
·y 4
J50
<<1
+5V Pwr On to 01F-S102 (PA452) r -4V Chk 01N-J54-9 (PA452) ,-
~
, .J.5-1 Com ../(
' 1
«2
,(3
L---
r-:.:!JJ.:.
-4V """ 1 -4V ,(2 Com ,(!3
-{(:5 Com ,(~
-~(."7
01N-
PC50
El
Diskette Control Card
01C-A1 Board (Disk Drive 1)
01 E-A1 Board (Disk Drive 2)
6-PA-46
·;._----------------@--A_-T_B_1_-6~---"-i Jl-3, J2-3, J3-3
~-------'-1 J4-3, J5-3, J6-3 .__;;,,.;___;_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..._, Row E Bus Bar
'--__.;.~---------------------1 RowJBusBar Row N Bus Bar
+5V Pin 003
Row S Bus Bar
._,...-_ _ _.....;;.;;.;;.__ _ _ _ _ _ _ll>-0_1_A_-T_B_1_-1_11'-_0_1_A_-T_B_1_-1_2_ ___.~ Jl _4 , J2-4, JJ-4,
} +8.5V Pin B11
.....__ _ _ _ _.......,......, J4-4, J5-4, J6-4
llP--+---41------0-1A---TB-1---10---"--i J1 -1, J2-1, J3-1
----------'""1 J4-1, J5-1, J6-1
} -5V Pin B06
01A-A1 Board
\---+-+-11>-----VJ-0_1A_-T_B_1_-1_4_ __,,~ J1 -4, J2-4, J3-4
01A-TB1-5
J1-3, J2-3, J3-3
"-..:~---------t--+--------------1 Row E Bus Bar
(-5V Pin B06) (+12V Pin B11)
} +5V Pin 003
L-4-;;;;;;..---------+-+---------------1 RowJBusBar
01 A-Cl Board
8
7 -I I I I
I
I I
I 9 I
+5V
01A-TB2-11
01A-TB2-5
J3-4 (PA440)
-8.SV 01A-TB1-7 To 01G-J3-1
01A-TB2-9
01A-TB2-7
II
+5V +5V +5V
01A-TB1-4
01A-TB2-8 01A-TB2-6 01A-TB2-12
J1-3, J2-3, J3-3 Row E Bus Bar J1-4, J2-4, J3-4
+5V Pin 003 (+8.5V Pin B11)
Jl-1, J2-1, J3-1
(-5V)
C2, E2, G2, J2
(-8.5VPin 007)
01 A-A2 Board
Jl-1, J2-1, J3-1 J1-4, J2-4, J3-4 J1-3, J2-3, J3-3 Row E Bus Bar Row J Bus Bar
(-5V Pin 806) (+8.5V)
} +5V P;n 003
.,
01 A-B2 Board
I 6~~--------~~~~~-0_1A_-_T_B_2-_s_ _ _ _ _ _ _~~J1-4,J2-4,J3-4
I 5
I
To 01G-J3-3 (PA440)
'----------t---41!....._-----------1J1-1, J2-1, J3-1
L.:. """" 01R-TB2-3
01R-TB4-3
To 01G-J3-1 (PA440)
C2, E2, F2, G2, J2
+5V 01R-F3 (PA440)
L
-
-
-
-
-
_
_
;
-
-
-
-
-
-
-
-
-
t
-
-
-
-
+
-
-
-
-
+
-
-
-
-
-
-
-+-51V
J1 -3, Row
J2-3, J3-3 E Bus Bar
'---------------------t---t----t--------""+51V Row J Bus Bar
(~~V~n B11)
(-5V Pin B06) (-8.5V Pin 007)
} +5V Pin 003
01 A-C2 Board
01G-TB8
ls- ..]_
I s
_l
I
I 1 _l
I8 J
I I
01G -W3
r:
I 1 "...", II I2 T
L- .. ...I
I I Ia l
l 1 _l
l2 l
I
I
7
8 .. l
I 6 l
I
, ( ', .....
-·I
s
+..J rv I
I a l1A
L_J
01G -W4
I
I
I
8 -.1.-
I
4 .1
I
_l 3
I
I I
I I
I I
I I
IL7_JI
01R-T82-4
/
""'
DC Return Distribution (Pin DOS)
01A-T81-15
~
I = J1-2, J2-2, J3-2 J4-2, J5-2, J6-2
Bus Bar C
Bus Bar G Bus Bar L
Bus Bar Q
01A-TB1-16
·
01A-A1 Board
J1-2, J2-2, J3-2 Bus Bar C Bus Bar G
01 A-C1 Board
01R-TB4-5 01A-TB2-15
II
J1-2, J2-2, J3-2
· 01A-TB2-16
01A-TB2-2
IJ
~
Bus Bar C 01 A-A2 Board
J1-?, J2-2, J3-2 Bus Bar C Bus Bar G
01 A-B2 Board
~ 01G-J3-7 A-TB2-1 IJ
01R-TB4-4
J1-2, J2-2, J3-2 Bus Bar C Bus Bar G
01 A-C2 Board
---I.I J1-2, J2-2, J3-2 Bus Bar C
01
A-TB2-6
-
-
- ++8-.5-V. -5V
.
.
.1·.=1------::::::.B:--t
J1
-4,
J2-4,
J3-4
01A-TB2-8
...
J1-1,J2-1,J3-1
01A-T82-10
e-:=.1i.11.:=--: ----8.-5-Vi
11
+5V
C2,
E2,
F2,
G2,
J2
(+8.5V Pin 811)
(-5V Pin B06)
f l (-8.5V Pin 007)
.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-+51V
Row Row
J E
Bus Bus
Bar Bar
+5V
01R-TB2-2
01R-TB4-2B 01A-TB2-14 ·
ll+sv
01 R-F2 ~-.--11~----------------------==-.------';;..;;....--';;;.;;;...--; J1-3, J2-3, J3-3
} +5V Pin 003
(PA440)
~----------
D 01A-D2 Board
Figure PA442-2 (Part 2 of 2). 8140 Models BXX DC Distribution
Notes:
B For units with Floating Point feature, this lead ties to
01R-TB4-2.
f l -8.5V is not present in rows G and J if the unit does not have
the Magnetic Tape Adapter.
I I This line is the +5V source for the 01A-CT board if the unit
has floating-point.
I I This board is not present if the unit has the Floating-Point
feature.
01 A-02 Board
I I This line Is not present if the unit has the Floating-Point
feature.
I I This line is not tied to 01A-TB2 if the board includes the
Display and Printer Adapter.
B This line consists of three leads originating in a common
terminal lug on 01A-TB1 or TB2.
I I This line consists of two leads originating Jn a common
terminal lug on 01A-TB2.
REA 06-88481
SY27-2521·3
(PA442 Cont)
5-PA-47
PA443 8101 DC Distribution
I J 01G-TB1
· 1 ·
~
·4 ·
~ 5 -.
c- --6 ....
~
.,.... 9 ..&. ~
-ta. 10 ,,._ ~
c: 11 ,A..
_.ta..
~
12 -4..
~
~
+8.5V
+5V +5V +5V +5V
J3/P3
1)/ 01G-PC1
a 3)/
4)/
-8.5V
-5V
-5V Sense
· DC Com 1
W3 2 ..
II 3.
40
4 ~
s·
W4 6 ~ ...
I I 7 ~~
80
DC Common
SV27-2521-3
REA 06-88481
01G Gate DC Power o·1stri·bution to the 01 A Logic Gate
01A-TB1
J
....., 1 ..- .., ~
-....., 2 ..-..., -...-.._1_.i.._. - -
--- -_......_ ___...i.-- -.,- 3 ,_,.
4
- - i.-- .._.
---......_
-- - --- .,.,.. 5 ..... -.....i,.._
·6 e
· 7 ·
~
· a 8
C10 - ,.._ ......
9
- ---1~
...,..~
~V""'" -- ~ ~
+5V Com +8.5V -5V
J1 (3 B3A01
(2
(4
'< 1
B2E14 B2A14 B3E01
01A-A1 Board
II
L.-.-._.j
..
-8.5V
...... J2D07
J2
+5V
(3 84A01
Com
'(2 B3E14
·
-5V +8.5V +5V Com
J3
"< 1 "< 4
(3
B5E01 B4A14 B5A01
'(2 B4E14
01A-TB2
1
1--
- -~~
c --It 2
- -- -- - ""
I--
3
~
~--1--
.,..,. 4
- ---- - ,._.
l.--/- 5 ..,
I--
· . / a 6
· <i 7
0 8
·9 Ao. ----1i--
c-- _. ~I--
- ... - 10 -
/
+5V Com +8.5V -5V
+5V Com
-5V +8.5V +5V Com
01A-A2 Board
m J1
(3 B3A01
(2 82E14
(4 B2A14
(1
J2
(3 B4A01
'(2
J3
(1
B3E14 B5E01
(4 B4A14
(3 B5A01
"(2 B4E14
+5V Com -5V +8.5V
J1
<3 B3A01
(2 B2E14
(1 B3E01
"< B2A14 4
.... -8.5V
J2007
+5V Com
J2 (3 B4A01 '(2 B3E14
l +5V
Com +8.5V
-5V
J3
"(3
(2
(4
"< 1
B5E01 B4A14 B5A01 B4E14
Figure PA443-1 (Part 1 of 2). 8101 Models A1X, A20, and A23 DC Distribution
5-PA-48
Notes:
D Required when code 9943 or 1503 is inta/led (communication
ports 1-4).
f l Required when code 1504 is installed (communication ports 5-8).
I J For additional wiring to TB1, see PA440.
a For additional wiring to PC1, see PA440, PA453.
I I For additional wiring to 01G-W3, W4, see PA440. I I For additional wiring to 01A-A 1 and A2 boards, use PA453. I I For additional wiring to 01G-PC2, see PA440 and PA453. I I For additional wiring to 01C Disk Drive, see PA453. I J For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6, P15/J15,
and P16/J16, see PA440.
IDJ For additional wiring to P1/J1, see PA453.
mFor additional wiring to P5/J5, see PA440, and PA453.
01G-TB111
DC Distribution to Disk and Diskette Drives
~
DC Common
-. 2 ~~'--~~~--~~~~~~~~~--~------~----------------~--,
IC 3 : ~----------------------------------------,
- - i--.........~~~~~------------~-----------------t-----t--------t"----t---t-~---,
-. 4 ._
-~-12V ............;...;_ _~--~~~--~~~~~--~--~------T-----1t--~--,
~
~
+5V
Diskette
IC 8~ t--....,._~~~~--~~~~~~------------~....
Control
A2
Card
~
~
---+----------+-5V+--<,( D03,J03
+24V ,( D10,J12
-5V
( D11,J13
____ _______ .__ '--~----4....-.....~_ ------~-.CJo"m~"-t"-'-'-( ---DO-B-------
01G-PC1
a
J2/P2
1 ) >.,.._.~+-24_v_.... 2 ) }>--4,_-_s_ v ___.
J6/P6
1 ))>-...+_1_2_v_ _ __ 3 )}>-1-+_24_v_ _ _......, 4..) )+-24V- - - -
J1
<< -12V
1
+12V )~2
See PA453 f,,__...,.-<-,.~ 3
01C-A1 Board Disk DrivelJ
82E1 B1E14
J2
Com
~
r--+--+--------------1r------------1t-<<(1 B3E1
+5V " - - - - - - - - - - + - - - - - - - + - < , ( 2 B2E14
,._---+-----------4-V+--<~~ (3 B3A1
Com
~
1-----------+-----+------------+-<<(4 B2A14
J4
----+---1--------C-o1m-~,<1 85E1
J15/P15
--+--+---------+----+-----+---------+-51V'-<,(2 84E14
PC2
IJ
>. ._-+------------------------ ______ 1 ~>>-1,C_o_m . Com
> --1--------------------------------" 2 ~~....;..;;.;...;___..........
.---+------4_v-+--<<( 3 B5A1
·
-----+-----+--+--+--------Co_m---11-<,(4 ,
B4A14
3)·;~~-4-V----+---1-----------------------------------.. -4V 4))~i-.;...;_--~__.,______________________________________.
JS .._________C_om--it-<,.( 1 86E1
)5 "
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-24 -V-+-<{(2
85A14
Brake
+24V ./.
3 B6A1
See PA453 ~,.___.._~""~ 4
------~-----
Figure PA443-1 (Part 2 of 2). 8101 Models A1X, A20, and A23 DC Distribution
REA 06-88481
SY27-2521-3
I J 01G-TB1
01G-W3 DC Com DC Com
DC Power - Resistor Box
,----01K --1
I TB1
+5V
R2
I
+5V
R4
I
-5V
R3
I
+8.5V
RS
I
+5V
R6
I
+5V
R1
I
I
I
L _
_
_
_
_
I
_J
Note: See PA743 for location.
(PA443)
5-PA-49
I I 01G-TB1
c ~
~
IL ~ .ta.. 5 ..ta..
.-. 6 .A
c,..,.
"W'
+8.5V
--11 9 .-._ta..-. +5V
- -Dll.. 10 ..ta.. +5V
~11Al. +5V
L- -- .-. 12 .4. +SV
a01G-PC1
J3/P3
1 »
3)) 4»
-a.5V -SV
-5V Sense
i-----i
~~
1
I IW3 2 ... 3.
DC Com
40 ......... .............
W6 llJ
,-- 1--i
0 5~ DC Common W4
7. II 5ti..
aQ> ...___
DC Distribution to 01A Gate
-...01A-TB1 1 _..)-" -~
---v .-A_.L. 2 _n.. t-----J
_,,.. 3 .A.
- I"'"-
t--
/ I ~ 4 .A.
- .,,/'1
~ ~
1'1.. 5..ta..
-~
- ll ~
~
~
lJ _La. 9 -.......i
IL -~~
/
..,-_..
10..ta..
-~~
J1
KO +5V 83A01
Com ~< 2 B2E14 +8.5V ~< 4 B2A14
k< -SV ....__1_ B3E01
~~
Jl-a.5V
--
J2007
+5V _&
r'< 3 B4A01
"'< Com
+5V
~
2 83E14
I
I'< 1 B5E01
+8.5V V( 4 B4A14
k< +5V 3 85A01
"< Com
2 B4E14
J3 01A-A111 Board '
01A-TB2
.A. 1 11 ........
l[ ~ ~
- -2 ..A
- - .......~ .-. 3 ,... ~
- 4 1:111.
--1_Jll.o-..
..A. 5 A
- ~I"'
-
~
~ ~
v ,,,,.. 9 ~
[- - ...._.,..,. 10.A ~
- L___.1
01A-A2
Board
B J1
+5V v(
I'' 3
83A01
k< Com 2 B2E14
+8.5V V(
I'< -5V v" . 4 B2A14 1 ~
J2
< +5V~ I' 3
B4A01
Com~ 2 B3E14
J3
-SV k<1 B5E01
+8.SV V(4 B4A14
+5V
Ik<<(2 Com
3 BSA01 B4E14
Figure PA443-2 (Part 1of2). 8101 Model A25 DC Distribution
SY27-2521-3
REA 06-88481
01A-B1
Board
J1 11
k< +5V 3 B3A01
J
Com ~(2 B2E14
-5V +8.5V
~< 1
~(4
83E01 B2A14
~
£:_ J2007 J2 +SV ,...~< 3 B4A01 Com ~ 83E14
J3
+SV V( I'' 3
85E01
I'< Com i.... 2 84A14
+8.5V ~< 4 B5A01 -5V ~< 1 84E14
Notes:
I I Required when code 9943 or 1503 is installed (communie11tion
ports 1-4).
I I Required when code 1504 is installed (communication ports
5-8).
I J For additions/ wiring to TB1, see PA440.
a For additions/ wiring ta PC1, see PA440, PA453.
I I For additions/ wiring ta 01G-W3, W4, see lf'A440. I I For additions/ wiring ta 01A-A 1 and A2 boards,
seePA453.
I I Far additional wiring to 01G-PC2, see PA440, PA463. I J For additional wiring ta Disk Dri'lfl 1, IN PA453.
I J For additional wiring ta Disk Dri'lfl 2, see PA453. ll!J For additional wiring ta W3, see PA440. I J For additional wiring to Pt /Jt, and P5/J6, lflfl PA463. I I For additional wiring to P2/J2, P3/J3, P4/J4, P6/J6, and
P15/J15, 1H PA440.
llJ Present with EC867485 installed.
5.PA-60
01G-TB1
if:Ir--I,I I 11 I ..... I , 10 I
I
~:
I -~I +5V
t:I ·~ 7 I +5V
I I
- ,- I
I
I
I -12V
I
I
.
.
4
-d':
~
I I
3 -_...
-- I
I
2_..r
I
I I
L
.,!.e
I
I
__ _J
DC Common
01 G Gate DC Distribution to Disk Drive Boards
J1
-12v_e.-<-;- B2E1
k<3 +12V]) ( 2 81 E14
k<4 L---
J
J2
r - - - Com
<( -·r-o·v.
I
1
(
1 2
B3E1 B2E14
-4V Com
I ) _l)
L'
(-( -43-
83A1 82A14
01 E-A 1 Board (Disk Drive 2)
Com rJ<J4.1-1 B5E1
ID
+5V I .) ( 2 84E14 -4VI ) (3 B5A1
L'--- Com I ) (4 B4A14
r - - - J5
Com ""(l
-t2:4V] +24V I
~ )
( (
2 3
B6E1 85E14 86A1
kL <_4__
-4V
Com -4V
JJ5522-6-3)
Com -12V
J52-2 J52-5 J50-4
PA440
t---, J5/P5
~~_>_J
~ ..:!?:.LP~ +24V
1) X.1
I I PC1
~~_>J
~-J6~/P,6 +12V
!~ ~ l) (I +24V I +24V
~-~J
l
E~r;~;gs((CIIo-C4omVm
4_)_)1.J -4V
Brake
J1
< -12~-J -1-
+12VIL~~-( -2 1
82E1 81 E14
J2
r,(1"" Com
+5V ~
Com
I } (2
1 )(3
I }(4
L~--
B3E1 B2E14 B3A1 B2A14
J4
Com +5V -4V Com
rJ(~-
I
I
)~ < 2
I ,(3
L~' <-4-
85E1 B4E14
B5A1 B4A1 4
J5
eom_e,---
+24V +24V
II_-)<(~~1
L--
B6E1 85E1 4 B6A1
01C-A1 Board (Disk Drive 1)
II
Figure PA443-2 (Part 2 of 2). 8101 Model A25 DC Distribution
DC Power - Resistor Box (See PA743 For Location)
r---- 01G-TB1 I-I,
~
· 4·
r---- - - - - -0-1K---------,
~--;,-1
I
_____+s_v__l..____<~--......;..l____-oA--..JV.R~2,--~B
I
+5V
2 I
A
R4 B
I
-5V I
3
I
I
+8.5V
4
A
R3 B
A
R5 B
+5V
7
A
R6 B
+5V
8
A
R1 B
6
L ___ _J
01G-W3 ll!J
DC Com DC Com
5
lr---_J
L __ -- -- - - _______J
REA 06-88481
SY27-2521-3
(PA443 Cont)
5-PA-51
SY27-2521-3
REA 06-88481
PA450 Power Logic Interconnections
PA451 8130 Power Logic Interconnections
JS/PB 812 ))
+24V Control
808 ))
» +5V Control
816
IJ » 815
PC1
>.. Common Cathodes
801
Power On
» 804
Disabled Indicator
J
Contains
PCJ Seq CD 806)) Power On Indicator
» Pwr/Thermal Check
805
814)) -Lamp Test
Secure Switch 803))
a 01 F Operator Panel
Main Pwr Sw
Off
On,..,
S1A
0::0-..,,2 I 1
On. -0· I
S1D
Keylock Sw (S5) Pwr Only
Secure 2 ~fc\Enable
0 ~
;l 1
D~
DS2
......,.
DS3
-i::*---
2 1
1 ]
A''X"'
c8o"'
:"XJ:-...,
..... -o
Dcr-o--o
EC1
E 0--0--0
F o--0--0
Go--o--o
Ho--o--0
SW5
Front
L-----...
l
0--0--0 A
0--0--08
o--o-oc
II-- 0--0--0 D
f'-.t'1'. EC2
'"' -0 -CE
o---o-oF _,....G .J"> __,....
z:1::7--f.-.
~H
~
Lu
01A Gate
-POR 2 809))
810)) -POR 3
I
-Seq Complete
A12))
-SCF A Present A13))
J
Square AC A16))
+60-Hz Control A14)/
J
-POR 1 (+Ve)
A15))
A01)/ A10)}
DC Common -Remote Pwr Off
J
J
807)) A09))
+Power Good -Thermal Closed
A05 ),.. A04)) A11),..
DC Common
-Thermal Closed
~
DC Common
?A~
B
J
01G-W6S1 Thermal
II
~
Notes:
D This point connected to ground for lamp test.
t i EC2-G is jumpered to EC2-H if keylock SW is not present. I I For additional wiring to PC1, see PA440 and PA441. I I For additional wiring to 01F BOP, see PA441.
J16
--.< 3 D6C02
~ D6805
J14
~ L6A02 ~ K6E05
J13
G 3 P6C02
~ P6B05
A1 Board
J12
..-'----
,(3 56D02
~(5 56D05
,(6 56C05
L---
J15
1«6 G6C05
II
A
8 "j
~
01A-S1 Thermal
I I For additional wiring to 01A-A 1 board, see PA441. I I For additional wiring to PC2, see PA440, PA441. I I For additional wiring to 01C Disk l!Jrive, see PA441. I I For additional wiring to P1 /J1 and P5/J5, see PA441.
____ .......
II
PC 1 Contains PC3 Seq CD.
J1/P1
» A14
A 13 ))A12)) A11))
A10)) A09 )) A08 )) A07 ))
A06))
-Lamp Test +Power Good +5V Cntl +Contacts Closed +12V Sense +5V Sense +24V Sense DC Com. -POR *
A05 ))-File Fault
A04)) AOJ )) -Sw Off A01)) -POA*
m
PC2
J16/P16
A10)) 803 )/ A11 ))
» 811
806 >>
A09 >) 807 )/ 801 )) AOJ )) A06)} A05)) A01)) 804 >) BOB)) A02 )7
» 809
A12)) 812 ))
-Pwr Good DC Common ·12V Sense
I I Present with EC 321965 installed.
5-PA-52
+Shutdown
DC Com
-S1
v 01 C Disk Drive
Interlock Sw
+Brake Applied K1·2 t (PA411-PA413)
01C-A1
Board
(Disk
Drive)
J1
II
~ ~ 82A1
J5
-F1 B5A14
DC Common T 81-2
-t To 01G-TB1-4
PA452 8140 Power Logic Interconnections
PC1 I I
Contains PC3 Seq CD
J8/P8
I I 01 F Operator Panel
+24V Control 812))
Main Pwr Sw
Keylock Sw (S5)
Off
S1A
808)) 816))
+24V Control +5V Control
OnJ'\ --..) 2 I1
Pwr Only
Power On/Off Switch 815))
» Common Cathodes
801
Power On Disabled Indicator 804),
Power On Indicator
806)>
1./1
» Power/Thermal Check
DS3
805 >-+-~~~~~~~~~~-{)f---
-Lamp Test 814))
l l
Ax_ J....,
cB~.... ..X.., _.;.:.:,
DO--O--O EC1
EO-O-O FO-O--O Go-o--o
~ Secure 2
Enable
Sw5 Front
1 .______
J
O--O--OA 0--0--0 B
o-<>--OC
D----~0
--0-0 EC2
D
~-0-0E
o---0--0 F ~ ~ .,...G
HO---O--O
Secure Switch 803))-
A15)) A12))
-POR 1 (+VE} -Seq Complete
01A Gate
I I A1 Board
A16))>--i1--S_q:.u_a_re__A_C__________________-+--------+-----1 Z1 802
14 z A ))>--i~+_60_-_H_z_C_o_n_tr_o_l________________,1--------1------1 1 002
I I A2 Board
>> el..,~01 A09))>-t--T-h-e-r-m-a-l-C-l-os-e-d----..0A~ G-W6S111J
AOS
DC Common
Thermal
~
l j A04)/,>-It-T·.h-e~rm--a-l-C-l-os-e-d------------------t·-----Ao---.~ 01A-S1
L.---...., A11~ DCCommon
.,.
Thermal
Notes:
I I This point connected to ground for lamp test f l EC2-G is jumpered to EC2-H if keylock SW is not present I J For additional wiring to PC 1, see PA440, PA442
I I For additional wiring to PC2, see PA440, PA442.
I I For additional wiring to 01C Disk Drive, see PA442
Figure PA452-1. 8140 Models AXX Power Logic Interconnections
I I For additional wiring to 01A-A 1, A2 boards, see PA442.
I I For additional Wiring to Op Panel, see PA442.
IJ This pin is:
-Seq Comp
Models
H6A04 (Z3802) A3X,A4X
A6D04 (Z1802) A5X
~
f>C111
Contains PCJ Seq Cd
J1/P1
A14 >) A13 >) A12)) A11))
A10 )).
A-OO >,,,'
A08)) A07))
A06))
-Lamp Test +Power Good +5V Cntl +Contacts Closed +12V Sense +5V Sense +24V Sense DC Com. ·POR
A05 ))A04)) A03)) A01 ))
-File Fault
-Sw Off
-POR *
PC211
J16/P16
» A10))
803 A11 >)
» 811 » 806
A09))
» 807 » 801
AOJ)) A06))
A05)) A01 )' 804 ),,
» 808
A02 )). 809 )) A12)) 812 ~
-Pwr Good DC Common -12V Sense
+Shut Down
DC Com
51
- v 1'
II
01C Disk Drive Interlock Sw
+Brake Applied K1 -2 t (PA411-PA413)
J1
T_L'.'< 2
01 C-A1 Board (Disk Driv~)
II
B2A1
+«J5 1 86A14
DC Common T 81-2
--? To 01G-TB1-4
IJ This pin is:
-POR 1 (V£)
Models
llJ Present with EC 867486 installed.
H6804 (Z3803) A3X, A4X
A6£04 (Z1803) A5X
E6A04 (Z2803) A6X, A7X
lml!J For additional wiring to P1 /J1, see PA442 For additional wiring to P16/J 16, see PA44a
lfJ For additional wiring to P5/J5, see PA440 and PA442.
REA 06-88481
SY27-2521-3
(PA450-PA452)
5-PA-53
SY27-2521-3
REA 06-88481
5-PA-54
II
PC1
Contains PC3 Seq CD.
JS/PS
» 812
To 01N·J51·2 +SV P/ON (PA442) +24V Control
sos»
816~
+24V P/ON +5V Control
815~
801 )""
+5V P/ON Common Cathodes
Power On Disabled lndicatqr(
804~
Power On Indicator 806):,
Power/Thermal Check
805)~
-Lamp Test 814))
Secure Switch 803))
Main Pwr Sw
I I 01 F Operator Panel
~1J
,........
DS2
_,...,.,.,
DS3
l
l
-·x: . B A·~A~y: ~~
Ct,,~ ~
DO-O-O
EC1
Eo-0--0
FO-O-O
~~
SW5
Front '--
J
0-0-0 A 0-0--0 B
D
0-0--0 c
0-0--0 D
..,..._ EC2
~ -0-0 E
-0-0--0 F
-.. ~
AOS)) +24V P/ON --" 01 E/ (PA442) 'K50·1
r -Lamp Test
A03)~
r -0-1A--A1- ,
-Seq Complete
I
I
A 1 12~,»+--------1--- Z1802
I
I
I
I
I
Square AC
I
A16)l~------~--, Z1D04
I I
A14~·~-
A15))
+60-Hz Control -POR 1 (+VE)
I
I
l Z1D02
I
J
- Z1B05
I
I
I
I
r---- 01A-A2 1
I
I I I
I
I
I
~
I
Z1D05
I
Z1805
r -01-A-C-2-,
I
I I I I I I I
Z1D05
A10))~---R~e~m~o~te~~Pw~r-O-f.f....iiI Z1B03
'1 I
l Z1805
L_ - - _...J
I
I
L-----_J
L_ - _J
- 01A-S1
A09))~----T-h-e-r-m-a-l--C-lo-s-e-d-+----------------...·
A
B
-- 01A-S2
B
A
B
DC Common
A11))!>+------------~-+-----------------------------------------.....1
'I"'---_ --
IJ
PC1
Contains PCJ Seq CD.
J1/P1
A14»
A13~ A12~ A11~ A10)~
A09)) AOS)) A07)."
A06)~
A05))
A04~
A03))
A01~
-·Lamp Test
+Power Good +5V Cntl + Contacts Closed +12V Sense +5V Sense +24V Sense DC Com. -POR + Sw Off -File Fault -Sw Off -POR*
Note: Switches shown in
operate (unlocked) position. EC1
Iii'~ ~~~~::::~===-=--=--=--=-=--=--=--=o~t ~)_ "V-V .-------------------....,.~~~t"'I~
n.~~~A-...._ _ _ _ _ _ _ _ _ _ _ _ __
"'B
__
s1
_ _ _ _J16/P16 +Shut·
II
PC2
A,O,.»--,~Dd-oCw..n...,C-om-+-+-+-+-~~-+-+4--1-+-i~---------1-....J _ _ _ _ _ _ ___. B03~»-+------+--+-+-......,a--.t.....6-.+-+~-+-._._
A11)>li>-ll---B11 )>.-------
8 0 6''","", » -- Fi ii-l e- -F l-t - - -
A80097w..»..J..D.-,1-i-.+_-PS-_wO-_-RO_--f_f.._._.._._i~_,_.
0-- o o o E
0
+-5-V--(-0-1-G---T-B-1---S-)...(.P..A,-4"42<)J..0.,
0 0 0
0
6 0
~ F
B01"~"',»·D-C-C-o-m---+-----
A03))»o1..,_-----~~~_,
A06~o....----..._.._~~~
_ __ _ . A05~,>-+-------~,.._.,.._....,.
_ _ _..... A01))~>4------_..--_._.._
r---9 01C-J1-3 (PA442)
B04>lD-+--------.._,.__._.~------'
_ _ _ _ _ ___. BOS»-..--------~.....,.......,
Pw__ A02 ~.,.-___ r_G_o_o_d-+-+-~~----------'
rt01G-TB1-4 (PA442)
-+-,._._.. _ 809~._..,__B _k_O____+-......,a--.t-------------"
A12>:_->-++---..r_.....n,__ 812 »>~~--1_2_v_s_e_n_s_e......-..-.._____________.
P53/J53
J54/P54
620 1~>
U s2 s1 52
01 E Disk Drive
Interlock Switches 01C Disk Drive
Interlock Switches
Notes:
D This point connected to ground for lamp test. f l EC2-G is jumpered to EC2-H if keylock SW is not preSBnt
I J For additional wiring to PC1, see PA440 and PA442.
a For additional wiring to 01 F BOP, see PA442.
I I For additional wiring to PC2, see,PA440 and PA442. d For additional wiring to Pt /J1, see PA442.
IJ Jumper installed with one disk and removed with two.
mJumper installed with two disks.
IJ Remove switch wire from this position and jumper C to D
for second disk drive power without first drive (mainten-
ance only).
+Start VE J12B07 (PA461) Lamp Test
(PA466) Ground
-<< 1
~ 2 (( 3
,< 4
PC51
1 »
-Pick K50
01 E-K50-2 (PA442)
01E-A1 Board (Disk Drive)
J1
--Pwr Good 5 )»)--+------------------~~ 2 B2A1
+Pwr Good
AOS>~
-POR
,< 5
,( 10
--4VChk 01N-J51·3
9 ))·>--+------- (PA442)
J5
+5V Cntl A04))
Sw Off
J12B13 -Sys Off (PA461)
-« 8
-<< 9
,( 6
+Brake Applied
10 »·)--+-------------+-<,( 1
--File Fault 6 ~/·>--+----------.
B5A14
Figure PA452-2. 8140 Models BXX Power Logic Interconnections
PA453 8101 Power Logic Interconnections
PC1
fl
Contains PC3 Seq CD
PC4 Pwr Seq CD
J8/P
812 )) +24V Control
Main Pwr Sw Off
808
»» 816
>-+t24-V-C~on~tro~l ~~~~~~~~~~~~-+-~~~~~O_n~f\
+5V Control
'-J2 I 1
01 F Operator Panel SlA
>> Power On/Off Switch
815
801 )) Common Cathodes
Power On Disabled Indicator
>> 804
(Not Connected)
J.
J
DS2
Power On Indicator
B06 ))
B05 ),~ , Pw~ r/The~ rmal~ Chec~ k ~~-Dt DS3 -
- Lamp Test B14))
Ax
8 ~
X'"'
-0 -0
co ~ -0
DO--O--O
EC1
EO-O--O
FO-O-O
GO--O--O
HO--O--O
l
0--0--0 A
0-0--0 B
0---0--0 c
11--~0
-
--0-
EC2
-
0
D
'-T<>~E
0---0--0 F
_X '-J '"'G
...., ~ ~ H
J9/P9
87 ))--
Local/Remote
lH Sl
Power Switch
O ·
01A Gate
84 B3
),,
)>,'>-1__T;_u:r;.n_-_O.:.n..__
_
02 1'"'r--,----' _____
_
_
_
_ -
-
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
.
.
.
.
.
,
BS ))~~+~5~V~C~tr~l~~~~~~~~~~~~~-l-~~~~~~....~--1r--~~~~~~~~~-,
1I 1
Ill
m 0
Ill 0
0
g
m
N NN
1
Itt
Ill
0 m
~
Ill 0
0
~
!m..,.
!al
Al Board
II
A2 Board
II
~
I I PC1
Contains PCJ Seq CD PC4 Pwr Seq Interface CD
J1/P1
-Lamp Test A14))
+Power Good A13))
» +5V Cntl
A12 +Contacts Closed
A11 )) +12VSense
AlO ))
A09 ), +5V Sense
» +24V Sense
A08
A07 ), DC Com A06 ), -POR
»- A05
>"' File Fault
A04 '/
A03 ), -Sw Off A01 ), -POR*
I J PC2
J16/P16
A10 ),
803 ))
» A11
811 ),,
BOO >,,",'
A09 ),
B07 ),
801 >/
A03 ),
A06 ),
>' A05 '/
» A01
804 ),
808 >'
» A02
809 ),
A12 ),
812 ~
- Pwr Good DC Common - 12V Sense
A09, ~)·/> Th-e- rm-a- l C~lo~se~d~~~~~~-~~~~-r---~-"-I A""~
B~J A11")' />- D. C - C. om.m~o~n~~~~~~~~~~~~--~~~~~'"',....
01A-S1
Thermal
~~~~~~~~~~~~~~~~~~~~~~~~~-
Figure PA453-1. 8101ModelsA1X, A20, and A23 Power Logic Interconnections
REA 06-88481
SY27-2521-3
+Shut Down
DC Com
v
,-,.
II
'-'
01 C Disk Dri11e
Interlock Sw
01C-A1
Board (Disk Drive)
a
Jl
i>< 2 B2A1
+Brake Applied Kl-2 f - - -
(PA411-PA413)
JS
< 1 B5A14
DC Common TB 1·2 ~To 01G-T81-4
Notes:
I I This point connected to ground for lamp tvst · 9 For additional wiring to PCT, see PA440, PA443. I I For additional wiring to PC2, see PA440, PA443.
I I For additional wiring to OTC Disk Drive, see PA443.
I I For additional wiring to 01A·A 1 and A2 board1, 11HJ PA443. I I Contacts are c/oStJd wht1n Dislc Drive heads are un/ocktld
(normal operating condition).
f l For additional wiring to Pt/J1, sse PA443. El For additional wiring to P5/J5, see PA440 and PA443.
(PA452 Cont, PA453)
5-PA-55
SY27-2521-3 This page intentionally left blank.
5-PA-56
J8/P8 +24V Control
B12~
BOS~ +24V Control +5V Control
816 :;:
PC1
B15~ Power On/Off Switch
fl
B01 ~ Common Cathodes
Contains PCJ Seq CD B06~ Power On Indicator
PC4 Pwr Seq CD
» Power/Thermal Check
805
904))
Power On
. Disabled Indicator
(Not Connected) .1
-Lamp Test
814~
J9/P9
01 F Operator Panel
Main Pwr Sw
Off~S1A
On_,..
.J
2 I1
°':~ On_,.. I 1 S1D 21
Power On/Off Switch
DS2
....J'oo.I.
J J D.....S.....3.
-x - A,..
~
B~ j _,,,
C\.- _.. ~
00-0--0
EC1
EO-O-O
FO--O-O
GO-O-O 'Ho-o-o
. O-O-OA ...
<>-0--0 B i!
D 0--0-0 c
~
~o ~ EC2 E
Q.
E
Ill
..J
I
J'\. J'\.
~F
J"t. _,.. ~G
- _A -
\.. - _,H
87~
84~ 83~
0s:t-
Tum-On +5V Ctrl
J Local /Remote
01 H-51 Power Switch
"J""t.?.
c ... 1
01A Gate
J8/P8 -POR 1 (+VE)
A15~
t ~~ ~
- - in
in
0
0
al
0
N
N
~t
..()
-0
al N
A1 Board
IJ
·~~
<J~
0 C) ()
.. . .. in
0 al
in 0
0
~
al
~
~
~
A2 Board
II
.._..... -
01G-W6S1
Thermal
- Thermal Closed A09))
AO~~ DC Common [ -Thermal Closed
A04>} A11)} DC Common
A~
J B " ' ~
~
a-_-:A j 01A-S1
..., Thermal
Figure PA453-2. 8101 Model A25 Power Logic Interconnections
PC50
II
....... - - · J9/P9 A07 >~
-File Fault
P53/J53
Ret
--k2 I
PC1
-f l Contains
PC3 Seq
IA14» -"' Card
A04>~
A 11 )')
A05>, ·Aos>~ A12>~
AOl>" AoS>~
+SwOff
-:f:OR
+Pwr Good #1
1--ln~hsibOit fDfel~
+5V Ctrl
·-~"~"'9S4
~~~~~r160
~ 8
J1/P1 -lamp Test
A13); +Power Good
A12)) A 11 >')
+5V Cntl
~ontacts__9ose~
PC4 Pwr Seq Interface Card
A10)~
AA<0>9f-iL~~,"
A07» AOS)~
+12V Sense +5V Sense +24V::sinse
DC Com. -POR
Aos>> -File Fault
AA0643-~>)"
A01~
~
-~R*
J16/P16
A10~
803>..-
A1u>
811).
BOS
-PC2
II
A09>~
B07>) sou~
jAAoOsJ>>r,.-":
A05>)
A01)}
880Q4s'>)";
.t_O?~~
809)
1Ai2);
1e12>:-
~wr~ood
DC Com
~nse
~ > 3)~ 4Check
J54/P54
PC51
6g5~>>?>-,~....wrGood
10 »
I I 01 E-A1 Board
(Disk Drive 2)
1'J:1'"2 82A1
Ul.....=..,
µ_~
t+8rk Applied JS
J~ :T-f
85A14
-Pick K5~ K50_2 (PA411-PA413)
DC Com +Shutdown
m~ EC1
mrg'X n.A V¢ _.8 ~ 0
~
(.,.
llJ· 0 0 0 E
00 0F
+5V (01G-TB1-8) (PA442) 0 0 OG -0 0 0
DC Com
01C-A1 Board (Disk Drive 1)
J1 I I
~ ~ 82A1
+Brake Applied K1 -2
.,(..PA411-PA413)
~ ~ B5A14
DC Com -12V Sense
..i TB1-2, PA440
-t TO 01G-TB14
Note: Switches shown in operate (unlocked) position.
ob --
_,.,
I~
S2 S1 52
01E Dis k Drive
lnterlock Switches
01 C Disk Drive
Interlock Switches
Notes:
D This point connected to ground for lamp test
fJ For additional wiring to PC1, see PA440, PA443.
I I For additional wiring to 01A, A 1 and A2 boards, see PA443.
a For additional wiring to PC2, Ille PA440, PA443.
I I For additional wiring to 01C Disk, see PA443. I I For additional wiring to 01E Disk, see PA443. I I For additional wiring to PCSO, see PA440. I I Switches shown in operate (unlocked) position.
I J For additional wiring to Pt /J1 and P5/J5, see PA443.
For additional wiring to P16/J16, see PA440.
Im Jumper installed with one disk and removed with two.
mmJumper installed with two disks.
Ill Remove switch wire firom this position and jumper C to D for second disk drive power without first drive (mainte-
nance only).
REA 06-88481
SY27-2521-3
(PA453 Cont)
5-PA-57
PA460 Power Card Assemblies
PA461 PC-1 Power Card Assembly
J10-1 ,..
CR7 v
- CR8
J: J10-3 ., -~ vr
>
~R4
~
J10-2 n..
:;r J10-9 ,.. A_
Jl0-8
CA3 ,,?
R3~
,.,,_ CA4
~
J10-S
J10-7 ,.. V1
- J ,...CR5
J10-4 ...,
J10.0 ..., C1R6
F10
~
F7
~
- F9 ....
:- J J7-1
J7-S
J7-4 ...,
J7-2 "-
:rJ7.0
J7-9
J7-3 ,...
: J J7-11
J7-14
- J7-10 "
J7-13 ..., J7-12 0 .......
J7-15, 60 Hz
-Jumper
J7-8
- J13.0 "' :_J J13-9 ,...
J13-12
: J J13-11
J13-8 J13-4 C> J13-1 C> J13-7 C>
J13-5 0
- J13-2 ,...
- J13-10 ,..
c~
J N
A_
~
~R1
- FB
DC Common
~
J v
C~10
+
c1=t
rr--~ HS1
_JvRl,Li
I 1 ~2IJ
+L..: 1-:..J
~C3
+ c2::j:::
-
l
..i.
cl:;12 } .... J'>I. 12R11
''>>1RS
SY27-2521-3
REA 06-88481
+12
--8.S
+8.S In
+24
-5 DC Common
lf
-SV Sense
+5V Ferro
+12.J'\JS +12"
--...J6-1 +24-0J6-3
-OJ6-4 +12-0J3-2
--8.S -0 J3-1 - 5 -OJ3-3 -S Sense Ret-0 JJ.7
"J3-4
a
.J">J1-A01 J1-A02 >< J1-A03..., J1-A04 0-
J12 (PC4)
El
B11 0
+Sw Off
B12 <>
-Sys Off
006 <>
BOS c-
J1-A05 v
.L"\B09
J1-A06..., -OJ1-A07 -OJ1-A08
1
-OJ1-A09
-OJ1-A10
L
-J1-A11
J1-A12 "-
J1-A13...,
l_
B07<> BOS., B10 n.
010<> 0120 802 0002 0-
013 c-
+POR +5V -POR
DC Com -Unit Power Control +5V Control -Turn On
-0J1-A14
l DC Common
,..BOS
1
;:_004 008_,. ,..804
+24V Control
011 - :001 " - 813
+5V Control
:009 :003
003-0
.J
-File Fault +Sw Off
+ SV Sense -5V Sense
+8.5 IN -SwOff
60 Hz Jumper
12VAC
+5V CTL
-POR* Com
+24V DC lBVAC 18VAC K2
J11(PC3)
G12.J'\ G11: 011
,..._JOS ,.. J07 - G10
61
-POR
G09: J11;
- G07:
B08-0
:GOO : J10 ::_GOB
;::0B0044
::080017
-Set Latch -Sys Off +1.4V Ref -POR·
J13 ..... :G02
:013
1 -,.. G13
.,.,..G04
Jl 008
-0 GOS
OOS~JOB"-JDS
- 009 ,..BOS
B02--...
l
JR51 ~>'R2 ~
Boo: ,,.010
006-0
n.012 :J02 n..G06 :_009
D
D
.......
~
-5 .r. J4-4 +Sin: J4-1
- Com_: J4-3 -0 J4.0
~ J4-2
-5
J2-2
Com: J2-3 ~
+24 -0 J2-1
l
[
l
L
±
I
J"> J9-A07
1'
"
J9-A11
-0 J9-A12
- J9-A10
-0 J5-A09
-0 J9-A08
-_,., J9-AOS
-0 J9-A04 -0 J9-809
--_-.,.,. J9-808
_,, J9-80S
-0 J9-804
1' J9-B07
--_,, J9-B06
1 --..'. J9-803
-0 J9-B12 1 --..'. J9-B01
--,-0......
J9-A06 J9-A02
J'\ J9-A01
+Po-r Good -Seq Complete - PSCF Present ]{iUare AC +60 Hz Control -POR 1 (+Ve)
-Remote Power Off
-POR 2
-0 J9-811
_,, JB-807 (To 01A-P15)
,...
~
J
8
-
A
1
2
,... JB-A13
--,-...... J8-A16
-..... J8-A14
-0 J8-A15
-_,, J8-A10
J'\ JS-809
--... J8-A01
Po-r On/Off Switch +24V Control
-0 JS-BOB
,...
~
J8-A08
-_,, J8-81S
_r. J8-B12
Thermal String
-0 JB-816
-J'\ J8-A09
~ J8-A07
..... J8-A06
1\ J8-A05
J'\ J8-A04
-J'\ J8-A03
--0 J8-A02
J'\ J8-A11
Secure Switch
-0 JB-811 _,., J8-B03
- Common Cathodes
-0 J8-B01
Fault Indicator
.,... JS-805
Power On Disabled Indicator ,--...... JS-804
Po-r On Indicator
_,., JS-806
-lamp Test - - - - 0 JB-814
-POR3
..n J8-B10
Notes:
I This signal used only in 8101. PC-3 installs in J11.
allPC-4 installs in J12 (8101 only}. See PA451-PA453.
A. PC-1 Power Card Diagram
5-PA-58
Jl1i.ii iii Hiii ii1
AO I A03 A05 AO 7 A09 A I I A 13 A02 A04 A06 A08A10 A12 Al4
·
J4
J2
J6
J7
~ F9·4A
R4
~
~
~
R2
·
F10 4A
.
J8
,j . ~ so~ n
j 10
Al6················ 816 ················, .___ _ _ _ _ _ _ A01
kl ~ V1 R1~ R
~01 r - - - - - : : : - - - ,
J9
00'1 ii!
·11 812 ···········
A 12 · · · · · · · · · · · ·
N 7
8
~--=--,--------©:::-=::-
AOl . ( ' \
/
602· ·002
,_,~©
803· ·D03
804· ·D04
BOS· ·DOS
806· ·D06
HS1
B07· ·D07
BOB· ·DOB
809· ·D09
610· ·DIO
811· ·Dll
812· ·D12
813· ·013
Jl 1
G02·
G03· G04·
·J04
GOS· ·JOS
G06· G07·
·J06 ·J07
GOS· ·Joe
G09· GlO·
·J09 ·J10
G11· ·J11
G12· ·J12
G13· ·J13
eJ-d
·
~ r - -
0 802· 803·
·D02 ·D03
804· ·D04
80511 ·D05
80611 ·D06
807· BOS·
·D07 J12 ·DOS
809· ·D09
810· ·010
811· ·D11
0 812· 813·
·012 ·D13
'--- 8---J
~ ~ ~ ~
~
~
Jl3
~
·
B. PC-1 Power Card Assembly Component Layout
Caution: When connecting PS to JS, engage both JS pin rows, or component damage occurs. Notes: 1. See PA650 for fuse specifications. 2. For anv defective PC-1 card component
except fuses, replace the entire card.
J11 (PC-3 Card S o c k e t ) - - - - - J12 (PC-4 Card Socket - 8101 O n l y ) - - - - - - - - - - '
J13~----------------_,
C. PC-1 Power Card Pictorial
REA 06-88481
SY27-2521-3
HS1
(PA460, PA461)
5-PA-59
PA462 PC-2 First-Disk -4 V Regulator and Sensing logic Card
Pins not shown:
J16 601 - GND
J16 603 - GND
J16 604 - +5V
J16 A04 - +5V
J14
Common
1
PC2
-4V Reg
J15
+4V de
-,
c 0--+----4---.
I
80--4-....:._.......
02 I I
Eo--~ L_-_-_ y _ _ _iI
HS3
Common Common -4V -4V
+Loss of .-----Voltage
Voltage Sensing Logic
- File Fault
DC Common
+Disk Drive lntlk Sw + Contacts Closed (K2 Aux NO)
- POR fl
FL
s t----+---t
+5V
DS 4
FL
s
- SW Off
81 l
- POR* IJ
-----1R
- lamp Test
Notes:
D Both AC and DC Voltages on these lines, simultaneously. fJ POR holds power good and file fault inactive until after POR condition.
IaJ
POR ·occurs each time the power cord is connected to the source AC. Voltages are for reference only. Typical value with unit operating properly.
Voltage measured with respect to ground.
A. PC-2 Minus 4-Volt Regulator and Sensing Logic Card Diagram
-PWR Good 609 To 01C P1-2
+PWR Good
SY27-2521-3
REA 06-88481
...........
\(,_{....;::.!_:,\/;\J
DCJ
B. PC-2 Minus 4-Volt Regulator Card Component Layout
J14
SCRl
J15 J16
Notes: 1. See PA650 for fuse specification.
2. For any defective PC-2 card component except fuse F14, replace the entire card.
C. PC-2 Minus ~olt Regulator Card Pictorial
5-PA-60
PA463 PC-3 Power Sequence Card
Pins Not Shown
D09 +24V D03 + 5V J03 + 5V Dll + 5V
1-
DOS GND JOB GND GOB 1.4 Ref
+SW On (on/off) -Sys Off
(Note 6)
1 G13
J10
Voltage Sense
-Fault
+5V
~
-Remote PWR Off
G02
+K lock
805
A
SW Closed
Start ay
A
Time Delay 2 215ms to 430ms
Time Delay 3 5.2 sec to 11.6 sec
Time Delay 1
215 ms to 990ms
-5V
GOS
Thermal String Open
-File Fault
2
I
I
-Lamp Test JOG
Time Delay 4 115ms to 280ms A
-POR (Note 4)
RRl
s Latch (Note 5)
R Relay
FL
Driver -Fault
'----~~~~~~~-!
R
l - G07
Gll D06 005
-SW Off +SW Off K2 Pick (OV) _DC Common (Tl-81
007
-POA1 (+VE) (Note 1)
013
-POR2 (Note 1)
809
-POR3 (Note 1I
GlO
-POR (Note 2)
J02
+Drive PWR
On Ind
012
+Drive PWR On Disable
010
+Drive PWR Thermal Check
G06
-Lamp Test Expand
18V ac
~2
Special
G05 _J_
-PQR·Note 2
18Vac
~
I ~3 ~
ac Power Detect 220.635 ms Delay
! ~
+ 804 ~
+POR"Note 2
_1-2V-6ac..TI=J0013~H~z~~lc'!'I.Ci.r-ucau-1n.tn<g Bgire- ~~- ~~~- ~~- ~r;- ;l~- --- ---- --- ---- ---- --- ---- --- ---- ---- --- ---- --- ---- ---'80,~ 0g74~-~1,~_+- 6_0_HS_zq_uca_ore_- nA~tCr..-ol
Control L _ _ _L_:J _ _ _ _ _ _ _ _ _ _ _ _ _ __J
Notes: 1. Used in system logic. 2. Used only in power system. 3. This circuit will drive OM but not both indicators. The -Drive !'WR/Thermal has priority if both signals are present. 4. Lamp test is degated by -POR. 5. This relay will latch in the set or reset state even if power is down.
6. SeePA461 forJ11 connections.
REA 06-88481
SY27-2521-3
D D
-0-D
-0-D
D
-0-D
DD
-
----
D
Note: For any de'fective PC-3 card component, replace the entire card, (PA462, PA463)
4M2
5-PA-61
SY27-2521-3 This page intentionally left blank.
5-PA-62
PA464 PC-4 8101 Power Sequence Card
+ 5V Control
003
-Turn On
013
- Unit Power Off
802
Ground
DOS
~
I
A .....
I ~
1-- 810 002
812
-1813
012
+ 5V Control - System Off
Ground
-POR
009
+POR
804
+Switch Off
809
+Power Good
005
010
-POR
805
+POR
811
+Switch Off
006
+Power Good
Notes: 1. The PC4 card is used in the 8101 only. 2. For any defective PC-4 card component,
replace the entire card.
A. Logic Flow
D
REA 06-88481
SV27-2521-3
B. Card Pictorial
(PA484)
6-PA-63
PA465 PC-50 Second Disk -4V Regulator Card
Com J50-1
-12V J50-4
ON Circuit
- 5V Sense (Not Used)
U/V Signal Circuit
+SV J51-2
rJ-~-+-~~-4~~~--1
Control
LED Circuit
A. PC-50 Card Logic Flow
J51-1 Com
Ref
SY27-2521-3
REA 06-88481
Pass Device
J52-3
J52-2 -4V
J52-1 -4V
J52-7 No Load Ind
J51-3 U/V Signal
Direction of Air Flow
~
Disk Storage Fault Indicator
Notes: 1. For any defective PC-50 card component except fuse F50, replace the entire card. 2. See PA650 for fuse specifications. 3. The PC-50 regulator assembly for the 8140 Models BXX is the same as for the
8101 Model A25 except that the PC-51 Card and its mounting are removed.
B. PC-50 Card Assembly
5-PA-64
PC-51 Card Mounting (8101 Model A25 Only) PC-51 Card (8101 Model A25 Only) (See PA466 for PC-51 card layout.)
0
DS50
Disk Storage Fault Indicator
@
3
@
2
,@
J52
I:o
C. PC-50 Card Pictorial
0
<>--CJ-<>
o-C:J--<>
BB
o-CJ--o
o-c=J-o
o--CJ--<>
~
~
o-C:=J-o
r-----....,
0 :
: 0
L-----...J
0
Input Voltage Level Gnd
-12V
+5V
Figure PA465-1 shows the PC-50 card signals and voltage levels with the unit powered on and operating properly. Note: When probing VTL voltage levels, use the General Logic Probe (PN 453212) to verify line status; when probing an actual de voltage level, use a voltmeter.
If, after probing these lines:
· Any one input is incorrect, either the voltage source or distribution is the probable cause.
· Multiple inputs are incorrect, either the common voltage source or the PC-50 card is the probable cause.
· Some inputs and outputs are both incorrect, either the voltage input or the PC-50 card is the probable cause.
· One or more outputs are incorrect, PC-50 is probably defective.
If replacing the card does not fix the problem, either the voltage distribution or load could be the probable cause.
Input Line Name
PC-50 Card
DC Common-----~ J50-1
-12V - - - - - - - - 1 J50-4
+5V Ctl - - - - - - - - - 1 J51-2
J51-1 J52-5 J52-6
J52-1 J52-2 J52-3
J51-3
J52-7
Output Line Name
DC Common DC Common DC Common
-4V -4V -4V
Undervoltage
No Load Indication
Output Voltage Level
Gnd Gnd Gnd
-4V -4V -4V
-4V
-4V
Figure PA465-1. PC-50 Card Signals
REA 06-88481
SV27-2521-3
(PA465)
5-PA-66
SY27-2521-3
REA 06-88481
PA466 PC-51 Second-Disk Control Card - Lamp Test
-
,......... OR
vv
-
L_
~
+ Sw Off-. N
............
- Sys Off
-POR +Power Good
Delay
A
r-- 4.5
Sec
Delay ~h 3.5ms
±10%
A i----+
1Disk2
r--
~ OR ~
A
.... Motor Relay ~
r ~
.--- A .....
- Power Check
5.PA-66
Figures PA466-1 and PA466-2 show the PC-51 card signals and voltage levels with the unit powered on and operating properly. Note: When probing VTL voltage levels, use the General Logic Probe (PN 453212) to verify line status,· when probing an actual de voltage level, use a voltmeter. If, after probing these lines:
· Any one input is incorrect, either the voltage source or distribution is the probable cause.
· Multiple inputs are incorrect, either the common voltage source or the PC-51 card is the probable cause.
· Some inputs and outputs are both incorrect, either the voltage input or the PC-51 card is the probable cause.
· One or more outputs are incorrect, PC-51 is probably defective. If replacing the card does not fix the problem either the voltage distribution or load could be the probable cause.
+ Brake Applied
-4V Chk
+ 5V Control
l
Ground
T
A. Logic Flow
.____
A ....
I~
A ....
Driver
- File Fault -Power Good
+Start VE
Input Voltage Level
Input Line Name
PC-51 Card
+VTL Gnd
+VTL +VTL +5Vdc -VTL +VTL
-Lamp Test Ground
-Power On Reset +Power Good + 5V Ctl +Switch Off -Sys Off
J53-2 J53-4 J53-5 J53-10 J53-8 J53-9 J53-6
J53-1
J54-5 J54-6 J54-10
-4Vdc
-4V Check
J54-9
J54-1
Figure PA466-1. 8140 Model BXX PC-51 Card Signals
Output Line Name
+Start VE
-Power Good -File Fault
+Brake Applied -Pick K50
Output Voltage Level
+VTL
-VTL +VTL
-VTL
-VTL
D --~'--'- -
...0..
-
-
10
1 10
I·
I
· I [i \
·I
I
\
J54
J53
Note: For any defective PC-51 card component, replace the entire card.
B. Card Pictorial
I
0551 Brake Applied LED Indicator
Input Voltage Level
+VTL Gnd
+VTL +VTL + 5Vdc -VTL +VTL
Input Line Name
-Lamp Test Gnd
-Power On Reset +Power Good +5V CtI + Switch Off -Sys 0 ff
PC-51 Card
J53-2 J53-4 J53-5 J53-6 J53-8 J53-9 J53-10
Output Line Name
J53-1 ._.,__+Start VE
J54-5 t-- -Power Good J54-6 I-- -File Fault
J54·10 t-- +Brake Applied
-4Vdc
-4VCh eek
J54-9
J54·1 t-- -Pick K50
Figure PA466-2. 8101 Model A25 PC-51 Card Signals
Output Voltage Level
+VTL
-VTL +VTL
-VTL
-VTL
PA500 Adjustment, Removal, and Replacement Information
DANGER With the power cord connected to the wall outlet, line voltage and the +5 and +24 control voltages are always present in all:
· 8130s, 8140 Models AXX, and 8101s. · 8140 Models BXX with the line voltage circuit breaker (CB1) on.
Before removing metal covers or internal power components (except for power control (PC) and logic cards), either (1) disconnect the power cord for all 8130s, 8140 Models AXX, and all 8101s, or (2) turn off CB1 for 8140 Models BXX.
Caution: To remove either power control (PC) or logic cards: 1. Place the operator panel power switch to the Off position. 2. Disconnect 01G-J8 from the PC-1 card.
PA510 +5V DC Adjustment
Before the customer receives the system, the factory adjusts the +5V de level while having all devices connected to the system that use this voltage. As this is the only adjustable de voltage, you should check all +5V de outputs after adding or deleting any feature in the field. You can use your tool bag meter, (IBM PN 1749231 or equivalent) to make this adjustment but, if possible, use a Weston 201 meter for accuracy. Referring to Figure PA510-1, proceed as follows:
1. To measure the +5V, connect the positive meter lead to 01G L1-2 and the negative lead to 01 G W3.
2. A voltage of from +5.15V to +5.25V de is within tolerance and does not need adjustment; if out of tolerance, go to step 3.
Caution: Turn power off before moving the transformer leads.
Note: Changing this +5V adjustment has some effect on other system voltages, but it should not cause an out of tolerance condition.
3. Power off the'machine at the operator panel.
4. Locate the T3 transformer leads marked 55 and 56 on 01G-TB6. Move both leads as necessary to adjust the +5V output according to the following chart. Moving both leads one position changes the +5V output approximately 0.1 V. Adjust as close to 5.20V as possible.
Lead 55
Lead 56
Comments
TB6-1 TB6-1 TB6-1 TB6-1 TB6-2 TB6-3 TB6-4
TB6-4 TB6-3 TB6-2 TB6-1 TB6-1 TB6-1 TB6-1
Minimum voltage level connections Bypasses T3 through common connection Maximum voltage level connections
5. After moving the leads, power up and check the +5V output between each of the following points. All four outputs must be between 4.85V and 5.45V.
+Lead
-Lead
01G TB1-8 01G TB1·9 01G TB1·10 01G TBH 1
01G-W3 01G-W3 01G-W3 01G-W3
6. Check all other machine voltages (PA660).
T2 Move these wires (55 and 56) to adjust T3.
Figure PA510-1. +5V DC Adjustment
REA 06-88481
SY27-2521-3
(PA466 - PA510)
5-PA-67
PA520 LED Removal and Replacement Procedure
SY27-2521-3
REA 06-88481
To replace the light emitting diodes (LEDs) mounted on the 8130/8140 operator panel requires replacing the mounting as well as the diode.
Removal
After turning off power, disconnect the cable to the diode pins. Cut through the diode and mount as close as possible to the metal panel as shown in Figure PA520-1, using diagonal cutting pliers, or equivalent.
Installation
Using new parts, assemble the diode and mount by engaging the two rings of the mount in the panel, one over the other.
5-PA-68
01 F-A1A2-J1
43 1
IC a ·Di
01F-A1A2-J2 20191817.16151413,121110 9 8 7 6 5 4 3 1
~oooooooooooooooooatj
hDS2 (Green) D~{Yellowl e DS3 (Red) Cut
Operator/ Panel
Cut
(+)
~h;teOot
(-)
Figure PA520-1. LED Assembly
Cable Assembly
PA530 BOP Adapter Card Removal and Replacement Procedure
Referring to Figure PA530-1, proceed as follows: 1. Remove the four front cables from the adapter card (locations B2A2, B2A3, B2A4,
and B2A5). 2. Remove the two retaining nuts from the front card and cable connector bracket. 3. Remove the adapter card from the rear card and cable connector bracket with the
front card and cable connector bracket stil I attached. 4. Remove the adapter card from the front card and cable connector. 5. To replace the card, perform the above steps in reverse order.
To 01A-A1 __..., T o T B - 1 - -. . i....
Card/Cable Connector
ToTB-1
_.,
To 01A-A1 ---..
BOPA 01 B-A1A2
figure PA530-1. Basic Operator Panel Adapter Card (01B)
4
To MD
.,4.....__ _ _ To EFP (8140 only, if installed)
4
To BOP
4
To BOP
PA540 How to Gain Access to BOP Components , To replace any operator panel component, you must first gain access to the rear of the panel, as follows: 1. Remove 8130/8140 power plug from the wall or turn off the line voltage circuit breaker (CB1) on 8140 Models BXX.
I DANGER DC voltage is still present at the operator panel with the 8130/8140 power switch in the Power Off position. 2. Open the 8130/8140 front covers and remove the bezel by sliding the two retainer
clips to the rear and lifting the front edge straight up and toward the front of the unit, ensuring that the studs are clear of the retainer clips (Figure PA540-1). 3. Pivot the BOP assembly toward the front of the 8130/8140 to gain access to any of the BOP field-replaceable units.
Bezel
Studs
figure PA540-1. BOP Frame Mounting
BOP Assembly
REA 06-88481
SY27-2521-3
(PA520 - PA540)
5-PA-69
PA550 01G Gate Capacitor and Thermal Replacement Procedure
Replace capacitors on the 01G gate as follows: · If any capacitor C1 through C7 or C12 is defective, replace the capacitor only. · If any capacitor CS through C11 or the 01G gate thermal is defective, replace all
capacitors C8-C11, and the W6 bus bar, which includes the thermal.
SY27-2521-3
REA 06-88481
5-PA-70
PA600 Service Checks
DANGER With the power cord connected to the wall outlet, line voltage and the +6 and +24 control voltages are always present in all:
· 8130s, 8140 Models AXX and 8101s. · 8140 Models BXX with the line voltage circuit breaker (CB1) on.
Before removing metal covers or internal power components (except for power control (PC and logic cards), either (1) disconnect the power cord for all 8130s, 8140 Models AXX, and all 8101s, or (2) turn off CB1 for 8140 Models BXX.
Caution: To remove either power control (PC) or logic cards: 1. Place the operator panel power switch to the Off position. 2. Disconnect 01G-J8 from the PC-1 card.
PA610 AC Ripple Service Check
Use the oscilloscope setups shown below with a Tektronix 453, 454, or similar scope; connect the scope ground lead to 01G TB1-2.
Control
Setting
Channel A sweep mode
Normal
Channel A level
+
Channel A coupling
DC
Channel A slope
+
Channel A source
Internal
Trigger
Auto trig
Mode
Channel 1
Channel 1 volts/div
50 mv*
Channel 1 input
AC
Times per division
0.1 sec
Channel 1 probe
See table below
*Use a X1 probe; adjust the scope for sharp focus.
REA 06-88481
SY27-2521-3
DC Voltage
Maximum Ripple Peak to Peak
. 4
*. 4 *. 4
** · 4
40mv 40mv 150 mv 150 mv
+ 5 + 5 + 5 + 5 * +5 * +5 * +5
100 mv 100 mv 100 mv 100 mv 160mv 150 mv 150 mv
+ 5 Control
200mv
. 5
200mv
+ 8.5
340mv
- 8.5
340mv
+12
960mv
-12
960mv
+24
1920 mv
+24 Control
200 mv
*Present only on 8140 Models BXX **Present only on 8101 Model A25.
Channel 1 Probe
PC-2 J15-3 PC-2 J15·3 PC-50 J52-2 PC-50 J52-2
01G TB1-7 01G TB1-9 01G TB1-10 01GTB1·11 01 R TB2·1 01R TB2·2 01R TB2·3
PC-1 J1A12
01G TB1·1
01G TB1-5
PC-1 J3-1
PC-1 J6·1
01G TB1-4
PC-1 J6-3
PC-1 J9B12
Fused by
01G-F14 01M-F14 01 N-F50 01G-F50
01G-F3 01G-F4 01G-F5 01G-F6 01 R-F1 01 R-F2 01 R·F3
01G-F8
01G·F2
01G-F7
01G·F10
01G-F1
01G-F9
(PA550 - PA610)
5-PA-71
PA620 8130/8140/8101 Indicator Check
The Lamp Test pushbutton provides a quick method to check the 8130/8140 operator panel indicators. You can also check the operation of all system indicators as follows: 1. Perform the procedure in PA540 to gain access to the rear of the panel. 2. On any operator panel, jumper 01 F EC2-e to ground. This should turn on all system
indicators except 0550. (See PA720 for EC2-e location and BU424 for EC2 point-topoint connections). 3. To check 0550, remove fuse F50. The indicator should turn on. 4. Perform the steps in PA540 in reverse order.
PA630 Capacitor Resistance Check
Caution: Check all capacitors for opens or shorts with the power cord disconnected from the wall outlet.
The capacitor (micro)farad rating generally determines both how far and the speed at which your ohmmeter deflects. Capacitors with a numerically large rating generally cause a wide meter needle deflection toward the zero ohms position and a slow return to the infinity position; capacitors with a small rating cause little deflection and rapid return to zero and are, therefore, sometimes difficult to check.
Use your ohmmeter to check capacitors as follows: 1. Isolate the capacitor from the circuit. 2. Short the capacitor terminals with a resistor to discharge it. Generally, capacitors
having a large (micro)farad rating retain a charge longer than those having a low value. 3. Set the meter on the R X 10 scale. 4. Connect the meter leads across the capacitor terminals. (Observe the +and - connec-
tions for polarized capacitors.) The needle should deflect rapidly toward zero ohms and then return slowly to the infinity position.
SY27-2621-3
REA 06-88481
&-PA-72
This page intentionally left blank.
SY27·2621·3
(PM20 - PA830>
l.PA-73
PA640 Tranformer Winding and Diode Service Checks PA641 01G Gate T2 Transformer Winding and Diode Service Check
Perform the following service check: 1. Unplug the power cord. 2. Disconnect the transformer winding leads from the diodes connected to the voltage
in question. See PA410-PA430 AC Power to identify transformer windings and Figure PA641·1 for the location of the diodes. 3. With the meter set to Rx1, verify continuity through the windings. 4. Set the meter to the highest resistance scale and check the diode front·to·back ratio. Exchange any diode that does not have at least a 10: 1 ratio reading. 5. Disconnect the center tap of winding under test. With the meter set to the highest resistance scale, check for an infinite reading between the winding and ground. 6. If a short to ground or open winding is found, exchange the transformer. 7. If no fault is found in the transformer winding at this point, connect the center tap of the winding, but not the leads that go to the diodes. Set the meter to the ac volt scale for the voltage expected for the windings to be checked. Make certain the leads are not touching anything. Connect the meter leads to the wir.ding leads and power up. If power rises momentarily, check the ac voltage. If it was not correct, exchange the transformer.
TB4
Figure PA641-1. 01G Transformer and Diode Locations
SY27-2521-3
REA 06-88481
5-PA-74
PA642 01G Gate Power Supply Diode Isolation
To isolate diodes in the power supply for resistance checks, you should use one of the following procedures:
Procedure
Diodes
A
D5,06,D7,08
B
D2,04
c
01, 03
Procedure A - Diodes 05, 06, 07, 08
1. Power down the unit and unplug the ac power cord.
2. Remove the plastic safety shield covering the CB, C9, and C11 capacitor area (see Figure PA642·1).
3. Remove jumper Bat the W5 bus bar end (Figure PA642· 1).
4. Remove jumper A at the W4 bus bar end (Figure PA642-1 ).
5. Check the diodes using the diode resistance check procedure (PA641 ). Measure between the removed wire ends of jumper A and jumper B. See Notes 1 and 2 below for additional information.
6. If a shorted condition exists, the diodes must be unsoldered from the T3 windings (see PA440) to further isolate the shorted diode or diodes.
7. If an open condition exists, exchange all four diodes. 8. Reinstall the wires and the safety shield removed in the preceding steps after you
have exchanged the defective diodes.
Notes:
1. These diodes are wired in parallel. They can be isolated as a group to check them for a shorted condition. If a shorted condition exists, one or more diodes could be shorted.
2. The only valid open condition that can be found by this procedure is if all diodes in a group are open. -A single open diode cannot be detected with this procedure. To check for a single open diode, remove the wires from each diode. Check each diode for an open condition using the diode resistance check procedure (PA641).
Procedure B - Diodes 02 and 04
1. Power down the unit and unplug the ac power cord. 2. Remove the plastic safety shield covering bus bars W3, W4, and WS (see
Figure PA642·1). 3. Remove wires 16 and 21 at the W3 bus bar. 4. Remove the plastic safety shield covering bus bars W1 and W2 (see Figure PA642-1). 5. Remove wire number 8 from the plus terminal of capacitor C2.
6. Check the diodes using the diode resistance check procedure (PA641 ). Measure between the removed ends of wire numbers 8 and 16. See Notes 1 and 2 below for additional information.
7. If a shorted condition exists, the diodes must be unsoldered from the T2 windings (see PA440) to further isolate the shorted diode or diodes.
01G Gate Power Supply
@
tj;3\ TB1 v:::.J
@ @
12
C!D
PC1
DO
F7 FS
0 0
F9 F10
Wire No. 2 1 - - - - - - + - - - - - - - - - - - -
Jumper A
05
l
08
01G-T2
Note: See PA440 for capacitor polarity.
Rear Service Area
Figure PA642-1. Diode Check Wire Removal
8. Replace diodes only in pairs. 9. Reinstall the wires and the safety shield removed in the preceding steps after you have
exchanged the defective diodes.
Notes: 1. These diodes are wired in parallel. They can be isolated as a group to check them for a
shorted condition. If a shorted condition exists, one or more diodes could be shorted. 2. The only valid open condition that can be found by this procedure is if all diodes in a
group are open. A single open diode cannot be detected with this procedure. To check for a single open diode, remove the wires from each diode. Check each diode for an open condition using the diode resistance check procedure (PA641).
Procedure C - Diodes 01 and 03
1. Power down the unit and remove the ac power cord. 2. Disconnect plug P10 from jack J10 on the PC1 card (PA461 ). 3. Remove the plastic safety shield covering bus bars W3, W4, and W5 (see Figure
PA642·1 ).
4. Remove wire numbers 16 and 21 from the W3 bus bar. 5. Remove the plastic safety shield covering the W1 and W2 bus bars (Figure PA642-1 ).
6. Remove wire number 6 from the plus terminal of capacitor C7. 7. Check the diodes using the diode resistance check procedure (PA641). Measure
between the removed ends of wire numbers 21 and 6. See Notes 1 and 2 below for additional information. 8. If a shorted condition exists, the diodes must be unsoldered from the T2 windings (see PA440) to further isolate the shorted diode or diodes.
9. If an open condition exists, exchange both diodes. 10. Reinstall the wires and the other safety shield removed in the preceding steps after
you have exchanged the defective diodes. 11. Reinstall plug P10 on the PC1 card.
Notes: 1. These diodes are wired in parallel. They can be isolated as a group to check them
for a shorted condition. If a shorted condition exists, one or more diodes could be shorted. 2. The only valid open condition that can be found by this procedure is if all diodes in a group are open. A single open diode cannot be detected with this procedure. To check for a single open diode, remove the wires from each diode. Check each diode for an open condition using the diode resistance check procedure (PA641).
PA643 Transistor 01and02 Check
1. Set a CE VOM to RX1 scale. 2. Put the positive probe on "B" (base); see below. 3. Probe pins E and C (emitter and collector) with the negative probe. Each pin should
read between 10 and 30 ohms. 4. Put the negative probe on B and probe pins E and C with the positive probe. Both
pins should show an infinite reading. 6. Connect one probe on E and the other on C, then reverse the probes; there should be
no reading either way. A low reading means a shorted transistor.
E
REA 06-88481
SY27-2521-3
View From Bottom
(PA640 - PA643)
5-PA-75
PA650 Fuse and Voltage Distribution
SY27-2521-3
REA 06-88481
Isolate power problems by disconnecting the loads from a fuse that opens repeatedly. See Figure PA650-1, PA650-2, PA650-3 or PA650-4 to determine the points to disconnect to isolate all of the loads for that fuse.
Caution: Unplug the power cord before disconnecting or connecting plugs or exchanging cards.
Disconnect the plugs for the voltage distribution to be checked. Power up and verify that the fuse does not open again. If the fuse opens again, a short in the wiring exists. Refer to the wiring diagrams for the voltage path for that fuse. Using your ohmmeter and the diagrams, isolate the short and make the necessary repairs.
If the fuse does not open with all of the loads disconnected, reconnect the plugs one at a time. If the fuse opens, the gate or board for that plug has either a defective card or a short in the board. If the plug connects to a single card, exchange the card. If not, remove all of the cards from the gate and install a new fuse. If the fuse opens again, carefully inspect the board for bent pins, broken or shorted wires, and other external damage. If there are no visual problems, exchange the board.
If the fuse does not open with all of the cards removed, power down, insert one card, and power up. If inserting a card causes the fuse to open, exchange the card. If not, continue until all cards are inserted, one at a time.
Return to the start of the PA MAPs when all of the cards are inserted, all of the loads are reconnected, and the fuse remains good.
5-PA-76
Fuse 01G F1 01G F2
Size 10A 15A
Type ABC ABC
Part No. 511063 596676
01G F3
15A
BAF
115971
01G F4 01G F5 01G F6 01G F7
01G F8
15A 15A 30A
3A
10A
BAF BAF NON AGC
ABC
115971 115971 7389944 855252
511063
01G F9 01G F10 01G F11 01G F12 01G F13 01G F14
4A
4A
0.5A 0.3A
15A BA 4A 2A 4A
MTH
MTH MDL MDL FNM FNM FNM FNM MTH
111257
111257 78999 78998
107670 107668 107665 92734 111257
Voltage ·12 de +8.5 de
+5 de
+5dc +5dc +5dc -8.5 de -5 de
+24 de +12 de 100·127ac 200-240ac 100·127ac 200-240 ac 100-127ac 200-240ac ·4dc
Load
01 C gate (disk)
01A-A1 board 01 A·A2 board 01 B gate (BOPA card) 01 G-PC-1 card
01 B gate (BOPA card) 01 C gate (disk) 01 D gate (diskette) 01F-A1 A2 BOP ind. card 01G-PC-1 card
01 A·A2 board
01 A-A2 board
01A-A1 board
01A-A1 board 01 A-A2 board
01A-A1 board 01 A-A2 board 01 B gate (BOPA card) 01 D gate (diskette) 01 G-PC-1 card
01 C gate (disk) 01 D gate (diskette)
01 C gate (disk)
01 G-T1 transformer
01 G-T2 transformer
01 H and 01 U gate convenience outlets
01 C gate (disk)
Connector (Note) J1 J7,J9,J11 J1 to J6 B1A4 cable P4 B1A3, B1A4cables J2, J4 A2 cable J1 P4 J1,J2,J3 J1 to J6 J1 to J5, J7, J9, J11 J4,J5 U4D07 J7, J9, J11 J1 to J6 B1A3 cable A2 cable
P2, P3, P4 *
J5 A2 cable J1
J2,J4
* -5V source.
Note: The connectors referenced in this column are always located on the gate, board, or card that provides the load. For multiple connectors,disconnect all to isolate the load. See PAlOO for connector locations.
Figure PA650-1. 8130 Fuse Specifications and Voltage Distribution Chart
Fuse
Size
Type
Part No.
Voltage
Load
01G F1
10A
ABC
511063
-12 de
01 C gate (disk)
01G F2
15A
ABC
511063 596676
+8.5 de
01A-A1 board 01 A-A2 board 01 B gate (BOPA card)
01G F3
15A
BAF
115971
+5dc
01 B gate (BOPA card) 01 C gate (disk) 01 D gate (diskette) 01 F-A1A2 BOP ind. card 01F-A1 A3 EFP ind. card 01G-PC-1 card
01G F4
20A
BAF
117252
+5dc
01A-A1 board
01G F5
20A
BAF
117252
+5 de
01A-A1 board
01G F6
30A
NON
7389944
+5dc
01 A-A2 board
01G F7
3A
AGC
855252
-8.5 de
01 A-A2 board
01G FS
10A
ABC
511063
-5dc
01A-A1 board 01 A-A2 board 01 B gate (BOPA card) 01 D gate (diskette) 01G-PC-1 card
01G F9
4A
MTH
111257
+24dc
01 C gate (disk) 01 D gate (diskette)
01G F10
4A
MTH
111257
+12dc
01 C gate (disk)
01G F11
1A 0.5A
MDL MDL
303549 78999
100-127 ac 200-240ac
01 G-T1 transformer
01G F12
15A SA
FNM FNM
107670 107668
100-127 ac 200-240ac
01 G-T2 transformer
01G F13
4A
2A
FNM FNM
107665 92734
100-127 ac 200-240ac
01 H and 01 U gate convenience outlets
01G F14
4A
MTH
111257
-4 de
01 C gate (disk)
* -5V source.
Note: The connectors referenced in this column are always located on the gate, board, or card that provides the load. For multiple connectors, disconnect all to isolate 'the load. See PA700 for connector locations.
Figure PA650-2. 8140 Models AXX Fuse Specifications and Voltage Distribution Chart
Connector (Note) J1 J1,J3 J1,J3 B1A4 cable B1A3, B1A4 cables J2,J4 A2 cable J1 J2 P4 Y2, Y3, Y4 Y2,Y3, Y4 Y2, Y3, Y4 H2 (Models A3X, A4X) J1 J1 B1A3 cable A2 cable P2, P3, P4 * J1 A2 cable J5
J2, J4
Fuse 01G F1
01G F2
Size 10A
15A
Type ABC
ABC
Part No. 511063
596676
Voltage -12 de
+8.5 de
01G F3
15A
BAF
115971
+5 de
01G F4 01G F5 01G F6
20A 20A 30A
8AF BAF
117252 117252 6814327
+5dc +5 de +5 de
Load
01 C gate (disk 1) 01 E gate (disk 2) 01 N-PC-50
01A-A1 board 01 A-A2 board 01 A-82 board 01 A-C2 board 01 A-D2 board 01 B gate (80PA card) 01G-PC-1
01 A-A2 board 018 gate (BOPA card) 01 C gate (disk 1) 01 D gate (diskette) 01 E gate (disk 2) 01F-A1A2 BOP ind. card 01F-A1A3 EFP ind. card 01G-PC-1 card
01 A-B2 board
01 A-Cl board *
01A-A1 board
01G F7 01G FS
3A 10A
AGC ABC
01G F9
4A
MTH
01G F10
4A
MTH
01G F11 01G F12 01G F13 01 L F1 01M F14 01N F50 01R F1 01R F2
01R F3
0.3A 5A 1.6A 1.BA 4A 6A 10A 15A
15A
MDL FNM
MTH ABC
855252
511063
111257
111257
78998 107666 228391 2495467 111257 5214456 511063 5236559 5236559
-8.5dc
-5 de
+24dc
+12 de
208-240ac 208-240 ac 208-240ac 208/240 ac -4dc -4 de +5 de +5dc +5dc
01 A-A2 board 01 A-C2 board * * 01A-D2 board **
01A-A1 board 01 A-C1 board 01 A-A2 board 01 A-82 board 01 A-C2 board 01 A-D2 board 01 B gate (BOPA card) 01 D gate (diskette)
01 C gate (disk 1) 01 D gate (diskette) 01 E gate (disk 2) 01 G-PC-1 card
01A-C1 board 01 C gate (disk 1) 01 E gate (disk 2) 01 G-PC-1 card
01G-T1 transformer
01 G-T2 transformer
01 R-T1 transformer
Convenience outlets
01 C gate (disk 1)
01 E gate (disk 2)
01 A-02 board *
01 A-C2 board
*Board D2 not present and 01 R-F2 provides +5V source for board C1 when floating-point is installed. **8.5V not present if these boards contain display/printer adapter.
Note: The connectors referenced in this column are always located on the gate, board, or card that provides the load. For multiple connectors, disconnect all to isolate the load. See PAlOO for connector loads.
Figure PA650-3. 8140 Models BXX Fuse Specifications and Voltage Distribution Chart
Connector (Note)
J1 J1 P50
J1-J6 J1,J2,J3 J1,J2,J3 J1, J2, J3 J1,J2,J3 B1A4 cable P4
J1-J3, bus bar E B1A3, B1A4 cables J1,J4 A2 cable J1' J4 J1 J2 P4
J1-J3, bus bars E, J
J1-J3, bus bars E, J
J1-J6, bus bars E, J, N, and S
TB2-10 TB2-9 TB2-10
J1-J6 J1-J3 J1-J3 J1-J3 J1-J3 J1-J3 B1A3 cable A2 cable
J5 A2 cable J5 P1
J1-J3 J1 J1 P1
J2, J4
J2,J4
J1,J2,J3 Bus bars E and J
J1,J2,J3 Bus bars E and J
REA 06-88481
SY27-2521-3
(PA650)
5-PA-77
Fuse 01G F1
Size 10A
Type ABC
Part No. 511063
Voltage -12 de
Load
01 C gate (disk 1) 01 E gate (disk 2)
01G F2 01G F3
15A
ABC
(Note 2)
15A
BAF
596676 115971
+8.5 de +5 de
01A-A1 board 01 A-A2 board 01A-B1 board
01 C gate (disk 1) 01 D gate (diskette) 01 E gate (disk 2) 01 G-PC-1 card
01G F4
20A
BAF
117252
+5 de
01A-A1 board
01G F5 01G F6 01G F7
20A 30A 3A
BAF NON AGC
117252 7389944 855252
+5 de +5 de -8.5 de
01A-B1 board
01 A-A2 board
01A-A1 board 01A-B1 board
01G F8
10A
ABC
511063
-5 de
01G F9
4A
MTH
111257
+24 de
01A-A1 board 01 A-A2 board 01A-B1 board 01 D gate (diskette) 01 G-PC-1 card
01 C gate (disk 1) 01 D gate (diskette) 01 E gate (disk 2)
01G F10
4A
MTH
111257
+12dc
01 C gate (disk 1) 01 E gate (disk 2)
01G F11
01GF12
01G F14 01G F50
1A 0.3A
15A SA
4A 6A
MDL MDL
FNM FNM
MTH
303549 78999
107670 107668
111257 5214456
100-127 ac 200-240ac
100-127 ac 200-240ac
-4 de -4 de
01 G-T1 transformer
01 G-T2 transformer
01 C gate (disk 1) 01 E gate (disk 2)
*-5V source **Present for feature codes 1503 or 9943 (communications ports 1-4). ***Present for feature code 1504 (communications ports 5-8).
Notes:
1. The connectors referenced in this column are alwavs located on the gate, board, or card that provides the load. For multiple connectors1disconnect all to isolate the load. See PAlOO for connector locations.
2. Use 10A for Models A25 (PN 511063).
Figure PA650-4. 8101 Fuse Specifications and Voltage Distribution Chart
Connector (Note 1)
J1 J1
J1,J3 J1,J3 J1,J3
J2,J4 A2 cable J2,J4 P4
J1,J2,J3
J1,J2,J3
J1,J2,J3
J2 ** J2 ***
J1,J3 J1,J3 J1,J3 A2 cable P2, P3, P4 *
J5 A2 cable J5
J1 J1
J2_,J4 J2,J4
SY27-2521-3
REA 06-88481
PA660 Voltage Verification
5-PA-78
Use PA661 through PA663 to verify system de voltages, as well as PC card ac reference and de logic voltages. Refer to the point-to-point diagrams in PA41 O-PA430 to verify the ac line voltage.
PA661 System DC Voltage Verification
Use the following chart to verify that all system de voltages are present and within tolerance. See PA710 and PA740 for TB and fuse locations, PA662 for PC-1 pin locations, PA663 for PC-2 pin locations, and PA664 for PC-50 pin locations.
· If a voltage is missing, use the PA MAP.
· If a voltage is present but missing at a gate or board, use PA440 and PA650 to isolate the open circuit.
DC Voltage Range in Volts +Lead
·Lead
Fuse
Sensed
-4 -4** -4* -4**
+5 +5 +5 +5 +5 +5 +5
-3.8 to -4.2 -3.8 to -4.2 -3.8 to -4.2 -3.8 to -4.2
+4.8to +5.5 +4.8to +5.5 +4.8to +5.5 +4.8to +5.5 +4.8 to +5.5 +4.Bto +5.5 +4.Bto +5.5
PC-2 J15-1 PC-2 J15-1 PC-50 J52-6 PC-50 J52-6
01G TB1-7 01G TB1-9 01G TB1-10 01G TB1-11 01 R TB2-1 01 R TB2-2 01 R TB2-3
PC-2 J15-3 PC-2 J15-3 PC-50 J52-2 PC-50 J52-2
01G-F14 01M-F14 01 N-F50 01G-F50
At PC-2 At PC-2 At PC-50 At PC-50
01G W3 01G W3 01GW3 01G W3 01 R TB2-4 01 R TB2-4 01 R TB2-4
01G-F3 01G-F4 01G-F5 01G-F6 01R-F1 01 R-F2 01 R-F3
At PC-2 No No No No No No
+5 Ctl
+4.8to +5.3
PC-1 J1A12 PC-1 J1A07 None
No
-5
-4.6 to -5.6
01G TB1-2 01G TB1-1 01G-F8 At PC-1
+8.5
+7.9 to +9.5
01G TB1-5
01G W3
01G-F2 No
-8.5
-7.9 to -9.3
01G TB1-2
PC-1 J3-1
01G-F7 No
+12
+11.0to +13.2 PC-1 J6-1
01G TB1-2 01G-F10 At PC-1
-12
-11.0 to -13.1 01G W3
01G TB1-4 01G-F1 At PC-1
+24
+22.0 to +26.4 PC-1 J6-3
01G TB1-2 01G-F9 At PC-1
+24 Ctl
+17.0 to +30.0 PC-1 J9812 PC-1 J9B01 None
No
*Present only on 8140 Models BXX. **Present only on 8101 Model A25.
PA662 PC-1 Card AC and DC Voltage Verification The PC-1 card converts certain ac reference voltages into de control and logic voltages, which are fused as indicated. Fuses F7-F10 mount on PC-1, while fuse F11 mounts on the 01 G gate.
Use the following chart and Figure PA662-1 to verify the ac input and de output voltages on the PC-1 card. See also PA461 for a point-to-point diagram, and PA650 for fuse specifications.
AC Input Input Pin DC Output Output Pin(s)
01G Gate Fuse
...
-----
Common J2-3, J4-3, J4-6
*
6V
J7-10 -5V
J2-2, J3-3, J4-4
FB
6V
J7-13
-5V
J2-2, J3-3, J4-4
FB
9.5V
J10-9
-8.5V
J3-1
F7
9.5V
J10-8 -8.5V
J7-4, J10-5
*
10V
J13-6 +5V Ctl
J1A12, J5, J11003, J12D03 F11
10V
J13-9 +5V Ctl
J8B16
F11
...
-----
+5V Ctl
J8B15**
F11
13V
J10-1
+12V
J1A10, J3-2, J5, J6-1
F10
13V
J10-3
+12V
J7-2
*
18V
J13-1
+24V Ctl J7-3, J8B12, J9B12, J13-4 F11
18V
J13-7
+24V Ctl
J13-4
*
---
-----
+24V Ctl J8A08**
F11
---
-----
+24V Ctl J11D09**
F11
---
-----
+24V Ctl J8B08**
F11
...
-----
+24V Ctl J12D11 **
F11
---
-----
+24V Ctl J13-10**
F11
26V
J10-7
+24V
26V
J10-4
+24V
J 1A08, J2-1, J6-3, J6-4
F9
J7-1, J7-5
*
*Not fused **Present only after power sequence completes successfully
·
J11 (PC3 Socket)
J12 (PC4 Socket)
2@s@s®1@ 3[!) 6@) 9@12@
J13
·
Figure PA662-1. PC-1 Connector Locations
Top----
A16 16
F9
D==CJ
A01 801 AO 01
J9 JS
F10
I® ®I J5
b 01@2® 3@) 4@l =>==mc::::JIU J6
F7
D==CJ
FS
D==CJ
J2 A01 A02 · A03 A04 AOIS AOI A07 A08 A08 A10 A11 A12 A13 A14 J1
J3
JlO
J7
J4
·
REA 06-88481
SV27-2521-3
(PA650 Cont - PA662)
5-PA-79
PA663 PC-2 Card DC Voltage Verification 1. Use the following chart and Figure PA663-1 to check the de input voltages on the PC-2 card.
DC Voltage
Common -4 -4 -4 -4 +4
Common -4 sense +5 +5 sense -12 sense +12 sense +24 sense
Input Pin
J14-1 J14-3 J14-4 J14-8 J14-9 J14-7
J16B01 J16A07 J16B04 J16A06 J16B12 J16A05 J16A03
2. Check the output of fuse F14 (-4V) at PC-2 J 15-3 and J15-4.
J15
· 812
801
· ·
·
·
·
·
·
·
·
·
··
··
·
·
·
·
·
·
·
·
·
·
J16
A12
A01
PC-2
Figure PA663-1. PC-2 Connector Locations
SY27-2521-3
REA 06-88481
PA670 Power Status Indicators and Their Meaning
5-PA-80
The following table shows how the 8100 activates and resets its power-related status indicators.
Indicator
Activated By
Reset By
Power On (DS2)
Power /Thermal Check {DS3)
The end of a power-on sequence to indicate successful completion.
· An overvoltage or undervoltage fault.
· A high gate temperature.
Start of power-off sequence.
Turning power off at the operator panel. (see Note)
Power On Disabled (8130/ 8140 only) {DS1)
Disk Storage Power Fault (DS4 on PC-2)
Disk Storage Power Fault {DS50 on PC-50) DS51
· A disk drive interlock switch open .
· Disconnecting and reconnecting ac power after a high temperature power failure, providing the thermal signal is not active when reconnected.
· Disconnecting and reconnecting ac power after a power failure due to an undervoltage or overvoltage fault.
· A power off sequence caused by a program power off signal. This is not a power fault, but the power logic responds as if it were.
· Disconnecting and reconnecting ac power after a disk drive interlock switch opened, providing the switch is not still open when reconnected.
· The keylock switch in the Secure position with power off.
· A disk storage-related undervoltage or overvoltage fault on the first disk drive.
· Drive interlock switch open on either the first or second disk drive.
A -4V or ·12V undervoltage condition on the second disk drive.
Brake Applied signal present at the second disk drive.
Turning power off at the operator panel and turning the keylock switch (if installed) to either Enable or Power Only. (see Note)
Turning power off at the operator panel. (see Note)
Turning power off at the operator panel. (see Note) Turning power off at the operator panel. (see Note)
Note: The indicator cannot be reset if either the thermal or the disk drive interlock switches remain open.
PA680 8140 Model BXX DC Parallel Wiring Check
Certain logic voltages in 8140 Models BXX have parallel wires used for voltage distribution. All loads, therefore, must be disconnected to check wiring continuity for these models.
Other than an open or shorted wire, noise or low-voltage problems in the de parallel wiring can also cause a machine failure: · Noise can be caused by bad connections, loose screws, or defective components.
Note: You cannot disconnect the load to troubleshoot noise problems that occur in circuits having parallel wiring. Disconnecting a good line from a noisy one gives a false error indication because either (1) the additional current through a defective connection can temporarily eliminate the noise or (2) the voltage drop exceeds allowable limits and causes a machine failure.
· Low voltage can be caused by one broken wire or one bad connection.
REA 06-88481
SY27-2521-3
(PA663 - PA680)
5-PA-81
SY27-2521-3 This page intentionally left blank.
5-PA-82
PA700 Locations
PA710 Gate and Other Subassembly Locations PA711 8130 Gate and Other Subassembly locations
01D Diskette Drive
Front View
Adapter Card I!
Gate Thermal 01 A Logic Gate 01A Gate Fan
01G Power Supply
\
01A TB2
01 T Gate (see PA7311
Rear View
REA 06-88481
SY27-2521-3
(PA700 - PA711)
5-PA-83
PA712 8140 Gate and Other Subassembly Locations
SY27-2521-3
REA 06-88481
Disk Storage Fault Indicator 054
5-PA-84
Front View Figure PA712-1. 8140 Models AXX Gate and Other Subassembly Locations
Rear View
01T Gate (see PA732)
01U Convenience Outlet
~
\ \
~;;.
" ',.
~
Disk No. 2 (and K50) 01E Gate (See Part 2)
Operator Panel and Adapter
Diskette 01D
+5V Power Supply 01 R Gate (See Part 2)
PC-2, PC-50, and PC-51 (See Part 3)
View From 01GGate
Rear
of ~
-- - ..,,.,--
/ /
"""""' ' '
/
\
(8140 BXX Only)
-..........;
I
I
TBB
\ l
\
I
\
I
' " -- \
a
I
' - ""-
/
/
.,/
Disk No. 1 01C Gate (See Part 2)
Front Cover Fan (B1-J1) (not shown)
-4V Power Supply and Controls 01 Mand 01 N Gate (See Part 3)
and Convenience Outlet Transformer 01L (See Part 3)
Convenience Outlet (See Part 4)
Figure PA712-2 (Part 1 of 4). 8140 Models BXX Gate and Other Subassembly Locations
REA 06-88481
SY27-2521·3
(PA712)
5-PA-85
Disk 2 01E Gate or Disk 1 01C Gate
K50 (On Disk 2 Only, see Part 4)
Al Board and Cables
SY27-2621-3
REA 06-88481
+5V Power Supply 01R Gate
01R-R1 01 R-R3 01 R-R2
01 R-TB1
I
I
I
I
I
I
~ "'-. ' '
Logic Fan AC Disconnect
Disk Motor Thermal Reset (location depends on motor type)
Figure PA712-2 (Part 2 of 4). 8140 Models BXX Gate and Other Subassembly Locations
01 R-F1 01 R-F2 01 R-F3
01 R-TB3
5-PA-86
01 R-TB4
0 0 0 0 0 0 0 0
AC Distribution Connectors and Convenience Outlet Transformer 01-L Gate
,
01L-f1 01H
Figure PA712-2 {Part 3 of 4). 8140 Models BXX Gate and Other Subassembly Locations
Disk 1 and 2 -4V Power Supply and Controls 01M and 01N Gate
02 and HS3
F14~ ~ J14 1
lo J1s 1
· 1001·
J16 oA12
·
Q054
Disk Storage 1 Fault Indicator
·o D D f 50 J50
1 0
0$50
3CJ J51 0
01 and
1 0
Disk Storage 2
52 ~J Fault Indicator
HS50
1
PC2 Card
Card
C13
Disk Storage 1
-4V Power Supply
and Controls
QD DS51
Brake AInpdpicliaetdor -
PC51 Card
~3
O~
12 L.....- - - - - - - - - - storaoe 2
D J54 12
-4V Power Supply and
Controls
01M
01N
REA 06-88481
SY27-2521-3
(PA712 Cont)
5-PA-87
Logic Gate - 01A Gate
S2 (Pin Side)
S1
02
CJ
Cl
Cl
J
c
C1
0 D
D
J
c
C2 Cl
CJ
D
J
c
A1
J4
J1
D
D
JS
J2
D
D
J6
J3
Cl
D
S 0 NL J G EC
82 CJ
CJ
CJ
J
c
A2
J2
D
J3 D
E c
TB1 12
SV27-2521-3
REA 06-88481
01 H - Convenience Outlet
Silver Terminal
1
0
2
0
Board J Connector Numbering (as plugged)
01 R - Line Voltage Circuit Breaker (CB1)
1A0 2A0
l
]
180 280
K50 Relay
6
5
2
5-PA-88
CR50
Figure PA712-2 (Part 4 of 4). 8140 Models BXX Gate and Other Subassembly Locations
PA713 8101 Gate and Other Subassembly Locations
01 H-81
Front View
Figure PA713-1. 8101 Models A1X, A20, and A23 Gate and Other Subassembly Locations
01A Gate Fans
REA 06-88481
SY27-2521-3
(PA712 Cont. PA713)
PC51 Car~
SY27-2521-3
REA 06-88481
01H-S1
· '
Front Cover Fan
01 E Gate Note: Partial detail only. Disk storage 2 is physically identical to disk storage 1.
Note: The second disk uses the PC-50 and PC-51 cards.
Figure PA713-2. 8101 Model A25 Gate and Other Subassembly Locations
5-PA-90
PA720 Operator Panel Component Locations PA721 8130/8140 Basic Operator Panel Locations
Power ON/OFF Switch DS1
!Ill 3 2
01F-A1A2-J2
BOP Keypad Assembly
Keylock Switch
POS 1
POS2
Front
Rear
01F.J3
REA 06-88481
SY27-2521-3
(PA713 Cont - PA721)
5-PA-91
PA122 8140 Expanded Function Operator Panel locations
DS3
SV27-2521-3
REA 06-88481
01F-A1A2-J1
01F-A1A2-J2
20
1
loco o o o o o o o o o o o o o o o · o I
Keylock Switch
POS 1
POS 2
Front
POS 1
Rear
BOP Keypad Assembly
lo·ooooool
1
8
EFP
Keypad Assembly
01F-A1A1-J1
,
16
10·000000000000001
01 F-A tA 1-J2
1~4
D · I.ft......----~ 0 0
3
12
I o · o o o a o o o ol
3
12
I a · o o a o a a o ol
01F-J1
5-PA-92.
PA723 8101 Operator Panel Locations
DS1
!DJ
a::n
3 2
01!=-A1A2-J1
4.,._1
(JL[K:Qj
01F-A1A2-J2
~
1
ccaaaaoaoooooooooa·o
PA730 01T Gate (1/0 Panel) Locations PA731 8130 01T Gate Locations
A
Pin
A= Integrated modem transmit and operational switches (U.S./Canada). Switch positions 7 and 8 are not used.
B = Not used by the 8130.
C = Communications connectors. D = For second lobe -
loop port number has 'XA' designation. E = Connectors for cables to 8101 and 8809.
REA 06-88481
SV27-2521-3
01T
(PA722 - PA731)
5-PA-93
PA732 8140 01T Gate locations
~~ A ~~
~~·~
7 Q)
B
Pin
SV27-2521-3
REA 06-88481
01G Gate
5-PA-94
A = Integrated modem transmit
and operational switches
(U.S./Canada)
B = Not used by 8140.
C = Communications connectors.
D = SSCF bus tailgate
E = Connectors for cables to
8101 and 8809.
1A-2A = For second lobe -
loop port number has
on
'XA' designation.
Figure PA732-1. 8140 Models AXX 01T 1/0 Panel Locations
01T Area Figure PA732-2. 8140 Models BXX 01T 1/0 Panel Locations
PA733 8101 OTT Gate Locations
A
Pin
A = Integrated modem transmit and operational switches (U.S./Canad1)
B · Communications second lobe loop connectors.
C · Communications connectors D · SSCF bus tailgate E · Connectors for cables to
8101 and 8809. 1-4A · For second lobe 5-8A loop pon number has
'XA' desi1111ation.
REA 06-88481
SY27-2521-3
(PA732, PA733)
5-PA-95
PA740 01 G Gate Power Supply Component Locations
PA741 8130 01G Gate Power Supply Component Locations
01G
G 1
e e
TBI
8 G
~
~
PCI
DO
F7 FB
0 0
F9 FIO
Note 1 Note 2
SY27-2521-3
REA 06-88481
Resistor Chart
Name
Resistance
Watt
R1
100 ohms
25
R2
10 ohms
50
R3
5 ohms*
50
R4
2ohms
50
R5
2ohms
50
R6**
5ohms
50
*30 ohms for 768K and 1024K stora9e. (PN 5724118) **Disconnected for 768K and 1024K storage.
09
8DJ 888
HS2
G
T2
Rear Service Area
Note 1: PC-3 plugs into PC-1. Note 2: See PA440 for capacitor polarity and PA650- for fuse specifications.
01G
D
F14
PC2
DS4
0
CIJ
Operate
[ Lock.
Front Service Area
/ 01H 0 JI
0 0
~
See Resistor Chart
5-PA-96
05 06 07 08
PA742 8140 01G Gate Power Supply Component Locations
01G
R7
e
@) TB1
e
e
12
~
PC1
OD
F7 FB
0 D
F9 F10
Note 1 Note 2
g..L-L---1-.1.~ "~Sl Ol
6
5 6
04
G[]J GGG
HS2
B
r-----------.,
T2
I
01 L Gate
I
I
I
8140 Model BXX
I
only
I I
See Fig. PA712-2.
I
00
R_ear Service Area
01U-J1
Note 1: PC-3 plugs into PC-1.
Note 2: See PA440 for capacitor polarity and PA650 for fuse specifications.
Note 3: PrflSent with EC 867486 (8140 AXX) or EC 862250 (8140 BXX) installed.
Name
R1 R2 R3 R4 R5 R6
Resistor Chart
Resistance
100 ohms 10 ohms 5 ohms 2ohms 2ohms 5ohms
Watt
25 50 50 50 50 50
Front Service Area
01G
121 D F14 PC2 DS4 0 C13
Operate
/,
0 J1
B
~
[ Lock
8140 Model AXX only. See PA712 for more detailed 8140 Model BXX locations.
REA 06-88481
SY27-2521-3
See Resistor Chart
05
06
07 08
(PA740 - PA742)
5-PA-97
PA743 8101 01G Gate Power Supply Component Locations
01G
ee TBI
e e
12
~
PCI
OD
F7 F8
D D
F9 FIO Note 1 Note 2
88
T2
OIHTB1
Rear Service Area Note 1: PC-3 and PC-4 plug into PC-1. Note 2: See PA440 for capacitor polarity and PA650 for fuse specifications.
Note 3: Present only on Model A25 with EC 867485 installed.
01G-PC 51 DS51Q
3,1.
2.
J53 ~
1121:'
2i
3.
. J54 : 11: 12·
View B-B
40 J50
1 0
3LfiJl J51
DS50
0
01 and HS50
Model A25
8
SY27-2521-3
REA 06-88481
Name
R1 R2 R3 R4 R5 R6
Resistor Chart 1
Resistance
100 ohms 10 ohms 5 ohms 2ohms 2ohms 5ohms
Watt
25 50 50 50 50 50
DOIG
HS3 (Rear View)
D
F14
PC2 DS4
0
C13
Operate
[ Lock Front Service Area
See Resistor Chart 2
_:_;_~_~-C-5-1..15
,,:"-
PC2
~A
I I
l.A
01H
S1 Jb
Front Service Area Model A25
CR50
View AA
Name
R1 R2 R3 R4 R5 R6
Resistor Chart 2
Resistance
2 ohms 1 ohm 15 ohms 1 ohm 8ohms 2 ohms
Watt
25 50 10 50 25 25
5-PA-98
05 06 07 08
This page intentionally left blank.
SY27 -2521-3
(PA743)
5-PA-99
PA750 Board DC Voltage Distribution PA151 8130 Board Voltages
8130 A1 Board Pin Side
SY27-2521-3
REA 06-88481
· ·
· ·
Y6
· ·
·~· · J1 · a
·· ··
Y5
·~· · ~2 ·
Y4
· · ·· ·· ·· ··
·~· · ~3 ·
·· ··
Y3
· ·
·~· · J4 · ao
·· ··
Y2
· ·
·~· J5
··ED··C··B··A··Y·E·1D··C··B··A···E·D··1
11 13
0
·· ··
· ·
· ·
D B
· ·2
(II ·
v
2
u
T
2
2
s
2
R
a
001
2
2
p 2
N 2
M 2
L 2
K 2
J 2
H
2
G 2
F 2
E 2
D 2
c
2
.' B
··A··
2 1:·2t··
· · · ·
v
· · · ·
· · · ·
· · · ·
· ·
· ·
· ·
· ·
· · · ·
· · · ·
· · · ·
· ·
· · · ·
· · · ·
· ·
· ·
· · · ·
· · · ·
· · · ·
· · · ·
."I ·1A · · · ·13
·· · .n
c
·J G
lil ·
·····A··e
3
· · · ·
v
4
· ·
· · · ·
· ·
· · · ·
· ·
· · · ·
· ·
·· ·· ·· ··
001
·· ··
· · · ·
· ·
· ·
· ·
· ·
· · · ·
· ·
· · · ·
· ·
· · · ·
· '!t
· · · ·
· ·
· · · ·
· ·
· · · ·
· ·
· · · ·
· ·
· · · ·
· ·
· · · ·
· ·
&·· 3···
·· ·
·· ··
:1a: .al · ·
: Ip M
· ·· ·A·
· ·
'·:··41··>
· ·[6J11 .,
· ·
v
5
· · ·
6 ·
·· ·· · · ·· ·· ·· ·· · ·
·~· ·~· · · · · · · · · · · · · ·
Z6
·. J12 m· l
Z5
J13
· 00.
· ·
Z4
·· ··
·~· · · · · J14
·mo·
· ·
· ·
Z3
·· ··
·~· · · · ·
· 00.
· ·
· ·
Z2
· · ·
· ·
·
· · ·
· a
u ·
s
· ·
=Ai
'. · · · · · · · · ·····5·~··· ············ 2 ·~ · mo ······Z·1····· 6 4
Voltage Symbols
··l:i Ground +8,5V
a -5V +5V
0 -8.SV
Note: Voltages present in all card rows A through V.
Special Voltage Pins 02007 04007 -24V
Input Signal Pins
I I POR 2 I I POR 3 I I -POR1 (+VE)
I I Seq Complete
I I SC1 Present I I Square AC fJ +60 Hz Control
El POR 1 II DCCommon IDJ Remote Power Off
5-PA-100
8130 A2 Board Pin Side
··-------Y-6-------·.
·-------· ·----Y5--- ·
··-------Y-4------··
··--------Y3------··
·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ··
v
u
T
s
R
a
p
N
M
L
K
J
H
2
2
2
2
2
2
2
2
2
2
2
2
2
B·· · · · · · · · · · · · · · · · · · · · · · · ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· v
··--------Y--2 ----··
·· ·· ··
G
F
E
2
2
·· ·· ··
·· ·· ··
EDCBAEDCBAED
· · · · · · · · · · · · 11
Y1
1
· ·· · ··· · ·· ·· 13
· ·
· ·
· ·
D B ·· 2
D
c
B I··IA···
.'1·2··
2
2
2
:+ · ·
··ee · ·
· ··
· ·13
J2 a
3
.. ~ ~ ··
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· ·
· ·
· · · ·
· ·
· ·
· · · ·
· · · ·
v
007
Voltage Symbols
fl Ground
$ +8.5V
· -5V
C +5V
Note: Voltages present in all card rows A through V.
Special Voltage Pin U4007 -8.5V
4
~ ~ · · · · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· ·
· ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· ·
· ·
· · · ·
v
5
·-------· .. .. · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
6 · -----Z6 --·
··--------Z5--
-
-
-
-
·
·
·
·
------Z--4 ------
·
·
-------
- - - -Z3- - -
·
·
--------Z--2
-
-
-
-
·
·
············ 2 ······Z·1····· 6 4
REA 06-88481
SY27-2521-3
(PA750, PA751,
5-PA-101
PA752 8140 Board Voltages
SY27·2521-3
REA 06-88481
8140 A1 Board Pin Side
·-------·
·----Y6 ---·
··--------Y5------··
··--------Y4------··
·· ·· ·· · · ·· ·· ·· ·· ·· ··
v
u
T
s
R
Q
p
N
M
L
2
2
2
2
2
2
2
2
2
2
·· ·· ·· · · ·· ·· · · ·· ·· ·· ·· ·· ·· · · ·· ·· ·· ·· ··
v
3
·· · · ·· · · ·· ·· · · ·· · · ·· ·· ·· ·· · · ·· ·· · · ·· · · ··
v
4
·· ·· ·· · · ·· ·· · · ·· ·· ·· ·· ·· ·· · · ·· ·· ·· ·· ·· ··
·· -- -- --- -Y3 ------··
·· · ·
K
J
2
2
2
·· ·· ·· ·· ·· ··
·· · · ·· ·· ·· ··
· · · · · '!' ·· ·· ··
··--------Y2------··
·· ·· ··
G
F
E
2
2
2
·· ·· ··
·· ·· ··
·· ·· ·· · · ·· ··
· · ·· ·· ·· ·· ··
EDCBAEDCBAED
· · · · · · · · · · · · 11
Y1
1
············ 13
· ·
D 2
· · · ·
· ·
· ·
c
· ·
8
C0···lAl ····82
' 2
2 &:··2···
. ;: !1 ·
· ·
·1~ ·
·
.JI .~I · ·
&[··········!)A3®Ge·········
· ·
· ·
· ·
·p M·
l:··!lAI···
· · · ·
· ·
·1~
·
· J
2
~I
·
A·····4(·····i)
u s
v
5
·· ·· ·· · · · · ·· · · · · · ·· ·· · · ·· · · ·· ·· ·· ·· · ·
· -------· 6 · ----Z6---·
·
·
-
-
-
-Z'5
· ·
· -------·
Z4
·
·
. · ----Z3--- ·
·-------·
········e··
Z2
Z1
6
· ---~---_-_-_-_-_-__· _____·_·_· ····· ·~4
II D
Voltage Symbols
A Ground
® +8.5V
· -5V Q +5V
Note: Voltages present in all card rows A through V.
Input Signal Pins
D A6004 fJI A6002 II A6E04
+50/60 Hz +60 Hz Ctl -Power Off to PS
5-PA-102
8140
A2 Board
Pin Side
r--:::::::::.._______ B---B-----------------------------------------------------------------------0-------------------------------------
·-------· . . . . ·--------· -------- ----------. --------.
EOCBAEOCBAEO
· · · · · · · · · · · · 11
. . . . . ·-------· v---Y-6---· ·----Y5---
----Y4----
----Y3---
Y2
Y1
0 · ·· · ··· · ·· ·· 13
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
0 B · ·2
v
2
· ·
· ·
v
3
· ·
u
2
· · · ·
· ·
T 2
· · · ·
· ·
s
2
· · · ·
· ·
R 2
· · · ·
· ·
Q 2
· ·
· ·
· ·
P
2
· · · ·
· ·
N
2
· · · ·
· ·
M
2
· · · ·
· ·
L 007 K
2
2
·· ·· · ·
·· ··
J 007 H
G 007 F
E
2
;2
2
2
2
·· ·· ·· ·· ··
·· ·· ·· ·· ··
·· ·· ·· ·· ··
D 2
· · · ·
· ·
c
B I··llA···
·.2'· 2
2 :·· <··f
· ; :1 ·
·1~ ·
.J1
.~I
(···!)A····
··· · · · · &······Je·····
·· ·· ·· · · ·· ·· · · ·· · · ·· ·· · · ·· · · · · ·· · · ·· · ·
v
4
Voltage Symbols A Ground Ci) +8.5V
· -5V
0 +5V
Note: Voltages present in all card rows A through V.
Special Voltage Pins
F2007} H2007 -8.5V K2007
Input Signal Pins
I I H6A04 -Pwr Seq Complete (Models A3X, A4X)
· H6B04
II A6004 D A6E04
-POR1 (+VE) (Models A3X, A4X) -Pwr Seq Complete (Models ASX) -POR1 (+VE) (Models ASX)
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· · · ·
· ·
· ·
· · · ·
· ·
· ·
· · · ·
· · · ·
· · · ·
· · · ·
· ·
· ·
· · · ·
· · · ·
· · · ·
··· ~ ·· ~·
us
·[i ··
v
5
·A··e·5A·:·e
it
.·-------·. . . · - p · - · · · · · · · · · · · · · · · · · · · · · · · · · ·
6
·
·
------------
--
· ·
-----Z-5 ---
· --------Z4------·
· ------- · Z3
'--===~------~--------------~~---------------------"""":::'~=======-=
· · ·· ·· ·· ·· · · ··
n · - - - - - - - ·
e · · · · · · · · · · · · 2
~
··········~~4
s\=~=t\_______________(\
)\ .
fl
II
11 II
REA 06-88481
SV27-2521-3
(PA752)
5-PA-103
PA153 8101 Board Voltages
8101 A 1 or 81 Board Pin Side
, ·
·
-
-
-
-
--Y3-
-
-
· ·
·-------·
·----Y-2 --·
·E·O·C·B·A·E·D·C·B·A·E·D 11 ······Y·1 ····· 1 13
' · ·
· ·
· ·
· ·
· ·
· ·
· · ··
· ·
D B ·· 2
K
J
H
G
F
E
0 c B :A:,
2
2
2
2
2
2
2
2
2 1:·2.:·.
· · · · · · · · · · · · · · · · rl:--'--?st·' ·· 13
·· ·· ·· ··
' '·:·· ·'·· &:··K3i:.··i
~
· ·
.··.
· · ·
· ·
· ·
~·· ®··
· :·
·· · · ·
L··IJ ®·· · ·
·· · · ·· · ·
· ·
· · · ·
· ·
· · · ·
· ·
· · · ·
· · ~ · ·JG · ·
' ····A:··
·· ··
·3.t..
.. ~:: · ·
· ·· rel
·· ~
K
(·:I ~··
4
·· ··
't:K:'
i·s+:·
· ·
· · · ·
· · · ·
· ·
· ·
· · ·
· ·
·
·
·
·
1·6-..·
·
3
J.
c011ut·····4.·:s···
' ::AA
:·5+·
6···--·------Z3--------··
·
···----· --·--Z--2·--·----···
·
· ·
·· · ··
·· · ··
··Z··1
· ·
· ·
SY27-2521-3
REA 06-88481
8101 A2 Board Pin Side
Vohage Symbols C::,. Ground
@ +8.5V
· -5V
0 +5V
Note: Voltages present in all card rows A through K.
Special Voltage Pins
J2D07 } G2007 E2007
C2D07
-8.5V
Input Signal Pins (A1 board only)
II 86804 -POR1 (+VE) fJ 86802 +5V Ctl II 86A04 - Turn-On Power
fl
·--------· ·-----Y3---·
·-------· ·----Y-2 --.
··E D1 C··B·AE··D·C·BA·E·,·D 11 · ·····v·1 ····· 1 13
': · · · ·
· ·
· ·
· ·
· ·
· · ·· ··
D B ·· 2
K
J
H
G
F
E
D c B :A,
1:
2
· · · ·
K
3
2
· · · ·
· ·
· ·
.2
· ·
· ·
2
· ·
· ·
2
· ·
· ·
2
· · · ·
2 2 :·2r1·i
· ·
·
·
·
6·1.. -·!!"J··1-·C®-~IJ····AG····· 13
' ··· ·
··:·3®·
.. · · · · · · · ·
· · ·· · · ··
· ·
· ·
· · · ·
· ·
· ·
~~ ::· ·
4
·· ·· ·· ·· ·· ··
· · · ·
· · · ·
· · · ·
I··IA···
.'... · ·
· ·
t : 1. · · -·-·-...,,...1:··· .·· 6 J3 a01 · · ·-· · .us·
K
:AA
5
··-· --· -·--·-·-· ·
··--· -·--·-·--.·
·
· · · · 1!···5c:l···J
············
2
ZJ
Z2
Z1
6
9. --------·
·--------.
············
4
5-PA-104
Voltage Symbols C::,. Ground (i) +8.5V · +5V
0 -5V
Note: Voltages present in all card rows A through K.
Input Signal Pins
0 K4804 - Turn-On Power fl K4D05 +5V Ctl II K4B05 -POR1 (+VE)
II
PA754 Disk Board Signal and Voltage Distribution (01C and 01E Gates)
A1 Board Pin Side
·
·
Y2
· E·D··C·B·A·EYD·1·C·B·A·E·D ·
·· ·· ·· ·
F
E
D
c
B
02
2
~ · · · ·
·· ··
F
3
~8··
' · ··
F
4
~ · · · ·
· · ··
F
5
~ · · · ·
·
Z2
2
2
2
2
· ·
· ·
· ·
·~ · ·
· ··
········JAG········
· · · ·
t~~ ·
····3····
· ·
· ·
·········pAM·········
:4:
· ·
· ·
· ·
· ·
·~ · ·
· ·· ·
· ·
u············A5···s·········
J5
· ·
·····
·····
··~·1······
·
··
2 6
4
J1-2 - B2A01 J1-3 - B1E14 J1-4 - B2E01
J2-1 J2-2 J2-3 J2-4 -
B2A14 B3A01 B2E14 B3E01
J3-1 J3-2 J3-3 J3-4 -
B3A14 B4A01 B3E14 84E01
-Power Good +12V -12V
Ground -4V +5V Ground
Brake Coil 1 Brake Coil 2 DE Adjust Resistors B DE Adjust Resistors A
J4-1 J4-2 J4-3 J4-4 -
84A14 B5A01 B4E14 85E01
J5-1 J5-2 J5-3 J5-4 -
B5A14 B6A01 B5E14 B6E01
Ground -4V +5V Ground
Brake Applied to System Brake Coil/24V Brake +24V Ground (+24V)
REA 06-88481
SY27-2521-3
(PA753, PA754)
5-PA-105
PA755 Diskette Signal and Voltage Distribution (01D Gate)
Line Name
Ground +24Vdc +5Vdc -5Vdc
Power Connections to
Diskette Drive (see PA440)
Diskette Drive Control (DA3) Card (01D-A1)
Conn Pin
Card Pin
Test Point
TB1-2 PC1-J2-1 TB1-7 PC1-J2-2
808
DOB
TPA6
810
D10/J12
TPAS
803
D03/J03
TP815
811
D11/J13
TPA9
Power Supply
r
Diskette Drive Card Retainer
Drive Control Card DA3
Head Cable
___ ,---;tb~t~j~~~---L
Diskette Drive
Internal Cable
P3
~
AC Pow" Cable~
SV27-2521-3
REA 06-88481
Diskette Drive Card Socket and Head Cable Connector Pins
53FD Maple Block
5-PA-106
THP16
Diskette Drive Card Logic Pins
Note: Maple block causes Band D pin reversal.
TPA1
Read/Write Head 0
(white I
Center Tap Read/Write Head O Read/Write Head 0
(bluel · · (blackl ; :
Head 0 Read/Write
Erase Head 0
tredl · 1
Head 0
.--~E_r~as_e_H~ea~d~O'--~~~~~~~~~~~~~~·~ve_11_ow_I~:~:~~~~__.Erase
Cable Shield Head 0
Cable Shield Head 1
+Access 0 +Access 1 +Access 2 +Access 3 Wrote Data +Wrote Gate +Erase Gate +Erase/Write Current Enabled +Sel·ct Head 1 +Head Engage +lnde· +File Data +Diskette Sense -Diskette Drove Sense +Inner Tracks +Switch Filter
Ground +24 V de +5 V de -5 V de
.--~E_r_as_e_H_e_ad_l~~~~~~~~~~~~ly_e_llo_w_l-t-<.i----~~~~-, Headl
Erase Head 1 Read/Write Head 1
lredl
·
1
Iblack I
Erase
IA 1l Connector Card
\
1 2 3 4 5 6 7 8 9 10 11 Head Connector iHCPI
D02
003
Center Tap Read/Write Head 1 Read/Write Head 1
lbluel : : (white I
(black I Iblack I GOB
Head 1 Read/Write
D04 D05 802 805 804 809 807 D10 D13
D07 D08 D09 806 D12 808-810 803 811
Diskette Drive Card
J09 JOG G07 GlO
G11 GOG G03 J02 G04 G02 c=J05 J04
GOS
809 33FD PTX Return
806 _l3FD LED Ground 007 53FD LED Voltage
OlO 53FD PTX
D11 D06 003 802 -D04 D02 805 804
53FD PTX Return 53FD LED Goound Stepper Motor MC-0 Stepper M_C?tor MC· 1 Stepper Motor MC·2 Stepper Motor MC·3 Stepper Motor Common Head Load Solenoid
D05 ·Head Load
33FD
PTX I yellow)
33FD LED
Ired)
(black I (black)
53FD PTX lyellowl
j
53FD LED
(red)
(orange)
tredl (yellow) (blue)
Stepper Motor
(black I
r----- - (yellow)
I I (yellow)
~--;;,1:;,--c;,;s64-,
I
I
Note: Drives with the late EC level card may not have the two resistors and the capacitor.
1
A
Head Load 1
1
Solenoid 1
I
1Go12
I
I
I
I
I
:
28!2 F
{white)
I
LI --------- Note-1 ---__JI
PA760 Board and Cable Connectors
4POS
Cable Connector Socket Side
0
ogo
PN 1847528
0
Cable Connector Socket Side
15 POS Board Connector Pin Side
PN 1701532
4POS Board Connector Pin Side
PN 1473910
9 POS Board Connector
Pin Side PN 1473911 6POS
1:8 0 30
40 I 4Pin
Voltage Connector 'Socket View (unplugged)
100 50
:bbDos
Pin Side PN 1295112
6 Pin Voltage Connector Socket View
caution: The board connectors might not be mounted as shown in these drawings.
00000000
PN 1847530
9POS Cable Connector
6 POS Cable Connector
Socket Side
PN 1847532
REA 06-88481
SV27-2521-3
000 0 000 '12POS
D0 0 0 Cable Connector
000
PN 1847534
Socket Side
PN 1847536
(PA755, PA760)
5-PA·107
SY27-2521-3 This page intentionally left blank.
5-PA-108
Chapter 5. MAP Reference Information System Control Facility (SC)
SY27-2621-3
5-SC-i
Introduction
This part of Chapter 5 provides maintenance information to service the 8100 system control facility (SCF). When used with the Maintenance Analysis Procedures (MAPs), the SC MAP diagnoses SCF problems and refers you to this part of Chapter 5 for information such as hardware locations, possible causes of failure, and wiring lists.
Th is part has five sections:
1. General Information (SC100-SC 123) - Contains configuration, operation, and repair strategy information.
2. Offline Tests (SC200-SC250) - Contains test information and lists possible causes of failure.
3. Intermittent Failure Repair Strategy (SC300-SC351) - Contains information used to repair intermittent failures.
4. Signal Paths and Detailed Operational Description (SC400-SC464) - Contains diagrams and charts that show wiring and point·to·point signal paths.
5. SCF System Test and Internal 1/0 Bus Cable Change Procedures (SC500-SC520) Contains information concerning a system test procedure and how to change SCF internal 1/0 bus cables.
SY27-2521-3
Contents
5-SC-ii
SC100 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC110 Components and Addressing ........................ .
SC111 Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . SC112 Addressing .................................. . SC113 SCF Configuration Table Entry .................... . SC120 SCF Basic Operational Description . . . . . . . . . . . . . . . . . . . . . SC121 PSCF Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC122 SSCF Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC123 PSCF and SSCF Combined Basic Functions . . . . . . . . . . . . .
5-SC·1 5-SC-1 5-SC-1 5-SC-15 5-SC-16 5-SC-17 5-SC-17 5-SC-17 5-SC-17
SC200 Offline Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC210 Offline Test Routine Descriptions ..................... .
SC211 PSCF Routine Descriptions . . . . . . . . . . . . . · . . . . . . . . . . SC212 PSCF/SSCF Combined Function Routine Descriptions ..... . SC213 SCF System Test Routine Descriptions ..... '. . . . . . . . . . . SC230 Test Message Formats and Status Registers . . . . . . . . . . . . . . . . SC231 SCF Offline Test Message Formats . . . . . . . . . . . . . . . . . . .
SC232 Not Used SC233 SCF Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSCF Basic Status Register (BSTAT) . . . . . . . . . . . . . . . . . . . . . PSCF Error Information Register (EIR) . . . . . . . . . . . . . . . . . . . SSCF Unit Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . SC240 Test Messages and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . SC250 Action Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-SC-19 5-SC-19 5-SC-19 5-SC-21 5-SC-23 5-SC-26 5-SC-26
5-SC-27 5-SC-27 5-SC-27 5-SC-28 5-SC-29 5-SC-30
SC300 Intermittent Failure Repair Strategy ................... . SC310 Adapter-Unique Intermittent Repair Strategy ............. .
SC311 Looping with MAP Interaction to Determine Failures ...... . SC312 Using the System Error Log to Determine Failures . . . . . . . . . SC313 Using the Free-Lance Utility to Determine Failures . . . . . . . . SC320 Error Log Information Needed for the SCF . . . . . . . . . . . . . . . . SC330 Error Log Formats and Meanings Used for the SC MAP . . . . . . . . SC331 DPPX Error Log Formats and Meanings . . . . . . . . . . . . . . . . SC332 DPCX Condition/Incident Log Formats and Meanings ...... . SC340 How to Use the Error Log for Fault Isolation . . . . . . . . . . . . . . SC341 Using the DPPX Error Log Record for Fault Isolation ...... . SC342 Using the DPCX Condition/Incident Log for Fault Isolation .. . SC350 Action Plan to Correct Intermittent Failures . . . . . . . . . . . . . . . SC351 Machine Check Action Plan . . . . . . . . . . . . . . . . . . . . . . . .
5-SC-33 5-SC-33 5-SC-33 5-SC-33 5-SC-33 5-SC-34 5-SC-34 5-SC-34 5-SC-37 5-SC-38 5-SC-38 5-SC-38 5-SC-39 5-SC-39
SC400 Signal Paths and Detailed Operational Description .......... . SC401 SCF General Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC410 SCF Point-to-Point Net Listing . . . . . . . . . . . . . . . . . . . . . . . . SC411 8130 SCF Point-to-Point Net Listing . . . . . . . . . . . . . . . . . . 8130 Without Expansion Feature, 1/0 Bus to Adapters . . . . . . . . . 8130 With Expansion Feature, 1/0 Bus to Adapters . . . . . . . . . . . . 8130 - SC2, SC3, and SC4 Signal Path . . . . . . . . . . . . . . . . . . . .
5-SC-41 5-SC-41 5-SC-42 5-SC-42 5-SC-42 5-SC-43 5-SC-44
SC414 8140 SCF Point-to-Point Net Listing . . . . . . . . . . . . . . . . . . 8140 Model AXX - SC2, SC3, and SC4 Signal Path on A2 Board .. 8140 Models A3X and A4X Board Wiring - SC5 to 01 A-A2 Board Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8140 Model A5X Board Wiring - SC5 to 01 A-A2 Board Adapters .. 8140 Model BXX - SC2, SC3, and SC4 Signal Path on A1 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8140 Model BXX Board Wiring - SC5 to 01A-A2 Communications Adapter Board . . . . . . . . . . . . . . . . . . . . . . . 8140 Model BXX Board Wiring - 01A-B2 Disk/Diskette Adapter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8140 Model BXX Board Wiring - SC5 to 01 A-C2 or 01 A-D2 Tape Adapter Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8140 Model BXX Board Wiring - SC5 to 01A-C2 or 01 A-D2 Communications Adapter Board . . . . . . . . . . . . . . . . . 8140 Model BXX Board Wiring - SC5 to 01 A-C2 or 01 A-D2 Display/Printer Adapter Board . . . . . . . . . . . . . . . . . . . . . . . .
SC417 8101 SCF Point-to-Point Net Listing . . . . . . . . . . . . . . . . . . 8101 Model A25 Board Wiring - SC5 to 01A-A2 Disk/Diskette/Tape Adapter Board . . . . . . . . . . . . . . . . . . . . . . 8101 Board Wiring - SC5 to 01A-A1 or 01A-B1 Communications Adapter Board . . . . . . . . . . . . . . . . . . . . . . . 8101 Board Wiring (All Models Except A25) -SC5 to 01A-A2 Disk/Diskette/Tape Adapter Board . . . . . . . . . . . . . . . . . . . . . . 8101 Board Wiring - SC5 to 01A-A1 or 01A-B1 Display/Printer Adapter Board . . . . . . . . . . . . . . . . . . . . . . . .
SC420 Card Wiring Charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC430 SCF Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC431 SCF Internal Cable Connections . . . . . . . . . . . . . . . . . . . . . SC432 SCF External Cable Connections . . . . . . . . . . . . . . . . . . . . . SC440 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. SC441 SC1 Card Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Test the IPL Parameter Switch Settings . . . . . . . . . . . . . . SC442 SC5 Card Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC5 Card Module 1 Switch Description . . . . . . . . . . . . . . . . . . . . SC5 Card Module 2 Switch Description . . . . . . . . . . . . . . . . . . . . SC450 8130/8140 Detailed Data Flow . . . . . . . . . . . . . . . . . . . . . . . . SC460 SCF Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . SC461 Primary System Control Facility (PSCF) . . . . . . . . . . . . . . . SC462 Secondary System Control Facility (SSCF) . . . . . . . . . . . . . . SC463 PSCF and SSCF Combined Functions . . . . . . . . . . . . . . . . . SC464 How the SCF Controls the BOP, EFP, and Adapter Bus ..... . PSCF Command Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-SC-45 5-SC-45
5-SC-46 5-SC-47
5-SC-48
5-SC-49
5-SC-50
5-SC-50
5-SC-51
5-SC-52 5-SC-52
5-SC-52
5-SC-53
5-SC-54
5-SC-54 5-SC-55 5-SC-60 5-SC-60 5-SC-60 5-SC-60 5-SC-60 5-SC-60 5-SC-62 5-SC-62 5-SC-62 5-SC-64 5-SC-70 5-SC-70 5-SC-71 5-SC-71 5-SC-71 5-SC-71 5-SC-72
SC500 SCF System Test and Internal 1/0 Bus Cable Change Procedures . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . .
SC510 SCF System Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . SC520 Procedure to Change SCF Internal 1/0 Bus Cables . . . . . . . . . . .
5-SC-73 5-SC-73 5-SC-73
Figures
SY27-2521-3
SC111-1. 8140 Model A and 8130 with System Expansion Feature SCF Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC111-2. 8130 without System Expansion Feature SCF Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC111-3. 8130 A2 Board SCF Card/Connector Locations ......... . SC111-4. 8130A1 and A2 Board SCF Cables and
Locations (with System Expansion Feature) . . . . . . . . . . . SC111-5. 8130 A1 and A2 Board SCF Cables and
Locations (without System Expansion Feature) ........ . SC111-6. 8130 External Cable and Terminator Locations ......... . SC111-7. 8130 SCF Addressing and Card Locations . . . . . . . . . . . . . . SC111-8. 8140 Model A A1 and A2 Board SCF
Card/Connector Locations ...................... . SC111-9. 8140 Model A A 1 and A2 Board SCF Cable Locations ..... . SC111-10. 8140 External Cable and Terminator Locations ......... . SC111-11. 8140 Model A/8101 SCF Addressing and
Card Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC111-12. 8140 Top Card Connector Orientation . . . . . . . . . . . . . . . . SC111-13. 8809 Model 1B SSCF Card and Cable Positions ......... . SC111-14. 8140 Model B Basic Data Flow . . . . . . . . . . . . . . . . . . . . . SC111-15. 8140 Model B Cable Locations . . . . . . . . . . . . . . . . . . . . . SC111-16. 8140 Model B Board SCF Card/Connector Locations ..... . SC111-17. 8140 Model B SCF Addressing and Card Locations ....... . SC111-18. 8101 Al and A2 Board SCF Card and Cable Locations .... . SC111-19. 8130/8140/8101 01T Gate D and E Position Cable, Socket,
and Terminator Location and Socket Pin Numbering ..... . SC112-1. SCF Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . SC112-2. 8130/8140 Address Label Designations . . . . . . . . . . . . . . . . SC112-3. 8101 Address Label Designations . . . . . . . . . . . . . . . . . . . . SC113-1. SCF Configuration Table Entries and Card Locations ..... . SC342-1. Type-1 Record B-STAT Field Error Description . . . . . . . . . . SC342-2. Type-1 Record X-STAT1 Field Error Description . . . . . . . . . SC342-3. Type-1 Record X-STAT2 Field Error Description ........ . SC401-1. 8130 Hardware SCF Data Flow (without
Expansion Feature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC401-2. 8130 Hardware SCF Data Flow (with Expansion Feature) . . . SC401-3. 8140 Model A Hardware SCF Data Flow . . . . . . . . . . . . . . .· SC401-4. 8140 Model B Hardware SCF Data Flow . . . . . . . . . . . . . . . SC420-1. SC1 and SC7 Card and Connector Signals . . . . . . . . . . . . . . SC420-2. SC2 Card and Connector Signals . . . . . . . . . . . . . . . . . . . . SC420-3. SC3 Card and Connector Signals . . . . . . . . . . . . . . . . . . . . SC420-4. SC4 Card and Connector Signals . . . . . . . . . . . . . . . . . . . . SC420-5. SC5 and SC6 Card and Connector Signals . . . . . . . . . . . . . . SC441-1. IPL Parameter Bit Descriptions . . . . . . . . . . . . . . . . . . . . . SC441-2. SC1 Card IPL Switch Settings . . . . . . . . . . . . . . . . . . . . . . SC441-3. SC1 Card IPL Switch Module Locations . . . . . . . . . . . . . . . SC442-1. SC5 Card Module 1 Switch Settings Relating
to SSCF Board Locations . . . . . . . . . . . . . . . . . . . . . . . . SC442-2. SC5 Card Switch Module Locations . . . . . . . . . . . . . . . . . . SC450-1. SCF Signal Bus Data Flow Diagram . . . . . . . . . . . . . . . . . . SC450-2. SCF Timing Chart for Read and Write Operations ........ . SC450-3. SCF SC1 Card Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . SC450-4. SCF SC2 Card Data Flow . . . . . . . . . . . . . . . . . . . . . . . . .
5-SC-2
5-SC-3 5-SC-3
5-SC-4
5-SC-4 5-SC-5 5-SC-5
5-SC-6 5-SC-6 5-SC-7
5-SC-8 5-SC-9 5-SC-9 5-SC-10 5-SC-11 5-SC-12 5-SC-13 5-SC-14
5-SC-14 5-SC-15 5-SC-15 5-SC-15 5-SC-16 5-SC-38 5-SC-38 5-SC-38
5-SC-41 5-SC-41 5-SC-41 5-SC-41 5-SC-55 5-SC-56 5-SC-57 5-SC-58 5-SC-59 5-SC-61 5-SC-61 5-SC-61
5-SC-62 5-SC-63 5-SC-64 5-SC-65 5-SC-66 5-SC-67
5-SC-iii
SC450-5. SC450-6. SC450-7. SC520-1. SC520-2. SC520-3. SC520-4.
SCF SC3 Card Data Flow ........................ . SCF SC4 Card Data Flow ........................ . SCF SC5 Card Data Flow ........................ . Typical Top Covers ............................ . Typical 8130 Cable Installation .................... . Typical 8140 Cable Installation .................... . Typical 8101 Cable Installation .................... .
5-SC-67 5-SC-68 5-SC-69 5-SC-74 5-SC-74 5-SC-75 5-SC-75
SV27-2521-3
Abbreviations
adr adwa ARC BCLE BOP BSC BSTAT CA C-CODE CHIO CNT COMPSTAT CPR CRP DPCX DPPX
OT
EFP EIR EIRV EN FRB
FRU FRWA hex 1/0 IOEP IPL
LV
lvl MAP MD PA PIO PSCF RES ROS SCA SCF SDLC SEO NO SS SSCF SYS-COND USR UT
address adapter work area address adapter return code buffer control list element basic operator panel Binary Synchronous Communications basic status register channel address completion code channel 1/0 count completion status channel pointer register channel request priority Distributed Processing Control Executive Distributed Processing Programming Executive device type expanded function panel error information register error information register vector error number function request block field-replaceable unit function request work area address hexadecimal input/output 1/0 interrupt entry point initial program load level level Maintenance Analysis Procedure Maintenance Device physical address Programmed 1/0 Primary System Control Facility reserved read-only storage secondary component address System Control Facility Synchronous Data Link Control sequence number start/stop Secondary System Control Facility system condition unit status register unit type
5-SC-iv
SC100 General Information
This section illustrates and describes the system control facility (SCF) used in the 8130, 8140, and 8101. It enables you to understand basic operational differences as well as physical differences. It also enables you to understand the SCF addressing scheme, and describes any system-unique repair strategy involved when performing fault isolation.
SC110 Components and Addressing
The following sections describe and illustrate the 8100 SCF components and locations that relate to the SC MAP, describe the SCF physical addressing scheme, and list the SCF configuration table entry.
SC111 Hardware Components
Figures SC111-1 through SCl 11-19 show the physical components and locations of the SCF.
SY27-2521-3
(SC100-SC111)
5·SC·1
,-
EFP
BOP
8130/8140
SY27-2521-3
5-SC-2
1
I
I I
ll
I
EFP* Adapter AdrOA
I *8140
I
Only
I
IL __
ll ~
BOP Adapter Adr09
System Direct Control Bus
Proc
Stor Addr and Control
SDO Dest Bus
PIO Signal Bus
Storage A2
Disk
....-----------~--------------1Adapter
1. . . -----------------------------1Adr80
Drive
Data Link or Directly Attached Loop
S CF Signal Bus
PSCF Adr08
OC
::::1--f--t,,____ SSCF
Adr88
1-------------------------------------c 8182
I I
L.Z---z--1...----LDinatka
,_ ___1-_-_-_-_-_---=----_-_----I_ - I l----- Modified----- PIO Bus -------------------------t
Diskette
Adapter Adr 87
~ ~Drive
-~
, - - - - - - - - - - ~_"] r = _ - - - - - - - - - - 1
1
---------S-C-F-S-ig-n-al-B-u-s-------.-r--l...---------------
I
I A1 A2
I I
I
I
A:~~
Drive
I
~ ~ O ~ Diskette~
A:: Adr 97
1
: I
A2
A 1
I I
A::B ~~: I
A I
I
i
~:~~1F
~l;~1er
::~~r
I I I I
i I
g1~;~ter
~=~:::Printer
~2F
I
I
i
I
Dr~
I I
J Disp.
Ptr
I
L _ _ _ _ _ _ _, t---_J L _________ _J
8101 #1
'--L-t
8101 #2
To Tape
Figure SC111-1. 8140 Model A and 8130 with System Expansion Feature SCF Basic Data Flow
1-- - -,---=----=---=--=
-- -- -
----
----
,
-
I I I I
I I
I I PIO
Signal
I Bus I I
I
Basic
I
Operator
I
Panel (BOP)
I
System
I I I
I I
I I
Direct
Control
I
Bus
I
I
I
I
Primary
l
I
- System Control
Modified
PIO Bus
' I
I
Facility
I
I
I
I
I
I
I
I
I
I
I
r-
I
I System Control
I
I
~a~ty - -------- _J I
I
I
I
L_ ----- ----- - -- ---- ---- - -
- --
J
] l_
J
l
l
J
::J
l
--
Figure SC111-2. 8130 without System Expansion Feature SCF Basic Data Flow
I - - --8,30
I
I
I
1
I
I
I
I
I
I
I
I
] II 1/0 Adapter
I
] I 1/0 Adapter I
I
] I 1/0 Adapter
I
:J
Card
SC1 SC2 SCJ SC4 SC5 SC6 SC7
Location
A2G2 *A2F2 *A2E2 *A2D2 *A2C2 *A2B2 **A2H2
*System Expansion Feature Only. **Not used with System Expansion Feature.
A2 Board Positions
(With System Expansion Feature)
B
c D
E F
G
2
A2 Board Positions (Without System Expansion Feature)
G H
2
3
4
3
Caution: In the above figure, the 2, 3, and 4 rows use 2-position top card connectors. 4
Note: Cables connect to the cards in
5
A2F2 and A2G2 by a double male
pin connector, PN 5997533.
P/N 4134831
Caution: In the above figure, the 2, 3, 4, and 5 rows use 3-position top card connectors. You must not swap the 3-position top card connector used on these cards with those used on the processor cards, as the SCF connector does not tie the grounds together and, therefore, is a different part number.
Figure SC111-3. 8130 A2 Board SCF Card/Connector Locations
SV27-2621-3
(SC111 Cont)
5-SC-3
A1 Board
Figure SC111-4. 8130 A1 and A2 Board SCF Cables and Locations (with System Expansion Feature)
SY27-2521-3
A1 Board
A2 Board
Figure SC111-5. 8130 A1 and A2 Board SCF Cables and Locations (without System Expansion Feature)
5-SC-4
Note: Terminators must be present whenever cables are not.
Figure SC111-6. 8130 External Cable and Terminator Locations
A
ADRAB LVL02
ADR98 LVL02
ADRBB LVL02
ADROB LVL01
Notes: 1. Physical locations of first and second 8101s can vary from the above
configuration. 2. For an 8809 Model 18, the SSCF address is hex 78 and the level is 02.
Figure SC111-7. 8130 SCF Addressing and Card Locations
SV27-2521-3
(SC111,Cont)
5-SC·5
A1 Board Position
A2
BO 2
I
I
I
13
2
33
I
Card SC1 SC2 SC3 SC4 SC5
Location A1A2 A2A2 A2B2 A2C2 A202
13 2
I
I
I
13
u
2
I
I
I
13
Note: Cables connect to the cards in A 1A2, A2A2, A2C2, and A2D2 by a double male pin connector, PN5997533.
A2 Board Positions
A
B
BO
BO
c
D
BO BO
2
I
I
I
13
2
I
I
13
2
I
I
I
13
2
I
3-position Top
13
Card Connector ----.JL-
P/N 6819248
Caution: You must not swap the 3-position top card connector used on these cards with those used on the processor cards, as the SCF connector ties the grounds together differently and, therefore, is a different part number. See Figure SC111-12 for orientation.
Figure SC111-8. 8140 Model A A1 and A2 Board SCF Card/Connector Locations
SY27-2521-3 E F
Figure SC111-9. 8140 Model A A 1 and A2 Board SCF Cable Locations
5-SC-6
Figure SC111-10. 8140 External Cable and Terminator Locations
SY27-2521-3
(SC111Cont)
5-SC-7
Notes: 1. Physical locations of 8101s can vary from the configuration
shown. 2. For an 8809 Model 18, the SSCF address is hex 78, and the
level is 02.
SY27-2521-3
,o" <(0-J.~~'b
r--o~ b,'Da -J\..o \..
,o"
6'0 ~co<'i
SC5
A K ADRC8 LVL02
SC5
A K ADA AB LVL02
'D'o,.C)
SC5
D ADR88 LVL02
SC5
K A ADA98 LVL02
SC5
K A ADA BS LVL02
Figure SC111-11. 8140 Model A/8101 SCF Addressing and Card Locations
5-SC-8
/
When installing the SCF 3-position top card connector, always keep the extra thickness of material down and to the left.
Figure SC111-12. 8140 Top Card Connector Orientation
Figure SC111-13. 8809 Model 18 SSCF Card and Cable Positions
SV27-2521-3
(SC111Cont)
5-SC-9
,-
EFP
1
I
I
I
I
EFP* Adapter AdrOA
I *8140
I
Only
I
IL_
SY27-2521-3
-- -- --- --- - --- ------8140B
BOP
C2
SSCF
Adr 58
--------
D/P
Adapter
Adr 5F
OR
Tape Adapter Adr5E
BOP
Adapter Adr09
Stor
MOO
Proc
Addr and Control
Dest Bus
PIO
SIGNAL BUS
A1
Storage A2
------------------------- Comm
...._______________________________ Adr:. ~50-53rr-----o;t;'i~~-----------
Drive 5C-5F
Disk
_ _... ------------------------""4Adap~r.,....._"""f'.__
--------------e Adr84 ....---..........__-"
Data Link or Directly Attached Loop
System Direct Control Bus
PSCF
Adr08
oc
SCF Signal Bus
SSCF
Adr 88
a---------------------------------1
Comm
80-83
Diskette ._M_o_d_if_ie_d_P_l_O_B_u_s________________________________________.,. Adapter
"------------------------------------~Adr87
,---------- ----------1
I
~---------------------.,..-------------. SCF Signal Bus
I
I A1 A2
I I
I
Diskette
Drive
I I
I A::
:~ Adr97 0 I:
A2
A 1
I
I
A~:s A:: I
I
I
I
Disk
I I1
Comm
I Adapter
I Adr1~1F
::~~r
Tape
Adapter
Dr~ Adr93
I
I I1
Disk
::~:or
I
D/P Adapter Adr 2F
I I
I
I L___
8101 #1
Fipure SC111-14. 8140 Model B Basic Data Flow
I I
Di~.
Ptr
I
_ _ _J L __________J
8101 #2
To Tape
8140 Model B
Rear View
5-SC-10
To 01T-D To C2A2Y
Card
A1
ABC
D
K 01 C1
C2 02
Figure SC111-15. 8140 Model B Cable Locations
SY27-2521-3
(SC111Cont)
5-SC-11
A1 Board Positions
A
B
c
0
BO BO BO BO
2
I
22
I
13
w
J
2
33
I
I
13 p
2
I
I
I
13
2
I
13
3-position Top Card Connector PN 6819248
A2 Board Position A2
BO
2
I
I
I
13
2
33
I
I
I
13
2
I
2
I
I
I
13
33
SY27-2521-3
C2 Board Position A2 BO 2
' I
I
13 2
I
13 2
I
2
I
I
I
13
Caution: You must not swap the 3-position top card connector used on these cards with those used on the processor cards, as the SCF connector ties the grounds together differently and, therefore, is a different part number. See Figure SC111-12 for orientation.
Note: Cables connect to the cards in A 1A2, A 1C2, A 102, A2A2, and C2A2 by a double male pin connector, PN5997533.
Figure SC111-16. 8140 Model B Board SCF Card/Connector Locations
Card SC1 SC2 SC3 SC4 1ST SC5 2NO SC5
Locations A102 A1C2 A1B2 A1A2 A2A2 C2A2
5-SC-12
Notes: 1. Physical locations of 8101s can vary from the configuration
shown.
2. For an 8809 Model 18, the SSCF address is hex 78, and the level is 02.
SC5
A ADRC8 LVL02
SC5
A K ADRA8 LVL02
SC5
ADR 88 LVL02
A
ADA 58 LVL02
ADR98 LVL02
ISC5 K A
ADRB8 LVL02
Figure SC111-17. 8140 Model B SCF Addressing and Card Locations
SY27-2521-3
(SC111Cont)
5-SC-13
01T-D1 01T-D2 01T-D3
SC5 Card
A1 Board
01T-E1 01T-E2 01T-E3
SC5 Card
A2 Board
K
Note: Depending on the type and number of adapters in an 8101, there may only be one SC5 card and it can be in either the A 1 or A2 board.
Figure SC111-18. 8101 A1 and A2 Board SCF Card and Cable Locations
SY27-2521-3
SC4/5 Pin No.
W02 W22 X02 X22 Y02 Y22
Dand E Pin No.
1002 1802 2002 2802 3002 3802
Terminator
6-SC-14
Cable
Notes: 1. For correct cable and terminator locations according to system configuration,
refer to Figures SC111-6 for 8130 and SC111-10 for 8140. 2. The 8130 does not have 01, D2, and 03 socket positions in 01T gate. 3. In the 8140 BXX the 01, 02, and 03 socket positions are alongside the E1,
E2, and E3 positions.
Figure SC111-19. 8130/8140/8101 01T Gate D and E Positions Cable, Socket, and Terminator Location and Socket Pin Numbering
SC112 Addressing
SSCF addressing always requires two entries: 1. The physical address (PA) entry of hex 08, which defines the primary system control
facility (PSCF). 2. This entry defines the address of any secondary system control facility (SSCF), which
depends on its board location and application. For the 8130, it also depends on whether the System Expansion Feature is installed.
Figure SC112-1 shows the 8100 SCF physical addresses. PSCF address hex 08 is always the first two digits of the PA that specifies the SSCF.
Use Figures SC112-2 and SCl 12-3 to determine the PSCF and SSCF addresses of any 8130, 8140, or 8101. The address (PA) of the SSCF in an 8809-18 is always 78. See Figure SCl 11-13 for its location. If the 8140 is a model B, there may be a second SSCF with an address of 58.
SCF Board Location
Physical Address
8130 A2 board or 8140 A1 or A2 board 8130/8140 A2 board 81408 C2 board First 8101 A1 board First 8101 A2 board Second 8101 A 1 board Second 8101 A2 board Third 8101 A1 board Third 8101 A2 board Fourth 8101 A1 board Fourth 8101 A2 board 8809, Model 1B
08 0888 0858 0818 0898 0828 08A8 0838* 0888* 0848* 08C8* 0878
*8140 only. **X82E to occasio11ally X81 E for system-type tests
Figure SC112-1. SCF Physical Addresses
Typical Error*·
081E xxxx 882E xx xx 582E xx xx 182E xx xx 982E xx xx 282E xx xx A82E xx xx 382E xx xx B82E xx xx 482E xx xx C82E xx xx 782E xx xx
Primary Control Facility Address (8130 or 8140A). In the 814OB it is the P of the PA for the SSCF on the A2 board
0 N
A -
4
::::!:
8 ~- N
4 - -----
The 'P' of the PA for the Secondary System Control Facility (SSCF) in the 8140A or 8130 with Expansion feature. In the 81408 it ·Is the P of the PA for the SSCF on the C2 board.
Model Number (Example)
.-
r - - C u stomer
Write-In Area
Figure SC112-2. 8130/8140 Address Label Designations
The "P" of the PA of the Secondary System Control Facility (Example shown is for first 8101)
1
A 1 1
' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Customer Write-In Area
Figure SC112-3. 8101 Address Label Designations
REA 06-88481
SY27-2521-3
(SC111 Cont, SC112)
5-SC-15
SC113 SCF Configuration Table Entry
The configuration table defines the SCF address path in the following standard format:
LV PA UTUT OP(1*) OP (2*) OP (3*) OP (4*).
SY27-2521-3
RE A 06-88481
For the SCF, these values are:
PSCF LV = 01
SSCF LV = 02
PA
Board dependent. Refer to Figures SC112-2 and SCl 12-3.
UTUT
OOFO (SCF unit type designation)
OP (1)
Channel request priority value (refer to Figure SCl 13-1.)
OP (2)
00
OP (3)
00 for SSCFs
OP (4)
00 for SSCFs
*These fields are physically represented in the format OPOP OPOP. The numbers in brackets are only used to explain the entry values.
Figure SC113-1 shows the configuration table entries, card locations, physical addresses, unit types, and option field entries for the PSCF and each SSCF. The SSCF (SC5 card) channel request priority switches determine the value of the first option (OP1) parameter. As explained above, the format is shown as two physical addresses: the PSCF value hex 08 (LV01) and the SSCF address (LV02), both of which depend on the machine type and board location. For example, address 0818 specifies that the SSCF is contained in the first 8101 in the A1 board.
5-SC16
PSC F Location
8130 A2 board 8140A A1 board 81408 A2 board
LV PA UTUT OP(1) OP(2) OP(3) OP(4)
01 08 OOFO 10
00
43
80
01 08 OOFO 10
00
43
84
SSCF Location 8130/40 A2 board 81408 C2 board First8101 A1 board First 8101 A2 board Second 8101 A 1 board Second 8101 A2 board ***Third 8101 A1 board ***Third 8101 A2 board ***Fourth 8101 A1 board ***Fourth 8101 A2 board 8809, Model 1B
LV PA UTUT OP(1)
02 88 OOFO
54
02 58 OOFO
6C
02 18 OOFO
*1C
02 98 OOFO **JC
02 28 OOFO
*14
02 AB OOFO **34
02 38 OOFO
*OC
02 88 OOFO **2C
02 48 OOFO
*04
02 CB OOFO **24
02 78 OOFO
64
OP(2) 00 00 00 00 00 00 00 00 00 00 00
OP(3) 00 00 00 00 00 00 00 00 00 00 00
OP(4) 00 00 00 00 00 00 00 00 00 00 00
*This field becomes 74 if the board contains the display and printer adapter. If an 8140 Model BXX has a display/printer adapter in the C2 board (OP1field6C) or in an 8101 A1 board ( OP1 field 74), this is the second display/printer adapter and has an OP1 field of 7C.
**This field becomes 5C if the board contains the Magnetic Tape Feature, becomes 4C if the board contains the Diskette Storage Feature without the Magnetic Tape Feature, and becomes 04 if the board contains only an SSCF card.
***8140 only.
Note: Use the Machine Configuration List, stapled to the Machine Level Control (MLC} history sheets for this unit to help determine the correct values for the OP(1) field of the above table.
Figure SC113·1. SCF Configuration Table Entries and Card Locations
SC120 SCF Basic Operational Description
The functions provided by the 8130 without the System Expansion Feature are identical to those provided by the 8140 primary system control facility (PSCF) SC1 card. Effectively, the SC1 card permits information transfer within the 8130/8140 Processors. The functions provided by the 8130 with the System Expansion Feature are identical to those provided by the 8140 system control facility (SCF). These functions permit information transfer and provide interrupt and SSCF addressing control for devices attached externally to either the 8130 or 8140.
Note: For purposes of discussion in this section, the terms "PSCF" and "SSCF" are used. "PSCF" refers to those functions performed by the SC1 card, while "SSCF" refers to those functions performed by the SC5 card. The SC2, SC3, and SC4 cards become part of the PSCF when there is an SC5 card in the system, while the SC6 card, used only in the 8130 with the System Expansion Feature, functions as a signal line terminator.
For physical differences, see section SC110; for functional differences, refer to the detailed data flow contained in section SC450.
SC121 PSCF Basic Functions The following Iists the functions provided by the PSCF and briefly describes what these functions perform:
· Power sequence - Controls power sequencing for the 8100.
· Operator panel and channel operations - Controls data transfer of the basic and expanded (8140 only, if installed) operator panels, and the logic necessary for processor· to-channel information transfer.
· Clocked interrupt - Provides a 100-ms timer used for processor program operation. · Programmed IPL parameters - Provides a register used for program mode IPL operations. · IPL switch parameters - Provides switches that determine primary mode IPL parameters. · BOP and PSCF priority level assignments - Permits the program to alter the PSCF and
BOP fixed hardware interrupt level from 3 to 0. · Error detection - Enables parity error detection for the PSCF, as well as the BOP and
EFP (if installed). · KOO instruction decode for PSCF operations - Decodes certain types of KOO instruc-
tions to permit execution of specific SCF control functions.
· Reset control - Executes PSCF/SSCF and 1/0 group resets. · Programmed SCF control - Uses the SSCF status register to control certain SCF func-
tions under program control.
SC122 SSCF Basic Functions The following lists and basically describes the functions provided by the SSCF: · 1/0 group address - Provides switches whose fixed assignment determine the first four bits of the PIO physical address used to specify the device. · Channel request priority - Provides switches whose fixed assignments determine interrupt priority for channel 1/0 operations. · Release request for BSC operations - Permits BSC operations to override channel 1/0 operations so that no BSC data overrun conditions occur. · Interrupt translation array - Permits programmable interrupt level and sublevel assignments for all except the PSCF, SSCF, BOP, and EFP.
SC123 PSCF and SSCF Combined Basic Functions The following lists those SCF functions provided by combining PSCF and SSCF hardware: · Wraps the SCF signal bus to check correct bus operation. · Permits devices attached to any SSCF to present 1/0 interrupts. · Determines SSCF addressing.
SY27-2521-3
(SC113-SC123)
5-SC-17
SY27-2521-3 This page intentionally left blank.
5-SC-18
SC200 Offline Tests
The system control facility (SCF) can only be tested and repaired in offline mode with the system dedicated to fault isolation. These tests verify PSCF operation, and then verify operation of the PSCF with one of its SSCFs, if installed.
The tests are contained on MD diskette 01, and check SCF functions to isolate failures to the FRU or FRUs most likely defective. You invoke these tests only from the MD by using either the SC MAP for MAP interaction, or the Free-Lance Utility in which no MAP interaction occurs.
When using the MAP, the tests are automatically invoked and you are prompted by the MD display to perform test procedures. Refer to SC313 for procedures relating to free· lance operation.
SC210 Offline Test Routine Descriptions
The SCF tests may be described by grouping them logically by overall function, as follows:
Note: During Initialization 'there is a Configuration Table verification. These tests are always performed.
Group 1 -
PSCF Test, routine numbers less than 30. These routines test the SC1 care:!, and the basic functions of the SC2, SC3, and SC4 cards, when they are present. The routines can be invoked by entering '088' at BOBC and 'B' at 81BC.
Group 2 -
SSCF Tests, routines 30 through 89. These routines test the SC2, 3, 4, and 5 cards. They are run in addition to Group 1 on a single SSCF address when invoked by entering '08X8B' at 80BC and '1 B' at 81 BC. It should be noted that these tests include the use and testing of common adapter functions.
Group 3 -
SCF System Tests. These tests assuume that all the individual adapter tests have been run successfully. These tests make use of the entire system (this includes all adapters, SSCFs and configuration table). Testing includes some multi-adapter operations. These tests are invoked by entering '69C' at SOBC and 'B' at 81 BC. See SC510 for System Test operating procedures.
Note: Routines 2C and 20 are 'the system routines for an 8130 sys'tem without the expansion feature. These routines must be invoked separately.
SC211 PSCF Routine Descriptions
Routine 01, Reset Error Information Register (EIR) Test. This test first performs a Reset Adapter command and issues Read PIO commands to the 16-bit PSCF EI R. It then compares the data read to the data expected.
Routine 02, Set Error Information Register (EIR) Test. Individually tests each bit of the PSCF El R. All bits not used are masked before beginning the test. Starting with bit 0 and ending with bit 15, this routine individually places bits in the El R, and then issues a Read command to verify the data.
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Routine 03, Reset Error Information Register (EIR) Data Test. Places 1-bits in the EIR and issues a PIO reset command with a mask having only one bit on. It then reads the El R to ensure that only the proper bit was reset. Bits 14 and 15 are not used, therefore no interrupts are expected.
Routine 04, Reset Error Information Register Single Bit Data Test. Places a single bit in the El Rand then issues a reset command with the same bit masked. The register should then be reset with only the forced bits on.
Routine 05, Reset PSCF Basic Status Register (BSTAT) Test. This test first performs a Reset Adapter command and issues Read PIO commands to the 16-bit PSCF BSTAT. It then compares the data read to the data expected.
Routine 06, Set PSCF Basic Status Register (BSTAT) Test. Individually tests each bit of the PSCF BSTAT. All bits not used are masked before beginning the test. Starting with bit O and ending with bit 15, this routine individually places bits in the BSTAT and then issues a Read command to verify the data.
Routine 07, Reset PSCF Basic Status Register (BSTAT) Data Test. Places 1-bits in the BSTAT and issues a PIO reset command with a mask having only one bit on. It then reads the BSTAT to ensure that only the proper bit was reset. The routine operates on level zero so that interrupt processing does not occur.
Routine 08, Reset PSCF Basic Status Register Single Bit Data Test. Places a single bit in the PSCF BSTAT and then issues a reset command with the same bit masked. The register should then be reset with only the forced bits on.
Routine 09, Reset PSCF BSTAT Bit 3 (Power On Reset) Test. Hardware turns on PSCF BSTAT bit 3 after a power-on reset, and the Reset Adapter command should not turn this bit off. This routine sets the bit, issues a Reset Adapter command, and ensures that the bit was not reset.
Routine OF, SCF Interrupt Request Test. The SCF should present interrupt requests if bits 14 and 15 of the PSCF BSTAT are on. Th is routine sets PSCF BSTAT bits 14 and 15, using processing level zero. The IOIRV is then read to see that the proper 1/0 interrupt request is active. Both level 0 and N requests are tested.
Routine 10, Timer Check Test. Bit 8 of the PSCF EIR (timer check) should set when a timeout condition occurs (bit 8 of the PSCF BSTAT on). This routine sets bit Bof the PSCF BSTAT, then enabies the timer (PSCF BSTAT bit 9), which causes an immediate timer interrupt. PSCF EIR bit 8 (timer check) should be set.
Routine 11, Timer Accuracy Test. Tests the accuracy of the SCF timer logic that generates the 100-ms clocked interrupt. The routine first enables the timer, and, after the first active interrupt, enters a loop that counts 10 interrupts. The time used to complete this loop is then compared to the high and low tolerances, and, if within. limits, the test completes successfully. The timer speed is based on the input AC line frequency. The limits are based on a variation of±% cycle from the norm (50/60 cycle).
Routine 12, PSCF Basic Status Register Invalid Operation Test. The PSCF decodes all PSCF adapter commands. This routine issues all invalid commands to PSCF address 08 and then checks for a system check condition.
Routine 13, PSCF Error Information Register Invalid Operation Test. Issues all invalid commands to PSCF address OC and then checks for a system-check conditi.on.
(SC200-SC211)
5-SC-19
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Routine 14, Byte Tag Test. Checks that correct data transfer occurs between the PSCF and the processor for byte 1/0 commands.
Routine 15, KOO Enable Test. The 1/0 Power Drop command should not drop power if an improper sequence has occurred.
Routine 17, PSCF BSTAT Interrupt Test. Causes an interrupt request in PSCF BSTAT, then enables the adapter to ensure that an interrupt occurs. This test is done on level 7. Dynamic level switching to hardware level N is tested.
Routine 18, PSCF BSTAT Interrupt Level Switching Test. A stream of 1/0 instructions are used to set and reset active interrupt conditions. The processor should handle this maximum interrupt rate test.
This routine causes PSCF BSTAT interrupt requests by issuing 1/0 halfword commands to the BSTAT, which turns on bits 14 and 15. It then immediately issues another 1/0 halfword command that resets bit 14 to disable the interrupt. Many interrupts occur but the results are predictable. If the bits set and reset correctly, the proper level swaps have occurred.
Routine 19, Read PSCF Programmed IPL Register Test. The PSCF programmed two-byte IPL register is set and reset under program control. Before beginning, the routine reads the register. It then tests each bit by setting the bit (resetting the adapter) and then reading the register bit value. If successful, the register contents saved at the beginning of the routine are returned to the register.
Routine 1A, BOP Primary Interrupt Level Test. The BOP adapter is wired to present its interrupt requests on the same level as the SCF. This routine forces a BOP interrupt request, and then reads the 10 I RV to ensure that the proper bit was set for the interrupt.
Routine 1B, Read IPL Switch Register Test. The 16 switches on the PSCF (SC1) card are contained in two 8-switch modules. This routine reads the PSCF IPL switches to ensure that the value is equal to the factory setting (as in the Configuration Table). The IPL switch settings are also checked for validity.
Routine 1C, Condition Value Test. The SCF should set the correct condition value into the processor after executing each 1/0 instruction. This routine tests that the correct condition value is set. A test is also made to insure that the condition value is not changed if the 1/0 instruction does not complete successfully (machine check).
Routine 10, Wait Test. This routine tests the ability of the processor to enter the wait state and then, after an interval (signaled by an 1/0 interrupt), to continue processing on the same level. This is done by activating the SCF 100-ms timer. After the first interrupt, the ·interrupt is cleared and the SCF is enabled. The level is Pl RR 'O off. The system should remain in the wait state until the interrupt is fielded.
Routine 20, 1/0 (Read) Bus "Parity Valid" Signal Test. With the data tag active, the adapter activates the "parity valid" line to signal the processor that data parity should be checked. This routine uses the KOO instruction to force data bits 2 and 10 on, which should cause invalid parity. A system check should then occur with the EI RV indicating invalid parity.
Routine·21, 1/0 (Read) Bus Parity Bit (KOO '0110'B) Test. The adapter should raise the P-valid line during 'TD' time so that the processor will check the parity on the data. In this test the KOO instruction is used to force the data parity bits on, thereby causing bad parity. A machine check should occur with the EIRV indicating invalid parity.
5-SC-20
Routine 22, PSCF Parity Read Test. The PSCF should detect bad parity on the 1/0 bus at TD time when data is being transferred to the processor from one of the system devices. The BOP is used to send bad parity data through the PSCF. If the "SDCI bus select" line is active (the device did not detect bad parity), the bad parity data causes a read check and a machine check in the PSCF. The "valid" signal is also suppressed, which causes an 1/0 timeout, setting the machine check bit in BOP basic status. After the test is completed, the BOP is re-initialized. If this fails, a BOP error is indicated, either a hot interrupt or an 1/0 Interface Check (panel indicator).
Routine 23, PSCF 1/0 Parity Write Test. The PSCF should detect bad outbound parity on the 1/0 bus. The KOO instruction forces data bits 2 and 10 on, which causes invalid parity. A system check should then occur with the EIRV indicating a timeout condition, and PSCF EIR bit 9 should be on (1/0 Write check). When bad parity is detected by the processor, the halt signal should set the MCK bit in the selected adapter BSTAT.
Routine 24, 1/0 Read 80/81 Data Check Halt Test. The marker force bit 2/10 command forces invalid parity. The EI RV 1/0 parity bit should also be on. The routine tests each byte separately.
Routine 25, Marker Reset Function Test. Uses the force 2/10 data command to test that the marker function is reset after the first 1/0 command. The routine first enables the marker function and then issues an 1/0 read data command to ensure odd parity. This is immediately followed by a command that should normally produce a system check. If marker function is properly reset, no system check should occur. If ECC is present, a storage test for bad parity is done via KOO commands.
Routine 26, Read Secondary Level Command Test. (Only run if Expansion feature is installed.) Adapters on the same primary level should be assigned to different secondary levels. When presenting interrupts, each adapter ORs its secondary bit to the bus in response to the Read Secondary Level command. This routine issues the Read Secondary Level command to each of the eight primary levels and then tests the returned data for no bits active (no adapters were presenting interrupts). A test is made to insure that the Expansion feature (bit 6 of El RV) agrees with configuration type. This is the first test of the SC2, SC3, and SC4 Expansion feature cards.
Routine 27, Unselected Unit Test. (Only run if Expansion feature is installed.) When 1/0 units are not logically connected to the system, the 1/0 bus should be disabled. This routine attempts to read unit status in the reset condition. No data or response should occur, and the processor should report an 1/0 timeout.
Routine 28, Unit Not Connected Broadcast Read Command Test. (Only run if Expan· sion feature is installed.) SSCF status can be determined by using three commands: (1) Read USA bit 0, (2) Read USR bits 1 and 2, and (3) Read USR bit 3. This routine issues each command and then checks to see that all SSCFs have no status pending.
Routine 29, Unit Not Connected Data Wrap Path Test. (Only run if Expansion feature is installed.) The SCF can wrap a byte of data from the PSCF wrap register to the processor through the BO bus. This routine issues the Wrap (CRP) command without any 1/0 unit connected to test the path from the wrap register to the processor only. The test checks for bit 7 on, then bit 6, etc, then for no bits on. If an error is reported, a B message may be entered to continue checking the remaining bits. This is the first test of the wrap register in the SC3 card.
Routine 2A, 8130 "Halt" Line System Test. Can be used to isolate halt line failures in the PSCF. When the processor detects incorrect parity, it activates the "halt" signal and the selected adapter should set its machine check bit in basic status. This routine issues a Read BSTAT command (with incorrect parity forced) to each adapter in the system, which should cause the "halt" line to set the machine check bit. The routine does three different tests: Machine check, Halt, and Reset.
Routine 28, 8130 Data Bus Parity Check Test. The marker force 2/10 command places invalid data parity on the 1/0 bus. This routine tests the adapter parity detection logic by using byte and halfword commands. The routine does a Machine Check and a Halt Test.
Routine 2C, 8130 File Channel 1/0 and Release Request Test (selectable only). This routine checks the operation of the operation of the release request line when activated by the BSC/S·S communications adapter. If the configuration table indicates this adapter was installed, and a BSC/S-S communications adapter is present, the routine will be run. The release request line should be activated by BYSNC interrupt request and should cause the file adapter doing CHIO operations to stop. The test should proceed as follows: 1. Run the test without the BSC/S-S adapter and check for success.
2. Force the BSC/S-S adapter to interrupt.
3. Start CH 10 and test for release request.
4. Delay and check for CH 10 complete.
5. Remove the BSC/S·S adapter interrupt.
6. Check for CHIO operation complete.
7. If ECC is installed, CHIO test is run with bad parity data in the buffer. CHIO and adapter machine checks should occur.
Routine 2D, 8130 Diskette Channel 1/0 and Release Request Test (selectable only). This routine checks the operation of the release request line when activated by the BSC/S-S communications adapter. If the configuration table indicates this adapter was installed, and a BSC/S-S communications adapter is present, the routine will be run. The release request line should be activated by BYSNC interrupt request and should cause the diskette adapter doing CHIO operations to stop. The test should proceed as follows:
1. Run the test without the BSC/S-S adapter and check for success.
2. Force the BSC/S-S adapter to interrupt. 3. Start CH 10 and test for release request. 4. Delay and check for CH 10 complete.
5. Remove the BSC/S-S adapter interrupt.
6. Check for CH 10 operation complete.
7. If ECC is installed, CHIO test is run with bad parity data in the buffer. CHIO and adapter machine checks should occur.
SC212 PSCF!SSCF Combined Function Routine Descriptions The following tests run only on the 8140 and the 8130 with the System Expansion Feature installed.
Routine 30, Unit Connected Command Test. Unit status register (USR) bit 3 (unit connected) determines the logical attachment of the 1/0 unit (SSCF/SC5 card) to the 8100. This routine sets bit 3 in each adapter's USR, and then reads the register to ensure that a timeout does not occur.
Routine 31, 1/0 Unit Invalid Operation Test. Each 1/0 unit appears as an individual adapter to the SCF. This routine tests the ability of an 1/0 unit to reject all invalid commands.
Routine 32, PSV Valid Bit 1/0 Test. The processor always checks for invalid parity during 1/0 read commands. If the adapter does not activate the "valid" line, it sets the V bit in the PSV. This test issues a Read Sublevel command with the parity even, (one byte at a time). The parity valid line is not activated by this command.
Routine 33, TagNalid Wrap Tests. The SCF can wrap a byte of data (P, 0-7) from the PSCF wrap register to the processor on the BO bus. The data is also sent over the Tag bus to the SSCF card. From the SSCF card it is sent to the PSCF on the Valid bus. From the PSCF it is sent to the processor over the 81 bus. The test checks one bit at a time. If an error is reported, a B message may be entered to continue checking the remaining bits. The last test is done using adapter address 08. This test sets all bits on.
Routine 40, Unit Status Register Data Test. After bit 3 (unit connected) has been set, this routine reads and writes the eight USA bits one at a time.
Routine 41, Reset Unit Status Register under Mask Test. Tests the Reset command by first setting the register to all 1's. The routine then issues a Reset command with the mask containing only a single bit. Bits 0-3 are individually reset, and bits 4-7 are loaded from the mask bits. Bit 3 must always be set to properly execute the read commands.
Routine 42, Time Test. This routine tests 1/0 timing of the 8100 System. A series of 1/0 write commands is given, and a count of the number of commands performed during a fixed interval is recorded. The same sequence is repeated using read commands; more read commands should be done during the time interval. The 1/0 commands are done in level 1, with the timer signaling an end to the time period by forcing a level-0 1/0 interrupt. If more passes are required, the interrupt is reset and 1/0 instructions are resumed.
Routine 43, Unit Connected Broadcast Read Command Test. SSCF status can be determined by using three commands: (1) Read bit 0, (2) Read bits 1 or 2, and (3) Read bit 3. All selected bits are OR'ed into a halfword, and each bit occupies a particular position depending on the unit address of the SSCF.
Routine 44, 1/0 Adapter Interface Connect Test. The 1/0 connect bit (bit O) can only be set if bit 3 is also set. This test attempts to set bit 0 without bit 3 on. Then bits Oand 3 are turned on and bit 3 only is reset. The unit status register is then checked to see that bit 0 was also reset so that the 1/0 unit is truly disabled.
Routine 45, Unit Interrupt BSR(N) Bit 12 Test. Bit 1 of the unit status register is reserved. If bit 3 and bit 1 are on, then bit 12 of the BSR(N) should not be set. This test sets bit 1 of the test unit status register. The BSA (N) is then checked for proper setting.
SV27-2521·3
(SC211 Cont, SC212)
5-SC-21
Routine 46, Unit Interrupt BSR(O) Bit 11 Test. Bit 2 of the unit status register is set by data tag time parity errors. This bit should then set BSR (O) bit 11. This test sets unit status register bit 2 with the SSCF enabled.
Routine 47, Selective Reset Test. The Reset Adapter command issued to PSCF(N) should not reset the SCF unit status register. In this test, bits 1 and 2 of the selected SSCF are set. This should set bit 11 of the BSR (O) and bit 12 of the BSR (N). The Reset Adapter command (N) is then issued. The BSRs are checked to ensure that the tests bit remain set. The adapter is disabled.
Routine 51, USR Bit 9 Interface Test. USR bit 9 is reserved. Byte 1 should always return zeros when the USR is read.
Routine 52, Channel Request Priority Switch Test. Each 1/0 unit contains a set of 4-bit switches that are used to further define channel request priority. To ensure that these switches are set properly, this test reads them. The data is then compared to the configuration data. The read CRP wrap command is used in this test. Release request and the two-bit CRP bus are also tested. Before wrap testing, the CRP values in the option field of the configuration table are checked for validity by scanning adapter types to determine the correct CRP values. The CRP switches are in module 1 and are switch numbers 7, 8, 9, and 10. If an error is reported, a B message may be entered to continue checking the remaining switches.
Routine 60, Translate Array and Command Test. The translate array in the SSCF is a 1 x 16 hardware array. It is used to provide the system with programmable interrupt capability. There are eight 2-byte slots of which only the odd byte is used. Bits 1-3 are for the primary level, and bits 4-7 are for the second level decodes. 1/0 halfword instructions are used to read and write these array slots. This test does an addressing test of the array and verifies that the instructions perform correctly.
Routine 61, Translate Array Primary Translator Test. Each SSCF uses a translator to convert hex values to a 1-of-16 bit code. In this test, each adapter slot is set to a unique level code. The Test Read Primary Level command is issued. The corresponding bit in the 81 bus should be returned. After all eight levels have been tested, the array is rewritten so that each slot has a new primary level. The test is complete after all slots have been tested for al I levels.
Routine 62, Translator Array Error Test. Each translator in the SSCF will only translate a primary code value less than 8. If the array has bit 0 set, a parity error will be signaled if the array slot is read, since bit 0 will always be read as a 0. This test sets bit 0 in all slots and then reads each slot. Bit 2 of the unit status register should be set, causing an SCF signal bus check in BSR(O) to also be set. A halt should also occur. The routine runs on Level 7.
Routine 63, Translator Array Second Level Test. Each SSCF translator converts a second hex value to a 1-to-16 bit code when requested by a Read Second Level command. Only the slots that have a matching primary level active (interrupt request pending) will be translated. In this test, each slot is assigned a primary equal to its slot address. All eight slots will be given unique second level assignments. The Read Second Level Translate command will then be used to force the translation one slot at a time. Each slot is tested for all 16 valid secondary translate values.
Routine 69, Translate Array Primary Translator Test. This test is similar to Routine 61, except array bit 0 is set.
SY27-2521-3
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Routine 6F, Solid Data Bus or IR Bit Test. The adapter data bus is connected when bits 0 and 3 of the USR are set on. This test uses a halfword read command (to the IPL SW Register) to read known data. All data bits, except the one under test, are set on in the IPL Register. If there is a stuck adapter data bus bit, {or adapter IRB1 bit) a machine check will occur when reading that pattern of data. If the data error is in byte 1, the 10 IRR is read to determine if the error is the data of the IR bit. This is done by setting each translate slot so that its presented interrupt will come in on a different line than the data bit under test.
Routine 70, Real 1/0 Connection Test. 1/0 adapters are connected to the bus when both bits 0 and 3 in the USA are set. This test does a reset adapter command to each of the 16 possible adapter addresses. At least one of the adapters should respond without timing out. First the adapters are polled with the unit disconnected. No response is expected.
Routine 71, 1/0 Bus Output Data Driver Test. When bits 0 and 3 are set in the USR, the adapter data bus is connected to the SCF bus. This test checks the 'basic' adapter data bus bits (13, 14, 15) for opens. The 'basic' bits are those output bits required by 1/0 operations during the TA/TC time. All existing adapters on the SSCF participate
in the test. The test first issues a Reset adapter command to each adapter (bit 14 + addr). If this is successful, a reset BSR command is issued (bit 13 + addr). The Read BSR command is issued {bit 15 + addr). The errors will indicate the first failing bit in the first
error data byte plus all the adapters that fail. Note that the active bits of the adapter addresss also participate in the test.
Routine 72, 1/0 Bus Input Data Receiver Test. When bits 0 and 3 are set in the USR, the adapter data bus is connected to the SCF bus. This test checks the 1/0 adapter data bus for opens. Driver bits (13, 14, and 15) and adapter address bits have already been tested in the driver test. The open test is done by using the basic status register of the available 1/0 adapters as a data source. It should be noted that only byte 1 of the data bus will be tested if no halfword adapters exist on the SSCF. All adapters will be tested. The routine records all failing adapters; however, only the first failing bit is indicated.
Routine 73, 10/IR Bus Open Test. When Bits 0 and 3 are set {in the USA), the adapter 10/1 R Bus is connected to the SCF bus. This test finds an adapter; then sets an interrupt on and reads the 10/1 R Bus for the proper data. The test is done eight times using the same adapter. Each time the translate array is set for a different level. Then the eight tests are repeated for each adapter on the SSCF.
Routine 74, 1/0 Adapter Interrupt Capacity Test. Checks the ability of the SSCF translate hardware to translate the required maximum number of interrupts. This is done by causing all the adapters on the SSCF to present a different primary interrupt. The 1/0 bus is then disabled. When the bus is reconnected, the 101 R.V is immediately read and the number of interrupts compared with an expected mask {derived from configuration table data). This test is also a test of the IRR line.
Routine 75, Selective 1/0 Group Reset Test. An SSCF with status bits 0 and 3 reset to zero will activate an 1/0 reset to all adapters {on the 1/0 unit). In this test, all the attached adapters are enabled. Then each of the bits (0 and 3) are individually reset and set. The adapters {BSR) should remain enabled. The bits (0 and 3) are then reset and set. All the adapters should receive the 1/0 reset and be disabled.
Routine 79, 1/0 Read 80/81 Data Check Test. The marker force bit 2/10 command is used in conjunction with the IOH instructions to verify that the 1/0 parity checkers are working properly. First a read without a parity valid is issued with bit 2 only, causing the even parity. Then the read with bit 10 causing even parity is issued. In each case, the data stored is tested.
Routine 7A, Dynamic SSCF Parity Check Read Test. When the processor detects bad parity on read 1/0 commands, the "halt" signal should be raised and the selected adapter should set its system check bit. Th is test forces a read with bad parity from the SSCF that should cause a system check at the processor. The halt line should then set USR 2 bit, which in turn should set BSRO bit 11.
Routine 78, Dynamic SSCF Parity Check Write Test. The SSCF should detect bad parity and set bit 2 of its USR directly. This should also cause the SSCF to withhold the "valid" signal and cause a processor timeout. In this test, a set USR command with bad data is used to set the test conditions.
Routine 87, Unit Release Request Switch Test. To be added.
Routine 88, "Halt" Line System Test. Can be used to isolate halt line failures in the PSCF and SSCFs.
When the processor detects incorrect parity, it activates the "halt" signal and the selected adapter should set its machine check bit in basic status. This routine issues a Read BSTAT command (with incorrect parity forced) to each adapter on the 1/0 unit, which should cause the "halt" line to set the machine check bits in the adapters BSTAT. The routine does 3 differenct tests:
Machine check test: Tests that each adapter that sends bad data will cause an 1/0 parity check.
Halt test:
Tests that BSTAT bit 5 is set on a bad parity operation.
Reset test:
Tests that KOO 1/0 reset will properly reset all adapters (BSTAT).
Routine 89, Data Bus Parity Check Test. The marker force 2/10 command places invalid data parity on the 1/0 bus. This routine tests the adapter parity detection logic by using byte and halfword commands. The routine does a Machine Check and a Halt Test.
SC213 SCF System Test Routine Descriptions
Routine 90, File Channel 1/0 and Release Request Test. This routine checks the operation of the release request line when activated by the BSC/S-S communications adapter. If the configuration table indicates a file adapter and a BSC/S-S communications adapter are present, the routine will be run. The release request line should .be activated by BYSYNC interrupt request and should cause the file adapter doing CHIO operations to stop. The test should proceed as follows:
1. Run the test without the BSC/S-S adapter and check for success.
2. Force the BSC/S-S adapter to interrupt.
3. Start CHIO and test for release request.
4. Delay and check for CHIO complete.
5. Remove the BSC/S-S adapter interrupt.
6. Check for CHIO operation complete.
7. If ECC is installed, CHIO test is run with bad parity data in the buffer. CHIO and adapter machine checks should occur.
SY27-2521-3
It should be noted that all CCA adapters using BSC must have the release request switch set on the SC5 card (SSCF). Start/Stop adapters must have the switch off. The switch is adapter/port-dependent. The test is run on all BSC/S-S adapters and file adapters in the system.
Routine 91, Byte Tag Test. Halfword adapters must deal with the BSR on a byte basis. This can be done by implementing the byte tag. In this test, all halfword adapters are scanned to see that they perform BSR operations properly. All errors are presented after the testing is completed. If all adapters failed, a different error message is issued.
Routine 92, Maintenance Tests, and Power Down and Timer (BOP) Tests (selectable only). The design of the 8140 allows for the online maintenance of adapters. To facilitate this feature, individual 8101s can be powered down without affecting the operation of the programs running in the 8140. In this test, the operator is told to power down a unit under test while the test is running. An 1/0 interrupt should occur (SSCF power drop). The operator can then repower the unit. After each change of power status, a message is issued confirming the change. The routine will run until the operator 'frees' the routine or 5 minutes have elapsed. This is done by allowing the timer to run and display on the
BOP. The display is XYYZ (X "' minutes, YY "' seconds, Z = tenths).
Routine 93, System Channel Request Priority Test. Each 1/0 unit contains a set of 4-bit switches that are used to further define channel request priority. To ensure that these switches are 'set properly and that the priority/contention circuits are working properly, a CRP wrap is done with all the 1/0 units participating in the function. First the configuration table is used for determining the expected unit according to priority. Then several wraps are done to check the priority logic, and a test is also made to ensure no duplicate CRP values exist.
Routine 94, Read Connected Control/Unit System Test. The USR connected bit (0) connects all the adapters on the unit with the 1/0 bus. The Read Connected Status Broadcast command presents all unit status in a halfword. Th is test attempts to connect all of the possible 1/0 units. A test is made to ensure that they connect according to the configuration table. After the connecting has occurred, the status of the connected units is determined by issuing the Read Connected Unit bit 0 and bit 3 commands.
Routine 95, Read Interrupt Request System Test. The Read Interrupt Request Broadcast command reads the interrupt status of all system units. The interrupt sequence is a combination interrupt request or USR check. All the units on the system are connected, then all the interrupt request bits are set and read. Then all the USR check bits are set and read.
Routine 96, Tape Channel 1/0 and Release Request Test. This routine checks the operation of the release request line when activated by the BSC/S-S communications adapter. If the configuration table indicates a tape adapter and a BSC/S-S communications adapter are present, the routine will be run. The release request line should be activated by BYSNC interrupt request and should cause the tape adapter doing CHIO operations to stop. The test should proceed as follows:
1. Run the test without the BSC/S-S adapter and check for success. 2. Force the BSC/S-S adapter to interrupt. 3. Start CH 10 and test for release request. 4. Delay and check for CHIO complete. 5. Remove the BSC/S-S adapter interrupt. 6. Check for CHIO operation complete. 7. If ECC is installed, CHIO test is run with bad parity data in the buffer. CHIO and
adapter machine checks should occur.
(SC212 Cont, SC213)
5-SC-23
It should be noted that all CCA adapters using BSC must have the release request switch set on the SC5 card (SSCF). Start/Stop adapters must have the switch off. The switch is adapter/port-dependent. The test is run on all BSC/S-S adapters and tape adapters in the system.
Routine 97, Display/Printer Channel 1/0 and Release Request Test. This routine checks the operation of the release request line when activated by the BSC/S-S communications adapter. If the configuration table indicates a display/printer adapter and a BSC/S·S communications adapter are present, the routine will be run. The release request line should be activated by BYSNC interrupt request and should cause the display/printer adapter doing CHIO operations to stop. The test should proceed as follows:
1. Run the test without the BSC/S-S adapter and check for success. 2. Force the BSC/S-S adapter to interrupt.
3. Start CH 10 and test for release request. 4. Delay and check for CH 10 complete. 5. Remove the BSC/S-S adapter interrupt. 6. Check for CHIO operation complete. 7. If ECC is installed, CHIO test is run with bad parity data in the buffer. CHIO and
adapter machine checks should occur.
It should be noted that all CCA adapters using BSC must have the release request switch set on the SC5 card (SSCF). Start/Stop adapters must have the switch off. The switch is adapter/port-dependent. The test is run on all BSC/S-S adapters and display/ printer adapters in the system.
Routine 98, Diskette Channel 1/0 and Release Request Test. This routine checks the operation of the release request line when activated by the BSC/S-S communications adapter. If the configuration table indicates a diskette adapter and a BSC/S·S communications adapter are present, the routine will be run. The release request line should be activated by BYSNC interrupt request and should cause the diskette adapter doing CHIO operations to stop. The test should proceed as follows: 1. Run the test without the BSC/S-S adapter and check for success. 2. Force the BSC/S-S adapter to interrupt. 3. Start CH 10 and test for release request. 4. Delay and check for CH 10 complete.
5. Remove the BSC/S-S adapter interrupt.
6. Check for CH 10 operation complete. 7. If ECC is installed, CHIO test is run with bad parity data in the buffer. CHIO and
adapter machine checks should occur.
It should be noted that all CCA adapters using BSC must have the release request switch set on the SC5 card (SSCF). Start/Stop adapters must have the switch off. The switch is adapter/port-dependent. The test is run on all BSC/S-S adapters and diskette adapters in the system.
Routine 99, Power Down Test (selectable only). The SCF should drop system power when the Drop Power command is issued and the KOO enable power drop and enable KOO commands have been issued. This test will fail only if the power does not drop.
SY27-2521-3
5-SC-24
Routine 9A, Modifier Test. This test of the modifier line is run on diskette and tape adapters. The modifier line is used by the diskette adapter to allow register sets 8-11 to be used for channel operations. The modifier line is used by the tape adapter to accomplish odd byte data transfers.
Routine 9C, Adapter System Test. Connects all the 1/0 units at once and then forces an 1/0 interrupt on all adapters possible on the system. Each adapter is assigned a unique primary/secondary interrupt level. The secondary level is set by the control address. The primary level is based on the 1/0 unit address. The IOIRV is tested for primary level interrupts. The Read Secondary command verifies that only the configured adapters respond. This test verifies the accuracy of the configuration table adapter addresses. All adapters are contained in the adapter table. All slots in the SSCF arrays are preset to in· terrupt on primary level 0, and the secondary level is the 1/0 unit address. The wired array adapter slot is contained in bits 0-2 of the configuration table byte entry for the adapter. This is set by routine 9F.
Routine 90, IPL Switch Display (selectable only). This routine reads the IPL switch register and presents the data as an information display to the operator.
Routine 9E, Release Request Switch Test. This routine checks the Release Request switches on the SC5 card. These eight switches are numbered by port number. Only a BSC communications adapter should have the switch set on. This routine scans all adapter addresses and runs the test on all adapters except the BSC/SS adapters. The test is similar to routine 90. The CH 10 device is the first file adapter in the configuration table. If the release Iine is activated, the Release Request switch is set on (error).
Routine 9F, Real 1/0 Adapter Scan Routine (selectable only). There can be a maximum of eight 1/0 adapters on each 1/0 unit. These adapters can have a possible 15 different addresses. This routine attempts to connect all 15 possible 1/0 units and then read the status for all possible 1/0 adapters. Any adapter that responds will be recorded and then presented to the operator as a list of all available adapters. The list will be given a line at a time on a unit basis, and will contain the slot that the adapter is actually as· signed to. This is done by forcing a level 7 1/0 interrupt to each responding adapter. The secondary level presented will be the slot assignment. For 8130, only the responding adapters are given.
Routine AO, System Translator Read Test. Each SSCF contains a translator array which is written at SYSGEN time. If a parity error occurs, improper 1/0 interrupts can occur, causing erroneous interrupt processing or a system hard wait. It is important not to run the SCF diagnostic as it could mask an intermittent error. This routine should be run and looped first. It will read all the slots in all the arrays in the system. It will force interrupts to 1/0 units and test interrupt translations for the 1/0 units on the system. The error message will indicate the failing SSCF card and the failing slot.
Routine A1, Miscellaneous Channel Operation Tests. Channel operation is allowed whenever the channel mask is set and the EIRV register bits 0-5 are zero. In the first test, a File is started with the channel mask off. The operation should not complete until the mask is enabled. The second group of tests is then done by setting all the 'El RV' bits (5 to 0), one at a time. Each bit (except bit 4) being set should cause the channel to be masked off. A file CHIO operation should not start or finish until the MCPC is cleared. The last test checks that all channel pointer registers will operate properly. The same CH 10 operation is performed with a different channel pointer set until each has been tested.
Routine A2, Disabled Channel Operation Tests. The channel request and grant lines are not gated by the SSCF cards. To test this function, the following tests are done: 1. The channel mask is disabled. 2. A channel buffered adapter is started. 3. Bit 0 of the SSCF status register is disabled. 4. The channel mask is enabled. 5. Wait for a period of time. 6. Turn off the channel mask. 7. Set SSCF status bit 0 on. 8. Read MCPC. 9. Test for successful completion.
Routine AE, Run All Channel Adapters Test. This routine runs all (see routine AF description) CHIO adapters while using storage volume 0 only. Each CHIO adapter is serially actuated to do an adapter write operation, and locations hex 0100 through hex FF FF are tested. (see background storage test)
Routine AF, Selectable, Run All, Multi Adapter Channel Tests. This selectable routine will run or loop routines BO through BF only. This routine provides a storage scan looping facility. After invoking this routine, an "enter test address" message is issued. This message allows the operator to enter up to 16 adapter addresses to select the adapters to be run in routines AE through CO. The default of entering no adapter addresses is to run all adapters in the configuration table.
Routine BO-BF, Multi Adapter Channel Test. Channel operation is allowed whenever the channel mask is set. In this test all channel adapters are started with channel write operations (file, diskette, tape, display, HPCA). The channel mask is disabled. All operations use the same buffer. After all operations have been started, the channel mask is enabled. All operations should complete without error. The data buffer is started at the first location in a volume. The first test (buffer location 0 volume 0) should cause all CHIO adapters to generate a machine check during the test. Testing continues by moving the buffer upward through storage until the upper boundary has been reached (either 32K or 64K). This interactive test is designed to uncover adapter/storage problems. On error, the first error is captured but not printed. The El RV is then cleared and the test allowed to complete. After all the adapters have finished their CHIO operations, the first error will be printed. Giving the 'B' message after this will present the adapter status of all the adapters participating in the test. The first error message will be as follows: OBXB, BX4B, ADP ADDA, ADP STATUS, MCPC, BUFFER VOL, BUFFER ADDA, EVEN CPR, ODD CPR
The second message will be as follows: 08X8, BX73, ADP, ADP STATUS. MCPC. ADPT 1. ADPT 1 STATUS. MCPC~ ETC
REA 06-88481
SY27·2521-3
Notes: 1. CHIO devices must be ready. 2. Background Storage Test - When all Channel Requests are active, after the Channel
Mask has been enabled, storage testing, using the same buffer, is started wit:h CLS, MVHS, and TS instructions. Before each Move test, a TS instruction is issued to the 2-byte area used in the Move, except in the move test.
The Move test will move the buffer to itself on a halfword basis. The buffer is saved and restored. The data pattern to be tested is a floated-one then a floated-zero for each address.
The Compare test sets the destination bus to all ones and then compares each byte of data in the buffer. On machines with ECC, the background storage test is not run. Each hex 800 byte block of storage is tested for data integrity. 3. As an adjunct test, all adapter interrupt slots are set to a unique primary/secondary level. After a pass has been completed, the IOIRR, each interrupt, and all channel pointer registers are tested. The HPCAs only support 16-bit addressing and require three channel pointer registers. Each HPCA writes from a "pong" buffer (address under test) and then in full duplex mode reads into the "ping" buffer (fixed address).
Routine CO, Channel Request High Release Request Tests. Adapters issuing a channelhigh request should also activate the release request line (to stop burst data transfers). In the 8100, HPCAs are the only adapters wired to the channel request high line. In this test, each HPCA is wrapped so that a byte of HPCA data is placed in the write buffer of an operating buffered channel request adapter. If the HPCA is wired to the channel request high line (HPCAs above 9.6K), then the data written to the buffered adapter should include the byte of HPCA data. To check this, the buffered adapter is read. Low-speed HPCAs should not activate the release request line. The buffer used by the test CHIO device contains hex 20 data. The HPCA buffer contains hex FF data. This test is run as follows:
1. Find all HPCAs; count and identify high-speed HPCAs (above 9.6Kb).
2. Find a CH 10 adapter (see routine AF description). Start the adapter; start an HPCA check for proper completion. Check for release line action.
3. Tests are repeated until all HPCAs are run against all CH 10 adapters specified.
(SC213 Cont)
5-SC-25
SC230 Test Message Formats and Status Registers
This section describes the message formats used for SCF testing. These messages occur only offline, as there are no SCF online tests available.
SC231 SCF Offline Test Message Formats The following test messages can be generated during SCF testing: PAOO SCF tests completed successfully. PAFO = SCF tests are running.
The following test error message formats are generated during SCF testing: Format 1 - PAXE RREN Format 2 - PAXE RREN DBAD (AD is optional) Format 3 - PAXE RREN ADAD ADAD ADAD ADAD* Format 4 - PAXE RREN CNFG (8 BYTES) !-OCA Format 5 - PARR ADAD (AD is optional) Format 6 - PAXE RREN IR
Where: PA
x
E RR EN DB AD CNFG = LOCA =
IR
Physical address. Depends on SSCF location. Refer to SC112. Level 1 = PSCF
2 = SSCF Error defined by the following: Failing routine number (01-AO) Error number. Refer to SC240, which defines the error. Data Bit Address of failing adapter* Configuration entry (see SC113) Location of configuration table entry from beginning of table in hex (0500 is the 6th entry in the configuration table). Interrupt request line number
*In Format 3, there may be from 1 to 8 failing adapter addresses.
The following error messages use Format 2: PA2E 335X PA2E 6F06 PA2E 6F11 PA2E 7161 PA2E 7163 PA2E 7203
SY27-2521-3
REA 06-88481
5-SC-26
The following error messages use Format 3:
PAXE RR01 PA1E 2A01 PA1 E 2A2D PA1E 282D PA1E2B02 PA2E 7420 PA2E 7520 PA2E 8802 PA2E 882D PA2E 8902 PA2E 892D PA2E 9C01 PA2E 9C02
The following error messages use Format 4: PAXE 0018 PAXE 003F PAXE 0041 PAXE 0042
Note: RR= 00 indicates configuration table errors.
The following error messages use Format 5:
PA 15 - Test stopped at Routine 15. PA20 - Test stopped at Routine 1D. PA30 · Test stopped at Routine 30. PA40 - Test stopped at Routine 40. PA43 - Test stopped at Routine 43. PA47 ·Test stopped at Routine 47. PA70 ·Test stopped at Routine 70. PA73 - Test stopped at Routine 73. PA74 - Test stopped at Routine 74. PA90 - Test stopped at Routine 90. PA91 - Test stopped at Routine 9A. PA92 ·Test stopped at Routine 9E. PA93 - Test stopped at Routine A1. PA96 - Test stopped at Routine 96. PA97 - Test stopped at Routine 97. PA98 - Test stopped at Routine 98. PA99 - Test stopped at Routine 99.
The following error message uses Format 6: PAXE 7305
Note: When entering a PAX£ test error message into the MD, MAP menue selection 4, enter with no spaces:
Correct
NOT Correct
PAXERREN
PAX£ RREN
SC232 Not Used
SC233 SCF Status Registers
The two PSCF status registers, BSTAT and PSCF EI R, are both physically located in the SC1 card. Each SSCF (SC5) card also contains an SSCF unit status register.
PSCF Basic Status Register (BSTAT) The SCF basic status register contains the current hardware status of SCF Levels 0 and 3. Several commands, such as Set, Reset, and Reset under Mask, can be used to perform various operations that affect the status of the register bits. This register is addressed with hex 08 on Level 3. The PSCF BSTAT, which uses address hex 08 for information transfer, also enables and controls the operation of the 100-ms timer. The following table describes the PSCF BSTAT bit meanings:
Bit
Meaning
0
Reserved
Programmed IPL Register Valid - Set only by the program, and indicates that the programmed IPL register contents can be used during a program mode IPL sequence. Either a power-on reset sequence, pressing the BOP Reset/IPL pushbutton, or the program, can reset this bit.
2
Reserved
3
Power-on Reset - Set by hardware during a power-on reset sequence to indicate
restoration of system power. This bit determines the system initialization
required during IPL execution, and can also be set and reset by programming.
4-6
Reserved
7*
Processor Storage Select - When on, all data read and write and all instruction
fetch operations access processor storage and not ROS. When off and using a
real storage address under 4K, all instruction fetch and read operations are
from ROS, but all writes are to processor storage regardless of bit status. This
bit can be set and reset by programming, and can also be reset by a power-on
reset or pressing the Reset/IPL pushbutton on the BOP.
8
100-ms Clocked Interrupt - Set by hardware when either bit 9 turns on or by
a 100-ms elapsed time interval with bit 9 on. Can also be set and reset by
program, and also turns on bit 15 when on.
9
Timer Enabled - Set only by programming, which then permits bit 8 to present
an interrupt from the 100-ms clock. Can be reset both by hardware and pro-
gramming, and, when reset and set, always turns on bit 8.
10 11**
12 13
Reserved
SSCF Power Outage - An 8101 dropped power. Can be set by programming, and also turns on bit 15.
Reserved
PSCF Equipment Check - While executing a PIO to either PSCF level hex 08,
the BOP, or the EFP, the channel detected an error and issued a "halt" signal. This bit can also be set and reset by programming, and reset by hardware.
Bit
Meaning
14
PSCF Enabled - Permits the PSCF to interrupt processing on the currently
assigned priority level. Bit 15 indicates the pending interrupts according to
the status of bits 8 and 11. Only set by programming, and can be reset by both
programming and hardware.
15
PSCF Interrupt Request - The PSCF is requesting processor interrupt servicing.
Set by programming and also by bits 8, 9, 11 and 12. Cannot interrupt
processing unless bit 14 is on, but stays set until being reset either from
programming or hardware.
*Applies only to 8130 with or without the System Expansion Feature. **Applies only to 8130 with System Expansion Feature and all 8140s.
PSCF Error Information Register (EIR)
The PSC°F El R provides current PSCF error status, and uses commands such as Set, Reset, and Reset under Mask to perform various operations that affect the register bit status. The following table describes the PSCF EIR bit meanings:
Bit
Meaning
0
Reserved
1
BOP/PSCF Priority Level Control - When set, BOP and PSCF are assigned to
Level 0, and, when reset, they are assigned to Level 3. Set only by program-
ming, and reset either by programming or hardware.
2,3
Reserved
4
1/0 Read Check - Set by hardware when an out-of-parity condition occurs
while returning (reading) data to the program and using either the BOP, EFP,
or PSCF. If using PSCF address hex 08, it also sets bit 13 in the PSCF BSTAT,
and, if using PSCF address hex OC, it sets bit 13 in this register. Can also be
set by programming.
5
Reserved
6
SSCF installed.
7
Reserved
8
Timer Check - Set by programming, or by hardware when it detected a timeout
condition of the 100-ms clocked interrupt. Reset either by programming or
hardware.
9
1/0 Write Check - Set by hardware when an out-of-parity condition occurs
while receiving (writing) either data or the command byte from the program
and using either the BOP, EFP, or PSCF. If write errors occur while using
PSCF address hex 08, bit 13 in the PSCF BSTAT is set by the HALT signal, and, if using PSCF address hex OC, it sets bit 13 in this register. Can also be set by programming, and reset either by programming or hardware.
SY27-2521-3
(SC230-SC233}
5-SC-27
Bit
Meaning
10
Reserved
11 *
SSCF Equipment Check - An enabled SSCF detected an error during a PIO
operation. The SSCF in error sets its own status register bit 2, and, if the
SSCF detected the error, it sets its own bit 2 and this bit also. Set by hardware
or programming.
12
Reserved
13
PSCF Address Hex QC Equipment Check - Set when (1) an invalid parity
condition was detected on either the command byte or the data received
(written) from a program, or the data sent (read) to the program, while
performing a Pl 0 operation to PSCF address hex OC, or (2) the channel issued
a halt to PSCF hex OC. Reset by either hardware or programming.
14
Reserved
15
Reserved
*Applies only to 8130 with the System Expansion Feature and the 8140.
SSCF Unit Status Register (USR) The SSCF USR physically resides in the SC5 card and contains status information specifically related to information transfer from the PSCF to the attached device through the SSCF. The following table describes the SSCF Unit Status Register bit meanings:
Bit
Meaning
0
1/0 Group Enabled - If on, permits programmed access to devices attached
to the register's associated SSCF. Set by program.
1
Reserved
2
SSCF-Detected Error - If on, the associated SSCF received either (1) a PIO
command with invalid parity, (2) an invalid PIO command, (3) an invalid
parity condition on a write data operation, (4) an invalid parity condition on
a read translation array priority level assignment, or (5) a halt signal from the
channel while executing an 1/0 operation. This bit sets bit 11 in the PSCF
El R. No SSCF information transfer can occur until the SSCF that detected
the error turns off this bit.
3
SSCF Enabled - If on, permits programmed access to the SSCF and its
attached devices for read and write-type operations. If off, only write-type
operations can occur.
4-7
Reserved
SY27-2521-3
5-SC-28
SC240 Test Messages and Descriptions
The following table lists and describes the test error messages generated while using the system control facility MAP. Normally, only RREN values will be displayed. SC231 shows special error formats for certain routines.
RREN
RR01 RR02 RR03 RR04 RR05 RR06 RR07 RR08 RR09 RROA RROB RROC RROD RROE RROF RR10 RR11 RR12 RR13 RR14 RR15 RR16 RR17 RR18 RR19 RR1A RR1B RR1C RR1D RR1E RR1F RR20 RR21
Meaning Unexpected system check System check did not occur when expected Wrong system check
Unexpected 1/0 interrupt No 1/0 interrupt when expected
Solid interrupt Basic status register error Device status register error Channel request for priority during write Channel request for priority during read Processor error SSCF array error SSCF translator error Spurious interrupt Halt error Wrong level Data error Operator panel error No secondary interrupt request Timer error Timer fast Timer slow Timer did not step Channel request high configuration error ROS/RAM bit error Driver error SSCF installed (status bit 6) error Reset device status register error Device connection error Channel request for priority error Switch error·
No response from 1/0 adapter
Select error
RREN
RR22 RR23 RR24 RR25 RR26 RR27 RR28 RR29 RR2A RR2B RR2C RR2D RR2E RR2F RR30 RR31 RR32 RR33 RR34 RR3E RR3F RR40 RR41 RR42 RR43 RR44 RR45 RR46 RR47 RR48 RR49 RR4A RR4B
Meaning
Multiple no responses from 1/0 adapters
Byte operation error Condition code error Unexpected response Read secondary error CHIO error
CH 10 error 1
CHIO error 3
CH 10 did not complete
CHIO error 2 Enable error Reset error Power drop Exception error Timer slow Timer fast No exception Interrupt error CHIO error 4 Storage error
Configuration table type error Wrap command error Configuration table error Configuration table system error KOO error Multiple system check Slot error Resource error Multiple byte error Input error CHIO device error CHIO machine check during release test CHIO machine check
SY27-2521-3
RREN
RR4C RR4D RR4E RR4F RR51 RR52 RR53 RR54 RR55 RR56 RR61 RR62 RR63 RR64 RR65 RR66 RR67 RR70 RR71 RR72 RR73 RR74 RR75 RR76 RR77 RR87 RR9B RAFE RAFF
Meaning Modifier error Expansion feature error Configuration option byte 1 error Release error Wrap error number 1 Wrap error number 2 Wrap error number 3 Wrap error number 4 Wrap error number 5 Wrap error number 6 Test 1 bit 14 +address (Reset Adapter cmd) Test 2 bit 13 +address (Reset BSR cmd) Test 3 bit 15 +address (Read BSR cmd) Test 4 bit P1 +address (Set BSR cmd) DSR error 1 DSR error 2 Double MC error CHAN error with mask off CHAN error with mask on CHAN operation error CHAN machine check error Tape adapter status error Bit 0 error Message error Unexpected adapter error Basic status register contents wrong No device connection Release timeout error Control error
(SC233 Cont-SC240)
5-SC-29
SC250 Action Plans
This section lists action plans that you can use, depending on the results of the SC tests.
Caution: Power must be off before removing cards or installing cables.
ACTION PLAN 1 If the error is PAXE 5241
or PAXE 524E the configuration entry for the indicated PA does not match the table in SC113. Do steps 4 and 5 below to correct.
If the error is PAXE 0018 CNFG LOCA or PAXE 003F CNFG LOCA or PAXE 0041 CNFG LOCA or PAXE 0042 CNFG LOCA or PAXE 1B3F CNFG LOCA or PAXE 1B41 CNFG LOCA
1. The LOCA field gives the location of the error in the configuration table in hex. (LOCA = 001 F 31st entry from the beginning of the configuration table.)
2. RR= 00, which points to the configuration table. 3. EN= 3F, etc. (see (SC240). 4. Use the Free-lance Utility of the MD to check or change the configuration table. 5. After the configuration entry is corrected, run the SC tests.
ACTION PLAN 2 If the error is PA1E 2AXX ADAD ADAD ADAD ADAD
or PA1E 2BXX ADAD ADAD ADAD ADAD 1. Count the number of adapters that are failing. (The number of AD addresses in
the error message; AD= BX for 8130). 2. If there is only one adapter address in the error message, go to the MAP for that
adapter to find the problem. 3. If all the adpaters in the 8130 are failing, go to Procedure 04 "SCF Signal Bus Fault
Isolation" in Chapter 1, ST440, and loosen the adapters one at a time. 4. After loosening each adapter, run the SC tests in free-lance mode. When the
error message changes, go to the MAP for that adapter to find the problem. 5. If after loosening all the adapters the error remains the same, go to the SC MAP
to find the problem. 6. If more than one, but not all, adapters are in the error message, perform step 3 but
only loosen the failing adapters one at a time.
SY27-2521-3
5-SC-30
ACTION PLAN 3 If the error is PA2E 4008
or PA2E 4308 or PA2E 6FXX
or PAXE 702X or PAXE 7123 or PAXE 7161 or PAXE 7177 or PAXE 7211
or PAXE 732X (example: 881 E 7320 or 982E 7320) or one of the following MI messages:
PA30 PA40 PA43 PA47 PA70 PA73 PA74
1. Match the P in the error message to an address label on an operator panel of an 8101 or 8130/8140. (See SC112 for address label description and SC111 for locations of SSCFs.)
2. Go to Procedure 04 "SCF Signal Bus Fault Isolation" in Chapter 1, ST440, and loosen the adapters attached to that SSCF one at a time.
3. After loosening each adapter, run the SC tests in free-lance mode. When the error message changes, the error is in the loosened adapter. Go to the MAP for that adapter to find the problem. If the adapter tests give an error which is too basic for the adapter MAP, replace adapter cards for the failing adapter, one at a time.
4. If after loosening all the adapters the error remains the same, go to the SC MAP to find the problem.
ACTION PLAN 4 If the error is PAXE 7420 AD
or PAXE 9C01 AD or PAXE 9C02 AD and other error messages using format 3 (see SC231): 1. Match the first digit of the AD field of the error message to an address label on an operator panel of an 8101or8130/8140 (see SC112 for address label description and SC111 for locations of SSCFs). 2. Run Routine 9F (see below) to confirm AD is the adapter address the SC tests have a problem with. If the AD address does not show in one of the Routine 9F displays, or if an 081 E 9F01 AD message appears, it confirms that the adapter is causing the problem. 3. Go to the MAP for that adapter to find the problem. If the adapter tests give an error which is too basic for the adapter MAP, replace adapter cards for the failing adapter, one at a time. 4. If that MAP cannot find the problem, return to the SC MAP.
ACTION PLAN 5 If the error is PA2E 7520 ADAD ADAD ADAD ADAD
or PA2E 88XX ADAD ADAD ADAD ADAD or PA2E 89XX ADAD ADAD ADAD ADAD 1. Count the number of adapters that are failing (the number of AD addresses in the error message). 2. Match the first digit of the AD field to an address label on an operator panel of an 8101 or 8130/8140. (See SC112 for address label description and SC111 for locations of SSCFs). 3. If there is only one adapter address in the error message, go to the MAP for that adapter to find the problem. 4. If all the adapters attached to an SSCF are failing, go to Procedure 04 "SCF Signal Bus Fault Isolation" in Chapter 1, ST440, and loosen the adapters one at a time. 5. After loosening each adapter, run the SC tests in free-lance mode. A PA2E 7161 OEAD error message will occur, where AD is the address of the loosened adapter. Ignore this message. Press the 'B' key on the MD hand held keypad. The test will continue. If the original error message appears, continue to loosen the adapters attached to that SSCF one at a time. When the error message changes, go to the MAP for that adapter to find the problem. 6. If after loosening all the adapters attached to that SSCF the error remains the same, go to the SC MAP to find the problem. 7. If more than one but not all of the adapter addresses attached to that SSCF are in the error message, perform step 4, but only loosen the failing adapters one at a time.
REA 06-88481
SY27-2521-3
ACTION PLAN 6 If the error is PAXE52XX, perform the following procedure.
Note: If the error is PAXE524E or PAXE5241, there is a configuration table error; go to Action Plan 1.
1. Match the P in the error message to an address label on an operator panel of an 8101 or 8130/8140 (see SC112 for address label description and SC111 for locations of SSCFs).
2. Remove that SSCF (SC5 card).
3. Use Figure SC442-1 to check that SSCF switches 7 through 10 of module 1 are correct (see Figure SC442-2 for the SC5 card switch module locations).
4. There is a chance that switches 1-4 of module 1 may be wrong. If all the switches are correct, replace with a new card and run the SC tests again.
ACTION PLAN 7 1. Using MD diskette 01, select the SC MAP. At the MAP menu, select option 1
TO TEST EVE RY SSCF. If an error message occurs, follow the MAP to fix the error. 2. If no error message occurs, select the Free-Lance Utility. 3. At 80BC, enter 088; at 81 BC, enter 009AB. 4. Look for an error 081 E 9A4C AD, where AD is the address of the failing diskette
adapter. 5. If there is another diskette adapter on the System, enter B.
6. If another 081 E 9A4C AD error occurs and the two AD fields are the addresses
of different diskette adapters, or if there is only one diskette adapter on the sys-
tem, the error can be in the:
8130
8140A 81408
a. SC1 card
at A2G2
at A1A2 at A1D2
b. Processor card
at A102
at A1C2 at A1F2
c. Line between processor and SC1 card
A2G2G04A102U07
A2G04C2U07
D2G04F2U07
7. If only one error occurs when more than one diskette adapter was tested, change its SC5 card if not already exchanged. If the error is not corrected, return to step 6.
(SC250)
5-SC-31
ACTION PLAN 8 - SCF BUS ERROR
(To be used when more than one SSCF is failing}
1. Pick an SSCF with an error message, preferably in the most outboard unit. (See SC111 for locations of SSCFs.)
2. Unplug the W, X, and Y top card cables from the SSCF. (See Note below.}
3. At the MD keypad, press the PF key. When the PF menu appears, select 1 to return to SC MAP menu. Re-IPL.
4. Select SC MAP menu 1, TO TEST EVERY SSCF.
5. When the SC tests have been run to every SSCF and the error messages are available, write them down. If only the SSCF with its W, X, and Y top card cables unplugged has an error message, go to step 11. Otherwise, go to step 6.
6. If all the SSCFs continue to have error messages (the SSCF with the W, X, and Y top card cables unplugged may now have a different error message), plug the W, X, and Y top card cables previously unplugged.
7. If there are other SSCFs you have not checked with this unplugging procedure, pick another SSCF and return to step 2.
8. If all the SSCFs have been checked with this unplugging procedure, at the MD keypad, press the PF key. When the PF menu appears, select 1 to return to SC MAP menu. Re-IPL.
9. Select SC MAP menu 4, TEST ERROR MESSAGE, using the 882E XXXX error message. Whenever the SC MAP calls out the SSCF card to be changed, ignore it as it has been isolated from the failure.
10. Leave this action plan and take directions from the MAP.
11. This SSCF card is holding down some line on the bus. Remove the SSCF card, replace it with a new SSCF card, making sure the switches on the card are set the same as on the old card. See SC442 if more information is needed about the switches.
12. Replug the W, X, and Y top-card cables.
13. Go to step 3 to rerun the tests to check there is no error message. If an error message occurs now, carefully check the ends of the top card cables and the interposers at the SSCF.
14. Go to step 3 again. If an error message persists, go to step 9.
Note: In 8130s, remove the SSCF card, then replace the top card connectors so that outboard SSCFs remain connected to the PSCF.
SY27-2521-3
REA 06-88481
5-SC-32
ACTION PLAN 9
1. Using MD diskette 01, select the SC MAP. At the MAP menu, select option 1 TO TEST EVERY SSCF. If an error messag.e occurs, follow the MAP to fix the error.
2. If no error message occurs, select the Free-Lance Utility. 3. At 80BC, enter 08B; at 81 BC, enter 0090B.
4. If there is no failure, a series of progress indicators will occur. A sample is as follows: X8908010 If the routine hangs here or X81 E 9048 8000 error occurs, go to step 6. X8908011 X8909010 If the routine hangs here or X81 E 9048 9000 error occurs, go to step 5. X8909011
These progress indicators show the machine running the first file adapter with the first communications adapter, then on through other combinations of both.
5. For instance this is the first time the file with address 90 is checked and the one with address 80 was OK. Error must come from the Modifier line being on between the SC5 card with address 98 and the DA 1 or TA 1 card with address 9X (see SC417 8101 Wiring), or the SC5, DA1, or TA1 card.
6. The error may be caused by the Modifier line being on in the following places (a meter is needed to check the condition of the signal): a. In the 8130/8140 between the SC5 card and the processor (see step 6 of Action Plan 7).
b. In the 8130/8140 between SC5 card and the DA1 (see SC415 for 8140 DA1 board wiring or SC412 for 8130 board wiring}.
c. In an 8101 upper board where the Modifier line is not used but is turned on at the SC5 card (A1A2B12 at ground}.
d. In steps a and b above, the SC5, the DA1, or the TA 1 card, if present, may be holding the Modifier line down.
ACTION PLAN 10 - TIMER ERRORS
08XE 1114 Timer error 08XE 1115 Timer extremely fast 08XE 1117 Timer did not step 08XE 1130 Timer slow 08XE 1131 Timer fast
where X =1 or 2
Go to step 5 Go to step 5 Go to step 1 Go to step 2 Go to step 2
1. Check to see if the -50/60-Hz line is open or grounded. This line enters the SC1 card at the P11 pin. Use PA450 and PA460 of the PA section to trace this line. It is called "Square AC" in the PA section. If no problem with this line is found, go to step 5.
2. If this error occurred while using a backup power source, the source may be out of specification. It may be checked at pin P11 of the SC1 card. If no problem is found, go to step 3.
3. If this is a 60-Hz machine, check that the jumper is present from J7-8 to J7-15. If this is a 50-Hz machine, check that the jumper is removed. (See PA460 of the PA section.) If the jumper is correct, go to step 4.
4. The +60-Hz Control line may be grounded. It may be checked at pin P10 of the SC1 card. Use PA450 and PA460 of the PA section to trace this line. This signal is inverted in the power logic so an open line may look like a grounded line at the SC1 card. If no problem with this line is found, go to step 5.
5. Return to the SC MAP to find the error. The SC1 card or the engine card containing the oscillator (A 102 in 8130) is suspect.
ACTION PLAN 11 - CHANNEL 1/0 ERRORS
Certain lines between SSCFs and Channel 1/0 adapters cannot be checked with the Primary and Secondary SCF tests. To check these lines, you must run certain routines of the SCF System tests.
If one or more files are on the 8100 System, run routine 90. If there is a tape drive on the 8100 System, run routine 96. If there is a display or printer on the system, run routine 97. If there is one or more diskette adapters on the system, run routine 98. The following table shows how to invoke these routines using the Free Lance utility:
For Adapter
Routine to be Run
How to Invoke
At80BC
At81BC
File
90
Tape
96
Display/Printer
97
Diskette
98
088
00908
088
00968
088
00978
088
00988
Read the routine descriptions in secti"on SC213 to familiarize yourself with the intent of each routine used. Read section SC510 for setup details and error message definitions.
Record each error message. From the error message (or combination of error messages) you may be able to pin-point the' problem to a board, an adapter on a board, or a certain· type of adapter (a byte-adapter, for example). Then use section SC410 to find the type of board or boards that match the suspected board(s), and check the continuity of Channel 1/0 lines that go to suspected adapters.
REA 06-88481
SY27-2521-3
ACTION PLAN 12- INTERRUPT BIT FAILURES WITH ERROR MESSAGE PA2E 7305 IR
1. Match the P in the error message to an address label on an operator panel of an 8101 or 8130/8140. See section SC112 for address label description and section SC111 for SSCF locations.
2. Go to section SC410 and pick the net listing that matches the board or boards with adapters using this SSCF.
3. Turn power off and use this net listing to check the continuity of the -I R/81 bit line that matches the IR field of the error message.
4. If bad, replace the net or board; if good, return to the SC MAP.
ACTION PLAN 13 - SPECIAL POWER PROBLEM
After reading the SC diagnostic routine descriptions, a 1901 error message points you immediately to the SCl card and its switches. Error message 1901 also occurs when the +5 Volts Control line going to the U05 pin of any SC5 card is open. To isolate this failure to one SC5 card, turn off power to the 8101 units on the system or loosen the SC5 cards in the system, one at a time, until the error message occurs beyond the 1901 error message.
Once you have isolated the problem to one SC5 card, check the continuity of the +5 Volts Control line. See section PA450 for the path this line takes to get to the board with the suspect SC5 card. The following table shows, for the various boards, the line name and path on the board to the U05 pin of the SC5 card:
Unit
Line Name
Board
From
To (SC5)
8130
+5V
A2
8140 Mod A +5V
A2
8140 Mod B +5V Control A2
8140 Mod B +5V Control C2
8101
+5V Control Al
8101
+5V Control A2
Any D03 Any D03 Z1D05 Z1D05 Z1D05 K4D05
C2U05 D2U05 A2U05 A2U05 A2U05 A2U05
While isolating to a single SC5 card, use the Free Lance utility. If the failure cannot be found, return to the SC MAP for further isolation.
HOW TO RUN ROUTINE 9F
To run SC routine 9F, use the Free-Lance Utility. At 80BC, enter 088; at 81 BC, enter 009FB. A typical display is:
0805 adapter address 101112131F
01237} Wired in slots
these lines only show when SSCFs are in system
where 0805 is displayed because 088 was entered and five adapters are found to use the first SSCF checked. The second line contains the physical addresses of the adapters, the third line contains the SSCF array slots used by the adapters.
Enter B for the routine to display the same information for the next SSCF. Continue
entering Bs until no more SSCFs are found. The 0800 is displayed to announce the routine is completed.
(SC250 Cont)
5-SC-32.1
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REA 06-88481
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5-SC-32.2
SC300 Intermittent Failure Repair Strategy
To invoke the Free-Lance Utility to verify a repair action on the System Control Facility:
When intermittent failures occur, you can attempt fault isolation either by using the error log, looping the tests for an extended period while under MAP control, or using the Freelance Utility loop option to selectively loop the tests. Sections SC311, SC312, and SC313 explain these repair strategies, and SC350 lists the action plans you can use to help determine the cause of intermittent failures.
SC310 Adapter-Unique Intermittent Repair Strategy
Other than the action plans contained in SC350, there are three options for determining the cause of an intermittent failure:
1. You can loop the SC tests offline under MAP control for 5 minutes.
2. You can obtain a copy of the system error log by using a DPPX or DPCX utility (see SC330 and also see Chapter 2, CP750 for DPPX and CP830 for DPCX). If the customer does not use an IBM operating system, error logging facilities are not available.
3. You can loop the tests selectively by using the Free-Lance Utility. In this manner, you can select a routine or group of routines and specify certain run options.
1. On an 8140 or an 8130 with the System Expansion Feature installed, enter "08P8B" at 80BC and "1 B" at 81 BC.
2. On an 8130 without the System Expansion Feature, enter "OSB" at 80BC and "B" at S1 BC.
If the tests do not determine an error, return the system to the customer. After the system is operating, examine the error log for any SCF failures. If the error log indicates the same failure, you should perform the next step in the action plan. If the error log indicated that no failures occurred, end the repair action.
SC313 Using the Free-Lance Utility to Determine Failures
Certain groups of SCF test routines are run depending on the invoke message used with the Free-Lance Utility:
At80BC
At81BC
Routines Run
088 08P8B 69C 08B
B 18 B OOAFB
01 through 2F 01 through BF 90 through CO BO through BF*
*Routine AF is run to set up for Routines AE, BO-BF and CO.
The following sections explain how to use these options.
SC311 Looping with MAP Interaction to Determine Failures
The SC tests can be looped offline by using the SC MAP menu options 1, 2, or 3. All selections ask "DO YOU WISH TO CHECK FOR INTERMITTENT FAILURE BY LOOPING SC TESTS?" · MAP menu option 1 consecutively tests each SSCF, and, when complete, automatically
reinitiates testing. · MAP menu option 2 loops only one SSCF continuously.
The SCF tests can be looped without MAP interaction by using the Free-Lance Utility (see CP462 in Chapter 2). Also, refer to the following procedures for how to loop SCF tests or to loop a specific routine with test options.
To loop all SCF routines using the Free-Lance Utility: 1. At the 80BC or PAOO prompt message, enter either: · "08P8B" for an 8140 or an 8130 with the System Expansion Feature. · "088" for an 8130 without the System Expansion Feature.
· MAP menu option 3 loops only the PSCF continuously.
Where:
These tests loop continuously and display "PASO TEST LOOPING" on the MD until either an error is detected or you press the F pushbutton on the MD.
If the MAP detects an error while looping, the MAP directs you toward fault isolation in the same manner as a solid failure. Once you perform a repair action, the MAP loops the SC tests to verify the repair.
If the MAPs do not detect an error after looping the tests for 5 minutes, or random test errors messages occur, use the Free-Lance Utility looping option (see SC313).
SC312 Using the System Error Log to Determine Failures
DPPX and DPCX use error logs to record any SCF failure that occurs during system operation. To use this log for intermittent fault isolation, obtain all error log records associated with the SCF. The information in the error log can be used to determine the failure type {see SC340) and also the action plan to use to correct this failure. If necessary refer to CP750 for DPPX and CP830 for DPCX in Chapter 2 for procedures. If the log does not contain any error entries, no SC failure occurred during system operation.
OS= PSCF physical address PS= SSCF physical address (refer to SC113 for "P" value of SSCFs installed);
otherwise use only the OS entry B = Begin 2. At the 81 BC prompt message, enter either: · "01 B" if testing an 8130 without the System Expansion Feature. · "11 B" if testing an S140 or an 8130 with the System Expansion Feature.
The tests loop continuously until detecting an error. You terminate them by pressing "F" on the MD keypad.
If an error occurs while looping, the MD displays a test error message. Record this message and refer to the failure action plans contained in SC250 to diagnose and repair the failure.
After performing any repair action, loop the SC tests for at least 5 minutes to verify the repair.
To loop specific SCF routines and select run options using the Free-Lance Utility:
You can verify the repair action by running the SC tests using the Free-Lance Utility on the MD diskettes. (See CP462 in Chapter 2 and SC313.)
REA 06~8481
SY27-2521-3
1. At either the 80BC or PAOO message, enter the SOBC parameters according to the procedure described in step 1 above for the SOBC or PAOO response.
(SC300 - SC313)
5-SC-33
2. At 81 BC, enter SLR RB, where: S ;;;;: O;;;;: run only PSCF routines 01 to 2F.
1 = run the primary and designated SSCF using routines 01 to CO (only on
8100s with SSCFs installed). L 0 = run selected routine(s) once.
1 =loop selected routine(s) and stop on error. 2 = loop selected routine(s) and bypass errors. RR zero or no entry runs all routines. A valid routine number runs only that routine, and must be specified to run selectable only routines 2C, 2D, 92, 99, 9D, 9F, or FF. B = begin test
SY27-2521-3
REA 06-88481
SC320 Error Log Information Needed for the SCF
Refer to Chapter 2 (CP750 for DPPX and CP830 for DPCX) for the procedure to obtain the error log. Perform two searches for log records. First, search for log records of the failing SSCF using its address 08P8 (see SC112). Then search for all log records of the SCF using 08 (see SC112).
SC330 Error Log Formats and Meanings Used for the SC MAP
The format of the error log depends on whether the customer is using DPPX or DPCX. For DPPX formats, refer to SC331; for DPCX formats, refer to SC332.
SC331 DPPX Error Log Formats and Meanings
DPPX Type 5 Hardware Incident Record Format HEADER I CLASS 05 SUBCLASS 01 OPTION ( 5) DATE VY.ODD TIME HH/MM/SS
HEADER II CLASS 05 SUBCLASS 01 OPTION ( 5) DATE VY.ODD SEQ NO. ( 1 )
RECORD PA (2) SCA (3) DT (4) CRC (7) COMPSTAT (8) ARC (9) DATA (11) RES (12) CNT (13) IOEP (14) ADWA (15) CA (16) CPR (17) FRWA (18) RES (19) EXTENDED DATA 001 (24)(25) 002 (26)(27) 003 (28)(29) D05 (32)(33) D06 (34)(35) D07 (36)(37) 009 (40)(41) 010 (42)(43) 011 (44)(45) D13 (48)(49) D14 (50)(51)
D04 (30)(31) DOB (38)(39) 012 (46)(47)
5-SC-34
DPPX Error Log Record Meanings
The following listing describes the error log records used for SCF:
--
Field
( 1)
SEQ NO.
Meaning
-
Sequence Number of the error log record. This is part of
the Header II format provided by DISPLAY.ERRLOG if
bit 0 of the Option Mask (field 5) ;;: 0. If bit 0 = 1, header
1 has a time stamp in the format hour/minute/second.
With either header, a data field contains the year and Julian date.
The date is only valid when the customer sets it after every IPL using the SET.DATE command. The time is only valid when the customer runs DPPX with Timer Management and sets the time after every IPL using the SET.TOD command.
( 2)
PA
Physical Adapter Address - Byte 0 of the FRB byte:
08 - PSCF Basic Status Register (BSTAT)
09 - Basic Operator Panel Adapter
OC - PSCF Error Information Register (EIR)
( 3)
SCA
Secondary Component Address - Bytes 26, 27 of the FRB:
02 - TOD timer
01 - RTIT timer
( 4)
DT
Device Type - "F" (hex 40C6)
( 5)
OPTION
Option Mask - Byte 4 of DPPX Header:
Bit 0 = 1 - Time stamp (Header I)
= 0 - Sequence number (Header 11)
Bit 1 Bit 2
= 1 - BCLE present
= 1 - Extended data present
( 7)
CRC
Bit 3-7 "" - Specifies format for extended data FDM Request Code - Byte 1 of the FRB:
Function Request Read EI R status Set EI R status
Adapter CRC Address SCA
91 oc 92 oc
Reset EI R status
96
OC
Open adapter
03
08
Terminate adapter
6B
08
No-op
07
08
Read BSTAT status
91
08
Set BSTAT status
92
08
Reset BSTAT status
96
08
Read IPL control
89
08
Write I PL control
86
08
Read IPL switch reg
80
08
Program power off
12
08
_...
Field
Meaning
( 7)
CRC
FDM Request Code - Byte 1 of the FRB: (continued)
Function Request
Adapter CRC Address SCA
Read timer TOD
S1
OS
02
Write timer TOD
S2
08
02
Disable timer TOD
SA
08
02
Read timer RTIT
S1
08
01
Write timer RTIT
S2
08
01
Disable timer RTIT
SA
08
01
Wrt SSCF xlate array
22
08
Connect
AE
08
Disconnect
A6
08
Read secondary interrupt A5
OS
Read SSCF xlate .array
21
08
Read SSCF status
A9
08
Open adapter (BOPA)
03
09
Terminate adapter
6B
09
No-op
07
09
Read BOPA BSTAT status 91
09
Set BOPA BSTAT status 92
09
Reset BOPA BSTAT status 96
09
Read BOPA control byte BD 09
Write BOPA control byte BA 09
Read BOPA display
B5
09
Write BOPA display Diag rotate MD reg
B2
09
87
09
Write message to MD
72
09
Read message from MD
71
09
( 8)
COMPSTAT Completion Status - Byte 2 of the FRB:
BitO - Extended status indicator
Bit 1 Bit2 Bit3 Bit4 Bit 5 Bit6
- Reenter
- Reenter FRB indicator - Reserved - Complete - Error - Exception
Bit 7 - Attention
I
Note: If bitO (ESI) equals 1, then Byte 4 of the FRWA (Extended Completion Sta'tus - field 28) has meaning.
SY27-2521-3
Field
( 9)
ARC
( 11)
DATA
(12)
RES
(13)
CNT
(14)
IOEP
(15)
ADWA
(16)
CA
(17)
CPR
(18)
FRWA
(19)
RES
(24)
(25)
(26)
(27)
(28)
(29) (30)(31)
(32)-(35) (36)(37) (38)(39) (40)
Meaning Adapter Return Code - Byte 3 of the FRB.
Note: The values in fields 8 and 9 represent the adapter status when it terminated its activity, either successfully or with error, and returned control to DPPX.
Bytes 4-7 of the F RB.
Reserved - Bytes 8, 9 of the FRB - not used
Count - Bytes 10, 11 of the FRB.
1/0 Interrupt Entry Point - Bytes 12-15 of the FRB.
Adapter Work Area Address - Bytes 16-19 of the FRB
Channel Address - Byte 24 of the FRB - not used
Channel Pointer Register - Byte 25 of the FRB - not used
Function Request Work Area Address - Bytes 20-23 of the FRB.
Reserved - Bytes 2S-31 of the FRB - not used
Reserved - Byte 0 of the FRWA
Reserved - Byte 1 of the FRWA
Reserved - Byte 2 of the FRWA
Reserved - Byte 3 of the FRWA
Byte 4 of the FRWA - extended completion status:
Bit 0 - Request Reject
Bit 1 - Error Record Indicator
Bit 2 - Program Request Interrupt
Bit 3 - Not used
Bit 4 - Not used
Bit 5 - Preemptive Request Complete
Bit 6 Bit 7
- Not used - Reserved
Note: Bit 1 is set whenever the FDM builds an error record in FRWA bytes 16-27 (fields 40-51).
Reserved - Byte 5 of the F AWA
Bytes 6, 7 of the FRWA - error record displacement (pointer to FRWA byte 16).
Bytes 8-11 of the F RWA - not used
Bytes 12, 13 of the FRWA - residual count.
Reserved - Bytes 14, 15 of the FRWA
Byte 16 of the FRWA - error record flags:
Bit 0 - Not used
Bit 1 - Not used
Bit 2 - Partial log
Bit 3 Bit4
- Not used
- Not used
(SC313 Cont-SC331)
5-SC-35
Field (41) (42) (43) (44)(45)
(46)(47)
1 Meaning
Bit 5 - Not used
Bit 6 - Not used
Bit 7 - Not used
Byte 17 of the FRWA- retry count of failing operation.
Byte 18 of the FRWA - not used
Byte 19 of the F RWA - not used
FRWA Bytes 20, 21 - PSCF El R
Byte 20:
Bit 0 - Not used
Bit 1 - BOP/PSCF Priority Level Control
Bit 2 - Not used
Bit3 - Not used
Bit4 - 1/0 Read Check
Bit 5 Bit6
- Not used
- 1 = SSCF Installed
Bit 7 - Not used
Byte 21:
Bit 0 Bit 1
- 100-ms Clocked Interrupt Overrun
- 1/0 Write Check
Bit 2 - Reserved
Bit 3 - SSCF Equipment Check
Bit4 - Not used
Bit 5 - PSCF Address OC Equipment Check
Bit6 - Not used
Bit 7 - Not used
FRWA Bytes 22, 23 - PSCF Basic Status Register
Byte 22:
Bit 0 Bit 1
- Not used - IPL Register Valid
Bit 2 Bit 3
- Not used - Power-On Reset
Bit 4 - Not used
Bit 5 Bit 6 Bit 7
- Not used
- Not used
-· Not used
SY27-2521-3
Field (48)(49)
l
l Meaning
Byte 23: Bit 0 Bit 1 Bit 2 Bit 3
- 100-ms Clocked Interrupt
- 100-msec Clock Enabled
- Not used
- SSCF Power Outage
Bit 4 - Reserved
Bit 5 Bit 6 Bit 7
- Equipment Check - Enable Interruption
- Interruption Request
FRWA Bytes 24, 25 - BOPA Basic Status
Byte 24: Bit 0 Bit 1 Bit 2 Bit 3
- Invalid Command
- MD Signal Bus Check
- BOPA Write Check
- BOPA Read Check
Bit4 - MD Enabled
Bit 5 - Reserved
Bit 6 Bit7
- IPL/Keylock Encode
- IPL/Keylock Encode
Byte 25:
Bit 0 - Enter Data pushbutton
Bit 1 - Enter Function pushbutton
Bit 2 Bit3 Bit4 Bit 5
- MD Transfer Complete
- MD Status In
- Any IPL
- Machine Check
Bit6 - Enable BOPA Interruption
- Bit 7
BOPA Interruption Request
!
5-SC-36
Field (50)(51)
Meaning
FRWA Bytes 26, 27 - SSCF basic status. Byte 26:
BitO - 1/0 Unit Enabled Bit 1 - Not used Bit2 - SSCF·Detected Error Bit 3 - SSCF Enabled Bit4 - Not used Bit 5 - Notused Bit 6 - Not used Bit 7 - Not used Byte 27: BitO - Not used Bit 1 - Not used Bit2 - Not used Bit 3 - Not used Bit4 - Not used Bit 5 - Not used Bit6 - Not used Bit 7 - Not used
SSCF basic status is only valid for machine checks durin~ connect, disconnect, read/write translate array, and read SSC F status requests.
SC332 DPCX Condition/Incident Log Formats and Meanings
The DPCX Condition/Incident Log stores three types of record formats for system control facility failures:
DPCX Type 1 Record Format
( 1) 1·TYPE 1-REC
( 6) CCODE-XX
( 2) SEO-XXXX
( 7) B·STAT-XX
(3)
(4)
NA-XX PA-XX
(8 ~
CFR-XX
( 5) LA·XX
( 9) X-STAT1-XX
(10) X·STAT2·00
(11) S-FR-XX
(12) 10CB-XXYY OOZZ
(13) RC-XX
(15) 01-XXXX
(16) 02-XXXX
(17) 03-XXXX
(18) 04-XXXX
SV27-2521-3
DPCX Type 2 Record Format
(1)
(2)
(3)
2-TYPE I-REC SEO-XXXX NA-XX
(19) 021-XXXX XXXX
(20) LVL·XX
(21) 022-XXXX XXXX
(22) MCXX
(23) 023-XXXX
(24) 024-XXXX
(4)
(5)
PA-XX LA-XX
( 8) C·FR-XX
(11) S-FR-XX
(25) 025-XXXX
DPCX Type 4 Record Format
( 1 )
( 2)
(26)
4-TYPE I-REC SEO-XXXX SYS-CONO·XX
(27)
(28)
(29)
(30)
(31)
001-XX 002-XX 003-XX 004-XX DOS-XX
DPCX Types 1, 2, and 4 Condition/Incident Log Record Contents
Field ( 1) ( 2 )
( 3)
( 4) ( 5)
( 6) ( 7 )
( 8)
( 9) (10) (11)
(26)
X-TYPE SEO NA PA LA CCODE B·STAT CFR X-STAT1 X-STAT2 S-FR SYS-COND
Contents
Indicates the record type (1, 2, or 4).
A four-digit decimal number (0001-4095). This number identifies the relative time the incident occurred.
A two-digit number indicating the number of active applications at the time of the error.
A two-digit number indicating the physical address of the PSCF (see SC112).
A two-digit number indicating the logical unit address (same as PA).
Completion code - A two-digit hex number indicating operation completion status.
PSCF Basic Status Register bits 8-15. See SC233 for bit definition.
A two-digit hex number indicating operation when the error occurred.
PSCF EIR bits 0-7. See SC233 for bit definition.
PSCF EIR bits 8-15. See SC233 for bit definition.
A two-digit hex number indicating system operation when the error occurred.
A system condition code that identifies the system event being recorded.
Note: Presently, DPCX does not use fields 12·25 and 27-31 for SCF incidents.
(SC331 Cont, SC332)
5-SC-37
SY27-2521-3
SC340 How to Use the Error Log for Fault Isolation
The procedure for examining the error log depends upon whether the customer is using DPPX or DPCX. For DPPX, see SC341; for DPCX, see SC342.
SC341 Using the DPPX Error Log Record for Fault Isolation
The log records should be examined for the failing area of the SCF. The physical address indicates the failing PSCF or SSCF (08 or P8 respectively).
Obtain the basic status information from the extended data field 011, D12, and the high order of D14. Convert the hex number to binary (see Appendix A) and see SC331 for field meaning.
SC342 Using the DPCX Condition/Incident Log for Fault Isolation
Examine the log records for the failing area of the SCF. The PA indicates the failing PSCF or SSCF (08 or PB respectively). · If any Type 2 format records are found, use the Machine Check Action Plan (SC351)
to initiate a repair action. · If no Type 2 records are found, examine the Type 1 format records to determine the
type of SCF failure.
Obtain the B·STAT value (field 7) from the Type 1 record and convert the hex number to binary (see Appendix A). If the 8-STAT contains either an active 0 or 5 bit, use the Machine Check Action Plan (SC351) to initiate a repair action. Use Figures SC342-1, 2, and 3 to further define the error.
8-STAT Bits *O
1 2 *3 4 5 6 7
PSCF Basic Status Register Bits 8 9 10 11 12 13 14 15
Description 100-ms clocked interrupt 100-ms clock enabled Not used SSCF power outage Reserved PSCF equipment check PSCF interruption enabled PSCF interruption request
*Turns on B·STAT bit 7.
Figure SC342-1. Type 1 Record B-STAT Field Error Description
5-SC-38
X-STAT1 Bits 0 1 2 3 4 5 6 7
PSCF EIR Bits 0 1 2 3 4 5 6 7
Description Not used BOP/PSCF priority level control Not used Not used 1/0 read check Not used SSCF installed Not used
Note: For more information concerning the errors contained in this figure, obtain the X-STA T1 and X-STA T2 fields from the Type 1 error record.
Figure SC342-2. Type 1 Record X-STAT1 Field Error Description
X-STAT2 Bits 0 1 2 3 4 5 6 7
PSCF EIR Bits 8 9 10 11 12 13 14 15
Description 100-ms clocked interrupt overrun 1/0 write check Reserved SSCF equipment check Not used PSCF addr OC equipment check Not used Not used
Figure SC342-3. Type 1 Record X-STAT2 Field Error Description
SC350 Action Plan to Correct Intermittent Failures
Intermittent failures can most easily be determined by using the error log. To determine the type of failure recorded in the error log, refer to How to Use Error Log for Fault Isolation (SC340), which then refers you to the correct action plan.
SC351 Machine Check Action Plan Use this action plan for the following conditions:
· DPCX Type 2 log format errors - The processor logic detected an SCF hardware operational error, such as a parity error.
· DPCX Type 1 log format errors - The SCF detected a hardware error in the SCF logic.
· DPPX Type 5 log errors - A hardware failure occurred in the adapter bus logic during an SCF operation.
Caution: Turn power off when removing or exchanging cards or cables.
Troubleshoot this failure in the following sequence:
Probable Cause
1. Incorrect voltage
Action
Measure board voltages at 8130/8140 01A-A1 and 01 A-A2 boards and also at the board of the failing SSCF.
Comment
Missing or out-oftolerance voltages; go to PA MAP.
2. Loose or defective SCF control cables
3. Defective SCF cards
a. D03 = +4.5 to +5.5 V de b. 811 = +7.7 to +9.3 V de c. 806 = -4.5 to -5.5 V de
Inspect for Ioose or defective cables (see SC111 ).
Exchange, in order, the SC5, SC4, SC2, SC3, SC1, and SC6 cards. See the following chart for locations.
See Note 1 below.
See Notes 1, 2, and 3 below. If this is an 8130 without the System Expansion Feature, only the SC1 card can be exchanged. If this is an 8140, there is no SC6 card.
Mach Type 8130 8140A 8140B
SC5 A2C2 A2D2 A2A2
SC4 A2D2 A2C2 A1A2
SC2 A2F2 A2A2 A1C2
SC3 A2E2 A282 A182
SC1 A2G2 A1A2 A1D2
SC6 A2B2
2nd SC5 C2A2
Notes: 1. To verify the fix, run the SC tests using the Free-Lance Utility. At 80BC, enter OBA; at 81 BC, enter 1 B (see SC211 ).
a. If the tests fail, record the test error message and use the SC MAP menu option 4 to find the failure.
b. If the tests complete successfully (P800), return the system to the customer. Obtain a new error log after the customer has used the system.
c. If the log indicates a failure pertaining to this action plan, go to the next step in the table.
d. End repair action when there are no SC failures indicated in the log.
2. If the system still fails after exchanging cards, reinstall the original cards and go to the next step in the table.
3. If the system still fails after exchanging the FRU and this is the last step in the action plan, go to SC250 and use the SCF Bus Error action plan (Action Plan 8).
SY27-2521-3
(SC340-SC351)
5-SC-39
SV27-2621·3 This page intentionally left blank.
6-SC-40
SC400 Signal Paths and Detailed Operational Description
SC401 SCF General Data Flow
Figures SC401-1 through SC401-4 show SCF general data flow in the processors. Figure SC401-1 depicts the 8130 without the expansion feature; Figure SC401-2 shows the 8130 with the expansion feature; Figure SC401-3 shows the 8140A; and Figure SC401-4 shows the 81408.
4
~
Modified PIO Bus
,
w.x. 8t y
Connectors
W,X,&Y Connectors
SC1 Card A2G2
SC7 Card A2H2
Board Side
__]
PIO Signal
Busto
Processor
4
~
Board Side
i-L_ -··~PIO Bus [
System Direct
Control Bus
to BOP Adapter
4
~
Y4,Y5,Y6 Cr;ossovers to A1 Board
Figure SC401-1. 8130 Hardware SCF Data Flow (without Expansion Feature)
· . Modified PIO Bus
_I
W,X,& Y
z
Connector
Conn
:::i
W, X, 8t Y Connectors
rr==
z
Conn
.Data In Bus
'
SC6 Card
A2B2
,,
(Terminatorsl W. X, & V Connectors
01T·
4
l·
E1,E2, E3 to Other
SCF Signal
Units
Bus to All SC5 Cards
z
Conn
r --r
W,X,&Y
z
Connectors Conn
::J.
W,X,&V Connectors
SC1 Card A2G2
SC2 Card A2F2
SC3 Card A2E2
SC4 Card A2D2
SC5 Card A2C2
Board Side
PIO Signal Bus to Processor
· ·
Board Side
Board Side
Board Side
L::J
Data and Controls for Common
Usage in All 3 Cards with Exception
of Data In Bus.
....
Board Side
1
Modified PIO
.. .. Bus to Adapters
In A1 & A2 Boards
Modified PIO Bus
01T·D1, D2, 03 01T·E1. E2, E3 to Other Units
rr=----.·Data In Bus tr----~ 4
SCF Signal Bus to All SC5 Cards
W,X,&Y Connectors
SC1 Card A1A2
W,X,& Y Connectors
z
Conn
SC2 Card A2A2
z
W,X,&Y
Conn Connectors
z
Conn·
SC3 Card A2B2
SC4 Card A2C2
W,X,& Y Connectors
SC5 Card A2D2
Board Side
__J
PIO Signal
.. Bus to
Processor 4
Board Side
·
Board Side
Board Side
L_J
~
Data and Controls for Common
Usage in All 3 Cards with Exception
of Data In Bus.
-.....
Board Side
Modified PIO
. .. Bus to Adapters in A2 board
System Direct
. .. Control Bus
to BOP Adapter
Figure SC401-3. 8140 Model A Hardware SCF Data Flow
Modified PIO Bus
W,X,&Y Connectors
SC1 card A1D2
rr==
01T-D1, D2, 03 01T-E1, E2, E3 to Other Units
. . . Data In Bus +--S-CF S~ig~na~l ~~~~·it --~~~~~~---t Bus to All SC5 Cards
.L--...C==:c=:c;--,__ _ _ _...r;...r---~~-----&.
W,X,&Y
W,X,&Y
Connectors
Connectors
SC5 Card A2A2
SC5 Card C2A2
Board Side
_J
PIO Signal
Bus to
Processor
4
..
Board Side
Board Side
Board Side
Data and Controls for Common
Usage in All 3 Cards with Exception
-
of Data In Bus.
--
Board Side
Board Side
Modified PIO
.. Bus to Adapters
in A2 & B2 boards
Modified PIO
... .. Bus to Adapters
in C2 & 02 boards
System Direct Control Bus
.... ....to BOP Adapter
Figure SC401-4. 8140 Model B Hardware SCF Data Flow
System Direct Control Bus
to .B.O.-P-A..d.a.p.ter
Figure SC401-2. 8130 Hardware SCF Data Flow (with Expansion Feature)
SY27-2521-3
(SC400, SC401)
5-SC-41
SC410 SCF Point-to-Point Net Listing
This section lists the point-to-point signal path for the SCF cards. It also lists the board wiring from the PSCF or SSCF card to the individual adapters.
SY27-2521-3
5-SC-42
SC411 8130 SCF Point-to-Point Net Listing
8130 Without Expansion Feature, 1/0 Bus to Adapters
Line Name
-PIO Data 0 -PIO Data 1 -PIO Data 2 -PIO Data 3 --PIO Data 4 -PIO Data 5 -PIO Data 6 -PIO Data 7 -PIO Data PO -PIO Data 8 -PIO Data 9 -PIO Data 10 -PIO Data 11 -PIO Data 12
-PIO Data 13 -PIO Data 14 -PIO Data 15 -PIO Data P1 -TD Tag -1/0 Tag -1/0 Tag (B) -Halt -TA Tag -TC Tag -Byte Tag
A2 Board
A1 Board
A2 Board
Communications Adapters
SCF Card A2G2
Board
Board
V4, VS& V6 Z4, ZS&. Z6
Diskette DA A1S2
File FA A1U2
CA1 A2J4 A2K2
CA2 A2J2 A2L2
CA3 A2N4 A2M2
CA4 A204 A2P2
CAS A2S4 A2R2
CA6 A2U4 A2T2
W22 W28 W11 W24 W04 W25 W07 W06 W27 W05 W30 W13 W09 W29
W10 W23 W32 W33 X22 X05 X06 X09 X30 X10 X11
T1C13 T1E11 T1D13 U1C13 U1B13 T1C11 T1D11 U1A13 U1A11 M1B11 N1B13 N1E11 N1A11 N1A13
N1B11 L1E13 N1013 N1E13 P1E13 01c11 01011 R1B11 R1C13 R1C11 R1D11
L6D04 M6E04 N6C02 M6A04 M6A02 M6B04 M6002 M6C02 M6004 M6B02 M6B04 N6B02 N6A02 N6A04
N6B02 L6E04 N6D04 N6B04 P6E04 06C02 06002 R6B02 R6C04 R6C02 R6D02
G04 013 J02 G02 J06 G07 GOB G03 812 D12 J04 G09 J07 010 MOB J09 G05 J05 810 U05 509
P02 U06 505
504 U11 507 U05 U10 513
sos
M10 P10 509 S10 U02
sos
812 U13 U04 U07 512 U12 P02 013
J04 MOS
K2G02 K2J02 K2010 K2GOS K2J04 K2D09 K2B09 K2006 K2B02
L2G02 l2J02 l2D10 L2GOS L2J04 L2D09 L2B09 L2006 L2B02
M2G02 M2J02 M2D10 M2G08 M2J04 M2D09 M2B09 M2D06 M2B02
P2G02 P2J02 P2D10 P2GOS P2J04 P2009 P2B09 P2006 P2B02
P2G02 R2J02 R2D10 R2G08 R2J04 R2D09 R2B09 R2D06 R2B02
T2G02 T2J02 T2D10 T2G08 T2J04 T2D09 T2B09 T2D06 T2B02
K2B05 L2B05 M2B05 P2B05 R2B05 T2B05
K2B05 K2G04 K2005 K2B08
l2B04 L2G04 L2D05 L2B08
M2B05 M2G04 M2D05 M2BOB
P2B05 P2G04 P2005 P2BOB
R2B04 R2G04 R2005 R2B08
T2B04 T2G04 T2005 T2B08
A2 Board
A1 Board
A2 Board
Communications Adapters
Line Name
-Valid HW -Exception -Modifier -EOC -PV -V81 (8) -V81 -IRR (8) -IRR -V80 -1/0 Reset
-Release -IPR -Ch Reg Hi -Ch Reg Med -Ch Reg Lo -CH Grant Hi
-CH Grant Med -CH Grant Lo -IR/81 0 -IR/81 1 -IR/81 2 -IR/81 3
-IR/81 4 -IR/81 5 -IR/81 6 -IR/81 7 -IR/81 P +vE (POR) -10MHZ
SCF Card A2G2
X02 X23 X24 X04 X25 X27 X07 X28 X29 X32 Y13
Y09 Y30 X33 X33 X13 X12
Y02 Y24 Y06 Y25 Y29
Y28 Y04 Y05 Y27 Y07 Y22 Y33
Board
Board
Y4, Y5 &. Y6 Z4, Z5 & Z6
P1 E11 01A13 01813 01811 01C13 01 E13 03E11 R1A13 R1813 R1E13 V1811
P6E02 06A04 06804 06802 06C04 06E04 06ED2 R6A04 R6804 R6E04 V6802
U1C11 U1013 S1A13 U1011 S1A11 R1 E11
U6C02 U6004 S6A04 U6002 S6A02 R6E02
T1813 T1A11 T1C13 T1 E11 T1013 U1C13
T6804 T6A02 T6C04 T6E02 T6004 U6C04
U1B13 T1C11 T1D11 U1A13 U1A11
U6804 T6C02 T6002 U6A04 U6A02
Diskette DA A1S2
File FA A1U2
CA1 A2J4 A2K2
CA2 A2J2 A2L2
CA3 A2N4 A2M2
CA4 A204 A2P2
CA5 A2S4 A2R2
CA& A2U4 A2T2
W07 P13 U13 U11
U02
P10
G02
808
K2P11 L2P11 M2P11 P2P11 R2P11 T2P11
005
K2D07 L2D07 M2D07 P2D07 R2007 T2007
K2G03 L2G03 M2G03 P2G03 R2G03 T2G03
K2D02 L2D02 M2D02 P2D02 R2D02 T2D02 809
S03
T2G09 X2J05 L2J05 M2J05 P2J05 R2J05 T2J05
M05
S02
T2J13
X2M13 L2M13 M2M13 P2M13 R2M13 T2M13
M05
J02
K2P05 L2P05 M2P05 P2P05 K2P04 L2P04 M2P04 P2P04
R2P05 T2P05 R2P04 T2P04
U10 P05
G03
K2G09 L2G09 M2G09 P2G09 R2G09 T2G09 K2J06 L2J06 M2J06 P2J06 R2J06 T2J06 K2G07 L2G07 M2G07 P1G07 R2G07 T2G07 K2807 L2807 M2807 P2807 R2807 T2807 K2J07 L2J07 M2J07 P2J07 R2J07 T2J07 K2G10 L2G10 M2G10 P2G10 R2G10 T2G10 K2J10 L2J10 M1J10 P2J10 R2J10 T2J10 K2J11 L2J11 M2J11 P2J11 R2J11 T2J11 K2J12 L2J12 M2J12 P2J12 R2J12 T2J12 K2G12 L2G12 M2G12 P2G12 R2G12 T2G12 J4D11 J2011 M4011 04011 84011 U4D11
8130 With Expansion Feature, 1/0 Bus to Adapters
Line Name
-PIO Data 0 -PIO Data 1 -PIO Data 2 -PIO Data 3 -PIO Data 4 -PIO Data 5 -PIO Data 6 -PIO Data 7 -PIO Data PO -PIO Data 8 -PIO Data 9 -PIO Data 10 -PIO Data 11 -PIO Data 12
-PIO Data 13 -PIO Data 14 -PIO Data 15 -PIO Data P1 -TD Tag -1/0 Tag -1/0 Tag (8) -Halt -TA Tag -TC Tag -Byte Tag
A2 Board
SSCF Card A2C2
B02 BOS D11 G04 J07 G09 M02 P10 M12 005 810 013 G05 GOS
J09 P06 P11 P13 G02 JOS G13 J06 G10 J10 J11
Board Y4, Y5& Y6
T1C13 T1 E11 T1013 U1C13 U1 B13 T1C11 T1D11 U1A13 U1A11 M1811 N1813 N1 E11 N1A11 N1A13
N1811 L1 E13 N1013 N1E13 P1E13 01C11 01011 R1811 R1C13 R1C11 R1D11
A1 Board
Board Z4, Z5& Z6
L6004 M6E04 N6C02 M6A04 M6A02 M6B04 M6D02 M6C02 M6D04 M6B02 M6804 N6E02 N6A02 N6A04
N6B02 L6E04 N6D04 N6E04 P6E04 06C02 06D02 R6802 R6C04 R6C02 R6D02
Diskette DA A1S2
File FA A1U2
G04 D13 J02 G02 J06 G07 GOS G03 B12 D12 J04 G09 J07 D10
$04 U11 S07 U05 U10 S13
sos
M10 P10 S09 S10 U02 S05 U13
J09
U04
GOS
U07
JOS
S12
B10
U12
U05
P02
$09
013
P02 U06 $05
J04 MOS
A2 Board
Communications Adapters
CA1 A2J4 A2K2
CA2 A2J2 A2L2
CA3 A2N4 A2M2
CA4 A204 A2P2
CA5 A2S4 A2R2
CA6 A2U4 A2T2
K2G02 K2J02 K2D10 K2G08 K2J04 K2D09 K2B09 K2D06 K2802
L2G02 L2J02 L2D10 L2G08 L2J04 L2D09 L2B09 L2D06 L2B02
M2G02 M2J02 M2D10 M2G08 M2J04 M2D09 M2B09 M2D06 M2B02
P2G02 P2J02 P2D10 P2GOS P2J04 P2D09 P2B09 P2D06 P2B02
R2G02 R2J02 R2D10 R2GOS R2J04 R2D09 R2B09 R2D06 R2B02
T2G02 T2J02 T2D10 T2GOS T2J04 T2D09 T2809 T2D06 T2802
K2B05 L2805 M2805 P2805 R2B05 T2B05
K2B05 K2G04 K2D05 K2B08
L2B04 L2G04 L2D05 L2B08
M2805 M2G04 M2D05 M2808
P2805 P2G04 P2D05 P2808
R2B04 R2G04 R2DOS R2B08
T2B04 T2G04 T2D05 T2B08
A2 Board
A1 Board
A2 Board
Communications Adapters
Line Name
-Valid HW -Exception -Modifier -EOC -PV -VB1 (8) -VB1 -IRA (8) -IRA -VBO -1/0 Reset
-Release -IPR -Ch Reg Hi -Ch Reg Med -Ch Reg Lo -CH Grant Hi
-CH Grant Med -CH Grant Lo -IR/B1 0 -IR/B1 1 -IR/B1 2 -IR/81 3
-IR/B1 4 -IR/81 5 -IR/81 6 -IR/81 7 -IR/B1 P +VE (POR) -10MHZ
SSCF Card A2C2
007 010 812 009 804 J12 006 J13 805 809 G12
P09 M10 M05 G03 J02 M04
P12 P02 002 004 807 J04
G07 P04 P05 M07 P07 B13 M13
Board
Board
Y4, Y5 & Y6 Z4, Z5 & Z6
P1E11 01A13 01813 01811 01C13 01E13 01E11 R1A13 R1813 R1 E13 V1 B11
P6E02 06A04 06804 06802 06C04 06E04 06E02 R6A04 R6804 R6E04 V6802
U1C11 U1D13 S1A13 U1 D11 S1A11 R1 E11
U6C02 U6D04 S6A04 U6D02 S6A02 R6E02
T1813 T1A11 T1C13 T1 E11 T1D13 U1C13
T6B04 T6A02 T6C04 T6E02 T6D04 U6C04
U1B13 T1C11 T1 D11 U1A13 U1A11
U6B04 T6C02 T6002 U6A04 U6A02
V1813
V6804
Diskette DA A1S2
File FA A1U2
CA1 A2J4 A2K2
CA2 A2J2 A2L2
CA3 A2N4 A2M2
CA4 A2Q4 A2P2
CA5 A2S4 A2R2
CA6 A2U4 A2T2
W07 P13 U13 U11
U02
P10
G02
BOB
K2P11 L2P11 M2P11 P2P11 R2P11 T2P11
DOS
K2D07 L2D07 M2007 P2007 R2007 T2D07
K2G03 L2G03 M2G03 P2G03 R2G03 T2G03
K2D02 L2002 M2D02 P2002 R2D02 T2002 809
$03
T2G09 K2J05 L2J05 M2J05 P2JOS R2J05 T2J05
MOS
S02
T2J13
K2M13 L2M13 M2M13 P2M13 R2M13 T2M13
MOS
J02 K2POS L2POS M2P05 P2P05 R2P05 T2P05 K2P04 L2P04 M2P04 P2P04 R2P04 T2P04
U10
MOB P05
G03
812
K2G09 L2G09 M2G09 P2G09 R2G09 T2G09
K2J06 L2J06 M2J06 P2J06 R2J06 T2J06
K2G07 L2G07 M2G07 P1G07 R2G07 T2G07
K2807 L2807 M2807 P2807 R2B07 T2807
K2J07 L2J07 M2J07 P2J07 R2J07 T2J07
K2G10 L2G10 M2G10 P2G10 R2G10 T2G10
K2J10 L2J10 M1J10 P2J10 R2J10 T2J10
K2J11 L2J11 M2J11 P2J11 R2J11 T2J11
K2J12 L2J12 M2J12 P2J12 R2J12 T2J12
K2G12 L2G12 M2G12 P2G12 R2G12 T2G12
J4D11 J2D11 M4D11 04011 54011 U4011
SY27 -2521-3
(SC410, SC411)
5-SC-43
8130 - SC2, SC3, and SC4 Signal Path
Line Name
+Parity Valid Lth +SSCF IR +SSCF Mck -SSCF Pwr Outage -Pwr Seq Comp -Cr to Card 2 +IPR to Card 2 -IRR to Card 2 + Exception Lth +XS Tag Wrap + 08 Brdcst Cmd +OC Stat Cmd +08 Stat Cmd +XS Crp Wrap +Inward + Pwr Outage Lth +Go + Enable Data Lths -10 Mhz -Parity Good + Load Chew Reg +Valid Hw Lth +Valid Byte 0 Lth +Valid Byte 1 Lth +Modifier Latch -EOC DOT -Data Out PO -Data Out 0 -Data Out 1 -Data Out 2 -Data Out 3 -Data Out4 -Data Out 5 -Data Out 6 -Data Out 7 -Data Out P1 -Data Out S -Data Out 9 -Data Out 10 -Data Out 11 -Data Out 12 -Data Out 13 -Data Out 14 -Data Out 15
SC2
F2004 F5009 F5006
F5004 F3B13 F4B08 F2005 F2810 F4007
F2B02 F2B03 F4809 F3006 F3B04 F3B02 F5804 F5B02 F4010 F4B02 F2B07 F2009 F2006 F2D12 F2B09 F4D12 F2D02 F2B08 F2D11 F3D04 F3B07 F3D09 F4D02 F4B10 F4B13 F2B05 F2010 F2B13 F3D05 F3B08 F3809 F4D06 F4011
SC3
E4B03
E4007 E2804 E2802 E2B03 E4B09 E3006 E3804 E3B02 E5B04 E5B03 E4010 E4B02 E2B07 E2009 E2006 E2012 E2B09 E4D12 E2D02 E2BOS E2011 E3D04 E3B07 E3D09 E4002 E4B10
E2B05 E2D10 E2B13 E3D05 E3B08 E3B09 E4006 E4011
SC4 D2D04 D5D09 D5D06 04803 05004 03813 04808 02005 02810 D4D07 D2804
D4809 D3D06
02807 02009 02006 D2D12 02809 04012 02002 D2808 D2011 D3D04 D3807 D3009 D4002 04810 04813 02805 02010 02813 03005 03BOS 03809 04006 04011
SY27-2521-3
Line Name
+1/0 +TA +TC +TD +Ch Grant +Any Tag -Byte Tag -Halt -SC1 Reset/not 1/0 -SC1 Reset -SC5 Reset -1/0 Reset -Outbound Ctrl -Xmit Ctrl -Int or Ml Vhw -Val Oly 150-200 -Val Dly 250-300 -Any Val Lth +10 Mhz + 2 Hz Free Run -Pwr Seq Complete
SC2
F3805 F3010 F3810 F3002 F3812 F4005 F3D11 F4B07 F4812 F3012 F4009 F2B12 F3013 F2013 F3D07 F4004 F4B04 F3013 F4805 F3B03 F5004
SC3 E3805 E3010 E3B10 E3002 E3812 E4005
E4812 E3012 E4009
E3013
E3D07
E4D13 E4805
SC4
03805 03D10 03810 D3D02 03812 D4D05 03011 04807
04009 D2812 03013 02013 03007 D4004 04804 04013 04805 03803 05004
5-SC-44
SC414 8140 SCF Point-to-Point Net Listing
8140 Model AXX - SC2, SC3, and SC4 Signal Path on A2 Board
Line Name
+Parity Valid Lth +SSCF IA +SSCF Mck -SSCF Pwr Outage -Pwr Seq Comp -Cr to Card 2 +IPR to Card 2 -I RR to Card 2 +Exception Lth +XS Tag Wrap
+as Brdcst Cmd +oc Stat Cmd +as Stat Cmd
+XS Crp Wrap +Inward +Pwr Outage Lth +Go +Enable Data Lths -10 Mhz -Parity Good +Load Chew Reg +Val id Hw Lth +Valid Byte 0 Lth +Valid Byte 1 Lth +Modifier Latch -EOC DOT -Data Out PO -Data Out 0 -Data Out 1 -Qata Out 2 -Data Out 3 -Data Out4 -Data Out 5
-Data Out 6
-Data Out 7 -Data Out P1 -Data Out 8 -Data Out 9 -Data Out 10 -Data Out 11 -Data Out 12 -Data Out 13 -Data Out 14 -Data Out 15
SC2
A2D04 A5D09 A5D06
A5004 A3813 A4BOS A2D05 A2810 A4D07
A2802 A2803 A4809 A3006 A3804 A3B02 A5B04 A5B02 A4010 A4B02 A2B07 A2D09 A2D06 A2D12 A2B09 A4D12 A2D02 A2808 A2D11 A3D04 A3807 A3D09 A4D02 A4B10 A4B13 A2B06 A2D10 A2813 A3D05 A3808 A3B09 A4D06 A4D11
SC3
84803
B4D07 82804 82802 82803 84809 83006 83804 83802 85804 A5803 84D10 84802 82807 B2D09 82D06 82D12 82809 84D12 82D02 8280S 82D11 83D04 83807 83D09 84002 84810
82805 82010 82813 83005 B380S 83809 84006 84011
SC4 C2D04 C5D09 C5D06 C4803 C5004 C3813 C480S C2D05 C2810 C4D07 C2B04
C4809 C3006
C2B07 C2D09 C2006 C2012 C2B09 C4012 C2D02 C2808 C2011 C3004 C3807 C3009 C4D02 C4B10 C4B13 C2B05 C2D10 C2813 C3D05 C3808 C3809 C4006 C4D11
SY27-2521-3
Line Name
+1/0 +TA +TC +TD +Ch Grant +Any Tag -Byte Tag -Halt
-SC1 Reset/not I/0 -SC1 Reset -SC5 Reset -1/0 Reset -Outbound Ctrl -Xmit Ctrl -Int or Ml Vhw -Val Dly 150-200 -Val Dly 250-300 -Any Val Lth +10 Mhz +2 Hz Free Run -Pwr Seq Complete
SC2
A3805 A3D10 A3B10 A3D02 A3B12 A4D05 A3D11 A4B07
A4812 A3D12 A4D09 A2812 A3D13 A2D13 A3007 A4004 A4804 A4D13 A4805 A3B03 A5D04
SC3 83805 83D10 83810 83D02 83812 84D05
84812 83D12 84D09
83D13
83D07
84D13 84805
SC4
C3805 C3D10 C3B10 C3D02 C3812 C4005 C3D11 C4807
C4D09 C2812 C3D13 C2D13 C3D07 C4D04 C4B04 C4D13 C4805 C3803 C5D04
(SC411 Cont, SC414)
5-SC-45
8140 Models A3X and A4X Board Wiring - SC5 to 01A-A2 Board Adapters
Line Name
-Valid Half Word -Parity Valid -End of Chain -IRR (HW) -CR Low -Exception -Modifier -Valid Byte 1 -IR/BI P1 -IR/BI 0 -IR/BI 1
-IR/Bl2
-IA/Bl 3
-IA/Bl 4 -IA/Bl 5 -IR/BI 6 -IA/Bl 7 -Valid Byte 1 (Byte) -IRR (Byte) -Ch Req Med -Ch Req Hi +5 Volts Ctrl -DB PH -DBO -DB 1 -DB2 -083 -084 -DB5
SSCF (SC5)
D2D07 D2B04 D2009 D2805 D3002 D2010 02812 D2D06 D4007 D2002 D2D04
D2B07
CA Adapter
E2D07 L2B02
E3B12 E3B09 E2B07 E3D06 E3B07
D3004 E3007
03B07 D4004 D4005 D4B07 D3012 D3013 D3B03 D4B05 D5D05 D4B12 D2B02 02808 D2011 D3B04 03007 D3B09
E3B10 E3D10 E3011 E3D12 E3803 E2D02 L2B13 L2B09 C5003 E2B02 E3B02 E3D02 E2D10 E3B08 E3004 E2D09
CA Adapter
CA Adapter
DA Diskette Adapter
G2007 L2803
J2007 L2804
G3B12 G3B09
J3B12 J3809
M5011 M5013 M4010 M4B05 M5007 M4013 M5D02
G3D06
J3D06
G2807
G3B07
J3B07
G3007
J3D07
J2D07
G3B10
J3810
G3010
J3010
G3011
J3011
G3012
J3012
G3803
J3803
G2D02
J2002
L2812
L2810
L2B08
L2B07
(just plain +5V)
G2B02
J2B02
G3802
J3802
G3D02
J3002
G2010
J2010
G3B08
J3808
G3004
J3004
G2009
J2009
M4BOB
Specials
M2B12 M3804 M2013 M3002 M3802 M3006 M3807
FA Disk Adapter 03B02 02005 02808 02809 03D02
02812
04010 05B04 05011 05B07 05D05 05010 05813
SV27-2521-3
5-SC-46
Line Name
SSCF (SC5)
CA Adapter
-DB6 -DB 7 -DBPL -DBS -DB9 -DB10 -DB 11 -DB12 -DB13 -DB14 -DB15 -TD
04B02 04010 D4013 02005 D2B10 D2013 D3B05 03B08 03009 D4D06 D4D11 D3B02
E2B09 E2006
E2805
-1/0 Op -Halt -TA -TC -System Reset -1/0 Op (Byte) -Ch Grant Lo -Ch Grant Hi (Special) -Release -10 Mhz
-Gate Inf Drvrs On (VE)
03D05 03D06 E3B04 03B10 E2005 03D10 E2808 03B12 E3005 D3B13 E2B04 D4D02 04804 L3B04 D4009 D5B0205002 C5D05 D5B05 H6B04
CA Adapter
G2B09 G2006
CA Adapter
J2B09 J2006
G2805
J2805
G3B04 G2005 G2B08 G3005 G2B04
L3B07
J3804 J2005 J2B08 J3005 J2B04
L3BOB
H4D11 F4011 F2011 H2D11 K2011 P3B10 M4005 04005 05006
DA Diskette Adapter
M3BOB M3B03 M2B10 M2D12 M3D04 M3809 M3007 M2010 M3009 M3805 M3005 M5D05
M5B09 M4D02 M5006 M5B05 M5B03
M5010 L3B09 M5802
FA Disk Adapter
05B08 04B10 05012 05B09 05B10 05002 05805 05013 05004 05007 05B12 04D02 P4B08 02D13 03D04 04B08
04B05 P3809
L3B10 P3013
8140 Model ASX Board Wiring - SC5 to 01 A-A2 Board Adapters
Line Name
-Val id Half Word -Parity Valid -End of Chain -IRR (HW) -CR Low -Exception -Modifier -Valid Byte 1 -IR/BI P1 -IR/81 0 -IR/81 1 -IR/81 2 -IR/81 3 -IR/8r 4 -IR/81 5 -IR/BI 6 -IR/81 7 -Val id Byte 1 (Byte) -IRR (Byte) -Ch Reg Med -Ch Reg Hi +5 Volts Ctrl -DB PH -DBO -DB 1 -DB2 -DB3 -DB4 -DB 5
SSCF (SC5)
D2007 D2B04 D2009 D2B05 D3D02 D2010 D2812 02006 04007 D2D02 D2004 D2807 D3004 D3807 04004 D4005 D4B07 03012 D3D13 D3B03 04805 D5005 D4812 D2802 02B08 02011 D3B04 D3007 03809
DA Diskette Adapter
G5D11 G5013 G4010 G4B05 G5007 G4013 G5002
FA Disk Adapter
F3B02 F2D05 F2B08 F2809 F3D02
F2812
G4B08
G2B12 G3804 G2013 G3D02 G3802 G3006 G3B07
F4D10 F5804 F5D11 F5B07 F5D05 F5D10 F5813
Line Name
-D86 -DB 7 -DB PL -D88 -DB 9 -DB 10 -DB 11 -D812 -0813 -D814 -D815 -TD
-1/0 Op -Halt -TA -TC -System Reset -1/0 Op (Byte) -Ch Grant Lo -Ch Grant Hi (Special) -Release -10 MHz
-Gate Inf Orvrs On (VE)
SSCF (SC5)
04802 04D10 D4D13 D2D05 02B10 D2D13 03B05 D3808 03009 D4006 04011 D3802
03D05 D3006 03810 03D10 03812 D3813 04002 04B04 D4D09 05B02D5002 C5005 05B05
DA Diskette Adapter G3B08 G3B03 G2810 G2012 G3D04 G3809 G3D07 G2D10 G3D09 G3805 G3D05 G5D05
G5809 G4D02 G5D06 G5805 G5B03
G5D10
G5802
E3B10 G4D05 F4005 F5D06
FA Disk Adapter
F5808 F4B10 F5D12 F5B09 F5810 F5D02 F5805 F5D13 F5004 F5007 F5812 F4002 E4808 F2013 F3004 G4808
F4B05 E3809
E3D13
SY27-2521-3
(SC414 Cont)
5-SC-47
8140 Model BXX - SC2, SC3, and SC4 Signal Path on A1 Board
Line Name
+Parity Valid Lth +SSCF IR +SSCF Mck -SSCF Pwr Outage -Pwr Seq Comp -Cr to Card 2 +IPR to Card 2 -IRR to Card 2 +Exception Lth +XS Tag Wrap
+oa Brdcst Cmd +oc Stat Cmd +oa Stat Cmd
+XB Crp Wrap +Inward +Pwr Outage Lth +Go +Enable Data Lths -10 Mhz -Parity Good +Load Chew Reg +Valid Hw Lth +Valid Byte 0 Lth +Valid Byte 1 Lth +Modifier Latch -EOC DOT -Data Out PO -Data Out 0 -Data Out 1 -Data Out 2 -Data Out 3 -Data Out 4 -Data Out 5 -Data Out 6 -Data Out 7 -Data Out P1 -Data out 8 -Data Out 9 -Data Out 10 -Data Out 11 -Data Out 12 -Data Out 13 -Data Out 14 -Data Out 15
SC2
C2D04 C5D09 C5D06
C5D04 C3B13 C4B08 C2D05 C2B10 C4D07
C2B02 C2B03 C4B09 C3D06 C3B04 C3B02 C5B04 C5B02 C4D10 C4B02 C2B07 C2D09 C2D06 C2D12 C2809 C4D12 C2D02 A2808 C2D11 C3D04 C3807 C3D09 C4D02 C4B10 C4B13 C2B05 C2D10 C2B13 C3D05 C3808 C3B09 C4D06 C4D11
SC3
84803
B4D07 82804 82802 82803 84809 B3D06 83804 83802 85804 A5803 84D10 84802 82807 82D09 82D06 82D12 82809 84D12 82D02 82808 B2D11 B3D04 83807 B3D09 84D02 84810
B2B05 B2D10 82813 83D05 83808 83D09 84D06 84D11
SC4 A2D04 A5D09 A5D06 A4803 A5D04 A3B13 A4B08 A2D05 A2B10 A4D07 A2804
A4809 A3D06
A2B07 A2D09 A2D06 A2D12 A2809 A4D12 A2D02 A2B08 A2D11 A3D04 A3807 A3D09 A4D02 A4810 A4813 A2B05 A2D10 A2813 A3D05 A3808 A3B09 A4D06 A4D11
SY27-2521-3
Line Name
+1/0 +TA +TC +TD +Ch Grant +Any Tag -Byte Tag -Halt -SC1 Reset/not 1/0 -SC1 Reset -SC5 Reset -1/0 Reset -Outbound Ctrl -Xmit Ctrl -Int or MI Vhw -Val Dly 150-200 -Val Dly 250-300 -Any Val Lth +10 Mhz +2 Hz Free Run -Pwr Seq Complete
SC2
C3B05 C3D10 C3810 C3D02 C3812 C4D05 C3D11 C4807 C4812 C3D12 C4D09 C2812 C3D13 C2D13 C3D07 C4D04 C4804 C4D13 C4B05 C3B03 C5D04
SC3 83805 83D10 83810 83D02 83812 84D05
84812 83D12 B4D09
B3D13
B3D07
B4D13 84805
SC4
A3B05 A3D10 A3B10 A3D02 A3812 A4D05 A3D11 A4807
A4D09 A2B12 A3D13 A2D13 A3D07 A4D04 A4804 A4D13 A4805 A3803 A5D04
5-SC-48
8140 Model BXX Board Wiring - SC5 to 01A-A2 Communications Adapter Board
Line Name
SC SSCF
CA Port 4
CA Port 3
-IA/Bl P1 -IA/Bl 0 -IR/BI 1 -IR/BI 2 -IR/BI 3 -IA/Bl 4 -IR/BI 5 -IR/BI 6 -IA/Bl 7 -Valid Byte 1 (Byte) -Parity Val id -IRR (Byte) -Valid Byte 1 (HW) -Valid HW -Valid Byte 0 -End of Chain -Exception -Modifier -Ch Req Lo -Ch Req Med** -Ch Req Hi** -IPR -DB PH -OBO -OB 1 -DB 2 -OB 3 -DB4 -OB5 -OB6 -087 -DB PL -088 -OB9 -0810 -OB 11 -0812 -0813 -0814 -0815 +5 Ve -TD Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Byte Tag -System Reset
A4007 A2002 A2004 A2B07 A3D04 A3B07 A4004 A4005 A4B07 A3012 A2804 A3013 A2006 A2007 A2B09 A2D09 A2D10 A2B12 A3002 A3B03 A4B05 A4B10 A4B12 A2802 A2B08 A2011 A3B04 A3007 A3809 A4802 A4010 A4013 A2005 A2810 A2013 A3805 A3808 A3009 A4D06 A4011 A2813 A3802 A3005 A3006 A3810 A3010 A3011 A3812
B3B12 83609 B3D06 83807 82B07 B3B10 B3D10 B3D11 B3D12 83B03 B2007 B2D02
G4B10
G4B05 G4013
B2B02 B3B02 83002 B2010 83808 83004 82D09 82809 B2006
C2011 82805
83804 82005 82008
83005
03B12 03609 03D06 D2B07 D3D07 D3B10 03D10 D3D11 03D12 03803 02007 02D02
G4B09
G4B04 G4011
02B02 03802 03002 02010 03808 03004 D2009 02809 D2006
E2011 02805
03804 02005 02808
03005
CA Port 2 F3812 F3B09_ F2B07 F3807 F3007 F3810 F3D10 F3011 F3012 F3B03 F2007 F2002
G4B08
G4B03 G4B13
F2B02 F3B02 F3002 F2010 F3B08 F3004 F2D09 F2B09 F2006
G2011 F2805
F3B04 F2005 F2808
F3005
CA Port 1 H3B12 H2B07 H3D06 H3B07 H3D07 H3810 H3D10 H3011 H3D12 H3B03 H2007 H2002
G4B07
G4B02 G4B12
H2B02 H3B02 H3D02 H2010 H3808 H3004 H2D09 H2809 H2D06
J2011 H2805
H3B04 H2005 H2808
H3005
To Board A-B2
K4007 K2002 K2004 K2B07 K3004 K3807 K4D04 K4005 K4B07 K3012 K2804 K3D13 K2006 K2D07 K2B09 K2009 K2010 K2B12 K3D02 K3B03 K4B05 K4B10 K4B12 K2B02 K2B08 K2011 K3B04 K3007 K3B09 K4B02 K4010 K4013 K2005 K2B10 K2013 K3B05 K3B08 K3009 K4006 K4011 K2813 K3B02 K3005 K3006 K3810 K3010 K3011 K3812
Line Name
-1/0 Tag (Byte) -Ch Grant Lo -Ch Grant Hi -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Med -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Release -Release Request
SC SSCF
CA Port4
A3B13 A4002 A4B04
B2B04
A4D12
G5812 G5B13
A4009 A4B08
G5012 G5D13
CA Port 3 02804
G5809 G5B10
G5010 G5011
CA Port 2 F2B04
G5B07 G5B08
G5006 G5007
CA Port 1 H2B04
G5803 G5B04
G5002 G5005
To Board A-B2 K3813 K4002
K4B04
K4D12 K4009
**Mutually exclusive.
***Illustrates Ch Grant (+) being passed through but not connected to any ports in the A 1 board and sent to the B1 board by wiring.
SY27-2621-3
(SC414 Cont)
5-SC-49
8140 Model BXX Board Wiring - 01A-B2 Disk/Diskette Adapter Board
Line Name
-Valid Byte -Valid HW -Parity Valid -End of Cha in -IRR -Chan Reg Lo -Modifier -IR/BI 0 -IR/BI 1 -IR/BI 2 -IR/BI 4 -IR/BI 5 -IR/BI 6 -IR/BI 7 -IR/BI P1 -DB PH -DB 0 -DB 1 -DB 2 -DB 3 -DB 4 -DB 5 -DB 6 -DB 7 -DB PL -DB 8 -DB 9 -DB10 -DB 11 -D812 -D813 -D814 -D815 +5 Ve
-TD Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Sys Reset
-;-Release -Ch Grant Lo -Ch Grant Lo Pass -Ch Grant Lo Pass
Lines From 01A-A2
A2D06 A2D07 A2804 A2D09 A2805 A3D02 A2812
DA Diskette
C5D02
C5D11 C5D13 C4D10 C4B05 C4D13
2nd FA Disk
F3B02 F2D05 F2B08 F2B09 F3D02
A3807 A4D04
A4B07
A4B12 A2802 A2808 A2D11 A3B04 A3D07 A3809 A4802 A4D10 A4D13 A2005 A2B10 A2013 A3B05 A3B08 A3D09 A4D06 A4D11 A2B13
A3802 A3D05 A3D06 A3B10 A3D10 A3B12
A4D09 A4D02
C4B08
C2B12 C3804 C2D13 C2D02 C3B02 C3D06 C3B07 C3B08 C3803 C2810 C2D12 C3D04 C3B09 C3D07 C2D10 C3D09 C3B05 C3D05 C4D05
C5D05 C5809 C4D02 C5D02 C5805 C5B03
C5B02 C5D10 C5B10
F2B12
F4D10 F5B04 F5D11 F5B07 F5D05 F5D10 F5B13 F5B08 F4B10 F5D12 F5B09 F5B10 F5D02 F5B05 F5D13 F5D04 F5D07 H5812 F4D05 F5D06 F4D02 F2D13 F3D04 F4808
F4B05 G3B09 G3D13
F3B03
1st FA Disk
H3802 H2D05 H2B08 H2B09 H3D02
H2812
H4D10 H5B04 H5D11 H5B07 H5D05 H5D10 H5813 H5B08 H4B10 H5D12 H5B09 H5B10 H5002 H5805 H5D13 H5D04 H5007 H5812 H4D05 H5D06 H4D02 H2D13 H3D04 H4808
H4B05 J3B09 J3D13
H3803
SV27-2521-3
8140 Model BXX Board Wiring - SC5 to 01A-C2 or 01A-D2 Tape Adapter Boards
Line Name
-Valid Byte -Valid HW -Parity Valid -End of Chain -IRR -Chan Req Lo -Modifier -IR/BI 0 -IR/BI 1 -IR/BI 2 -IR/BI 3 -IR/BI 4 -IR/BI 5 -IR/BI 6 -IR/BI 7 -IR/BI P1 -DBPH -DBO -DB 1 -DB2 -DB3 -DB4 -DBS -DB6 -DB7 -DBPL -DBS -DB9 -D810 -D811 -DB12 -D813 -D814 -D815 +5Ve -TD Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Sys Reset -Release -Ch Grant Lo -Ch Grant Lo Pass -Ch Grant Lo Pass
Cable or
SC5 SSCF
A2D06 A2D07 A2B04 A2D09 A2B05 A3D02 A2B12
TA Tape
G3D11 G3D02 G3B03 G3D05 G3B08 G3B10 G5813
A4D05 G3D10
A4B12 A2B02 A2B08 A2D11 A3B04 A3D07 A3809 A4B02 A4D10 A4D13 A2D05 A2B10 A2D13 A3B05 A3808 A3D09 A4D06 A4D11 A2813 A3B02 A3D05 A3D06 A3B10 A3D10 A3B12 A4D09 A4D02
G4804 G4805 G4803 G4D06 G4809 G4807 G4D11 G4D05 G4D12 G4009 G4D13 G4B12 G4810 G4D10 G4813 G4004 G4808 G4D07 H5B02 G3D09 G2B12 G3B09 G5B04
G2805 H3D02
G3807 G3D07
5-SC-50
8140 Model BXX Board Wiring - SC5 to 01A-C2 or 01A-D2 Communications Adapter Board
Line Name
-IR/81 P1 -IR/81 0 -IR/81 1 -IR/81 2 -IR/81 3 -IR/814 -IR/81 5 -IR/81 6 -IR/81 7 -Valid Byte 1 (Byte) -Parity Valid -IRR (Byte) -Valid Byte 1 ( HW) -Valid HW -Valid Byte 0 --End of Chain -Exception -Modifier -Ch Req Lo -Ch Req Med** -Ch Req Hi** -IPR -OBPH -080 -081 -08 2 -OB 3 -084 -085 -086 -087 -08PL -088 -089 -0810 -0811 -0812 -0813 -0814 -0815 +5 Ve -TO Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Byte Tag -System Reset
SC SSCF
CA Port 8/12
A4007 83812 A2002 83809 A2004, 83006 A2807 83807 A3004 82807* A3807 83810 A4004 83010 A4005 83011 A4807 83012* A3012 83803 A2804 82007 A3013 82002 A2006 A2007 A2809 A2009 G4B10 A2010 A2812 A3002 A3803 G4805 A4805 G4013 A4810 A4812 82802 A2802 83802 A2808 83002 A2011 82010 A3804 83808 A3007 83004 A3809 82009 A4802 82809 A4010 82006 A4013 A2005 A2810 A2013 A3805 A3808 A3009 A4006 A4011 A2813 C2011 A3802 82805 A3005 A3006 83804 A3810 82005 A3010 82008 A3011 A3812 83005
CA Port 7/11 03812 03809 03006 02807* 03007 03810 03010 03011 * 03012 03803 02007 02002
G4809
G4804 G4011
02802 03802 03002 02010 03808 03004 02009 02809 02006
E2011 02805
03804 02005 02808
03005
CA Port 6/10 F3812 F3809 F2807* F3B07 F3007 F3810 F3010* F3011 F3012 F3B03 F2007 F2002
G4808
G4803 G4813
F2802 F3802 F3002 F2010 F3808 F3004 F2009 F2809 F2006
G2011 F2805
F3804 F2005 F2808
F3005
CA Port 5/9 H3812 H2807* H3006 H3B07 H3007 H3810* H3010 H3011 H3012 H3803 H2007 H2002
G4807
G4802 G4812
H2802 H3802 H3002 H2010 H3808 H3004 H2009 H2809 H2006
J2011 H2805
H3804 H2005 H2808
H3005
To Board A-02
K4007 K2D02 K2004 K2807 K3004 K3807 K4004 K4005 K4807 K3012 K2804 K3013 K2D06 K2007 K2809 K2009 K2010 K2812 K3002 K3803 K4805 K4810 K4812 K2802 K2808 K2011 K3804 K3007 K3809 K4802 K4010 K4013 K2005 K2810 K2013 K3805 K3808 K3009 K4006 K4011 K2813 K3802 K3005 K3006 K3810 K3010 K3011 K3812
Line Name
-1/0 Tag (Byte) --Ch Grant Lo -Ch Grant Hi -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Med -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Release -Release Request
SC
SSCF
CA Port 4
A3813 A4002 A4804
82804
A4012
G5812 G5813
A4009 A4808
G5012 G5013
CA Port 3 02804
G5809 G5810
G5010 G5011
CA Port 2 F2804
G5807 G5808
G5006 G5007
CA Port 1 H2804
G5803 G5804
G5002 G5005
To Board A-02 K3813 K4002
K4804
K4012 K4009
*If A202 board: H2807 = H3809
F2807 = F3006 02807 = 03807
82807 = 83007
**Mutually exclusive.
H3810 = H2807 F3010 = F2807 03011 = 02807 83012 = 82807
***Illustrates Ch Grant (+) being passed through but not connected to any ports in the A 1 board and sent to the 81 board by wiring.
SY27-2521-3
(SC414 Cont)
5-SC-51
8140 Model BXX Board Wiring - SC5 to 01A-C2 or 01A-D2 Display/Printer Adapter Board
Line Name
-IRR -Ch Req Lo -End of Chain -Valid HW -IR/817 -DB PH -DB 0 -DB 1 -DB 2 -DB 3 -DB4 -DB 5 -DB6 -DB 7 -DB PL -DB 8 -DB 9 -0810 -DB 11 -DB12 -DB13 -DB14 -0815 +5Ve
-TD Tag -1/0 Tag -Halt Tag -TA Tag -Sys Reset -Release -Ch Grant Lo
Cable or
SC5
A2B05 A3D03 A2009 A2007 A4B07 A4B12 A2B02 A2B08 A2D11 A3B04 A3D07 A3B09 A4B02 A4D10 A4D13 A2D05 A2810 A2D13 A3805 A3808 A3D09 A4D06 A4011 A2B13
Display/ Printer Cards
E4813 B2D05 84D09 82805 E4D13 C3B04 C3D06 C3B05 C2D09 C3B02 C3D02 C2810 C3B03 C2D12 C3D12 C4B04 C4D04 C4D02 C4D07 C4802 C4D05 C3D11 C3B13 H2D13
A3B02 A3D05 A3006 A3B10 A3B12 A4D09 A4D02
B4B02 E5B03 E4002 E2006 E2004 C5B09 E2808
J2013 E2002
K2013 H4013
K4D13 J4013
SY27-2521-3
5-SC-52
SC417 8101 SCF Point-to-Point Net Listing
8101 Model A25 Board Wiring - SC5 to 01A-A2 Disk/Diskette/ Tape Adapter Board
Line Name
-Valid Byte -Valid HW -Parity Val id -End of Chain -IRR -Chan Req Lo -Modifier -IA/Bl 0 -IR/BI 1 -IA/Bl 2 -IA/Bl 3 -IR/BI 4 -IR/BI 5 -IA/Bl 6 -IA/Bl 7 -IA/Bl P1 -DB PH -DBO -DB1 -DB2 -DB3 -DB4 -DB 5 -DB 6 -DB 7 -DB PL -DBS -OB9 -0810 -DB 11 -DB12 -DB13 -DB14 -DB15 +5 Ve
-TD Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Sys Reset
-Release -Ch Grant Lo -Ch Grant Lo Pass -Ch Grant Lo Pass
SC5 SSCF
A2006 A2D07 A2B04 A2D09 A2B05 A3D02 A2B12 A2002 A2D04
A3D04
TA Tape B3D11 B3D02 B3B03 B3D05 B3B08 B3B10 B5B13
B3D10
A4B07
A4B12 A2B02 A2B08 A2D11 A3B04 A3D07 A3B09 A4B02 A4010 A4013 A2005 A2B10 A2013 A3B05 A3B08 A3009 A4006 A4011 A2B13
A3B02 A3D05 A3006 A3810 A3D10 A3812
A4009 A4002
B4B04 B4B05 B4B03 B4D06 B4B09 B4B07 B4011 B4005 B4012 84009 84013 B4B12 84810 B4010 84813 B4004 B4B08 84007 C5B02
B3D09 82812 83809 85804
82005
C3002
83807 83007
2nd FA Disk
F3B02 F2D05 F2B08 F2B09 F3D02
F2B12
F4D10 F5B04 F5D11 F5B07 F5D05 F5D10 F5B13 F5B08 F4B10 F5D12 F5B09 F5B10 F5002 F5B05 F5D13 F5D04 F5D07 F5B12 F4D05 F5D06 F4D02 F2D13 F3D04 F4B08
F4B05 G3B09 G3013
F3B03
DA Diskette
G5D02
G5D11 G5D13 G4010 G4B05 G4D13
1st FA Disk
H3B02 H2D05 H2B08 H2B09 H3002
H2B12
G4B08
G2B12 G3B04 G2D13 G3D02 G3B02 G3D06 G3B07 G3B08 G3B03 G2B10 G2012 G3004 G3B09 G3007 G2D10 G3009 G3B05 G3D05 G4D05
G5D05 G5809 G4D02 G5D02 G5B05 G5B03
G5802 G5D10 G5810
H4D10 H5B04 H5D11 H5B07 H5005 H5D10 H5813 H5808 H4810 H5D12 H5809 H5B10 H5D02 H5805 H5D13 H5004 H5007 H5B12 H4D05 H5D06 H4D02 H2D13 H3D04 H4B08
H4B05 J3809 J3013
H3B03
8101 Board Wiring - SC5 to 01A-A1 or 01A-B1 Communications Adapter Board
Line Name
-IA/Bl P1 -IR/BI 0 -I R/81 1 -IA/Bl 2 -IR/BI 3 -IR/BI 4 -IR/BI 5 -IR/81 6 -IA/Bl 7 -Valid Byte 1 (Byte) -Parity Valid -IRA (Byte) -Valid Byte 1 (HW) -Valid HW -Valid Byte 0 --End of Chain -Exception -Modifier -Ch Req Lo -Ch Aeq Med** -Ch Req Hi** -IPR -DB PH -DB 0 -DB 1 -DB 2 -DB 3 -DB4 -DB 5 -DB 6 -DB 7 -DB PL -DBS -DB 9 -DB10 -DB 11 -DB12 -DB13 -DB 14 -DB15 +5 Ve -TD Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Byte Tag -System Reset
SC SSCF
A4D07 A2D02 A2D04 A2807 A3004 A3807 A4D04 A4D05 A4807 A3012 A2B04 A3D13 A2D06 A2D07 A2B09 A2D09 A2D10 A2B12 A3D02 A3B03 A4B05 A4810 A4B12 A2802 A2B08 A2D11 A3804 A3D07 A3B09 A4B02 A4D10 A4D13 A2D05 A2B10 A2013 A3B05 A3808 A3009 A4006 A4011 A2813 A3B02 A3005 A3006 A3B10 A3010 A3D11 A3812
CA Port 4 B3B12 B3809 B3D06 83807 B2B07* 83B10 B3D10 B3011 83012* B3B03 B2007 B2D02
G4810
G4B05 G4013
82802 83802 B3002 B2010 B3808 B3D04 B2D09 B2809 B2D06
C2011 B2805
B3804 B2005 82D08
83005
CA Port 3 D3B12 D3B09 D3D06 D2807* D3007 D3B10 D3D10 D3011 * 03D12 D3803 D2D07 D2002
G4809
G4804 G4011
D2802 D3B02 D3D02 02010 03B08 03D04 D2009 D2809 02006
E2011 02805
03804 02005 02808
03005
CA Port 2 F3B12 F3809 F2807* F3B07 F3007 F3B10 F3010* F3011 F3012 F3803 F2007 F2002
G4B08
G4B03 G4B13
F2802 F3802 F3002 F2010 F3808 F3004 F2009 F2809 F2D06
G2011 F2805
F3804 F2005 F2808
F3005
CA Port 1 H3812 H2807* H3D06 H3807 H3007 H3810" H3D10 H3D11 H3D12 H3B03 H2D07 H2D02
G4807
G4802 G4B12
H2802 H3B02 H3D02 H2D10 H3B08 H3D04 H2D09 H2B09 H2006
J2011 H2805
H3804 H2D05 H2808
H3005
To Board A-82
K4D07 K2D02 K2004 K2807 K3D04 K3B07 K4D04 K4D05 K4B07 K3012 K2B04 K3D13 K2006 K2D07 K2B09 K2D09 K2D10 K2B12 K3D02 K3B03 K4805 K4B10 K4B12 K2B02 K2B08 K2D11 K3B04 K3007 K3B09 K4B02 K4D10 K4D13 K2D05 K2B10 K2013 K3B05 K3B08 K3009 K4D06 K4011 K2B13 K3B02 K3005 K3D06 K3810 K3D10 K3011 K3812
Line Name
-1/0 Tag (Byte) ··Ch Grant Lo -Ch Grant Hi -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Med -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Ch Grant Pass -Release -Release Request
SC SSCF
CA Port 4
AJB13 A4002 A4804
82B04
A4012
G5B12 G5813
A4D09 A4B08
G5012 G5D13
CA Port 3 D2804
G5B09 G5B10
G5D10 G5D11
CA Port2 F2804
G5B07 G5B08
G5D06 G5007
CA Port 1 H2804
G5803 G5804
G5002 G5005
To Board A-82 K3B13 K4D02
K4B04
K4012 K4D09
*If A181 board: H2B07 = H3B09
F2807 = F3006
D2B07 = D3B07
B2B07 = 83007
H3810 = H2B07
F3D10 = F2807
D3D11 = D2B07
83012 = B2807
**Mutually exclusive.
***Illustrates Ch Grant(+) being passed through but not connected to any ports in the A1 board and sent to the B1 board by wiring.
SY27-2521-3
(SC414 Cont, SC417)
5-SC-53
8101 Board Wiring (All Models Except A25) - SC5 to 01A-A2 Disk/Diskette/
Tape Adapter Board
Line Name
SC5 SSCF
TA Tape
-Valid Byte
A2D06 B3D11
-Valid HW
A2D07 B3D02
-Parity Valid
A2804 B3B03
-End of Chain
A2D09 83D05
-IRR
A2805 83808
-Chan Req Lo
A3D02 83B10
-Modifier
A2812 B5B13
-IR/BI 0
A2D02
-IR/BI 1
-IR/Bl 2 -IR/BI 3
A3D04 83D10
-IR/Bl 4
-IR/Bl 5
-IR/BI 6
-IR/BI 7
A4B07
-IR/Bl P1
-DB PH
A4812 B4804
-DBO
A2B02 84B05
-DB 1 -DB2
A2B08 A2D11
B4803 84D06
-DB 3 -DB4
A3B04 A3D07
84B09 84B07
-DB 5 -DB6 -DB 7
A3B09 A4802 A4D10
84011 84D05 84D12
-DB PL
A4D13 B4D09
-DBS
A2D05 B4D13
-DB9
A2810 84B12
-DB10
A2D13 84810
-DB 11
A3805 84D10
-0612
A3808 84B13
-DB13
A3D09 B4D04
-D814
A4D06 84808
-DB15 +5 Ve
A4D11 A2813
84007 C5802
-TD Tag -1/0 Tag -Halt Tag -TA Tag -TC Tag -Sys Reset
A3802 A3005 A3D06 A3B10 A3D10 A3812
83D09 82812 83809 85804
82005
-Release -Ch Grant Lo -Ch Grant Lo Pass -Ch Grant Lo Pass
A4D09 A4D02
C3D02
83807 B3D07
DA Diskette G5D02
G5D11 G5D13 G4D10 G4805 G4D13
FA Disk
H3B02 H2D05 H2808 H2B09 H3D02
H2812
G4808
G2B12 G3B04 G2D13 G3002 G3B02 G3D06 G3B07 G3B08 G3B03 G2B10 G2D12 G3D04 G3809 G3D07 G2D10 G3D09 G3B05 G3D05 G4D05
G5D05 G5809 G4D02 G5002 G5B05 G5803
G5802 G5D10 G5810
H4D10 H5804 H5D11 H5807 H5D05 H5D10 H5813 H5808 H4810 H5012 H5B09 H5B10 H5002 H5805 H5D13 H5D04 H5D07 H5812 H5D05 H5006 G4002 H2D13 H3D04 H4808
H4805 J3809 J3D13
H3803
SY27-2521-3
8101 Board Wiring - SC5 to 01A-A1 or 01A-B1 Display/Printer Adapter Board
Line Name
-IRR -Ch Req Lo -End of Chain -Valid HW -IR/817 -DB PH -DBO -DB 1 -DB 2 -DB 3 -DB4 -DB 5 -DB6 -DB 7 -DB PL -DB 8 -DB 9 -DB10 -DB 11 -0812 -DB13 -DB14 -DB15 +5Ve
-TO Tag -1/0 Tag -Halt Tag -TA Tag -Sys Reset -Release -Ch Grant Lo
SC5
A2805 A3D03 A2D09 A2D07 A4B07 A4812 A2B02 A2808 A2D11 A3B04 A3D07 A3B09 A4B02 A4D10 A4D13 A2D05 A2B10 A2D13 A3B05 A3808 A3D09 A4006 A4D11 A2B13
Display/ Printer Cards
E4B13 B2D05 84009 82805 E4D13 C3804 C3006 C3B05 C2D09 C3B02 C3D02 C2B10 C3B03 C2D12 C3D12 C4B04 C4D04 C4D02 C4007 C4B02 C4D05 C3011 C3B13 H2D13
A3B02 A3D05 A3D06 A3810 A3B12 A4009 A4D02
84802 E5B03 E4002 E2D06 E2004 C5B09 E2808
J2D13 E2002
K2D13 H4D13
K4D13 J4013
5-SC-54
SC420 Card Wiring Charts
Figure SC420-1 through SC420-5 are wiring charts that show SCF card and connector pin assignments.
Board Signal Names
SC1 & SC7 Cards
SC7 Card TCC Signal Names Board Pins
- PIO Data 0 (0.0)
802
Spare
D02
- PIO Data 14 (1.6)--- 803
+ SV
D03
- PIO Data 3 (0.3)
804
- PIO Data 4 (0.4)
D04
- PIO Data 5 (0.S)
80S
- PIO Data 8 (1.0)
D05
-SV
806
- PIO Data 7 (0.7)
D06
- PIO Data PO (O.P)
B07
- PIO Data 6 (0.6)
D07
- PIO Data 1 (0.1)
808
GND
DOB
- PIO Data 12 ( 1 . 4 ) - 809
- PIO Data 11 (1.3) - - - D09
- PIO Data 9 (1.1)
810
-PIO Data 13 (1.5)
D10
+ 8.SV
811
- PIO Data 2 (0.2)
D11
- PIO Data 1S (1.7)
812
-Save PSW
D12
- PIO Data P1 (1.P)
813
- PIO Data 10 (1.2)
D13
W22
GND~W02
W23 W03 W24 W04 W2S W05 W26 W06 W27 W07 W28 W08 W29 W09 W30 W10 W31 W11 W32
~W12
W33 W13
PIO Data 0 (0.0) SC Present PIO Data 14 (1.6) GND PIO Data 3 (0.3) PIO Data 4 (0.4) PIO Data S (0.S) PIO Data 8 ( 1.0) GND PIO Data 7 (0.7) PIO Data PO (0.P) PIO Data 6 (0.6) PIO Data 1 (0.1) GND PIO Data 12 (1.4) PIO Data 11 (1.3) PIO Data 9 (1.1) PIO Data 13 (1.5) GND PIO Data 2 (0.2) PIO Data 15 (1.7) Data In 6 (0.6) PIO Data P1 (1.P) PIO Data 10 (1.2)
B02 D02 B03 003 B04 D04 B05 D05 B06 D06 807 D07 BOB DOB 809 009
B10 D10 B11 D11
812 D12 813 D13
+TD Tag - LVL N Request 2
G02
J02~
- Exception
G03
+ 5V
J03
- Modifier
G04
- End of Chain
J04
-PV
GOS
-1/0 Tag
JOS
-5V
G06
-Valid Hw
JOG
- Wait State Gate 10 - - G07
-V81
J07
Spare
GOS
GND
J08
- Irr
G09
- Halt
J09
-TA Tag
G10
-TC Tag
J10
+ B.5V
G11
- Byte Tag
J11
-VBO
G12
- Ch Grant
J12
- Wait State Out
G13
- Ch Request
J13
X22 X02 · X23 X03 X24 X04 X25 X05 X26 X06 X27 X07 X28
xoa
X29 X09 X30 X10 X31 X11 X32 X12
-----< X33
X13
TDTag Valid Hw Exception GND Modifier End of Chain PV 1/0 Tag GND 1/0 Tag (B) V81 (Bl VB1 Irr (8) GND Irr Halt TATag TC Tag GND Byte Tag VBO Ch Grant Hi Ch Req Hi Ch Req Low
G02 J02 G03 J03 G04 J04 G05 J05 G06 JOO G07 J07 GOS JOB G09
J09 G10 J10 G11 J11 G12 J12 G13 J13
- Dest 12 6 -Dest136 - Dest 14 6 + 5V
M02 P02 M03 P03
Y22 + VE (- Por)
Y02
Ch Grant Low
~Y23
Data In 12 (1.4)
Y03
GND
M02 P02 M03 P03
Figure SC420-1. SC1 and SC7 Card and Connector Signals
Board Signttl Names
- Dest 15
M04
_... 7
- Restart
P04<-
-1 MHz + PMO
MOS~
P05
..,__...
-5V - Monitor
M06
P06
...!.>..I
+VE (-POR)
M07~
- SDCI 8us(BOP) Sel'td - - P07
.~ ,.
- SDCI Bus Halt
MOB~
GND
POS
+ RAM/-ROS Acc'bl 3 --M09 E--
- BOP CT/CK (X2 Dec)--P09 ~
- BOP PNL/CK (X4 Dec)-M10E--
+ 60 Hz Ctrl
P10~
+ 8.5V
M11
- 50/60 Hz
P11~
- 500 Ms Rate (2Hz) --M12 :>
- BOP lrpt
P12~
-1.02 Ms Rate (1 KHz)-M13<E--
- 500 Ms Rate (2 Hz) - - P13 E-
-1.02 Ms Rate (1 KHz)--S02')
-10 MHz -1/0 OP
U02)
S03 <E-
+ SV
U03
- PB Request - System Reset
S04
=>
U04 E
- SDCI Bus 2
S05~
-SDCI Bus 7 -5V -SDCI Bus6 - HFP lrpt
U05~
sos
U06~
S07 ~
- SDCI Bus 3
U07~
-SDCI Bus4 GND
SOB~
uos
-SDCI Bus 1
S09~
-SDCI Bus 0
U09~
- SDCI Bus 5
S10~
Spare
U10
+8.5M
S11
Spare - SDCI Bus P
U11
S12~
- Power Off To PS 5 - - - U12 ~
- Read Gate Drivers - - - S13 ~
- SDCI Bus Sync
U13~
SY27-2521-3
I
1
J
SC1 & SC7 Cards
TCC Signal Names
SC7 Card Board Pins
~Y24 - IR/81-0 ' E- -Y04 - IR/81-S +--Y2S - IR/B1-2
~Y05 - IR/81-6
Y26
·~Y06 -Y27
+ -Y07
-
-
-
GND IR/B1-1 IR/81-7 IR/B1-P
8130
> alone
~Y28 - IR/81-4
Y08 ~ Y29
GND
- IR/81-3
~ Y09 - Release
(
Y30 - lpr
<E-- Y10 - Data In 11 (1.3)
Y31
~Y11
GND
- SC1 Reset (Ext)
~Y32 - SCF-B Lvl N
- )' Y12
500 Ms Rate (2 Hz)
~Y33 ~Y13
- 10 MHz (Repow'rd)
- 1/0 Reset
Z22
~ Z02
~ Z23 ~ Z03
.~.......,.,. Z24
._,.)...
Z04 Z25
~ Z05
-:;:: Z26
~ Z06
Z27
Z07
.....
"'7
Z28
Z08
-' Z29 ~ Z09
~ Z30
~ Z10
__.,,,,., Z31
Z11
_..
7
Z32
Z12
Z33
Z13
Interlock
- 1.024 Ms Rt (1 KHz)
- SDCIBusO
- SOO Ms Rate (2Hz)
- SDCI Bus 1
- l/OOP
- 5DCI Bus 2 - 1 MHz
- SDCI Bus 3
- SDCI Bus Sync
GND
Spare
- SDC1Bus4
GND
- SDCI Bus S
- System Reset
- SDCI Bus6
- PB Reset Req - 5DCI Bus 7
Spare
- SDCI Bus P
Spare
Interlock
Spare
M04 P04 MOS P05 M06 P06 M07 P07 MOS P08 M09 P09 M10 P10 M11
P11 M12 P12 M13 P13
S02 U02 503 U03 S04 U04
sos
U05 506 U06 507 U07
sos uos
509 U09 S10 U10 511 U11 512 U12 S13 U13
(SC417 Cont, SC420)
5-SC-55
Board Signal Names
+ Oc Stat Cmd - Data Out Bus 0 + 08 Stat Cmd + 5 Volts
+ Parity Val Lth - Data Out Bus 8 - Irr to Card 2
+ Val Byte 1 Lth +Val Hw lth
- Data Out Bus 1 GND
- End of Chain + Val Byte 0 lth + Exception lth - Data Out Bus 9
- Data Out Bus 2 - 10 Reset To LLD + Modifier Lth - Data Out Bus 10 - Xmit Ctrl
> - B02
<- D02 >-- B03
>- D03
-B04
>- D04' < - B05
>-D05
- B06
> - D06
> - B07
- D07 <-Boa
- DOB
> - B09 >- D09 > - B10 <- D10
- B11
< - D11 >- B12
>- D12
< - B13
< - D13
+Go +TD
2 Hz Free Run + 5 Volts + Pwr Outage lth - Data Out Bus 3
>-- G02 < - J02 < - G03 >-- JOJ > - G04 < - J04
+ 1/0
<-G05
< - - Data Out Bus 11
J05
+ Inward - Data Out Bus 4 - Int or ML Vhw
-G06
>-- J06 < - G07
<>-- J07
- Data Out Bus 12 <-GOS
GND
- JOB
- Data Out Bus 13 - Data Out Bus 5 +TC +TA
< - G09
< - J09 < - G10 <- J10
- Byte Tag To LLD +Ch Grant - SC1 Reset
- G11
< - J11 < - G12 <- J12
-CR to Card 2 - Outbound Ctrl
<-G13
< - J13
1/0 Pin Assignments
5 5,3 5
3 5,3 3
3 3
5,3
3 3 3 5,3
5 3 3 5,3 3
5 6,3 3 3 5 5,3 5 5, 3
5 5,3 5 5, 3
5,3 5, 3 5,3 5,3
3 5 5 3 5,3
Figure SC420-2. SC2 Card and Connector Signals
W22 W02 W23 W03 W24 W04 W25 W05 W26 W06 W27 W07 W28
woe
W29 W09 W30 W10 W31 W11 W32 W12 W33 W13
X22 X02 X23 X03 X24 X04 X25 X05 X26 X06 X27 X07 X28 XOB X29 X09 X30 X10 X31 X11 X32 X12 X33 X13
TCC Signal Names
PIO Data 0 (0.0) SC1 Present PIO Data 14 (1.6) GND PIO Data 3 (0.3) PIO Data 4 (0.4) PIO Data 5 (0.5) PIO Data 8 (1.0) GND PIO Data 7 (0.7) PIO Data PO (0.P) PIO Data 6 (0.6) PIO Data 1 (0.1) GND PIO Data 12 (1.4) PIO Data 11 (1.3) PIO Data 9 (1.1) PIO Data 13 (1, 5) GND PIO Data 2 (0.2) P10 Data 16 (1.7) Data In 6 (0.6) PIO Data P1 (1.P) PIO Data 10 (1.2)
TD Tag Valid Hw Exception GND Modifier End of Chain PV 1/0 Tag GND 1/0 Tag (B) VB1 (8) VB1 Irr (B)
GND Irr Halt TA Tag TC Tag GND Byte Tag VBO Ch Grant Hi Ch Req Hi Ch Req Low
SY27-2521-3
5-SC-66
Board Sipnal Names
< - + Load Chew Reg
M02
- Data Out Bus 6 < - P02
M03
+ 5 Volts
> - P03
< - - Val Dly 250-300
M04
< - - Val Dly 150-200
P04
+ 10 MHz
< - M05
+Any Tag
< - P05
M06
< - - Data Out Bus 14
P06
- Halt To Lid
< - M07
+XS Tag Wrap + IPR To Card 2
> - P07 >-- MOS
GND
POS
+XS Crp Wrap
> - M09
- SSCF Res To lid < - P09
- Data Out Bus 7 < - M10
- Parity Good
< - P10
M11
- Data Out Bus 15 < - P11 - SCFA Res/Not 10 < - - M12
< - - Data Out Bus PO
P12
< - - Data Out Bus P1
M13
-Any Val Lth
< - P13
5 5, 3
3 3 5,3 5,3
5,3 3 5.3 3
5 5, 3 5, 3 5
5, 3 5 5,3 5,3 6, 3
1/0 Pin Assignments
S02
U02
S03
+ 5 Volts
> - U03
>-- + Enable Data lths
S04
5
> - - Power Seq Comp
U04
3
S05
U05
+SSCF MCK
S06
>-- U06 S07
U07
SOB
GND
U08
509
+ SSCF IR
>- U09
3
S10
U10
S11
U11
S12
U12
513
U13
Note: "1" indicates a signal is from/to SC1; "3" indicates a signal is from/to SC3; "5" indicates a signal is from/to SC4.
TCC Signal Names
--Y22 + Ve (-POR)
-
Y02
Ch Grant Low
- - Y23
Data In 12 (1.4)
- - Y03
GND
- - Y24
IR/B1-0 '
--Y04
IR/B1·5
--Y25
IR/B1·2
-
Y05
IR/B1-6
-Y26
GND
-Y06
IR/B1-1 >Not Used
- - Y27
IR/B1-7
-
Y07
IR/B1-P
--Y2B
IR/B1-4
-
YOB
GND
- - Y29
IR/B1 ·3
- - Y09
Release
-
Y30
IPR
-
Y10
Data In 11 (1.3)
--Y31
GND
- - Y11
SC1 Reset (EXT)
--Y32
PSCF Bstat
--Y12
500 Ms Rate (2Hz)
--Y33 --Y13
10 MHz (Repow'rd) 1/0 Reset
3 --Z22
3 --zo2
3 --Z23
--Z03
3 - - Z24
3 -
Z04
3 - - Z25
3 - - Z05
-
Z26
3 --Z06
3 -Z27
3 --Z07
3 --Z28
--ZOB
3 - - Z29
3 - - Z09 3 --Z30
3 -z10
--Z31
3 - - Z11
3 -Z32
3 --Z12
-Z33
-Z13
+ Data In PO + Data In 0 + Data In 1
GND
+ Data In 2 + Data In 3 + Data In 4
+ Data In 5
GND
+ Data In 6 + Data In 7
+ Data In P1
+ Data In 8
GND + Data In 9
+ Data In 10
+ Dataln11 + Data In 12
GND + Data In 13 + Data In 14 + Data In 15
Board Signal Names
1/0 Pin Assignments
+ OC Status Cmd < - - B02
2
- Data Out Bus 0 <>-- D02
2
+ OS Stat Cmd < - - B03
2
+ 5 Volts
>-- D03
+ 08 Broadcast < - - B04
3
D04
- Data Out 8
>-- BOS
2
D05
B06
> - - + Valid Byte 1
D06
3
> - - + Valid Halfword
B07
3
D07
- Data Out Bus 1 <>-- BOS
2
GND
DOS
-EOC
> - B09
3
+Valid Byte 0 > - - 009
3
810
> - - - Data Out Bus 9
010
3
B11
> - - Data Out Bus 2 (
D11
3
812
> - - + Modifier Lth
D12
3
- Data Out 10 > - - B13
2
D13
+GO
<-- G02
2
+TD
>-- J02
2
G03
+ 5 Volts
> - J03
+ Pwr Outage Lth < - - G04
2
- Data Out Bus 3 <>-- J04
2
+ -
10 Data
Out
Bus
1 1
>> -- --
G05 J05
2 2
G06
+ Inward
<-·- J06
3,2
- Data Out Bus 4 < > - - G07
2
- Int/ML Vhw
J07
>> ---- - Data Out Bus 12
GOB
3, 2 2
GND
JOB
> - - - Data Out Bus 13
G09
2
- Data Out Bus 5 > - - J09
2
+TC
>-- G10
2
+TA
>-- J10
2
G11
J11
+CG
>-- G12
2
-SC1 Reset
>-- J12
2
G13
- Outbound Ctrl < - - J13
3, 2
> - - + Load Chew Reg
M02
2
- Data Out Bus 6 <> - - P02
2
- SSCF Pwr Out > - - M03
3
+ 5 Volts
>-- P03
M04
P04
10MHz
>-- M05
2
+Any Tag
>-- P05
2
M06
- Data Out Bus 14 > - - P06
2
M07
Figure SC420-3. SC3 Card and Connector Signals
W22 W02 W23 W03 W24 W04 W25 W05 W26 W06 W27 W07 W28 W08 W29 W09 W30 W10 W31 W11 W32 W12 W33 W13
X22 X02 X23 X03 X24 X04 X25 X05 X26 X06 X27 X07 X28 XOB X29 X09 X30 X10 X31 X11 X32 X12 X33 X13
Y22 Y02 Y23 Y03 Y24 Y04 Y25 Y05 Y26 Y06 Y27
TCC Signal Names GND GND GND GND
GND GND GND GND
GND GND
Board Signal Names
< - +XS Tag Wrap
P07
MOS
GND
<-.- POS
+XS CrpWrap <-- M09 - SSCF Res To Lid < - - P09 - Data Out Bus 7 <>-- M10
- Parity Good > - - P10
M11
> - - - Data Out Bus 15
P11
- 5CFA Res/Not 10>-- M12
- Data Out PO < - - P12
M13
- Any Valid Lth >--- P13
+ 5 Volts + Enbl Data Lths
GND
502 U02 503
>-- U03 <-- 504
U04 505 U05 506 U06 507 U07
sos uos
509 U09 510 U10 511 U11 512 U12 513 U13
Note: "2" indicates a signal is from/to SC2; "3" indicates a signal is from/to SC4.
1/0 Pin Assignments 2,3
3,2 3 2 2 2 2 3 2
2
Y07 Y28 YOB Y29 Y09 Y30 Y10 Y31 Y11 Y32 Y12 Y33 Y13
3-- Z22 3-- Z02 3-- Z23
Z03 3-- Z24 3-- Z04 3-- Z25 3-- Z05
Z26 3-- Z06 3-- Z27
Z07 3-- Z28
--zos
Z29 Z09 Z30 Z10 Z31 Z11 3-- Z32 3-- Z12 - - Z33 - - Z13
TCC Signal Names
GND
GND
+ Data In PO + Data In 0 + Data In 1
GND + Data In 2 + Data In 3 + Data In 4 + Data In 5
GND + Data In 6 + Data In 7 + Data In 8
GND
GND + Data In 14 + Data In 15
SY27-2521-3
(SC420 Cont)
5-SC-57
Board Signal Names
B02
- Data Out Bus 0 >-- D 0 2 - - - - - 2, 5
+ 5 Volts + 08 Brdcst Cmd + Parity Valid
- Data Out Bus 8 - Irr To Card 2
+ Valid Byte 1 + Valid Halfword
BOJ
>-- D03 >-- B04----- 5
<-- D04
2
>-- B05
2
<-- D05
2
806
< - - DOS -----=-2.5
<-- B07
2,5
D07
- Data Out Bus 1 >--- 80B - - - - - 2 , 5
GND - EOC Dot
+ Valid Byte 0 + Exception Lth
- Data Out Bus 9
DOB
< - - B09 - - - - - 2, 5
<-- D09
2,5
<-- 810
2
>-- D10
2
B11
- Data Out Bus 2 > - - D 1 1 - - - - - 2, 5
-10 Reset To lid > - - B12
2
+ Modifier lth <-- D12
2, 5
- Data Out Bus 10 >-- B13
2
- Xmit Ctrl
>-- D13
2
+ TD 2 Hz Free Run
+ 5 Volts
G02
>-- J02 - - - - - 2
>--- G03
2
>--- J03
- Data Out Bus 3 + 10 - Data Out Bus 11
G04
>-- J04 - - - - - 2
>-- G05
2
>-- J05
2
G06
+ Inward
- Data Out Bus 4
>>---
JOO - - - - - 5
G07
2, 5
- Int/Ml Vhw <>-- J07
2, 5
- Data Out Bus 12 > - - GOB
2
GND
JOB
- Data Out Bus 13 < - - G09 - - - - - 2
- Data Out Bus 5 >--- J09
2, 5
+TC
>-- G10
2
+TA
>-- J10
2
G11
- Byte Tag To lid >-- J 1 1 - - - - - 2
+ Ch Grant
>-- G12
2
- CR To Card 2 - Outbound Ctrl
J12
<-- G13-----2
>--- J13
2,5
M02
- Data Out Bus 6 >-- P02 - - - - - 2 , 5
- SSCF Pwr Outage < - - M03
5
+ 5 Volts
>--- P03
- Val Dly 250-300 >--- M04 - - - - - 2
-Val Dly 150-200 >-- P04
2
+ 10 MHz
>-- M05
2
+ Any Tag
>-- P05
2
MOO
Figure SC420-4. SC4 Card and Connector Signals
1/0 Pin Assignments
TCC Signal Names
01 - - W22 + SCF Signal Bus PO
01 - - W02 + CR-1
--W23
GND
01 - - W03 + CR-2
01 - - W24 + Ch Grant
--W04
GND
01 - - W25 + IPR 01 - - W05 + SCF Signal Bus P1
01 --W26 + 10 Reset
01 - - W06 + 10
--W27
GND
01 - W 0 7 + End of Chain
01 - - W28 + SCF Signal Bus 0
--woa
GND
01 - W 2 9 + Halt
01 - - W09 + Valid Byte 0
01 - - WJO + SCF Signal Bus 8
01 --W10 + SSCF Reset
--W31
GND
01 - - W11 + SCF Signal Bus 1 01 - - W32 + 10 MHz (Unused)
--W12
GND
--W33
01 - - W13 + SCF Signal Bus 9
01 - - X22 + TC
01 - - X02 + Xmit Ctrl
- - X23 + GND
01 - - X03 + Hold Power On
01 - - X24 + SCF Signal Bus 2
- - X04
GND
01 - - X25 + SCF Signal Bus 10
01 - - X05 + Valid Byte 1
01 - - X26 + Release Req
01 - - X06 + TD
- - X27
GND
01 - - X07 + SCF Signal Bus 3
01 - - X28 + SCF Signal Bus 11
- xoa
GND
01 - - X29 + SCF Signal Bus 4 01 - - X09 + SCF Signal Bus 12
01 - - X30 + Val id Halfword 01 - - X10 + TA
-X31
GND
01 - - X11 + Parity Valid
01 - - X32 + CRP-4
- - X12
GND
01 - - X33 + CRP-2
01 - - X13 + CRP-1
01 - - Y22 01 - - Y02
- - Y23 01 --Y03 01 - - Y24
--Y04 01 --Y25 01 --Y05 01 --Y26
+ SCF Signal Bus 5
+ Outbound Ctrl GND
+ CRP-8 + Irr
GND
+ Power Drop + Byte Tag
All SSCF Sel'd
SY27-2521-3
5-SC-58
Board Signal Names
1/0 Pin Assignments
- Data Out Bus 14 >--- P06 - - - - - 2
- Halt To Lid > - - M07
2
+ XS Tag Wrap > - - P07
5
+ IPR To Card 2 < - MOB
2
GND + XS Crp Wrap
P08
>-- M09 - - - - - 5
- SSCF Res To Lid>-- P09
2, 5
- Data Out Bus 7 >--- M10
2, 5
P10
M11
- Data Out Bus 15 >--- P11 - - - - - 2
M12
> - - - Data Out Bus PO
P12 - - - - - 2, 5
- Data Out Bus P1 > - - M13
2
- Any Valid Lth > - - P13
2
S02
U02
+ 5 Volts
S03
>--- U03
S04
- Pwr Seq Comp < - - U04 - - - - - 2 Pwr Ctrl Card
+ 5 Volts Ve
505
>--- U05 - - - - - Pwr Ctrl Card
+ SSCF Mck
S06
<-- U06 - - - - - 2
S07
U07
508
GND
uoa
- SSCF lrpt
509
<-- U09 - - - - - 2
S10
U10
S11
U11
S12
U12
S13
U13
Note: "2" indicates a signal is from/to SC2; "5" indicates a signal is from/to SC3; "OJ" indicates a signal is from/to SCF signal bus.
01-- Y06 Y27
01-- Y07 01-- Y28
YOB 01-- Y29 01-- Y09 01-- Y30
01 - - Y10 Y31
01--- Y11 01-- Y32
Y12 01-- Y33 01-- Y13 2,5-- Z22 2,5- Z02 2.5-- Z23
Z03 2,5-- Z24 2.5-- Z04 2,5 - - Z25 2,5-- Z05
Z25 2,5- Z06 2,5 - - Z27 2,5- Z07 2.5- Z28
zoa
2 - - Z29 2-- Z09 2 - Z30 2-- Z10
Z31 2 - Z11 5,2 - - Z32 5,2-- Z12
Z33 Z13
TCC Signal Names
+ SCF Signal Bus 13
GND
+ SSCF lrp+ GND
+ SSCF Mck Irpt + Modifier + Release + SCF Signal Bus 6
GND
+ SCF Signal Bus 14 + SCF Signal Bus 7
GND + Exception
+ SCF Signal Bus 15 + Data In PO + Data In 0 + Data In 1
GND + Data In 2 + Data In 3 + Data In 4
+ Data In 5 GND
+ Data In 6 + Data In 7 + Data In P1 + Data In S
GND + Data In 9
+ Data In 10 + Data In 11 + Data In 12
GND
+ Data In 13 + Data In 14 + Data In 15
To SC6 Card
ToSC4 Card
Pin
Signal Name
Pin
802
+ SCF Signal Bus PO <> W22
002
+ CR-1
<> W02
803
GND
W23
003
+ CR-2
<> W03
B04
+ Ch Grant
> W24
004
GND
W04
B05
+IPR
< W25
005
+ SCF Signal Bus P1 <> W05
B06
+ 1/0 Reset
D06
+ 1/0 Tag
> W26
> W06
B07
GNO
W27
D07
+ End of Chain
< W07
808
+ SCF Signal Bus 0
<> W28
DOS
GND
W08
809
+ Halt
> W29
D09
+ Valid Byte 0
< W09
810
+ SCF Signal Bus 8
<> W30
D10
+ SSCF Reset
> W10
B.11
GNO
W31
D11
+ SCF Signal Bus 1
<> W11
B12
W32
012
GND
W12
B13
W33
013
+ ML SCF Signal Bus 9 <> W13
B02 D02 B03 D03 B04 D04 B05 D05 806 D06 B07 D07 BOS DOS B09 D09 B10 D10 B11 D11 B12 D12 B13 D13
+TC + Xmit Ctrl
GNO + Hold Pwr On + SCF Signal Bus 2
GND + SCF Signal Bus 10 + Valid Byte 1 + Release Req +TD
GND + SCF Signal Bus 3 + SCF Signal Bus 11
GNO + SCF Signal Bus 4 + SCF Signal Bus 12 + Valid Halfword +TA
GND + Parity Valid + CRP-4
GND + CRP-2 + CRP-1
> X22
> X02
X23
> X03 <> X24
X04
<> X25 < X05
< X26 > X06
X27
<> X07 <> X28
X08
<> X29 <> X09 < X30
> X10
X31
< X11
<> X32 X12
<> X33
<> X13
SSCF Card (SC5)
Figure SC420-6. SC5 and SC6 Card and Connector Signals
Pin
B02 D02 B03 D03 B04 D04 B05 005 B06 DOG B07 D07 B08 DOS B09 009 B10 DlO Bl 1 Dl 1 B12 D12 B13 D13
G02 J02 G03 J03 G04 J04 G05 J05 GOO J06 G07 J07 GOS JOB G09 J09 G10 J10 G11 J11 G12 J12 G13 J13
1/0 or Processor Board
Signal Name
- SCF Signal Bus 0 - IR/B1-8 + 4 MHz Osc + 5 Volts - Parity Valid - IR/B1-9 - IRR (Hw) - SCF Signal Bus 8 - 5 Volts (Unused) - Valid Byte 1 - IR/B1-10 - Valid Halfword - SCF Signal Bus 1
GND - Valid Byte 0 - End of Chain - SCF Signal Bus 9 - Exception + 8.5 Volts (Unused) - SCF Signal Bus 2 - Modifier
+ Ve - SCF Signal Bus 10
-TD - Ch Request Low - Ch Request Med + 5 Volts - SCF Signal Bus 3 - IR/B1-11 - SCF Signal Bus 11 - 1/0 Tag (Hw) - 5 Volts (Unused) - Halt - IR/B1-12 - SCF Signal Bus 4 - SCF Signal Bus 12
GND - SCF Signal Bus 5 - SCF Signal Bus 13 -TA -TC + 8.5 Volts (Unused) - Byte Tag - System Reset - Valid Byte 1 (B) - 1/0 Tag (B) - IRR (B)
<> <
< < < <>
< < < <>
< < <> < <>
<
> <>
> <
< <>
< <>
>
< > <> <>
<> <>
> >
> > <
>
<
ToSC6 Card
ToSC4 Card
Pin
Signal Name
Pin
802 002 B03 D03 B04 D04 BOS D05 B06 D06 B07 D07 BOS 008 809 D09 B10 D10 B11 D11 B12 012 B13 D13
+ SCF Signal Bus 5 + Outbound Ctrl
GND + CRP-8 + IRR
GND + Power Drop + Byte Tag - All SSCF Sel'd + SCF Signal Bus 13
GND
+ SSCF lrpt GND
+ SSCF MC lrpt + Modifier + Release + SCF Signal Bus 6
GND + SCF Signal Bus 14 + SCF Signal Bus 7
GND + Exception + SCF Signal Bus 15
<> ·Y22 > Y02
Y23
<> Y03 < Y24
Y04
< Y25 > Y05
< Y26 <> Y06
Y27
Y07
< Y28
YOB
< Y29 < Y09
> Y30 < > IY10
Y31
<> Y11 <> Y32
Y12
< Y33
< > Y13
B02
Z22
D02
GNO
Z02
803
+ SSCF Stat AO
<> Z23
003
+ SSCF Stat AS
<> Z03
804
- SSCF Stat A 1
<> Z24
004
- SSCF Stat A9
<> Z04
805
- SSCF Stat A2
< Z25
005
- SSCF Stat A10
> Z05
B06
+ SSCF Stat A3
< Z26
006
+ SSCF Stat A11
> Z06
B07
GND
Z27
007
Z07
808
Z28
008
GND
zoa
BOO
+ SSCF Stat A4
< Z29
009
+ SSCF Stat A12
> Z09
810
+ SSCF Stat A5
< Z30
010
+ SSCF Stat A13
> Z10
B11
+ SSCF Stat A6
< Z31
011
+ SSCF Stat A 14
> Z11
B12
+ SSCF Stat A7
< Z32
012
+ SSCFStatA15
> Z12
B13
GND
Z33
013
< - SC6 Card Present
Z13
SSCF Card (SC5)
Pin
M02 P02 M03 P03 M04 P04 M05 P05 M06 P06 M07 P07 MOS POB M09 P09 M10 P10 M11 P11 M12 P12 M13 P13
S02 U02 S03 U03 S04 U04 S05 U05 S06 U06 S07 U07 SQ8
uos
S09 U09 S10 U10 S11 U11 S12 U12 S13 U13
1/0 or Processor Board
Signal Name
- SCF Signal Bus 6 - Ch Grant Low
+ 5 Volts - Ch Grant High - IR/81-13 - Ch Request High - IR/81-14 - 5 Volts (Unused) - SCF Signal Bus 14 - IR/B1-15 - IR/B1 P1 - Release Req
GND
- Release - IPR - SCF Signal Bus 7 + 8.5 Volts (Unused) - SCF Signal Bus 15 - SCF Signal Bus PO - Ch Grant Med - 10 MHz to Adapt - SCF Signal Bus P1
<> >
>
< < < <> < < <
> < <> <> <>
>
> <>
+ 5 Volts
-Turn Pwr On
>
+ 5 Volts Ve
<
+ 5 Volts Vetri
<
- 5 Volts (Unused)
GNO
+ 8.5 Volts (Unused)
SY27-2521-3
(SC420 Cont)
5-SC-59
SC430 SCF Cable Connections
Sections SC431 and SC432 are charts that show the 8100 SCF cable routing. The SCC designation indicates the pseudo numbering for the SCF cables.
SC431 SCF Internal Cable Connections
8130 Internal Without System Expansion Feature
From A2G2W A2G2X A2G2Y A2Y4 A2Y5 A2Y6 A2A5 A2Z1
Through
--
---
--
---
--
--
Through
--
--
-------
To A2H2W A2H2X A2H2Y A1Z4 A1Z5 A1Z6 B1A5 B1A2
Cable
sec 19
SCC20
sec 21
SCC22 SCC23 SCC24 SSC7 SSC 11
8130 Internal With System Expansion Feature
From A2G2W A2G2X A2G2Y A2A2 A2A3 A2A4 A2Y1 A2Y2 A2Y3 A2Y4 A2Y5 A2Y6 A2A5 A2Z1
Through
--
--
--
--
--
--
---
---
---
--
--
Through
----
--
-----
--
-- --
----
To A2F2W A2F2X A2F2Y T-E1 T-E2 T·E3 A1Z1 A1Z2 A1Z3 A1Z4 A1Z5 A1Z6 B1A5 B1A2
Cable
sec 1
SCC2 SCC3 SCC4
secs
SCC6
secs
SCC9
sec 10
SCC22 SCC23 SCC24 SCC7
sec 11
8140 Model A Internal
From A1A2W A1A2X A1A2Y
Through
----
T-01
A2C2W
T-02
A2C2X
T-03
A2C2Y
Through
---
--
A202W
A202X
A202Y
To A2A2W A2A2X A2A2Y T-E1 T-E2 T-E3
Cable
sec 1
SCC2 SCC3 SCC4
secs
SCC6
SY27-2621-3
6-SC-60
8101 Internal
From
Through
T-01
A1A2W
T-02
A1A2X
T-03
A1A2Y
T-01
T-02
T-03
T-01
A1A2W
T-02
A1A2X
T-03
A1A2Y
Through
---
-----
A2A2W
A2A2X
A2A2Y
A2A2W
A2A2X
A2A2Y
To T-E1 T-E2 T-E3 T-E1 T-E2 T-E3 T-E1 T-E2 T-E3
Cable
SCC7 SCCS SCC9
sec 1
SCCS SCC9
sec 1 secs
SCC9
Note: The three cable locations depend on the 8101 features installed, and are always
secs 7, 8, and 9.
SC432 SCF External Cable Connections
8130/8140 External
From
Through
T-01
---
T-02
---
T-03
---
Through
To
Cable
T-E1
sec 1s
T-E2
sec 11
T-E3
SCC18
SC440 Switches SC441 SC1 Card Switches
(See SC111 for location of SC1 card.} The SC1 card contains the switches used to specify the primary mode IPL parameters, and are fixed at hex 43SO.
Note: If 'these switch settings are changed, DPPX and DPCX do not perform a primary mode IPL properly.
Figure SC441-2 shows the switch settings as they relate to the IPL parameter bits specified in Figure SC441-1, and Figure SC441-3 shows their physical location.
How To Test the IPL Parameter Switch Settings 1. Press Reset/IPL at the BOP. 2. At the 0200 display message, press Enter Data. 3. At the 0201 display message, enter "0001" and press Enter Data.
The contents of the IPL parameter switches are then displayed in the BOP, and the value should be hex 43SO.
Bit 0 1
2
3 4-7
8-15
Meaning
Reserved
Auto restart primary IPL - If on, executes a primary IPL using the parameters specified in the PSCF IPL parameter switches. If off, terminates the IPL with 0122 in the BOP display.
Extended test - Specifies manual mode testing parameters according to DPPX or DPCX, and also according to whether IPL occurred either from a power-on sequence or from the IPL pushbutton. Refer to CP523 "Manual Mode IPL and Its Testing Options" in Chapter 2 for a detailed explanation.
Initialize storage - Refer to bit 2 for explanation.
IPL device type
0001 = diskette 0011 =disk 1111 = maintenance device
IPL device address according to the following:
8-11 12-15 80 84 90 AO
BO
co
87 97 A7 B7 C7
= SSCF address = device address = Disk storage, 8130 or 8140A = Disk storage, 8140B = Disk storage, First 8101 = Disk storage, Second 8101 = Disk storage, Third 8101 = Disk storage, Fourth 8101 = Diskette storage, 8130 or 8140 = Diskette storage, First 8101 = Diskette storage, Second 8101 = Diskette storage, Third 8101
= Diskette storage, Fourth 8101
Figure SC441·1. IPL Parameter Bit Descriptions
IPL Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Switch Number 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Switch Module 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2
Initial Setting On Off On On On On Off Off Off On On On On On* On On
Description Reserved Auto restart primary IPL Extended test Initialize storage IPL device type IPL device type IPL device type IPL device type IPL device address IPL device address IPL device address IPL device address IPL device address IPL device address IPL device address IPL device address
Note: The signals from 'the IPL switch register are inverted before being used, so 'the initial setting as indicated in the figure is read as 4380 at 'the IPL register.
*Off if 8140 Model B
Figure SC441·2. SC1 Card IPL Switch Settings
Byte 0 (Module 1)
Byte 1 (Module 2)
Note: Modules 1and2 are rocker switches. Pressing down the right side turns the switch on, and pressing the left side turns them off. (4380 shown)
Figure SC441-3. SC1 Card IPL Switch Module Locations
SY27-2521-3
(SC430-SC441)
5-SC-61
SC442 SC5 Card Switches
SY27-2521-3
5-SC-62
REA 06-88481
SC5 Card Module 1 Switch Description Switches 1-4 determine the value of the leftmost hexadecimal digit of the SSCF physical
Figures SC442-1 and SC442-2 show the SC5 card switches, locations, and meanings. (See SC111 for locations ~f SC5 cards.)
address. The rightmost value is always hex 8. The PSCF physical address is fixed to hex 08. To address any SSCF, the PSCF and SSCF physical addresses are specified. Therefore, to address the SSCF contained in the fourth 8101 A2 board, for example, requires a PAPA
· The ten Module 1 switches specify the SSCF address, release request signal propagation,
designation of hex 08C8. Switches 1-4 specify the "C". The 08 and 8 are always the
tag delay, and channel request priority
same.
· The eight Module 2 switches each enable use of an interrupt request bus to turn on release request.
Refer to the configuration table shown in SC113 to relate the following explanation of the SC5 card (SSCF) switch settings to the SCF physical addressing scheme.
Switches 6, 7, 8, 9, 10, and 5 in that order determine the first six bits of the first Op field of the table in SC113, and the last two are always zero. Therefore, the Op value for the SSCF contained in the fourth 8101 A2 board is hex 24. See Figure SC442-2 for the SC5 card module locations. The following shows Module 1 switch assignments:
SSCF Board Location 8130/40 A2 8140 C2 First8101 Al* First 8101 A2** Second 8101 A1* Second 8101A2** Third 8101 A1* Third 8101 A2** Fourth 8101 A 1* Fourth 8101 A2* * 8809 Model 1B
Module 1 Switches and Settings
1
2
3
4
5
6
7
8
9
10
ON OFF OFF OFF ON OFF ON OFF ON OFF
OFF ON OFF ON ON OFF ON ON OFF ON
OFF OFF OFF ON ON OFF OFF OFF ON ON
ON OFF OFF ON ON OFF OFF ON ON ON
OFF OFF ON OFF ON OFF OFF OFF ON OFF
ON OFF ON OFF ON OFF OFF ON ON OFF
OFF OFF ON ON ON OFF OFF OFF OFF ON
ON OFF ON ON ON OFF OFF ON OFF ON
OFF ON OFF OFF ON OFF OFF OFF OFF OFF
ON ON OFF OFF ON OFF OFF ON OFF OFF
OFF ON ON ON ON OFF ON ON OFF OFF
This figure shows settings for switches 7-10 for 8101 A1 boards containing only communications features and 8101 A2 boards containing only a file feature (see* and**).
*When adding the display and printer feature to any 8101 A1or81 board, switches 7-10 are set to ON, ON, ON, OFF (hex E) for the first adapter and to ON, ON, ON, ON (hex Fl tor the second adapter (8140 model BXX systems only).
**When adding the Magnetic Tape Feature to any 8101 A2 board, switches 7-10 are set to ON, OFF,
ON, ON (hex BL When adding the Diskette Storage Feature without the Magnetic Tape Feature to
any 8101 A2 board, switches 7-10 are set to ON, OFF, OFF, ON (hex 9). Any board with only the SSCF card has switches 7-10 set to OFF.
Figure SC442-1. SC5 Card Module 1 Switch Settings Relating to SSCF Board Locations
Function SSCF address Release request Tag delay Channel request priority
Switch 1-4 5 6 7-10
Switch Position Dependent on board location Always on Always off Fixed according to system configuration
SC5 Card Module 2 Switch Description The Module 2 switches enable the BSC/S-S communications adapters, when in BSC mode, to send a release request signal to the processor. The table below shows the relationship between the communications adapter physical addresses and the switch numbers. When a BSC/S-S adapter is in BSC mode, the switch corresponding to its physical address must be on.
81408 50 80 51 81 52 82 53 83 5C 50 5E 5F
Communications Adapters Addresses
8130
81 82 83 84 85 86
8140A
81 82 83
8101* XO X1 X2 X3
xc
XD XE XF
SSCF Card
Module 2 Switch No. 1 2 3 4 5 6 7 8
*X = 1, 2, 3, or 4 depending on which 8101 the communications adapters
are in.
Module 1 is the 10-position switch module; Module 2 is the 8-position switch module.
L
oz OU.LL
m~rj le-'.i
IO'I
~,
Ni
.-'
oz: ou..u..J
Figure SC442-2. SC5 Card Switch Module Locations
SY27-2521-3
(SC442)
5-SC-63
SY27-2521-3
SC450 8130/8140 Detailed Data Flow
Figures SC450-1 through SC450-7 show the SCF data flow and timing, as well as the data flow within each PSCF and SSCF card.
5-SC-64
Processor
.... I( _!LO ]:us]!yte~
r
.....
PIO Bus_E!yte 1
,...
PIO Tags 5
.... Chan Req
[:, Chan~rant
1-
11/fafl<erJ!us anTiags
.....
)
~~ I< ~us_!!yte_Q_.~L_
:a..
,..)
......
~ r
....
.:.J..
.... ...)
PSCF SC1 Card (A2G2) and SC7 Feed Thru (A2H2)
......
_;:
... - IC..... P!Q Bus]!yte1 .,2.
2 ~ _..-le' ~ags
~~
~
IC IAIB1 Bus Byte 1
IC,.......
_l_R@1
Tags""""~ -,,,..
~
_ r-:· I"""
....-
- ....
~
~ -- ... _.
Chan Req Hi ....
Chan Grant Hi .:..'...
Chan Req Lo ......
... Chan~ant Lo~
Release __
~CDIBu§;>
[_
Note: This figure Is for the 8130 without Expansion feature; see SC401 for other configurations.
BOP Adapter
Figure SC450-1. SCF Signal Bus Data Flow Diagram
-~
...LI.
i'
~
.L ::I..L _IL
... * 4'4'*
I
IH
H
~
, ~---
H
~·
t t . ,~~ ,.~~I
Diskette Adapter
.!h. :::I.IL
i+JL
~
I
:n:
~*
~ ~*
II-
I...-.
-.
~
..:..
1·
I-
It t t , I ~~ ~~,
I vi(-- ~
PIO Bus Byte 02
I/"
I""
.-J
~
-I( PIO Bus Byte 1 2_
.../ic(L PIO Tags
~I<.: IR7B1 Bus Byte 1
- ~ IR/B1 Tags
--i.... Chan Req Hi
-- /..... Chan_Qrant_lii :
n . . Chan Req Lo :.
_
~ Chan_Qrant Lo:
rr
....
....... Release -.........
v
_........1
l'"""T""
~.L
_,
lll
'Ii *
- t'nnT
<Iii.
I~
....
r,, ~I
i I~
~
~I~
r
~~~ I
:i.
~
~
..., *
:J._llD:T
-4'".".'..
t t~ ~I
Disk Adapter
SDLC Comm Adapter
BSC/S-S Comm Adapter
*Interrupt Connections for 8130 without Expansion Feature
Adapter Type Wired To
Interrupt Level
Bisync CCA
IR/B1 Bus Bit 1 1
Start/Stop CCA IR/B1 Bus Bit 3 3
SDLC HPCA
IR/B1 Bus Bit 3 3
Diskette
PIO Bus 1 Bit 4 4
Disk
PIO Bus 1 Bit 4 4
-1/0 Tag -TA Tag (Addreu) - TD Tag (Data)
(Write Operation)
-Valid HW
-IRR
SCF Sign1I Bus
Addre11 a Commend
- Parity Velld
Figure SC450-2. SCF Timing Ch1rt for Reed ind Write Operltion·
Date Bytes 0 Ii 1
LJ
Interrupt Time
(Read Operation)
L
Address & Command
All Os
Read Data
Os
Interrupt Time
SY27-2521·3
(SC450)
5-SC-65
SY27-2621-3
I I Manual IPL Sw Reg
r Rd IPLSw
IPL Switch, Gating and Drive
l':-1. :!
J
·-~ --- --- J --- --- ""' , 4~
Q)
.:.?.!.
0 <(
Cl
cQc )
.:
... _t - Set Bits on Bus
- 1
Set Data In
::E Ill KOO Reset
I
Ill
LO 0
N
~
Reset
1/0 Reset _I
Sys Reset
SEF *
BSTAT
l -- - t ~
Mkr Bus .......,
~
ROS Latch ~~
Halt_=:i
~n ..._, 1~
---- --- u r -- r __,
:"s '
IO
- - 11. - __, ici:i 0 "fl
I!!
f ' --- - - - 0
- I
PmO Monitor 1/0 TA TD Power Off
Val Hw
Marker Bus
~
Controls
~
g J
0 <( f- f-
t ~
._ __ Save PSV To Proc
Oecto BOP._~
Power-Off Cmd-
e..n. ccc;;
"' E GI
cGc I
Cl
"-
Cmd Decode ~~
cCc l
PSCF BSTAT
AeadBSTAT .....
~-
"'- S/R BSTAT (EIR Reg Addr'd (OC)
~ ~
.-
- - -- ·~ t · ,..... l - lJ l -.
ID __ PV
-
0 0:
.: IRR
-- -- =-- ~ r J ___.. t f --- ___,
Halt
i...
PIO Tag Control
lnh Rd PC
Inv Cmd BO=e-:lrDt
_tf PC + PG
"C
u E
Cmd Reg
..._~
- R l Reset
_ Addr Cmpr T
Set BOP Cmd
.......__, -- t __ IR's
Set Data Du':. I
l
-.
T
- --- ::r~drCm~
"""
~~
PSCF EIR
I ,. - - 1 l l . II ~lrr(B)
__ 1/0 (B) (To CCA)
... -- CR Hi/Lo
- l t CG Hi/Lo
--- - Tf Release to Adapter
-- D - CG from Proc ._.._, CR to Proc
- --- End of Chain
I j_
Adapter Priority
--- -.-.-. - Byte 1
2 .. --- (Interrupt Bus)
."..'
GI
... 0 Cl
cCcl>
.ii!:
::J
<(
0 ::E
10 MHz (From Proc)
_tClThk
IT IR
To BSTAT
ca
d
c..o.I.
50/60 Hz from PS Timer .- and
Set IT IA
Osc
Enable Timer : Clock Gen Set IT Chk
I
1 MH~
1/0 PB Reset Req (From BOP) IPR
+ 10 MHz (Repowered)
* System Expansion Feature
(8130)
1 kHz (1 ms) 2 Hz (500 ms)
Bits 0.6, 1.3 and 1.4 from SEF*
~
""'-
.---1 ~~
Byte To HW
soc
Bus Rcvrs
Byte to HW Control
Programmable IPL SwReg
Cl
cGc I
TD~
t-. BOP Sel'td
SDC Bus SOC Sync Bus
..J
Control
!!:
jand
~ cc
Set BOP Cmd
!Sequencing SOC Halt Bus
~
~ ...
~
Gx I
a.GI
·;:
"5
... ~ :E ID
>
ID
Byte Multplx Control
soc
Bus Orvrs
__ From BOP _._.To BOp
._soc_.
Bus To BOp
.... ~
..;
The "Data in Reg" and
j
"Data Out Reg" are one shared
halfword Reg.
Figure SC450-3. SCF SC1 Card Data Flow
5-SC-66
~
~
~
0-15, PO, P1 From SC4 Card 0-15 PO, P1
2
/
~
2--,
Bus To and From Processor
~ ~
1+ ~ it IFC
Reg
Drvrs ~ ,..~.o.rrocessor~
Rcvrs From Processor
0-15 PO, P1 ;I'
~
0-15, PO, P1
7
Data Out 0-15 from Card SC2
~
ADDA
, /
:;) Dcd ~ ,..
10 MHz
~
SSCF Sel CtrI
Val ids
-- Tag Wrap _...,
- 1/0
- SC1 Reset
J
1/0 Reset
-J
Read OB
-- Read OC
-- SC5 lntrpt
SC5 Mck Pwr Outage Pwr Seq Complete
Tag Wrap
NotVhw Any Tag Crp Tag Wrap
TA 1/0
----.-.------..---.-
J
8-~
~
IR Reg
~ t8----1-51 Drvrs
P1 To
ri !-'-'-- Processor
~D..rs "1
To
..,__....
Processor
LJ Vhw Gen
-o~ Parity
~ Chk
Reset Cntl
r:Status
r
and
.J
lntrpt
Cntl
To SC3 and SC4 Cards
Parity Good
..
SC1
Reset
1/0
Reset
---
Status Bit 6 Status Bit 1
Status Bit 12 BSTATJReq Interrupt
----~ -------
+VE(-POR)
...
--- Vhw To Processor
Parity Good -
.--. SC1 Reset
...,
~ ~
Crnd Dcd
_..
l"""""'i
~ Bit15
From Cal'd SC4
Data In PO, 0-8, 14, 15
~
~
L
7
~
~
r---
.. Load CHCV 1/0 -..
TA --
TC
- TD
CG ~
EOC
P0,0-7
VHW
-
VBO --
Dir Ctr I
Wrap Reg
Figure SC450-4. SCF SC2 Card Data Flow
-- VB1
MOD
- PAR. Valid
-~
SC1 Reset
---
Pwr Ctrl
SC5 Pwr Out
Figure SC450-5. SCF SC3 Card Data Flow
08 Brdcst Cmd X8CrpWrap
-----
Read 08 Status
-
XS Tag Wrap
--
Read OC Status
......
Enable Data Ltchs
--
...... Inward Outbound Ctrl
---
--
~
Data Out
PO 0-7
7
..... Pwr Out
SC5 Reset
------
SY27-2521-3
(SC450 Cont)
5-SC-67
SCF Signal
\
Bui Data Lines 0-15, PO, P1
' L
7
Data Out 0-15 PO, P1 From Cardi SC2 and SC3
_i
2
~
SCF Signal
Bus Data Drvrs
Ctrl Signals From SSCFs
Tags
SCF Signal
_i
' L
T
Bus Rcvrs
..
Ch Grant
-_..
Bus To and From SSCFs (SC5s)
~ ~
v "'!:
Chan Req Ctrl
CG, Rel
SV27-2521-3
SCF Signal
Bus Data Rcvrs
SCF Signal
Bus Drvrs
~I
~
0-15, PO, P1 Data Lines
7
~ Data In
, 0-15, PO, P1
To Cards SC2 and SC3
~ Ctrl Signals To SSCFs (SC5s)
7
Valids SC1 Mck SC1 lntrpt SC1 Pwr Out
-------...
-
EOC
--
Ch Req
--
VE
-
2 Hz
__]
Figure SC450-6. SCF SC4 Card Data Flow
Pwr
CRP 1-4
On
Seq
Ctrl
-- Pwr Seq Complete
5-SC-68
SCF Signal Bus
1/0
CG
Halt
Data PO, 0, 1
w
Data P1, 8, 9
#1
VBO
EOC
IPR
SCF Signal Bus
TA
TC
TD Data 2-4
x
Data 10-12
#2
VB1
VHW
P-VAL
SCF Signal Bus
REL
B-TAG
OBCTL
Data 5-7
y
Data 13-15
#3
MOD
IRR
EXCP
AD 1/0 OP B y t e - - - - - -
Rel Req Logic
CH Req Lo Med Hi
SW Ctrl
SSCF Address Switches
Status Reg SSCF Bus
Cmnd Reg
SSCF Bus
MLCG
CR-1 CR-2 Note: Numbers in circles specify number of bits on bus.
Figure SC450-7. SCF SC5 Card Data Flow
Lo Med Hi Adapt CG
SSCF Adr Cm pr
Selection Process Select Error Report Address Conversion
SV27-2521·3
BSC/S-S Rel Req Module 2 Switches
lnh 0-7 Adapt
- - -.....~- 81/IR
SSCF Bus 8-15
PR I/Sec GTS
BXS RAM XLate Array
8
Gates
SSCF
Bus
Bus
8-16
(SC460 Cont)
5-SC-69
SC460 SCF Detailed Description
The SCF provides the logical attachment for 1/0 devices and communications control, performs 8101 power-on signal sequence control, and also provides several programmable functions.
The SCF hardware responds to addresses hex 08 (SCF Level 3), hex OC (SCF Level 0), hex 09 (BOP), and hex OA (EFP, if installed) for information transfer. It can request interrupts on Level 3 fixed assignment, which can be programmed to occur on Level 0. Level 3 interrupt requests can occur from: · The BOP · The 100-ms interval timer · A control program · The SC F adapter
Power can be turned off with a command to the Level 3 address after first enabling the power-off circuitry with a KOO command.
The physical location and functions performed depend on the processor model. · The basic 8140 Processor provides all functions. · The basic 8130 requires addition of the System Expansion Feature to perform those
functions equivalent to the 8140.
The location and number of these cards also vary between the 8130 and 8140 because of physical board configuration. The PSCF cards and one SSCF card reside in the processor boards. Up to six more SSCF cards can reside in 8101 boards, with one or two in each 8101, depending on its 1/0 device configuration.
Note: For purposes of discussion in this section, the terms "PSCF" and "SSCF" are used "PSCF" refers to those functions performed by the SC1 card, while uSSCF" refers to those functions performed by the SC5 card. The SC2, SC3, and SC4 cards control interrupt priority, while the SC6 card, used only in the 8130 with the System Expansion Feature, functions as a signal line terminator.
For physical differences, see section SC11 O; for functional differences, refer to the detailed data flow contained in section SC450; for operational differences, refer to the following information.
SC461 Primary System Control Facility (PSCF) The PSCF and SSCF each provide certain functions and also logically combine to provide others. The following explains the functions provided by the PSCF:
Power Sequence Control. As the 8130/8140 powers up, signals from the PSCF provide power sequencing to the attached devices. The sequencing order for attached 8101 s depends on the setting of the channel request priority (CRP) switches of the SSCF, in the order of the highest CRP value first, and the sequence bypasses any 8101 not powered on. The complete sequence occurs in approximately 64 seconds.
SY27-2521-3
5-SC-70
Operator Panel to Channel Operations. The PSCF provides the method of information transfer with both operator panels (BOP and Expanded Function on the 8140) and the channel for processor operation. The panels use PIO halfword instructions for address and data transfer, and the panel adapter transmits any panel error conditions to the PSCF, which suppresses any response to the channel. The PSCF also parity checks operator panel address and data transfers before initiating any PIO operation to it, and does not initiate panel operation if errors occur.
Clocked Interrupt. The processor receives an interrupt every 100 ms, depending on PSCF BSTAT bits 8, 9, and 14. The interrupt occurs either on Level 0 or 3, according to the PSCF El R bit 1 value. The program controls the timer that generates this clocked interrupt.
Programmed IPL Parameters. The PSCF has a programmable register to contain IPL parameters, and the PSCF BSTAT bit 1 determines its use when performing a program-initiated IPL. The bit meanings are identical to those contained in the IPL switches. Refer to SC441 for IPL switch meanings.
IPL Switches. Sixteen PSCF hardware switches provide a source for IPL parameters when normal register parameters are not available. The bit meanings are the same as the programmed IPL register, and determine:
1. The IPL device type. 2. Whether an automatic restart primary IPL sequence can be performed. 3. Whether extended bringup tests should be executed. 4. Whether storage should be initialized to FFs with correct parity.
Refer to SC441 for IPL parameter meanings.
BOP and PSCF Level Assignments. Processor board wiring assigns Level 3 to the BOP and the PSCF, which can be swapped to 0 by altering the value of the PSCF EI R bit 1 value, as OPPX and OPCX use the fixed value assignment. The expanded panel always operates on Level 0 and cannot be altered.
Error Detection. PSCF logic provides parity error detection for BOP and EFP operations as well as for its own functions. These conditions are indicated in the PSCF EI R.
KOO Instruction Decode ~or PSCF Operations. The marker bus decodes processor-toPSCF KOO instructions, which perform 1/0 resets, system resets, enable power-off, and other operations used to test the SCF hardware.
When a program executing in either master or supervisor mode performs two sequential Control Direct Out (KOO) instructions, PSCF logic decodes the second KOO to perform certain control functions. The I-field of the first KOO must be 0, and the I-field value (from 0 to 7) of the second determines the function to be performed. These functions are: enable PSCF decodes, 1/0 reset, set 1/0 interface check, system reset, set panel check, force bits 2 and 10 to 1, force parity bits to 1, and enable system power-off.
Reset Control. Reset facilities for the SCF, PSCF, 1/0 devices, and the system, as well as selective programming resets are provided by PSCF logic. The PSCF responds to the following reset conditions:
Power-on reset from the power supply IPL Pushbutton - Reset from panel Marker bus - System reset Marker bus - 1/0 reset Pl 0 command - Reset control
PSCF Priority Assignments for Adapters. The PSCF services adapters according to the following priority, and uses additional lines from the PSCF to the adapters to accomplish this:
Priority Class
Type
Example
First
Real time services
PIO
Second Unbuffered, overrunable CHIO
SDLC communications
Third
Unbuffered, overrunable PIO
BSC/S-S communications
Fourth Buffered, non-overrunable CHIO
Disk storage
Fifth
Buffered, non-overrunable PIO
Basic Operator Panel
Programmed SCF Function Control. The PSCF controls several functions of the SCF through specific bits in the SSCF status registers.
SC462 Secondary System Control Facility (SSCFJ The following paragraphs explain the functions provided by the SSCF.
1/0 Group Addresses. Hardware switches are used to determine the high-order four bits of the PIO address for each SSCF and its attached devices. These are fixed assignments; although you can change them at the user's request, it is not recommended, as both DPPX and DPCX use the fixed assignment values for addressing.
Refer to Chapter 2, CP220, for SSCF addressing assignment values.
Channel Request Priority (CRP) Switches. The fixed channel request priority switch value determines which SSCF receives interrupt servicing with more than one request pending. The values are hex 0 to hex F with hex F being the highest priority. These are fixed assignments; although you can change them at the user's request, it is not recommended, as both DPPX and DPCX use the fixed assignment values for addressing.
Refer to Chapter 2, CP220, for CRP addressing assignment values, and to SC441 for the switch settings.
Release Request Switch. Each SSCF has a switch used to activate the release request signal to the PSCF. This signal occurs when a device assigned to the SSCF channel-hi priority chain generates a channel request to the SSCF. This switch is set to the On position; although you can change it at the user's request, it is not recommended because it can result in improper operation of devices on the channel.
Interrupt Translation Array. Each SSCF has eight 8-bit locations used to contain the programmable priority level and sublevel assignments for its attached devices. Bit zero is not used, bits 1-3 specify the priority level (0-7), and bits 4-7 specify the sublevel (0-F). The PSCF, SSCFs, BOP, and EFP cannot be assigned through the translation array as their
addresses are fixed, but all other devices can be assigned address priority through the programmable array values.
Refer to Chapter 2, CP220, for the translation array addressing values.
SC463 PSCF and SSCF Combined Functions The 8100 requires both the PSCF and the SSCF to provide the following functions:
· Wrap Testing and the SCF Signal Path - Logic in each of these components provides a path to all attached 1/0 devices through the SCF signal bus. It also uses this path to check SCF signal bus integrity by using certain test commands.
· 1/0 Interrupt Presentation - All requests to the processor's channel facility require use of specific functions logically controlled by both the PSCF and SSCFs. Each performs certain operations required to present and prioritize the requests from both the hardware and software.
SC464 How the SCF Controls the BOP, EFP, and Adapter Bus
The PSCF responds to the BOP and EFP halfword commands, and controls processor-toBOP/EFP information transfer through the 9-bit (8 +parity) system direct control bus. It also transfers information on the SCF signal bus and decodes certain processor KDO commands, which perform 1/0 resets, system resets, enable power-off, and other operations that test SCF hardware. The PSCF does not accept an out-of-parity address and command, and generates an 1/0 timeout error for this condition.
The system direct control bus transfers commands and data to the BOP and EFP one byte at a time. It does not check these commands for validity, but does perform parity checking.
The SCF signal bus transfers commands and data to PSCF addresses hex 08 and hex OC, where the PSCF then checks them for both parity and validity. Invalid commands cause an equipment check, while commands with invalid parity cause an 1/0 timeout. The PSCF El R also indicates invalid parity.
PSCF Command Functions
If the PSCF accepts a command to address hex 08, it performs one of the following operations: · Reads, sets, and resets the PSCF BSTAT. · Reads the IPL switch register. · Reads and writes the programmed IPL register. · Turns power off. · Resets the adapter. · Loads the wrap register. If the PSCF accepts a command to address hex OC, it performs one of the following operations: · Reads, sets, and resets the error information register. · Resets the adapter.
· Loads the wrap register
SY27-2521-3
(SC460-SC464)
5-SC-71
Halt Signal
SY27-2521-3
This signal terminates a PIO operation to either the BOP, EFP, or PSCF address hex 08, and indicates that one of the following conditions occurred: · The PSCF received an out-of-parity command, and the "val id" response for that
command was suppressed to force an interface timeout.
· The PSCF, BOP, or EFP received an invalid command, and the "valid" response was suppressed to force an interface timeout.
· A PSCF address hex 08 write operation was in progress, and the PSCF sensed out-of· parity data on either the BO or B1 data bus. The "valid" response for that data is suppressed to force an interface timeout.
· A PSCF address hex 08 read operation was in progress, and the channel received out-ofparity data from the PSCF. The PSCF has not signaled the channel to assign parity to the data, and the channel then activates the Halt signal to terminate the PIO operation.
· The BOP failed to respond to the initial signal from the PSCF to initiate a channel I operation. The PSCF suppresses all responses to force an interface timeout.
Out-of-parity conditions sensed during read or write operations with the PSCF (address 08 or OC) or the BOP (address 09) are recorded in the PSCF EIR, bits 4 (1/0 Read Check) and 9 (1/0 Write Check) to further define the error condition.
6·SC·72
SC500 SCF System Test and Internal 1/0 Bus Cable Change Procedures
SC610 SCF System Test Procedure
The SCF System Routines provide the additional testing needed to test system functions. In most cases the interaction of multiple adapters is needed. Therefore, run all adapter test, PSCF tests, and SSCF tests {see SC210) before using these SCF system routines.
Note that: 1. Normally an SCF System Routine will use all of the same type adapter needed for
the test. 2. Testing will continue until all of the same type adapter have been tested. Multiple
errors in a single routine can occur but only one per group of adapters. 3. Each time a new adapter is used in a test, a progress indicator is presented to describe
the routine number and the adapters used in the test.
OSXE RR3E ADDA
OSXE RR46 OBXE RR49 AD OSXE RR4A AD OBXE RR4B AD
RR= First R always B Second R 0-F is storage volume number (high-order address byte of storage)
ADDR = Storage address within a volume Replace storage card at failing address.
Resource error. Could not find a needed adapter.
Device error. Not ready. Make device ready and retry test. (If AD= file adapter, refer to Action Plan 7 .)
CHIO machine check during Release Request test. Replace AD. Call support center.
RR =AE, BO-BF
CHIO machine check. If RR= 9X, replace AD; call support center. If RR= AE or BO-BF, see error message format in routine BO-BF description.
4. The tests are run using the Free-Lance Utility. At SOBC, enter 69C; at 81 BC, enter B. Routines 90, 91, 93, 94, 95, 96, 97, 98, 9A, 9C, 9E, AO, A1, AE, AF, BO, BF, and CO will be run; if the correct type of adapters is not available, a resource error will occur.
5. 1/0 devices must be ready (tape unit power on and ready, diskette in place and door closed, display powered, etc).
6. OSR R messages that flash on the hand held display are progress indicators that show the addresses of the adapters being tested. If these messages remain on the display for more than 1 minute, a hard error has occurred. Record the message, depress the 'B' key to continue. If the tests will not continue, start over to see if the same error halt occurs.
If a system test failure occurs, refer to the System Error Message Chart, below for the appropriate action. Be sure to record all error messages before calling for assistance.
OSXE RR4C AD
Modifier error. Refer to Action Plan 7.
OSXE RAFE AD
CHIO device failed to complete. Call support center.
1st AD= CHIO
2nd AD =Release Request adapter
SC520 Procedure to Change SCF Internal 1/0 Bus Cables
1. Power down the system and remove power plugs from the AC power source.
2. At the unit it is necessary to change the flat white 1/0 cables, open the front cover and front subcover, reach under the top cover to disengage the bezel stud latches, and remove the bezel (see Figure SC520-1 ).
3. Reach under the top cover frame members to disengage the top cover stud latches. Lift front of top cover, push to rear and lift off.
System Error Message Chart
4. Open the rear cover and rear subcover, remove the card retention covers over the cable or cables you wish to change, then unplug the cable or cables.
Msg 08RR ADAD
Description/ Action
Progress indicator. RR Does not alway.; indicate the test routine being
executed when in an Ml message (see SC231). AD Is the physical address of the adapter or adapters
being used for the test. Go to the MAPs and run the tests for these adapters.
5. If possible, swing the logic gate to its most advantageous position and remove the cable retainers and cable from the gate. If this is impossible:
a. First, get someone to help you.
b. Then remove the logic gate from its hinges and set it on the floor of the unit, or out of the unit, as far from the 01T panel and as gently as possible to not damage the fans at the bottom of the gate.
c. Remove the cable retainers and cable from the gate.
08XE RR27 AD
CHIO Data register error. Call support center.
6. Swing the logic gate open and using a mirror continue to remove the same cable from the cable trough through the unit and from the 01T 1/0 panel. If this is impossible:
08XE RR28 ADAD 08XE RR29 ADAD
Unexpected interruption during Release Request test. Bysync Release Request switch not set.
Control CHIO register setting in error. Call support center.
a. First, get someone to help you.
b. Then remove the logic gate from its hinges and set it on the floor of the unit, or out of the unit, as far from the 01T panel and as gently as possible to not damage the fans at the bottom of the gate.
08XE RR2A ADAD
CH 10 operation did not complete during Release Request test. Bad 'AD'. Replace first AD. Retry test.
c. Remove the cable from the cable trough through the unit and from the 01T 1/0 panel.
08XE RR2B ADAD
Lost CHIO interruption during Release Request test. CCA Release Request switch not set off.
7. Reverse the above steps to install the replacement cable, starting at the 01T 1/0 panel.
08XE RR34 ADAD
CHIO Data register error during Release Request test. Bad AO. Replace first AD. Retry test.
REA 06-88481
SV21-2521-3
8. Run the SC tests, using Menu Selection 1 to check if the new cable has corrected the problem.
(SC464 Cont-SC520)
5-SC-73
----Rear Cover
- - - G a t e (01 A)
SV27-2521-3
REA 06-88481
5-SC-74
Figure SC520-1. Typical Top Covers
Machine Identification Label
Figure SC520-2. Typical 8130 Cable Installation
rn I
01T 1/0 Panel
Figure SC520-3. Typical 8140 Cable Installation
rn,
I I
I I
L~I
r f',,
I I I I
' )I
If:YkI1IJ
01T 1/0 Panel
Figure SC520-4. Typical 8101 Cable Installation SY27-2521-3
(SC520 Cont)
5-SC-75
SY27-2521-3 This page intentionally left blank.
5-SC-76
Chapter 5. MAP Reference Information Expanded Function Panel
(SP)
SY27-2521-3
5-SP-i
Introduction
This part of Chapter 5 provides maintenance information to service the 8140 Expanded Function Operator Panel (EFP) Feature. When used with the Maintenance Analysis Procedures (MAPs), the MAP diagnoses EFP problems and refers to this part of Chapter 5 for information such as hardware locations, possible causes of failure, and wiring lists.
This part has five sections:
1. General Information (SP1OO-SP134) - Contains configuration, operation, and repair strategy information.
2. Offline Tests (SP200-SP254) - Contains test information and lists possible causes of failure.
3. Intermittent Failure Repair Strategy (SP300-SP350) - Contains information used to repair intermittent failures.
4. Signal Paths and Detailed Operational Description (SP400-SP450) - Contains diagrams and charts that show wiring and signal paths.
5. Adjustment, Removal, and Replacement Information (SP500-SP540) - Contains reference information used for card and component replacement.
SY27-2521-3
Contents
5-SP-ii
SP100 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. SP110 Components and Addressing ........................ .
SP111 Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . SP112Addressing .................................. . SP 120 Basic Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . SP121 Panel Functional Operation . . . . . . . . . . . . . . . . . . . . . . . .
Displays....................................... . Hardware Indicators............................... . State Indicators.................................. . Mode Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Pushbuttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection Pushbuttons ............................. . Action Pushbutton/Indicators ........................ . SP130 Adapter-Unique Repair Strategy ...................... . SP132 DPPX Repair Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP134 Intermittent Failure Repair Strategy ................. .
SP200 Offline Tests ................................... . SP210 Offline Test Routine Descriptions ..................... .
SP211 Adapter Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP212 Manual Intervention Panel Tests . . . . . . . . . . . . . . . . . . . . . SP230 Test Message Formats and Status Registers . . . . . . . . . . . . . . . . SP231 Adapter Test Message Formats . . . . . . . . . . . . . . . . . . . . . . SP232 Manual Intervention Test Message Format . . . . . . . . . . . . . . SP233 EFP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EFP Control Register .............................. . Expanded Panel Registers Other Than Control and BSTAT ..... . SP240 Test Messages and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . SP241 EFP Offline Test Messages . . . . . . . . . . . . . . . . . . . . . . . . . SP242 Manual Intervention Test Messages and Procedures . . . . . . . . . SP250 Action Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EFP Initial Action Plan Procedure ..................... . Action Plan Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP251 Visually-Detected Failure Action Plans................ . SP252 Adapter Failure Action Plans . . . . . . . . . . . . . . . . . . . . . . . SP253 Panel Failure Action Plans . . . . . . . . . . . . . . . . . . . . . . . . . Keypad Failure Action Plan........................... . Hex Display Card Failure' Action Plan . . . . . . . . . . . . . . . . . . . . Mode and State Indicator Card Failure Action Plan . . . . . . . . . . . SP254 Cable Check Action Plan . . . . . . . . . . . . . . . . . . . . . . . . . .
SP300 Intermittent Failure Repair Strategy ................... . SP310 Adapter-Unique Intermittent Repair Strategy ............. . SP350 Action Plan to Correct Intermittent Failures . . . . . . . . . . . . . . .
SP400 Signal Paths and Detailed Operational Description . . . . . . . . . . . SP410 Point-to-Point Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . SP420 Card and Top Card Connector Signals . . . . . . . . . . . . . . . . . . . SP430 Expanded Panel FRU Component and Connector Diagrams .... . SP450 Detailed Data Flow .............................. .
SPSOO Adjustment, Removal, and Replacement Information . . . . . . . . . SP510 Adapter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SP520 Keypad ...................................... . SP530 Hexadecimal Display Card .......................... . SP540 Mode and State Indicator Card . . . . . . . . . . . . . . . . . . . . . . . .
5-SP-1 5-SP-1 5-SP-1 5-SP-3 5-SP-3 5-SP-4 5-SP-4 5-SP-4 5-SP-4 5-SP-4 5-SP-4 5-SP·6 5-SP-6 5-SP-6 5-SP-6 5-SP-6
5-SP-7 5-SP-7 5-SP-7 5-SP-8 5-SP-10 5-SP-10 5-SP-11 5-SP-11 5-SP-11 5-SP-12 5-SP-12 5-SP-13 5-SP-13 5-SP-15 5-SP-16 5-SP-16 5-SP-16 5-SP-16 5-SP-17 5-SP-17 5-SP-17 5-SP-18 5-SP-19 5-SP-19
5-SP-21 5-SP-21 5-SP-21
5-SP-23 5-SP-23 5-SP-24 5-SP-25 5-SP-30
5-SP-33 5-SP-33 5-SP-33 5-SP-33 5-SP-33
Figures
SP111-1. SP111-2. SP111-3. SP121-1. SP254-1. SP254-2.
SP254-3. SP254-4. SP254-5. SP410-1. SP410-2. SP420-1. SP420-2. SP430-1. SP430-2. SP430-3. SP430-4.
SP430-5.
SP430-6. SP430-7. SP430-8. SP450-1. SP450-2. SP500-1. SP500-2. SP500-3.
EFP Adapter Card and Card Assembly............. . EF Panel, BOP Adapter Card, and EFP Cable Assembly .. EF Panel FRU Components (Rear View) . . . . . . . . . . . . Basic and Expanded Function Operator Panel . . . . . . . . . Hex Display Card-to-Power Connections . . . . . . . . . . . . EFP Adapter Card-to-EFP Mode and State
Indicator Card Wiring . . . . . . . . . . . . . . . . . . . . . . . . EFP Adapter Card-to-EFP Keypad Wiring . . . . . . . . . . . EFP Adapter Card-to-EFP Hex Display Card Wiring .... . EFP Adapter Card-to-BOP Adapter Card Wiring . . . . . . . E FP Point-to-Point Signal Path . . . . . . . . . . . . . . . . . . . Processor-PSCF-BOPA Card Signal Path . . . . . . . . . . . . . EFP Adapter Card Signal Lines (Pin Side) . . . . . . . . . . . EFP Adapter Card Signal Lines (Card Side) . . . . . . . . . . E FP Keypad Card . . . . . . . . . . . . . . . . . . . . . . . . . . . EFP Adapter Card-to-EFP Keypad Wiring . . . . . . . . . . . Mode and State Indicator Card (Front View) . . . . . . . . . EFP Adapter Card-to-EFP Mode and State
Indicator Card Wiring . . . . . . . . . . . . . . . . . . . . . . . . Mode and State Indicator Card-to-Power
Connections ............................. . Hexadecimal Display Card (Front Vi~w) . . . . . . . . . . . . EFP Adapter Card-to-EFP Hex Display Card Wiring .... . Hex Display Card-to-Power Connections . . . . . . . . . . . . EFP Adapter Card Data Flow Diagram ............ . EFP Adapter Card-to-BOP Adapter Card . . . . . . . . . . . . BOP and EFP Access . . . . . . . . . . . . . . . . . . . . . . . . BOP and EFP Frame Mounting . . . . . . . . . . . . . . . . . . BOP and EFP Component Bezel Mounting . . . . . . . . . . .
5-SP-1 5-SP-2 5-SP-2 5-SP-5 5-SP-19
5-SP-19 5-SP-20 5-SP-20 5-SP-20 5-SP-23 5-SP-24 5-SP-24 5-SP-25 5-SP-25 5-SP-26 5-SP-26
5-SP-27
5-SP-27 5-SP-28 5-SP-29 5-SP-29 5-SP-30 5-SP-31 5-SP-33 5-SP-34 5-SP-34
Abbreviations
BOP BOPA BSTAT conn DAT DPPX EF EFP EIR EIRV EN EXPO flt pt FRU hex insn 1/0 IPL LED MAP MD Ml op PA PIO PSCF RECD reg SCF
basic operator panel basic operator panel adapter Basic status register connector dynamic address translation Distributed Processing Programming Executive expanded function Expanded function operator panel error interrupt request error interrupt request vector error number expected data floating point field-replaceable unit hexadecimal instruction input/output Initial program load light emitting diode Maintenance Analysis Procedure Maintenance Device Manual Intervention operation Physical Address programmed 1/0 primary system control facility received data register System Control Facility
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SP100 General Information
This SP section provides the reference information used to perform fault isolation for the 8140 Processor expanded function operator panel (EFP) feature. It should be used in conjunction with the EFP MAP, which can only be run offline using the Maintenance Device (MD). The MAP and EFP tests reside on MD diskette 01, and use reference material contained in this section for information such as hardware components and addressing, wiring checks, offline test routine descriptions and messages, and possible failure causes.
SP110 Components and Addressing
This section contains information to assist in understanding the EFP physical components. It also describes the software addressing scheme and the configuration table entry used to specify the EFP.
SP111
Hardware Components The EFP is a physical extension of the basic operator panel (BOP).
Refer to Figure
SP120-1 for an illustration of the basic and expanded operator panels. The EFP uses
one adapter card that plugs into the processor board, whose location depends on the
8140 model selected : · Models A31-34 use board position A1M2. · Other A models use board position A1P2. · B models use board position A 1S2.
The adapter card, board wiring and a single, multi-ended cable assembly provide the EFP hardware necessary for panel-to-processor information transfer. One of the cable connectors plugs into the top card connector "Z" position of the EFP adapter card, and the wires connected to it terminate at another connector that plugs into the basic operator panel keypad. In the same manner, the cable that plugs into the EFP adapter card ''W" top card connector position plugs into the expanded panel's mode and state indicator card, the "X" connector to the EFP keypad card, and the "Y" connector to the EFP hexadecimal display card. The following chart shows the W, X, Y and Z
connections:
Connector
w x
y
z
Attaches EFP Adapter Card To
EFP mode and state card EFP keypad card EFP hex display card BOP Data/Function pushbuttons
Additional wires in this cable assembly connect system power to the EF panel, and others terminate in a connector that plugs into the BOP Data/Function pushbutton keypad to permit its use by the EFP. Refer to Figures SP111-1 and SP111-2 for illustration of the cabling used to connect the EFP and its associated components.
Other than the adapter card, the EFP has three FR Us that attach to the rear of the panel (see Figure SP111-3): hexadecimal display card, EFP keypad card, and mode
and state indicator card.
01E
'
·I 11 1I' I I II I I I I
II II I
1I I
Notes: 1. This cable is actually four flat cables, shown for illustration only. Each cable
connects to the card by a double male pin-connector, PN 5997533. 2. Card location depends on 8140 model. See SP111 "Hardware Components."
Figure SP111-1. EFP Adapter Card and Cable Assembly
SY27-2521-3
(SP100-SP111)
Note 1
5-SP-1
Note 1 ----------
Keypad Card
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1 l
J1
J
J2
E FP Hex Display Card
01 F-A1A3
EFP Keypad Card 01F-A1A2
1
r l
J3
~-.,
J40
J5 Mode and State Indicator Card
01F-A1 A1
J6
l J
Figure SP111-3. EF Panel FRU Components (Rear View)
5-SP-2
Note 1: This is actually a multiended cable assembly shown for illustration only. Note 2: BOP Adapter Card lays flat under the Operators Panel in 81408 Models.
Figure SP111-2. EF Panel, BOP Adapter Card, and EFP Cable Assembly
SP 112 Addressing
The EFP adapter has a fixed physical address (PA) of hex OA, and all EFP to processor data transfer occurs through the system control facility (SCF) by using this address.
SP120 Basic Operational Description
The EFP feature, available only on the 8140 Models A31-34, A41-44, A61-64, A71-74, and B51-72, combines hardware and software facilities to permit user access to the information contained within certain processor areas. Primarily, a programmer uses the EFP as an adjunct to conventional software troubleshooting aids.
Note: The system must be offline to use the EFP.
A typical EFP application would be to test and debug any control program that the customer can modify, such as the IBM Distributed Processing Programming Executive (DPPX). It can also be used to debug any application or 1/0 programs.
The EFP adapter card: · Controls all instructions sent to the EFP. · Physically and logically attaches the EFP pushbutton functions and indicators to
the EFP program through the system direct control bus and system control facility. This permits processor hardware access so that the user can:
Stop on system check/program exception conditions. Know when dynamic address translation occurs. Perform address compares. Know the current and last levels of processor instruction execution. Determine the mode of processor instruction execution. Know what PSV was used for each instruction.
The EFP feature allows you to read and write to the following areas through programming:
Storage locations Registers Translation table Instruction addresses Program status vectors Address control vectors
In addition to the read and write capabilities, the EFP provides several special functions, which:
Transform an address. Stop on an address compare. Step instructions. Start and stop processing. Stop when detecting a system check/program exception.
With the EFP, certain conditions can be indicated by using discrete LEDs: If using EFP register 1 If using EFP register 2 The processing instruction mode If a primary or secondary PSV is in use If using dynamic address translation If the processor is stopped If the BOP Data/Function pushbuttons are logically locked
The remaining LED indicators have a 4 x 7 matrix that indicates the current and last processing level and the contents of EFP registers 1 and 2.
Note: Only DPPX provides commands to enable and disable EFP operation.
The EFP presents 1/0 interruptions to the processor on priority level zero and uses
physical address hex OA, and both assignments are fixed. During actual interrupt presentations, only the Enable/Disable EF Panel pushbutton remains active. The EFP adapter enables the transfer of information from the panel to the processor. This in-
formation transfer occurs on the programmed 1/0 signal bus using only PIO halfword
commands, and does not use any CHIO-type operations.
SY27-2521-3
(SP111 Cont-SP120)
5-SP-3
SP 121 Panel Functional Operation
The following text describes the function of the displays, pushbuttons, and indicators of the expanded function operator panel (EFP). See Figure SP121-1.
Displays Hardware Indicators
The eight position hexadecimal display, a Current or Last Level display, 15 discrete LED indicators, and 23 pushbuttons are divided into functionally associated groups. The following lists and describes the panel components by group:
There are two displays used to indicate hexadecimal values:
Current or Last Level - Normally displays the current level, and used in conjunction with the Display Last Level pushbutton to indicate the last priority level (1-7 and not 0) active for the presently executing program.
Address or Data - Has eight hexadecimal positions and displays either data or address information. Depending on the status of EFP control register bit 4 that controls the Reg 1 and Reg 2 indicator status, the hex display contains either the register 1 or register 2 value. The characters enter the rightmost position and move to the left for successive entries. When all eight positions contain characters, each additional entry eliminates the leftmost position.
Operator Attention/EF Panel - The last expanded operation was incorrect. EFP control register bit 6 determines the indicator status, which blinks twice a second when on.
EF Panel Check - A parity check occurred during a programmed information exchange to the panel, or an interruption occurred in the physical panel cable interconnection.
Reg 1 - When on during a store, fetch, or display operation, the hexadecimal display indicates the Register 1 Value. Either the Access Address Reg 1 pushbutton or a clear or default operation activates this indicator.
Reg 2 - When on during a store, fetch, or display operation, the hexadecimal display indicates the Register 2 value. The Access Data Reg 2 pushbutton activates this indicator, which cannot be on the same time as the Reg 1 indicator.
DAT Active - Dynamic address translation is being used to access processor storage. All addresses generated are logical, and the address translation occurs on the level specified by the Current or Last Level display. The address mode register value determines the indicator status.
Primary (Seedy) PSV - Indicates whether the last instruction used a primary (indicator on) or secondary PSV for the processing level specified by the Current or Last Level display. Used in conjunction with the Display Last Level pushbutton to indicate the previous PSV used.
SY27 -2621-3 State Indicators
MQde Indicators Logical Pushbuttons
5-SP-4
Keyboard Locked - When on permits no functional keypad input except for the following pushbuttons: (1) Enable/Disable EF Panel. (2) Reset/Restore. (3) Display Last Level, (4) Access Address Reg 1, and (5) Access Data Reg 2. EFP control register bit 7 on turns on this indicator, and the Reset/Restore pushbutton resets it. Refer to SP233 for the conditions that turn on control register bit 7.
Processor Stopped - Priority Levels 1-7 are not active and processor is at level 0. Turned on by an address compare stop condition, a system check/program exception stop, or pressing the Stop pushbutton. EFP control register bit 5 determines the indicator status.
The discrete LED mode indicators correspond to the program mode active when executing on the current priority level (1-7) specified by the Current or Last Level display. The program mode register determines which indicator turns on according to information in the current program status vector PSV. The mode indicators are: Master, Supervisor, 1/0, and Application.
Clear EF Panel - Resets registers 1 and 2 to zero, and turns on the Reg 1 indicator. Resets the transform address bit (3) and the access register 2 bit (4) in the EFP basic status register, System Check on the BOP, and the Reg 2, Operator Attention, and Panel Check indicators on the EFP.
Display Last Level - When held, displays the priority level (1-7 and not O) of the last active instruction in the Current or Last Level indicator, and permits display of the PSV used in the Primary (Seedy) PSV indicator.
Access Address Reg 1 - Turns on the Reg 1 indicator and selects register 1 to receive any entry from the BOP Data/Function pushbuttons. Also pressed to return to register 1 after completing register 2 processing.
Access Data Reg 2 - Turns on the Reg 2 indicator and selects register 2 to receive any entry from the BOP Data/Function pushbuttons indicator. Resets the transform address bit (3) and the access register 2 bit (4) in the EFP basic status register, System Check on the BOP, and the Reg 2, Operator Attention, and Panel Check indicators on the EFP.
Enable/Disable EF Panel - Enables or disables the expanded function panel and also transfers control of the Reset/IPL and Lamp Test pushbutton functions and hex key· pad operation to the EFP. The keylock switch, if installed, must be set to Enable to permit operation.
Expanded Function Panel
Basic Operator Panel
Operator Attention EF Panel
0
EF Panel Check
0
DAT Active
Reg 1 Address or Data
0
_, 8 c-: 9 8 0
Reg 2
0
,~ ,-i ...1
I -;e
I
I
I
Primary (Seedy)
PSV
0
State
Keyboard Locked
0
Processor Stopped
0
Mode
~ Supervisr
0
Action
Clear EF a t o r e[display Function Panel
DODD
Transform Address
D
Storage Address Compare Stop Fetch
0 D
Storage Address Compare Stop Store
0 D
Stop on System Check/ Program Excpn
0 D
Selection
Storage Register Location
D D
Address lnsn Control Address
D
Compare Stop Address
D
D
Display
Last Level
D
Access Address Reg 1
D
Translatn Table Entry
D
Program Status
D
Access Data Reg 2
D
Enable/ Disable EF Panel
D
lnsn Step
D
5J 5J
Reset/ Restore
D
Operator System Attention Check
0 0
1/0 Interface
Check
0
Panel Check
0
(]
, 4
'1'
1-\
.,..,.
I,·_'I
( ] Test Mode 0
I'\
/
Clear Display
Enter Data
Enter Function
Reset/ IPL
D DD D
Data/Function
IL
~
r5JBBB
BBBB
BBBB Processor Test D
bIBBB Lamp Test D
Power On Disabled
0 [ ; ]
Power/ Thermal Check
0
.,__ _""'oPnower
~
0 Power
i;;;;;;;;;;;;;;;;J Off
IPL Mode
Power Only
Figure SP121-1. Basic and Expanded Function Operator Panel
SY27-2521-3-
(SP121)
5-SP-5
Selection Pushbuttons Action Pushbutton/Indicators
Transform Address - Operates in conjunction with pushbuttons in the same row used to address the processor, registers, or storage, in either store or display modes. When pressed, transforms the logical address contained in register 1 into a real address, places it in register 2, and turns on EFP BSTAT bit 3. It is reset by the Clear Panel pushbutton.
Storage Location -When pressed, EFP BSTAT bit 2 turns on, and the next valid access is to the storage location specified by the register 1 value.
Register -When pressed, EFP BSTAT bit 1 turns on, and the next valid access is to the register location specified by register 1.
Translatn Table Entry - When pressed, EFP BSTAT bits 1 and 2 turn on, and the next valid access is to the translation table address specified by the register 1 value.
Address Control -When pressed, turns on EFP BSTAT bits 0, 1, and 2, and selects the specified adjunct register addressing information.
lnsn (Instruction) Address - Pressed before a display or store operation, it displays or alters the first 32 bits of the PSV (instruction address) located in register 1, and turns on EFP BSTAT bit 0.
Program Status - Pressed before a display or store operation, it displays or alters the last 32 bits of the PSV, but not the instruction address, and turns on EFP BSTAT bits 0 and 2.
Compare Stop Address - Used in conjunction with Storage Address Compare Stop Fetch or Store pushbuttons, stores the register 1 address in the compare stop address register, stops processing when the addresses agree, and turns on EFP BSTAT bits O and 1.
Display Last Level - When held, displays the priority level (1-7 and not 0) of the last active instruction in the Current or Last Level indicator, and permits display of the PSV used in the Primary (Seedy) PSV indicator.
Access Address Reg 1 - Turns on the Reg 1 indicator and selects register 1 to receive any entry from the BOP Data/Function pushbuttons. Also pressed when returning to register 1 after completing register 2 processing.
Access Data Reg 2 - Turns on the Reg 2 indicator and selects register 2 to receive any entry from the BOP Data/Function pushbuttons.
Store - Either (1) places the contents of register 2 into the address specified by register 1, or (2) displays the contents of the address indicated in the hex display.
Display - When pressed in conjunction with a selection pushbutton, causes display of the address in register 1 according to th.e selection pushbutton used. If Transform Address was pressed for a display address function, the address is logical.
Function - Only ~ctive when in stop mode, and uses the register 1 contents for display or store operations according to the selection pushbutton pressed. This pushbutton can also be used to display the control vectors by using 28 control immediate (Kl) instructions. Any store operation must have previously placed data in register 2.
SY27-2521-3
5-SP-6
lnsn (Instruction) Step - Executes one instruction at the level indicated, and displays the PSV instruction address in register 1. The processor must be stopped for this to occur, and interruptible instructions do not execute completely by pressing this pushbutton once.
Start - Begins instruction execution at the highest pending interrupt level if the processor was previously in stop mode.
Stop - Turns on the Stop indicator and stops instruction execution. Last level display procedures indicate the last executed address, and logic forces a current processing level of zero.
Reset/Restore - Resets the processor but not the EFP logic, turns off the Keyboard Locked indicator if on, enables all EFP pushbuttons, turns on EFP BSTAT bits 8, 9, 10, and 15, and requests an interrupt if EFP BSTAT bit 14 is on.
Storage Address Compare Stop Fetch - Operates in conjunction with the Compare Stop Address pushbutton. Specifies that if the address compare register contents are identical with the priority level, PSV selection, and processor address used during a fetch storage operation, processing stops and the indicator turns on. EFP control register bit 0 determines the indicator status.
Storage Address Compare Stop Store - Operates in conjunction with the Compare Stop Address pushbutton. Specifies that if the address compare register contents and a processor storage address compare during a store operation, processing stops. EFP control register bit 1 determines the indicator status.
Stop on System Check/Program Excpn - Stops instruction execution after detecting a system check/program exception error. When this condition occurs, the panel indicators show either the failing instruction or the next instruction, together with status information. EFP control register bit 2 determines the indicator status, and the pushbutton turns on EFP BSTAT bit 6.
SP130 Adapter-Unique Repair Strategy
The following sections refer to those repair strategies that are unique to the EFP. Refer to the Chapter 4 general maintenance approach section for those that are common to the 8100.
SP132 DPPX Repair Strategy
The EFP cannot be tested online under DPPX.
Caution: Serious damage to the customer control program could result from improper operation of the EFP.
SP134 Intermittent Failure Repair Strategy
For intermittent EFP error action plans, refer to section SP300.
SP200 Offline Tests
All testing and repair of the EFP occurs offline. These tests reside on MD diskette 01, and require system dedication to verify operation or isolate failures, some of which may require manual intervention. The test can be initiated by specifying physical address hex OA and the desired options.
The MAP either detects a failure in the adapter card, or prompts you to perform some action at the panel. As a result of this action, the test compares the results received with the results expected. If the MAP detects an error, refer to section SP250 for repair action according to the failure. If the MAP does not isolate the failure, refer to section SP250 for further corrective action.
SP210 Offline Test Routine Descriptions
The first group of routines verify proper adapter card operation, and the last group permits you to perform manual intervention routines to determine panel problems. The adapter routines complete in less than 4 seconds, while the time required to run the manual intervention routines is operator-dependent. The SP MAP uses two logical sections: Routines 1-19 test only the ~dapter, while Routines 20-31 test the LED indicators, panel switches, and cables, including the adapter functions necessary to operate them.
The MD invokes the adapter routines either by the MAP or by using the Free-Lance Utility.
· When using the MAP, the tests are invoked automatically when required. · When using the Free-Lance Utility, the following test invocation procedure must
be used: 1. At 80BC or PAOO, enter 08PAB. 2. At 81BC, enter SLRRB.
Where: PA= adapter address (always OA) S = sense option: O run only adapter tests, Routines 1-19, without using loop option 1. run adapter tests, Routines 1-19, using loop option 1. 2 run adapter/device tests with manual intervention, routines 1-31
l = loop option: 0 run selected routines one time. loop selected routines; stop on error. 2 loop selected routines; bypass error.
RR =routine number. If 00 or no entry is made, all routines for sense option are run. If a routine number is entered, only that routine is run.
B = begins execution and enters the invocation message.
OAOO indicates successful completion of the adapter tests. For more information on test invocation and operation, refer to CP600 Common Test Procedures and Messages in Chapter 2.
SP211 Adapter Tests
SY27-2521-3
These routines test the adapter hardware, EFP 1/0 commands, and the SCF to EFP signal bus. The following describes the adapter test routines and the function performed by each.
Routine 1, Reset Adapter Test. The processor issues a Reset Adapter command to the EFP. This determines if the EFP recognizes the hex OA address used for all EFP information transfer, and resets the EFP registers to zero. The test then issues read commands to determine if the adapter was completely reset. This routine tests the Reset Adapter, Read Basic Status, Read Register 1 Low, Read Register 1 High, Read Register 2 Low, Read Register 2 High, and Read Control Register commands. The valid routine test error messages are hex 0101, 0104, and 0120 to 0125.
Routine 2, E FP Basic Status Register Test. Issues Read and Write PIO commands to test the EFP basic status register and to verify that all bits set and reset correctly. This routine also tests proper operation of the adapter drivers and receivers common to all registers. It uses five data patterns, and tests the Set BSTAT and Reset BSTAT EFP commands. The valid routine test error messages are hex 0201, 0204, and 0220 to 0222.
Routine 3, EFP Interrupt Request Test. The EFP uses mostly interrupt requests for processor information transfer. This test enables the EFP interrupt request logic and conditions the EFP BSTAT to request an interrupt. The interrupt then occurs, and the EFP status indicates a pending interrupt request. The valid routine test error messages are hex 0301, 0304, 0305, and 0320.
Routine 4, Control Register Data Test. The 8-bit control register determines operation of address compare stop, system check/program exception stop, keyboard lock, enable panel, and indicator functions. This test verifies the correct set and reset of the control register data. It uses Read and Write commands to store and fetch the five data patterns used, and checks the Write Control Register command. The valid routine test error messages are hex 0401, 0404, and 0420.
Routine 5, Register 2 High Data Test. Control register bit 3, if active, permits access to EFP register 2. This 32-bit register has both a high and a low data area, each of which determines four EFP hexadecimal display values. Data characters enter the rightmost half byte and shift all other characters to the left. When full, each subsequent entry causes loss of the high-order position. This routine verifies that the 16 high-order register 2 bit positions can be correctly set and reset. It uses Read and Write commands to store and fetch the five data patterns used, and checks the Write Register 2 High command. The valid routine test error messages are hex 0501, 0504, 0520 and 0521.
Routine 6. NOT USED.
Routine 7, Register 2 Low Data Test. Verifies the correct set and reset of the 16 loworder register 2 bit positions. It uses Read and Write commands to store and fetch the five data patterns used, and checks the Write Register 2 Low command. The valid routine test error messages are hex 0701, 0704, 0720, and 0721.
Routine 8, Register 1 Low Data Test. Control register bit 3, if off, permits access to EFP register 1. This 32-bit register has both a high and a low data area, each of which determines four EFP hexadecimal display values. This routine verifies the correct set and reset of the 16 low-order register 1 bit positions. It uses Read and Write commands to store and fetch the five data patterns used, and checks the Write Register 1 Low command. The valid routine test error messages are hex 0801, 0804, 0820 and 0821.
(SP121 Cont-SP211)
5-SP-7
Routine 9, Register 1 High Data Test. Verifies the correct set and reset of the 16 highorder register 1 bit positions. It uses Read and Write commands to store and fetch the five data patterns used, and checks the Write Register 1 High command. The valid routine test error messages are hex 0901, 0904, 0920, and 0921.
Routine 10, Address Compare Test. Places a test address value in the EFP address registers and sets the level compare to zero to compare only the test address value. It sets both store and fetch compare bits in the control register, and then fetches the test address. The test then verifies that an interrupt occurred, reads the status, and compares it to the expected value. The routine uses the Write Address Compare Register High and Write Address Compare Register Low commands. The valid routine test error messages are hex 1001, 1004, 1005, and 1020.
Routine 11, Store Address Compare Test. Fetches storage location hex OOOQ and sets up an address compare condition for a store to this location. It then stores the previously fetched data, and an address compare occurs. The test then performs the same operation on storage locations OOOOF FF E to 0007F FF E by incrementing address byte 1, and an equal compare should occur on each store. The valid routine test error messages are 1101, 1104, 1120,and 1121.
Routine 12, Fetch Address Compare Test. Uses storage address locations hex 0000 and FFFF to test the EFP fetch address compare logic. It conditions the control register to stop on a fetch address compare, fetches storage location hex 0000, and ensures that an equal compare occurs. It then fetches storage location hex FFFF and also ensures that an equal compare occurs, and, in both cases, checks proper status and interrupt conditions. The valid routine test error messages are hex 1201, 1204, and 1220 to 1222.
Routine 13, No Stop on Store or Fetch Compare Test. Places a test address, in the address compare register and then conditions the control register to stop on a store compare operation. It then fetches the test address and no equal compare should occur.
Next, it conditions the control register to stop on a fetch to the test address, performs a store to it, and does not expect an equal compare. The routine checks for proper status after each test location access. The valid routine test error messages are hex 1301, 1304, 1320, and 1321.
Routine 14, Processing Level Address Compare Test. Performs an address compare fetch on processing levels 1-7, using both the primary and secondary PSVs, and
checks that the compare occurs only on the proper level with the correct PSV. It
first conditions the address compare register for a specific level and PSV, executes on all levels, and then ensures that the compare occurred only for the correct level. The routine uses the secondary PSV for 49 passes and then uses the primary PSV for 49 more. It checks status for each valid compare to ensure proper operation, and uses the BOP to display errors if either no compare occurs on any level, a compare error occurs, ,pr for incorrect status after a compare. The valid routine test error messages are hex 1401, 1404, and 1420 to 1422.
Routine 15, Interruptible Instruction Compare Test. Verifies that an address compare causes an interrupt request at the proper time. It first conditions the address compare register to compare on the first byte of a storage field, then issues an MVRS interruptible instruction to move data from the test field to another field. The address compare interrupt should occur on the first MVHS instruction data fetch. The test
SY27-2521-3
5-SP-8
verifies correct operation by saving the count register when the interrupt occurs, and comparing it to the expected count when instruction execution completes. The valid routine test error messages are hex 1501, 1504, and 1520.
Routine 16, No Compare on Unsuccessful Branch. After conditioning the address compare logic to compare on the target of an unsuccessful branch, it executes the branch instruction and no branch or compare should occur. The valid routine test error messages are hex 1601, 1604, and 1620.
Routine 17, Stop on Instruction Fetch Test. Verifies that the panel presents an interrupt request at the proper time on an address compare during instruction fetch. It first conditions the address compare logic with an invalid op code, and then executes the instruction. The address compare should occur before the program check.
It next conditions the address compare logic, using the second half of an MVHS instruction, and executes a Kl swap to the primary PSV. The address compare should occur before the Kl swap. The valid routine test error messages are hex 1701, 1704, 1720, and 1721.
Routine 18, Stop on System Check/Program Exception Test. This routine first conditions the EFP to stop on either a system check or a program exception. It then issues an invalid command of hex FF to the EFP that causes a system check. The test then examines panel status to verify that the panel interrupted processing when the system check occurred.
Next, the test saves the level 7 primary PSV, changes it to point to the routine's program exception handler, and executes an op code of hex FF FF, which causes a program exception. It then stores the primary PSV, returns to the secondary PSV for program execution, and checks status to verify that the panel interrupted processing when the program exception occurred. The valid routine test error messages are hex 1801, 1804, 1820, and 1821.
Routine 19, Invalid Command Test. The previous routines tested all valid commands. This routine issues all the invalid EFP commands from hex 00 to FF, each of which should cause a system check. After issuing each invalid command sequence, the test checks EFP status to determine if the proper response occurred. The valid routine test error messages are hex 1901, 1904, 1920, and 1921.
SP212 Manual Intervention Panel Tests
The manual intervention EFP routines test the panel logic, indicators, pushbuttons, and the panel adapter signal bus. This section describes these routines. Refer to SP242 for actions required by manual intervention messages.
Routine 20, EFP Operator Attention Indicator Test. Blinks the Operator Attention indicator and prompts you for a response to this condition. The MD display indicates an error for a negative response, and the BOP displays test error messages of either hex 2001.or 2004 if unexpected system conditions occurred during the test.
Routine 21, Action Pushbutton Test. Tests the function of the Display, Store, Start, Function, lnsn Step, Stop, Reset/Restore, Storage Address Compare Stop Fetch, Storage Address Compare Stop Store, and Stop on System Check/Program Excpn pushbuttons.
The routine enables the EFP pushbuttons and uses the MD to prompt you for activation of these pushbuttons in the specified order. When each pushbutton generates an interrupt request, the test checks the corresponding EFP BSTAT bit to verify that it turned on. The BOP displays valid test error messages hex 2121, 2123, 2125, 2127, 2129, 2131, 2133, 2135, 2137, and 2139 for incorrect pushbutton functional operation, and 2101 and 2104 if unexpected system error conditions occurred.
Routine 22, Selection Pushbutton Test. Tests the function of the Storage Location, Register, Translation Table Entry, Address Control, lnsn Address, Program Status, Compare Stop Address, and Transform Address pushbuttons.
The routine enables the EFP pushbuttons and prompts you from the MD. Each pushbutton should be pressed in the specified order. followed by the Start pushbutton to generate an interrupt request. The test then checks the corresponding EFP BSTAT bit to verify that it turned on. The BOP displays valid test error messages hex 2221 to 2225 and 2236 to 2238 for incorrect pushbutton functional operation, and 2201 and 2204 if unexpected system error conditions occur.
Routine 23, Reg 1, Reg 2 and Hexadecimal Display LED Test. The MD prompts you if all patterns should be tested, and, if not, uses only hex 0000 and FF FF. The test first places hex 00000000 in register 1 and hex BADOBADO in register 2, and prompts you to verify that the hexadecimal display output from register 1 contains zeros with the Reg 1 indicator on. The test then reverses the register 1 and register 2 values and performs the same operation. The Reg 2 indicator should now be on, Reg 1 off, and the register 2 display value should be all zeros.
The test steps to either hex 11111111 or FFFFFFFF, depending on the option selected, performs the same operation with the new register values, and prompts for response to the display and indicator conditions. A negative response to the MD prompt results in an error message on the MD display, and the BOP displays test error message numbers hex 2301 and 2304 when unexpected system error conditions occur.
Routine 24, Action Pushbutton Test. Tests the Enable/Disable EF Panel, Clear Panel, Access Address Reg 1, and Access Data Reg 2 pushbuttons.
The test first turns on the EFP control register operator attention bit, but does not enable the panel. The MD then prompts you to press the Enable/Disable EF Panel pushbutton, followed by the Start pushbutton.
Note: The Start pushbutton did not function properly if the panel pushbuttons remain inoperative. Before continuing, the test checks for valid basic staws.
The MD prompts for your response after observing if the Operator Attention indicator blinks. An EF panel reset then occurs, and BSTAT bits 3 and 14 turn on.
Next, the test fills registers 1 and 2 with hex FF FF FF FF and accesses register 2 with the Operator Attention indicator still blinking. The test prompts you to press the Clear Panel pushbutton and enter a '1' in the MD keypad. The EFP BSTAT should now have bit 3 reset, registers 1 and 2 should be all zeros, and the control register attention and access register 2 bits should be off. The test then resets the panel.
Finally, the test fills register 1 with hex 11111111, register 2 with hex 22222222, and accesses register 2. The prompt message requests verification of the display value, followed by pressing the Access Address Register 1 pushbutton. You should
SY27-2521-3
verify the register 1 display value of hex 11111111, press the Access Data Register 2 pushbutton, and verify the register 2 display value of hex 22222222.
The BOP displays valid test error messages hex 2421 and 2424 to 2427 for functions checked by this routine, and hex 2401 and 2404 when unexpected system errors occur.
Routine 25, Data/Function Pushbutton to Register 1 and 2 Exerciser. Checks the BOP Data/Function pushbutton encoding logic and the Data/Function pushbutton to register 1 and 2 data path. The MD prompts you to access registers 1 and 2 from the keypad. The test terminates by pressing Stop.
The MD prompt message then asks if the test functioned properly. A negative response prompts an MD display error message, and unexpected system error conditions display valid test error message numbers hex 2501 and 2504 on the BOP.
Routine 26, Data/Function Pushbutton locked Test. Enables the panel and logically locks the Data/Function pushbuttons. The MD then asks you to check that the pushbuttons do not operate and that the Keyboard Locked indicator turned on. A negative response prompts an MD error message, and unexpected system error conditions cause the BOP to display valid test error message numbers hex 2601 and 2604.
Routine 27, Compare Stop and Processor Stopped Indicator Test. Tests the Storage Address Compare Stop Fetch, Storage Address Compare Stop Store, Stop on System Check/Program Excpn, and Processor Stopped indicators. The test turns on each indicator one at a time, and prompts a response from the MD for proper indicator operation. A negative response prompts an MD error message, and unexpected system error conditions cause the BOP to display valid test error message numbers hex 2701 and 2704.
Routine 28, Panel Check Test. Tests the panel check logic by attempting to execute an invalid command. The test first enables the panel indicators and issues an invalid command. This causes a system check, which should turn on the EF Panel Check indicator. The MD asks if the indicator is on, and displays an error message for a negative response. The MD then prompts you to press the Clear Panel pushbutton and ensure that the Panel Check indicator turned off. The MD again displays an error message for a negative response, and unexpected system errors result in valid test error messages hex 2801 and 2804.
Routine 29, DAT Active Test. Tests the panel's capability to detect and display dynamic address translation mode. The routine first builds a translation table that assigns the same actual storage locations to real addresses 0-66K and logical addresses 0-64K. It then sets the level 7 adjunct register contents to logical address values.
The MD instructs you to press the Start pushbutton to cause a level 0 interrupt. The test then returns to level 7 in logical addressing mode, which should turn on the expanded panel DAT Active indicator.
Next, the test restores the level 7 adjunct registers to real addressing values and prompts you to press Start if the DAT Active indicator turned on or Stop if it did not. Either pushbutton causes an interrupt to level 0, restores the processor to real addressing mode, and returns to level 7 processing. The test then checks status to determine the pushbutton used. The BOP displays the error message hex 2922 if it was the Stop pushbutton, and also displays test error messages 2901 and 2904 for unexpected system error conditions.
(SP211 Cont-SP212)
5-SP-9
Routine 30, Mode Indicator Test. Checks the Master, Supervisor, 1/0, and Appl mode indicators and logic.
After initiating the routine, the MD asks you to check the Supervisr mode indicator status. A negative reply places a test error message in the BOP display.
To test the other three indicators, the routine stores a test mode byte in a fixed storage location, and prompts you to press the Start pushbutton, which causes an interrupt to processing level 0. The level 0 interrupt handler then conditions level 7 for the test.
The test returns to level 7, and the indicator for the mode under test remains on for about 10 seconds. The MD then prompts you to press Start if the indicator comes on and then turns off, or Stop if it doesn't.
The test reads basic status after each operation to determine the pushbutton pressed, and each indicator must be tested three times. The BOP displays test error messages hex 3020, 3023, 3025, and 3027 for negative responses to the prompt message, and hex 3001 and 3004 if unexpected system error conditions occurred during testing.
Routine 31, Current or Last Level Display and PSV Indicator Test. Checks the Current or Last Level display, the Primary (Seedy) PSV indicator, and the Display Last Level pushbutton. During the test, the Current or Last Level indicator displays the level, and the Primary/Seedy PSV displays the mode.
The level steps once every 5 seconds for each primary level 1-7, and then repeats the stepping procedure using secondary mode. The eight-position hexadecimal display and Current or Last Level display provides test status information as follows, in conjunction with the Primary/Seedy PSV indicator:
8-Position Hexadecimal Display
0
Primary /Secondary PSV Indicator
L Expected Last Level Mode Expected Last Level Expected Current Level Mode Expected Current Level
Current or Last Level Indicator
I
Actual Last
Level
The routine uses the four leftmost positions of the EFP hexadecimal display to indicate the expected status:
· The first and third indicate the expected current and last processing levels (1-7)
· The second and fourth indicate the expected mode (primary or secondary):
If the second and fourth digits are 1's, the Primary/Seedy PSV indicator should be on (primary PSV).
If the second and fourth digits are O's, the Primary/Seedy PSV indicator should be off (secondary PSV).
SY27-2521-3
Press the Display Last Level pushbutton during the test to check the correct last processing level and mode.
When the test terminates, the MD asks if the display values compared and the Display Last Level pushbutton operated properly. A negative response displays an error on the MD. Unexpected system error conditions display test error messages hex 3101 and 3104 on the BOP.
5-SP-10
SP230 Test Message Formats and Status Registers
The following sections describe the format of the test messages generated when performing offline testing.
SP231 Adapter Test Message Formats The following test message formats occur when performing adapter Routines 1-19.
Test Messages
OAOO OAFO OA2E RREN OOMM 1111 OA2E RREN OOML 1111 OA2E RREN OOBS EXPO RECD
Meaning
Test ran successfully Tests running Format 1 error message Format 2 error message Format 3 error message
Where:
OA EFP physical address
2
Processing level
E
Error
RR Failing routine
EN Error number within the routine
00 Not used
MM = EI RV contents when failure occurred
1111 = Instruction address when failure occurred
ML = PSV used and processing level active when failure occurred
M= 0 Primary mode
M=
Secondary mode
L
Processing level
EXPO Expected data
RECD= Received data
SP232 Manual Intervention Test Message Format
The EFP manual intervention routines use format 1 test error messages (RREN) if an unexpected error occurs. They also display 73 prompt messages numbered from 1 to 74, with 73 not used. These messages prompt you to answer questions concerning status, or to perform certain procedures. The following message format occurs when performing Routines 20-31:
TEST MESSAGE
PAMI
Where: PA MI
EFP physical address hex OA Prompt message number
SP233 EFP Registers Basic Status Register
This section describes the EFP basic status and control registers and their bit meanings, as well as all other EFP registers.
The 16-bit EFP basic status register indicates the pushbuttons that were activated, equal compare conditions, adapter-detected error conditions, and interrupt priority request status. The bits are programmable, and also reflect the activation of certain EFP pushbuttons. The following table describes the bit meanings when on.
Bit
Pushbutton Pressed or Condition Detected
0-2
EFP selection pushbutton encode - Binarily determines which of
the Selection pushbuttons were pressed according to the following:
000 = None 001 = Storage Location 010 = Register 011 = Translation Table Entry 100 = lnsn Address 101 = Program Status
110 = Compare Stop Address
111 = Address Control
3
Transform Address pushbutton pressed.
*4
Storage address compare stop fetch condition occurred.
*5
Storage address compare stop store condition occurred.
*6
Stop on system check/program exception condition occurred.
SY27-2521-3
Bit
Pushbutton Pressed or Condition Detected
7
Reserved
*8-10
EFP Action pushbutton encode - Binarily determines which of the Action pushbuttons were pressed according to the following:
000 = None 001 = Display 010 = Store 011 = Start 100 = Function
101 = lnsn Step 110 = Stop 111 = Reset/Restore
11
Initialize - Only set by programming and reset by programming or
the Enable/Disable EF Panel pushbutton.
*12
Stop condition met - Address compare or system check/program
exception condition occurred. When detected with bit 14 on, (1)
signals the processor to stop execution and (2) in conjunction with
bit 15, requests a level 0 interrupt to ensure the EPF control program
receives control.
*13
Equipment check - One of the following conditions occurred:
· 1/0 command parity error from the channel
· Data parity error from the processor
· Invalid program command
· 1/0 operation occurred after the channel halted EFP operation. This condition does not present an interrupt request.
This EFP-detected error occurred while the channel was waiting for a valid EFP response which was suppressed by the EFP adapter. The channel, therefore, turned on the timeout bit (1) in the EIRV which, in turn, activated the processor halt signal. The timeout bit also requests processing on level zero, which, if enabled, causes a system check interruption. For a processor-detected error, the PSCF would recognize the halt signal and turn on this bit.
14
EFP enabled - Set by programming and reset by programming and
an EFP Control Reset command. When off, does not permit interrupt
presentation to the processor.
15
EFP interrupt request - Turned on by bits 4, 5, 6, 8, 9, 10, 12, or
13. When on in conjunction with bit 14, presents a level 0 interrupt
request to the processor and disables EFP pushbutton operation,
except for Enable/Disable EF Panel.
*Turns on EFP interrupt request (bit 15).
(SP212 Cont-SP233)
5-SP-11
EFP Control Register
The EFP control register permits program control of certain EFP functions and indica· tors. All bits of this 8-bit register can be set by the program, and bits 3 and 4 can also be set by EFP pushbuttons. The register is reset by either Reset EFP Control command or a system reset, and bits 3 and 4 can also be reset by EFP pushbuttons. The following table describes the bit meanings when on.
Bit
Meaning
0
Stop on storage address compare fetch - Enables a comparison
between the storage address compare register and a storage address
issued by the processor during fetch operations. This bit determines
the status of the corresponding EFP indicator.
1
Stop on storage address compare store - Enables a comparison
between the storage address compare register and a storage address
issued by the processor during store operations. This bit determines
the status of the corresponding EFP indicator.
2
Stop on system check/program exception - Enables the EFP logic for
this function and determines the status of the corresponding EFP
indicator.
3
Enable EFP entry/display - Enables operation of EFP displays,
indicators, pushbuttons, and BOP Data/Function pushbutton to
register 1 and 2 information transfer. Bit status can either be pro·
grammed or changed by the Enable/Disable EF Panel pushbutton
(with keylock, if installed, in Enable).
4
Access EFP register 2 - Enables access and display of EFP register 2
if on, and register 1 if reset, and determines register 1 and 2 indicator
status. Bit status can either be programmed or changed by the Access
Data Register 2 and Access Address Register 1 pushbuttons.
5
Processor stopped - Either an address compare stop or system check/
program exception occurred, or the Stop pushbutton was pressed.
6
Operator attention - Determines the status of the corresponding
indicator, which blinks twice each second.
7
Keyboard locked - Disables input and encoding of all but five EFP
pushbuttons. Turned on by any "Stop on -"condition, a system
check/program exception in the EFP, or a program-detected EFP
error.
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6-SP-12
Expanded Panel Registers Other Than Control and BSTAT
This section describes EFP registers other than the control and basic status registers.
Address Compare Register. This 32-bit register operates in conjunction with address compare stop logic, and specifies: · Whether a primary or secondary PSV should be active to permit a Stop on
Compare (bit 3).
· The processing level that should be active to permit a Stop on Compare (bits 5-7).
Note: If bits 3 and 5-7 are zeros, a Stop on Compare occurs on any processing level except zero for either PSV value.
· The real address that should stop processing if a compare occurs (bits 12-30 with 31 ignored).
Either a system reset or a Reset Device command resets this register.
Register 1. A 32-bit register used for operations that can be performed either from the panel or by programming. EFP control register 4 being reset and 3 being set permits access to this register. Manual register output places the first character in the units position, which shifts to the left when entering another character. Either a system reset, Reset Device command, or the Clear Panel pushbutton resets this register.
Register 2. Functions identically to register 1, except that E FP control register bit 4 being set permits access to register 2.
Current Level Register. A read-only 4-bit register whose value results from processor logic, and cannot be programmed. It specifies the current processing level of the PSV being used, and displays this value (1-7 and not 0) in the Current or Last Level Display.
Last Level Register. Functions identically to the current level register, but retains the last processing level executed. Display of this level occurs in the Current or Last Level display by holding in the Display Last Level pushbutton.
Program Mode Register. Contains a read-only binary value that results from processor logic and cannot be programmed. The value reflects the current processing execution mode, encodes to activate one of the four Mode indicators, and cannot indicate the last processing execution mode.
Address Mode Register. A one-bit read-only register whose value results from pro· cessor logic and cannot be programmed. The value indicates whether the processor is currently performing real or logical addressing for the indicated PSV and current pro· cessing level, and determines the status of the DAT Active indicator. It does not indi· cate the last processing execution mode.
SP240 Test Messages and Descriptions
This section describes those messages generated when running the EFP tests, which can only be run offline.
SP241 describes the messages generated while running all routines except those requiring manual intervention. SP242 describes messages used for the manual intervention routines.
SP241
EFP Offline Test Messages The messages listed below are in the RREN format, where RR indicates the routine number and EN the error number. See section SP231 for an explanation of the three error formats used.
RREN
Format
Meaning
0101
0104
2
0120
3
0121
3
0122
3
0123
3
0124
3
0125
3
0201
0204
2
0220
3
0221
3
0222
3
0301
1
0304
2
0305
3
0320
3
0401
1
0404
2
0420
3
0501
1
0504
2
0520
3
0521
3
0701
0704
2
0720
3
Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Basic status not zero after adapter reset. Register 1 low not zero after adapter reset. Register 1 high not zero after adapter reset. Register 2 low not zero after adapter reset. Register 2 high not zero after adapter reset. Control register not zero after adapter reset. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Status bits write/read do not compare. Extra bits reset in basic status register. Status bits not reset by Reset Status command. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Expected 1/0 interrupt did not occur. Basic status not hex 0001 after interrupt. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Control register write/read do not compare. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Register 2 high write/read do not compare. Register 2 high not zero after adapter reset. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Register 2 low write/read do not compare.
SY27-2521-3
RREN
0721 0801 0804 0820 0821 0901 0904 0920 0921 1001 1004 1005 1020 1101 1104 1120 1121 1201 1204 1220 1221 1222 1301 1304 1320
1321 1401 1404 1420 1421 1422 1501 1504 1520
1601 1604 1620
Format
3
2 3 3 1 2 3 3
2 3 3
2 3 3 1 2 3 3 3
2 3
3 1 2 3 3 3
2 3
1 2 3
Meaning
Register 2 low not zero after adapter reset. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Register 1 low write/read do not compare. Register 1 low not zero after adapter reset. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Register 1 high write/read do not compare. Register 1 high not zero after adapter reset. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Expected 1/0 interrupt did not occur. Basic status incorrect after interrupt. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. No address compare interrupt. Basic status incorrect after interrupt. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. No address compare interrupt at address hex 5554. Basic status incorrect after interrupt. No address compare interrupt at address hex AAAA. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Received an address compare when none shou Id have occurred. Extended status incorrect. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Received an address compare on incorrect level. Did not receive an address compare. Extended status incorrect. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Either no address compare occurred or it occurred late in the MVHS instruction. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Received an address compare on the target of an unsuccessfu I branch.
(SP233 Cont-SP241)
5-SP-13
RREN 1701 1704 1720
1721
1801 1804 1820 1821
1901 1904 1920 1921 2001 2004 2101 2104 2121 2123 2125 2127 2129 2131 2133 2135
2137
2139
2201 2204 2221
2222 2223
2224
Format 1 2 3
3
2 3 3
2 3 3 1 2 1 2 3 3 3 3 3 3 3 3
3
3
2 2
3 3
3
Meaning
Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Did not receive an address compare before taking program exception. Did not receive an address compare on second half of MVHS just before a Kl swap. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Panel operation did not stop on system check. Panel operation did not stop on program exception. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Invalid command did not cause a system check. Basic status incorrect after invalid command. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Basic status incorrect after pressing Store. Basic status incorrect after pressing Display. Basic status incorrect after pressing Function. Basic status incorrect after pressing lnsn Step. Basic status incorrect after pressing Start. Basic Status incorrect after pressing Stop. Basic status incorrect after pressing Reset/Restore. Basic status incorrect after pressing Storage Address Compare Stop Fetch. Basic status incorrect after pressing Storage Address Compare Stop Store. Basic status incorrect after pressing Stop on System Check/Program Excpn. Unexpected machine check occurred. Unexpected 1/0 interrupt occurred. Basic status incorrect after pressing Storage Location. Basic status incorrect after pressing Register. Basic status incorrect after pressing Translatn Table Entry. Basic status incorrect after pressing Address Control.
SY27-2521-3
RREN
2225 2236 2237
2238
2301 2304 2401 2404 2421 2424
2425 2426 2427
2501 2504 2601 2604 2701 2704 2801 2804 2901 2904 2922 3001 3004 3020 3023 3025 3027 3101 3104
Format 3 3 3
3
1 2
2 3 3
3 3 3
2
2 1 2
2
2 3
2 3 3 3 3
2
5-SP-14
Meaning
Basic status incorrect after pressing lnsn Address. Basic status incorrect after pressing Program Status. Basic status incorrect after pressing Compare Stop Address. Basic status incorrect after pressing Transform Address. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Basic status incorrect after pressing Start. Modifier bit in basic status not reset by pressing Clear Panel. Reg 1 not zero after pressing Clear Panel. Reg 2 not zero after pressing Clear Panel. Control register incorrect after pressing Clear Panel. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. DAT Active indicator did not turn on. Unexpected system check occurred. Unexpected 1/0 interrupt occurred. Supervisor mode indicator not on. Master mode indicator did not turn on, then off. 1/0 mode indicator did not turn on, then off. Appl mode indicator did not turn on, then off. Unexpected system check occurred. Unexpected 1/0 interrupt occurred.
SP242 Manual Intervention Test Messages and Procedures
The following table describes the actions required for the test messages that display when performing the EFP manual intervention routines. In the PAMI column, PA= the EFP physical address and Ml= the manual intervention number.
PAMI
OA01 OA02 OA03 OA04 OA05 OA06 OA07 OA08 OA09 OA10 OA11 OA12 OA13 OA14 OA15 OA16 OA17 OA18 OA19 OA20 OA21 OA22 OA23 OA24 OA25 OA26 OA27 OA28 OA29 OA30 OA31 OA32 OA33 OA34 OA35
Procedure
If Operator Attention indicator blinks, enter B. Press Store. Press Display. Press Function. Press Insn Step. Press Start. Press Stop. Press Reset/Restore. Press Storage Address Compare Stop Fetch. Press Storage Address Compare Stop Store. Press Stop On System Check/Program Excpn. Press Storage Location and then press Start. Press Register and then press Start. Press Translatn Table Entry and then press Start. Press Address Control and then press Start. Press lnsn Address and then press Start. Press Program Status and then press Start. Press Compare Stop and then press Start. Press Transform Address and then press Start. Reg 1 indicator= on and display= 00000000. Enter B if correct. Reg 2 indicator= on and display = 00000000. Enter B if correct. Reg 1 indicator= on and display = 11111111. Enter B if correct. Reg 2 indicator= on and display= 11111111. Enter B if correct. Reg 1 indicator= on and display = 22222222. Enter B if correct. Reg 2 indicator= on and display= 22222222. Enter B if correct. Reg 1 indicator = on and display = 33333333. Enter B if correct. Reg 2 indicator= on and display= 33333333. Enter B if correct. Reg 1 indicator= on and display = 44444444. Enter B if correct. Reg 2 indicator= on and display = 44444444. Enter B if correct. Reg 1 indicator = on and display = 55555555. Enter B if correct. Reg 2 indicator = on and display = 55555555. Enter B if correct. Reg 1 indicator = on and display = 66666666. Enter B if correct. Reg 2 indicator= on and display= 66666666. Enter B if correct. Reg 1 indicator= on and display= 77777777. Enter B if correct. Reg 2 indicator = on and display = 77777777. Enter B if correct.
SY27-2521-3
PAMI OA36 OA37 OA38 OA39 OA40
OA41 OA42 OA43 OA44 OA45 OA46 OA47 OA48 OA49 OA50 OA51 OA52 OA53 OA54 OA55
OA56
OA57
OA58
OA59
OA60 OA61 OA62 OA63 OA64 OA65 OA66
Procedure
Reg 1 indicator= on and display = 88888888. Enter B if correct. Reg 2 indicator= on and display= 88888888. Enter B if correct. Reg 1 indicator= on and display= 99999999. Enter B if correct. Reg 2 indicator= on and display= 99999999. Enter B if correct. Reg 1 indicator= on and display= AAAAAAAA. Enter B if correct. Reg 2 indicator= on and display = AAAAAAAA. Enter B if correct. Reg 1 indicator= on and display= BBBBBBBB. Enter B if correct. Reg 2 indicator= on and display= BBBBBBBB. Enter B if correct. Reg 1 indicator= on and display= CCCCCCCC. Enter B if correct. Reg 2 indicator = on and display= CCCCCCCC. Enter B if correct. Reg 1 indicator= on and display= DDDDDDDD. Enter B if correct. Reg 2 indicator= on and display= DDDDDDDD. Enter B if correct. Reg 1 indicator= on and display= EEEEEEEE. Enter B if correct. Reg 2 indicator= on and display= EEEEEEEE. Enter B if correct. Reg 1 indicator= on and display= FFFFFFFF. Enter B if correct. Reg 2 indicator= on and display= FFFFFFFF. Enter B if correct. Press Enable/Disable EF Panel and then press Start. If Operator Attention indicator blinks, enter B. Press Clear Panel and then enter B. Press Access Address Register1 pushbutton. The Reg 1 indicator should turn on and the display should be 11111111. Enter B if true. Press Access Data Register 2. The Reg 2 indicator should turn on and the display should be 22222222. Enter B if true. Exercise the hex keypad. Keys pressed should be displayed in the data display, entering from the right and moving to the left as keys are pressed. Press Access Address Register 1 and Access Data Register 2 to verify that register 1 and 2 both operate from the keypad. Press Stop to end test. Keypad, register 1, and register 2 functioned correctly. Enter B if true. Keypad does not work and Keyboard Locked indicator= on. Enter B if true. Enter B if the Storage Address Compare Stop Fetch indicator= on. Enter B if the Storage Address Compare Stop Store indicator= on. Enter B if the Stop on System Check/Program Excpn indicator= on. Enter B if the Processor Stopped indicator= on. Enter B if the Panel Check indicator= on. Press Clear Panel. The Panel Check indicator= off. Enter B if true. Press Start. This should turn the DAT Active indicator on. If on, press Start. If off, press Stop.
{SP241 Cont-SP242)
5-SP-15
SY27-2521-3
5-SP-16
PAMI OA67 OA68
OA69
OA70
OA71
OA72 OA74
Procedure
Supervisor mode indicator= on. Enter B if on. Press Start. This should cause the Master mode indicator to turn on, then off. If correct, press Start. If incorrect, press Stop. Press Start. This should cause the 1/0 mode indicator to turn on, then off. If correct, press Start. If incorrect, press Stop. Press Start. This should cause the Appl mode indicator to turn on, then off. If correct, press Start. If incorrect, press Stop. The level indicator steps slowly and the expected level and mode are displayed. Enter B. Test ran correctly. Enter B if true. Enter 1 for short test. Enter 0 for long test. Used in Routine 23.
SP250 Action Plans
Action plans for correcting EFP failures are divided into three categories: · Visually detected failures · Adapter logic failures · Panel failures
The test and manual intervention routines might refer you to one of the action plans in th is section for problem isolation and recovery.
EFP Initial Action Plan Procedure
The first procedure used for E FP fau It isolation is to reseat the cards and connections. Before performing any of the individual action plans, you should reseat the following: 1. Adapter card 2. Adapter top card cables 3. EFP keypad connectors 4. Hex display card connectors 5. Mode and state indicator card connectors 6. Cable in position B2A3 on the BOP adapter card, 01B-A1 A2
Refer to SP111 for EFP card and cable layouts, and BU 111 for the BOP card and cable layouts. After performing the above procedure, again run the adapter tests and manual intervention routines. Return to this section if a problem still exists.
Action Plan Summary
The following table should be used according to the failure indication. Find the failure in the Action Plan column, then go to the specified section to perform the action plan.
Action Plan Visually detected failure Adapter logic failure Panel failure Keypad failure Hex display card failure Mode and state indicator card failure Cable Check
Section SP251* SP252 SP253
SP254
* Use the action plan in SP251 only for fault isolation without MAP interaction.
When the MAP refers you to SP250, first perform the Initial Action Plan Procedure described above. If the problem still exists, go to either SP252, SP253, or SP254, according to the failure indication.
SP251 Visually-Detected Failure Action Plans
Use the following action plans only for any failure that can be detected visually:
Probable Cause Pushbutton or LEDs
Action
Observe condition of pushbuttons and hex displays. Any obvious loose or broken pushbuttons, or faulty LEDs indicate that the affected panel component should be replaced.
Indicators
Press Lamp Test on the BOP. If any indicators fail to turn on, replace the affected panel component.
Unknown
A visual panel failure can also be caused by other failures. The MAP and test program help to further isolate the problem.
SP252 Adapter Failure Action Plans The following action plans isolate EFP adapter failures to either voltage, card, board, bus, or card-to-panel signal path problems. These action plans assume that both bring up tests and the system control facility (SC) MAP ran successfully. After performing this action plan, select the EFP test to verify any repair.
Probable Cause Voltage
Card
Bus Card-to-Panel Board Unknown
Action
Check all de voltages at the EFP adapter card socket. 003 = +4.5 to +5.5V 811 = +7.7 to +9.3V 806 = -4.5 to -5.5V
Comment
If no voltage, or if voltage is out of tolerance, go to the PA MAP.
Change the adapter card, if not already done, and return to the MAP.
For models A31-34, card is in board location A1M2. For other A models, card is in A1P2. For B models, card is in A1S2.
Change the SC1 card. Return to the MAP.
Card location 01A·A1A2 for A models. Card location 01A-A102 for 8 models.
Go to the cable check action plan SP254 Check board wiring.
Request aid.
For net listings, go to SP410.
SY27-2521-3
SP253 Panel Failure Action Plans
The panel failure action plans are grouped according to the three field replaceable panel units: EFP keyboard card, hexadecimal display card, and mode and state indicator card.
Use the description of the failing routine (SP212) to help select the proper action plan.
Keypad Failure Action Plan
Use the following action plan for failures relating to the EFP keypad:
Probable Cause Card
Card-to-Panel Shorted or Stuck Keys
Open Switches
Action
Replace the EFP adapter card. Return to MAP.
If the problem has not been solved, go to the cable check action plan.
Use this action plan for manual intervention numbers OA02-0A 19, OA52, OA54, OA55, OA56, OA71, OA72, OA73
Check for shorted, open, or binding pushbuttons according to the following list of J6 connector pins.
Meter the J6 connector pins on the EFP keypad and press the corresponding keypad keys as follows:
Comment For models A31-34, card is in board location A1M2. For other A models, card is in A1P2. For 8 models, card is in A1S2.
See SP254.
See SP430 for pin and connector locations.
If any switches are shorted or open, replace the EFP keypad and skip the next action plan. (See SP520)
J6-12 to J6-3 Clear Panel
J6-12 to J6-4 Transform Address
J6-12 to J6-5 Storage Address Compare Stop Fetch
J6-12 to J6-6 Storage Address Compare Stop Store
J6-12 to J6-7 Stop on System Check/ Program Excpn
J6-11 to J6-3 Store
(SP242 Cont-SP253)
5-SP-17
Probable Cause Board
Action
J6-11 to J6-4 Storage Location J6-11 to J6-5 Address Control J6-11 to J6-6 Compare Stop Address
J6-11 to J6-7 Display Last Level J6-10 to J6-3 Display J6-10 to J6-4 Register J6-10 to J6-5 lnsn Address J6-10 to J6-7 Access Address Reg 1
J6-9 to J6-3 Function J6-9 to J6-4 Translatn Table Entry J6-9 to J6-5 Program Status J6-9 to J6-7 Access Data Reg 2
J6-8 to J6-3 Enable/Disable EF Panel J6-8 to J6-4 lnsn Step J6-8to J6-5 Start J6-8 to J6-6 Stop J6-8to J6-7 Reset/A estore
After replacing the keypad, be sure that the face plate is aligned and all pushbuttons do not bind on the face plate before tightening the panel screws.
Check board wiring.
Comment
See SP520 for instructions on replacing the EFP keypad. For net listing, see SP410.
SY27-2521-3
5-SP-18
Probable Cause BOP Card BOP Card-to-Panel Board
Action
Replace the BOP adapter card if not already done and return to MAP.
If the problem still exists, go to the cable check action plan.
Check board wiring.
Request aid.
Comment Position 01B-A1 A2 See SP254. For net listing, see SP410.
Hex Display Card Failure Action Plan Use the following action plan for failures relating to the hexadecimal display card that result from Ml prompt messages OA01, OA20-0A51, OA53-0A55, OA59, OA64-0A66, OA71, OA73, and OA74.
Probable Cause Card
Action Replace the EFP adapter card if not already done and return to MAP.
Check board wiring.
Comment
Card location on models A31-34: A1M2. Other A models: A1P2. B models: A1S2.
For net listing, see SP410.
Card-to-Panel
Go to cable check action plan.
See SP254.
Hex Display
Replace hex display card.
See SP530 for instructions on replacing the hex display card.
BOP Card-to-Panel
Check cabling from the BOP adapter.
Board
Check board wiring.
Unknown
Request aid.
Mode and State Indicator Card Failure Action Plan Use the following action plan for failures relating to the mode and state indicator card that result from Ml prompt messages OA59-0A63 and OA67-0A70.
Probable Cause Card
Action
Replace the EFP adapter card if not already done and return to MAP.
Comment
Card location on models A31-34: A1M2. Other A models: A1P2. B models: A1S2.
Card-to-Panel
Mode and State Indicator Card
Voltage at Mode and Indicator Card Unknown
If the problem still exists, go to the cable check action plan.
If problem still exists, replace the mode and indicator card on the EFP.
Check voltage to mode and indicator card.
See SP254.
See SP540 for instructions on replacing the mode and state indicator card.
Request aid.
SP254 Cable Check Action Plan
Probable Cause Card-to-Panel Cables
Action
Check to be sure the connections between the appropriate top card connector and the EFP component or power section affected are good.
Comment
Figures SP254-2, -3, -4, and ·5 illustrate the connection!. between top card connectors W, X, Y, and Z respectively, and the EFP components. Figure SP254-1 shows the power connections for the hex display card and mode and state indicator card.
EFP Hexadecimal Display Card
01 F-A1A3 Cable
Line Name
J2 P2
TB1
Ground~
Ground
7
+ 5 Volts 3
+ 5 Volts- 3
Power Section
~~~:~r D EFP Mode
and State
J1
the Op
Panel
0 - - 0 P1
T81
+5 volts
Power Sectlon
·
Figure SP254-1. Hex Display Card-to-Power Connections
EFP Adapter Card
w
02
01A-A1 M2, 01A-A1 P2,
03
or 01A-A1S2
04
(See SP111)
05 06
07 08
09 10 11 12 13
22
- Stop
23
- Stop on Store TP Bk
24
- Stop on Store TP Bk
25
- Stop on Fetch TP Bk
26
- Stop on Fetch TP Bk
27
- Stop on System
28
Ck/Pgm Exception TP B
- Stop on System
29
Ck/Pgm Exception TP B
+ Control Bit 5
30
+ Control Bit 5
31
Spare
32
33
w
D03 D04
D05 006
007 DOS
009 D10 011 012 013
802 803 804 805 B06 807 BOB
B09
810
01F-A1A1 Cable Line Name
- Interlock - PM3 Ind - Stop On MCPC - PM02 Ind - Stop On Store - PM01 Ind - Stop On Fetch - PMO Ind - Processor Stop Ind - KBD Lock Ind - Access Reg 2 Ind - Access Reg 1 Ind - Panel Chk Ind - Operator Atten
Interlock
P5
J5
01
05
05
04
04
07
07
06
06
03
03
08
08
09
09
10
10
11
11
16
16
EFP Mode and State Indicator Card
1/0 Ind Stop On System Ck/Pgm Exception Supervisor Storage Address Compare Stop Stor. Appl Storage Address Compare Stop Fetch Master Processor Stopped Keyboard Locked Spare Spare Spare Spare Spare Interlock
11 3
D}J3 Connector on the Hexadecimal Display Card
Figure SP254-2. EFP Adapter Card-to-EFP Mode and State Indicator Card Wiring
SY27-2521-3
(SP253 Cont-SP254)
5-SP-19
EFP Adapter Card
x
01A-A1M2, 01A-A1P2, 02
or 01 A-A1S2
03
(See SP111)
04
05
06
07
08
09
10
11
- Adap Sel TP Bk
12
- Adap Sel TP Bk
13
01 F-A1A2
x . . . - - - - - - Cable Line Name
,-----,
002
- Sense 0
D03
- Sense 1
004
Sense 2
D05
- Sense 3
D06
- Sense 4
007
- Strobe 0
008
- Strobe 1
009
- Strobe 2
010
- Strobe 3
011
- Strobe 4
012
D13
- SDC Bus Sync TP - SDC Bus Sync TP - Sync Reset TP - Sync Reset TP - Sys Reset TP - Sys Reset TP - Chip lnh TP Bk - Chip Sel TP Bk - Clear Pn TP - Clear Pn TP -VTLMS Clk TP - VTLMS Clk TP
22
802
23
803
24
804
25
805
26
806
27
807
28
808
29
809
30
810
31
811
32
812
33
-813
Figure SP254-3. EFP Adapter Card-to-EFP Keypad Wiring
PS
J6
r------1
3
3
4
4
5
5
6
6
7
7
12
12
11
11
10
10
9
9
. . .8_ _
8
EFP Keypad
-;-i EFP Adapter Card y
02
01A-A1M2, 01A-A1P2, 03
or 01A-A1S2
04
(See SP111)
05
005
06
006
07
D07
08
DOB
09
D09
10
D10
11
D11
12
D12
13
013
Spare
01F-A1A3 Cable Line Name
- Interlock - Hex Drive 3 - Hex Drive 2 - Hex Drive 1 - Hex Drive 0
+ Blanked
- Enable Hex Digit 0 - Enable Hex Digit 1 - Enable Hex Digit 2 - Enable Hex Digit 3 - Enable Hex Digit 4 - Enable Hex Digit 5
- Enable Hex Digit 6 - Enable Hex Digit 7
+ Level 2 + Level 1 + Level 3
+Tie Up i- Blanked -Tie Down - VIR/Rel Ind - PIR/Sec Ind
Interlock
Figure SP254-4. EFP Adapter Card-to-EFP Hex Display Card Wiring
~ EFP Hex Display Card
P2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
17
17
18
18
16
16
19
19
20
20
21
21
23
23
Primary (Seedy) PSV Ind
22
22
DAT Active Ind
SY27-2521-3
I I EFP Adapter Card
01A-A1 M2, 01A-A1 P2,
or 01A-A1S2 (See SP111)
z
z
02
D02
- Lvl Chg TP - Lvl Chg TP
03
D03
04
004
05
D05
06
006
07
D07
Spare
08
DOS
09
D09
10
D10
Spare
11
011
12
D12
13
D13
Lvl Chg Out TP Lvl Chg Out TP C83 EFP Enable C83 EFP Enable
22
B02
23
B03
24
B04
25
B05
26
806
27
807
28
808
29
809
0 Filter TP 0 Filter TP
30
810
31
811
32
812
33
813
5-SP-20
Cable Line Name
Interlock
- Keylock 1 - Keylock 2 - Lamp Test - Strobe 0 - Strobe 1 - Strobe 3 - Strobe 4
11
A3
D02 D03 D04 005 006 007 DOS D09 D10 011 012 D13
BOP Adapter Card
01 B-A1A2
A3
X02 t-X03 X04 X05 X06 X07
xos
X09 X10 X11 X12 X13
- Sense 0
B02
- Sense 1
803
- Sense 2
804
- Sense 3
805
806
807
BOS
-C83EFP-- 809
Enable
810
811
- Strobe 2
812
- Interlock
813
X22 X23 X24 X25 X26 X27 X28 X29
X30 X31 X32 X33 t--
Figure SP254-5. EFP Adapter Card-to-BOP Adapter Card Wiring
SP300 Intermittent Failure Repair Strategy
Intermittent failures can possibly never be detected, or might indicate different test error messages while running the test. Intermittent failures make the MAPs ineffective. To resolve this type of problem, you should record all information relating to the problem, such as the failing operation, visual symptoms, test error messages, and any other pertinent information. Refer to section SP350 for fault isolation of intermittent failures.
SP310 Adapter-Unique Intermittent Repair Strategy
For intermittent failures that could possibly be caused by the EFP, obtain the system error log and use this information to determine if there might be an EFP problem. Refer to Chapter 2 for information on obtaining the error log. Use these results to develop your own action plan.
SP350 Action Plan to Correct Intermittent Failures
Perform the following action plan, in order, from top to bottom. Any time you perform a repair action, action, you must run the expanded function panel tests to verify the repair.
Probable Cause Unknown
Action
Make sure that the bringup and System Control Facility tests have run correctly.
Comments
Voltage
Check all de voltages at EFP adapter card socket. 003 = +4.5 to +5.5V 811 = +7.7 to +9.3V
806 = -4.5 to -5.5V
If missing or out of tolerance, go to PA MAP.
Adapter card defective
Change card.
Board or bus
1. Change PSCF card and BOP adapter card.
2. Check board wiring. See section SP410.
Adapter to panel signal path
Go to the panel failure action plan, SP250.
Failure still unknown
Request aid.
SY27-2521-3
(SP254 Cont-SP350)
5-SP-21
SY27-2521-3 This page intentionally left blank.
5-SP-22
SP400 Signal Paths and Detailed Operational Description
This section contains information that is not usually necessary for fault isolation but assists in understanding EFP hardware operation.
SP410 Point-to-Point Signal Path
Figure SP410-1 lists the signal lines by name from the processor to the EFP for most A models. Use the chart below for other models.
Note: The "xx" designation is used for the storage card positions. See Chapter 3 for
locations.
Card locations on 01A-A1 board for various 8140 models:
Model Nos.
A51-54 A31-34 Other A Models B Models
Processor
PSCF STOR FLT PT EFP
(I)
0a:
0
0a:
Cl>
"O u 0
Cl>
Q
(/)
a0 :
(I)
.0....... -=
oCS
:0:::
... .0...
(I)
C)
aQ:)
uc: "ai..:
Q)
"O u 0
Q)
Q....... (I)
-=
g...
(I)
C)
aC:l>
i
...
"O
~
8.c.o.,
0
Ii)
No EFP Feature Available
xx C2 02 E2 G2 H2 J2 K2 A2 xx C2 02 E2 G2 H2 J2 K2 A2 xx f 2 G2 H2 K2 L2 M2 N2 02
M2 M2 P2 02 S2
Net
Wait St Gate PMO System Reset EFP Int Req SOC BusO SOC Bus 1 SOC Bus 2 SOC Bus 3 SOC Bus4 SOC Bus 5 SOC Bus6 SOC Bus 7 SOC Bus 8 SOC Selected SOC Sync SOC Halt l/OOp 1 MHz Osc 500ms 1024 ms
Processor Processor PSCF
Flt Pt
EFP
Conn
BOPA
C2002-E2M10--A2G07------- P2002
J2M07--H2G04--A2P05 --M2G04--- P2009
K2807--D2B08 --A2U04 - - M2B07--- P2G08 - C1A 11 --A2B06
A2S07 - - - - - - - P2004 A2U09------- P2U09 -A1E13 --A2012
A2S09 - - - - - - - P2S09 - B1A13 - - A2011
A2S05
P2U10 - 81813 --A2010
A2U07
P2B02 -B1C13 --A2009
A2S08
P2803 -B1D13 - A2008
A2S10
P2804 - B1E13 --A2007
A2U06
P2B05 -C1A13 --A2006
A2U05
P2B07 -C1B13 -A2005
A2S12
P2B08 --C1C13 -A2004
A2P07
P2S12 -F1C13 -A2U05
A2U13
P2M05-B1C11 --A2B09
A2M08
P2S04 - E1E11 -A2S08
A2S03
P2006 -B1A11 --A2B11
A2M05
P2M12 -B1B11 --A2B10
A2M12,P13
P2U07 -A1E11 --A2B12
A2M13,S02
P2S07 -A1011 --A2813
Figure SP410-1. EFP Point-to-Point Signal Path
Net
Sys Ck Not 0 Pie Bit 0 PM 1
RIV
ROS Stor Ctrl 1 T2 I Fetch Exit Long lnsn PSV Switch Stk Adr Bus 9 Stk Adr Bus 11 Stk Adr Bus 12 Stk Adr Bus 13 PSV 2 Stor Adr Bus 0 Stor Adr Bus 1 Stor Adr Bus 2 Stor Adr Bus 3 Stor Adr Bus 4 Stor Adr Bus 5 Stor Adr Bus 6 Stor Adr Bus 7 Stor Adr Bus 8 Stor Adr Bus 9 Stor Adr Bus 10 Stor Adr Bus 11 Stor Adr Bus 12 Stor Adr Bus 13 Stor Adr Bus 14 Stor Write Hi Stor Write Lo Stor Sel 0 Stor Sel 1 StorSel 2 Stor Sel 3 Stor Sel 4 Stor Sel 5 StorSel 6 Stor Sel 7
Processor Processor Processor Storage
Flt Pt
EFP
Conn
o~m
mm -F1B13
J2B08--- 02012---------------- P2D12
K2D07 - - J2P02-- H2D07
P2D07
K2B10
P2B10
K2011 --J2013-- C2D13
P2013
E2M05 - - D2P11-- C2P11
P2J06
02G07
M2G08-- P2G07
H2011 - - E2P09-- 02011
P2005
H2M09- D2P04
P2G09
E2S09
P2010
J2P13 --G2G13- E2G13
P2M12
J2M10 - - G2M10- E2U13--------M~10
P2P11
J2P04 - - G2P04-- E2U07
M2G02
P2P05
J2M09 --G2M09- E2S03
M2G05--- P2P07
K2J06 --J2S12-- E2S12
M2J06
P2U02
K2P13 - - XXU13/S12
P2P13
K2P12 - - XXU12
P2P12
K2M08-- XXS07
P2M08
K2P06 - - XXU05
P2P06
K2M03-- XXS03
P2M03
K2M04-- XXS04
P2M04
K2M10-.- XXS09
P2M10
K2P09 - - XXU09
P2P09
K2P10 - - XXU10
P2P10
K2M09-- XXS08
P2M09
K2M13-- XXS10
P2M13
K2M07-- XXS05
P2M07
K2P04 - - XXU04
P2P04
K2P02 - - XXU02
P2P02
K2M09-- XXS02
P2M02
K2S02 - - XXB13
P2S02
K2S03 - - XXD13 K~09 - - XXU11
P2S03 P2J09
K~11 - - XXU11
P2J11
K2J12 - - XXU11
P2J12
K2J13 - - XXU11
P2J13
K2P05 - - XXU11
P2G12
K2P07 - - XXU11
P2G10
K2U04 - - XXU11
P2J10
K2P11 - - XXU11
P2G13
BOPA
A2U06
SY27-2521-3
(SP400-SP410)
5-SP-23
Figure SP410-2 shows the processor-PSCF-BOPA card signal path.
01A-A1 UC
Board
PSCF
K2B07
D2B08
YYU09 YYS09 YYS05 YYU07 YYSOS YYS10 YYU06 YYU05 YYS12 YYM13, S02 YYM12, P13 YYS03 YYM05 YYU13 YYU04 YYP07 YYM08
XX= M2 in models A31-34 P2 in other A models S2 in B models
YY= A2 in A models 02 in B models
EFP
XXU09 XXS09 XXU10 XXB02 XXB03 XXB04 XXB05 XXB07 XXB08 XXS07 XXU07 XXD06 XXM12 XXM05 XX GOS XXS12 XXS04
A1013 A1E13 B1A13 B1B13 B1C13 B1013 B1E13 C1A13 C1B13 C1C13 A1D11 A1 E11 B1A11 B1 B11 B1C11 C1A11 F1C13 El E11
01A-A1 Y1 003
Flat Cable
Interlock SOC Bus 0 SOC Bus 1 SOC Bus 2 SOC Bus 3 Ground SOC Bus 4 SDC Bus 5 SOC Bus 6 SOC Bus 7 1.024 ms 500 ms 1/0 Op 1 mHz OSC SOC Sync System Ast SDC Selected SDC Halt
018-81 A2
BOP 013 Control 012 Card 011 018 010 A1A2 009 DOS 007 006 005 004 B13 B12 B11 B10 B09 BOS U05 S08
Figure SP410-2. Processor-PSCF-BOPA Card Signal Path
SY27·2521·3
SP420 Card and Top Card Connector Signals Figures SP420-1 and SP420-2 show line names of the respective pins when the EFP adapter card plugs into any of the three possible board positions.
5-SP-24
Line Name - Wait State Gate + 5V - Panel Interrupt Req + Enable/Disable Panel - 1/0 Operation + Primary Mode 1
Ground
+ Primary Mode 0
- PSV Switch Gate
- PIC Bit 0 - Stop Request - Select 1M Storage
- System Check Not Zero
- Storage Select Bit 0 - Storage Select Bit 6 - Storage Select Bit 1 - Storage Select Bit 2 - Storage Select Bit 3 - Storage Adr Bus 13
- Storage Adr Bus 12 - Stack Adr Bus 12 - Storage Adr Bus 3 - Stack Adr Bus 13
- Storage Adr Bus 7 - Storage Adr Bus 8 - Stack Adr Bus 11 - Storage Adr Bus 1 - Storage Adr Bus 0 -PSV2
- 1 Megahertz Osc Clock TP Ground
- 500 Ms Rate Clock
- SDC Bus 0 - SOC Bus 2
D02 B02
003 B03
004 B04
005 BOS
DOS B06
007 B07
008 BOS
009 B09
010 B10
011 B11
012 B12
013 B13 1-- - r- - -
J02 G02
J03 G03
J04 G04
J05 GOS
JOS GOS
J07 G07
J08 GOB
J09 G09
J10 G10
J11 G11
J12 G12
1
-J-1-3--t
G13 -- -
-
P02 M02
P03 M03
P04 M04
P05 M05
P06 MOS
P07 M07
POS MOS
P09 M09
P10 M10
P11 M11
P12 M12
t----- P13 M13
t---U02 S02
U03 S03
U04 S04
U05 S05
UOS sos
U07 S07
UOB SOB
U09 S09
U10 S10
U11 S11
U12 S12
U13 S13
Line Name
- SOC Bus 3 - SOC Bus4 - SOC Bus 5 - SOC Bus6 -5V - SOC Bus 7 - SOC Bus P
- DAT Active
+ 8.5V
- Compare Equal TP - Compare Equal TP
- 5 Volts - I Fetch - System Reset/Restore - Long Instruction - Storage Select Bit 5 -8.5 Volts - Storage Select Bit 4 - Storage Select Bit 7
- Storage Adr Bus 14 - Storage Adr Bus 4 - Storage Adr Bus 5 - SOC Bus Sync - 5 Volts - Storage Adr Bus 11 - Storage Adr Bus 2 - Storage Adr Bus 9 - Storage Adr Bus 6 + 8.5 Volts - Stack Adr Bus 9 - Storage Adr Bus 10
- Storage Write Hi - Storage Write Lo -SOC Halt - 1 Megahertz Osc -5 Volts -1.024 Ms Rate Clock
- SOC Bus 1
+ 8.5 Volts - SDC Selected
Figure SP420·1. EFP Adapter Card Signal Lines (Pin Side)
Line Name
- Panel Check Indicator
- Operator Attention
- Stop On Store TP Bk
*
+ Stop On Store
- Stop On Fetch TP Bk
- Stop On Fetch TP Bk
- Stop On Sys Ck TP Bk
- Stop On Sys Ck TP Bk
+ Control Bit 5
+ Control Bit 5
Spare
Interlock (To Y02)
- SOC Bus Sync - SOC Bus Sync - Sync Reset - TP Break - System Reset - System Reset
CHIO Inhibit TP Bk CH 10 Select TO Bk - Clear PN TP Bk TP Break VTL Msec Clock 2 VTL Msec Clock 2
22
02
23
03
24
04
25 aa: 05
26 t; 06
27 28
wzz
07 08
29 0u 09
30 :: 10
31
11
32
12
33
13
22
02
23
03
24
04
25 a: 05
§ 26
06
27 w 07
28 zz 08
29 8
30 31
x
09 10 11
32
12
33
13
- Enable Hex Digit 6 - Enable Hex Digit 7 + Level 2 + Level 1 + Level 3 +Tie Up
+ Blanked -Tie Down - DAT Active Indicator - Pri/Secdy PSV Ind.
Spare Interlock
- Sense 0 4x4 BOPA 0
- Sense 1 4x4 BOPA 1
- Sense 2 4x4 BOPA 2
- Sense 3 4x4 BOPA 3
Chg Out TP Bk
*
Lvl Chg Out
-TP Bk
*
CB3 EFP Enable
- 0 FLT Test Break
+ Non Zero Level
- Strobe 2 BOPA
Interlock (To W02)
22
02
23
03
24
04
25
a:
0
05
26 t; 06
27 28
wzz
07 08
29 8 09
30 >- 10
31
11
32
12
33
13
22
02
23
03
24
04
25 a: 05
26 27 28
t
z z w
06 07 08
29 8 09
30
10
31 N
11
32
12
33
13
* These jumpers are physically in the top card connectors.
Figure SP420·2. EFP Adapter Card Signal Lines (Card Side)
Line Name
Interlock (to Z33) - Prog Mode 3 Indicator - Stop On System Check - Prog Mode 2 Indicator - Stop On Store - Prog Mode 1 Indicator - Stop On Fetch - Prog Mode 0 Indicator - Processor Stopped Ind. - Keyboard Locked Ind. - Access Register 2 Ind. - Access Register 1 Ind.
- Sense 0 5x5 Keypad - Sense 1 5x5 Keypad - Sense 2 5x5 Keypad - Sense 3 5x5 Keypad - Sense 4 5x5 Keypad - Strobe 0 BOPA - Strobe 1 BOPA - Strobe 2 BOPA - Strobe 3 BOPA - Strobe 4 BOPA
+ Control Select + Control Select
Interlock (To W33) - Hex Drive 3 - Hex Drive 2 - Hex Drive 1 - Hex Drive 0 + Blanked - Enable Hex Digit 0 - Enable Hex Digit 1 - Enable Hex Digit 2 - Enable Hex Digit 3 - Enable Hex Digit 4 - Enable Hex Digit 5
Interlock (To W33) - Level Change - Level Change - Keylock 1 From BOPA - Keylock 2 from BOPA - Lamp Test From BOPA
Spare - Strobe 0 BOPA - Strobe 1 BOPA
Spare
- Strobe 3 BOPA
- Strobe 4 BOPA
SP430 Expanded Panel FRU Component and Connector Diagrams
Figures SP430-1 through SP430-8 show the physical layout and wiring of the EFP keypad card, mode and state indicator card, and hex display card.
F1
F2
F3
F4
F5
12 11 10 9 8 7 6 5 4 3 J6 Connector
Figure SP430-1. E FP Keypad Card
SY27-2521-3
(SP410 Cont-SP430)
6-SP-25
EFP Adapter Card
x
01A-A1M2, 01A-A1P2, 02
or 01A-A1S2
03
(See SP111)
04
05
06
07
OB
09
10
11
- Adap Set TP Bk
12
- Adap Set TP Bk
13
- SOC Bus Sync TP
22
- SOC Bus Sync TP
23
- Sync Reset TP
24
- Sync Reset TP
25
- Sys Reset TP
26
- Sys Reset TP
27
-Chip lnh TP Bk
2B
- Chip Set TP Bk
29
-Clear Pn TP
30
-Clear Pn TP
31
-VTLMS Clk TP
32
- VTLMS Clk TP
33
x
....-----.
002 003 004 005 006 007 DOB 009 010 011 012 013
602 B03 B04 605 B06 807 BOB B09 610 811 B12 613
~
Cable Line Name
- Sense 0 - Sense 1
Sense 2 - Sense 3 - Sense 4 - Strobe 0
Strobe 1 - Strobe 2
Strobe 3 - Strobe 4
Figure SP430-2. EFP Adapter Card-to-EFP Keypad Wiring
01F-A1A2
P6
JG
3
4
5
6
7
7
12
12
11
11
10
10
9
9
8
8
EFP Keypad
SY27-2521-3
Keyboard Locked
5-SP-26
0
)1----------~-- Processor Stopped
Storage Address _,.....___ Compare Stop
Fetch
~~- Storage Address Compare Stop Store
cua:::i
~
0
Mri--Stopon System Check/
Program Excpn
Figure SP430-3. Mode and State Indicator Card (Front View)
Cable Line Name
- Interlock -PM3 Ind - Stop On MCPC
- PM02 Ind - Stop On Store
- PM01 Ind - Stop On Fetch
- PMO Ind - Processor Stop Ind - KBD Lock Ind - Access Reg 2 Ind - Access Reg 1 Ind
- Panel Chk Ind - Operator Atten
01F-A1A1
P5
JS
01
05
05
04
04
07
07
06
06
03
03
08
08
09
09
10
10
11
11
16
16
EFP Mode and S-t;;ate Indicator Card
1/0 Ind Stop On Systell'l Ck/Pg11T1 Exception Supervisor Storage Address Comp-ar e · Stop Stor. Appl Storage Address Comp are! Stop Fetch Master Processor Stoi-p.ecj Keyboard Loe ked Spare Spare Spare Spare Spare Interlock
Interlock
01F-A1 A3
11 3
[l]} J3 Connector on the Hexadmec:i.-nal Display Card
Figure SP430-4. EFP Adapter Card-to-EFP Mode and State Indicator Card Wiring
EFP Mode
and State
Indicator
Card
J4
8
P1
TB1 Power
[}-+5Volts--[J Section
Figure SP430-5. Mode and State Indicator Card-to-Power Connections
SY27-2 5:21-3
(SP430 Cont}
5-SP-27
SY27-2521-3
J3
Operator Attention
Panel Check
(1) Key (3)
(8)
~
-I _,
~
(3CR1)
,--
0
I
LI __
--,
I B I
)
I
__ _J
,-,
.... ~
(2CR1)
~
,, ---
_,
(DS2)
- - -(DS1)
--- -----, r--
(DS3)
---
l-_l II
-~s~
I .... ,
lL_D'sscJ_
---
(DS6)
---
--- ----
-,
(DS7)
f I
- - - (DSS)-
0
(1)
(1)
(1)
(1)
( 1)
,-
..... ~
(DS9)
(1)
Primarv (Seedy) PSV
Current or Last Level
Figure SP430-6. Hexadecimal Display Card (Front View)
Hexadecimal Display
&-SP-28
01 F-A1A3
71 EFP Adapter Card
01A-A1 M2, 01A-A1 P2, 02
or 01A-A1S2
03
(SeeSP111)
04
05
06
07
08
09
10
11
12
13
Cable
. - - - - - - Line Name - - - - - - - - - .
y
P2
.----.
- lnterlock
1
- Hex Drive 3
3
D04
- Hex Drive 2
4
D05
- Hex Drive 1
5
D06
- Hex Drive 0
6
D07
+ Blanked
7
DOS
- Enable Hex Digit 0
8
D09
- Enable Hex Digit 1
9
D10
- Enable Hex Digit 2
10
D11
- Enable Hex Digit 3
11
D12
- Enable Hex Digit 4
12
D13
- Enable Hex Digit 5
13
Spare
22
802
- Enable Hex Digit 6
14
23
803
- Enable Hex Digit 7
15
24
804
+ Level 2
17
25
805
+ Level 1
18
26
806
+ Level 3
16
27
807
+ Tie Up
28
808
+ Blanked
19
.....
20
29
809
-Tie Down
21
30
810
- VIR/ReI Ind
23
31
B 11
- PIR/Seclnd
32
22
-
33
lnterlo ck
24
'------'
J.::-- EFP Hex Display Card
I J2
3 4 5 6 7 8 9 10 11 12 13
14
15
17
18
16
19
20
21
23
Primary (Seedy) PSV Ind
22
DAT Active Ind
24
Figure SP430-7. EFP Adapter Card-to-EFP Hex Display Card Wiring
EFP Hexadecimal Display Card
J2 P2
TB1
rn Li}3 G Groruondund7m 4 +5 Volts 3 5 +5 Volts 3
Figure SP430-8. Hex Display Card-to-Power Connections
SY27-2521-3
(SP430 Cont)
5-SP-29
SY27-2521-3
SP450 Detailed Data Flow
Figure SP450-1 shows the EFP adapter card detailed data flow and Figure SP450-2 shows the EFP adapter card to BOP adapter card wiring. Refer to SP120 for a brief operational description if necessary.
5X5 (7) 4X4 (4)
-
~ 4 e
Strobe Keyboard (5)
~ e
--
Card Module Select
--- (8)
Control
I
'
--- System Direct Cntl
Bus SYNC
System Direct Cntl Bus (9) Bidirectional
I
4H J Addr Comp
~
--
-
--
H ·Cmd Decode ]
..-.....
l Parity Chk
It
H t · 21 Lvl
P/S
-- ,, ,, · 0
3
Stg Select
ilo
11
t
T
Stg Address
,, l
--
15]
,...------..,
-- Dr
~ .___
.----
Rec
~
~
.,
Processor
Lv1Pri(11) SEC
Mode Bits (3)
-- ~ --
_i_
Lvl Reg
L_J
Stg Addr Bus (19)
Sys Ck/Proc
Excptn Pl
-
w
a:
(4)
<(
~ :a:
--(15)
0
()
---
-
,, ,,
11 ~ Control Reg 0
Yo
r--4~
'
~
I If
718 Status
j_
llvlReg]
-- -i:
,...........,
I·
1 1
l l 1 P Lvl
~
L Lvl
LJ .-.
Ind
~ Stop
-- Logic
-.....
,, ' L r I
l Reg
~I 15 16Ext 19
j
~
.,, , ,,
~o Data 7 8
Reg 1 151,6 23 24 3J
,, '
'
J Mode
Bits
-~ -
Ind
·
_.ii
Yo
·~
Data
7 8
I , Reg 2
15 16 23 24
J
'
~ --
·
-=:-
Figure SP450-1. EFP Adapter Card Data Flow Diagram
5-SP-30
I I EFP Adapter Card
01A-A1 M2, 01A-A1 P2,
or 01A-A1$2
(SeeSP111)
z
z
- Lvl Chg TP - Lvl Chg TP
Spare Spare
02
D02
03
D03
04
D04
05
D05
06
D06
07
D07
OS
DOS
09
D09
10
D10
11
D11
12
D12
13
D13
Lvl Chg Out TP Lvl Chg Out TP CB3 EFP Enable CB3 EFP Enable
22
802
23
803
24
804
25
805
26
806
27
807
2S
808
29
809
0 Filter TP 0 Filter TP
30
810
31
811
32
812
33
813
Cable Line Name
Interlock
- Keylock 1 - Keylock 2 - Lamp Test - Strobe 0 - Strobe 1 - Strobe 3 - Strobe 4
11
A3
D02 D03 D04 D05 D06 D07 DOS D09 D10 D11 D12 D13
BOP Adapter Card
018-A1A2
A3
X02 t--X03 X04 X05 X06 X07
xoa
X09 X10 X11 X12 X13
- Sense 0
802
- Sense 1
803
- Sense 2
804
- Sense 3
805
BOS
807
BOS
-CB3EFP-- 809
Enable
810
811
- Strobe 2
812
- Interlock
813
X22 X23 X24 X25 X26 X27 X28 X29
X30 X31 X32 X33 1-----1
Figure SP450-2. EFP Adapter Card-to-BOP Adapter Card
SY27-2521-3
(SP450)
5-SP-31
SY27-2521-3 This page intentionally left blank.
5-SP-32
SP500 Adjustment, Removal, and Replacement Information
SP510 Adapter Card SP520 Keypad
This section describes how to adjust, remove, and install (exchange) EFP components. Refer to Figures SP500-1 through SP500-3, and if necessary, to SP111 for illustrations showing locations.
To replace any operator panel component, you must first gain access to the rear of the panel. Perform the following: 1. Remove 8140 power plug from the wall.
Caution: DC voltage is still present at the operator panel with the 8140 power switch in the Off position.
2. Open the 8140 front covers and remove the BOP/EFP bezel by sliding the two retainer clips to the rear. These are located at the bottom of the bezel. Remove the bezel by lifting it straight up.
3. Pivot the BOP/EFP assembly toward the front of the 8140 to gain access to any of the EFP field-replaceable units.
1. Turn off power to the 8140. 2. Remove card from M2, P2, or S2, depending on the model. 3. Move any card jumpers to the replacement card. 4. Replace card, power up 8140 and run EFP test for verification of correct panel
operation.
To remove the keypad: 1. Unplug cable from JG connector on keypad FR U. 2. Remove keypad retaining hardware. 3. Remove keypad.
To replace keypad, reverse keypad removal procedure.
SP530 Hexadecimal Display Card
To remove hexadecimal display card: 1. Unplug J1 and J2 connectors. 2. Remove card retaining hardware. 3. Remove card.
To replace hexadecimal display card, reverse the card removal procedure.
SP540 Mode and State Indicator Card
To remove mode and state indicator card: 1. Unplug J3, J4, and J5 connectors. 2. Remove card retaining hardware. 3. Remove card.
To replace mode and state indicator card, reverse the card removal procedure.
Figure SP500-1. BOP and EFP Access
~ Front
SY27-2521-3
(SP500-SP540)
5-SP-33
- - - - - Top Cover
- - - - - - - - - ' S c r e w , Adjusting Nut
, Figure SP500-2. BOP and EFP Fraine Mounting
SY27-2521-3
\\
'
9 Mode and State Indicator Card
EFP Hex
LI _5-SP-34
BOP Keypad
Keylock Switch
IPL Mode Switch
Figure SP500-3. BOP and EFP Component Bezel Mounting
Chapter 5. MAP Reference Information Magnetic Tape Adapter (TA)
SV27-2521-3
5·TA·i
Introduction
This part of Chapter 5 provides maintenance information to service the 8809 Magnetic Tape Attachment Feature adapter used for the IBM 8100 Information System. When used with IBM's MAP Maintenance Package, the TA MAP diagnoses tape adapter, problems and refers to this part of Chapter 5 for such information as hardware locations, possible-cause-of-failure lists, and wiring checks.
This part consists of five sections: 1. General Information (TA 100-TA133): Contains information on TA components,
addressing, operation, and repair strategy. 2. OffIine and Online Tests (TA200-TA255): Contains test information and action
plans. 3. Intermittent Failure Repair Strategy (TA300-TA353): Contains information to
repair intermittent failures. 4. Signal Paths and Detailed Operational Description (TA400-TA453): Contains
diagrams and wiring charts which show wiring and signal paths.
5. Console Messages (TA500-TA520): Contains information about the operating system console messages.
SY27-2521-3
Contents
5-TA-ii
TA100 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA 110 Components and Addressing ......................... .
TA 111 Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . TA112 Addressing .................................. . TA113 Configuration Table Entry ........................ . TA120 Basic Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . TA 121 8809 Adapter to Tape Drive Basic Operations . . . . . . . . . . . . TA130 Adapter-Unique Repair Strategy ...................... . TA131 Offline Checkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA132 DPCX Online Exerciser . . . . . . . . . . . . . . . . . . . . . . . . . . . TA133 Intermittent Failures ............................ .
5-TA-1 5-TA-1 5-TA-1 5-TA-4 5-TA-4 5-TA-5 5-TA-5 5-TA-6 5-TA-6 5-TA-6 5-TA-6
TA200 Offline and Online Tests ..........·..........·...... TA210 Offline Test Routine Descriptions ..................... .
TA211 Adapter Tests ................................ . TA212 Tape Drive Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA213 Special Requirement Tests ........................ . TA220 DPCX Online Exerciser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA221 Running the DPCX Online Tape Exerciser . . . . . . . . . . . . . . . TA222 DPCX Exerciser Invocation Examples Using the
Basic Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA230 Test Messages and Status Information . . . . . . . . . . . . . . . . . . .
TA231 Offline Tape Adapter Tests ....................... . TA232 DPCX Online Exerciser . . . . . . . . . . . . . . . . . . . . . . . . . . . TA233 Status and Sense Bytes .......................... .
Sense Byte 0 (Tape Unit Status) . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense Byte 6-Write Block or Write Tape Mark Only (Bit 0 = 1) ... . Sense Byte 6-Not Write Block or Write Tape Mark (Bit 0 = O) ... .
Sense Byte 7-Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 8 .................................... . Sens~ Byte 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Sense Byte 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Byte 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Sense Byte 15 ................................... . Adapter Status Bytes ............................... . TA240 Test Error Message Descriptions . . . . . . . . . . . . . . . . . . . . . . . TA241 Adapter Test Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA242 Tape Drive Test Messages . . . . . . . . . . . . . . . . . . . . . . . . . . TA243 Special Requirement Test Messages . . . . . . . . . . . . . . . . . . . Symptom Codes (SCs) Generated by Routine 6C . . . . . . . . . . . . .
5-TA-7 5-TA-7 5-TA-7 5-TA-8 5-TA-9 5-TA-10 5-TA-10
5-TA-10 5-TA-10 5-TA-10 5-TA-11 5-TA-12 5-TA-12 5-TA-13 5-TA-13 5-TA-13 5-TA-13 5-TA-14 5-TA-14 5-TA-14 5-TA-14 5-TA-15 5-TA-15 5-TA-16 5-TA-16 5-TA-16 5-TA-17 5-TA-17 5-TA-17 5-TA-18 5-TA-19 5-TA-19 5-TA-21 5-TA-27 5-TA-30
TA244 DPCX Online Exerciser Messages ...... : ............. . TA250 Failure Action Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TA251 SCF/Tape Adapter Failure Action Plan ................ . TA252 Tape Adapter Failure Action Plan ................... . TA253 Tape Adapter/Tape Drive Failure Action Plan ........... . TA254 Tape Drive Action Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . TA255 Card Exchange Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-TA-31 5-TA-32 5-TA-32 5-TA-32 5-TA-32 5-TA-32 5-TA-33
TA300 Intermittent Failure Repair Strategy ...·..·..·.....·.... TA310 Adapter-Unique Intermittent Repair Strategy ............. .
TA311 Looping with MAP Interaction to Determine Intermittent Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TA312 Using the System Error Log to Determine Intermittent Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TA313 Using the Free-Lance Utility to Determine Intermittent Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TA320 Error Log Information Needed for the Tape Adapter ........ . TA321 DPPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA322 DPCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TA330 Error Log Formats and Meanings Used for the Tape Adapter ... . TA331 DPPX Error Log Formats and Meanings ............... . DPPX Error Log Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Record Meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA332 DPCX Condition/Incident Log Formats and Meanings ...... . Temporary Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Permanent Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Data Display, Temporary Errors ................... . Error Data Display, Permanent Records .................. . Record Meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA333 DPPX and DPCX Common Error Log Byte Meanings ...... . Adapter Return Code (ARC) . . . . . . . . . . . . . . . . . . . . . . . . . . Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Module Request Code . . . . . . . . . . . . . . . . . . . . . . . . PIO Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA334 Tape Statistical Data (TSO) Counters ................. .
TA340 How to Use the Error Log to Determine Tape Adapter Failures .. . T A341 DPPX Error Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA342 DPCX Condition/Incident Log ..................... .
TA350 Action Plan to Correct Intermittent Failures .............. . TA351 8809 Model 1A Intermittent Failure Action Plan (Adapter in 8101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA352 8809 Model 1A Intermittent Failure Action Plan (Adapter in 8140) .................................. . TA353 8809 Model 1B Intermittent Failure Action Plan ......... .
5-TA-35 5-TA-35
5-TA-35
5-TA-35
5-TA-35 5-TA-35 5-TA-35 5-TA-35 5·TA-36 5-TA-36 5-TA-36 5-TA-36 5-TA-38 5-TA-38 5-TA-38 5-TA-38 5-TA-38 5-TA-39 5-TA-40 5-TA-40 5-TA-40 5-TA-40 5-TA-40 5-TA-41 5-TA-41 5-TA-42 5-TA-42 5-TA-42 5-TA-42
5-TA-42
5-TA-42 5-TA-42
TA400 Signal Paths and Detailed Operational Description .··....·..· TA410 Adapter Card Interconnection Logic Signals . . . . . . . . . . . . ..· TA420 Adapter Card Wiring Diagrams . . . . . . . . . . . . . . . . . . . . . . . .
TA421 8809 Model 1A Adapter Card Wiring (Adapter in 8101) .... . TA422 8809 Model 1A Adapter Card Wiring (Adapter in 8140) .... . TA423 8809 Model 1B Adapter Card Wiring ................. . TA430 Adapter Card and Top Card Connector Locations and Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA431 8809 Model 1A Adapter Card and Top Card
Connector Locations (Adapter in 8101) ................... .
5-TA-43 5-TA-46 5-TA-47 5-TA-47 5-TA-48 5-TA-49
5-TA-50
5-TA-50
Figures
SY27-2521-3
TA432 8809 Model 1A Adapter Card and Top Card Connector Locations (Adapter in 8140) ................... .
TA433 8809 Model 1B Adapter Card and Top Card Connector Locations ................................ .
TA434 8809 Adapter Card Illustrations .................... . TA440 Tape Adapter Voltage Checks . . . . . . . . . . . . . . . . . . . . . . . . . TA450 Adapter Point-to-Point Net Checklists .................. .
TA451 8809 Model 1A Point-to-Point Net Checklist (Adapter in 8101) .................................. .
TA452 8809 Model 1A Point-to-Point Net Checklist (Adapter in 8140) .................................. .
TA453 8809 Model 1B Point-to-Point Net Checklist ............ .
5-TA-51
5-TA-52 5-TA-53 5-TA-54 5-TA-56
5-TA-56
5-TA-58 5-TA-60
TA500 Console Messages ··.·.··...··.·····.··..·..·.··.·· TA510 DPPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA520 DPCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-TA-63 5-TA-63 5-TA-63
T A 111-1. T A 111-2.
TA111-3. T A 111-4.
T A 111-5. T A 111-6.
TA120-1.
TA120-2.
T A 120-3.
T A233-1. TA331-1. TA331-2. TA332-1. T A332-2. T A332-3. T A334-1. TA400-1. TA410-1. TA410-2. T A410-3. TA431-1.
8100/8809 Model 1A Tape System (Adapter in 8101) ..... . 8809 Model 1A Adapter and SCF Card and Cable
Locations (Adapter in 8101) ..................... . 8100/8809 Model 1A Tape System (Adapter in 8140) ..... . 8809 Model 1A Adapter and SCF Card Locations
(Adapter in 8140) ............................ . 8100/8809 Model 1B Tape System . . . . . . . . . . . . . . . . . . 8809 Model 1B Adapter and SCF Card and
Cable Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8809 Model 1A Tape System Basic Data Flow
(Adapter in 8101) ............................ . 8809 Model 1A Tape System Basic Data Flow
(Adapter in 8140 Model Bxx) .................... . 8809 Model 1B Tape System Basic Data Flow
(Adapter in 8809) .........................·... Status and Sense Bytes . . . . . . . . . . . . . . . . . . . . ..... . DPPX Error Log Display for Mount/Dismount Records .... . DPPX Error Log Display for Error Records (Format 1) .... . DPCX Type-2 System Check Record Display ........... . DPCX Type-4 System Condition Record Display ........ . DPCX Type-5 Variable Data Record Display ........... . 8809 Tape Statistical Data (TSO) Counters . . . . . . . . .... . Adapter Detailed Data Flow Diagram (2 Parts) .......... . Logic Signals Between Adapter Top Card Connectors ..... . Logic Signals Between Adapter Cards .........·.....·. Adapter Card Locations . . . . . . . . . . . . . . . . . . . . . . . . ·. Top Card Connector Location and Pin Numbering,
Model 1A (Adapter in 8101) ..................... .
5-TA-2
5-TA-2 5-TA-3
5·TA·3 5-TA-4
5-TA-4
5-TA·5
5-TA-5
5·TA-5 5-TA-12 5-TA36 5-TA-36 5-TA-38 5-TA-38 5-TA-38 5-TA-41 5-TA-44 5-TA-46 5-TA-46 5·TA-46
5-TA-50
5-TA-iii
Abbreviations
TA431-2.
TA432-1.
TA432-2. TA433-1.
TA433-2.
TA434-1. TA434-2. TA434-3. TA451-1.
TA452·1.
TA453-1.
Adapter Card and Cable Locations-8101 01 A-A2 Board (Card Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top Card Connector Location and Pin Numbering, Model 1A (Adapter in 8140) . . . . . . . . . . . . . . . . . . . . . .
Adapter and SCF Card Locations-8140 C2 or D2 Board .... Top Card Connector Location and Pin Numbering,
Model 18 . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . Adapter Card and Cable Locations-8809 01A-A1 Board
(Card Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA1 Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA2 Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TA3 Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model 1A Adapter Net Checklist (Adapter in 8101)
(2 Parts) . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . Model 1A Adapter Net Checklist (Adapter in 8140)
(2 Parts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model 1B Adapter Net Checklist (2 Parts) . . . . . . . . . . . . . .
5-TA-50
5-TA-51 5-TA-51
5-TA-52
5-TA-52 5-TA-53 5-TA-53 5-TA-54
5-TA-56
5-TA-58 5-TA-60
SY27-2521-3
amp ARC BAD DR BG ERR BOP BOT BSB BSF CHCV CHCVC CHCVD CHIO CIL ck
CLSAR cmd cnt cntl CNTL-L cntr conn DA det DPCX DPPX DRV/RCV DSE EADDR ELDA ELSA
Amplifier Adapter Return Code Basic Address Register Background Error Basic Operator Panel Beginning of Tape Back Space Block Back Space File Channel Control Vector Channel Control Vector Command Channel Control Vector Data Channel 1/0 Condition/Incident Log Check
Control Lines Storage Address Register Command Count Control Control Lines Counter Connector Drive address Detect Distributed Processing Control Executive Distributed Processing Programming Executive Driver/Receiver Data Security Erase Extended Address Register Error Log Data Analysis Error Log Summary and Archive
env EOD ERG ERi FCB FDM FRB FRU FSB FSF fwd GFI HW IBG IC ID 1/0 IPS LA LED
LO LV LWR MAP MCK MD MED MTE PA PEID PIO PSAR REG R/W SAR SC SCF seg SHS SLG SLI SLS SSCF SYSLERR SYSLTSD SYSTCM TACH TARC TIC TM TSO TSTCLP UT WRT WTM
Envelope End of Data Erase Gap Error Record Indicator Function Control Block Function Definition Module Function Request Block Field Replaceable Unit Forward Space Block Forward Space File Forward General Failure Index Halfword Inter Block Gap Isolation Code ldentif ication Input/Output Inches Per Second Logical Address Light-Emitting Diode
Low Level Loop Write to Read Maintenance Analysis Procedure Machine Check Maintenance Device Medium Multi-Track Error Physical Address Phase Encoded ldentification Programmed 1/0 Processor Storage Address Register Register Read/Write Storage Address Register Symptom Code System Control Facility Segment Set High Speed Set Long Gap Suppress Length Indication Set Low Speed Secondary System Control Facility System List Error Log System List Tape Statistical Data System Test Control Monitor Tachometer Translated Adapter Return Code Transfer in Channel Tape Mark Tape Statistical Data Test Control Line Parity Unit Type Write Write Tape Mark
5-TA~iv
TA100 General Information
This section contains information on hardware components, addressing, operation, and adapter-unique repair strategy.
TA 110 Components and Addressing
TA 111 Hardware Components An 8809 tape subsystem has three different configurations which are mutually exclusive. Each may have up to four tape units.
In the first configuration, the two tape adapter cards and a driver/receiver card reside in the 8101. The System Control Facility (SCF) card for the adapter can be shared with either the diskette or disk adapters or both, depending on the 8101 configuration. The first tape unit, always a Model 1A, connects to the 8101. See Figures TA111-1 and TA111-2.
In the second configuration, the two tape adapter cards and a driver/receiver card reside in the 8140 Model Bxx. The System Control Facility (SCF) card for the adapter can be shared with a display printer or communications adapter, depending on the 8140 configuration. The first tape unit, always a Model 1A, connects to the 8140. See Figures TA111-3 and TA111-4.
In the third configuration, which uses an 8809 Model 1B, the adapter cards, as well as the SCF card, reside in the first tape unit. In this configuration, the SCF is not shared, and the tape unit connects to the 8130 or 8140 Processor or the 8101 and must be physically adjacent. See Figures TA111·5 and TA111-6.
For a description of the Model 2 and 3 tape units, see Chapter 4, GR300.
SV27-2521-3
(TA100-TA111)
5-TA-1
8130/8140
8101 (01A-A2)
AB CD
> I.I..
u
..-
<(
C'I <(
a:
(I) (I)
I-
-I- (.J a: >
a:
~
0
M <(
I-
,, ~
Bus
Tag
10M (33 Feet)
1 I I
1---_J
a:
--- > (.J
.. a: >a:
0
Model 1A
1 :
1 I I
L _ _j
Model 2
Figure TA111-1. 8100/8809 Model 1A Tape System (Adapter in 8101)
l _t
I I
L
_
I
_J
Modet3
SY27-2521-3
j_
Model 2
5·TA·2
01U
01 V (Bus and Tag Connectors)
8101 Rear View
Figure TA 111-2. 8809 Model 1A Adapter and SCF Card and Cable Locations (Adapter in 8101)
8140 C2 or 02 Board
A
G HJ
<I-
N
~
-a>:
()
a:
->a:
·u.
()
0
M <(
*SSCF card in C2 board only
Cl)
I-
Cl)
h ~
Bus
Tag
'\.. \..
10M (33 Feet)
{
1
1-- - _J
---- a: > () >aa:: 0
Model 1A
t-. i-.
I I
L-.J
Model 2
Figure TA111-3. 8100/8809 Model 1A Tape System (Adapter in 8140)
1
T
_-.I
I I
L-J
Model 3
l
Model 2
Figure TA111-4. 8809 Model 1A Adapter and SCF Card Locations (Adapter in 8140)
SY27-2521-3
(TA111 Cont)
6·TA-3
8130/8140/8101
01B-A182
lo E i
LI. ..- N
I
(.) <( <(
I
CJ'J I- I- 1--J
CJ'J
~
Model 18
1 i
I
I
I
I
L
_
.
I
J I
Model 2
Figure TA111-5. 8100/8809 Model 18 Tape System
i I
I :
I
,_ _
_JI
Model 3
l
Model 2
Baseplate (Tape Deck)
Power Supply
01 A (Tape Adapter Logic)
Note: Refer to Figure SC111-13 in SC section for detailed drawing of SCF card and cabling.
8809 Front View
8809 Rear View
Figure TA111-6. 8809 Model 1B Adapter and SCF Card and Cable Locations
(SCF Logic) 01 C (l/O Panel)
SY27-2521-3
5-TA-4
TA 112 Addressing
To specify a particular tape drive for any operation, the adapter physical address (PA) and a drive address (DA) must be used.
The adapter PA consists of two hexadecimal (hex) characters. The first (P) specifies the SSCF Group address and is determined by the SSCF card address switch settings_ The second {A) specifies the tape adapter address within the SSCF group address. Refer to Chapter 2, CP200, for a discussion of addressing. The DA also consists of two hex characters and is determined by switch settings on a tape drive card.
TA 113 Configuration Table Entry This configuration table entry example aids in understanding how to specify a particular tape drive for testing. When running tests and the prompt message 'Enter PADA' displays, you must specify both a level 01 and a level 02 {adapter and drive) address. For example, 9301 selects drive address 01 that is connected to the first 8101.
The following shows a maximum tape configuration entry. Be aware that only one level 01 PA entry can exist in the configuration table
SSCF Group and Tape Adapter Addresses {PA)
LV
PA
01
5E
01
73
01
93
01
A3
01
83
01
C3
l
UTUT
0040 0040 0040 0040 0040 0040
OPOP
0000 0000 0000 0000 0000 0000
OPOP
0000 0000 0000 0000 0000 0000
Comments
8140 Model Bxx 8809 Model 1B First 8101 Second 8101 Third 8101 Fourth 8101
Tape Drive Addresses {DA)
LV
DA
02
00
02
01
02
02
02
03
02
04
02
05
02
06
02
07
UTUT
0040 0040 0040 0040 0040 0040 0040 0040
OPOP
0000 0000 0000 0000 0000 0000 0000 0000
OPOP
0000 0000 0000 0000 0000 0000 0000 0000
TA120 Basic Operational Description
The tape adapter consists of two adapter cards (TA 1 and TA2) plus one driver/receiver card (Model 1A Tape System only). The adapter controls the operation of from 1 to 4 tape drives, depending upon the customer configuration. Figures TA120-1, TA120-2, and TA120-3 show the general layout and data flow of the adapter. Refer to the TA400 section for detailed information.
B2 TA1 SSCF Control and Data
C2 TA2
02
ORV/ RCVR
Edge
Figure TA120-1. 8809 Model 1A Tape System Basic Data Flow (Adapter in 8101)
1/0 Panel 01V
01V
Bus Cable to Tape Drive
Tag Cable to Tape Drive
G2 TA1 SSCF Control and Data
Edge
1/0
H2
J2
Conn
Panel
TA2
ORV/
RCVR
Bus Cable to Tape Drive
~--....... Tag Cable to Tape Drive
Figure TA120-2. 8809 Model 1A Tape System Basic Data Flow (Adapter in 8140 Model Bxx)
02
TA1
- _.SSCF Control and Data_
-..
E2 TA2
-- -~ -
- To Tape Drive Logic
Figure TA120·3. 8809 Model 18 Tape System Basic Data Flow (Adapter in 8809)
TA 121 8809 Adapter to Tape Drive Basic Operations
Several basic types of operations use commands betwen the adapter and the attached tape drives. The following briefly describes these operations:
· Write-directs the adapter to transfer 'X' bytes of data from processor storage to the tape drive. The tape drive moves forward towards the end of tape (EQT) marker, while writing the data from processor storage to the tape.
· Read-directs the adapter to transfer 'X' bytes of data from the tape drive to processor storage. The tape drive moves tape forward towards the EQT marker, assembling the data from tape and passing it to the adapter, where it can then transfer to processor storage.
· Forward Space Block-moves tape forward towards the EQT marker to the next interblock gap (IBG). No data transfer or error detection occurs using the information contained within that block.
· Back Space Block-moves the tape backward towards the beginning of tape (BOT) marker either to the next interblock gap or to the load point, whichever comes first. No data transfer or error detection occurs using the information contained within that block.
· Forward Space File-moves tape towards the EQT marker to the interblock gap beyond the next tape mark. No data transfer or error detection occurs using the information contained within that file.
· Backspace File-moves tape towards the BOT marker either to the interblock gap beyond the next tape mark or to load point, whichever comes first. No data transfer or error detection occurs using the information contained within that file.
· Write Tape Mark-writes a tape mark (a block of significant non-data bytes separating files), and does not require processor information transfer.
· Data Security Erase-erases tape information from the present position of the tape to one meter beyond the EQT marker.
· Erase Gap-moves the tape forward towards the EQT marker, and erases approximately 8. 75 cm (3.5 inches) of information.
· Rewind-rewinds the tape, which remains loaded when the tape reaches load point.
· Rewind/Unload-rewinds the tape to load point and unloads the tape. If already at load point, the tape immediately unloads.
· Mode Set-sets the speed and the IBG length.
SY27-2521·3
(TA111 Cont-TA121)
5-TA-5
TA130 Adapter-Unique Repair Strategy
This section describes that repair strategy unique to the 8809 Magnetic Tape adapter. Refer to Chapter 4, GR500, for general 8100 Information System repair strategy.
The General Failure Index (GF I) initially determines whether the tape drive or the adapter caused a problem. Before entering the 8809/8100 maintenance package, ensure that the 8100 operates properly. Use the TA MAP contained on MD diskette 03 to determine the cause of the failure. When the MAPs instruct you to run a test and detects a failure, the
MAP then generates an Isolation Code (IC). The IC then points to a MAP to provide further direction.
TA 131 Offline Checkout
To perform the adapter offline checkout, obtain the 8100 from the customer. Use maintenance device diskette 03 and specify the offline basic checkout option selection 'A' from the TA MAP menu. Run the offline tests to isolate the problem to the adapter, the tape drive, or to the unit's Secondary System Control Facility (SSCF).
If the problem is isolated to the adapter, the TA MAP directs you to replace the FRU(s) causing the problem. If the problem is not corrected, you are referred to TA250 (Failure Action Plans) for further corrective action.
If the problem is isolated to the tape drive, the TA MAP refers you to the 8809 Tape Drive MAPs for further corrective action.
If the problem is isolated to SSCF, the TA MAP refers you to the system control facility MAP {SC) for further corrective action.
SY27-2521-3
6·TA·6
TA 132 DPCX Online Exerciser With DPCX, you can check the adapter and drive(s) online by using the DPCX Online Exerciser, which tests operations that a customer might normally execute. If a failure occurs, the program collects and analyzes the error data, and then generates a Symptom Code {SC) to identify the failing area or FRU. The SC points to a MAP which then provides further direction.
TA 133 Intermittent Failures An intermittent failure can occur so infrequently that looping the test might not detect it. You should then use the system error log. See TA330 and TA340 for detailed information on the error log.
An error can also occur at random times and generate different test error messages, which makes the MAPs ineffective. After the MAPs detect three different test error messages, you are instructed to use the action plans in TA250.
If errors occur only after looping the tests for more than 15 minutes, record the test error message and use the free-lance looping operation {TA313) and the action plans in TA250.
See TA300 for detailed information on intermittent failures.
TA200 Offline aod Online Tests
To test and repair the adapter and attached tape drive(s), IBM provides offline tests and a DPCX online exerciser.
The offline tests reside on MD diskette 03. The DPCX online exerciser is provided only for those systems using DPCX, and is part of the program.
The offline tests detect and report failures between the System Control Facility (SCF) and the tape adapter, in the adapter, between the tape adapter and the tape unit, and in the tape unit under test.
The DPCX online exerciser contains routines to isolate data transfer problems from tape motion problems, and to functionally exercise the tape unit.
TA210 Offline Test Routine Descriptions
The offline test, which consists of 48 routines on MD diskette 03, is divided into three parts: adapter routines, device routines, and special requirement tests. The maintenance device runs and controls offline test operation, which requires dedication of the entire 8100.
The adapter tests complete in 15 seconds, while the device tests take 5.5 minutes. For the run times of the special requirement tests, see the individual routine descriptions in TA213.
TA211 Adapter Tests
The 14 adapter routines test the adapter hardware, 1/0 commands, and the SCF signal bus path from the SSCF to the tape adapter. The MD invokes the adapter routines either by the MAP or by a free-lance operation. See TA241 for error descriptions.
When using the MAP, the tests are invoked automatically when required. When using the free-lance operation, the following test invocation procedure must be used:
1. At 80BC or PAOO, enter PADAB.
2. At 81 BC, enter SLR RB
Where:
PA adapter address (see TA113) DA address of the drive to be tested (see TA113)
S
sense option:
0 = run only adapter tests, routine 01-15
1 = run adapter/device tests, routines 01-56 2 = run adapter/device tests with manual intervention routines 01-56
L
loop option:
0 run selected routines one time 1 loop selected routines; stop on error 2 loop selected routines; bypass error
RR routine number. If 00 or no entry is made, all routines for sense option are run. If a routine number is entered, only that routine is run.
B
begins execution and enters the invocation message.
SV27-2521-3
Successful completion of the adapter tests (PAOO) occurs in 15 seconds. A short description of each routine follows:
Routine 01, Address Recognition Test. Determines if the adapter under test recognizes its own address by issuing an Adapter Reset command. A machine check or an 1/0 interruption should not occur.
Routine 02, Command Test. Determines if the adapter under test responds to all valid commands and causes a machine check for all invalid commands. All bit patterns from hex 00 to hex FF are issued as commands.
Routine 03, Adapter Register Test. This routine tests: (1) whether all bit combinations can be written into each adapter register, and (2) whether all adapter registers are reset by the Reset Adapter command. Except for the status register, this routine checks all registers by writing all patterns to each register. It then reads them back while comparing the values to the write mask values. Each register is reset and checked for zero.
Routine 04, Basic and Extended Status Register Set/Reset and Interrupt Test. Tests that the basic and extended status registers: (1) can be written correctly, (2) can be reset selectively, and (3) have certain bit settings that cause generation of interruptions. Five tests are performed:
1. Reset the status registers.
2. Write hex FF to the status registers and test that selective bits are reset. 3. Check extended status for setting and reading all bit combinations,
4. Check that the extended bits set the interrupt bit. 5. Check basic status for setting and reading all bit combinations.
R«;lutine 05, Timer Test. Tests the timer to ensure that an interruption: (1) occurs, (2) occurs only once, and (3) occurs within 800 to 1500 ms.
Routine 06, Counter Test. Checks that the Increment and Decrement commands cause the appropriate counters to increment or decrement correctly, and ensures that the adapter storage address counters wrap correctly. The counters are first set to a beginning value of either 1's or O's, depending on whether the counter increments or decrements. The counters are then stepped through their complete range while being checked for the correct value at each step. They are also checked to ensure that only the correct command loads each counter.
Routine 07, Buffer Test. Checks that the alternate buffers can be written and read correctly, and that the processor storage address register (PSAR) counter steps during these Read/Write Buffer commands.
Five data patterns and their complements are used to test every buffer address:
Pattern
Even Address
1
FFOO
2
DOFF
3
AA55
4
55AA
*5
0101
*Used for parity checking.
Odd Address
OOFF FFOO 55AA AA55 F7F7
(TA130-TA211)
5-TA-7
TA212 Tape Drive Tests
SY27-2521-3
The routine writes every address by using a write loop, then reads and checks them by using a read and compare loop. The routine also checks the wrapping of the processor storage address register by using a loop count of 257 for 256 addresses.
Routine 08, Wrap Test. Tests that the Wrap command: (1) increments the control line storage address register (CLSAR) and (2) wraps data through the buffer with no errors.
The routine first issues a Reset Adapter command to set the processor storage address register (PSAR) and CLSAR to zero, and writes a halfword of hex FFOO into the first buffer address. The routine then issues a Wrap command and a Read Buffer command. The first address should now contain hex FF FF, and the CLSAR should increment.
The routine completes successfully when the hex FFFF pattern ripples through all buffer positions by using the Wrap command. The routine checks every step to ensure that it completed correctly and that no parity errors occurred.
Routine 09, Function Control Block (FCB) Test. Checks the FCB fetch operation by using no-op FCB values. It executes an FCB list containing five no-op FCBs and an end-op FCB, and then checks the channel pointer register for correct ending status and value.
Routine 11, Command Transfer In Channel (TIC) Test. Checks command TIC operation by using no-op FCB values. It executes an FCB list containing a no-op, TIC, and end-op, and then checks the channel pointer register for the correct command value.
Routine 12, Program-Requested Interrupt (PRI) Test. Checks program-requested interrupt operation in FCB mode by using no-op FCB values with the PR I bit on. It executes an FCB list containing a no-op (with the PR I bit on) and an end-op, and then checks status to ensure that the PR I and interrupt bits are on.
Routine 13, Invalid Subcommand Test (FCB Mode). Checks invalid subcommand detection in FCB mode. It executes four invalid FCBs, each one of which should set interrupt and invalid subcommand status.
Routine 14, Parity Check Test. Checks the parity status bit by wrapping a bad parity byte with the Test Control Line Parity (TSTCLP) command. The command is the same as the Wrap command, except that parity is inverted, which causes a parity error.
Routine 15, Control Lines Sequence Error Test. Checks that a control line sequence error occurs when issuing a command to a nonselected tape unit. It first issues a Stop COIT)mand before selecting the drive, which should turn on the control line sequence error status bit.
The 20 tape unit routines test for correct adapter-to-tape unit information transfer, as well as correct operation of the selected tape unit, and complete in 5.5 minutes. Refer to TA211 for the test invocation procedure when using free-lance mode.
These routines also use a background error (BGERR) function, which checks for errors on operations that have been tested by a previous routine. It is used to aid in resolving intermittent errors by giving the correct error indication for failures that occurred in previously tested hardware. The BGERR error numbers are FO, F1, F2, F7, F8, and F9. See TA242 for a description of these error numbers.
5-TA-8
The DIAG section of the 8809 Maintenance Manual contains a detailed description of the tape drive tests. The following briefly describes each routine:
Routine 40, Control Line Test. Exercises the control Iines into the tape unit. It first executes an adapter reset and checks status to verify that no inbound lines to the. status register are active. It then selects a drive and checks status to verify that correct selection occurred and that the drive responded with the correct address on Bus In.
Routine 41, Select Active Test. Tests the ability of the adapter to get a control line sequence error when selecting a tape unit that was previously selected. The routine first selects the drive, which should operate correctly. It then reselects the drive, which should cause a control line sequence error because Select Active was still on.
Routine 42, Sense Byte Test. Verifies: (1) the operation of the Sense command and (2) that certain sense bytes contain the proper information after a Check Reset command.
Routine 43, Loop Write-to-Read Test. Tests the data transfer circuits by transferring data patterns, which vary in length and content, through the write and read path. This routine is the first one to check the data TIC function of the adapter.
Routine 44, Poll Test. Tests that the tape unit can both suppress response and correctly respond to a poll tag.
Routine 46, Low-Speed Test. Ensures that various functions can be performed in low speed mode.
Routine 47, Write/Read Phase Encoded Identification (PEID) Test. Writes a PEID and then performs a read back check.
Routine 48, 31.75 Centimeter/sec (12.5 ips) Write/Read Test. Writes stress data patterns that vary in length, and then performs a read back check.
Routine 49, Dual Gap Test. Checks that the Set Long Gap and Set Short Gap commands function correctly.
Routine 4A. Backward Creep Test. Ensures that a Backspace and Write command sequence does not destroy data in the record previous to the one being rewritten.
Routine 4C, High-Speed Test. Ensures that various functions can be performed in highspeed mode.
Routine 40, Repositioning Test. Ensures that the hardware repositions the tape to the proper location when the Reinstruct command occurs too late. Only the 254 centimeter/second (100 ips) tape mode uses this routine.
Routine 4E, Write Tape Mark Test. Writes a tape mark (TM) and then performs a read back check. The tape is backspaced and then spaced forward over the tape mark to determine that the TM can be written and read correctly.
Routine 4F, Basic Write/Read High-Speed Test. Writes variable-length stress data pattern records, and then performs a read-back check with the tape unit in the 254 centimeter/second (100 ips) mode of operation.
Routine 50, Incorrect Length Detection and Suppression Test. Tests that the adapter can recognize an incorrect length record by reading both long and short. It also tests the suppress length indicator bit by reading long and short. No length error should occur with the suppress length indicator bit on.
Routine 52, Erase Gap (ERG) Test. Writes several 4K byte records, rewinds the tape, and executes erase gap operations to erase the records. It then reads the records to ensure that they were erased.
Routine 53, Write High-Speed, Read Low-Speed Test. Writes stress data patterns at 254 centimeters/second (100 ips) and then reads them at 31.75 centimeters/second (12.5 ips).
Routine 54, Read High-Speed Test. Uses high-speed mode to read the tape that was written by Routine 53. Status and data compare operations are used to verify correct operation.
Routine 55, Magnetized Head Test. Writes a 2K byte record, moves the record over the head assembly 10 times, and then reads the record. This sequence is repeated twice. If the last read operation is successful, the write head is considered to be properly demagnetized.
Routine 56, Data Security Erase Test. Tests the Oita Security Erase command.
TA213 Special Requirement Tests
These 14 tests are selectable and can only be invoked in free-lance mode. You use these tests to perform skew adjustment, verify the read operation, display the sense bytes, check read/write reliability-interchange, and to complete the functional testing of the read path.
These routines use the background error (BG ERR) function. Refer to TA212 for a brief description of BGERR, and to TA211 for test invocation procedures. See TA243 for error descriptions.
The OIAG section of the 8809 Maintenance Manual contains a detailed description of the tape drive tests. The following briefly describes each routine:
Routine 5A, Read Test Pattern Tape (Part 1 ). Reads a previously written test tape to check read functions and error-checking circuits, and runs in approximately two minutes.
Routine 58, Read Test Pattern Tape (Part 2). Reads a previously written test tape and compares the expected data with the data read. It also tests the Write command on a file-protected tape, and runs in approximately 5 minutes.
Routine 60, Write Reliability-Interchange Test. Tests the write operation by writing interchange test tapes, and runs in 35 seconds.
Routine 61, Read Reliability-Interchange Test. Reads tape written by Routine 60 and runs in 50 seconds.
Routine 62, Tape Control Line Exerciser. Exercises the control lines, and runs in 10 seconds.
Routine 63, Load/Rewind/Ready Problem Analysis. Performs an analysis of load, rewind, and ready problems, and runs in 10 seconds.
Routine 64, Reinstruct Timing Test-Short Gap. Checks Reinstruct command timing in short gap mode, and runs in approximately 5 minutes when using a 2400-foot reel.
Routine 65, Reinstruct Timing Test-Long Gap. Checks Reinstruct command timing in long gap mode, and runs in approximately 5 minutes when using a 2400-foot reel.
Routine 66, Read Continuous High-Speed Test. Reads continuously in high-speed mode, and runs in approximately 5 minutes when using a 2400-foot reel.
Routine 67, Inter-Block Gap IBG Measurement Test. Ensures that correct length gaps are written, and runs in 90 seconds.
Routine GA, Skew Adjustment Exerciser. Exercises the tape while you perform mechanical skew adjustments. The routine takes 5 minutes when using a 2400-foot reel, and cannot be looped.
Routine 68, Sense Byte Display Utility. Displays sense information from the most recent test error, and runs in 10 seconds.
Routine &C, Symptom Code (SC) Generator Utility. Generates the symptom code for the most recent test error, and runs in 10 minutes.
Routine 6D, 'P' Track Only (PTO) Exerciser. Writes and reads a 4096-byte record of hex 00 by using a loop function to perform 40,000 operations. The run time is 3 1/2 hours.
Note: The tape does not move when running routine 6D.
SY27-2521-3
(TA211 Cont-TA213)
5-TA-9
SV27-2521-3
5-TA-10
TA220 DPCX Online Exerciser
The OPCX online exerciser runs under the SYSTCM utility and uses the normal invocation procedure.
Note: Only the tape unit under t:est must be dedicated.
Normal error logging, as well as any program error recovery procedures, are suppressed for the tested unit, but all other tape units operate normally.
The online exerciser uses two routines (01 and 02) that test tape-unit operations under normal conditions. These routines, described briefly below, might not determine highly intermittent problems:
Routine 01, Data Path and Tape Motion Test. Isolates data transfer problems from tape motion problems. It uses the loop write-read and erase gap functions, and runs in 15 seconds.
Routine 02, Functional Test Exerciser. Performs a functional verification of each start 1/0 operation, such as write, read, forward space block, and rewind, and runs in 70 seconds.
When detecting an error, the exerciser presents the 16 tape unit sense bytes, the two adapter status bytes, the symptom code (SC) for that error, and any other important completion and error codes from the system.
TA221 Running the DPCX Online Tape Exerciser
The SYSTCM utility must be used to invoke the DPCX online tape exerciser. This section contains information that relates only to tape-unique functions. For procedures on how to run the SYSTCM utility, refer to the Chapter 2, CP810, 'How to Log On and Run DPCX Online Tests.'
Before running the exerciser: 1. Clean the tape unit to be tested. Tape-cleaning instructions are found on OPER
60 of the 8809 Maintenance Information Manual. 2. Mount a known good scratch tape reel containing a write enable ring. 3. Load the tape drive and make it ready. (The READY indicator should be on.)
Invoke SYSTCM from either the basic operator panel or a terminal: 1. At the 80BC or PAOO message, enter 'PADAB', where PA= the tape physical address
and DA = the drive address. Refer to TA 113 for these values.
2. At the 81 BC prompt message, enter any options in the SLR RB format. Refer to TA211 for these values; for the meaning of the test messages that can be generated while running this exerciser, see TA232.
3. To continue the test after an error, enter 'B' and press either Enter Function at the BOP, or ENTER at a terminal.
4. To terminate the exerciser, enter 'F' and press either Enter Function at the BOP or ENTER at a terminal. The exerciser terminates only at either a manual intervention or error stop, or at the end of testing.
TA222 DPCX Exerciser Invocation Examples Using the Basic
Operator Panel
The following chart can be used for a quick reference for invoking the DPCX online
exerciser from the 8130/8140 operator panel:
Routine Options
Enter Data
Enter Function
Enter Enter Data Function
01 & 02 No loop
PADA B
01 & 02 No loop
PADA B
01 & 02 Loop, stop on error*
PADA B
02 only No loop
PADA B
02 only Loop, stop on error*
PADA B
02 only Loop, no stop on error** PADA B
B
B
11
B
1002 B
1102 B
1202 B
* The tests will loop for 4 minutes unless an error is detected. The tests cannot be
terminated until after the 4-minute loop or unless an error is detected.
**The tests cannot be terminated until after the 4-minute loop.
1. To terminate the utility at a terminal, enter 'D' and press ENTER. This action terminates the SYSTCM function, but the terminal is NOT logged .off. To log off, perform the appropriate terminal logoff procedure.
2. To terminate the utility at the basic operator panel, enter 'D' and press Enter Function.
If invoked from a terminal, the terminal displays the complete error data. If using the basic operator panel, additional data must be displayed by entering 'E' and pressing Enter Function. Four hexadecimal digits display each time you enter 'E' and press Enter
Function. The number of digits in a message varies according to the error format, but a
blank field always indicates the end of the message. If you continue to enter 'E' and press Enter Function, it repeats the message fields.
TA230 Test Messages and Status Information
TA231 Off/ine Tape Adapter Tests
The following messages are generated while running the offline tests:
e PAOO
successful test completion
· PASO
channel 1/0 hang condition
· PAFO
test started
· XXBC
test control monitor error
· PAXE RREN SCF, adapter, or tape drive error
The following table lists the different message formats produced by the tests:
Format Type
2 3 4 5 5 5 5
Message
PAXE RREN SSSS PAXE RREN AACC SSSS PAXE RREN SSSS TTPP BBBB XXXX XXXX (See Note ll PAXE RREN EEGG TTPP BBBB XXXX XXXX (See Note 1) XXBC PAOO PASO PAFO
Where: PA
x
x
E RREN EE GG AA
cc ssss
TT
pp
BBBB
xx xx
XXBC
tape unit or adapter address 1 then PA= adapter address
2 then PA = tape unit address E which indicates an error
Isolation Code, where:
RR = Routine number EN = Error number
Expected data byte Actual data byte
Adapter address Adapter command Adapter status (See Note 2), where:
Bit 0 = Nonrecoverable error 1 = Invalid subcommand 2 = Parity error 3 = Control line sequence error
4 = Poll detect
5 = Count error 6 = Disconnected operation 7 = Overrun/underrun 8 = Normal/FCB end 9 = Bus not zero 10 = Timeout 11 = End error
12 = Program requested interrupt
13 = Machine check 14 = Enabled
15 = Interruption
Tape unit status byte, where:
Bit 0 = Ready 1 = Busy 2 = Write Enabled 3 = Beginning of Tape
4 = End of Tape
5 = Op Complete
6 = Low Speed 7 = Positioning
Program set status byte, where:
Bit 0 = Adapter status indicates an error 1 = Error on Read Sense command 2 = Busy and Op Complete on together 3 = 10-second ending timeout in disconnected Op
4 = Sense information in storage is valid 5 = 10-second ending status timeout not disconnected Op
6 = Reel selected alert 7 = Real control line timeout
Last command sent to tape unit Sixteen tape unit sense bytes
See General Failure Index (ST100)
Notes: 1. Formats 3 and 4 may be truncared from the right, by field, on certain errors, depending
on available information.
2. Will be FFFF if status is not reliable.
TA232 DPCX Online Exerciser The following messages are generated while running the DPCX online exerciser.
Format Type
1 2 3
Message
XXBC PAXX PAXE RR EN SYMC CFPF ECOP ARCX TCSB XXXX XXXX MCOO MEME
Note: XXBC and SYMC are the error messages needed for MAP "Test Symptom Code'~
Where:
Format 1 - XXBC:
XX
Error number
BC
= Indicates a system error detected by the test control monitor
(see General Failure Index, ST200)
Format 2 - PAXX:
PA
The address of the component under test
XX
00 - Successful completion test
XX
01 - Mount a tape. Enter 'B' when complete
XX
02 - Waiting for ready
XX
90 - Selected device busy or unavailable for testing
XX
FO - Test in progress
Format 3 - PAXE:
PA
The address of the component under test
x
1 - Indicates the 'PA' is the adapter address
x
2 - Indicates the 'PA' is the tape drive address
E
E - Indicates that this is an error message
RR
Routine number that failed
EN
Error number (see TA244 for explanation)
SYMC Symptom Code (see TA243 Routine SC for list of codes)
*CF
Retry and Completion Flags (IOCB Byte 2)
*PF
Program Flags (IOCB Byte 3)
*EC
Error Code (IOCB Byte 23)
*OP
Operation number
*ARCX = Adapter Return Code
TCSB Adapter Status Bytes
xxxx = Tape Unit Sense Bytes (16)
*MCOO = Macro completion Code plus 1 byte of 00 *MEME = Macro Error Code
*This information is not needed by the MAPs.
SY27-2621-3
(TA220-TA232)
6-TA·11
TA233 Status and Sense Bytes
This section lists and describes the status and sense bytes used for the 8809. Figure 233-1 shows all 16 tape drive sense bytes, as well as the two adapter status bytes, which are then discussed and shown in detail.
Sense Byte 0 (Tape Unit Status)
Ready
Busy
Write Enable
BOT
EOT
Operation Complete
Low Speed
Positioning
Bit 0 - Ready: indicates that the tape drive has a tape loaded with tension established.
Bit 1 - Busy: set with the initiation of a Disconnected command and remains set until receiving an Op Complete or a Check Reset. Also set while performing a load rewind operation from the tape operator panel.
Bit 2 - Write Enable: set when the tape is not file protected (write enable ring installed). Write commands set Selected Alert when issued to the tape drive with Write Enable off.
Bit 3 - BOT: set when the tape is positioned at the beginning of tape (BOT) marker. Any backward command issued to the tape drive with BOT on sets Selected Alert.
Bit 4 - EQT: set when sensing the end of tape (EQT) marker in the forward tape direction and reset when sensing the EQT marker in the reverse direction.
Bit 5 - Operation Complete: set when completing a disconnected command (other than space file) with the tape drive at the stop lock position. During a space file operation, the bit sets when a tape mark is detected. Also set when performing a load rewind from the tape operator panel. This bit is reset by Check Reset.
Bit 6 - Low Speed: when set, indicates that the speed of the tape drive is 31.75 centimeters/seconds (12.5 ips). When reset, the speed is 254 centimeters/second (100 ips).
Bit 7 - Positioning: indicates that the tape drive is in a positioning sequence.
SY27-2521-3
5-TA-12
Status Byte
Sense Byte
0
Ready
Busy
Write Enable
BOT
EQT
Operation Complete
Low Speed
Positioning
Check End Sense
Bus Out Parity Check *
Tag Bus Formatter
Parity
Write or *
Check * CNT-L Failure
CNTL-L Sequence Check *
Command Drive
Register
Control
Parity Chk * Parity Chk*
Formatter Read Failure *
2
Data Overrun
Data Check
---
BOT
EQT
Tape Mark Detected
Not Capable
3
Write Bus Parity Check *
Bus Out Register Parity Chk*
Gap Control Check *
Sync Out Check *
Drive
D Not
Response Capable
Check * (Space File)*
Track in Error P
4
Same as 3-0
Read Bus Parity Check *
Same as 3-2
Same as 3-3
---
---
Same as 3-6
POINTER REGISTER
5
Track
Track
Track
Track
Track
Track
Track
0
1
2
3
4
5
6
1 =Write
PEID
Multitrack End
Start
Read Back Envelope
I I Command Check
Error
Data Check Read Check Failure
Check
fl -- ------ 6
- - ~-- - -
- -------,
------ I- - -- --- -- - - -
0 =Non Write
No Track Pointer
Multitrack End
Start
Error
Data Check Read Check
Crease
Unused
---
Write Enable Error *
Same as 3-7
Track 7
Write TM Error
- - - ----"
Skew Error
7
---
---
---
--- ---
---
---
---
8
9
10
11
12
13
14
15 Adapter Status Extended Adapter Status
0
TRANSPORT STATE
,
2
3
Sequence
4
Error *
Start
End
PEID
Clock
Velocity
Velocity
Velocity
Parity
Check
* Check
* Check
* Error
*
SERVO STATE
0
1
Load Check
Tension * Check
Cover/Reel
*
Latch Interrupt
*
Tension Status
Not Ready
Due to Reset *
Long Gap Mode
PRESENT TRANSPORT STATE
Cover/Reel
Latch Inter-
0
1
2
3
4
..Llock Status
Servo Logic Failure * Idler Tach Failure *
BOT/EQT LED Failure
Servo Analog Failure * Machine Tach Failure * Tape Present
LED Failure *
Write Current Failure File Tach Failure Reel Size LED Failure
Erase
Current * Failure *
Idler Tach
Rotation
* Check
*
Drive
Control
* Failure *
PRESENT SERVO STATE.
0
1
---
---
--- ---
File Amplifier Saturation *
NonRecoverable Error
Machine Amplifier Saturation * Invalid Sub Command
Write Status
Adapter Parity Check
PA Cable Unseated
*
LWR Failure
CNTL-L Poll/
Sequence Command
Error
Mach Chk
Adapter PIO Command
Residual Count Error
Normal/ FCB End
Bus Not Equal to Zero
Timeout
End Error
Program Requested Interrupt
Machine Check
**
0 Sense byte 1, bit 0 (1-0) and 2-6.
f l I J Any bit sets 2-1 (except Read Back Failure-see I J If 1-0 is off, brings up 1-7 and activates the Selected Alert line.
*These bits activate the Selected Alert line. **These adapter bits do NOT cause an interrupt.
Sense Bus Parity Check * Same as 8-6
Same as 8-6
Same as 8-6
Same as 8-6
Same as 8-6
Same as 8-6
Same as 8-6
Disconnect
Interrupt Enable
**
---
---
---
---
---
---
---
Unexpected Adapter Status Overrun/ Underrun Interrupt/ Halt
**
Figure TA233-1. Status and Sense Bytes
Sense Byte 1 Sense Byte 2
Check End Sense
. Bus Out
Parity Check
Tag Bus Formatter
Parity Check
* WCNriTte-LorFailur*e
CNTL-L Sequence Check *
Command Register Parity Chk *
Drive
Formatter
Control
Read
Parity Chk* Failure *
*These bits activate the Selected Alert line.
Bit 0 - Check End Sense: indicates that either a Check End occurred following the last command or that Not Capable occurred during a space file operation. Sense byte 2 is valid when this bit is on.
Bit 1 - Bus-Out Parity Check: set if even parity is detected on the Control Line Bus Out during a Write Data transfer.
Bit 2 - Tag Bus Parity Check: set if even parity is detected on the Control Line Tag Bus Out.
Bit 3 - Formatter Write or Control Line Failure: indicates internal failure of either the Control Line or the Write modules.
Bit 4 - Control Line Sequence Check: set when a Control Line sequence error occurred.
Bit 5 - Command Register Parity Check: set when odd parity is detected on the Command Register bus from the formatter card to the drive control card.
Bit 6 - Drive Control Parity Check: set when odd parity is detected on the control bus from the drive control card.
Bit 7 - Formatter Read Failure: indicates either an internal failure of the Read, or readback data did not occur when expected during a Write command.
Data Overrun
Data
---
BOT
Check
EQT
Tape Mark Detected
Not Capable
---
Bit O - Data Overrun: no write data available when the tape drive is ready to receive it.
Bit 1 - Data Check: indicates that one or more of the sense byte 6 bits are active.
Bit 2 - not used.
Bit 3 - BOT: see sense byte 0, bit 3.
Bit 4 - EQT: set only when EQT is detected during either a Write, Write Tape Mark, or Erase Gap operation.
Bit 5 - Tape Mark Detected: indicates a tape mark was detected during a Read or Space Block operation.
Bit 6 - Not Capable: set when a 160crbpi ID burst is not detected while reading or spacing from BOT. This bit is also set with a Data Check (sense byte 2, bit 1) due to a PEID Burst Check (sense byte 6, bit 1) during a write from BOT.
Bit 7 - not used.
Sense Byte 3
Sense Byte 4
Write Bus Parity Check *
Bus Out Register Parity Chk*
Gap
Control Check *
Sync Out Check
*
Drive
D Response
.. Check
Not Capable (Space File)
* These bits activate the Selected Alert line.
D Sets sense byte 1, bit 0 and sense byte 2, bit 6.
Track in Error P
Write Enable Error *
Bit 0 - Write Bus Parity Check: indicates even parity on the 10-bit bus to the write card.
Bit 1 - Bus-Out Register Parity Check: indicates even parity on the internal formatter bus from the bus-out register.
Bit 2 - Gap Control Check: indicates the gap control line dropped before writing a complete record.
Bit 3 - Sync-Out Check (Write only): set when more than one sync-out signal is received from the adapter in response to a single sync-in, or the sync-out signal did not reset in the specified time.
Bit 4 - Drive Response Check: set if motion logic responds either early or late to the Formatter command.
Bit 5 - Not Capable (Space File): set when the PEID burst is not detected while executing a space file operation from BOT. This bit sets sense byte 1, bit 0 and sense byte 2, bit 6.
Bit 6 - Track in Error P: indicates the Track P pointer was on at the end of the last operation in which a data check occurred.
Bit 7 - Write Enable Error: indicates that a write was attempted with Write Enable off.
Same as 3-0
Read Bus Parity Check *
Same as 3-2
Same as 3-3
*These bits activate the Selected Alert line.
---
---
Same as 3-6
Same as 3-7
Bit 0 - Write Bus Parity Check: same as sense byte 3, bit 0.
Bit 1 - Read Bus Parity Check: indicates bad parity on the read data bus from the Read Control module to the Bus In Assembler.
Bit 2 - Gap Control Check: same as sense byte 3, bit 2.
Bit 3 - Sync-Out Check: same as sense byte, bit 3. Bits 4 & 5 - Not used.
Bit 6 - Track in Error P: same as sense byte 3, bit 6. Bit 7 - Write Enable Error: same as sense byte, bit 7.
SY27-2521-3
(TA233)
5-TA-13
SY27-2521-3
5-TA-14
Sense Byte 5
Track 0
Track 1
Track
2
POINTER REGISTER
Track
Track
3
4
Track 5
Track 6
Track 7
This byte contains the track-in-error pointers for tracks 0-7. It contains track(s) for which pointers were on at the end of the last operation in which a data check occurred.
Sense Byte 6 - Write Block or Write Tape Mark Only (Bit 0 = 1)
1 =Write
PEID
I J Command
Check
- - - 1------ - - - - - - 1-- - - -
-
Multitrack End
Start
Read Back
Envelope
Error
Data Check Read Check Failure
Check
----- --------1
- - 1------<
Write TM Error
- ---
fl I I ). Any bit sets sense byte 2, bit 1 except for a Read Back Failure (see
IJ If sense byte 1, bit 0 is off, sets sense byte 1, bit 7 and also activates the
Selected Alert line.
Bit 0 = 1 =Write Command.
Bit 1 - PEID Check (with Data Check): set when PEID burst is not detected during read-back check when writing from the BOT marker.
Bit 2 - Multi-Track Error: set if a multiple track error (more than one pointer) is detected during read-back check.
Bit 3 - End llita Check: set when an IBG is detected earlier or later than expected during read-back check.
Bit 4 - Start Read Check: set if Beginning of Record drops, or an IBG is detected after Beginning of Record but before the first 1-bits of the preamble during read-back check.
Bit 5 - Read-Back Failure:
· Sense byte 1, bit 0 not set: indicates read-back data did not occur when expected during a Write command. Also sets Selected Alert and Formatter Read Failure (sense byte 1, bit 7).
· Sense byte 1, bit 0 set: indicates that a crease was detected during the read-back check of a Write command, and does not set Selected Alert.
Bit 6 - Envelope Check: set when a skew buffer parity check or any phase error is detected during read-back check.
Bit 7 -WTM Error: indicates fewer than 40 bytes of tape mark were written during a write tape mark operation.
Sense Byte 6 - Not Write Block or Write Tape Mark (Bit 0 = 0)
- ~--- - - - - - - - - - - ----..., -----;1----- '""1--- -- - - ---i
0 =Non Write
No Track Pointer
Multitrack Error
End
Start
Data Check Reed Check
Crease
Unused
Skew Error
f l Any bit sets sense byte 2, bit 1.
Bit 0 = 0 = Non-Write Command.
Bit 1 - No Track Pointer: indicates Skew Buffer parity check (VRC) with no track pointer on.
Bit 2 - Multi-Track Error: set-if a multiple error (more than one pointer) is detected. The data was uncorrectable.
Bit 3 - End Data Check: set when an IBG is detected earlier or later than expected
Bit 4 - Start Read Check: set if Beginning of Record drops, or an IBG is detected after Beginning of Record but before the first 1-bits of the preamble.
Bit 5 - Crease: set when IBG is detected during data transfer and crease timeout is not reached.
Bit 6 - Not used.
Sense Byte 7 - Not Used
Bit 7 - Skew Error: indicates a skew buffer overflow.
Sense Byte 8
TRANSPORT STATE
l J l 0
1
l 2
3
4
* These bits activate the Selected Alert line.
. . Sequence
Error
Sense Bus Parity Check
---
Bits 0-4 Transport State: show the encoded state of the tape drive at the time a sequence error (sense byte 8, bit 5) occurred.
The transport states are:
Sense Bit
01234
State Name
00000 00001 00010 00011 00100 00101 00110
00111
01100 01101 01111 01110 01001 01000 11000 11001 11011 11010 11110 11111 11101 11100 10100 10101 10111 10110 10010 10011 10001
Idle Take Up Slack Enable Servo Sample Radius High-Speed Load Point Rewind Stop Rewind Forward Space Rewind Low-Speed Load Point Move to BOT Space Over BOT Write ID Burst Unload Leader Space to Low-Speed Load Data Security Erase Set Erase Gate, Alternate Direction Low-Speed Degauss Prepare Gap Control, Alternate Direction Prepare Gap Control, Previous Direction Write Backward Hitch Set Erase Gate, Previous Direction Low-Speed Wait High-Speed Walt Overrun, Alternate Direction Move From Hold Degauss Area Reversal Overrun Same Direction Go Hold Over
Bit 5 - Sequence Error: indicates the loss of tension while the servo is active (Tension Check - sense byte 10, bit 1) or a Load Check (sense byte 10, bit 0) occurred.
Bit 6 - Sense Bus Parity Check: set when even parity is detected on the internal sense bus during a Read Sense command for sense bytes 8-15. Any byte 8-15 can contain the first occurrence of this error indicator, and, once detected, sets bit 6 of all remaining check bytes.
Bit 7 - Not used.
Sense Byte 9
Start Velocity Check
End Velocity
· Check
. PEID Velocity Check
. Clock Parity Error
.
* These bits activate the Selected Alert line.
SERVO STATE
l 0
1
Same as 8-6
---
Bit 0 - Start Velocity Check: indicates a velocity problem occurred before a write data transfer.
Bit 1 - End Velocity Check: indicates a velocity problem occurred during a write data transfer.
Bit 2 - PEID Velocity Check: indicates a velocity problem occurred while attempting to write a PE ID burst.
Bit 3 - Clock Parity Error: set if an internal parity error is detected in the clock generation module.
Bits 4 & 5 - Servo State: indicate the encoded state of the servo at the time of a sequence error (sense byte 8, bit 5).
The following shows bits 4 and 5 interpretation:
Blt14 and 6 State Name
00
Idle
01
Stoplock
10
Run
11
Plug Start
Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6. Bit 7 - Not used.
SY27-2521-3
(TA233 Cont)
6-TA-15
SY27-2521-3
5-TA-16
Sense Byte 10
Load Check
Tension * Check
Cover/Reel Latch * Interrupt *
Tension Status
*These bits activate the Selected Alert line.
Not Ready
Due to Reset *
Long Gap Mode
Same as 8-6
---
Bit 0 - Load Check: indicates that a load rewind initiated from the tape operator panel failed to execute.
Bit 1 - Tension Check: indicates tension failure caused a sequence error (sense byte 8, bit 5).
Bit 2 - Cover/Reel Latch Interrupt: indicates an active condition of either the cover interlock or the reel latch interlock while the tape is loaded and the reel motors are under servo control. This condition inhibits Ready and Reset.
Bit 3 - Tension Status: indication to the transducer channel that a tape is present as detected by the 'tape present' sensor.
Bit 4 - Not Ready Due to Reset: indicates that the RESET pushbutton on the tape operator panel has reset Drive Ready. Also set when a command was issued that expected a ready condition, and the drive was not ready.
Bit 5 - Long Gap Mode: indicates that the tape drive is in Long Gap Mode.
Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6.
Bit 7 - Not used.
Sense Byte 11
PRESENT TRANSPORT STATE
I l I l 0
1
2
3
4
Cover/Reel Latch Interlock Status
Same as 8-6
---
Sense byte 11 presents the tape drive and cover interlock status while executing the Read Sense Byte 11 command.
Bits 0-4 - Present Transport State: show the present tape drive status. See Sense Byte 8 for an explanation of the bits.
Bit 5 - Cover/Reel Latch Interlock Status: indicates the cover is open.
Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6.
Bit 7 - Not used.
Sense Byte 12
Servo Logic Failure
Servo
. Analog Failure
Write Current * Failure
Erase Current * Failure
PRESENT SERVO STATE
*
l 0
1
Same as 8-6
---
*These bits activate the Selected Alert line.
Bit 0 - Servo Logic Failure: indicates a failure on the drive control card associated with the servo.
Bit 1 - Servo Analog Failure: indicates a failure on the power amplifier card.
Bit 2 - Write Current Failure: indicates either detection of no write current after setting write status or detection of improper current in the write head, which could destroy data.
Bit 3 - Erase Current F~ilure: indicates either detection of no erase current after setting erase status or detection of improper current in the erase head, which could destroy data.
Bits 4 & 5 - Present Servo State: indicate the state of the servo while executing the Read Sense Byte 12 command. See Sense Byte 9 for an explanation of the bits.
Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6.
Bit 7 - Not used.
Sense Byte 13
Idler Tach Failure
. Machine
File
Tach
Tach
Failure * Failure
. . Idler Tach Rotation Check
---
---
Same as
---
8-6
* These bits activate the Selected Alert line.
Bit O - Idler Tach Failure: indicates detection of an idler tachometer failure in the 'run' servo state.
Bit 1 - Machine Tach Failure: indicates detection of a drive reel motor tachometer failure. Bit 2 - File Tach Failure: Indicates detection of a file reel motor tachometer failure.
Bit 3 - Idler Tach Rotation Check: indicates the idler tachometer frequency is below a minimum allowable level during a normal start/stop operation. This condition can be caused by a tension failure, the tape sticking at the read/write head, or an idler tachometer failure.
Bits 4 & 5 - Not used.
Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6.
Bit 7 - Not used.
Sense Byte 14
BOT/EQT
LED Failure*
. . Tape Present Reel Size
LED
LED
Failure
Failure
Drive Control Failure
.
---
---
Same as 8-6
---
*These bits activate the Selected Alert line.
Bit 0- BOT/EOT LED Failure: indicates no current is detected in the BOT or EOT sensor LEDs.
Bit 1 - Tape Present LED Failure: indicates no current is detected in the tape sensor LED.
Bit 2 - Reel Size LED Failure: indicates either (1) that no current is detected in one of the reel size sensor LEDs, (2) that the measured radius of the tape exceeds the reel size, or (3) detection of an incorrect reel size.
Bit 3 - Drive Control Failure: indicates a failure in the control module. Bits 4 & 5 - Not used. Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6. Bit 7 - Not used.
Sense Byte 15
. File
Amplifier Saturation
Machine Amplifier Saturation ·
Write Status
PA Cable Unseated
·
* These bits activate the Selected Alert line.
LWR Failure
Adapter PIO Command
Same as 8-6
Unexpected Adapter Status
Bh 0 - File Amplifier Saturation: indicates that the file reel motor amplifier detected a
voltage saturation condition.
Bit 1 - Machine Amplifier Saturation: indicates that the machine reel motor amplifier detected a voltage saturation condition.
Bit 2 - Write Status: indicates that the tape drive has just executed a Write, Write Tape Mark, Erase Gap, or ll:lta Security Erase command.
Bit 3 - Power Amplifier Cable Unseated: indicates that the cable between the logic gate and the power amplifier board is not properly seated at either or both connectors.
Bit 4 - LWR Failure: indicates a failure occurred while performing an LWR command.
Bit 5 - Adapter PIO Command: indicates the last command issued by the adapter was a PIO-type command.
Bit 6 - Sense Bus Parity Check: same as sense byte 8, bit 6.
Bit 7 - Unexpected Adapter Status: indicates the adapter status bits were not as expected after issuing a command.
SY27-2521-3
(TA233 Cont)
5-TA-17
Adapter Status Bytes
Adapter
St~tus
Extended
Adapter Status
NonRecoverable Error
Normal/ FCB End
Invalid Sub Command
Bus Not Equal to Zero
Adapter Parity Check
Timeout
CNTL·L Sequence Error
End Error
Poll/ Command Mach Chk
Program Requested Interrupt
** These adapter bits do NOT cause an interrupt.
Residual Count Error
Machine Check
··
Disconnect
Overrun/ Underrun
.. .. Interrupt
Enable
Interrupt/ Halt
Bit 0 - Nonrecoverable Error: set when the adapter detects a parity error when transmitting either the basic or extended address to the processor during a Transfer in Channel (TIC) command.
Bit 1 - Invalid Subcommand: set when (1) tape command bits 5-7 Byte 0, halfword 0 do not compare with bits 1-3 Byte 0, halfword 1 in the command FCB; (2) either an FCB data bit does not follow a read/write FCB command, or when receiving a new command before receiving the end of data in an 8809 read/write sequence; (3) receiving an invalid command during a PIO operation.
Bit 2 - Adapter Parity Check: an internal adapter parity error was detected.
· If the error occurred on data transfer from the tape bus, bit 3 is also set. · If the error occurred on data transfer to the processor, parity is corrected before any
transfer and the operation terminates. · If the error occurred on data transfer to the tape, recycle drops, parity is corrected
before any transfer, and the operation 'erminates.
Bit 3 - Control Line Sequence Error: set for the following conditions:
· Along with status bit 2 when a parity error is detected while transferring data from tape.
· Along with basic status bit 10 when no response causes a timeout error. · When Select Hold and Select Active are not on either when initiating a sequence other
than Selection, or when receiving a Select command with 'Select' active. · Along with End Error when Normal End did not set with Tag Valid active.
Bit 4 - Poll/Command Machine Check: set when either receiving a response to a Poll command, or when a machine check occurs during any channel 1/0 operation using a channel control vector (CHCV).
Bit 5 - Residual Count Error: set during a read sequence with the Suppress Length Flag off, when the number of bytes transferred by a tape unit does not equal the segment count.
Bit 6 - Disconnect: set when the adapter issues a Disconnect command.
Bit 7 - Overrun/Underrun: set when a delay occurs in processor information transfer. The adapter either does not have sufficient buffer space to continue operation to the tape or sufficient data to transfer to the processor.
SY27-2521·3
5-TA-18
Bit 8 - Normal or FCB End: after receiving a Sequence command on the PIO bus, this bit sets when receiving a Normal End from the tape drive at the completion of an Execute sequence. For a Sequence command received from an FCB, this bit is set only: (1) if the Normal End Tag Line from the tape drive is active and Ending Status does not equal O; (2) after the completion of the 'Disconnect Command Sequence'; or (3) after an FCB 'End Op' Command.
Bit 9 - Bus Not Equal to 0: set when receiving a Normal End (bit 8 is also set) with ending status not equal to hex 00 (BOT or EQT mark detected). If command was received from an FCB, no additional requests to the FCB are made. Also set when the address of the TAM responding to a Select sequence does not agree with the transmitted address.
Bit 10 - Timeout: set approximately one second after receiving the Enable Timer com· mand. Also set when the entire sequence did not complete within the time expected, and also sets Status Bit 3 for this condition.
Bit 11 - End Error: set when receiving either Selected Alert or Check End from tape.
Bit 12 - Program Requested Interrupt: set when receiving Program Requested Interrupt (PRI bit) during FCB operation.
*Bit 13 - Machine Check: set when a processor machine check occurred while communicating with the tape adapter.
*Bit 14 - Interrupt Enable: set to allow the adapter to make interrupt requests and to initiate channel requests. When reset, the adapter removes any requests'before responding with valid.
Bit 15 - Interrupt/Halt: this bit is the 'OR' of conditions defined that cause an interrupt. Set by the Halt signal, and also when the adapter is going to suppress a response because of receiving bad parity on the processor bus.
*Bits 13 and 14 do not cause an interrupt.
TA240 Test Error Message Descriptions
All TA offline and DPCX online exerciser test error messages (such as PAXE RREN SSSS) have an error number (EN). This error number indicates the type of failure detected, as well as additional status information available according to the test error message format. The routine number {RR) and the EN determine the error message formats.
The following sections contain a list of all error numbers used for each routine and describe their meaning. Section TA241 lists and describes the adapter test error numbers, section TA242 contains those used for tape drive testing, TA243 contains the test error messages used for the special requirement tests, and TA244 Iists and describes the test error messages generated when running the DPCX Online Exerciser. Refer to the TA230 section for test message formats.
TA241 Adapter Test Messages
The following table lists, for each routine, the error numbers and their description for the adapter tests. For test message formats, see T A231.
RREN
0101 0104 0106 0109 010C
Format
2 1 1 1 2
Meaning
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. CHIO machine check. Solid 1/0 machine check.
0201
2
0202
1
0204
1
0206
1
0207
1
0208
1
0209
1
020C
2
Unexpected machine check. Expected machine check did not occur. Unexpected 1/0 interruption. Interruption always active. Machine check status not set by invalid command. Invalid subcommand bit not set by invalid command. CHIO machine check. Solid 1/0 machine check.
0301
2
0304
1
0306
1
0309
1
030C
2
0310
1
0311
1
0312
1
0313
1
0314
1
0315
1
0316
1
0317
1
0318
1
0319
1
031A
1
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. CHIO machine check. Solid 1/0 machine check. CHCVD register write-read did not compare. CHCVD register not 0 after adapter reset. CHCVC register write-read did not compare. CHCVC register not 0 after adapter reset. Segment count register write-read non-compare. Segment count register not 0 after adapter reset. BADDR write-read did not compare. BADO R not 0 after adapter reset. EADDR write-read did not compare. EADD R not 0 after adapter reset. PSAR write-read did not compare.
SV27-2521-3
RREN
0318 031C 0310 031E 031F 0320 0321
0401 0404 0405 0406 0409 040C 0422 0423 0424 0425 0426 0427 0428 042A 042B 042C 0420
0501 0504 0506 0507 0509 050C 052E 052F 0530 0531 0532
0601 0604 0606 0609 060C 0633 0634 0635
0636
0637 0638 0639 063A
Format
1 1 1 1 1 1 1
Meaning
PSAR not 0 after adapter reset. CLSAR write-read did not compare. CLSAR not 0 after adapter reset. Burst length register write·read did not compare. Burst length register not 0 after adapter reset. Burst length counter set-read did not compare. Burst length counter not 0 after adapter reset.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
1/0 interruption did not occur.
1
Interruption always active.
1
CHIO machine check.
2
Solid 1/0 machine check.
1
Basic status not 0 after adapter reset.
1
Extended status not 0 after adapter reset.
1
Extended status set/read did not compare.
1
Interrupt bit not set by extended status bit.
1
Basic status set/read did not compare.
1
Interrupt bit not set by basic status bit.
1
Interrupt bit set by machine check bit.
1
Extended status bit not reset under mask.
1
Basic status bit not reset under mask.
1
Set basic status failed to set pending bit.
1
Enable bit not reset by reset basic status.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
1
Incorrect basic status after timer interruption.
1
CHIO machine check.
2
Solid 1/0 machine check.
1
Timer did not cause interruption.
1
Incorrect extended status after timer interruption.
1
Timer less than 800 ms.
1
Timer longer than 1200 ms.
1
Extra timer interrupt.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
1
CHIO machine check.
2
Solid 1/0 machine check.
1
CLSAR set by Set PSAR command.
1
PSAR set by Set CLSAR command.
1
Burst Length Counter set by Write Segment Counter
command.
1
Segment Counter set by Load Burst Length Counter
command.
1
PSAR not stepping correctly.
1
CLSAR not stepping correctly.
1
Segment counter not stepping correctly.
1
Burst length counter not stepping correctly.
(TA233 Cont-TA241)
5-TA-19
RREN
0640 0641 0650 0651
0701 0704 0706 0709 070C 0738 073C 0730 073E 073F
0801 0804 0806 0807 0809 OBOC 082F 0840 0841
0901 0904 0905
0906 0909 090C 0942 0943
1101 1104 1105 1106 1109 110C 1143
1201 1204 1205 1206 1209 120C 1244
Format 1 1 1 1
Meaning
CLSAR set by Write Segment Counter command. CLSAR set by Load Burst Length Counter command. PSAR set by Write Segment Counter command. PSAR set by Load Burst Length Counter command.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
1
CH 10 machine check.
2
Solid 1/0 machine check.
1
Buffer write-read did not compare.
1
PSAR did not step on read buffer command.
1
PSAR did not step on write buffer command.
1
Parity error while reading buffer.
1
Parity error while writing buffer.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
1
Basic status incorrect.
1
CHIO machine check.
2
Solid 1/0 machine check.
1
Extended status incorrect.
1
CLSAR did not step on wrap.command.
1
Wrapped data not equal to original
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
No interruption after executing Function Control Block
(FCB) list.
1
Interruption always active.
1
CH 10 machine check.
2
Solid 1/0 machine check.
1
Command CPR not stepping correctly.
1
Normal end status not set after FCB list was executed.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
No 1/0 interruption after executing FCB list.
1
Interruption always active.
1
CH 10 machine check.
2
Solid 1/0 machine check.
1
Command TIC did not branch.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
No 1/0 interruption after executing FCB list.
1
Interruption always active.
1
CH I0 machine check.
2
Solid 1/0 machine check.
1
Program-Requested Interrupt (PR I) bit not on in status
byte after PR I FCB.
SY27-2521-3
RREN
1301 1304 1305 1306 1309 130C 1345
1401 1404 1405 1406 1408 1409 140C 1446
1501 1504 1505 1506 1509 150C 1540
Format
2 1 1 1 1 2 1
Meaning
Unexpected machine check. Unexpected 1/0 interruption. No 1/0 interruption after executing in valid FCB. Interruption always active. CHIO machine check. Solid 1/0 machine check. Invalid subcommand bit not set by bad FCB.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
No interr,uption after executing TSTCLP command.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
1
Parity error status bit not on after TSTCLP command
execution
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
No 1/0 interruption from test Stop command.
1
Interruption always active.
1
CH 10 machine check.
2
Solid 1/0 machine check.
1
Control line sequence error bit not set.
5-TA-20
TA242 Tape Drive Test Messages The following table lists, for each routine, the error numbers and their meaning for the tape drive tests. For test message formats, see TA231.
RREN Format Meaning
4001
2
4004
1
4006
1
4008
3
4009
1
400C
2
4011
3
4014
3
4016
3
4017
3
4018
3
4019
3
401A
4
4021
4
40FO
3
40F1
3
40F2
3
40F7
3
40F8
3
40F9
3
4101
2
4104
1
4106
1
4108
3
4109
1
410C
2
4111
3
41FO
3
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active Open adapter failure. CHIO machine check. Solid 1/0 machine check. Selected Active did not come on or low-order 3 bits of
returned adddress incorrect. End error up after adapter reset. Bus not 0 after adapter reset. Timeout on select command.
Check the following items for possible causes of failure:
1. Tape drive is powered down.
2. Tape drive was not ready prior to running tests. Power down tape drive, then power up drive and make ready.
3. Invalid drive address entered or no drive on system with that address.
4. Incorrect address set in drive address switches.
5. No LV L 02 entry in Configuration Table for drive address entered.
6. Bus and Tag cables loose or not connected (Model 1A only).
7. 8101 paddle connectors at A2 Y1 and A2 Z1 loose (Model 1A only).
No normal end after select command. Bus-in parity error on selection. High-order 5 bits of returned address on selection are
incorrect. A bus-in bit did not turn on. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error. Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CHIO machine check. Solid 1/0 machine check. Control line sequence error not set by selecting a selected drive. Selected Alert when not expected.
SY27-2521-3
RREN
41F1 41F2 41F7 41F8 41F9 4201 4204 4206 4208 4209 420C 4210-17 4218-1 F 4220-27 4228 4229 422A 4228 422C 4220 422E 422F 4230-37 4238 4239 4240-47 4248 4249 4258 4259 4268 4269 4278 4279 4280-87 4288 4289 4290-97 4299 42AO-A7 42A9 4280-87 4289 42CO-C7 42C9 4200-07 4209 42DA 4208 42EO-E7 42E8-EF
Format
3 3 3 3 3 2 1 1 3 1 2 4 4 4 3 3 3 3 3 3 3 3 4 3 3 4 3 3 3 3 3 3 3 3 4 3 3 4 3 4 3 4 3 4 3 4 3 3 3 4 4
Meaning
Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error. Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CH 10 machine check. Solid 1/0 machine check. Sense byte 1 not correct. Sense byte 0 not c.orrect. Sense byte 2 not correct. Control line timeout on check reset. Bus-in parity error on check reset. Control line timeout reading status byte. Bus-in parity error reading status byte. Control line timeout reading byte 1. Control line parity error reading byte 1. Control line timeout reading byte 2. Control line parity error reading byte 2. Sense byte 3 not correct. Control line timeout reading byte 3. Control line parity error reading byte 3. Sense byte 4 not correct. Control line timeout reading byte 4. Control line parity error reading byte 4. Control line timeout reading byte 5. Control line parity error reading byte 5. Control line timeout reading byte 6. Control line parity error reading byte 6. Control line timeout reading byte 7. Control line parity error reading byte 7. Sense byte 8 not correct. Control line timeout readir,g byte 8. Control line parity error reading byte 8. Sense byte 9 not correct. Control line parity error reading byte 9. Sense byte 10 not correct. Control line parity error reading byte 10. Sense byte 11 not correct. Control line parity error reading byte 11. Sense byte 12 not correct. Control line parity error reading byte 12. Sense byte 13 not correct. Control line parity error reading byte 13. Control line parity error reading byte 14. Control line parity error reading byte 15.
Sense byte 14 not correct. Sense byte 15 not correct.
(TA241 Cont, TA242)
5-TA-21
RREN
4301 4304 4306 4308 4309 430C 4311
4313 4314 4315
4316 4317 4318 4319
431A 431B
431C 431D 43A1 43A2
43A3 43A4 43A5 43A6 43A7 43A8 43A9 43AA 43AB 43AC 43AD 43FO 43F1 43F2 43F7 43F8 43F9 4401 4404 4406 4408 4409 440C 4411 4412 4413
Format
2 1 1 3 1 2 3
3 3 3
3 3 3 3
3 3
3 3 3 3
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 1 1 3 1 2 3 3 3
Meaning
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CHIO machine check. Solid 1/0 machine check. Control line timeout on Loop write to Read (LWR)
command.
Check end on LWR and check byte 6, bit 0 = 0. Check end on LWR and check byte 6, bit 4 = 1.
Check end on LWR and check byte 6, bits 1, 3, 6, 7 not all 0.
Check end on LWR and check byte 6, bits 1, 3, 6, 7 all 0. LWR command failed. Tape drive file protected. One or more pointers are on following an LWR command
that ended with normal end. Normal End did not drop. Check End not set. Normal End and Select Alert are both
off. Data overrun. Sense byte 2, bit 1 failed. Selected Alert on LWR and bus-out parity check was on. Selected Alert on LWR·and WRT/INTF PLA
failure. Selected Alert on LWR and sequence check is on. Selected Alert on LWR and write bus parity check is on. Selected Alert on LWR and gap control check is on. Selected Alert on LWR and sync out check is on. Selected Alert on LWR and no tape drive response. Selected Alert on LWR and read back fail is on. Selected Alert on LWR and write/erase current fail. Selected Alert on LWR. Appears to be a motion problem. Clock fail during LWR. Selected Alert on LWR and none of the above conditions. Read PLA fail. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error. Unexpected machine check. Unexpected 1/0 interruption. Interruptiuo always active. Op~n adapter failure CHIO machine check. Solid 1/0 machine check. Bus-in bit for device under test is on and should be off. Bus-in bit for device under test is off and should be on. Op Complete not on.
SY27-2521-3
6·TA·22
RREN
4414 4415 4416
4420 4421 4422 4423 4424 4425 44FO 44F1 44F2 44F7 44F8 44F9
4601 4604 4606 4608 4609 460C 4614 4615 4616 4617 4618 4619 461F 4620 4621 4622 4623 4627 4628
4629
4631 4632 4633 4634 4635
4636
4637 4638 4639 463A 4638 463C
Format
3 3 3
3 3 3 3 3 3 3 3 3 3 3 3
Meaning
Op Complete not reset by check reset. Bus-in bit for device under test is on and should be off. Bus-in bit for device under test is on. It was suppressed
and should be off. Control line timeout on poll operation. Selected Alert on poll operation. Control line timeout on rewind operation. Selected Alert on rewind operation. Ready status off after rewind. Busy after reception of OP Complete Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
Bus-in parity error on SLS.
3
Bus-in parity error on ERG.
3
EQT status after ERG operation.
3
Control line timeout on SLS command.
3
Ten-second ending status timeout on SLS operation.
3
Busy still on after OP complete on SLS operation.
3
Sense byte 11, bits 0-4 = 01100 after SLS.
3
Op Complete not reset by check reset.
3
Sense byte 12, bits 4 & 5 not= 01 after rewind.
3
Control line timeout on ERG operation.
3
Ending status timeout on erase gap command.
3
BOT status still on after erase gap command.
3
Sense byte 11 not equal to 011 OOXXX after erase gap
command.
3
Sense byte 12 not equal to XXXX01 XX after erase gap
command.
3
End status timeout on erase gap command.
3
End statue timeout on rewind command.
3
Busy status still on after rewind complete.
3
BOT not on after rewind complete.
3
Sense byte 11 not equal to 011 OOXXX after rewind
command.
3
Sense byte 12 not equal to XXXX01 XX after rewind
command.
3
Cover/reel latch interlock interrupt check bit on.
3
BOT/EQT LED failure check bit on.
3
Tape present LED failure check bit on.
3
Reel size LED failure check bit on.
3
PA cable unseated check bit on.
3
Idle tach failure check bit on.
RREN
463D 463E 463F 4641 4642 4643 4644 4645 4646 4647 4648 464C 464D
4651 4652 4653 4654 4655 4656 4657
46FO 46F1 46F2 46F7 46F8 46F9
4701 4704 4706 4708 4709 470C 4711 4712 4713 4714 4715 4716 4717 4718 4719 471A 4718 471C 4710 471E 471F 4721 4722 4723
Format
3 3
3
3 3 3 3 3 3 3 3 3 3
3 3 3 3 3 3 3
3 3 3 3 3 3
Meaning
Match tach failure check bit on. File tach failure check bit on. Idler tach rotation check bit on. Drive control PLA failure check bit on. Servo logic failure check bit on. Servo analog failure check bit on. File AMP saturation check bit on. Mach AMP saturation check bit on. Load check bit on and sequence error bit not on. Not ready due to reset check bit on. Tension check and sequence error bits on. Load check and sequence check bits on. Sequence error bit on without tension check bit or load
check bit on. This condition indicates a false error. Start velocity check. End velocity check. PEID velocity check. Drive response check is on. Drive control parity check. Gap control check is on. Selected Alert is on and a motion error is not indicated in
the sense bytes. The sense bits that were checked are shown in error numbers 37-56. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
Control line timeout on data securing erase command.
3
Control line timeout on test set ready operation.
3
Control line timeout on FSB command.
3
No check end on FSB command.
3
Not capable not on after FSB.
3
Not capable not off.
3
Sense byte 2, bit 6 not reset by check reset.
3
Control line timeout on FSP command.
3
Selected Alert not set by FSF command.
3
Sense byte 2, bit 6 not on.
3
Sense byte 3, bit 5 not on.
3
Sense byte 3, bit 5 not reset by check reset.
3
Sense byte 6, bit 1 is on (PEID check).
3
Sense byte 6, bit 0 not on (write command).
3
Sense byte 6, bit 0 is on (write command).
3
Write status not on after DSE command.
3
Write status not reset by FSB command.
3
Busy not on during DSE operation.
SY27-2521·3
RREN
4724 4725 4726 4727 47A1 47A2 47A3 47FO 47F1 47F2 47F7 47F8 47F9
4801 4804 4806 4808 4809 480C 4811 4813 4814 4816 4818 481A 4818 481C 4810 481E 481F 4820
4821 4822 4823 4824 4826 482E 48A1 48A2 48A6 48A7 48A8 48A9 48AF 48FO 48F1 48F2 48F7 48F8 48F9
Format
3 3 3 3 3 3 3 3 3 3 3 3 3
Meaning
Busy not off after DSE operation. BSB at load point did not cause selected alert. Control line timeout on BSB at load point. Data check set on erase gap. Selected Alert on erase gap operation. Selected Alert and sense byte 12, bits 2 & 3 off. Selected Alert and sense byte 12, bits 2 & 3 not = 00. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
8-second control line timeout on write.
3
Check end after a BSB command.
3
Status error on write 2.
3
Status error on write 3.
3
Status error on write 4.
3
Status error on write 5.
3
8-second control line timeout on read command.
3
Write sense bit is up on a read operation.
3
No data check on check end on read operation.
3
Data check on read operation.
3
10-second ending status timeout on read command.
3
Check end after a write command and write bit in sense
is not on.
3
PEID check on a write command.
3
Envelope check on a write command.
3
MTE, data check, or start read check on write operation.
3
Check end on write and sense byte 6 bits 2-4 = 0.
3
Check end set but not data check.
3
10-second ending status timeout write 1.
3
Selected Alert on write 1 (WAT/ERASE fail).
3
Selected Alert on BSB operation.
3
Selected Alert and read back fail on read operation.
3
Selected Alert and gap control check on write 1.
3
Selected Alert and read back fail on write 1.
3
Sele.cted Alert on write 1.
3
Selected Alert on read operation.
3
Selected Alert when not expected.
3
Check end status received.
3
Bus-in parity error.
3
End status 10-second timeout.
3
Control line timeout or selection error.
3
Unexpected adapter error.
(TA242 Cont)
5-TA·23
RREN
4901 4904 4906 4908 4909 490C 4912 4913 4915 4916 4918 491C 4921 492C 4920 4931 4933 4934 4935
4936 4937 4939 493A
493B 49FO 49F1 49F2 49F7 49F8 49F9
4A01 4A04 4A06 4A08 4A09 4AOC 4A11 4A12 4A16 4A17 4A19 4A23 4A27 4A2B 4A2D 4A33 4A35 4A37 4A39 4AFO
Format
2 1 1 3 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3
3 3 3 3
3 3 3 3 3 3 3
Meaning
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CH 10 machine check. Solid 1/0 machine check. Control line timeout on set long gap operation. Selected Alert after reset long gap. Long gap sense bit did not reset. Low-Speed sense bit not on. Selected .Alert on set long gap command. Control line timeout on set long gap operation. Long gap sense bit did not turn on. Selected Alert on read block command. 8-second ending status timeout. Selected Alert on read block command. Check end after a read block command. Ending status timeout on read block command. Data compare error on last record read. Adapter status in message is replaced by expected and actual data. Long gap mode not reset by RLG command. Selected Alert on read command. Check end while trying to read the hex 33 record. After reading 12 records, the tape was not in position to read the hex 33 record. Long gap mode did not reset. 8-second ending status timeout. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
Low speed did not set.
3
Long gap did not reset.
3
Selected Alert after backspace block.
3
Selected Alert on backspace operation. Not at load point.
3
Check end on backspace block.
3
Selected Alert on read 1.
3
Check end after read 1.
3
Selected Alert on read 2.
3
Check end on read 2.
4
Read compare error on read 2.
3
Selected Alert on read 3.
3
Check end on read 3.
4
Read compare error on record 3.
3
Selected Alert when not expected.
SY27-2521-3
5-TA-24
RREN
4AF1 4AF2 4AF7 4AF8 4AF9
4C01 4C04 4C06 4C08 4C09 4COC 4C11 4C12 4C13 4C14 4C15 4C16 4C17
4C18
4C19 4C1A 4C1B 4C1C
4C1D
4C1E
4C1F 4C21 4CFO 4CF1 4CF2 4CF7 4CF8 4CF9
4001 4004 4006 4008 4009 400C 4011 4012 4013 4014 4015 4016 4017
Format
3 3 3 3 3
Meaning
Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid machine check.
3
Control line timeout on set high-speed operation.
3
Selected Alert on set high-speed command.
3
Ending status timeout on set high-speed command.
3
Busy status on after set high-speed command.
3
Low-speed status on after set high-speed command.
3
Positioning status after set high-speed command.
3
Sense byte 11 not equal to 00100XXX after set high-
speed command.
3
Sense byte 12 not equal to XXXX01 XX after set high-
speed command.
3
OP Complete not reset by check reset.
3
Selected Alert on ERG in high-speed command.
3
Ending status timeout on ERG operation.
3
Sense byte 11 not equal to 10100XXX after erase gap
command.
3
Sense byte 12 not equal to XXXX01 XX after erase gap
command.
3
Sense byte 11 not equal to 001 OOXXX after rewind
command.
3
Low-speed status not on after set low-speed command.
3
Bus-in parity error on set high-speed operation.
3
Selected Alert when not expected.
3
,Check end status received.
3
Bus-in parity error.
3
End status 10-second ti me out.
3
Control line timeout or selection error.
3
Unexpected adapter error.
2
Unexpected machine error.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Selected Alert on first write command.
3
Check end on first write command.
3
Selected Alert reading record 1.
3
Check end on reading record 1.
4
Compare error in record 1.
3
Selected alert reading record 2.
3
Check end on reading record 2.
RREN
4018 4019 401A 401B 401C 4010 401E 401F 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 403A 4038 403C 4030 403E 403F 40FO 40F1 40F2 40F7 40F8 40F9
4E01 4E04 4E06 4E08 4E09 4EOC 4E11 4E12 4E13 4E14 4E15 4E16
4E18 4E19 4E1A 4E1B 4E1C 4E1D 4E1F 4E21
Format
4
3 3 4 3 3 4 3 3 4 3 3 4 3 3 4 3 3 4 4 3 3 4 3 3 3 3 3 3 3 3
Meaning
Compare error in record 2. Selected Alert reading record 3. Check end on reading record 3. Compare error in record 3. Selected Alert reading record 4. Check end on reading record 4. Compare error in record 4. Selected Alert reading record 5. Check end on reading record 5. Compare error in record 5. Selected Alert reading record 6. Check end on reading record 6. Compare error in record 6. Selected Alert reading record 7. Check end on reading record 7. Compare error in record 7. Selected Alert reading record 8. Check end on reading record 8. Compare error in record 10. Compare error in record 8. Selected Alert reading record 9. Check end on reading record 9. Compare error in record 9. Selected Alert reading record 10. Check end on reading record 10. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control Iine timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Control line timeout on write tape mark (WTM) operation.
3
Ending status timeout on WTM command.
3
Check end with PEID CK or WTM command.
3
Check end with WTM CK on WTM command.
3
Check end with check byte 6, bit 0 off on WTM operation.
3
Check end with check byte 6, bit 0 on during WTM
operation.
3
BSB over TM failed to set check end.
3
TM detected bit not on.
3
Check end not set by BSB command.
3
TM detected bit not on.
3
TM detected not reset by check reset.
3
Control line timeout on BSF command.
3
Op Complete not on after BSF command.
3
Busy and Op Complete on after BSF command.
SV27-2521-3
RREN
4E22 4E23 4EA1 4EFO 4EF1 4EF2 4EF7 4EF8 4EF9
4F01 4F04 4F06 4F08 4F09 4FOC 4F11 4F12 4F13 4F14 4F15 4F16 4FA1 4FFO 4FF1 4FF2 4FF7 4FF8 4FF9
5001 5004 5006 5008 5009 500C 5011 5012 5013 5014 5015 5016 50FO 50F1 50F2 50F7 50F8 50F9
5201 5204 5206 5208
Format
3 3 3 3 3 3 3 3 3
Meaning
Op Complete not reset by check reset. No normal end and data check not set. Selected Alert during a write tape mark command. Selected Alert when not expected. Check end status received. Bus·in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Check end received writing record 1.
3
Check end received-not a write problem.
3
No normal end while writing record 2.
3
No normal end while writing record 3.
3
No normal end while writing record 4.
3
No normal end while writing record 5.
3
Selected Alert on a write operation-record 1.
3
Selected Alert when not expected.
3
Check end status received.
3
Bus-in parity error.
3
End status 10-second timeout
3
Control line timeout or selection error.
3
Unexpected adapter error
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Unable to write tape.
3
No normal end on read with correct count.
3
No count error on read long.
3
No count error on read long.
3
Count error on read long with SLI bit on.
3
Count error on read short with SLI bit on.
3
Selected Alert when not expected.
3
Check end status received.
3
Bus-in parity error.
3
End status 10-second timeout.
3
Control line timeout or selection error.
3
Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
(TA242 Cont)
5-TA-25
RREN
5209 520C 5211 5212 5213 5214 5215 5216 52A1 52FO 52F1 52F2 52F7 52F8 52F9
5301 5304 5306 5308 5309 530C 5311 5312 5313 5314 5315 5316 5317 5318 5319 531A 5318 531C 5310 531E 531F 53A1 53FO 53F1 53F2 53F7 53F8 53F9
5401 5404 5406 5408 5409 540C 5416 5417 5418
Format
1 2 3 3 3 3 3 3 3 3 3 3 3 3 3
Meaning
CHIO machine check.
Solid 1/0 machine check.
Write errors-could not write tape. Check end not on after BSB operation. TM detected not set after BSB operation. Check end not set on read. TM detected not set after read operation. Normal end off and data check off. Selected Alert on write Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Unable to write pattern 1 after 5 retries.
3
Unable to write pattern 2 after 5 retries.
3
Unable to write pattern 3 after 5 retries.
3
Unable to write pattern 4 after 5 retries.
3
Unable to write pattern 5 after 5 retries.
3
Status error reading record 1.
4
Compare error record 1.
3
Status error reading record 2.
4
Compare error record 2.
3
Status error reading record 3.
4
Compare error record 3.
3
Status error reading record 4.
4
Compare error record 4.
3
Status error reading record 5.
4
Compare error record 5.
3
Selected Alert reading record 1.
3
Selected Alert when not expected.
3
Check end status received.
3
Bus-in parity error.
3
End status 10-second timeout.
3
Control line timeout or selection error.
3
Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Status error on record 1 read.
3
Read data compare error record 1.
3
Status error on record 2 read.
SY27-2521-3
5-TA-26
RREN
5419 541A 5418 541C 5410 541E 541F 54A1 54FO 54F1 54F2 54F7 54F8 54F9
5501 5504 5506 5508 5509 550C 5511 5512
5513
55A1 55FO 55F1 55F2 55F7 55F8 55F9
5601 5604 5606 5608 5609 560C 5613 5614 56A3 56A4 56FO 56F1 S6F2 56F7 56F8 56F9
Format
4 3 4 3 4 3 4 3 3 3 3 3 3 3
Meaning
Read data compare error record 2. Status error on record 3 read. Read data compare error record 3. Status error on record 4 read. Read data compare error record 4. Status error on record 5 read. Read data compare error record 5. Selected Alert on read record 1. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
Could not write tape. Tried five times.
3
No normal end received after read due to read error or
runaway tape. Either a write/read problem or magne-
tized head or cleaner blade.
4
Data compare error on read. Possible magnetized head
or cleaner blade.
3
Selected Alert while writing.
3
Selected Alert when not expected.
3
Check end status received.
3
Bus-in parity error.
3
End status 10-second timeout.
3
Control Iine timeout or selection error.
3
Unexpected adapter error.
2
Un~xpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
Data record not erased.
3
TM detected not set on FSB command.
3
Selected Alert or tape runaway on PSB command.
3
Selected Alert on write operation.
3
Selected Alert when not expected.
3
Check end status received.
3
Bus-in parity error.
3
End status 10-second timeout.
3
Control line timeout or selection error.
3
Unexpected adapter error.
TA243 Special Requirement Test Messages
. .
The following table lists, for each routine, the error numbers and their meaning for the
special requirement tests. For test message formats, see TA231.
RREN
5A01 5A04 5A06 5A08 5A09 5AOC 5A11 5A12 5A13 5A14 5A15 5A16 5A21 5A22 5A23 5A24 5A25 5A26 5A27 5A28 5A29 5A2A 5A28 5A2C 5A31 5A32 5A33 5A41 5A42 5A43 5A44 5A51 5A52 5A53 5A54 5A55 5A56 5A57 5A58 5A59 5A5A 5A58 5A5C 5A5D 5A5E 5A71 5A72 5A73 5A81
Format
2 1 1 3 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Meaning
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CHIO machine check. Sol id I/0 machine check. Not ready, not at BOT, or not file protected. Check end not set by FSB over TM. Tape mark not detected. Check end not reset by check reset. Normal end not set by FS8 operation. Data check not set. Test pattern delimiter not found by FSB. Test pattern delimiter not found by BSB. Test pattern delimiter not found by FSB. No check end on reading BOR test record. Start data check not set. Data check not set. Start read check not reset. No normal end on FS8. No normal end on BS8. No normal end, no CK end or no TM DET on 8S8. No normal end on FS8. No normal end on FSB. Test pattern delimiter not found by FSB. Pointers on for test record failure. Check end on with no pointers. IBG detect incorrect on FSB. 18G detect incorrect on BS8. No normal end on FS8. MTE and crease not reset by check reset. Check end not set by FSB over TM. Tape mark not detected. No check end on reading creased record. MTE not set by reading creased record. Crease bit not set by reading creased record. Tape position is questionable. TM DET not on reading creased record. TM DET not on after 8SB on creased record.
TM DET not on after FSB on creased record.
Crease with no pointers. Start read check not reset. Write command sense after read command. Pointer P not set by creased record. Data check not set. Test record delimiter not found by FS8. No check end on record with 2 bad tracks. No MTE on record with 2 bad tracks. Test record delimiter not found by FSB.
SY27-2521-3
RREN
5A82 5A83 5A84 5AA1 5AA2 5AA3 5AA4 5AA5 5AA6 5AA7 5AA8 5AA9 5AFO 5AF1 5AF2 5AF7 5AF8 5AF9
5801 5804 5806 5808 5809 5BOC 5811 5812 5813 5814 5815 5816 5817 5818 5819 581A 5818 581C 581D 581E 581F 5821 5822 5823 5824 5825 5826 5827 5828 5829 582A 5828 582C 582D
Format
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Meaning
No check end. No end data check. Data check not set. Check end not set by tape mark. Tape mark not detected. Selected Alert on 1-bit skew record. Check end on 1-bit skew record. Skew check on 1-bit skew record. Data check not set. Data check not set. No check end on 3-bit skew record. No skew error on 3-bit skew record. Selected alert when not expected. Check end status received. Bus-in partity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH I 0 machine check.
2
Solid 1/0 machine check.
3
Test record delimiter not found by FSB.
3
Read fai I pattern 1.
4
Data compare error pattern 1.
3
Read fail pattern 2.
4
Data compare error pattern 2.
3
Read fail pattern 3.
4
Data compare error pattern 3.
3
Read fail pattern 4.
4
Data compare error pattern 4.
3
Read fail pattern 5.
4
Data compare error pattern 5.
3
Read fail pattern 6.
4
Data compare error pattern 6.
3
Read fail pattern 7.
4
Data compare error pattern 7.
3
Read fail pattern 8.
4
Data compare error pattern 8.
3
Read fail pattern 9.
4
Data compare error pattern 9.
3
Read fail pattern 10.
4
Data compare error pattern 10.
3
Read fail pattern 11.
4
Data compare error pattern 11.
3
Read fail pattern 12.
4
Data compare error pattern 12.
3
Read fail pattern 13.
4
Data compare error pattern 13.
3
Read fail pattern 14.
(TA242 Cont, TA243)
5-TA-27
RREN
5B2E 5B31 5B32 5B33 5B34 5B35 5B36 5B37 5B38 5B39 5B3A 5B3B 5B3C 5B3D 5BFO 5BF1 5BF2 5BF7 5BF8 5BF9
6001 6004 6006 6008 6009 600C 6011 6012 6013 6014 6015 6016 6017 6018 6019 601A 6018 601C 6010 601E 6021 6022 6023 6024 6025 6026 6027 6028 6029 602A 602B 602C
Format
4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Meaning
Data compare error pattern 14. Test pattern tape delimiter not found. No select alert on write to protected tape. Write enable error. Write enable error did not reset. Timeout with no EQT or check end. Control line timeout on rewind unload. Ending status timeout on rewind unload. EQT status on early. EQT status did not go off. Busy not on during rewind unload. Ending status timeout on rewind unload. Busy did not drop after Op Complete. Op Complete not reset by check reset. Select alert when not expected. Check end status received. Bus-in partity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
No normal end on write 1 at low speed.
3
No normal end on write 2 at low speed.
3
No normal end on write 3 at low speed.
3
No normal end on write 4 at low speed.
3
No normal end on write 5 at low speed.
3
No normal end on write 6 at low speed.
3
No normal end on write 7 at low speed.
3
No normal end on write 8 at low speed.
3
No normal end on write 9 at low speed.
3
No normal end on write 10 at low speed.
3
No normal end on write 11 at low speed.
3
No normal end on write 12 at low speed.
3
No normal end on write 13 at low speed.
3
No normal end on write 14 at low speed.
3
No normal end on write 1 at high speed.
3
No normal end on write 2 at high speed.
3
No normal end on write 3 at high speed.
3
No normal end on write 4 at high speed.
3
No normal end on write 5 at high speed.
3
No normal end on write 6 at high speed.
3
No normal end on write 7 at high speed.
3
No normal end on write 8 at high speed.
3
No normal end on write 9 at high speed.
3
No normal end on write 10 at high speed.
3
No normal end on write 11 at high speed.
3
No normal end on write 12 at high speed.
SY27-2521-3
RREN
602D 602E 60FO 60F1 60F2 60F7 60F8 60F9
6101 6104 6106 6108 6109 610C 6111 6112 6113 6114 6115 6116 6117 6118 6119 61 lA 6118 61 lC 6110 611E 6121 6122 6123 6124 6125 6126 6127 6128 6129 612A 6128 612C 612D 612E 6151 6152 6153 6154 6155 6156 6157 6158 6159 615A
Format
3 3 3 3 3 3 3 3
Meaning
No normal end on write 13 at high speed. No normal end on write 14 at high speed. Selected Alert when not expected. Check end status received. Bus-in parity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
No normal end after read record 1.
3
No normal end after read record 2.
3
No normal end after read record 3.
3
No normal end after read record 4.
3
No normal end after read record 5.
3
No normal end after read record 6.
3
No normal end after read record 7.
3
No normal end after read record 8.
3
No normal end after read record 9.
3
No normal end after read record 10.
3
No normal end after read record 11.
3
No normal end after read record 12.
3
No normal end after read record 13.
3
No normal end after read record 14.
3
No normal end after read record 15.
3
No normal end after read record 16.
3
No normal end after read record 17.
3
No normal end after read record 18.
3
No normal end after read record 19.
3
No normal end after read record 20.
3
No normal end after read record 21.
3
No normal end after read record 22.
3
No normal end after read record 23.
3
No normal end after read record 24.
3
No normal end after read record 25.
3
No normal end after read record 26.
3
No normal end after read record 27.
3
No normal end after read record 28.
4
Data compare error on record 1.
4
Data compare error on record 2.
4
Data compare error on record 3.
4
Data compare error on record 4.
4
Data compare error on record 5.
4
Data compare error on record 6.
4
Data compare error on record 7.
4
Data compare error on record 8.
4
Data compare error on record 9.
4
Data compare error on record 10.
5-TA-28 I
RREN
6158 615C 615D 615E 6161 6162 6163 6164 6165 6166 6167 6168 6169 616A 6168 616C 616D 616E 6191
6192
61FO 61F1 61 F2 61F7 61F8 61F9
6201 6204 6206 6208 6209 620C 6211
6301 6304 6306 6308 6309 630C 6313 6314 6315 6316 6317 6318 6319 631A 6318 631C 6310
Format
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3
3
3 3 3 3 3 3
2 1 1 3 1 2 3
2 1 1 3 1 2 3 3 3 3 3 3 3 3 3 3 3
Meaning
Data compare error on record 11. Data compare error on record 12. Data compare error on record 13. Data compare error on record 14. Data compare error on record 15. Data compare error on record 16. Data compare error on record 17. Data compare error on record 18. Data compare error on record 19. Data compare error on record 20. Data compare error on record 21. Data compare error on record 22. Data compare error on record 23. Data compare error on record 24. Data compare error on record 25. Data compare error on record 26. Data compare error on record 27. Data compare error on record 28. Tape mark detected not on after FSB operation over a tape
mark. Tape mark detected not on after BSB operation over a tape
mark. Selected Alert when not expected. Check end status received. Bus-in partity error. End status 10-second timeout. Control line timeout or selection error. Unexpected adapter error.
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CH 10 machine cneck. Solid 1/0 machine check. Normal routine completion.
Unexpected machine check. Unexpected 1/0 interruption. Interruption always active. Open adapter failure. CH 10 machine check. Solid 1/0 machine check. Cover/reel latch interlock is open. Drive state is 'idle'. Drive state is 'take up slack'. Drive state is 'sample radius'. Drive state is 'enable servo'. Drive state is 'rewind FWD space'. Drive state is 'rewind'. Drive state is 'rewind stop'. Drive state is 'high-speed load point' and low speed is on. Drive state is 'space to low-speed load point'. Drive state is 'not low-speed load point' and the drive is in
low-speed mode.
SV27-2521-3
RREN 631E 631F 6321 6322
6323 6324 6325
6326
6328
6329 632A 6328 632C
632D 632E 632F
6331
6334 6335 6336 6337 6338 6339 633A 633B 633C 6341 6342 6343 6344 6345 6346
6347 6348 634B 634C 634D
634E
Format 3 3 3 3
3 3 3
3
3
3 3 3 3
3 3 3
3
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
3 3 3 3 3
3
Meaning
Drive state is 'low-speed load point' and busy. Drive state is 'low-speed load point' and BOT is not on. Drive state is 'low-speed load point' and EQT is on. Drive state is 'low-speed load point' and Op Complete is not
on. This error occurs if drive was reset after pressing LOAD REWIND or if LOAD REWIND is not pressed each time this routine is run. Drive state is 'low-speed load point' and positioning. Drive state is 'low-speed load point' and stoplock is not on. Drive state is 'low-speed load point' and READY light is not on. Drive state is 'low-speed load point' and all status appears correct. The READY light should be on; if not, check the READY light and circuit. Drive state is not 'high-speed load point' and the drive is in high-speed mode. Drive state is 'high-speed load point' and busy. Drive state is 'high-speed load point' and BOT is not on. Drive state is 'high-speed load point' and EQT is on. Drive state is 'high-speed load point' and Op Complete is not on. This condition occurs if RESET is pressed after load rewind or if LOAD REWIND is not pressed each time this routine is run. Drive state is 'high-speed load point' and positioning. Drive state is 'high-speed load point' and stoplock is not on. Drive state is 'high-speed load point' and READY light is not on. Drive state is 'high-speed load point' and the READY light should be on; if it is not, then check the READY light and circuit. Cover/reel latch interrupt is on. BOT/EQT LED failure. Tape present LED failure. Reel size LED failure. PA cable unseated. Idler tach failure. Machine tach failure. File tach failure. Idler tach rotation check. Drive control PLA failure. Servo logic failure. Servo analog failure. File amp saturation. Machine amp saturation. Load check is on and sequence check is not on. This condition indicates a false error. Not ready due to reset. Selected Alert is on but there are not motion checks. Tension check is on and drive state is rewind Load check and sequence error are on. Sequence check is on without tension or load check. This condition indicates a false error. Tension check is on and drive state is not rewind.
(TA243 Cont)
5-TA-29
SV27-2521-3
5-TA-30
RREN
6351 6352 6361 6362 63FO 63F1 63F2 63F7 63F8 63F9
6401 6404 6406 6408 6409 640C 6411 6412
6501 6504 6506 6508 6509 650C 6511 6512 6601 6604 6606 6608 6609 660C 6611 6612
6701 6704 6706 6708 6709 670C 6711 6712 6713 6714
6A01 6A04 6A06 6A08 6A09 6AOC 6A11 6AA2
Format
3 3 4 4 3 3 3 3 3 3
3 1 1 3 1 2 3 3
2 1 1 3 1 2 3 3 2 1 1 3 1 2 3 3
2 1 1 3 1 2 3 3
3
3
Meaning
Drive control parity check.
Drive response check is on. Write current failure. Erase current failure. Selected Alert when not expected. Check end status received. Bus·in parity error. End status 10·second timeout. Control line timeout or selection error. Unexpected adapter error.
Unexpected machine check.
Unexpected 1/0 interruption.
Interruption always active. Open adapter failure.
CH 10 machine check. Solid 1/0 machine check.
Selected alert from write operation. Check end on write operation.
Unexpected machine check.
Unexpected 1/0 interruption.
Interruption always active. Open adapter failure. CHIO machine check.
Solid 1/0 machine check.
Selected Alert from write operation. Check end on write operation. Unexpected machine check.
Unexpected 1/0 interruption.
Interruption always active. Open adapter failure.
CH 10 machine check. Solid 1/0 machine check.
Selected Alert from read operation. Check end on read operation.
Unexpected machine check.
Un~xpected 1/0 interruption.
Interruption always active. Open adapter failure. CHIO machine check.
Solid 1/0 machine check.
Positioning bit not turned on in 15 ms. Gap is too short-less than 1.4 cm (0.55 inch). Gap is too long-greater than 1.65 cm (0.65 inch). Bad status after read operation.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Not capable not on for first FSB. Check for proper skew tape.
3
Tape motion was terminated by select alert condition other
than tape running out.
RREN 6AFF
6801 6804 6806 6809 680C 6811
6C01 6C04 6C06 6COS 6C09 6COC 6CFF
6001 6004 6006 600S 6009 6DOC
Format 3
Meaning Normal test end (tape ran out).
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
1
CH 10 machine check.
2
Solid 1/0 machine check.
3
Normal error number that is displayed with the sense
information.
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
3
Normal message, not an error. (The symptom code is the
last 2 bytes of the message; see Symptom Code table below.)
2
Unexpected machine check.
1
Unexpected 1/0 interruption.
1
Interruption always active.
3
Open adapter failure.
1
CHIO machine check.
2
Solid 1/0 machine check.
Symptom Codes (SCs) Generated by Routine 6C Symptom
code
AXXX
8001 8002 8004 BOOS 8010 8020 B040 BOSO B120 B140 B180
coos
C010 C020 C040
COBO
C08J C110 C120 C140 C180 C208 C210
Meaning
Adapter detected error Sync out check Sequence error Control line tag bus parity error Control line bus-out parity error Formatter read failure Formatter write or control line failure Sense bus parity error Clock failure Check bus parity error Bus-out gated parity error Command register parity error Power amp cable is unseated Reel size LED failure Tape present LED failure BOT/EQT LED failure Cover interrupt with cover closed Cover interrupt with cover open Idler tach rotation check File tach failure Machine tach failure Idler tach failure Machine amp saturation File amp saturation
Symptom Code
C220 C240 C280 C380 C381 C382 C420 C440 C480 C520 C540 C580 C640 C641 C680 D010 D020 D040 D080 D180 D220 D240 D280 E001 E020 E040 E080 E202 E204 E208 E210 E220 E240 E280
E302
E304 E308 E310
E320
E340 E380 E404 E408 E410 E420
E440
E480
Meaning
Servo analog failure Servo logic failure Drive control PLA failure Sequence error and load check Sequence error and tension check Sequence check without tension or load check PE ID velocity check End velocity check Start velocity check Gap control check Drive control parity check Drive response check Not ready due to reset Not ready due to reset and drive ready Load check Read back fail Write-bus parity check Write current fail Erase current fail Read-bus parity check Selected Alert with BOT Write enable error Not capable on forward space fail EQT on write Tape mark detected Not capable Overrun Not capable and write status PEID check during write Write tapemark error MTE on write ENV check on write Start read check on write End data check during write Not capable and write status off Creased No pointer error on non-write MTE on non-write Skew error on non-write Start read check on non-write End data check on non-write PEID check on loop write read (LWR) WTM error on LWR MTEon LWR ENVCKon LWR Start read check on LWR End data check on LWR
The following SCs could not be completely determined:
Symptom Code
FFF1 FFF2 FFF3 FFF4 FFF5 FFF6 FFFF
Meaning
Selected Alert but no select alert sense bits Check end with data check on write Check end with data check on LWR Check end on but data check off Check end with data check on Invalid status and check bytes No Check End and no Selected Alert
TA244 DPCX Online Exerciser Messages
The following table lists, for each routine, the error numbers and their meanings for the DPCX online exerciser. See TA232 for error message formats.
RREN
0101 Ot21 0122 0123
0124 0125 01FO 01F1 01F2 01F3 01F4 0201 0203 0204 0205 0206 0207 0208 0209 020A 0208 020C 020D 020E 020F 0210 0211 0212 02FO 02F1 02F2 02F3 02F4
Meaning
Failure during a rewind Failure during LWR-18 bytes, pattern= 0101010101010101 Failure during LWR-128 bytes, pattern= 2222222222222222 Failure during LWR-256 bytes, pattern= FFFFFFFFFFFFFFFF or pattern= 7F08AAFF5504FFAB Failure during LWR-2048 bytes, pattern= 7F08AAFF6504FFAB Failure during ERG-15 erase gaps Failure on When Ready macro Failure on Open Device macro-programming error Failure on Open Device macro-hardware error Failure on Close Device macro-programming error Failure on Close Device macro-hardware error Failure during a rewind Failure during write-18 bytes, pattern= FFFFFFFFFFFFFFFF Failure during write-128 bytes, pattern= 7F08AAFF5604FFAB Failure during write-256 bytes, pattern= 7F08AAFF5504FFAB Failure during write tape mark Failure during read-18 bytes Failure during forward space block Failure during read-256 bytes Failure during read (tape mark was being read) Failure during backspace file Failure during forward space file Failure during read-128 bytes Failure during backspace block Failure while comparing data-128 bytes Failure while comparing data-266 bytes Failure during write-2048 bytes, pattern= 0123456789ABCDEF Failure during read-2048 bytes Failure on When Ready macro Failure on Open Device macro-programming error Failure on Open Device macro-hardware error Failure on Close Device macro-programming error Failure on Close Device macro-hardware error
SV27-2621-3
(TA243 Cont. TA244)
5-TA-31
TA250 Failure Action Plans
This section provides an action plan for the type of error detected by the TA offline tests. The failing routine number in the test error message indicates the type of error detected (see TA230 for error message format). The types of errors and their action plans are:
Failing Routine (RR)
01,02,03, 09 04-08, 11-15 40-43 44-56
Type of Failure
SCF/tape adapter Tape adapter Tape adapter/tape drive Tape drive
Go to Action Plan
TA251 TA252 TA253 TA254
Other Test Error Messages
PASO XX8C
Type of Failure
Tape adapter failed to initiate a data transfer SCF/tape adapter failure
Go to Action Plan
TA251 TA251
Determine the type of error and go to the appropriate action plan. The action plan provides you with a list of possible failing FR Us to correct the type of failure.
Caution: Turn power off when removing or exchanging cards or cables.
TA251 SCF/Tape Adapter Failure Action Plan A failure was detected either in the SCF bus lines or the tape adapter circuitry associated with them. The operation that failed was not related to operations involving the tape drive. Proceed as follows:
1. Measure the board voltages. See TA440. If there are missing or out-of-tolerance voltages, either go to the PA MIM for an 8809 Model 1A or the 8809 START MAP for an 8809 Model 18.
2. Reseat tape adapter cards and the SCF card. See TA431, TA432, or TA433.
3. Check SCF top card connectors.
4. Check card and board pins for bent or broken pins and connectors.
5. Exchange all possible cards that could cause the failure. For a list of cards related to the test error message, see TA255 (Routine 01, 02, 03, 09, XXBC, or PASO). Run tests after each exchange.
6. If the 8809 is a Model 1A, test all other adapters in the same SCF address group. Exchange any failing adapter.
7. Check the board wiring and correct if necessary. See TA451, TA452, or TA453.
8. If the error was 92BC, return to the ST action plan that sent you here, and continue with the next ST action plan step.
9. Request aid.
SY27-2521-3
5-TA-32
TA252 Tape Adapter Failure Action Plan A failure was detected in the tape adapter circuitry. The operation that failed was not. related to operations involving the tape drive. Proceed as follows:
1. Measure the board voltages (see TA440). If there are missing or out-of-tolerance voltages, either go to the PA MIM for an 8809 Model 1A or to the 8809 START MAP for an 8809 Model 18.
2. Reseat tape adapter cards and top card connectors. Reseat SCF card and top card paddle connectors. Reseat cables from SCF card to 01A board (Model 18 only). See TA431, TA432, or TA433.
3. Model 1A only: Check and reseat paddle cards at Y1 and Z1 (adapter in 8101) or Y3 and Z3 (adapter in 8140).
4. Check card and board pins for bent or broken pins and connectors.
5. Exchange all possible cards that could cause the failure. For a list of cards related to the test error message, see TA255 (Routines 04-08 and 11-15). Run tests after each exchange.
6. Check the board wiring and correct if necessary. See TA451, TA452, or TA453. 7. Request aid.
TA253 Tape Adapter/Tape Drive Failure Action Plan A failure was detected when the tape adapter initiated its first operations involving the tape drive. Proceed as follows:
1. Ensure that the tape drive is clean, has a known good reel of tape mounted, and the drive is ready. Correct if necessary and rerun tests.
2. Reseat tape adapter cards and top card connectors. See TA431, TA432, or TA433. 3. Model 1A only: Check and reseat paddle cards at Y1 and Z1 (adapter in 8101) or
Y3 and Z3 (adapter in 8140). 4. Model 1A only: Check the Bus and Tag cables for bent pins or loose connections.
SeeTA111. 5. Exchange all possible cards that could cause the failure. For a list of cards related
to the test error message, see TA255 (Routines 40-43). Run tests after each exchange.
6. Check the board wiring and correct if necessary. See TA451, TA452, or TA453. 7. Go to TA254 (Tape Drive Action Plan) and perform that action plan.
TA254 Tape Drive Action Plan A failure was detected while running the device tests. Proceed as follows:
1. Ensure that the tape drive is clean, has a known good reel of tape mounted, and the drive is ready. Correct if necessary and rerun the tests.
2. Check the card list in TA255. If the routine number and error number (RREN) appear in the list, exchange the cards shown one at a time. Run tests after each exchange.
3. Go to the 8809 tape drive MAPs.
TA255 Card Exchange Table
Model 1A
Model 18
Adapter in 8101 Exchange in Order
Adapter in 8140 C2 Board Exchange in Order
Adapter in 8140 02 Board Exchange in Order
Adapter in 8809 Exchange in Order
Error Pattern
1st 2nd 3rd
1st 2nd 3rd
1st 2nd 3rd
1st 2nd 3rd
PASO XXBC PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE PAXE
01XX 02XX 03XX 04XX 05XX 06XX 07XX OBXX 09XX 11XX 12XX 13XX 14XX 15XX 40XX 41XX 42XX 43XX 4420 4701 4725 481A 4935 49F9 4A33 4AF8 5319 5512
A2A2 A2B2 A2A2 A2B2 A2C2 A2C2 A2B2 A2A2 A2C2 A2B2 A2A2 A2B2 A2C2 A2A2 A2B2 A2C2 A2D2 A2B2 A2C2 A2C2 A2B2 A2C2 A2B2 A2C2 A2B2 A2B2 A2A2 A2C2 A2B2 A2A2 A2B2 A2A2 A2B2 A2A2 A2C2 A2B2 A2C2 A2B2 A2C2 A2D2 A2B2 A2C2 A2D2 A2B2 A2D2 A2C2 A2B2 A2D2 A2C2 A2B2 A2C2 A2D2 A2B2 A2D2 A2C2 A2B2 A2D2 A2C2 A2B2 A2B2 A2C2 A2B2 A2C2 A2A2 A2C2 A2B2 A2A2 A2B2 A2C2 A2B2 A2C2 A2B2 A2C2 A2C2 A2B2
C2A2 C2G2 C2A2 C2G2 C2H2 C2H2 C2G2 C2A2 C2H2 C2G2 C2A2 C2G2 C2H2 C2A2 C2G2 C2H2 C2J2 C2G2 C2H2 C2H2 C2G2 C2H2 C2G2 C2H2 C2G2 C2G2 C2A2 C2H2 C2G2 C2A2 C2G2 C2A2 C2G2 C2A2 C2H2 C2G2 C2H2 C2G2 C2H2 C2J2 C2G2 C2H2 C2J2 C2G2 C2J2 C2H2 C2G2 C2J2 C2H2 C2G2 C2H2 C2J2 C2G2 C2J2 C2H2 C2G2 C2J2 C2H2 C2G2 C2G2 C2H2 C2G2 C2H2 C2A2 C2H2 C2G2 C2A2
C2G2 C2H2 C2G2 C2H2 C2G2 C2H2 C2H2 C2G2
C2A2 D2G2 C2A2 D2G2 D2H2 D2H2 D2G2 C2A2 D2H2 D2G2 C2A2 D2G2 D2H2 C2A2 D2G2 D2H2 D2J2 D2G2 D2H2 D2H2 D2G2 D2H2 D2G2 D2H2 D2G2 D2G2 C2A2 D2H2 D2G2 C2A2 D2G2 C2A2 D2G2 C2A2 D2H2 D2G2 D2H2 D2G2 D2H2 D2J2 D2G2 D2H2 D2J2 D2G2 D2J2 D2H2 D2G2 D2J2 D2H2 D2G2 D2H2 D2J2 D2G2 D2J2 D2H2 D2G2 D2J2 D2H2 D2G2 D2G2 D2H2 D2G2 D2H2 C2A2 D2H2 D2G2 C2A2 D2G2 D2H2 D2G2 D2H2 D2G2 D2H2 D2H2 D2G2
SCF A1D2 SCF A1D2 A1E2 A1E2 A1D2 SCF A1E2 A1D2 SCF A1D2 A1E2 SCF A1D2 A1E2 A1D2 A1E2 A1E2 A1D2 A1E2 A1D2 A1E2 A1D2 A1D2 SCF A1E2 A1D2 SCF A1D2 SCF A1D2 SCF A1E2 A1D2 A1E2 A1D2 A1E2 A1D2 A1E2 A102 A1E2 A102 A1E2 A102 A1E2 A102 A1E2 A1D2 A1E2 A1D2 A2D2 A1E2 A1D2 A1E2 SCF A1E2 A102 SCF A1D2 A1E2 A1D2 A1E2 A1D2 A1E2 A1E2 A1D2
*The Local/Remote power switch should be in Local, and the 8809 should be powered off when exchanging cards.
SY27-2521-3
(TA250-TA255)
5-TA-33
SY27-2621·3 This page intentionally left blank.
5-TA-34
TA300 Intermittent Failure Repair Strategy
TA310 Adapter-Unique Intermittent Repair Strategy
System-detected or customer-reported failures are considered intermittent if they cannot be readily reproduced by the DLS tests (see 8809 Maintenance Manual for definition) or other maintenance manual-instructed action by the service representative.
Looping the tests provides the most effective method of detection for an intermittent failure. Should a failure not occur, then you must use the error log.
TA311 Looping with MAP Interaction to Determine Intermittent Failures
The DLS tests may be looped using the MAP during basic checkout (MAP selection A). Each complete test sequence takes 7 minutes, and, if there are no errors on the first pass, the tests loop continuously. The MD displays 'PAFO TEST LOOPING' until the test either detects an error, or you terminate the test by entering 'F' at the MD.
If an error is detected while looping, the MAP directs repairs of the failure in the same manner as a solid failure. Once you perform a repair action, the MAP loops the tests to verify the repair.
If the tests do not detect an error while looping, you should terminate the tests. The MAP directs you to run either ELDA (DPPX systems) or SYSLERR (DPCX systems) and obtain the symptom code for the customer-reported failure. You then reenter the MAP at Entry Point D (Test Symptom Code) and are directed to the appropriate FRU exchange list.
TA312 Using the System Error Log to Determine Intermittent Failures
To obtain this log for DPPX systems, you use the ELDA utility, and to obtain it for sys· terns operating under DPCX, you use the SYSLER R utility and obtain a symptom code using the sense data collected at the time of failure.
In general, the procedure is to replace the highest probability FRU indexed by the symp· tom code. Once the FRU has been exchanged, run the DLS tests or the DPCX Online Exerciser. Assuming no detected failures, record the FRU in the FRU Exchange History Table, which is located in the 8809 Maintenance Manual MAP reference pages, and return the machine to the customer.
On subsequent calls for the same failure, exchange the next lower probability FRUs, one at a time, using the above procedure. When the list of F RUs is exhausted and the intermittent failure persists, go to TA250 and perform all action plans.
The action plans direct you to some low probability FRUs of a more general nature, but still related to the failure being diagnosed. If the failure still persists, you are directed to collect pertinent information before calling the support level.
TA313 Using the Free-lance Utility to Determine Intermittent Failures
The TA test can be looped by using the Free-Lance Utility contained on the MD diskettes. A complete test sequence occurs in 7 minutes. To invoke the TA tests, at the SOBC message enter PA DAB, at the 81 BC message enter 11 B (see TA211 ). The test loops continuously until either detecting an error or you terminate the test by entering an 'F' at the MD.
If an error occurs while looping, the MD displays the test error message (see TA231 ). Record this message and use the Failure Action Plans section (TA250) to isolate and repair the failure. Once a repair action has been taken, loop the test for at least 15 min· utes to verify the repair.
TA320 Error-Log Information Needed for the Tape Adapter
TA321 DPPX TA322DPCX
l;rror-log information may be obtained in several ways, depending upon which system the customer uses and what type of information you want. The following lists the different methods of obtaining the information and briefly describes the information.
· DISPLAY.ERR LOG Command-Outputs either all or selected records in the error log, depending upon the options selected. The output is in detailed form.
· ELSA Utility-Outputs either all or selected records in the error log, depending upon the options selected. The output is in summary form.
· ELDA Utility-Outputs all records pertaining to the tape drive and the tape adapter. The records are in summary form and the user can select the type of information to be summarized. The output also includes the symptom code (SC).
· SYS LE RR Utility-Outputs all or selected records in the error log (called the Condition/Incident Log), depending upon the options selected. The output is in detailed form. In addition, if the record is a Type-5 tape unit or tape adapter record the utility generates the outputs the symptom code for the error. See TA332 for Type-5 record format.
· SYSLTSO Utility-Outputs the summary of all temporary errors occurring in the tape subsystem.
Note: Chapter 2 contains the invocation procedures for each of these methods, as well as additional information aboutSYSL TSO and ELDA.
SY27-2521-3
(TA300-TA322)
5-TA-35
.TA330 Error Log Formats and Meanings Used for the Tape Adapter
The format of the error log depends upon whether the customer is using DPPX or DPCX.
TA331 DPPX Error Log Formats and Meanings The following conditions generate an entry in the DPPX error log:
· Permanent errors. Figure TA331·2 shows the format of this record.
· Temporary errors. Temporary errors are not logged for each event but are counted by threshold counters in the program. See Figure TA334-1 for the Tape Statistical Data (TSO) threshold counters. When a threshold counter reaches a predetermined value, the Error Record Indicator (ERi) bit turns on in the extended status, and the data is logged. The record format is the same as for permanent errors.
· A volume is mounted or dismounted. Figure TA331·1 shows the contents of the entry.
DPPX Error Log Display
The DISPLAY.ER RLOG command prints the detailed error log data. Figure TA331-1 shows the Mount/Dismount display, and Figure TA331·2 shows the Error Record display.
The ELSA utility prints summary error data. Error data may also be printed using the Error Log Data Analysis (ELDA) report (see Chapter 2, CP730).
CLASS 04 SUBCLASS 02 OPTION
xx
DATE VY.DOD TIME HH:MM:SS
PA XX SCA XXXX OT T
VOLID XXXXXX
M/D X
Note: uX" indicates the field size in bytes, where two Xs equals one byte.
Figure TA331-1. OPPX Error Log Display for Mount/Dismount Records
xx CLASS 05 SUBCLASS 01 OPTION
DATE VY.DOD TIME HH:MM:SS
PA XX SCA XXXX DT T
CRC XX COMPSTAT XX ARC XX
DATA XXXXXXXX RES XXXX CNT XXXX
IOEP XXXXXXXX ADWA XXXXXXXX
CA XX CPR XX FRWA XXXXXXXX
RES XXXXXXXX
BCLE xx xx xxxx xxxxxxxx
EXTENDED DATA
D01 xxxx D02 xxxx 005 xxxx 006 xx xx 009 xxxx 010 xx xx 013 xxxx 014 xx xx 017 xxxx 018 xxxx 021 xxxx 022 xx xx 025 xxxx 026 xx xx 029 xxxx 030 xxxx 033 xxxx 034 xx xx 037 xxxx 038 xxxx 041 xx xx 042 xx xx 045 xx xx 046 xx xx
D03 xxxx 007 xx xx 011 xxxx 015 xxxx 019 xxxx 023 xxxx 027 xxxx 031 xxxx 035 xxxx 039 xxxx 043 xxxx 047 xxxx
004 xxxx 008 xxxx 012 xxxx 016 xx xx 020 xxxx 024 xxxx 028 xxxx 032 xxxx 036 xxxx 040 xxxx 044 xx xx
Note: "X" indicates the field size in bytes, where two Xs equals one byte.
Figure TA331-2. DPPX Error Log Display for Error Records (Format 1)
SY27-2521-3 Record Meaning
5-TA-36
The following describes the meaning of the DPPX error log fields used to analyze tape hardware errors:
CLASS SUBCLASS DATE TIME PA
SCA DT CRC COMPSTAT ARC DATA RES CNT IOEP ADWA CA CPR FRWA RES BCLE
VOLID M/D
4 = Mount/dismount
5 Hardware 1/0 error
1 = Hardware 1/0 error record 2 = Mount/dismount record YY.DDD = The year and Julian date of the log output
HH :MM :SS = The hour/minute/second of the log output
XX = Tape adapter physical address 5E = Adapter in 8140 Model BXX 73 = Adapter in Model 1B tape drive 93 = Adapter in first 8101 A3 = Adapter in second 8101 B3 = Adapter in third 8101 C3 = Adapter in fourth 8101 XXXX = Indicates the tape drive address T = Tape device type
XX Function Module Request Code (see TA333)
XX = Completion status (see TA333) XX = Adapter Return Code (see TA333) XXXXXXXX = Data address XXXX = Not used XXXX = Byte count XXXXXXXX = 1/0 interrupt entry point XXXXXXXX = Adapter work area address XX = Channel address XX = Channel pointer register XXXXXXXX = Function request work area XXXXXXXX = Not used 8 bytes = Buffer control Iist element Byte 0 = Flag byte
Bits 0-2 Not used
Bit 3 Program request interrupt
Bits 4, 5 Incorrect data length suppression
Bit 6 Chain data
Bit 7 Chain record
Byte 1 Command byte (see TA333)
Bytes 2, 3 = Count = Number of bytes transmitted Bytes 4-7 = Address or data XXXXXX = Volume ID x = M/Mount
D/Dismount
EXTENDED DATA
D01, D02 4 bytes = Not used
D03
= XXXX = First byte = Extended completion status
Bit 0 = Not used
Bit 1 = Error record indicator
Bit 2 = Program request interrupt
Bit 3 = Not used
Bit 4 = Not used
Bit 5 = Preemptive request complete
Bit 6 = Not used
Bit 7 = Not used
= Second byte = Not used
D04
XXXX = Error record displacement
D05,D06 4 bytes = BCLE address
007
XXXX = Residual count
008
XXXX = Not used
009
XXXX = DPPX/CAC control byte
010, 011 4 bytes = Reserved
012
XXXX = Count (size of FCB build area)
013, 014 4 bytes = Address of FCB build area
015-018 8 bytes = CAC work area
019-024 12 bytes = Reserved
025-036 Tape Statistical Data (TSO) counters (see TA334)
037
XXXX = First byte
Tape sense byte 0 (see TA233)
Second byte = Tape sense byte 1 (see TA233)
038
XXXX = First byte
Tape sense byte 2 (see TA233)
Second byte = Tape sense byte 3 (see TA233)
039
XXXX = First byte
Tape sense byte 4 (see TA233)
Second byte = Tape sense byte 5 (see TA233)
040
XXXX = First byte
Tape sense byte 6 (see TA233)
Second byte = Tape sense byte 7 (see TA233)
041
XXXX= First byte
Tape sense byte 8 (see TA233)
Second byte = Tape sense byte 9 (see TA233)
042
XXXX= First byte
Tape sense byte 10 (see TA233)
Second byte = Tape sense byte 11 (see TA233)
043
XXXX= First byte
Tape sense byte 12 (see TA233)
Second byte = Tape sense byte 13 (see TA233)
044
XXXX= First byte
Tape sense byte 14 (see TA233)
Second byte = Tape sense byte 15 (see TA233)
045
XXXX= First byte
Adapter status extended (see TA233)
Second byte = Adapter status (see TA233)
046
XXXX= First byte
Device address
Second byte = PIO command (see TA333)
D47
XXXX= First byte
Tag bus
Second byte = Bus Out
Note: See IBM 8809 Magnetic Tape Unit Description, Form GA26-1659, for detailed explanation of D47 field.
SY27-2521-3
(TA330, TA331)
5-TA-37
TA332 DPCX Condition/Incident Log Formats and Meanings
Temporary Errors
Temporary errors are not logged for each event but are counted by threshold counters in the program. When a threshold counter reaches a predetermined value, the error record indicator (ERi) bit turns on in the extended status, and the Tape Statistical Data (TSO) counters in processor storage save the data. When a TSO counter overflows or a tape is dismounted, a history file on disk storage (Data Set 24) is updated. The data is stored by Volume ID and Tape Unit LA. The history file has the ability to hold 80 volume entries and 4 tape unit entries. Refer to Chapter 2, CP853, for details.
Permanent Errors
The 8100 enters selected system events into an error log (Condition/Incident Log), contained on the system-resident disk storage drive (see Figure TA332-1 ). An incident type and a sequence number identify each event. Sequence numbers are assigned in order of occurrence, sequentially from 1 to 4095. The log wraps around at 4095, starting over at 1, and any previous recordings are overwritten.
Note: Some error log records may be lost after an 8100 power-off sequence if (1) the Control Operator did not perform a normal termination of system operations prior to power-off, or (2) you did not initalize die 8100 before power-off.
Three types of error records are used by the tape adapter and tape drive:
· Type-2 records, associated with system check failures (Figure TA332-1 ). · Type-4 records, associated with various system events such as system start, system
abend, and system shutdown (Figure TA332-2). · Type-5 records, associated with tape adapter and tape drive failures (Figure TA332-3).
The log typically can be used for intermittent failure analysis when the various tests do not detect a failure.
SY27-2521-3
Error Data Display, Temporary Errors The SYSLTSO utility permits you to display or print the temporary error counters (tape statistical data or TSO) from the history file. See Chapter 2, CP853, for invocation procedures and allowable options. Supported devices are the same as for SYSLERR.
You can display the TSO counters in two different formats: detailed or summary. The detailed format shows all the counters sorted by tape unit LA and the major counters sorted by Volume ID and LA. The summary format shows the major counters summarized in percentages sorted by Volume ID and LA. Refer to Chapter 2, CP853, for details.
Error Data Display, Permanent Records The SYSLERR utility displays or prints permanent errors. See Chapter 2, CP830, for invocation procedures and allowable options.
During the SYSLER R processing of a Type-5 record, a call is made to a subroutine which generates a Symptom Code (SC) from the 8809 sense and status bytes, the tape adapter status bytes, and the Tag Bus Out. This symptom code displays in the 021 field of the record.
( 1)
(2)
2-TYPE 1·REC sea-xxxx
(3)
(4)
(5)
NA-XX 'PA-XX LA-XX
(6)
(7)
(8)
021-XXXX XXXX (9)
LVL-XX (10)
C-FR·XX ( 11)
022-XXXX XXXX (12)
MC-XX (13)
S·FR·XX (14)
023-XXXX
024-XXXX
025-XXXX
Figura TA332·1. DPCX Typa-2 System Check Record Display
5-TA-38
(1) 4-TYPE (4) 001-XX
(2)
(3)
1-REC SEO-XXXX SYS-CONO-XX
(5)
(6)
(7)
(8)
002-XX 003-XX 004-XX 005-XX
Figure TA332-2. DPCX Type-4 System Condition Record Display
(1) 5-TYPE
(2)
I-REC SEO-XXX
(5)
(6)
01-XX 02-XX
(9)
(10)
05-XX 06-XX
(7) 03-XX
07-XX
(3) PA-XX
(8) 04-XX
08-XX
(4) LA-XX
09-XXXXXX (11) 010-XXXX 011-XXXX
012-XXXX
013-XXXX
016-XXXX (13) 019-XXXX
014-XXXX
017-XXXX (14) 020-XXXX
015-XXXX (12)
018-XXXX (15) 021-XXXX
022-XXXX 023-XXXX 024-XXXX
025-XXXX 026-XXXX 027-XXXX
028-XXXX 029-XXXX 030-XXXX
Figure TA332-3. DPCX Type-5 Variable Data Record Display
Record Meaning
2-TYPE 4-TYPE 5-TYPE SEQ NA PA
LA
C-FR MC
S-FR
CIL record type 2 (see Figure CP840-2 in Chapter 2 for D21-D25 and LVL description) Cl L record type 4 (see Figure CP840-4 in Chapter 2 for detailed description) CI L record type 5 XXXX = A 4-digit decimal value from 0001 to 4095 that identifies the relative time when the record occurred. XX = Number of applications active when the error occurred XX = Tape adapter physical address 5E Adapter in 8140 Model BXX 73 Adapter in Model 1B tape drive 93 Adapter in first 8101 A3 Adapter in second 8101 83 Adapter in third 8101 C3 Adapter in fourth 8101 XX = Tape drive logical address 04 Tape drive unit 0 05 Tape drive unit 1 06 Tape drive unit 2 07 Tape drive unit 3 XX = Command byte (adapter operation) at time of error (see TA333) XX = System check code 1X Program check 2X Storage parity error 4X 1/0 timeout
ax 1/0 bus parity error
XX = System Function Module Request code (see TA333)
EXTENDED DATA
D1
XX = System Function Module Request code (see TA333)
02
XX = Command byte (adapter operation) at time of error (see TA333)
03
XX = Completion status (see TA333)
04
XX = Tape drive unit physical address
00 Tape drive unit 0
01 Tape drive unit 1
02 Tape drive unit 2
03 Tape drive unit 3
D5
XX = Adapter Return Code (see TA333)
D6
XX = Translated Adapter Return Code (see TA333)
07
XX = Not used (set to 00)
DB
XX = Record type (FF= permanent error)
09
XXXXXX = Volume ID
SY27·2521·3
010
xxxx First byte
Tape sense byte 0 (see TA233)
Second byte = Tape sense byte 1 (see TA233)
011
xxxx First byte
Tape sense byte 2 (see TA233)
Second byte = Tape sense byte 3 (see TA233)
012
xxxx First byte
Tape sense byte 4 (see TA233)
Second byte = Tape sense byte 5 (see TA233)
013
xx xx First byte
Tape sense byte 6 (see TA233)
Second byte = Tape sense byte 7 (see TA233)
014
xxxx First byte
Tape sense byte 8 (see TA233)
Second byte = Tape sense byte 9 (see TA233)
015
xxxx First byte
Tape sense byte 10 (see TA233)
Second byte = Tape sense byte 11 (see TA233)
016
xxxx First byte
Tape sense byte 12 (see TA233)
Second byte = Tape sense byte 13 (see TA233)
017
xxxx First byte
Tape sense byte 14 (see TA233)
Second byte = Tape sense byte 15 (see TA233)
018
xxxx First byte
Adapter status extended (see TA233)
Second byte = Adapter status (see TA233)
019 xxxx First byte
Device address
Device Address
Adr Adr Adr Not Not Not Not Not
Bit Bit Bit Used Used Adr Adr Adr
4
2
1
4
2
1
When an address mismatch occurs during selection, bits 0 through 7 are set to the value returned on the Control Line Bus In during Select Device Tag hex 83.
For all other cases, the drive address is binary encoded and placed in bits 0 to 2 by the Magnetic Tape Attachment; bits 3 to 7 are not used.
Second byte = PIO command (see TA333)
D20
xxxx First byte
Tag bus
Second byte = Bus Out
Note: See IBM 8809 Magnetic Tape Unit Description, Form GA26-1659, for detailed explanation of D20 field
D21 = XXXX = Symptom code
D22 = xxxx = 0
D23-D30 = XXXX = Not used
(TA332)
5·TA·39
TA333 DPPX and DPCX Common Error Log Byte Meanings Certain fields in the DPPX error log and the DPCX condition/incident log, although named differently, have identical bit or byte meanings. The following paragraphs explain these fields and their meanings, as well as list the field names as used by each operating system.
Adapter Return Code (ARC)
You can find the DPPX adapter return code in the ARC field and the DPCX adapter return code in the 05 field. (For DPCX, a Translated Adapter Return Code (TARC) is found in the 06 field.) The following explains their meanings:
ARC (in Hex)
00 02 03 09
OA OB
11 12 20 21 22 29 2B 33 38 39 3A 38 61 62 68 69 6A 75 76 E3 F6
Meaning
Normal completion FRB busy SCA busy SCA not open Adapter not open SCA already open FRB program check BCL program check Indeterminate equipment check Adapter equipment check SCA equipment check Overrun Position lost PEID check DSE failure Read data check Write data check Loop write-to-read File protected (TARC"" 41) SCA not ready (TARC "" 42) Incorrect mode (TARC"" 48) Marker sensor (TARC = 49) Ready recovery (TARC = 4A)
AIO machine check (TARC = 45)
PIO machine check - nonrecursive (TARC = 46) Data unsafe (TARC = 53)
PIO machine check - recursive (TARC = 56)
SY27-2521-3
5-TA-40
Command Byte
You can find the DPPX BCLE command byte in byte 1 of the BCLE field and the DPCX command byte in the 02 field or the C-F R field. The following explains their meanings:
Command Byte (in Hex)
00 01 02 07 93 9B B3 BB C2 03 F2 F3 FB
Meaning
Transfer control Read Write No operation Forward space file Forward space block Backspace file Backspace block Data security erase Rewind unload Write tape mark Rewind Mode set
Completion Status
You can find the DPPX completion status in the COMPSTAT field and the DPCX completion status in the 03 field. The following explains their meanings:
Bit
Meaning
0
Extended status indicator
1
Reenter
2
Reenter FR B indicator
3
Not used
4
Complete
5
Error
6
Exception
7
Attention
Function Module Request Code
You can find the DPPX function module request code in the CRC field and the DPCX function module request code in the S-FR field or 01 field. The following explains their meanings:
Code (in Hex)
00 03 05 07 OD 23 25 35 AB EB
Meaning
Execute Open adapter Read operational statistics No operation Terminate FRB Open SCA Read SCA state Read SCA state when ready Close SCA Terminate adapter
PIO Command
You can find the OPPX PIO command in the second byte of 046 field, and the OPCX PIO command in the second byte of 019 field. The following explains their meanings:
PIO Command (in Hex)
02 04 06 07 08
OA
10 14 16 24 27 2C 2F 30 34 37 38 3A 3C 3F 48 48 50 53 54 57 58 58 5C 5F 61 62 66 69 6C 6E 74 76 7C
Meaning
Adapter reset Reset basic status Set basic status Read status Enable timer End op Set burst length counter Reset status Set status Step counters Read burst length counter Load burst length register Read burst length register Disconnect TAM Set UC SAR counter Read UC SAR counter Test control line parity Wrap Set control line SAR counter Read control line SAR counter Set segment count Read segment count Write command pointer number Read command pointer number Set extended address register Read extended address register Write data pointer number Read data pointer number Set basic address register Read basic address register Read control lines bus in Write buffer Execute poll sequence Read buffer Execute selection sequence Execute immediate sequence Execute immediate disconnect sequence Execute external without data sequence Execute FCB list
TA334 Tape Statistical Data (TSD) Counters You can find Tape Statistical Data (TSO) counter information in the OPPX error log 025-036 fields; for OPCX, run the SYSLTSO utility (see CP853 in Chapter 2) to obtain TSO counter information. Figure TA334-1 shows the 8809 TSO counters.
Counter Size in Bytes
DPPX Error Log Byte
Counter Name
Set by
Sense Byte
Sense Bit
2
D32
2
D35
2
D36
C01-Start I /0 Count C02-Write Skips C03-Read Retry
Determined by FDM Determined by FDM Determined by FDM
1
D31 , ti rst byte
*C04-Temp Read Errors
1
031 , second byte *C05-Temp Write Errors
1
0 (Byte 6 Bit 0 =0)
1
0 (Byte 6 Bit 0 = 1)
1
034, first byte
COS-Tape Adapter Parity Errors 16
2
1
034, second byte
C07-0verrun
2
0
1
D25, first byte
COS-Multi-Track Errors
6
2
1
D25, second byte
C09-End Data Check
6
3
1
D26, first bYte
C10-Start Read Check
1
026, second byte
C11-Read Back Failure
6
4
6
5 (Bit 0 = 1)
1
027, first byte
C12-Envelope Check
6
6
1
D27, second byte
C13-No Pointer Error
1
D28, first byte
C14-Crease Error
1
028, second byte
C15-Skew Error
6
1 (Bit 0 = 0)
6
5 (Bit 0 =0)
6
7 (Bit 0 =0)
1
029, first byte
C16-Track 4 Error
5
4
1
029, second byte
C17-Track 5 Error
5
5
1
030, first byte
C18-Track P Error
4
6
1
030, second byte *C19-Velocity Check
9
0, 1, or 2
1
D33, second byte *C20-Read Bus Parity Check
4
1
*THRESHOLDS:
Temporary Read Errors Temporary Write Errors Read Bus Parity Checks Velocity Checks All others
16 16 16 8 Full Count
Figure TA334-1. 8809 Tape Statistical Data (TSO) Counters
SY27-2521-3
(TA333, TA334)
5-TA-41
TA340 How to Use the Error Log to Determine Tape Adapter Failures
TA341 DPPX Error Log
The procedure for examining the error log depends upon whether the customer is using DPPX or DPCX. For DPPX, see TA341; for DPCX, see TA342.
Run ELOA and obtain the Symptom Code from the last error occurring on the suspected tape drive. You can then either use the TA MAP by selecting entry point D 'Test Symptom Code' or use the action plan in section TA350.
Chapter 2 contains the invocation µrocedures and outµut format for ELOA.
TA342 DPCX Condition/Incident Log
Run SYSLERR and obtain the Symptom Code (021 field) from the last Type-5 error record occurring on the suspected tape drive. You can then use the TA MAP by selecting entry point D 'Test Symptom Code' or use the action plan in T A350.
Chapter 2 contains the invocation procedures for SYSLERR, and TA332 shows the format of the log records and the location of the Symptom Code (field 021) in the Type-5 record.
TA350 Action Plan to Correct Intermittent Failures
For any Symptom Code format of from BXXX to FXXX that you obtained by running ELDA 01· SYSLERR, go to the tape drive MAP to correct the problem. For any symptom code format of AXXX, or if no symptom code is available, use either TA351, TA352, or TA353 to troubleshoot in the sequence tabulated below.
Caution: Turn power off when removing or exchanging cards or cables. If Model 1B, the Local/Remote power switch should be in Local position.
TA351 8809 Model 1A Intermittent Failure Action Plan (Adapter in 8101)
Probable Causes 1. Incorrect voltages
2. Loose or· defective cables. See TA431 for locations
3. Defectrve tape adapter cards
4. Defective SCF card
Action
Measure A2 board voltages:
02003 = +4.5 to +5.5V de 02811 =+7.7 to +9.3V de 02806 = -4.5 to -5.5V de
lnsj.Ject for loose or defective cables:
1. Y1 to Bus 2. 21 to Tag 3. SCF cable 4. Bus and Tag cables to taµe drrve
(rnsJ.Ject both f~nds)
Exct1ange A2B2, A2C2, an'd A202 carus with new ones.
Exchange card A2A2 with a new one.
Comments For rnissing or out-of-tolerance voltages, go to 8100 PA MIM section Se1~ Note.
See Nott!. Set~ Note.
Note: To ve.·rifv the fix, run the TA tests and loop fora minimum of 15 minutes {each loop takes 7 minutes). If the tests fail, use the TA MAP to find the failure. If the tests do not fail after looping,
return the system to the customer. O/Jtain a new error log after the customer has used the system. If the same error has occurred, replace any cards that were excl1anged and go to the next step in the table. If all steps have been performed and the error persists, request aid.
SY27-2521-3
5-TA-42
TA352 8809 Model 1A Intermittent Failure Action Plan (Adapter in 8140)
Probable Causes
Action
Comments
1. Incorrect voltages
Measure voltages on adapter board (C2 or D2):
J2003 = +4.5 to +5.5V de J2811 = +7.7 to +9.3V de J2B06 = -4.5 to -5.5V de
For missing or out-of-tolerance voltages, go to PA section.
2. Loose or defective cables. See TA432 for locations.
Inspect for loose or defective cables:
1. Y3 to bus 2. Z3 to tag 3. SCF cables (on C2A2 card) 4. Bus and tag cables to tape drive
(inspect both ends).
See Note.
3. Defective tape adapter cards.
Exchange G2, H2, and J2 on adapter board (C2 or 02) with new ones.
See Note.
4. Defective SCF card
Exchange card C2A2 with a new one.
See Note.
Note: To verify the fix, run the TA tests and loop for a minimum of 15 minutes (each loop takes 7 minutes). If the tests fail, u· the TA MAP to find the failure. If the teits do not fail after looping, return the system to the customer. Obtain a new e"or Jog after the customer has UIJ6d the syitem. If the same error has occurred, replace any cards that were exchanged and go to ths nsxt step in the table. If all steps have been performed and the error persists, requeit aid.
TA353 8809 Model 18 Intermittent Failure Action Plan
Probable Causes 1. Incorrect voltages
2. Loose or defective cables. See TA433 for locations.
3. Defective tape adapter cards
4. Defective SCF card
Action Measure 01 A Gate voltages:
E2D03 = +4.5 to +5.5V de E2B11 =+7.7 to +9.3Vdc E2B06 =-4.5 to -5.5V de
Measure the 01 B gate voltage
82003 = +4.5 to +5.5V de
Inspect for loose or defective SCF cables:
1. From OlA-82 to 018-A2 2. From SCF top-card connectors to
1/0 panel. Exchange 01 A-02 and 01 A-E2 cards
witll new ones. Exchange 018-82 card with a new one.
Comments For rnissing or out-of-toleraric1? voltages, go to 8809 Start MAP.
I
See Note 1.
See Note 1.
Sec Notes 1 and 2.
Notes: 1. To verify the fix, run the TA tests and loop for a minimum of 15 minutes (each loop takes 7
minutes). If the tests fail, use the TA MAP to find the failure. If the tests do not fail after looping, return the 1ystem to the customer. Obtain a new error log after the customer has used the system. If the 1ame error has occurred, replace any cards that were exchanged and go on to the next step in the table. If all steps have been performed and the error persists, request aid. 2. The 8809 Local/Remote power switch should be in Local, and the 8809 should be powered off before exchanging the SCF card.
TA400 Signal Paths and Detailed Operational Description
This section contains point-to-point wiring diagrams and data flow illustrations of the 8809 adapter cards. Figure TA400-1 shows the detailed data flow of the tape adapter.
SV27-2521-3
(TA340-TA400)
5-TA-43
Bus 0 Bus 1
0-7. p
r--,
I I Control
Processor
I -+-+-----t~ Tag
L __ _J
CARD 1
SY27-2621-3
Bus 0 0-7, P
--,
r-
-----, ~---'I I
r ,
I t
OP
I
I
1
I
I
_ _J L--' I
ADDRESS
I
1 1 _ -_-_-_
L.:_
r---
- ---,
'--- --------- SEGMENT
1
I
1
CHCVD
SEG Counter CHCVC CHCVO I
1 - ......- ._H_1...,.._ _ _H_1_._L_o_ _ LO
LO
I
I
I
I I
ORV
ORV
L-----------
I
I I _ _ _JI
Ir - - - - ,I Processor Driver A
Bus A GT 14-+---+----~
Bus C
Bus B
.Bus B 0-7, P
,-----,
I Processor Driver B
I I
I Bus c·
14-r-~-+-~~~~~~~~~~~~~----4~~~~~~~~~~~~~___,
Bus B
Bus B 8-15, P
Bus A
Bus A 8-15, P
From Card 2
Figure TA400-1 (Part 1of2). Adapter Detailed Data Flow Diagram
6-TA-44
Bus 0 Bus 1
r------
I SAR
I
Burst
Length
A~
PSAA
----,
Control Line SAR
Burst Cntr
LI _ _
DAV
Bus B
CARD2
0-4
5-P
r
I Funnel I r--G-.......- ...
1 I t-3-=~~~
0-4
5-P
G2 G1 OR DAV
L_ - -
I
I
L-- -
: Funnel
~~~G~3.... I 2
I
_..J
Cntl In
,.,._.;..;.;._.___}~=
... Bus In
Wrap
Buffer
BO
Buffer 81
5-P 5-P
Control
Bus Out
rn
Tag Out
To Tape Drive
Cntil Out
~
Bus B Bus A Figure TA400-1 (Part 2 of 2). Adapter Detailed Data Flow Diagram
0-4 0-4
Funnel 2
SY27-2521-3
(TA400 Cont)
5-TA-45
TA410 Adapter Card Interconnection Logic Signals
Figures TA410-1 and TA410-2 show the logic signals between the adapter cards for both 8809 models. See Figure TA410-3 for adapter card locations.
Top Card Connectors (See Note)
Adapter Card 1
W27
X02
Y02
Y03
Y24
Z02
Z03
Z23
Z22
Y08
Y27
Y28
Y07
Y33
Y13
Y32
Y12
- W07
- woa
W26
-.-..
-- W28
- xoa -
- X22
---- X28
- Y05 --
- Y06
--- Y22
- Y23
---- Y25
-- Y26
Y30
...
Y10
-- Y09
--- Y29
--- Y11
W02
W03
-- W05 ...
W06 W22
W23
W25
Z27
Z13
ZOB
Z09
Z06
Z30
Z11
Z10
Z32
- Sample TD Sync
-Wrap -NE or CE + Seg Even - Cycle Proc -TD Delay - End Burst -TO Sync + Read/ - Write +OP SAR 1 +OP SAR 2 +OP SAR 3 +OP SAR 4 +OP CL 1 +OP CL 2 +OP CL3 +OP CL 4 - Reset 6 Sec - Valid 2
+High I - Low
- EN Timer 2 - POR To Int Adapter
- DH FOC 1 - Selected Alert Int +Cl= 0 + SB9;. SB9 - Storage Check - TD Gone + Proc Full + PSAR =SAR - Proc Perr +CL OP 1 +CL OP 2 +CL OP 3 +CL OP 4 - Gate Off SAR - CS Req Pulse - Reset CSR - CS Req Ctl - R Tag Valid - CM Tag Valid +CL SAR 1 - Data Bus Int PO - Data Bus Int 0 - Data Bus Int 1 - Data Bus Int 2
- Data Bus Int 3 - Data Bus Int 4 - Data Bus Int 5 - Data Bus Int 6 - Data Bus Int 7
Adapter Card 2
---_.-.... -_... -......
W27 X02 Y02 Y03 Y24
Z02
-_.,
_.,
----_.,
Z03 Z23 Z22 VOS
.. Y27 Y28
__..-----....,,
Y07 Y33 Y13 Y32 Y12
W07
woa
W26
W28
xoa
X22
X28
Y05
Y06
Y22
Y23
Y25
Y26
Y30
Y10
Y09
Y29
Y11
-- W02
...
W03 W05
W06
.-. W22 W~3
...
W25 Z27
- Z13
---- zoa
_.,
.--...
Z09 Z06
Z30
Z11
--... Z10 Z32
Adapter Card 1
Z29
Z07
Z12
Z26
Z33
Z24
Z28
Z25
- Z05
X11
...
X12
-- X32 ..._
-- X13 --
- X10 .....
X09
--- X33 -- X30 .....
X29
- W29
---- W11 .....
W12
--- W30
- W09 .....
- W32
--- W13 --
- W33 .....
-- W10
X27
- X24
.----.- X03
X23
---
X25
- X05 .....
.--- X06
. X26 - X07
...
- Data Bus Int P1 - Data Bus Int 8 - Data Bus Int 9 - Data Bus Int 10 - Data Bus Int 11 - Data Bus Int 12 - Data Bus Int 13 - Data Bus Int 14 - Data Bus Int 15 - Bus A Pl - Bus A 8 - Bus A 9 -BusA10 - Bus A 11 -Bus A 12 -BusA13 - Bus A 14 - Bus A 15 - Bus B PO - Bus B 0 - Bus B 1 - Bus B 2 - Bus B 3 - Bus B 4 - Bus B 5 - Bus B 6 - Bus B 7 - Bus B P1 - Bus B 8 - Bus B 9 -BusB10 - Bus B 11 - Bus B 12 -Bus813 -BusB 14 - Bus B 15
Adapter Card 2
.. Z29 Z07
--.. Z12 Z26
- Z33
--_., Z24 - Z28
-.. Z25
--.. Z05 X11 X12 X32 X13 X10 X09 X33 X30 X29 W29 W11 W12 W30 W09 W32 W13 W33 W10 X27 X24 X03 X23 X25 XOS X06 X26 X07
Figure TA410-1. Logic Signals Between Adapter Top Card Connectors
SY27-2521-3
lntercard Connections
Adapter Card 1
B03 002 006 B13
d 009
P02
--~ G02
J06 U13
-- U11
---- S09
---~ 510
s--- G04
G05 012
p 808
G12
p 809
J12
w 804
_.._
004
J04
M02
U02
$02
U04
uos
D08
sos
S03 003
l-_--
.-I
- B Clk + C Clk - POR SUNC +Time Out 2 - Reset PLA
+Sample TD1 and TD2
- Normal End SUNC -Check End SUNC + PLA MS to BURL AB
- Sync Clock
- EN Timer 1
-Time Out 1
20 Mhz Osc
- LSSD A Clk - LSSD A Clk + High Adr Bit 1 + Hig_h Adr Bit 2 +High Adr Bit 4 +AdrBit5 Gnd
+ Adr Bit 6 + Adr Bit 7 + 5 Volts
Adapter Shown Wired for Adr 3
Adapter Card 2
-----_..
--~-
M04 P06 P12 P02 M07
MOS
G04
J04
-- P04
1= S04
L : _.._
S09 P07
P09
w G02
.....
M03
µ G03
P11 M02
w-- MOS
-- p M10
P10
µ POS
..-.
U11
w S03 .....
U09
P13 .....
w sos
-- p M13
U04
U10
M09
M12
POS
- Tape Window - Power Good - Proc Window 1
- Proc Window 2
-TOM Clock +SR PLA MS
+DC PLA MS
- PLA MS
- Enable LSSD A Clk LSSD A Clk Gnd
Figure TA410-2. Logic Signals Between Adapter Cards
Adapter Card 1 Adapter Card 2
Adapter in 8101
A2B2 A2C2
Model 1A
Adapter in 8140 C2 Board
C2G2 C2H2
Model 18
Adapter in 8140 Adapter in 8809 02 Board
D2G2 D2H2
A102 A1 E2
Figure TA410-3. Adapter Card Locations
5-TA-46
TA420 Adapter Card Wiring Diagrams
Sections TA421-1, TA422-1, and TA423-1 show the point-to-point connections from the SSCF (SC5) card to adapter card 1 (TA1) and from adapter card 2 (TA2) to the tag and bus cables for 8809 Models 1A and 1B.
TA421 8809 Model 1A Adapter Card Wiring (Adapter in 8101)
SCCF Card A2A2
J06 J05 G12 G10 G02
SSCF Signal Bus
- Halt Tag - 1/0 Tag - System Reset -TA Tag -TD Tag
Adapter
Card 1
A282
-.. G09
:..:_.. B12 DOS
.. S04
-.. J09
006 007 B04 J02
- Valid Byte
-.-. - Valid Halfword
-- - Parity Valid
-.. - Channel Request Low
J11 J02 G03 G10
009 812 J04 805
~ - End of Chain
--..... - Modifier - - Interrupt Req Bit 3
--..... - Interrupt Req Removed
J05 513 J10 GOB
M12 B02 B08 D11 G04 J07 G09
M'o2
P10 P13 D05 B10 013 GOS GOS J09 P06 P11
.. - Data Bus PO
.. - Data Bus 0
- - Data Bus 1
-- - Data Bus 2
- - Data Bus 3
--.. - Data Bus 4 - Data Bus 5
-- - Data Bus 6
----..... - Data Bus 7 - Data Bus P1
--.-. - Data Bus S
.. - Data Bus 9 - Data Bus 10
--.-. - Data Bus 11
.-. - Data Bus 12 - Data Bus 13
- - Data Bus 14
---- - Data Bus ts
-_...-.......~ .......
M04 MOS M03 P06 M09 M07
_---.....-......._..-...............
P11 P05 P12 P09 P13 M12 M10 P10 M13 P04 MOS P07
.. To Other - CH Grant Low ... -- Adapters ,.- CH Grant Pass
G07 J07
P09 813
- Release +Voltage Enable
Adapter Card 2 A2C2
B05 B08 B12 B09
Adapter Orv Rev A202
T BOS so2
808 M12 812 U04 B09 P13
Tape Drive Control Lines
+ Select Hold ·+Response +Recycle +Tag Gate
B13 012 013 B10 009 002
813 U02 012 813 013 U06
B10 sos
009 U05 002 804
+Tag Bus O
+Tag Bus 4 +lag Bus 5 +Tag Bus 6 +Tag Bus 7
+Tag Bus P
G05 G12
G13 J06
G05
..... L_
G12 J05
G13
J06
... M04
--- MOS
+Normal End + Selected Alert
POS P02 M02
--------
+Check End + Select Active +Tag Valid
I uos
Ground
010
010 M13
+Sync Out
007
007 U09
+Bus Out 0
D04
004 809
+Bus Out 1
D06
oos
B03
006 U10 005 810 B03 U11
+Bus Out 2 +Bus Out 3 +Bus Out 4
B02
B02 807
+Bus Out S
B07
B07 512
+Bus Out 6
011
011 U13
+Bus Out 7
B04
B04 50B
+Bus Out P
G09
J07
G10
GOS
J11
J09
G07
J10
J12
J13
..-r J02 .- 802
t
These
G09 J07 G10 GOB J11 J09 G07 J10 J12 J13
-... P04
P09 .....
- M09 ....
P10
-- M10
P11
-- P07
----- M07
----- P06
- MOS
+Sync In
+Bus In 0 +Busln1 +Bus In 2 +Bus In 3 +Bus In 4 +BuslnS +Bus In 6 +Bus In 7 +Bus In P
l DOS
Ground
Lines Are
Minus
Edge Conn
_..
-....
-.....
_.
C6804 C6C04 C6004 C6A04
__.......
-......
-__..
-.__..
-
A6D04 B6A04 A6E04 B6C04 B6B04 B6E04
E
B6B02 B6002 B6C02 A6E02 B6A02 A6D02 B6D04 C6E04
_. C1013
.- A1E13
-__. B1A13
.-...~
B1B13 B1C13
..-.. 81E13
-__.. C1A13
-_..
-...... .
C1B13 C1C13
-- A1D13
E
C1 E11 B1A11 81811 B1C11 81011 C1A11 C1B11 C1C11 C1011 A1 E11 A1011 B1013 C1E13
Edge Conn
Paddle Card A2Z1
B10 B11 B12 B09
B02 B04 B03 BOS BOS BOB
005 007 D06 D03 D04 D02 B07 813
B12 B03 B04 80S 806 80B 809 810 811 802
013 004 005 006 007 009 010 011 012 003 002 807 813 Paddle Card A2Y1
SV27-2521-3
Tag Cable 01V-A2
011 812 D13 810
803 BOS 004 BOS D06 D09
G05 GOS J06 G03 J04
D13 D04 B05 006 BOS 009 B10 011 B12 B03
J13 J04 GOS JOO GOS J09 G10 J11 G12 G03
Bus Cable 01V·A1
(TA410-TA421)
6-TA-47
TA422 8809 Model 1A Adapter Card Wiring (Adapter in 8140)
SCCF Card C2A2
J06 J05 G12 G10 G02
SSCF Signal Bus
- Halt Tag - 1/0 Tag - System Reset - TA Tag - TD Tag
Adapter Card 1 "G2
.. G09
---: 812 005
- S04
.--. J09
006 007 804 J02 D09 812 J04 B05
- Valid Byte
-- - Val id Halfword -.-.- - Parity Valid
.. - Channel Request Low - End of Chain
--- - Modifier -- - Interrupt Req Bit 3
---.. - Interrupt Req Removed
J11 J02 G03 G10 ·J05 S13 J10 GOB
M12 B02 BOB D11
~ - Data Bus PO
.. - Data Bus 0 .-. - Data Bus 1 - - Data Bus 2
-..- - Data Bus 3
G04 J07 G09 M'o2 P10 P13 D05 B10 D13 G05 GOB J09 P06 P11
- Data Bus 4
-..- - Data Bus 5
-..._ - Data Bus 6
- - Data Bus 7
-- - Data Bus Pl -- - Data Bus 8
.. - Data Bus 9
.. - Data Bus 10
- - Data Bus 11
-- - Data Bus 12
--- - Data Bus 13
.. - Data Bus 14 --.. - Data Bus 15
-.... M04 M05
-.. M03
---..... P06 M09
--.-.....
.-...
M07 P11 P05 P12
_...,. P09
P13
-.._... M12
....... M10
----.. P10 M13
... P04
.. MOB
-..... P07
To Other Adapters
- CH Grant Low ..
-.. - CH Grant Pass -
G07 J07
P09
- Release +Voltage Enable
813
*Card may be in C2 or D2 board
Adapter Card 2 *H2
805 BOS B12 809
Adapter Orv Rev *J2
T 805 S02
BOS M12 B12 U04 B09 P13
Tape Drive Control Lines
+Select Hold +Response +Recycle +Tag Gate
B13 012 013 B10 009 002
B13 U02 012 S13 D13 U06 B10 S05 DOS U05 D02 S04
+Tag Bus O +Tag Bus 4 +Tag Bus 5 +Tag Bus 6 +Tag Bus 7
+Tag Bus P
G05 G12
G13 J06
G05
~ G12 J05 G13 J06
M04 M05 P05 P02 M02
-------.--.
+Normal End + Selected Alert +Check End + Select Active +Tag Valid
010 007 D04 D06 D05 803 B02 B07 011 804
I
D10 M13
007 U09
D04 sos
D06 U10
D05 S10
803 U11
B02 S07
807 S12
D11
U13
804 SOB
+Sync Out +Bus Out 0 +Bus Out 1 +Bus Out 2 +Bus Out 3 +Bus Out 4 +Bus Out 5 +Bus Out 6 +Bus Out 7 +Bus Out P
GOS
J07
G10
GOB
J 11
JOS
G07
J10
J12
-.-... J13 J02
... S02
t
These
G09 J07 G10 GOS J11 J09 G07 J10 J12 J13
P04
--..- P09
-.. M09 - P10
- M10
---.. P11
--... P07
M07
--- P06 ....
MOS
+Sync In
+Bus In 0 +Bus In 1 +Busln2 +Bus In 3 +Bus In 4 +Busln5 +Bus In 6 +Bus In 7 +Bus In P
l
Lines Are
Minus
SY27-2521-3
Edge
Conn
-_.._....,
-. -
J6D04 J6E04 K6A04 J6C04
.. H6A04
-_.. H6C04
-_._..., H6B04
. H6E04
-.. H6004
-.. J6B04
H6002 J6A02 H6E02 H6802 H6C02
Paddle Card *Z3
810 B11 B12 809
B02 804 B03 B06 B05 BOB
D05 D07 006 003 D04
Tag Cable 01V
011 B12 D13 B10
B03 B05 004 BOB D06 D09
G05 GOB J06 G03 J04
.. K1A13
---.. H1813
.__., H1C13
... H1013
- H1E13
.---.. J1B13
... J1C13
. J1D13
- J1E13 -----. H1A13
K1 B11 H1 C11 H1011 H1 E11 J1A11 J1C11 J1D11 J1E11 K1A11 H1B11
Edge Conn
812 803 B04 805 B06 808 B09 B10 B 11 B02
D13 D04 D05 D06 D07 D09 D10 011 D12 D03
Paddle Card *Y3
D13 004 B05 006 BOB DOS B10 D11 B12 803
J13 J04 G05 JOO GOB J09 G10 J 11 G12 G03
Bus Cable
01 v
5-TA-48
TA423 8809 Model 18 Adapter Card Wiring
01 B Gate
01A Gate
SSCF
Adapter
Adapter
Card
SSCF Signal Bus
A2
82
Card 1
Card 2
Tape Drive
B2
J06 J05 G10 G02 G12
- Halt Tag - 1/0 Tag -TA Tag -TD Tag - System Reset
Socket
-.-__.. J06 J05
G10
.- G02
-. G12
A2
Flat Cables (3)
Socket
J06
J05
G10
G02
B2
G12
02
G09 B12 S04 J09 D05
E2
B05 BOB B12 B09
Control Lines
- Select Hold - Response - Recycle - Tag Gate
C2
. 805
__.. BOB
B12
-...... B09
G2
B05 BOB B12 B09
006 ....--
------ D07 --- B04
D09 .....
B12 .__
-- J02
-.-. J04
-- 805 ---
- Valid Byte - Valid Halfword - Parity Valid - End of Chain - Modifier - Channel Request Low - Interrupt Reg Bit 3 - Interrupt Req Removed
D06. D07 B04 D09 B12 J02 J04 B05
A3
006 D07 B04 D09 B12 J02 J04 B05
83
813 D12
-Tag Bus 0 - Tag Bus 4 - Tag Bus 5
_.. B13
-__... D12
B13 012
J11 J02 G03
D13
-T~ Bus 6
:-"
D13
D13
B10 D09 002
- Tag Bus 7 - Tag Bus P
__.
--_.
810 D09 D02
B10 D09 002
J05
S13 G10 J10
G13 ......-
--.--. J06 ......-
- Select Active - Tag Valid - Normal End
G13 J06
G13 JOG
Goa
G05
=- [G12
-- U02
- Selected Alert - Check End
G05
G12 J05
G05 G12 J05
M12 .....
B02
---- BOS
-- D11 ..... -..- G04
J07
- G09
--.. M02 ....-
P10
--.. P13 ....-
- 005 ---
B10 ....-
-- D13 .....-
-.-. G05 ....-
.-.- GOS
J09
- P06 .....
-- P11 ......-
- Data Bus PO - Data Bus 0 - Data Bus 1 - Data Bus 2 - Data Bus 3 - Data Bus 4 - Data Bus 5 - Data Bus 6 - Data Bus 7 - Data Bus Pl - Data Bus 8 - Data Bus 9 - Data Bus 10 -DataBus11 - Data Bus 12 - Data Bus 13 - Data Bus 14
- Data Bus 15
. M12
-.. B02 -__....
.- BOS D11
...
G04 J07
.-.--..
G09 M02
. P10
.--... P13 D05
- B10
- 013
- G05
. -_
GOS
-__.... J09
..-- P06
A4
- P11
M12
B02
BOS
011
G04
J07
G09
M02
P10
P13
B4
005
B10
D13
G05
G08
J09
P06
P11
M04 M05 M03 P06 M09 M07 P11 P05 P12 P09 P13 M12 M10 P10 M13 P04 M08 P07
010 007 004 DOG 005 B03 B02 B07 011 B04
- Sync Out - Bus Out 0 - Bus Out 1 - Bus Out 2 - Bus Out 3 - Bus Out 4 - Bus Out 5 - Bus Out 6 - Bus Out 7 - Bus Out P
G09 J07 G10 GOS J11 J09 G07
..-.-..-_ --....-
-......-
----
-....-
- Sync In -BuslnO - Bus In 1 -Busln2 -Busln3 -Busln4 - Bus In 5
..
D10
...... D07 004
..__.. 006
__.. 005
...
-__..
.-__..
B03 B02 807 011 B04
G09 J07 G10 G08 J11 J09 G07
D10 D07 004 006 D05 B03 B02 B07 011 B04
G09 J07 G10 GOS J11 J09 G07
P02
- Channel Grant Low
-... P02
P02
G07
-- J10 ....-
---- J12
J13 ......-
-Busln6 - Bus In 7 -BuslnP
JlO J12 J13
J10 J12 J13
P09
- Release
B13
+ Voltage Enable
__... P09
-__.. B13
P09 813
J02 S02
SY27-2521-3
(TA422, T~423)
5-TA-49
TA430 Adapter Card and Top Card Connector Locations and Illustrations
The figures in the following sections show the location and pin numbering scheme of the tape adapter card top card connectors, as well as locations and ii lustrations of the adapter cards for 8809 Models 1A and 1B.
TA4318809 Model TA Adapter Card and Top Card Connector Locations (Adapter in 8101)
813
SCF Cable (3) D02
002 - X02 802 - X22 013 - X13 813 - X33
813 013
Top Card Connections
<.,,, -- -..... >
~--v_1___o_. Bus
2
A2
82
C2
SSCF
A2
Top Card Connector
Each top card pin is connected to the corresponding pin on the other card.
Example:
82 X23 to C2 X23 82 X10 to C2 X10
Note: There are 4 top card connectors. A4
813
~-~-------.i:
--- -..
Z1
802
Figure TA431-1. Top Card Connector Location and Pin Numbering, Model 1A {Adapter in 8101)
Top Card Locations A2, 82, C2 B D 2
I
13
2
I
13
2
I
I
I
13
2
I
I
I
13
SY27-2621-3
u.
(J
2 3
Cl)
N
Cl)
A2
"C
li
'Eca
(.)
(.)
e....
Q.
....
Cl)
0.
Ill
~
Ill "C
c(
i
'Qi u
Cl)
~
A3
!ca.
I-
!ca.
I-
~
~
4
A4
5
Figure TA431-2. Adapter Card and Cabla Locations-8101 01A-A2 Board (Card Side)
6-TA-60
TA432 8809 Model TA Adapter Card and Top Card Connector Locations (Adapter in 8140)
Top Card Connections
G2
H2
Top Card Locations
B D 2
I
·22
' ' ··········33
········2 ···13
·22
··········'33
· · · · · · · ·
I
· ·
2
13
Top Card Connector
Each top card pin is connected to the corresponding pin on the other card.
Example:
G2 X23 to H2 X23 G2 X10 to H2 X10
Note: There are 4 top card connectors.
13
2
22--1Ll 2 I
i3 p
2
3:Jt 13
I
fit 22
2
I
I
3:Jl 13 u
2
13
22jj~ 2
I
I
3:Ji I 13
13
Figure TA432-1. Top Card Connector Location and Pin Numbering. Model 1A (Adapter in 8140)
2
u.
()
(/)
(/)
A2
3 A3
4 A4
5
N ...
"E "E
·~ ca
a...
(..).
Q)
Fg
a & ca
"C
ca
"C
.~
c <( <C
8. 8.
~ {2.
Note: SSCF card in C2 board only.
Figure TA432-2. Adapter and SCF Card Locations 8140 C2 or 02 Board
SY27-2521-3
(TA430-TA432)
5·TA·51
TA433 8809 Model 18 Adapter Card and Top Card Connector Locations (Figures TA433-1, -2)
Top Card Connections
D2
E2
Top Card Locations
B D 2
I
·22
' " ··········33
········2 · ·
·13
·22
%
· · · · · · · ·
·33
· · · · · · · ·
%
· ·
2 13
Top Card Connector
Each top card pin is connected to the corresponding pin on the other card.
Example:
02 X23 to E2 X23 D2 X10 to E2 X10
Note: There are 4 top card connectors.
13
2:_w 2
33-4 13
22~2
_JIJ
3:JL 13
22JIr 2
3:J i 13
Figure TA433-1. Top Card Connector Location and Pin Numbering, Model 18
13 J
2
I
13 p
2
I
I
I
13
u
2
I
13
SY27-2521-3
002
802
2
---
3
------
4
N
82
'E 'E
uI.V.. uI.V..
Q)
Q.
~ Q.
IV
IV
1J 1J
83
<(
<(
8. ~
tIV-
al
t-
84
013
5
SCF to Adapter Cables (3}
The SCF card is shown in Figure TA 111-4.
Figure TA433-2. Adapter Card and Cabla Locations-8809 01A-A1 Board (Card Side)
5-TA-62
TA434 8809 Adapter Card Illustrations (Figures TA434-1, -2, and -3)
0
TOP
Note: 8101 Location = A2B2 8809 Location =A 102 8140 Location = C2G2 or D2G2
Figure TA434-1. TA1 Card
D
TOP
SY27-2521-3
Note: 8101 Location · A2C2 8809 Location ·A 1E2 8140 Location · C2H2 or D2H2
Figure TA434-2. TA2 Card
D
(TA433, T A434)
5-TA-63
SV27-2621-3
&·TA-64
D D
~
D
......
TOP
D
D
Ii-
~
TA440 Tape Adapter Voltage Checks
To ensure correct voltages to the tape adapter cards, meter the voltages as follows: 8809 Model 1A Voltage Check Pins (Adapter in 8101)·
Pin
Range
02003 +4.5V to +5.5V de
02811 +7. 7V to +9.3V de
02806 -4.5V to -5.5V de
*Meter these voltages on the 8101 01A-A2 board.
8809 Model 1A Voltage Check Pins (Adapter in 8140)*
Pin
Range
J2D03 +4.5V to +5.5V de
J21;111 +7.7V to +9.3V de
J2B06 -4.5V to -5.5V de
*Meter these voltages on the 8140 adapter board (01A-C2 or 02).
8809 Model 18 Voltage Check Pins*
Pin
Range
E2D03 +4.5V to +5.5V. de
E2811 +7.7V to +9.3V de
E2B06 -4.5V to -5.5V de
*Meter these voltages on the 8809 board. In addition, check the 003 pin on the SCF card for the presence of +5.0V de.
i""""'I.
Note: Used only for Model TA. 8101 Location= A2D2 8140 Location = C2J2 or D2J2
Figure TA434-3. TA3 Card
This page intentionally left blank.
SY27-2521-3
(TA434 Cont, TA440)
5-TA-66
,A450 Adapter Point-to-Point Net Checklists
TA451 8809 Model 1A Point-to-Point Net Checklist (Adapter in 8101)
Find the test error message pattern in Figure TA451-1. All nets in the figure refer to all test error patterns indicated. Line entries reading from left to right are separate nets, and apply for any error listed in the test error pattern column. Check continuity between the test points, which are al I located on the 8101 A2 board. If any net does not indicate continuity, correct by wire-wrapping the points together.
Test Error Pattern
Point A
Point B
Point C
Point D
Point E
PASO PA95 PA96 XX8C PAXE 01XX PAXE 02XX PAXE 03XX PAXE 09XX
82803 82804 82812 82002 82005 82006 82009 82012 B2G02 82G03 B2G08 82G09 B2G10 82J02 82J04 82J05 B2J09 82J10 B2J11 B2M03 B2M04 B2M05 82M07 B2M08 82M09 B2M10 82M12 B2M13 82P04 B2P05 B2P06 82P07 B2P09 82P10 82P11 82P12 82P13 82804 82813 C2M09 C2803 C2804 82J07 82G07
C2M04 82004 A2J05 C2P06 A2G12 C2P12 82P02 B2G04 B2J06 A2B04 A2B05 A2J06 A2J02 A2007 GNO A2009 A2G02 A2J04 A2D06 A2808 A2M12 A2802 A2J07 A2P06 A2G04 A2D13 A2810 A2G08 A2J09 A2M02 A2D11 A2P11 A2P13 A2G05 A2G09 A2P10 A2D05 A2G10 A2812 GND C2U09 C2S09 H2G03 G2S07
C2M07 B2G05 C2M05
C2P04
C2P07 82509
C2P09 82510
Figure TA451-1(Part1of2). Model 1AAdapter Net Checklist (Adapter in 8101)
SY27-2521-3
Note: If an adapter is installed, the jumper at 82607 to B2J07 MUST be removed.
Test Error Pattern
PAXE 04XX through
PAXE oaxx
and
PAXE11XX through PAXE 15XX
Point A
82808 82809 B2G02 C2G02 C2G12 C2M02 C2M03 C2M10 C2P05 C2P07 C2P13 C2U10 82J10
Point B
B2G12 82J12 82J06 C2M03 D2G12 C2M08 C2G02 C2P10 C2U11 C2P09 C2S05 GND A2J04
Point C C2M05 D2J05
82012
Point D B2G04
Point E 82G05
5-TA-56
Test Error Pattern
PAXE 40XX through PAXE43XX
Point A
82813 82U11 82U13 C2802 C2803 C2804 C2805 C2807 C2808 C2809 C2810 C2812 C2B13 C2002 C2004 C2005 C2D06 C2007 C2009 C2010 C2D11 C2012 C2013 C2G05 C2G07 C2G08 C2G09 C2G10 C2G13 C2J02 C2J06 C2J07 C2J09 C2J10
Point B
C2P02 C2J04 C2G04 02802 02803 02804 02805 02807 02808 02809 02810 02812 02813 02002 02004 02005 02006 02007 02009 02010 02011 02012 02013 02G05 02G07 02G08 02G09 02G10 02G13 A2P09 02J06 02J07 02J09 02J10
Test Error Pattern
PAXE 40XX through PAXE 43XX (cont'd.I
Point A
C2J11 C2J12 C2J13 C2M13 D2M02 02M04 02M07 D2M08 02M09 02M10 02M12 02M13 02P02 02P04 02P06 02P07 02P09 02P10 02P11 02P13 02502 02504 02505 02S07 02508 02509 02810 02512 02U02 02U04 02U05 02U09 02U10 02U11 02U13
Point B
D2J11 D2J12 D2J13 C2U04 86A02 86802 C1C11 A 1.E11 81811 81011 C6C04 C1013 A6E02 C1E11 C1D11 C1B11 81A11 81C11 C1A11 C6A04 C6804 86E04 B6C04 C1A13 A1013 B1A13 B1C13 C1813 A6D04 C6D04 86804 A1E13 81813 B1E13 C1C13
Figure TA451-1 (Part 2 of 2). Meal 1A Adapter Net Checklist (Adap18r in 8101)
Test Error Pattern
PAXE44XX through PAXE 56XX
Point A
82J11 82513 82U13 C2805 C2009 C2G10 C2G12 02M05 02M09 02M12 02M13 02P04 02P05 02P11 02510 02513 02U04 02U06
Point B
A2006 A2812 C2G04 02805 02009 02G10 02G12 86002 81811 C6C04 C1013 C1E11 86C02 C1A11 81C13 B6A04 C6004 A6E04
Point C 02J05
The net check points listed below do not cause test failures when both open and grounded, but should be checked to ensure proper tape logic continuity and operation.
Point A
82808 82813 82009 82G03 82G08 B2G09 82M02 82U11 C2012 C2013 C2G03 C2G13 C2M10 C2M12 C2M13 C2S02 C2S04 C2P05 02513 D2U06 82J07 C2J02 02008 02U08
Point B
B2G12 C2P02 82P02 A2804 A2805 A2J06 Gnd C2J04 02012 02013 C2P11 02G13 C2P10 Gnd C2U04 A2813 C2S09 C2U11 86A04 A6E04 H2G03 A2P09 C1E13 C6E04
Pointe C2M07
C2P04 81013 86004
Point D
82S09 A1011 A6002
Point E 82510
SY27·2621-3
CTMIO. TMl1)
SY27-2621-3
TA452 8809 Model TA Point-to-Point Net Checklist (Adapter in 8140) Find the test error message pattern in Figure TA452·1. All nets in the figure refer to all test error patterns indicated. Line entries reading from left to right are separate nets, and apply for any error listed in the test error pattern column. Check continuity between the test points, which are all located on the 8140 C2 or 02 board. If any net does not indicate continuity, correct by wire-wrapping the points together.
Test Error Pattern
Point A
Point B
Pointe
Point D
Point E
PASO PA95 PA96 XXBC PAXE 01XX PAXE 02XX PAXE 03XX PAXE 09XX
G2B03 G2B04 G2B12 G2D02 G2005 G2D06 G2009 G2D12 G2G02 G2G03 G2G08 G2G09 G2G10 G2J02 G2J04 G2J05 G2J09 G2J10 G2J11 G2M03 G2M04 G2M05 G2M07 G2M08 G2M09 G2M10 G2M12 G2M13 G2P04 G2P05 G2P06 G2P07 G2P09 G2P10 G2P11 G2P12 G2P13 G2504 G2S13 H2M09 H2S03 H2S04 G2J07 G2G07
H2M04 G2004 A2J05 H2P06 A2G12 H2P12 G2P02 G2G04 G2J06 A2B04 A2B05 A2J06 A2J02 A2007 GND A2D09 A2G02 A2J04 A2006 A2B08 A2M12 A2B02 A2J07 A2P06 A2G04 A2013 A2810 A2G08 A2J09 A2M02 A2011 A2P11 A2P13 A2G05 A2G09 A2P10 A2005 A2G10 A2B12 GND H2U09 H2S09 K2P02 A2P02
H2M07 G2G05 H2M05
H2P04
H2P07 G2S09
H2P09 G2S10
Figure TA452-1 (Part 1 of 2). Model 1A Adapter Net Checklist (Adapter in 8140)
Test Error Pattern
Point A
Point B
Point C
Point D
Point E
PAXE 04XX through
PAXE oaxx
and
PAXE 11XX through PAXE 15XX
G2B08 G2B09 G2G02 H2G02 H2G12 H2M02 H2M03 H2M10 H2P05 H2P07 H2P13 H2U10 G2J10
G2G12 G2J12 G2J06 H2M03 J2G12 H2M08 H2G02 H2P10 H2U11 H2P09 H2S05 GND A2J04
H2M05 J2J05
G2D12
G2G04
G2G05
Note: If an adapter is installed, the jumper at G2G07 to G2J07 MUST be removed.
5-TA-58
Test Error Pattern
Point A
Point B
Test Error Pattern
Point A
PAXE 40XX through PAXE 43XX
G2B13 G2U11 G2U13 H2B02 H2B03 H2B04 H2B05 H2807 H2B08 H2B09 H2B10 H2B12 H2813 H2002 H2004 H2005 H2006 H2007 H2009 H2010 H2011 H2012 H2013 H2G05 H2G07 H2G08 H2G09 H2G10 H2G13 H2J02 H2J06 H2J07 H2J09 H2J10
H2P02 H2J04 H2G04 J2802 J2803 . J2804 J2805 J2807 J2808 J2809 J2810 J2812 J2813 J2D02 J2004 J2D05 J2D06 J2007 J2009 J2D10 J2D11 J2D12 J2D13 J2G05 J2G07 J2G08 J2G09 J2G10 J2G13 A2P09 J2J06 J2J07 J2J09 J2J10
PAXE 40XX through PAXE 43XX
(cont'd)
H2J11 H2J12 H2J13 H2M13 J2M02 J2M04 J2M07 J2M08 J2M09 J2M10 J2M12 J2M13 J2P02 J2P04 J2P06 J2P07 J2P09 J2P10 J2P11 J2P13 J2S02 J2S04 J2S05 J2S07 J2S08 J2S09 J2510 J2512 J2U02 J2U04 J2U05 J2U09 J2U10 J2U11 J2U13
Figure TA452-1 (Part 2 of 2). Model 1A Adapter Net checklist (Adapter in 8140)
Point B
J2J11 J2J12 J2J13 H2U04 H6C02 H6002 J1 E11 H1811 H1011 J1A11 J6E04 K1A13 H6802 K1811 K1A11 J1011 H1C11 H1 E11 J1C11 J6C04 J6004 J6B04 H5E04 J1C13 H1A13 H1C13 H1 E13 J1013 H6A04 K6A04 H6004 H1813 H1013 J1813 J1E13
Test Error Pattern
Point A
Point B
Point C
PAXE 44XX through PAXE 56XX
G2J11 G2513 G2U13 H2805 H2009 H2G10 H2G12 J2M05 J2M09 J2M12 J2M13 J2P04 J2P05 J2P11 J2S10 J2S13 J2U04 J2U06
A2006 A2812 H2G04 J2806 J2009 J2G10 J2G12 J6A02 H1011 J6E04 K1A13 K1B11 H6E02 J1C11 H1E13 H6C04 K6A04 H6B04
J2J05
The net check points listed below do not cause test failures when both open and grounded, but should be checked to ensure proper tape logic continuity and operation.
Point A
Point B
Point C
Point D
Point E
G2B08 G2B13 G2009 G2G03 G2G08 G2G09 G2M02 G2U11 H2012 H2013 H2G03 H2G13 H2M10 H2M12 H2M13 H2S02 H2S04 H2P05 J2S13 J2U06 G2J07 H2J02
G2G12 H2P02 G2P02 A2B04 A2805 A2J06 GND H2J04 J2012 J2013 H2P11 J2G13 H2P10 GND H2U04 A2813 H2S09 H2U11 H6C04 H6B04 K2P02 A2P09
H2M07
H2P04
G2S09
G2S10
SY27-2521-3
(TA462)
6-TA-59
J 8809 Model 18 Point-to-Point Net Checklist
Find the test error message pattern in Figure TA452-1. All nets in the figure refer to all test error patterns indicated. Line entries reading from left to right are separate nets, and apply for any error listed in the test error pattern column. Check continuity between the test points, which are all located on the 8809 01A gate unless otherwise indicated. If any net does not indicate continuity, correct by wire-wrapping the points together.
Test Error Pattern
PAS() PA95 PA96 XX8C PAXE OlXX
PAXE o2xx
PAXE 03XX PAXE 09XX
Point A
02812 02005 02G03 D2G08 02G09 D2J02 02J05 02J09 02J11 D2M03 02M04 02M05 02M07 02M08 02M09 02M10 02M12 02M13 02P04 02P05 02P06 D2P07 02P09 D2P10 02P11 02P12 02P13 02504 02513 D2G07 02G10 02J10 02803 02804 02002 02006 02009 02012 02G02 02J04 02509
E2M09 E2503
Point B
82J05 82G12 82804 82805 82J06 82007 82009 82G02 82006 82808 82M12 82802 82J07 82P06 82G04 82013 82810 82GOB 82J09 82M02 82011 82P11 82P13 82G05 82G09 82P10 82005 82G10 82812 82P02 82J02 82J04 E2M04 02004 E2P06 E2P12 02P02 02G04 D2J06 GND 02510 GND E2U09
Point C
Cable 83 Cable 83 Cable 82 Cable 82 Cable 83 Cable 82 Cable 82 Cable 83 Cable 82 Cable 82 Cable 84 Cable 82 Cable 83 Cable 84 Cable 83 Cable 82 Cable 82 Cable 83 Cable 83 Cable 84 Cable 83 Cable 84 Cable 84 Cable 83 Cable 83 Cable 84 Cable 82 Cable 83 Cable 82 Cable 84 Cable 83 Cable 83
Point D
018-A2J05 018-A2G12 018-A2804 018-A2805 018-A2J06 018-A2007 018-A2009 018-A2G02 018-A2006 018-A2808 018-A2M12 018-A2802 018-A2J07 018-A2P06 018-A2G04 018-A2013 018-A2B10 018-A2G08 018-A2J09 018-A2M02 018-A2011 018-A2P11 018-A2P13 018-A2G05 018·A2G09 018-A2P10 018-A2005 018-A2G10 018-A2812 018-A2P02 018-A2J02 018-A2J04
Point E
018-B2J05 018-B2G12 018-82804 018-82805 018-82J06 01 B-82007 018-82009 01B-82G02 01 B-82006 018-82808 018-B2M12 018-82802 018-B2J07 018-82P06 018-82G04 018-82013 018-82810 018-82008 01B-82J09 01B-82M02 018-82011 018-82P11 018-82P13 01B-B2G05 018-82009 01B-B2P10 018-82005 018-B2G10 018-82812 018-B2P02 01B-B2J02 018-B2J04
E2M07 02G05 E2M05
E2504
E2P07 E2509
E2P09 E2P04
Figure TA453-1 (Part 1 of 2). Model 18 Adapter Net Checklist
SY27-2521-3
Test Error Pattern PAXE 04XX through PAXE o8xx
and
PAXE 11XX through PAXE 15XX
Point A
02J10 02808 02809 02G02 E2G02 E2G12 E2U02 E2M02 E2M03 E2M10 E2P05 E2P07 E2P13 E2U10
Point B
82J04 02G12 02J12 02J06 E2M03 C2G12 C2J05 E2M08 E2G02 E2P10 E2U11 E2P09 E2S05 GND
Point C Cable 83
Point D 018-A2J04
E2M05
G2G12 G2J05
02012
02G04
Point E 018-82J04
02G05
5-TA«>
Test Error Pattern
PAXE 40XX through PAXE 43XX
Point A
02813 D2U11 D2U13 E2802 E2803 E2804 E2805 E2807 E2808 E2809 E2810 E2812 E2813 E2D02 E2D04 E2D05 E2006 E2D07 E2009 E2D10 E2D11 E2D12 E2D13 E2G05 E2G07 E2G08 E2G09 E2G10 E2G13 E2J02 E2J06 E2J07 E2J09 E2J10 E2J11 E2J12 E2J13 E2M13
Point B
E2P02 E2J04 E2G04 C2B02 C2803 C2804 C2805 C2807 C2808 C2B09 C2B10 C2812 C2813 C2D02 C2D04 C2D05 C2D06 C2D07 C2D09 C2D10 C2D11 C2D12 C2D13 C2G05 C2G07 C2G08 C2G09 C2G10 C2G13 82P09 C2J06 C2J07 C2J09 C2J10 C2J11 C2J12 C2J13 E2U04
Point C
Point D
G2802 G2803 G2804 G2805 G2807 G2808 G2809 G2810 G2812 G2813 G2D02 G2D04 G2005 G2D06 G2D07 G2009 G2D10 G2D11 G2012 G2013 G2G05 G2G07 G2G08 C2G09 G2G10 G2G13 Cable 84 G2J06 G2J07 G2J09 G2J10 G2J11 G2J12 T2J13
018-A2P09
Figure TA453-1 (Part 2 of 2). Model 18 Adapter Net Checklist
Point E 018-82P09
Test Error Pattern
PAXE 44XX through PAXE 56XX
Point A
D2J11 D2S13 D2U13 E2805 E2D09 E2G10 E2G12 E2U02
Point B
82D06 82812 E2G04 C2805 C2D09 C2G10 C2G12 C2J05
Point C
Cable 82 Cable 82
G2805 G2D09 G2G10 G2G12 G2J05
Point D
018-A2D06 018-A2812
Point E
018-82006 018-82812
The net check points listed below do not cause test failures when both open and grounded, but should be checked to ensure proper tape logic continuity and operation.
Point A
D2G03 D2G08 D2G09 E2S02 E2J02 02808 02813 02009 02M02 D2U11 E2D12 E2D13 E2G03 E2G13 E2M10 E2M12 E2M13 E2S04 E2P05
Point B
82804 82805 82J06 82813 82P09 D2G12 E2P02 D2P02 GND E2J04 C2D12 C2D13 E2P11 C2G13 E2P10 GND E2U04 E2S09 E2U11
Point C
Cable 82 Cable 82 Cable 82 Cable 82 Cable 82
Point D
01B-A2804 018-A2805 018-A2J06 018-A2813 018-A2P09
Point E
018-82804 018-82805 018-82J06 018-82813 018-82P09
E2M07
G2D12 G2D13
G2G13
E2P04
D2S09
02810
SY27-2521-3
(TA453)
5-TA-61
SY27-2521-3 This page intentionally left blank.
5-TA-62
TA500 Console Messages
Each permanent error generates a console message to the control operator. The operator then refers to the system messages and codes manual for appropriate action. The following paragraphs show the format and content of the console messages for DPPX and DPCX.
TA510 DPPX
There are nine different console messages, each representing a different category of error:
1. HDIT0052P PA= XX SCA= XXXX OT= XXXX TAPE MEDIA PROBLEM ERROR CODE= XXXX
2. HDIT0053P PA= XX SCA= XXXX OT= XXXX TAPE OVERRUN ERROR CODE= XXXX
3. HDIT0055P PA= XX SCA= XXXX OT= XXXX INCORRECT TAPE MODE ERROR CODE= XXXX
4. HDIT0056P PA= XX SCA= XXXX OT= XXXX TAPE MARKER SENSOR FAILURE -TAPE DRIVE DEACTIVATED-ERROR CODE= XXXX
5. HDIT0057P PA= XX SCA= XXXX OT= XXXX TAPE DATA UNSAFE-ERASE HEAD IS LIVE, REMOVE TAPE FROM UNIT WITHOUT MOVING IT PAST HEADSTAPE DRIVE DEACTIVATED-ERROR CODE= XXXX
6. HDIV0051P PA= XX SCA= XXXX OT= XXXX LOGIC ADAPTER CARD ERROR-LOGIC CARD DEACTIVATED-ERROR CODE= XXXX
7. HDIV0054P PA= XX SCA= XXXX OT= XXXX DEVICE NOT READY-INTERVENTION REQUIRED-ERROR CODE= XXXX
8. HDIV0058P PA= XX SCA= XXXX OT= XXXX PERMANENT 1/0 ERROR-DEVICE DEACTIVATED-ERROR CODE= XXXX
9. HDIV0059P PA= XX SCA= XXXX OT= XXXX INTERNAL SEQUENCE ERRORDEVICE DEACTIVATED-ERROR CODE= XXXX
Where:
PA = Physical address of the tape adapter SCA = Secondary component address.
OT = Device type ERROR CODE= Tape adapter return code
Refer to the DPPX General Failure Index (Chapter 1, ST110) for associated action plans.
TA520 DPCX
SV27·2521·3
The DPCX console message has the following format:
XXXX-LA=nn FPID=nnnn LOC=nnnnn OPID=nn 1/0 ERROR, COMPLETION CODE=nnn ERROR CODE=xnn
Where:
XXXX =System message number (SMN).
LA = The logical address (nn) of the unit on which the failure occurred.
FPID =The functional program identification number (nnnn).
LOC · The address (nnnnn) of the instruction being performed when the error occurred.
OPID =The operator ID number (nn).
COMPLETION CODE = The code (nnn) assigned by the program to indicate the
category of error that occurred (for example; media, tape drive, tape control).
ERROR CODE = x = 0
= 1
=2
=3 =4
Error while not accessing a tape data set. Error while processing a label for input. Error while processing a label for output. Error while reading from an opened data set. .Error while writing to an opened data set.
= nn
Translated tape adapter return code (TARC) (in decimal)
The TARC is derived from the last two digits of the
adapter return code (ARC) returned by the FDM. The
TARC and the ARC are the same except when the
ARC= 6X or EX. Then the ARC translates into 4X and 5X respectively. See TA333 for list of TARCs.
Refer to the OPCX General Failure Index (Chapter 1, ST210) for associated action plan.
(TA&OO-TA620)
6·TA-83
SY27-2521-3 This page intentionally left blank.
5-TA-64
Appendix A. Hexadecimal-to-Binary Conversion
SY27-2521-3
A-1
SY27·2521-3
A-2
Appendix A. Hexadecimal-to-Binary Conversion
Hexadecimal messages consist of two to four hex values. Use the following chart to convert the hex value to a binary bit value:
Hex Value
Binary Bits
0123 4567
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
c
1100
D
1101
E
1110
F
1111
Two hex values equal one byte of status or sense information. For example: Status byte= 3A (hex).
Status Byte
0
234 5 6 7
Hex Representation
3
A
Binary Bits
0 0
0
0
Active bits are 2, 3, 4, and 6.
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