Device Page Erase Size ( Instructions ) Program Flash Memory (Kbytes) RAM (Kbyte) Remappable Peripherals I 2 16-Bit/32-Bit Timers Input Capture Output Compare UART C CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators CTMU PTG I/O Pins Pins Packages SPI (2) ECAN™ Technology External Interrupts (3) PIC24EP32GP202 512 32 4
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, Op Amps and Advanced Analog
Operating Conditions
· 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS · 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS · 3.0V to 3.6V, -40°C to +150°C, DC to 40 MIPS
Core: 16-Bit dsPIC33E/PIC24E CPU
· Code Efficient (C and Assembly) Architecture · Two 40-Bit Wide Accumulators · Single Cycle (MAC/MPY) with Dual Data Fetch · Single-Cycle, Mixed-Sign MUL plus Hardware Divide · 32-Bit Multiply Support
Clock Management
· 1.0% Internal Oscillator · Programmable PLLs and Oscillator Clock Sources · Fail-Safe Clock Monitor (FSCM) · Independent Watchdog Timer (WDT) · Fast Wake-up and Start-up
Power Management
· Low-Power Management modes (Sleep, Idle, Doze) · Integrated Power-on Reset and Brown-out Reset · 0.6 mA/MHz Dynamic Current (typical) · 30 µA IPD Current (typical)
High-Speed PWM
· Up to Three PWM Pairs with Independent Timing · Dead Time for Rising and Falling Edges · 7.14 ns PWM Resolution · PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting - BLDC, PMSM, ACIM, SRM · Programmable Fault Inputs · Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
· ADC module: - Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H - Six analog inputs on 28-pin devices and up to 16 analog inputs on 64-pin devices
· Flexible and Independent ADC Trigger Sources · Up to Three Op Amp/Comparators with
Direct Connection to the ADC module: - Additional dedicated comparator - Programmable references with 32 voltage points · Charge Time Measurement Unit (CTMU): - Supports mTouch® capacitive touch sensing - Provides high-resolution time measurement (1 ns) - On-chip temperature measurement
Timers/Output Compare/Input Capture
· 12 General Purpose Timers: - Five 16-bit and up to two 32-bit timers/counters - Four Output Compare (OC) modules, configurable as timers/counters - PTG module with two configurable timers/counters - 32-bit Quadrature Encoder Interface (QEI) module, configurable as a timer/counter
· Four Input Capture (IC) modules · Peripheral Pin Select (PPS) to allow Function Remap · Peripheral Trigger Generator (PTG) for Scheduling
Complex Sequences
Communication Interfaces
· Two UART modules (17.5 Mbps): - With support for LIN/J2602 protocols and IrDA®
· Two Four-Wire SPI modules (15 Mbps) · ECANTM module (1 Mbaud) CAN 2.0B Support · Two I2C modules (up to 1 Mbaud) with SMBus Support · PPS to allow Function Remap · Programmable Cyclic Redundancy Check (CRC)
Direct Memory Access (DMA)
· 4-Channel DMA with User-Selectable Priority Arbitration · UART, SPI, ADC, ECAN, IC, OC and Timers
Input/Output
· Sink/Source 12 mA or 6 mA, Pin-Specific for Standard VOH/VOL, Up to 22 or 14 mA, respectively for Non-Standard VOH1
· 5V Tolerant Pins · Peripheral Pin Select (PPS) to allow Digital Function
Remapping · Selectable Open-Drain, Pull-ups and Pull-Downs · Up to 5 mA Overvoltage Clamp Current · Change Notification Interrupts on All I/O Pins
Qualification and Class B Support
· AEC-Q100 REVG (Grade 1, -40°C to +125°C) · AEC-Q100 REVG (Grade 0, -40°C to +150°C) · Class B Safety Library, IEC 60730
Debugger Development Support
· In-Circuit and In-Application Programming · Two Program and Two Complex Data Breakpoints · IEEE 1149.2 Compatible (JTAG) Boundary Scan · Trace and Run-Time Watch
2011-2020 Microchip Technology Inc.
DS70000657J-page 1
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1 (General Purpose Families) and Table 2 (Motor Control Families). Their pinout diagrams appear on the following pages.
TABLE 1:
dsPIC33EPXXXGP50X and PIC24EPXXXGP20X GENERAL PURPOSE FAMILIES
Remappable Peripherals
Device
Page Erase Size (Instructions) Program Flash Memory (Kbytes)
RAM (Kbyte) 16-Bit/32-Bit Timers
Input Capture Output Compare
UART SPI(2) ECANTM Technology External Interrupts(3)
I2C CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators
CTMU PTG I/O Pins Pins Packages
PIC24EP32GP202
512 32 4
PIC24EP64GP202
1024 64 8
SPDIP,
PIC24EP128GP202
1024 128 16 5
4
4
2
2--3
2
1
6 2/3(1) Yes Yes 21
28
SOIC, SSOP(4),
PIC24EP256GP202 1024 256 32
QFN-S
PIC24EP512GP202 1024 512 48
PIC24EP32GP203 PIC24EP64GP203
512 32 4 1024 64 8
5
4
4
2
2--3
2
1
8
2/4 Yes Yes 25 36
VTLA, UQFN
PIC24EP32GP204
512 32 4
PIC24EP64GP204
1024 64 8
VTLA(4),
PIC24EP128GP204
1024 128 16 5
4
4
2
2--3
2
1
9
3/4 Yes Yes 35
44/ 48
TQFP, QFN,
PIC24EP256GP204 1024 256 32
UQFN
PIC24EP512GP204 1024 512 48
PIC24EP64GP206
1024 64 8
PIC24EP128GP206 PIC24EP256GP206
1024 128 16 1024 256 32
5
4
4
2
2--3
2
1
16 3/4 Yes Yes 53 64
TQFP, QFN
PIC24EP512GP206 1024 512 48
dsPIC33EP32GP502 512 32 4
dsPIC33EP64GP502 1024 64 8
SPDIP,
dsPIC33EP128GP502 1024 128 16 5
4
4
2
2
1
3
2
1
6 2/3(1) Yes Yes 21
28
SOIC, SSOP(4),
dsPIC33EP256GP502 1024 256 32
QFN-S
dsPIC33EP512GP502 1024 512 48
dsPIC33EP32GP503 512 32 4 dsPIC33EP64GP503 1024 64 8
5
4
4
2
2
1
3
2
1
8
2/4 Yes Yes 25 36
VTLA, UQFN
dsPIC33EP32GP504 512 32 4
dsPIC33EP64GP504 1024 64 8
VTLA(4),
dsPIC33EP128GP504 1024 128 16 5
4
4
2
2
1
3
2
1
9
3/4 Yes Yes 35
44/ 48
TQFP, QFN,
dsPIC33EP256GP504 1024 256 32
UQFN
dsPIC33EP512GP504 1024 512 48
dsPIC33EP64GP506 1024 64 8
dsPIC33EP128GP506 1024 128 16 dsPIC33EP256GP506 1024 256 32
5
4
4
2
2
1
3
2
1
16 3/4 Yes Yes 53 64
TQFP, QFN
dsPIC33EP512GP506 1024 512 48
Note 1: 2: 3: 4:
On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 "Op Amp/Comparator Module" for details. Only SPI2 is remappable. INT0 is not remappable. The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
DS70000657J-page 2
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 2:
dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL FAMILIES
Remappable Peripherals
Device
Page Erase Size (Instructions) Program Flash Memory (Kbytes)
RAM (Kbytes) 16-Bit/32-Bit Timers
Input Capture Output Compare Motor Control PWM(4)
(Channels) Quadrature Encoder Interface
UART SPI(2) ECANTM Technology External Interrupts(3)
I2C CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators
CTMU PTG I/O Pins Pins Packages
PIC24EP32MC202
512 32 4
PIC24EP64MC202 1024 64 8
SPDIP,
PIC24EP128MC202 1024 128 16 5 4 4
6
1
2
2--3
2
1
6
2/3(1) Yes Yes 21
28
SOIC, SSOP(5),
PIC24EP256MC202 1024 256 32
QFN-S
PIC24EP512MC202 1024 512 48
PIC24EP32MC203 PIC24EP64MC203
512 32 4 1024 64 8
5
4
4
6
1
2
2--
3
2
1
8
2/4 Yes Yes 25 36
VTLA, UQFN
PIC24EP32MC204
512 32 4
PIC24EP64MC204 1024 64 8
VTLA(5),
PIC24EP128MC204 1024 128 16 5 4 4
6
1
2
2--
3
2
1
9
3/4
Yes Yes 35
44/ 48
TQFP, QFN,
PIC24EP256MC204 1024 256 32
UQFN
PIC24EP512MC204 1024 512 48
PIC24EP64MC206 1024 64 8
PIC24EP128MC206 1024 128 16 PIC24EP256MC206 1024 256 32 5 4 4
6
1
2
2--
3
2
1
16
3/4 Yes Yes 53 64
TQFP, QFN
PIC24EP512MC206 1024 512 48
dsPIC33EP32MC202 512 32 4
dsPIC33EP64MC202 1024 64 8
SPDIP,
dsPIC33EP128MC202 1024 128 16 5 4 4
6
1
2
2--3
2
1
6
2/3(1) Yes Yes 21
28
SOIC, SSOP(5),
dsPIC33EP256MC202 1024 256 32
QFN-S
dsPIC33EP512MC202 1024 512 48
dsPIC33EP32MC203 512 32 4 dsPIC33EP64MC203 1024 64 8
5
4
4
6
1
2
2--
3
2
1
8
2/4 Yes Yes 25 36
VTLA, UQFN
dsPIC33EP32MC204 512 32 4
dsPIC33EP64MC204 1024 64 8
VTLA(5),
dsPIC33EP128MC204 1024 128 16 5 4 4
6
1
2
2--
3
2
1
9
3/4
Yes Yes 35
44/ 48
TQFP, QFN,
dsPIC33EP256MC204 1024 256 32
UQFN
dsPIC33EP512MC204 1024 512 48
dsPIC33EP64MC206 1024 64 8
dsPIC33EP128MC206 1024 128 16 dsPIC33EP256MC206 1024 256 32
5
4
4
6
1
2
2--
3
2
1
16
3/4 Yes Yes 53 64
TQFP, QFN
dsPIC33EP512MC206 1024 512 48
dsPIC33EP32MC502 512 32 4
dsPIC33EP64MC502 1024 64 8
SPDIP,
dsPIC33EP128MC502 1024 128 16 5 4 4
6
1
2
2
1
3
2
1
6
2/3(1) Yes Yes 21
28
SOIC, SSOP(5),
dsPIC33EP256MC502 1024 256 32
QFN-S
dsPIC33EP512MC502 1024 512 48
dsPIC33EP32MC503 512 32 4 dsPIC33EP64MC503 1024 64 8
5
4
4
6
1
2
2
1
3
2
1
8
2/4 Yes Yes 25 36
VTLA, UQFN
Note 1: 2: 3: 4: 5:
On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 "Op Amp/Comparator Module" for details. Only SPI2 is remappable. INT0 is not remappable. Only the PWM Faults are remappable. The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
2011-2020 Microchip Technology Inc.
DS70000657J-page 3
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 2:
dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL FAMILIES (CONTINUED)
Remappable Peripherals
Device
Page Erase Size (Instructions) Program Flash Memory (Kbytes)
RAM (Kbytes) 16-Bit/32-Bit Timers
Input Capture Output Compare Motor Control PWM(4)
(Channels) Quadrature Encoder Interface
UART SPI(2) ECANTM Technology External Interrupts(3)
I2C CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators
CTMU PTG I/O Pins Pins Packages
dsPIC33EP32MC504 512 32 4
dsPIC33EP64MC504 1024 64 8
VTLA(5),
dsPIC33EP128MC504 1024 128 16 5 4 4
6
1
2
2
1
3
2
1
9
3/4
Yes Yes 35
44/ 48
TQFP, QFN,
dsPIC33EP256MC504 1024 256 32
UQFN
dsPIC33EP512MC504 1024 512 48
dsPIC33EP64MC506 1024 64 8
dsPIC33EP128MC506 1024 128 16 dsPIC33EP256MC506 1024 256 32 5 4 4
6
1
2
2
1
3
2
1
16
3/4 Yes Yes 53 64
TQFP, QFN
dsPIC33EP512MC506 1024 512 48
Note 1: 2: 3: 4: 5:
On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 "Op Amp/Comparator Module" for details. Only SPI2 is remappable. INT0 is not remappable. Only the PWM Faults are remappable. The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
DS70000657J-page 4
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1,2)
= Pins are up to 5V tolerant
MCLR 1 AN0/OA2OUT/RA0 2
AN1/C2IN1+/RA1 3 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 PGEC1/AN4/C1IN1+/RPI34/RB2 6 PGED1/AN5/C1IN1-/RP35/RB3 7 VSS 8 OSC1/CLKI/RA2 9 OSC2/CLKO/RA3 10 RP36/RB4 11 CVREF2O/RP20/T1CK/RA4 12 VDD 13 PGED2/ASDA2/RP37/RB5 14
dsPIC33EPXXXGP502 PIC24EPXXXGP202
28 AVDD 27 AVSS 26 RPI47/T5CK/RB15 25 RPI46/T3CK/RB14 24 RPI45/CTPLS/RB13 23 RPI44/RB12 22 TDI/RP43/RB11 21 TDO/RP42/RB10 20 VCAP 19 VSS 18 TMS/ASDA1/SDI1/RP41/RB9(3) 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8 16 SCK1/RP39/INT0/RB7 15 PGEC2/ASCL2/RP38/RB6
MCLR 1 AN0/OA2OUT/RA0 2
AN1/C2IN1+/RA1 3 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 PGEC1/AN4/C1IN1+/RPI34/RB2 6 PGED1/AN5/C1IN1-/RP35/RB3 7 VSS 8 OSC1/CLKI/RA2 9 OSC2/CLKO/RA3 10 FLT32/RP36/RB4 11 CVREF2O/RP20/T1CK/RA4 12 VDD 13 PGED2/ASDA2/RP37/RB5 14
dsPIC33EPXXXMC202/502 PIC24EPXXXMC202
28 AVDD 27 AVSS 26 RPI47/PWM1L/T5CK/RB15 25 RPI46/PWM1H/T3CK/RB14 24 RPI45/PWM2L/CTPLS/RB13 23 RPI44/PWM2H/RB12 22 TDI/RP43/PWM3L/RB11 21 TDO/RP42/PWM3H/RB10 20 VCAP 19 VSS 18 TMS/ASDA1/SDI1/RP41/RB9(3) 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8 16 SCK1/RP39/INT0/RB7 15 PGEC2/ASCL2/RP38/RB6
Note 1: 2: 3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 5
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
28-Pin QFN-S(1,2,3)
= Pins are up to 5V tolerant
AN1/C2IN1+/RA1 AN0/OA2OUT/RA0 MCLR AVDD AVSS RPI47/T5CK/RB15 RPI46/T3CK/RB14
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 PGEC1/AN4/C1IN1+/RPI34/RB2 PGED1/AN5/C1IN1-/RP35/RB3 VSS OSC1/CLKI/RA2 OSC2/CLKO/RA3
28 27 26 25 24 23 22
1
21
2
20
3
19
4
dsPIC33EPXXXGP502 PIC24EPXXXGP202
18
5
17
6
16
7
15
8 9 10 11 12 13 14
RPI45/CTPLS/RB13 RPI44/RB12 TDI/RP43/RB11 TDO/RP42/RB10 VCAP VSS TMS/ASDA1/SDI1/RP41/RB9(4)
RP36/RB4 CVREF2O/RP20/T1CK/RA4
VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6
SCK1/RP39/INT0/RB7 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 6
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
28-Pin QFN-S(1,2,3)
= Pins are up to 5V tolerant
AN1/C2IN1+/RA1 AN0/OA2OUT/RA0 MCLR AVDD AVSS RPI47/PWM1L/T5CK/RB15 RPI46/PWM1H/T3CK/RB14
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 PGEC1/AN4/C1IN1+/RPI34/RB2 PGED1/AN5/C1IN1-/RP35/RB3 VSS OSC1/CLKI/RA2 OSC2/CLKO/RA3
28 27 26 25 24 23 22
1
21
2
20
3
19
4
dsPIC33EPXXXMC202/502 PIC24EPXXXMC202
18
5
17
6
16
7
15
8 9 10 11 12 13 14
RPI45/PWM2L/CTPLS/RB13 RPI44/PWM2H/RB12 TDI/RP43/PWM3L/RB11 TDO/RP42/PWM3H/RB10 VCAP VSS TMS/ASDA1/SDI1/RP41/RB9(4)
FLT32/RP36/RB4 CVREF2O/RP20/T1CK/RA4
VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6
SCK1/RP39/INT0/RB7 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 7
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
36-Pin UQFN(1,2,3)
= Pins are up to 5V tolerant
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 AN1/C2IN1+/RA1 AN0/OA2OUT/RA0 MCLR AVDD AVSS RPI47/T5CK/RB15 RPI46/T3CK/RB14
36 35 34 33 32 31 30 29 28
PGEC1/AN4/C1IN1+/RPI34/RB2 PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0 AN7/C3IN1-/C4IN1-/RC1 VDD VSS OSC1/CLKI/RA2 OSC2/CLKO/RA3 SDA2/RPI24/RA8
1
27
2
26
3
dsPIC33EP32GP503
25
4
dsPIC33EP64GP503
24
5
PIC24EP32GP203
23
6
PIC24EP64GP203
22
7
21
8
20
9
19
10 11 12 13 14 15 16 17 18
RPI45/CTPLS/RB13 RPI44/RB12 TDI/RP43/RB11 TDO/RP42/RB10 VDD VCAP VSS RP56/RC8 TMS/ASDA1/SDI1/RP41/RB9(4)
SCL2/RP36/RB4 CVREF2O/RP20/T1CK/RA4
VSS VDD VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6 SCK1/RP39/INT0/RB7 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information. If the op amp is selected when OPMODE (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used. There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 8
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
36-Pin UQFN(1,2,3)
= Pins are up to 5V tolerant
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 AN1/C2IN1+/RA1 AN0/OA2OUT/RA0 MCLR AVDD AVSS RPI47/PWM/1L/T5CK/RB15 RPI46/PWM1H/T3CK/RB14
36 35 34 33 32 31 30 29 28
PGEC1/AN4/C1IN1+/RPI34/RB2 PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0 AN7/C3IN1-/C4IN1-/RC1 VDD VSS OSC1/CLKI/RA2 OSC2/CLKO/RA3 SDA2/RPI24/RA8
1
27
2
26
3
25
dsPIC33EP32MC203/503
4 dsPIC33EP64MC203/503 24
5
PIC24EP32MC203
23
6
PIC24EP64MC203
22
7
21
8
20
9
19
10 11 12 13 14 15 16 17 18
RPI45/PWM2L/CTPLS/RB13 RPI44/PWM2H/RB12 TDI/RP43/PWM3L/RB11 TDO/RP42/PWM3H/RB10 VDD VCAP VSS RP56/RC8 TMS/ASDA1/SDI1/RP41/RB9(4)
FLT32/SCL2/RP36/RB4 CVREF2O/RP20/T1CK/RA4
VSS VDD VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6 SCK1/RP39/INT0/RB7 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information. If the op amp is selected when OPMODE (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used. There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 9
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
36-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 AN1/C2IN1+/RA1 AN0/OA2OUT/RA0 MCLR AVDD AVSS RPI47/T5CK/RB15 RPI46/T3CK/RB14
36 35 34 33 32 31 30 29 28 27 RPI45/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 1
26 RPI44/RB12
PGED1/AN5/C1IN1-/RP35/RB3 2
25 TDI/RP43/RB11
AN6/OA3OUT/C4IN1+/OCFB/RC0 3 AN7/C3IN1-/C4IN1-/RC1 4 VDD 5 VSS 6
dsPIC33EP32GP503 dsPIC33EP64GP503
PIC24EP32GP203 PIC24EP64GP203
24 TDO/RP42/RB10 23 VDD 22 VCAP 21 VSS
OSC1/CLKI/RA2 7
20 RP56/RC8
OSC2/CLKO/RA3 8
19 TMS/ASDA1/SDI1/RP41/RB9(4)
SDA2/RPI24/RA8 9 10 11 12 13 14 15 16 1177 18
SCL2/RP36/RB4 CVREF2O/RP20/T1CK/RA4
VSS VDD VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6 SCK1/RP39/INT0/RB7 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 10
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
36-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 AN1/C2IN1+/RA1 AN0/OA2OUT/RA0 MCLR AVDD AVSS RPI47/PWM1L/T5CK/RB15 RPI46/PWM1H/T3CK/RB14
PGEC1/AN4/C1IN1+/RPI34/RB2 PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0 AN7/C3IN1-/C4IN1-/RC1 VDD VSS OSC1/CLKI/RA2 OSC2/CLKO/RA3 SDA2/RPI24/RA8
36 35 34 33 32 31 30 29 28 27
1
26
2
25
3
24
4
dsPIC33EP32MC203/503 dsPIC33EP64MC203/503
23
5
PIC24EP32MC203
22
6
PIC24EP64MC203 21
7
20
8
19
9 10 11 12 13 14 15 16 17 18
RPI45/PWM2L/CTPLS/RB13 RPI44/PWM2H/RB12 TDI/RP43/PWM3L/RB11 TDO/RP42/PWM3H/RB10 VDD VCAP VSS RP56/RC8 TMS/ASDA1/SDI1/RP41/RB9(4)
FLT32/SCL2/RP36/RB4 CVREF2O/RP20/T1CK/RA4
VSS VDD VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6 SCK1/RP39/INT0/RB7 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 11
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin TQFP(1,2)
= Pins are up to 5V tolerant
44 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 43 RP39/INT0/RB7 42 PGEC2/ASCL2/RP38/RB6 41 PGED2/ASDA2/RP37/RB5 40 VDD 39 VSS 38 SCL1/RPI53/RC5 37 SDA1/RPI52/RC4 36 SCK1/RPI51/RC3 35 SDI1/RPI25/RA9 34 CVREF2O/SDO1/RP20/T1CK/RA4
TMS/ASDA1/RP41/RB9(3)
1
RP54/RC6 2
RP55/RC7 3
RP56/RC8 4
RP57/RC9 5
VSS
6
VCAP
7
RP42/RB10 8
RP43/RB11 9
RPI44/RB12 10
RPI45/CTPLS/RB13 11
dsPIC33EPXXXGP504 PIC24EPXXXGP204
33 SCL2/RP36/RB4
32 SDA2/RPI24/RA8
31 OSC2/CLKO/RA3
30 OSC1/CLKI/RA2
29
VSS
28
VDD
27 AN8/C3IN1+/U1RTS/BCLK1/RC2
26 AN7/C3IN1-/C4IN1-/RC1
25 AN6/OA3OUT/C4IN1+/OCFB/RC0
24 PGED1/AN5/C1IN1-/RP35/RB3
23 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 12 TDI/RA7 13
RPI46/T3CK/RB14 14 RPI47/T5CK/RB15 15
AVSS 16 AVDD 17 MCLR 18 AN0/OA2OUT/RA0 19 AN1/C2IN1+/RA1 20 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 21 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 22
Note 1: 2: 3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 12
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin TQFP(1,2)
= Pins are up to 5V tolerant
44 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 43 RP39/INT0/RB7 42 PGEC2/ASCL2/RP38/RB6 41 PGED2/ASDA2/RP37/RB5 40 VDD 39 VSS 38 SCL1/RPI53/RC5 37 SDA1/RPI52/RC4 36 SCK1/RPI51/RC3 35 SDI1/RPI25/RA9 34 CVREF2O/SDO1/RP20/T1CK/RA4
TMS/ASDA1/RP41/RB9(3) 1 RP54/RC6 2 RP55/RC7 3 RP56/RC8 4 RP57/RC9 5 VSS 6 VCAP 7
RP42/PWM3H/RB10 8 RP43/PWM3L/RB11 9 RPI44/PWM2H/RB12 10 RPI45/PWM2L/CTPLS/RB13 11
dsPIC33EPXXXMC204/504 PIC24EPXXXMC204
33
FLT32/SCL2/RP36/RB4
32
SDA2/RPI24/RA8
31
OSC2/CLKO/RA3
30
OSC1/CLKI/RA2
29
VSS
28
VDD
27
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
26
AN7/C3IN1-/C4IN1-/RC1
25
AN6/OA3OUT/C4IN1+/OCFB/RC0
24
PGED1/AN5/C1IN1-/RP35/RB3
23
PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 12 TDI/RA7 13
RPI46/PWM1H/T3CK/RB14 14 RPI47/PWM1L/T5CK/RB15 15
AVSS 16 AVDD 17 MCLR 18 AN0/OA2OUT/RA0 19 AN1/C2IN1+/RA1 20 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 21 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 22
Note 1: 2: 3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 13
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CVREF2O/SDO1/RP20/T1CK/RA4
44 43 42 41 40 39 38 37 36 35 34 33
TMS/ASDA1/RP41/RB9(4) 1
32
RP54/RC6 2
31
RP55/RC7 3
30
RP56/RC8 4
29
RP57/RC9 5 VSS 6
dsPIC33EPXXXGP504
28
PIC24EPXXXGP204
27
VCAP 7
26
RP42/RB10 8
25
RP43/RB11 9
24
RPI44/RB12 10
23
RPI45/CTPLS/RB13 11 12 13 14 15 16 17 18 19 20 21 22
SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 VSS VDD AN8/C3IN1+/U1RTS/BCLK1/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 TDI/RA7
RPI46/T3CK/RB14 RPI47/T5CK/RB15
AVSS AVDD MCLR AN0/OA2OUT/RA0 AN1/C2IN1+/RA1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 14
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CVREF2O/SDO1/RP20/T1CK/RA4
44 43 42 41 40 39 38 37 36 35 34 33
TMS/ASDA1/RP41/RB9(4) 1
32
RP54/RC6 2
31
RP55/RC7 3
30
RP56/RC8 4
29
RP57/RC9 5 VSS 6
dsPIC33EPXXXMC204/504 28
PIC24EPXXXMC204
27
VCAP 7
26
RP42/PWM3H/RB10 8
25
RP43/PWM3L/RB11 9
24
RPI44/PWM2H/RB12 10
23
RPI45/PWM2L/CTPLS/RB13 11 12 13 14 15 16 17 18 19 20 21 22
FLT32/SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 VSS VDD AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 TDI/RA7
RPI46/PWM1H/T3CK/RB14 RPI47/PWM1L/T5CK/RB15
AVSS AVDD MCLR AN0/OA2OUT/RA0 AN1/C2IN1+/RA1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 15
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin QFN(1,2,3)
= Pins are up to 5V tolerant
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CVREF2O/SDO1/RP20/T1CK/RA4
TMS/ASDA1/RP41/RB9(4) RP54/RC6 RP55/RC7 RP56/RC8 RP57/RC9 VSS VCAP
RP42/RB10 RP43/RB11 RPI44/RB12 RPI45/CTPLS/RB13
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
dsPIC33EPXXXGP504 PIC24EPXXXGP204
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 VSS VDD AN8/C3IN1+/U1RTS/BCLK1/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 TDI/RA7
RPI46/T3CK/RB14 RPI47/T5CK/RB15
AVSS AVDD MCLR AN0/OA2OUT/RA0 AN1/C2IN1+/RA1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 16
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin QFN(1,2,3)
= Pins are up to 5V tolerant
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CVREF2O/SDO1/RP20/T1CK/RA4
TMS/ASDA1/RP41/RB9(4) RP54/RC6 RP55/RC7 RP56/RC8 RP57/RC9 VSS VCAP
RP42/PWM3H/RB10 RP43/PWM3L/RB11 RPI44/PWM2H/RB12 RPI45/PWM2L/CTPLS/RB13
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
dsPIC33EPXXXMC204/504 PIC24EPXXXMC204
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
FLT32/SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 VSS VDD AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 TDI/RA7
RPI46/PWM1H/T3CK/RB14 RPI47/PWM1L/T5CK/RB15
AVSS AVDD MCLR AN0/OA2OUT/RA0 AN1/C2IN1+/RA1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 17
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
48-Pin UQFN(1,2,3)
= Pins are up to 5V tolerant
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 N/C VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CVREF2O/SDO1/RP20/T1CK/RA4
TMS/ASDA1/RP41/RB9(4) RP54/RC6 RP55/RC7 RP56/RC8 RP57/RC9 VSS VCAP N/C
RP42/RB10 RP43/RB11 RPI44/RB12 RPI45/CTPLS/RB13
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
dsPIC33EPXXXGP504
31
7
PIC24EPXXXGP204
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 N/C VSS VDD AN8/C3IN1+/U1RTS/BCLK1/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 TDI/RA7
RPI46/T3CK/RB14 RPI47/T5CK/RB15
AVSS AVDD MCLR
N/C AN0/OA2OUT/RA0
AN1/C2IN1+/RA1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 18
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
48-Pin UQFN(1,2,3)
= Pins are up to 5V tolerant
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 N/C VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CVREF2O/SDO1/RP20/T1CK/RA4
TMS/ASDA1/RP41/RB9(4) RP54/RC6 RP55/RC7 RP56/RC8 RP57/RC9 VSS VCAP N/C
RP42/PWM3H/RB10 RP43/PWM3L/RB11 RPI44/PWM2H/RB12 RPI45/PWM2L/CTPLS/RB13
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
dsPIC33EPXXXMC204/504
31
7
PIC24EPXXXMC204
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
FLT32/SCL2/RP36/RB4 SDA2/RPI24/RA8 OSC2/CLKO/RA3 OSC1/CLKI/RA2 N/C VSS VDD AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0 PGED1/AN5/C1IN1-/RP35/RB3 PGEC1/AN4/C1IN1+/RPI34/RB2
TDO/RA10 TDI/RA7
RPI46/PWM1H/T3CK/RB14 RPI47/PWM1L/T5CK/RB15
AVSS AVDD MCLR
N/C AN0/OA2OUT/RA0
AN1/C2IN1+/RA1 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 19
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
64-Pin TQFP(1,2,3)
= Pins are up to 5V tolerant
64 TDO/RA10 63 RPI45/CTPLS/RB13 62 RPI44/RB12 61 RP43/RB11 60 RP42/RB10 59 RP97/RF1 58 RPI96/RF0 57 VDD 56 VCAP 55 RP57/RC9 54 RD6 53 RD5 52 RP56/RC8 51 RP55/RC7 50 RP54/RC6 49 TMS/ASDA1/RP41/RB9(4)
TDI/RA7 1
RPI46/T3CK/RB14 2 RPI47/T5CK/RB15 3
RP118/RG6 4 RPI119/RG7 5 RP120/RG8 6
MCLR 7 RPI121/RG9 8
VSS 9
VDD 10 AN10/RPI28/RA12 11
AN9/RPI27/RA11 12 AN0/OA2OUT/RA0 13
AN1/C2IN1+/RA1 14 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16
dsPIC33EP64GP506
dsPIC33EP128GP506 dsPIC33EP256GP506 dsPIC33EP512GP506
PIC24EP64GP206
PIC24EP128GP206 PIC24EP256GP206
PIC24EP512GP206
48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 47 RC13 46 RP39/INT0/RB7 45 RPI58/RC10 44 PGEC2/ASCL2/RP38/RB6 43 PGED2/ASDA2/RP37/RB5 42 RD8 41 VSS 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 38 VDD 37 SCL1/RPI53/RC5 36 SDA1/RPI52/RC4 35 SCK1/RPI51/RC3 34 SDI1/RPI25/RA9 33 CVREF2O/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2 17 PGED1/AN5/C1IN1-/RP35/RB3 18 AVDD 19 AVSS 20
AN6/OA3OUT/C4IN1+/OCFB/RC0 21 AN7/C3IN1-/C4IN1-/RC1 22
AN8/C3IN1+/U1RTS/BCLK1/RC2 23 AN11/C1IN2-(3)/U1CTS/RC11 24 VSS 25 VDD 26
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12 27 AN13/C3IN2-(3)/U2CTS/RE13 28 AN14/RPI94/RE14 29 AN15/RPI95/RE15 30 SDA2/RPI24/RA8 31 SCL2/RP36/RB4 32
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 20
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
64-Pin TQFP(1,2,3)
= Pins are up to 5V tolerant
64 TDO/RA10 63 RPI45/PWM2L/CTPLS/RB13 62 RPI44/PWM2H/RB12 61 RP43/PWM3L/RB11 60 RP42/PWM3H/RB10 59 RP97/RF1 58 RPI96/RF0 57 VDD 56 VCAP 55 RP57/RC9 54 RD6 53 RD5 52 RP56/RC8 51 RP55/RC7 50 RP54/RC6 49 TMS/ASDA1/RP41/RB9(4)
TDI/RA7 1
RPI46/PWM1H/T3CK/RB14 2 RPI47/PWM1L/T5CK/RB15 3
RP118/RG6 4 RPI119/RG7 5 RP120/RG8 6
MCLR 7 RPI121/RG9 8
VSS 9 VDD 10 AN10/RPI28/RA12 11 AN9/RPI27/RA11 12 AN0/OA2OUT/RA0 13 AN1/C2IN1+/RA1 14 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16
dsPIC33EP64MC206/506 dsPIC33EP128MC206/506 dsPIC33EP256MC206/506
dsPIC33EP512MC206/506
PIC24EP64MC206 PIC24EP128MC206
PIC24EP256MC206 PIC24EP512MC206
48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
47 RC13
46 RP39/INT0/RB7
45 RPI58/RC10 44 PGEC2/ASCL2/RP38/RB6 43 PGED2/ASDA2/RP37/RB5 42 RD8 41 VSS 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 38 VDD 37 SCL1/RPI53/RC5 36 SDA1/RPI52/RC4 35 SCK1/RPI51/RC3 34 SDI1/RPI25/RA9 33 CVREF2O/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2 17 PGED1/AN5/C1IN1-/RP35/RB3 18 AVDD 19 AVSS 20
AN6/OA3OUT/C4IN1+/OCFB/RC0 21 AN7/C3IN1-/C4IN1-/RC1 22
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 23 AN11/C1IN2-(3)/U1CTS/FLT4/RC11 24 VSS 25 VDD 26
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12 27 AN13/C3IN2-(3)/U2CTS/RE13 28 AN14/RPI94/RE14 29 AN15/RPI95/RE15 30 SDA2/RPI24/RA8 31 FLT32/SCL2/RP36/RB4 32
Note 1: 2: 3: 4:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 21
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
64-Pin QFN(1,2,3,4)
= Pins are up to 5V tolerant
64 TDO/RA10 63 RPI45/CTPLS/RB13 62 RPI44/RB12 61 RP43/RB11 60 RP42/RB10 59 RP97/RF1 58 RPI96/RF0 57 VDD 56 VCAP 55 RP57/RC9 54 RD6 53 RD5 52 RP56/RC8 51 RP55/RC7 50 RP54/RC6 49 TMS/ASDA1/RP41/RB9(5)
TDI/RA7 1 RPI46/T3CK/RB14 2 RPI47/T5CK/RB15 3
RP118/RG6 4 RPI119/RG7 5 RP120/RG8 6
MCLR 7 RPI121/RG9 8
VSS 9 VDD 10 AN10/RPI28/RA12 11 AN9/RPI27/RA11 12 AN0/OA2OUT/RA0 13 AN1/C2IN1+/RA1 14 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16
dsPIC33EP64GP506 dsPIC33EP128GP506
dsPIC33EP256GP506 dsPIC33EP512GP506
PIC24EP64GP206
PIC24EP128GP206 PIC24EP256GP206
PIC24EP512GP206
48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 47 RC13 46 RP39/INT0/RB7 45 RPI58/RC10 44 PGEC2/ASCL2/RP38/RB6 43 PGED2/ASDA2/RP37/RB5 42 RD8 41 VSS 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 38 VDD 37 SCL1/RPI53/RC5 36 SDA1/RPI52/RC4 35 SCK1/RPI51/RC3 34 SDI1/RPI25/RA9 33 CVREF2O/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2 17 PGED1/AN5/C1IN1-/RP35/RB3 18 AVDD 19 AVSS 20
AN6/OA3OUT/C4IN1+/OCFB/RC0 21 AN7/C3IN1-/C4IN1-/RC1 22
AN8/C3IN1+/U1RTS/BCLK1/RC2 23 AN11/C1IN2-(3)/U1CTS/RC11 24 VSS 25 VDD 26
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12 27 AN13/C3IN2-(3)/U2CTS/RE13 28 AN14/RPI94/RE14 29 AN15/RPI95/RE15 30 SDA2/RPI24/RA8 31 SCL2/RP36/RB4 32
Note 1:
2:
3: 4:
5:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
This pin is not available as an input when OPMODE (CMxCON[10]) = 1. The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 22
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
64-Pin QFN(1,2,3,4)
= Pins are up to 5V tolerant
64 TDO/RA10 63 RPI45/PWM2L/CTPLS/RB13 62 RPI44/PWM2H/RB12 61 RP43/PWM3L/RB11 60 RP42/PWM3H/RB10 59 RP97/RF1 58 RPI96/RF0 57 VDD 56 VCAP 55 RP57/RC9 54 RD6 53 RD5 52 RP56/RC8 51 RP55/RC7 50 RP54/RC6 49 TMS/ASDA1/RP41/RB9(5)
TDI/RA7 1
RPI46/PWM1H/T3CK/RB14 2 RPI47/PWM1L/T5CK/RB15 3
RP118/RG6 4 RPI119/RG7 5 RP120/RG8 6
MCLR 7 RPI121/RG9 8
VSS 9
VDD 10 AN10/RPI28/RA12 11
AN9/RPI27/RA11 12 AN0/OA2OUT/RA0 13
AN1/C2IN1+/RA1 14 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16
dsPIC33EP64MC206/506
dsPIC33EP128MC206/506 dsPIC33EP256MC206/506 dsPIC33EP512MC206/506
PIC24EP64MC206 PIC24EP128MC206 PIC24EP256MC206
PIC24EP512MC206
48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 47 RC13 46 RP39/INT0/RB7 45 RPI58/RC10 44 PGEC2/ASCL2/RP38/RB6 43 PGED2/ASDA2/RP37/RB5 42 RD8 41 VSS 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 38 VDD 37 SCL1/RPI53/RC5 36 SDA1/RPI52/RC4 35 SCK1/RPI51/RC3 34 SDI1/RPI25/RA9 33 CVREF2O/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2 17 PGED1/AN5/C1IN1-/RP35/RB3 18 AVDD 19 AVSS 20
AN6/OA3OUT/C4IN1+/OCFB/RC0 21 AN7/C3IN1-/C4IN1-/RC1 22
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 23 AN11/C1IN2-(3)/U1CTS/FLT4/RC11 24 VSS 25 VDD 26
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12 27 AN13/C3IN2-(3)/U2CTS/RE13 28 AN14/RPI94/RE14 29 AN15/RPI95/RE15 30 SDA2/RPI24/RA8 31 FLT32/SCL2/RP36/RB4 32
Note 1:
2:
3: 4:
5:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 "Peripheral Pin Select (PPS)" for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 "I/O Ports" for more information.
This pin is not available as an input when OPMODE (CMxCON[10]) = 1. The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
2011-2020 Microchip Technology Inc.
DS70000657J-page 23
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 27 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers and Microcontrollers......................................................... 31 3.0 CPU ............................................................................................................................................................................................ 37 4.0 Memory Organization ................................................................................................................................................................. 47 5.0 Flash Program Memory ............................................................................................................................................................ 121 6.0 Resets ..................................................................................................................................................................................... 125 7.0 Interrupt Controller ................................................................................................................................................................... 129 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 141 9.0 Oscillator Configuration ............................................................................................................................................................ 155 10.0 Power-Saving Features ............................................................................................................................................................ 165 11.0 I/O Ports ................................................................................................................................................................................... 175 12.0 Timer1 ...................................................................................................................................................................................... 205 13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 209 14.0 Input Capture............................................................................................................................................................................ 215 15.0 Output Compare ....................................................................................................................................................................... 221 16.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) ....................................... 227 17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)........... 251 18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 267 19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 275 20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 283 21.0 Enhanced CAN (ECANTM) Module (dsPIC33EPXXXGP/MC50X Devices Only) ..................................................................... 289 22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 317 23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 323 24.0 Peripheral Trigger Generator (PTG) Module ............................................................................................................................ 339 25.0 Op Amp/Comparator Module ................................................................................................................................................... 357 26.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 375 27.0 Special Features ...................................................................................................................................................................... 381 28.0 Instruction Set Summary .......................................................................................................................................................... 395 29.0 Development Support............................................................................................................................................................... 405 30.0 Electrical Characteristics .......................................................................................................................................................... 407 31.0 High-Temperature Electrical Characteristics ............................................................................................................................ 473 32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 481 33.0 Packaging Information.............................................................................................................................................................. 485 Appendix A: Revision History............................................................................................................................................................. 521 Index ................................................................................................................................................................................................. 533 The Microchip Website....................................................................................................................................................................... 541 Customer Change Notification Service .............................................................................................................................................. 541 Customer Support .............................................................................................................................................................................. 541 Product Identification System............................................................................................................................................................. 543
DS70000657J-page 24
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Website; http://www.microchip.com · Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2011-2020 Microchip Technology Inc.
DS70000657J-page 25
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Referenced Sources
This device data sheet is based on the following individual chapters of the "dsPIC33/PIC24 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature.
Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33EP64MC506 product page of the Microchip website (www.microchip.com) or select a family reference manual section from the following list.
In addition to parameters, features and other documentation, the resulting page provides links to the related family reference manual sections.
· "Introduction" (www.microchip.com/DS70573) · "CPU" (www.microchip.com/DS70359) · "Data Memory" (www.microchip.com/DS70595) · "dsPIC33/PIC24 Program Memory" (www.microchip.com/DS70000613) · "Flash Programming" (www.microchip.com/DS70000609) · "Interrupts" (www.microchip.com/DS70000600) · "Oscillator" (www.microchip.com/DS70580) · "Reset" (www.microchip.com/DS70602) · "Watchdog Timer and Power-Saving Modes" (www.microchip.com/DS70615) · "I/O Ports" (www.microchip.com/DS70000598) · "Timers" (www.microchip.com/DS70362) · "Input Capture with Dedicated Timer" (www.microchip.com/DS70000352) · "Output Compare" (www.microchip.com/DS70000358) · "High-Speed PWM" (www.microchip.com/DS70645) · "Quadrature Encoder Interface (QEI)" (www.microchip.com/DS70000601) · "Analog-to-Digital Converter (ADC)" (www.microchip.com/DS70621) · "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/DS70000582) · "Serial Peripheral Interface (SPI)" (www.microchip.com/DS70005185) · "Inter-Integrated Circuit (I2C)" (www.microchip.com/DS70000195) · "Enhanced Controller Area Network (ECANTM)" (www.microchip.com/DS70353) · "Direct Memory Access (DMA)" (www.microchip.com/DS70348) · "CodeGuardTM Security" (www.microchip.com/DS70634) · "Programming and Diagnostics" (www.microchip.com/DS70608) · "Op Amp/Comparator" (www.microchip.com/DS70000357) · "Programmable Cyclic Redundancy Check (CRC)" (www.microchip.com/DS70346) · "Device Configuration" (www.microchip.com/DS70000618) · "Peripheral Trigger Generator (PTG)" (www.microchip.com/DS70000669) · "Charge Time Measurement Unit (CTMU)" (www.microchip.com/DS70661)
DS70000657J-page 26
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
1.0 DEVICE OVERVIEW
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive resource. To complement the information in this data sheet, refer to the related section of the "dsPIC33/ PIC24 Family Reference Manual", which is available from the Microchip website (www.microchip.com)
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
This document contains device-specific information for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X Digital Signal Controller (DSC) and Microcontroller (MCU) devices.
dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core and peripheral modules. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.
FIGURE 1-1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X BLOCK DIAGRAM
CPU Refer to Figure 3-1 for CPU diagram details.
PORTA 16
PORTB
OSC1/CLKI
Timing Generation
MCLR VDD, VSS AVDD, AVSS
Power-up Timer
Oscillator Start-up Timer POR/BOR
Watchdog Timer
PORTC
PORTD
PORTE 16
PORTF
PTG
Op Amp/ Comparator
ECAN1(2)
ADC
Input Capture
Output Compare
I2C1, I2C2
PORTG
CTMU
QEI1(1)
Peripheral Modules
PWM(1)
Timers
CRC
SPI1, SPI2
UART1, UART2
Remappable Pins
PORTS
Note 1: This feature or peripheral is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. 2: This feature or peripheral is only available on dsPIC33EPXXXGP/MC50X devices.
2011-2020 Microchip Technology Inc.
DS70000657J-page 27
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name(4)
Pin Type
Buffer Type
PPS
Description
AN0-AN15
I Analog No Analog input channels.
CLKI
I
ST/ No External clock source input. Always associated with OSC1 pin function.
CMOS
CLKO
O
-- No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1 OSC2
I
ST/ No Oscillator crystal input. ST buffer when configured in RC mode; CMOS
CMOS
otherwise.
I/O -- No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
REFCLKO
O
-- Yes Reference clock output.
IC1-IC4
I
ST Yes Capture Inputs 1 through 4.
OCFA OCFB OC1-OC4
I
ST Yes Compare Fault A input (for Compare channels).
I
ST No Compare Fault B input (for Compare channels).
O
-- Yes Compare Outputs 1 through 4.
INT0 INT1 INT2
I
ST No External Interrupt 0.
I
ST Yes External Interrupt 1.
I
ST Yes External Interrupt 2.
RA0-RA4, RA7-RA12 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15
I/O ST No PORTB is a bidirectional I/O port.
RC0-RC13, RC15
I/O ST No PORTC is a bidirectional I/O port.
RD5, RD6, RD8
I/O ST No PORTD is a bidirectional I/O port.
RE12-RE15
I/O ST No PORTE is a bidirectional I/O port.
RF0, RF1
I/O ST No PORTF is a bidirectional I/O port.
RG6-RG9
I/O ST No PORTG is a bidirectional I/O port.
T1CK T2CK T3CK T4CK T5CK
I
ST No Timer1 external clock input.
I
ST Yes Timer2 external clock input.
I
ST No Timer3 external clock input.
I
ST No Timer4 external clock input.
I
ST No Timer5 external clock input.
CTPLS CTED1 CTED2
O ST No CTMU pulse output.
I
ST No CTMU External Edge Input 1.
I
ST No CTMU External Edge Input 2.
U1CTS U1RTS U1RX U1TX BCLK1
I
ST No UART1 Clear-to-Send.
O
-- No UART1 Ready-to-Send.
I
ST Yes UART1 receive.
O
-- Yes UART1 transmit.
O
ST No UART1 IrDA® baud clock output.
Legend:
Note 1: 2: 3:
4: 5:
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select
Analog = Analog input O = Output TTL = TTL input buffer
P = Power I = Input
This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
This pin is available on dsPIC33EPXXXGP/MC50X devices only.
This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See Section 16.0 "High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)" for more information.
Not all pins are available in all package variants. See the "Pin Diagrams" section for pin availability.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
DS70000657J-page 28
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name(4)
Pin Type
Buffer Type
PPS
Description
U2CTS U2RTS U2RX U2TX BCLK2
I
ST No UART2 Clear-to-Send.
O
-- No UART2 Ready-to-Send.
I
ST Yes UART2 receive.
O
-- Yes UART2 transmit.
O
ST No UART2 IrDA® baud clock output.
SCK1 SDI1 SDO1 SS1
I/O ST No Synchronous serial clock input/output for SPI1.
I
ST No SPI1 data in.
O
-- No SPI1 data out.
I/O ST No SPI1 slave synchronization or frame pulse I/O.
SCK2 SDI2 SDO2 SS2
I/O ST Yes Synchronous serial clock input/output for SPI2.
I
ST Yes SPI2 data in.
O
-- Yes SPI2 data out.
I/O ST Yes SPI2 slave synchronization or frame pulse I/O.
SCL1 SDA1 ASCL1 ASDA1
I/O ST No Synchronous serial clock input/output for I2C1. I/O ST No Synchronous serial data input/output for I2C1. I/O ST No Alternate synchronous serial clock input/output for I2C1. I/O ST No Alternate synchronous serial data input/output for I2C1.
SCL2
I/O
SDA2
I/O
ASCL2
I/O
ASDA2
I/O
TMS(5)
I
TCK
I
TDI
I
TDO
O
C1RX(2)
I
C1TX(2)
O
FLT1(1), FLT2(1)
I
FLT3(1), FLT4(1)
I
FLT32(1,3)
I
DTCMP1-DTCMP3(1) I
PWM1L-PWM3L(1)
O
PWM1H-PWM3H(1)
O
SYNCI1(1)
I
SYNCO1(1)
O
INDX1(1)
I
HOME1(1)
I
QEA1(1)
I
QEB1(1)
I
CNTCMP1(1)
O
ST No Synchronous serial clock input/output for I2C2. ST No Synchronous serial data input/output for I2C2. ST No Alternate synchronous serial clock input/output for I2C2. ST No Alternate synchronous serial data input/output for I2C2.
ST No JTAG Test mode select pin. ST No JTAG test clock input pin. ST No JTAG test data input pin. -- No JTAG test data output pin.
ST Yes ECAN1 bus receive pin. -- Yes ECAN1 bus transmit pin.
ST Yes PWM Fault Inputs 1 and 2. ST No PWM Fault Inputs 3 and 4. ST No PWM Fault Input 32 (Class B Fault). ST Yes PWM Dead-Time Compensation Inputs 1 through 3. -- No PWM Low Outputs 1 through 3. -- No PWM High Outputs 1 through 3. ST Yes PWM Synchronization Input 1. -- Yes PWM Synchronization Output 1.
ST Yes Quadrature Encoder Index1 pulse input. ST Yes Quadrature Encoder Home1 pulse input. ST Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer
external clock/gate input in Timer mode. ST Yes Quadrature Encoder Phase B input in QEI1 mode. Auxiliary timer
external clock/gate input in Timer mode. -- Yes Quadrature Encoder Compare Output 1.
Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select
Analog = Analog input O = Output TTL = TTL input buffer
P = Power I = Input
Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This pin is available on dsPIC33EPXXXGP/MC50X devices only.
3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See Section 16.0 "High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)" for more information.
4: Not all pins are available in all package variants. See the "Pin Diagrams" section for pin availability.
5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
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TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name(4)
Pin Type
Buffer Type
PPS
Description
C1IN1C1IN2C1IN1+ OA1OUT C1OUT
I Analog No Op Amp/Comparator 1 Negative Input 1.
I Analog No Comparator 1 Negative Input 2.
I Analog No Op Amp/Comparator 1 Positive Input 1.
O Analog No Op Amp 1 output.
O
-- Yes Comparator 1 output.
C2IN1C2IN2C2IN1+ OA2OUT C2OUT
I Analog No Op Amp/Comparator 2 Negative Input 1.
I Analog No Comparator 2 Negative Input 2.
I Analog No Op Amp/Comparator 2 Positive Input 1.
O Analog No Op Amp 2 output.
O
-- Yes Comparator 2 output.
C3IN1C3IN2C3IN1+ OA3OUT C3OUT
I Analog No Op Amp/Comparator 3 Negative Input 1.
I Analog No Comparator 3 Negative Input 2.
I Analog No Op Amp/Comparator 3 Positive Input 1.
O Analog No Op Amp 3 output.
O
-- Yes Comparator 3 output.
C4IN1C4IN1+ C4OUT
I Analog No Comparator 4 Negative Input 1.
I Analog No Comparator 4 Positive Input 1.
O
-- Yes Comparator 4 output.
CVREF1O CVREF2O
PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3
O Analog No Op amp/comparator voltage reference output. O Analog No Op amp/comparator voltage reference divided by 2 output.
I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1.
I
ST No Clock input pin for Programming/Debugging Communication Channel 1.
I/O ST No Data I/O pin for Programming/Debugging Communication Channel 2.
I
ST No Clock input pin for Programming/Debugging Communication Channel 2.
I/O ST No Data I/O pin for Programming/Debugging Communication Channel 3.
I
ST No Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD
P
P No Positive supply for analog modules. This pin must be connected at all
times.
AVSS
P
P No Ground reference for analog modules. This pin must be connected at all
times.
VDD
P
-- No Positive supply for peripheral logic and I/O pins.
VCAP
P
-- No CPU logic filter capacitor connection.
VSS
P
-- No Ground reference for logic and I/O pins.
VREF+
I Analog No Analog voltage reference (high) input.
VREF-
I Analog No Analog voltage reference (low) input.
Legend:
Note 1: 2: 3:
4: 5:
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select
Analog = Analog input O = Output TTL = TTL input buffer
P = Power I = Input
This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
This pin is available on dsPIC33EPXXXGP/MC50X devices only.
This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See Section 16.0 "High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)" for more information.
Not all pins are available in all package variants. See the "Pin Diagrams" section for pin availability.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS AND MICROCONTROLLERS
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "dsPIC33/PIC24 Family Reference Manual", which is available from the Microchip website (www.microchip.com)
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
2.1 Basic Connection Requirements
Getting started with the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X
and
PIC24EPXXXGP/MC20X families requires attention
to a minimal set of device pin connections before
proceeding with development. The following is a list
of pin names, which must always be connected:
· All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors")
· All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 "Decoupling Capacitors")
· VCAP (see Section 2.3 "CPU Logic Filter Capacitor Connection (VCAP)")
· MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin")
· PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins")
· OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 "External Oscillator Pins")
Additionally, the following pins may be required:
· VREF+/VREF- pins are used when external voltage reference for the ADC module is implemented
Note:
The AVDD and AVSS pins must be connected, independent of the ADC voltage reference source.
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required.
Consider the following criteria when using decoupling capacitors:
· Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended to use ceramic capacitors.
· Placement on the Printed Circuit Board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.
· Handling high-frequency noise: If the board is experiencing high-frequency noise, above tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.
· Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB track inductance.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 2-1:
RECOMMENDED MINIMUM CONNECTION
VDD
10 µF Tantalum
0.1 µF Ceramic
VCAP VDD VSS
R R1
MCLR
C dsPIC33E/PIC24E
VSS
VDD
0.1 µF
VDD
Ceramic
VSS 0.1 µF Ceramic
AVDD AVSS VDD VSS
L1(1)
0.1 µF Ceramic
0.1 µF Ceramic
Note 1:
As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor capacity greater than 10 mA.
Where:
f = -F----C-2--N----Vf = -----------1------------
2 LC
(i.e., ADC conversion rate/2)
L
=
---2-------f1------C-----
2
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF.
2.3 CPU Logic Filter Capacitor Connection (VCAP)
A low-ESR (< 1 Ohm) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD and must have a capacitor greater than 4.7 µF (10 µF is recommended), 16V connected to ground. The type can be ceramic or tantalum. See Section 30.0 "Electrical Characteristics" for additional information.
The placement of this capacitor should be close to the VCAP pin. It is recommended that the trace length not exceeds one-quarter inch (6 mm). See Section 27.3 "On-Chip Voltage Regulator" for details.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions:
· Device Reset · Device Programming and Debugging.
During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is recommended that the capacitor, C, be isolated from the MCLR pin during programming and debugging operations.
Place the components as shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
VDD
EXAMPLE OF MCLR PIN CONNECTIONS
R(1) R1(2)
JP C
MCLR dsPIC33E/PIC24E
Note 1: 2:
R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met.
R1 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2.5 ICSP Pins
The PGECx and PGEDx pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin Voltage Input High (VIH) and Voltage Input Low (VIL) requirements.
Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® PICkitTM 3, MPLAB ICD 3 or MPLAB REAL ICETM.
For more information on MPLAB ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website.
· "Using MPLAB® ICD 3" (poster) DS51765 · "MPLAB® ICD 3 Design Advisory" DS51764 · "MPLAB® REAL ICETM In-Circuit Emulator User's
Guide" DS51616 · "Using MPLAB® REAL ICETM In-Circuit Emulator"
(poster) DS51749
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator. For details, see Section 9.0 "Oscillator Configuration" for details.
The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Main Oscillator Guard Ring Guard Trace
Oscillator Pins
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2.7 Oscillator Value Conditions on Device Start-up
If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to a certain frequency (see Section 9.0 "Oscillator Configuration") to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed.
Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLFBD, to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word.
2.8 Unused I/Os
Unused I/O pins should be configured as outputs and driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS and unused pins, and drive the output to logic low.
2.9 Application Examples
· Induction heating · Uninterruptable Power Supplies (UPS) · DC/AC inverters · Compressor motor control · Washing machine 3-phase motor control · BLDC motor control · Automotive HVAC, cooling fans, fuel pumps · Stepper motor control · Audio and fluid sensor monitoring · Camera lens focus and stability control · Speech (playback, hands-free kits, answering
machines, VoIP) · Consumer audio · Industrial and building control (security systems
and access control) · Barcode reading · Networking: LAN switches, gateways · Data storage device management · Smart cards and smart card readers
Examples of typical application connections are shown in Figure 2-4 through Figure 2-8.
FIGURE 2-4:
BOOST CONVERTER IMPLEMENTATION
VINPUT
IPFC
VOUTPUT
k1
k2
FET Driver
ADC Channel
Op Amp/ PWM Comparator Output
dsPIC33EP
k3 ADC Channel
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 2-5:
SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
12V Input
5V Output I5V
k7 ADC Channel
PWM PWM
FET Driver
k1
k2
Op Amp/
ADC
Comparator Channel
dsPIC33EP
FIGURE 2-6:
MULTIPHASE SYNCHRONOUS BUCK CONVERTER
12V Input
3.3V Output
k6
k7
FET Driver
FET Driver
ADC Channel
PWM PWM PWM PWM
PWM PWM
FET Driver
Op Amp/Comparator
k3
dsPIC33EP
Op Amp/Comparator
k4
Op Amp/Comparator
k5
ADC Channel
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 2-7:
INTERLEAVED PFC
|VAC|
VOUT+
k4 VAC
k1 FET Driver
k2 FET Driver
k3 VOUT-
Op Amp/Comparator ADC Channel
PWM Op Amp/ PWM Op Amp/
ADC
Comparator
Comparator Channel
dsPIC33EP
FIGURE 2-8:
BEMF VOLTAGE MEASURED USING THE ADC MODULE
dsPIC33EP/PIC24EP
PWM3H PWM3L PWM2H PWM2L PWM1H PWM1L
FLTx
Fault
BLDC
3-Phase Inverter
R49 R41 R34 R36 R44
AN2
R52
Demand
AN3
AN4
AN5 Phase Terminal Voltage Feedback
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.0 CPU
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "CPU" (www.microchip.com/DS70359) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for digital signal processing. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space.
An instruction prefetch mechanism helps maintain throughput and provides predictable execution. Most instructions execute in a single-cycle effective execution rate, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction, PSV accesses and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
3.1 Registers
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices have sixteen, 16-bit Working registers in the programmer's model. Each of the Working registers can act as a data, address or address offset register. The 16th Working register (W15) operates as a Software Stack Pointer (SSP) for interrupts and calls.
3.2 Instruction Set
The instruction set for dsPIC33EPXXXGP50X and dsPIC33EPXXXMC20X/50X devices has two classes of instructions: the MCU class of instructions and the DSP class of instructions. The instruction set for PIC24EPXXXGP/MC20X devices has the MCU class of instructions only and does not support DSP instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many addressing modes and was designed for optimum C compiler efficiency.
3.3 Data Space Addressing
The base Data Space can be addressed as 64 Kbytes (32K words).
The Data Space includes two ranges of memory, referred to as X and Y data memory. Each memory range is accessible through its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear Data Space. On dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices, certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y Data Spaces have memory locations that are device-specific, and are described further in the data memory maps in Section 4.2 "Data Address Space".
The upper 32 Kbytes of the Data Space memory map can optionally be mapped into Program Space (PS) at any 32-Kbyte aligned program word boundary. The Program-to-Data Space mapping feature, known as Program Space Visibility (PSV), lets any instruction access Program Space as if it were Data Space. Moreover, the Base Data Space address is used in conjunction with a Read or Write Page register (DSRPAG or DSWPAG) to form an Extended Data Space (EDS) address. The EDS can be addressed as 8M words or 16 Mbytes. Refer to the "Data Memory" (www.microchip.com/DS70595) and "dsPIC33/PIC24 Program Memory" (www.microchip.com/DS70000613) sections in the "dsPIC33/PIC24 Family Reference Manual" for more details on EDS, PSV and table accesses.
On the dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices, overhead-free circular buffers (Modulo Addressing) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. The X AGU Circular Addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data re-ordering for radix-2 FFT algorithms. PIC24EPXXXGP/MC20X devices do not support Modulo and Bit-Reversed Addressing.
3.4 Addressing Modes
The CPU supports these addressing modes:
· Inherent (no operand) · Relative · Literal · Memory Direct · Register Direct · Register Indirect
Each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. As many as six addressing modes are supported for each instruction.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 3-1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X CPU BLOCK DIAGRAM
X Address Bus
Y Data Bus(1)
X Data Bus
Interrupt Controller
24
PSV and Table
Data Access 24 Control Block
8
16 16 16 Data Latch
16 Data Latch
16
Y Data RAM(1)
X Data RAM
Address
Address
16
24
Latch
Latch
24 Address Latch
PCU PCH PCL
Program Counter
Stack Control Logic
Loop Control Logic
Y Address Bus
16
16
X RAGU
16
X WAGU
Program Memory
Y AGU(1)
Data Latch
16
16
EA MUX
16 24
24
ROM Latch IR
Literal Data
16
16 x 16
W Register Array
16
16 16
DSP Engine(1)
Divide Support
Control Signals to Various Blocks
Instruction Decode and
Control
16-Bit ALU
16
16
Power, Reset and Oscillator
Modules
Ports
Peripheral Modules
Note 1: This feature is not available on PIC24EPXXXGP/MC20X devices.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.5 Programmer's Model
The
programmer's
model
for
the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X is shown in Figure 3-2.
All registers in the programmer's model are memory-
mapped and can be manipulated directly by instructions.
Table 3-1 lists a description of each register.
In addition to the registers contained in the programmer's model, the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X devices contain control registers for Modulo Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only), Bit-Reversed Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only) and interrupts. These registers are described in subsequent sections of this document.
All registers associated with the programmer's model are memory-mapped, as shown in Table 4-1.
TABLE 3-1: PROGRAMMER'S MODEL REGISTER DESCRIPTIONS
Register(s) Name
Description
W0 through W15
Working Register Array
ACCA, ACCB
40-Bit DSP Accumulators
PC
23-Bit Program Counter
SR
ALU and DSP Engine STATUS Register
SPLIM
Stack Pointer Limit Value Register
TBLPAG
Table Memory Page Address Register
DSRPAG
Extended Data Space (EDS) Read Page Register
DSWPAG
Extended Data Space (EDS) Write Page Register
RCOUNT DCOUNT(1) DOSTARTH(1,2), DOSTARTL(1,2) DOENDH(1), DOENDL(1)
REPEAT Loop Counter Register DO Loop Counter Register DO Loop Start Address Register (High and Low) DO Loop End Address Register (High and Low)
CORCON
Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1: This register is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: The DOSTARTH and DOSTARTL registers are read-only.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 3-2:
PROGRAMMER'S MODEL
DSP Operand Registers DSP Address Registers PUSH.s and POP.s Shadows
D15
D0
W0 (WREG)
W1
W2 W3
W4
W5
W6
W7
W8
W9 W10 W11
W12 W13
Frame Pointer/W14 Stack Pointer/W15 0
Nested DO Stack
SPLIM
0
Working/Address Registers Stack Pointer Limit
DSP Accumulators(1)
PC23 0
23 0 23 0
AD39 ACCA ACCB
AD31
AD15
AD0
PC0 0
7
0
TBLPAG
9
0
DSRPAG
8
0
DSWPAG
15
0
RCOUNT
15
0
DCOUNT
0
DOSTART
0
Program Counter Table Memory Page Address Extended Data Space Read Page Extended Data Space Write Page REPEAT Loop Counter DO Loop Counter and Stack(1) DO Loop Start Address and Stack(1)
DOEND
0
0
DO Loop End Address and Stack(1)
15 CORCON
0 CPU Core Control Register
SRL OA(1) OB(1) SA(1) SB(1) OAB(1) SAB(1) DA(1) DC IPL2 IPL1 IPL0 RA N OV Z C
STATUS Register
Note 1: This feature or bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.6 CPU Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
3.6.1 KEY RESOURCES
· "CPU" (www.microchip.com/DS70359) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
2011-2020 Microchip Technology Inc.
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3.7 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R/W-0 OA(1)
bit 15
R/W-0 OB(1)
R/W-0 SA(1,4)
R/W-0 SB(1,4)
R/W-0(2,3)
R/W-0(2,3) R/W-0(2,3)
R-0
IPL2
IPL1
IPL0
RA
bit 7
R/C-0 OAB(1)
R/W-0 N
R/C-0 SAB(1)
R/W-0 OV
R-0 DA(1)
R/W-0 Z
R/W-0 DC bit 8
R/W-0 C bit 0
Legend: R = Readable bit -n = Value at POR
C = Clearable bit W = Writable bit `1'= Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
OA: Accumulator A Overflow Status bit(1)
1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed OB: Accumulator B Overflow Status bit(1)
1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed SA: Accumulator A Saturation `Sticky' Status bit(1,4)
1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated SB: Accumulator B Saturation `Sticky' Status bit(1,4)
1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated OAB: OA || OB Combined Accumulator Overflow Status bit(1)
1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed SAB: SA || SB Combined Accumulator `Sticky' Status bit(1)
1 = Accumulators A or B are saturated or have been saturated at some time 0 = Neither Accumulators A or B are saturated DA: DO Loop Active bit(1)
1 = DO loop is in progress 0 = DO loop is not in progress
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred
Note 1: 2:
3: 4:
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
The IPL[2:0] bits are concatenated with the IPL[3] bit (CORCON[3]) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL[3] = 1. User interrupts are disabled when IPL[3] = 1.
The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.
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REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
bit 4 bit 3 bit 2 bit 1 bit 0
IPL[2:0]: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress 0 = REPEAT loop not in progress
N: MCU ALU Negative bit
1 = Result was negative 0 = Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two's complement). It indicates an overflow of the magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
Note 1: 2:
3: 4:
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
The IPL[2:0] bits are concatenated with the IPL[3] bit (CORCON[3]) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL[3] = 1. User interrupts are disabled when IPL[3] = 1.
The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.
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REGISTER 3-2: CORCON: CORE CONTROL REGISTER
R/W-0 VAR bit 15
U-0
R/W-0
R/W-0
R/W-0
--
US1(1)
US0(1)
EDT(1,2)
R-0 DL2(1)
R-0 DL1(1)
R-0 DL0(1)
bit 8
R/W-0 SATA(1)
bit 7
R/W-0 SATB(1)
R/W-1
R/W-0
SATDW(1) ACCSAT(1)
R/C-0 IPL3(3)
R-0 SFA
R/W-0 RND(1)
R/W-0 IF(1)
bit 0
Legend: R = Readable bit -n = Value at POR
C = Clearable bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13-12
bit 11 bit 10-8
bit 7 bit 6 bit 5 bit 4 bit 3
VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing latency is enabled 0 = Fixed exception processing latency is enabled
Unimplemented: Read as `0' US[1:0]: DSP Multiply Unsigned/Signed Control bits(1)
11 = Reserved 10 = DSP engine multiplies are mixed-sign 01 = DSP engine multiplies are unsigned 00 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1,2)
1 = Terminates executing DO loop at end of current loop iteration 0 = No effect DL[2:0]: DO Loop Nesting Level Status bits(1)
111 = Seven DO loops are active · · · 001 = One DO loop is active 000 = Zero DO loops are active SATA: ACCA Saturation Enable bit(1)
1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled SATB: ACCB Saturation Enable bit(1)
1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit(1)
1 = Data Space write saturation is enabled 0 = Data Space write saturation is disabled ACCSAT: Accumulator Saturation Mode Select bit(1)
1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(3)
1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less
Note 1: 2: 3:
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. This bit is always read as `0'. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.
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REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 2
SFA: Stack Frame Active Status bit
1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and DSWPAG values
0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space
bit 1
RND: Rounding Mode Select bit(1)
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0
IF: Integer or Fractional Multiplier Mode Select bit(1)
1 = Integer mode is enabled for DSP multiply 0 = Fractional mode is enabled for DSP multiply
Note 1: 2: 3:
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. This bit is always read as `0'. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.
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3.8 Arithmetic Logic Unit (ALU)
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X ALU is 16 bits wide, and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.
Refer to the "16-Bit MCU and DSC Programmer's Reference Manual" (DS70000157) for information on the SR bits affected by each instruction.
The core CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division.
3.8.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed, or mixed-sign operation in several MCU multiplication modes:
· 16-bit x 16-bit signed · 16-bit x 16-bit unsigned · 16-bit signed x 5-bit (literal) unsigned · 16-bit signed x 16-bit unsigned · 16-bit unsigned x 5-bit (literal) unsigned · 16-bit unsigned x 16-bit signed · 8-bit unsigned x 8-bit unsigned
3.8.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:
· 32-bit signed/16-bit signed divide
· 32-bit unsigned/16-bit unsigned divide
· 16-bit signed/16-bit signed divide
· 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.
3.9 DSP Engine (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)
The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a 40-bit barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic).
The DSP engine can also perform inherent accumulatorto-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below:
· Fractional or integer DSP multiply (IF)
· Signed, unsigned or mixed-sign DSP multiply (US)
· Conventional or convergent rounding (RND)
· Automatic saturation on/off for ACCA (SATA)
· Automatic saturation on/off for ACCB (SATB)
· Automatic saturation on/off for writes to data memory (SATDW)
· Accumulator Saturation mode selection (ACCSAT)
TABLE 3-2:
Instruction
CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC
DSP INSTRUCTIONS SUMMARY
Algebraic Operation
ACC Write Back
A = 0
Yes
A = (x y)2
No
A = A + (x y)2
No
A = A + (x · y)
Yes
A = A + x2
No
No change in A
Yes
A=x·y
No
A = x2
No
A=x·y
No
A=Ax·y
Yes
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4.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "dsPIC33/PIC24 Program Memory" (www.microchip.com/DS70000613) in the "dsPIC33/PIC24 Family Reference Manual".
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X architecture features separate program and data memory spaces, and buses. This architecture also allows the direct access of program memory from the Data Space (DS) during code execution.
4.1 Program Address Space
The program address memory space of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit PC during program execution, or from table operation or Data Space remapping, as described in Section 4.8 "Interfacing Program and Data Memory Spaces".
User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD operations, which use TBLPAG[7] to read Device ID sections of the configuration memory space.
The program memory maps, which are presented by device family and memory size, are shown in Figure 4-1 through Figure 4-5.
FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X AND PIC24EP32GP/MC20X DEVICES
User Memory Space
GOTO Instruction Reset Address Interrupt Vector Table
User Program Flash Memory (11K instructions)
Flash Configuration Bytes
0x000000 0x000002 0x000004 0x0001FE 0x000200
0x0057EA 0x0057EC 0x0057FE 0x005800
Note: Memory areas are not shown to scale.
Configuration Memory Space
Unimplemented (Read `0's)
Reserved USERID Reserved Write Latches
Reserved
DEVID Reserved
0x7FFFFE 0x800000 0x800FF6 0x800FF8 0x800FFE 0x801000 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004
0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE
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FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X AND PIC24EP64GP/MC20X DEVICES
User Memory Space
GOTO Instruction Reset Address Interrupt Vector Table
User Program Flash Memory (22K instructions)
Flash Configuration Bytes
0x000000 0x000002 0x000004 0x0001FE 0x000200
0x00AFEA 0x00AFEC 0x00AFFE 0x00B000
Unimplemented (Read `0's)
Reserved USERID Reserved Write Latches
Reserved
DEVID Reserved
0x7FFFFE 0x800000 0x800FF6 0x800FF8 0x800FFE 0x801000 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004
0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE
Configuration Memory Space
Note: Memory areas are not shown to scale.
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FIGURE 4-3: PROGRAM MEMORY MAP FOR dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X AND PIC24EP128GP/MC20X DEVICES
User Memory Space
GOTO Instruction Reset Address Interrupt Vector Table User Program Flash Memory (44K instructions)
Flash Configuration Bytes
0x000000 0x000002 0x000004 0x0001FE 0x000200
0x0157EA 0x0157EC 0x0157FE 0x015800
Unimplemented (Read `0's)
Reserved USERID Reserved Write Latches
Reserved
DEVID Reserved
0x7FFFFE 0x800000 0x800FF6 0x800FF8 0x800FFE 0x801000 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004
0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE
Configuration Memory Space
Note: Memory areas are not shown to scale.
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FIGURE 4-4: PROGRAM MEMORY MAP FOR dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X AND PIC24EP256GP/MC20X DEVICES
User Memory Space
GOTO Instruction Reset Address Interrupt Vector Table
User Program Flash Memory (88K instructions)
Flash Configuration Bytes
0x000000 0x000002 0x000004 0x0001FE 0x000200
0x02AFEA 0x02AFEC 0x02AFFE 0x02B000
Unimplemented (Read `0's)
Reserved USERID Reserved Write Latches
Reserved
DEVID Reserved
0x7FFFFE 0x800000 0x800FF6 0x800FF8 0x800FFE 0x801000 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004
0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE
Configuration Memory Space
Note: Memory areas are not shown to scale.
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FIGURE 4-5: PROGRAM MEMORY MAP FOR dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X AND PIC24EP512GP/MC20X DEVICES
User Memory Space
GOTO Instruction Reset Address Interrupt Vector Table User Program Flash Memory (175K instructions)
Flash Configuration Bytes
0x000000 0x000002 0x000004 0x0001FE 0x000200
0x0557EA 0x0557EC 0x0557FE 0x055800
Unimplemented (Read `0's)
Reserved USERID Reserved Write Latches
Reserved
DEVID Reserved
0x7FFFFE 0x800000 0x800FF6 0x800FF8 0x800FFE 0x801000 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004
0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE
Configuration Memory Space
Note: Memory areas are not shown to scale.
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4.1.1
PROGRAM MEMORY ORGANIZATION
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-6).
Program memory addresses are always word-aligned on the lower word and addresses are incremented, or decremented by two, during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible.
4.1.2 INTERRUPT AND TRAP VECTORS
All dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices reserve the addresses between 0x000000 and 0x000200 for hardcoded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at address, 0x000000, of Flash memory, with the actual address for the start of code at address, 0x000002, of Flash memory.
A more detailed discussion of the Interrupt Vector Tables (IVTs) is provided in Section 7.1 "Interrupt Vector Table".
FIGURE 4-6:
PROGRAM MEMORY ORGANIZATION
msw Address
0x000001 0x000003 0x000005 0x000007
most significant word
23 00000000 00000000 00000000 00000000
Program Memory `Phantom' Byte (read as `0')
least significant word
16
8
Instruction Width
PC Address (lsw Address)
0 0x000000 0x000002 0x000004 0x000006
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4.2 Data Address Space
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X CPU has a separate 16-bit wide data memory space. The Data Space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps, which are presented by device family and memory size, are shown in Figure 4-7 through Figure 4-16.
All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the Data Space. This arrangement gives a base Data Space address range of 64 Kbytes (32K words).
The base Data Space address is used in conjunction with a Read or Write Page register (DSRPAG or DSWPAG) to form an Extended Data Space, which has a total address range of 16 Mbytes.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices implement up to 52 Kbytes of data memory (4 Kbytes of data memory for Special Function Registers and up to 48 Kbytes of data memory for RAM). If an EA points to a location outside of this area, an all-zero word or byte is returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byteaddressable, 16-bit wide blocks. Data are aligned in data memory and registers as 16-bit words, but all Data Space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.
4.2.2
DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC® MCU devices and improve Data Space memory usage efficiency, the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results in a value of Ws + 1 for byte operations and Ws + 2 for word operations.
A data byte read, reads the complete word that contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.
All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/ or user application to examine the machine state prior to execution of the address Fault.
All byte loads into any W register are loaded into the LSB. The MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address.
4.2.3 SFR SPACE
The first 4 Kbytes of the Near Data Space, from 0x0000 to 0x0FFF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X core and peripheral modules for controlling the operation of the device.
SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'.
Note:
The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.
4.2.4 NEAR DATA SPACE
The 8-Kbyte area, between 0x0000 and 0x1FFF, is referred to as the Near Data Space. Locations in this space are directly addressable through a 13-bit absolute address field within all memory direct instructions. Additionally, the whole Data Space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a Working register as an Address Pointer.
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FIGURE 4-7: DATA MEMORY MAP FOR dsPIC33EP32MC20X/50X AND dsPIC33EP32GP50X DEVICES
4-Kbyte SFR Space
MSB Address
0x0001 0x0FFF 0x1001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
LSB Address
0x0000 0x0FFE 0x1000
4-Kbyte SRAM Space
0x17FF 0x1801
Y Data RAM (Y)
0x17FE 0x1800
0x1FFF 0x2001
0x1FFE 0x2000
8-Kbyte Near Data Space
0x8001
X Data Unimplemented (X)
0x8000
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
Optionally
Mapped
into Program
Memory Space (PSV)
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FIGURE 4-8: DATA MEMORY MAP FOR dsPIC33EP64MC20X/50X AND dsPIC33EP64GP50X DEVICES
4-Kbyte SFR Space
MSB Address
0x0001 0x0FFF 0x1001
16 Bits
MSB
LSB
SFR Space
LSB Address
0x0000 0x0FFE 0x1000
X Data RAM (X)
8-Kbyte SRAM Space
0x1FFF 0x2001
Y Data RAM (Y)
0x1FFE 0x2000
0x2FFF 0x3001
0x2FFE 0x3000
8-Kbyte Near Data Space
0x8001
X Data Unimplemented (X)
0x8000
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
Optionally Mapped into Program Memory Space (PSV)
2011-2020 Microchip Technology Inc.
DS70000657J-page 55
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-9: DATA MEMORY MAP FOR dsPIC33EP128MC20X/50X AND dsPIC33EP128GP50X DEVICES
4-Kbyte SFR Space
16-Kbyte SRAM Space
MSB Address
0x0001
0x0FFF 0x1001
0x1FFF 0x2001
0x2FFF 0x3001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
Y Data RAM (Y)
LSB Address
0x0000
0x0FFE 0x1000
0x1FFE 0x2000
0x2FFE 0x3000
0x4FFF 0x5001
0x4FFE 0x5000
8-Kbyte Near Data Space
0x8001
X Data Unimplemented (X)
0x8000
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
Optionally
Mapped
into Program
Memory Space (PSV)
DS70000657J-page 56
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-10: DATA MEMORY MAP FOR dsPIC33EP256MC20X/50X AND dsPIC33EP256GP50X DEVICES
4-Kbyte SFR Space
32-Kbyte SRAM Space
MSB Address
0x0001
0x0FFF 0x1001
0x1FFF 0x2001
0x4FFF 0x5001
0x7FFF 0x8001
0x8FFF 0x9001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
Y Data RAM (Y)
LSB Address
0x0000
0x0FFE 0x1000
0x1FFE 0x2000
0x4FFE 0x5000
0x7FFE 0x8000
0x8FFE 0x9000
8-Kbyte Near Data Space
X Data Unimplemented (X)
Optionally Mapped into Program Memory Space (PSV)
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
2011-2020 Microchip Technology Inc.
DS70000657J-page 57
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-11: DATA MEMORY MAP FOR dsPIC33EP512MC20X/50X AND dsPIC33EP512GP50X DEVICES
4-Kbyte SFR Space
48-Kbyte SRAM Space
MSB Address
0x0001
0x0FFF 0x1001
0x1FFF 0x2001
0x7FFF 0x8001
0x8FFF 0x9001
0xCFFF 0xD001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
Y Data RAM (Y)
LSB Address
0x0000
0x0FFE 0x1000
0x1FFE 0x2000
0x7FFE 0x8000
0x8FFE 0x9000
0xCFFE 0xD000
8-Kbyte Near Data Space
X Data Unimplemented (X)
Optionally Mapped into Program Memory Space (PSV)
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
DS70000657J-page 58
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-12: DATA MEMORY MAP FOR PIC24EP32GP/MC20X/50X DEVICES
4-Kbyte SFR Space
MSB Address
0x0001 0x0FFF 0x1001
16 Bits
MSB
LSB
SFR Space
LSB Address
0x0000 0x0FFE 0x1000
4-Kbyte SRAM Space
X Data RAM (X)
8-Kbyte Near Data Space
0x1FFF 0x2001
0x1FFE 0x2000
0x8001
X Data Unimplemented (X)
0x8000
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
Optionally Mapped into Program Memory Space (PSV)
2011-2020 Microchip Technology Inc.
DS70000657J-page 59
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-13: DATA MEMORY MAP FOR PIC24EP64GP/MC20X/50X DEVICES
4-Kbyte SFR Space
MSB Address
0x0001 0x0FFF 0x1001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
LSB Address
0x0000 0x0FFE 0x1000
8-Kbyte SRAM Space
0x1FFF 0x2001
0x1FFE 0x2000
8-Kbyte Near Data Space
0x2FFF 0x3001
0x2FFE 0x3000
0x8001
X Data Unimplemented (X)
0x8000
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
Optionally Mapped into Program Memory Space (PSV)
DS70000657J-page 60
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-14: DATA MEMORY MAP FOR PIC24EP128GP/MC20X/50X DEVICES
4-Kbyte SFR Space
16-Kbyte SRAM Space
MSB Address
0x0001
0x0FFF 0x1001
0x1FFF 0x2001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
LSB Address
0x0000
0x0FFE 0x1000
0x1FFE 0x2000
8-Kbyte Near Data Space
0x4FFF 0x5001
0x4FFE 0x5000
0x8001
X Data Unimplemented (X)
0x8000
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
Optionally
Mapped
into Program
Memory Space (PSV)
2011-2020 Microchip Technology Inc.
DS70000657J-page 61
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-15: DATA MEMORY MAP FOR PIC24EP256GP/MC20X/50X DEVICES
4-Kbyte SFR Space
32-Kbyte SRAM Space
MSB Address
0x0001 0x0FFF 0x1001 0x1FFF 0x2001
0x7FFF 0x8001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
LSB Address
0x0000 0x0FFE 0x1000
0x1FFE 0x2000
0x7FFE 0x8000
8-Kbyte Near Data Space
0x8FFF 0x9001
0x8FFE 0x9000
X Data Unimplemented (X)
Optionally
Mapped
into Program
Memory Space (PSV)
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
DS70000657J-page 62
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-16: DATA MEMORY MAP FOR PIC24EP512GP/MC20X/50X DEVICES
4-Kbyte SFR Space
48-Kbyte SRAM Space
MSB Address
0x0001 0x0FFF 0x1001 0x1FFF 0x2001
0x7FFF 0x8001
16 Bits
MSB
LSB
SFR Space
X Data RAM (X)
LSB Address
0x0000 0x0FFE 0x1000
0x1FFE 0x2000
0x7FFE 0x8000
8-Kbyte Near Data Space
0xCFFF 0xD001
0xCFFE 0xD000
X Data Unimplemented (X)
Optionally Mapped into Program Memory Space (PSV)
0xFFFF Note: Memory areas are not shown to scale.
0xFFFE
2011-2020 Microchip Technology Inc.
DS70000657J-page 63
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.2.5 X AND Y DATA SPACES
The
dsPIC33EPXXXMC20X/50X
and
dsPIC33EPXXXGP50X core has two Data Spaces,
X and Y. These Data Spaces can be considered either
separate (for some DSP instructions) or as one unified
linear address range (for MCU instructions). The Data
Spaces are accessed using two Address Generation
Units (AGUs) and separate data paths. This feature
allows certain instructions to concurrently fetch two
words from RAM, thereby enabling efficient execution
of DSP algorithms, such as Finite Impulse Response
(FIR) filtering and Fast Fourier Transform (FFT).
The X Data Space is used by all instructions and supports all addressing modes. X Data Space has separate read and write data buses. The X read data bus is the read data path for all instructions that view Data Space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class).
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths.
Both the X and Y Data Spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X Data Space. Modulo Addressing and Bit-Reversed Addressing are not present in PIC24EPXXXGP/MC20X devices.
All data memory writes, including in DSP instructions, view Data Space as combined X and Y address space. The boundary between the X and Y Data Spaces is device-dependent and is not user-programmable.
4.3 Memory Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
4.3.1 KEY RESOURCES
· "dsPIC33/PIC24 Program Memory" (www.microchip.com/DS70000613) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
DS70000657J-page 64
2011-2020 Microchip Technology Inc.
DS70000657J-page 65
2011-2020 Microchip Technology Inc.
4.4 Special Function Register Maps TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY
File Name Addr. Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
W0
0000
W0 (WREG)
W1
0002
W1
W2
0004
W2
W3
0006
W3
W4
0008
W4
W5
000A
W5
W6
000C
W6
W7
000E
W7
W8
0010
W8
W9
0012
W9
W10
0014
W10
W11
0016
W11
W12
0018
W12
W13
001A
W13
W14
001C
W14
W15
001E
W15
SPLIM
0020
SPLIM
ACCAL
0022
ACCAL
ACCAH
0024
ACCAH
ACCAU
0026
Sign Extension of ACCA[39]
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
Sign Extension of ACCB[39]
PCL
002E
PCL[15:0]
PCH
0030
--
--
--
--
--
--
--
--
--
DSRPAG 0032
--
--
--
--
--
--
DSWPAG 0034
--
--
--
--
--
--
--
RCOUNT 0036
RCOUNT[15:0]
DCOUNT 0038
DCOUNT[15:0]
DOSTARTL 003A
DOSTARTL[15:1]
DOSTARTH 003C
--
--
--
--
--
--
--
--
--
DOENDL 003E
DOENDL[15:1]
DOENDH 0040
--
--
--
--
--
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ACCAU
ACCBU PCH[6:0]
DSRPAG[9:0] DSWPAG[8:0]
--
DOSTARTH[5:0]
--
DOENDH[5:0]
Bit 0
-- -- --
All Resets
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0000 0000 0000 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 66
TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED)
File Name Addr. Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL[2:0]
RA
N
CORCON 0044 VAR
--
US[1:0]
EDT
DL[2:0]
SATA
SATB SATDW ACCSAT IPL3
MODCON 0046 XMODEN YMODEN --
--
BWM[3:0]
YWM[3:0]
XMODSRT 0048
XMODSRT[15:0]
XMODEND 004A
XMODEND[15:0]
YMODSRT 004C
YMODSRT[15:0]
YMODEND 004E
YMODEND[15:0]
XBREV
0050 BREN
XBREV[14:0]
DISICNT
0052
--
--
DISICNT[13:0]
TBLPAG
0054
--
--
--
--
--
--
--
--
TBLPAG[7:0]
MSTRPR 0058
MSTRPR[15:0]
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
OV
Z
SFA
RND
XWM[3:0]
C
0000
IF
0020
0000
--
0000
--
0001
--
0000
--
0001
0000
0000
0000
0000
2011-2020 Microchip Technology Inc.
DS70000657J-page 67
2011-2020 Microchip Technology Inc.
TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGP/MC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
W0
0000
W0 (WREG)
W1
0002
W1
W2
0004
W2
W3
0006
W3
W4
0008
W4
W5
000A
W5
W6
000C
W6
W7
000E
W7
W8
0010
W8
W9
0012
W9
W10
0014
W10
W11
0016
W11
W12
0018
W12
W13
001A
W13
W14
001C
W14
W15
001E
W15
SPLIM
0020
SPLIM[15:0]
PCL
002E
PCL[15:1]
PCH
0030
--
--
--
--
--
--
--
--
--
DSRPAG 0032
--
--
--
--
--
--
DSWPAG 0034
--
--
--
--
--
--
--
RCOUNT 0036
RCOUNT[15:0]
SR
0042
--
--
--
--
--
--
--
DC
IPL[2:0]
CORCON 0044 VAR
--
--
--
--
--
--
--
--
--
DISICNT 0052
--
--
DISICNT[13:0]
TBLPAG 0054
--
--
--
--
--
--
--
--
MSTRPR 0058
MSTRPR[15:0]
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
Bit 4
Bit 3
PCH[6:0] DSRPAG[9:0]
DSWPAG[8:0]
RA
N
--
--
IPL3
TBLPAG[7:0]
Bit 2
OV SFA
Bit 1
Z --
Bit 0
-- C --
All Resets
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0001 0001 0000 0000 0020 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 68
TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IFS0
0800 --
DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
IFS1
0802 U2TXIF U2RXIF INT2IF
T5IF
T4IF OC4IF OC3IF DMA2IF
IFS2
0804 --
--
--
--
--
--
--
--
IFS3
0806 --
--
--
--
--
--
--
--
IFS4
0808 --
--
CTMUIF
--
--
--
--
--
IFS8
0810 JTAGIF ICDIF
--
--
--
--
--
--
IFS9
0812 --
--
--
--
--
--
--
--
IEC0
0820 --
DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
IEC1
0822 U2TXIE U2RXIE INT2IE
T5IE
T4IE OC4IE OC3IE DMA2IE
IEC2
0824 --
--
--
--
--
--
--
--
IEC3
0826 --
--
--
--
--
--
--
--
IEC4
0828 --
--
CTMUIE
--
--
--
--
--
IEC8
0830 JTAGIE ICDIE
--
--
--
--
--
--
IEC9
0832 --
--
--
--
--
--
--
--
IPC0
0840 --
T1IP[2:0]
--
OC1IP[2:0]
IPC1
0842 --
T2IP[2:0]
--
OC2IP[2:0]
IPC2
0844 --
U1RXIP[2:0]
--
SPI1IP[2:0]
IPC3
0846 --
--
--
--
--
DMA1IP[2:0]
IPC4
0848 --
CNIP[2:0]
--
CMIP[2:0]
IPC5
084A --
--
--
--
--
--
--
--
IPC6
084C --
T4IP[2:0]
--
OC4IP[2:0]
IPC7
084E --
U2TXIP[2:0]
--
U2RXIP[2:0]
IPC8
0850 --
--
--
--
--
--
--
--
IPC9
0852 --
--
--
--
--
IC4IP[2:0]
IPC12
0858 --
--
--
--
--
MI2C2IP[2:0]
IPC16
0860 --
CRCIP[2:0]
--
U2EIP[2:0]
IPC19
0866 --
--
--
--
--
--
--
--
IPC35
0886 --
JTAGIP[2:0]
--
ICDIP[2:0]
IPC36
0888 --
PTG0IP[2:0]
--
PTGWDTIP[2:0]
IPC37
088A --
--
--
--
--
PTG3IP[2:0]
INTCON1 08C0 NSTDIS OVAERR OVBERR
--
--
--
--
--
INTCON2 08C2 GIE
DISI SWTRAP
--
--
--
--
--
INTCON3 08C4 --
--
--
--
--
--
--
--
INTCON4 08C6 --
--
--
--
--
--
--
--
INTTREG 08C8 --
--
--
--
ILR[3:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
T2IF -- -- -- -- -- -- T2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
--
--
INT1IF
CNIF
CMIF
MI2C1IF SI2C1IF
IC4IF
IC3IF
DMA3IF
--
--
SPI2IF SPI2EIF
--
--
--
--
MI2C2IF SI2C2IF
--
--
--
--
CRCIF
U2EIF
U1EIF
--
--
--
--
--
--
--
--
PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF --
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
--
--
INT1IE
CNIE
CMIE
MI2C1IE SI2C1IE
IC4IE
IC3IE
DMA3IE
--
--
SPI2IE SPI2EIE
--
--
--
--
MI2C2IE SI2C2IE
--
--
--
--
CRCIE
U2EIE
U1EIE
--
--
--
--
--
--
--
--
PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE --
IC1IP[2:0]
--
INT0IP[2:0]
IC2IP[2:0]
--
DMA0IP[2:0]
SPI1EIP[2:0]
--
T3IP[2:0]
AD1IP[2:0]
--
U1TXIP[2:0]
MI2C1IP[2:0]
--
SI2C1IP[2:0]
--
--
--
--
INT1IP[2:0]
OC3IP[2:0]
--
DMA2IP[2:0]
INT2IP[2:0]
--
T5IP[2:0]
SPI2IP[2:0]
--
SPI2EIP[2:0]
IC3IP[2:0]
--
DMA3IP[2:0]
SI2C2IP[2:0]
--
--
--
--
U1EIP[2:0]
--
--
--
--
CTMUIP[2:0]
--
--
--
--
--
--
--
--
--
--
--
PTGSTEPIP[2:0]
--
--
--
--
PTG2IP[2:0]
--
PTG1IP[2:0]
DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
--
--
--
--
--
INT2EP
INT1EP INT0EP
--
DAE
DOOVR
--
--
--
--
--
--
--
--
--
--
SGHT
VECNUM[7:0]
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 0004 4444 4444 0044 0444 0440 4440 0040 4400 4440 0444 0000 8000 0000 0000 0000
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IFS0 IFS1 IFS2 IFS3 IFS4 IFS5 IFS6 IFS8 IFS9 IEC0 IEC1 IEC2 IEC3 IEC4 IEC5 IEC6 IEC8 IEC9 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC12 IPC14 IPC16 IPC19 IPC23 IPC24 Legend:
0800 -- DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
0802 U2TXIF U2RXIF INT2IF
T5IF
T4IF OC4IF OC3IF DMA2IF
0804 --
--
--
--
--
--
--
--
0806 --
--
--
--
--
QEI1IF PSEMIF --
0808 --
--
CTMUIF
--
--
--
--
--
080A PWM2IF PWM1IF
--
--
--
--
--
--
080C --
--
--
--
--
--
--
--
0810 JTAGIF ICDIF
--
--
--
--
--
--
0812 --
--
--
--
--
--
--
--
0820 -- DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
0822 U2TXIE U2RXIE INT2IE
T5IE
T4IE OC4IE OC3IE DMA2IE
0824 --
--
--
--
--
--
--
--
0826 --
--
--
--
--
QEI1IE PSEMIE --
0828 --
--
CTMUIE
--
--
--
--
--
082A PWM2IE PWM1IE
--
--
--
--
--
--
082C --
--
--
--
--
--
--
--
0830 JTAGIE ICDIE
--
--
--
--
--
--
0832 --
--
--
--
--
--
--
--
0840 --
T1IP[2:0]
--
OC1IP[2:0]
0842 --
T2IP[2:0]
--
OC2IP[2:0]
0844 --
U1RXIP[2:0]
--
SPI1IP[2:0]
0846 --
--
--
--
--
DMA1IP[2:0]
0848 --
CNIP[2:0]
--
CMIP[2:0]
084A --
--
--
--
--
--
--
--
084C --
T4IP[2:0]
--
OC4IP[2:0]
084E --
U2TXIP[2:0]
--
U2RXIP[2:0]
0850 --
--
--
--
--
--
--
--
0852 --
--
--
--
--
IC4IP[2:0]
0858 --
--
--
--
--
MI2C2IP[2:0]
085C --
--
--
--
--
QEI1IP[2:0]
0860 --
CRCIP[2:0]
--
U2EIP[2:0]
0866 --
--
--
--
--
--
--
--
086E --
PWM2IP[2:0]
--
PWM1IP[2:0]
0870 --
--
--
--
--
--
--
--
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
T2IF -- -- -- -- -- -- -- -- T2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC2IF
IC2IF
DMA0IF
--
--
INT1IF
IC4IF
IC3IF
DMA3IF
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PTG3IF PTG2IF PTG1IF
OC2IE
IC2IE
DMA0IE
--
--
INT1IE
IC4IE
IC3IE DMA3IE
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PTG3IE PTG2IE PTG1IE
IC1IP[2:0]
IC2IP[2:0]
SPI1EIP[2:0]
AD1IP[2:0]
MI2C1IP[2:0]
--
--
--
OC3IP[2:0]
INT2IP[2:0]
SPI2IP[2:0]
IC3IP[2:0]
SI2C2IP[2:0]
PSEMIP[2:0]
U1EIP[2:0]
CTMUIP[2:0]
--
--
--
--
--
--
T1IF CNIF
-- -- CRCIF -- -- -- PTG0IF T1IE CNIE -- -- CRCIE -- -- -- PTG0IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC1IF
IC1IF
INT0IF
CMIF
MI2C1IF SI2C1IF
--
SPI2IF SPI2EIF
MI2C2IF SI2C2IF
--
U2EIF
U1EIF
--
--
--
--
--
--
PWM3IF
--
--
--
PTGWDTIF PTGSTEPIF --
OC1IE
IC1IE
INT0IE
CMIE
MI2C1IE SI2C1IE
--
SPI2IE SPI2EIE
MI2C2IE SI2C2IE
--
U2EIE
U1EIE
--
--
--
--
--
--
PWM3IE
--
--
--
PTGWDTIE PTGSTEPIE --
INT0IP[2:0]
DMA0IP[2:0]
T3IP[2:0]
U1TXIP[2:0]
SI2C1IP[2:0]
INT1IP[2:0]
DMA2IP[2:0]
T5IP[2:0]
SPI2EIP[2:0]
DMA3IP[2:0]
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PWM3IP[2:0]
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 0004 4444 4444 0044 0444 0440 0440 4440 0040 4400 4004
DS70000657J-page 69
2011-2020 Microchip Technology Inc.
DS70000657J-page 70
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY (CONTINUED)
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IPC35
0886
--
JTAGIP[2:0]
--
ICDIP[2:0]
IPC36
0888
--
PTG0IP[2:0]
--
PTGWDTIP[2:0]
IPC37 088A --
--
--
--
--
PTG3IP[2:0]
INTCON1 08C0 NSTDIS OVAERR OVBERR
--
--
--
--
--
INTCON2 08C2 GIE
DISI SWTRAP
--
--
--
--
--
INTCON3 08C4 --
--
--
--
--
--
--
--
INTCON4 08C6 --
--
--
--
--
--
--
--
INTTREG 08C8 --
--
--
--
ILR[3:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
--
--
--
--
--
--
--
PTGSTEPIP[2:0]
--
--
--
--
PTG2IP[2:0]
--
PTG1IP[2:0]
-- DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
--
--
--
--
--
INT2EP
INT1EP
--
--
DAE
DOOVR
--
--
--
--
--
--
--
--
--
--
VECNUM[7:0]
Bit 0
All Resets
-- --
-- INT0EP
-- SGHT
4400 4440 0444 0000 8000 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
File Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IFS0 IFS1 IFS2 IFS3 IFS4 IFS6 IFS8 IFS9 IEC0 IEC1 IEC2 IEC3 IEC4 IEC8 IEC9 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11 IPC12 IPC16 IPC17 IPC19 IPC35 IPC36 IPC37 Legend:
0800 -- DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
0802 U2TXIF U2RXIF INT2IF
T5IF
T4IF OC4IF OC3IF DMA2IF
0804 --
--
--
--
--
--
--
--
0806 --
--
--
--
--
--
--
--
0808 --
--
CTMUIF
--
--
--
--
--
080C --
--
--
--
--
--
--
--
0810 JTAGIF ICDIF
--
--
--
--
--
--
0812 --
--
--
--
--
--
--
--
0820 -- DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
0822 U2TXIE U2RXIE INT2IE
T5IE
T4IE OC4IE OC3IE DMA2IE
0824 --
--
--
--
--
--
--
--
0826 --
--
--
--
--
--
--
--
0828 --
-- CTMUIE
--
--
--
--
--
0830 JTAGIE ICDIE
--
--
--
--
--
--
0832 --
--
--
--
--
--
--
--
0840 --
T1IP[2:0]
--
OC1IP[2:0]
0842 --
T2IP[2:0]
--
OC2IP[2:0]
0844 --
U1RXIP[2:0]
--
SPI1IP[2:0]
0846 --
--
--
--
--
DMA1IP[2:0]
0848 --
CNIP[2:0]
--
CMIP[2:0]
084A --
--
--
--
--
--
--
--
084C --
T4IP[2:0]
--
OC4IP[2:0]
084E --
U2TXIP[2:0]
--
U2RXIP[2:0]
0850 --
C1IP[2:0]
--
C1RXIP[2:0]
0852 --
--
--
--
--
IC4IP[2:0]
0856 --
--
--
--
--
--
--
--
0858 --
--
--
--
--
MI2C2IP[2:0]
0860 --
CRCIP[2:0]
--
U2EIP[2:0]
0862 --
--
--
--
--
C1TXIP[2:0]
0866 --
--
--
--
--
--
--
--
0886 --
JTAGIP[2:0]
--
ICDIP[2:0]
0888 --
PTG0IP[2:0]
--
PTGWDTIP[2:0]
088A --
--
--
--
--
PTG3IP[2:0]
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
T2IF -- -- -- -- -- -- --
T2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC2IF
IC2IF
DMA0IF
--
--
INT1IF
IC4IF
IC3IF
DMA3IF
--
--
--
C1TXIF
--
--
--
--
--
--
--
--
PTG3IF PTG2IF PTG1IF
OC2IE
IC2IE DMA0IE
--
--
INT1IE
IC4IE
IC3IE DMA3IE
--
--
--
C1TXIE
--
--
--
--
--
PTG3IE PTG2IE PTG1IE
IC1IP[2:0]
IC2IP[2:0]
SPI1EIP[2:0]
AD1IP[2:0]
MI2C1IP[2:0]
--
--
--
OC3IP[2:0]
INT2IP[2:0]
SPI2IP[2:0]
IC3IP[2:0]
--
--
--
SI2C2IP[2:0]
U1EIP[2:0]
--
--
--
CTMUIP[2:0]
--
--
--
PTGSTEPIP[2:0]
PTG2IP[2:0]
T1IF CNIF C1IF
-- CRCIF
-- -- PTG0IF T1IE CNIE C1IE -- CRCIE -- PTG0IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC1IF
IC1IF
INT0IF
CMIF
MI2C1IF SI2C1IF
C1RXIF
SPI2IF SPI2EIF
MI2C2IF SI2C2IF
--
U2EIF
U1EIF
--
--
--
PWM3IF
--
--
--
PTGWDTIF PTGSTEPIF --
OC1IE
IC1IE
INT0IE
CMIE
MI2C1IE SI2C1IE
C1RXIE
SPI2IE SPI2EIE
MI2C2IE SI2C2IE
--
U2EIE
U1EIE
--
--
--
--
PTGWDTIE PTGSTEPIE --
INT0IP[2:0]
DMA0IP[2:0]
T3IP[2:0]
U1TXIP[2:0]
SI2C1IP[2:0]
INT1IP[2:0]
DMA2IP[2:0]
T5IP[2:0]
SPI2EIP[2:0]
DMA3IP[2:0]
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PTG1IP[2:0]
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 0004 4444 4444 4444 0444 0000 0440 4440 0400 0040 4400 4440 0444
DS70000657J-page 71
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 72
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED)
File Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE
INTCON2 08C2 GIE
DISI SWTRAP
--
--
--
--
INTCON3 08C4 --
--
--
--
--
--
--
INTCON4 08C6 --
--
--
--
--
--
--
INTTREG 08C8 --
--
--
--
ILR[3:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
COVTE -- -- --
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR
--
--
--
--
--
--
--
DAE
DOOVR
--
--
--
--
--
--
VECNUM[7:0]
STKERR INT2EP
-- --
OSCFAIL INT1EP
-- --
-- INT0EP
-- SGHT
0000 8000 0000 0000 0000
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IFS0 IFS1 IFS2 IFS3 IFS4 IFS5 IFS6 IFS8 IFS9 IEC0 IEC1 IEC2 IEC3 IEC4 IEC5 IEC6 IEC8 IEC9 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC12 IPC14 IPC16 IPC19 IPC23 IPC24 Legend:
0800 -- DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
0802 U2TXIF U2RXIF INT2IF
T5IF
T4IF OC4IF OC3IF DMA2IF
0804 --
--
--
--
--
--
--
--
0806 --
--
--
--
--
QEI1IF PSEMIF --
0808 --
--
CTMUIF
--
--
--
--
--
080A PWM2IF PWM1IF
--
--
--
--
--
--
080C --
--
--
--
--
--
--
--
0810 JTAGIF ICDIF
--
--
--
--
--
--
0812 --
--
--
--
--
--
--
--
0820 -- DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
0822 U2TXIE U2RXIE INT2IE
T5IE
T4IE OC4IE OC3IE DMA2IE
0824 --
--
--
--
--
--
--
--
0826 --
--
--
--
--
QEI1IE PSEMIE --
0828 --
--
CTMUIE
--
--
--
--
--
082A PWM2IE PWM1IE
--
--
--
--
--
--
082C --
--
--
--
--
--
--
--
0830 JTAGIE ICDIE
--
--
--
--
--
--
0832 --
--
--
--
--
--
--
--
0840 --
T1IP[2:0]
--
OC1IP[2:0]
0842 --
T2IP[2:0]
--
OC2IP[2:0]
0844 --
U1RXIP[2:0]
--
SPI1IP[2:0]
0846 --
--
--
--
--
DMA1IP[2:0]
0848 --
CNIP[2:0]
--
CMIP[2:0]
084A --
--
--
--
--
--
--
--
084C --
T4IP[2:0]
--
OC4IP[2:0]
084E --
U2TXIP[2:0]
--
U2RXIP[2:0]
0850 --
--
--
--
--
C1RXIP[2:0]
0852 --
--
--
--
--
IC4IP[2:0]
0858 --
--
--
--
--
MI2C2IP[2:0]
085C --
--
--
--
--
QEI1IP[2:0]
0860 --
CRCIP[2:0]
--
U2EIP[2:0]
0866 --
--
--
--
--
--
--
--
086E --
PWM2IP[2:0]
--
PWM1IP[2:0]
0870 --
--
--
--
--
--
--
--
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
T2IF -- -- -- -- -- -- -- -- T2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC2IF --
IC4IF -- -- -- -- --
PTG3IF OC2IE
-- IC4IE
-- -- -- -- -- PTG3IE
--
-- --
IC2IF
DMA0IF
--
INT1IF
IC3IF
DMA3IF
--
--
--
--
--
--
--
--
--
--
PTG2IF PTG1IF
IC2IE
DMA0IE
--
INT1IE
IC3IE
DMA3IE
--
--
--
--
--
--
--
--
--
--
PTG2IE PTG1IE
IC1IP[2:0]
IC2IP[2:0]
SPI1EIP[2:0]
AD1IP[2:0]
MI2C1IP[2:0]
--
--
OC3IP[2:0]
INT2IP[2:0]
SPI2IP[2:0]
IC3IP[2:0]
SI2C2IP[2:0]
PSEMIP[2:0]
U1EIP[2:0]
CTMUIP[2:0]
--
--
--
--
T1IF CNIF
-- -- CRCIF -- -- -- PTG0IF T1IE CNIE -- -- CRCIE -- -- -- PTG0IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC1IF
IC1IF
INT0IF
CMIF
MI2C1IF SI2C1IF
--
SPI2IF SPI2EIF
MI2C2IF SI2C2IF
--
U2EIF
U1EIF
--
--
--
--
--
--
PWM3IF
--
--
--
PTGWDTIF PTGSTEPIF --
OC1IE
IC1IE
INT0IE
CMIE
MI2C1IE SI2C1IE
--
SPI2IE SPI2EIE
MI2C2IE SI2C2IE
--
U2EIE
U1EIE
--
--
--
--
--
--
PWM3IE
--
--
--
PTGWDTIE PTGSTEPIE --
INT0IP[2:0]
DMA0IP[2:0]
T3IP[2:0]
U1TXIP[2:0]
SI2C1IP[2:0]
INT1IP[2:0]
DMA2IP[2:0]
T5IP[2:0]
SPI2EIP[2:0]
DMA3IP[2:0]
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PWM3IP[2:0]
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 0004 4444 4444 0444 0444 0440 0440 4440 0040 4400 0004
DS70000657J-page 73
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 74
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY (CONTINUED)
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IPC35 0886 --
JTAGIP[2:0]
--
ICDIP[2:0]
IPC36 0888 --
PTG0IP[2:0]
--
PTGWDTIP[2:0]
IPC37 088A --
--
--
--
--
PTG3IP[2:0]
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
INTCON2 08C2 GIE
DISI SWTRAP
--
--
--
--
--
INTCON3 08C4 --
--
--
--
--
--
--
--
INTCON4 08C6 --
--
--
--
--
--
--
--
INTTREG 08C8 --
--
--
--
ILR[3:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
--
--
--
--
--
PTGSTEPIP[2:0]
--
--
PTG2IP[2:0]
--
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR
--
--
--
--
--
--
--
DAE
DOOVR
--
--
--
--
--
--
VECNUM[7:0]
--
--
--
--
PTG1IP[2:0]
STKERR OSCFAIL
INT2EP INT1EP
--
--
--
--
-- --
-- INT0EP
-- SGHT
4400 4440 0444 0000 8000 0000 0000 0000
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IFS0 IFS1 IFS2 IFS3 IFS4 IFS5 IFS6 IFS8 IFS9 IEC0 IEC1 IEC2 IEC3 IEC4 IEC5 IEC6 IEC7 IEC8 IEC9 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC12 IPC14 IPC16 IPC17 IPC19 Legend:
0800 --
DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF
0802 U2TXIF U2RXIF INT2IF
T5IF
T4IF OC4IF OC3IF DMA2IF
0804 --
--
--
--
--
--
--
--
0806 --
--
--
--
--
QEI1IF PSEMIF --
0808 --
--
CTMUIF
--
--
--
--
--
080A PWM2IF PWM1IF
--
--
--
--
--
--
080C --
--
--
--
--
--
--
--
0810 JTAGIF ICDIF
--
--
--
--
--
--
0812 --
--
--
--
--
--
--
--
0820 -- DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE
0822 U2TXIE U2RXIE INT2IE
T5IE
T4IE OC4IE OC3IE DMA2IE
0824 --
--
--
--
--
--
--
--
0826 --
--
--
--
--
QEI1IE PSEMIE --
0828 --
--
CTMUIE
--
--
--
--
--
082A PWM2IE PWM1IE
--
--
--
--
--
--
082C --
--
--
--
--
--
--
--
082E --
--
--
--
--
--
--
--
0830 JTAGIE ICDIE
--
--
--
--
--
--
0832 --
--
--
--
--
--
--
--
0840 --
T1IP[2:0]
--
OC1IP[2:0]
0842 --
T2IP[2:0]
--
OC2IP[2:0]
0844 --
U1RXIP[2:0]
--
SPI1IP[2:0]
0846 --
--
--
--
--
DMA1IP[2:0]
0848 --
CNIP[2:0]
--
CMIP[2:0]
084A --
--
--
--
--
--
--
--
084C --
T4IP[2:0]
--
OC4IP[2:0]
084E --
U2TXIP[2:0]
--
U2RXIP[2:0]
0850 --
C1IP[2:0]
--
C1RXIP[2:0]
0852 --
--
--
--
--
IC4IP[2:0]
0858 --
--
--
--
--
MI2C2IP[2:0]
085C --
--
--
--
--
QEI1IP[2:0]
0860 --
CRCIP[2:0]
--
U2EIP[2:0]
0862 --
--
--
--
--
C1TXIP[2:0]
0866 --
--
--
--
--
--
--
--
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
T2IF -- -- -- -- -- -- -- --
T2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC2IF
IC2IF
DMA0IF
--
--
INT1IF
IC4IF
IC3IF
DMA3IF
--
--
--
C1TXIF
--
--
--
--
--
--
--
--
--
--
--
PTG3IF PTG2IF PTG1IF
OC2IE
IC2IE DMA0IE
--
--
INT1IE
IC4IE
IC3IE DMA3IE
--
--
--
C1TXIE
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PTG3IE PTG2IE PTG1IE
IC1IP[2:0]
IC2IP[2:0]
SPI1EIP[2:0]
AD1IP[2:0]
MI2C1IP[2:0]
--
--
--
OC3IP[2:0]
INT2IP[2:0]
SPI2IP[2:0]
IC3IP[2:0]
SI2C2IP[2:0]
PSEMIP[2:0]
U1EIP[2:0]
--
--
--
CTMUIP[2:0]
T1IF CNIF C1IF
-- CRCIF
-- -- -- PTG0IF T1IE CNIE C1IE -- CRCIE -- -- -- -- PTG0IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
OC1IF
IC1IF
INT0IF
CMIF
MI2C1IF SI2C1IF
C1RXIF
SPI2IF SPI2EIF
MI2C2IF SI2C2IF
--
U2EIF
U1EIF
--
--
--
--
--
--
PWM3IF
--
--
--
PTGWDTIF PTGSTEPIF --
OC1IE
IC1IE
INT0IE
CMIE
MI2C1IE SI2C1IE
C1RXIE
SPI2IE SPI2EIE
MI2C2IE SI2C2IE
--
U2EIE
U1EIE
--
--
--
--
--
--
PWM3IE
--
--
--
--
--
--
PTGWDTIE PTGSTEPIE --
INT0IP[2:0]
DMA0IP[2:0]
T3IP[2:0]
U1TXIP[2:0]
SI2C1IP[2:0]
INT1IP[2:0]
DMA2IP[2:0]
T5IP[2:0]
SPI2EIP[2:0]
DMA3IP[2:0]
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 0004 4444 4444 4444 0444 0440 0440 4440 0400 0040
DS70000657J-page 75
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 76
TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY (CONTINUED)
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
IPC23 086E --
PWM2IP[2:0]
--
PWM1IP[2:0]
--
--
--
--
--
IPC24 0870 --
--
--
--
--
--
--
--
--
--
--
--
--
IPC35 0886 --
JTAGIP[2:0]
--
ICDIP[2:0]
--
--
--
--
--
IPC36 0888 --
PTG0IP[2:0]
--
PTGWDTIP[2:0]
--
PTGSTEPIP[2:0]
--
IPC37 088A --
--
--
--
--
PTG3IP[2:0]
--
PTG2IP[2:0]
--
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR
INTCON2 08C2 GIE
DISI SWTRAP
--
--
--
--
--
--
--
--
--
--
INTCON3 08C4 --
--
--
--
--
--
--
--
--
--
DAE
DOOVR
--
INTCON4 08C6 --
--
--
--
--
--
--
--
--
--
--
--
--
INTTREG 08C8 --
--
--
--
ILR[3:0]
VECNUM[7:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
--
PWM3IP[2:0]
--
--
--
--
PTG1IP[2:0]
STKERR OSCFAIL
INT2EP
INT1EP
--
--
--
--
--
-- --
-- INT0EP
-- SGHT
4400 0004 4400 4440 0444 0000 8000 0000 0000 0000
2011-2020 Microchip Technology Inc.
DS70000657J-page 77
2011-2020 Microchip Technology Inc.
TABLE 4-8: TIMER1 THROUGH TIMER5 REGISTER MAP
SFR Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON 0104 TON
--
TSIDL
--
--
--
--
--
--
TGATE
TCKPS[1:0]
TMR2
0106
Timer2 Register
TMR3HLD 0108
Timer3 Holding Register (for 32-bit timer operations only)
TMR3
010A
Timer3 Register
PR2
010C
Period Register 2
PR3
010E
Period Register 3
T2CON 0110 TON
--
TSIDL
--
--
--
--
--
--
TGATE
TCKPS[1:0]
T3CON 0112 TON
--
TSIDL
--
--
--
--
--
--
TGATE
TCKPS[1:0]
TMR4
0114
Timer4 Register
TMR5HLD 0116
Timer5 Holding Register (for 32-bit operations only)
TMR5
0118
Timer5 Register
PR4
011A
Period Register 4
PR5
011C
Period Register 5
T4CON 011E TON
--
TSIDL
--
--
--
--
--
--
TGATE
TCKPS[1:0]
T5CON 0120 TON
--
TSIDL
--
--
--
--
--
--
TGATE
TCKPS[1:0]
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 3
Bit 2
Bit 1
--
TSYNC TCS
T32
--
TCS
--
--
TCS
T32
--
TCS
--
--
TCS
Bit 0 --
-- --
-- --
All Resets
xxxx FFFF 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
DS70000657J-page 78
TABLE 4-9: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
IC1CON1 0140
--
--
ICSIDL
ICTSEL[2:0]
--
--
--
ICI[1:0]
IC1CON2 0142
--
--
--
--
--
--
--
IC32 ICTRIG TRIGSTAT --
IC1BUF 0144
Input Capture 1 Buffer Register
IC1TMR 0146
Input Capture 1 Timer Register
IC2CON1 0148
--
--
ICSIDL
ICTSEL[2:0]
--
--
--
ICI[1:0]
IC2CON2 014A
--
--
--
--
--
--
--
IC32 ICTRIG TRIGSTAT --
IC2BUF 014C
Input Capture 2 Buffer Register
IC2TMR 014E
Input Capture 2 Timer Register
IC3CON1 0150
--
--
ICSIDL
ICTSEL[2:0]
--
--
--
ICI[1:0]
IC3CON2 0152
--
--
--
--
--
--
--
IC32 ICTRIG TRIGSTAT --
IC3BUF 0154
Input Capture 3 Buffer Register
IC3TMR 0156
Input Capture 3 Timer Register
IC4CON1 0158
--
--
ICSIDL
ICTSEL[2:0]
--
--
--
ICI[1:0]
IC4CON2 015A
--
--
--
--
--
--
--
IC32 ICTRIG TRIGSTAT --
IC4BUF 015C
Input Capture 4 Buffer Register
IC4TMR 015E
Input Capture 4 Timer Register
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 4 ICOV ICOV ICOV ICOV
Bit 3
Bit 2
Bit 1
ICBNE
ICM[2:0]
SYNCSEL[4:0]
ICBNE
ICM[2:0]
SYNCSEL[4:0]
ICBNE
ICM[2:0]
SYNCSEL[4:0]
ICBNE
ICM[2:0]
SYNCSEL[4:0]
Bit 0
All Resets
0000 000D xxxx 0000 0000 000D xxxx 0000 0000 000D xxxx 0000 0000 000D xxxx 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 79
2011-2020 Microchip Technology Inc.
TABLE 4-10: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
OC1CON1 0900 --
--
OCSIDL
OCTSEL[2:0]
--
ENFLTB ENFLTA
--
OCFLTB
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV
--
--
--
OC32 OCTRIG TRIGSTAT OCTRIS
OC1RS
0904
Output Compare 1 Secondary Register
OC1R
0906
Output Compare 1 Register
OC1TMR 0908
Timer Value 1 Register
OC2CON1 090A --
--
OCSIDL
OCTSEL[2:0]
--
ENFLTB ENFLTA
--
OCFLTB
OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV
--
--
--
OC32 OCTRIG TRIGSTAT OCTRIS
OC2RS 090E
Output Compare 2 Secondary Register
OC2R
0910
Output Compare 2 Register
OC2TMR 0912
Timer Value 2 Register
OC3CON1 0914 --
--
OCSIDL
OCTSEL[2:0]
--
ENFLTB ENFLTA
--
OCFLTB
OC3CON2 0916 FLTMD FLTOUT FLTTRIEN OCINV
--
--
--
OC32 OCTRIG TRIGSTAT OCTRIS
OC3RS
0918
Output Compare 3 Secondary Register
OC3R
091A
Output Compare 3 Register
OC3TMR 091C
Timer Value 3 Register
OC4CON1 091E --
--
OCSIDL
OCTSEL[2:0]
--
ENFLTB ENFLTA
--
OCFLTB
OC4CON2 0920 FLTMD FLTOUT FLTTRIEN OCINV
--
--
--
OC32 OCTRIG TRIGSTAT OCTRIS
OC4RS
0922
Output Compare 4 Secondary Register
OC4R
0924
Output Compare 4 Register
OC4TMR 0926
Timer Value 4 Register
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
OCFLTA TRIGMODE
OCM[2:0]
SYNCSEL[4:0]
OCFLTA TRIGMODE
OCM[2:0]
SYNCSEL[4:0]
OCFLTA TRIGMODE
OCM[2:0]
SYNCSEL[4:0]
OCFLTA TRIGMODE
OCM[2:0]
SYNCSEL[4:0]
Bit 0
All Resets
0000 000C xxxx xxxx xxxx 0000 000C xxxx xxxx xxxx 0000 000C xxxx xxxx xxxx 0000 000C xxxx xxxx xxxx
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 80
TABLE 4-11: PTG REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
All Resets
PTGCST 0AC0 PTGEN
-- PTGSIDL PTGTOGL
--
PTGSWT PTGSSEN PTGIVIS PTGSTRT
PTGCON 0AC2
PTGCLK[2:0]
PTGDIV[4:0]
PTGBTE 0AC4
ADCTS[4:1]
IC4TSS IC3TSS IC2TSS IC1TSS OC4CS
PTGHOLD 0AC6
PTGHOLD[15:0]
PTGT0LIM 0AC8
PTGT0LIM[15:0]
PTGT1LIM 0ACA
PTGT1LIM[15:0]
PTGSDLIM 0ACC
PTGSDLIM[15:0]
PTGC0LIM 0ACE
PTGC0LIM[15:0]
PTGC1LIM 0AD0
PTGC1LIM[15:0]
PTGADJ 0AD2
PTGADJ[15:0]
PTGL0
0AD4
PTGL0[15:0]
PTGQPTR 0AD6 --
--
--
--
--
--
--
--
--
PTGQUE0 0AD8
STEP1[7:0]
PTGQUE1 0ADA
STEP3[7:0]
PTGQUE2 0ADC
STEP5[7:0]
PTGQUE3 0ADE
STEP7[7:0]
PTGQUE4 0AE0
STEP9[7:0]
PTGQUE5 0AE2
STEP11[7:0]
PTGQUE6 0AE4
STEP13[7:0]
PTGQUE7 0AE6
STEP15[7:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
PTGWTO -- PTGPWD[3:0] OC3CS OC2CS
--
--
--
--
--
PTGITM[1:0]
--
PTGWDT[2:0]
OC1CS OC4TSS OC3TSS OC2TSS OC1TSS
STEP0[7:0] STEP2[7:0] STEP4[7:0] STEP6[7:0] STEP8[7:0] STEP10[7:0] STEP12[7:0] STEP14[7:0]
PTGQPTR[4:0]
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
PTCON
0C00 PTEN
--
PTSIDL SESTAT SEIEN
EIPU SYNCPOL SYNCOEN SYNCEN
SYNCSRC[2:0]
PTCON2 0C02
--
--
--
--
--
--
--
--
--
--
--
--
--
PTPER
0C04
PTPER[15:0]
SEVTCMP 0C06
SEVTCMP[15:0]
MDC
0C0A
MDC[15:0]
CHOP
0C1A CHPCLKEN --
--
--
--
--
CHOPCLK[9:0]
PWMKEY 0C1E
PWMKEY[15:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
SEVTPS[3:0] PCLKDIV[2:0]
All Resets
0000 0000 00F8 0000 0000 0000 0000
TABLE 4-13: PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
All Resets
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN
ITB
MDCS
DTC[1:0]
DTCP
--
MTBS CAM
XPRES
IUE
IOCON1 0C22 PENH
PENL
POLH
POLL
PMOD[1:0]
OVRENH OVRENL OVRDAT[1:0]
FLTDAT[1:0]
CLDAT[1:0]
SWAP OSYNC
FCLCON1 0C24
--
CLSRC[4:0]
CLPOL CLMOD
FLTSRC[4:0]
FLTPOL
FLTMOD[1:0]
PDC1
0C26
PDC1[15:0]
PHASE1 0C28
PHASE1[15:0]
DTR1
0C2A
--
--
DTR1[13:0]
ALTDTR1 0C2C
--
--
ALTDTR1[13:0]
TRIG1
0C32
TRGCMP[15:0]
TRGCON1 0C34
TRGDIV[3:0]
--
--
--
--
--
--
TRGSTRT[5:0]
LEBCON1 0C3A PHR
PHF
PLR
PLF FLTLEBEN CLLEBEN
--
--
--
--
BCH
BCL BPHH BPHL
BPLH
BPLL
LEBDLY1 0C3C
--
--
--
--
LEB[11:0]
AUXCON1 0C3E
--
--
--
--
BLANKSEL[3:0]
--
--
CHOPSEL[3:0]
CHOPHEN CHOPLEN
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
0000 C000 0000 FFF8 0000 0000 0000 0000 0000 0000 0000 0000
DS70000657J-page 81
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 82
TABLE 4-14: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
All Resets
PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN
ITB
MDCS
DTC[1:0]
DTCP -- MTBS CAM XPRES
IUE
IOCON2 0C42 PENH
PENL
POLH
POLL
PMOD[1:0]
OVRENH OVRENL
OVRDAT[1:0]
FLTDAT[1:0]
CLDAT[1:0]
SWAP OSYNC
FCLCON2 0C44
--
CLSRC[4:0]
CLPOL CLMOD
FLTSRC[4:0]
FLTPOL
FLTMOD[1:0]
PDC2
0C46
PDC2[15:0]
PHASE2 0C48
PHASE2[15:0]
DTR2
0C4A
--
--
DTR2[13:0]
ALTDTR2 0C4C
--
--
ALTDTR2[13:0]
TRIG2
0C52
TRGCMP[15:0]
TRGCON2 0C54
TRGDIV[3:0]
--
--
--
--
--
--
TRGSTRT[5:0]
LEBCON2 0C5A PHR
PHF
PLR
PLF FLTLEBEN CLLEBEN
--
--
--
--
BCH BCL BPHH BPHL
BPLH
BPLL
LEBDLY2 0C5C
--
--
--
--
LEB[11:0]
AUXCON2 0C5E
--
--
--
--
BLANKSEL[3:0]
--
--
CHOPSEL[3:0]
CHOPHEN CHOPLEN
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
0000 C000 00F8 0000 0000 0000 0000 0000 0000 0000 0000 0000
TABLE 4-15: PWM GENERATOR 3 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15
Bit 14
Bit 13
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
All Resets
PWMCON3 0C60 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN
ITB
MDCS
DTC[1:0]
DTCP -- MTBS CAM XPRES
IUE
IOCON3 0C62 PENH
PENL
POLH
POLL
PMOD[1:0]
OVRENH OVRENL
OVRDAT[1:0]
FLTDAT[1:0]
CLDAT[1:0]
SWAP OSYNC
FCLCON3 0C64
--
CLSRC[4:0]
CLPOL CLMOD
FLTSRC[4:0]
FLTPOL
FLTMOD[1:0]
PDC3
0C66
PDC3[15:0]
PHASE3 0C68
PHASE3[15:0]
DTR3
0C6A
--
--
DTR3[13:0]
ALTDTR3 0C6C
--
--
ALTDTR3[13:0]
TRIG3
0C72
TRGCMP[15:0]
TRGCON3 0C74
TRGDIV[3:0]
--
--
--
--
--
--
TRGSTRT[5:0]
LEBCON3 0C7A PHR
PHF
PLR
PLF FLTLEBEN CLLEBEN
--
--
--
--
BCH BCL BPHH BPHL
BPLH
BPLL
LEBDLY3 0C7C
--
--
--
--
LEB[11:0]
AUXCON3 0C7E
--
--
--
--
BLANKSEL[3:0]
--
--
CHOPSEL[3:0]
CHOPHEN CHOPLEN
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
0000 C000 00F8 0000 0000 0000 0000 0000 0000 0000 0000 0000
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-16: QEI1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
QEI1CON 01C0 QEIEN
--
QEISIDL
PIMOD[2:0]
IMV[1:0]
--
INTDIV[2:0]
CNTPOL GATEN
CCM[1:0]
QEI1IOC 01C2 QCAPEN FLTREN
QFDIV[2:0]
OUTFNC[1:0]
SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA
QEI1STAT 01C4 --
-- PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN
POS1CNTL 01C6
POSCNT[15:0]
POS1CNTH 01C8
POSCNT[31:16]
POS1HLD 01CA
POSHLD[15:0]
VEL1CNT 01CC
VELCNT[15:0]
INT1TMRL 01CE
INTTMR[15:0]
INT1TMRH 01D0
INTTMR[31:16]
INT1HLDL 01D2
INTHLD[15:0]
INT1HLDH 01D4
INTHLD[31:16]
INDX1CNTL 01D6
INDXCNT[15:0]
INDX1CNTH 01D8
INDXCNT[31:16]
INDX1HLD 01DA
INDXHLD[15:0]
QEI1GECL 01DC
QEIGEC[15:0]
QEI1ICL 01DC
QEIIC[15:0]
QEI1GECH 01DE
QEIGEC[31:16]
QEI1ICH 01DE
QEIIC[31:16]
QEI1LECL 01E0
QEILEC[15:0]
QEI1LECH 01E2
QEILEC[31:16]
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
0000 000x 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DS70000657J-page 83
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 84
TABLE 4-17: I2C1 AND I2C2 REGISTER MAP
File Name
Addr.
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
I2C1RCV 0200
--
--
--
--
--
--
--
I2C1TRN 0202
--
--
--
--
--
--
--
I2C1BRG 0204
--
--
--
--
--
--
--
I2C1CON 0206 I2CEN
--
I2CSIDL SCLREL IPMIEN A10M DISSLW
I2C1STAT 0208 ACKSTAT TRSTAT
--
--
--
BCL GCSTAT
I2C1ADD 020A
--
--
--
--
--
--
I2C1MSK 020C
--
--
--
--
--
--
I2C2RCV 0210
--
--
--
--
--
--
--
I2C2TRN 0212
--
--
--
--
--
--
--
I2C2BRG 0214
--
--
--
--
--
--
--
I2C2CON 0216 I2CEN
--
I2CSIDL SCLREL IPMIEN A10M DISSLW
I2C2STAT 0218 ACKSTAT TRSTAT
--
--
--
BCL GCSTAT
I2C2ADD 021A
--
--
--
--
--
--
I2C2MSK 021C
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
-- --
SMEN ADD10
-- --
SMEN ADD10
Bit 7
GCEN IWCOL
GCEN IWCOL
Bit 6
Bit 5
Bit 4
Bit 3
I2C1 Receive Register
I2C1 Transmit Register
Baud Rate Generator
STREN ACKDT ACKEN RCEN
I2COV
D_A
P
S
I2C1 Address Register
I2C1 Address Mask Register
I2C2 Receive Register
I2C2 Transmit Register
Baud Rate Generator
STREN ACKDT ACKEN RCEN
I2COV
D_A
P
S
I2C2 Address Register
I2C2 Address Mask Register
Bit 2
PEN R_W
PEN R_W
Bit 1
RSEN RBF
RSEN RBF
Bit 0
SEN TBF
SEN TBF
All Resets
0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000
TABLE 4-18: UART1 AND UART2 REGISTER MAP
SFR Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8 Bit 7
Bit 6
U1MODE 0220 UARTEN
--
USIDL
IREN RTSMD
--
UEN[1:0]
WAKE LPBACK
U1STA
0222 UTXISEL1 UTXINV UTXISEL0
--
UTXBRK UTXEN UTXBF TRMT
URXISEL[1:0]
U1TXREG 0224
--
--
--
--
--
--
--
U1RXREG 0226
--
--
--
--
--
--
--
U1BRG 0228
Baud Rate Generator Prescaler
U2MODE 0230 UARTEN
--
USIDL
IREN RTSMD
--
UEN[1:0]
WAKE LPBACK
U2STA
0232 UTXISEL1 UTXINV UTXISEL0
--
UTXBRK UTXEN UTXBF TRMT
URXISEL[1:0]
U2TXREG 0234
--
--
--
--
--
--
--
U2RXREG 0236
--
--
--
--
--
--
--
U2BRG 0238
Baud Rate Generator Prescaler
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
Bit 4
Bit 3
ABAUD URXINV BRGH ADDEN RIDLE PERR
UART1 Transmit Register UART1 Receive Register
ABAUD URXINV BRGH ADDEN RIDLE PERR
UART2 Transmit Register UART2 Receive Register
Bit 2
Bit 1
PDSEL[1:0]
FERR
OERR
PDSEL[1:0]
FERR
OERR
Bit 0
All Resets
STSEL URXDA
STSEL URXDA
0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000
2011-2020 Microchip Technology Inc.
DS70000657J-page 85
2011-2020 Microchip Technology Inc.
TABLE 4-19: SPI1 AND SPI2 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
SPI1STAT 0240 SPIEN
--
SPISIDL
--
--
SPIBEC[2:0]
SRMPT SPIROV SRXMPT
SPI1CON1 0242 --
--
--
DISSCK DISSDO MODE16 SMP
CKE
SSEN CKP MSTEN
SPI1CON2 0244 FRMEN SPIFSD FRMPOL --
--
--
--
--
--
--
--
SPI1BUF 0248
SPI1 Transmit and Receive Buffer Register
SPI2STAT 0260 SPIEN
--
SPISIDL
--
--
SPIBEC[2:0]
SRMPT SPIROV SRXMPT
SPI2CON1 0262 --
--
--
DISSCK DISSDO MODE16 SMP
CKE
SSEN CKP MSTEN
SPI2CON2 0264 FRMEN SPIFSD FRMPOL --
--
--
--
--
--
--
--
SPI2BUF 0268
SPI2 Transmit and Receive Buffer Register
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 4 -- --
Bit 3
SISEL[2:0] SPRE[2:0]
--
Bit 2 --
SISEL[2:0]
SPRE[2:0]
--
--
Bit 1
Bit 0
All Resets
SPITBF SPIRBF 0000
PPRE[1:0]
0000
FRMDLY SPIBEN 0000
0000
SPITBF SPIRBF 0000
PPRE[1:0]
0000
FRMDLY SPIBEN 0000
0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
DS70000657J-page 86
TABLE 4-20: ADC1 REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
ADC1BUF0 0300
ADC1 Data Buffer 0
ADC1BUF1 0302
ADC1 Data Buffer 1
ADC1BUF2 0304
ADC1 Data Buffer 2
ADC1BUF3 0306
ADC1 Data Buffer 3
ADC1BUF4 0308
ADC1 Data Buffer 4
ADC1BUF5 030A
ADC1 Data Buffer 5
ADC1BUF6 030C
ADC1 Data Buffer 6
ADC1BUF7 030E
ADC1 Data Buffer 7
ADC1BUF8 0310
ADC1 Data Buffer 8
ADC1BUF9 0312
ADC1 Data Buffer 9
ADC1BUFA 0314
ADC1 Data Buffer 10
ADC1BUFB 0316
ADC1 Data Buffer 11
ADC1BUFC 0318
ADC1 Data Buffer 12
ADC1BUFD 031A
ADC1 Data Buffer 13
ADC1BUFE 031C
ADC1 Data Buffer 14
ADC1BUFF 031E
ADC1 Data Buffer 15
AD1CON1 0320 ADON
--
ADSIDL ADDMABM
--
AD12B
FORM[1:0]
SSRC[2:0]
AD1CON2 0322
VCFG[2:0]
--
--
CSCNA
CHPS[1:0]
BUFS
AD1CON3 0324 ADRC
--
--
SAMC[4:0]
AD1CHS123 0326 --
--
--
--
--
CH123NB[1:0]
CH123SB
--
--
AD1CHS0 0328 CH0NB
--
--
CH0SB[4:0]
CH0NA
--
AD1CSSH 032E
CSS[31:30]
--
--
--
CSS[26:24]
--
--
AD1CSSL 0330
CSS[15:0]
AD1CON4 0332 --
--
--
--
--
--
--
ADDMAEN
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
-- -- -- --
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
SSRCG SIMSAM ASAM SAMP
SMPI[4:0]
BUFM
ADCS[7:0]
--
--
CH123NA[1:0]
CH0SA[4:0]
--
--
--
--
DONE ALTS
CH123SA
--
--
--
DMABL[2:0]
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-21: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 0 OR 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
File Name Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1CTRL1
0400
--
--
CSIDL
ABAT CANCKS
REQOP[2:0]
OPMODE[2:0]
-- CANCAP --
--
WIN
C1CTRL2
0402
--
--
--
--
--
--
--
--
--
--
--
DNCNT[4:0]
C1VEC
0404
--
--
--
FILHIT[4:0]
--
ICODE[6:0]
C1FCTRL
0406
DMABS[2:0]
--
--
--
--
--
--
--
--
FSA[4:0]
C1FIFO
0408
--
--
FBP[5:0]
--
--
FNRB[5:0]
C1INTF
040A
--
--
TXBO
TXBP RXBP TXWAR RXWAR EWARN IVRIF
WAKIF ERRIF
--
FIFOIF RBOVIF RBIF
TBIF
C1INTE
040C
--
--
--
--
--
--
--
--
IVRIE
WAKIE ERRIE
--
FIFOIE RBOVIE RBIE TBIE
C1EC
040E
TERRCNT[7:0]
RERRCNT[7:0]
C1CFG1
0410
--
--
--
--
--
--
--
--
SJW[1:0]
BRP[5:0]
C1CFG2
0412
--
WAKFIL
--
--
--
SEG2PH[2:0]
SEG2PHTS SAM
SEG1PH[2:0]
PRSEG[2:0]
C1FEN1
0414
FLTEN[15:0]
C1FMSKSEL1 0418
F7MSK[1:0]
F6MSK[1:0]
F5MSK[1:0]
F4MSK[1:0]
F3MSK[1:0]
F2MSK[1:0]
F1MSK[1:0]
F0MSK[1:0]
C1FMSKSEL2 041A
F15MSK[1:0]
F14MSK[1:0]
F13MSK[1:0]
F12MSK[1:0]
F11MSK[1:0]
F10MSK[1:0]
F9MSK[1:0]
F8MSK[1:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
All Resets
0480 0000 0040 0000 0000 0000 0000 0000 0000 0000 FFFF 0000 0000
TABLE 4-22: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 0 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
File Name Addr Bit 15 Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0400041E
See definition when WIN = x
C1RXFUL1 0420
RXFUL[15:0]
C1RXFUL2 0422
RXFUL[31:16]
C1RXOVF1 0428
RXOVF[15:0]
C1RXOVF2 042A
RXOVF[31:16]
C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1
TX1PRI[1:0]
TXEN0 TXABAT0 TXLARB0
C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3
TX3PRI[1:0]
TXEN2 TXABAT2 TXLARB2
C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5
TX5PRI[1:0]
TXEN4 TXABAT4 TXLARB4
C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7
TX7PRI[1:0]
TXEN6 TXABAT6 TXLARB6
C1RXD
0440
ECAN1 Receive Data Word
C1TXD
0442
ECAN1 Transmit Data Word
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TXERR0 TXERR2 TXERR4 TXERR6
TXREQ0 TXREQ2 TXREQ4 TXREQ6
RTREN0 RTREN2 RTREN4 RTREN6
Bit 1
Bit 0
TX0PRI[1:0] TX2PRI[1:0] TX4PRI[1:0] TX6PRI[1:0]
All Resets
0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx
DS70000657J-page 87
2011-2020 Microchip Technology Inc.
DS70000657J-page 88
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400041E
See definition when WIN = x
C1BUFPNT1 0420
F3BP[3:0]
F2BP[3:0]
F1BP[3:0]
C1BUFPNT2 0422
F7BP[3:0]
F6BP[3:0]
F5BP[3:0]
C1BUFPNT3 0424
F11BP[3:0]
F10BP[3:0]
F9BP[3:0]
C1BUFPNT4 0426
F15BP[3:0]
F14BP[3:0]
F13BP[3:0]
C1RXM0SID 0430
SID[10:3]
SID[2:0]
C1RXM0EID 0432
EID[15:8]
C1RXM1SID 0434
SID[10:3]
SID[2:0]
C1RXM1EID 0436
EID[15:8]
C1RXM2SID 0438
SID[10:3]
SID[2:0]
C1RXM2EID 043A
EID[15:8]
C1RXF0SID 0440
SID[10:3]
SID[2:0]
C1RXF0EID 0442
EID[15:8]
C1RXF1SID 0444
SID[10:3]
SID[2:0]
C1RXF1EID 0446
EID[15:8]
C1RXF2SID 0448
SID[10:3]
SID[2:0]
C1RXF2EID 044A
EID[15:8]
C1RXF3SID 044C
SID[10:3]
SID[2:0]
C1RXF3EID 044E
EID[15:8]
C1RXF4SID 0450
SID[10:3]
SID[2:0]
C1RXF4EID 0452
EID[15:8]
C1RXF5SID 0454
SID[10:3]
SID[2:0]
C1RXF5EID 0456
EID[15:8]
C1RXF6SID 0458
SID[10:3]
SID[2:0]
C1RXF6EID 045A
EID[15:8]
C1RXF7SID 045C
SID[10:3]
SID[2:0]
C1RXF7EID 045E
EID[15:8]
C1RXF8SID 0460
SID[10:3]
SID[2:0]
C1RXF8EID 0462
EID[15:8]
C1RXF9SID 0464
SID[10:3]
SID[2:0]
C1RXF9EID 0466
EID[15:8]
C1RXF10SID 0468
SID[10:3]
SID[2:0]
C1RXF10EID 046A
EID[15:8]
C1RXF11SID 046C
SID[10:3]
SID[2:0]
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
MIDE
EID[7:0]
--
MIDE
EID[7:0]
--
MIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
EID[7:0]
--
EXIDE
F0BP[3:0]
F4BP[3:0]
F8BP[3:0]
F12BP[3:0]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
--
EID[17:16]
All Resets
0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 89
2011-2020 Microchip Technology Inc.
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY (CONTINUED)
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1RXF11EID 046E
EID[15:8]
C1RXF12SID 0470
SID[10:3]
C1RXF12EID 0472
EID[15:8]
C1RXF13SID 0474
SID[10:3]
C1RXF13EID 0476
EID[15:8]
C1RXF14SID 0478
SID[10:3]
C1RXF14EID 047A
EID[15:8]
C1RXF15SID 047C
SID[10:3]
C1RXF15EID 047E
EID[15:8]
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
SID[2:0] SID[2:0] SID[2:0] SID[2:0]
EID[7:0]
--
EXIDE
--
EID[7:0]
--
EXIDE
--
EID[7:0]
--
EXIDE
--
EID[7:0]
--
EXIDE
--
EID[7:0]
EID[17:16] EID[17:16] EID[17:16] EID[17:16]
All Resets
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 90
TABLE 4-24: CRC REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CRCCON1 0640 CRCEN
--
CSIDL
VWORD[4:0]
CRCFUL CRCMPT CRCISEL CRCGO LENDIAN
--
--
CRCCON2 0642
--
--
--
DWIDTH[4:0]
--
--
--
PLEN[4:0]
CRCXORL 0644
X[15:1]
CRCXORH 0646
X[31:16]
CRCDATL 0648
CRC Data Input Low Word
CRCDATH 064A
CRC Data Input High Word
CRCWDATL 064C
CRC Result Low Word
CRCWDATH 064E
CRC Result High Word
Legend: -- = unimplemented, read as `0'. Shaded bits are not used in the operation of the programmable CRC module.
Bit 0 -- --
All Resets
0000 0000 0000 0000 0000 0000 0000 0000
TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC202/502 AND PIC24EPXXXGP/MC202 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 Legend:
0680 --
--
RP35R[5:0]
0682 --
--
RP37R[5:0]
0684 --
--
RP39R[5:0]
0686 --
--
RP41R[5:0]
0688 --
--
RP43R[5:0]
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
--
--
--
--
--
--
--
--
--
RP20R[5:0] RP36R[5:0] RP38R[5:0] RP40R[5:0] RP42R[5:0]
0000 0000 0000 0000 0000
TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC203/503 AND PIC24EPXXXGP/MC203 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
RPOR0 0680 --
--
RP35R[5:0]
--
--
RP20R[5:0]
0000
RPOR1 0682 --
--
RP37R[5:0]
--
--
RP36R[5:0]
0000
RPOR2 0684 --
--
RP39R[5:0]
--
--
RP38R[5:0]
0000
RPOR3 0686 --
--
RP41R[5:0]
--
--
RP40R[5:0]
0000
RPOR4 0688 --
--
RP43R[5:0]
--
--
RP42R[5:0]
0000
RPOR5 068A --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0000
RPOR6 068C --
--
--
--
--
--
--
--
--
--
RP56R[5:0]
0000
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC204/504 AND PIC24EPXXXGP/MC204 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 Legend:
0680 --
--
RP35R[5:0]
0682 --
--
RP37R[5:0]
0684 --
--
RP39R[5:0]
0686 --
--
RP41R[5:0]
0688 --
--
RP43R[5:0]
068A --
--
RP55R[5:0]
068C --
--
RP57R[5:0]
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
RP20R[5:0] RP36R[5:0] RP38R[5:0] RP40R[5:0] RP42R[5:0] RP54R[5:0] RP56R[5:0]
0000 0000 0000 0000 0000 0000 0000
TABLE 4-28: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC206/506 AND PIC24EPXXXGP/MC206 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
RPOR0 0680 --
--
RP35R[5:0]
--
--
RP20R[5:0]
0000
RPOR1 0682 --
--
RP37R[5:0]
--
--
RP36R[5:0]
0000
RPOR2 0684 --
--
RP39R[5:0]
--
--
RP38R[5:0]
0000
RPOR3 0686 --
--
RP41R[5:0]
--
--
RP40R[5:0]
0000
RPOR4 0688 --
--
RP43R[5:0]
--
--
RP42R[5:0]
0000
RPOR5 068A --
--
RP55R[5:0]
--
--
RP54R[5:0]
0000
RPOR6 068C --
--
RP57R[5:0]
--
--
RP56R[5:0]
0000
RPOR7 068E --
--
RP97R[5:0]
--
--
--
--
--
--
--
--
0000
RPOR8 0690 --
--
RP118R[5:0]
--
--
--
--
--
--
--
--
0000
RPOR9 0692 --
--
--
--
--
--
--
--
--
--
RP120R[5:0]
0000
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
DS70000657J-page 91
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 92
TABLE 4-29: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
File Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RPINR0 06A0 --
INT1R[6:0]
--
--
--
--
--
--
RPINR1 06A2 --
--
--
--
--
--
--
--
--
INT2R[6:0]
RPINR3 06A6 --
--
--
--
--
--
--
--
--
T2CKR[6:0]
RPINR7 06AE --
IC2R[6:0]
--
IC1R[6:0]
RPINR8 06B0 --
IC4R[6:0]
--
IC3R[6:0]
RPINR11 06B6 --
--
--
--
--
--
--
--
--
OCFAR[6:0]
RPINR12 06B8 --
FLT2R[6:0]
--
FLT1R[6:0]
RPINR14 06BC --
QEB1R[6:0]
--
QEA1R[6:0]
RPINR15 06BE --
HOME1R[6:0]
--
INDX1R[6:0]
RPINR18 06C4 --
--
--
--
--
--
--
--
--
U1RXR[6:0]
RPINR19 06C6 --
--
--
--
--
--
--
--
--
U2RXR[6:0]
RPINR22 06CC --
SCK2INR[6:0]
--
SDI2R[6:0]
RPINR23 06CE --
--
--
--
--
--
--
--
--
SS2R[6:0]
RPINR26 06D4 --
--
--
--
--
--
--
--
--
--
--
--
--
--
RPINR37 06EA --
SYNCI1R[6:0]
--
--
--
--
--
--
RPINR38 06EC --
DTCMP1R[6:0]
--
--
--
--
--
--
RPINR39 06EE --
DTCMP3R[6:0]
--
DTCMP2R[6:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 1 --
-- -- --
Bit 0 --
-- -- --
All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2011-2020 Microchip Technology Inc.
TABLE 4-30: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RPINR0 06A0 --
INT1R[6:0]
--
--
--
--
--
--
RPINR1 06A2 --
--
--
--
--
--
--
--
--
INT2R[6:0]
RPINR3 06A6 --
--
--
--
--
--
--
--
--
T2CKR[6:0]
RPINR7 06AE --
IC2R[6:0]
--
IC1R[6:0]
RPINR8 06B0 --
IC4R[6:0]
--
IC3R[6:0]
RPINR11 06B6 --
--
--
--
--
--
--
--
--
OCFAR[6:0]
RPINR18 06C4 --
--
--
--
--
--
--
--
--
U1RXR[6:0]
RPINR19 06C6 --
--
--
--
--
--
--
--
--
U2RXR[6:0]
RPINR22 06CC --
SCK2INR[6:0]
--
SDI2R[6:0]
RPINR23 06CE --
--
--
--
--
--
--
--
--
SS2R[6:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 1 --
Bit 0 --
All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-31: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
File Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RPINR0 06A0 --
INT1R[6:0]
--
--
--
--
--
--
RPINR1 06A2 --
--
--
--
--
--
--
--
--
INT2R[6:0]
RPINR3 06A6 --
--
--
--
--
--
--
--
--
T2CKR[6:0]
RPINR7 06AE --
IC2R[6:0]
--
IC1R[6:0]
RPINR8 06B0 --
IC4R[6:0]
--
IC3R[6:0]
RPINR11 06B6 --
--
--
--
--
--
--
--
--
OCFAR[6:0]
RPINR18 06C4 --
--
--
--
--
--
--
--
--
U1RXR[6:0]
RPINR19 06C6 --
--
--
--
--
--
--
--
--
U2RXR[6:0]
RPINR22 06CC --
SCK2INR[6:0]
--
SDI2R[6:0]
RPINR23 06CE --
--
--
--
--
--
--
--
--
SS2R[6:0]
RPINR26 06D4 --
--
--
--
--
--
--
--
--
C1RXR[6:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 1 --
Bit 0 --
All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TABLE 4-32: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
File Name Addr. Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RPINR0 06A0 --
INT1R[6:0]
--
--
--
--
--
--
RPINR1 06A2 --
--
--
--
--
--
--
--
--
INT2R[6:0]
RPINR3 06A6 --
--
--
--
--
--
--
--
--
T2CKR[6:0]
RPINR7 06AE --
IC2R[6:0]
--
IC1R[6:0]
RPINR8 06B0 --
IC4R[6:0]
--
IC3R[6:0]
RPINR11 06B6 --
--
--
--
--
--
--
--
--
OCFAR[6:0]
RPINR12 06B8 --
FLT2R[6:0]
--
FLT1R[6:0]
RPINR14 06BC --
QEB1R[6:0]
--
QEA1R[6:0]
RPINR15 06BE --
HOME1R[6:0]
--
INDX1R[6:0]
RPINR18 06C4 --
--
--
--
--
--
--
--
--
U1RXR[6:0]
RPINR19 06C6 --
--
--
--
--
--
--
--
--
U2RXR[6:0]
RPINR22 06CC --
SCK2INR[6:0]
--
SDI2R[6:0]
RPINR23 06CE --
--
--
--
--
--
--
--
--
SS2R[6:0]
RPINR26 06D4 --
--
--
--
--
--
--
--
--
C1RXR[6:0]
RPINR37 06EA --
SYNCI1R[6:0]
--
--
--
--
--
--
RPINR38 06EC --
DTCMP1R[6:0]
--
--
--
--
--
--
RPINR39 06EE --
DTCMP3R[6:0]
--
DTCMP2R[6:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 1 --
-- --
Bit 0 --
-- --
All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DS70000657J-page 93
2011-2020 Microchip Technology Inc.
DS70000657J-page 94
TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
File Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RPINR0 06A0 --
INT1R[6:0]
--
--
--
--
--
--
RPINR1 06A2 --
--
--
--
--
--
--
--
--
INT2R[6:0]
RPINR3 06A6 --
--
--
--
--
--
--
--
--
T2CKR[6:0]
RPINR7 06AE --
IC2R[6:0]
--
IC1R[6:0]
RPINR8 06B0 --
IC4R[6:0]
--
IC3R[6:0]
RPINR11 06B6 --
--
--
--
--
--
--
--
--
OCFAR[6:0]
RPINR12 06B8 --
FLT2R[6:0]
--
FLT1R[6:0]
RPINR14 06BC --
QEB1R[6:0]
--
QEA1R[6:0]
RPINR15 06BE --
HOME1R[6:0]
--
INDX1R[6:0]
RPINR18 06C4 --
--
--
--
--
--
--
--
--
U1RXR[6:0]
RPINR19 06C6 --
--
--
--
--
--
--
--
--
U2RXR[6:0]
RPINR22 06CC --
SCK2INR[6:0]
--
SDI2R[6:0]
RPINR23 06CE --
--
--
--
--
--
--
--
--
SS2R[6:0]
RPINR37 06EA --
SYNCI1R[6:0]
--
--
--
--
--
--
RPINR38 06EC --
DTCMP1R[6:0]
--
--
--
--
--
--
RPINR39 06EE --
DTCMP3R[6:0]
--
DTCMP2R[6:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 1 --
-- --
Bit 0 --
-- --
All Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-34: NVM REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13
Bit 12 Bit 11 Bit 10
NVMCON
0728
WR
WREN WRERR NVMSIDL --
--
NVMADRL 072A
NVMADRH 072C
--
--
--
--
--
--
NVMKEY
072E
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 9 --
-- --
Bit 8
Bit 7
--
--
NVMADR[15:0]
--
--
Bit 6 --
Bit 5 --
Bit 4 --
Bit 3
Bit 2
Bit 1
NVMOP[3:0]
NVMADR[23:16] NVMKEY[7:0]
Bit 0
All Resets
0000 0000 0000 0000
TABLE 4-35: SYSTEM CONTROL REGISTER MAP
File Name Addr. Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1
RCON
0740 TRAPR IOPUWR
--
-- VREGSF --
OSCCON 0742
--
COSC[2:0]
--
CLKDIV
0744 ROI
DOZE[2:0]
DOZEN
PLLFBD
0746
--
--
--
--
--
--
OSCTUN 0748
--
--
--
--
--
--
Legend: Note 1:
2:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. RCON register Reset values are dependent on the type of Reset.
OSCCON register Reset values are dependent on the Configuration Fuses.
CM
VREGS
NOSC[2:0]
FRCDIV[2:0]
--
--
--
EXTR
SWR
CLKLOCK IOLOCK
PLLPOST[1:0]
--
--
SWDTEN WDTO
LOCK
--
--
PLLDIV[8:0]
SLEEP IDLE BOR
CF
--
--
PLLPRE[4:0]
TUN[5:0]
Bit 0
All Resets
POR Note 1 OSWEN Note 2
3040 0030 0000
TABLE 4-36: REFERENCE CLOCK REGISTER MAP
File Name Addr. Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
REFOCON 074E ROON
--
ROSSLP ROSEL
RODIV[3:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 8
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 --
Bit 3 Bit 2
--
--
Bit 1 --
Bit 0 --
All Resets
0000
DS70000657J-page 95
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 96
TABLE 4-37: PMD REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
PMD1 PMD2 PMD3 PMD4 PMD6
0760 0762 0764 0766 076A
T5MD -- -- -- --
T4MD -- -- -- --
T3MD -- -- -- --
T2MD -- -- -- --
T1MD IC4MD
-- -- --
-- IC3MD CMPMD
-- --
-- IC2MD
-- -- --
-- IC1MD
-- -- --
I2C1MD --
CRCMD -- --
Bit 6
U2MD -- -- -- --
PMD7 076C
--
--
--
--
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
U1MD -- -- -- --
--
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
SPI2MD -- -- -- --
DMA0MD DMA1MD DMA2MD DMA3MD
SPI1MD OC4MD
-- REFOMD
--
PTGMD
-- OC3MD
-- CTMUMD
--
--
-- OC2MD I2C2MD
-- --
--
AD1MD OC1MD
-- -- --
--
0000 0000 0000 0000 0000
0000
TABLE 4-38: PMD REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
PMD1 PMD2 PMD3 PMD4 PMD6
0760 0762 0764 0766 076A
T5MD -- -- -- --
T4MD -- -- -- --
T3MD -- -- -- --
T2MD -- -- -- --
T1MD IC4MD
-- -- --
QEI1MD IC3MD CMPMD
-- PWM3MD
PWMMD
--
IC2MD IC1MD
--
--
--
--
PWM2MD PWM1MD
I2C1MD --
CRCMD -- --
PMD7 076C --
--
--
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 6
U2MD -- -- -- --
--
Bit 5
U1MD -- -- -- --
--
Bit 4
Bit 3
Bit 2
Bit 1
SPI2MD SPI1MD
--
--
--
OC4MD OC3MD OC2MD
--
--
--
I2C2MD
-- REFOMD CTMUMD --
--
--
--
--
DMA0MD
DMA1MD
PTGMD
--
--
DMA2MD
DMA3MD
Bit 0
All Resets
AD1MD OC1MD
-- -- --
0000 0000 0000 0000 0000
--
0000
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-39: PMD REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
PMD1 PMD2 PMD3 PMD4 PMD6
0760 0762 0764 0766 076A
T5MD -- -- -- --
T4MD -- -- -- --
T3MD -- -- -- --
T2MD -- -- -- --
T1MD IC4MD
-- -- --
-- IC3MD CMPMD
-- --
-- IC2MD
-- -- --
-- IC1MD
-- -- --
I2C1MD --
CRCMD -- --
U2MD -- -- -- --
PMD7 076C --
--
--
--
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
U1MD -- -- -- --
--
Bit 4
Bit 3
Bit 2
Bit 1
SPI2MD SPI1MD
--
C1MD
--
OC4MD OC3MD OC2MD
--
--
--
I2C2MD
-- REFOMD CTMUMD --
--
--
--
--
DMA0MD
DMA1MD
PTGMD
--
--
DMA2MD
DMA3MD
Bit 0
All Resets
AD1MD OC1MD
-- -- --
0000 0000 0000 0000 0000
--
0000
TABLE 4-40: PMD REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
PMD1 PMD2 PMD3 PMD4 PMD6
0760 0762 0764 0766 076A
T5MD -- -- -- --
T4MD -- -- -- --
T3MD -- -- -- --
T2MD -- -- -- --
T1MD IC4MD
-- -- --
QEI1MD PWMMD
--
IC3MD IC2MD IC1MD
CMPMD
--
--
--
--
--
PWM3MD PWM2MD PWM1MD
I2C1MD --
CRCMD -- --
U2MD -- -- -- --
PMD7 076C --
--
--
--
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
U1MD -- -- -- --
--
Bit 4
Bit 3
Bit 2
Bit 1
SPI2MD SPI1MD
--
C1MD
--
OC4MD OC3MD OC2MD
--
--
--
I2C2MD
-- REFOMD CTMUMD --
--
--
--
--
DMA0MD
DMA1MD
PTGMD
--
--
DMA2MD
DMA3MD
Bit 0
All Resets
AD1MD OC1MD
-- -- --
0000 0000 0000 0000 0000
--
0000
DS70000657J-page 97
2011-2020 Microchip Technology Inc.
DS70000657J-page 98
TABLE 4-41: PMD REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
PMD1 PMD2 PMD3 PMD4 PMD6
0760 0762 0764 0766 076A
T5MD -- -- -- --
T4MD -- -- -- --
T3MD -- -- -- --
T2MD -- -- -- --
T1MD IC4MD
-- -- --
QEI1MD IC3MD CMPMD
-- PWM3MD
PWMMD
--
IC2MD IC1MD
--
--
--
--
PWM2MD PWM1MD
I2C1MD --
CRCMD -- --
U2MD -- -- -- --
PMD7 076C --
--
--
--
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 5
U1MD -- -- -- --
--
Bit 4
Bit 3
Bit 2
Bit 1
SPI2MD SPI1MD
--
--
--
OC4MD OC3MD OC2MD
--
--
--
I2C2MD
-- REFOMD CTMUMD --
--
--
--
--
DMA0MD
DMA1MD
PTGMD
--
--
DMA2MD
DMA3MD
Bit 0
All Resets
AD1MD OC1MD
-- -- --
0000 0000 0000 0000 0000
--
0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-42: OP AMP/COMPARATOR REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
CMSTAT
0A80 PSIDL
--
--
--
C4EVT C3EVT C2EVT C1EVT
--
--
--
--
CVRCON
0A82 --
CVR2OE
--
--
--
VREFSEL
--
--
CVREN CVR1OE CVRR CVRSS
CM1CON
0A84 CON
COE
CPOL
--
--
OPMODE CEVT
COUT
EVPOL[1:0]
--
CREF
CM1MSKSRC 0A86 --
--
--
--
SELSRCC[3:0]
SELSRCB[3:0]
CM1MSKCON 0A88 HLMS
--
OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN
CM1FLTR
0A8A --
--
--
--
--
--
--
--
--
CFSEL[2:0]
CM2CON
0A8C CON
COE
CPOL
--
--
OPMODE CEVT
COUT
EVPOL[1:0]
--
CREF
CM2MSKSRC 0A8E --
--
--
--
SELSRCC[3:0]
SELSRCB[3:0]
CM2MSKCON 0A90 HLMS
--
OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN
CM2FLTR CM3CON(1) CM3MSKSRC(1) CM3MSKCON(1) CM3FLTR(1)
0A92 0A94 0A96 0A98 0A9A
-- CON
-- HLMS
--
-- COE
-- -- --
-- CPOL
-- OCEN
--
-- -- -- OCNEN --
-- --
OBEN --
--
--
OPMODE CEVT
SELSRCC[3:0]
OBNEN OAEN
--
--
-- COUT
OANEN --
--
CFSEL[2:0]
EVPOL[1:0]
--
CREF
SELSRCB[3:0]
NAGS PAGS ACEN ACNEN
--
CFSEL[2:0]
CM4CON
0A9C CON
COE
CPOL
--
--
--
CEVT
COUT
EVPOL[1:0]
--
CREF
CM4MSKSRC 0A9E --
--
--
--
SELSRCC[3:0]
SELSRCB[3:0]
CM4MSKCON 0AA0 HLMS
--
OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN
CM4FLTR
0AA2 --
--
--
--
--
--
--
--
--
CFSEL[2:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: These registers are unavailable on dsPIC33EPXXXGP502/MC502/MC202 and PIC24EP256GP/MC202 (28-pin) devices.
C4OUT
--
ABEN CFLTREN
--
ABEN CFLTREN
--
ABEN CFLTREN
--
ABEN CFLTREN
C3OUT C2OUT C1OUT
CVR[3:0]
--
CCH[1:0]
SELSRCA[3:0]
ABNEN AAEN AANEN
CFDIV[2:0]
--
CCH[1:0]
SELSRCA[3:0]
ABNEN AAEN AANEN
CFDIV[2:0]
--
CCH[1:0]
SELSRCA[3:0]
ABNEN AAEN AANEN
CFDIV[2:0]
--
CCH[1:0]
SELSRCA[3:0]
ABNEN AAEN AANEN
CFDIV[2:0]
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TABLE 4-43: CTMU REGISTER MAP
File Name Addr. Bit 15
Bit 14
Bit 13 Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
CTMUCON1 033A CTMUEN
--
CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG
--
--
--
CTMUCON2 033C EDG1MOD EDG1POL
EDG1SEL[3:0]
EDG2STAT EDG1STAT EDG2MOD EDG2POL
CTMUICON 033E
ITRIM[5:0]
IRNG[1:0]
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 4 Bit 3
--
--
EDG2SEL[3:0]
--
--
Bit 2 -- --
Bit 1
-- -- --
Bit 0
All Resets
-- 0000 -- 0000 -- 0000
TABLE 4-44: JTAG INTERFACE REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
JDATAH JDATAL Legend:
0FF0
--
--
--
--
0FF2
JDATAL[15:0]
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 6
Bit 5
JDATAH[27:16]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
xxxx 0000
DS70000657J-page 99
2011-2020 Microchip Technology Inc.
DS70000657J-page 100
TABLE 4-45: DMAC REGISTER MAP
File Name Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
DMA0CON 0B00 CHEN
SIZE
DIR
HALF NULLW
--
DMA0REQ 0B02 FORCE
--
--
--
--
--
DMA0STAL 0B04
DMA0STAH 0B06
--
--
--
--
--
--
DMA0STBL 0B08
DMA0STBH 0B0A
--
--
--
--
--
--
DMA0PAD 0B0C
DMA0CNT 0B0E
--
--
DMA1CON 0B10 CHEN
SIZE
DIR
HALF NULLW
--
DMA1REQ 0B12 FORCE
--
--
--
--
--
DMA1STAL 0B14
DMA1STAH 0B16
--
--
--
--
--
--
DMA1STBL 0B18
DMA1STBH 0B1A
--
--
--
--
--
--
DMA1PAD 0B1C
DMA1CNT 0B1E
--
--
DMA2CON 0B20 CHEN
SIZE
DIR
HALF NULLW
--
DMA2REQ 0B22 FORCE
--
--
--
--
--
DMA2STAL 0B24
DMA2STAH 0B26
--
--
--
--
--
--
DMA2STBL 0B28
DMA2STBH 0B2A
--
--
--
--
--
--
DMA2PAD 0B2C
DMA2CNT 0B2E
--
--
DMA3CON 0B30 CHEN
SIZE
DIR
HALF NULLW
--
DMA3REQ 0B32 FORCE
--
--
--
--
--
DMA3STAL 0B34
DMA3STAH 0B36
--
--
--
--
--
--
DMA3STBL 0B38
DMA3STBH 0B3A
--
--
--
--
--
--
DMA3PAD 0B3C
DMA3CNT 0B3E
--
--
DMAPWC 0BF0
--
--
--
--
--
--
DMARQC 0BF2
--
--
--
--
--
--
DMAPPS 0BF4
--
--
--
--
--
--
DMALCA 0BF6
--
--
--
--
--
--
DSADRL 0BF8
DSADRH 0BFA
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 9 -- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- -- --
Bit 8
Bit 7
Bit 6
--
--
--
--
STA[15:0]
--
STB[15:0]
--
PAD[15:0]
CNT[13:0]
--
--
--
--
STA[15:0]
--
STB[15:0]
--
PAD[15:0]
CNT[13:0]
--
--
--
--
STA[15:0]
--
STB[15:0]
--
PAD[15:0]
CNT[13:0]
--
--
--
--
STA[15:0]
--
STB[15:0]
--
PAD[15:0]
CNT[13:0]
--
--
--
--
--
--
--
--
--
--
--
--
DSADR[15:0]
--
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
AMODE[1:0]
--
--
IRQSEL[7:0]
STA[23:16]
STB[23:16]
MODE[1:0]
AMODE[1:0]
--
--
IRQSEL[7:0]
STA[23:16]
STB[23:16]
MODE[1:0]
AMODE[1:0]
--
--
IRQSEL[7:0]
STA[23:16]
STB[23:16]
MODE[1:0]
AMODE[1:0]
--
--
IRQSEL[7:0]
STA[23:16]
STB[23:16]
MODE[1:0]
--
-- PWCOL3 PWCOL2 PWCOL1 PWCOL0
--
-- RQCOL3 RQCOL2 RQCOL1 RQCOL0
--
--
PPST3 PPST2 PPST1 PPST0
--
--
LSTCH[3:0]
DSADR[23:16]
0000 00FF 0000 0000 0000 0000 0000 0000 0000 00FF 0000 0000 0000 0000 0000 0000 0000 00FF 0000 0000 0000 0000 0000 0000 0000 00FF 0000 0000 0000 0000 0000 0000 0000 0000 0000 000F 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-46: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14 Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA 0E00
--
--
--
TRISA[12:7]
--
--
TRISA4
--
--
PORTA 0E02
--
--
--
RA[12:7]
--
--
RA4
--
--
LATA
0E04
--
--
--
LATA[12:7]
--
--
LATA4
--
--
ODCA 0E06
--
--
--
ODCA[12:7]
--
--
ODCA4
--
--
CNENA 0E08
--
--
--
CNIEA[12:7]
--
--
CNIEA4
--
--
CNPUA 0E0A
--
--
--
CNPUA[12:7]
--
-- CNPUA4 --
--
CNPDA 0E0C
--
--
--
CNPDA[12:7]
--
-- CNPDA4 --
--
ANSELA 0E0E
--
--
--
ANSA[12:11]
--
--
--
--
--
--
ANSA4
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TRISA[1:0] RA[1:0]
LA1TA[1:0] ODCA[1:0] CNIEA[1:0] CNPUA[1:0] CNPDA[1:0] ANSA[1:0]
All Resets
1F93 0000 0000 0000 0000 0000 0000 1813
TABLE 4-47: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISB 0E10
TRISB[15:0]
PORTB 0E12
RB[15:0]
LATB 0E14
LATB[15:0]
ODCB 0E16
ODCB[15:0]
CNENB 0E18
CNIEB[15:0]
CNPUB 0E1A
CNPUB[15:0]
CNPDB 0E1C
CNPDB[15:0]
ANSELB 0E1E
--
--
--
--
--
--
--
ANSB8
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ANSB[3:0]
Bit 0
All Resets
FFFF xxxx xxxx 0000 0000 0000 0000 010F
DS70000657J-page 101
TABLE 4-48: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISC 0E20 TRISC15 --
TRISC[13:0]
PORTC 0E22 RC15
--
RC[13:0]
LATC
0E24 LATC15
--
LATC[13:0]
ODCC 0E26 ODCC15 --
ODCC[13:0]
CNENC 0E28 CNIEC15 --
CNIEC[13:0]
CNPUC 0E2A CNPUC15 --
CNPUC[13:0]
CNPDC 0E2C CNPDC15 --
CNPDC[13:0]
ANSELC 0E2E
--
--
--
--
ANSC11
--
--
--
--
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ANSC[2:0]
Bit 0
All Resets
BFFF xxxx xxxx 0000 0000 0000 0000 0807
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 102
TABLE 4-49: PORTD REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISD 0E30
--
--
--
--
--
--
--
TRISD8
--
PORTD 0E32
--
--
--
--
--
--
--
RD8
--
LATD
0E34
--
--
--
--
--
--
--
LATD8
--
ODCD 0E36
--
--
--
--
--
--
--
ODCD8
--
CNEND 0E38
--
--
--
--
--
--
--
CNIED8
--
CNPUD 0E3A
--
--
--
--
--
--
--
CNPUD8
--
CNPDD 0E3C
--
--
--
--
--
--
--
CNPDD8
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TRISD[6:5] RD[6:5]
LATD[6:5] ODCD[6:5] CNIED[6:5] CNPUD[6:5] CNPDD[6:5]
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 0
-- -- -- -- -- -- --
All Resets
0160 xxxx xxxx 0000 0000 0000 0000
TABLE 4-50: PORTE REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISE 0E40
TRISE[15:12]
--
--
--
--
--
--
--
--
--
--
--
PORTE 0E42
RE[15:12]
--
--
--
--
--
--
--
--
--
--
--
LATE
0E44
LATE[15:12]
--
--
--
--
--
--
--
--
--
--
--
ODCE 0E46
ODCE[15:12]
--
--
--
--
--
--
--
--
--
--
--
CNENE 0E48
CNIEE[15:12]
--
--
--
--
--
--
--
--
--
--
--
CNPUE 0E4A
CNPUE[15:12]
--
--
--
--
--
--
--
--
--
--
--
CNPDE 0E4C
CNPDE[15:12]
--
--
--
--
--
--
--
--
--
--
--
ANSELE 0E4E
ANSE[15:12]
--
--
--
--
--
--
--
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Bit 0
-- -- -- -- -- -- -- --
All Resets
F000 xxxx xxxx 0000 0000 0000 0000 F000
2011-2020 Microchip Technology Inc.
TABLE 4-51: PORTF REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISF
0E50
--
--
--
--
--
--
--
--
--
--
--
--
--
--
PORTF 0E52
--
--
--
--
--
--
--
--
--
--
--
--
--
--
LATF
0E54
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ODCF
0E56
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CNENF 0E58
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CNPUF 0E5A --
--
--
--
--
--
--
--
--
--
--
--
--
--
CNPDF 0E5C --
--
--
--
--
--
--
--
--
--
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TRISF[1:0] RF[1:0]
LATF[1:0] ODCF[1:0] CNIEF[1:0] CNPUF[1:0] CNPDF[1:0]
All Resets
0003 xxxx xxxx 0000 0000 0000 0000
DS70000657J-page 103
2011-2020 Microchip Technology Inc.
TABLE 4-52: PORTG REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISG PORTG LATG ODCG CNENG CNPUG CNPDG Legend:
0E60 --
--
--
--
--
--
TRISG[9:6]
0E62 --
--
--
--
--
--
RG[9:6]
0E64 --
--
--
--
--
--
LATG[9:6]
0E66 --
--
--
--
--
--
ODCG[9:6]
0E68 --
--
--
--
--
--
CNIEG[9:6]
0E6A --
--
--
--
--
--
CNPUG[9:6]
0E6C --
--
--
--
--
--
CNPDG[9:6]
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 0
-- -- -- -- -- -- --
All Resets
03C0 xxxx xxxx 0000 0000 0000 0000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 104
TABLE 4-53: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14 Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA 0E00
--
--
--
--
--
TRISA[10:7]
--
--
TRISA[4:0]
PORTA 0E02
--
--
--
--
--
RA[10:7]
--
--
RA[4:0]
LATA
0E04
--
--
--
--
--
LATA[10:7]
--
--
LATA[4:0]
ODCA 0E06
--
--
--
--
--
ODCA[10:7]
--
--
ODCA[4:0]
CNENA 0E08
--
--
--
--
--
CNIEA[10:7]
--
--
CNIEA[4:0]
CNPUA 0E0A
--
--
--
--
--
CNPUA[10:7]
--
--
CNPUA[4:0]
CNPDA 0E0C
--
--
--
--
--
CNPDA[10:7]
--
--
CNPDA[4:0]
ANSELA 0E0E
--
--
--
--
--
--
--
--
--
--
--
ANSA4
--
--
ANSA[1:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
All Resets
079F 0000 0000 0000 0000 0000 0000 0013
TABLE 4-54: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISB 0E10
TRISB[15:0]
PORTB 0E12
RB[15:0]
LATB 0E14
LATB[15:0]
ODCB 0E16
ODCB[15:0]
CNENB 0E18
CNIEB[15:0]
CNPUB 0E1A
CNPUB[15:0]
CNPDB 0E1C
CNPDB[15:0]
ANSELB 0E1E
--
--
--
--
--
--
--
ANSB8
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ANSB[3:0]
Bit 0
All Resets
FFFF xxxx xxxx 0000 0000 0000 0000 010F
2011-2020 Microchip Technology Inc.
TABLE 4-55: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISC 0E20
--
--
--
--
--
--
TRISC[9:0]
PORTC 0E22
--
--
--
--
--
--
RC[9:0]
LATC
0E24
--
--
--
--
--
--
LATC[9:0]
ODCC 0E26
--
--
--
--
--
--
ODCC[9:0]
CNENC 0E28
--
--
--
--
--
--
CNIEC[9:0]
CNPUC 0E2A
--
--
--
--
--
--
CNPUC[9:0]
CNPDC 0E2C --
--
--
--
--
--
CNPDC[9:0]
ANSELC 0E2E
--
--
--
--
--
--
--
--
--
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ANSC[2:0]
Bit 0
All Resets
03FF xxxx xxxx 0000 0000 0000 0000 0007
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
TABLE 4-56: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14 Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA 0E00
--
--
--
--
--
--
PORTA 0E02
--
--
--
--
--
--
LATA
0E04
--
--
--
--
--
--
ODCA 0E06
--
--
--
--
--
--
CNENA 0E08
--
--
--
--
--
--
CNPUA 0E0A
--
--
--
--
--
--
CNPDA 0E0C
--
--
--
--
--
--
ANSELA 0E0E
--
--
--
--
--
--
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
--
TRISA8
--
--
--
TRISA[4:0]
--
RA8
--
--
--
RA[4:0]
--
LATA8
--
--
--
LATA[4:0]
--
ODCA8
--
--
--
ODCA[4:0]
--
CNIEA8
--
--
--
CNIEA[4:0]
--
CNPUA8
--
--
--
CNPUA[4:0]
--
CNPDA8
--
--
--
CNPDA[4:0]
--
--
--
--
--
ANSA4
--
--
ANSA[1:0]
All Resets
011F 0000 0000 0000 0000 0000 0000 0013
TABLE 4-57: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISB 0E10
TRISB[15:0]
PORTB 0E12
RB[15:0]
LATB
0E14
LATB[15:0]
ODCB 0E16
ODCB[15:0]
CNENB 0E18
CNIEB[15:0]
CNPUB 0E1A
CNPUB[15:0]
CNPDB 0E1C
CNPDB[15:0]
ANSELB 0E1E
--
--
--
--
--
--
--
ANSB8
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ANSB[3:0]
Bit 0
All Resets
FFFF xxxx xxxx 0000 0000 0000 0000 010F
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TABLE 4-58: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISC 0E20
--
--
--
--
--
--
--
TRISC8
--
--
--
--
--
--
PORTC 0E22
--
--
--
--
--
--
--
RC8
--
--
--
--
--
--
LATC
0E24
--
--
--
--
--
--
--
LATC8
--
--
--
--
--
--
ODCC 0E26
--
--
--
--
--
--
--
ODCC8
--
--
--
--
--
--
CNENC 0E28
--
--
--
--
--
--
--
CNIEC8
--
--
--
--
--
--
CNPUC 0E2A
--
--
--
--
--
--
-- CNPUC8 --
--
--
--
--
--
CNPDC 0E2C
--
--
--
--
--
--
-- CNPDC8 --
--
--
--
--
--
ANSELC 0E2E
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TRISC[1:0] RC[1:0]
LATC[1:0] ODCC[1:0] CNIEC[1:0] CNPUC[1:0] CNPDC[1:0] ANSC[1:0]
All Resets
0103 xxxx xxxx 0000 0000 0000 0000 0003
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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TABLE 4-59: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14 Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA 0E00
--
--
--
--
--
--
--
--
--
--
--
TRISA[4:0]
PORTA 0E02
--
--
--
--
--
--
--
--
--
--
--
RA[4:0]
LATA
0E04
--
--
--
--
--
--
--
--
--
--
--
LATA[4:0]
ODCA 0E06
--
--
--
--
--
--
--
--
--
--
--
ODCA[4:0]
CNENA 0E08
--
--
--
--
--
--
--
--
--
--
--
CNIEA[4:0]
CNPUA 0E0A
--
--
--
--
--
--
--
--
--
--
--
CNPUA[4:0]
CNPDA 0E0C
--
--
--
--
--
--
--
--
--
--
--
CNPDA[4:0]
ANSELA 0E0E
--
--
--
--
--
--
--
--
--
--
--
ANSA4
--
--
ANSA[1:0]
Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
All Resets
001F 0000 0000 0000 0000 0000 0000 0013
TABLE 4-60: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISB 0E10
TRISB[15:0]
PORTB 0E12
RB[15:0]
LATB
0E14
LATB[15:0]
ODCB 0E16
ODCB[15:0]
CNENB 0E18
CNIEB[15:0]
CNPUB 0E1A
CNPUB[15:0]
CNPDB 0E1C
CNPDB[15:0]
ANSELB 0E1E
--
--
--
--
--
--
--
ANSB8
--
--
--
--
Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
ANSB[3:0]
Bit 0
All Resets
FFFF xxxx xxxx 0000 0000 0000 0000 010F
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4.4.1 PAGED MEMORY SCHEME
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X architecture extends the available Data Space through a paging scheme, which allows the available Data Space to be accessed using MOV instructions in a linear fashion for pre-modified and post-modified Effective Addresses (EA). The upper half of the base Data Space address is used in conjunction with the Data Space Page registers, the 10-bit Read Page register (DSRPAG) or the 9-bit Write Page register (DSWPAG), to form an
Extended Data Space (EDS) address or Program Space Visibility (PSV) address. The Data Space Page registers are located in the SFR space.
Construction of the EDS address is shown in Example 4-1. When DSRPAG[9] = 0 and the base address bit, EA[15] = 1, the DSRPAG[8:0] bits are concatenated onto EA[14:0] to form the 24-bit EDS read address. Similarly, when base address bit, EA[15] = 1, DSWPAG[8:0] are concatenated onto EA[14:0] to form the 24-bit EDS write address.
EXAMPLE 4-1:
EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
16-Bit DS EA
Byte Select
EA[15] = 0 (DSRPAG = Don't care)
Generate PSV Address
No EDS Access
0
EA[15] Y DSRPAG[9] 1
= 1?
Select N DSRPAG
0
DSRPAG[8:0]
9 Bits
EA EA
15 Bits
24-Bit EDS EA Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Byte Select
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EXAMPLE 4-2: EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION
EA[15] = 0 (DSWPAG = don't care)
16-Bit DS EA
Byte Select
Generate
No EDS Access
0
EA
PSV Address
EA[15]
1
EA
DSWPAG[8:0]
9 Bits
15 Bits
24-Bit EDS EA Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Byte Select
The paged memory scheme provides access to multiple 32-Kbyte windows in the EDS and PSV memory. The Data Space Page registers, DSxPAG, in combination with the upper half of the Data Space address, can provide up to 16 Mbytes of additional address space in the EDS and 8 Mbytes (DSRPAG only) of PSV address space. The paged data memory space is shown in Example 4-3.
The Program Space (PS) can be accessed with a DSRPAG of 0x200 or greater. Only reads from PS are supported using the DSRPAG. Writes to PS are not supported, so DSWPAG is dedicated to DS, including EDS only. The Data Space and EDS can be read from, and written to, using DSRPAG and DSWPAG, respectively.
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2011-2020 Microchip Technology Inc.
EXAMPLE 4-3: PAGED DATA MEMORY SPACE
Local Data Space
EDS (DSRPAG[9:0]/DSWPAG[8:0])
DS_Addr[14:0]
0x0000
Page 0
Reserved
(Will produce an
0x7FFF address error trap)
0x0000 0x7FFF
EDS Page 0x001 (DSRPAG = 0x001) (DSWPAG = 0x001)
Program Space (Instruction & Data)
Table Address Space (TBLPAG[7:0])
Program Memory (lsw [15:0])
0x00_0000
DS_Addr[15:0] 0x0000
0xFFFF
(TBLPAG = 0x00) lsw Using
TBLRDL/TBLWTL MSB Using
TBLRDH/TBLWTH
DS_Addr[15:0] 0x0000 0x0FFF 0x1000
0x2FFF 0x3000 0x7FFF 0x8000
0xFFFF
SFR Registers
Up to 8-Kbyte RAM(1)
32-Kbyte EDS Window
0x0000
0x7FFF 0x0000
0x7FFF
EDS Page 0x1FF (DSRPAG = 0x1FF) (DSWPAG = 0x1FF)
EDS Page 0x200 (DSRPAG = 0x200) No writes allowed
0x0000
0x7FFF 0x0000
0x7FFF
EDS Page 0x2FF (DSRPAG = 0x2FF) No writes allowed
EDS Page 0x300 (DSRPAG = 0x300) No writes allowed
0x0000 0x7FFF
EDS Page 0x3FF (DSRPAG = 0x3FF) No writes allowed
PSV Program Memory
(lsw)
PSV Program Memory
(MSB)
0x7F_FFFF
Program Memory (MSB [23:16]) 0x00_0000
0x0000 0xFFFF
0x7F_FFFF
Note 1: For 64K Flash devices. RAM size and end location is dependent on device; see Section 4.2 "Data Address Space" for more information.
(TBLPAG = 0x7F) lsw Using
TBLRDL/TBLWTL MSB Using
TBLRDH/TBLWTH
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Allocating different Page registers for read and write access allows the architecture to support data movement between different pages in data memory. This is accomplished by setting the DSRPAG register value to the page from which you want to read, and configuring the DSWPAG register to the page to which it needs to be written. Data can also be moved from different PSV to EDS pages, by configuring the DSRPAG and DSWPAG registers to address PSV and EDS space, respectively. The data can be moved between pages by a single instruction.
When an EDS or PSV page overflow or underflow occurs, EA[15] is cleared as a result of the register indirect EA calculation. An overflow or underflow of the EA in the EDS or PSV pages can occur at the page boundaries when:
· The initial address prior to modification addresses an EDS or PSV page
· The EA calculation uses Pre-Modified or Post-Modified Register Indirect Addressing; however, this does not include Register Offset Addressing
In general, when an overflow is detected, the DSxPAG register is incremented and the EA[15] bit is set to keep the base address within the EDS or PSV window. When an underflow is detected, the DSxPAG register is decremented and the EA[15] bit is set to keep the base address within the EDS or PSV window. This creates a linear EDS and PSV address space, but only when using Register Indirect Addressing modes.
Exceptions to the operation described above arise when entering and exiting the boundaries of Page 0, EDS and PSV spaces. Table 4-61 lists the effects of overflow and underflow scenarios at different boundaries.
In the following cases, when overflow or underflow occurs, the EA[15] bit is set and the DSxPAG is not modified; therefore, the EA will wrap to the beginning of the current page:
· Register Indirect with Register Offset Addressing
· Modulo Addressing
· Bit-Reversed Addressing
TABLE 4-61: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS and PSV SPACE BOUNDARIES(2,3,4)
O/U, R/W
Operation
DSxPAG
Before
DS EA[15]
Page Description
DSxPAG
After
DS EA[15]
Page Description
O, Read
DSRPAG = 0x1FF
1 EDS: Last page DSRPAG = 0x1FF
0 See Note 1
O, Read
O, Read
[++Wn] or
[Wn++]
DSRPAG = 0x2FF DSRPAG = 0x3FF
1 PSV: Last lsw DSRPAG = 0x300 page
1 PSV: Last MSB DSRPAG = 0x3FF page
1 PSV: First MSB page
0 See Note 1
O, Write
DSWPAG = 0x1FF
1 EDS: Last page DSWPAG = 0x1FF
0 See Note 1
U, Read
U, Read
U, Read
[--Wn] or
[Wn--]
DSRPAG = 0x001 DSRPAG = 0x200 DSRPAG = 0x300
1 PSV page
DSRPAG = 0x001
1 PSV: First lsw DSRPAG = 0x200 page
1 PSV: First MSB DSRPAG = 0x2FF page
0 See Note 1
0 See Note 1
1 PSV: Last lsw page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x8000).
2: An EDS access with DSxPAG = 0x000 will generate an address error trap.
3: Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate an address error trap.
4: Pseudolinear Addressing is not supported for large offsets.
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4.4.2 EXTENDED X DATA SPACE
The lower portion of the base address space range, between 0x0000 and 0x7FFF, is always accessible regardless of the contents of the Data Space Page registers. It is indirectly addressable through the register indirect instructions. It can be regarded as being located in the default EDS Page 0 (i.e., EDS address range of 0x000000 to 0x007FFF with the base address bit, EA[15] = 0, for this address range). However, Page 0 cannot be accessed through the upper 32 Kbytes, 0x8000 to 0xFFFF, of base Data Space, in combination with DSRPAG = 0x000 or DSWPAG = 0x000. Consequently, DSRPAG and DSWPAG are initialized to 0x001 at Reset.
Note 1: DSxPAG should not be used to access Page 0. An EDS access with DSxPAG set to 0x000 will generate an address error trap.
2: Clearing the DSxPAG in software has no effect.
FIGURE 4-17:
EDS MEMORY MAP
EA[15:0] 0x0000 Conventional DS Address 0x8000
0xFFFF
SFR/DS DS
(PAGE 0)
The remaining pages, including both EDS and PSV pages, are only accessible using the DSRPAG or DSWPAG registers in combination with the upper 32 Kbytes, 0x8000 to 0xFFFF, of the base address, where base address bit, EA[15] = 1.
For example, when DSRPAG = 0x001 or DSWPAG = 0x001, accesses to the upper 32 Kbytes, 0x8000 to 0xFFFF, of the Data Space will map to the EDS address range of 0x008000 to 0x00FFFF. When DSRPAG = 0x002 or DSWPAG = 0x002, accesses to the upper 32 Kbytes of the Data Space will map to the EDS address range of 0x010000 to 0x017FFF and so on, as shown in the EDS memory map in Figure 4-17.
For more information on the PSV page access using Data Space Page registers, refer to the "Program Space Visibility from Data Space" section in "dsPIC33/PIC24 Program Memory" (www.microchip.com/DS70000613) of the "dsPIC33/PIC24 Family Reference Manual".
PAGE 1 PAGE 2 PAGE 3
0x008000 0x010000 0x018000
PAGE 1FD PAGE 1FE PAGE 1FF
0xFE8000 0xFF0000 0xFF8000
DSRPAG[9] = 0 EDS EA Address (24 bits)
(DSRPAG[8:0], EA[14:0]) (DSWPAG[8:0], EA[14:0])
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4.4.3
DATA MEMORY ARBITRATION AND BUS MASTER PRIORITY
EDS accesses from bus masters in the system are arbitrated.
The arbiter for data memory (including EDS) arbitrates between the CPU, the DMA and the ICD module. In the event of coincidental access to a bus by the bus masters, the arbiter determines which bus master access has the highest priority. The other bus masters are suspended and processed after the access of the bus by the bus master with the highest priority.
By default, the CPU is Bus Master 0 (M0) with the highest priority and the ICD is Bus Master 4 (M4) with the lowest priority. The remaining bus master (DMA Controller) is allocated to M3 (M1 and M2 are reserved and cannot be used). The user application may raise or lower the priority of the DMA Controller to be above that of the CPU by setting the appropriate bits in the EDS Bus Master Priority Control (MSTRPR) register. All bus masters with raised priorities will maintain the same priority relationship relative to each other (i.e., M1 being highest and M3 being lowest, with M2 in between). Also, all the bus masters with priorities below
FIGURE 4-18:
ARBITER ARCHITECTURE
that of the CPU maintain the same priority relationship relative to each other. The priority schemes for bus masters with different MSTRPR values are tabulated in Table 4-62.
This bus master priority control allows the user application to manipulate the real-time response of the system, either statically during initialization or dynamically in response to real-time events.
TABLE 4-62: Priority
DATA MEMORY BUS ARBITER PRIORITY
MSTRPR[15:0] Bits Setting(1)
0x0000
0x0020
M0 (highest)
CPU
DMA
M1
Reserved
CPU
M2
Reserved
Reserved
M3
DMA
Reserved
M4 (lowest)
ICD
ICD
Note 1: All other values of MSTRPR[15:0] are reserved.
DMA
Reserved
ICD
CPU
MSTRPR[15:0]
M0 M1 M2 M3 M4 Data Memory Arbiter
SRAM
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4.4.4 SOFTWARE STACK
The W15 register serves as a dedicated Software Stack Pointer (SSP) and is automatically modified by exception processing, subroutine calls and returns; however, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies reading, writing and manipulating of the Stack Pointer (for example, creating stack frames).
Note:
To protect against misaligned stack
accesses, W15[0] is fixed to `0' by the hardware.
W15 is initialized to 0x1000 during all Resets. This address ensures that the SSP points to valid RAM in all dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices, and permits stack availability for non-maskable trap exceptions. These can occur before the SSP is initialized by the user software. You can reprogram the SSP during initialization to any location within Data Space.
The Software Stack Pointer always points to the first available free word and fills the software stack working from lower toward higher addresses. Figure 4-19 illustrates how it pre-decrements for a stack pop (read) and post-increments for a stack push (writes).
When the PC is pushed onto the stack, PC[15:0] are pushed onto the first available stack word, then PC[22:16] are pushed into the second available stack location. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, as shown in Figure 4-19. During exception processing, the MSB of the PC is concatenated with the lower 8 bits of the CPU STATUS Register, SR. This allows the contents of SRL to be preserved automatically during interrupt processing.
Stack Grows Toward Higher Address
Note 1: To maintain system Stack Pointer (W15) coherency, W15 is never subject to (EDS) paging, and is therefore restricted to an address range of 0x0000 to 0xFFFF. The same applies to the W14 when used as a Stack Frame Pointer (SFA = 1).
2: As the stack can be placed in, and can access X and Y spaces, care must be taken regarding its use, particularly with regard to local automatic variables in a C development environment
FIGURE 4-19:
0x0000 15
CALL STACK FRAME
0 CALL SUBR
PC[15:0] b`000000000' PC[22:16]
[Free Word]
W15 (before CALL) W15 (after CALL)
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4.5 Instruction Addressing Modes
The addressing modes shown in Table 4-63 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types.
4.5.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a Working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire Data Space.
4.5.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 [function] Operand 2
where Operand 1 is always a Working register (that is, the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W register fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
· Register Direct · Register Indirect · Register Indirect Post-Modified · Register Indirect Pre-Modified · 5-Bit or 10-Bit Literal
Note:
Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes.
TABLE 4-63: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct Register Direct Register Indirect Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset
The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn form the Effective Address (EA). The contents of Wn form the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. The sum of Wn and Wb forms the EA.
The sum of Wn and a literal forms the EA.
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4.5.3
MOVE AND ACCUMULATOR INSTRUCTIONS
Move
instructions,
which
apply
to
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices, and the
DSP accumulator class of instructions, which
apply to the dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices, provide a greater
degree of addressing flexibility than other instructions.
In addition to the addressing modes supported by most
MCU instructions, move and accumulator instructions
also support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one).
In summary, the following addressing modes are supported by move and accumulator instructions:
· Register Direct · Register Indirect · Register Indirect Post-modified · Register Indirect Pre-modified · Register Indirect with Register Offset (Indexed) · Register Indirect with Literal Offset · 8-Bit Literal · 16-Bit Literal
Note:
Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes.
4.5.4
MAC INSTRUCTIONS (dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY)
The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the Data Pointers through register indirect tables.
The Two-Source Operand Prefetch registers must be members of the set: {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The Effective Addresses generated (before and after modification) must therefore, be valid addresses within X Data Space for W8 and W9, and Y Data Space for W10 and W11.
Note:
Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space).
In summary, the following addressing modes are supported by the MAC class of instructions:
· Register Indirect · Register Indirect Post-Modified by 2 · Register Indirect Post-Modified by 4 · Register Indirect Post-Modified by 6 · Register Indirect with Register Offset (Indexed)
4.5.5 OTHER INSTRUCTIONS
Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ULNK, the source of an operand or result is implied by the opcode itself. Certain operations, such as a NOP, do not have any operands.
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4.6 Modulo Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)
Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms.
Modulo Addressing can operate in either Data or Program Space (since the Data Pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into Program Space) and Y Data Spaces. Modulo Addressing can operate on any W Register Pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively.
Note:
Modulo Addressing has address alignment restrictions for the buffer start or end address. See the "Data Memory" FRM (www.microchip.com/DS70595) for more information.
4.6.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a starting and ending address be specified, and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1).
Note:
Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear).
The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes).
4.6.2
W ADDRESS REGISTER SELECTION
The Modulo and Bit-Reversed Addressing Control register, MODCON[15:0], contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that operate with Modulo Addressing:
· If XWM = 1111, X RAGU and X WAGU Modulo Addressing is disabled
· If YWM = 1111, Y AGU Modulo Addressing is disabled
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in MODCON[3:0] (see Table 4-1). Modulo Addressing is
enabled for X Data Space when XWM is set to any
value other than `1111' and the XMODEN bit is set (MODCON[15]).
The Y Address Space Pointer W register (YWM), to which Modulo Addressing is to be applied, is stored in MODCON[7:4]. Modulo Addressing is enabled for Y Data Space when YWM is set to any value other than `1111' and the YMODEN bit is set at MODCON[14].
FIGURE 4-20:
Byte Address 0x1100
MODULO ADDRESSING OPERATION EXAMPLE
MOV
#0x1100, W0
MOV
W0, XMODSRT ;set modulo start address
MOV
#0x1163, W0
MOV
W0, MODEND
;set modulo end address
MOV
#0x8001, W0
MOV
W0, MODCON
;enable W1, X AGU for modulo
MOV
#0x0000, W0 ;W0 holds buffer fill value
0x1163
Start Addr = 0x1100 End Addr = 0x1163 Length = 50 words
MOV
#0x1110, W1
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;point W1 to buffer
;fill the 50 buffer locations ;fill the next location ;increment the fill value
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Note:
Modulo Addressing has address alignment restrictions for the buffer start or end address. See the "Data Memory" FRM (www.microchip.com/DS70595) for more information.
Note:
The modulo corrected Effective Address is written back to the register only when Pre-Modify or Post-Modify Addressing mode is used to compute the Effective Address. When an address offset (such as [W7 + W2]) is used, Modulo Addressing correction is performed but the contents of the register remain unchanged.
4.7 Bit-Reversed Addressing (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X Devices Only)
Bit-Reversed Addressing mode is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.
The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier.
4.7.1
BIT-REVERSED ADDRESSING IMPLEMENTATION
Bit-Reversed Addressing mode is enabled when all these conditions are met:
· BWMx bits (W register selection) in the MODCON register are any value other than `1111' (the stack cannot be accessed using Bit-Reversed Addressing)
· The BREN bit is set in the XBREV register
· The addressing mode used is Register Indirect with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes, the last `N' bits of the data buffer start address must be zeros.
XBREV[14:0] is the Bit-Reversed Addressing modifier, or `pivot point', which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.
Note:
All bit-reversed EA calculations assume word-sized data (LSb of every EA is always clear). The XBREVx value is scaled accordingly to generate compatible (byte) addresses.
When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It does not function for any other addressing mode or for byte-sized data and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XBREVx) and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data are a requirement, the LSb of the EA is ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed Addressing can be enabled simultaneously using the same W register, but BitReversed Addressing operation will always take precedence for data writes when enabled.
If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV[15]) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer.
FIGURE 4-21:
BIT-REVERSED ADDRESSING EXAMPLE
Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0
Bit Locations Swapped Left-to-Right Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address
Pivot Point XBREV[14:0] = 0x0008 for a 16-Word Bit-Reversed Buffer
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TABLE 4-64:
A3
A2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
1
0
2
0
1
0
0
4
1
1
3
1
1
0
0
12
0
0
4
0
0
1
0
2
0
1
5
1
0
1
0
10
1
0
6
0
1
1
0
6
1
1
7
1
1
1
0
14
0
0
8
0
0
0
1
1
0
1
9
1
0
0
1
9
1
0
10
0
1
0
1
5
1
1
11
1
1
0
1
13
0
0
12
0
0
1
1
3
0
1
13
1
0
1
1
11
1
0
14
0
1
1
1
7
1
1
15
1
1
1
1
15
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4.8 Interfacing Program and Data Memory Spaces
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X architecture uses a 24-bit wide Program Space (PS) and a 16-bit wide Data Space (DS). The architecture is also a modified Harvard scheme, meaning that data can also be present in the Program Space. To use these data successfully, they must be accessed in a way that preserves the alignment of information in both spaces.
Aside from normal execution, the architecture of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices provides two methods by which Program Space can be accessed during operation:
· Using table instructions to access individual bytes or words anywhere in the Program Space
· Remapping a portion of the Program Space into the Data Space (Program Space Visibility)
Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word.
TABLE 4-65: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Type
Access
Program Space Address
Space
[23]
[22:16]
[15]
[14:1]
[0]
Instruction Access (Code Execution)
User
0
PC[22:1]
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
User
(Byte/Word Read/Write)
TBLPAG[7:0] 0xxx xxxx
Data EA[15:0] xxxx xxxx xxxx xxxx
Configuration
TBLPAG[7:0]
Data EA[15:0]
1xxx xxxx
xxxx xxxx xxxx xxxx
FIGURE 4-22:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter
0
23 Bits
Table Operations(2)
1/0
TBLPAG
8 Bits
EA
1/0
16 Bits
24 Bits
User/Configuration Space Select
Byte Select
Note 1: 2:
The Least Significant bit (LSb) of Program Space addresses is always fixed as `0' to maintain word alignment of data in the Program and Data Spaces.
Table operations are not required to be word-aligned. Table Read operations are permitted in the configuration memory space.
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4.8.1
DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any
address within the Program Space without going
through Data Space. The TBLRDH and TBLWTH instructions are the only method to read or write the
upper 8 bits of a Program Space word as data.
The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses
to directly map to Data Space addresses. Program
memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the
same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte.
Two table instructions are provided to move byte or word-sized (16-bit) data to and from Program Space. Both function as either byte or word operations.
· TBLRDL (Table Read Low):
- In Word mode, this instruction maps the lower word of the Program Space location (P[15:0]) to a data address (D[15:0])
- In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is `1'; the lower byte is selected when it is `0'.
· TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire upper word of a program address (P[23:16]) to a data address. The `phantom' byte (D[15:8]) is always `0'.
- In Byte mode, this instruction maps the upper or lower byte of the program word to D[7:0] of the data address in the TBLRDL instruction. The data are always `0' when the upper `phantom' byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a Program Space address. The details of their operation are explained in Section 5.0 "Flash Program Memory".
For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user application and configuration spaces. When TBLPAG[7] = 0, the table page is located in the user memory space. When TBLPAG[7] = 1, the page is located in configuration space.
FIGURE 4-23:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
TBLPAG
02
23
15
Program Space
0 0x000000
0x020000 0x030000
23
16
00000000
00000000
00000000
00000000
8
0
`Phantom' Byte
0x800000
TBLRDH.B (Wn[0] = 0) TBLRDL.B (Wn[0] = 1) TBLRDL.B (Wn[0] = 0)
TBLRDL.W
The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.
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5.0 FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Flash Programming" (www.microchip.com/DS70000609) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range.
Flash memory can be programmed in two ways:
· In-Circuit Serial ProgrammingTM (ICSPTM) programming capability
· Run-Time Self-Programming (RTSP)
ICSP allows for a dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the
alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
RTSP is accomplished using TBLRD (Table Read) and TBLWT (Table Write) instructions. With RTSP, the user application can write program memory data a single program memory word, and erase program memory in blocks or `pages' of 1024 instructions (3072 bytes) at a time.
5.1 Table Instructions and Flash Programming
Regardless of the method used, all programming of Flash memory is done with the Table Read and Table Write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits[7:0] of the TBLPAG register and the Effective Address (EA) from a W register, specified in the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to read or write to bits[15:0] of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read or write to bits[23:16] of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
Using Program Counter
0
24 Bits
Program Counter
0
Using Table Instruction
1/0 TBLPAG Reg 8 Bits
Working Reg EA 16 Bits
User/Configuration Space Select
24-Bit EA
Byte Select
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5.2 RTSP Operation
RTSP allows the user application to erase a single page of memory and to program two instruction words at a time. See the General Purpose and Motor Control Family tables (Table 1 and Table 2, respectively) for the page sizes of each device.
For more information on erasing and programming Flash memory, refer to "Flash Programming" (www.microchip.com/DS70000609) in the "dsPIC33/ PIC24 Family Reference Manual".
5.3 Programming Operations
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished.
For erase and program times, refer to Parameters D137a and D137b (Page Erase Time), and D138a and D138b (Word Write Cycle Time) in Table 30-14 in Section 30.0 "Electrical Characteristics".
Setting the WR bit (NVMCON[15]) starts the operation and the WR bit is automatically cleared when the operation is finished.
5.3.1
PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY
Programmers can program two adjacent words (24 bits x 2) of program Flash memory at a time on every other word address boundary (0x000002, 0x000006, 0x00000A, etc.). To do this, it is necessary to erase the page that contains the desired address of the location the user wants to change.
For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs.
Refer to Flash Programming" (www.microchip.com/ DS70000609) in the "dsPIC33/PIC24 Family Reference Manual" for details and codes examples on programming using RTSP.
5.4 Flash Memory Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
5.4.1 KEY RESOURCES
· "Flash Programming" (www.microchip.com/ DS70000609) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
5.5 Control Registers
Four SFRs are used to erase and write the program Flash memory: NVMCON, NVMKEY, NVMADRH and NVMADRL.
The NVMCON register (Register 5-1) enables and initiates Flash memory erase and write operations.
NVMKEY (Register 5-4) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register.
There are two NVM Address registers: NVMADRH and NVMADRL. These two registers, when concatenated, form the 24-bit Effective Address (EA) of the selected word for programming operations or the selected page for erase operations.
The NVMADRH register is used to hold the upper eight bits of the EA, while the NVMADRL register is used to hold the lower 16 bits of the EA.
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REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0(6)
R/W-0(1)
R/W-0(1)
R/W-0
U-0
U-0
U-0
WR
WREN
WRERR NVMSIDL(2)
--
--
--
bit 15
U-0 -- bit 7
U-0
U-0
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
--
--
--
NVMOP[3:0](3,4)
U-0 --
bit 8
R/W-0(1)
bit 0
Legend: R = Readable bit -n = Value at POR
SO = Settable Only bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14 bit 13
bit 12 bit 11-4 bit 3-0
WR: Write Control bit(6)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally NVMSIDL: NVM Stop in Idle Control bit(2)
1 = Flash voltage regulator goes into Standby mode during Idle mode 0 = Flash voltage regulator is active during Idle mode
Unimplemented: Read as `0' NVMOP[3:0]: NVM Operation Select bits(1,3,4)
1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 0011 = Memory page erase operation 0010 = Reserved 0001 = Memory double-word program operation(5) 0000 = Reserved
Note 1: 2:
3: 4: 5: 6:
These bits can only be reset on a POR. If this bit is set, there will be minimal power savings (IIDLE) and upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes operational. All other combinations of NVMOP[3:0] are unimplemented. Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. Two adjacent words on a 4-word boundary are programmed during execution of this operation. This bit can only be reset on a POR or a BOR.
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REGISTER 5-2:
U-0 -- bit 15
NVMADRH: NONVOLATILE MEMORY ADDRESS REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
U-0 --
bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR[23:16]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Unimplemented: Read as `0' NVMADR[23:16]: Nonvolatile Memory Write Address High bits
Selects the upper eight bits of the location to program or erase in program Flash memory. This register may be read or written by the user application.
REGISTER 5-3: NVMADRL: NONVOLATILE MEMORY ADDRESS REGISTER LOW
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
NVMADR[15:0]: Nonvolatile Memory Write Address Low bits
Selects the lower 16 bits of the location to program or erase in program Flash memory. This register may be read or written by the user application.
REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
bit 15
U-0
U-0
--
--
bit 8
W-0 bit 7
W-0
W-0
W-0
W-0
W-0
NVMKEY[7:0]
W-0
W-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Unimplemented: Read as `0' NVMKEY[7:0]: Key Register (write-only) bits
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6.0 RESETS
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Reset" (www.microchip.com/DS70602) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources:
· POR: Power-on Reset
· BOR: Brown-out Reset
· MCLR: Master Clear Pin Reset
· SWR: RESET Instruction · WDTO: Watchdog Timer Time-out Reset
· CM: Configuration Mismatch Reset
· TRAPR: Trap Conflict Reset
· IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset
A simplified block diagram of the Reset module is shown in Figure 6-1.
Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected.
Note:
Refer to the specific peripheral section or Section 4.0 "Memory Organization" of this manual for register Reset states.
All types of device Reset set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1).
A POR clears all the bits, except for the POR and BOR bits (RCON[1:0]), that are set. The user application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur.
The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual.
Note:
The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset is meaningful.
For all Resets, the default clock source is determined by the FNOSC[2:0] bits in the FOSCSEL Configuration register. The value of the FNOSC[2:0] bits is loaded into NOSC[2:0] (OSCCON[10:8]) on Reset, which in turn, initializes the system clock.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
MCLR
Glitch Filter
WDT Module Sleep or Idle
Internal VDD Regulator
BOR
VDD Rise Detect
Trap Conflict Illegal Opcode Uninitialized W Register Security Reset Configuration Mismatch
POR
SYSRST
2011-2020 Microchip Technology Inc.
DS70000657J-page 125
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
6.1 Reset Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
6.1.1 KEY RESOURCES
· "Reset" (www.microchip.com/DS70602) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
DS70000657J-page 126
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0
R/W-0
U-0
TRAPR
IOPUWR
--
bit 15
U-0
R/W-0
U-0
--
VREGSF
--
R/W-0 CM
R/W-0 VREGS
bit 8
R/W-0 EXTR bit 7
R/W-0 SWR
R/W-0 SWDTEN(2)
R/W-0 WDTO
R/W-0 SLEEP
R/W-0 IDLE
R/W-1 BOR
R/W-1 POR
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14
bit 13-12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
Unimplemented: Read as `0'
VREGSF: Flash Voltage Regulator Standby During Sleep bit
1 = Flash voltage regulator is active during Sleep 0 = Flash voltage regulator goes into Standby mode during Sleep
Unimplemented: Read as `0'
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred. 0 = A Configuration Mismatch Reset has not occurred
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred
SWR: Software RESET (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled 0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred 0 = WDT time-out has not occurred
Note 1: 2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
2011-2020 Microchip Technology Inc.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode 0 = Device was not in Idle mode
bit 1
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred
Note 1: 2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
7.0 INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Interrupts" (www.microchip.com/DS70000600) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X CPU.
The interrupt controller has the following features:
· Up to Eight Processor Exceptions and Software Traps
· Eight User-Selectable Priority Levels
· Interrupt Vector Table (IVT) with a Unique Vector for Each Interrupt or Exception Source
· Fixed Priority within a Specified User Priority Level
· Fixed Interrupt Entry and Return Latencies
7.1 Interrupt Vector Table
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X Interrupt Vector Table (IVT), shown in Figure 7-1, resides in program memory starting at location, 000004h. The IVT contains seven non-maskable trap vectors and up to 246 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with Vector 0 takes priority over interrupts at any other vector address.
7.2 Reset Sequence
A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices clear their registers in response to a Reset, which forces the PC to zero. The device then begins program execution at location, 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine.
Note:
Any unimplemented or unused vector locations in the IVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.
2011-2020 Microchip Technology Inc.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 7-1:
Decreasing Natural Order Priority IVT
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X INTERRUPT VECTOR TABLE
Reset GOTO Instruction Reset GOTO Address
Oscillator Fail Trap Vector Address Error Trap Vector Generic Hard Trap Vector
Stack Error Trap Vector Math Error Trap Vector DMAC Error Trap Vector Generic Soft Trap Vector
Reserved Interrupt Vector 0 Interrupt Vector 1
: : : Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 : : : Interrupt Vector 116 Interrupt Vector 117 Interrupt Vector 118 Interrupt Vector 119 Interrupt Vector 120 : : : Interrupt Vector 244 Interrupt Vector 245 START OF CODE
0x000000 0x000002 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 0x000012 0x000014 0x000016
: : : 0x00007C 0x00007E 0x000080 : : : 0x0000FC 0x0000FE 0x000100 0x000102 0x000104 : : : 0x0001FC 0x0001FE 0x000200
See Table 7-1 for Interrupt Vector Details
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TABLE 7-1: INTERRUPT VECTOR DETAILS
Interrupt Source
Vector IRQ
#
#
IVT Address
Interrupt Bit Location
Flag Enable
Priority
Highest Natural Order Priority
INT0 External Interrupt 0
8
0
0x000014
IFS0[0] IEC0[0] IPC0[2:0]
IC1 Input Capture 1
9
1
0x000016
IFS0[1] IEC0[1] IPC0[6:4]
OC1 Output Compare 1
10
2
0x000018
IFS0[2] IEC0[2] IPC0[10:8]
T1 Timer1
11
3
0x00001A
IFS0[3] IEC0[3] IPC0[14:12]
DMA0 DMA Channel 0
12
4
0x00001C
IFS0[4] IEC0[4] IPC1[2:0]
IC2 Input Capture 2
13
5
0x00001E
IFS0[5] IEC0[5] IPC1[6:4]
OC2 Output Compare 2
14
6
0x000020
IFS0[6] IEC0[6] IPC1[10:8]
T2 Timer2
15
7
0x000022
IFS0[7] IEC0[7] IPC1[14:12]
T3 Timer3
16
8
0x000024
IFS0[8] IEC0[8] IPC2[2:0]
SPI1E SPI1 Error
17
9
0x000026
IFS0[9] IEC0[9] IPC2[6:4]
SPI1 SPI1 Transfer Done
18
10
0x000028
IFS0[10] IEC0[10] IPC2[10:8]
U1RX UART1 Receiver
19
11
0x00002A
IFS0[11] IEC0[11] IPC2[14:12]
U1TX UART1 Transmitter
20
12
0x00002C
IFS0[12] IEC0[12] IPC3[2:0]
AD1 ADC1 Convert Done
21
13
0x00002E
IFS0[13] IEC0[13] IPC3[6:4]
DMA1 DMA Channel 1
22
14
0x000030
IFS0[14] IEC0[14] IPC3[10:8]
Reserved
23
15
0x000032
--
--
--
SI2C1 I2C1 Slave Event
24
16
0x000034
IFS1[0] IEC1[0] IPC4[2:0]
MI2C1 I2C1 Master Event
25
17
0x000036
IFS1[1] IEC1[1] IPC4[6:4]
CM Comparator Combined Event
26
18
0x000038
IFS1[2] IEC1[2] IPC4[10:8]
CN Input Change Interrupt
27
19
0x00003A
IFS1[3] IEC1[3] IPC4[14:12]
INT1 External Interrupt 1
28
20
0x00003C
IFS1[4] IEC1[4] IPC5[2:0]
Reserved
29-31 21-23 0x00003E-0x000042
--
--
--
DMA2 DMA Channel 2
32
24
0x000044
IFS1[8] IEC1[8] IPC6[2:0]
OC3 Output Compare 3
33
25
0x000046
IFS1[9] IEC1[9] IPC6[6:4]
OC4 Output Compare 4
34
26
0x000048
IFS1[10] IEC1[10] IPC6[10:8]
T4 Timer4
35
27
0x00004A
IFS1[11] IEC1[11] IPC6[14:12]
T5 Timer5
36
28
0x00004C
IFS1[12] IEC1[12] IPC7[2:0]
INT2 External Interrupt 2
37
29
0x00004E
IFS1[13] IEC1[13] IPC7[6:4]
U2RX UART2 Receiver
38
30
0x000050
IFS1[14] IEC1[14] IPC7[10:8]
U2TX UART2 Transmitter
39
31
0x000052
IFS1[15] IEC1[15] IPC7[14:12]
SPI2E SPI2 Error
40
32
0x000054
IFS2[0] IEC2[0] IPC8[2:0]
SPI2 SPI2 Transfer Done C1RX CAN1 RX Data Ready(1) C1 CAN1 Event(1)
41
33
42
34
43
35
0x000056 0x000058 0x00005A
IFS2[1] IFS2[2] IFS2[3]
IEC2[1] IEC2[2] IEC2[3]
IPC8[6:4] IPC8[10:8] IPC8[14:12]
DMA3 DMA Channel 3
44
36
0x00005C
IFS2[4] IEC2[4] IPC9[2:0]
IC3 Input Capture 3
45
37
0x00005E
IFS2[5] IEC2[5] IPC9[6:4]
IC4 Input Capture 4
46
38
0x000060
IFS2[6] IEC2[6] IPC9[10:8]
Reserved
47-56 39-48 0x000062-0x000074
--
--
--
SI2C2 I2C2 Slave Event
57
49
0x000076
IFS3[1] IEC3[1] IPC12[6:4]
MI2C2 I2C2 Master Event
58
50
0x000078
IFS3[2] IEC3[2] IPC12[10:8]
Reserved
59-64 51-56 0x00007A-0x000084
--
--
--
PWMSpEventMatch PWM Special Event Match(2)
65
57
0x000086
IFS3[9] IEC3[9] IPC14[6:4]
Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. 2: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Source
Vector IRQ
#
#
IVT Address
Interrupt Bit Location
Flag Enable
Priority
QEI1 QEI1 Position Counter Compare(2) 66
58
0x000088
IFS3[10] IEC3[10] IPC14[10:8]
Reserved
67-72 59-64 0x00008A-0x000094
--
--
--
U1E UART1 Error Interrupt
73
65
0x000096
IFS4[1] IEC4[1] IPC16[6:4]
U2E UART2 Error Interrupt
74
66
0x000098
IFS4[2] IEC4[2] IPC16[10:8]
CRC CRC Generator Interrupt
75
67
0x00009A
IFS4[3] IEC4[3] IPC16[14:12]
Reserved C1TX CAN1 TX Data Request(1)
76-77 78
68-69 0x00009C-0x00009E
--
70
0x000A0
IFS4[6]
-- IEC4[6]
-- IPC17[10:8]
Reserved
79-84 71-76 0x0000A2-0x0000AC --
--
--
CTMU CTMU Interrupt
85
77
0x0000AE
IFS4[13] IEC4[13] IPC19[6:4]
Reserved PWM1 PWM Generator 1(2) PWM2 PWM Generator 2(2) PWM3 PWM Generator 3(2)
86-101 102 103 104
78-93 94 95 96
0x0000B0-0x0000CE 0x0000D0 0x0000D2 0x0000D4
-- IFS5[14] IFS5[15] IFS6[0]
-- IEC5[14] IEC5[15] IEC6[0]
-- IPC23[10:8] IPC23[14:12] IPC24[2:0]
Reserved
105-149 97-141 0x0001D6-0x00012E
--
--
--
ICD ICD Application
150
142
0x000142
IFS8[14] IEC8[14] IPC35[10:8]
JTAG JTAG Programming
151
143
0x000130
IFS8[15] IEC8[15] IPC35[14:12]
Reserved
152
144
0x000134
--
--
--
PTGSTEP PTG Step
153
145
0x000136
IFS9[1] IEC9[1] IPC36[6:4]
PTGWDT PTG Watchdog Time-out
154
146
0x000138
IFS9[2] IEC9[2] IPC36[10:8]
PTG0 PTG Interrupt 0
155
147
0x00013A
IFS9[3] IEC9[3] IPC36[14:12]
PTG1 PTG Interrupt 1
156
148
0x00013C
IFS9[4] IEC9[4] IPC37[2:0]
PTG2 PTG Interrupt 2
157
149
0x00013E
IFS9[5] IEC9[5] IPC37[6:4]
PTG3 PTG Interrupt 3
158
150
0x000140
IFS9[6] IEC9[6] IPC37[10:8]
Reserved
159-245 151-245 0x000142-0x0001FE
--
--
--
Lowest Natural Order Priority
Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. 2: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
DS70000657J-page 132
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
7.3 Interrupt Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
7.3.1 KEY RESOURCES
· "Interrupts" (www.microchip.com/DS70000600) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
7.4 Interrupt Control and Status Registers
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices implement the following registers for the interrupt controller:
· INTCON1 · INTCON2 · INTCON3 · INTCON4 · INTTREG
7.4.1 INTCON1 THROUGH INTCON4
Global interrupt control functions are controlled from INTCON1, INTCON2, INTCON3 and INTCON4.
INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources.
The INTCON2 register controls external interrupt request signal behavior and also contains the Global Interrupt Enable (GIE) bit.
INTCON3 contains the status flags for the DMA and DO stack overflow status trap sources.
The INTCON4 register contains the Software-Generated Hard Trap (SGHT) status bit.
7.4.2 IFSx
The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software.
7.4.3 IECx
The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.
7.4.4 IPCx
The IPCx registers are used to set the Interrupt Priority Level (IPL) for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.
7.4.5 INTTREG
The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt Priority Level, which are latched into the Vector Number bits (VECNUM[7:0]) and Interrupt Priority Level bits (ILR[3:0]) fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence as they are listed in Table 7-1. For example, the INT0 (External Interrupt 0) is shown as having Vector Number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0[0], the INT0IE bit in IEC0[0] and the INT0IP bits in the first position of IPC0 (IPC0[2:0]).
7.4.6 STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. For more information on these registers refer to "CPU" (www.microchip.com/DS70359) in the "dsPIC33/PIC24 Family Reference Manual".
· The CPU STATUS Register, SR, contains the IPL[2:0] bits (SR[7:5]). These bits indicate the current CPU Interrupt Priority Level. The user software can change the current CPU Interrupt Priority Level by writing to the IPLx bits.
· The CORCON register contains the IPL3 bit which, together with IPL[2:0], also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software.
All Interrupt registers are described in Register 7-3 through Register 7-7 in the following pages.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 7-1: SR: CPU STATUS REGISTER(1)
R/W-0 OA
bit 15
R/W-0 OB
R/W-0 SA
R/W-0 SB
R/C-0 OAB
R/W-0(3)
R/W-0(3)
R/W-0(3)
R-0
IPL[2:0](2)
RA
bit 7
R/W-0 N
R/C-0 SAB
R/W-0 OV
R-0 DA
R/W-0 Z
R/W-0 DC bit 8
R/W-0 C bit 0
Legend: R = Readable bit -n = Value at POR
C = Clearable bit W = Writable bit `1'= Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 7-5
IPL[2:0]: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)
Note 1: 2:
3:
For complete register details, see Register 3-1.
The IPL[2:0] bits are concatenated with the IPL[3] bit (CORCON[3]) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL[3] = 1. User interrupts are disabled when IPL[3] = 1.
The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.
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REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
R/W-0 VAR bit 15
U-0
R/W-0
R/W-0
R/W-0
R-0
--
US1
US0
EDT
DL2
R-0
R-0
DL1
DL0
bit 8
R/W-0
R/W-0
R/W-1
R/W-0
R/C-0
R-0
SATA
SATB
SATDW
ACCSAT
IPL3(2)
SFA
bit 7
R/W-0 RND
R/W-0 IF bit 0
Legend: R = Readable bit -n = Value at POR
C = Clearable bit W = Writable bit `1'= Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 3
VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing is enabled 0 = Fixed exception processing is enabled IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2. 2: The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.
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REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 NSTDIS bit 15
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR(1) OVBERR(1) COVAERR(1) COVBERR(1)
R/W-0 OVATE(1)
R/W-0 OVBTE(1)
R/W-0 COVTE(1)
bit 8
R/W-0 SFTACERR(1)
bit 7
R/W-0 DIV0ERR
R/W-0 DMACERR
R/W-0 MATHERR
R/W-0 ADDRERR
R/W-0 STKERR
R/W-0 OSCFAIL
U-0 --
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled OVAERR: Accumulator A Overflow Trap Flag bit(1)
1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A OVBERR: Accumulator B Overflow Trap Flag bit(1)
1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit(1)
1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit(1)
1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B OVATE: Accumulator A Overflow Trap Enable bit(1)
1 = Trap overflow of Accumulator A 0 = Trap is disabled OVBTE: Accumulator B Overflow Trap Enable bit(1)
1 = Trap overflow of Accumulator B 0 = Trap is disabled COVTE: Catastrophic Overflow Trap Enable bit(1)
1 = Trap on catastrophic overflow of Accumulator A or B is enabled 0 = Trap is disabled SFTACERR: Shift Accumulator Error Status bit(1)
1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift
DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero
DMACERR: DMAC Trap Flag bit
1 = DMAC trap has occurred 0 = DMAC trap has not occurred
Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
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REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 4
MATHERR: Math Error Status bit
1 = Math error trap has occurred 0 = Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred 0 = Address error trap has not occurred
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred 0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as `0'
Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
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REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
GIE
DISI
SWTRAP
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
--
INT2EP
INT1EP
INT0EP
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-3 bit 2 bit 1 bit 0
GIE: Global Interrupt Enable bit
1 = Interrupts and associated IE bits are enabled 0 = Interrupts are disabled, but traps are still enabled
DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active
SWTRAP: Software Trap Status bit
1 = Software trap is enabled 0 = Software trap is disabled
Unimplemented: Read as `0'
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge 0 = Interrupt on positive edge
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge 0 = Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge 0 = Interrupt on positive edge
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REGISTER 7-5: INTCON3: INTERRUPT CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
--
--
DAE
DOOVR
--
--
--
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-6 bit 5
bit 4
bit 3-0
Unimplemented: Read as `0'
DAE: DMA Address Error Soft Trap Status bit
1 = DMA address error soft trap has occurred 0 = DMA address error soft trap has not occurred
DOOVR: DO Stack Overflow Soft Trap Status bit 1 = DO stack overflow soft trap has occurred 0 = DO stack overflow soft trap has not occurred
Unimplemented: Read as `0'
REGISTER 7-6: INTCON4: INTERRUPT CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
--
--
--
--
--
--
--
SGHT
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-1 bit 0
Unimplemented: Read as `0'
SGHT: Software-Generated Hard Trap Status bit
1 = Software-generated hard trap has occurred 0 = Software-generated hard trap has not occurred
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REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 -- bit 15
U-0
U-0
U-0
R-0
R-0
R-0
--
--
--
ILR[3:0]
R-0 bit 8
R-0 bit 7
R-0
R-0
R-0
R-0
R-0
VECNUM[7:0]
R-0
R-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12 bit 11-8
bit 7-0
Unimplemented: Read as `0'
ILR[3:0]: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15] · · · 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0
VECNUM[7:0]: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use · · · 00001001 = 9, IC1 Input Capture 1 00001000 = 8, INT0 External Interrupt 0 00000111 = 7, Reserved; do not use 00000110 = 6, Generic soft error trap 00000101 = 5, DMAC error trap 00000100 = 4, Math error trap 00000011 = 3, Stack error trap 00000010 = 2, Generic hard trap 00000001 = 1, Address error trap 00000000 = 0, Oscillator fail trap
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8.0 DIRECT MEMORY ACCESS (DMA)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Direct Memory Access (DMA)" (www.microchip.com/DS70348) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The DMA Controller transfers data between Peripheral Data registers and Data Space SRAM.
In addition, DMA can access the entire data memory space. The Data Memory Bus Arbiter is utilized when either the CPU or DMA attempts to access SRAM, resulting in potential DMA or CPU stalls.
The DMA Controller supports four independent channels. Each channel can be configured for transfers to or from selected peripherals. Some of the peripherals supported by the DMA Controller include:
· ECANTM · Analog-to-Digital Converter (ADC) · Serial Peripheral Interface (SPI) · UART · Input Capture · Output Compare
Refer to Table 8-1 for a complete list of supported peripherals.
FIGURE 8-1:
DMA CONTROLLER MODULE
PERIPHERAL
DMA
Data Memory Arbiter
(see Figure 4-18)
SRAM
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In addition, DMA transfers can be triggered by timers as well as external interrupts. Each DMA channel is unidirectional. Two DMA channels must be allocated to read and write to a peripheral. If more than one channel receives a request to transfer data, a simple fixed priority scheme based on channel number, dictates which channel completes the transfer and which channel, or channels, are left pending. Each DMA channel moves a block of data, after which, it generates an interrupt to the CPU to indicate that the block is available for processing.
The DMA Controller provides these functional capabilities:
· Four DMA channels
· Register Indirect with Post-Increment Addressing mode
· Register Indirect without Post-Increment Addressing mode
· Peripheral Indirect Addressing mode (peripheral generates destination address)
· CPU interrupt after half or full block transfer complete
· Byte or word transfers
· Fixed priority channel arbitration
· Manual (software) or automatic (peripheral DMA requests) transfer initiation
· One-Shot or Auto-Repeat Block Transfer modes
· Ping-Pong mode (automatic switch between two SRAM start addresses after each block transfer is complete)
· DMA request for each channel can be selected from any supported interrupt source
· Debug support features
The peripherals that can utilize DMA are listed in Table 8-1.
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
Peripheral to DMA Association
DMAxREQ Register IRQSEL[7:0] Bits
DMAxPAD Register (Values to Read from
Peripheral)
INT0 External Interrupt 0 IC1 Input Capture 1 IC2 Input Capture 2 IC3 Input Capture 3 IC4 Input Capture 4 OC1 Output Compare 1
00000000 00000001 00000101 00100101 00100110 00000010
-- 0x0144 (IC1BUF) 0x014C (IC2BUF) 0x0154 (IC3BUF) 0x015C (IC4BUF)
--
OC2 Output Compare 2
00000110
--
OC3 Output Compare 3
00011001
--
OC4 Output Compare 4
00011010
--
TMR2 Timer2 TMR3 Timer3 TMR4 Timer4 TMR5 Timer5 SPI1 Transfer Done SPI2 Transfer Done UART1RX UART1 Receiver UART1TX UART1 Transmitter UART2RX UART2 Receiver UART2TX UART2 Transmitter ECAN1 RX Data Ready ECAN1 TX Data Request ADC1 ADC1 Convert Done
00000111 00001000 00011011 00011100 00001010 00100001 00001011 00001100 00011110 00011111 00100010 01000110 00001101
-- -- -- -- 0x0248 (SPI1BUF) 0x0268 (SPI2BUF) 0x0226 (U1RXREG) -- 0x0236 (U2RXREG) -- 0x0440 (C1RXD) -- 0x0300 (ADC1BUF0)
DMAxPAD Register (Values to Write to
Peripheral)
-- -- -- -- -- 0x0906 (OC1R) 0x0904 (OC1RS) 0x0910 (OC2R) 0x090E (OC2RS) 0x091A (OC3R) 0x0918 (OC3RS) 0x0924 (OC4R) 0x0922 (OC4RS) -- -- -- -- 0x0248 (SPI1BUF) 0x0268 (SPI2BUF) -- 0x0224 (U1TXREG) -- 0x0234 (U2TXREG) -- 0x0442 (C1TXD) --
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FIGURE 8-2:
DMA CONTROLLER BLOCK DIAGRAM
SRAM Arbiter
Peripheral Indirect Address
DMA Control
DMA Controller
DMA Channels 01 2 3
DMA Ready Peripheral 1
CPU DMA
DMA X-Bus CPU Peripheral X-Bus
IRQ to DMA and Interrupt
Controller Modules
CPU
Non-DMA Peripheral
CPU DMA
DMA Ready Peripheral 2
CPU DMA
DMA Ready Peripheral 3
IRQ to DMA and Interrupt Controller
Modules
IRQ to DMA and Interrupt Controller
Modules
Note: CPU and DMA address buses are not shown for clarity.
8.1 DMA Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
8.1.1 KEY RESOURCES
· "Direct Memory Access (DMA)" (www.microchip.com/DS70348) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
8.2 DMAC Registers
Each DMAC Channel x (where x = 0 through 3) contains the following registers:
· 16-Bit DMA Channel Control register (DMAxCON)
· 16-Bit DMA Channel IRQ Select register (DMAxREQ)
· 32-Bit DMA RAM Primary Start Address register (DMAxSTA)
· 32-Bit DMA RAM Secondary Start Address register (DMAxSTB)
· 16-Bit DMA Peripheral Address register (DMAxPAD)
· 14-Bit DMA Transfer Count register (DMAxCNT)
Additional status registers (DMAPWC, DMARQC, DMAPPS, DMALCA and DSADR) are common to all DMAC channels. These status registers provide information on write and request collisions, as well as on last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx register in the interrupt controller. The corresponding interrupt enable control bits (DMAxIE) are located in an IECx register in the interrupt controller, and the corresponding interrupt priority control bits (DMAxIP) are located in an IPCx register in the interrupt controller.
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REGISTER 8-1: DMAXCON: DMA CHANNEL X CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CHEN
SIZE
DIR
HALF
NULLW
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
U-0
--
AMODE1 AMODE0
--
U-0
R/W-0
R/W-0
--
MODE1
MODE0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-6 bit 5-4
bit 3-2 bit 1-0
CHEN: DMA Channel Enable bit
1 = Channel is enabled 0 = Channel is disabled
SIZE: DMA Data Transfer Size bit
1 = Byte 0 = Word
DIR: DMA Transfer Direction bit (source/destination bus select)
1 = Reads from RAM address, writes to peripheral address 0 = Reads from peripheral address, writes to RAM address
HALF: DMA Block Transfer Interrupt Select bit
1 = Initiates interrupt when half of the data have been moved 0 = Initiates interrupt when all of the data have been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear) 0 = Normal operation
Unimplemented: Read as `0'
AMODE[1:0]: DMA Channel Addressing Mode Select bits
11 = Reserved 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode
Unimplemented: Read as `0'
MODE[1:0]: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer) 10 = Continuous, Ping-Pong modes are enabled 01 = One-Shot, Ping-Pong modes are disabled 00 = Continuous, Ping-Pong modes are disabled
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REGISTER 8-2: DMAXREQ: DMA CHANNEL X IRQ SELECT REGISTER
R/S-0
U-0
U-0
U-0
U-0
U-0
U-0
FORCE(1)
--
--
--
--
--
--
bit 15
U-0 --
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
IRQSEL[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
S = Settable bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14-8 bit 7-0
FORCE: Force DMA Transfer bit(1)
1 = Forces a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request
Unimplemented: Read as `0'
IRQSEL[7:0]: DMA Peripheral IRQ Number Select bits
01000110 = ECAN1 TX Data Request(2) 00100110 = IC4 Input Capture 4 00100101 = IC3 Input Capture 3 00100010 = ECAN1 RX Data Ready(2) 00100001 = SPI2 Transfer Done 00011111 = UART2TX UART2 Transmitter 00011110 = UART2RX UART2 Receiver 00011100 = TMR5 Timer5 00011011 = TMR4 Timer4 00011010 = OC4 Output Compare 4 00011001 = OC3 Output Compare 3 00001101 = ADC1 ADC1 Convert done 00001100 = UART1TX UART1 Transmitter 00001011 = UART1RX UART1 Receiver 00001010 = SPI1 Transfer Done 00001000 = TMR3 Timer3 00000111 = TMR2 Timer2 00000110 = OC2 Output Compare 2 00000101 = IC2 Input Capture 2 00000010 = OC1 Output Compare 1 00000001 = IC1 Input Capture 1 00000000 = INT0 External Interrupt 0
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the forced DMA transfer is complete or the channel is disabled (CHEN = 0).
2: This selection is available in dsPIC33EPXXXGP/MC50X devices only.
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REGISTER 8-3:
U-0 -- bit 15
DMAXSTAH: DMA CHANNEL X START ADDRESS REGISTER A (HIGH)
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
U-0 --
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STA[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Unimplemented: Read as `0' STA[23:16]: Primary Start Address bits (source or destination)
REGISTER 8-4: DMAXSTAL: DMA CHANNEL X START ADDRESS REGISTER A (LOW)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
STA[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STA[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
STA[15:0]: Primary Start Address bits (source or destination)
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REGISTER 8-5:
U-0 -- bit 15
DMAXSTBH: DMA CHANNEL X START ADDRESS REGISTER B (HIGH)
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
U-0 --
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STB[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Unimplemented: Read as `0' STB[23:16]: Secondary Start Address bits (source or destination)
REGISTER 8-6: DMAXSTBL: DMA CHANNEL X START ADDRESS REGISTER B (LOW)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
STB[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STB[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
STB[15:0]: Secondary Start Address bits (source or destination)
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REGISTER 8-7: DMAXPAD: DMA CHANNEL X PERIPHERAL ADDRESS REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PAD[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PAD[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PAD[15:0]: Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided.
REGISTER 8-8:
U-0 -- bit 15
DMAXCNT: DMA CHANNEL X TRANSFER COUNT REGISTER(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
CNT[13:8](2)
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
CNT[7:0](2)
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-0
Unimplemented: Read as `0' CNT[13:0]: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided.
2: The number of DMA transfers = CNT[13:0] + 1.
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REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
R-0 bit 7
R-0
R-0
R-0
R-0
R-0
DSADR[23:16]
R-0
R-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Unimplemented: Read as `0' DSADR[23:16]: Most Recent DMA Address Accessed by DMA bits
REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR[15:8]
bit 15
R-0 bit 8
R-0 bit 7
R-0
R-0
R-0
R-0
R-0
DSADR[7:0]
R-0
R-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
DSADR[15:0]: Most Recent DMA Address Accessed by DMA bits
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REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
U-0
U-0
U-0
R-0
R-0
R-0
R-0
--
--
--
PWCOL3 PWCOL2 PWCOL1 PWCOL0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0'
PWCOL3: DMA Channel 3 Peripheral Write Collision Flag bit
1 = Write collision is detected 0 = No write collision is detected
PWCOL2: DMA Channel 2 Peripheral Write Collision Flag bit
1 = Write collision is detected 0 = No write collision is detected
PWCOL1: DMA Channel 1 Peripheral Write Collision Flag bit
1 = Write collision is detected 0 = No write collision is detected
PWCOL0: DMA Channel 0 Peripheral Write Collision Flag bit
1 = Write collision is detected 0 = No write collision is detected
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REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
U-0
U-0
U-0
R-0
R-0
R-0
R-0
--
--
--
RQCOL3
RQCOL2
RQCOL1 RQCOL0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0'
RQCOL3: DMA Channel 3 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision is detected 0 = No request collision is detected
RQCOL2: DMA Channel 2 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision is detected 0 = No request collision is detected
RQCOL1: DMA Channel 1 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision is detected 0 = No request collision is detected
RQCOL0: DMA Channel 0 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision is detected 0 = No request collision is detected
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REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
U-0
U-0
U-0
R-1
R-1
R-1
R-1
--
--
--
LSTCH[3:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-4 bit 3-0
Unimplemented: Read as `0'
LSTCH[3:0]: Last DMAC Channel Active Status bits
1111 = No DMA transfer has occurred since system Reset 1110 = Reserved · · · 0100 = Reserved 0011 = Last data transfer was handled by Channel 3 0010 = Last data transfer was handled by Channel 2 0001 = Last data transfer was handled by Channel 1 0000 = Last data transfer was handled by Channel 0
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REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 8
U-0 -- bit 7
U-0
U-0
U-0
R-0
R-0
R-0
R-0
--
--
--
PPST3
PPST2
PPST1
PPST0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0'
PPST3: DMA Channel 3 Ping-Pong Mode Status Flag bit
1 = DMASTB3 register is selected 0 = DMASTA3 register is selected
PPST2: DMA Channel 2 Ping-Pong Mode Status Flag bit
1 = DMASTB2 register is selected 0 = DMASTA2 register is selected
PPST1: DMA Channel 1 Ping-Pong Mode Status Flag bit
1 = DMASTB1 register is selected 0 = DMASTA1 register is selected
PPST0: DMA Channel 0 Ping-Pong Mode Status Flag bit
1 = DMASTB0 register is selected 0 = DMASTA0 register is selected
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NOTES:
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9.0 OSCILLATOR CONFIGURATION
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Oscillator" (www.microchip.com/DS70580) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X oscillator system provides:
· On-Chip Phase-Locked Loop (PLL) to Boost Internal Operating Frequency on Select Internal and External Oscillator Sources
· On-the-Fly Clock Switching between Various Clock Sources
· Doze mode for System Power Savings · Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application Recovery or Shutdown · Configuration Bits for Clock Source Selection
A simplified diagram of the oscillator system is shown in Figure 9-1.
FIGURE 9-1:
OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator OSC1
POSCCLK
OSC2
S3 S1 POSCMD[1:0]
PLL(1)
XT, HS, EC S2
XTPLL, HSPLL, ECPLL, FRCPLL, FPLLO S1/S3
DOZE[2:0]
FRC
FRCCLK
Oscillator
÷ 2 FRCDIVN
S7
FCY(2) FP(2) FOSC
FRCDIV DOZE
TUN[5:0]
LPRC Oscillator
FRCDIV[2:0]
FRC S0 LPRC S5
Reference Clock Generation
POSCCLK FOSC
REFCLKO ÷ N
RPn
ROSEL RODIV[3:0]
COSC[2:0]
Clock Fail Clock Switch
Reset
0b000
NOSC[2:0]
FNOSC[2:0]
WDT, PWRT, FSCM
Note 1: 2:
See Figure 9-2 for PLL details.
The term, FP, refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used with a doze ratio of 1:2 or lower.
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9.1 CPU Clocking System
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X family of devices provides six system clock options:
· Fast RC (FRC) Oscillator · FRC Oscillator with Phase-Locked Loop (PLL) · FRC Oscillator with Postscaler · Primary (XT, HS or EC) Oscillator · Primary Oscillator with PLL · Low-Power RC (LPRC) Oscillator
FIGURE 9-2:
PLL BLOCK DIAGRAM
Instruction execution speed or device operating frequency, FCY, is given by Equation 9-1.
EQUATION 9-1: DEVICE OPERATING FREQUENCY
FCY = FOSC/2
Figure 9-2 is a block diagram of the PLL module. Equation 9-2 provides the relationship between input frequency (FIN) and output frequency (FPLLO). In clock modes S1 and S3, when the PLL output is selected, FOSC = FPLLO. Equation 9-3 provides the relationship between input frequency (FIN) and VCO frequency (FVCO).
0.8 MHz < FPLLI(1) < 8.0 MHz
120 MHZ < FVCO(1) < 340 MHZ
FPLLO(1) 120 MHz @ +125ºC FPLLO(1) 140 MHz @ +85ºC
FIN
÷ N1
FPLLI
PFD
PLLPRE[4:0]
VCO
FVCO
÷ N2
FPLLO To FOSC Clock Multiplexer
PLLPOST[1:0] ÷ M
PLLDIV[8:0] Note 1: This frequency range must be met at all times.
EQUATION 9-2: FPLLO CALCULATION
FPLLO
=
F
IN
N-----1----M-----N-----2-
=
FI
N
---P----L----L---P----R----E------+-P---2-L----L---D----2-I--V---P--+--L---2-L---P----O-----S---T-----+-----1----
Where: N1 = PLLPRE + 2 N2 = 2 x (PLLPOST + 1) M = PLLDIV + 2
EQUATION 9-3:
FVCO CALCULATION
Fvco
=
F
IN
N--M---1-
=
F
I
N
---PP----LL----LL---P-D---R--I--VE-----+-+----2-2---
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TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source POSCMD[1:0]
Fast RC Oscillator with Divide-by-N (FRCDIVN)
Internal
xx
Low-Power RC Oscillator (LPRC)
Internal
xx
Primary Oscillator (HS) with PLL (HSPLL)
Primary
10
Primary Oscillator (XT) with PLL (XTPLL)
Primary
01
Primary Oscillator (EC) with PLL (ECPLL)
Primary
00
Primary Oscillator (HS)
Primary
10
Primary Oscillator (XT)
Primary
01
Primary Oscillator (EC)
Primary
00
Fast RC Oscillator (FRC) with Divide-by-N and
Internal
xx
PLL (FRCPLL)
Fast RC Oscillator (FRC)
Internal
xx
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
FNOSC[2:0]
See Notes
111
1, 2
101
1
011
011
011
1
010
010
010
1
001
1
000
1
9.2 Oscillator Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
9.2.1 KEY RESOURCES
· "Oscillator" (www.microchip.com/DS70580) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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9.3 Oscillator Control Registers
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0 -- bit 15
R-0
R-0
R-0
U-0
R/W-y
COSC2
COSC1
COSC0
--
NOSC2(2)
R/W-y NOSC1(2)
R/W-y NOSC0(2)
bit 8
R/W-0
R/W-0
R-0
U-0
R/W-0
U-0
CLKLOCK
IOLOCK
LOCK
--
CF(3)
--
bit 7
U-0
R/W-0
--
OSWEN
bit 0
Legend: R = Readable bit -n = Value at POR
y = Value set from Configuration bits on POR
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-12
bit 11 bit 10-8
bit 7 bit 6 bit 5
Unimplemented: Read as `0'
COSC[2:0]: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL) 000 = Fast RC Oscillator (FRC)
Unimplemented: Read as `0' NOSC[2:0]: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL) 000 = Fast RC Oscillator (FRC)
CLKLOCK: Clock Lock Enable bit
1 = If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and PLL configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
IOLOCK: I/O Lock Enable bit
1 = I/O lock is active 0 = I/O lock is not active
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: 2:
3:
Writes to this register require an unlock sequence. Refer to "Oscillator" (www.microchip.com/DS70580) in the "dsPIC33/PIC24 Family Reference Manual" (available from the Microchip website) for details.
Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes.
This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and trigger an oscillator failure trap.
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REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 4 bit 3
bit 2-1 bit 0
Unimplemented: Read as `0' CF: Clock Fail Detect bit(3)
1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure
Unimplemented: Read as `0'
OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to selection specified by the NOSC[2:0] bits 0 = Oscillator switch is complete
Note 1: 2:
3:
Writes to this register require an unlock sequence. Refer to "Oscillator" (www.microchip.com/DS70580) in the "dsPIC33/PIC24 Family Reference Manual" (available from the Microchip website) for details.
Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes.
This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and trigger an oscillator failure trap.
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REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER
R/W-0 ROI
bit 15
R/W-0 DOZE2(1)
R/W-1 DOZE1(1)
R/W-1
R/W-0
DOZE0(1) DOZEN(2,3)
R/W-0 FRCDIV2
R/W-0 FRCDIV1
R/W-0 FRCDIV0
bit 8
R/W-0
R/W-1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST1 PLLPOST0
--
PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-12
bit 11 bit 10-8
bit 7-6 bit 5
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit 0 = Interrupts have no effect on the DOZEN bit DOZE[2:0]: Processor Clock Reduction Select bits(1)
111 = FCY divided by 128 110 = FCY divided by 64 101 = FCY divided by 32 100 = FCY divided by 16 011 = FCY divided by 8 (default) 010 = FCY divided by 4 001 = FCY divided by 2 000 = FCY divided by 1 DOZEN: Doze Mode Enable bit(2,3)
1 = DOZE[2:0] field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock and peripheral clock ratio is forced to 1:1
FRCDIV[2:0]: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 000 = FRC divided by 1 (default)
PLLPOST[1:0]: PLL VCO Output Divider Select bits (also denoted as `N2', PLL postscaler)
11 = Output divided by 8 10 = Reserved 01 = Output divided by 4 (default) 00 = Output divided by 2
Unimplemented: Read as `0'
Note 1:
2: 3:
The DOZE[2:0] bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to DOZE[2:0] are ignored.
This bit is cleared when the ROI bit is set and an interrupt occurs.
The DOZEN bit cannot be set if DOZE[2:0] = 000. If DOZE[2:0] = 000, any attempt by user software to set the DOZEN bit is ignored.
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REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
bit 4-0
PLLPRE[4:0]: PLL Phase Detector Input Divider Select bits (also denoted as `N1', PLL prescaler)
11111 = Input divided by 33 · · · 00001 = Input divided by 3 00000 = Input divided by 2 (default)
Note 1:
2: 3:
The DOZE[2:0] bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to DOZE[2:0] are ignored.
This bit is cleared when the ROI bit is set and an interrupt occurs.
The DOZEN bit cannot be set if DOZE[2:0] = 000. If DOZE[2:0] = 000, any attempt by user software to set the DOZEN bit is ignored.
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REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
R/W-0
--
PLLDIV8
bit 8
R/W-0 bit 7
R/W-0
R/W-1
R/W-1
R/W-0
PLLDIV[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-9 bit 8-0
Unimplemented: Read as `0'
PLLDIV[8:0]: PLL Feedback Divisor bits (also denoted as `M', PLL multiplier)
111111111 = 513 · · · 000110000 = 50 (default) · · · 000000010 = 4 000000001 = 3 000000000 = 2
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REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
TUN[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-6 bit 5-0
Unimplemented: Read as `0'
TUN[5:0]: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation of 1.453% (7.477 MHz) 011110 = Center frequency + 1.406% (7.474 MHz) · · · 000001 = Center frequency + 0.047% (7.373 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency 0.047% (7.367 MHz) · · · 100001 = Center frequency 1.453% (7.263 MHz) 100000 = Minimum frequency deviation of -1.5% (7.259 MHz)
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REGISTER 9-5: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 ROON bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
ROSSLP
ROSEL RODIV3(1) RODIV2(1) RODIV1(1)
R/W-0 RODIV0(1)
bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11-8
bit 7-0
ROON: Reference Oscillator Output Enable bit 1 = Reference Oscillator output is enabled on the REFCLK pin(2) 0 = Reference Oscillator output is disabled
Unimplemented: Read as `0'
ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference Oscillator output continues to run in Sleep 0 = Reference Oscillator output is disabled in Sleep
ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock 0 = System clock is used as the reference clock RODIV[3:0]: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock
Unimplemented: Read as `0'
Note 1: The Reference Oscillator output must be disabled (ROON = 0) before writing to these bits. 2: This pin is remappable. See Section 11.4 "Peripheral Pin Select (PPS)" for more information.
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10.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Watchdog Timer and Power-Saving Modes" (www.microchip.com/DS70615) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of peripherals being clocked constitutes lower consumed power.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices can manage power consumption in four ways:
· Clock Frequency
· Instruction-Based Sleep and Idle modes
· Software-Controlled Doze mode
· Selective Peripheral Control in Software
Combinations of these methods can be used to selectively tailor an application's power consumption while still maintaining critical application features, such as timing-sensitive communications.
10.1 Clock Frequency and Clock Switching
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSCx bits (OSCCON[10:8]). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 9.0 "Oscillator Configuration".
10.2 Instruction-Based Power-Saving Modes
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices have two special power-saving modes that are entered
through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV instruction is shown in Example 10-1.
Note:
SLEEP_MODE and IDLE_MODE are constants defined in the assembler include
file for the selected device.
Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up".
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX
PWRSAV #IDLE_MODE PWRSAV #SLEEP_MODE
; Put the device into Idle mode ; Put the device into Sleep mode(1)
Note 1: The use of PWRSV #SLEEP_MODE has limitations when the Flash Voltage Regulator bit, VREGSF (RCON[11]), is set to Standby mode. Refer to Section 10.2.1 "Sleep Mode" for more information.
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10.2.1 SLEEP MODE
The following occurs in Sleep mode:
· The system clock source is shut down. If an on-chip oscillator is used, it is turned off.
· The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current.
· The Fail-Safe Clock Monitor does not operate, since the system clock source is disabled.
· The LPRC clock continues to run in Sleep mode if the WDT is enabled.
· The WDT, if enabled, is automatically cleared prior to entering Sleep mode.
· Some device features or peripherals can continue to operate. This includes items such as the Input Change Notification (ICN) on the I/O ports or peripherals that use an external clock input.
· Any peripheral that requires the system clock source for its operation is disabled.
The device wakes up from Sleep mode on any of these events:
· Any interrupt source that is individually enabled · Any form of device Reset · A WDT time-out
On wake-up from Sleep mode, the processor restarts with the same clock source that was active when Sleep mode was entered.
For optimal power savings, the internal regulator and the Flash regulator can be configured to go into standby when Sleep mode is entered by clearing the VREGS (RCON[8]) and VREGSF (RCON[11]) bits (default configuration). However, putting the Flash voltage regulator in Standby mode (VREGSF = 0) when in Sleep has the effect of corrupting the prefetched instructions placed in the instruction queue. When the part wakes up, these instructions may cause undefined behavior. To remove this problem, the instruction queue must be flushed after the part wakes up. A way to flush the instruction queue is to perform a branch. Therefore, it is required to implement the SLEEP instruction in a function with 4-instruction word alignment. The 4-instruction word alignment will assure that the SLEEP instruction is always placed on the correct address to make sure the flushing will be effective. Example 10-2 shows how this is performed.
EXAMPLE 10-2: SLEEP MODE PWRSAV INSTRUCTION SYNTAX (WITH FLASH VOLTAGE REGULATOR SET TO STANDBY MODE)
.global .section .align
_GoToSleep .text 4
_GoToSleep:
PWRSAV
#SLEEP_MODE
BRA
TO_FLUSH_QUEUE_LABEL
TO_FLUSH_QUEUE_LABEL:
RETURN
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If the application requires a faster wake-up time, and can accept higher current requirements, the VREGS (RCON[8]) and VREGSF (RCON[11]) bits can be set to keep the internal regulator and the Flash regulator active during Sleep mode.
10.2.2 IDLE MODE
The following occurs in Idle mode:
· The CPU stops executing instructions. · The WDT is automatically cleared. · The system clock source remains active. By
default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 "Peripheral Module Disable"). · If the WDT or FSCM is enabled, the LPRC also remains active.
The device wakes from Idle mode on any of these events:
· Any interrupt that is individually enabled · Any device Reset · A WDT time-out
On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution will begin (two-four clock cycles later), starting with the instruction following the PWRSAV instruction or the first instruction in the Interrupt Service Routine (ISR).
All peripherals also have the option to discontinue operation when Idle mode is entered to allow for increased power savings. This option is selectable in the control register of each peripheral; for example, the TSIDL bit in the Timer1 Control register (T1CON[13]).
10.2.3
INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3 Doze Mode
The preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. In some circumstances, this cannot be practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely.
Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is
reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate.
Doze mode is enabled by setting the DOZEN bit (CLKDIV[11]). The ratio between peripheral and core clock speed is determined by the DOZE[2:0] bits (CLKDIV[14:12]). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting.
Programs can use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the ROI bit (CLKDIV[15]). By default, interrupt events have no effect on Doze mode operation.
For example, suppose the device is operating at 20 MIPS and the ECANTM module has been configured for 500 kbps, based on this device operating speed. If the device is placed in Doze mode with a clock frequency ratio of 1:4, the ECAN module continues to communicate at the required bit rate of 500 kbps, but the CPU now starts executing instructions at a frequency of 5 MIPS.
10.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid.
A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC® DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default.
Note:
If a PMD bit is set, the corresponding module is disabled after a delay of one instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation).
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10.5 Power-Saving Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
10.5.1 KEY RESOURCES
· "Watchdog Timer and Power-Saving Modes" (www.microchip.com/DS70615) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0 T5MD bit 15
R/W-0 T4MD
R/W-0 T3MD
R/W-0 T2MD
R/W-0 T1MD
R/W-0 QEI1MD(1)
R/W-0 PWMMD(1)
U-0 --
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
--
C1MD(2)
AD1MD
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4
T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled
T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled
T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled
T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled
T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled QEI1MD: QEI1 Module Disable bit(1) 1 = QEI1 module is disabled 0 = QEI1 module is enabled PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled
Unimplemented: Read as `0'
I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled
U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled
U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled
SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.
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REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
bit 3
SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled 0 = SPI1 module is enabled
bit 2
Unimplemented: Read as `0'
bit 1
C1MD: ECAN1 Module Disable bit(2)
1 = ECAN1 module is disabled 0 = ECAN1 module is enabled
bit 0
AD1MD: ADC1 Module Disable bit
1 = ADC1 module is disabled 0 = ADC1 module is enabled
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.
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REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
--
IC4MD
IC3MD
IC2MD
bit 15
R/W-0 IC1MD
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
--
--
--
--
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12 bit 11 bit 10 bit 9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0
Unimplemented: Read as `0'
IC4MD: Input Capture 4 Module Disable bit
1 = Input Capture 4 module is disabled 0 = Input Capture 4 module is enabled
IC3MD: Input Capture 3 Module Disable bit
1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled
IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled
IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled
Unimplemented: Read as `0'
OC4MD: Output Compare 4 Module Disable bit
1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled
OC3MD: Output Compare 3 Module Disable bit
1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled
OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled
OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled
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REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
--
--
--
--
--
CMPMD
--
bit 15
U-0 --
bit 8
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
CRCMD
--
--
--
--
--
I2C2MD
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-11 bit 10
bit 9-8 bit 7
bit 6-2 bit 1
bit 0
Unimplemented: Read as `0'
CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled 0 = Comparator module is enabled
Unimplemented: Read as `0'
CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled
Unimplemented: Read as `0'
I2C2MD: I2C2 Module Disable bit
1 = I2C2 module is disabled 0 = I2C2 module is enabled
Unimplemented: Read as `0'
REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
--
--
--
--
REFOMD CTMUMD
--
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-4 bit 3
bit 2
bit 1-0
Unimplemented: Read as `0'
REFOMD: Reference Clock Module Disable bit
1 = Reference clock module is disabled 0 = Reference clock module is enabled
CTMUMD: CTMU Module Disable bit
1 = CTMU module is disabled 0 = CTMU module is enabled
Unimplemented: Read as `0'
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REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
--
--
--
--
--
PWM3MD(1) PWM2MD(1)
bit 15
R/W-0 PWM1MD(1)
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-11 bit 10
bit 9
bit 8
bit 7-0
Unimplemented: Read as `0' PWM3MD: PWM3 Module Disable bit(1)
1 = PWM3 module is disabled 0 = PWM3 module is enabled PWM2MD: PWM2 Module Disable bit(1)
1 = PWM2 module is disabled 0 = PWM2 module is enabled PWM1MD: PWM1 Module Disable bit(1)
1 = PWM1 module is disabled 0 = PWM1 module is enabled
Unimplemented: Read as `0'
Note 1: This bit is available on dsPIC33EPXXXMC50X/20X and PIC24EPXXXMC20X devices only.
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REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
DMA0MD(1)
--
--
--
DMA1MD(1) DMA2MD(1)
PTGMD
--
--
--
DMA3MD(1)
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-5 bit 4
bit 3 bit 2-0
Unimplemented: Read as `0' DMA0MD: DMA0 Module Disable bit(1)
1 = DMA0 module is disabled 0 = DMA0 module is enabled DMA1MD: DMA1 Module Disable bit(1)
1 = DMA1 module is disabled 0 = DMA1 module is enabled DMA2MD: DMA2 Module Disable bit(1)
1 = DMA2 module is disabled 0 = DMA2 module is enabled DMA3MD: DMA3 Module Disable bit(1)
1 = DMA3 module is disabled 0 = DMA3 module is enabled
PTGMD: PTG Module Disable bit
1 = PTG module is disabled 0 = PTG module is enabled
Unimplemented: Read as `0'
Note 1: This single bit enables and disables all four DMA channels.
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11.0 I/O PORTS
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "I/O Ports" (www.microchip.com/DS70000598) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
Many of the device pins are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity.
11.1 Parallel I/O (PIO) Ports
Generally, a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port
has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through," in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 illustrates how ports are shared with other peripherals and the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port.
All port pins have eight registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Latch register (LATx) read the latch. Writes to the Latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch.
Any bit and its associated data and control registers that are not valid for a particular device is disabled. This means the corresponding LATx and TRISx registers and the port pin are read as zeros.
When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data
Output Multiplexers
I/O 1 Output Enable 0
Read TRIS
PIO Module
1 Output Data 0
Data Bus WR TRIS
WR LAT + WR Port Read LAT Read Port
DQ
CK TRIS Latch
DQ
CK Data Latch
I/O Pin Input Data
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11.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx and TRISx registers for data control, port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.
The open-drain feature allows the generation of outputs other than VDD by using external pull-up resistors. The maximum open-drain voltage allowed on any pin is the same as the maximum VIH specification for that particular pin.
See the "Pin Diagrams" section for the available 5V tolerant pins and Table 30-11 for the maximum VIH specification for each pin.
11.2 Configuring Analog and Digital Port Pins
The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs or outputs must have their corresponding ANSELx and TRISx bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared. When ANSELx = 1 (the port is selected as analog) and TRISx = 1 (digital I/O enabled), the digital input value read by the port is always `0'.
The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are analog (not digital) by default.
Pins with analog functions affected by the ANSELx registers are listed with a buffer type of analog in the Pinout I/O Descriptions (see Table 1-1).
If the TRISx bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or comparator module.
When the PORTx register is read, all pins configured as analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications.
11.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP, as shown in Example 11-1.
11.3 Input Change Notification (ICN)
The Input Change Notification function of the I/O ports allows devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature can detect input Change-of-States even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a Change-of-State.
Three control registers are associated with the Change Notification (CN) functionality of each I/O port. The CNENx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins.
Each I/O pin also has a weak pull-up and a weak pull-down connected to it. The pull-ups and pulldowns act as a current source or sink source connected to the pin and eliminate the need for external resistors when push button, or keypad devices are connected. The pull-ups and pull-downs are enabled separately, using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins.
Note:
Pull-ups and pull-downs on Change Notification pins should always be disabled when the port pin is configured as a digital output.
EXAMPLE 11-1: PORT WRITE/READ EXAMPLE
MOV 0xFF00, W0
MOV W0, TRISB
NOP BTSS PORTB, #13
; Configure PORTB<15:8> ; as inputs ; and PORTB<7:0> ; as outputs ; Delay 1 cycle ; Next Instruction
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11.4 Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient work arounds in application code, or a complete redesign, may be the only option.
Peripheral Pin Select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device.
The Peripheral Pin Select configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to any one of these I/O pins. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established.
11.4.1 AVAILABLE PINS
The number of available pins is dependent on the particular device and its pin count. Pins that support the Peripheral Pin Select feature include the label, "RPn" or "RPIn", in their full pin designation, where "n" is the remappable pin number. "RP" is used to designate pins that support both remappable input and output functions, while "RPI" indicates pins that support remappable input functions only.
11.4.2 AVAILABLE PERIPHERALS
The peripherals managed by the Peripheral Pin Select are all digital-only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs.
In comparison, some digital-only peripheral modules are never included in the Peripheral Pin Select feature. This is because the peripheral's function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C and the PWM. A similar requirement excludes all modules with analog inputs, such as the ADC Converter.
A key difference between remappable and nonremappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral.
When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin.
11.4.3
CONTROLLING PERIPHERAL PIN SELECT
Peripheral Pin Select features are controlled through two sets of SFRs: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint.
The association of a peripheral to a peripheralselectable pin is handled in two different ways, depending on whether an input or output is being mapped.
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11.4.4 INPUT MAPPING
The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 11-1 through Register 11-17). Each register contains sets of 7-bit fields, with each set associated with one of the remappable peripherals. Programming a given peripheral's bit field with an appropriate 7-bit value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field corresponds to the maximum number of Peripheral Pin Selections supported by the device.
For example, Figure 11-2 illustrates remappable pin selection for the U1RX input.
FIGURE 11-2:
REMAPPABLE INPUT FOR U1RX
U1RXR[6:0]
0 RP0
1
RP1
U1RX Input
2 to Peripheral
RP3
11.4.4.1 Virtual Connections
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices support virtual (internal) connections to the output of the op amp/ comparator module (see Figure 25-1 in Section 25.0 "Op Amp/Comparator Module") and the PTG module (see Section 24.0 "Peripheral Trigger Generator (PTG) Module").
In addition, dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices support virtual connections to the filtered QEI module inputs: FINDX1, FHOME1, FINDX2 and FHOME2 (see Figure 17-1 in Section 17.0 "Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)".
Virtual connections provide a simple way of interperipheral connection without utilizing a physical pin. For example, by setting the FLT1R[6:0] bits of the RPINR12 register to the value of `b0000001, the output of the analog comparator, C1OUT, will be connected to the PWM Fault 1 input, which allows the analog comparator to trigger PWM Faults without the use of an actual physical pin on the device.
Virtual connection to the QEI module allows peripherals to be connected to the QEI digital filter input. To utilize this filter, the QEI module must be enabled and its inputs must be connected to a physical RPn pin. Example 11-2 illustrates how the input capture module can be connected to the QEI digital filter.
RPn Note:
n
For input only, Peripheral Pin Select functionality does not have priority over TRISx settings. Therefore, when configuring an RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to `1').
EXAMPLE 11-2: CONNECTING IC1 TO THE HOME1 QEI1 DIGITAL FILTER INPUT ON PIN 43 OF THE dsPIC33EPXXXMC206 DEVICE
RPINR15 = 0x2500; RPINR7 = 0x009;
/* Connect the QEI1 HOME1 input to RP37 (pin 43) */ /* Connect the IC1 input to the digital filter on the FHOME1 input */
QEI1IOC = 0x4000; QEI1CON = 0x8000;
/* Enable the QEI digital filter */ /* Enable the QEI module */
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TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Input Name(1)
Function Name
Register
Configuration Bits
External Interrupt 1
INT1
RPINR0
INT1R[6:0]
External Interrupt 2
INT2
RPINR1
INT2R[6:0]
Timer2 External Clock
T2CK
RPINR3
T2CKR[6:0]
Input Capture 1
IC1
RPINR7
IC1R[6:0]
Input Capture 2
IC2
RPINR7
IC2R[6:0]
Input Capture 3
IC3
RPINR8
IC3R[6:0]
Input Capture 4
IC4
RPINR8
IC4R[6:0]
Output Compare Fault A PWM Fault 1(3) PWM Fault 2(3) QEI1 Phase A(3) QEI1 Phase B(3) QEI1 Index(3) QEI1 Home(3)
OCFA FLT1 FLT2 QEA1 QEB1 INDX1 HOME1
RPINR11 RPINR12 RPINR12 RPINR14 RPINR14 RPINR15 RPINR15
OCFAR[6:0] FLT1R[6:0] FLT2R[6:0] QEA1R[6:0] QEB1R[6:0] INDX1R[6:0] HOM1R[6:0]
UART1 Receive
U1RX
RPINR18
U1RXR[6:0]
UART2 Receive
U2RX
RPINR19
U2RXR[6:0]
SPI2 Data Input
SDI2
RPINR22
SDI2R[6:0]
SPI2 Clock Input
SCK2
RPINR22
SCK2R[6:0]
SPI2 Slave Select CAN1 Receive(2) PWM Sync Input 1(3) PWM Dead-Time Compensation 1(3) PWM Dead-Time Compensation 2(3) PWM Dead-Time Compensation 3(3)
SS2 C1RX SYNCI1 DTCMP1 DTCMP2 DTCMP3
RPINR23 RPINR26 RPINR37 RPINR38 RPINR39 RPINR39
SS2R[6:0] C1RXR[6:0] SYNCI1R[6:0] DTCMP1R[6:0] DTCMP2R[6:0] DTCMP3R[6:0]
Note 1: 2: 3:
Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. This input source is available on dsPIC33EPXXXGP/MC50X devices only. This input source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
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TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES
Peripheral Pin Select Input
Register Value
Input/ Output
Pin Assignment
Peripheral Pin Select Input
Register Value
Input/ Output
Pin Assignment
000 0000
I
000 0001
I
000 0010
I
000 0011
I
000 0100
I
VSS C1OUT(1) C2OUT(1) C3OUT(1) C4OUT(1)
010 1101
I
010 1110
I
010 1111
I
011 0000
--
011 0001
--
RPI45 RPI46 RPI47
-- --
000 0101 000 0110 000 0111 000 1000 000 1001
--
--
I
PTGO30(1)
I
PTGO31(1)
I
FINDX1(1,2)
I
FHOME1(1,2)
011 0010
--
011 0011
I
011 0100
I
011 0101
I
011 0110
I/O
-- RPI51 RPI52 RPI53 RP54
000 1010
--
--
011 0111
I/O
RP55
000 1011
--
--
011 1000
I/O
RP56
000 1100
--
--
011 1001
I/O
RP57
000 1101
--
--
011 1010
I
RPI58
000 1110
--
--
011 1011
--
--
000 1111
--
--
011 1100
--
--
001 0000
--
--
011 1101
--
--
001 0001
--
--
011 1110
--
--
001 0010
--
--
011 1111
--
--
001 0011
--
--
100 0000
--
--
001 0100
I/O
RP20
100 0001
--
--
001 0101
--
--
100 0010
--
--
001 0110
--
--
100 0011
--
--
001 0111
--
--
100 0100
--
--
001 1000
I
RPI24
100 0101
--
--
001 1001
I
RPI25
100 0110
--
--
001 1010
--
--
100 0111
--
--
001 1011
I
RPI27
100 1000
--
--
001 1100
I
RPI28
100 1001
--
--
001 1101
--
--
100 1010
--
--
001 1110
--
--
100 1011
--
--
001 1111
--
--
100 1100
--
--
010 0000
I
RPI32
100 1101
--
--
010 0001
I
RPI33
100 1110
--
--
010 0010
I
RPI34
100 1111
--
--
010 0011
I/O
RP35
101 0000
--
--
010 0100
I/O
RP36
101 0001
--
--
010 0101
I/O
RP37
101 0010
--
--
010 0110
I/O
RP38
101 0011
--
--
010 0111
I/O
RP39
101 0100
--
--
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 "Virtual Connections" for more information on selecting this pin assignment.
2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only.
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TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED)
Peripheral Pin Select Input
Register Value
Input/ Output
Pin Assignment
Peripheral Pin Select Input
Register Value
Input/ Output
Pin Assignment
010 1000
I/O
RP40
101 0101
--
--
010 1001
I/O
RP41
101 0110
--
--
010 1010
I/O
RP42
101 0111
--
--
010 1011
I/O
RP43
101 1000
--
--
010 1100
I
RPI44
101 1001
--
--
101 1010
--
--
110 1101
--
--
101 1011
--
--
110 1110
--
--
101 1100
--
--
110 1111
--
--
101 1101
--
--
111 0000
--
--
101 1110
I
RPI94
111 0001
--
--
101 1111
I
RPI95
111 0010
--
--
110 0000
I
RPI96
111 0011
--
--
110 0001
I/O
RP97
111 0100
--
--
110 0010
--
--
111 0101
--
--
110 0011
--
--
111 0110
I/O
RP118
110 0100
--
--
111 0111
I
RPI119
110 0101
--
--
111 1000
I/O
RP120
110 0110
--
--
111 1001
I
RPI121
110 0111
--
--
111 1010
--
--
110 1000
--
--
111 1011
--
--
110 1001
--
--
111 1100
--
--
110 1010
--
--
111 1101
--
--
110 1011
--
--
111 1110
--
--
110 1100
--
--
111 1111
--
--
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 "Virtual Connections" for more information on selecting this pin assignment.
2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only.
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11.4.4.2 Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets of 6-bit fields, with each set associated with one RPn pin (see Register 11-18 through Register 11-27). The value of the bit field corresponds to one of the peripherals and that peripheral's output is mapped to the pin (see Table 11-3 and Figure 11-3).
A null output is associated with the output register Reset value of `0'. This is done to ensure that remappable outputs remain disconnected from all output pins by default.
FIGURE 11-3: MULTIPLEXING REMAPPABLE OUTPUT FOR RPn
RPxR[5:0]
Default 0 U1TX Output 1 SDO2 Output 2
RPn Output Data
QEI1CCMP Output 48 REFCLKO Output 49
11.4.4.3 Mapping Limitations
The control schema of the peripheral select pins is not limited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced lockouts between any of the peripheral mapping SFRs. Literally any combination of peripheral mappings across any or all of the RPn pins is possible. This includes both many-toone and one-to-many mappings of peripheral inputs and outputs to pins. While such mappings may be technically possible from a configuration point of view, they may not be supportable from an electrical point of view.
TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Function
RPxR[5:0]
Output Name
Default PORT
000000
RPn tied to Default Pin
U1TX
000001
RPn tied to UART1 Transmit
U2TX
000011
RPn tied to UART2 Transmit
SDO2
001000
RPn tied to SPI2 Data Output
SCK2
001001
RPn tied to SPI2 Clock Output
SS2 C1TX(2)
001010 001110
RPn tied to SPI2 Slave Select RPn tied to CAN1 Transmit
OC1
010000
RPn tied to Output Compare 1 Output
OC2
010001
RPn tied to Output Compare 2 Output
OC3
010010
RPn tied to Output Compare 3 Output
OC4
010011
RPn tied to Output Compare 4 Output
C1OUT
011000
RPn tied to Comparator Output 1
C2OUT
011001
RPn tied to Comparator Output 2
C3OUT SYNCO1(1) QEI1CCMP(1)
011010 101101 101111
RPn tied to Comparator Output 3 RPn tied to PWM Primary Time Base Sync Output RPn tied to QEI 1 Counter Comparator Output
REFCLKO
110001
RPn tied to Reference Clock Output
C4OUT
110010
RPn tied to Comparator Output 4
Note 1: This function is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This function is available in dsPIC33EPXXXGP/MC50X devices only.
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11.5 I/O Helpful Tips
1. In some cases, certain pins, as defined in Table 30-11, under "Injection Current", have internal protection diodes to VDD and VSS. The term, "Injection Current", is also referred to as "Clamp Current". On designated pins, with sufficient external current-limiting precautions by the user, I/O pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings, with respect to the VSS and VDD supplies. Note that when the user application forward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device, that is clamped internally by the VDD and VSS power rails, may affect the ADC accuracy by four to six counts.
2. I/O pins that are shared with any analog input pin (i.e., ANx) are always analog pins by default after any Reset. Consequently, configuring a pin as an analog input pin automatically disables the digital input pin buffer and any attempt to read the digital input level by reading PORTx or LATx will always return a `0', regardless of the digital logic level on the pin. To use a pin as a digital I/O pin on a shared ANx pin, the user application needs to configure the Analog Pin Configuration registers in the I/O ports module (i.e., ANSELx) by setting the appropriate bit that corresponds to that I/O port pin to a `0'.
Note:
Although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital I/O output function, TRISx = 0x0, while the analog function is also enabled. However, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would create signal contention between the analog signal and the output pin driver.
3. Most I/O pins have multiple functions. Referring to the device pin diagrams in this data sheet, the priorities of the functions allocated to any pins are indicated by reading the pin name from left-to-right. The left most function name takes precedence over any function to its right in the naming convention. For example: AN16/T2CK/T7CK/RC1. This indicates that AN16 is the highest priority in this example and will supersede all other functions to its right in the list. Those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. This rule applies to all of the functions listed for a given pin.
4. Each pin has an internal weak pull-up resistor and pull-down resistor that can be configured using the CNPUx and CNPDx registers, respectively. These resistors eliminate the need for external resistors in certain applications. The internal pull-up is up to ~(VDD 0.8), not VDD. This value is still above the minimum VIH of CMOS and TTL devices.
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5. When driving LEDs directly, the I/O pin can source or sink more current than what is specified in the VOH/IOH and VOL/IOL DC characteristic specification. The respective IOH and IOL current rating only applies to maintaining the corresponding output at or above the VOH, and at or below the VOL levels. However, for LEDs, unlike digital inputs of an externally connected device, they are not governed by the same minimum VIH/VIL levels. An I/O pin output can safely sink or source any current less than that listed in the absolute maximum rating section of this data sheet. For example: VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V The maximum output current sourced by any 8 mA I/O pin = 12 mA. LED source current < 12 mA is technically permitted. Refer to the VOH/IOH graphs in Section 30.0 "Electrical Characteristics" for additional information.
6. The Peripheral Pin Select (PPS) pin mapping rules are as follows: a) Only one "output" function can be active on a given pin at any time, regardless if it is a dedicated or remappable function (one pin, one output). b) It is possible to assign a "remappable output" function to multiple pins and externally short or tie them together for increased current drive. c) If any "dedicated output" function is enabled on a pin, it will take precedence over any remappable "output" function. d) If any "dedicated digital" (input or output) function is enabled on a pin, any number of "input" remappable functions can be mapped to the same pin. e) If any "dedicated analog" function(s) are enabled on a given pin, "digital input(s)" of any kind will all be disabled, although a single "digital output", at the user's cautionary discretion, can be enabled and active as long as there is no signal contention with an external analog input signal. For example, it is possible for the ADC to convert the digital output logic level, or to toggle a digital output on a comparator or ADC input provided there is no external analog input, such as for a built-in self-test. f) Any number of "input" remappable functions can be mapped to the same pin(s) at the same time, including to any pin with a single output from either a dedicated or remappable "output".
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g) The TRISx registers control only the digital I/O output buffer. Any other dedicated or remappable active "output" will automatically override the TRIS setting. The TRISx register does not control the digital logic "input" buffer. Remappable digital "inputs" do not automatically override TRIS settings, which means that the TRISx bit must be set to input for pins with only remappable input function(s) assigned
h) All analog pins are enabled by default after any Reset and the corresponding digital input buffer on the pin has been disabled. Only the Analog Pin Select registers control the digital input buffer, not the TRISx register. The user must disable the analog function on a pin using the Analog Pin Select registers in order to use any "digital input(s)" on a corresponding pin, no exceptions.
11.6 I/O Ports Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
11.6.1 KEY RESOURCES
· "I/O Ports" (www.microchip.com/DS70000598) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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11.7 Peripheral Pin Select Registers
REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0 INT1R[6:0]
R/W-0
R/W-0
R/W-0 bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7-0
Unimplemented: Read as `0'
INT1R[6:0]: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
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REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 INT2R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
INT2R[6:0]: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 T2CKR[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
T2CKR[6:0]: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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REGISTER 11-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0 IC2R[6:0]
R/W-0
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 IC1R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
IC2R[6:0]: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
IC1R[6:0]: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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REGISTER 11-5: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0 IC4R[6:0]
R/W-0
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 IC3R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
IC4R[6:0]: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
IC3R[6:0]: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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REGISTER 11-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 OCFAR[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
OCFAR[6:0]: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-7: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0 FLT2R[6:0]
R/W-0
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 FLT1R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
FLT2R[6:0]: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
FLT1R[6:0]: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-8: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0 QEB1R[6:0]
R/W-0
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 QEA1R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
QEB1R[6:0]: Assign B (QEB) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
QEA1R[6:0]: Assign A (QEA) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-9: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HOME1R[6:0]
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 INDX1R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
HOME1R[6:0]: Assign QEI1 HOME1 (HOME1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
IND1XR[6:0]: Assign QEI1 INDEX1 (INDX1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-10: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 U1RXR[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
U1RXR[6:0]: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
REGISTER 11-11: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 U2RXR[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
U2RXR[6:0]: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCK2INR[6:0]
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 SDI2R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
SCK2INR[6:0]: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
SDI2R[6:0]: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 SS2R[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
SS2R[6:0]: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
REGISTER 11-14: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26 (dsPIC33EPXXXGP/MC50X DEVICES ONLY)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0 C1RXR[6:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-0
Unimplemented: Read as `0'
C1RXR[6:0]: Assign CAN1 RX Input (CRX1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-15: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37 (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCI1R[6:0]
R/W-0
R/W-0 bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7-0
Unimplemented: Read as `0'
SYNCI1R[6:0]: Assign PWM Synchronization Input 1 (SYNCI1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-16: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38 (dsPIC33EPXXXMC20X AND PIC24EPXXXMC20X DEVICES ONLY)
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP1R[6:0]
R/W-0
R/W-0 bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7-0
Unimplemented: Read as `0'
DTCMP1R[6:0]: Assign PWM Dead-Time Compensation Input 1 (DTCMP1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-17: RPINR39: PERIPHERAL PIN SELECT INPUT REGISTER 39 (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
U-0 -- bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP3R[6:0]
R/W-0
R/W-0 bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP2R[6:0]
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-8
bit 7 bit 6-0
Unimplemented: Read as `0'
DTCMP3R[6:0]: Assign PWM Dead-Time Compensation Input 3 (DTCMP3) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
Unimplemented: Read as `0'
DTCMP2R[6:0]: Assign PWM Dead-Time Compensation Input 2 (DTCMP2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121 · · · 0000001 = Input tied to CMP1 0000000 = Input tied to VSS
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-18: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP35R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP20R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP35R[5:0]: Peripheral Output Function is Assigned to RP35 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP20R[5:0]: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 11-3 for peripheral function numbers)
REGISTER 11-19: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP37R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP36R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP37R[5:0]: Peripheral Output Function is Assigned to RP37 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP36R[5:0]: Peripheral Output Function is Assigned to RP36 Output Pin bits (see Table 11-3 for peripheral function numbers)
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-20: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP39R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP38R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP39R[5:0]: Peripheral Output Function is Assigned to RP39 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP38R[5:0]: Peripheral Output Function is Assigned to RP38 Output Pin bits (see Table 11-3 for peripheral function numbers)
REGISTER 11-21: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP41R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP40R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP41R[5:0]: Peripheral Output Function is Assigned to RP41 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP40R[5:0]: Peripheral Output Function is Assigned to RP40 Output Pin bits (see Table 11-3 for peripheral function numbers)
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-22: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP43R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP42R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP43R[5:0]: Peripheral Output Function is Assigned to RP43 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP42R[5:0]: Peripheral Output Function is Assigned to RP42 Output Pin bits (see Table 11-3 for peripheral function numbers)
REGISTER 11-23: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP55R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP54R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP55R[5:0]: Peripheral Output Function is Assigned to RP55 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP54R[5:0]: Peripheral Output Function is Assigned to RP54 Output Pin bits (see Table 11-3 for peripheral function numbers)
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-24: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP57R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP56R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
RP57R[5:0]: Peripheral Output Function is Assigned to RP57 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
RP56R[5:0]: Peripheral Output Function is Assigned to RP56 Output Pin bits (see Table 11-3 for peripheral function numbers)
REGISTER 11-25: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP97R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-0
Unimplemented: Read as `0' RP97R[5:0]: Peripheral Output Function is Assigned to RP97 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-26: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP118R[5:0]
R/W-0 bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-0
Unimplemented: Read as `0' RP118R[5:0]: Peripheral Output Function is Assigned to RP118 Output Pin bits (see Table 11-3 for peripheral function numbers)
Unimplemented: Read as `0'
REGISTER 11-27: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
RP120R[5:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-6 bit 5-0
Unimplemented: Read as `0'
RP120R[5:0]: Peripheral Output Function is Assigned to RP120 Output Pin bits (see Table 11-3 for peripheral function numbers)
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NOTES:
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12.0 TIMER1
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Timers" (www.microchip.com/DS70362) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Timer1 module is a 16-bit timer that can operate as a free-running interval timer/counter.
The Timer1 module has the following unique features over other timers:
· Can be Operated in Asynchronous Counter mode from an External Clock Source
· The External Clock Input (T1CK) can Optionally be Synchronized to the Internal Device Clock and the Clock Synchronization is Performed after the Prescaler
A block diagram of Timer1 is shown in Figure 12-1.
The Timer1 module can operate in one of the following modes:
· Timer mode · Gated Timer mode · Synchronous Counter mode · Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, the input clock is derived from the external clock input at the T1CK pin.
The Timer modes are determined by the following bits:
· Timer Clock Source Control bit (TCS): T1CON[1] · Timer Synchronization Control bit (TSYNC):
T1CON[2] · Timer Gate Control bit (TGATE): T1CON[6]
Timer control bit setting for different operating modes are given in the Table 12-1.
TABLE 12-1:
Mode
Timer Gated Timer Synchronous Counter Asynchronous Counter
TIMER MODE SETTINGS
TCS
TGATE TSYNC
0
0
x
0
1
x
1
x
1
1
x
0
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
T1CK
Gate Sync
Falling Edge Detect
FP(1) Prescaler
10
(/n)
TCKPS[1:0]
00
0
Prescaler (/n)
x1
Sync
1
TCKPS[1:0]
TSYNC
TGATE TCS
1 Set T1IF Flag
0
T1CLK TMR1 Reset
TGATE Latch
Data
CLK
Comparator Equal
CTMU Edge Control
Logic
PR1
Note 1: FP is the peripheral clock.
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12.1 Timer1 Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
12.1.1 KEY RESOURCES
· "Timers" (www.microchip.com/DS70362) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
DS70000657J-page 206
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12.2 Timer1 Control Register
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
TON(1)
--
TSIDL
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
TGATE
TCKPS1 TCKPS0
--
TSYNC(1)
TCS(1)
U-0 --
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-7 bit 6
bit 5-4
bit 3 bit 2
bit 1 bit 0
TON: Timer1 On bit(1)
1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1
Unimplemented: Read as `0'
TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
Unimplemented: Read as `0'
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1: This bit is ignored.
When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled
TCKPS[1:0]: Timer1 Input Clock Prescale Select bits
11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1
Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input
When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge) 0 = Internal clock (FP)
Unimplemented: Read as `0'
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any attempts by user software to write to the TMR1 register are ignored.
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NOTES:
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13.0 TIMER2/3 AND TIMER4/5
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Timers" (www.microchip.com/DS70362) of the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes.
As 32-bit timers, Timer2/3 and Timer4/5 operate in three modes:
· Two Independent 16-Bit Timers (e.g., Timer2 and Timer3) with all 16-Bit Operating modes (except Asynchronous Counter mode)
· Single 32-Bit Timer
· Single 32-Bit Synchronous Counter
They also support these features:
· Timer Gate Operation · Selectable Prescaler Settings · Timer Operation during Idle and Sleep modes
· Interrupt on a 32-Bit Period Register Match · Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only) · ADC1 Event Trigger (32-bit timer pairs, and
Timer3 and Timer5 only)
Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed previously, except for the event trigger; this is implemented only with Timer2/3. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, and T4CON, T5CON registers. T2CON and T4CON are shown in generic form in Register 13-1. T3CON and T5CON are shown in Register 13-2.
For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word (lsw); Timer3 and Timer5 are the most significant word (msw) of the 32-bit timers.
Note:
For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 and Timer5 interrupt flags.
A block diagram for an example 32-bit timer pair (Timer2/3 and Timer4/5) is shown in Figure 13-3.
Note: Only Timer2, 3, 4 and 5 can trigger a DMA data transfer.
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FIGURE 13-1:
TYPE B TIMER BLOCK DIAGRAM (x = 2 AND 4)
TxCK
Gate Sync
Falling Edge Detect
FP(1) Prescaler
10
(/n)
TCKPS[1:0]
00
Prescaler (/n)
Sync
x1
1 Set TxIF Flag
0
TxCLK TMRx Reset
TGATE Latch
Data
CLK
Comparator Equal
TCKPS[1:0]
TGATE
TCS
PRx
Note 1: FP is the peripheral clock.
FIGURE 13-2:
TYPE C TIMER BLOCK DIAGRAM (x = 3 AND 5)
TxCK
Gate Sync
Falling Edge Detect
FP(1) Prescaler
10
(/n)
TCKPS[1:0]
00
Prescaler (/n)
Sync
x1
TCKPS[1:0]
TGATE TCS
1 Set TxIF Flag
0
TxCLK TMRx Reset
TGATE Latch
Data
CLK
Comparator Equal
ADC Start of Conversion Trigger(2)
PRx
Note 1: FP is the peripheral clock. 2: The ADC trigger is available on TMR3 and TMR5 only.
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FIGURE 13-3:
TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
TxCK
Gate Sync
Falling Edge Detect
FP(1) Prescaler
10
(/n)
TCKPS[1:0]
00
Prescaler (/n)
Sync
x1
TCKPS[1:0]
TGATE TCS
PRx
PRy
Comparator
Equal
lsw TMRx
msw
TMRy
Reset
1 Set TyIF Flag
0 TGATE
Data Latch
ADC CLK
TMRyHLD
Data Bus[15:0]
Note 1: 2: 3:
The ADC trigger is available on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs. Timerx is a Type B timer (x = 2 and 4). Timery is a Type C timer (y = 3 and 5).
13.1 Timerx/y Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/ wwwproducts/Devices.aspx?d DocName=en555464
13.1.1 KEY RESOURCES
· "Timers" (www.microchip.com/DS70362) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
2011-2020 Microchip Technology Inc.
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13.2 Timer Control Registers
REGISTER 13-1: TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
TON
--
TSIDL
--
--
--
--
bit 15
U-0 --
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
--
TGATE
TCKPS1 TCKPS0
T32
--
TCS(1)
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14 bit 13 bit 12-7 bit 6
bit 5-4
bit 3 bit 2 bit 1 bit 0
TON: Timerx On bit
When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When T32 = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx
Unimplemented: Read as `0'
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
Unimplemented: Read as `0'
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1: This bit is ignored.
When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled
TCKPS[1:0]: Timerx Input Clock Prescale Select bits
11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1
T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers
Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge) 0 = Internal clock (FP)
Unimplemented: Read as `0'
Note 1: The TxCK pin is not available on all devices. See the "Pin Diagrams" section for the available pins.
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REGISTER 13-2: TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
TON(1)
--
TSIDL(2)
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0
R/W-0
R/W-0
U-0
TGATE(1) TCKPS1(1) TCKPS0(1)
--
U-0
R/W-0
U-0
--
TCS(1,3)
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-7 bit 6
bit 5-4
bit 3-2 bit 1 bit 0
TON: Timery On bit(1)
1 = Starts 16-bit Timery 0 = Stops 16-bit Timery
Unimplemented: Read as `0' TSIDL: Timery Stop in Idle Mode bit(2)
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1: This bit is ignored.
When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS[1:0]: Timery Input Clock Prescale Select bits(1)
11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1
Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(1,3)
1 = External clock is from pin, TyCK (on the rising edge) 0 = Internal clock (FP)
Unimplemented: Read as `0'
Note 1: 2: 3:
When 32-bit operation is enabled (T2CON[3] = 1), these bits have no effect on Timery operation; all timer functions are set through TxCON.
When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON[3]), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode.
The TyCK pin is not available on all devices. See the "Pin Diagrams" section for the available pins.
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NOTES:
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14.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Input Capture with Dedicated Timer" (www.microchip.com/DS70000352) in the "dsPIC33/dsPIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices support four input capture channels.
Key features of the input capture module include:
· Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules
· Synchronous and Trigger modes of output compare operation, with up to 19 user-selectable Trigger/Sync sources available
· A 4-level FIFO buffer for capturing and holding timer values for several events
· Configurable interrupt generation
· Up to six clock sources available for each module, driving a separate internal 16-bit counter
FIGURE 14-1:
INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM[2:0]
ICI[1:0]
ICx Pin
Prescaler Counter 1:1/4/16
ICTSEL[2:0]
Edge Detect Logic and
Clock Synchronizer
Event and Interrupt
Logic
CTMU Edge Control Logic Set ICxIF PTG Trigger Input
IC Clock Sources
Clock Select
Increment
ICxTMR
16 4-Level FIFO Buffer
16
Trigger and Sync Sources
Trigger and Sync Logic
Reset SYNCSEL[4:0] Trigger(1)
16 ICxBUF
ICOV, ICBNE
System Bus
Note 1: The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for proper ICx module operation or the Trigger/Sync source must be changed to another source option.
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14.1 Input Capture Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
14.1.1 KEY RESOURCES
· "Input Capture with Dedicated Timer" (www.microchip.com/DS70000352) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
14.2 Input Capture Registers
REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
--
ICSIDL
ICTSEL2
ICTSEL1 ICTSEL0
--
U-0 --
bit 8
U-0 -- bit 7
R/W-0 ICI1
R/W-0 ICI0
R/HC/HS-0 R/HC/HS-0
ICOV
ICBNE
R/W-0 ICM2
R/W-0 ICM1
R/W-0 ICM0
bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit W = Writable bit `1' = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13 bit 12-10
bit 9-7 bit 6-5
bit 4 bit 3 bit 2-0
Unimplemented: Read as `0'
ICSIDL: Input Capture Stop in Idle Control bit
1 = Input capture will halt in CPU Idle mode 0 = Input capture will continue to operate in CPU Idle mode
ICTSEL[2:0]: Input Capture Timer Select bits
111 = Peripheral clock (FP) is the clock source of the ICx 110 = Reserved 101 = Reserved 100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported) 011 = T5CLK is the clock source of the ICx 010 = T4CLK is the clock source of the ICx 001 = T2CLK is the clock source of the ICx 000 = T3CLK is the clock source of the ICx
Unimplemented: Read as `0'
ICI[1:0]: Number of Captures per Interrupt Select bits (this field is not used if ICM[2:0] = 001 or 111)
11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture buffer overflow occurred 0 = No input capture buffer overflow occurred
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty
ICM[2:0]: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only in CPU Sleep and Idle modes (rising edge detect only, all other control bits are not applicable)
110 = Unused (module is disabled) 101 = Capture mode, every 16th rising edge (Prescaler Capture mode) 100 = Capture mode, every 4th rising edge (Prescaler Capture mode) 011 = Capture mode, every rising edge (Simple Capture mode) 010 = Capture mode, every falling edge (Simple Capture mode) 001 = Capture mode, every edge rising and falling (Edge Detect mode (ICI[1:0]) is not used in this mode) 000 = Input capture module is turned off
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
R/W-0 IC32
bit 8
R/W-0
R/W/HS-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
ICTRIG(2) TRIGSTAT(3)
--
SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
HS = Hardware Settable bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-9 bit 8 bit 7
bit 6 bit 5
Unimplemented: Read as `0'
IC32: Input Capture 32-Bit Timer Mode Select bit (Cascade mode) 1 = Odd IC and Even IC form a single 32-bit input capture module(1) 0 = Cascade module operation is disabled ICTRIG: Input Capture Trigger Operation Select bit(2)
1 = Input source used to trigger the input capture timer (Trigger mode) 0 = Input source used to synchronize the input capture timer to a timer of another module
(Synchronization mode) TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running 0 = ICxTMR has not been triggered and is being held clear
Unimplemented: Read as `0'
Note 1: 2: 3:
4: 5: 6:
The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
The input source is selected by the SYNCSEL[4:0] bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL[4:0] bits). It can be read, set and cleared in software.
Do not use the ICx module as its own Sync or Trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. PTGO8 = IC1 PTGO9 = IC2 PTGO10 = IC3 PTGO11 = IC4
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL[4:0]: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = No Sync or Trigger source for ICx 11110 = Reserved 11101 = Reserved 11100 = CTMU module synchronizes or triggers ICx(5) 11011 = ADC1 module synchronizes or triggers ICx(5) 11010 = CMP3 module synchronizes or triggers ICx(5) 11001 = CMP2 module synchronizes or triggers ICx(5) 11000 = CMP1 module synchronizes or triggers ICx(5) 10111 = Reserved 10110 = Reserved 10101 = Reserved 10100 = Reserved 10011 = IC4 module synchronizes or triggers ICx 10010 = IC3 module synchronizes or triggers ICx 10001 = IC2 module synchronizes or triggers ICx 10000 = IC1 module synchronizes or triggers ICx 01111 = Timer5 synchronizes or triggers ICx 01110 = Timer4 synchronizes or triggers ICx 01101 = Timer3 synchronizes or triggers ICx (default) 01100 = Timer2 synchronizes or triggers ICx 01011 = Timer1 synchronizes or triggers ICx 01010 = PTGOx module synchronizes or triggers ICx(6) 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = OC4 module synchronizes or triggers ICx 00011 = OC3 module synchronizes or triggers ICx 00010 = OC2 module synchronizes or triggers ICx 00001 = OC1 module synchronizes or triggers ICx 00000 = No Sync or Trigger source for ICx
Note 1: 2: 3:
4: 5: 6:
The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
The input source is selected by the SYNCSEL[4:0] bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL[4:0] bits). It can be read, set and cleared in software.
Do not use the ICx module as its own Sync or Trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. PTGO8 = IC1 PTGO9 = IC2 PTGO10 = IC3 PTGO11 = IC4
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NOTES:
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
15.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Output Compare" (www.microchip.com/DS70000358) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The output compare module can select one of seven available clock sources for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value. The output compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. The output compare module can also generate interrupts on compare match events and trigger DMA data transfers.
Note:
Refer to "Output Compare" (www.microchip.com/DS70000358) in the "dsPIC33/PIC24 Family Reference Manual" for OCxR and OCxRS register restrictions.
FIGURE 15-1:
OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1 OCxCON2
OCxR Rollover/Reset
OCxR Buffer
OC Clock Sources
Trigger and Sync Sources SYNCSEL[4:0] Trigger(1)
Clock Select
Increment
Reset
Trigger and Sync Logic
Match Event
Comparator OCxTMR
Match Event Rollover
Comparator
Match Event
OCxRS Buffer
Rollover/Reset OCxRS
Reset
CTMU Edge Control Logic
OCx Pin
OC Output and Fault Logic
OCFB OCFA
PTG Trigger Input
OCx Synchronization/Trigger Event OCx Interrupt
Note 1: The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for proper OCx module operation or the Trigger/Sync source must be changed to another source option.
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15.1 Output Compare Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
15.1.1 KEY RESOURCES
· "Output Compare" (www.microchip.com/ DS70000358) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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15.2 Output Compare Control Registers
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
--
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0
--
R/W-0 ENFLTB
bit 8
R/W-0 ENFLTA bit 7
U-0
HSC/R/W-0 HSC/R/W-0
R/W-0
R/W-0
--
OCFLTB
OCFLTA TRIGMODE OCM2
R/W-0 OCM1
R/W-0 OCM0
bit 0
Legend: R = Readable bit -n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13 bit 12-10
bit 9 bit 8 bit 7 bit 6 bit 5 bit 4
Unimplemented: Read as `0'
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL[2:0]: Output Compare x Clock Select bits
111 = Peripheral clock (FP) 110 = Reserved 101 = PTGOx clock(2) 100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported) 011 = T5CLK is the clock source of the OCx 010 = T4CLK is the clock source of the OCx 001 = T3CLK is the clock source of the OCx 000 = T2CLK is the clock source of the OCx
Unimplemented: Read as `0'
ENFLTB: Fault B Input Enable bit
1 = Output Compare Fault B input (OCFB) is enabled 0 = Output Compare Fault B input (OCFB) is disabled
ENFLTA: Fault A Input Enable bit
1 = Output Compare Fault A input (OCFA) is enabled 0 = Output Compare Fault A input (OCFA) is disabled
Unimplemented: Read as `0'
OCFLTB: PWM Fault B Condition Status bit
1 = PWM Fault B condition on OCFB pin has occurred 0 = No PWM Fault B condition on OCFB pin has occurred
OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on OCFA pin has occurred 0 = No PWM Fault A condition on OCFA pin has occurred
Note 1: 2:
OCxR and OCxRS are double-buffered in PWM mode only.
Each Output Compare x module (OCx) has one PTG clock source. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. PTGO4 = OC1 PTGO5 = OC2 PTGO6 = OC3 PTGO7 = OC4
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REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 3 bit 2-0
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2[6]) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is cleared only by software
OCM[2:0]: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1) 101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle 011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin 010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces
OCx pin low 001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces
OCx pin high 000 = Output compare channel is disabled
Note 1: 2:
OCxR and OCxRS are double-buffered in PWM mode only.
Each Output Compare x module (OCx) has one PTG clock source. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. PTGO4 = OC1 PTGO5 = OC2 PTGO6 = OC3 PTGO7 = OC4
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
FLTMD
FLTOUT FLTTRIEN
OCINV
--
--
--
bit 15
R/W-0 OC32
bit 8
R/W-0 OCTRIG bit 7
HS/R/W-0 TRIGSTAT
R/W-0 OCTRIS
R/W-0 SYNCSEL4
R/W-1 SYNCSEL3
R/W-1 SYNCSEL2
R/W-0 SYNCSEL1
R/W-0 SYNCSEL0
bit 0
Legend: R = Readable bit -n = Value at POR
HS = Hardware Settable bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14 bit 13 bit 12 bit 11-9 bit 8 bit 7 bit 6 bit 5
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTx bit is cleared in software and a new PWM period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition 0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
OCINV: Output Compare x Invert bit
1 = OCx output is inverted 0 = OCx output is not inverted
Unimplemented: Read as `0'
OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled 0 = Cascade module operation is disabled
OCTRIG: Output Compare x Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits 0 = Synchronizes OCx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear
OCTRIS: Output Compare x Output Pin Direction Select bit
1 = OCx is tri-stated 0 = Output Compare x module drives the OCx pin
Note 1: 2:
3:
Do not use the OCx module as its own Synchronization or Trigger source.
When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.
Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. PTGO0 = OC1 PTGO1 = OC2 PTGO2 = OC3 PTGO3 = OC4
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL[4:0]: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization 11110 = INT2 pin synchronizes or triggers OCx 11101 = INT1 pin synchronizes or triggers OCx 11100 = CTMU module synchronizes or triggers OCx 11011 = ADC1 module synchronizes or triggers OCx 11010 = CMP3 module synchronizes or triggers OCx 11001 = CMP2 module synchronizes or triggers OCx 11000 = CMP1 module synchronizes or triggers OCx 10111 = Reserved 10110 = Reserved 10101 = Reserved 10100 = Reserved 10011 = IC4 input capture event synchronizes or triggers OCx 10010 = IC3 input capture event synchronizes or triggers OCx 10001 = IC2 input capture event synchronizes or triggers OCx 10000 = IC1 input capture event synchronizes or triggers OCx 01111 = Timer5 synchronizes or triggers OCx 01110 = Timer4 synchronizes or triggers OCx 01101 = Timer3 synchronizes or triggers OCx 01100 = Timer2 synchronizes or triggers OCx (default) 01011 = Timer1 synchronizes or triggers OCx 01010 = PTGOx synchronizes or triggers OCx(3) 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = OC4 module synchronizes or triggers OCx(1,2) 00011 = OC3 module synchronizes or triggers OCx(1,2) 00010 = OC2 module synchronizes or triggers OCx(1,2) 00001 = OC1 module synchronizes or triggers OCx(1,2) 00000 = No Sync or Trigger source for OCx
Note 1: 2:
3:
Do not use the OCx module as its own Synchronization or Trigger source.
When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.
Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. PTGO0 = OC1 PTGO1 = OC2 PTGO2 = OC3 PTGO3 = OC4
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16.0 HIGH-SPEED PWM MODULE (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "High-Speed PWM" (www.microchip.com/DS70645) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The
dsPIC33EPXXXMC20X/50X
and
PIC24EPXXXMC20X devices support a dedicated
Pulse-Width Modulation (PWM) module with up to
six outputs.
The high-speed PWMx module consists of the following major features:
· Three PWM Generators
· Two PWM Outputs per PWM Generator · Individual Period and Duty Cycle for Each PWM Pair · Duty Cycle, Dead Time, Phase Shift and Frequency
Resolution of TCY/2 (7.14 ns at FCY = 70 MHz) · Independent Fault and Current-Limit Inputs for
Six PWM Outputs · Redundant Output · Center-Aligned PWM mode · Output Override Control · Chop mode (also known as Gated mode)
· Special Event Trigger · Prescaler for Input Clock · PWMxL and PWMxH Output Pin Swapping · Independent PWM Frequency, Duty Cycle and
Phase-Shift Changes for Each PWM Generator
· Dead-Time Compensation · Enhanced Leading-Edge Blanking (LEB)
Functionality · Frequency Resolution Enhancement · PWM Capture Functionality
Note:
In Edge-Aligned PWM mode, the duty cycle, dead time, phase shift and frequency resolution are 7.14 ns.
The high-speed PWMx module contains up to three PWM generators. Each PWM generator provides two PWM outputs: PWMxH and PWMxL. The master time base generator provides a synchronous signal as a common time base to synchronize the various PWM outputs. The individual PWM outputs are available on the output pins of the device. The input Fault signals and current-limit signals, when enabled, can monitor and protect the system by placing the PWM outputs into a known "safe" state.
Each PWMx can generate a trigger to the ADC module to sample the analog signal at a specific instance during the PWM period. In addition, the high-speed PWMx module also generates a Special Event Trigger to the ADC module based on either of the two master time bases.
The high-speed PWMx module can synchronize itself with an external signal or can act as a synchronizing source to any external device. The SYNCI1 input pin that utilizes PPS, can synchronize the high-speed PWMx module with an external signal. The SYNCO1 pin is an output pin that provides a synchronous signal to an external device.
Figure 16-1 illustrates an architectural overview of the high-speed PWMx module and its interconnection with the CPU and other peripherals.
16.1 PWM Faults
The PWMx module incorporates multiple external Fault inputs to include FLT1 and FLT2 which are remappable using the PPS feature, FLT3 and FLT4 which are available only on the larger 44-pin and 64-pin packages, and FLT32 which has been implemented with Class B safety features, and is available on a fixed pin on all dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
These Faults provide a safe and reliable way to safely shut down the PWM outputs when the Fault input is asserted.
16.1.1 PWM FAULTS AT RESET
During any Reset event, the PWMx module maintains ownership of the Class B Fault, FLT32. At Reset, this Fault is enabled in Latched mode to ensure the fail-safe power-up of the application. The application software must clear the PWM Fault before enabling the highspeed motor control PWMx module. To clear the Fault condition, the FLT32 pin must first be pulled low externally or the internal pull-down resistor in the CNPDx register can be enabled.
Note:
The Fault mode may be changed using the FLTMOD[1:0] bits (FCLCON[1:0]), regardless of the state of FLT32.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
16.1.2 WRITE-PROTECTED REGISTERS
On dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices, write protection is implemented for the IOCONx and FCLCONx registers. The write protection feature prevents any inadvertent writes to these registers. This protection feature can be controlled by the PWMLOCK Configuration bit (FOSCSEL[6]). The default state of the write protection feature is enabled (PWMLOCK = 1). The write protection feature can be disabled by configuring, PWMLOCK = 0.
To gain write access to these locked registers, the user application must write two consecutive values of (0xABCD and 0x4321) to the PWMKEY register to perform the unlock operation. The write access to the IOCONx or FCLCONx registers must be the next SFR access following the unlock process. There can be no other SFR accesses during the unlock process and subsequent write access. To write to both the IOCONx and FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in Example 16-1.
EXAMPLE 16-1: PWMx WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; FLT32 pin must be pulled low externally in order to clear and disable the fault ; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd,w10 mov #0x4321,w11 mov #0x0000,w0 mov w10, PWMKEY mov w11, PWMKEY mov w0,FCLCON1
; Load first unlock key to w10 register ; Load second unlock key to w11 register ; Load desired value of FCLCON1 register in w0 ; Write first unlock key to PWMKEY register ; Write second unlock key to PWMKEY register ; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register ; Writing to IOCON1 register requires unlock sequence
mov #0xabcd,w10 mov #0x4321,w11 mov #0xF000,w0 mov w10, PWMKEY mov w11, PWMKEY mov w0,IOCON1
; Load first unlock key to w10 register ; Load second unlock key to w11 register ; Load desired value of IOCON1 register in w0 ; Write first unlock key to PWMKEY register ; Write second unlock key to PWMKEY register ; Write desired value to IOCON1 register
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FIGURE 16-1:
HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW
FOSC
Data Bus Master Time Base
SYNCI1
PWM1 Interrupt(1)
CPU
PWM2 Interrupt(1)
PWM3 Interrupt(1)
Primary Trigger ADC Module Primary Special
Event Trigger
Synchronization Signal
PWM Generator 1
Fault, Current-Limit and Dead-Time Compensation Synchronization Signal
PWM Generator 2
Fault, Current-Limit and Dead-Time Compensation Synchronization Signal
PWM Generator 3
Fault, Current-Limit and Dead-Time Compensation
SYNCO1 PWM1H PWM1L
PWM2H PWM2L
PWM3H PWM3L FLT1-FLT4, FLT32 DTCMP1-DTCMP3
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the given PWM generator. Refer to "High-Speed PWM" (www.microchip.com/DS70645) in the "dsPIC33/PIC24 Family Reference Manual" for more information.
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FIGURE 16-2:
HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM
FOSC PTCON, PTCON2
Module Control and Timing
PWMKEY
IOCONx and FCLCONx Unlock Register
SYNCI1
PTPER
SEVTCMP
Special Event Compare Trigger
Comparator
Comparator
Master Time Base Counter
Special Event Postscaler
PTG Trigger Input Special Event Trigger
PTG Trigger Input
PMTMR
Clock Prescaler
Primary Master Time Base
MDC
Master Duty Cycle Register
SYNCO1
16-Bit Data Bus Synchronization
Master Duty Cycle Master Period
PDCx MUX Comparator
PTMRx PHASEx PTG Trigger
Input
PWMCONx, AUXCONx
PWM Generator 1
PWMCAPx ADC Trigger
Comparator
TRIGx
PWM Output Mode Control Logic
User Override Logic
Current-Limit Override Logic
Fault Override Logic
Interrupt Logic(1)
Fault and Current-Limit
Logic
Dead-Time Logic
Pin Control Logic
TRGCONx
FCLCONx
IOCONx
ALTDTRx
LEBCONx, LEBDLYx
DTRx
PWM1H PWM1L
FLTx DTCMP1
Synchronization Master Duty Cycle
Master Period
PWM Generator 2 and PWM Generator 3
PWMxH PWMxL FLTx DTCMPx
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the given PWM generator. Refer to "High-Speed PWM" (www.microchip.com/DS70645) in the "dsPIC33/PIC24 Family Reference Manual" for more information.
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16.2 PWM Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
16.2.1 KEY RESOURCES
· "High-Speed PWM" (www.microchip.com/ DS70645) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
2011-2020 Microchip Technology Inc.
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16.3 PWMx Control Registers
REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER
R/W-0
U-0
R/W-0
HS/HC-0
R/W-0
R/W-0
PTEN
--
PTSIDL
SESTAT
SEIEN
EIPU(1)
bit 15
R/W-0
R/W-0
SYNCPOL(1) SYNCOEN(1)
bit 8
R/W-0 SYNCEN(1)
bit 7
R/W-0
R/W-0
SYNCSRC2(1) SYNCSRC1(1)
R/W-0
R/W-0
R/W-0
SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1)
R/W-0 SEVTPS1(1)
R/W-0 SEVTPS0(1)
bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit W = Writable bit `1' = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7
PTEN: PWMx Module Enable bit
1 = PWMx module is enabled 0 = PWMx module is disabled
Unimplemented: Read as `0'
PTSIDL: PWMx Time Base Stop in Idle Mode bit
1 = PWMx time base halts in CPU Idle mode 0 = PWMx time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending 0 = Special event interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled 0 = Special event interrupt is disabled EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWMx cycle boundaries SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCI1/SYNCO1 polarity is inverted (active-low) 0 = SYNCI1/SYNCO1 is active-high SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO1 output is enabled 0 = SYNCO1 output is disabled SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled
Note 1: 2:
These bits should only be changed when PTEN = 0. In addition, when using the SYNCI1 feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal.
See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for information on this selection.
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REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)
bit 6-4 bit 3-0
SYNCSRC[2:0]: Synchronous Source Selection bits(1)
111 = Reserved · · · 100 = Reserved 011 = PTGO17(2) 010 = PTGO16(2) 001 = Reserved 000 = SYNCI1 input from PPS
SEVTPS[3:0]: PWMx Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event · · · 0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event
Note 1: 2:
These bits should only be changed when PTEN = 0. In addition, when using the SYNCI1 feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal.
See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for information on this selection.
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REGISTER 16-2: PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
--
--
PCLKDIV[2:0](1)
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-3 bit 2-0
Unimplemented: Read as `0'
PCLKDIV[2:0]: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved 110 = Divide-by-64 101 = Divide-by-32 100 = Divide-by-16 011 = Divide-by-8 010 = Divide-by-4 001 = Divide-by-2 000 = Divide-by-1, maximum PWMx timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.
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REGISTER 16-3: PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER
R/W-1 bit 15
R/W-1
R/W-1
R/W-1
R/W-1
PTPER[15:8]
R/W-1
R/W-1
R/W-1 bit 8
R/W-1 bit 7
R/W-1
R/W-1
R/W-1
R/W-1
PTPER[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTPER[15:0]: Primary Master Time Base (PMTMR) Period Value bits
REGISTER 16-4: SEVTCMP: PWMx PRIMARY SPECIAL EVENT COMPARE REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
SEVTCMP[15:0]: Special Event Compare Count Value bits
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REGISTER 16-5: CHOP: PWMx CHOP CLOCK GENERATOR REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
CHPCLKEN
--
--
--
--
--
bit 15
R/W-0
R/W-0
CHOPCLK[9:8]
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
CHOPCLK[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14-10 bit 9-0
CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled 0 = Chop clock generator is disabled
Unimplemented: Read as `0'
CHOPCLK[9:0]: Chop Clock Divider bits
The frequency of the chop clock signal is given by the following expression: Chop Frequency = (FP/PCLKDIV[2:0])/(CHOPCLK[9:0] + 1)
REGISTER 16-6: MDC: PWMx MASTER DUTY CYCLE REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
MDC[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
MDC[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
MDC[15:0]: PWMx Master Duty Cycle Value bits
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REGISTER 16-7: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0 FLTSTAT(1)
bit 15
HS/HC-0 CLSTAT(1)
HS/HC-0 TRGSTAT(6)
R/W-0 FLTIEN
R/W-0 CLIEN
R/W-0 TRGIEN(6)
R/W-0 ITB(2)
R/W-0 MDCS(2)
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
DTC1
DTC0
DTCP(3)
--
MTBS
CAM(2,4)
XPRES(5)
IUE(2)
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit W = Writable bit `1' = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending 0 = No Fault interrupt is pending This bit is cleared by setting FLTIEN = 0. CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending This bit is cleared by setting CLIEN = 0. TRGSTAT: Trigger Interrupt Status bit(6)
1 = Trigger interrupt is pending 0 = No trigger interrupt is pending This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled 0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared TRGIEN: Trigger Interrupt Enable bit(6)
1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared ITB: Independent Time Base Mode bit(2)
1 = PHASEx register provides time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator MDCS: Master Duty Cycle Register Select bit(2)
1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx register provides duty cycle information for this PWM generator
Note 1: 2: 3: 4:
5:
6:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
These bits should not be changed after the PWMx is enabled (PTEN = 1).
DTC[1:0] = 11 for DTCP to be effective; otherwise, DTCP is ignored. The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be `1' and the CLMOD bit in the FCLCONx register must be `0'. When the local time base counter matches the value specified by the user in the TRIGx register, an ADC trigger signal is generated. Also, see the TRIGx register description.
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REGISTER 16-7: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
bit 7-6 bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
DTC[1:0]: Dead-Time Control bits
11 = Dead-Time Compensation mode 10 = Dead-time function is disabled 01 = Negative dead time is actively applied for Complementary Output mode 00 = Positive dead time is actively applied except for Push-Pull mode DTCP: Dead-Time Compensation Polarity bit(3)
When Set to `1': If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened. If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
When Set to `0': If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened. If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.
Unimplemented: Read as `0'
MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and as the clock source for the PWM generation logic (if secondary time base is available)
0 = PWM generator uses the primary master time base for synchronization and as the clock source for the PWM generation logic
CAM: Center-Aligned Mode Enable bit(2,4)
1 = Center-Aligned mode is enabled 0 = Edge-Aligned mode is enabled XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode
0 = External pins do not affect PWMx time base IUE: Immediate Update Enable bit(2)
1 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are immediate 0 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are synchronized to the
PWMx period boundary
Note 1: 2: 3: 4:
5:
6:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
These bits should not be changed after the PWMx is enabled (PTEN = 1). DTC[1:0] = 11 for DTCP to be effective; otherwise, DTCP is ignored.
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be `1' and the CLMOD bit in the FCLCONx register must be `0'.
When the local time base counter matches the value specified by the user in the TRIGx register, an ADC trigger signal is generated. Also, see the TRIGx register description.
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REGISTER 16-8: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PDCx[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PDCx[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PDCx[15:0]: PWMx Generator # Duty Cycle Value bits
REGISTER 16-9: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PHASEx[15:0]: PWMx Phase-Shift Value or Independent Time Base Period for the PWM Generator bits
Note 1: If ITB (PWMCONx[9]) = 0, the following applies based on the mode of operation: Complementary, Redundant and Push-Pull Output mode (PMOD[1:0] (IOCON[11:10]) = 00, 01 or 10), PHASEx[15:0] = Phase-shift value for PWMxH and PWMxL outputs
2: If ITB (PWMCONx[9]) = 1, the following applies based on the mode of operation: Complementary, Redundant and Push-Pull Output mode (PMOD[1:0] (IOCONx[11:10]) = 00, 01 or 10), PHASEx[15:0] = Independent time base period value for PWMxH and PWMxL
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REGISTER 16-10: DTRx: PWMx DEAD-TIME REGISTER
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
--
DTRx[13:8]
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
DTRx[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-0
Unimplemented: Read as `0' DTRx[13:0]: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 16-11: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
--
--
ALTDTRx[13:8]
bit 15
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-0
Unimplemented: Read as `0' ALTDTRx[13:0]: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
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REGISTER 16-12: TRGCONx: PWMx TRIGGER CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
TRGDIV[3:0]
--
--
--
--
bit 15
bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
TRGSTRT[5:0](1)
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-6 bit 5-0
TRGDIV[3:0]: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event
Unimplemented: Read as `0'
TRGSTRT[5:0]: Trigger Postscaler Start Enable Select bits(1)
111111 = Waits 63 PWM cycles before generating the first trigger event after the module is enabled ·
·
·
000010 = Waits 2 PWM cycles before generating the first trigger event after the module is enabled 000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Waits 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1: The secondary PWM generator cannot generate PWMx trigger interrupts.
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REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER(2,3)
R/W-1 PENH bit 15
R/W-1 PENL
R/W-0 POLH
R/W-0 POLL
R/W-0 PMOD1(1)
R/W-0 PMOD0(1)
R/W-0 OVRENH
R/W-0 OVRENL
bit 8
R/W-0 OVRDAT1 bit 7
R/W-0 OVRDAT0
R/W-0 FLTDAT1
R/W-0 FLTDAT0
R/W-0 CLDAT1
R/W-0 CLDAT0
R/W-0 SWAP
R/W-0 OSYNC
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11-10
bit 9 bit 8 bit 7-6 bit 5-4 bit 3-2
PENH: PWMxH Output Pin Ownership bit
1 = PWMx module controls PWMxH pin 0 = GPIO module controls PWMxH pin
PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls PWMxL pin 0 = GPIO module controls PWMxL pin
POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low 0 = PWMxH pin is active-high
POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low 0 = PWMxL pin is active-high PMOD[1:0]: PWMx # I/O Pin Mode bits(1)
11 = Reserved; do not use 10 = PWMx I/O pin pair is in the Push-Pull Output mode 01 = PWMx I/O pin pair is in the Redundant Output mode 00 = PWMx I/O pin pair is in the Complementary Output mode
OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT[1] controls output on PWMxH pin 0 = PWMx generator controls PWMxH pin
OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT[0] controls output on PWMxL pin 0 = PWMx generator controls PWMxL pin
OVRDAT[1:0]: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT[1]. If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT[0].
FLTDAT[1:0]: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits
If Fault is active, PWMxH is driven to the state specified by FLTDAT[1]. If Fault is active, PWMxL is driven to the state specified by FLTDAT[0].
CLDAT[1:0]: Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits
If current-limit is active, PWMxH is driven to the state specified by CLDAT[1]. If current-limit is active, PWMxL is driven to the state specified by CLDAT[0].
Note 1: 2:
3:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
If the PWMLOCK Configuration bit (FOSCSEL[6]) is a `1', the IOCONx register can only be written after the unlock sequence has been executed.
The OSYNC bit (IOCON[0]) must be set to `1' prior to changing the state of the SWAP bit (IOCON[1]), else the SWAP function will attempt to occur in the middle of the PWM cycle and unpredictable results may occur.
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REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER(2,3) (CONTINUED)
bit 1
SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0
OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT[1:0] bits are synchronized to the PWMx time base. In Edge-Aligned mode, output overrides are updated when the local time base equals zero. In Center-Aligned mode,
output overrides are updated when the local time base matches the PHASEx register.
0 = Output overrides via the OVDDAT[1:0] bits occur on the next CPU clock boundary
Note 1: 2:
3:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
If the PWMLOCK Configuration bit (FOSCSEL[6]) is a `1', the IOCONx register can only be written after the unlock sequence has been executed.
The OSYNC bit (IOCON[0]) must be set to `1' prior to changing the state of the SWAP bit (IOCON[1]), else the SWAP function will attempt to occur in the middle of the PWM cycle and unpredictable results may occur.
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REGISTER 16-14: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
TRGCMP[15:0]: Trigger Control Value bits
When the primary PWMx functions in local time base, this register contains the compare values that can trigger the ADC module.
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REGISTER 16-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1)
U-0 -- bit 15
R/W-0 CLSRC4
R/W-0 CLSRC3
R/W-0 CLSRC2
R/W-0 CLSRC1
R/W-0 CLSRC0
R/W-0 CLPOL(2)
R/W-0 CLMOD
bit 8
R/W-1 FLTSRC4 bit 7
R/W-1 FLTSRC3
R/W-1 FLTSRC2
R/W-1 FLTSRC1
R/W-1 FLTSRC0
R/W-0 FLTPOL(2)
R/W-0 FLTMOD1
R/W-0 FLTMOD0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-10
bit 9 bit 8
Unimplemented: Read as `0'
CLSRC[4:0]: Current-Limit Control Signal Source Select for PWM Generator # bits
11111 = Fault 32 11110 = Reserved · · · 01100 = Reserved 01011 = Comparator 4 01010 = Op Amp/Comparator 3 01001 = Op Amp/Comparator 2 01000 = Op Amp/Comparator 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 (default)
CLPOL: Current-Limit Polarity for PWM Generator # bit(2)
1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high
CLMOD: Current-Limit Mode Enable for PWM Generator # bit
1 = Current-Limit mode is enabled 0 = Current-Limit mode is disabled
Note 1: 2:
If the PWMLOCK Configuration bit (FOSCSEL[6]) is a `1', the IOCONx register can only be written after the unlock sequence has been executed.
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.
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REGISTER 16-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1)
bit 7-3
bit 2 bit 1-0
FLTSRC[4:0]: Fault Control Signal Source Select for PWM Generator # bits
11111 = Fault 32 (default) 11110 = Reserved ·
·
· 01100 = Reserved 01011 = Comparator 4 01010 = Op Amp/Comparator 3 01001 = Op Amp/Comparator 2 01000 = Op Amp/Comparator 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1
FLTPOL: Fault Polarity for PWM Generator # bit(2)
1 = The selected Fault source is active-low 0 = The selected Fault source is active-high
FLTMOD[1:0]: Fault Mode for PWM Generator # bits
11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDATx values (cycle) 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDATx values (latched condition)
Note 1: 2:
If the PWMLOCK Configuration bit (FOSCSEL[6]) is a `1', the IOCONx register can only be written after the unlock sequence has been executed.
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.
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REGISTER 16-16: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER
R/W-0 PHR bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
PHF
PLR
PLF
FLTLEBEN CLLEBEN
--
U-0 --
bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
BCH(1)
BCL(1)
BPHH
BPHL
BPLH
BPLL
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxH
PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxH
PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxL
PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxL
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected Fault input 0 = Leading-Edge Blanking is not applied to selected Fault input
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input 0 = Leading-Edge Blanking is not applied to selected current-limit input
Unimplemented: Read as `0' BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high 0 = No blanking when selected blanking signal is high BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low 0 = No blanking when selected blanking signal is low
BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high 0 = No blanking when PWMxH output is high
BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low 0 = No blanking when PWMxH output is low
BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high 0 = No blanking when PWMxL output is high
BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low 0 = No blanking when PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-17: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER
U-0 -- bit 15
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
LEB[11:8]
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
LEB[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12 bit 11-0
Unimplemented: Read as `0' LEB[11:0]: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-18: AUXCONx: PWMx AUXILIARY CONTROL REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
--
BLANKSEL[3:0]
bit 15
R/W-0 bit 8
U-0 -- bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12 bit 11-8
bit 7-6 bit 5-2
bit 1 bit 0
Unimplemented: Read as `0'
BLANKSEL[3:0]: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the BCH and BCL bits in the LEBCONx register). 1001 = Reserved · · · 0100 = Reserved 0011 = PWM3H selected as state blank source 0010 = PWM2H selected as state blank source 0001 = PWM1H selected as state blank source 0000 = No state blanking
Unimplemented: Read as `0'
CHOPSEL[3:0]: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (CHOP) the selected PWMx outputs. 1001 = Reserved · · · 0100 = Reserved 0011 = PWM3H selected as CHOP clock source 0010 = PWM2H selected as CHOP clock source 0001 = PWM1H selected as CHOP clock source 0000 = Chop clock generator selected as CHOP clock source
CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled
CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled
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NOTES:
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
17.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Quadrature Encoder Interface (QEI)" (www.microchip.com/ DS70000601) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
This chapter describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data.
The operational features of the QEI module include:
· 32-Bit Position Counter · 32-Bit Index Pulse Counter · 32-Bit Interval Timer · 16-Bit Velocity Counter · 32-Bit Position Initialization/Capture/Compare
High register · 32-Bit Position Compare Low register · x4 Quadrature Count mode · External Up/Down Count mode · External Gated Count mode · External Gated Timer mode · Internal Timer mode
Figure 17-1 illustrates the QEI block diagram.
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FIGURE 17-1:
QEI BLOCK DIAGRAM
FLTREN
GATEN
HOMEx INDXx QEBx
Digital Filter
FHOMEx
QFDIV
FP
FINDXx
Quadrature
Decoder Logic
COUNT DIR
COUNT EXTCNT DIVCLK
DIR_GATE
DIR
DIR_GATE
1'b0
CCM
QEAx
EXTCNT
CNTPOL
DIR_GATE
CNTCMPx
PCHGE PCLLE
OUTFNC
PCLLE PCHGE
FP
INTDIV
FINDXx CNT_DIR
(INDX1CNT) 32-Bit Index Counter Register
INDX1CNTH INDX1CNTL
DIVCLK
COUNT_EN
32-Bit Interval Timer Register
(INT1TMR)
CNT_DIR
PCLEQ
32-Bit Less Than or Equal Comparator
PCLLE
32-Bit Less Than or Equal Compare Register
(QEI1LEC)
(POS1CNT) 32-Bit Position Counter Register
COUNT_EN
COUNT_EN CNT_DIR
POS1CNTH POS1CNTL
1 COUNT_EN
0
CNT_DIR
PCHEQ
32-Bit Greater Than or Equal Comparator
PCHGE
32-Bit Greater Than or Equal Compare Register (QEI1GEC)(1)
16-Bit Index Counter Hold Register
(INDX1HLD)
32-Bit Interval Timer
Hold Register (INT1HLD)
16-Bit Velocity
Counter Register (VEL1CNT)
16-Bit Position Counter Hold Register
(POS1HLD)
QCAPEN
32-Bit Initialization and Capture Register (QEI1IC)(1)
2011-2020 Microchip Technology Inc.
Data Bus Note 1: These registers map to the same memory location.
Data Bus
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
17.1 QEI Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
17.1.1 KEY RESOURCES
· "Quadrature Encoder Interface" (www.microchip.com/DS70000601) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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17.2 QEI Control Registers
REGISTER 17-1: QEI1CON: QEI1 CONTROL REGISTER
R/W-0 QEIEN bit 15
U-0
R/W-0
R/W-0
R/W-0
--
QEISIDL PIMOD2(1) PIMOD1(1)
R/W-0 PIMOD0(1)
R/W-0 IMV1(2)
R/W-0 IMV0(2)
bit 8
U-0 -- bit 7
R/W-0 INTDIV2(3)
R/W-0
R/W-0
INTDIV1(3) INTDIV0(3)
R/W-0 CNTPOL
R/W-0 GATEN
R/W-0 CCM1
R/W-0 CCM0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-10
bit 9 bit 8 bit 7
QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled 0 = Module counters are disabled, but SFRs can be read or written to
Unimplemented: Read as `0'
QEISIDL: QEI Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode PIMOD[2:0]: Position Counter Initialization Mode Select bits(1)
111 = Reserved 110 = Modulo Count mode for position counter 101 = Resets the position counter when the position counter equals QEI1GEC register 100 = Second index event after home event initializes position counter with contents of QEI1IC register 011 = First index event after home event initializes position counter with contents of QEI1IC register 010 = Next index input event initializes the position counter with contents of QEI1IC register 001 = Every index input event resets the position counter 000 = Index input event does not affect position counter IMV1: Index Match Value for Phase B bit(2)
1 = Phase B match occurs when QEB = 1 0 = Phase B match occurs when QEB = 0 IMV0: Index Match Value for Phase A bit(2)
1 = Phase A match occurs when QEA = 1 0 = Phase A match occurs when QEA = 0
Unimplemented: Read as `0'
Note 1: 2:
3:
When CCM[1:0] = 10 or 11, all of the QEI counters operate as timers and the PIMOD[2:0] bits are ignored.
When CCM[1:0] = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
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REGISTER 17-1: QEI1CON: QEI1 CONTROL REGISTER (CONTINUED)
bit 6-4
bit 3 bit 2 bit 1-0
INTDIV[2:0]: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter), velocity counter and index counter internal clock divider select)(3)
111 = 1:128 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value
CNTPOL: Position and Index Counter/Timer Direction Select bit
1 = Counter direction is negative unless modified by external up/down signal 0 = Counter direction is positive unless modified by external up/down signal
GATEN: External Count Gate Enable bit
1 = External gate signal controls position counter operation 0 = External gate signal does not affect position counter/timer operation
CCM[1:0]: Counter Control Mode Selection bits
11 = Internal Timer mode with optional external count is selected 10 = External clock count with optional external count is selected 01 = External clock count with external up/down direction is selected 00 = Quadrature Encoder Interface (x4 mode) Count mode is selected
Note 1: 2:
3:
When CCM[1:0] = 10 or 11, all of the QEI counters operate as timers and the PIMOD[2:0] bits are ignored.
When CCM[1:0] = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
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REGISTER 17-2: QEI1IOC: QEI1 I/O CONTROL REGISTER
R/W-0 QCAPEN bit 15
R/W-0 FLTREN
R/W-0 QFDIV2
R/W-0 QFDIV1
R/W-0 QFDIV0
R/W-0 OUTFNC1
R/W-0 OUTFNC0
R/W-0 SWPAB
bit 8
R/W-0 HOMPOL bit 7
R/W-0 IDXPOL
R/W-0 QEBPOL
R/W-0 QEAPOL
R-x HOME
R-x INDEX
R-x QEB
R-x QEA
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13-11
bit 10-9
bit 8 bit 7 bit 6 bit 5 bit 4 bit 3
QCAPEN: QEI Position Counter Input Capture Enable bit
1 = Index match event triggers a position capture event 0 = Index match event does not trigger a position capture event
FLTREN: QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit
1 = Input pin digital filter is enabled 0 = Input pin digital filter is disabled (bypassed)
QFDIV[2:0]: QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits
111 = 1:128 clock divide 110 = 1:64 clock divide 101 = 1:32 clock divide 100 = 1:16 clock divide 011 = 1:8 clock divide 010 = 1:4 clock divide 001 = 1:2 clock divide 000 = 1:1 clock divide
OUTFNC[1:0]: QEI Module Output Function Mode Select bits
11 = The CTNCMPx pin goes high when QEI1LEC POS1CNT QEI1GEC 10 = The CTNCMPx pin goes high when POS1CNT QEI1LEC 01 = The CTNCMPx pin goes high when POS1CNT QEI1GEC 00 = Output is disabled
SWPAB: Swap QEA and QEB Inputs bit
1 = QEAx and QEBx are swapped prior to quadrature decoder logic 0 = QEAx and QEBx are not swapped
HOMPOL: HOMEx Input Polarity Select bit
1 = Input is inverted 0 = Input is not inverted
IDXPOL: INDXx Input Polarity Select bit
1 = Input is inverted 0 = Input is not inverted
QEBPOL: QEBx Input Polarity Select bit
1 = Input is inverted 0 = Input is not inverted
QEAPOL: QEAx Input Polarity Select bit
1 = Input is inverted 0 = Input is not inverted
HOME: Status of HOMEx Input Pin After Polarity Control bit
1 = Pin is at logic `1' 0 = Pin is at logic `0'
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 17-2: QEI1IOC: QEI1 I/O CONTROL REGISTER (CONTINUED)
bit 2
INDEX: Status of INDXx Input Pin After Polarity Control bit
1 = Pin is at logic `1' 0 = Pin is at logic `0'
bit 1
QEB: Status of QEBx Input Pin After Polarity Control And SWPAB Pin Swapping bit
1 = Pin is at logic `1' 0 = Pin is at logic `0'
bit 0
QEA: Status of QEAx Input Pin After Polarity Control And SWPAB Pin Swapping bit
1 = Pin is at logic `1' 0 = Pin is at logic `0'
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REGISTER 17-3: QEI1STAT: QEI1 STATUS REGISTER
U-0 -- bit 15
U-0
HS/R/C-0
R/W-0
HS/R/C-0
R/W-0
HS/R/C-0
R/W-0
--
PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN
bit 8
HS/R/C-0 PCIIRQ(1)
bit 7
R/W-0 PCIIEN
HS/R/C-0
R/W-0
HS/R/C-0
VELOVIRQ VELOVIEN HOMIRQ
R/W-0 HOMIEN
HS/R/C-0 IDXIRQ
R/W-0 IDXIEN
bit 0
Legend: R = Readable bit -n = Value at POR
HS = Hardware Settable bit W = Writable bit `1' = Bit is set
C = Clearable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3
Unimplemented: Read as `0'
PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit
1 = POS1CNT QEI1GEC 0 = POS1CNT < QEI1GEC
PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled
PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit
1 = POS1CNT QEI1LEC 0 = POS1CNT > QEI1LEC
PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled
POSOVIRQ: Position Counter Overflow Status bit
1 = Overflow has occurred 0 = No overflow has occurred
POSOVIEN: Position Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit(1)
1 = POS1CNT was reinitialized 0 = POS1CNT was not reinitialized
PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled
VELOVIRQ: Velocity Counter Overflow Status bit
1 = Overflow has occurred 0 = No overflow has not occurred
VELOVIEN: Velocity Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled
HOMIRQ: Status Flag for Home Event Status bit
1 = Home event has occurred 0 = No Home event has occurred
Note 1: This status bit is only applicable to PIMOD[2:0] modes, `011' and `100'.
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REGISTER 17-3: QEI1STAT: QEI1 STATUS REGISTER (CONTINUED)
bit 2
HOMIEN: Home Input Event Interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled
bit 1
IDXIRQ: Status Flag for Index Event Status bit
1 = Index event has occurred 0 = No Index event has occurred
bit 0
IDXIEN: Index Input Event Interrupt Enable bit
1 = Interrupt is enabled 0 = Interrupt is disabled
Note 1: This status bit is only applicable to PIMOD[2:0] modes, `011' and `100'.
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REGISTER 17-4: POS1CNTH: POSITION COUNTER 1 HIGH WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
POSCNT[31:16]: High Word Used to Form 32-Bit Position Counter Register (POS1CNT) bits
REGISTER 17-5: POS1CNTL: POSITION COUNTER 1 LOW WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
POSCNT[15:0]: Low Word Used to Form 32-Bit Position Counter Register (POS1CNT) bits
REGISTER 17-6: POS1HLD: POSITION COUNTER 1 HOLD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
POSHLD[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
POSHLD[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
POSHLD[15:0]: Hold Register for Reading and Writing POS1CNTH bits
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 17-7: VEL1CNT: VELOCITY COUNTER 1 REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
VELCNT[15:0]: Velocity Counter bits
REGISTER 17-8: INDX1CNTH: INDEX COUNTER 1 HIGH WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INDXCNT[31:16]: High Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits
REGISTER 17-9: INDX1CNTL: INDEX COUNTER 1 LOW WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INDXCNT[15:0]: Low Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits
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REGISTER 17-10: INDX1HLD: INDEX COUNTER 1 HOLD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INDXHLD[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INDXHLD[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INDXHLD[15:0]: Hold Register for Reading and Writing INDX1CNTH bits
REGISTER 17-11: QEI1ICH: QEI1 INITIALIZATION/CAPTURE HIGH WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
QEIIC[31:16]: High Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits
REGISTER 17-12: QEI1ICL: QEI1 INITIALIZATION/CAPTURE LOW WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
QEIIC[15:0]: Low Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits
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REGISTER 17-13: QEI1LECH: QEI1 LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
QEILEC[31:16]: High Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits
REGISTER 17-14: QEI1LECL: QEI1 LESS THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
QEILEC[15:0]: Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits
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REGISTER 17-15: QEI1GECH: QEI1 GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC[31:24]
bit 15
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
QEIGEC[31:16]: High Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits
REGISTER 17-16: QEI1GECL: QEI1 GREATER THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC[15:8]
bit 15
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
QEIGEC[15:0]: Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits
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REGISTER 17-17: INT1TMRH: INTERVAL 1 TIMER HIGH WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INTTMR[31:16]: High Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits
REGISTER 17-18: INT1TMRL: INTERVAL 1 TIMER LOW WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INTTMR[15:0]: Low Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits
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REGISTER 17-19: INT1HLDH: INTERVAL 1 TIMER HOLD HIGH WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INTHLD[31:16]: Hold Register for Reading and Writing INT1TMRH bits
REGISTER 17-20: INT1HLDL: INTERVAL 1 TIMER HOLD LOW WORD REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
INTHLD[15:0]: Hold Register for Reading and Writing INT1TMRL bits
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18.0 SERIAL PERIPHERAL INTERFACE (SPI)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Serial Peripheral Interface (SPI)" (www.microchip.com/ DS70005185) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The SPI module is a synchronous serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, ADC Converters, etc. The SPI module is compatible with Motorola® SPI and SIOP interfaces.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X device family offers two SPI modules on a single device. These modules, which are designated as SPI1 and SPI2, are functionally identical. Each SPI module includes an eight-word FIFO buffer and allows DMA bus connections. When using the SPI module with DMA, FIFO operation can be disabled.
Note:
In this section, the SPI modules are referred to together as SPIx, or separately as SPI1 and SPI2. Special Function Registers follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 and SPI2 modules.
The SPI1 module uses dedicated pins which allow for a higher speed when using SPI1. The SPI2 module takes advantage of the Peripheral Pin Select (PPS) feature to allow for greater flexibility in pin configuration of the SPI2 module, but results in a lower maximum speed for SPI2. See Section 30.0 "Electrical Characteristics" for more information.
The SPIx serial interface consists of four pins, as follows:
· SDIx: Serial Data Input · SDOx: Serial Data Output · SCKx: Shift Clock Input or Output · SSx/FSYNCx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPIx module can be configured to operate with two, three or four pins. In 3-pin mode, SSx is not used. In 2-pin mode, neither SDOx nor SSx is used.
Figure 18-1 illustrates the block diagram of the SPIx module in Standard and Enhanced modes.
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FIGURE 18-1:
SCKx
SPIx MODULE BLOCK DIAGRAM
SSx/FSYNCx
Sync Control
SDOx
Control Clock
Select Edge
Shift Control
SDIx
bit 0 SPIxSR
Transfer
Transfer
1:1 to 1:8
1:1/4/16/64
Secondary
Primary
FP
Prescaler
Prescaler
SPIxCON1[1:0] SPIxCON1[4:2] Enable Master Clock
8-Level FIFO
8-Level FIFO
Receive Buffer(1) Transmit Buffer(1)
SPIxBUF
Read SPIxBUF
Write SPIxBUF 16
Note 1: In Standard mode, the FIFO is only one level deep.
Internal Data Bus
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18.1 SPI Helpful Tips
1. In Frame mode, if there is a possibility that the master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2[13]) = 1, use a pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on SSx.
Note: This insures that the first frame transmission after initialization is not shifted or corrupted.
2. In Non-Framed Three-Wire mode, (i.e., not using SSx from a master):
a) If CKP (SPIxCON1[6]) = 1, always place a pull-up resistor on SSx.
b) If CKP = 0, always place a pull-down resistor on SSx.
Note:
This will insure that during power-up and initialization the master/slave will not lose Sync due to an errant SCKx transition that would cause the slave to accumulate data shift errors for both transmit and receive appearing as corrupted data.
3. FRMEN (SPIxCON2[15]) = 1 and SSEN (SPIxCON1[7]) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
Note:
Not all third-party devices support Frame mode timing. Refer to the SPIx specifications in Section 30.0 "Electrical Characteristics" for details.
4. In Master mode only, set the SMP bit (SPIxCON1[9]) to a `1' for the fastest SPIx data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1[5]) is set.
To avoid invalid slave read data to the master, the user's master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. It is always advisable to preload the SPIxBUF Transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPIx Shift register and is empty once the data transmission begins.
18.2 SPI Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
18.2.1 KEY RESOURCES
· "Serial Peripheral Interface (SPI)" (www.microchip.com/DS70005185) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
2011-2020 Microchip Technology Inc.
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18.3 SPIx Control Registers
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 SPIEN bit 15
U-0
R/W-0
U-0
--
SPISIDL
--
U-0
R/W-0
--
SPIBEC2
R/W-0 SPIBEC1
R/W-0 SPIBEC0
bit 8
R/W-0 SRMPT bit 7
HS/R/C-0 SPIROV
R/W-0 SRXMPT
R/W-0 SISEL2
R/W-0 SISEL1
R/W-0 SISEL0
HS/HC/R-0 SPITBF
HS/HC/R-0 SPIRBF bit 0
Legend: R = Readable bit -n = Value at POR
C = Clearable bit W = Writable bit `1' = Bit is set
HS = Hardware Settable bit HC = Hardware Clearable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-11 bit 10-8
bit 7 bit 6
bit 5 bit 4-2
SPIEN: SPIx Enable bit
1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables the module
Unimplemented: Read as `0'
SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the module operation when device enters Idle mode 0 = Continues the module operation in Idle mode
Unimplemented: Read as `0'
SPIBEC[2:0]: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode: Number of SPIx transfers that are pending.
Slave mode: Number of SPIx transfers that are unread.
SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and Ready-to-Send or receive the data 0 = SPIx Shift register is not empty
SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user application has not read the previous data in the SPIxBUF register
0 = No overflow has occurred
SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty 0 = RX FIFO is not empty
SISEL[2:0]: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPIxSR and as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete 100 = Interrupt when one data are shifted into the SPIxSR and as a result, the TX FIFO has one open
memory location 011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set) 010 = Interrupt when the SPIx receive buffer is 3/4 or more full 001 = Interrupt when data are available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer are read and as a result, the buffer is empty
(SRXMPT bit is set)
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REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty
Standard Buffer mode: Automatically set in hardware when core writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write operation.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full 0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.
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REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1
U-0 -- bit 15
U-0
U-0
R/W-0
R/W-0
--
--
DISSCK DISSDO
R/W-0 MODE16
R/W-0 SMP
R/W-0 CKE(1)
bit 8
R/W-0 SSEN(2)
bit 7
R/W-0 CKP
R/W-0 MSTEN
R/W-0 SPRE2(3)
R/W-0 SPRE1(3)
R/W-0 SPRE0(3)
R/W-0 PPRE1(3)
R/W-0 PPRE0(3)
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7 bit 6 bit 5
Unimplemented: Read as `0'
DISSCK: Disable SCKx Pin bit (SPIx Master modes only)
1 = Internal SPIx clock is disabled, pin functions as I/O 0 = Internal SPIx clock is enabled
DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode: 1 = Input data are sampled at end of data output time 0 = Input data are sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data change on transition from Active Clock state to Idle Clock state (refer to bit 6) 0 = Serial output data change on transition from Idle Clock state to Active Clock state (refer to bit 6) SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode 0 = SSx pin is not used by the module; pin is controlled by port function
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode 0 = Slave mode
Note 1: 2: 3:
The CKE bit is not used in Framed SPI modes. Program this bit to `0' for Framed SPI modes (FRMEN = 1). This bit must be cleared when FRMEN = 1. Do not set both primary and secondary prescalers to the value of 1:1.
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REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 (CONTINUED)
bit 4-2 bit 1-0
SPRE[2:0]: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 · · · 000 = Secondary prescale 8:1
PPRE[1:0]: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1
Note 1: 2: 3:
The CKE bit is not used in Framed SPI modes. Program this bit to `0' for Framed SPI modes (FRMEN = 1). This bit must be cleared when FRMEN = 1. Do not set both primary and secondary prescalers to the value of 1:1.
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REGISTER 18-3: SPIXCON2: SPIX CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
--
--
--
--
--
FRMDLY
SPIBEN
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-2 bit 1 bit 0
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output) 0 = Framed SPIx support is disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high 0 = Frame Sync pulse is active-low
Unimplemented: Read as `0'
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with first bit clock 0 = Frame Sync pulse precedes first bit clock
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Standard mode)
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19.0 INTER-INTEGRATED CIRCUIT (I2C)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Inter-Integrated Circuit (I2C)" (www.microchip.com/ DS70000195) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
3: There are minimum bit rates of approximately FCY/512. As a result, high processor speeds may not support 100 Kbit/second operation. See timing specifications, IM10 and IM11, and the "Baud Rate Generator" in the "dsPIC33/ PIC24 Family Reference Manual".
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X family of devices contains two Inter-Integrated Circuit (I2C) modules: I2C1 and I2C2.
The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard, with a 16-bit interface.
The I2C module has a 2-pin interface:
· The SCLx pin is clock · The SDAx pin is data
The I2C module offers the following key features:
· I2C Interface Supporting both Master and Slave modes of Operation
· I2C Slave mode Supports 7 and 10-Bit Addressing · I2C Master mode Supports 7 and 10-Bit Addressing · I2C Port allows Bidirectional Transfers between
Master and Slaves · Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control) · I2C Supports Multi-Master Operation, Detects Bus Collision and Arbitrates Accordingly
· Intelligent Platform Management Interface (IPMI) Support
· System Management Bus (SMBus) Support
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 19-1:
I2Cx BLOCK DIAGRAM (X = 1 OR 2)
SCLx/ASCLx SDAx/ASDAx
I2CxRCV
Shift Clock
I2CxRSR LSb
Match Detect
Address Match
Control Logic
I2CxADD
Start and Stop Bit Detect
Start and Stop Bit Generation
Collision Detect
Acknowledge Generation Clock Stretching
I2CxTRN LSb
Shift Clock Reload Control
BRG Down Counter
FP/2
Internal Data Bus
Read
I2CxMSK Write
Write Read
Read
I2CxSTAT I2CxCON
Write
Read Write
Read
Write
Read
I2CxBRG
Write Read
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19.1 I2C Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
19.1.1 KEY RESOURCES
· "Inter-Integrated Circuit (I2C)" (www.microchip.com/DS70000195) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes
· Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
2011-2020 Microchip Technology Inc.
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19.2 I2C Control Registers
REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
U-0
R/W-0
HC/R/W-1
R/W-0
I2CEN
--
I2CSIDL
SCLREL IPMIEN(1)
bit 15
R/W-0 A10M
R/W-0 DISSLW
R/W-0 SMEN
bit 8
R/W-0 GCEN bit 7
R/W-0 STREN
R/W-0 ACKDT
HC/R/W-0 ACKEN
HC/R/W-0 RCEN
HC/R/W-0 PEN
HC/R/W-0 RSEN
HC/R/W-0 SEN bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12
bit 11 bit 10 bit 9 bit 8 bit 7
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C pins are controlled by port functions
Unimplemented: Read as `0'
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write `0' to initiate stretch and write `1' to release clock). Hardware is clear at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave address byte reception. Hardware is clear at the end of every slave data byte reception.
If STREN = 0: Bit is R/S (i.e., software can only write `1' to release clock). Hardware is clear at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave address byte reception. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit(1)
1 = IPMI mode is enabled; all addresses are Acknowledged 0 = IPMI mode disabled
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled 0 = Slew rate control is enabled
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception) 0 = General call address disabled
Note 1: When performing master operations, ensure that the IPMIEN bit is set to `0'.
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REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
is clear at the end of the master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive
data byte.
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop
sequence.
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the
master Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start sequence.
0 = Start condition is not in progress
Note 1: When performing master operations, ensure that the IPMIEN bit is set to `0'.
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REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER
HSC/R-0 HSC/R-0
U-0
U-0
ACKSTAT TRSTAT
--
--
bit 15
U-0
HS/R/C-0
--
BCL
HSC/R-0 GCSTAT
HSC/R-0 ADD10
bit 8
HS/R/C-0 IWCOL bit 7
HS/R/C-0 I2COV
HSC/R-0 D_A
HSC/R/C-0 HSC/R/C-0
P
S
HSC/R-0 R_W
HSC/R-0 RBF
HSC/R-0 TBF bit 0
Legend: R = Readable bit -n = Value at POR
C = Clearable bit W = Writable bit `1' = Bit is set
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13-11 bit 10 bit 9 bit 8
bit 7 bit 6 bit 5 bit 4
ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
1 = NACK received from slave 0 = ACK received from slave Hardware is set or clear at the end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
Unimplemented: Read as `0'
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation 0 = No bus collision detected Hardware is set at detection of a bus collision.
GCSTAT: General Call Status bit
1 = General call address was received 0 = General call address was not received Hardware is set when address matches general call address. Hardware is clear at Stop detection.
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop detection.
IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at a device address match. Hardware is set by reception of a slave byte.
P: Stop bit
1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected.
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REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read Indicates data transfer is output from the slave 0 = Write Indicates data transfer is input to the slave Hardware is set or clear after reception of an I2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads
I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.
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REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
--
--
--
--
--
AMSK[9:8]
bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
AMSK[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-10 bit 9-0
Unimplemented: Read as `0'
AMSK[9:0]: Address Mask Select bits
For 10-Bit Address: 1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position 0 = Disables masking for bit Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK[6:0] only): 1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position 0 = Disables masking for bit Ax + 1; bit match is required in this position
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/DS70000582) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X family of devices contains two UART modules.
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X device family. The UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces.
The module also supports a hardware flow control option with the UxCTS and UxRTS pins, and also includes an IrDA® encoder and decoder.
Note:
Hardware flow control using UxRTS and UxCTS is not available on all pin count devices. See the "Pin Diagrams" section for availability.
The primary features of the UARTx module are:
· Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX Pins
· Even, Odd or No Parity Options (for 8-bit data) · One or Two Stop bits · Hardware Flow Control Option with UxCTS and
UxRTS Pins · Fully Integrated Baud Rate Generator with 16-Bit
Prescaler · Baud Rates Ranging from 4.375 Mbps to 67 bps at
16x mode at 70 MIPS · Baud Rates Ranging from 17.5 Mbps to 267 bps at
4x mode at 70 MIPS · 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer · 4-Deep FIFO Receive Data Buffer
· Parity, Framing and Buffer Overrun Error Detection · Support for 9-bit mode with Address Detect
(9th bit = 1) · Transmit and Receive Interrupts · A Separate Interrupt for all UARTx Error Conditions
· Loopback mode for Diagnostic Support
FIGURE 20-1:
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control UARTx Receiver
UxRTS/BCLKx UxCTS
UxRX
UARTx Transmitter
UxTX
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20.1 UART Helpful Tips
1. In multinode, direct-connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (UxMODE[4]), which defines the Idle state, the default of which is logic high (i.e., URXINV = 0). Because remote devices do not initialize at the same time, it is likely that one of the devices, because the RX line is floating, will trigger a Start bit detection and will cause the first byte received, after the device has been initialized, to be invalid. To avoid this situation, the user should use a pullup or pull-down resistor on the RX pin depending on the value of the URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the RX pin.
b) If URXINV = 1, use a pull-down resistor on the RX pin.
2. The first character received on a wake-up from Sleep mode caused by activity on the UxRX pin of the UARTx module will be invalid. In Sleep mode, peripheral clocks are disabled. By the time the oscillator system has restarted and stabilized from Sleep mode, the baud rate bit sampling clock, relative to the incoming UxRX bit timing, is no longer synchronized, resulting in the first character being invalid; this is to be expected.
20.2 UART Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
20.2.1 KEY RESOURCES
· "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/ DS70000582) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples
· Application Notes · Software Libraries · Webinars
· All Related "dsPIC33/PIC24 Family Reference Manual" Sections
· Development Tools
DS70000657J-page 284
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
20.3 UARTx Control Registers
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
UARTEN(1)
--
USIDL
IREN(2)
RTSMD
--
bit 15
R/W-0 UEN1
R/W-0 UEN0
bit 8
HC/R/W-0 WAKE
bit 7
R/W-0 LPBACK
HC/R/W-0 ABAUD
R/W-0 URXINV
R/W-0 BRGH
R/W-0 PDSEL1
R/W-0 PDSEL0
R/W-0 STSEL
bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8
bit 7
bit 6
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN[1:0] 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
Unimplemented: Read as `0'
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode
Unimplemented: Read as `0'
UEN[1:0]: UARTx Pin Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches(3) 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used(4) 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches(4) 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge; bit is cleared in hardware on the following rising edge
0 = No wake-up is enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode 0 = Loopback mode is disabled
Note 1:
2: 3: 4:
Refer to "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/DS70000582) in the "dsPIC33/PIC24 Family Reference Manual" for information on enabling the UARTx module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0). This feature is only available on 44-pin and 64-pin devices.
This feature is only available on 64-pin devices.
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REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5 bit 4 bit 3 bit 2-1
bit 0
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character requires reception of a Sync field (55h) before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1'
BRGH: High Baud Rate Enable bit
1 = BRG generates four clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
PDSEL[1:0]: Parity and Data Selection bits
11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity
STSEL: Stop Bit Selection bit
1 = Two Stop bits 0 = One Stop bit
Note 1:
2: 3: 4:
Refer to "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/DS70000582) in the "dsPIC33/PIC24 Family Reference Manual" for information on enabling the UARTx module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0). This feature is only available on 44-pin and 64-pin devices.
This feature is only available on 64-pin devices.
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REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 UTXISEL1 bit 15
R/W-0 UTXINV
R/W-0 UTXISEL0
U-0
HC/R/W-0
R/W-0
--
UTXBRK UTXEN(1)
R-0 UTXBF
R-1 TRMT
bit 8
R/W-0 URXISEL1 bit 7
R/W-0 URXISEL0
R/W-0 ADDEN
R-1 RIDLE
R-0 PERR
R-0 FERR
R/C-0 OERR
R-0 URXDA
bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit W = Writable bit `1' = Bit is set
C = Clearable bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15,13
bit 14
bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-6
UTXISEL[1:0]: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0: 1 = UxTX Idle state is `0' 0 = UxTX Idle state is `1'
If IREN = 1: 1 = IrDA encoded, UxTX Idle state is `1' 0 = IrDA encoded, UxTX Idle state is `0'
Unimplemented: Read as `0'
UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL[1:0]: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has four data characters) 10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has three data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/DS70000582) in the "dsPIC33/PIC24 Family Reference Manual" for information on enabling the UARTx module for transmit operation.
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REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle 0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1 0 transition) resets the
receiver buffer and the UxRSR to the empty state
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty
Note 1: Refer to "Universal Asynchronous Receiver Transmitter (UART)" (www.microchip.com/DS70000582) in the "dsPIC33/PIC24 Family Reference Manual" for information on enabling the UARTx module for transmit operation.
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21.0 ENHANCED CAN (ECANTM) MODULE (dsPIC33EPXXXGP/ MC50X DEVICES ONLY)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Enhanced Controller Area Network (ECANTM)" (www.microchip.com/DS70353) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
21.1 Overview
The Enhanced Controller Area Network (ECAN) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The dsPIC33EPXXXGP/MC50X devices contain one ECAN module.
The ECAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the BOSCH CAN specification. The module supports CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is not covered within this data sheet. The reader can refer to the BOSCH CAN specification for further details.
The ECAN module features are as follows:
· Implementation of the CAN Protocol, CAN 1.2, CAN 2.0A and CAN 2.0B
· Standard and Extended Data Frames
· 0-8 Bytes Data Length
· Programmable Bit Rate Up to 1 Mbit/sec
· Automatic Response to Remote Transmission Requests
· Up to Eight Transmit Buffers with ApplicationSpecified Prioritization and Abort Capability (each buffer can contain up to 8 bytes of data)
· Up to 32 Receive Buffers (each buffer can contain up to 8 bytes of data)
· Up to 16 Full (Standard/Extended Identifier) Acceptance Filters
· Three Full Acceptance Filter Masks
· DeviceNetTM Addressing Support
· Programmable Wake-up Functionality with Integrated Low-Pass Filter
· Programmable Loopback mode supports Self-Test Operation
· Signaling via Interrupt Capabilities for All CAN Receiver and Transmitter Error States
· Programmable Clock Source
· Programmable Link to Input Capture (IC2) module for Timestamping and Network Synchronization
· Low-Power Sleep and Idle mode
The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers.
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FIGURE 21-1:
ECANTM MODULE BLOCK DIAGRAM
DMA Controller
TRB7 TX/RX Buffer Control Register TRB6 TX/RX Buffer Control Register TRB5 TX/RX Buffer Control Register TRB4 TX/RX Buffer Control Register TRB3 TX/RX Buffer Control Register TRB2 TX/RX Buffer Control Register TRB1 TX/RX Buffer Control Register TRB0 TX/RX Buffer Control Register
RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter RxF11 Filter RxF10 Filter RxF9 Filter RxF8 Filter RxF7 Filter RxF6 Filter RxF5 Filter RxF4 Filter RxF3 Filter RxF2 Filter RxF1 Filter RxF0 Filter
RxM2 Mask RxM1 Mask RxM0 Mask
Transmit Byte Sequencer
Message Assembly Buffer
CAN Protocol Engine
CxTx CxRx
Control Configuration
Logic
CPU Bus Interrupts
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21.2 Modes of Operation
The ECAN module can operate in one of several operation modes selected by the user. These modes include:
· Initialization mode · Disable mode · Normal Operation mode · Listen Only mode
· Listen All Messages mode
· Loopback mode
Modes are requested by setting the REQOP[2:0] bits (CxCTRL1[10:8]). Entry into a mode is Acknowledged by monitoring the OPMODE[2:0] bits (CxCTRL1[7:5]). The module does not change the mode and the OPMODEx bits until a change in mode is acceptable, generally during bus Idle time, which is defined as at least 11 consecutive recessive bits.
21.3 ECAN Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
21.3.1 KEY RESOURCES
· "Enhanced Controller Area Network (ECANTM)" (www.microchip.com/DS70353) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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21.4 ECAN Control Registers
REGISTER 21-1: CxCTRL1: ECANx CONTROL REGISTER 1
U-0 -- bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-1
--
CSIDL
ABAT
CANCKS REQOP2
R/W-0 REQOP1
R/W-0 REQOP0
bit 8
R-1
R-0
R-0
U-0
R/W-0
U-0
OPMODE2 OPMODE1 OPMODE0
--
CANCAP
--
bit 7
U-0
R/W-0
--
WIN
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13 bit 12 bit 11 bit 10-8
bit 7-5
bit 4 bit 3 bit 2-1 bit 0
Unimplemented: Read as `0'
CSIDL: ECANx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions are aborted
CANCKS: ECANx Module Clock (FCAN) Source Select bit
1 = FCAN is equal to 2 * FP 0 = FCAN is equal to FP
REQOP[2:0]: Request Operation Mode bits
111 = Set Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Set Configuration mode 011 = Set Listen Only mode 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode
OPMODE[2:0]: Operation Mode bits
111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode
Unimplemented: Read as `0'
CANCAP: CAN Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on CAN message receive 0 = Disables CAN capture
Unimplemented: Read as `0'
WIN: SFR Map Window Select bit
1 = Uses filter window 0 = Uses buffer window
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REGISTER 21-2: CxCTRL2: ECANx CONTROL REGISTER 2
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 8
U-0 -- bit 7
U-0
U-0
R-0
R-0
R-0
R-0
R-0
--
--
DNCNT[4:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-5 bit 4-0
Unimplemented: Read as `0'
DNCNT[4:0]: DeviceNetTM Filter Bit Number bits
10010-11111 = Invalid selection 10001 = Compares up to Data Byte 3, bit 6 with EID[17] · · · 00001 = Compares up to Data Byte 1, bit 7 with EID[0] 00000 = Does not compare data bytes
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REGISTER 21-3: CxVEC: ECANx INTERRUPT CODE REGISTER
U-0 -- bit 15
U-0
U-0
R-0
R-0
R-0
R-0
--
--
FILHIT[4:0]
R-0 bit 8
U-0 -- bit 7
R-1
R-0
R-0
R-0
R-0
ICODE[6:0]
R-0
R-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13 bit 12-8
bit 7 bit 6-0
Unimplemented: Read as `0'
FILHIT[4:0]: Filter Hit Number bits
10000-11111 = Reserved 01111 = Filter 15 ·
· ·
00001 = Filter 1 00000 = Filter 0
Unimplemented: Read as `0'
ICODE[6:0]: Interrupt Flag Code bits
1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt ·
·
· 0010000-0111111 = Reserved 0001111 = RB15 buffer interrupt · ·
·
0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 buffer interrupt
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REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
DMABS[2:0]
--
--
--
bit 15
U-0
U-0
--
--
bit 8
U-0 -- bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
--
FSA[4:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-5 bit 4-0
DMABS[2:0]: DMA Buffer Size bits
111 = Reserved 110 = 32 buffers in RAM 101 = 24 buffers in RAM 100 = 16 buffers in RAM 011 = 12 buffers in RAM 010 = 8 buffers in RAM 001 = 6 buffers in RAM 000 = 4 buffers in RAM
Unimplemented: Read as `0'
FSA[4:0]: FIFO Area Starts with Buffer bits
11111 = Read Buffer RB31 11110 = Read Buffer RB30 · · · 00001 = TX/RX Buffer TRB1 00000 = TX/RX Buffer TRB0
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REGISTER 21-5: CxFIFO: ECANx FIFO STATUS REGISTER
U-0 -- bit 15
U-0
R-0
R-0
R-0
R-0
--
FBP[5:0]
R-0
R-0
bit 8
U-0 -- bit 7
U-0
R-0
R-0
R-0
R-0
--
FNRB[5:0]
R-0
R-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13-8
bit 7-6 bit 5-0
Unimplemented: Read as `0'
FBP[5:0]: FIFO Buffer Pointer bits
011111 = RB31 buffer 011110 = RB30 buffer · · · 000001 = TRB1 buffer 000000 = TRB0 buffer
Unimplemented: Read as `0'
FNRB[5:0]: FIFO Next Read Buffer Pointer bits
011111 = RB31 buffer 011110 = RB30 buffer · · · 000001 = TRB1 buffer 000000 = TRB0 buffer
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REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER
U-0 -- bit 15
U-0
R-0
R-0
R-0
R-0
--
TXBO
TXBP
RXBP
TXWAR
R-0 RXWAR
R-0 EWARN
bit 8
R/C-0 IVRIF bit 7
R/C-0 WAKIF
R/C-0 ERRIF
U-0
R/C-0
R/C-0
R/C-0
R/C-0
--
FIFOIF
RBOVIF
RBIF
TBIF
bit 0
Legend: R = Readable bit -n = Value at POR
C = Writable bit, but only `0' can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
Unimplemented: Read as `0'
TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state
TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state
RXBP: Receiver in Error State Bus Passive bit
1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state
TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state
RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state
EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state 0 = Transmitter or receiver is not in Error Warning state
IVRIF: Invalid Message Interrupt Flag bit
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
WAKIF: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF[13:8])
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
Unimplemented: Read as `0'
FIFOIF: FIFO Almost Full Interrupt Flag bit
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
RBOVIF: RX Buffer Overflow Interrupt Flag bit
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER (CONTINUED)
bit 1
RBIF: RX Buffer Interrupt Flag bit
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
bit 0
TBIF: TX Buffer Interrupt Flag bit
1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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REGISTER 21-7: CxINTE: ECANx INTERRUPT ENABLE REGISTER
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 8
R/W-0 IVRIE bit 7
R/W-0 WAKIE
R/W-0 ERRIE
U-0
R/W-0
R/W-0
R/W-0
R/W-0
--
FIFOIE
RBOVIE
RBIE
TBIE
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0'
IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
WAKIE: Bus Wake-up Activity Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
ERRIE: Error Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
Unimplemented: Read as `0'
FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt request is enabled 0 = Interrupt request is not enabled
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REGISTER 21-8: CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT[7:0]
bit 15
R-0 bit 8
R-0 bit 7
R-0
R-0
R-0
R-0
R-0
RERRCNT[7:0]
R-0
R-0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
TERRCNT[7:0]: Transmit Error Count bits RERRCNT[7:0]: Receive Error Count bits
REGISTER 21-9: CxCFG1: ECANx BAUD RATE CONFIGURATION REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
R/W-0 SJW1 bit 7
R/W-0 SJW0
R/W-0 BRP5
R/W-0 BRP4
R/W-0 BRP3
R/W-0 BRP2
R/W-0 BRP1
R/W-0 BRP0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-6
bit 5-0
Unimplemented: Read as `0'
SJW[1:0]: Synchronization Jump Width bits
11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ
BRP[5:0]: Baud Rate Prescaler bits
11 1111 = TQ = 2 x 64 x 1/FCAN · · · 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN
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REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2
U-0
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
--
WAKFIL
--
--
--
SEG2PH2 SEG2PH1
bit 15
R/W-x SEG2PH0
bit 8
R/W-x SEG2PHTS bit 7
R/W-x SAM
R/W-x
R/W-x
R/W-x
SEG1PH2 SEG1PH1 SEG1PH0
R/W-x PRSEG2
R/W-x PRSEG1
R/W-x PRSEG0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13-11 bit 10-8
bit 7 bit 6 bit 5-3
bit 2-0
Unimplemented: Read as `0'
WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up
Unimplemented: Read as `0'
SEG2PH[2:0]: Phase Segment 2 bits
111 = Length is 8 x TQ · · · 000 = Length is 1 x TQ
SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable 0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater
SAM: Sample of the CAN Bus Line bit
1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point
SEG1PH[2:0]: Phase Segment 1 bits
111 = Length is 8 x TQ · · · 000 = Length is 1 x TQ
PRSEG[2:0]: Propagation Time Segment bits
111 = Length is 8 x TQ · · · 000 = Length is 1 x TQ
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REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1
R/W-1 bit 15
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN[15:8]
R/W-1
R/W-1
R/W-1 bit 8
R/W-1 bit 7
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN[7:0]
R/W-1
R/W-1
R/W-1 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
FLTEN[15:0]: Enable Filter n to Accept Messages bits
1 = Enables Filter n 0 = Disables Filter n
REGISTER 21-12: CxBUFPNT1: ECANx FILTER 0-3 BUFFER POINTER REGISTER 1
R/W-0 bit 15
R/W-0
R/W-0
F3BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F2BP[3:0]
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
F1BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F0BP[3:0]
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-8 bit 7-4 bit 3-0
F3BP[3:0]: RX Buffer Mask for Filter 3 bits
1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 · · · 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0
F2BP[3:0]: RX Buffer Mask for Filter 2 bits (same values as bits[15:12])
F1BP[3:0]: RX Buffer Mask for Filter 1 bits (same values as bits[15:12])
F0BP[3:0]: RX Buffer Mask for Filter 0 bits (same values as bits[15:12])
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REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2
R/W-0 bit 15
R/W-0
R/W-0
F7BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F6BP[3:0]
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
F5BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F4BP[3:0]
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-8 bit 7-4 bit 3-0
F7BP[3:0]: RX Buffer Mask for Filter 7 bits
1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 · · · 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0
F6BP[3:0]: RX Buffer Mask for Filter 6 bits (same values as bits[15:12])
F5BP[3:0]: RX Buffer Mask for Filter 5 bits (same values as bits[15:12])
F4BP[3:0]: RX Buffer Mask for Filter 4 bits (same values as bits[15:12])
REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3
R/W-0 bit 15
R/W-0
R/W-0
F11BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F10BP[3:0]
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
F9BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F8BP[3:0]
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-8 bit 7-4 bit 3-0
F11BP[3:0]: RX Buffer Mask for Filter 11 bits
1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 · · · 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0
F10BP[3:0]: RX Buffer Mask for Filter 10 bits (same values as bits[15:12])
F9BP[3:0]: RX Buffer Mask for Filter 9 bits (same values as bits[15:12])
F8BP[3:0]: RX Buffer Mask for Filter 8 bits (same values as bits[15:12])
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REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4
R/W-0 bit 15
R/W-0
R/W-0
F15BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F14BP[3:0]
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
F13BP[3:0]
R/W-0
R/W-0
R/W-0
R/W-0
F12BP[3:0]
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-8 bit 7-4 bit 3-0
F15BP[3:0]: RX Buffer Mask for Filter 15 bits
1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 · · · 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0
F14BP[3:0]: RX Buffer Mask for Filter 14 bits (same values as bits[15:12])
F13BP[3:0]: RX Buffer Mask for Filter 13 bits (same values as bits[15:12])
F12BP[3:0]: RX Buffer Mask for Filter 12 bits (same values as bits[15:12])
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REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER REGISTER (n = 0-15)
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
SID[10:3]
R/W-x
R/W-x
R/W-x bit 8
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
SID[2:0]
--
EXIDE
--
bit 7
R/W-x
R/W-x
EID[17:16]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-5 bit 4 bit 3
bit 2 bit 1-0
SID[10:0]: Standard Identifier bits
1 = Message address bit, SIDx, must be `1' to match filter 0 = Message address bit, SIDx, must be `0' to match filter
Unimplemented: Read as `0'
EXIDE: Extended Identifier Enable bit
If MIDE = 1: 1 = Matches only messages with Extended Identifier addresses 0 = Matches only messages with Standard Identifier addresses If MIDE = 0: Ignores EXIDE bit.
Unimplemented: Read as `0'
EID[17:16]: Extended Identifier bits
1 = Message address bit, EIDx, must be `1' to match filter 0 = Message address bit, EIDx, must be `0' to match filter
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REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTER (n = 0-15)
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
EID[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
EID[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
EID[15:0]: Extended Identifier bits
1 = Message address bit, EIDx, must be `1' to match filter 0 = Message address bit, EIDx, must be `0' to match filter
REGISTER 21-18: CxFMSKSEL1: ECANx FILTER 7-0 MASK SELECTION REGISTER 1
R/W-0
R/W-0
F7MSK[1:0]
bit 15
R/W-0
R/W-0
F6MSK[1:0]
R/W-0
R/W-0
F5MSK[1:0]
R/W-0
R/W-0
F4MSK[1:0]
bit 8
R/W-0
R/W-0
F3MSK[1:0]
bit 7
R/W-0
R/W-0
F2MSK[1:0]
R/W-0
R/W-0
F1MSK[1:0]
R/W-0
R/W-0
F0MSK[1:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0
F7MSK[1:0]: Mask Source for Filter 7 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask F6MSK[1:0]: Mask Source for Filter 6 bits (same values as bits[15:14])
F5MSK[1:0]: Mask Source for Filter 5 bits (same values as bits[15:14])
F4MSK[1:0]: Mask Source for Filter 4 bits (same values as bits[15:14])
F3MSK[1:0]: Mask Source for Filter 3 bits (same values as bits[15:14])
F2MSK[1:0]: Mask Source for Filter 2 bits (same values as bits[15:14])
F1MSK[1:0]: Mask Source for Filter 1 bits (same values as bits[15:14])
F0MSK[1:0]: Mask Source for Filter 0 bits (same values as bits[15:14])
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REGISTER 21-19: CxFMSKSEL2: ECANx FILTER 15-8 MASK SELECTION REGISTER 2
R/W-0
R/W-0
F15MSK[1:0]
bit 15
R/W-0
R/W-0
F14MSK[1:0]
R/W-0
R/W-0
F13MSK[1:0]
R/W-0
R/W-0
F12MSK[1:0]
bit 8
R/W-0
R/W-0
F11MSK[1:0]
bit 7
R/W-0
R/W-0
F10MSK[1:0]
R/W-0
R/W-0
F9MSK[1:0]
R/W-0
R/W-0
F8MSK[1:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0
F15MSK[1:0]: Mask Source for Filter 15 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask F14MSK[1:0]: Mask Source for Filter 14 bits (same values as bits[15:14])
F13MSK[1:0]: Mask Source for Filter 13 bits (same values as bits[15:14])
F12MSK[1:0]: Mask Source for Filter 12 bits (same values as bits[15:14])
F11MSK[1:0]: Mask Source for Filter 11 bits (same values as bits[15:14])
F10MSK[1:0]: Mask Source for Filter 10 bits (same values as bits[15:14])
F9MSK[1:0]: Mask Source for Filter 9 bits (same values as bits[15:14])
F8MSK[1:0]: Mask Source for Filter 8 bits (same values as bits[15:14])
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REGISTER 21-20: CxRXMnSID: ECANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER REGISTER (n = 0-2)
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
SID[10:3]
R/W-x
R/W-x
R/W-x bit 8
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID[2:0]
--
MIDE
--
EID[17:16]
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4 bit 3
bit 2 bit 1-0
SID[10:0]: Standard Identifier bits
1 = Includes bit, SIDx, in filter comparison 0 = SIDx bit is a don't care in filter comparison
Unimplemented: Read as `0'
MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in the filter 0 = Matches either standard or extended address message if filters match (i.e., if (Filter SID) = (Message
SID) or if (Filter SID/EID) = (Message SID/EID))
Unimplemented: Read as `0'
EID[17:16]: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is a don't care in filter comparison
REGISTER 21-21: CxRXMnEID: ECANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER REGISTER (n = 0-2)
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
EID[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
EID[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
EID[15:0]: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is a don't care in filter comparison
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REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1
R/C-0 bit 15
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL[15:8]
R/C-0
R/C-0
R/C-0 bit 8
R/C-0 bit 7
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL[7:0]
R/C-0
R/C-0
R/C-0 bit 0
Legend: R = Readable bit -n = Value at POR
C = Writable bit, but only `0' can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
RXFUL[15:0]: Receive Buffer n Full bits
1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software)
REGISTER 21-23: CxRXFUL2: ECANx RECEIVE BUFFER FULL REGISTER 2
R/C-0 bit 15
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL[31:24]
R/C-0
R/C-0
R/C-0 bit 8
R/C-0 bit 7
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL[23:16]
R/C-0
R/C-0
R/C-0 bit 0
Legend: R = Readable bit -n = Value at POR
C = Writable bit, but only `0' can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
RXFUL[31:16]: Receive Buffer n Full bits
1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software)
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REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0 bit 15
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF[15:8]
R/C-0
R/C-0
R/C-0 bit 8
R/C-0 bit 7
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF[7:0]
R/C-0
R/C-0
R/C-0 bit 0
Legend: R = Readable bit -n = Value at POR
C = Writable bit, but only `0' can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
RXOVF[15:0]: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software)
REGISTER 21-25: CxRXOVF2: ECANx RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0 bit 15
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF[31:24]
R/C-0
R/C-0
R/C-0 bit 8
R/C-0 bit 7
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF[23:16]
R/C-0
R/C-0
R/C-0 bit 0
Legend: R = Readable bit -n = Value at POR
C = Writable bit, but only `0' can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
RXOVF[31:16]: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software)
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REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7)
R/W-0 TXENn bit 15
R-0 TXABTn
R-0 TXLARBn
R-0 TXERRn
R/W-0 TXREQn
R/W-0 RTRENn
R/W-0 TXnPRI1
R/W-0 TXnPRI0
bit 8
R/W-0 TXENm bit 7
R-0
R-0
R-0
R/W-0
TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm
R/W-0 RTRENm
R/W-0 TXmPRI1
R/W-0 TXmPRI0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7 bit 6 bit 5 bit 4 bit 3
bit 2 bit 1-0
See Definition for bits[7:0], Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer TXABTm: Message Aborted bit(1)
1 = Message was aborted 0 = Message completed transmission successfully TXLARBm: Message Lost Arbitration bit(1)
1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERRm: Error Detected During Transmission bit(1)
1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent
0 = Clearing the bit to `0' while set requests a message abort
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected
TXmPRI[1:0]: Message Transmission Priority bits
11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
Note: The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.
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21.5 ECAN Message Buffers
ECAN Message Buffers are part of RAM memory. They are not ECAN Special Function Registers. The user application must directly write into the RAM area that is configured for ECAN Message Buffers. The location and size of the buffer area is defined by the user application.
BUFFER 21-1:
U-0 -- bit 15
ECANTM MESSAGE BUFFER WORD 0
U-0
U-0
R/W-x
R/W-x
--
--
R/W-x SID[10:6]
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
SID[5:0]
R/W-x
R/W-x
R/W-x SRR
R/W-x IDE bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13 bit 12-2 bit 1
bit 0
Unimplemented: Read as `0'
SID[10:0]: Standard Identifier bits
SRR: Substitute Remote Request bit
When IDE = 0: 1 = Message will request remote transmission 0 = Normal message When IDE = 1: The SRR bit must be set to `1'.
IDE: Extended Identifier bit
1 = Message will transmit Extended Identifier 0 = Message will transmit Standard Identifier
BUFFER 21-2:
U-0 -- bit 15
ECANTM MESSAGE BUFFER WORD 1
U-0
U-0
U-0
R/W-x
--
--
--
R/W-x
R/W-x
EID[17:14]
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
EID[13:6]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12 bit 11-0
Unimplemented: Read as `0' EID[17:6]: Extended Identifier bits
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(
BUFFER 21-3:
ECANTM MESSAGE BUFFER WORD 2
R/W-x EID5 bit 15
R/W-x EID4
R/W-x EID3
R/W-x EID2
R/W-x EID1
R/W-x EID0
R/W-x RTR
R/W-x RB1
bit 8
U-x -- bit 7
U-x
U-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
--
--
RB0
DLC3
DLC2
DLC1
DLC0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-10 bit 9
bit 8 bit 7-5 bit 4 bit 3-0
EID[5:0]: Extended Identifier bits
RTR: Remote Transmission Request bit
When IDE = 1: 1 = Message will request remote transmission 0 = Normal message When IDE = 0: The RTR bit is ignored.
RB1: Reserved Bit 1 User must set this bit to `0' per CAN protocol.
Unimplemented: Read as `0'
RB0: Reserved Bit 0
User must set this bit to `0' per CAN protocol.
DLC[3:0]: Data Length Code bits
BUFFER 21-4: ECANTM MESSAGE BUFFER WORD 3
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
Byte 1[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
Byte 0[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Byte 1[15:8]: ECAN Message Byte 1 bits Byte 0[7:0]: ECAN Message Byte 0 bits
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BUFFER 21-5: ECANTM MESSAGE BUFFER WORD 4
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
Byte 3[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
Byte 2[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Byte 3[15:8]: ECAN Message Byte 3 bits Byte 2[7:0]: ECAN Message Byte 2 bits
BUFFER 21-6: ECANTM MESSAGE BUFFER WORD 5
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
Byte 5[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
Byte 4[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Byte 5[15:8]: ECAN Message Byte 5 bits Byte 4[7:0]: ECAN Message Byte 4 bits
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BUFFER 21-7: ECANTM MESSAGE BUFFER WORD 6
R/W-x bit 15
R/W-x
R/W-x
R/W-x
R/W-x
Byte 7[15:8]
R/W-x
R/W-x
R/W-x bit 8
R/W-x bit 7
R/W-x
R/W-x
R/W-x
R/W-x
Byte 6[7:0]
R/W-x
R/W-x
R/W-x bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
Byte 7[15:8]: ECAN Message Byte 7 bits Byte 6[7:0]: ECAN Message Byte 6 bits
BUFFER 21-8:
U-0 -- bit 15
ECANTM MESSAGE BUFFER WORD 7
U-0
U-0
R/W-x
R/W-x
--
--
R/W-x FILHIT[4:0](1)
R/W-x
R/W-x bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13 bit 12-8
bit 7-0
Unimplemented: Read as `0' FILHIT[4:0]: Filter Hit Code bits(1) Encodes number of filter that resulted in writing this buffer.
Unimplemented: Read as `0'
Note 1: Only written by module for receive buffers, unused for transmit buffers.
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NOTES:
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22.0 CHARGE TIME MEASUREMENT UNIT (CTMU)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Charge Time Measurement Unit (CTMU)" (www.microchip.com/DS70661) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include:
· Four Edge Input Trigger Sources
· Polarity Control for Each Edge Source
· Control of Edge Sequence
· Control of Response to Edges
· Precise Time Measurement Resolution of 1 ns
· Accurate Current Source Suitable for Capacitive Measurement
· On-Chip Temperature Measurement using a Built-in Diode
Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock.
The CTMU module is ideal for interfacing with capacitive-based sensors.The CTMU is controlled through three registers: CTMUCON1, CTMUCON2 and CTMUICON. CTMUCON1 and CTMUCON2 enable the module and control edge source selection, edge source polarity selection and edge sequencing. The CTMUICON register controls the selection and trim of the current source.
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FIGURE 22-1:
CTMU BLOCK DIAGRAM
CTMUCON1 or CTMUCON2(1)
CTMUICON ITRIM[5:0] IRNG[1:0]
Current Source
CTED1
CTED2
Timer1 OC1 IC1
CMP1
Edge Control Logic
EDG1STAT EDG2STAT
Current Control
TGEN
CTMU TEMP(3) CTMU
Temperature Sensor
CTMUI to ADC(2)
C1IN1CDelay
CTMUP
ADC CH0(5)
External Capacitor for Pulse Generation
CTMU Control Logic Pulse Generator
CMP1
Current Control Selection
CTMU TEMP CTMUI to ADC(2) CTMUP Internal Current Flow(4)
TGEN
0 0 1 1
EDG1STAT, EDG2STAT
EDG1STAT = EDG2STAT EDG1STAT EDG2STAT EDG1STAT EDG2STAT EDG1STAT = EDG2STAT
Analog-to-Digital Trigger CTPLS
Note 1:
2: 3: 4: 5:
When the CTMU is not actively used, set TGEN = 1, and ensure that EDG1STAT = EDG2STAT. All other settings allow current to flow into the ADC or the C1IN1- pin. If using the ADC for other purposes besides the CTMU, set IDISSEN = 0. If IDISSEN is set to `1', it will short the output of the ADC CH0 MUX to VSS. CTMUI connects to the output of the ADC CH0 MUX. When CTMU current is steered into this node, the current will flow out through the selected ADC channel determined by the CH0 MUX (see the CH0Sx bits in the AD1CHS0 register).
CTMU TEMP connects to one of the ADC CH0 inputs; see CH0SA and CH0SB (AD1CHS0[12:8,4:0).
If TGEN = 1 and EDG1STAT = EDG2STAT, CTMU current source is still enabled and may be shunted to VSS internally. This should be considered in low-power applications.
The switch connected to ADC CH0 is closed when IDISSEN (CTMUCON1[9]) = 1, and opened when IDISSEN = 0.
22.1 CTMU Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
22.1.1 KEY RESOURCES
· "Charge Time Measurement Unit (CTMU)" (www.microchip.com/DS70661) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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22.2 CTMU Control Registers
REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0 CTMUEN bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
CTMUSIDL
TGEN
EDGEN EDGSEQEN IDISSEN(1)
R/W-0 CTTRIG
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-0
CTMUEN: CTMU Enable bit
1 = Module is enabled 0 = Module is disabled
Unimplemented: Read as `0'
CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
TGEN: Time Generation Enable bit
1 = Enables edge delay generation 0 = Disables edge delay generation
EDGEN: Edge Enable bit
1 = Hardware modules are used to trigger edges (TMRx, CTEDx, etc.) 0 = Software is used to trigger edges (manual set of EDGxSTAT)
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(1)
1 = Analog current source output is grounded 0 = Analog current source output is not grounded
CTTRIG: ADC Trigger Control bit
1 = CTMU triggers ADC start of conversion 0 = CTMU does not trigger ADC start of conversion
Unimplemented: Read as `0'
Note 1:
The ADC module Sample-and-Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
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REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0 EDG1MOD bit 15
R/W-0 EDG1POL
R/W-0 EDG1SEL3
R/W-0 EDG1SEL2
R/W-0 EDG1SEL1
R/W-0 EDG1SEL0
R/W-0 EDG2STAT
R/W-0 EDG1STAT
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
--
bit 7
U-0 --
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13-10
bit 9 bit 8 bit 7 bit 6 bit 5-2
bit 1-0
EDG1MOD: Edge 1 Edge Sampling Mode Selection bit
1 = Edge 1 is edge-sensitive 0 = Edge 1 is level-sensitive
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response
EDG1SEL[3:0]: Edge 1 Source Select bits
1xxx = Reserved 01xx = Reserved 0011 = CTED1 pin 0010 = CTED2 pin 0001 = OC1 module 0000 = Timer1 module
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source. 1 = Edge 2 has occurred 0 = Edge 2 has not occurred
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source. 1 = Edge 1 has occurred 0 = Edge 1 has not occurred
EDG2MOD: Edge 2 Edge Sampling Mode Selection bit
1 = Edge 2 is edge-sensitive 0 = Edge 2 is level-sensitive
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response
EDG2SEL[3:0]: Edge 2 Source Select bits
1111 = Reserved 01xx = Reserved 0100 = CMP1 module 0011 = CTED2 pin 0010 = CTED1 pin 0001 = OC1 module 0000 = IC1 module
Unimplemented: Read as `0'
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REGISTER 22-3: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 ITRIM5 bit 15
R/W-0 ITRIM4
R/W-0 ITRIM3
R/W-0 ITRIM2
R/W-0 ITRIM1
R/W-0 ITRIM0
R/W-0 IRNG1
R/W-0 IRNG0
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
--
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-10
bit 9-8 bit 7-0
ITRIM[5:0]: Current Source Trim bits
011111 = Maximum positive change from nominal current + 62% 011110 = Maximum positive change from nominal current + 60% · · · 000010 = Minimum positive change from nominal current + 4% 000001 = Minimum positive change from nominal current + 2% 000000 = Nominal current output specified by IRNG[1:0] 111111 = Minimum negative change from nominal current 2% 111110 = Minimum negative change from nominal current 4% · · · 100010 = Maximum negative change from nominal current 60% 100001 = Maximum negative change from nominal current 62%
IRNG[1:0]: Current Source Range Select bits 11 = 100 Base Current(2) 10 = 10 Base Current(2) 01 = Base Current Level(2) 00 = 1000 Base Current(1,2)
Unimplemented: Read as `0'
Note 1: This current range is not available to be used with the internal temperature measurement diode.
2: Refer to the CTMU Current Source Specifications (Table 30-56) in Section 30.0 "Electrical Characteristics" for the current range selection values.
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NOTES:
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23.0 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Analog-to-Digital Converter (ADC)" (www.microchip.com/DS70621) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices have one ADC module. The ADC module supports up to 16 analog input channels.
On ADC1, the AD12B bit (AD1CON1[10]) allows the ADC module to be configured by the user as either a 10-bit, four Sample-and-Hold (S&H) ADC (default configuration) or a 12-bit, one S&H ADC.
Note: The ADC module needs to be disabled before modifying the AD12B bit.
23.1 Key Features
23.1.1 10-BIT ADC CONFIGURATION
The 10-bit ADC configuration has the following key features:
· Successive Approximation (SAR) Conversion · Conversion Speeds of Up to 1.1 Msps · Up to 16 Analog Input Pins · Connections to Three Internal Op Amps · Connections to the Charge Time Measurement Unit
(CTMU) and Temperature Measurement Diode · Channel Selection and Triggering can be Controlled
by the Peripheral Trigger Generator (PTG) · External Voltage Reference Input Pins · Simultaneous Sampling of:
- Up to four analog input pins - Three op amp outputs - Combinations of analog inputs and op amp outputs · Automatic Channel Scan mode · Selectable Conversion Trigger Source · Selectable Buffer Fill modes · Four Result Alignment Options (signed/unsigned, fractional/integer) · Operation during CPU Sleep and Idle modes
23.1.2 12-BIT ADC CONFIGURATION
The 12-bit ADC configuration supports all the features listed above, with the exception of the following:
· In the 12-bit configuration, conversion speeds of up to 500 ksps are supported
· There is only one S&H amplifier in the 12-bit configuration; therefore, simultaneous sampling of multiple channels is not supported
Depending on the particular device pinout, the ADC can have up to 16 analog input pins, designated AN0 through AN15. These analog inputs are shared with op amp inputs and outputs, comparator inputs, and external voltage references. When op amp/comparator functionality is enabled, or an external voltage reference is used, the analog input that shares that pin is no longer available. The actual number of analog input pins, op amps and external voltage reference input configuration depends on the specific device.
A block diagram of the ADC module is shown in Figure 23-1. Figure 23-2 provides a diagram of the ADC conversion clock period.
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FIGURE 23-1:
ADC MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS
This diagram depicts all of the available ADC connection options to the four S&H amplifiers, which are designated: CH0, CH1, CH2 and CH3.
The ANx analog pins or op amp outputs are connected to the CH0-CH3 amplifiers through the multiplexers, controlled by the SFR control bits, CH0Sx, CHONx, CH123Sx and CH123Nx.
AN0-ANx OA1-OA3 CTMU Temp
Open
AN0/OA2OUT/RA0 PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
AN9/RPI27/RA11
00000
11111
CH0Sx VREFL 0 1
+ CH0
++
OPMODE
CMP1
/OA1
OA1
0 1 CH123Sx
CH0Nx
VREFL
0x
10
11
+ CH1
From CTMU Current Source (CTMUI)
S&H0
S&H1
Channel Scan
1
CH0SA[4:0](3) 0
CSCNA
CH0SB[4:0](3)
CH0NA(3) CH0NB(3)
CH123SA CH123SB
CH123NA[2:0] CH123NB[2:0]
A CH0Sx
B
A CH0Nx
B
A CH123Sx
B
A CH123Nx
B
2011-2020 Microchip Technology Inc.
AN1/C2IN1+/RA1 AN10/RPI28/RA12
CH123Nx
0 + OPMODE
1
OA2 CH123Sx
+ CH2
VREFL
0x
10
11
S&H2
ALTS
Alternate Input (MUXA/MUXB)
Selection
VREF+(1) AVDD VREF-(1) AVSS
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 AN8/C3IN1+/U1RTS/BCLK1/RC2 AN7/C3IN1-/C4IN1-/RC1 AN6/OA3OUT/C4IN1+/OCFB/RC0
AN11/C1IN2-/U1CTS/RC11
CH123Nx
+ OPMODE
0
1
OA3(5) CH123Sx
+ CH3
VREFL
0x
10
11
S&H3
VCFG[2:0]
VREFH
VREFL
SAR ADC
CH123Nx
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: These bits can be updated with Step commands from the PTG module. See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for more information. 4: When ADDMAEN (AD1CON4[8]) = 1, enabling DMA, only ADC1BUF0 is used. 5: OA3 is not available for 28-pin devices.
ADC1BUF0(4) ADC1BUF1(4) ADC1BUF2(4)
ADC1BUFE(4) ADC1BUFF(4)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 23-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3[15]
ADC Internal RC Clock(2)
TP(1)
AD1CON3[7:0]
6
ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 256
1 TAD
0
Note 1: TP = 1/FP.
2: See the ADC electrical specifications in Section 30.0 "Electrical Characteristics" for the exact RC clock value.
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23.2 ADC Helpful Tips
1. The SMPIx control bits in the AD1CON2 register:
a) Determine when the ADC interrupt flag is set and an interrupt is generated, if enabled.
b) When the CSCNA bit in the AD1CON2 register is set to `1', this determines when the ADC analog scan channel list, defined in the AD1CSSL/AD1CSSH registers, starts over from the beginning.
c) When the DMA peripheral is not used (ADDMAEN = 0), this determines when the ADC Result Buffer Pointer to ADC1BUF0ADC1BUFF gets reset back to the beginning at ADC1BUF0.
d) When the DMA peripheral is used (ADDMAEN = 1), this determines when the DMA Address Pointer is incremented after a sample/conversion operation. ADC1BUF0 is the only ADC buffer used in this mode. The ADC Result Buffer Pointer to ADC1BUF0ADC1BUFF gets reset back to the beginning at ADC1BUF0. The DMA address is incremented after completion of every 32nd sample/conversion operation. Conversion results are stored in the ADC1BUF0 register for transfer to RAM using DMA.
2. When the DMA module is disabled (ADDMAEN = 0), the ADC has 16 result buffers. ADC conversion results are stored sequentially in ADC1BUF0-ADC1BUFF, regardless of which analog inputs are being used subject to the SMPIx bits and the condition described in 1c) above. There is no relationship between the ANx input being measured and which ADC buffer (ADC1BUF0-ADC1BUFF) that the conversion results will be placed in.
3. When the DMA module is enabled (ADDMAEN = 1), the ADC module has only one ADC result buffer (i.e., ADC1BUF0) per ADC peripheral and the ADC conversion result must be read, either by the CPU or DMA Controller, before the next ADC conversion is complete to avoid overwriting the previous value.
4. The DONE bit (AD1CON1[0]) is only cleared at the start of each conversion and is set at the completion of the conversion, but remains set indefinitely, even through the next sample phase until the next conversion begins. If application code is monitoring the DONE bit in any kind of software loop, the user must consider this behavior because the CPU code execution is faster than the ADC. As a result, in Manual Sample mode, particularly where the user's code is setting the SAMP bit (AD1CON1[1]), the DONE bit should also be cleared by the user application just before setting the SAMP bit.
5. Enabling op amps, comparator inputs and external voltage references can limit the availability of analog inputs (ANx pins). For example, when Op Amp 2 is enabled, the pins for AN0, AN1 and AN2 are used by the op amp's inputs and output. This negates the usefulness of Alternate Input mode since the MUXA selections use AN0-AN2. Carefully study the ADC block diagram to determine the configuration that will best suit your application. Configuration examples are available in the "Analog-to-Digital Converter (ADC)" (www.microchip.com/DS70621) section in the "dsPIC33/PIC24 Family Reference Manual".
23.3 ADC Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
23.3.1 KEY RESOURCES
· "Analog-to-Digital Converter (ADC)" (www.microchip.com/DS70621) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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23.4 ADC Control Registers
REGISTER 23-1: AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0 ADON bit 15
U-0
R/W-0
R/W-0
U-0
--
ADSIDL ADDMABM
--
R/W-0 AD12B
R/W-0 FORM1
R/W-0 FORM0
bit 8
R/W-0 SSRC2 bit 7
R/W-0 SSRC1
R/W-0 SSRC0
R/W-0 SSRCG
R/W-0 SIMSAM
R/W-0 ASAM
HC/HS/R/W-0 SAMP
HC/HS/R/C-0 DONE(3)
bit 0
Legend: R = Readable bit -n = Value at POR
HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12
bit 11 bit 10 bit 9-8
ADON: ADC1 Operating Mode bit
1 = ADC module is operating 0 = ADC is off
Unimplemented: Read as `0'
ADSIDL: ADC1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
ADDMABM: DMA Buffer Build Mode bit
1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer
0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer.
Unimplemented: Read as `0'
AD12B: ADC1 10-Bit or 12-Bit Operation Mode bit
1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation
FORM[1:0]: Data Output Format bits
For 10-Bit Operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d[9]) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d[9]) 00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-Bit Operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d[11]) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d[11]) 00 = Integer (DOUT = 0000 dddd dddd dddd)
Note 1: 2: 3:
See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for information on this selection. This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Do not clear the DONE bit in software if auto-sample is enabled (ASAM = 1).
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REGISTER 23-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 7-5
bit 4 bit 3 bit 2 bit 1 bit 0
SSRC[2:0]: Sample Trigger Source Select bits
If SSRCG = 1: 111 = Reserved 110 = PTGO15 primary trigger compare ends sampling and starts conversion(1) 101 = PTGO14 primary trigger compare ends sampling and starts conversion(1) 100 = PTGO13 primary trigger compare ends sampling and starts conversion(1) 011 = PTGO12 primary trigger compare ends sampling and starts conversion(1) 010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion(2) 001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion(2) 000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion(2)
If SSRCG = 0: 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = PWM primary Special Event Trigger ends sampling and starts conversion(2) 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on the INT0 pin ends sampling and starts conversion 000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode)
SSRCG: Sample Trigger Source Group bit
See SSRC[2:0] for details.
SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS[1:0] = 01 or 1x)
In 12-bit mode (AD21B = 1), SIMSAM is Unimplemented and is Read as `0': 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS[1:0] = 1x); or samples CH0 and CH1
simultaneously (when CHPS[1:0] = 01) 0 = Samples multiple channels individually in sequence
ASAM: ADC1 Sample Auto-Start bit
1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is set
SAMP: ADC1 Sample Enable bit
1 = ADC Sample-and-Hold amplifiers are sampling 0 = ADC Sample-and-Hold amplifiers are holding If ASAM = 0, software can write `1' to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC[2:0] = 000, software can write `0' to end sampling and start conversion. If SSRC[2:0] 000, automatically cleared by hardware to end sampling and start conversion.
DONE: ADC1 Conversion Status bit(3)
1 = ADC conversion cycle has completed 0 = ADC conversion has not started or is in progress Automatically set by hardware when the ADC conversion is complete. Software can write `0' to clear the DONE status bit (software is not allowed to write `1'). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at the start of a new conversion.
Note 1: 2: 3:
See Section 24.0 "Peripheral Trigger Generator (PTG) Module" for information on this selection. This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Do not clear the DONE bit in software if auto-sample is enabled (ASAM = 1).
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REGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
VCFG2
VCFG1
VCFG0
--
--
bit 15
R/W-0 CSCNA
R/W-0 CHPS1
R/W-0 CHPS0
bit 8
R-0 BUFS bit 7
R/W-0 SMPI4
R/W-0 SMPI3
R/W-0 SMPI2
R/W-0 SMPI1
R/W-0 SMPI0
R/W-0 BUFM
R/W-0 ALTS
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-11 bit 10 bit 9-8 bit 7 bit 6-2
VCFG[2:0]: Converter Voltage Reference Configuration bits
Value
VREFH
VREFL
000
AVDD
001 External VREF+
010
AVDD
011 External VREF+
1xx
AVDD
AVSS AVSS External VREFExternal VREFAVSS
Unimplemented: Read as `0'
CSCNA: Input Scan Select bit
1 = Scans inputs for CH0+ during Sample MUXA 0 = Does not scan inputs
CHPS[1:0]: Channel Select bits
In 12-bit mode (AD21B = 1), the CHPS[1:0] bits are Unimplemented and are Read as `0': 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling the second half of the buffer; the user application should access data in the first half of the buffer
0 = ADC is currently filling the first half of the buffer; the user application should access data in the second half of the buffer
SMPI[4:0]: Increment Rate bits
When ADDMAEN = 0: x1111 = Generates interrupt after completion of every 16th sample/conversion operation x1110 = Generates interrupt after completion of every 15th sample/conversion operation · · · x0001 = Generates interrupt after completion of every 2nd sample/conversion operation x0000 = Generates interrupt after completion of every sample/conversion operation
When ADDMAEN = 1: 11111 = Increments the DMA address after completion of every 32nd sample/conversion operation 11110 = Increments the DMA address after completion of every 31st sample/conversion operation · · · 00001 = Increments the DMA address after completion of every 2nd sample/conversion operation 00000 = Increments the DMA address after completion of every sample/conversion operation
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REGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED)
bit 1
BUFM: Buffer Fill Mode Select bit
1 = Starts the buffer filling the first half of the buffer on the first interrupt and the second half of the buffer on next interrupt
0 = Always starts filling the buffer from the start address
bit 0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample MUXA on first sample and Sample MUXB on next sample 0 = Always uses channel input selects for Sample MUXA
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REGISTER 23-3: AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0
U-0
ADRC
--
bit 15
U-0
R/W-0
R/W-0
--
R/W-0 SAMC[4:0](1)
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
ADCS[7:0](2)
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-13 bit 12-8
bit 7-0
ADRC: ADC1 Conversion Clock Source bit
1 = ADC internal RC clock 0 = Clock derived from system clock
Unimplemented: Read as `0' SAMC[4:0]: Auto-Sample Time bits(1)
11111 = 31 TAD · · · 00001 = 1 TAD 00000 = 0 TAD ADCS[7:0]: ADC1 Conversion Clock Select bits(2)
11111111 = TP · (ADCS[7:0] + 1) = TP ·256 = TAD · · · 00000010 = TP · (ADCS[7:0] + 1) = TP ·3 = TAD 00000001 = TP · (ADCS[7:0] + 1) = TP ·2 = TAD 00000000 = TP · (ADCS[7:0] + 1) = TP ·1 = TAD
Note 1: This bit is only used if SSRC[2:0] (AD1CON1[7:5]) = 111 and SSRCG (AD1CON1[4]) = 0. 2: This bit is not used if ADRC (AD1CON3[15]) = 1.
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REGISTER 23-4: AD1CON4: ADC1 CONTROL REGISTER 4
U-0 -- bit 15
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
U-0
R/W-0
--
ADDMAEN
bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
--
DMABL[2:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-9 bit 8
bit 7-3 bit 2-0
Unimplemented: Read as `0'
ADDMAEN: ADC1 DMA Enable bit
1 = Conversion results are stored in the ADC1BUF0 register for transfer to RAM using DMA 0 = Conversion results are stored in ADC1BUF0 through ADC1BUFF registers; DMA will not be used
Unimplemented: Read as `0'
DMABL[2:0]: Selects Number of DMA Buffer Locations per Analog Input bits
111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input
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REGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNELS 1, 2, 3 SELECT REGISTER
U-0 -- bit 15
U-0
U-0
U-0
U-0
R/W-0
R/W-0
--
--
--
--
CH123NB1 CH123NB0
R/W-0 CH123SB
bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
--
--
--
--
CH123NA1 CH123NA0 CH123SA
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-11 bit 10-9
bit 8
bit 7-3 bit 2-1
Unimplemented: Read as `0' CH123NB[1:0]: Channel 1, 2, 3 Negative Input Select for Sample MUXB bits In 12-Bit Mode (AD21B = 1), CH123NB is Unimplemented and is Read as `0':
Value
11 10(1,2) 0x
CH1
AN9 OA3/AN6
VREFL
ADC Channel CH2 AN10 AN7 VREFL
CH3
AN11 AN8 VREFL
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample MUXB bit In 12-Bit Mode (AD21B = 1), CH123SB is Unimplemented and is Read as `0':
Value
1(2) 0(1,2)
CH1
OA1/AN3 OA2/AN0
ADC Channel CH2
OA2/AN0 AN1
CH3
OA3/AN6 AN2
Unimplemented: Read as `0' CH123NA[1:0]: Channel 1, 2, 3 Negative Input Select for Sample MUXA bits In 12-Bit Mode (AD21B = 1), CH123NA is Unimplemented and is Read as `0':
Value
CH1
ADC Channel CH2
CH3
11 10(1,2)
0x
AN9 OA3/AN6
VREFL
AN10 AN7 VREFL
AN11 AN8 VREFL
Note 1: 2:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.
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REGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNELS 1, 2, 3 SELECT REGISTER (CONTINUED)
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample MUXA bit
In 12-bit mode (AD21B = 1), CH123SA is Unimplemented and is Read as `0':
Value
1(2) 0(1,2)
CH1
OA1/AN3 OA2/AN0
ADC Channel CH2
OA2/AN0 AN1
CH3
OA3/AN6 AN2
Note 1: 2:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.
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REGISTER 23-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
CH0NB
--
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
--
CH0SB[4:0](1)
R/W-0 bit 8
R/W-0
U-0
CH0NA
--
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
CH0SA[4:0](1)
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-13 bit 12-8
bit 7 bit 6-5
CH0NB: Channel 0 Negative Input Select for Sample MUXB bit 1 = Channel 0 negative input is AN1(1) 0 = Channel 0 negative input is VREFL
Unimplemented: Read as `0' CH0SB[4:0]: Channel 0 Positive Input Select for Sample MUXB bits(1)
11111 = Open; use this selection with CTMU capacitive and time measurement 11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP) 11101 = Reserved 11100 = Reserved 11011 = Reserved 11010 = Channel 0 positive input is the output of OA3/AN6(2,3) 11001 = Channel 0 positive input is the output of OA2/AN0(2) 11000 = Channel 0 positive input is the output of OA1/AN3(2) 10111 = Reserved · · · 10000 = Reserved 01111 = Channel 0 positive input is AN15(3) 01110 = Channel 0 positive input is AN14(3) 01101 = Channel 0 positive input is AN13(3) · · · 00010 = Channel 0 positive input is AN2(3) 00001 = Channel 0 positive input is AN1(3) 00000 = Channel 0 positive input is AN0(3)
CH0NA: Channel 0 Negative Input Select for Sample MUXA bit 1 = Channel 0 negative input is AN1(1) 0 = Channel 0 negative input is VREFL
Unimplemented: Read as `0'
Note 1:
2: 3:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.
See the "Pin Diagrams" section for the available analog channels for each device.
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REGISTER 23-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED)
bit 4-0
CH0SA[4:0]: Channel 0 Positive Input Select for Sample MUXA bits(1)
11111 = Open; use this selection with CTMU capacitive and time measurement 11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP) 11101 = Reserved 11100 = Reserved 11011 = Reserved 11010 = Channel 0 positive input is the output of OA3/AN6(2,3) 11001 = Channel 0 positive input is the output of OA2/AN0(2) 11000 = Channel 0 positive input is the output of OA1/AN3(2) 10110 = Reserved ·
·
·
10000 = Reserved 01111 = Channel 0 positive input is AN15(1,3) 01110 = Channel 0 positive input is AN14(1,3) 01101 = Channel 0 positive input is AN13(1,3) ·
·
· 00010 = Channel 0 positive input is AN2(1,3) 00001 = Channel 0 positive input is AN1(1,3) 00000 = Channel 0 positive input is AN0(1,3)
Note 1:
2: 3:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.
See the "Pin Diagrams" section for the available analog channels for each device.
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REGISTER 23-7: AD1CSSH: ADC1 INPUT SCAN SELECT REGISTER HIGH(1)
R/W-0
R/W-0
U-0
CSS31
CSS30
--
bit 15
U-0
U-0
R/W-0
R/W-0
--
--
CSS26(2)
CSS25(2)
R/W-0 CSS24(2)
bit 8
U-0 -- bit 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7-0
CSS31: ADC1 Input Scan Selection bit
1 = Selects CTMU capacitive and time measurement for input scan (Open) 0 = Skips CTMU capacitive and time measurement for input scan (Open)
CSS30: ADC1 Input Scan Selection bit
1 = Selects CTMU on-chip temperature measurement for input scan (CTMU TEMP) 0 = Skips CTMU on-chip temperature measurement for input scan (CTMU TEMP)
Unimplemented: Read as `0' CSS26: ADC1 Input Scan Selection bit(2)
1 = Selects OA3/AN6 for input scan 0 = Skips OA3/AN6 for input scan CSS25: ADC1 Input Scan Selection bit(2)
1 = Selects OA2/AN0 for input scan 0 = Skips OA2/AN0 for input scan CSS24: ADC1 Input Scan Selection bit(2)
1 = Selects OA1/AN3 for input scan 0 = Skips OA1/AN3 for input scan
Unimplemented: Read as `0'
Note 1: 2:
All AD1CSSH bits can be selected by user software. However, inputs selected for scan, without a corresponding input on the device, convert VREFL.
The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.
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REGISTER 23-8: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2,3)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
CSS[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
CSS[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
CSS[15:0]: ADC1 Input Scan Selection bits
1 = Selects ANx for input scan 0 = Skips ANx for input scan
Note 1: 2: 3:
On devices with less than 16 analog inputs, all AD1CSSL bits can be selected by the user. However, inputs selected for scan, without a corresponding input on the device, convert VREFL.
CSSx = ANx, where x = 0-15. The outputs for Op Amps 1, 2 and 3 can be scanned by selecting analog inputs, AN3, AN0 and AN6, respectively.
For analog inputs that have op amp output function (OAxOUT), op amp output can be accessed for input scan if the corresponding op amp is selected (OPMODE (CMxCON[10[) = 1); otherwise, the ANx input is used.
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24.0 PERIPHERAL TRIGGER GENERATOR (PTG) MODULE
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Peripheral Trigger Generator (PTG)" (www.microchip.com/DS70000669) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
24.1 Module Introduction
The Peripheral Trigger Generator (PTG) provides a means to schedule complex high-speed peripheral operations that would be difficult to achieve using software. The PTG module uses 8-bit commands, called "Steps", that the user writes to the PTG Queue registers (PTGQUE0-PTGQUE7). The registers perform operations, such as wait for input signal, generate output trigger and wait for timer.
The PTG module has the following major features:
· Multiple Clock Sources · Two 16-Bit General Purpose Timers · Two 16-Bit General Limit Counters · Configurable for Rising or Falling Edge Triggering · Generates Processor Interrupts to Include:
- Four configurable processor interrupts - Interrupt on a Step event in Single-Step mode - Interrupt on a PTG Watchdog Timer time-out · Able to Receive Trigger Signals from these Peripherals: - ADC - PWM - Output Compare - Input Capture - Op Amp/Comparator - INT2 · Able to Trigger or Synchronize to these Peripherals: - Watchdog Timer - Output Compare - Input Capture - ADC - PWM - Op Amp/Comparator
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FIGURE 24-1:
PTG BLOCK DIAGRAM
PTGHOLD PTGADJ
PTGL0[15:0] Step Command
PTGTxLIM[15:0]
PTG General Purpose Timerx
PTGCxLIM[15:0] PTG Loop Counter x
PTGSDLIM[15:0]
PTG Step Delay Timer
16-Bit Data Bus
PTGBTE[15:0] PTGCST[15:0] PTGCON[15:0] PTGDIV[4:0] PTGCLK[2:0]
FP TAD T1CLK T2CLK T3CLK FOSC
PWM OC1 OC2
IC1 CMPx
ADC INT2
Trigger Inputs
Clock Inputs
Step Command
PTGQPTR[4:0]
PTG Control Logic
PTG Interrupts
Trigger Outputs
Step Command
PTGO0 · · ·
PTGO31
Step Command
PTG0IF · · ·
PTG3IF
AD1CHS0[15:0]
PTGQUE0 PTGQUE1 PTGQUE2 PTGQUE3 PTGQUE4 PTGQUE5 PTGQUE6 PTGQUE7
Command Decoder
PTG Watchdog Timer(1)
PTGWDTIF
PTGSTEPIF
Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.
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24.2 PTG Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
24.2.1 KEY RESOURCES
· "Peripheral Trigger Generator" (www.microchip.com/DS70000669) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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24.3 PTG Control Registers
REGISTER 24-1: PTGCST: PTG CONTROL/STATUS REGISTER
R/W-0 PTGEN bit 15
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
--
PTGSIDL PTGTOGL
--
PTGSWT(2) PTGSSEN(3) PTGIVIS
bit 8
R/W-0
HS-0
U-0
U-0
U-0
PTGSTRT PTGWDTO
--
--
--
bit 7
U-0
R/W-0
R/W-0
--
PTGITM1(1) PTGITM0(1)
bit 0
Legend: R = Readable bit -n = Value at POR
HS = Hardware Settable bit
W = Writable bit
U = Unimplemented bit, read as `0'
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12
bit 11 bit 10 bit 9 bit 8
bit 7 bit 6 bit 5-2
PTGEN: Module Enable bit
1 = PTG module is enabled 0 = PTG module is disabled
Unimplemented: Read as `0'
PTGSIDL: PTG Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
PTGTOGL: PTG TRIG Output Toggle Mode bit
1 = Toggles state of the PTGOx for each execution of the PTGTRIG command 0 = Each execution of the PTGTRIG command will generate a single PTGOx pulse determined by the
value in the PTGPWDx bits
Unimplemented: Read as `0' PTGSWT: PTG Software Trigger bit(2)
1 = Triggers the PTG module 0 = No action (clearing this bit will have no effect) PTGSSEN: PTG Enable Single-Step bit(3)
1 = Enables Single-Step mode 0 = Disables Single-Step mode
PTGIVIS: PTG Counter/Timer Visibility Control bit
1 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the current values of their corresponding counter/timer registers (PTGSD, PTGCx, PTGTx)
0 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the value previously written to those limit registers
PTGSTRT: PTG Start Sequencer bit
1 = Starts to sequentially execute commands (Continuous mode) 0 = Stops executing commands
PTGWDTO: PTG Watchdog Timer Time-out Status bit
1 = PTG Watchdog Timer has timed out 0 = PTG Watchdog Timer has not timed out
Unimplemented: Read as `0'
Note 1: 2: 3:
These bits apply to the PTGWHI and PTGWLO commands only. This bit is only used with the PTGCTRL Step command software trigger option. Use of the PTG Single-Step mode is reserved for debugging tools only.
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REGISTER 24-1: PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED)
bit 1-0
PTGITM[1:0]: PTG Input Trigger Command Operating Mode bits(1)
11 = Single level detect with Step delay not executed on exit of command (regardless of the PTGCTRL command)
10 = Single level detect with Step delay executed on exit of command 01 = Continuous edge detect with Step delay not executed on exit of command (regardless of the
PTGCTRL command) 00 = Continuous edge detect with Step delay executed on exit of command
Note 1: 2: 3:
These bits apply to the PTGWHI and PTGWLO commands only. This bit is only used with the PTGCTRL Step command software trigger option. Use of the PTG Single-Step mode is reserved for debugging tools only.
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REGISTER 24-2: PTGCON: PTG CONTROL REGISTER
R/W-0 PTGCLK2 bit 15
R/W-0 PTGCLK1
R/W-0 PTGCLK0
R/W-0 PTGDIV4
R/W-0 PTGDIV3
R/W-0 PTGDIV2
R/W-0 PTGDIV1
R/W-0 PTGDIV0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
PTGPWD3 PTGPWD2 PTGPWD1 PTGPWD0
--
bit 7
R/W-0 PTGWDT2
R/W-0 PTGWDT1
R/W-0 PTGWDT0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-4
bit 3 bit 2-0
PTGCLK[2:0]: Select PTG Module Clock Source bits
111 = Reserved 110 = Reserved 101 = PTG module clock source will be T3CLK 100 = PTG module clock source will be T2CLK 011 = PTG module clock source will be T1CLK 010 = PTG module clock source will be TAD 001 = PTG module clock source will be FOSC 000 = PTG module clock source will be FP
PTGDIV[4:0]: PTG Module Clock Prescaler (divider) bits
11111 = Divide-by-32 11110 = Divide-by-31 · · · 00001 = Divide-by-2 00000 = Divide-by-1
PTGPWD[3:0]: PTG Trigger Output Pulse-Width bits
1111 = All trigger outputs are 16 PTG clock cycles wide 1110 = All trigger outputs are 15 PTG clock cycles wide · · · 0001 = All trigger outputs are 2 PTG clock cycles wide 0000 = All trigger outputs are 1 PTG clock cycle wide
Unimplemented: Read as `0'
PTGWDT[2:0]: Select PTG Watchdog Timer Time-out Count Value bits
111 = Watchdog Timer will time-out after 512 PTG clocks 110 = Watchdog Timer will time-out after 256 PTG clocks 101 = Watchdog Timer will time-out after 128 PTG clocks 100 = Watchdog Timer will time-out after 64 PTG clocks 011 = Watchdog Timer will time-out after 32 PTG clocks 010 = Watchdog Timer will time-out after 16 PTG clocks 001 = Watchdog Timer will time-out after 8 PTG clocks 000 = Watchdog Timer is disabled
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REGISTER 24-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2)
R/W-0 ADCTS4 bit 15
R/W-0 ADCTS3
R/W-0 ADCTS2
R/W-0 ADCTS1
R/W-0 IC4TSS
R/W-0 IC3TSS
R/W-0 IC2TSS
R/W-0 IC1TSS
bit 8
R/W-0 OC4CS bit 7
R/W-0 OC3CS
R/W-0 OC2CS
R/W-0 OC1CS
R/W-0 OC4TSS
R/W-0 OC3TSS
R/W-0 OC2TSS
R/W-0 OC1TSS
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5
ADCTS4: Sample Trigger PTGO15 for ADC bit
1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed
ADCTS3: Sample Trigger PTGO14 for ADC bit
1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed
ADCTS2: Sample Trigger PTGO13 for ADC bit
1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed
ADCTS1: Sample Trigger PTGO12 for ADC bit
1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed
IC4TSS: Trigger/Synchronization Source for IC4 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
IC3TSS: Trigger/Synchronization Source for IC3 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
IC2TSS: Trigger/Synchronization Source for IC2 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
IC1TSS: Trigger/Synchronization Source for IC1 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
OC4CS: Clock Source for OC4 bit
1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed
OC3CS: Clock Source for OC3 bit
1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed
OC2CS: Clock Source for OC2 bit
1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.
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REGISTER 24-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED)
bit 4
OC1CS: Clock Source for OC1 bit
1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed
bit 3
OC4TSS: Trigger/Synchronization Source for OC4 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 2
OC3TSS: Trigger/Synchronization Source for OC3 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 1
OC2TSS: Trigger/Synchronization Source for OC2 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 0
OC1TSS: Trigger/Synchronization Source for OC1 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.
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REGISTER 24-4: PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGT0LIM[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGT0LIM[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGT0LIM[15:0]: PTG Timer0 Limit Register bits General Purpose Timer0 Limit register (effective only with a PTGT0 Step command).
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
REGISTER 24-5: PTGT1LIM: PTG TIMER1 LIMIT REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGT1LIM[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGT1LIM[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGT1LIM[15:0]: PTG Timer1 Limit Register bits General Purpose Timer1 Limit register (effective only with a PTGT1 Step command).
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
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REGISTER 24-6: PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGSDLIM[15:0]: PTG Step Delay Limit Register bits
Holds a PTG Step delay value representing the number of additional PTG clocks between the start of a Step command and the completion of a Step command.
Note 1: 2:
A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register (Step Delay = (PTGSDLIM) + 1).
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
REGISTER 24-7: PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGC0LIM[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGC0LIM[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGC0LIM[15:0]: PTG Counter 0 Limit Register bits
May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the General Purpose Counter 0.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
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REGISTER 24-8: PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGC1LIM[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGC1LIM[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGC1LIM[15:0]: PTG Counter 1 Limit Register bits
May be used to specify the loop count for the PTGJMPC1 Step command or as a limit register for the General Purpose Counter 1.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
REGISTER 24-9: PTGHOLD: PTG HOLD REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGHOLD[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGHOLD[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGHOLD[15:0]: PTG General Purpose Hold Register bits
Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 registers with the PTGCOPY command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
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REGISTER 24-10: PTGADJ: PTG ADJUST REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGADJ[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGADJ[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGADJ[15:0]: PTG Adjust Register bits
This register holds user-supplied data to be added to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 registers with the PTGADD command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
REGISTER 24-11: PTGL0: PTG LITERAL 0 REGISTER(1)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
PTGL0[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
PTGL0[7:0]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
PTGL0[15:0]: PTG Literal 0 Register bits
This register holds the 16-bit value to be written to the AD1CHS0 register with the PTGCTRL Step command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
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REGISTER 24-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
--
PTGQPTR[4:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-5 bit 4-0
Unimplemented: Read as `0' PTGQPTR[4:0]: PTG Step Queue Pointer Register bits This register points to the currently active Step command in the Step queue.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
REGISTER 24-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-7)(1,3)
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
STEP(2x + 1)[7:0](2)
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
STEP(2x)[7:0](2)
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-8 bit 7-0
STEP(2x + 1)[7:0]: PTG Step Queue Pointer Register bits(2) A queue location for storage of the STEP(2x + 1) command byte. STEP(2x)[7:0]: PTG Step Queue Pointer Register bits(2) A queue location for storage of the STEP(2x) command byte.
Note 1:
2: 3:
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).
Refer to Table 24-1 for the Step command encoding.
The Step registers maintain their values on any type of Reset.
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24.4 Step Commands and Format
TABLE 24-1: PTG STEP COMMAND FORMAT
Step Command Byte:
STEPx[7:0]
CMD[3:0]
OPTION[3:0]
bit 7
bit 4 bit 3
bit 0
bit 7-4 CMD[3:0]
Step Command
Command Description
Note 1: 2: 3:
0000 PTGCTRL
Execute control command as described by OPTION[3:0].
0001 PTGADD
Add contents of PTGADJ register to target register as described by OPTION[3:0].
PTGCOPY
Copy contents of PTGHOLD register to target register as described by OPTION[3:0].
001x PTGSTRB
Copy the value contained in CMD[0]:OPTION[3:0] to the CH0SA[4:0] bits (AD1CHS0[4:0]).
0100 PTGWHI
Wait for a low-to-high edge input from the selected PTG trigger input as described by OPTION[3:0].
0101 PTGWLO
Wait for a high-to-low edge input from the selected PTG trigger input as described by OPTION[3:0].
0110 Reserved Reserved.
0111 PTGIRQ
Generate individual interrupt request as described by OPTION3[:0].
100x PTGTRIG
Generate individual trigger output as described by <<CMD[0]:OPTION[3:0]>.
101x PTGJMP
Copy the value indicated in <<CMD[0]:OPTION[3:0]> to the Queue Pointer (PTGQPTR) and jump to that Step queue.
110x PTGJMPC0 PTGC0 = PTGC0LIM: Increment the Queue Pointer (PTGQPTR).
PTGC0 PTGC0LIM: Increment Counter 0 (PTGC0) and copy the value
indicated in <<CMD[0]:OPTION[3:0]> to the Queue Pointer (PTGQPTR), and
jump to that Step queue
111x PTGJMPC1 PTGC1 = PTGC1LIM: Increment the Queue Pointer (PTGQPTR).
PTGC1 PTGC1LIM: Increment Counter 1 (PTGC1) and copy the value
indicated in <<CMD[0]:OPTION[3:0]> to the Queue Pointer (PTGQPTR), and
jump to that Step queue.
All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
Refer to Table 24-2 for the trigger output descriptions.
This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
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TABLE 24-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0
Step
Command
OPTION[3:0]
Option Description
PTGCTRL(1) 0000
Reserved.
0001
Reserved.
0010
Disable Step Delay Timer (PTGSD).
0011
Reserved.
0100
Reserved.
0101
Reserved.
0110
Enable Step Delay Timer (PTGSD).
0111
Reserved.
1000
Start and wait for the PTG Timer0 to match the Timer0 Limit Register.
1001
Start and wait for the PTG Timer1 to match the Timer1 Limit Register.
1010
Reserved.
1011
Wait for the software trigger bit transition from low-to-high before continuing (PTGSWT = 0 to 1).
1100
Copy contents of the Counter 0 register to the AD1CHS0 register.
1101
Copy contents of the Counter 1 register to the AD1CHS0 register.
1110
Copy contents of the Literal 0 register to the AD1CHS0 register.
1111 PTGADD(1) 0000
Generate triggers indicated in the Broadcast Trigger Enable register (PTGBTE).
Add contents of the PTGADJ register to the Counter 0 Limit register (PTGC0LIM).
0001
Add contents of the PTGADJ register to the Counter 1 Limit register (PTGC1LIM).
0010
Add contents of the PTGADJ register to the Timer0 Limit register (PTGT0LIM).
0011
Add contents of the PTGADJ register to the Timer1 Limit register (PTGT1LIM).
0100
Add contents of the PTGADJ register to the Step Delay Limit register (PTGSDLIM).
0101
Add contents of the PTGADJ register to the Literal 0 register (PTGL0).
0110
Reserved.
0111 PTGCOPY(1) 1000
Reserved.
Copy contents of the PTGHOLD register to the Counter 0 Limit register (PTGC0LIM).
1001
Copy contents of the PTGHOLD register to the Counter 1 Limit register (PTGC1LIM).
1010
Copy contents of the PTGHOLD register to the Timer0 Limit register (PTGT0LIM).
1011
Copy contents of the PTGHOLD register to the Timer1 Limit register (PTGT1LIM).
1100
Copy contents of the PTGHOLD register to the Step Delay Limit register (PTGSDLIM).
1101
Copy contents of the PTGHOLD register to the Literal 0 register (PTGL0).
1110
Reserved.
1111
Reserved.
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). 2: Refer to Table 24-2 for the trigger output descriptions.
3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
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TABLE 24-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0
Step
Command
OPTION[3:0]
Option Description
PTGWHI(1) or PTGWLO(1)
0000 0001 0010 0011 0100 0101 0110
PWM Special Event Trigger.(3) PWM master time base synchronization output.(3) PWM1 interrupt.(3) PWM2 interrupt.(3) PWM3 interrupt.(3)
Reserved.
Reserved.
0111
OC1 Trigger event.
1000
OC2 Trigger event.
1001
IC1 Trigger event.
1010
CMP1 Trigger event.
PTGIRQ(1)
1011 1100 1101 1110 1111 0000
CMP2 Trigger event. CMP3 Trigger event. CMP4 Trigger event. ADC conversion done interrupt. INT2 external interrupt. Generate PTG Interrupt 0.
0001
Generate PTG Interrupt 1.
0010
Generate PTG Interrupt 2.
0011
Generate PTG Interrupt 3.
0100 ·
Reserved. ·
·
·
·
·
PTGTRIG(2)
1111 00000 00001
Reserved. PTGO0. PTGO1.
·
·
·
·
·
·
11110
PTGO30.
11111
PTGO31.
Note 1: 2: 3:
All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). Refer to Table 24-2 for the trigger output descriptions. This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
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TABLE 24-2: PTG OUTPUT DESCRIPTIONS
PTG Output Number
PTG Output Description
PTGO0 PTGO1 PTGO2 PTGO3 PTGO4 PTGO5 PTGO6 PTGO7 PTGO8 PTGO9 PTGO10 PTGO11 PTGO12 PTGO13 PTGO14 PTGO15 PTGO16 PTGO17 PTGO18 PTGO19 PTGO20 PTGO21 PTGO22 PTGO23 PTGO24 PTGO25 PTGO26 PTGO27 PTGO28 PTGO29 PTGO30 PTGO31 Note 1:
Trigger/Synchronization Source for OC1 Trigger/Synchronization Source for OC2 Trigger/Synchronization Source for OC3 Trigger/Synchronization Source for OC4 Clock Source for OC1 Clock Source for OC2 Clock Source for OC3 Clock Source for OC4 Trigger/Synchronization Source for IC1 Trigger/Synchronization Source for IC2 Trigger/Synchronization Source for IC3 Trigger/Synchronization Source for IC4 Sample Trigger for ADC Sample Trigger for ADC Sample Trigger for ADC Sample Trigger for ADC PWM Time Base Synchronous Source for PWM(1) PWM Time Base Synchronous Source for PWM(1) Mask Input Select for Op Amp/Comparator Mask Input Select for Op Amp/Comparator Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PTG Output to PPS Input Selection PTG Output to PPS Input Selection This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
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NOTES:
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25.0 OP AMP/COMPARATOR MODULE
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Op Amp/Comparator" (www.microchip.com/DS70000357) in the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices contain up to four comparators, which can be configured in various ways. Comparators, CMP1, CMP2 and CMP3, also have the option to be configured as op amps, with the output being brought to an external pin for gain/filtering connections. As shown in Figure 25-1, individual comparator options are specified by the comparator module's Special Function Register (SFR) control bits.
Note:
Op Amp/Comparator 3 is not available on the dsPIC33EPXXXGP502/MC502/MC202 and PIC24EP256GP/MC202 (28-pin) devices.
These options allow users to:
· Select the edge for trigger and interrupt generation · Configure the comparator voltage reference · Configure output blanking and masking · Configure as a comparator or op amp
(CMP1, CMP2 and CMP3 only)
Note:
Not all op amp/comparator input/output connections are available on all devices. See the "Pin Diagrams" section for available connections.
FIGURE 25-1:
OP AMP/COMPARATOR x MODULE BLOCK DIAGRAM (MODULES 1, 2 AND 3)
CCH[1:0] (CMxCON[1:0])
CxIN1CXIN2-(1)
CxIN1+
00
Op Amp/Comparator(2)
01
VIN-
CMPx
0
VIN+ +
CVREFIN(1)
1
Op Ampx
+
CREF (CMxCON[4])
Blanking Function (see Figure 25-4)
Digital
Filter (see Figure 25-5)
OPMODE (CMxCON[10]) RINT1
CxOUT(1,4) PTG Trigger Input
OAxOUT/ANx(5) OAx/ANx(3) (to ADC)
Note 1: 2: 3:
4: 5:
This input/output is not available as a selection when configured as an op amp (OPMODE (CMxCON[10]) = 1). This module can be configured either as an op amp or a comparator using the OPMODE bit.
When configured as an op amp (OPMODE = 1), the ADC samples the op amp output; otherwise, the ADC samples the ANx pin.
CxOUT is not a predefined pin; instead, it must be mapped to a physical pin using Peripheral Pin Select.
In order to use the op amp function, OAxOUT/ANx, on the relevant pin, set the corresponding TRISx bit to `1' and the ANSELx bit to `1'.
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FIGURE 25-2:
OA1/AN3 OA2/AN0 OA3/AN6
C4IN1-
C4IN1+ CVREFIN
COMPARATOR MODULE BLOCK DIAGRAM (MODULE 4)
CCH[1:0] (CM4CON[1:0])
01
10
11
00
VIN-
CMP4
1
VIN+ +
0 CREF (CMxCON[4])
Blanking
Function (see Figure 25-4)
Digital
Filter (see Figure 25-5)
C4OUT Trigger Output
FIGURE 25-3:
OP AMP/COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD
CVREN
CVRSS = 1(1)
CVRSRC
CVRSS = 0
8R
R
R R R 16 Steps
CVR3 CVR2 CVR1 CVR0
CVRCON[3:0]
VREFSEL (CVRCON[10])
1 CVREFIN
0
CVREF1O
16-to-1 MUX
R
CVR1OE
R
(CVRCON[6])
R
CVRR
8R
AVDD
AVSS
AVSS
CVR2OE (CVRCON[14])
CVREF2O(2)
Note 1: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled. 2: This reference is (AVDD + AVSS)/2.
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FIGURE 25-4:
USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM
SELSRCA[3:0] (CMxMSKSRC[3:0])
MUX B
MUX A
Blanking Signals
MAI MAI
MBI
SELSRCB[3:0]
MCI
(CMxMSKSRC[7:4)
Blanking Signals
MBI
Comparator Output "AND-OR" Function
AND
ANDI
Blanking Logic
To Digital Filter
MAI
HLMS
(CMxMSKCON[15)
MBI
OR MASK
MCI
SELSRCC[3:0] (CMxMSKSRC[11:8)
Blanking
MCI
Signals
CMxMSKCON
MUX C
FIGURE 25-5:
DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM
TxCLK(1,2)
1xx
SYNCO1(3)
010
FP(4)
000
FOSC(4)
001
CFSEL[2:0] (CMxFLTR[6:4])
CFDIV
From Blanking Logic
Digital Filter
CFLTREN (CMxFLTR[3])
1
0
CXOUT
Note 1: 2: 3: 4:
See the Type C Timer Block Diagram (Figure 13-2). See the Type B Timer Block Diagram (Figure 13-1). See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2). See the Oscillator System Diagram (Figure 9-1).
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25.1 Op Amp Application Considerations
There are two configurations to take into consideration when designing with the op amp modules that are available in the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices. Configuration A (see Figure 25-6) takes advantage of the internal connection to the ADC module to route the output of the op amp directly to the ADC for measurement. Configuration B (see Figure 25-7) requires that the designer externally route the output of the op amp (OAxOUT) to a separate analog input pin (ANy) on the device. Table 30-55 in Section 30.0 "Electrical Characteristics" describes the performance characteristics for the op amps, distinguishing between the two configuration types where applicable.
When the op amp output is made available on the corresponding OAxOUT pin, set both the pin's TRISx bit and the corresponding ANSELx bit to `1'.
25.1.1 OP AMP CONFIGURATION A
Figure 25-6 shows a typical inverting amplifier circuit taking advantage of the internal connections from the op amp output to the input of the ADC. The advantage of this configuration is that the user does not need to consume another analog input (ANy) on the device, and allows the user to simultaneously sample all three op amps with the ADC module, if needed. However, the presence of the internal resistance, RINT1, adds an error in the feedback path. Since RINT1 is an internal resistance, in relation to the op amp output (VOAxOUT) and ADC internal connection (VADC), RINT1 must be included in the numerator term of the transfer function. See Table 30-53 in Section 30.0 "Electrical Characteristics" for the typical value of RINT1. Table 30-60 and Table 30-61 in Section 30.0 "Electrical Characteristics" describe the minimum Sample Time (TSAMP) requirements for the ADC module in this configuration. Figure 25-6 also defines the equations that should be used when calculating the expected voltages at points, VADC and VOAXOUT.
FIGURE 25-6:
OP AMP CONFIGURATION A
RFEEDBACK(2)
R1 VIN Bias Voltage(4)
CxIN1CxIN1+
Op Ampx +
VADC
ADC(3)
RINT1(1) OAx (to ADC)
OAxOUT (VOAXOUT)
VADC
=
R----F----E---E---D----B---A--R-C---1-K----+-----R----I--N---T---1-
Bias Voltage VIN
VOAxOUT
=
R----F----E---E--R-D--1--B---A---C----K-
Bias Voltage VIN
Note 1: 2: 3: 4:
See Table 30-53 for the Typical value. See Table 30-53 for the Minimum value for the feedback resistor. See Table 30-60 and Table 30-61 for the minimum Sample Time (TSAMP). CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps.
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25.1.2 OP AMP CONFIGURATION B
Figure 25-7 shows a typical inverting amplifier circuit with the output of the op amp (OAxOUT) externally routed to a separate analog input pin (ANy) on the device. This op amp configuration is slightly different in terms of the op amp output and the ADC input connection, therefore, RINT1 is not included in the transfer function. However, this configuration requires the designer to externally route the op amp output (OAxOUT) to another analog input pin (ANy). See Table 30-53 in Section 30.0 "Electrical Characteristics" for the typical value of RINT1.
Table 30-60 and Table 30-61 in Section 30.0 "Electrical Characteristics" describe the minimum Sample Time (TSAMP) requirements for the ADC module in this configuration.
Figure 25-7 also defines the equation to be used to calculate the expected voltage at point VOAXOUT. This is the typical inverting amplifier equation.
Table 25-1 is a summary of the availability of the comparators (1 to 4) and the op amp (1 to 3) for the different packages.
TABLE 25-1: OP AMP/COMPARATOR ANALYSIS
28-Pin (SOIC/SPDIP)
28-Pin (QFN)
36-Pin
44/48-Pin
64-Pin
Comparators/ Op Amps
Reference Comparator Op Amp Comparator Op Amp Comparator Op Amp Comparator Op Amp Comparator Op Amp
Neg Pos Neg Pos Neg Pos Neg Pos Neg Pos Neg Pos Neg Pos Neg Pos Neg Pos Neg Pos
OA1INM1
OA1INM2 Comparator/Op Amp 1
OA1INP
VREF
OA2INM1
OA2INM2 Comparator/Op Amp 2
OA2INP
VREF
OA3INM1
OA3INM2 Comparator/Op Amp 3
OA3INP
VREF
C4INB
OA1OUT
OA2OUT
Comparator 4
OA3OUT/ C4INA
C4INA/ OA3OUT
VREF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend:
X = Available connection; N/A = Unavailable connection (nominal module input not connected to any device pin); Grayed out cells = Op amp functionality not available for Comparator 4
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25.2 Op Amp/Comparator Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
25.2.1 KEY RESOURCES
· "Op Amp/Comparator" (www.microchip.com/ DS70000357) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
FIGURE 25-7:
OP AMP CONFIGURATION B
RFEEDBACK(2)
VIN
R1
CxIN1-
Bias Voltage(4)
CxIN1+
Op Ampx +
RINT1(1)
OAxOUT (VOAXOUT)
ADC(3)
ANy
VOAxOUT
=
R----F----E---E--R-D--1--B---A---C----K-
Bias Voltage VIN
Note 1: 2: 3: 4:
See Table 30-53 for the Typical value. See Table 30-53 for the Minimum value for the feedback resistor. See Table 30-60 and Table 30-61 for the minimum Sample Time (TSAMP). CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps.
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25.3 Op Amp/Comparator Registers
REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER
R/W-0
U-0
U-0
U-0
R-0
R-0
PSIDL
--
--
--
C4EVT(1)
C3EVT(1)
bit 15
R-0 C2EVT(1)
R-0 C1EVT(1)
bit 8
U-0 -- bit 7
U-0
U-0
U-0
R-0
R-0
R-0
R-0
--
--
--
C4OUT(2)
C3OUT(2)
C2OUT(2) C1OUT(2)
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14-12 bit 11 bit 10 bit 9 bit 8 bit 7-4 bit 3
bit 2
PSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all comparators in Idle mode
Unimplemented: Read as `0' C4EVT: Op Amp/Comparator 4 Event Status bit(1)
1 = Op amp/comparator event occurred 0 = Op amp/comparator event did not occur C3EVT: Comparator 3 Event Status bit(1)
1 = Comparator event occurred 0 = Comparator event did not occur C2EVT: Comparator 2 Event Status bit(1)
1 = Comparator event occurred 0 = Comparator event did not occur C1EVT: Comparator 1 Event Status bit(1)
1 = Comparator event occurred 0 = Comparator event did not occur
Unimplemented: Read as `0' C4OUT: Comparator 4 Output Status bit(2)
When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VIN-
When CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINC3OUT: Comparator 3 Output Status bit(2)
When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VIN-
When CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register, CMxCON[9].
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON[8].
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REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER (CONTINUED)
bit 1
C2OUT: Comparator 2 Output Status bit(2)
When CPOL = 0:
1 = VIN+ > VIN0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 0
C1OUT: Comparator 1 Output Status bit(2)
When CPOL = 0:
1 = VIN+ > VIN0 = VIN+ < VIN-
When CPOL = 1: 1 = VIN+ < VIN-
0 = VIN+ > VIN-
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register, CMxCON[9].
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON[8].
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REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3)(3)
R/W-0
R/W-0
R/W-0
U-0
CON
COE(2)
CPOL
--
bit 15
U-0
R/W-0
R/W-0
--
OPMODE
CEVT
R/W-0 COUT
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
EVPOL1
EVPOL0
--
CREF(1)
--
bit 7
U-0
R/W-0
R/W-0
--
CCH1(1)
CCH0(1)
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-11 bit 10 bit 9
bit 8
CON: Op Amp/Comparator Enable bit
1 = Op amp/comparator is enabled 0 = Op amp/comparator is disabled COE: Comparator Output Enable bit(2)
1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted 0 = Comparator output is not inverted
Unimplemented: Read as `0'
OPMODE: Op Amp/Comparator Operation Mode Select bit
1 = Circuit operates as an op amp 0 = Circuit operates as a comparator
CEVT: Comparator Event bit
1 = Comparator event according to the EVPOL[1:0] settings occurred; disables future triggers and interrupts until the bit is cleared
0 = Comparator event did not occur
COUT: Comparator Output bit
When CPOL = 0 (noninverted polarity): 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1 (inverted polarity): 1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1:
2: 3:
Inputs that are selected and not available will be tied to VSS. See the "Pin Diagrams" section for available inputs for each package.
This output is not available when OPMODE (CMxCON[10]) = 1. CM3CON is not available on 28-pin devices.
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REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3)(3) (CONTINUED)
bit 7-6
bit 5 bit 4 bit 3-2 bit 1-0
EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output.
If CPOL = 0 (noninverted polarity): High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity-selected comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity): High-to-low transition of the comparator output.
If CPOL = 0 (noninverted polarity): Low-to-high transition of the comparator output
00 = Trigger/event/interrupt generation is disabled
Unimplemented: Read as `0' CREF: Comparator Reference Select bit (VIN+ input)(1) 1 = VIN+ input connects to internal CVREFIN voltage(2) 0 = VIN+ input connects to CxIN1+ pin
Unimplemented: Read as `0' CCH[1:0]: Op Amp/Comparator Channel Select bits(1)
11 = Unimplemented 10 = Unimplemented 01 = Inverting input of the comparator connects to the CxIN2- pin(2) 00 = Inverting input of the op amp/comparator connects to the CxIN1- pin
Note 1:
2: 3:
Inputs that are selected and not available will be tied to VSS. See the "Pin Diagrams" section for available inputs for each package.
This output is not available when OPMODE (CMxCON[10]) = 1. CM3CON is not available on 28-pin devices.
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REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CON
COE
CPOL
--
--
--
bit 15
R/W-0 CEVT
R/W-0 COUT
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
EVPOL1
EVPOL0
--
CREF(1)
--
bit 7
U-0
R/W-0
R/W-0
--
CCH1(1)
CCH0(1)
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12-10 bit 9
bit 8
CON: Comparator Enable bit
1 = Comparator is enabled 0 = Comparator is disabled
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted 0 = Comparator output is not inverted
Unimplemented: Read as `0'
CEVT: Comparator Event bit
1 = Comparator event according to EVPOL[1:0] settings occurred; disables future triggers and interrupts until the bit is cleared
0 = Comparator event did not occur
COUT: Comparator Output bit
When CPOL = 0 (noninverted polarity): 1 = VIN+ > VIN0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity): 1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1: Inputs that are selected and not available will be tied to VSS. See the "Pin Diagrams" section for available inputs for each package.
2: This input pin is not available in 28-pin devices. Refer to Table 25-1.
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REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER (CONTINUED)
bit 7-6
EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output.
If CPOL = 0 (noninverted polarity): High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity): High-to-low transition of the comparator output.
If CPOL = 0 (noninverted polarity): Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as `0'
bit 4
CREF: Comparator Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to internal CVREFIN voltage 0 = VIN+ input connects to C4IN1+ pin
bit 3-2 bit 1-0
Unimplemented: Read as `0'
CCH[1:0]: Comparator Channel Select bits(1)
11 = VIN- input of comparator connects to OA3/AN6(2) 10 = VIN- input of comparator connects to OA2/AN0 01 = VIN- input of comparator connects to OA1/AN3 00 = VIN- input of comparator connects to C4IN1-(2)
Note 1: Inputs that are selected and not available will be tied to VSS. See the "Pin Diagrams" section for available inputs for each package.
2: This input pin is not available in 28-pin devices. Refer to Table 25-1.
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REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER
U-0 -- bit 15
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
RW-0
--
--
--
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0
bit 8
R/W-0 SELSRCB3 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3
R/W-0 SELSRCA2
R/W-0 SELSRCA1
R/W-0 SELSRCA0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-12 bit 11-8
bit 7-4
Unimplemented: Read as `0'
SELSRCC[3:0]: Mask C Input Select bits
1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L
SELSRCB[3:0]: Mask B Input Select bits
1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L
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REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER (CONTINUED)
bit 3-0
SELSRCA[3:0]: Mask A Input Select bits
1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L
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REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER
R/W-0 HLMS bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
--
OCEN
OCNEN
OBEN
OBNEN
R/W-0 OAEN
R/W-0 OANEN
bit 8
R/W-0 NAGS bit 7
R/W-0 PAGS
R/W-0 ACEN
R/W-0 ACNEN
R/W-0 ABEN
R/W-0 ABNEN
R/W-0 AAEN
R/W-0 AANEN
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4
HLMS: High or Low-Level Masking Select bits
1 = The masking (blanking) function will prevent any asserted (`0') comparator signal from propagating 0 = The masking (blanking) function will prevent any asserted (`1') comparator signal from propagating
Unimplemented: Read as `0'
OCEN: OR Gate C Input Enable bit
1 = MCI is connected to OR gate 0 = MCI is not connected to OR gate
OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate 0 = Inverted MCI is not connected to OR gate
OBEN: OR Gate B Input Enable bit
1 = MBI is connected to OR gate 0 = MBI is not connected to OR gate
OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate 0 = Inverted MBI is not connected to OR gate
OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate 0 = MAI is not connected to OR gate
OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate 0 = Inverted MAI is not connected to OR gate
NAGS: AND Gate Output Inverted Enable bit 1 = Inverted ANDI is connected to OR gate 0 = Inverted ANDI is not connected to OR gate
PAGS: AND Gate Output Enable bit 1 = ANDI is connected to OR gate 0 = ANDI is not connected to OR gate
ACEN: AND Gate C Input Enable bit
1 = MCI is connected to AND gate 0 = MCI is not connected to AND gate
ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate 0 = Inverted MCI is not connected to AND gate
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REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER (CONTINUED)
bit 3
ABEN: AND Gate B Input Enable bit
1 = MBI is connected to AND gate 0 = MBI is not connected to AND gate
bit 2
ABNEN: AND Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate 0 = Inverted MBI is not connected to AND gate
bit 1
AAEN: AND Gate A Input Enable bit
1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate
bit 0
AANEN: AND Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate
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REGISTER 25-6: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
--
--
--
--
--
--
--
bit 15
U-0 --
bit 8
U-0 -- bit 7
R/W-0 CFSEL2
R/W-0 CFSEL1
R/W-0 CFSEL0
R/W-0 CFLTREN
R/W-0 CFDIV2
R/W-0 CFDIV1
R/W-0 CFDIV0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-7 bit 6-4
bit 3 bit 2-0
Unimplemented: Read as `0'
CFSEL[2:0]: Comparator Filter Input Clock Select bits 111 = T5CLK(1) 110 = T4CLK(2) 101 = T3CLK(1) 100 = T2CLK(2) 011 = Reserved 010 = SYNCO1(3) 001 = FOSC(4) 000 = FP(4)
CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled 0 = Digital filter is disabled
CFDIV[2:0]: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128 110 = Clock Divide 1:64 101 = Clock Divide 1:32 100 = Clock Divide 1:16 011 = Clock Divide 1:8 010 = Clock Divide 1:4 001 = Clock Divide 1:2 000 = Clock Divide 1:1
Note 1: 2: 3: 4:
See the Type C Timer Block Diagram (Figure 13-2). See the Type B Timer Block Diagram (Figure 13-1). See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2). See the Oscillator System Diagram (Figure 9-1).
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REGISTER 25-7: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- bit 15
R/W-0
U-0
CVR2OE(1)
--
U-0
U-0
R/W-0
U-0
--
--
VREFSEL
--
U-0 --
bit 8
R/W-0 CVREN bit 7
R/W-0 CVR1OE(1)
R/W-0 CVRR
R/W-0 CVRSS(2)
R/W-0 CVR3
R/W-0 CVR2
R/W-0 CVR1
R/W-0 CVR0
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15 bit 14
bit 13-11 bit 10
bit 9-8 bit 7
bit 6
bit 5
bit 4
bit 3-0
Unimplemented: Read as `0' CVR2OE: Comparator Voltage Reference 2 Output Enable bit(1)
1 = (AVDD AVSS)/2 is connected to the CVREF2O pin 0 = (AVDD AVSS)/2 is disconnected from the CVREF2O pin
Unimplemented: Read as `0'
VREFSEL: Comparator Voltage Reference Select bit
1 = CVREFIN = VREF+ 0 = CVREFIN is generated by the resistor network
Unimplemented: Read as `0'
CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on 0 = Comparator voltage reference circuit is powered down CVR1OE: Comparator Voltage Reference 1 Output Enable bit(1)
1 = Voltage level is output on the CVREF1O pin 0 = Voltage level is disconnected from then CVREF1O pin
CVRR: Comparator Voltage Reference Range Selection bit
1 = CVRSRC/24 step-size 0 = CVRSRC/32 step-size CVRSS: Comparator Voltage Reference Source Selection bit(2)
1 = Comparator voltage reference source, CVRSRC = (VREF+) (AVSS) 0 = Comparator voltage reference source, CVRSRC = AVDD AVSS
CVR[3:0] Comparator Voltage Reference Value Selection 0 CVR[3:0] 15 bits
When CVRR = 1: CVREFIN = (CVR[3:0]/24) (CVRSRC)
When CVRR = 0: CVREFIN = (CVRSRC/4) + (CVR[3:0]/32) (CVRSRC)
Note 1: The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs or outputs must have their corresponding ANSELx and TRISx bits set.
2: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled.
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26.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR
Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to "Programmable Cyclic Redundancy Check (CRC)" (www.microchip.com/DS70346) of the "dsPIC33/PIC24 Family Reference Manual".
2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 26-1:
CRC BLOCK DIAGRAM
The programmable CRC generator offers the following features:
· User-Programmable (up to 32nd order) Polynomial CRC Equation
· Interrupt Output · Data FIFO
The programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. It offers the following features:
· User-Programmable CRC Polynomial Equation, Up to 32 Bits
· Programmable Shift Direction (little or big-endian) · Independent Data and Polynomial Lengths · Configurable Interrupt Output · Data FIFO
A simplified block diagram of the CRC generator is shown in Figure 26-1. A simple version of the CRC shift engine is shown in Figure 26-2.
CRCDATH
CRCDATL
2 * FP Shift Clock
Variable FIFO (4x32, 8x16 or 16x8)
FIFO Empty Event
Shift Buffer 0 1 LENDIAN
CRCISEL 1 Set CRCIF 0
CRC Shift Engine
Shift Complete Event
CRCWDATH CRCWDATL
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FIGURE 26-2:
CRC SHIFT ENGINE DETAIL
Shift Buffer Data
CRCWDATH Read/Write Bus
X(1)(1)
Bit 0
Bit 1
CRCWDATL
X(2)(1) Bit 2
X(n)(1) Bit n(2)
Note 1: Each XOR stage of the shift engine is programmable. See text for details. 2: Polynomial length n is determined by ([PLEN[4:0]] + 1).
26.1 Overview
The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN[4:0] bits (CRCCON2[4:0]).
The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation; functionally, this includes an XOR operation on the corresponding bit in the CRC engine. Clearing the bit disables the XOR.
For example, consider two CRC polynomials, one a 16-bit equation and the other a 32-bit equation:
x16 + x12 + x5 + 1
and
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
To program these polynomials into the CRC generator, set the register bits as shown in Table 26-1.
Note that the appropriate positions are set to `1' to indicate that they are used in the equation (for example, X26 and X23). The 0 bit required by the equation is always XORed; thus, X0 is a don't care. For a polynomial of length N, it is assumed that the Nth bit will always be used, regardless of the bit setting. Therefore, for a polynomial length of 32, there is no 32nd bit in the CRCxOR register.
TABLE 26-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL
CRC Control Bits
Bit Values
16-Bit Polynomial
32-Bit Polynomial
PLEN[4:0] X[31:16]
X[15:0]
01111
0000 0000 0000 000x
0001 0000 0010 000x
11111
0000 0100 1100 0001
0001 1101 1011 011x
26.2 Programmable CRC Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information.
Note:
In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464
26.2.1 KEY RESOURCES
· "Programmable Cyclic Redundancy Check (CRC)" (www.microchip.com/DS70346) in the "dsPIC33/PIC24 Family Reference Manual"
· Code Samples · Application Notes · Software Libraries · Webinars · All Related "dsPIC33/PIC24 Family Reference
Manual" Sections · Development Tools
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26.3 Programmable CRC Registers
REGISTER 26-1: CRCCON1: CRC CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R-0
R-0
CRCEN
--
CSIDL
VWORD4 VWORD3
bit 15
R-0 VWORD2
R-0 VWORD1
R-0 VWORD0
bit 8
R-0
R-1
R/W-0
R/W-0
R/W-0
U-0
CRCFUL
CRCMPT CRCISEL CRCGO LENDIAN
--
bit 7
U-0
U-0
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15
bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0
CRCEN: CRC Enable bit
1 = CRC module is enabled 0 = CRC module is disabled; all state machines, pointers and CRCWDAT/CRCDAT are reset, other
SFRs are not reset
Unimplemented: Read as `0'
CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode
VWORD[4:0]: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN[4:0] > 7 or 16 when PLEN[4:0] 7.
CRCFUL: CRC FIFO Full bit
1 = FIFO is full 0 = FIFO is not full
CRCMPT: CRC FIFO Empty Bit
1 = FIFO is empty 0 = FIFO is not empty
CRCISEL: CRC Interrupt Selection bit
1 = Interrupt on FIFO is empty; final word of data is still shifting through CRC 0 = Interrupt on shift is complete and CRCWDAT results are ready
CRCGO: Start CRC bit
1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off
LENDIAN: Data Word Little-Endian Configuration bit
1 = Data word is shifted into the CRC starting with the LSb (little-endian) 0 = Data word is shifted into the CRC starting with the MSb (big-endian)
Unimplemented: Read as `0'
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REGISTER 26-2: CRCCON2: CRC CONTROL REGISTER 2
U-0 -- bit 15
U-0
U-0
R/W-0
R/W-0
--
--
R/W-0 DWIDTH[4:0]
R/W-0
R/W-0 bit 8
U-0 -- bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
--
--
PLEN[4:0]
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-13 bit 12-8
bit 7-5 bit 4-0
Unimplemented: Read as `0' DWIDTH[4:0]: Data Width Select bits These bits set the width of the data word (DWIDTH[4:0] + 1). Unimplemented: Read as `0' PLEN[4:0]: Polynomial Length Select bits These bits set the length of the polynomial (Polynomial Length = PLEN[4:0] + 1).
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REGISTER 26-3: CRCXORH: CRC XOR POLYNOMIAL HIGH REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
X[31:24]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0
R/W-0
X[23:16]
R/W-0
R/W-0
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-0
X[31:16]: XOR of Polynomial Term Xn Enable bits
REGISTER 26-4: CRCXORL: CRC XOR POLYNOMIAL LOW REGISTER
R/W-0 bit 15
R/W-0
R/W-0
R/W-0
R/W-0
X[15:8]
R/W-0
R/W-0
R/W-0 bit 8
R/W-0 bit 7
R/W-0
R/W-0
R/W-0 X[7:1]
R/W-0
R/W-0
R/W-0
U-0 --
bit 0
Legend: R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 15-1 bit 0
X[15:1]: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as `0'
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NOTES:
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27.0 SPECIAL FEATURES
Note:
This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "dsPIC33/PIC24 Family Reference Manual", which is available from the Microchip website (www.microchip.com).
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are:
· Flexible Configuration · Watchdog Timer (WDT)
· Code Protection and CodeGuardTM Security · JTAG Boundary Scan Interface · In-Circuit Serial ProgrammingTM (ICSPTM)
· In-Circuit Emulation
27.1 Configuration Bits
In dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices, the Configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data are stored at the top of the on-chip program memory space, known as the Flash Configuration bytes. Their specific locations are shown in Table 27-1. The configuration data are automatically loaded from the Flash Configuration bytes to the proper Configuration Shadow registers during device Resets.
Note: Configuration data are reloaded on all types of device Resets.
When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration bytes for configuration data in their code for the compiler. This is to make certain that program code is not stored in this address when the code is compiled.
The upper 2 bytes of all Flash Configuration Words in program memory should always be `1111 1111 1111 1111'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation.
Note:
Performing a page erase operation on the last page of program memory clears the Flash Configuration bytes, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory.
The Configuration Flash bytes map is shown in Table 27-1.
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TABLE 27-1: CONFIGURATION BYTE REGISTER MAP
File Name
Address
Device Memory
Size (Kbytes)
Bits 23-8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved 0057EC 32
00AFEC 64
0157EC 128
--
--
--
--
--
--
--
--
--
02AFEC 256
0557EC 512
Reserved 0057EE 32
00AFEE 64
0157EE 128
--
--
--
--
--
--
--
--
--
02AFEE 256
0557EE 512
FICD
0057F0
32
00AFF0 64 0157F0 128
--
Reserved(3)
--
JTAGEN Reserved(2) Reserved(3)
--
ICS[1:0]
02AFF0 256
0557F0 512
FPOR
0057F2
32
00AFF2 64
0157F2 128
--
WDTWIN[1:0]
ALTI2C2 ALTI2C1 Reserved(3)
--
--
--
02AFF2 256
0557F2 512
FWDT
0057F4
32
00AFF4 64
0157F4 128
--
FWDTEN
WINDIS
PLLKEN WDTPRE
WDTPOST[3:0]
02AFF4 256
0557F4 512
FOSC
0057F6
32
00AFF6 64
0157F6 128
--
FCKSM[1:0]
IOL1WAY
--
--
OSCIOFNC
POSCMD[1:0]
02AFF6 256
0557F6 512
FOSCSEL 0057F8
32
00AFF8 64
0157F8 128
--
IESO PWMLOCK(1)
--
--
--
FNOSC[2:0]
02AFF8 256
0557F8 512
FGS
0057FA
32
00AFFA 64
0157FA 128
--
--
--
--
--
--
--
GCP
GWRP
02AFFA 256
0557FA 512
Reserved 0057FC 32
00AFFC 64
0157FC 128
--
--
--
--
--
--
--
--
--
02AFFC 256
0557FC 512
Reserved 057FFE 32
00AFFE 64
0157FE 128
--
--
--
--
--
--
--
--
--
02AFFE 256
0557FE 512
Legend: -- = unimplemented, read as `1'. Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: This bit is reserved and must be programmed as `0'. 3: These bits are reserved and must be programmed as `1'.
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TABLE 27-2: CONFIGURATION BITS DESCRIPTION
Bit Field
Description
GCP
General Segment Code-Protect bit
1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space
GWRP
General Segment Write-Protect bit
1 = User program memory is not write-protected 0 = User program memory is write-protected
IESO PWMLOCK(1)
Two-Speed Oscillator Start-up Enable bit 1 = Start up device with FRC, then automatically switch to the user-selected oscillator
source when ready 0 = Start up device with user-selected oscillator source
PWM Lock Enable bit 1 = Certain PWM registers may only be written after a key sequence 0 = PWM registers may be written without a key sequence
FNOSC[2:0]
Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN) 110 = Reserved; do not use 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved; do not use 011 = Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC)
FCKSM[1:0]
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations
OSCIOFNC
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output 0 = OSC2 is a general purpose digital I/O pin
POSCMD[1:0]
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode
FWDTEN
Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC Oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode
PLLKEN
PLL Lock Enable bit
1 = PLL lock is enabled 0 = PLL lock is disabled
Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins
other than TMS for this purpose.
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TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
WDTPRE
Watchdog Timer Prescaler bit
1 = 1:128 0 = 1:32
WDTPOST[3:0]
Watchdog Timer Postscaler bits
1111 = 1:32,768 1110 = 1:16,384
·
·
·
0001 = 1:2 0000 = 1:1
WDTWIN[1:0]
Watchdog Window Select bits
11 = WDT window is 25% of WDT period 10 = WDT window is 37.5% of WDT period 01 = WDT window is 50% of WDT period 00 = WDT window is 75% of WDT period
ALTI2C1
Alternate I2C1 pin
1 = I2C1 is mapped to the SDA1/SCL1 pins 0 = I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2 JTAGEN(2)
Alternate I2C2 pin 1 = I2C2 is mapped to the SDA2/SCL2 pins 0 = I2C2 is mapped to the ASDA2/ASCL2 pins
JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled
ICS[1:0]
ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use
Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to
JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins other than TMS for this purpose.
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REGISTER 27-1: FGS CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 15
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
R/W-1
R/W-1
--
--
--
--
--
--
GCP
GWRP
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
PO = Program Once bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 23-8 bit 7-2 bit 1
bit 0
Unimplemented: Read as `1'
Unused: Reads contents of Flash Configuration Words
GCP: General Segment Code Flash Protection Level bit 1 = General Segment has no security 0 = General Segment has high security
GWRP: General Segment Program Flash Write Protection bit 1 = General Segment is not write-protected 0 = General Segment is write-protected
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REGISTER 27-2: FICD CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 15
bit 8
r-1
U-1
R/PO-1
U-1
U-1
U-1
R/PO-1
R/PO-1
--
--
JTAGEN
--
--
--
ICS[1:0]
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
PO = Program Once bit W = Writable bit `1' = Bit is set
r = Reserved bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 23-8 bit 7 bit 6 bit 5
bit 4-2 bit 1-0
Unimplemented: Read as `1'
Reserved: Maintain as `1'
Unimplemented: Read as `1'
JTAGEN: JTAG Enable bit
1 = JTAG port is enabled 0 = JTAG port is disabled
Unimplemented: Read as `1'
ICS[1:0]: ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1 10 = Communicates on PGEC2 and PGED2 01 = Communicates on PGEC3 and PGED3 00 = Reserved, do not use
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REGISTER 27-3: FOSC CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 15
bit 8
RW-1
R/W-1
R/W-0
U-1
FCKSM[1:0]
IOL1WAY
--
bit 7
U-1
R/W-0
R/W-0
R/W-0
--
OSCIOFNC
POSCMD[1:0]
bit 0
Legend: R = Readable bit -n = Value at POR
PO = Program Once bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 23-8 bit 7-6
bit 5
bit 4-3 bit 2
bit 1-0
Unimplemented: Read as `1'
FCKSM[1:0]: Clock Switching and Monitor Selection bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY: IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON[6]) can be set and cleared as needed (provided an unlocking sequence is executed)
0 = The IOLOCK bit (OSCCON[6]) can only be set once (provided an unlocking sequence is executed); once IOLOCK is set, this prevents any possible RP register changes
Unused: Reads contents of Flash Configuration Words
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal is active on the OSC2 pin; Primary Oscillator must be disabled or configured for the External Clock (EC) mode for the CLKO to be active (POSCMD[1:0] = 11 or 00)
0 = CLKO output is disabled
POSCMD[1:0]: Primary Oscillator Configuration bits
11 = Primary Oscillator is disabled 10 = HS Oscillator mode selected (10 MHz-40 MHz) 01 = MS Oscillator mode selected (3.5 MHz-10 MHz) 00 = External Clock mode selected
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REGISTER 27-4: FOSCSEL CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 15
bit 8
RW-0
R/W-0
U-1
U-1
U-1
R/W-0
R/W-1
R/W-0
IESO
PWMLOCK
--
--
--
FNOSC[2:0]
bit 7
bit 0
Legend: R = Readable bit -n = Value at POR
PO = Program Once bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 23-8 bit 7
bit 6
bit 5-3 bit 2-0
Unimplemented: Read as `1'
IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled)
PWMLOCK: PWM Lock Enable bit
1 = Certain PWM registers may only be written after key sequence 0 = PWM registers may be written without key
Unused: Reads contents of Flash Configuration Words
FNOSC[2:0]: Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIV) 110 = Reserved; do not use 101 = Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (MS+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (MS, HS, EC) 001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC (FRC) Oscillator
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REGISTER 27-5: FPOR CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 15
bit 8
RW-1
R/W-1
R/W-1
R/W-1
r-1
WDTWIN[1:0]
ALTI2C2
ALTI2C1
--
bit 7
U-1
U-1
U-1
--
--
--
bit 0
Legend: R = Readable bit -n = Value at POR
PO = Program Once bit W = Writable bit `1' = Bit is set
r = Reserved bit
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 23-8 bit 7-6
bit 5 bit 4 bit 3 bit 2-0
Unimplemented: Read as `1'
WDTWIN[1:0]: Watchdog Timer Window Select bits
11 = WDT window is 25% of WDT period 10 = WDT window is 37.5% of WDT period 01 = WDT window is 50% of WDT period 00 = WDT window is 75% of WDT period
ALTI2C2: Alternate I2C2 Pin Mapping bit
1 = Default location for SCL2/SDA2 pins 0 = Alternate location for SCL2/SDA2 pins (ASCL2/ASDA2)
ALTI2C1: Alternate I2C1 Pin Mapping bit
1 = Default location for SCL1/SDA1 pins 0 = Alternate location for SCL1/SDA1 pins (ASCL1/ASDA1)
Reserved: Read as `1'
Unused: Reads contents of Flash Configuration Words
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REGISTER 27-6: FWDT CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
--
--
--
--
--
--
--
--
bit 15
bit 8
RW-0 FWDTEN bit 7
R/W-0 WINDIS
R/W-1 PLLKEN
R/W-0 WDTPRE
R/W-0
R/W-0
R/W-0
WDTPOST[3:0]
R/W-0 bit 0
Legend: R = Readable bit -n = Value at POR
PO = Program Once bit W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0'
`0' = Bit is cleared
x = Bit is unknown
bit 23-8 bit 7 bit 6
bit 5 bit 4 bit 3-0
Unimplemented: Read as `1'
FWDTEN: Watchdog Timer Enable bit
1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit)
WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard WDT selected; windowed WDT is disabled 0 = Windowed WDT is enabled; note that executing a CLRWDT instruction while the WDT is disabled
in hardware and software (FWDTEN = 0; SWDTEN = 0) will not cause a device Reset
PLLKEN: PLL Lock Enable bit
1 = PLL lock is enabled 0 = PLL lock is disabled
WDTPRE: WDT Prescaler bit
1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32
WDTPOST[3:0]: Watchdog Timer Postscale Select bits
1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1
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REGISTER 27-7: DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
DEVID[23:16](1)
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVID[15:8](1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID[7:0](1)
bit 7
bit 0
Legend: R = Read-Only bit
U = Unimplemented bit
bit 23-0
DEVID[23:0]: Device Identifier bits(1)
Note 1: Refer to the "dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits" (DS70663) for the list of device ID values.
REGISTER 27-8: DEVREV: DEVICE REVISION REGISTER
R bit 23
R
R
R
R
R
DEVREV[23:16](1)
R
R
bit 16
R bit 15
R
R
R
R
R
DEVREV[15:8](1)
R
R
bit 8
R bit 7
R
R
R
R
R
DEVREV[7:0](1)
R
R
bit 0
Legend: R = Read-only bit
U = Unimplemented bit
bit 23-0
DEVREV[23:0]: Device Revision bits(1)
Note 1: Refer to the "dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits" (DS70663) for the list of device revision values.
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27.2 User ID Words
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices contain four User ID Words, located at addresses, 0x800FF8 through 0x800FFE. The User ID Words can be used for storing product information such as serial numbers, system manufacturing dates, manufacturing lot numbers and other application-specific information.
The User ID Words register map is shown in Table 27-3.
TABLE 27-3: USER ID WORDS REGISTER MAP
File Name Address Bits 23-16 Bits 15-0
FUID0 FUID1 FUID2 FUID3 Legend:
0x800FF8
--
UID0
0x800FFA
--
UID1
0x800FFC
--
UID2
0x800FFE
--
UID3
-- = unimplemented, read as `1'.
27.3 On-Chip Voltage Regulator
All
of
the
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X devices power their core digital logic at a
nominal 1.8V. This can create a conflict for designs that
are required to operate at a higher typical voltage, such
as 3.3V. To simplify system design, all devices in the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X family incorporate an on-
chip regulator that allows the device to run its core logic
from VDD.
The regulator provides power to the core from the other VDD pins. A low-ESR (less than 1 Ohm) capacitor (such as tantalum or ceramic) must be connected to the VCAP pin (Figure 27-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 30-5 located in Section 30.0 "Electrical Characteristics".
Note:
It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin.
FIGURE 27-1:
CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3)
3.3V
dsPIC33E/PIC24E
CEFC
VDD VCAP VSS
Note 1: 2: 3:
These are typical operating voltages. Refer to Table 30-5 located in Section 30.1 "DC Characteristics" for the full operating ranges of VDD and VCAP.
It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin.
Typical VCAP pin voltage = 1.8V when VDD VDDMIN.
27.4 Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage, VCAP. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines or voltage sags due to excessive current draw when a large inductive load is turned on).
A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC[2:0] and POSCMD[1:0]).
If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON[5]) is `1'.
Concurrently, the PWRT Time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM is applied. The total delay in this case is TFSCM. Refer to Parameter SY35 in Table 30-22 of Section 30.0 "Electrical Characteristics" for specific TFSCM values.
The BOR status bit (RCON[1]) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage.
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27.5 Watchdog Timer (WDT)
For dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices, the WDT is driven by the LPRC Oscillator. When the WDT is enabled, the clock source is also enabled.
27.5.1 PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a WDT Timeout period (TWDT), as shown in Parameter SY12 in Table 30-22.
A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST[3:0] Configuration bits (FWDT[3:0]), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
· On any device Reset
· On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSCx bits) or by hardware (i.e., Fail-Safe Clock Monitor)
· When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)
· When the device exits Sleep or Idle mode to resume normal operation
· By a CLRWDT instruction during normal execution
Note:
The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts
when executed.
FIGURE 27-2:
WDT BLOCK DIAGRAM
All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction
SWDTEN FWDTEN
LPRC Clock
WDTPRE
RS Prescaler (Divide-by-N1)
27.5.2 SLEEP AND IDLE MODES
If the WDT is enabled, it continues to run during Sleep or Idle modes. When the WDT time-out occurs, the device wakes the device and code execution continues from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bit (RCON[3,2]) needs to be cleared in software after the device wakes up.
27.5.3 ENABLING WDT
The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled.
The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON[5]). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings.
The WDT flag bit, WDTO (RCON[4]), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software.
27.5.4 WDT WINDOW
The Watchdog Timer has an optional Windowed mode, enabled by programming the WINDIS bit in the WDT Configuration register (FWDT[6]). In the Windowed mode (WINDIS = 0), the WDT should be cleared based on the settings in the programmable Watchdog Timer Window select bits (WDTWIN[1:0]).
Watchdog Timer
WDTPOST[3:0]
RS Postscaler
(Divide-by-N2)
Sleep/Idle 1 0
WDT Wake-up WDT Reset
WINDIS WDTWIN[1:0]
WDT Window Select
CLRWDT Instruction
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27.6 JTAG Interface
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices implement a JTAG interface, which supports boundary scan device testing. Detailed information on this interface is provided in future revisions of the document.
Note:
Refer to "Programming and Diagnostics" (www.microchip.com/DS70608) in the "dsPIC33/PIC24 Family Reference Manual" for further information on usage, configuration and operation of the JTAG interface.
27.7 In-Circuit Serial Programming
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X devices can be serially programmed while in the end application circuit. This is done with two lines for clock and data, and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the "dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits" (DS70663) for details about In-Circuit Serial Programming (ICSP).
Any of the three pairs of programming clock/data pins can be used:
· PGEC1 and PGED1
· PGEC2 and PGED2
· PGEC3 and PGED3
27.8 In-Circuit Debugger
When MPLAB® ICD 3 or REAL ICETM is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can be used:
· PGEC1 and PGED1
· PGEC2 and PGED2
· PGEC3 and PGED3
To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins (PGECx and PGEDx).
27.9 Code Protection and CodeGuardTM Security
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X, and PIC24EPXXXGP/MC20X devices offer basic implementation of CodeGuard Security that supports only General Segment (GS) security. This feature helps protect individual Intellectual Property.
Note:
Refer to "CodeGuardTM Security" (www.microchip.com/DS70634) in the "dsPIC33/PIC24 Family Reference Manual" for further information on usage, configuration and operation of CodeGuard Security.
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28.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the "dsPIC33/PIC24 Family Reference Manual", which is available from the Microchip website (www.microchip.com).
The dsPIC33EP instruction set is almost identical to that of the dsPIC30F and dsPIC33F. The PIC24EP instruction set is almost identical to that of the PIC24F and PIC24H.
Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations.
Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
The instruction set is highly orthogonal and is grouped into five basic categories:
· Word or byte-oriented operations
· Bit-oriented operations · Literal operations · DSP operations
· Control operations
Table 28-1 lists the general symbols used in describing the instructions.
The dsPIC33E instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction.
Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands:
· The first source operand, which is typically a register `Wb' without any address modifier
· The second source operand, which is typically a register `Ws' with or without an address modifier
· The destination of the result, which is typically a register `Wd' with or without an address modifier
However, word or byte-oriented file register instructions have two operands:
· The file register specified by the value `f'
· The destination, which could be either the file register `f' or the W0 register, which is denoted as `WREG'
Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands:
· The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f')
· The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb')
The literal instructions that involve data movement can use some of the following operands:
- A literal value to be loaded into a W register or file register (specified by `k')
· The W register or file register where the literal value is to be loaded (specified by `Wb' or `f')
However, literal instructions that involve arithmetic or logical operations use some of the following operands:
· The first source operand, which is a register `Wb' without any address modifier
· The second source operand, which is a literal value
· The destination of the result (only if not the same as the first source operand), which is typically a register `Wd' with or without an address modifier
The MAC class of DSP instructions can use some of the following operands:
· The accumulator (A or B) to be used (required operand)
· The W registers to be used as the two operands · The X and Y address space prefetch operations · The X and Y address space prefetch destinations · The accumulator write back destination
The other DSP instructions do not involve any multiplication and can include:
· The accumulator to be used (required) · The source or destination operand (designated as
Wso or Wdo, respectively) with or without an address modifier · The amount of shift specified by a W register `Wn' or a literal value
The control instructions can use some of the following operands:
· A program memory address · The mode of the Table Read and Table Write
instructions
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Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it executes as a NOP.
The double-word instructions execute in two instruction cycles.
Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the Program Counter is changed as a result of the instruction, or a PSV or Table Read is performed, or an SFR register is read. In these cases, the execution takes multiple instruction cycles with the additional instruction cycle(s) executed as a NOP. Certain instructions that involve skipping over the subsequent instruction require either
two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles.
Note:
For more details on the instruction set, refer to the "16-Bit MCU and DSC Programmer's Reference Manual" (www.microchip.com/DS70000157).
For more information on instructions that take more than one instruction cycle to execute, refer to "CPU" (www.microchip.com/ DS70359) in the "dsPIC33/PIC24 Family Reference Manual", particularly the "Instruction Flow Types" section.
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text (text) [text] { } a {b, c, d} [n:m] .b .d .S .w Acc AWB bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None OA, OB, SA, SB PC Slit10 Slit16 Slit6 Wb Wd Wdo
Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation a is selected from the set of values b, c, d Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) One of two accumulators {A, B} Accumulator write back destination address register {W13, [W13]+ = 2} 4-bit bit selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0x0000...0x1FFF} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSb must be `0' Field does not require an entry, can be blank DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0...W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
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TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm,Wn Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx
Wxd Wy
Wyd
Dividend, Divisor Working register pair (direct addressing)
Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
One of 16 Working registers {W0...W15}
One of 16 destination Working registers {W0...W15}
One of 16 source Working registers {W0...W15}
W0 (Working register used in file register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
X Data Space Prefetch Address register for DSP instructions {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none}
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Y Data Space Prefetch Address register for DSP instructions {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none}
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
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TABLE 28-2: INSTRUCTION SET OVERVIEW
Base
Instr #
Assembly Mnemonic
Assembly Syntax
Description
# of
# of Status Flags
Words Cycles(2) Affected
1
ADD
ADD
Acc(1)
Add Accumulators
1
1
OA,OB,SA,SB
ADD
f
f = f + WREG
1
1
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
OA,OB,SA,SB
2
ADDC
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C,DC,N,OV,Z
3
AND
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
4
ASR
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
5
BCLR
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
6
BRA
BRA
C,Expr
Branch if Carry
1
1 (4)
None
BRA
GE,Expr
Branch if Greater Than or Equal
1
1 (4)
None
BRA
GEU,Expr
Branch if Unsigned Greater Than or Equal 1
1 (4)
None
BRA
GT,Expr
Branch if Greater Than
1
1 (4)
None
BRA
GTU,Expr
Branch if Unsigned Greater Than
1
1 (4)
None
BRA
LE,Expr
Branch if Less Than or Equal
1
1 (4)
None
BRA
LEU,Expr
Branch if Unsigned Less Than or Equal
1
1 (4)
None
BRA
LT,Expr
Branch if Less Than
1
1 (4)
None
BRA
LTU,Expr
Branch if Unsigned Less Than
1
1 (4)
None
BRA
N,Expr
Branch if Negative
1
1 (4)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (4)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (4)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (4)
None
BRA
NZ,Expr
BRA
OA,Expr(1)
BRA
OB,Expr(1)
BRA
OV,Expr(1)
BRA
SA,Expr(1)
BRA
SB,Expr(1)
Branch if Not Zero Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated
1
1 (4)
1
1 (4)
1
1 (4)
1
1 (4)
1
1 (4)
1
1 (4)
None None None None None None
BRA
Expr
Branch Unconditionally
1
4
None
BRA
Z,Expr
Branch if Zero
1
1 (4)
None
BRA
Wn
Computed Branch
1
4
None
7
BSET
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
8
BSW
BSW.C Ws,Wb
Write C bit to Ws[Wb]
1
1
None
BSW.Z Ws,Wb
Write Z bit to Ws[Wb]
1
1
None
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70000657J-page 398
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base Instr
#
Assembly Mnemonic
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles(2) Affected
9
BTG
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
10 BTSC
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
11 BTSS
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
12 BTST
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C Ws,Wb
Bit Test Ws[Wb] to C
1
1
C
BTST.Z Ws,Wb
Bit Test Ws[Wb] to Z
1
1
Z
13 BTSTS
BTSTS f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
14 CALL
CALL
lit23
Call Subroutine
2
4
SFA
CALL
Wn
Call Indirect Subroutine
1
4
SFA
CALL.L Wn
Call Indirect Subroutine (long address)
1
4
SFA
15 CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB(1)
Ws = 0x0000 Clear Accumulator
1
1
None
1
1
OA,OB,SA,SB
16 CLRWDT CLRWDT
Clear Watchdog Timer
1
1
WDTO,Sleep
17 COM
COM
f
f = f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
18 CP
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
CP
Wb,#lit8
Compare Wb with lit8
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb Ws)
1
1
C,DC,N,OV,Z
19 CP0
CP0
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
20 CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit8
Compare Wb with lit8, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow (Wb Ws C)
1
1
C,DC,N,OV,Z
21 CPSEQ
CPSEQ Wb,Wn
Compare Wb with Wn, Skip if =
1
1
(2 or 3)
None
CPBEQ
CPBEQ Wb,Wn,Expr
Compare Wb with Wn, Branch if =
1
1 (5)
None
22 CPSGT
CPSGT Wb,Wn
Compare Wb with Wn, Skip if >
1
1
(2 or 3)
None
CPBGT
CPBGT Wb,Wn,Expr
Compare Wb with Wn, Branch if >
1
1 (5)
None
23 CPSLT
CPSLT Wb,Wn
Compare Wb with Wn, Skip if <
1
1
(2 or 3)
None
CPBLT
CPBLT Wb,Wn,Expr
Compare Wb with Wn, Branch if <
1
1 (5)
None
24 CPSNE
CPSNE Wb,Wn
Compare Wb with Wn, Skip if
1
1
(2 or 3)
None
CPBNE
CPBNE Wb,Wn,Expr
Compare Wb with Wn, Branch if
1
1 (5)
None
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2011-2020 Microchip Technology Inc.
DS70000657J-page 399
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr #
Assembly Mnemonic
Assembly Syntax
Description
# of
# of Status Flags
Words Cycles(2) Affected
25 DAW
DAW
Wn
Wn = Decimal Adjust Wn
1
1
C
26 DEC
DEC
f
f = f 1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws 1
1
1
C,DC,N,OV,Z
27 DEC2
DEC2
f
f = f 2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f 2
1
1
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws 2
1
1
C,DC,N,OV,Z
28 DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles 1
1
None
29 DIV
DIV.S Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
30 DIVF 31 DO
32 ED
DIV.UD DIVF DO DO ED
Wm,Wn Wm,Wn(1) #lit15,Expr(1) Wn,Expr(1) Wm*Wm,Acc,Wx,Wy,Wxd(1)
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
Signed 16/16-bit Fractional Divide
1
18
N,Z,C,OV
Do code to PC + Expr, lit15 + 1 Times
2
2
None
Do code to PC + Expr, (Wn) + 1 Times
2
2
None
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
33 EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd(1)
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34 EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
35 FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
36 FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
37 FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
38 GOTO
GOTO
Expr
Go to Address
2
4
None
GOTO
Wn
Go to Indirect
1
4
None
GOTO.L Wn
Go to Indirect (long address)
1
4
None
39 INC
INC
f
f = f + 1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
40 INC2
INC2
f
f = f + 2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
C,DC,N,OV,Z
41 IOR
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
42 LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
43 LNK
LNK
#lit14
Link Frame Pointer
1
1
SFA
44 LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
45 MAC
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(1) Multiply and Accumulate
1
1
N,Z
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1)
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70000657J-page 400
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr #
Assembly Mnemonic
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles(2) Affected
46 MOV
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
None
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit Literal to Wn
1
1
None
MOV.b #lit8,Wn
Move 8-bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd 1
2
None
MOV.D Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd) 1
2
None
47 MOVPAG MOVPAG #lit10,DSRPAG
Move 10-bit Literal to DSRPAG
1
1
None
MOVPAG #lit9,DSWPAG
Move 9-bit Literal to DSWPAG
1
1
None
MOVPAG #lit8,TBLPAG
Move 8-bit Literal to TBLPAG
1
1
None
MOVPAG Ws, DSRPAG
Move Ws[9:0] to DSRPAG
1
1
None
MOVPAG Ws, DSWPAG
Move Ws[8:0] to DSWPAG
1
1
None
MOVPAG Ws, TBLPAG
48 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB(1)
49 MPY
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1)
Move Ws[7:0] to TBLPAG Prefetch and Store Accumulator Multiply Wm by Wn to Accumulator
1
1
None
1
1
None
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1)
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
50 MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1)
-(Multiply Wm by Wn) to Accumulator
1
51 MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB(1) Multiply and Subtract from Accumulator
1
1
None
1
OA,OB,OAB,
SA,SB,SAB
52 MUL
MUL.SS Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SS Wb,Ws,Acc(1)
Accumulator = signed(Wb) * signed(Ws)
1
1
None
MUL.SU Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
1
1
None
MUL.SU Wb,Ws,Acc(1) MUL.SU Wb,#lit5,Acc(1)
Accumulator = signed(Wb) * unsigned(Ws)
Accumulator = signed(Wb) * unsigned(lit5)
1
1
1
1
None None
MUL.US Wb,Ws,Wnd MUL.US Wb,Ws,Acc(1)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
Accumulator = unsigned(Wb) * signed(Ws)
1
1
1
1
None None
MUL.UU Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws)
1
1
None
MUL.UU Wb,#lit5,Acc(1)
Accumulator = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL.UU Wb,Ws,Acc(1)
Accumulator = unsigned(Wb) * unsigned(Ws)
1
1
None
MULW.SS Wb,Ws,Wnd
Wnd = signed(Wb) * signed(Ws)
1
1
None
MULW.SU Wb,Ws,Wnd
Wnd = signed(Wb) * unsigned(Ws)
1
1
None
MULW.US Wb,Ws,Wnd
Wnd = unsigned(Wb) * signed(Ws)
1
1
None
MULW.UU Wb,Ws,Wnd
Wnd = unsigned(Wb) * unsigned(Ws)
1
1
None
MUL.SU Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
None
MUL.SU Wb,#lit5,Wnd
Wnd = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL.UU Wb,#lit5,Wnd
Wnd = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2011-2020 Microchip Technology Inc.
DS70000657J-page 401
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr #
Assembly Mnemonic
Assembly Syntax
Description
# of
# of Status Flags
Words Cycles(2) Affected
53 NEG
NEG
Acc(1)
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
54 NOP
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
55 POP
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1)
1
2
None
POP.S
Pop Shadow Registers
1
1
All
56 PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D Wns
Push W(ns):W(ns + 1) to Top-of-Stack
1
2
(TOS)
None
PUSH.S
Push Shadow Registers
1
1
None
57 PWRSAV PWRSAV #lit1
Go into Sleep or Idle mode
1
1
WDTO,Sleep
58 RCALL
RCALL Expr
Relative Call
1
4
SFA
RCALL Wn
Computed Call
1
4
SFA
59 REPEAT REPEAT #lit15
Repeat Next Instruction lit15 + 1 Times
1
1
None
REPEAT Wn
Repeat Next Instruction (Wn) + 1 Times
1
1
None
60 RESET
RESET
Software Device Reset
1
1
None
61 RETFIE RETFIE
Return from Interrupt
1
6 (5)
SFA
62 RETLW
RETLW #lit10,Wn
Return with Literal in Wn
1
6 (5)
SFA
63 RETURN RETURN
Return from Subroutine
1
6 (5)
SFA
64 RLC
RLC
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
65 RLNC
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
66 RRC
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
67 RRNC
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
68 SAC
RRNC SAC SAC.R
Ws,Wd Acc,#Slit4,Wdo(1) Acc,#Slit4,Wdo(1)
Wd = Rotate Right (No Carry) Ws Store Accumulator Store Rounded Accumulator
1
1
1
1
1
1
N,Z None None
69 SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C,N,Z
70 SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
71 SFTAC
SETM SFTAC
SFTAC
Ws Acc,Wn(1)
Acc,#Slit6(1)
Ws = 0xFFFF Arithmetic Shift Accumulator by (Wn)
Arithmetic Shift Accumulator by Slit6
1
1
None
1
1
OA,OB,OAB,
SA,SB,SAB
1
1
OA,OB,OAB,
SA,SB,SAB
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70000657J-page 402
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr #
Assembly Mnemonic
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles(2) Affected
72 SL
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
73 SUB
SL
Wb,#lit5,Wnd
SUB
Acc(1)
Wnd = Left Shift Wb by lit5 Subtract Accumulators
1
1
N,Z
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb lit5
1
1
C,DC,N,OV,Z
74 SUBB
SUBB
f
f = f WREG (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f WREG (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn lit10 (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb Ws (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb lit5 (C)
1
1
C,DC,N,OV,Z
75 SUBR
SUBR
f
f = WREG f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 Wb
1
1
C,DC,N,OV,Z
76 SUBBR
SUBBR f
f = WREG f (C)
1
1
C,DC,N,OV,Z
SUBBR f,WREG
WREG = WREG f (C)
1
1
C,DC,N,OV,Z
SUBBR Wb,Ws,Wd
Wd = Ws Wb (C)
1
1
C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd
Wd = lit5 Wb (C)
1
1
C,DC,N,OV,Z
77 SWAP
SWAP.b Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
78 TBLRDH TBLRDH Ws,Wd
Read Prog[23:16] to Wd[7:0]
1
5
None
79 TBLRDL TBLRDL Ws,Wd
Read Prog[15:0] to Wd
1
5
None
80 TBLWTH TBLWTH Ws,Wd
Write Ws[7:0] to Prog[23:16]
1
2
None
81 TBLWTL TBLWTL Ws,Wd
Write Ws to Prog[15:0]
1
2
None
82 ULNK
ULNK
Unlink Frame Pointer
1
1
SFA
83 XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
84 ZE
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C,Z,N
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2011-2020 Microchip Technology Inc.
DS70000657J-page 403
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
NOTES:
DS70000657J-page 404
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
29.0 DEVELOPMENT SUPPORT
Move a design from concept to production in record time with Microchip's award-winning development tools. Microchip tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs) in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools. Providing the ultimate ease-of-use experience, Microchip's line of programmers, debuggers and emulators work seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application, while our line of third party tools round out our comprehensive development tool solutions. Microchip's MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which support multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows. Go to the following website for more information and details: https://www.microchip.com/development-tools/
2011-2020 Microchip Technology Inc.
DS70000657J-page 405
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
NOTES:
DS70000657J-page 406
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(3).................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3)................................................... -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3)................................................... -0.3V to +3.6V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................300 mA Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA Maximum current sunk/sourced by any 8x I/O pin ..................................................................................................25 mA Maximum current sunk by all ports(2,4) .................................................................................................................200 mA
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2). 3: See the "Pin Diagrams" section for the 5V tolerant pins. 4: Exceptions are: dsPIC33EPXXXGP502, dsPIC33EPXXXMC202/502 and PIC24EPXXXGP/MC202 devices,
which have a maximum sink/source capability of 130 mA.
2011-2020 Microchip Technology Inc.
DS70000657J-page 407
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS VS. VOLTAGE
Maximum MIPS
Characteristic
VDD Range (in Volts)
Temp Range (in °C)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
-- -- Note 1:
3.0V to 3.6V(1)
-40°C to +85°C
70
3.0V to 3.6V(1)
-40°C to +125°C
60
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
TABLE 30-2: THERMAL OPERATING CONDITIONS
Rating
Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range
Extended Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range
Power Dissipation: Internal chip power dissipation:
PINT = VDD x (IDD IOH) I/O Pin Power Dissipation:
I/O = ({VDD VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation
Symbol Min. Typ. Max. Unit
TJ
-40
--
+125
°C
TA
-40
--
+85
°C
TJ
-40
--
+140
°C
TA
-40
--
+125
°C
PD
PINT + PI/O
W
PDMAX
(TJ TA)/JA
W
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol Typ.
Max.
Unit Notes
Package Thermal Resistance, 64-Pin QFN
JA
28.0
--
°C/W
1
Package Thermal Resistance, 64-Pin TQFP 10x10 mm
JA
48.3
--
°C/W
1
Package Thermal Resistance, 48-Pin UQFN 6x6 mm
JA
41
--
°C/W
1
Package Thermal Resistance, 44-Pin QFN
JA
29.0
--
°C/W
1
Package Thermal Resistance, 44-Pin TQFP 10x10 mm
JA
49.8
--
°C/W
1
Package Thermal Resistance, 44-Pin VTLA 6x6 mm
JA
25.2
--
°C/W
1
Package Thermal Resistance, 36-Pin VTLA 5x5 mm
JA
28.5
--
°C/W
1
Package Thermal Resistance, 36-Pin UQFN 5x5 mm
JA
29.2
--
°C/W
1
Package Thermal Resistance, 28-Pin QFN-S
JA
30.0
--
°C/W
1
Package Thermal Resistance, 28-Pin SSOP
JA
71.0
--
°C/W
1
Package Thermal Resistance, 28-Pin SOIC
JA
69.7
--
°C/W
1
Package Thermal Resistance, 28-Pin SPDIP
JA
60.0
--
°C/W
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS70000657J-page 408
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.
Typ. Max. Units
Conditions
Operating Voltage
DC10 VDD
Supply Voltage
3.0
--
3.6
V
DC16 VPOR
VDD Start Voltage to Ensure Internal Power-on Reset Signal
--
--
VSS
V
DC17 SVDD
VDD Rise Rate to Ensure Internal Power-on Reset Signal
0.03
--
-- V/ms 0V-1V in 100 ms
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
TABLE 30-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristics
Min. Typ. Max.
CEFC
External Filter Capacitor Value(1)
4.7
10
--
Note 1: Typical VCAP voltage = 1.8 volts when VDD VDDMIN.
Units
Comments
µF Capacitor must have a low series resistance (< 1 Ohm)
2011-2020 Microchip Technology Inc.
DS70000657J-page 409
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
Typ.
Max.
Units
Conditions
Operating Current (IDD)(1)
DC20d
9
15
mA
-40°C
DC20a DC20b
9
15
mA
9
15
mA
+25°C +85°C
3.3V
10 MIPS
DC20c
9
15
mA
+125°C
DC22d
16
25
mA
-40°C
DC22a DC22b
16
25
mA
16
25
mA
+25°C +85°C
3.3V
20 MIPS
DC22c
16
25
mA
+125°C
DC24d
27
40
mA
-40°C
DC24a DC24b
27
40
mA
27
40
mA
+25°C +85°C
3.3V
40 MIPS
DC24c
27
40
mA
+125°C
DC25d
36
55
mA
-40°C
DC25a DC25b
36
55
mA
36
55
mA
+25°C +85°C
3.3V
60 MIPS
DC25c
36
55
mA
+125°C
DC26d
41
60
mA
-40°C
DC26a
41
60
mA
+25°C
3.3V
70 MIPS
DC26b
41
60
mA
+85°C
Note 1:
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows:
· Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
· CLKO is configured as an I/O input pin in the Configuration Word
· All I/O pins (except OSC1) are configured as outputs and driven low
· MCLR = VDD, WDT and FSCM are disabled
· CPU, SRAM, program memory and data memory are operational
· No peripheral modules are operating or being clocked (defined PMDx bits are all `1's) · NOP instructions are executed in while(1) loop · JTAG is disabled
DS70000657J-page 410
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
Typ.
Max.
Units
Conditions
Idle Current (IIDLE)(1)
DC40d
3
8
mA
-40°C
DC40a DC40b
3
8
mA
+25°C
3
8
mA
+85°C
3.3V
10 MIPS
DC40c
3
8
mA
+125°C
DC42d
6
12
mA
-40°C
DC42a DC42b
6
12
mA
6
12
mA
+25°C +85°C
3.3V
20 MIPS
DC42c
6
12
mA
+125°C
DC44d
11
18
mA
-40°C
DC44a DC44b
11
18
mA
11
18
mA
+25°C +85°C
3.3V
40 MIPS
DC44c
11
18
mA
+125°C
DC45d
17
27
mA
-40°C
DC45a DC45b
17
27
mA
17
27
mA
+25°C +85°C
3.3V
60 MIPS
DC45c
17
27
mA
+125°C
DC46d
20
35
mA
-40°C
DC46a
20
35
mA
+25°C
3.3V
70 MIPS
DC46b
20
35
mA
+85°C
Note 1:
Base Idle current (IIDLE) is measured as follows:
· CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
· CLKO is configured as an I/O input pin in the Configuration Word
· All I/O pins are configured as inputs and pulled to VSS
· MCLR = VDD, WDT and FSCM are disabled
· No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed)
· The NVMSIDL bit (NVMCON[12]) = 1 (i.e., Flash regulator is set to standby while the device is in Idle mode)
· The VREGSF bit (RCON[11]) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode)
· JTAG is disabled
2011-2020 Microchip Technology Inc.
DS70000657J-page 411
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
Typ.
Max.
Units
Conditions
Power-Down Current (IPD)(1) dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X and PIC24EP32GP/MC20X
DC60d
30
100
µA
-40°C
DC60a DC60b
35
100
µA
150
200
µA
+25°C +85°C
3.3V
DC60c
250
500
µA
+125°C
Power-Down Current (IPD)(1) dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X and PIC24EP64GP/MC20X
DC60d
25
100
µA
-40°C
DC60a DC60b
30
100
µA
150
350
µA
+25°C +85°C
3.3V
DC60c
350
800
µA
+125°C
Power-Down Current (IPD)(1) dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X and PIC24EP128GP/MC20X
DC60d
30
100
µA
-40°C
DC60a DC60b
35
100
µA
150
350
µA
+25°C +85°C
3.3V
DC60c
550
1000
µA
+125°C
Power-Down Current (IPD)(1) dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X and PIC24EP256GP/MC20X
DC60d
35
100
µA
-40°C
DC60a DC60b
40
100
µA
250
450
µA
+25°C +85°C
3.3V
DC60c
1000
1200
µA
+125°C
Power-Down Current (IPD)(1) dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X and PIC24EP512GP/MC20X
DC60d
40
100
µA
-40°C
DC60a DC60b
45
100
µA
350
800
µA
+25°C +85°C
3.3V
DC60c
1100
1500
µA
+125°C
Note 1:
IPD (Sleep) current is measured as follows:
· CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
· CLKO is configured as an I/O input pin in the Configuration Word
· All I/O pins are configured as inputs and pulled to VSS
· MCLR = VDD, WDT and FSCM are disabled
· All peripheral modules are disabled (PMDx bits are all set)
· The VREGS bit (RCON[8]) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode)
· The VREGSF bit (RCON[11]) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode)
· JTAG is disabled
DS70000657J-page 412
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT)(1)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
Typ.
Max.
Units
Conditions
DC61d DC61a DC61b DC61c Note 1:
8
--
µA
-40°C
10
--
µA
12
--
µA
+25°C +85°C
3.3V
13
--
µA
+125°C
The IWDT current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. All parameters are characterized but not tested during manufacturing.
TABLE 30-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
Typ.
Max.
Doze Ratio
Units
Conditions
Doze Current (IDOZE)(1)
DC73a(2)
35
DC73g
20
DC70a(2)
35
DC70g
20
DC71a(2)
35
DC71g
20
DC72a(2)
28
DC72g
15
-- 30
1:2 1:128
mA mA
-40°C 3.3V FOSC = 140 MHz
--
1:2
mA
30
1:128
mA
+25°C 3.3V FOSC = 140 MHz
--
1:2
mA
30
1:128
mA
+85°C 3.3V FOSC = 140 MHz
-- 30
1:2 1:128
mA mA
+125°C 3.3V FOSC = 120 MHz
Note 1: 2:
IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows:
· Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
· CLKO is configured as an I/O input pin in the Configuration Word
· All I/O pins are configured as inputs and pulled to VSS
· MCLR = VDD, WDT and FSCM are disabled
· CPU, SRAM, program memory and data memory are operational
· No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed)
· CPU is executing while(1) statement · JTAG is disabled
Parameter is characterized but not tested in manufacturing.
2011-2020 Microchip Technology Inc.
DS70000657J-page 413
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.
Typ.
Max. Units
Conditions
VIL
Input Low Voltage
DI10
Any I/O Pin and MCLR
VSS
--
0.2 VDD V
DI18
I/O Pins with SDAx, SCLx
VSS
--
0.3 VDD V SMBus disabled
DI19
I/O Pins with SDAx, SCLx
VSS
--
0.8
V SMBus enabled
VIH
Input High Voltage
DI20
I/O Pins Not 5V Tolerant
0.8 VDD
--
VDD
V Note 3
I/O Pins 5V Tolerant and MCLR
0.8 VDD
--
5.5
V Note 3
I/O Pins with SDAx, SCLx 0.8 VDD --
5.5
V SMBus disabled
I/O Pins with SDAx, SCLx
2.1
--
5.5
V SMBus enabled
ICNPU Change Notification Pull-up Current
DI30
150
250
550
µA VDD = 3.3V, VPIN = VSS
ICNPD Change Notification Pull-Down Current(4)
DI31
20
50
100
µA VDD = 3.3V, VPIN = VDD
Note 1:
2: 3:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See the "Pin Diagrams" section for the 5V tolerant pins.
4: VIL source < (VSS 0.3). Characterized but not tested. 5: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 6: Digital 5V tolerant pins do not have an internal high-side diode to VDD, and therefore, cannot tolerate any
"positive" input injection current. 7: Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.
DS70000657J-page 414
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.
Typ.
Max. Units
Conditions
IIL
Input Leakage Current(1,2)
DI50
I/O Pins 5V Tolerant(3)
-1
--
+1
µA VSS VPIN VDD,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(3)
-1
--
+1
µA VSS VPIN VDD,
Pin at high-impedance,
-40°C TA +85°C
DI51a
I/O Pins Not 5V Tolerant(3)
-1
--
+1
µA Analog pins shared with
external reference pins,
-40°C TA +85°C
DI51b
I/O Pins Not 5V Tolerant(3)
-1
--
+1
µA VSS VPIN VDD,
Pin at high-impedance,
-40°C TA +125°C
DI51c
I/O Pins Not 5V Tolerant(3)
-1
--
+1
µA Analog pins shared with
external reference pins,
-40°C TA +125°C
DI55 DI56
MCLR OSC1
-5
--
+5
µA VSS VPIN VDD
-5
--
+5
µA VSS VPIN VDD,
XT and HS modes
Note 1:
2: 3: 4: 5: 6:
7: 8:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See the "Pin Diagrams" section for the 5V tolerant pins.
VIL source < (VSS 0.3). Characterized but not tested.
VIH source > (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high-side diode to VDD, and therefore, cannot tolerate any "positive" input injection current.
Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.
2011-2020 Microchip Technology Inc.
DS70000657J-page 415
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.
Typ.
Max. Units
Conditions
IICL DI60a
Input Low Injection Current 0
--
-5(4,7) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
IICH DI60b
Input High Injection Current 0
--
+5(5,6,7) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(6)
IICT Total Input Injection Current
DI60c
(sum of all I/O and control -20(8)
--
+20(8) mA Absolute instantaneous sum
pins)
of all ± input injection
currents from all I/O pins
( | IICL + | IICH | ) IICT
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.
3: See the "Pin Diagrams" section for the 5V tolerant pins.
4: VIL source < (VSS 0.3). Characterized but not tested.
5: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
6: Digital 5V tolerant pins do not have an internal high-side diode to VDD, and therefore, cannot tolerate any "positive" input injection current.
7: Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.
DS70000657J-page 416
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min. Typ. Max. Units
Conditions
DO10 VOL DO20 VOH DO20A VOH1
Output Low Voltage 4x Sink Driver Pins(2)
Output Low Voltage 8x Sink Driver Pins(3)
Output High Voltage 4x Source Driver Pins(2) Output High Voltage 8x Source Driver Pins(3) Output High Voltage 4x Source Driver Pins(2)
Output High Voltage 8x Source Driver Pins(3)
--
--
0.4
V VDD = 3.3V,
IOL 6 mA, -40°C TA +85°C,
IOL 5 mA, +85°C TA +125°C
--
--
0.4
V VDD = 3.3V,
IOL 12 mA, -40°C TA +85°C,
IOL 8 mA, +85°C TA +125°C
2.4 --
--
V IOH -10 mA, VDD = 3.3V
2.4 --
--
V IOH -15 mA, VDD = 3.3V
1.5(1) --
--
V IOH -14 mA, VDD = 3.3V
2.0(1) --
--
IOH -12 mA, VDD = 3.3V
3.0(1) --
--
IOH -7 mA, VDD = 3.3V
1.5(1) --
--
V IOH -22 mA, VDD = 3.3V
2.0(1) --
--
IOH -18 mA, VDD = 3.3V
3.0(1) --
--
IOH -10 mA, VDD = 3.3V
Note 1: 2: 3:
Parameters are characterized but not tested.
Includes all I/O pins that are not 8x Sink Driver pins (see below).
Includes the following pins: For devices with less than 64 pins: RA3, RA4, RA9, RB[7:15] and RC3 For 64-pin devices: RA4, RA9, RB[7:15], RC3 and RC15
TABLE 30-13: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.(2) Typ. Max. Units
Conditions
BO10 Note 1:
2: 3:
VBOR
BOR Event on VDD Transition 2.65
--
2.95
High-to-Low
V VDD (Notes 2 and 3)
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance.
Parameters are for design guidance only and are not tested in manufacturing.
The VBOR specification is relative to VDD.
2011-2020 Microchip Technology Inc.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-14: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ.(1) Max. Units
Conditions
Program Flash Memory
D130 EP
Cell Endurance
10,000 --
-- E/W -40C to +125C
D131 VPR
VDD for Read
3.0
--
3.6
V
D132b VPEW VDD for Self-Timed Write
3.0
--
3.6
V
D134 TRETD Characteristic Retention
20
--
-- Year Provided no other specifications
are violated, -40C to +125C
D135 IDDP
Supply Current during Programming(2)
--
10
--
mA
D136 IPEAK Instantaneous Peak Current -- During Start-up
--
150 mA
D137a TPE
Page Erase Time
-- 146,893 -- FRC TA = +85°C cycles
D137b TPE
Page Erase Time
-- 146,893 -- FRC TA = +125°C cycles
D138a TWW Word Write Cycle Time
--
346
-- FRC TA = +85°C
cycles
D138b TWW Word Write Cycle Time
--
346
-- FRC TA = +125°C
cycles
Note 1: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
2: Parameter characterized but not tested in manufacturing.
DS70000657J-page 418
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
30.2 AC Characteristics and Timing Parameters
This section defines dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X AC characteristics and timing parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS AC
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended Operating voltage VDD range as described in Section 30.1 "DC Characteristics".
FIGURE 30-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 for all pins except OSC2 VDD/2
Load Condition 2 for OSC2
RL
Pin
CL
VSS
Pin
CL
VSS
RL = 464 CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
DO50 COSCO OSC2 Pin
DO56 CIO DO58 CB
All I/O Pins and OSC2 SCLx, SDAx
--
-- 15 pF In XT and HS modes, when
external clock is used to drive
OSC1
--
-- 50 pF EC mode
--
-- 400 pF In I2C mode
2011-2020 Microchip Technology Inc.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-2: OSC1 CLKO
EXTERNAL CLOCK TIMING
Q1
Q2 Q3
Q4 Q1
Q2 Q3
Q4
OS20 OS25
OS30 OS30
OS31 OS31
OS41
OS40
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symb
Characteristic
Min.
Typ.(1)
Max.
Units Conditions
OS10 FIN External CLKI Frequency
DC
--
60
MHz EC
(External clocks allowed only
in EC and ECPLL modes)
Oscillator Crystal Frequency
3.5
--
10
MHz XT
10
--
25
MHz HS
OS20 TOSC TOSC = 1/FOSC
8.33
--
DC
ns +125°C
TOSC = 1/FOSC OS25 TCY Instruction Cycle Time(2)
Instruction Cycle Time(2)
7.14
--
DC
ns +85°C
16.67
--
DC
ns +125°C
14.28
--
DC
ns +85°C
OS30
TosL, External Clock in (OSC1) TosH High or Low Time
0.45 x TOSC -- 0.55 x TOSC ns EC
OS31
OS40 OS41
TosR, TosF
TckR
TckF
External Clock in (OSC1) Rise or Fall Time CLKO Rise Time(3,4) CLKO Fall Time(3,4)
--
--
20
ns EC
--
5.2
--
ns
--
5.2
--
ns
OS42 GM
External Oscillator Transconductance(4)
--
12
--
mA/V HS, VDD = 3.3V,
TA = +25°C
--
6
--
mA/V XT, VDD = 3.3V,
TA = +25°C
Note 1: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Minimum" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Maximum" cycle time limit is "DC" (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: This parameter is characterized, but not tested in manufacturing.
DS70000657J-page 420
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ.(1) Max. Units
Conditions
OS50 FPLLI
PLL Voltage Controlled Oscillator 0.8
--
8.0 MHz ECPLL, XTPLL modes
(VCO) Input Frequency Range
OS51 FVCO On-Chip VCO System Frequency 120
--
340 MHz
OS52 TLOCK PLL Start-up Time (Lock Time)
0.9
1.5
3.1
ms
OS53 DCLK
CLKO Stability (Jitter)(2)
-3
0.5
3
%
Note 1: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for individual time bases, or communication clocks used by the application, use the following formula:
Effective Jitter = ---------------------------------------D-----C---L----K---------------------------------------T----i--m----e----B----a---s--e----o---r----C---F-o---mO----Sm---C--u---n---i-c---a---t--i-o---n-----C----l--o---c--k-
For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows:
Effective Jitter
=
D-----C----L---K1--1-2--0-0--
=
D-----C----L---K12
=
-D3---.-C4---6-L---4K-
TABLE 30-19: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Characteristic
Min. Typ. Max. Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a FRC
-1.5
0.5
+1.5
% -40°C TA -10°C VDD = 3.0-3.6V
-1
0.5
+1
% -10°C TA +85°C VDD = 3.0-3.6V
F20b FRC
-2
1
+2
% +85°C TA +125°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Characteristic
Min.
Typ. Max. Units
Conditions
LPRC @ 32.768 kHz(1)
F21a LPRC
-30
--
+30
-20
--
+20
F21b LPRC
-30
--
+30
Note 1: The change of LPRC frequency as VDD changes.
% -40°C TA -10°C VDD = 3.0-3.6V % -10°C TA +85°C VDD = 3.0-3.6V % +85°C TA +125°C VDD = 3.0-3.6V
2011-2020 Microchip Technology Inc.
DS70000657J-page 421
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-3:
I/O TIMING CHARACTERISTICS
I/O Pin (Input)
DI35 DI40
I/O Pin (Output)
Old Value
Note: Refer to Figure 30-1 for load conditions.
DO31 DO32
New Value
TABLE 30-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ.(1) Max. Units
Conditions
DO31
TIOR
Port Output Rise Time
--
5
10
ns
DO32
TIOF
Port Output Fall Time
--
5
10
ns
DI35
TINP
INTx Pin High or Low Time (input) 20
--
--
ns
DI40
TRBP
CNx High or Low Time (input)
2
--
--
TCY
Note 1: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
FIGURE 30-4:
BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR BOR
Reset Sequence
TMCLR (SY20)
TBOR (SY30)
Various Delays (depending on configuration)
CPU Starts Fetching Code
DS70000657J-page 422
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SY00 TPU
Power-up Period
--
400
600 µs
SY10 TOST
Oscillator Start-up Time -- 1024 TOSC -- -- TOSC = OSC1 period
SY12 TWDT
Watchdog Timer Time-out Period
0.81
0.98 1.22 ms WDTPRE = 0,
WDTPOST[3:0] = 0000, using
LPRC tolerances indicated in F21
(see Table 30-20) at +85ºC
3.26
3.91 4.88 ms WDTPRE = 1,
WDTPOST[3:0] = 0000, using
LPRC tolerances indicated in F21
(see Table 30-20) at +85ºC
SY13 TIOZ
I/O High-Impedance
0.68
0.72
1.2 µs
from MCLR Low or
Watchdog Timer Reset
SY20 TMCLR
MCLR Pulse Width (low) 2
--
-- µs
SY30 TBOR
BOR Pulse Width (low) 1
--
-- µs
SY35 TFSCM
Fail-Safe Clock Monitor -- Delay
500
900 µs -40°C to +85°C
SY36 TVREG
Voltage Regulator
--
Standby-to-Active mode
Transition Time
--
30 µs
SY37 TOSCDFRC FRC Oscillator Start-up 46
48
54 µs
Delay
SY38 TOSCDLPRC LPRC Oscillator Start-up -- Delay
--
70 µs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
2011-2020 Microchip Technology Inc.
DS70000657J-page 423
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-5:
TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK TMRx
Tx10
Tx11
Tx15 OS60
Tx20
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(2)
Min.
Typ.
Max.
Units Conditions
TA10 TTXH
T1CK High Synchronous Greater of: --
--
ns Must also meet
Time
mode
20 or
Parameter TA15,
(TCY + 20)/N
N = prescaler value
(1, 8, 64, 256)
Asynchronous
35
--
--
ns
TA11 TTXL
T1CK Low Synchronous Greater of: --
--
ns Must also meet
Time
mode
20 or
Parameter TA15,
(TCY + 20)/N
N = prescaler value
(1, 8, 64, 256)
Asynchronous
10
--
--
ns
TA15 TTXP
T1CK Input Synchronous
Greater of:
--
--
ns N = prescale value
Period
mode
40 or
(1, 8, 64, 256)
(2 TCY + 40)/N
OS60 Ft1
T1CK Oscillator Input
DC
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON[1]))
--
50
kHz
TA20
TCKEXTMRL Delay from External T1CK Clock Edge to Timer Increment
0.75 TCY + 40
-- 1.75 TCY + 40 ns
Note 1: Timer1 is a Type A.
2: These parameters are characterized, but are not tested in manufacturing.
DS70000657J-page 424
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-24: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units Conditions
TB10 TtxH
TxCK High Synchronous Greater of:
--
--
ns Must also meet
Time
mode
20 or
Parameter TB15,
(TCY + 20)/N
N = prescale
value
(1, 8, 64, 256)
TB11 TtxL
TxCK Low Synchronous Greater of:
--
--
ns Must also meet
Time
mode
20 or
Parameter TB15,
(TCY + 20)/N
N = prescale
value
(1, 8, 64, 256)
TB15 TtxP
TxCK
Synchronous Greater of:
--
--
ns N = prescale
Input
mode
40 or
value
Period
(2 TCY + 40)/N
(1, 8, 64, 256)
TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 -- 1.75 TCY + 40 ns Clock Edge to Timer Increment
Note 1: These parameters are characterized, but are not tested in manufacturing.
TABLE 30-25: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units Conditions
TC10 TtxH
TxCK High Synchronous TCY + 20
--
--
ns Must also meet
Time
Parameter TC15
TC11 TtxL
TxCK Low Synchronous TCY + 20
--
--
ns Must also meet
Time
Parameter TC15
TC15 TtxP
TxCK Input Synchronous, 2 TCY + 40
--
--
ns N = prescale
Period
with prescaler
value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment
0.75 TCY + 40
-- 1.75 TCY + 40 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2011-2020 Microchip Technology Inc.
DS70000657J-page 425
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-6:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10 Note: Refer to Figure 30-1 for load conditions.
IC11 IC15
TABLE 30-26: INPUT CAPTURE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. No.
Symbol
Characteristics(1)
Min.
Max. Units
Conditions
IC10 IC11 IC15 Note 1:
TCCL ICx Input Low Time
Greater of
--
12.5 + 25 or
(0.5 TCY/N) + 25
ns Must also meet Parameter IC15
TCCH ICx Input High Time
Greater of
--
12.5 + 25 or
(0.5 TCY/N) + 25
ns Must also meet Parameter IC15
TCCP ICx Input Period
Greater of
--
ns
25 + 50 or
(1 TCY/N) + 50
These parameters are characterized, but not tested in manufacturing.
N = prescale value (1, 4, 16)
DS70000657J-page 426
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-7:
OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
OCx (Output Compare x
or PWMx Mode) OC11
Note: Refer to Figure 30-1 for load conditions.
OC10
TABLE 30-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min. Typ. Max. Units
Conditions
OC10 TccF OCx Output Fall Time
--
--
--
ns
OC11 TccR OCx Output Rise Time
--
--
--
ns
Note 1: These parameters are characterized but not tested in manufacturing.
See Parameter DO32 See Parameter DO31
FIGURE 30-8:
OCx/PWMx MODULE TIMING CHARACTERISTICS
OCFA OCx
OC20 OC15
TABLE 30-28: OCx/PWMx MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min.
Typ.
Max. Units
Conditions
OC15 TFD
Fault Input to PWMx I/O Change
--
-- TCY + 20 ns
OC20 TFLT
Fault Input Pulse Width
TCY + 20 --
--
ns
Note 1: These parameters are characterized but not tested in manufacturing.
2011-2020 Microchip Technology Inc.
DS70000657J-page 427
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-9:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
Fault Input (active-low)
PWMx
MP30 MP20
FIGURE 30-10:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
MP11 MP10
PWMx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min. Typ. Max. Units
Conditions
MP10 TFPWM PWMx Output Fall Time
--
--
--
ns
MP11 TRPWM PWMx Output Rise Time
--
--
--
ns
MP20 TFD
Fault Input to PWMx I/O Change
--
--
15
ns
MP30 TFH
Fault Input Pulse Width
15
--
--
ns
Note 1: These parameters are characterized but not tested in manufacturing.
See Parameter DO32 See Parameter DO31
DS70000657J-page 428
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-11:
TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
QEB POSCNT
TQ10
TQ11
TQ15
TQ20
TABLE 30-30: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min.
Typ. Max. Units Conditions
TQ10 TtQH
TQCK High Synchronous, Greater of 12.5 + 25 --
--
Time
with prescaler
or
(0.5 TCY/N) + 25
TQ11 TtQL
TQCK Low Synchronous, Greater of 12.5 + 25 --
--
Time
with prescaler
or
(0.5 TCY/N) + 25
TQ15 TtQP
TQCP Input Synchronous, Greater of 25 + 50 --
--
Period
with prescaler
or
(1 TCY/N) + 50
TQ20 TCKEXTMRL Delay from External TQCK
--
1
TCY
Clock Edge to Timer
Increment
Note 1: These parameters are characterized but not tested in manufacturing.
ns Must also meet Parameter TQ15
ns Must also meet Parameter TQ15
ns
--
2011-2020 Microchip Technology Inc.
DS70000657J-page 429
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-12:
QEA/QEB INPUT CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
TQ36
QEA (input)
TQ31
TQ30
TQ35
QEB (input)
TQ41
TQ40
QEB Internal
TQ31
TQ30 TQ35
TABLE 30-31: QUADRATURE DECODER TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Typ.(2)
Max. Units
Conditions
TQ30 TQ31 TQ35 TQ36 TQ40
TQ41
Note 1: 2:
3:
TQUL Quadrature Input Low Time
6 TCY
--
ns
TQUH Quadrature Input High Time
6 TCY
--
ns
TQUIN Quadrature Input Period
12 TCY
--
ns
TQUP Quadrature Phase Period
3 TCY
--
ns
TQUFL Filter Time to Recognize Low, 3 * N * TCY
--
with Digital Filter
ns N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3)
TQUFH Filter Time to Recognize High, 3 * N * TCY
--
with Digital Filter
ns N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3)
These parameters are characterized but not tested in manufacturing.
Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
N = Index Channel Digital Filter Clock Divide Select bits. Refer to "Quadrature Encoder Interface (QEI)" (www.microchip.com/DS70000601) in the "dsPIC33/PIC24 Family Reference Manual". Please see the Microchip website for the latest family reference manual sections.
DS70000657J-page 430
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-13:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
QEA (input)
QEB (input)
Ungated Index
TQ51
Index Internal
Position Counter Reset
TQ50 TQ55
TABLE 30-32: QEI INDEX PULSE TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min.
Max. Units
Conditions
TQ50 TqiL
Filter Time to Recognize Low, with Digital Filter
3 * N * TCY --
ns N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2)
TQ51 TqiH
Filter Time to Recognize High, with Digital Filter
3 * N * TCY --
ns N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2)
TQ55 Tqidxr Index Pulse Recognized to Position Counter Reset (ungated index)
3 TCY
--
ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on the falling edge.
2011-2020 Microchip Technology Inc.
DS70000657J-page 431
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-33: SPI2 MAXIMUM DATA/CLOCK RATE SUMMARY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Maximum Data Rate
Master Transmit Only (Half-Duplex)
Master
Slave
Transmit/Receive Transmit/Receive
(Full-Duplex)
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 30-33
--
--
0,1
0,1
0,1
9 MHz
--
Table 30-34
--
1
0,1
1
9 MHz
--
Table 30-35
--
0
0,1
1
15 MHz
--
--
Table 30-36
1
0
0
11 MHz
--
--
Table 30-37
1
1
0
15 MHz
--
--
Table 30-38
0
1
0
11 MHz
--
--
Table 30-39
0
0
0
FIGURE 30-14:
SCK2 (CKP = 0)
SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS
SCK2 (CKP = 1)
SP10 SP35
SP21
SP20
SP20
SP21
SDO2
MSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
Bit 14 - - - - - -1
LSb
SP30, SP31
DS70000657J-page 432
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-15:
SCK2 (CKP = 0)
SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS
SP36
SCK2 (CKP = 1)
SP10 SP35
SP21
SP20
SP20
SP21
SDO2
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-34: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10 FscP
Maximum SCK2 Frequency
--
--
15 MHz Note 3
SP20 TscF
SCK2 Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP21 TscR
SCK2 Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO2 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO2 Data Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO2 Data Output Valid after
--
TscL2doV SCK2 Edge
6
20
ns
SP36 TdiV2scH, SDO2 Data Output Setup to TdiV2scL First SCK2 Edge
30
--
--
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 433
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-16:
SCK2 (CKP = 0)
SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS
SP36
SCK2 (CKP = 1)
SP10 SP35
SDO2
SP40
MSb
Bit 14 - - - - - -1
SP30, SP31
SDI2
MSb In SP41
Bit 14 - - - -1
Note: Refer to Figure 30-1 for load conditions.
SP21
SP20
SP20
SP21
LSb
LSb In
TABLE 30-35: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10 FscP
Maximum SCK2 Frequency
--
--
9
MHz Note 3
SP20 TscF
SCK2 Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP21 TscR
SCK2 Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO2 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO2 Data Output Rise Time --
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO2 Data Output Valid after -- TscL2doV SCK2 Edge
6
20
ns
SP36 TdoV2sc, SDO2 Data Output Setup to
30
TdoV2scL First SCK2 Edge
--
--
ns
SP40
TdiV2scH, Setup Time of SDI2 Data TdiV2scL Input to SCK2 Edge
30
--
--
ns
SP41 TscH2diL, Hold Time of SDI2 Data Input 30 TscL2diL to SCK2 Edge
--
--
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
DS70000657J-page 434
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-17:
SCK2 (CKP = 0)
SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS
SCK2 (CKP = 1)
SP10 SP35 SP36
SP21
SP20
SP20
SP21
SDO2 SDI2
MSb SP30, SP31
MSb In SP40 SP41
Bit 14 - - - - - -1
LSb
Bit 14 - - - -1
SP30, SP31 LSb In
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-36: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10 FscP
Maximum SCK2 Frequency
--
--
9
MHz -40ºC to +125ºC
(Note 3)
SP20 TscF
SCK2 Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP21 TscR
SCK2 Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO2 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO2 Data Output Rise Time --
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO2 Data Output Valid after -- TscL2doV SCK2 Edge
6
20
ns
SP36 TdoV2scH, SDO2 Data Output Setup to
30
TdoV2scL First SCK2 Edge
--
--
ns
SP40
TdiV2scH, Setup Time of SDI2 Data TdiV2scL Input to SCK2 Edge
30
--
--
ns
SP41 TscH2diL, Hold Time of SDI2 Data Input 30 TscL2diL to SCK2 Edge
--
--
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 435
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-18:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS
SP60 SS2
SCK2 (CKP = 0)
SP50
SP52
SCK2 (CKP = 1)
SP70
SP35
SP73
SP72
SP36
SP72
SP73
SDO2
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI2
MSb In SP41
SP40
Bit 14 - - - -1
Note: Refer to Figure 30-1 for load conditions.
LSb In
SP51
DS70000657J-page 436
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-37: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP
Maximum SCK2 Input Frequency
--
-- Lesser MHz Note 3
of FP
or 15
SP72 TscF
SCK2 Input Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP73 TscR
SCK2 Input Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO2 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO2 Data Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO2 Data Output Valid after
--
6
20
ns
TscL2doV SCK2 Edge
SP36 TdoV2scH, SDO2 Data Output Setup to TdoV2scL First SCK2 Edge
30
--
--
ns
SP40 TdiV2scH, Setup Time of SDI2 Data Input
30
TdiV2scL to SCK2 Edge
--
--
ns
SP41 TscH2diL, Hold Time of SDI2 Data Input TscL2diL to SCK2 Edge
30
--
--
ns
SP50 TssL2scH, SS2 to SCK2 or SCK2 TssL2scL Input
120
--
--
ns
SP51 TssH2doZ SS2 to SDO2 Output High-Impedance
10
--
50
ns Note 4
SP52 TscH2ssH SS2 after SCK2 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
SP60 TssL2doV SDO2 Data Output Valid after SS2 Edge
--
--
50
ns
Note 1: 2: 3:
4:
These parameters are characterized, but are not tested in manufacturing. Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI2 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 437
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-19:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS
SP60 SS2
SCK2 (CKP = 0)
SP50
SP52
SCK2 (CKP = 1)
SP70
SP35
SP73 SP36
SP72
SP72 SP73
SDO2
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI2
MSb In SP41
Bit 14 - - - -1
SP40
Note: Refer to Figure 30-1 for load conditions.
LSb In
SP51
DS70000657J-page 438
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-38: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP
Maximum SCK2 Input
--
Frequency
SP72 TscF
SCK2 Input Fall Time
--
SP73 TscR
SCK2 Input Rise Time
--
SP30 TdoF
SDO2 Data Output Fall Time
--
SP31 TdoR
SDO2 Data Output Rise Time
--
SP35 TscH2doV, SDO2 Data Output Valid after
--
TscL2doV SCK2 Edge
SP36 TdoV2scH, SDO2 Data Output Setup to
30
TdoV2scL First SCK2 Edge
SP40 TdiV2scH, Setup Time of SDI2 Data Input
30
TdiV2scL to SCK2 Edge
SP41 TscH2diL, Hold Time of SDI2 Data Input
30
TscL2diL to SCK2 Edge
SP50 TssL2scH, SS2 to SCK2 or SCK2
120
TssL2scL Input
-- Lesser MHz Note 3 of FP or 11
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
6
20
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
SP51 TssH2doZ SS2 to SDO2 Output High-Impedance
10
--
50
ns Note 4
SP52 TscH2ssH SS2 after SCK2 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
SP60 TssL2doV SDO2 Data Output Valid after SS2 Edge
--
--
50
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 439
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-20:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS
SS2 SCK2
(CKP = 0)
SP50
SP70
SP52 SP73 SP72
SCK2
(CKP = 1)
SDO2 SDI2
SP35 SP36
SP72 SP73
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
MSb In SP41
Bit 14 - - - -1
SP40
SP51 LSb In
Note: Refer to Figure 30-1 for load conditions.
DS70000657J-page 440
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-39: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP
Maximum SCK2 Input Frequency
--
--
15 MHz Note 3
SP72 TscF
SCK2 Input Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP73 TscR
SCK2 Input Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO2 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO2 Data Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO2 Data Output Valid after
--
6
20
ns
TscL2doV SCK2 Edge
SP36 TdoV2scH, SDO2 Data Output Setup to TdoV2scL First SCK2 Edge
30
--
--
ns
SP40 TdiV2scH, Setup Time of SDI2 Data Input
30
TdiV2scL to SCK2 Edge
--
--
ns
SP41 TscH2diL, Hold Time of SDI2 Data Input TscL2diL to SCK2 Edge
30
--
--
ns
SP50 TssL2scH, SS2 to SCK2 or SCK2 TssL2scL Input
120
--
--
ns
SP51 TssH2doZ SS2 to SDO2 Output High-Impedance
10
--
50
ns Note 4
SP52 TscH2ssH SS2 after SCK2 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
Note 1: 2: 3:
4:
These parameters are characterized, but are not tested in manufacturing. Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI2 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 441
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-21:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS
SS2 SCK2
(CKP = 0)
SP50
SP70
SP52 SP73 SP72
SCK2
(CKP = 1)
SDO2
SP35 SP36 MSb
SP72 SP73
Bit 14 - - - - - -1
LSb
SDI2
SP30, SP31
MSb In SP41
SP40
Bit 14 - - - -1
SP51 LSb In
Note: Refer to Figure 30-1 for load conditions.
DS70000657J-page 442
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-40: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP SP72 TscF
Maximum SCK2 Input Frequency
--
SCK2 Input Fall Time
--
SP73 TscR
SCK2 Input Rise Time
--
SP30 TdoF
SDO2 Data Output Fall Time
--
SP31 TdoR
SDO2 Data Output Rise Time
--
SP35 TscH2doV, SDO2 Data Output Valid after
--
TscL2doV SCK2 Edge
SP36 TdoV2scH, SDO2 Data Output Setup to
30
TdoV2scL First SCK2 Edge
SP40 TdiV2scH, Setup Time of SDI2 Data Input
30
TdiV2scL to SCK2 Edge
SP41 TscH2diL, Hold Time of SDI2 Data Input
30
TscL2diL to SCK2 Edge
SP50 TssL2scH, SS2 to SCK2 or SCK2
120
TssL2scL Input
SP51 TssH2doZ SS2 to SDO2 Output
10
High-Impedance
--
11 MHz Note 3
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
6
20
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
50
ns Note 4
SP52 TscH2ssH SS2 after SCK2 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 443
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-41: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Maximum Data Rate
Master Transmit Only (Half-Duplex)
Master
Slave
Transmit/Receive Transmit/Receive
(Full-Duplex)
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 30-42
--
--
0,1
0,1
0,1
10 MHz
--
Table 30-43
--
1
0,1
1
10 MHz
--
Table 30-44
--
0
0,1
1
15 MHz
--
--
Table 30-45
1
0
0
11 MHz
--
--
Table 30-46
1
1
0
15 MHz
--
--
Table 30-47
0
1
0
11 MHz
--
--
Table 30-48
0
0
0
FIGURE 30-22:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS
SCK1 (CKP = 0)
SCK1 (CKP = 1)
SP10 SP35
SP21
SP20
SP20
SP21
SDO1
MSb SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
Bit 14 - - - - - -1
LSb
SP30, SP31
DS70000657J-page 444
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-23:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS
SCK1 (CKP = 0)
SP36
SCK1 (CKP = 1)
SP10 SP35
SP21
SP20
SP20
SP21
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-42: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10 FscP
Maximum SCK1 Frequency
--
--
15 MHz Note 3
SP20 TscF
SCK1 Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP21 TscR
SCK1 Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO1 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO1 Data Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO1 Data Output Valid after
--
TscL2doV SCK1 Edge
6
20
ns
SP36 TdiV2scH, SDO1 Data Output Setup to TdiV2scL First SCK1 Edge
30
--
--
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 445
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-24:
SCK1 (CKP = 0)
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS
SP36
SCK1 (CKP = 1)
SP10 SP35
SP21
SP20
SP20
SP21
SDO1 SDI1
SP40
MSb
Bit 14 - - - - - -1
SP30, SP31
MSb In SP41
Bit 14 - - - -1
LSb LSb In
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-43: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10 FscP
Maximum SCK1 Frequency
--
--
10
MHz Note 3
SP20 TscF
SCK1 Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP21 TscR
SCK1 Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO1 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO1 Data Output Rise Time --
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO1 Data Output Valid after -- TscL2doV SCK1 Edge
6
20
ns
SP36 TdoV2sc, SDO1 Data Output Setup to
30
TdoV2scL First SCK1 Edge
--
--
ns
SP40
TdiV2scH, Setup Time of SDI1 Data TdiV2scL Input to SCK1 Edge
30
--
--
ns
SP41 TscH2diL, Hold Time of SDI1 Data Input 30 TscL2diL to SCK1 Edge
--
--
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
DS70000657J-page 446
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-25:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS
SCK1 (CKP = 0)
SCK1 (CKP = 1)
SP10 SP35 SP36
SP21
SP20
SP20
SP21
SDO1 SDI1
MSb
SP30, SP31 MSb In
SP40 SP41
Bit 14 - - - - - -1
LSb
Bit 14 - - - -1
SP30, SP31 LSb In
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-44: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10 FscP
Maximum SCK1 Frequency
--
--
10
MHz -40ºC to +125ºC
(Note 3)
SP20 TscF
SCK1 Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP21 TscR
SCK1 Output Rise Time
--
--
--
ns See Parameter DO31
(Note 4)
SP30 TdoF
SDO1 Data Output Fall Time
--
--
--
ns See Parameter DO32
(Note 4)
SP31 TdoR
SDO1 Data Output Rise Time --
--
--
ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO1 Data Output Valid after -- TscL2doV SCK1 Edge
6
20
ns
SP36 TdoV2scH, SDO1 Data Output Setup to
30
TdoV2scL First SCK1 Edge
--
--
ns
SP40
TdiV2scH, Setup Time of SDI1 Data TdiV2scL Input to SCK1 Edge
30
--
--
ns
SP41 TscH2diL, Hold Time of SDI1 Data Input 30 TscL2diL to SCK1 Edge
--
--
ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 447
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-26:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS
SP60 SS1
SCK1 (CKP = 0)
SP50
SP52
SCK1 (CKP = 1)
SP70
SP73
SP72
SP36
SP35
SP72
SP73
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In SP41
SP40
Bit 14 - - - -1
Note: Refer to Figure 30-1 for load conditions.
LSb In
SP51
DS70000657J-page 448
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-45: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP
Maximum SCK1 Input
--
Frequency
SP72 TscF
SCK1 Input Fall Time
--
SP73 TscR
SCK1 Input Rise Time
--
SP30 TdoF
SDO1 Data Output Fall Time
--
SP31 TdoR
SDO1 Data Output Rise Time
--
SP35 TscH2doV, SDO1 Data Output Valid after
--
TscL2doV SCK1 Edge
SP36 TdoV2scH, SDO1 Data Output Setup to
30
TdoV2scL First SCK1 Edge
SP40 TdiV2scH, Setup Time of SDI1 Data Input
30
TdiV2scL to SCK1 Edge
SP41 TscH2diL, Hold Time of SDI1 Data Input
30
TscL2diL to SCK1 Edge
-- Lesser of MHz Note 3 FP or 15
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
6
20
ns
--
--
ns
--
--
ns
--
--
ns
SP50 TssL2scH, SS1 to SCK1 or SCK1
120
TssL2scL Input
--
--
ns
SP51 TssH2doZ SS1 to SDO1 Output High-Impedance
10
--
50
ns Note 4
SP52 TscH2ssH SS1 after SCK1 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
SP60 TssL2doV SDO1 Data Output Valid after
--
SS1 Edge
--
50
ns
Note 1: 2: 3:
4:
These parameters are characterized, but are not tested in manufacturing. Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI1 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 449
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-27:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS
SP60 SS1
SCK1 (CKP = 0)
SP50
SCK1 (CKP = 1)
SP70
SP52
SP73
SP36
SP35
SP72
SP72 SP73
SDO1 SDI1
MSb
Bit 14 - - - - - -1
SP30, SP31
MSb In SP41
SP40
Bit 14 - - - -1
LSb LSb In
SP51
Note: Refer to Figure 30-1 for load conditions.
DS70000657J-page 450
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-46: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP
Maximum SCK1 Input
--
Frequency
SP72 TscF
SCK1 Input Fall Time
--
SP73 TscR
SCK1 Input Rise Time
--
SP30 TdoF
SDO1 Data Output Fall Time
--
SP31 TdoR
SDO1 Data Output Rise Time
--
SP35 TscH2doV, SDO1 Data Output Valid after
--
TscL2doV SCK1 Edge
SP36 TdoV2scH, SDO1 Data Output Setup to
30
TdoV2scL First SCK1 Edge
SP40 TdiV2scH, Setup Time of SDI1 Data Input
30
TdiV2scL to SCK1 Edge
SP41 TscH2diL, Hold Time of SDI1 Data Input
30
TscL2diL to SCK1 Edge
-- Lesser of MHz Note 3 FP or 11
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
6
20
ns
--
--
ns
--
--
ns
--
--
ns
SP50 TssL2scH, SS1 to SCK1 or SCK1
120
--
--
ns
TssL2scL Input
SP51 TssH2doZ SS1 to SDO1 Output High-Impedance
10
--
50
ns Note 4
SP52 TscH2ssH, SS1 after SCK1 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
SP60 TssL2doV SDO1 Data Output Valid after
--
SS1 Edge
--
50
ns
Note 1: 2: 3:
4:
These parameters are characterized, but are not tested in manufacturing. Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI1 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 451
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-28:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS
SS1 SCK1
(CKP = 0)
SP50
SP70
SP52 SP73 SP72
SCK1
(CKP = 1)
SDO1 SDI1
SP35 SP36 MSb
SP72 SP73
Bit 14 - - - - - -1
LSb
SP30, SP31
MSb In SP41
Bit 14 - - - -1
SP40
SP51 LSb In
Note: Refer to Figure 30-1 for load conditions.
DS70000657J-page 452
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-47: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP SP72 TscF
Maximum SCK1 Input Frequency
--
SCK1 Input Fall Time
--
SP73 TscR
SCK1 Input Rise Time
--
SP30 TdoF
SDO1 Data Output Fall Time
--
SP31 TdoR
SDO1 Data Output Rise Time
--
SP35 TscH2doV, SDO1 Data Output Valid after
--
TscL2doV SCK1 Edge
SP36 TdoV2scH, SDO1 Data Output Setup to
30
TdoV2scL First SCK1 Edge
SP40 TdiV2scH, Setup Time of SDI1 Data Input
30
TdiV2scL to SCK1 Edge
SP41 TscH2diL, Hold Time of SDI1 Data Input
30
TscL2diL to SCK1 Edge
SP50 TssL2scH, SS1 to SCK1 or SCK1
120
TssL2scL Input
SP51 TssH2doZ SS1 to SDO1 Output
10
High-Impedance
--
15 MHz Note 3
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
6
20
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
50
ns Note 4
SP52 TscH2ssH, SS1 after SCK1 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 453
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-29:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS
SS1 SCK1
(CKP = 0)
SP50
SP70
SP52 SP73 SP72
SCK1
(CKP = 1)
SDO1 SDI1
SP35 SP36
SP72
MSb
Bit 14 - - - - - -1
SP30, SP31
MSb In SP41
SP40
Bit 14 - - - -1
SP73
LSb SP51
LSb In
Note: Refer to Figure 30-1 for load conditions.
DS70000657J-page 454
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-48: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
SP70 FscP SP72 TscF
Maximum SCK1 Input Frequency
--
SCK1 Input Fall Time
--
SP73 TscR
SCK1 Input Rise Time
--
SP30 TdoF
SDO1 Data Output Fall Time
--
SP31 TdoR
SDO1 Data Output Rise Time
--
SP35 TscH2doV, SDO1 Data Output Valid after
--
TscL2doV SCK1 Edge
SP36 TdoV2scH, SDO1 Data Output Setup to
30
TdoV2scL First SCK1 Edge
SP40 TdiV2scH, Setup Time of SDI1 Data Input
30
TdiV2scL to SCK1 Edge
SP41 TscH2diL, Hold Time of SDI1 Data Input
30
TscL2diL to SCK1 Edge
SP50 TssL2scH, SS1 to SCK1 or SCK1
120
TssL2scL Input
SP51 TssH2doZ SS1 to SDO1 Output
10
High-Impedance
--
11 MHz Note 3
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
--
--
ns See Parameter DO32
(Note 4)
--
--
ns See Parameter DO31
(Note 4)
6
20
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
--
50
ns Note 4
SP52 TscH2ssH, SS1 after SCK1 Edge TscL2ssH
1.5 TCY + 40 --
--
ns Note 4
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in "Typical" column are at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
2011-2020 Microchip Technology Inc.
DS70000657J-page 455
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-30: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx SDAx
IM30
IM31
IM33
IM34
Start Condition Note: Refer to Figure 30-1 for load conditions.
Stop Condition
FIGURE 30-31:
SCLx SDAx In SDAx Out
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM11 IM10
IM11
IM10
IM26 IM25
IM21 IM33
IM40
IM40
IM45
Note: Refer to Figure 30-1 for load conditions.
DS70000657J-page 456
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-49: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(4)
Min.(1)
Max. Units
Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) --
µs
400 kHz mode TCY/2 (BRG + 2) --
µs
1 MHz mode(2) TCY/2 (BRG + 2)
--
µs
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) --
µs
400 kHz mode TCY/2 (BRG + 2) --
µs
1 MHz mode(2) TCY/2 (BRG + 2)
--
µs
IM20
TF:SCL
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode(2)
-- 20 + 0.1 CB
--
300
ns CB is specified to be
300
ns from 10 to 400 pF
100
ns
IM21
TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
1 MHz mode(2)
-- 20 + 0.1 CB
--
1000 300 300
ns CB is specified to be ns from 10 to 400 pF
ns
IM25 TSU:DAT Data Input
100 kHz mode
250
Setup Time
400 kHz mode
100
1 MHz mode(2)
40
--
ns
--
ns
--
ns
IM26 THD:DAT Data Input
100 kHz mode
0
Hold Time
400 kHz mode
0
1 MHz mode(2)
0.2
--
µs
0.9
µs
--
µs
IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) --
Setup Time
400 kHz mode TCY/2 (BRG + 2) --
1 MHz mode(2) TCY/2 (BRG + 2)
--
µs Only relevant for µs Repeated Start µs condition
IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) --
Hold Time
400 kHz mode TCY/2 (BRG +2)
--
1 MHz mode(2) TCY/2 (BRG + 2)
--
µs After this period, the µs first clock pulse is µs generated
IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) --
µs
Setup Time
400 kHz mode TCY/2 (BRG + 2) --
µs
1 MHz mode(2) TCY/2 (BRG + 2)
--
µs
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) --
µs
Hold Time
400 kHz mode TCY/2 (BRG + 2) --
µs
1 MHz mode(2) TCY/2 (BRG + 2)
--
µs
IM40 TAA:SCL Output Valid
100 kHz mode
--
From Clock
400 kHz mode
--
1 MHz mode(2)
--
3500
ns
1000
ns
400
ns
IM45 TBF:SDA Bus Free Time 100 kHz mode
4.7
400 kHz mode
1.3
1 MHz mode(2)
0.5
--
µs Time the bus must be
--
µs free before a new
--
µs transmission can start
IM50 CB
Bus Capacitive Loading
--
400
pF
IM51 TPGD Pulse Gobbler Delay
65
390
ns Note 3
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to "Inter-Integrated Circuit (I2C)"
(www.microchip.com/DS70000195) in the "dsPIC33/PIC24 Family Reference Manual". Please see the
Microchip website for the latest family reference manual sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
4: These parameters are characterized, but not tested in manufacturing.
2011-2020 Microchip Technology Inc.
DS70000657J-page 457
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-32: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx SDAx
IS30
IS31
Start Condition
IS33
IS34
Stop Condition
FIGURE 30-33: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
SCLx SDAx In SDAx Out
IS20 IS30
IS31 IS40
IS11
IS10 IS25
IS26
IS40
IS21 IS33
IS45
DS70000657J-page 458
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-50: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. No.
Symbol
Characteristic(3)
Min.
Max. Units
Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode
4.7
400 kHz mode
1.3
1 MHz mode(1)
0.5
IS11 THI:SCL Clock High Time 100 kHz mode
4.0
--
µs
--
µs
--
µs
--
µs
400 kHz mode
0.6
--
µs
1 MHz mode(1)
0.5
--
µs
IS20 TF:SCL SDAx and SCLx 100 kHz mode
--
300 ns
Fall Time
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode(1)
--
100 ns
IS21 TR:SCL SDAx and SCLx 100 kHz mode
--
1000 ns
Rise Time
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode(1)
--
300 ns
IS25
TSU:DAT Data Input Setup Time
100 kHz mode
250
400 kHz mode
100
1 MHz mode(1)
100
--
ns
--
ns
--
ns
IS26 THD:DAT Data Input
100 kHz mode
0
Hold Time
400 kHz mode
0
1 MHz mode(1)
0
--
µs
0.9
µs
0.3
µs
IS30
TSU:STA Start Condition Setup Time
100 kHz mode
400 kHz mode 1 MHz mode(1)
4.7 0.6 0.25
--
µs
--
µs
--
µs
IS31
THD:STA Start Condition Hold Time
100 kHz mode
400 kHz mode 1 MHz mode(1)
4.0 0.6 0.25
--
µs
--
µs
--
µs
IS33 TSU:STO Stop Condition 100 kHz mode
4.7
Setup Time
400 kHz mode
0.6
1 MHz mode(1)
0.6
--
µs
--
µs
--
µs
IS34
THD:STO Stop Condition Hold Time
100 kHz mode
400 kHz mode 1 MHz mode(1)
4 0.6 0.25
--
µs
--
µs
µs
IS40 TAA:SCL Output Valid
100 kHz mode
0
3500 ns
From Clock
400 kHz mode
0
1000 ns
1 MHz mode(1)
0
350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode
4.7
--
µs
400 kHz mode
1.3
1 MHz mode(1)
0.5
--
µs
--
µs
IS50 CB
Bus Capacitive Loading
--
400 pF
IS51 TPGD Pulse Gobbler Delay
65
390 ns
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.
3: These parameters are characterized, but not tested in manufacturing.
Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF
Only relevant for Repeated Start condition After this period, the first clock pulse is generated
Time the bus must be free before a new transmission can start Note 2
2011-2020 Microchip Technology Inc.
DS70000657J-page 459
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-34: ECANx MODULE I/O TIMING CHARACTERISTICS
CxTx Pin (output) CxRx Pin (input)
Old Value
CA10, CA11 CA20
New Value
TABLE 30-51: ECANx MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
CA10 CA11 CA20
Note 1: 2:
TIOF
Port Output Fall Time
--
--
--
ns See Parameter DO32
TIOR
Port Output Rise Time
--
--
--
ns See Parameter DO31
TCWF
Pulse Width to Trigger CAN Wake-up Filter
120
--
--
ns
These parameters are characterized but not tested in manufacturing.
Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 30-35: UARTx MODULE I/O TIMING CHARACTERISTICS
UxRX UXTX
UA20
MSb In UA10
Bits 1-6
LSb In
TABLE 30-52: UARTx MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +125°C
Param No.
Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
UA10 UA11 UA20
Note 1: 2:
TUABAUD UARTx Baud Time
66.67 --
--
ns
FBAUD
UARTx Baud Frequency
--
--
15 Mbps
TCWF
Start Bit Pulse Width to Trigger 500 --
--
ns
UARTx Wake-up
These parameters are characterized but not tested in manufacturing.
Data in "Typical" column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
DS70000657J-page 460
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.
Typ.(2)
Max.
Units
Conditions
Comparator AC Characteristics
CM10 TRESP
Response Time(3)
CM11 TMC2OV
Comparator Mode Change to Output Valid
Comparator DC Characteristics
CM30 VOFFSET
Comparator Offset Voltage
CM31 VHYST
Input Hysteresis Voltage(3)
CM32 TRISE/TFALL Comparator Output Rise/ Fall Time(3)
CM33 VGAIN
Open-Loop Voltage Gain(3)
CM34 VICM
Input Voltage Range
-- --
-- -- -- -- AVSS
19
--
--
10
±10
±15(7)
30
65(7)
20
--
90
--
--
AVDD
ns V+ input step of 100 mV, V- input held at VDD/2
µs
mV
mV
ns 1 pF load capacitance on input
db
V
Op Amp AC Characteristics
CM20 SR
Slew Rate(3)
3.7
7.5
16
V/µs 10 pF load
CM21a PM
Phase Margin (Configuration A)(3,4)
--
55
--
Degree G = 4V/V; 10 pF load
CM21b PM CM22 GM
Phase Margin (Configuration B)(3,5) Gain Margin(3)
--
40
--
Degree G = 4V/V; 10 pF load
--
20
--
db G = 100V/V; 10 pF load
CM23a GBW
Gain Bandwidth (Configuration A)(3,4)
--
10
--
MHz 10 pF load
CM23b GBW
Gain Bandwidth (Configuration B)(3,5)
--
6
--
MHz 10 pF load
Note 1:
2: 3: 4: 5: 6: 7: 8:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
Data in "Typ" column are at 3.3V, +25°C unless otherwise stated.
Parameter is characterized but not tested in manufacturing.
See Figure 25-6 for configuration information.
See Figure 25-7 for configuration information.
Resistances can vary by ±10% between op amps.
These parameters have a combined effect on the actual performance of the comparator.
Input resistance (R1) must be less than or equal to 2 kOhm. The resulting minimum gain of the op amp circuit is equal to four.
2011-2020 Microchip Technology Inc.
DS70000657J-page 461
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min.
Typ.(2)
Max.
Units
Conditions
Op Amp DC Characteristics
CM40 VCMR
Common-Mode Input Voltage Range
AVSS
--
AVDD
V
CM41 CMRR
Common-Mode Rejection Ratio(3)
--
40
--
db VCM = AVDD/2
CM42 VOFFSET
Op Amp Offset Voltage(3)
-30
±5
+30
mV
CM43 VGAIN
Open-Loop Voltage Gain(3)
--
90
--
db
CM44 IOS
Input Offset Current
--
--
--
-- See pad leakage
currents in Table 30-11
CM45 IB
Input Bias Current
--
--
--
-- See pad leakage
currents in Table 30-11
CM46 IOUT
Output Current
CM48 RFEEDBACK(8) Feedback Resistance Value
--
--
420
µA With minimum value of
RFEEDBACK (CM48)
8
--
--
k
CM49a VOADC
Output Voltage
AVSS + 0.077 -- AVDD 0.077 V IOUT = 420 µA
Measured at OAx Using AVSS + 0.037 -- AVDD 0.037 V IOUT = 200 µA
ADC(3,4)
AVSS + 0.018 -- AVDD 0.018 V IOUT = 100 µA
CM49b VOUT CM51 RINT1(6)
Output Voltage
AVSS + 0.210 -- AVDD 0.210 V IOUT = 420 µA
Measured at OAxOUT AVSS + 0.100 -- AVDD 0.100 V IOUT = 200 µA
Pin(3,4,5)
AVSS + 0.050 -- AVDD 0.050 V IOUT = 100 µA
Internal Resistance 1 (Configuration A and B)(3,4,5)
198
264
317
Min = -40ºC Typ = +25ºC Max = +125ºC
Note 1:
2: 3: 4: 5: 6: 7: 8:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
Data in "Typ" column are at 3.3V, +25°C unless otherwise stated.
Parameter is characterized but not tested in manufacturing.
See Figure 25-6 for configuration information.
See Figure 25-7 for configuration information.
Resistances can vary by ±10% between op amps.
These parameters have a combined effect on the actual performance of the comparator.
Input resistance (R1) must be less than or equal to 2 kOhm. The resulting minimum gain of the op amp circuit is equal to four.
DS70000657J-page 462
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-54: OP AMP/COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.
Max. Units
Conditions
VR310 TSET
Settling Time
--
1
10
µs Note 1
Note 1: Settling time is measured while CVRR = 1 and CVR[3:0] bits transition from `0000' to `1111'.
2: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
TABLE 30-55: OP AMP/COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristics
Min.
Typ.
Max.
Units
Conditions
VRD310 VRD311 VRD313 VRD314 Note 1:
2:
CVRES CVRAA
Resolution Absolute Accuracy(2)
CVRSRC/24 -- CVRSRC/32 LSb
--
±25
--
mV CVRSRC = 3.3V
CVRSRC Input Reference Voltage
0
-- AVDD + 0.3 V
CVROUT Buffer Output Resistance(2)
--
1.5k
--
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
Parameter is characterized but not tested in manufacturing.
2011-2020 Microchip Technology Inc.
DS70000657J-page 463
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-56: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions:3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
CTMU Current Source
CTMUI1 CTMUI2 CTMUI3 CTMUI4
IOUT1 IOUT2 IOUT3 IOUT4
Base Range(1) 10x Range(1) 100x Range(1) 1000x Range(1)
0.29
--
0.77 µA CTMUICON[9:8] = 01
3.85
--
7.7
µA CTMUICON[9:8] = 10
38.5
--
77
µA CTMUICON[9:8] = 11
385
--
770
µA CTMUICON[9:8] = 00
CTMUFV1 VF
Temperature Diode Forward -- 0.598 -- Voltage(1,2)
V TA = +25°C, CTMUICON[9:8] = 01
-- 0.658 --
V TA = +25°C, CTMUICON[9:8] = 10
-- 0.721 --
V TA = +25°C, CTMUICON[9:8] = 11
CTMUFV2 VFVR
Temperature Diode Rate of --
Change(1,2,3)
--
-1.92 -1.74
-- mV/ºC CTMUICON[9:8] = 01 -- mV/ºC CTMUICON[9:8] = 10
--
-1.56
-- mV/ºC CTMUICON[9:8] = 11
Note 1: Nominal value at center point of current trim range (CTMUICON[15:10] = 000000).
2: Parameters are characterized but not tested in manufacturing.
3: Measurements taken with the following conditions:
· VREF+ = AVDD = 3.3V · ADC configured for 10-bit mode
· ADC module configured for conversion speed of 500 ksps
· All PMDx bits are cleared (PMDx = 0) · Executing a while(1) statement · Device operating from the FRC with no PLL
DS70000657J-page 464
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-57: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
Device Supply
AD01 AVDD Module VDD Supply
Greater of: -- Lesser of: V
VDD 0.3
VDD + 0.3
or 3.0
or 3.6
AD02 AVSS Module VSS Supply
VSS 0.3 -- VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.5 --
AVDD
V VREFH = VREF+ VREFL = VREF- (Note 1)
AD05a
3.0
--
3.6
V VREFH = AVDD
VREFL = AVSS = 0
AD06 VREFL Reference Voltage Low
AVSS
-- AVDD 2.5 V Note 1
AD06a
0
--
0
V VREFH = AVDD
VREFL = AVSS = 0
AD07 VREF
Absolute Reference Voltage
2.5
--
3.6
V VREF = VREFH - VREFL
AD08 IREF AD09 IAD
Current Drain Operating Current(2)
--
--
10
µA ADC off
--
--
600
µA ADC on
--
5
--
mA ADC operating in 10-bit mode
(Note 1)
--
2
--
mA ADC operating in 12-bit mode
(Note 1)
Analog Input
AD12 VINH
Input Voltage Range VINH
VINL
--
VREFH
V This voltage reflects Sample-and-
Hold Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13 VINL
Input Voltage Range VINL
VREFL
-- AVSS + 1V V This voltage reflects Sample-andHold Channels 0, 1, 2 and 3 (CH0-CH3), negative input
AD17 RIN
Recommended Impedance of Analog Voltage Source
--
--
200
Impedance to achieve maximum
performance of ADC
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: Parameter is characterized but not tested in manufacturing.
2011-2020 Microchip Technology Inc.
DS70000657J-page 465
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-58: ADC MODULE SPECIFICATIONS (12-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
ADC Accuracy (12-Bit Mode)
AD20a Nr
Resolution
12 Data Bits
bits
AD21a INL
Integral Nonlinearity
-2.5
--
2.5 LSb -40°C TA +85°C (Note 2)
-5.5
--
5.5 LSb +85°C TA +125°C (Note 2)
AD22a DNL
Differential Nonlinearity
-1
--
1
LSb -40°C TA +85°C (Note 2)
AD23a GERR
Gain Error(3)
-1
--
1
LSb +85°C TA +125°C (Note 2)
-10
--
10 LSb -40°C TA +85°C (Note 2)
-10
--
10 LSb +85°C TA +125°C (Note 2)
AD24a EOFF
Offset Error
-5
--
5
LSb -40°C TA +85°C (Note 2)
-5
--
5
LSb +85°C TA +125°C (Note 2)
AD25a
-- Monotonicity
--
--
--
-- Guaranteed
AD30a THD
Dynamic Performance (12-Bit Mode)
Total Harmonic Distortion(3) --
75
--
dB
AD31a SINAD Signal to Noise and Distortion(3)
--
68
--
dB
AD32a SFDR
Spurious Free Dynamic Range(3)
--
80
--
dB
AD33a FNYQ
Input Signal Bandwidth(3)
--
250
--
kHz
AD34a ENOB Effective Number of Bits(3) 11.09 11.3
--
bits
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: For all accuracy specifications, VINL = AVSS = VREFL = 0V and AVDD = VREFH = 3.6V.
3: Parameters are characterized but not tested in manufacturing.
DS70000657J-page 466
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-59: ADC MODULE SPECIFICATIONS (10-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
ADC Accuracy (10-Bit Mode)
AD20b Nr
Resolution
10 Data Bits
bits
AD21b INL
Integral Nonlinearity
-0.625 -- 0.625 LSb -40°C TA +85°C (Note 2)
-1.5
--
1.5 LSb +85°C TA +125°C (Note 2)
AD22b DNL
Differential Nonlinearity
-0.25 -- 0.25 LSb -40°C TA +85°C (Note 2)
-0.25 -- 0.25 LSb +85°C TA +125°C (Note 2)
AD23b GERR
Gain Error
-2.5
--
2.5 LSb -40°C TA +85°C (Note 2)
-2.5
--
2.5 LSb +85°C TA +125°C (Note 2)
AD24b EOFF
Offset Error
-1.25 -- 1.25 LSb -40°C TA +85°C (Note 2)
-1.25 -- 1.25 LSb +85°C TA +125°C (Note 2)
AD25b
-- Monotonicity
--
--
--
-- Guaranteed
AD30b THD
Dynamic Performance (10-Bit Mode)
Total Harmonic Distortion(3)
--
64
--
dB
AD31b SINAD
Signal to Noise and Distortion(3)
--
57
--
dB
AD32b SFDR
AD33b FNYQ AD34b ENOB
Spurious Free Dynamic Range(3) Input Signal Bandwidth(3) Effective Number of Bits(3)
--
72
--
dB
--
550
--
kHz
--
9.4
-- bits
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: For all accuracy specifications, VINL = AVSS = VREFL = 0V and AVDD = VREFH = 3.6V.
3: Parameters are characterized but not tested in manufacturing.
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FIGURE 30-36:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC[2:0] = 000, SSRCG = 0)
AD50
ADCLK
Instruction Execution
Set SAMP
SAMP
AD61
DONE AD1IF
Clear SAMP
AD60 TSAMP
AD55
12
34 5 6
789
1 Software sets AD1CON1. SAMP to start sampling.
2 Sampling starts after discharge period. TSAMP is described in "Analog-to-Digital Converter (ADC)" (DS70621) in the "dsPIC33/PIC24 Family Reference Manual".
3 Software clears AD1CON1. SAMP to start conversion.
4 Sampling ends, conversion sequence starts.
5 Convert bit 11. 6 Convert bit 10. 7 Convert bit 1. 8 Convert bit 0. 9 One TAD for end of conversion.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-60: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
Clock Parameters
AD50 TAD ADC Clock Period
117.6
--
--
ns
AD51 tRC
ADC Internal RC Oscillator Period(2) --
250
--
ns
Conversion Rate
AD55 tCONV Conversion Time
-- 14 TAD
ns
AD56 FCNV Throughput Rate
--
--
500 ksps
AD57a TSAMP Sample Time when Sampling any 3 TAD
--
--
--
ANx Input
AD57b TSAMP Sample Time when Sampling the Op 3 TAD
--
--
--
Amp Outputs (Configuration A and Configuration B)(4,5)
Timing Parameters
AD60 tPCS
Conversion Start from Sample Trigger(2,3)
2 TAD
-- 3 TAD
-- Auto-convert trigger is not selected
AD61 tPSS
Sample Start from Setting Sample (SAMP) bit(2,3)
2 TAD
-- 3 TAD
--
AD62 tCSS
Conversion Completion to Sample Start (ASAM = 1)(2,3)
-- 0.5 TAD --
--
AD63 tDPU
Time to Stabilize Analog Stage from ADC Off to ADC On(2,3)
--
--
20
µs Note 6
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: Parameters are characterized but not tested in manufacturing.
3: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (AD1CON1[15]) = 1). During this time, the ADC result is indeterminate.
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FIGURE 30-37:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS[1:0] = 01, SIMSAM = 0, ASAM = 0, SSRC[2:0] = 000, SSRCG = 0)
AD50
ADCLK
Instruction Execution
Set SAMP
SAMP
AD61
DONE AD1IF
Clear SAMP
AD60 TSAMP
AD55
AD55
12
34 5 6
78
1 Software sets AD1CON1. SAMP to start sampling.
2 Sampling starts after discharge period. TSAMP is described in "Analog-to-Digital Converter (ADC)" (DS70621) in the "dsPIC33/PIC24 Family Reference Manual".
3 Software clears AD1CON1. SAMP to start conversion.
4 Sampling ends, conversion sequence starts.
56
78
5 Convert bit 9. 6 Convert bit 8. 7 Convert bit 0. 8 One TAD for end of conversion.
FIGURE 30-38:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS[1:0] = 01, SIMSAM = 0, ASAM = 1, SSRC[2:0] = 111, SSRCG = 0, SAMC[4:0] = 00010)
ADCLK
AD50
Instruction Execution
Set ADON
SAMP
AD1IF DONE
1
TSAMP 2
AD55
AD55
34
56 734
56
AD62 TSAMP
AD55
8
1 Software sets AD1CON1. ADON to start AD operation.
2 Sampling starts after discharge period. TSAMP is described in "Analog-to-Digital Converter (ADC)" (DS70621) in the "dsPIC33/PIC24 Family Reference Manual".
3 Convert bit 9.
4 Convert bit 8.
5 Convert bit 0. 6 One TAD for end of conversion. 7 Begin conversion of next channel. 8 Sample for time specified by SAMC[4:0].
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-61: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
Clock Parameters
AD50 TAD
ADC Clock Period
76
--
--
ns
AD51 tRC
ADC Internal RC Oscillator Period(2) --
250
--
ns
Conversion Rate
AD55 tCONV Conversion Time
-- 12 TAD --
--
AD56 FCNV Throughput Rate
--
--
1.1 Msps Using simultaneous
sampling
AD57a TSAMP Sample Time when Sampling any 2 TAD --
--
--
ANx Input
AD57b TSAMP Sample Time when Sampling the 4 TAD --
--
--
Op Amp Outputs (Configuration A
and Configuration B)(4,5)
Timing Parameters
AD60 tPCS
Conversion Start from Sample Trigger(2,3)
2 TAD
--
3 TAD
-- Auto-convert trigger is not selected
AD61 tPSS
Sample Start from Setting Sample (SAMP) bit(2,3))
2 TAD
--
3 TAD
--
AD62 tCSS
Conversion Completion to Sample Start (ASAM = 1)(2,3)
-- 0.5 TAD --
--
AD63 tDPU
Time to Stabilize Analog Stage from ADC Off to ADC On(2,3)
--
--
20
µs Note 6
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: Parameters are characterized but not tested in manufacturing.
3: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (AD1CON1[15]) = 1). During this time, the ADC result is indeterminate.
TABLE 30-62: DMA MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No.
Characteristic
Min.
Typ.(1)
Max. Units Conditions
DM1 DMA Byte/Word Transfer Latency
1 TCY(2)
--
--
ns
Note 1: These parameters are characterized, but not tested in manufacturing. 2: Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.
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NOTES:
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
31.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C.
The specifications between -40°C to +150°C are identical to those shown in Section 30.0 "Electrical Characteristics" for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, Parameter DC10 in Section 30.0 "Electrical Characteristics" is the Industrial and Extended temperature equivalent of HDC10.
Absolute maximum ratings for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X high-temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias(2) .........................................................................................................-40°C to +150°C Storage temperature .............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(3) .................................................... -0.3V to 3.6V Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3)..................................................... -0.3V to 5.5V Maximum current out of VSS pin .............................................................................................................................60 mA Maximum current into VDD pin(4).............................................................................................................................60 mA Maximum junction temperature............................................................................................................................. +155°C Maximum current sourced/sunk by any 4x I/O pin ..................................................................................................10 mA Maximum current sourced/sunk by any 8x I/O pin ..................................................................................................15 mA Maximum current sunk by all ports combined.........................................................................................................70 mA Maximum current sourced by all ports combined(4) ................................................................................................70 mA
Note 1: Stresses above those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability.
2: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc.
3: Refer to the "Pin Diagrams" section for 5V tolerant pins.
4: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
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31.1 High-Temperature DC Characteristics
TABLE 31-1: OPERATING MIPS VS. VOLTAGE
Characteristic
VDD Range (in Volts)
Temperature Range (in °C)
Max MIPS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
HDC5 Note 1:
3.0 to 3.6V(1)
-40°C to +150°C
40
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules, such as the ADC, may have degraded performance. Device functionality is tested but not characterized.
TABLE 31-2: THERMAL OPERATING CONDITIONS
Rating
High-Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range
Power Dissipation: Internal Chip Power Dissipation:
PINT = VDD x (IDD IOH) I/O Pin Power Dissipation:
I/O = ({VDD VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation
Symbol Min
Typ
Max Unit
TJ
-40
--
+165
°C
TA
-40
--
+150
°C
PD
PINT + PI/O
W
PDMAX
(TJ TA)/JA
W
TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Parameter No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
Operating Voltage
HDC10 Supply Voltage
VDD
--
3.0
3.3
3.6
V -40°C to +150°C
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Parameter No.
Typical
Max
Units
Conditions
Power-Down Current (IPD)
HDC60e
1400
2500
µA
+150°C
3.3V Base Power-Down Current
(Notes 1 and 3)
HDC61c
15
--
µA
+150°C
3.3V Watchdog Timer Current: IWDT
(Notes 2 and 4)
Note 1: 2:
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off and VREGS (RCON[8]) = 1.
The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
3: These currents are measured on the device containing the most memory in this family.
4: These parameters are characterized, but are not tested in manufacturing.
TABLE 31-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Parameter No.
Typical
Max
Units
Conditions
HDC44e
12
30
mA
+150°C
3.3V
40 MIPS
TABLE 31-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Parameter No.
Typical
Max
Units
Conditions
HDC20
9
HDC22
16
HDC23
30
15
mA
+150°C
3.3V
25
mA
+150°C
3.3V
50
mA
+150°C
3.3V
10 MIPS 20 MIPS 40 MIPS
TABLE 31-7: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Parameter No.
Typical
Max
Doze Ratio
Units
Conditions
HDC72a
24
HDC72f(1)
14
HDC72g(1)
12
35
1:2
mA
--
1:64
mA +150°C
3.3V
--
1:128
mA
40 MIPS
Note 1: Parameters with Doze ratios of 1:64 and 1:128 are characterized, but are not tested in manufacturing.
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TABLE 31-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Param. Symbol
Characteristic
Min. Typ. Max. Units
Conditions
HDO10 VOL HDO20 VOH HDO20A VOH1
Output Low Voltage 4x Sink Driver Pins(2) Output Low Voltage 8x Sink Driver Pins(3) Output High Voltage 4x Source Driver Pins(2) Output High Voltage 8x Source Driver Pins(3) Output High Voltage 4x Source Driver Pins(2)
--
-- 0.4
V
--
-- 0.4
V
2.4
----
V
2.4
----
V
1.5
----
V
2.0
----
3.0
----
Output High Voltage 8x Source Driver Pins(3)
1.5
----
V
2.0
----
3.0
----
Note 1: 2: 3:
Parameters are characterized, but not tested.
Includes all I/O pins that are not 8x Sink Driver pins (see below).
Includes the following pins: For devices with less than 64 pins: RA3, RA4, RA9, RB[15:7] and RC3 For 64-pin devices: RA4, RA9, RB[15:7], RC3 and RC15
IOL 5 mA, VDD = 3.3V (Note 1)
IOL 8 mA, VDD = 3.3V (Note 1)
IOH -10 mA, VDD = 3.3V (Note 1)
IOH 15 mA, VDD = 3.3V (Note 1)
IOH -3.9 mA, VDD = 3.3V (Note 1)
IOH -3.7 mA, VDD = 3.3V (Note 1)
IOH -2 mA, VDD = 3.3V (Note 1)
IOH -7.5 mA, VDD = 3.3V (Note 1)
IOH -6.8 mA, VDD = 3.3V (Note 1)
IOH -3 mA, VDD = 3.3V (Note 1)
TABLE 31-9: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C for High Temperature
Param. Symbol
Characteristic(1)
Min. Typ. Max. Units
Conditions
Program Flash Memory
HD130 EP
Cell Endurance
10,000 --
HD134 TRETD Characteristic Retention
20
--
-- E/W -40°C to +150°C(2) -- Year 1000 E/W cycles or less and no
other specifications are violated
Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing.
2: Programming of the Flash memory is allowed up to +150°C.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
31.2 AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X AC characteristics and timing parameters for high-temperature devices. However, all AC timing specifications in this section are the same as those in Section 30.2 "AC Characteristics and Timing Parameters", with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, Parameter OS53 in Section 30.2 "AC Characteristics and Timing Parameters" is the Industrial and Extended temperature equivalent of HOS53.
TABLE 31-10: TEMPERATURE AND VOLTAGE SPECIFICATIONS AC
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C Operating voltage VDD range as described in Table 31-1.
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 for all pins except OSC2
Load Condition 2 for OSC2
VDD/2
RL
Pin
CL
VSS
Pin
CL
VSS
RL = 464 CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
TABLE 31-11: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Param No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
HOS53 DCLK
CLKO Stability (Jitter)(1)
-5
0.5
5
% Measured over 100 ms
period
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula:
Peripheral Clock Jitter = ------------------------------D----C----L---K------------------------------
P----e---r--i--p---h---e---r--a---lF---B-O---i-St---C-R---a---t--e----C----l--o---c--k-
For example: FOSC = 32 MHz, DCLK = 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz.
SPI SCK Jitter =
---------D----C----L---K---------
3--2-2----M--M----H-H---z--z-
=
-5----%---16
=
5---4-%---
= 1.25%
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TABLE 31-12: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature +125°C TA +150°C for High Temperature
Param No.
Characteristic
Min Typ Max Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
H20 FRC
-3
-2
+3
% +125°C TA +150°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V.
TABLE 31-13: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Param No.
Characteristic
Min Typ Max Units
Conditions
LPRC @ 32.768 kHz(1,2)
HF21 LPRC
-30
--
+30
% -40°C TA +150°C VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT). See Section 27.5 "Watchdog Timer (WDT)" for more information.
TABLE 31-14: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Param No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
Op Amp DC Characteristics
HCM42 VOFFSET Op Amp Offset Voltage
-40
±5
+40
mV
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 31-15: ADC MODULE SPECIFICATIONS (12-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Param No.
Symbol
Characteristic
Min Typ Max Units
Conditions
HAD20a Nr
Resolution(3)
ADC Accuracy (12-Bit Mode)(1)
12 Data Bits
bits
HAD21a INL HAD22a DNL HAD23a GERR HAD24a EOFF
Integral Nonlinearity
-5.5
--
5.5 LSb
Differential Nonlinearity -1
--
1
LSb
Gain Error
-10
--
10 LSb
Offset Error
-5
--
5
LSb
Dynamic Performance (12-Bit Mode)(2)
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
HAD33a Note 1:
2: 3:
FNYQ
Input Signal Bandwidth --
--
200 kHz
These parameters are characterized, but are tested at 20 ksps only.
These parameters are characterized by similarity, but are not tested in manufacturing.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
TABLE 31-16: ADC MODULE SPECIFICATIONS (10-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C
Param No.
Symbol
Characteristic
Min Typ Max Units
Conditions
HAD20b Nr
Resolution(3)
ADC Accuracy (10-Bit Mode)(1)
10 Data Bits
bits
HAD21b INL HAD22b DNL HAD23b GERR HAD24b EOFF
Integral Nonlinearity
-1.5
--
1.5 LSb
Differential Nonlinearity -0.25 -- 0.25 LSb
Gain Error
-2.5
--
2.5 LSb
Offset Error
-1.25 -- 1.25 LSb
Dynamic Performance (10-Bit Mode)(2)
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V
HAD33b Note 1:
2: 3:
FNYQ
Input Signal Bandwidth
--
--
400 kHz
These parameters are characterized, but are tested at 20 ksps only.
These parameters are characterized by similarity, but are not tested in manufacturing.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
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NOTES:
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2011-2020 Microchip Technology Inc.
32.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 32-1:
VOH 4x DRIVER PINS
FIGURE 32-3:
VOL 4x DRIVER PINS
IOH(A)
-0.050
VOH (V)
-0.045 3.6V
-0.040 -0.035 -0.030
3.3V 3V
-0.025
-0.020 -0.015
Absolute Maximum
-0.010
-0.005
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
0.050 0.045
VOL(V)
3.6V
0.040
3.3V
0.035
3V
0.030
0.025
0.020 0.015
Absolute Maximum
0.010
0.005
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 32-2:
VOH 8x DRIVER PINS
IOH(A)
-0.080 -0.070 -0.060
3.6V 3.3V
-0.050
3V
VOH(V)
-0.040
-0.030 -0.020
Absolute Maximum
-0.010
0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 32-4:
0.080
VOL 8x DRIVER PINS VOL(V)
8X
3.6V
0.070
3.3V
0.060
3V
0.050
IOH(A)
0.040
0.030 0.020
Absolute Maximum
0.010
0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
DS70000657J-page 481
2011-2020 Microchip Technology Inc.
DS70000657J-page 482
FIGURE 32-5:
TYPICAL IPD CURRENT @ VDD = 3.3V
IPD Current (µA)
800.00 700.00 600.00 500.00 400.00 300.00 200.00 100.00
0.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (Celsius)
FIGURE 32-6:
TYPICAL/MAXIMUM IDD CURRENT @ VDD = 3.3V
FIGURE 32-7:
TYPICAL IDOZE CURRENT @ VDD = 3.3V
IDOZE Current (mA)
45.00
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
1:1
1:2
1:4
1:8
1:16 1:32 1:64 1:128
Doze Ratio
FIGURE 32-8:
TYPICAL IIDLE CURRENT @ VDD = 3.3V
IIDLE Current (mA)
25.00
20.00
15.00
10.00 5.00
IIDLE (EC+PLL)
0.00
IIDLE (EC)
0
10
20
30
40
50
60
70
MIPS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 483
2011-2020 Microchip Technology Inc.
FIGURE 32-9:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FRC Frequency (kHz)
7380 7370 7360 7350 7340 7330 7320 7310 7300 7290 7280
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (Celsius)
FIGURE 32-10: TYPICAL LPRC FREQUENCY @ VDD = 3.3V
36
LPRC Frequency (kHz)
Frequency(KHx)
35 34 33 32 31 30 29 28
)LPRC
27 26 25
24 -40C
25C
125C 150C
min 25.2 30.8
30
29.6
mean 28.9
32
31.2 30.8
max 32.8 34.8
34
33.6
min mean max
FIGURE 32-11:
TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE
0.850 0.800
Forward Voltage (V)
0.750 0.700 0.650 0.600 0.550 0.500 0.450 0.400
VF = 0.721 VF = 0.658 VF = 0.598
65 µA, V6F.V5Rµ=A,-1V.5F0V6.6Rm5=Vµ-/A1ºC,.7V4FVmRV=/ºC-1.92 mV/ºC
0.350 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Temperature (Celsius)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
NOTES:
DS70000657J-page 484
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
33.0 PACKAGING INFORMATION
33.1 Package Marking Information
28-Lead SPDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33EP64GP 502-I/SP e3
1310017
28-Lead SOIC (.300")
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33EP64GP 502-I/SO e3
1310017
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX
YYWWNNN
Example
dsPIC33EP64 GP502-I/SS e3
1310017
28-Lead QFN-S (6x6x0.9 mm)
XXXXXXXX XXXXXXXX YYWWNNN
Example
33EP64GP 502-I/MM
1310017
Legend:
XX...X Y YY WW NNN
e3 *
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3) can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
2011-2020 Microchip Technology Inc.
DS70000657J-page 485
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
33.1 Package Marking Information (Continued) 36-Lead VTLA (TLA)
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
YYWWNNN
36-Lead UQFN (5x5 mm)
33EP64GP 504-I/TL e3
1310017
Example
XXXXXXX XXXXXXX XXXXXXX YYWWNNN
44-Lead VTLA (TLA)
33EP64GP 503-I/TLe3 1310017
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
YYWWNNN
44-Lead TQFP
33EP64GP 504-I/TL e3
1310017
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
YYWWNNN
44-Lead QFN (8x8x0.9 mm)
XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX
YYWWNNN
33EP64GP 504-I/PT e3
1310017
Example
33EP64GP 504-I/ML e3
1310017
DS70000657J-page 486
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
33.1 Package Marking Information (Continued) 48-Lead UQFN (6x6x0.5 mm)
Example
XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX
YYWWNNN
33EP64GP 504-I/MV e3
1310017
64-Lead QFN (9x9x0.9 mm)
XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX
YYWWNNN
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
YYWWNNN
Example
dsPIC33EP 64GP506 -I/MR e3
1310017
Example
dsPIC33EP 64GP506 -I/PT e3
1310017
2011-2020 Microchip Technology Inc.
DS70000657J-page 487
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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DS70000657J-page 488
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011-2020 Microchip Technology Inc.
DS70000657J-page 489
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS70000657J-page 490
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2011-2020 Microchip Technology Inc.
DS70000657J-page 491
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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2011-2020 Microchip Technology Inc.
DS70000657J-page 493
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
/HDG3ODVWLF6KULQN6PDOO2XWOLQH66 PP%RG\>6623@
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DS70000657J-page 494
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
DS70000657J-page 495
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 496
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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2011-2020 Microchip Technology Inc.
DS70000657J-page 497
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN] With Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
NOTE 1
D
N
A B
SEE DETAIL A
1 2
(DATUM B) (DATUM A)
2X 0.10 C
2X 0.10 C
E
TOP VIEW
D2
0.10 C A B
0.10 C C
A
36X 0.08 C
SEATING PLANE
SIDE VIEW
0.10 C A B
E2
2 1
NOTE 1
L
N
e
BOTTOM VIEW
K
16X b 0..07 0.05
CAB C
Microchip Technology Drawing C04-436M5 Rev B Sheet 1 of 2
DS70000657J-page 498
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN] With Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
CA
SEATING PLANE
(A3)
A1
DETAIL A
Notes:
Units
Dimension Limits
Number of Terminals
N
Pitch
e
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed-Pad
K
MILLIMETERS
MIN
NOM
MAX
36
0.40 BSC
0.50
0.55
0.60
0.00
0.02
0.05
0.152 REF
5.00 BSC
3.60
3.70
3.80
5.00 BSC
3.60
3.70
3.80
0.15
0.20
0.25
0.30
0.40
0.50
0.25 REF
1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-436M5 Rev B Sheet 2 of 2
2011-2020 Microchip Technology Inc.
DS70000657J-page 499
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN] With Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
C1 X2
EV 36
1 2
Y2 C2
EV
Y3 ØV
G
Y1
R X3 E
X1 SILK SCREEN
RECOMMENDED LAND PATTERN
Notes:
Units
Dimension Limits
Contact Pitch
E
Center Pad Width
X2
Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X36)
X1
Contact Pad Length (X36
Y1
Corner Pad Width (X4)
X3
Corner Pad Length (X4)
Y3
Corner Pad Radius
R
Contact Pad to Center Pad (X36) G
Thermal Via Diameter
V
Thermal Via Pitch
EV
MILLIMETERS
MIN
NOM
MAX
0.40 BSC
3.80
3.80
5.00
5.00
0.20
0.80
0.85
0.85
0.10
0.20
0.30
1.00
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process
Microchip Technology Drawing C04-2436M5 Rev B
DS70000657J-page 500
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
DS70000657J-page 501
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 502
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2011-2020 Microchip Technology Inc.
DS70000657J-page 503
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
44-Terminal Very Thin Leadless Array Package (TL) 6x6x0.9 mm Body With Exposed Pad [VTLA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N NOTE 1
1 2
AB
E (DATUM B)
2X 0.20 C
2X 0.20 C
C
SEATING
A
PLANE
11 10 (NE-1) X e
(DATUM A)
TOP VIEW
0.10 C
A1
SIDE VIEW
D2
0.08 C
0.10 C A B 22
23 DETAIL A
0.10 C A
E2
2 32
1
N
33
44X K
(ND-1) X e
BOTTOM VIEW
Microchip Technology Drawing C04-157D Sheet 1 of 2
DS70000657J-page 504
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
44-Terminal Very Thin Leadless Array Package (TL) 6x6x0.9 mm Body With Exposed Pad [VTLA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(DATUM A OR B)
e/2 e
44X L
DETAIL A
44X b
0.10 0.05
CAB C
Units
Dimension Limits
Number of Terminals
N
Number of Terminals per Side
ND
Number of Terminals per Side
NE
Pitch
e
Overall Height
A
Standoff
A1
Overall Width
E
Exposed Pad Width
E2
Overall Length
D
Exposed Pad Length
D2
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed Pad
K
MIN
0.80 0.025 4.40 4.40 0.20 0.20 0.20
MILLIMETERS NOM 44 12 10
0.50 BSC 0.90 -
6.00 BSC 4.55
6.00 BSC 4.55 0.25 0.25 -
MAX
1.00 0.075 4.70 4.70 0.30 0.30
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-157D Sheet 2 of 2
2011-2020 Microchip Technology Inc.
DS70000657J-page 505
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657J-page 506
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
NOTE 2
D
A
D1
B
(DATUM A) (DATUM B)
NOTE 1
A
2X 0.20 H A B N
2X
123
0.20 H A B
TOP VIEW
C SEATING PLANE
0.10 C
A
SIDE VIEW
123
N NOTE 1
E1 E
A
4X 11 TIPS 0.20 C A B A2
A1
e
BOTTOM VIEW
44 X b 0.20 C A B
Microchip Technology Drawing C04-076C Sheet 1 of 2
2011-2020 Microchip Technology Inc.
DS70000657J-page 507
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
H c
L
(L1)
SECTION A-A
Units Dimension Limits
MILLIMETERS
MIN
NOM
MAX
Number of Leads Lead Pitch Overall Height Standoff Molded Package Thickness
N
44
e
0.80 BSC
A
-
-
1.20
A1
0.05
-
0.15
A2
0.95
1.00
1.05
Notes:
Overall Width Molded Package Width Overall Length Molded Package Length Lead Width Lead Thickness Lead Length Footprint Foot Angle
E
12.00 BSC
E1
10.00 BSC
D
12.00 BSC
D1
10.00 BSC
b
0.30
0.37
0.45
c
0.09
-
0.20
L
0.45
0.60
0.75
L1
1.00 REF
0°
3.5°
7°
1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076C Sheet 2 of 2
DS70000657J-page 508
2011-2020 Microchip Technology Inc.
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44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
C1 44
1 2
G C2
Y1
X1
E
RECOMMENDED LAND PATTERN
SILK SCREEN
Notes:
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X44)
X1
Contact Pad Length (X44)
Y1
Distance Between Pads
G
MILLIMETERS
MIN
NOM
MAX
0.80 BSC
11.40
11.40
0.55
1.50
0.25
1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2076B
2011-2020 Microchip Technology Inc.
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44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N NOTE 1
1 2
AB
(DATUM B) (DATUM A) 2X
0.20 C
2X 0.20 C
C
SEATING PLANE
A A3
L
TOP VIEW
SIDE VIEW
D2
E
0.10 C
A1
44X 0.08 C
0.10 C A B
0.10 C A B
E2
K 2 1
NOTE 1
N
e
BOTTOM VIEW
44X b 0.07 0.05
CAB C
Microchip Technology Drawing C04-103D Sheet 1 of 2
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44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
Pitch
e
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Width
E
Exposed Pad Width
E2
Overall Length
D
Exposed Pad Length
D2
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed-Pad
K
MILLIMETERS
MIN
NOM
MAX
44
0.65 BSC
0.80
0.90
1.00
0.00
0.02
0.05
0.20 REF
8.00 BSC
6.25
6.45
6.60
8.00 BSC
6.25
6.45
6.60
0.20
0.30
0.35
0.30
0.40
0.50
0.20
-
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103D Sheet 2 of 2
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44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
44
1 2
C1 X2 EV
EV C2 Y2
G2
ØV G1
Y1
E
SILK SCREEN
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X44)
X1
Contact Pad Length (X44)
Y1
Contact Pad to Contact Pad (X40) G1
Contact Pad to Center Pad (X44) G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MILLIMETERS
MIN
NOM
MAX
0.65 BSC
6.60
6.60
8.00
8.00
0.35
0.85
0.30
0.28
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process
Microchip Technology Drawing No. C04-2103C
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
NOTE 2
D D1
D1/2 D
A
SEE DETAIL 1
N
4X N/4 TIPS 0.20 C A-B D NOTE 1
E1/2 B
A
A
E1 E
123
TOP VIEW
4X 0.20 H A-B D
A C
SEATING PLANE
0.08 C
e
A2 0.05
64 X b
A1
0.08 C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
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64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
H
E L
(L1)
SECTION A-A
c
T X=A--B OR D
X
e/2
DETAIL 1
Notes:
Units
Dimension Limits
Number of Leads
N
Lead Pitch
e
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
L1
Foot Angle
I
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
Lead Thickness
c
Lead Width
b
Mold Draft Angle Top
D
Mold Draft Angle Bottom
E
MILLIMETERS
MIN
NOM
MAX
64
0.50 BSC
-
-
1.20
0.95
1.00
1.05
0.05
-
0.15
0.45
0.60
0.75
1.00 REF
0°
3.5°
7°
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
0.09
-
0.20
0.17
0.22
0.27
11°
12°
13°
11°
12°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
C1
E
C2 G
Y1 X1
RECOMMENDED LAND PATTERN
Notes:
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X28)
X1
Contact Pad Length (X28)
Y1
Distance Between Pads
G
MILLIMETERS
MIN
NOM
0.50 BSC
11.40
11.40
0.20
1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances.
MAX
0.30 1.50
Microchip Technology Drawing C04-2085B Sheet 1 of 1
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APPENDIX A: REVISION HISTORY
Revision A (April 2011)
This is the initial released version of the document.
Revision B (July 2011)
This revision includes minor typographical and formatting changes throughout the data sheet text.
All other major changes are referenced by their respective section in Table A-1.
TABLE A-1: MAJOR SECTION UPDATES
Section Name
Update Description
"High-Performance, 16-bit Digital Signal Controllers and Microcontrollers"
Section 4.0 "Memory Organization"
Section 5.0 "Flash Program Memory"
Changed all pin diagrams references of VLAP to TLA.
Updated the All Resets values for CLKDIV and PLLFBD in the System Control Register Map (see Table 4-35). Updated "one word" to "two words" in the first paragraph of Section 5.2 "RTSP Operation".
Section 9.0 "Oscillator Configuration"
Updated the PLL Block Diagram (see Figure 9-2).
Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL (FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL).
Changed (FRCDIVN + PLL) to (FRCPLL) for COSC[2:0] = 001 and NOSC[2:0] = 001 in the Oscillator Control Register (see Register 9-1).
Changed the POR value from 0 to 1 for the DOZE[1:0] bits, from 1 to 0 for the FRCDIV[0] bit, and from 0 to 1 for the PLLPOST[0] bit; Updated the default definitions for the DOZE[2:0] and FRCDIV[2:0] bits and updated all bit definitions for the PLLPOST[1:0] bits in the Clock Divisor Register (see Register 9-2).
Changed the POR value from 0 to 1 for the PLLDIV[5:4] bits and updated the default definitions for all PLLDIV[8:0] bits in the PLL Feedback Division Register (see Register 9-2).
Section 22.0 "Charge Time Updated the bit definitions for the IRNG[1:0] bits in the CTMU Current Control Measurement Unit (CTMU)" Register (see Register 22-3).
Section 25.0 "Op amp/ Comparator Module"
Updated the voltage reference block diagrams (see Figure 25-1 and Figure 25-2).
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TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 30.0 "Electrical Characteristics"
Update Description Removed Voltage on VCAP with respect to Vss and added Note 5 in Absolute Maximum Ratings(1).
Section 31.0 "Packaging Information"
"Product Identification System"
Removed Parameter DC18 (VCORE) and Note 3 from the DC Temperature and Voltage Specifications (see Table 30-4). Updated Note 1 in the DC Characteristics: Operating Current (IDD) (see Table 30-6). Updated Note 1 in the DC Characteristics: Idle Current (IIDLE) (see Table 30-7). Changed the Typical values for Parameters DC60a-DC60d and updated Note 1 in the DC Characteristics: Power-down Current (IPD) (see Table 30-8). Updated Note 1 in the DC Characteristics: Doze Current (IDOZE) (see Table 30-9). Updated Note 2 in the Electrical Characteristics: BOR (see Table 30-12). Updated Parameters CM20 and CM31, and added Parameters CM44 and CM45 in the AC/DC Characteristics: Op amp/Comparator (see Table 30-14). Added the Op amp/Comparator Reference Voltage Settling Time Specifications (see Table 30-15). Added Op amp/Comparator Voltage Reference DC Specifications (see Table 30-16). Updated Internal FRC Accuracy Parameter F20a (see Table 30-21). Updated the Typical value and Units for Parameter CTMUI1, and added Parameters CTMUI4, CTMUFV1, and CTMUFV2 to the CTMU Current Source Specifications (see Table 30-55). Updated packages by replacing references of VLAP with TLA.
Changed VLAP to TLA.
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Revision C (December 2011)
This revision includes typographical and formatting changes throughout the data sheet text.
In addition, where applicable, new sections were added to each peripheral chapter that provide information and links to related resources, as well as helpful tips. For examples, see Section 20.1 "UART Helpful Tips" and Section 3.6 "CPU Resources".
All occurrences of TLA were updated to VTLA throughout the document, with the exception of the pin diagrams (updated diagrams were not available at time of publication).
A new chapter, Section 31.0 "DC and AC Device Characteristics Graphs", was added.
All other major changes are referenced by their respective section in Table A-2.
TABLE A-2: MAJOR SECTION UPDATES
Section Name
Update Description
"16-bit Microcontrollers and Digital Signal Controllers (up to 256-Kbyte Flash and 32-Kbyte SRAM) with HighSpeed PWM, Op amps, and Advanced Analog" Section 1.0 "Device Overview"
Section 2.0 "Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers" Section 3.0 "CPU"
Section 4.0 "Memory Organization"
Section 8.0 "Direct Memory Access (DMA)" Section 14.0 "Input Capture" Section 15.0 "Output Compare"
The content on the first page of this section was extensively reworked to provide the reader with the key features and functionality of this device family in an "at-a-glance" format.
Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/MC20X Block Diagram (see Figure 1-1), which now contains a CPU block and a reference to the CPU diagram. Updated the description and Note references in the Pinout I/O Descriptions for these pins: C1IN2-, C2IN2-, C3IN2-, OA1OUT, OA2OUT, and OA3OUT (see Table 1-1). Updated the Recommended Minimum Connection diagram (see Figure 2-1).
Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/MC20X CPU Block Diagram (see Figure 3-1). Updated the Status register definition in the Programmer's Model (see Figure 3-2). Updated the Data Memory Maps (see Figure 4-6 and Figure 4-11). Removed the DCB[1:0] bits from the OC1CON2, OC2CON2, OC3CON2, and OC4CON2 registers in the Output Compare 1 Through Output Compare 4 Register Map (see Table 4-10). Added the TRIG1 and TRGCON1 registers to the PWM Generator 1 Register Map (see Table 4-13). Added the TRIG2 and TRGCON2 registers to the PWM Generator 2 Register Map (see Table 4-14). Added the TRIG3 and TRGCON3 registers to the PWM Generator 3 Register Map (see Table 4-15). Updated the second note in Section 4.7.1 "Bit-Reversed Addressing Implementation". Updated the DMA Controller diagram (see Figure 8-1).
Updated the bit values for the ICx clock source of the ICTSEL[12:10] bits in the ICxCON1 register (see Register 14-1). Updated the bit values for the OCx clock source of the OCTSEL[2:0] bits in the OCxCON1 register (see Register 15-1). Removed the DCB[1:0] bits from the Output Compare x Control Register 2 (see Register 15-2).
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TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 16.0 "High-Speed Updated the High-Speed PWM Module Register Interconnection Diagram (see
PWM Module
Figure 16-2).
(dsPIC33EPXXXMC20X/50X Added the TRGCONx and TRIGx registers (see Register 16-12 and Register 16-14, and PIC24EPXXXMC20X respectively). Devices Only)"
Section 21.0 "Enhanced CAN (ECANTM) Module (dsPIC33EPXXXGP/MC50X Devices Only)"
Updated the CANCKS bit value definitions in CiCTRL1: ECAN Control Register 1 (see Register 21-1).
Section 22.0 "Charge Time Updated the IRNG[1:0] bit value definitions and added Note 2 in the CTMU Current Measurement Unit (CTMU)" Control Register (see Register 22-3).
Section 25.0 "Op amp/ Comparator Module"
Updated the Op amp/Comparator I/O Operating Modes Diagram (see Figure 25-1). Updated the User-programmable Blanking Function Block Diagram (see Figure 25-3). Updated the Digital Filter Interconnect Block Diagram (see Figure 25-4).
Added Section 25.1 "Op amp Application Considerations".
Added Note 2 to the Comparator Control Register (see Register 25-2).
Updated the bit definitions in the Comparator Mask Gating Control Register (see Register 25-5).
Section 27.0 "Special Features"
Updated the FICD Configuration Register, updated Note 1, and added Note 3 in the Configuration Byte Register Map (see Table 27-1).
Added Section 27.2 "User ID Words".
Section 30.0 "Electrical Characteristics"
Updated the following Absolute Maximum Ratings:
· Maximum current out of VSS pin · Maximum current into VDD pin
Added Note 1 to the Operating MIPS vs. Voltage (see Table 30-1).
Updated all Idle Current (IIDLE) Typical and Maximum DC Characteristics values (see Table 30-7).
Updated all Doze Current (IDOZE) Typical and Maximum DC Characteristics values (see Table 30-9).
Added Note 2, removed Parameter CM24, updated the Typical values Parameters CM10, CM20, CM21, CM32, CM41, CM44, and CM45, and updated the Minimum values for CM40 and CM41, and the Maximum value for CM40 in the AC/DC Characteristics: Op amp/Comparator (see Table 30-14).
Updated Note 2 and the Typical value for Parameter VR310 in the Op amp/ Comparator Reference Voltage Settling Time Specifications (see Table 30-15).
Added Note 1, removed Parameter VRD312, and added Parameter VRD314 to the Op amp/Comparator Voltage Reference DC Specifications (see Table 30-16).
Updated the Minimum, Typical, and Maximum values for Internal LPRC Accuracy (see Table 30-22).
Updated the Minimum, Typical, and Maximum values for Parameter SY37 in the Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements (see Table 30-24).
The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock Rate Summary (see Table 30-35)
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TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 30.0 "Electrical Characteristics" (Continued)
These SPI2 Timing Requirements were updated:
· Maximum value for Parameter SP10 and the minimum clock period value for SCKx in Note 3 (see Table 30-36, Table 30-37, and Table 30-38)
· Maximum value for Parameter SP70 and the minimum clock period value for SCKx in Note 3 (see Table 30-40 and Table 30-42)
· The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock Rate Summary (see Table 30-43)
These SPI1 Timing Requirements were updated: · Maximum value for Parameters SP10 and the minimum clock period value for
SCKx in Note 3 (see Table 30-44, Table 30-45, and Table 30-46) · Maximum value for Parameters SP70 and the minimum clock period value for
SCKx in Note 3 (see Table 30-47 through Table 30-50) · Minimum value for Parameters SP40 and SP41 see Table 30-44 through
Table 30-50) Updated all Typical values for the CTMU Current Source Specifications (see Table 30-55).
Updated Note1, the Maximum value for Parameter AD06, the Minimum value for AD07, and the Typical values for AD09 in the ADC Module Specifications (see Table 30-56).
Added Note 1 to the ADC Module Specifications (12-bit Mode) (see Table 30-57).
Added Note 1 to the ADC Module Specifications (10-bit Mode) (see Table 30-58).
Updated the Minimum and Maximum values for Parameter AD21b in the 10-bit Mode ADC Module Specifications (see Table 30-58).
Updated Note 2 in the ADC Conversion (12-bit Mode) Timing Requirements (see Table 30-59).
Updated Note 1 in the ADC Conversion (10-bit Mode) Timing Requirements (see Table 30-60).
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Revision D (December 2011)
This revision includes typographical and formatting changes throughout the data sheet text.
All other major changes are referenced by their respective section in Table A-3.
TABLE A-3: MAJOR SECTION UPDATES
Section Name
Update Description
"16-bit Microcontrollers and Digital Signal Controllers (up to 512-Kbyte Flash and 48-Kbyte SRAM) with HighSpeed PWM, Op amps, and Advanced Analog"
Removed the Analog Comparators column and updated the Op amps/Comparators column in Table 1 and Table 2.
Section 21.0 "Enhanced CAN (ECANTM) Module (dsPIC33EPXXXGP/MC50X Devices Only)"
Updated the CANCKS bit value definitions in CiCTRL1: ECAN Control Register 1 (see Register 21-1).
Section 30.0 "Electrical Characteristics"
Updated the VBOR specifications and/or its related note in the following electrical characteristics tables:
· Table 30-1 · Table 30-4 · Table 30-12 · Table 30-14 · Table 30-15 · Table 30-16 · Table 30-56 · Table 30-57 · Table 30-58 · Table 30-59 · Table 30-60
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Revision E (April 2012)
This revision includes typographical and formatting changes throughout the data sheet text.
All other major changes are referenced by their respective section in Table A-3.
TABLE A-4: MAJOR SECTION UPDATES
Section Name
Update Description
"16-bit Microcontrollers and Digital Signal Controllers (up to 512-Kbyte Flash and 48-Kbyte SRAM) with HighSpeed PWM, Op amps, and Advanced Analog"
The following 512-Kbyte devices were added to the General Purpose Families table (see Table 1): · PIC24EP512GP202 · PIC24EP512GP204 · PIC24EP512GP206 · dsPIC33EP512GP502 · dsPIC33EP512GP504 · dsPIC33EP512GP506
The following 512-Kbyte devices were added to the Motor Control Families table (see Table 2): · PIC24EP512MC202 · PIC24EP512MC204 · PIC24EP512MC206 · dsPIC33EP512MC202 · dsPIC33EP512MC204 · dsPIC33EP512MC206 · dsPIC33EP512MC502 · dsPIC33EP512MC504 · dsPIC33EP512MC506 Certain Pin Diagrams were updated to include the new 512-Kbyte devices.
Section 4.0 "Memory Organization"
Added a Program Memory Map for the new 512-Kbyte devices (see Figure 4-4). Added a Data Memory Map for the new dsPIC 512-Kbyte devices (see Figure 4-11). Added a Data Memory Map for the new PIC24 512-Kbyte devices (see Figure 4-16).
Section 7.0 "Interrupt Controller"
Updated the VECNUM bits in the INTTREG register (see Register 7-7).
Section 11.0 "I/O Ports"
Added tip 6 to Section 11.5 "I/O Helpful Tips".
Section 27.0 "Special Features"
The following modifications were made to the Configuration Byte Register Map (see Table 27-1): · Added the column Device Memory Size (Kbytes) · Removed Notes 1 through 4 · Added addresses for the new 512-Kbyte devices
Section 30.0 "Electrical Characteristics"
Updated the Minimum value for Parameter DC10 (see Table 30-4).
Added Power-Down Current (Ipd) parameters for the new 512-Kbyte devices (see Table 30-8).
Updated the Minimum value for Parameter CM34 (see Table 30-53).
Updated the Minimum and Maximum values and the Conditions for paramteer SY12 (see Table 30-22).
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Revision F (November 2012)
Removed "Preliminary" from data sheet footer.
Revision G (March 2013)
This revision includes the following global changes:
· changes "FLTx" pin function to "FLTx" on all occurrences
· adds Section 31.0 "High-Temperature Electrical Characteristics" for high-temperature (+150°C) data
This revision also includes minor typographical and formatting changes throughout the text.
Other major changes are referenced by their respective section in Table A-5.
TABLE A-5: MAJOR SECTION UPDATES
Section Name
Update Description
Cover Section
Section 4.0 "Memory Organization"
Section 6.0 "Resets"
Section 7.0 "Interrupt Controller" Section 9.0 "Oscillator Configuration"
Section 13.0 "Timer2/3 and Timer4/5" Section 15.0 "Output Compare" Section 16.0 "High-Speed PWM Module" Section 17.0 "Quadrature Encoder Interface (QEI) Module" Section 23.0 "10-Bit/12-Bit Analog-to-Digital Converter (ADC)" Section 25.0 "Op Amp/ Comparator Module"
Section 27.0 "Special Features"
· Changes internal oscillator specification to 1.0% · Changes I/O sink/source values to 12 mA or 6 mA · Corrects 44-pin VTLA pin diagram (pin 32 now shows as 5V tolerant)
· Deletes references to Configuration Shadow registers · Corrects the spelling of the JTAGIP and PTGWDTIP bits throughout · Corrects the Reset value of all IOCON registers as C000h · Adds footnote to Table 4-42 to indicate the absence of Comparator 3 in 28-pin
devices
· Removes references to cold and warm Resets, and clarifies the initial configuration of the device clock source on all Resets
· Corrects the definition of GIE as "Global Interrupt Enable" (not "General")
· Clarifies the behavior of the CF bit when cleared in software · Removes POR behavior footnotes from all control registers · Corrects the tuning range of the TUN[5:0] bits in Register 9-4 to an overall range
±1.5%
· Clarifies the presence of the ADC Trigger in 16-bit Timer3 and Timer5, as well as the 32-bit timers
· Corrects the first trigger source for SYNCSEL[4:0] (OCxCON2[4:0]) as OCxRS match
· Clarifies the source of the PWM interrupts in Figure 16-1 · Corrects the Reset states of IOCONx[15:14] in Register 16-13 as `11' · Clarifies the operation of the IMV[1:0] bits (QEICON[9:8]) with updated text and addi-
tional notes · Corrects the first prescaler value for QFVDIV[2:0] (QEI1OC[13:11]), now 1:128
· Adds note to Figure 23-1 that Op Amp 3 is not available in 28-pin devices · Changes "sample clock" to "sample trigger" in AD1CON1 (Register 23-1) · Clarifies footnotes on op amp usage in Registers 23-5 and 23-6
· Adds Note text to indicate that Comparator 3 is unavailable in 28-pin devices · Splits Figure 25-1 into two figures for clearer presentation (Figure 25-1 for Op amp/
Comparators 1 through 3, Figure 25-2 for Comparator 4). Subsequent figures are renumbered accordingly. · Corrects reference description in xxxxx (now (AVDD+AVSS)/2) · Changes CMSTAT[15] in Register 25-1 to "PSIDL"
· Corrects the addresses of all Configuration bytes for 512 Kbyte devices
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TABLE A-5: MAJOR SECTION UPDATES (CONTINUED)
Section Name Section 30.0 "Electrical Characteristics"
Section 32.0 "DC and AC Device Characteristics Graphs" Section 33.0 "Packaging Information"
Update Description
· Throughout: qualifies all footnotes relating to the operation of analog modules below VDDMIN (replaces "will have" with "may have")
· Throughout: changes all references of SPI timing parameter symbol "TscP" to "FscP" · Table 30-1: changes VDD range to 3.0V to 3.6V · Table 30-4: removes Parameter DC12 (RAM Retention Voltage) · Table 30-7: updates Maximum values at 10 and 20 MIPS · Table 30-8: adds Maximum IPD values, and removes all IWDT entries · Adds new Table 30-9 (Watchdog Timer Delta Current) with consolidated values
removed from Table 30-8. All subsequent tables are renumbered accordingly. · Table 30-10: adds footnote for all parameters for 1:2 Doze ratio · Table 30-11:
- changes Minimum and Maximum values for D120 and D130 - adds Minimum and Maximum values for D131 - adds Minimum and Maximum values for D150 through D156, and removes
Typical values · Table 30-12:
- reformats table for readability - changes IOL conditions for DO10 · Table 30-14: adds footnote to D135 · Table 30-17: changes Minimum and Maximum values for OS30 · Table 30-19: - splits temperature range and adds new values for F20a - reduces temperature range for F20b to extended temperatures only · Table 30-20: - splits temperature range and adds new values for F21a - reduces temperature range for F20b to extended temperatures only · Table 30-53: - adds Maximum value to CM30 - adds footnote ("Parameter characterized...") to multiple parameters · Table 30-55: adds Minimum and Maximum values for all CTMUI specifications, and removes Typical values · Table 30-57: adds new footnote to AD09 · Table 30-58: - removes all specifications for accuracy with external voltage references - removes Typical values for AD23a and AD24a - replaces Minimum and Maximum values for AD21a, AD22a, AD23a and AD24a
with new values, split by Industrial and Extended temperatures - removes Maximum value of AD30 - removes Minimum values from AD31a and AD32a - adds or changes Typical values for AD30, AD31a, AD32a and AD33a · Table 30-59: - removes all specifications for accuracy with external voltage references - removes Maximum value of AD30 - removes Typical values for AD23b and AD24b - replaces Minimum and Maximum values for AD21b, AD22b, AD23b and AD24b
with new values, split by Industrial and Extended temperatures - removes Minimum and Maximum values from AD31b, AD32b, AD33b and AD34b - adds or changes Typical values for AD30, AD31a, AD32a and AD33a · Table 30-61: Adds footnote to AD51
· Updates Figure 32-6 (Typical IDD @ 3.3V) with individual current vs. processor speed curves for the different program memory sizes
· Replaces drawing C04-149C (64-pin QFN, 7.15 x 7.15 exposed pad) with C04-154A (64-pin QFN, 5.4 x 5.4 exposed pad)
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Revision H (August 2013)
This revision includes minor typographical and formatting changes throughout the text.
Other major changes are referenced by their respective section in Table A-6.
TABLE A-6: MAJOR SECTION UPDATES
Section Name
Update Description
Cover Section
· Adds Peripheral Pin Select (PPS) to allow Digital Function Remapping and Change Notification Interrupts to Input/Output section
· Adds heading information to 64-Pin TQFP
Section 4.0 "Memory Organization"
Section 5.0 "Flash Program Memory" Section 9.0 "Oscillator Configuration"
· Corrects Reset values for ANSELE, TRISF, TRISC, ANSELC and TRISA · Corrects address range from 0x2FFF to 0x7FFF · Corrects DSRPAG and DSWPAG (now 3 hex digits) · Changes Call Stack Frame from [15:1] to PC[15:0] · Word length in Figure 4-20 is changed to 50 words for clarity · Corrects descriptions of NVM registers
· Removes resistor from Figure 9-1 · Adds Fast RC Oscillator with Divide-by-16 (FRCDIV16) row to Table 9-1 · Removes incorrect information from ROI bit in Register 9-2
Section 14.0 "Input Capture"
Section 17.0 "Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)" Section 19.0 "InterIntegrated Circuit (I2C)" Section 22.0 "Charge Time Measurement Unit (CTMU)" Section 23.0 "10-Bit/12-Bit Analog-to-Digital Converter (ADC)" Section 24.0 "Peripheral Trigger Generator (PTG) Module" Section 25.0 "Op Amp/ Comparator Module"
· Changes 31 user-selectable Trigger/Sync interrupts to 19 user-selectable Trigger/ Sync interrupts
· Corrects ICTSEL[12:10] bits (now ICTSEL[2:0]) · Corrects QCAPEN bit description
· Adds note to clarify that 100kbit/sec operation of I2C is not possible at high processor speeds
· Clarifies Figure 22-1 to accurately reflect peripheral behavior
· Correct Figure 23-1 (changes CH123x to CH123Sx)
· Adds footnote to Register 24-1 (In order to operate with CVRSS=1, at least one of the comparator modules must be enabled.
· Adds note to Figure 25-3 (In order to operate with CVRSS=1, at least one of the comparator modules must be enabled)
· Adds footnote to Register 25-2 (COE is not available when OPMODE (CMxCON[10]) = 1)
Section 27.0 "Special Features"
Section 30.0 "Electrical Characteristics"
· Corrects the bit description for FNOSC[2:0]
· Corrects 512K part power-down currents based on test data · Corrects WDT timing limits based on LPRC oscillator tolerance
Section 31.0 "HighTemperature Electrical Characteristics"
· Adds Table 31-5 (DC Characteristics: Idle Current (IIDLE)
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Revision J (June 2020)
This revision includes minor typographical and formatting changes throughout the text.
Other major changes are referenced by their respective section in Table A-7.
TABLE A-7: MAJOR SECTION UPDATES
Section Name
Update Description
Cover Section
· Removes "Planned" from the "Qualification and Class B Support" section. · Adds UQFN package to Table 1 and Table 2. · Adds two 36-pin UQFN pin diagrams. · Changes the RD8 pin to non-5V tolerant. · Adds the "Referenced Sources" section.
Section 2.7 "Oscillator Value
· Corrects the oscillator source frequency.
Conditions on Device Start-up"
Section 3.0 "CPU"
· Changes to Note 1 here and every chapter throughout document.
Section 4.0 "Memory Organization"
· Changes to Figure 4-11 and Figure 4-16. · Changes to Table 4-35.
Section 5.0 "Flash Program Memory"
· Changes to Register 5-1.
Section 7.0 "Interrupt Controller" · Changes to Table 7-1.
Section 9.0 "Oscillator Configuration"
· Changes to Table 9-1.
Section 10.0 "Power-Saving Features"
· Replaces Example 10-1 and adds Example 10-2. · Changes to Section 10.2.1 "Sleep Mode".
Section 11.0 "I/O Ports"
· Changes to Section 11.2 "Configuring Analog and Digital Port Pins".
Section 13.0 "Timer2/3 and Timer4/5"
· Changes to Register 13-1 and Register 13-2.
Section 14.0 "Input Capture" · Changes to Register 14-2.
Section 16.0 "High-Speed PWM · Changes to Note in Section 16.0 "High-Speed PWM Module
Module (dsPIC33EPXXXMC20X/ (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)".
50X and PIC24EPXXXMC20X · Changes to Register 16-7 and Register 16-13. Devices Only)"
Section 23.0 "10-Bit/12-Bit Analog-to-Digital Converter (ADC)"
· Changes to Register 23-8.
Section 25.0 "Op Amp/ Comparator Module"
· Changes to Figure 25-1. · Changes to Section 25.1 "Op Amp Application Considerations". · Changes to Register 25-2 and Register 25-7.
Section 27.0 "Special Features" · Changes to Table 27-2.
Section 30.0 "Electrical Characteristics"
· Changes to Table 30-3, Table 30-6, Table 30-11, Table 30-14 and Table 30-53.
Section 31.0 "HighTemperature Electrical Characteristics"
· Changes to Table 31-2. · Adds Table 31-9, Table 31-10 and Table 31-13.
Section 32.0 "DC and AC Device · Replaces Figure 32-10. Characteristics Graphs"
Section 33.0 "Packaging Information"
· Adds package marking diagram in Section 33.1 "Package Marking Information". · Adds packaging diagrams to Section 33.2 "Package Details".
"Product Identification System" · Adds M5 packaging description.
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NOTES:
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INDEX
A
Absolute Maximum Ratings .............................................. 407 AC Characteristics .................................................... 419, 477
10-Bit ADC Conversion Requirements ..................... 471 12-Bit ADC Conversion Requirements ..................... 469 ADC Module.............................................................. 465 ADC Module (10-Bit Mode)............................... 467, 479 ADC Module (12-Bit Mode)............................... 466, 479 Capacitive Loading Requirements on
Output Pins ....................................................... 419 DMA Module Requirements...................................... 471 ECANx I/O Requirements ......................................... 460 External Clock........................................................... 420 High-Speed PWMx Requirements ............................ 428 I/O Timing Requirements .......................................... 422 I2Cx Bus Data Requirements (Master Mode) ........... 457 I2Cx Bus Data Requirements (Slave Mode) ............. 459 Input Capture x Requirements .................................. 426 Internal FRC Accuracy...................................... 421, 478 Internal LPRC Accuracy............................................ 421 Internal RC Accuracy ................................................ 478 Load Conditions ................................................ 419, 477 OCx/PWMx Mode Requirements.............................. 427 Op Amp/Comparator Voltage Reference Settling
Time Specifications........................................... 463 Output Compare x Requirements ............................. 427 PLL Clock.......................................................... 421, 477 QEI External Clock Requirements ............................ 429 QEI Index Pulse Requirements................................. 431 Quadrature Decoder Requirements.......................... 430 Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer Requirements ......................... 423 SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x,
SMP = 1) Requirements ................................... 447 SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x,
SMP = 1) Requirements ................................... 446 SPI1 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 445 SPI1 Maximum Data/Clock Rate Summary .............. 444 SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements .................... 455 SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements .................... 453 SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements .................... 449 SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements .................... 451 SPI2 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements .................... 435 SPI2 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements .................... 434 SPI2 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 433 SPI2 Maximum Data/Clock Rate Summary .............. 432 SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements .................... 443 SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements .................... 441 SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements .................... 437 SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements .................... 439 Timer1 External Clock Requirements ....................... 424
2011-2020 Microchip Technology Inc.
Timer2/Timer4 External Clock Requirements........... 425 Timer3/Timer5 External Clock Requirements........... 425 UARTx I/O Requirements......................................... 460 ADC Control Registers...................................................... 327 Helpful Tips............................................................... 326 Key Features ............................................................ 323 Resources ................................................................ 326 Arithmetic Logic Unit (ALU) ................................................ 46
B
Bit-Reversed Addressing .................................................. 117 Example.................................................................... 117 Implementation ......................................................... 117 Sequence Table (16-Entry) ...................................... 118
Block Diagrams Data Access from Program Space Address Generation................................................ 119
16-Bit Timer1 Module ............................................... 205 ADC Conversion Clock Period ................................. 325 ADC with Connection Options for ANx Pins
and Op Amps ................................................... 324 Arbiter Architecture................................................... 112 BEMF Voltage Measurement Using ADC................... 36 Boost Converter Implementation ................................ 34
CALL Stack Frame .................................................. 113
Comparator (Module 4) ............................................ 358 Connections for On-Chip Voltage Regulator ............ 392 CPU Core ................................................................... 38 CRC Module ............................................................. 375 CRC Shift Engine ..................................................... 376 CTMU Module .......................................................... 318 Digital Filter Interconnect .......................................... 359 DMA Controller ......................................................... 143 DMA Controller Module ............................................ 141 dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X ............................ 27 ECAN Module........................................................... 290 EDS Read Address Generation................................ 107 EDS Write Address Generation................................ 108 Example of MCLR Pin Connections ........................... 32 High-Speed PWMx Architectural Overview .............. 229 High-Speed PWMx Register Interconnection ........... 230 I2Cx Module ............................................................. 276 Input Capture x ......................................................... 215 Interleaved PFC.......................................................... 36 Multiphase Synchronous Buck Converter .................. 35 Multiplexing Remappable Output for RPn ................ 182 Op Amp Configuration A........................................... 360 Op Amp Configuration B........................................... 362 Op Amp/Comparator Voltage Reference Module..... 358 Op Amp/Comparator x (Modules 1, 2, 3).................. 357 Oscillator System...................................................... 155 Output Compare x Module ....................................... 221 PLL Module .............................................................. 156 Programmer's Model .................................................. 40 PTG Module ............................................................. 340 Quadrature Encoder Interface .................................. 252 Recommended Minimum Connection ........................ 32 Remappable Input for U1RX .................................... 178 Reset System ........................................................... 125 Shared Port Structure............................................... 175 Single-Phase Synchronous Buck Converter .............. 35 SPIx Module ............................................................. 268
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Suggested Oscillator Circuit Placement...................... 33 Type B Timer (Timer2 and Timer4)........................... 210 Type B/Type C Timer Pair (32-Bit Timer).................. 211 Type C Timer (Timer3 and Timer5) .......................... 210 UARTx Module.......................................................... 283 User-Programmable Blanking Function .................... 359 Watchdog Timer (WDT) ............................................ 393 Brown-out Reset (BOR) .................................................... 392
C
Charge Time Measurement Unit. See CTMU. Code Examples
IC1 Connection to QEI1 Input on Pin 43 of dsPIC33EPXXXMC206................................. 178
Port Write/Read ........................................................ 176 PWMx Write-Protected Register
Unlock Sequence.............................................. 228
PWRSAV Instruction Syntax ...................................... 165 Sleep Mode PWRSAV Instruction Syntax.................. 166
Code Protection ........................................................ 381, 394 CodeGuard Security.................................................. 381, 394 Configuration Bits.............................................................. 381
Description ................................................................ 383 Configuration Byte Register Map ...................................... 382 Configuring Analog and Digital Port Pins .......................... 176 CPU
Addressing Modes ...................................................... 37 Clocking System Options .......................................... 156
Fast RC (FRC) Oscillator .................................. 156 FRC Oscillator with PLL.................................... 156 FRC Oscillator with Postscaler ......................... 156 Low-Power RC (LPRC) Oscillator..................... 156 Primary (XT, HS, EC) Oscillator........................ 156 Primary Oscillator with PLL............................... 156 Control Registers ........................................................ 42 Data Space Addressing .............................................. 37 Instruction Set ............................................................. 37 Resources ................................................................... 41 CTMU Control Registers ...................................................... 319 Resources ................................................................. 318 Customer Change Notification Service ............................. 540 Customer Notification Service........................................... 540 Customer Support ............................................................. 540
D
Data Address Space ........................................................... 53 Memory Map for dsPIC33EP128MC20X/50X, dsPIC33EP128GP50X Devices .......................... 56 Memory Map for dsPIC33EP256MC20X/50X, dsPIC33EP256GP50X Devices .......................... 57 Memory Map for dsPIC33EP32MC20X/50X, dsPIC33EP32GP50X Devices ............................ 54 Memory Map for dsPIC33EP512MC20X/50X, dsPIC33EP512GP50X Devices .......................... 58 Memory Map for dsPIC33EP64MC20X/50X, dsPIC33EP64GP50X Devices ............................ 55 Memory Map for PIC24EP128GP/MC20X/50X Devices ............................................................... 61 Memory Map for PIC24EP256GP/MC20X/50X Devices ............................................................... 62 Memory Map for PIC24EP32GP/MC20X/50X Devices ............................................................... 59 Memory Map for PIC24EP512GP/MC20X/50X Devices ............................................................... 63
Memory Map for PIC24EP64GP/MC20X/50X Devices............................................................... 60
Near Data Space ........................................................ 53 Organization, Alignment ............................................. 53 SFR Space ................................................................. 53 Width .......................................................................... 53 Data Memory Arbitration and Bus Master Priority ........................... 112 Data Space Extended X ............................................................... 111 Paged Memory Scheme ........................................... 107 DC and AC Characteristics Graphs ...................................................................... 481 DC Characteristics BOR .......................................................................... 417 CTMU Current Source Requirements....................... 464 Doze Current (IDOZE) ........................................ 413, 475 High Temperature..................................................... 474 I/O Pin Input Specifications....................................... 414 I/O Pin Output Specifications............................ 417, 476 Idle Current (IIDLE) ............................................ 411, 475 Op Amp/Comparator Requirements ................. 461, 478 Op Amp/Comparator Voltage Reference
Requirements ................................................... 463 Operating Current (IDD) .................................... 410, 475 Operating MIPS vs. Voltage ............................. 408, 474 Power-Down Current (IPD)................................ 412, 475 Program Memory .............................................. 418, 476 Temperature and Voltage ......................................... 474 Temperature and Voltage Specifications.................. 409 Thermal Operating Conditions.................................. 474 Watchdog Timer Delta Current ................................. 413 Development Support ....................................................... 405 Device Overview................................................................. 27 DMA Controller Channel to Peripheral Associations.......................... 142 Control Registers ...................................................... 143
DMAxCNT ........................................................ 143 DMAxCON........................................................ 143 DMAxPAD ........................................................ 143 DMAxREQ ........................................................ 143 DMAxSTA ......................................................... 143 DMAxSTB ......................................................... 143 Resources ................................................................ 143 Supported Peripherals .............................................. 141 Doze Mode ....................................................................... 167 DSP Engine ........................................................................ 46
E
ECAN Module Control Registers ...................................................... 292 Message Buffers Word 0 .............................................................. 312 Word 1 .............................................................. 312 Word 2 .............................................................. 313 Word 3 .............................................................. 313 Word 4 .............................................................. 314 Word 5 .............................................................. 314 Word 6 .............................................................. 315 Word 7 .............................................................. 315 Modes of Operation .................................................. 291 Overview................................................................... 289 Resources ................................................................ 291
Electrical Characteristics .................................................. 407 AC..................................................................... 419, 477
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Enhanced CAN (ECAN) Module ....................................... 289 Equations
Device Operating Frequency .................................... 156 FPLLO Calculation...................................................... 156 FVCO Calculation....................................................... 156 Errata .................................................................................. 25
F
Filter Capacitor (CEFC) Specifications............................... 409 Flash Program Memory .................................................... 121
Control Registers ...................................................... 122 Programming Operations.......................................... 122 Resources................................................................. 122 RTSP Operation........................................................ 122 Table Instructions...................................................... 121 Flexible Configuration ....................................................... 381
G
Guidelines for Getting Started............................................. 31 Application Examples.................................................. 34 Basic Connection Requirements................................. 31 CPU Logic Filter Capacitor Connection (VCAP) .......... 32 Decoupling Capacitors................................................ 31 External Oscillator Pins............................................... 33 ICSP Pins.................................................................... 33 Master Clear (MCLR) Pin............................................ 32 Oscillator Value Conditions on Start-up ...................... 34 Unused I/Os ................................................................ 34
H
High-Speed PWM ............................................................. 227 Control Registers ...................................................... 232 Faults ........................................................................ 227 Resources................................................................. 231
High-Temperature Electrical Characteristics..................... 473 Absolute Maximum Ratings ...................................... 473
I
I/O Ports ............................................................................ 175 Helpful Tips ............................................................... 183 Parallel I/O (PIO)....................................................... 175 Resources................................................................. 184 Write/Read Timing .................................................... 176
In-Circuit Debugger ........................................................... 394 In-Circuit Emulation........................................................... 381 In-Circuit Serial Programming (ICSP) ....................... 381, 394 Input Capture .................................................................... 215
Control Registers ...................................................... 217 Resources................................................................. 216 Input Change Notification (ICN) ........................................ 176 Instruction Addressing Modes........................................... 114 File Register Instructions .......................................... 114 Fundamental Modes Supported................................ 114 MAC Instructions....................................................... 115 MCU Instructions ...................................................... 114 Move and Accumulator Instructions.......................... 115 Other Instructions...................................................... 115 Instruction Set Overview ................................................................... 398 Summary................................................................... 395 Symbols Used in Opcode Descriptions..................... 396 Inter-Integrated Circuit (I2C).............................................. 275 Control Registers ...................................................... 278 Resources................................................................. 277
Internal RC Oscillator Use with WDT........................................................... 393
Internet Address ............................................................... 540 Interrupt Controller
Control and Status Registers.................................... 133 INTCON1.......................................................... 133 INTCON2.......................................................... 133 INTCON3.......................................................... 133 INTCON4.......................................................... 133 INTTREG.......................................................... 133
Interrupt Vector Details............................................. 131 Interrupt Vector Table (IVT)...................................... 129 Reset Sequence ....................................................... 129 Resources ................................................................ 133
J
JTAG Boundary Scan Interface ........................................ 381 JTAG Interface ................................................................. 394
M
Memory Maps Extended Data Space............................................... 111
Memory Organization ......................................................... 47 Resources .................................................................. 64
Microchip Internet Web Site.............................................. 540 Modulo Addressing ........................................................... 116
Operation Example................................................... 116 Start and End Address ............................................. 116 W Address Register Selection.................................. 116
O
Op Amp Application Considerations ....................................... 360 Configuration A................................................. 360 Configuration B................................................. 361
Op Amp/Comparator......................................................... 357 Control Registers...................................................... 363 Resources ................................................................ 362
Open-Drain Configuration................................................. 176 Oscillator
Control Registers...................................................... 158 Resources ................................................................ 157 Output Compare ............................................................... 221 Control Registers...................................................... 223 Resources ................................................................ 222
P
Packaging ......................................................................... 485 Marking............................................................. 485, 487
Peripheral Module Disable (PMD) .................................... 167 Peripheral Pin Select (PPS).............................................. 177
Available Peripherals................................................ 177 Available Pins ........................................................... 177 Control ...................................................................... 177 Control Registers...................................................... 185 Input Mapping........................................................... 178 Output Selection for Remappable Pins .................... 182 Pin Selection for Selectable Input Sources .............. 180 Selectable Input Sources.......................................... 179 Peripheral Trigger Generator (PTG) Module .................... 339 Pinout I/O Descriptions (table)............................................ 28
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Power-Saving Features..................................................... 165 Clock Frequency ....................................................... 165 Clock Switching......................................................... 165 Instruction-Based Modes .......................................... 165 Idle .................................................................... 167 Interrupts Coincident with Power Save Instructions ............................................... 167 Sleep................................................................. 166 Resources ................................................................. 168
Program Address Space ..................................................... 47 Construction .............................................................. 119 Data Access from Program Memory Using Table Instructions.............................................. 120 Memory Map (dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X, PIC24EP128GP/MC20X Devices) ...................... 49 Memory Map (dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X, PIC24EP256GP/MC20X Devices) ...................... 50 Memory Map (dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X, PIC24EP32GP/MC20X Devices) ........................ 47 Memory Map (dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X, PIC24EP512GP/MC20X Devices) ...................... 51 Memory Map (dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X, PIC24EP64GP/MC20X Devices) ........................ 48 Table Read High Instructions (TBLRDH) ................... 120 Table Read Low Instructions (TBLRDL) .................... 120
Program Memory Organization................................................................ 52 Reset Vector ............................................................... 52
Programmable CRC Generator......................................... 375 Control Registers ...................................................... 377 Overview ................................................................... 376 Resources ................................................................. 376
Programmer's Model........................................................... 39 Register Descriptions .................................................. 39
PTG Control Registers ...................................................... 342 Introduction ............................................................... 339 Output Descriptions .................................................. 355 Resources ................................................................. 341 Step Commands and Format .................................... 352
Q
QEI Control Registers ...................................................... 254 Resources ................................................................. 253
Quadrature Encoder Interface (QEI) ................................. 251
R
Referenced Sources ........................................................... 26 Register Maps
ADC1 .......................................................................... 86 CPU Core (dsPIC33EPXXXMC20X/50X,
dsPIC33EPXXXGP50X Devices)........................ 65 CPU Core (PIC24EPXXXGP/MC20X Devices) .......... 67 CRC ............................................................................ 90 CTMU.......................................................................... 99 DMAC ....................................................................... 100 ECAN1 (When WIN (C1CTRL1) = 0 or 1) for
dsPIC33EPXXXMC/GP50X Devices .................. 87 ECAN1 (When WIN (C1CTRL1) = 0) for
dsPIC33EPXXXMC/GP50X Devices .................. 87
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ECAN1 (WIN (C1CTRL1) = 1) for dsPIC33EPXXXMC/GP50X Devices.................. 88
I2C1 and I2C2 ............................................................ 84 Input Capture 1 through Input Capture 4 .................... 78 Interrupt Controller
(dsPIC33EPXXXGP50X Devices) ...................... 71 Interrupt Controller
(dsPIC33EPXXXMC20X Devices)...................... 73 Interrupt Controller
(dsPIC33EPXXXMC50X Devices)...................... 75 Interrupt Controller
(PIC24EPXXXGP20X Devices).......................... 68 Interrupt Controller
(PIC24EPXXXMC20X Devices) ......................... 69 JTAG Interface ........................................................... 99 NVM............................................................................ 95 Op Amp/Comparator................................................... 99 Output Compare 1 through Output Compare 4 .......... 79 PMD (dsPIC33EPXXXGP50X Devices) ..................... 97 PMD (dsPIC33EPXXXMC20X Devices)..................... 98 PMD (dsPIC33EPXXXMC50X Devices)..................... 97 PMD (PIC24EPXXXGP20X Devices) ......................... 96 PMD (PIC24EPXXXMC20X Devices)......................... 96 PORTA (PIC24EPXXXGP/MC202,
dsPIC33EPXXXGP/MC202/502 Devices) ........ 106 PORTA (PIC24EPXXXGP/MC203,
dsPIC33EPXXXGP/MC203/503 Devices) ........ 105 PORTA (PIC24EPXXXGP/MC204,
dsPIC33EPXXXGP/MC204/504 Devices) ........ 104 PORTA (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) ........ 101 PORTB (PIC24EPXXXGP/MC202,
dsPIC33EPXXXGP/MC202/502 Devices) ........ 106 PORTB (PIC24EPXXXGP/MC203,
dsPIC33EPXXXGP/MC203/503 Devices) ........ 105 PORTB (PIC24EPXXXGP/MC204,
dsPIC33EPXXXGP/MC204/504 Devices) ........ 104 PORTB (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) ........ 101 PORTC (PIC23EPXXXGP/MC203,
dsPIC33EPXXXGP/MC203/503 Devices) ........ 105 PORTC (PIC24EPXXXGP/MC204,
dsPIC33EPXXXGP/MC204/504 Devices) ........ 104 PORTC (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) ........ 101 PORTD (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) ........ 102 PORTE (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) ........ 102 PORTF (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) ........ 102 PORTG (PIC24EPXXXGP/MC206 and
dsPIC33EPXXXGP/MC206/506 Devices) ........ 103 PPS Input (dsPIC33EPXXXGP50X Devices) ............. 93 PPS Input (dsPIC33EPXXXMC20X Devices)............. 94 PPS Input (dsPIC33EPXXXMC50X Devices)............. 93 PPS Input (PIC24EPXXXGP20X Devices)................. 92 PPS Input (PIC24EPXXXMC20X Devices) ................ 92 PPS Output (dsPIC33EPXXXGP/MC202/502,
PIC24EPXXXGP/MC202 Devices)..................... 90 PPS Output (dsPIC33EPXXXGP/MC203/503,
PIC24EPXXXGP/MC203 Devices)..................... 90 PPS Output (dsPIC33EPXXXGP/MC204/504,
PIC24EPXXXGP/MC204 Devices)..................... 91
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
PPS Output (dsPIC33EPXXXGP/MC206/506, PIC24EPXXGP/MC206 Devices) ....................... 91
PTG............................................................................. 80 PWM (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices) ........................... 81 PWM Generator 1 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices) ........................... 81 PWM Generator 2 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices) ........................... 82 PWM Generator 3 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices) ........................... 82 QEI1 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices) ........................... 83 Reference Clock ......................................................... 95 SPI1 and SPI2 ............................................................ 85 System Control ........................................................... 95 Timer1 through Timer5 ............................................... 77 UART1 and UART2 .................................................... 84 Registers AD1CHS0 (ADC1 Input Channel 0 Select) ............... 335 AD1CHS123 (ADC1 Input
Channels 1, 2, 3 Select) ................................... 333 AD1CON1 (ADC1 Control 1) .................................... 327 AD1CON2 (ADC1 Control 2) .................................... 329 AD1CON3 (ADC1 Control 3) .................................... 331 AD1CON4 (ADC1 Control 4) .................................... 332 AD1CSSH (ADC1 Input Scan Select High) .............. 337 AD1CSSL (ADC1 Input Scan Select Low)................ 338 ALTDTRx (PWMx Alternate Dead-Time) .................. 240 AUXCONx (PWMx Auxiliary Control)........................ 249 CHOP (PWMx Chop Clock Generator)..................... 236 CLKDIV (Clock Divisor)............................................. 160 CM4CON (Comparator 4 Control) ............................ 367 CMSTAT (Op Amp/Comparator Status) ................... 363 CMxCON (Comparator x Control, x = 1,2,3) ............. 365 CMxFLTR (Comparator x Filter Control)................... 373 CMxMSKCON (Comparator x
Mask Gating Control) ........................................ 371 CMxMSKSRC (Comparator x
Mask Source Select Control) ............................ 369 CORCON (Core Control) .................................... 44, 135 CRCCON1 (CRC Control 1) ..................................... 377 CRCCON2 (CRC Control 2) ..................................... 378 CRCXORH (CRC XOR Polynomial High) ................. 379 CRCXORL (CRC XOR Polynomial Low) .................. 379 CTMUCON1 (CTMU Control 1) ................................ 319 CTMUCON2 (CTMU Control 2) ................................ 320 CTMUICON (CTMU Current Control) ....................... 321 CVRCON (Comparator Voltage
Reference Control) ........................................... 374 CxBUFPNT1 (ECANx Filter 0-3
Buffer Pointer 1)................................................ 302 CxBUFPNT2 (ECANx Filter 4-7 Buffer Pointer 2)..... 303 CxBUFPNT3 (ECANx Filter 8-11
Buffer Pointer 3)................................................ 303 CxBUFPNT4 (ECANx Filter 12-15
Buffer Pointer 4)................................................ 304 CxCFG1 (ECANx Baud Rate Configuration 1) ......... 300 CxCFG2 (ECANx Baud Rate Configuration 2) ......... 301 CxCTRL1 (ECANx Control 1) ................................... 292 CxCTRL2 (ECANx Control 2) ................................... 293 CxEC (ECANx Transmit/Receive Error Count)......... 300 CxFCTRL (ECANx FIFO Control) ............................. 295 CxFEN1 (ECANx Acceptance Filter Enable 1) ......... 302 CxFIFO (ECANx FIFO Status).................................. 296
CxFMSKSEL1 (ECANx Filter 7-0 Mask Selection 1) ............................................. 306
CxFMSKSEL2 (ECANx Filter 15-8 Mask Selection 2) ............................................. 307
CxINTE (ECANx Interrupt Enable) ........................... 299 CxINTF (ECANx Interrupt Flag)................................ 297 CxRXFnEID (ECANx Acceptance Filter n
Extended Identifier) .......................................... 306 CxRXFnSID (ECANx Acceptance Filter n
Standard Identifier) ........................................... 305 CxRXFUL1 (ECANx Receive Buffer Full 1).............. 309 CxRXFUL2 (ECANx Receive Buffer Full 2).............. 309 CxRXMnEID (ECANx Acceptance Filter Mask n
Extended Identifier) .......................................... 308 CxRXMnSID (ECANx Acceptance Filter Mask n
Standard Identifier) ........................................... 308 CxRXOVF1 (ECANx Receive Buffer Overflow 1) ..... 310 CxRXOVF2 (ECANx Receive Buffer Overflow 2) ..... 310 CxTRmnCON (ECANx TX/RX Buffer mn
Control)............................................................. 311 CxVEC (ECANx Interrupt Code)............................... 294 DEVID (Device ID).................................................... 391 DEVREV (Device Revision)...................................... 391 DMALCA (DMA Last Channel Active Status) ........... 152 DMAPPS (DMA Ping-Pong Status) .......................... 153 DMAPWC (DMA Peripheral Write
Collision Status)................................................ 150 DMARQC (DMA Request Collision Status) .............. 151 DMAxCNT (DMA Channel x Transfer Count) ........... 148 DMAxCON (DMA Channel x Control)....................... 144 DMAxPAD (DMA Channel x
Peripheral Address).......................................... 148 DMAxREQ (DMA Channel x IRQ Select) ................. 145 DMAxSTAH (DMA Channel x
Start Address A, High)...................................... 146 DMAxSTAL (DMA Channel x
Start Address A, Low)....................................... 146 DMAxSTBH (DMA Channel x S
tart Address B, High) ........................................ 147 DMAxSTBL (DMA Channel x
Start Address B, Low)....................................... 147 DSADRH (DMA Most Recent RAM
High Address)................................................... 149 DSADRL (DMA Most Recent RAM
Low Address).................................................... 149 DTRx (PWMx Dead-Time)........................................ 240 FCLCONx (PWMx Fault Current-Limit Control)........ 245 FGS Configuration.................................................... 385 FICD Configuration................................................... 386 FOSC Configuration ................................................. 387 FOSCSEL Configuration .......................................... 388 FPOR Configuration ................................................. 389 FWDT Configuration................................................. 390 I2CxCON (I2Cx Control)........................................... 278 I2CxMSK (I2Cx Slave Mode Address Mask)............ 282 I2CxSTAT (I2Cx Status) ........................................... 280 ICxCON1 (Input Capture x Control 1)....................... 217 ICxCON2 (Input Capture x Control 2)....................... 218 INDX1CNTH (Index Counter 1 High Word) .............. 261 INDX1CNTL (Index Counter 1 Low Word) ............... 261 INDX1HLD (Index Counter 1 Hold) .......................... 262 INT1HLDH (Interval 1 Timer Hold High Word) ......... 266 INT1HLDL (Interval 1 Timer Hold Low Word)........... 266 INT1TMRH (Interval 1 Timer High Word) ................. 265 INT1TMRL (Interval 1 Timer Low Word) .................. 265
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INTCON1 (Interrupt Control 1) .................................. 136 INTCON2 (Interrupt Control 2) .................................. 138 INTCON3 (Interrupt Control 3) .................................. 139 INTCON4 (Interrupt Control 4) .................................. 139 INTTREG (Interrupt Control and Status)................... 140 IOCONx (PWMx I/O Control) .................................... 242 LEBCONx (PWMx Leading-Edge
Blanking Control) .............................................. 247 LEBDLYx (PWMx Leading-Edge
Blanking Delay)................................................. 248 MDC (PWMx Master Duty Cycle).............................. 236 NVMADRH (Nonvolatile Memory Address High) ...... 124 NVMADRL (Nonvolatile Memory Address Low)........ 124 NVMCON (Nonvolatile Memory (NVM) Control) ....... 123 NVMKEY (Nonvolatile Memory Key) ........................ 124 OCxCON1 (Output Compare x Control 1) ................ 223 OCxCON2 (Output Compare x Control 2) ................ 225 OSCCON (Oscillator Control) ................................... 158 OSCTUN (FRC Oscillator Tuning) ............................ 163 PDCx (PWMx Generator Duty Cycle) ....................... 239 PHASEx (PWMx Primary Phase-Shift) ..................... 239 PLLFBD (PLL Feedback Divisor) .............................. 162 PMD1 (Peripheral Module Disable Control 1) ........... 169 PMD2 (Peripheral Module Disable Control 2) ........... 171 PMD3 (Peripheral Module Disable Control 3) ........... 172 PMD4 (Peripheral Module Disable Control 4) ........... 172 PMD6 (Peripheral Module Disable Control 6) ........... 173 PMD7 (Peripheral Module Disable Control 7) ........... 174 POS1CNTH (Position Counter 1 High Word) ........... 260 POS1CNTL (Position Counter1 Low Word) .............. 260 POS1HLD (Position Counter 1 Hold) ........................ 260 PTCON (PWMx Time Base Control)......................... 232 PTCON2 (PWMx Primary Master
Clock Divider Select 2)...................................... 234 PTGADJ (PTG Adjust) .............................................. 350 PTGBTE (PTG Broadcast Trigger Enable) ............... 345 PTGC0LIM (PTG Counter 0 Limit) ............................ 348 PTGC1LIM (PTG Counter 1 Limit) ............................ 349 PTGCON (PTG Control) ........................................... 344 PTGCST (PTG Control/Status) ................................. 342 PTGHOLD (PTG Hold) ............................................. 349 PTGL0 (PTG Literal 0) .............................................. 350 PTGQPTR (PTG Step Queue Pointer) ..................... 351 PTGQUEx (PTG Step Queue x) ............................... 351 PTGSDLIM (PTG Step Delay Limit).......................... 348 PTGT0LIM (PTG Timer0 Limit) ................................. 347 PTGT1LIM (PTG Timer1 Limit) ................................. 347 PTPER (PWMx Primary Master
Time Base Period) ............................................ 235 PWMCONx (PWMx Control) ..................................... 237 QEI1CON (QEI1 Control).......................................... 254 QEI1GECH (QEI1 Greater Than or Equal Compare
High Word)........................................................ 264 QEI1GECL (QEI1 Greater Than or Equal Compare
Low Word)......................................................... 264 QEI1ICH (QEI1 Initialization/Capture
High Word)........................................................ 262 QEI1ICL (QEI1 Initialization/Capture
Low Word)......................................................... 262 QEI1IOC (QEI1 I/O Control) ..................................... 256 QEI1LECH (QEI1 Less Than or Equal Compare
High Word)........................................................ 263 QEI1LECL (QEI1 Less Than or Equal Compare
Low Word)......................................................... 263 QEI1STAT (QEI1 Status) .......................................... 258
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RCON (Reset Control).............................................. 127 REFOCON (Reference Oscillator Control) ............... 164 RPINR0 (Peripheral Pin Select Input 0).................... 185 RPINR1 (Peripheral Pin Select Input 1).................... 186 RPINR11 (Peripheral Pin Select Input 11)................ 189 RPINR12 (Peripheral Pin Select Input 12)................ 190 RPINR14 (Peripheral Pin Select Input 14)................ 191 RPINR15 (Peripheral Pin Select Input 15)................ 192 RPINR18 (Peripheral Pin Select Input 18)................ 193 RPINR19 (Peripheral Pin Select Input 19)................ 193 RPINR22 (Peripheral Pin Select Input 22)................ 194 RPINR23 (Peripheral Pin Select Input 23)................ 195 RPINR26 (Peripheral Pin Select Input 26)................ 195 RPINR3 (Peripheral Pin Select Input 3).................... 186 RPINR37 (Peripheral Pin Select Input 37)................ 196 RPINR38 (Peripheral Pin Select Input 38)................ 197 RPINR39 (Peripheral Pin Select Input 39)................ 198 RPINR7 (Peripheral Pin Select Input 7).................... 187 RPINR8 (Peripheral Pin Select Input 8).................... 188 RPOR0 (Peripheral Pin Select Output 0).................. 199 RPOR1 (Peripheral Pin Select Output 1).................. 199 RPOR2 (Peripheral Pin Select Output 2).................. 200 RPOR3 (Peripheral Pin Select Output 3).................. 200 RPOR4 (Peripheral Pin Select Output 4).................. 201 RPOR5 (Peripheral Pin Select Output 5).................. 201 RPOR6 (Peripheral Pin Select Output 6).................. 202 RPOR7 (Peripheral Pin Select Output 7).................. 202 RPOR8 (Peripheral Pin Select Output 8).................. 203 RPOR9 (Peripheral Pin Select Output 9).................. 203 SEVTCMP (PWMx Primary
Special Event Compare)................................... 235 SPIxCON1 (SPIx Control 1)...................................... 272 SPIxCON2 (SPIx Control 2)...................................... 274 SPIxSTAT (SPIx Status and Control) ....................... 270 SR (CPU STATUS)............................................. 42, 134 T1CON (Timer1 Control) .......................................... 207 TRGCONx (PWMx Trigger Control) ......................... 241 TRIGx (PWMx Primary Trigger Compare Value)...... 244 TxCON (Timer2 and Timer4 Control) ....................... 212 TyCON (Timer3 and Timer5 Control) ....................... 213 UxMODE (UARTx Mode).......................................... 285 UxSTA (UARTx Status and Control)......................... 287 VEL1CNT (Velocity Counter 1)................................. 261 Resets............................................................................... 125 Brown-out Reset (BOR)............................................ 125 Configuration Mismatch Reset (CM)......................... 125 Illegal Condition Reset (IOPUWR)............................ 125
Illegal Opcode................................................... 125 Security............................................................. 125 Uninitialized W Register ................................... 125 Master Clear (MCLR) Pin Reset ............................... 125 Power-on Reset (POR)............................................. 125
RESET Instruction (SWR) ........................................ 125
Resources ................................................................ 126 Trap Conflict Reset (TRAPR) ................................... 125 Watchdog Timer Time-out Reset (WDTO) ............... 125 Revision History................................................................ 521
S
Serial Peripheral Interface (SPI) ....................................... 267 Software Stack Pointer (SSP)........................................... 113 Special Features of the CPU ............................................ 381 SPI
Control Registers ...................................................... 270 Helpful Tips............................................................... 269 Resources ................................................................ 269
2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
T
Temperature and Voltage Specifications AC ..................................................................... 419, 477
Thermal Operating Conditions .......................................... 408 Thermal Packaging Characteristics .................................. 408 Timer1 ............................................................................... 205
Control Register ........................................................ 207 Resources................................................................. 206 Timer2/3 and Timer4/5...................................................... 209 Control Registers ...................................................... 212 Resources................................................................. 211 Timing Diagrams 10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) .... 470 10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010) ....................................... 470 12-Bit ADC Conversion (ASAM = 0, SSRC<2:0> = 000, SSRCG = 0)...................................................... 468 BOR and Master Clear Reset ................................... 422 ECANx I/O ................................................................ 460 External Clock........................................................... 420 High-Speed PWMx Fault .......................................... 428 High-Speed PWMx Module....................................... 428 I/O Characteristics .................................................... 422 I2Cx Bus Data (Master Mode) .................................. 456 I2Cx Bus Data (Slave Mode) .................................... 458 I2Cx Bus Start/Stop Bits (Master Mode) ................... 456 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 458 Input Capture x (ICx)................................................. 426 OCx/PWMx ............................................................... 427 Output Compare x (OCx) .......................................... 427 QEA/QEB Input......................................................... 430 QEI Module Index Pulse ........................................... 431 SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) ........................................... 447 SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) ........................................... 446 SPI1 Master Mode (Half-Duplex, Transmit Only, CKE = 0)................................... 444 SPI1 Master Mode (Half-Duplex, Transmit Only, CKE = 1)................................... 445 SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) ........................................... 454
SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) ........................................... 452
SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) ........................................... 448
SPI1 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) ........................................... 450
SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) ........................................... 435
SPI2 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) ........................................... 434
SPI2 Master Mode (Half-Duplex, Transmit Only, CKE = 0) .................................. 432
SPI2 Master Mode (Half-Duplex, Transmit Only, CKE = 1) .................................. 433
SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) ........................................... 442
SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) ........................................... 440
SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) ........................................... 436
SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) ........................................... 438
Timer1-Timer5 External Clock .................................. 424 TimerQ (QEI Module) External Clock ....................... 429 UARTx I/O ................................................................ 460
U
Universal Asynchronous Receiver Transmitter (UART) .................................................. 283 Control Registers...................................................... 285 Helpful Tips............................................................... 284 Resources ................................................................ 284
User ID Words .................................................................. 392
V
Voltage Regulator (On-Chip) ............................................ 392
W
Watchdog Timer (WDT)............................................ 381, 393 Programming Considerations ................................... 393
WWW Address ................................................................. 540 WWW, On-Line Support ..................................................... 25
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2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
THE MICROCHIP WEBSITE
Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:
· Product Support Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software
· General Technical Support Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
· Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.
To register, access the Microchip website at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
· Distributor or Representative · Local Sales Office · Field Application Engineer (FAE) · Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the website at: http://microchip.com/support
2011-2020 Microchip Technology Inc.
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2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 EP 64 MC5 04 T I / PT - XXX
Examples:
Microchip Trademark Architecture Flash Memory Family Program Memory Size (Kbyte) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern
dsPIC33EP64MC504-I/PT: dsPIC33, Enhanced Performance, 64-Kbyte Program Memory, Motor Control, 44-Pin, Industrial Temperature, TQFP package.
Architecture:
33 = 16-bit Digital Signal Controller 24 = 16-bit Microcontroller
Flash Memory Family: EP = Enhanced Performance
Product Group:
GP = General Purpose family MC = Motor Control family
Pin Count:
02 = 28-pin 03 = 36-pin 04 = 44-pin 06 = 64-pin
Temperature Range: I E H
= -40C to +85C (Industrial) = -40C to +125C (Extended) = -40C to +150C (High)
Package:
M5 = Ultra Thin Plastic Quad Flat, No Lead - (36-pin) 5x5 mm body (UQFN) ML = Plastic Quad, No Lead Package - (44-pin) 8x8 mm body (QFN) MM = Plastic Quad, No Lead Package - (28-pin) 6x6 mm body (QFN-S) MR = Plastic Quad, No Lead Package - (64-pin) 9x9 mm body (QFN) MV = Thin Quad, No Lead Package - (48-pin) 6x6 mm body (UQFN) PT = Plastic Thin Quad Flatpack - (44-pin) 10x10 mm body (TQFP) PT = Plastic Thin Quad Flatpack - (64-pin) 10x10 mm body (TQFP) SO = Plastic Small Outline, Wide - (28-pin) 7.50 mm body (SOIC) SP = Skinny Plastic Dual In-Line - (28-pin) 300 mil body (SPDIP) SS = Plastic Shrink Small Outline - (28-pin) 5.30 mm body (SSOP) TL = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA) TL = Very Thin Leadless Array - (44-pin) 6x6 mm body (VTLA)
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NOTES:
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2011-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet.
· Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
· There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
· Microchip is willing to work with the customer who is concerned about the integrity of their code.
· Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
For information regarding Microchip's Quality Management Systems, please visit www.microchip.com/quality.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies.
© 2011-2020, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-6208-8
2011-2020 Microchip Technology Inc.
DS70000657J-page 545
AMERICAS
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China - Shenzhen Tel: 86-755-8864-2200
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China - Wuhan Tel: 86-27-5980-5300
China - Xian Tel: 86-29-8833-7252
China - Xiamen Tel: 86-592-2388138
China - Zhuhai Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444
India - New Delhi Tel: 91-11-4160-8631
India - Pune Tel: 91-20-4121-0141
Japan - Osaka Tel: 81-6-6152-7160
Japan - Tokyo Tel: 81-3-6880- 3770
Korea - Daegu Tel: 82-53-744-4301
Korea - Seoul Tel: 82-2-554-7200
Malaysia - Kuala Lumpur Tel: 60-3-7651-7906
Malaysia - Penang Tel: 60-4-227-8870
Philippines - Manila Tel: 63-2-634-9065
Singapore Tel: 65-6334-8870
Taiwan - Hsin Chu Tel: 886-3-577-8366
Taiwan - Kaohsiung Tel: 886-7-213-7830
Taiwan - Taipei Tel: 886-2-2508-8600
Thailand - Bangkok Tel: 66-2-694-1351
Vietnam - Ho Chi Minh Tel: 84-28-5448-2100
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393
Denmark - Copenhagen Tel: 45-4485-5910 Fax: 45-4485-2829
Finland - Espoo Tel: 358-9-4520-820
France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany - Garching Tel: 49-8931-9700
Germany - Haan Tel: 49-2129-3766400
Germany - Heilbronn Tel: 49-7131-72400
Germany - Karlsruhe Tel: 49-721-625370
Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
Germany - Rosenheim Tel: 49-8031-354-560
Israel - Ra'anana Tel: 972-9-744-7705
Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781
Italy - Padova Tel: 39-049-7625286
Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340
Norway - Trondheim Tel: 47-7288-4388
Poland - Warsaw Tel: 48-22-3325737
Romania - Bucharest Tel: 40-21-407-87-50
Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91
Sweden - Gothenberg Tel: 46-31-704-60-40
Sweden - Stockholm Tel: 46-8-5090-4654
UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820
DS70000657J-page 546
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