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Data Book
*NOVRAM is Xicor's nonvolatile static RAM device family. E2POTTM is a trademark of Xicor, Inc.
lil:ll!
INOVRAM* Data Sheets
Serial Products Data Sheets
E2PROM Data Sheets
I E2POTTM Data Sheets Microcontroller Peripheral Products
Memory Subsystems
Die Products
Application Notes and Briefs
Product and Technology Reliability Reports Ordering Information and Package Drawings
iCIP DATA BOOK �
President's Message
Dear Customer: For Xicor, the company focus is toward achieving the goal of total customer satisfaction. As part of this effort, being the leader of the exciting field of full-featured E2PROM and NOVRAM memories, Xicor has charted a course to provide the most extensive product offering to cover the needs of your company in the field-programmable nonvolatile area. This data book contains data sheets for full-featured E2PROMs, NOVRAMs, and the revolutionary E2POT potentiometers. These products are typically available in a wide variety of speeds, package types and both parallel and serial interface configurations. The majority of the products are offered with extended temperature range, and many comply with all the requirements of Mil-Std-883 Revision C for Class B products. This data book also contains product and process reliability reports and applications notes.
To date, Xicor has shipped close to 100 million E2PROM and NOVRAM memories to its customers. Our research and development activities are substantial and will enable us to continue to introduce innovative products based on the most optimized technology for fullfeatured, nonvolatile, field-programmable products. Our worldwide sales, marketing and applications organizations are dedicated to supporting your requirements. We appreciate your business and look forward to supplying your present and future requirements.
Raphael Klein President October, 1990
Second Edition First Printing
Printed in U.S.A. � XICOR, INC., 1990 "All Rights Reserved"
Fact Sheets contain information on products under development. Xicor reserves the right to change these specifications or modify the product at any time, without notice.
Advanced Data Sheets contain typical product specifications which are subject to change upon device characterization over the full specified temperature range. Xicor reserves the right to change these specifications or modify the product at any time, without notice.
Preliminary Data Sheets contain minimum and maximum limits specified over the full temperature range based upon initial production device characterization. Xicor reserves the right to change these specifications or modify the product at any time, without notice.
Final Data Sheets contain minimum and maximum limits specified over the full temperature range for production devices.
Contact your local Xicor sales representative to obtain the latest specifications prior to order placement.
-
and Xicor is a trademark of Xicor, Inc.
AutostoreTM, E2POTTM and Store-LockTM are trademarks of Xicor, Inc.
NOVRAM is Xicor's nonvolatile static RAM device.
COPSTM is a trademark of National Semiconductor Corp.
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction; redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
iii
Precautions for the Handling of MOS Devices
Xicor products are designed with effective input protection to prevent damage to the devices under most conditions. However, any MOS circuit can be catastrophically damaged by excessive electrostatic discharge or transient voltages. The following procedures are recommended to avoid accidental circuit damage.
I. Testing .MOS Circuits: 1. All units should be handled directly from the conductive or antistatic plastic tube in which they were shipped if possible. This action minimizes touching of individual leads. 2. If units are to be tested without using the tube carrier, the following precautions should be taken: a. Table surfaces which potentially will come in contact with the devices either directly or indirectly (such as through shipping tubes) must be metal or of another conductive material and should be electrically connected to the test equipment and to the test operator (a grounding bracelet is recommended). b. The units should be transported in bundled antistatic tubes or metal trays, both of which will assume a common potential when placed on a conductive table top. c. Do not band tubes together with adhesive tape or rubber bands without first wrapping them in a conductive layer.
II. Test Equipment (Including Environmental Equipment): 1. All equipment must be properly returned to the same reference potential (ground) as the devices, the operator, and the container for the devices. 2. Devices to be tested should be protected from high voltage surges developed by: a. Turning electrical equipment on or off. b. Relay switching. c. Transients from voltage sources (AC line or power supplies).
Ill. Assembling MOS Devices Onto PC Boards: 1. The MOS circuits should be mounted on the PC board last. 2. Similar precautions should be taken as in Item I above, at the assembly work station. 3. Soldering irons or solder baths should be at the same reference (ground) potential as the devices. 4. Plastic materials which are not antistatic treated should be kept away from devices as they develop and maintain high levels of static charge.
IV. Device Handling: 1. Handling of devices should be kept to a minimum. If handling is required, avoid touching the leads directly.
V. General: 1. The handler should take every precaution that the device will see the same reference potential when moved. 2. Anyone handling individual devices should develop a habit of first touching the container in which the units are stored before touching the units. 3. Before placing the units into a PC board, the handler should touch the PC board first. 4. Personnel should not wear clothing which will build up static charge. They should wear smocks and clothing made of 100% cotton rather than wool or synthetic fibers. 5. Be careful of electrostatic build up through the movement of air over plastic material. This is especially true of acid sinks. 6. Personnel or operators should always wear grounded wrist straps when working with MOS devices. 7. A 1 megohm resistance ground strap is recommended and will protect people up to 5,000 volts AC RMS or DC by limiting current to 5 milliamperes. 8. Antistatic ionized air equipment is very effective and useful in preventing electrostatic damage. 9. Low humidity maximizes potential static problems. Maintaining humidity levels above 45% is one of the most effective ways to guard against static handling problems.
iv
Product Index
Device No.
Description
Page No.
NOVRAMs X2201A X2210, X22101 X2210A X2212, X22121 X2212A X22C10, X22C101 X22C11, X22C11 I X2001, X2001 I X2004, X20041
1024x1 NOVRAM .................................. 1-1 64 x 4 NOVRAM .................................... 1-9 64 x 4 NOVRAM .................................... 1-17 256 x 4 NOVRAM ................................... 1-25 256 x 4 NOVRAM ................................... 1-33 CMOS 64 x 4 NOVRAM .............................. 1-41 CMOS 64 x 4 NOVRAM with AutoStore ................ 1-49 12B x B NOVRAM ................................... 1-51 512x B NOVRAM ................................... 1-59
Serial Products NOVRAMs X2444, X24441 X24C44, X24C441 X24C45, X24C451
16 x 16 Serial NOVRAM .............................2-1 16 x 16 CMOS Serial NOVRAM ....................... 2-11 16 x 16 CMOS Serial NOVRAM with AutoStore . . . . . . . . . 2-19
E2PROMs X2402, X24021 X2404, X24041 X24C01, X24C01 I X24C02, X24C021 X24C04, X24C041 X24C16, X24C161
256 x B Serial E2PROM .............................. 2-23 512 x B Serial E2PROM ..............................2-33 12B x B CMOS Serial E2PROM ........................ 2-43 256 x B CMOS Serial E2PROM ........................ 2-53 512 x B CMOS Serial E2PROM ........................ 2-63 2K x B CMOS Serial E2PROM ........................ 2-73
Parallel E2PROM Products
X2B04A, X2804AI
512 x B E2PROM ....................................3-1
X2816B, X2816BI
2K x B E2PROM ....................................3-9
X2B16C, X2816CI
2K x B E2PROM ....................................3-19
X2B64A, X2864AI
8K x B E2PROM ....................................3-29
X2864B, X2864BI
BK x B E2PROM ....................................3-39
X2B64H, X2864HI
BK x B E2PROM ....................................3-47
X28C64, X2BC641
BK x B CMOS E2PROM ..............................3-55
X28256, X282561
32K x B E2PROM ...................................3-69
X28C256, X28C2561
32K x 8 CMOS E2PROM ............................. 3-83
X28C512, X28C5121
64K x B CMOS E2PROM ............................. 3-97
X28C010, X28C0101
12BK x B CMOS E2PROM ............................ 3-111
Digital Potentiometer X9MME, X9MMEI
E2POTTM ..........................................4-1
Microcontroller Peripheral Products
XB8C64, X8BC641
BK x B Multiplexed Address/Data E2PROM ............. 5-1
Memory Subsystems XM28C010, XM28C0101 XM28C020, XM28C0201
12BK x B E2PROM Module ...........................6-1 256K x B E2PROM Module ........................... 6-15
v
Table of Contents
Section 1-NOVRAM Data Sheets
(See Product Index for sequence) ............................................ v
Section 2-Serial Products Data Sheets
(SeeProductlndexforsequence) ............................................ v
Section 3-E2PROM Data Sheets
(See Product Index for sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Section 4-E2POTTM Digitally Controlled Potentiometer Data Sheets
(See Product Index for sequence) ............................................ v
Section 5-Microcontroller Peripheral Products
(SeeProductlndexforsequence) ............................................ v
Section 6-Memory Subsystems
(See Product Index for sequence) ............................................ v
Section 7-Die Products ................................................ 7-1
Section 8-Applications
Application Notes
AN-101 Xicor NOVRAMs* Easier Than Ever to Use
8-1
AN-103 Xicor Replaces DIP Switches and Trimmers with NOVRAM* Memories . 8-9
AN-105 The X2444 Serial NOVRAM* Teams Up with the 8051 Microcontroller Family .................................... . 8-17
AN-106 E2POTTM Digitally Controlled Potentiometer Brings Microprocessor Control to Audio Systems-Adds Features ....................... . 8-23
Application Briefs Nonvolatile Data Integrity: Inadvertent Write/Store Elimination ................... 8-33 Replacing DIP Switches with Nonvolatile Technology ........................... 8-37 Using DATA Polling in an Interrupt Driven Environment ......................... 8-41 E2PROM Provides the Solution to Field Alterable Software . . . . . . . . . . . . . . . . . . . . . . 8-45 ''tov''-What is it? .......................................................... 8-49
*NOVRAM is Xicor's nonvolatile static RAM device.
vii
Table of Contents
Section 8-Applications (Continued)
Article Reprints Understand your application in choosing NOVRAM, EEPROM ................... 8-51
EDN, May 12, 1983 Non-volatile memories keep appliances out of the dark . . . . . . . . . . . . . . . . . . . . . . . . . 8-63
Design News, October 1983 Nonvolatile Memory Gives New Life to Old Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-69
Computer Design, October 1, 1984 Save volatile data during power loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-77
EDN, February 21, 1985 Thick Oxide Beats Thin Film in Building Big EEPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . 8-85
Electronics, May 12, 1986 Solid-State Potentiometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-89
Machine Design, May 22, 1986 Bit Maps for Xicor Products ............................................... 8-91
Section 9-Reliability
RR-502A NOVRAM* Reliability Report ...................................... 9-1 RR-504 Endurance of Xicor E2PROMs and NOVRAMs*. . . . . . . . . . . . . . . . . . . . . . 9-23 RR-505 X2816A/X2804A Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 RR-506A Byte-Wide NOVRAM* (X2001 /X2004) Reliability Report . . . . . . . . . . . . . . 9-45 RR-507A X2864A Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59 RR-508 X2404 Reliability Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-73 RR-509 X2816B Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-81 RR-511 X28C64/X28C256 Reliability Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-89 RR-513 X28256 Reliability Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-101 RR-515 Data Retention in Xicor E2PROM Memory Arrays . . . . . . . . . . . . . . . . . . . . 9-109 RR-516 Latch-Up Considerations in Xicor CMOS Processes .................. 9-113 RR-518 X24C01 Reliability Report. ........................................ 9-123 Determining System Reliability from E2PROM Endurance Data . . . . . . . . . . . . . . . . . . 9-131 Radiation-Induced Soft Errors and Floating Gate Memories . . . . . . . . . . . . . . . . . . . . . 9-135 Endurance Model for Textured Poly Floating Gate Memories . . . . . . . . . . . . . . . . . . . . 9-141 The Prediction of Textured Poly Floating Gate Memory Endurance . . . . . . . . . . . . . . . 9-147 Comparison and Trends in Today's Dominant E2 Technologies .................. 9-155 New Ultra-High Density Textured Poly-Si Floating Gate E2PROM Cell ............ 9-161 Reliability Comparison of Flotox and Textured Poly E2PROMs . . . . . . . . . . . . . . . . . . . 9-163
Section 10-General Information
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 Sales Offices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
viii
Memory Overview
Since its founding, Xicor has developed and placed into production a wide range of system-alterable nonvolatile memory devices. These devices, manufactured with Xicor's proprietary state-of-the-art textured triple-poly floating gate process, are available in a variety of architectures (NOVRAM* and E2PROM), interfaces (nibble-wide, byte-wide and serial), densities, and speeds. Xicor's success as an innovator and leader in system-alterable nonvolatile memory is affirmed with an Electronic Product Magazine Product of the Year award in 1980 and again in 1982 for the first 5-volt only NOVRAM and the first 5-volt only full featured E2PROM, respectively.
Lower density E2PROMs and NOVRAMs have been readily available for a number of years and have provided unique niche applications solutions. Serial devices have replaced DIP switches in a wide range of products that offer user selectable operating parameters. Nibblewide and byte-wide NOVRAMs and E2PROMs are being used in instrumentation and industrial control applications to store calibration data and control information. Communications equipment has implemented these same devices to store phone numbers in repertory dialers and antenna positioning equipment.
The list of first generation applications goes on at length; however, with the second generation represented by the X2864A, the direction of applications began to diverge. The higher density allowed practical usage of E2PROMs in program and mass data storage. The advent of the X28256 has pushed this application usage even higher.
Xicor strives to serve the marketplace by providing next generation devices in existing product areas as evidenced by the X28648 and X2864H high speed 64K E2PROMs. Similarly, the X24C16 and X24C04 maintain compatibility with the original X2404 but offer low power opera-
tion over a much wider Vcc range.
As designers have gained experience implementing the denser E2PROM devices into system memories, they have given Xicor feedback on features they would like. Xicor has listened.
Xicor's response has been active. The issues addressed by the Xicor design team have been: faster read access time, faster write cycle time, denser memory devices and write protection mechanisms.
Xicor has also implemented added features via software control rather than "dedicated pin" hardware control for optional system use. Xicor is committed to providing solutions that neither hinder nor limit the system designer's imagination. The products and features shown in the data sheets in this data book illustrate Xicor's dedication to listening to you, the designer, in providing memory design solutions.
*NOVRAM is Xicor's nonvolatile static RAM device.
ix
X2201A ................................. .
1-1
X2210, X22101. .......................... .
1-9
X2210A ................................. . 1-17
X2212, X22121. .......................... . 1-25
X2212A ................................. . 1-33
X22C10, X22C101 . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
X22C11, X22C11 I . . . . . . . . . . . . . . . . . . . . . . . . . 1-49
X2001, X2001 I............................ 1-51
X2004, X20041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59
J(ic1,
NOVRAM* Data Sheets
lil:I'
1K
Commercial
X2201A
Nonvolatile Static RAM
1024 x 1 Bit
FEATURES � Single SV Supply � Fully TTL Compatible � Infinite E2PROM Array Recall, RAM Read
and Write Cycles � Access Time of 300 ns Max. �Nonvolatile Store Inhibit: Vee= 3V Typical � High Reliability
-Store Cycles: 10,000 -Data Retention: 100 Years
DESCRIPTION
The Xicor X2201 A is a 1024 x 1 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The X2201A is fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V nonvolatile memories.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and from E2PROM to RAM (recall). The store operation is completed in 1O ms or less and the recall is typically completed in 1 �s.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM. The E2PROM array is designed for a minimum 10,000 store cycles and inherent data retention is specified to be greater than 100 years. Refer to RR-520 and RR-515 for details on Xicor nonvolatile memory endurance and data retention characteristics.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM ~~~~iLATILE-:;ljm;md:mm:m�
MEMORY ARRAY
STORE
ARRAY RECALL
0056-1
PIN NAMES
Ao-Ag
D1N
Dour
WE
cs
ARRAY RECALL STORE
Vee Vss
Address Inputs Data Input Data Out Write Enable Chip Select Array Recall Store +5V Ground
Vss 'kc
0056-2
1-1
X2201A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... -10�c to + 85�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current. ................................. 5 mA Lead Temperature
o (Soldering, 1 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is Qot implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
Limits
Min.
Max.
Ice
Power Supply Current
60
lu ILQ V1L(2) V1H(2) Vol VoH
Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1.0 2.0
2.4
10 10 0.8 Vee +1.0 0.4
Units
mA
�A �A
v v v v
Test Conditions
All Inputs = Vee 1110 = 0 mA V1N = GND to Vee VouT = GND to Vee
loL = 4.2 mA loH = -2 mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
1,000
Data Changes Per Bit
Store Cycles
10,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
CAPACITANCE TA = 25�C, f = 1.0 MHz, Vee = 5V
Symbol
Test
C110(1) C1N(1)
Input/Output Capacitance Input Capacitance
Max. 8 6
Notes: (1) This parameter is periodically sampled and not 100% tested. (2) V1L min. and VtH max. are for reference only and are not tested.
Units pF pF
Conditions V110 = OV V1N = OV
1-2
X2201A
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
Inputs
Input Output
cs WE ARRAY RECALL STORE
1/0
H x
H
H Output High Z
Mode Not Selected(3)
L H
H
H Output Data ReadRAM
L L
H
H Input Data High Write "1" RAM
L L
H
x H
L
H x
L
x H
H
H x
H
H Input Data Low Write "O" RAM H Output High Z Array Recall H Output High Z Array Recall L Output High Z Nonvolatile Storing(4) L Output High Z Nonvolatile Storing(4)
A.C. CHARACTERISTICS
TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
tRc tA tco toH tLz(5) tHz(S)
Read Cycle Time
300
Access Time
Chip Select to Output Valid
Output Hold from Address Change
50
Chip Select to Output in Low Z
10
Chip Deselect to Output in High Z
10
Max. 300 200
100
Units ns ns ns ns ns ns
Read Cycle
ADDRESS
l-4-----tA-----.1
DATA OUT
DATA VALID
HIZ 0056-3
Notes: (3) Chip is deselected but may be automatically completing a store cycle.
(4) STORE = L is required only to initiate the store cycle, after which the store cycle will be automatically completed (STORE= X).
(5) tLz min. and tHz min. are periodically sampled and not 100% tested.
1-3
X2201A
Write Cycle Limits Symbol twc tcw tAs twp twR tow toH twz tow
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write
Min. 300 150 50 150 25 100
0 10 10
Max. 100
Units ns ns ns ns ns ns ns ns ns
ADDRESS
DATA IN DATA OUT
0056-4
1-4
X2201A
Early Write Cycle
�----lwp�------1..i
VIE ~--------.....---t-.-.....--..t
~---------~
DATA OUT
HIGH Z
Store Cycle Limits
Symbol
Parameter
Min.
tsTc
Store Time
tsTP
Store Pulse Width
100
tsTz
Store to Output in High Z
tosT
Output Active from End of Store
10
Store Cycle
Max. 10
500
0056-5
Units ms ns ns ns
. - - t S T P ' _ _ _ _,
STORE~---
~----------------4r1------------t.-.-+...---~
- - - - - - DATA OUT
0056-6
1-5
X2201A
Array Recall Cycle Limits
Symbol
Parameter
tRcC tRCP tRCZ toRC tARC
Array Recall Cycle Time Recall Pulse Width(6)
Recall to Output in High Z
Output A~tive from End of R~call Recalled Data .Access Time from End of Recall
Array Recall Cycle
Min. 1200 450
10
Max.
150 750
Units ns ns ns ns ns
1-------------IAcc-------------ti~ ADDRESSES VALID
ARRAY RECALL
_____ DATA OUT
,
HIGHZ
Note: (6) Array Recall rise time must be less than 1 �s.
DATA VALID
0056-7
1-6
X2201A
PIN DESCRIPTIONS AND DEVICE OPERATION Addresses (Ao-Ag) The address inputs select a memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read/ write operations with the RAM array. CS HIGH will place the Dour in the high impedance state.
Write Enable (WE) The Write Enable input controls the Dour buffer, determining whether a RAM read or write operation is enabled. WE HIGH enables a read and WE LOW enables a write.
Data In (D1N) Data is written into the device via the D1N input.
Data Out (DouT) Data from a selected address is output on the Dour output. This pin is in the high impedance state when either CS is HIGH or when WE is LOW.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and ARRAY RECALL inputs are inhibited during the store cycle. The store operation will be completed in 1O ms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM.
ARRAY RECALL The ARRAY RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when ARRAY RECALL is asserted. ARRAY RECALL LOW will also inhibit the STORE input.
WRITE PROTECTION The X2201 A has three write protect features that are employed to protect the contents of the nonvolatile memory.
�Vee Sense-All functions are inhibited when Vee is <S.3V, typically.
�Write Inhibit-Holding either STORE HIGH or ARRAY RECALL LOW during power-up or power-down will prevent an inadvertent store operation and E2PROM data integrity will be maintained. It should be noted; whichever method is employed, all control inputs should be stable and the device deselected prior to release of the controlling protection signal.
� Noise Protection-A STORE pulse of less than 20 ns
(typical) will not initiate a store cycle.
Part Number X2201A
Store Cycles 10,000
Data Changes Per Bit
1,000
SYMBOL TABLE WAVEFORM
JllT
~
xxxxx
~�K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
1-7
X2201A
Normalized Active Supply Current vs. Ambient Temperature
1.4 .-------.---------. Vcc=5.0V
(.) 1.2
.J}
c
La.I
:N::; 1.0
<C(
::I DI::
0z 0.8
0.6 '--------'----------'
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0056-8
Normalized Access Time vs. Ambient Temperature
...~..
e
:N::;
<C(
::I DI::
0 z
0.6 .____ _ __.___ _ _ _ _____,
-55
+25
+125
AMBIENT TEMPERATURE (0 c)
0056-9
1-8
.,,
256 Bit
Commercial Industrial
X2210 X2210I
Nonvolatile Static RAM
64 x 4 Bit
FEATURES � Single 5V Supply � Fully TTL Compatible � Infinite E2PROM Array Recall, RAM Read
and Write Cycles � Access Time of 300 ns Max. �Nonvolatile Store Inhibit: Vee= 3V Typical �High Reliability
-Store Cycles: 100,000 -Data Retention: 100 Years � JEDEC Standard 18-Pin Package
DESCRIPTION The Xicor X2210 is a 64 x 4 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The X221 O is fabricated with the same reliable N-channel floating gate MOS technology used
PIN CONFIGURATION
NC A. A3 A, A, Ao
cs
Vss STORE
Vee NC As 110. 110. 1102
we
ARRAY RECALL
0045-1
in all Xicor 5V nonvolatile memories. The X221 O features the JEDEC approved pinout for 4-bit-wide memories, compatible with industry standard RAMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and from E2PROM to RAM (recall). The store operation is completed in 1O ms or less and the recall is typically completed in 1 �s.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM. The E2PROM array is designed for a minimum 100,000 store cycles and inherent data retention is specified to be greater than 100 years. Refer to RR-520 and RR-515 for details on Xicor nonvolatile memory endurance and data retention characteristics.
FUNCTIONAL DIAGRAM
PIN NAMES
Ao-As 1/01-1/04 WE
cs
ARRAY RECALL STORE
Vee Vss NC
Address Inputs Data Inputs/Outputs Write Enable Chip Select Array Recall Store +5V Ground No Connect
0045-2
1-9
X2210, X22101
ABSOLUTE MAXIMUM RATINGS�
Temperature Under �sias x2210 ................................. -1o�c to +es�c x22.101 ......................... : ..... -ss�c to + 1as�c
Storage Temperature .................... -65�C to + 1so�c
Voltage on any Pin with
Respect to Ground �............ �' ...�.�.....--1.0V to +7V
D.C. Output Current .... ; ....... ~ ..................... 5 niA Lead Temperature
(Soldering, 10 Seconds) ........... , ............... 300-C
*COMMENT
Stresses above those listed under. "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional qperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
x2210 TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. x22101 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2210 Limits
Min.
Max.
X22101 Limits
Min.
Max.
Units
Ice
Power Supply Current
50
55
mA
lu ILQ V1L(2) V1H(2) Vol VoH
Input Load Current
10
10
�A
Output Leakage Current
10
10
�A
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1.0
0.8
-1.0
0.8
V�
2.0 Vee +1.0 2.0 Vee +1.o
v
0.4
�0.4
v
2.4
2.4
v
Test Conditions All Inputs= Vee
q 1110 = mA
V1N = GND to Vee VouT = GNDtoVcc
loL = 4.2mA loH = -2mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
10,000
Data Changes Per Bit
Store Cycles
100,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
C110<1> C1N(1)
Input/Output Capacitance Input Capacitance
Max. 8 6
Notes: (1) This parameter is periodically sampled and� not 100% tested. (2) V1L min. andV1H max. are for reference� only and are not tested.
Units pF pF
Conditions V110 = OV V1N = OV
1-10
X2210, X22101
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
Inputs
Input Output
cs WE ARRAY RECALL STORE
1/0
H x
H
H Output High Z
Mode Not Selected(3)
L H
H
H Output Data Read RAM
L L
H
H Input Data High Write "1" RAM
L L
H
x H
L
H x
L
x H
H
H x
H
H Input Data Low Write "O" RAM H Output High Z Array Recall H Output High Z Array Recall L Output High Z Nonvolatile Storing(4) L Output High Z Nonvolatile Storing(4)
A.C. CHARACTERISTICS
X2210 TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X22101 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
Max.
Units
tRc
Read Cycle Time
300
ns
tA
Access Time
300
ns
tco
Chip Select to Output Valid
200
ns
toH
Output Hold from Address Change
50
ns
tLz(5)
Chip Select to Output in Low Z
10
ns
tHz(5)
Chip Deselect to Output in High Z
10
100
ns
Read Cycle
HIZ 0045-3
Notes: (3) Chip is deselected but may be automatically completing a store cycle. (4) STORE = L is required only to initiate the store cycle, after which the store cycle will be automatically completed (STORE= X). (5) tLz min. and tHz min. are periodically sampled and not 100% tested.
1-11
X2210, X22101
Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
twc
Write Cycle Time
300
ns
tcw
Chip Select to End of Write
150
ns
tAs
Address Setup Time
50
ns
twp
Write Pulse Width
150
ns
twR
Write Recovery Time
25
ns
tow
Data Valid to End of Write
100
ns
toH
Data Hold Time
1 X2210
0
ns
r X22101
20
ns
twz
Write Enable to Output in High Z
10
100
ns
tow
Output Active from End of Write
10
ns
Write Cycle
1-12
0045-4
X2210, X22101
Early Write Cycle
1- - - - - - - t w c � - - - - - - . - 1 ...__.AS_.,.
DATA OUT
HIGHZ
Store Cycle Limits
Symbol
Parameter
Min.
tsTC
Store Time
tsTP
Store Pulse Width
100
tsTz
Store to Output in High Z
tosT
Output Active from End of Store
10
Store Cycle
Max. 10
500
0045-5
Units ms ns ns ns
~�srp�--~
STORE-~~,i
~-..,..---""""'ll~-.~lf-""""'ll~-.----+---+.~~-~
DATA 1/0 - - - - + - - ' I
0045-6
1-13
X2210, X22101
Array Recall Cycle Limits
Symbol
Parameter
tRCC
Array Recall Cycle Time
tRCP
Recall Pulse Width(6)
tRcz
Recall to Output in High Z
to RC
Output Active from End of Recall
tARC
Recalled Data Access Time from End of Recall
Array Recall Cycle
Min.
1200 450
10
Max.
150 750
Units ns ns ns ns ns
-----� DATAl/O
___. loRc HIGHZ
Note: (6) Array Recall rise time must be less than 1 �s.
DATA VALID
0045-7
1-14
X2210, X22101
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (Ao-As) The address inputs select a 4-bit memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read/ write operations with the RAM array. CS HIGH will place the 1/0 pins in the high impedance state.
Write Enable (WE) The Write Enable input controls the 1/0 buffers, determining whether a RAM read or write operation is enabled. WE HIGH enables a read and WE LOW enables a write.
Data In/Data Out (1/01-1104) Data is written to or read from the X221 O through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and ARRAY RECALL inputs are inhibited during the store cycle. The store operation will be completed in 1O ms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM.
ARRAY RECALL The ARRAY RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when ARRAY RECALL is asserted. ARRAY RECALL LOW will also inhibit the STORE input.
WRITE PROTECTION The X221 O has three write protect features that are employed to protect the contents of the nonvolatile memory.
�Vee Sense-All functions are inhibited when Vee is s. 3V, typically.
�Write Inhibit-Holding either STORE HIGH or ARRAY RECALL LOW during power-up or power-down will prevent an inadvertent store operation and E2PROM data integrity will be maintained. It should be noted; whichever method is employed, all control inputs should be stable and the device deselected prior to release of the controlling protection signal.
� Noise Protection-A STORE pulse of less than 20 ns
(typical) will not initiate a store cycle.
Part Number
X2210 X22101 X2210/5 X22101/5 X2210/10 X22101/10
Store Cycles 10,000 50,000 100,000
Data Changes Per Bit 1,000
5,000
10,000
SYMBOL TABLE WAVEFORM
_///T
~
xxxxx
~�[
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
1-15
X2210, X22101
Normalized Active Supply Current vs. Ambient Temperature
Normalized Access Time vs. Ambient Temperature
(.) 1.2 .J:>
0.....
N
:< i
1.0
a~ :
0z 0.8
0.6 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0045-8
....~. 1.25
.0....
N
:i
1.00
<
a~ :
0z 0.75
0.50 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0045-9
1-16
liCI'
256 Bit
Commercial
X2210A
Nonvolatile Static RAM
64 x 4 Bit
FEATURES � Single 5V Supply � Fully TTL Compatible � JEDEC Standard 18-Pin Package � Infinite E2PROM Array Recall, RAM Read
and Write Cycles � Access Time of 250 ns Max. �Nonvolatile Store Inhibit: Vee = 3V Typical � 100 Year Data Retention
DESCRIPTION The Xicor X221 OA is a 64 x 4 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The X221 OA is fabricated with the same reliable N-channel floating gate MOS technology used
PIN CONFIGURATION
in all Xicor 5V nonvolatile memories. The X221 OA features the JEDEC approved pinout for 4-bit-wide memories, compatible with industry standard RAMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and from E2PROM to RAM (recall). The store operation is completed in 1O ms or less and the recall is typically completed in 1 �s.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM. The E2PROM array is designed for a minimum 10,000 store cycles. Data retention is specified to be greater than 100 years.
FUNCTIONAL DIAGRAM
NC A. A, Az A, Ao
cs
Vss STORE
Vee NC As 110. 1/0, 1/02 1/01
WE
ARRAY RECALL
0128-1
STORE ----1
RECALL
PIN NAMES
Ao-As 1/01-1/04 WE
cs
ARRAY RECALL STORE
Vee Vss NC
Address Inputs Data Inputs/Outputs Write Enable Chip Select Array Recall Store +5V Ground No Connect
0128-2
1-17
X2210A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... -1 o�c to + 85�C Storage Temperature .................... -65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
O.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1OSeconds) ...........................300-C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS TA= 0�C to +70�C, Vee= +5V �5%, unless otherwise specified.
Symbol
Parameter
Limits
Min.
Max.
lee
Power Supply Current
50
lu
Input Load Current
10
ILQ
Output Leakage Current
10
V1L
Input Low Voltage
-1.0
0.8
V1H
Input High Voltage
2.0
Vee +o.5
Vol
Output Low Voltage
0.4
VoH
Output High Voltage
2.4
Units
mA
�A �A
v v v v
Test Conditions
All Inputs = Vee 1110 = OmA V1N = GND to Vee Vour = GND to Vee
loL = 4.2 mA loH = -2mA
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
C110<1>
Input/Output Capacitance
C1N(1)
Input Capacitance
Max. 8 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
Inputs
Input Output
cs WE ARRAY RECALL STORE
1/0
H x
H
H Output High Z
Mode Not Selected(2)
L H
H
H Output Data Read RAM
L L
H
H Input Data High Write "1" RAM
L L
H
x H
L
H x
L
x H
H
H x
H
H Input Data Low Write "O" RAM
H Output High Z Array Recall
H Output High Z Array Recall
L Output High Z Nonvolatile Storing(3)
L Output High Z Nonvolatile Storing(3)
Notes: (1) This parameter is periodically sampled and not 100% tested.
(2) Chip is deselected but may be automatically completing a store cycle.
(3) STORE = L is required only to initiate the store cycle, after which the store cycle will be automatically completed
(STORE= X).
1-18
X2210A
A.C. CHARACTERISTICS
TA = 0�C to + 70�C, Vcc = + 5V �5% , unless otherwise specified.
Read Cycle Limits Symbol tRc tA
tea
toH tLz tHz
Parameter Read Cycle Time Access Time Chip Select to Output Valid Output Hold from Address Change Chip Select to Output in Low Z Chip Deselect to Output in High Z
Min. 250
50 10 10
Read Cycle
ADDRESS
Max. 250 200
100
Units ns ns ns ns ns ns
DATAl/O
HIZ 0128-3
1-19
X2210A
Write Cycle Limits Symbol twc tcw tAs twp twR tow toH twz tow
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write
Min.
250 150 50 150 25 100
0 10 10
Max.
100
Units ns ns ns ns ns ns ns ns ns
0128-4
Early Write Cycle
� - - - - - - - - l w c - - - - - - - 1 1..1
ADDRESS ----------'l--------------'I""------
DATA OUT
HIGHZ 1-20
0128-5
X2210A
Store Cycle Limits
Symbol
Parameter
Min.
Max.
Units
tsrc
Store Cycle Time
10
ms
tsrP
Store Pulse Width
100
ns
tsrz
Store to Output in High Z
500
ns
tosr
Output Active from End of Store
10
ns
Store Cycle
STORE---.. 1
DATAl/O ----t---�1
0128-6
1-21
X2210A
Array Recall Cycle Limits
Symbol
Parameter
tRcc tRCP
Array Recall Cycle Time Recall Pulse Width(4)
tRcz
Recall to Output in High Z
toRC
Output Active from End of Recall
tARC
Recalled Data Access Time from End of Recall
Array Recall Cycle
Min.
1200
450
10
Max.
150 750
Units ns ns ns ns ns
- - - - - 1 DATAl/O
HIGHZ
Note: (4) Array Recall rise time must be less than 1 �s.
DATA VALID
0128-7
1-22
X2210A
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (Ao-As) The address inputs select a 4-bit memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read/ write operations with the RAM array. CS HIGH will place the 1/0 pins in the high impedance state.
Write Enable (WE) The Write Enable input controls the 1/0 buffers, determining whether a RAM read or write operation is enabled. WE HIGH enables a read and WE LOW enables a write.
Data In/Data Out (1101-1/04) Data is written to or read from the X221 OA through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and ARRAY RECALL inputs are inhibited during the store cycle. The store operation will be completed in 1O ms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM.
ARRAY RECALL The ARRAY RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when ARRAY RECALL is asserted. ARRAY RECALL LOW will also inhibit the STORE input.
WRITE PROTECTION The X221 OA has three write protect features that are employed to protect the contents of the nonvolatile memory.
�Vee Sense-All functions are inhibited when Vee is ::;; 3V, typically.
�Write Inhibit-Holding either STORE HIGH or RECALL LOW during power-up or power-down will prevent an inadvertent store operation and E2PROM data integrity will be maintained.
�Noise Protection-A STORE pulse of less than 20 ns will not initiate a store cycle.
ENDURANCE
The endurance specification of a device is characterized by the predicted first bit failure to occur in the entire memory (device or system) array rather than the average or typical value for the array. Since endurance is limited by the number of electrons trapped in the oxide during data changes, Xicor NOVRAMs are designed to minimize the number of changes an E2PROM bit cell undergoes during store operations. Only those bits in the E2PROM that are different from their corresponding location in the RAM will be "cycled" during a nonvolatile store. This characteristic reduces unnecessary cycling of any of the rest of the bits in the array, thereby increasing the potential endurance of each bit and increasing the potential endurance of the entire array. Reliability data documented in RR-504, the Xicor Reliability Report on Endurance, and additional reports are available from Xicor.
Part Number X2210A
Store Cycles 10,000
Data Changes Per Bit
1,000
1-23
NOTES
1-24
J(ic1,
1K
Commercial Industrial
X2212 X22121
Nonvolatile Static RAM
256 x 4 Bit
FEATURES � Single 5V Supply � Fully TTL Compatible � Infinite E2PROM Array Recall, RAM Read
and Write Cycles � Access Time of 300 ns Max.
�Nonvolatile Store Inhibit: Vee = 3V Typical
� High Reliability -Store Cycles: 100,000 -Data Retention: 100 Years
� JEDEC Standard 18-Pin Package
DESCRIPTION
The Xicor X2212 is a 256 x 4 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The X2212 is fabricated with the same reliable N-channel floating gate MOS technology used
PIN CONFIGURATION
A, A� A, A, A, Ao
cs
Vss STORE
Ike
A� As 110. 1/03 1/0, 1/01
'WE ARRAY
RECALL 0058-1
in all Xicor 5V nonvolatile memories. The X2212 features the JEDEC approved pinout for 4-bit-wide memories, compatible with industry standard RAMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and from E2PROM to RAM (recall). The store operation is completed in 1O ms or less and the recall is typically completed in 1 �s.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM. The E2PROM array is designed for a minimum 100,000 store cycles and inherent data retention is specified to be greater than 100 years. Refer to RR-520 and RR-515 for details on Xicor nonvolatile memory endurance and data retention characteristics.
FUNCTIONAL DIAGRAM
PIN NAMES
Ao-A7
1/01-1/04 WE
cs
ARRAY RECALL
STORE
Vee Vss
NC
Address Inputs Data Inputs/Outputs Write Enable Chip Select Array Recall Store +5V Ground No Connect
0058-2
1-25
X2212, X22121
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias X2212 ................................. -10�c to +85�C x22121 ............................... -65�C to + 135�C
Storage Temperature .................... -65�C to + 150�C Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V D.C. Output Current. .................................5 mA Lead Temperature
(Soldering, 1OSeconds) ........................... 30C�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X2212 TA = 0�C to + 70�C, Vcc = + 5V � 10%, unless otherwise specified. X22121 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2212 Limits
Min.
Max.
X22121 Limits
Min.
Max.
Units
Ice
Power Supply Current
60
70
mA
lu ILO V1L(2) V1H(2) Vol VoH
Input load Current
10
10
�.A
Output Leakage Current
10
10
�.A
Input low Voltage
-1.0
0.8
-1.0
0.8
v
Input High Voltage Output Low Voltage Output High Voltage
2.0 Vee +1.0 2.0 Vee +1.0 v
0.4
0.4
v
2.4
2.4
v
Test Conditions
All Inputs= Vee 1110 = OmA V1N = GND to Vee Vour = GND to Vee
loL = 4.2mA loH = -2mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
10,000
Data Changes Per Bit
Store Cycles
100,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
CAPACITANCE TA= 25�C, f = 1.0MHz, Vee= 5V
Symbol C110<1> C1N(1)
Test Input/Output Capacitance Input Capacitance
Max. 8 6
Notes: (1) This parameter is periodically sampled and not 100% tested. (2) V1L min. and V1H max. are for reference only and are not tested.
Units pF pF
Conditions V110 = OV
V1N = OV
1-26
X2212, X22121
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
Inputs
Input Output
cs WE ARRAY RECALL STORE
1/0
H x
H
H Output High Z
Mode Not Selected(3)
L H
H
H Output Data Read RAM
L L
H
H Input Data High Write "1" RAM
L L
H
x H
L
H x
L
x H
H
H x
H
H Input Data Low Write "O" RAM H Output High Z Array Recall H Output High Z Array Recall L Output High Z Nonvolatile Storing(4) L Output High Z Nonvolatile Storing(4)
A.C. CHARACTERISTICS
X2212 TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X22121 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
Max.
Units
tRc
Read Cycle Time
300
ns
tA
Access Time
300
ns
tco
Chip Select to Output Valid
200
ns
toH
Output Hold from Address Change
50
ns
tLz(5)
Chip Select to Output in Low Z
10
ns
tHz(5)
Chip Deselect to Output in High Z
10
100
ns
Read Cycle
ADDRESS
DATAl/0
HIZ 0058-3
Notes: (3) Chip is deselected but may be automatically completing a store cycle.
(4) STOA~= L is required only to initiate the store cycle, after which the store cycle will be automatically completed (STORE= X).
(5) tLz min. and tHz min. are periodically sampled and not 100% tested.
1-27
X2212, X22121
Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
twc
Write Cycle Time
300
ns
tcw
Chip Select to End of Write
150
ns
tAs
Address Setup Time
50
ns
twp
Write Pulse Width
150
ns
twR
Write Recovery Time
25
ns
tow
Data Valid to End of Write
100
ns
toH
Data Hold Time
X2212
J X22121
0 20
ns ns
twz
Write Enable to Output in High Z
10
100
ns
tow
Output Active from End of Write
10
ns
Write Cycle
ADDRESS
DATA IN DATA OUT
0058-4
1-28
X2212, X22121
Early Write Cycle
�--------lwc-------l~I
ADDRESS ~----------'I
�----twp----~
WE - - - - - - - - - - - - - - - - - - �
�~----------
DATA OUT
HIGHZ
Store Cycle Limits
Symbol
Parameter
Min.
tsrc
Store Time
tsrP
Store Pulse Width
100
tsrz
Store to Output in High Z
tosr
Output Active from End of Store
10
Store Cycle
Max. 10
500
0058-5
Units ms ns ns ns
..--lsTp----I
STORE---~�
...... ......_ 1.--._.~--~...---.
~~---__,
_
_..___.,..,__
_
_ _
DATA 1/0
0058-6
1-29
X2212, X22121
Array Recall Cycle Limits
Symbol
Parameter
tRCC
Array Recall Cycle Time
tRCP
Recall Pulse Width(6)
tRCZ
Recall to Output in High Z
toRC
Output Active from End of Recall
tARC
Recalled Data Access Time from End of Recall
Array Recall Cycle
Min. 1200 450
10
Max.
150 750
Units ns ns ns ns ns
DATAl/0 ----'�
HIGHZ
Note: (6) Array Recall rise time must be less than 1 �s.
DATA VALID
0058-7
1-30
X2212, X22121
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (Ao-A1) The address inputs select a 4-bit memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read/ write operations with the RAM array. CS HIGH will place the 1/0 pins in the high impedance state.
Write Enable (WE) The Write Enable input controls the 1/0 buffers, determining whether a RAM read or write operation is enabled. WE HIGH enables a read and WE LOW enables a write.
Data In/Data Out (1/01-1/04) Data is written to or read from the X2212 through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and ARRAY RECALL inputs are inhibited during the store cycle. The store operation will be completed in 1O ms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM.
ARRAY RECALL The ARRAY RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when ARRAY RECALL is asserted. ARRAY RECALL LOW will also inhibit the STORE input.
WRITE PROTECTION The X2212 has three write protect features that are employed to protect the contents of the nonvolatile memory.
�Vee Sense-All functions are inhibited when Vee is
s: 3V, typically.
� Write Inhibit-Holding either STORE HIGH or ARRAY RECALL LOW during power-up or powerdown will prevent an inadvertent store operation and E2PROM data integrity will be maintained. It should be noted; whichever method is employed, all control inputs should be stable and the device deselected prior to release of the controlling protection signal.
�Noise Protection-A STORE pulse of less than 20 ns (typical) will not initiate a store cycle.
Part Number
X2212 X22121 X2212/5 X22121/5 X2212/10 X22121/10
Store Cycles 10,000 50,000 100,000
Data Changes Per Bit 1,000
5,000
10,000
SYMBOL TABLE WAVEFORM
_///T ~
xxxxx
~~
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
1-31
X2212, X22121
Normalized Active Supply Current vs. Ambient Temperature
(.) 1.3 ...Y
w c
N
:<:i
1.0
:a:::E:
z0 0.7
0.4
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0058.-8
Normalized Access Time vs. Ambient Temperature
1.8 r--------r--------, Vcc=5.0V
...~.. 1.4
c w ~ 1.0 t-------::;~'---------j
<
:a:::E:
0
z
0.6 >-------+---------<
0.2 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0058-9
,1:1,
1K
Commercial
X2212A
Nonvolatile Static RAM
256 x 4 Bit
FEATURES � Single 5V Supply � Fully TTL Compatible � JEDEC Standard 18-Pin Package � Infinite E2PROM Array Recall, RAM Read
and Write Cycles � Access Time of 250 ns Max. �Nonvolatile Store Inhibit: Vee = 3V Typical � 100 Year Data Retention
DESCRIPTION The Xicor X2212A is a 256 x 4 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The X2212A is fabricated with the same reliable N-channel floating gate MOS technology used
PIN CONFIGURATION
in all Xicor 5V nonvolatile memories. The X2212A features the JEDEC approved pinout for 4-bit-wide memories, compatible with industry standard RAMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and from E2PROM to RAM (recall). The store operation is completed in 1O ms or less and the recall is typically completed in 1 �s.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM. The E2PROM array is designed for a minimum 10,000 store cycles. Data retention is specified to be greater than 100 years.
FUNCTIONAL DIAGRAM
A1 A� A, A, A, Ao
cs
Vss STORE
Vee As As 110. 1/03 1/02 1/0,
WE
ARRAY RECALL 0129-1
PIN NAMES
Ao-A7 1/01-1/04 WE
cs
ARRAY RECALL STORE
Vee Vss NC
Address Inputs Data Inputs/Outputs Write Enable Chip Select Array Recall Store
+sv
Ground No Connect
A,
""
A.
S'fORE RECAIT 110, 110. 1/03 110.
cs
WE
ROW SELECT
0129-2
1-33
X2212A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........ ; .......... -10"C to + 85�C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65�C to + 150�C
Voltage on any Pin with
�
Respect to Ground ........................ -1.ov to +7V
D.C. Output Current .................................. 5 mA
Lead Temperature
(Soldering, 1o Seconds) .. ; ; .... ; ... ; .............. 300�C
*COMMENT
Stre$ses above those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a
stress rating only and the functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect device reliability.
�
D.C. OPERATING CHARACTERISTICS
TA = 0�C to + 70�C, Vee = + 5V �5%, unless otherwise specified.
Symbol
Parameter
Limits
Min.
Max.
Ice
Power Supply Current
60
. lu ILQ V1L V1H VoL VoH
Input Load Current
Output Leakage Current
Input Low Voltage
-1.0
Input High Voltage
2.0
Output Low Voltage
Output High Voltage
�:' 2.4
10 10 0.8 Vee +o.5 0.4
Units
mA
�A �A
v v v v
Test Conditions
All Inputs= Vee 1110 = 0 mA V1N = GND to Vee VouT = GND to Vee
loL = 4.2 mA loH = -2mA
CAPACITANCE TA= 25?C, f = 1.0 MHz, Vee= 5V
Symbol
Test
C110(1)
Input/Output Capacitance
CjN(1)
Input Capacitance
Max. 8 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
Inputs
Input Output
cs WE ARRAY RECALL STORE
1/0
H x
H
H Output High Z
Mode Not Selected(2)
L H
H
H Output Data Read RAM
L L
H
H Input Data High Write "1" RAM
L �L
H
x H
L
H x
L
x H
H
H x
H
H Input Data Low Write "O" RAM
H Output High z Array Recall
H Output High Z Array Recall L Output High Z Nonvolatile Storing(3) L Output High Z Nonvolatile Storing(3)
Notes: (1) This parameter is periodically sampled and not 100% tested.
(
(2) Chip is deselected but may be automatically completing a store cycle.
(3) STORE = L is required only to initiate the store cycle, after which the store cycle will be automatically completed
(STORE= X).
1-34
X2212A
A.C. CHARACTERISTICS
TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
tRe
Read Cycle Time
250
tA
Access Time
tea
Chip Select to Output Valid
toH
Output Hold from Address Change
50
tLz
Chip Select to Output in Low Z
10
tHz
Chip Deselect to Output in High Z
10
Read Cycle
�---------1tRc----------t~
Max. 250 200
100
Units ns ns ns ns ns ns
DATAl/O
DATA VALID
HIZ
0129-3
1-35
X2212A
Write Cycle Limits Symbol twc tcw tAs twp twR tow toH twz tow
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write
Min.
250 150 50 150 25 100 0 10 10
Max.
100
Units ns ns ns ns ns ns ns ns ns
ADDRESS
DATA IN DATA OUT
Early Write Cycle
0129-4
DATA OUT
HIGHZ
1-36
0129-5
X2212A
Store Cycle Limits
Symbol
Parameter
Min.
Max.
Units
tsTC
Store Cycle Time
10
ms
tsTP
Store Pulse Width
100
ns
tsTZ
Store to Output in High Z
500
ns
tosr
Output Active from End of Store
10
ns
Store Cycle
.---tSTP_ _.._. ,_.,..____._._._-<1,..._.____.__...__.._....,.______
STORE---~1
DATAl/O ----+--
0129-6
1-37
X2212A
Array Recall Cycle Limits
Symbol
Parameter
tRCC
Array Recall Cycle Time
tRCP
Recall Pulse Width(4)
tRcz
Recall to Output in High Z
toRC
Output Active from End of Recall
tARC
Recalled Data Access Time from End of Recall
Array Recall Cycle
Min. 1200 450
10
Max.
150 750
Units ns ns ns ns ns
------� DATAl/O
_______. toRC
HIGHZ
...... l.r------~11,...------
DATA VALID
0129-7
Note: (4) Array Recall rise time must be less than 1 �s.
1-38
X2212A
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (Ao-A1) The address inputs select a 4-bit memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read/ write operations with the RAM array. CS HIGH will place the 1/0 pins in the high impedance state.
Write Enable (WE) The Write Enable input controls the 1/0 buffers, determining whether a RAM read or write operation is enabled. WE HIGH enables a read and WE LOW enables a write.
Data In/Data Out (1/01-1/04) Data is written to or read from the X2212A through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and ARRAY RECALL inputs are inhibited during the store cycle. The store operation will be completed in 1O ms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM.
ARRAY RECALL The ARRAY RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when ARRAY RECALL is asserted. ARRAY RECALL LOW will also inhibit the STORE input.
WRITE PROTECTION The X2212A has three write protect features that are employed to protect the contents of the nonvolatile memory.
�Vee Sense-All functions are inhibited when Vee is <S.3V, typically.
�Write Inhibit-Holding either STORE HIGH or RECALL LOW during power-up or power-down will prevent an inadvertent store operation and E2PROM data integrity will be maintained.
�Noise Protection-A STORE pulse of less than 20 ns will not initiate a store cycle.
ENDURANCE
The endurance specification of a device is characterized by the predicted first bit failure to occur in the entire memory (device or system) array rather than the average or typical value for the array. Since endurance is limited by the number of electrons trapped in the oxide during data changes, Xicor NOVRAMs are designed to minimize the number of changes an E2PROM bit cell undergoes during store operations. Only those bits in the E2PROM that are different from their corresponding location in the RAM will be "cycled" during a nonvolatile store. This characteristic reduces unnecessary cycling of any of the rest of the bits in the array, thereby increasing the potential endurance of each bit and increasing the potential endurance of the entire array. Reliability data documented in RR-504, the Xicor Reliability Report on Endurance, and additional reports are available from Xicor.
Part Number X2212A
Store Cycles 10,000
Data Changes Per Bit
1,000
1-39
NOTES
1-40
ADVANCED INFORMATION
256 Bit
Commercial Industrial
X22C10 X22C101
Nonvolatile Static RAM
Ji1:1,
64 x 4 Bit
FEATURES � 100% Compatible with X2210
-With Timing Enhancements � Infinite Array Recall, RAM Read and Write
Cycles � High Reliability
-Store Cycles: 1,000,000 -Data Retention: 100 Years � High Performance CMOS -120 ns RAM Access Time -Low Power Consumption
Active: 40 mA Max. Standby: 100 �A Max. �Nonvolatile Store Inhibit: Vee = 3.5V Typ � Fully TTL and CMOS Compatible � JEDEC Standard 18-Pin 300-mil DIP
PIN CONFIGURATION
PLASTIC DIP CERDIP
NC 1
A4 2 A3 3 A2 4 A1 5 Ao 6
cs 7
Vss 8 STORE 9
Vee NC
A5 1/04 1/03 1/02 1/01 WE ARRAY RECALL
0123-1
DESCRIPTION
The X22C1 O is a 64 x 4 NOVRAM featuring a highspeed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (STORE) and from E2PROM to RAM (RECALL). The STORE operation is completed within 1O ms or less and the RECALL is typically completed within 1 �s.
Xicor NOVRAMs are designed for unlimited write operations to the RAM, either RECALLS from E2PROM or writes from the host. The X22C1 O will reliably endure 1,000,000 STORE cycles. Inherent data retention is greater than 100 years. Refer to RR-515, RR-504 and RR-520 for details of data retention and endurance characteristics for Xicor nonvolatile memories.
PIN NAMES
Ao-As 1101-1/04 WE
cs
RECALL STORE
Vee
Vss NC
Address Inputs Data Inputs/Outputs Write Enable Chip Select Array Recall Store +5V Ground No Connect
1-41
X22C10, X22C101
ABSOLUTE MAXIMUM RATINGS*
Tetnperature Under Blas ........... ~ ...... -"- 65�C to + 135�C Storage Temperature .................... -65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) .................... ; ...... 300�C
*COMMENT
Stresses above those listed� under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any ottier conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X22C10 TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X22C101 TA= ...::.40�c to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
Min. Max. Units
Test Conditions
Ice
Vcc Supply Current, RAM
Read/Write
40
mA CS = VIL� I/Os = Open, All Others = V1H.
Addresses = TTL Levels @ f = 5 MHz
lss1
Vcc Standby Current
(TTL Inputs)
2
mA Store or Recall Functions Not Active,
I/Os = Open, All Other Inputs = V1H
lss2
Vcc Standby Current
(CMOS Inputs)
100
�A Store or Recall Functions Not Active,
I/Os= Open, All Other Inputs= Vee -0.3V
lu
Input Leakage Current
10
�A V1N = GND to Vee
ILO V1L(4) V1H(4) Vol VoH
Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
10
�A VouT = GND to Vee
-1.0
0.8
v
v 2.0 Vee +1.0
0.4
v loL = 4.2 mA
2.4
v loH = -2.0 mA
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
c 11o(1)
Input/Output Capacitance
C1N(1)
Input Capacitance
Max. 8 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
cs WE RECALL
H x
H
L H
H
L L
H
L L
H
x H
L
H x
L
x H
H
H x
H
STORE H H H H H H L L
110 Output High Z Output Data Input Data High Input Data Low Output High Z
z Output High
Output High Z Output High Z
Mode Not� Selected(2) Read RAM Write "1" RAM Write "O" RAM Array Recall Array Recall Nonvolatile Storing(3) Nonvolatile Storing(3)
Notes: (1) This parameter is periodically sampled and not 100% tested.
(2) Chip is deselected but may be automatically completing a store cycle.
(3) STORE = LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed (e.g. STORE = X).
(4) V1L min. and V1H max. are for reference only and are not tested.
1-42
X22C10, X22C101
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
Data Changes Per Bit
Store Cycles
1,000,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
POWER-UP TIMING(5) Symbol tpuR tpuw
Parameter Power-Up to Read Operation Power-Up to Write or Store Operation
Max. 100
5
Units �s ms
A.C. CHARACTERISTICS
X22C1 OTA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified. X22C101 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
tRe
Read Cycle Time
150
tAA
Access Time
tea
Chip Select to Output Valid
toH
Output Hold from Address Change
0
tLz
Chip Select to Output in Low Z
0
tHz
Chip Deselect to Output in High Z
Max. 150 150
50
Units ns ns ns ns ns ns
Read Cycle
ADDRESS
DATAl/O
HIZ 0123-2
Note: (5) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
1-43
X22C10, X22C101
Write Cycle Limits Symbol twc tcw tAs twp twR tow toH twz tow
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write
Min. 150 90
0 90 0 40 0 0 0
Max. 50
Units ns ns ns ns ns ns ns ns ns
Early Write Cycle
0123-3
.-----lwp-----i
WE-----~--......-<ri...,........-, 1
�~----------
DATA OUT
HIGHZ 1-44
0123-4
X22C 10, X22C 101
Recall Cycle Limits
Symbol
Parameter
tRcc
Array Recall Time
tRCP tRcz
Recall Pulse Width(6)
Recall to Output in High Z
toRC
Output Active from End of Recall
tARC
Recalled Data Access Time from End of Recall
Min.
90 0
Array Recall Cycle
ADDRESS
xxxxx><Xx
1 4 - - - - - - - tRCC - - - - - . l
Max.
1200
50
150
Units ns ns ns ns ns
DATA 1/0
Store Cycle Limits Symbol tsTC tsTP tsTZ tosT
Store Cycle
Parameter Internal Store Time Store Pulse Width Store to Output in High Z Output Active from End of Store
Min.
90 0
Max.
10
50
0123-5
Units ms ns ns ns
-+---tsrp,--...-i
STORE---~�
. 1~,--..,..--.,...---ir-...,.~[~....,---------+i.-- . .- - - - - - - -
DATAl/O ----+---
Note: (6) RECALL rise time must be less than 1 �s. 1-45
0123-6
X22C10, X22C101
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (Ao-As) The address inputs select a 4-bit memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read or write operations with the RAM array. CS HIGH will place the 1/0 pins in the high impedance state.
Write Enable (WE) The Write Enable input controls the 1/0 buffers, determining whether a RAM read or write operation is enabled. When CS is LOW and WE is HIGH the 1/0 pins will output data from the selected RAM address location. When both CS and WE are LOW, data presented at the 1/0 pins will be written to the selected address location.
Data In/Data Out (1101-1104) Data is written to or read from the X22C1 O through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and RECALL inputs are inhibited during the store cycle. The store operation is completed in 1O ms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted
during a RAM write operation, the write will be immediately terminated and the store performed.. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM arrays.
RECALL The RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when RECALL is asserted. RECALL LOW will also inhibit the STORE input.
AUTOMATIC RECALL Upon power-up the X22C1 O will automatically recall data from the E2PROM array into the RAM array.
WRITE PROTECTION The X22C1 0 has three write protect features that are employed to protect the contents of the nonvolatile memory.
�Vee Sense-All functions are inhibited when Vee is <3.5V.
� Write Inhibit-Holding either STORE HIGH or RECALL LOW during power-up or power-down will prevent an inadvertent store operation and E2PROM data integrity will be maintained.
� Noise Protection-A STORE pulse of less than 20 ns will not initiate a store cycle.
1-46
X22C 10, X22C 101
FUNCTIONAL DIAGRAM
ROW SELECT
- - - - STORE
RECALL
CONTROL LOGIC
INPUT DATA CONTROL
cs we
SYMBOL TABLE WAVEFORM
.....lllT
~
xxxxx
~�[
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
1-47
0123-7
NOTES
1-48
FACT SHEET
256 Bit
Commercial Industrial
X22C11 X22C111
Nonvolatile Static RAM
JiCI'
64 x 4 Bit
FEATURES � AutostoreTM
-Automatically Stores Data Upon Detection of Power Loss
� Store-LockTM -Software Enabled Store Lockout
� 100% Compatible with X2210 and X22C10 -With Timing Enhancements
� Infinite Array Recall, RAM Read and Write Cycles
� High Reliability -Store Cycles: 1,000,000 -Data Retention: 100 Years
� High Performance CMOS -120 ns RAM Access Time -Low Power Consumption Active: 40 mA Max. Standby: 100 �A Max.
� Nonvolatile Store Inhibit: Vcc = 3.5V Typ
� Fully TTL and CMOS Compatible � JEDEC Standard 18-Pin 300-mil DIP
PIN CONFIGURATION
PLASTIC DIP CERDIP
NC
A4 2 A3 3 A2 4
A1 Ao 6
cs 7
Vss 8
STORE 9
Vee
NC As 1/04 1/03 1/02 1/01 WE RECALL
0124-1
DESCRIPTION
The X22C11 is a 64 x 4 NOVRAM featuring a highspeed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (STORE) and from E2PROM to RAM (RECALL). The STORE opera~ tion is completed within 1O ms or less and the RECALL is typically completed within 1 �s.
In addition, the X22C11 features Autostore and StoreLock. Autostore is a user selectable option that will automatically perform a Store operation when power is removed from the X22C11. Store-Lock will lockout all inadvertent store conditions.
Xicor NOVRAMs are designed for unlimited write operations to the RAM; either RECALLS from E2PROM or writes from the host. The X22C11 will reliably endure 1,000,000 STORE cycles. Inherent data retention is greater than 100 years. Refer to RR-515, RR-504 and RR-520 for details of data retention and endurance characteristics for Xicor nonvolatile memories.
PIN NAMES
Ao-A5 1101-1/04 WE
cs
RECALL STORE
Vee Vss NC
Address Inputs Data Inputs/Outputs Write Enable Chip Select Array Recall Store +5V Ground No Connect
1-49
X22C11, X22C111
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (Ao-As) The address inputs select a 4-bit memory location during a read or write operation.
Chip Select (CS) The Chip Select input must be LOW to enable read or write operations with the RAM array. CS HIGH will place the 1/0 pins in the high impedance state.
Write Enable (WE) The Write Enable input controls the 1/0 buffers, determining whether a RAM read or write operation is enabled. When CS is LOW and WE is HIGH, the 1/0 pins will output data from the selected RAM address location. When both CS and WE are LOW, data presented at the 1/0 pins will be written to the selected address location.
Data In/Data Out (1/0rl/04) Data is written to or read from the X22C11 through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CS is HIGH or during either a store or recall operation.
STORE The STORE input, when LOW, will initiate the transfer of the entire contents of the RAM array to the E2PROM array. The WE and RECALL inputs are inhibited during the store cycle. The store operation is completed in 1Oms or less.
A store operation has priority over RAM read/write operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted during a RAM write operation, the write will be immediately terminated and the store performed. The data at the RAM address that was being written will be unknown in both the RAM and E2PROM arrays.
RECALL The RECALL input, when LOW, will initiate the transfer of the entire contents of the E2PROM array to the RAM array. The transfer of data will typically be completed in 1 �s or less.
An array recall has priority over RAM read/write operations and will terminate both operations when RECALL is asserted. RECALL LOW will also inhibit the STORE input.
Automatic Recall Upon power-up the X22C11 will automatically recall data from the E2PROM array into the RAM array.
Store-Lock Store-Lock will lockout all attempts to store data from the RAM array into the E2PROM array unless the Store Enable Latch has been set by the user. This feature can eliminate the need for any external power-up/power-down inadvertent store circuits.
The X22C11 is always in the store lockout mode. In order to enable a store operation the user must first bring RECALL high and STORE low, then write a two byte command sequence to the X22C11 and then bring STORE high. The X22C11 is now ready to store data the next time STORE is strobed low. After each valid store operation, the Store Enable Latch is reset, protecting the data. A power-up condition will reset the latch regardless of its state prior to power-down.
Autostore Autostore will automatically store data from the RAM array into the E2PROM array� after detecting Vcc has fallen below the Autostore threshold. The Autostore Enable Latch is enabled by first bringing RECALL high and STORE low, then writing a two byte command sequence to the X22C11 and then bringing STORE high. At this point the X22C11 is "armed" to perform an autostore operation. The Autostore Enable Latch will be reset upon power-up.
1-50
1K
Commercial Industrial
X2001 X20011
Nonvolatile Static RAM
--=1-: 128 x 8 Bit
FEATURES �Nonvolatile Data Integrity � Automatic Store Timing � Store and Array Recall Combined on One
Line (NE) � Enhanced Store Protection � Infinite E2PROM Array Recall, and RAM
Read and Write Cycles � Single SV Supply � High Reliability
-Store Cycles: 100,000 -Data Retention: 100 Years � Fast Access Time: 200 ns Max. � Automatic Recall on Power-Up � JEDEC Approved Byte-Wide Pinout
DESCRIPTION The Xicor X2001 is a byte-wide NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X2001
is fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories. The X2001 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs, EPROMs and E2PROMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). With NE LOW, these functions are performed in the same manner as RAM read and write op-
erations. The store operation is completed in 1o ms or
less and the recall operation is completed in 5 �s or less.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 100,000 store operations to the E2PROM. Inherent data retention is specified to be greater than 100 years. Refer to RR-520, RR-504 and RR-515 for details on Xicor nonvolatile memory endurance and data retention characteristics.
PIN CONFIGURATION
0051-1
PIN NAMES
Ao-A6 l/Oo-1/07 CE OE WE NE Vee Vss NC
Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Nonvolatile Enable +5V Ground No Connect
FUNCTIONAL DIAGRAM
NONVOLATILE E2PROM MEMORY ARRAY
"3-----0~~~~~.-.
... --rr--t
As--fr=-:-:-1
STORE
ARRAY RECALL
:---r--rrn~""=::::!:""=""""*'l=""=""===f'.'.11---__JI we
UO>------rl-++-f::>--1 I/Cl) ---.++++-f::>--1
110. --.-H+~.---1 110$ -~1+1-1-'"'-"'---'
110. --rl-++++-l+-f:>--1
COLUMN 110 CIRCUITS
1-51
' - - - - - - - ' - - - - - - - - - _ _ J 0051-2
X2001, X20011
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias x2001 ..................
.
....
.
.
....
.
...
-1
o�c
to
+ a5�c
x20011 ............................... - 65�C to + 135�C
Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + ?V
o.e. Output Current .................................. 5 mA
Le(aSdoTldeemrinpge,ra1tourSeeconds) ........................... 300�e
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
= D.C. OPERATING CHARACTERISTICS
X2001 TA 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X2001 I TA = -40�C to + 85�C, Vee = + 5V � 10%, unless otherwise specified.
Symbol
Parameter
X2001 Limits
Min.
Max.
X20011 Limits
Min.
Max.
Units
Test Conditions
Ice
Vee Current (Active)
80
100
mA CE= V1L.
All Other Inputs = Vee
1110 = 0 mA
lss
lu ILo V1L(2) V1H(2) Vol VoH
Vcc Current (Standby)
50
65
mA All Inputs= Vee
1110 = 0 mA
Input Leakage Current
10
10
�,A V1N = GND to Vee
Output Leakage Current
10
10
�,A Vour = GND to Vee
Input Low Voltage
-1.0
0.8
-1.0
0.8
v
Input High Voltage
v 2.0 Vee +0.5 2.0 Vee +1.0
Output Low Voltage
0.4
0.4
v loL = 2.1 mA
Output High Voltage
2.4
2.4
v loH = -400 �A
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
c11o(1)
C1N(1)
Test Input/Output Capacitance Input Capacitance
Max. 10 6
Units
pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION CE WE NE OE
H x x x
L H H L
L L Hx L L Hx
L H L L L L LH L HHH L L LL L H LH
Mode Not Selected Read RAM Write "1" RAM Write "O" RAM Array Recall Nonvolatile Storing Output Disabled Not Allowed No Operation
1/0
Output High Z Output Data Input Data High Input Data Low Output High Z Output High Z Output High Z Output High Z Output High Z
Power Standby Active Active Active Active Active Active Active Active
Notes: (1) This parameter is periodically sampled and not 100% tested. (2) V1L min. and V1H max. are for reference only and are not tested.
1-52
X2001, X20011
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
10,000
Data Changes Per Bit
Store Cycles
100,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 � Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS
X2001 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. x20011 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
tRe teE tAA toE tLz(3) tHz(3) toLz<3> toHz(3) toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change
X2001-20 X20011-20
Min. Max.
200
200
200
70
10
10
100
10
10
100
0
X2001-25 X20011-25
Min. Max.
250
250
250
100
10
10
100
10
10
100
0
X2001 X20011 Min. Max. 300
300 300 150 10 10 100 10 10 100 0
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
ADDRESS
1------IRc------.-.1 .....__tee-.
..._toe__.
DATAl/O --H-IG-H-Z--+---11:
0051-3
Note: (3) tLz min., tHz min., toLz min. and toHz min. are periodically sampled and not 100% tested. tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
1-53
X2001, X20011
Write Cycle Limits
Symbol
Parameter
twc
Write Cycle Time
tcw
Chip Enable to End of Write Input
tAs
Address Setup Time
twp
Write Pulse Width
twR
Write Recovery Time
tow
Data Valid to End of Write
toH
Data Hold Time
twz
Write Enable to Output in High Z
tow
Output Active from End of Write
toz
Output Enable to Output in High Z
WE Controlled Write Cycle
X2001-20 X20011-20
Min. Max.
200
200
0
120
0
120
0
10
100
10
10
100
X2001-25 X20011-25
Min. Max.
250
250
0
150
0
150
0
10
100
10
10
100
X2001 X20011 Min. Max.
300 300 0 200
0 200
0 10 100 10 10 100
Units
ns ns ns ns ns ns ns ns ns ns
CE Controlled Write Cycle
1------lwc�------I ADDRESS - - . . . . - - - - - , - ' l ' - - - - . . . . . - - - - . - - - - - - ' r ' - - - - - - -
Oi v,.
14---lcw____..
0051-4
1-54
X2001, X20011
Store Limits
Symbol
Parameter
tsrc tsp tNHZ to EST tsoE tNs
Store Time Store Pulse Width Nonvolatile Enable to Output in High Z Output Enable from End of Store OE Disable to Store Function NE Setup Time from WE
Store Timing
X2001�20 X20011�20 Min. Max.
10 120
100 10 20 0
X2001�25 X20011-25 Min. Max.
10 150
100 10 20 0
X2001 X20011 Min. Max.
10 200
100 10 20 0
Units
ms ns ns ns ns ns
_________ Vee -------------------1,,V_ee MIN(4)
0051-6
Note: (4) x2001 Vee Min. = 4.75V X2001 I Vee Min. = 4.5V
The Store Pulse Width (tsp) is a minimum time that NE, WE and CE must be LOW simultaneously. To insure data integrity, NE and CE must return HIGH after initiation of and throughout the duration (tsrc. 1O ms) of the Store operation. During tsrc. OE and WE may go LOW providing the host system access to other devices in the system.
1-55
X2001, X20011
Array Recall Cycle Limits
Symbol
Parameter
tRcc
tRCP
-:-
tRWE
Array Recall Time Recall Pulse Width to Initiate Recall WE Setup Time-to NE
Array Recall Cycle
X2001-20 X20011-20 Min. Max.
5.0 120
0
X2001-25 X20011-25 Min. Max.
5.0 150
0
X2001 X20011 Min. Max.
5.0 200
0
Units
�s ns ns
ADDRESS
-----tRcc-----
DATAVo-------------------------------------<~+(~(-(E-+(~(-(H)t-------
0051-7
The Recall Pulse Width (tRcP) is a minimum time that NE, OE. and CE must be LOW simultaneously. To insure data integrity, NE and CE must return HIGH after initiation of and through the duration (tRcc. 5 �s) of the Recall operation. During tRcc. OE and WE may go LOW providing the host access to other devices in the system.
1-56
X2001, X20011
PIN DESCRIPTIONS Addresses (Ao-A&) The address inputs select an 8-bit word during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE or NE.
Data In/Data Out (l/Oo-1/07) Data is written to or read from the X2001 through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE) The Write Enable input controls the writing of data to both the static RAM and stores to the E2PROM.
Nonvolatile Enable (NE) The Nonvolatile Enable input controls all accesses to the E2PROM array (store and recall functions).
DEVICE OPERATION The CE, OE, WE and NE inputs control the X2001 operation. The X2001 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The 1/0 bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW.
RAM OPERATIONS RAM read and write operations are performed as they would be with any static RAM. A read operation
requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X2001.
NONVOLATILE OPERATIONS With NE LOW, recall and store operations are performed in the same manner as RAM read and write operations. A recall operation causes the entire contents of the E2PROM to be written into the RAM array. The time required for the operation to complete is 5 �s or less. A store operation causes the entire contents of the RAM array to be stored in the nonvolatile E2PROM. The time for the operation to complete is 1O ms or less, typically 5 ms.
POWER-UP RECALL Upon power-up (Vee). the X2001 performs an automatic array recall. When Vee minimum is reached, the recall is initiated, regardless of the state of CE, OE, WE and NE.
WRITE PROTECTION The X2001 has three write protect features that are employed to protect the contents of both the nonvolatile memory and the RAM.
� Noise Protection-A WE pulse of less than 20 ns will not initiate a write cycle.
� Combined Signal Noise Protection-A combined WE and NE (WE � NE) pulse of less than 20 ns will not initiate a store cycle.
� Write Inhibit-Holding either OE LOW, WE HIGH, CE HIGH or NE HIGH during power-up or power-down, will prevent an inadvertent store operation.
1-57
X2001, X20011
Part Number Store Cycles
_j
X2001
100,000
X20011
100,000
Data Changes Per Bit. 10,000
10,000
Normalized Active Supply Current vs. Ambie.nt Temperature
~ 1.2
0
Lo.I
N
:<::i
1.0
a:::::E:
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0051-8
Normalized Access Time vs. Ambient Temperature
SYMBOL TABLE WAVEFORM
__,--
~
xxxxx
it) .~
INPUTS �Must be steady
May change from Low.to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Wiii be steady
Wiii change from Low to High
Will change fro.m High to Low
Changing: State Not Known
Center Line is High Impedance
Normalized Standby Supply Current vs. Ambient Temperature
1.4 ~--__....,-----~ Vcc=5.0V
m 1.2
.J!I
0
Lo.I
N
:<::i
1.0
:a::::E:
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0051-9
...~.. 1.2
0
Lo.I
N
:<::i
1.0
:a::::E:
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0051-10
1-58
)lic1,
4K
Commercial Industrial
X2004 X20041
Nonvolatile Static RAM
512 x 8 Bit
FEATURES �Nonvolatile Data Integrity � Automatic Store Timing � Store and Array Recall Combined on One
Line (NE) � Enhanced Store Protection � Infinite E2PROM Array Recall, and RAM
Read and Write Cycles � Single 5V Supply � High Reliability
-Store Cycles: 100,000 -Data Retention: 100 Years � Fast Access Time: 200 ns Max. �Automatic Recall on Power-Up � JEDEC Approved Byte-Wide Pinout
DESCRIPTION The Xicor X2004 is a byte-wide NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X2004
is fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories. The X2004 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs, EPROMs and E2PROMs.
The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). With NE LOW, these functions are performed in the same manner as RAM read and write operations. The store operation is completed in 10 ms or less and the recall operation is completed in 5 �s or less.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from� the host or recalls from E2PROM, and a minimum 100,000 store operations to the E2PROM. Data retention is� specified to be greater than 100 years. Refer to RR-520, RR-504 and RR-515 for details on Xicor nonvolatile memory endurance and data retention characteristics.
PIN CONFIGURATIONS
PIN NAMES
Ao-Aa l/Oo-1/07 CE OE WE NE
Vee Vss NC
0043-1
0043-2
Address. Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Nonvolatile Enable +5V Ground No Connect
FUNCTIONAL DIAGRAM
NONVOLATILE E2PROM
MEMORY ARRAY
L
.Ao
/
<?- j- STORE
A5
ROW
Ao
SELECT
A,
.3-::Ao
.",..___
=�ARRAY
cOL lRECALL
STATIC RAM MEMORY ARRAY
vr:'.?- I- ~~~:~L
~
"�'
1102 1/03 110. I/Os
"�'
1----
II-
1--
III-
I-
I-
1----
INPUT 1----
CONTROL I - - -
COLUMN 1/0 CIRCUITS
DATA
~
I---
~rn~ ._____
1-59
l
l l L._ L
0043-3
X2004, X20041
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X2004 ................................. -10�C to + 85�C X20041 ............................... - 65�C to + 135�C Storage Temperature .......... ; ......... -65�C to + 150�C
Voltage on any Pin with
Respect to Gr<;>und ........................ -1.0V to + 7V
o.e~ Output Current .................................. 5 mA
Lead Temperature (Soldering, 10 Seconds) , .......................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X2004 TA= 0�C to +70�C, Vee= +5V �5%, unless otherwise specified. X20041 TA= -40�C to +85�C, Vee= +sv �10%, unless otherwise specified.
Symbol
Parameter
X2004 Limits
M�in.
Max.
X20041 Limits
Min.
Max.
Units
Test Conditions
Ice
Vee Current (Active)
100
120
mA CE= V1L.
All Other Inputs= Vee
1110 = O mA
lss
lu ILO V1L(2) V1H(2) Vol VoH
Vcc Current (Standby)
55
90
mA All Inputs = Vcc
1110 = 0 mA
Input Leakage Current
10
10
�A V1N = GND to Vee
Output Leakage Current
10
10
�A VouT = GND to Vee
Input Low Voltage
-1.0
0.8
~1.0
0.8
v
Input High Voltage
2.0 Vee +0.5 2.0 Vee +1.0 v
Output Low Voltage
0.4
0.4
v loL = 2.1 mA
Output High Voltage
2.4
2.4
v loH = -400 �A
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
C110(1)
Input/Output Capacitance
C1N(1)
Input Capacitance
Max. 10 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE WE NE OE
H xxx
L HHL
L L Hx L L Hx
L H L L
L L LH
L HHH L L LL
LH LH
Mode Not Selected Read RAM Write "1" RAM Write "O" RAM Array Recall Nonvolatile Storing Output Disabled Not Allowed No Operation
1/0 Output High Z Output Data Input Data High Input Data Low Output High Z Output High Z Output High Z Output High Z Output High Z
Power Standby Active Active Active Active Active Active Active Active
Notes: (1) This parameter is periodically sampled and not 100% tested. (2) V1L min. and V1H max. are for reference only and are not tested.
1-60
X2004, X20041
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
10,000
Data Changes Per Bit
Store Cycles
100,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS
o�c X2004 TA =
to + 70�C, Vee = + 5V � 5%, unless otherwise specified.
X20041 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits Symbol
Parameter
tRe teE tAA toE tLz(3) tHz(3) toLz(3) toHz(3) toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change
X2004-20 X20041-20
Min. Max.
200
200
200
70
10
10
100
10
10
100
0
X2004-25 X20041-25
Min. Max.
250
250
250
100
10
10
100
10
10
100
0
x2004 X20041
Min. Max.
300
300
300
150
10
10
100
10
10
100
0
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
,.,__ _ _ _ _ t R c - - - - - - - 1
ADDRESS --'l'--------------"'I'------------' ""---
-4--lce---. CE - - -.. r
...__toE_..,. OE----+--...
,..__,AA__.
0043-4
Note: (3) tLz min., tHz min., toLz min. and toHz min. are periodically sampled and not 100% tested. tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
1-61
X2004, X20041
Write Cycle Limits Symbol
Parameter
twc
Write Cycle Time
tcw
Chip Enable to End of Write Input
tAs
Address Setup Time
twp
Write Pulse Width
twR
Write Recovery Time
tow
Data Valid to End of Write
toH
Data Hold Time
twz
Write Enable to Output in High Z
tow
Output Active from End of Write
toz
Output Enable to Output in High Z
WE Controlled Write Cycle
X2004-20 X20041-20
Min. Max.
200
200
0
120
0
120
0
10
100
10
10
100
X2004-25 X20041-25
Min. Max.
250
250
0
150
0
150
0
10
100
10
10
100
X2004 X20041 Min. Max.
300 300
0 200
0 200 0 10 100 10 10 100
Units
ns ns ns ns ns ns ns ns ns ns
CE Controlled Write Cycle
1------lwc------I ADDRESS _ _ _ __, 1.....__ _ _. . , . - - - - - , - - - - - ' T ' - - - - - - - -
0043-5
DATAIN _ _ _ _ _ _ _ _ _ __
1-62
0043-6
X2004, X20041
Store Limits Symbol
Parameter
tsrc tsp tNHZ toEST tsoE tNs
Store Time Store Pulse Width Nonvolatile Enable to Output in High Z Output Enable from End of Store OE Disable to Store Function NE Setup Time from WE
Store Timing
X2004-20 X20041-20 Min. Max.
10 120
100 10 20 0
X2004�25 X20041�25 Min. Max.
10 150
100 10 20 0
X2004 X20041 Min. Max.
10 200
100 10 20 0
Units
ms ns ns ns ns ns
________ Vcc------------------1,.V_ee MIN(4)
0043-7
Note: (4) X2004 Vee Min. = 4.75V X20041 Vee Min. = 4.5V
The Store Pulse Width (tsp) is a minimum time that NE, WE and CE must be LOW simultaneously. To insure data integrity, NE and CE must return HIGH after initiation of and throughout the duration (tsrc. 1O ms) of the Store operation. During tsrc. OE and WE may go LOW providing the host system access to other devices in the system.
1-63
X2004, X20041
Array Recall Cycle Limits
Symbol
Parameter
tRcc tRCP tRWE
Array Recall Time Recall Pulse Width to Initiate Recall WE Setup Time to NE
X2004�20 X20041�20 Min.' Max.
5.0 120 0
X2004�25 X20041�25 Min. Max.
5.0 150
0
X2004 X20041 Min. Max.
5.0 200
0
Units
�s ns ns
Array Recall Cycle
ADDRESS
- - - - - t R C C _ _ _ __
DATA 1/0 -------------------+(-4(:-+(-+(~(:-+(-tQ-t----
0043-B
The Recall Pulse Width (tRcP) is a minimum time that NE, OE and CE must be LOW simultaneously. To insure data integrity, NE and CE must return HIGH after initiation of and through the duration (tRcc. 5 �s) of the Recall operation. During tRcc. OE and WE may go LOW providing the host access to other devices in the system.
1-64
X2004, X20041
PIN DESCRIPTIONS Addresses (Ao-As) The address inputs select an 8-bit word during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE or NE.
Data In/Data Out (l/Oo-1/07) Data is written to or read from the X2004 through the 1/0 pins. The 1/0 pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE) The Write Enable input controls the writing of data to both the static RAM and stores to the E2PROM.
Nonvolatile Enable (NE) The Nonvolatile Enable input controls all accesses to the E2PROM array (store and recall functions).
DEVICE OPERATION The CE, OE, WE and NE inputs control the X2004 operation. The X2004 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The 1/0 bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW.
RAM OPERATIONS RAM read and write operations are performed as they would be with any static RAM. A read operation
requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X2004.
NONVOLATILE OPERATIONS With NE LOW, recall and store operations are performed in the same manner as RAM read and write operations. A recall operation causes the entire contents of the E2PROM to be written into the RAM array. The time required for the operation to complete is 5 �s or less. A store operation causes the entire contents of the RAM array to be stored in the nonvolatile E2PROM. The time for the operation to complete is 1O ms or less, typically 5 ms.
POWER-UP RECALL Upon power-up (Vee), the X2004 performs an automatic array recall. When Vee minimum is reached, the recall is initiated, regardless of the state of CE, OE, WE and NE.
WRITE PROTECTION The X2004 has four write protect features that are employed to protect the contents of both the nonvolatile memory and the RAM.
� Noise Protection-A WE pulse of less than 20 ns will not initiate a write cycle.
� Combined Signal Noise Protection-A combined WE and NE (WE � NE) pulse of less than 20 ns will not initiate a store cycle.
�Vee Sense-All functions are inhibited when Vee is
~2V.
� Write Inhibit-Holding either OE LOW, WE HIGH, CE HIGH or NE HIGH during power-up or power-down, will prevent an inadvertent store operation.
1-65
X2004, X20041
Part Number
X2004 X20041
Store Cycles
100,000 100,000
Data Changes Per Bit 10,000
10,000
Normalized Active Supply Current vs. Ambient Temperature
1.4 ~---~----~ Vcc=5.0V
Ji 1.2
Q
la.I
N
:<::i
1.0
a:2::
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (<>c)
0043-9
Normalized Access Time vs. Ambient Temperature
SYMBOL TABLE WAVEFORM
_//fr ~
xxxxx
B<!K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
Normalized Standby Supply Current vs. Ambient Temperature
ID 1.2
..!!'
Q
la.I
N
:::i
1.0
<
a:2::
0z 0.8
0.6 ~---~----~
-55
+25
+125
AMBIENT TEMPERATURE (0 c)
0043-10
I-~ 1.25
Q
la.I
N
:<::i
1.00
:a2::
0z 0.75
0.50
-55
+25
+125
AMBIENT TEMPERATURE (<>c)
0043-11
1-66
liCll!
X2444, X24441 ........................... . X24C44, X24C441 ........................ . X24C45, X24C451 ........................ . X2402, X24021 ........................... . X2404, X24041 ........................... . X24C01, X24C011 ........................ . X24C02, X24C021 ........................ . X24C04, X24C041 ........................ . X24C16,X24C161 ........................ .
2-1
NOVRAM* Data Sheets
2-11
2-19
2-23
2-33 2-43 2-53
c)
Serial Products Data Sheets
2-63
2-73
256 Bit
Commercial Industrial
X2444 X24441
Nonvolatile Static RAM
1'iCll!
16 x 16 Bit
FEATURES � Ideal for use with Single Chip
Microcomputers -Static Timing -Minimum 1/0 Interface -Serial Port Compatible (COPSTM, 8051) -Easily Interfaces to Microcontroller Ports -Minimum Support Circuits � Software and Hardware Control of Nonvolatile Functions -Maximum Store Protection � TTL Compatible � 16 x 16 Organization � Low Power Dissipation -Active Current: 15 mA Typical -Store Current: 8 mA Typical -Standby Current: 6 mA Typical -Sleep Current: 5 mA Typical � High Reliability -Store Cycles: 100,000 -Data Retention: 100 Years � 8 Pin Mini-DIP and 8 Lead SOIC Packages
DESCRIPTION The Xicor X2444 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit for bit with a nonvolatile E2PROM array. The X2444 is fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V nonvolatile memories.
The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 1O ms or less and a recall operation (E2PROM data to RAM) is completed in 2.5 �s or less.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM and a minimum 100,000 store operations. Data retention is specified to be greater than 100 years. Refer to RR-520 and RR-515 for details on Xicor nonvolatile memory endurance and data retention characteristics.
COPSTM is a trademark of National Semiconductor Corp.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
CE
Vee
SK
STORE
DI
RECALL
DO
Vss
ROW DECODE
0042-1
PIN NAMES
CE(1)
11(3)
CE
Chip Enable
Sll(2)
SK
Serial Clock
DI
Serial Data In
DO
Serial Data Out
RECALL
Recall
STORE
Store
Vee
+5V
Vss
Ground
0042-2
2-1
)(2444, X24441
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X2444 ................................. -:---10�C to + 85�C-- X24441 ............................... -�65�C to + 135�C Storage Temperature ... ; ................ - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.e. Output Current .................................. 5 mA Lead Temperature
(Soldering, 10 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may qause permanent damage to the device. This is a stress rating onty and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.q. OPERATING CHARACTERISTICS X2444 TA = 0�C to + 70�C, Vee�= + 5V � 5%, unless otherwise specified. X24441 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2444 Limits
Min.
Max.
X24441 Limits
Min.
Max.
Ice
Power Supply Current
15
25
Isl lss lsrn lu ILO V1l(2) V1H(2) Vol VoH
Sleep Current Standby Current Store Current Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1.0 2.0
2.4
7 10 12 10 10 0.8 Vee +0.5 0.4
-1.0 2.0
2.4
10 15 15 10 10 0.8 Vee +1.0 0.4
Units
mA
mA mA mA �A �A
v v v v
Conditions
All Inputs = Vee. 1110 = 0 mA
CE= V1l
V1N =Vee VouT =Vee
lol = 2.4 mA loH = -0.8 mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
10,000
Data Changes Per Bit
Store Cycles
100,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 a,nd RR-504 Xicor Reliability Report RR-515
CAPACITANCE TA = 25�C, f = 1.0 MHz, Vee = 5V
Symbol
Test
Max.
C11o<1>
Input/Output Capacitance
8
'
C1N(1)
Input Capacitance
6
_.::_
-"-
Notes: (1) This parameter is periodically sampled and not 100% tested.
(2) V1L min. and V1H max. are for reference only and are not tested.
Units pF pF
Conditions V110 = OV V1N = OV
2-2
X2444, X24441
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels
Output Load
OVto 3.0V 10 ns
1.5V 1 TTL Gate and CL= 100 pF
NONVOLATILE OPERATIONS
Operation
STORE
Hardware Recall
1
Software Recall
1
Hardware Store
0
Software Store
1
RECALL
0 1 1 1
INST
NOP(3) RCL
NOP(3) STO
WRITE ENABLE LATCH
x x
SET
SET
Previous RECALL
x x
True
True
A.C. CHARACTERISTICS
X2444 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X24441 TA = - 40�C to + 85�C, Vcc = + 5V � 10%, unless otherwise specified.
Read and Write Cycle Limits
Symbol
Parameter
FsK
SK Frequency
tsKH
SK Positive Pulse Width
t s KL
SK Negative Pulse Width
tos
Data Setup Time
toH
Data Hold Time
tpo1
SK~ to Data OValid
tpo
SK ~ to Data Valid
tz
Chip Enable to Output High Z
teES
Chip Enable Setup
tcEH
Chip Enable Hold
teos
Chip Deselect
Min.
0.4 0.4 0.4 0.08
0.8 0.4 0.8
Max. 1.0
375 375 1.0
Units MHz �s �s �s �s
ns ns �s �s �s �s
Power-Up Timing(4) Symbol tpuR tpuw
Parameter Power-Up to Read Operation Power-Up to Write Operation
Typical(5) 2.5 2.5
Units �s �s
Notes: (3) NOP designates when the X2444 is not currently executing an instruction.
(4) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
(5) Typical values are for TA = 25�e and Vee = 5V.
2-3
X2444, X24441
Write Cycle
SK CYCLE# SK
CE DI
Read Cycle
SK CYCLE#
6
7
8
SK
CE V1"
DI
DO
Array Recall Cycle Limits
Symbol
Parameter
tRCC
Recall Cycle Time
tRCP
Recall Pulse Width(6)
tRcz
Recall to Output High Z
Recall Cycle
9
Min. 2.5 1.0
10
Max. 0.5
0042-3
0042-4
Units �.s �.s �.s
------tAcp------- ----+---
DO Note: (6) Recall rise time must be <10.�.s.
HIGHZ
0042-5
2-4
X2444, X24441
Store Cycle Limits
Symbol
Parameter
Min.
Typ.(7)
Max.
Units
tsr
Store Time
5
10
ms
tsrP
Store Pulse Width
0.2
�s
tsrz
Store To Output High Z
Vee
Store Inhibit
1.0
�s
3
v
Hardware Store
DO
Figure 1: RAM Read
CE
SK
__ DI
__,
*Bit 8 of Read Instructions is Don't Care
Note: (7) Typical values are for TA = 25�C and nominal supply voltage.
0042-6 0042-7
2-5
X2444, X24441
Figure 2: RAM Write
SK
DI
Figure 3: Non-Data Operations
CE Ill
__ SK
_..
DI
TABLE 1: INSTRUCTION SET
Instruction
Format, 1211 lo
WRDS (Figure 3)
1XXXXOOO
STO (Figure 3)
1XXXX001
SLEEP (Figure 3)
1XXXX010
WRITE (Figure 2)
1AAAA011
WREN (Figure 3)
1XXXX100
RCL (Figure 3)
1XXXX101
READ (Figure 1)
1AAAA11X
X = Don't Care A = Address Bit
\__
\___
0042-8
0042-9
Operation Reset Write Enable Latch (Disables writes and stores) Store RAM Data in E2PROM Enter SLEEP Mode Write Data into RAM Address AAAA Set Write Enable Latch (Enables writes and stores) Recall E2PROM Data into RAM Read Data from RAM Address AAAA
2-6
X2444, X24441
PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be HIGH to enable read/write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X2444 in the standby power mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command.
Serial Clock (SK) The Serial Clock input is used to clock all data into and out of the device.
Data In (DI) Data In is the serial data input.
Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction.
STORE STORE LOW will initiate an internal transfer of data from RAM to E2PROM.
RECALL RECALL LOW will initiate an internal transfer of data from E2PROM to RAM.
DEVICE OPERATION The X2444 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation.
Table 1 contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a one, bits 6 through 3 are either RAM address (A) or don't care (X) and bits 2 through O are the operation codes. The X2444 requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X2444 will not begin to interpret the data stream until a one has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X2444 will begin any action.
In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data.
WRDS and WREN Internally the X2444 contains a "write enable" latch. This latch must be set for either writes to the RAM or store operations to the E2PROM. The WREN instruction sets the latch and the WADS instruction resets the latch, disabling both RAM writes and E2PROM stores. The write enable latch is automatically reset on powerup.
SLEEP The SLEEP instruction removes power from the RAM, placing the X2444 in a very low power quiescent state. Data in the RAM is lost once a SLEEP instruction is issued; however, data from the last store operation is retained in the E2PROM. The sleep mode can be exited by either a software or hardware recall operation.
RCL and RECALL Either the RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. A recall operation must be performed after a power-up before any store or RAM write operation can be enabled. This recall operation and the recall recovery from the sleep mode guarantees a known state of data in RAM. Both recall operations set an internal "previous recall" latch which must be set to enable any write or store operations.
STO and STORE Either the STO instruction or a LOW on the STORE input will initiate the transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true:
1. STO instruction issued or STORE input is LOW;
2. The internal write enable latch must be set (WREN instruction issued);
3. The "previous recall" latch must be set.
Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset.
2-7
X2444, X24441
WRITE
The write instruction contains the 4 bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted in will be written to RAM. If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data) the data already shifted in will be overwritten.
READ
The read instruction contains the 4 bit address of the word to b.e accessed. Unlike the other six instructions, lo is a "don't care" for the read instruction. This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an 1/0 line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle.
DO, the first� bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram).
WRITE PROTECTION
The X2444 provides three hardware and software write protection mechanisms to prevent inadvertent stores of unknown data.
Power-Down Condition (when "write enable" latch and "previous recall" latch are not in the reset state):
� Write Inhibit-Holding either RECALL LOW, CE LOW or STORE HIGH during power-down will prevent an inadvertent store.
Power-Up Condition �Write Enable Latch-Upon power-up the "write en-
able" latch is in the reset state, disabling any store operation.
Unknown Data Store � Previous Recall Latch-The "previous recall" latch
must be set after power-up and after exiting the sleep mode. It may be set only by performing a recall operation, which assures that data in all RAM locations is valid.
LOW POWER MODES The X2444 provides two power conservation modes. When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode. Entering the sleep mode removes power from the entire RAM array, placing the device in a very low power quiescent state (sleep mode).
Part Number
X2444 X24441
Store Cycles
100,000 100,000
Data Changes Per Bit 10,000 10,000
2-8
X2444, X24441
SYSTEM CONSIDERATIONS
Power-Down Data Protection Because the X2444 is a 5V only nonvolatile memory device it may be susceptible to inadvertent writes to the E2PROM array during power-down cycles. Powerup cycles are not a problem because the previous recall latch and write enable latch are reset, preventing any possible corruption of E2PROM data.
If the STORE and RECALL pins are tied to Vee through a pullup resistor and only software store operations are performed to initiate stores, there is little likelihood of an inadvertent store. However, if these two lines are under microprocessor control, positive action should be employed to negate the possibility of these control lines bouncing and generating an unwanted
store. The safest method is to issue the WRDS command after a write sequence and also following store operations. Note: an internal store may take up to 1O ms; therefore, the host microprocessor should delay 1O ms after initiating the store prior to issuing the WRDS command.
Power-On Recall The X2444 performs a power-on recall that transfers the E2PROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the previous recall latch. During this power-on recall operation, all commands are ignored. Therefore, the host should delay any operation with the X2444 a minimum 2.5 �s (tRed after Vee is stable.
SYMBOL TABLE
WAVEFORM
_///T ~
xxxxx
2ID �K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
2-9
X2444, X24441
t\lormalized Active Supply Current v~. Ambient Temperature
1.50 ~---~-----~ Vcc=5.qv
0 Lo.I
; ~ 1.00 r-----------------< <
::E 0:
0 z
Normalized Standby Supply Current
vs. Ambient Temperature
m 1.25 f------+------'-----j ..!!.'
0 Lo.I
~ 1.00 1-----------------1 <
::E 0:
0 z
0.50 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0042-10
0.50 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0042-11
2-10
ADVANCED INFORMATION
256 Bit
Commercial Industrial
X24C44 X24C441
Nonvolatile Static RAM
liCI'
16 x 16 Bit
FEATURES � Advanced CMOS Version of Xicor's X2444 � 16 x 16 Organization � Single 5 Volt Supply � Ideal for use with Single Chip
Microcomputers -Static Timing -Minimum 1/0 Interface -Serial Port Compatible (COPSTM, 8051) -Easily Interfaced to Microcontroller Ports � Software and Hardware Control of Nonvolatile Functions � Auto Recall on Power-Up � TTL and CMOS Compatible � Low Power Dissipation -Active Current: 2 mA -Standby Current: 50 �A � 8 Pin Mini-DIP and 8 Lead SOIC Packages � High Reliability -Store Cycles: 1,000,000 -Data Retention: 100 Years
PIN CONFIGURATION
CE
8 Vee
SK 2
7 STORE
X24C44
DI 3
6 RECALL
DO 4
5 Vss
0121-1
DESCRIPTION
The Xicor X24C44 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit by bit with a nonvolatile E2PROM array. The X24C44 is fabricated with Xicor's Advanced CMOS Floating Gate technologyi
The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 5 ms or less and a recall operation (E2PROM data to RAM) is completed in 2 �s or less.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM and a minimum 1,000,000. store operations. Inherent data retention is specified to be greater than 100 years. Refer to RR-520 and RR-515 for details of endurance and data retention characteristics for Xicor nonvolatile memories.
COPSTM is a trademark of National Semiconductor Corp.
PIN NAMES
CE SK DI DO RECALL STORE
Vee
Vss
Chip Enable Serial Clock Serial Data In Serial Data Out Recall Input Store Input +5V Ground
2-11
X24C44,. X24C441
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X24C44 ............................... :-10�C to .+ 85�e X24C441 .............................. - 65�e to + 135�e Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) ...........................300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" .may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X24C44 TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified.
X24C441 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
Min. Max. Units
Conditions
Ice
Vee Supply Current (TTL Inputs)
2
mA SK = TTL Levels @ 1 MHz,
DO= Open, All Other Inputs= V1H
lss1. . Vee Standby Current (TTL Inputs)
1
mA DO = Open, CE = VIL�
All Other Inputs = V1H
lss2
Vee Standby Current (CMOS Inputs)
50
�A DO = Open, CE = GND,
All Other Inputs= Vee -.0.3V
lu
Input Load Current
10
�A V1N = GND to Vee
ILO V1L(1) V1H(1) YoL YoH
Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
10
�A VouT = GND to Vee
-1.0
0.8
v
.2.0 Vee+ 1 v
0.4
v loL = 4.2 mA
2.4
v loH = -2mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
Data Changes .Per Bit
Store Cycles
1,000,000
Store Cycles
Data Retention
100
Years
Conditions Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Reports RR-520 and RR-504 Xicor Reliability Report RR-515
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol CouT(2)
Test Output Capacitance
C1N(2)
Input Capacitance
Notes: (1) V1L min. and V1H max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Max. 8 6
Units pF pF
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Conditions
VouT = ov
V1N = OV
OVto 3.0V 10 ns
1.5V 1 TTL Gate and CL= 100 pF
2-12
X24C44, X24C441
A.C. CHARACTERISTICS X24C44 TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X24C441 TA = -40�C to + 85�C, Vee = + 5V � 10%, unless otherwise specified.
Read and Write Cycle Limits
Symbol
Parameter
Min.
Max.
FsK
SK Frequency
1.0
tsKH
SK Positive Pulse Width
400
t s KL
SK Negative Pulse Width
400
tos
Data Setup Time
400
toH
Data Hold Time
80
tpo1
SK to Data Bit OValid
375
tpo
SK to Data Valid
375
tz
Chip Enable to Output High Z
1.0
tcES
Chip Enable Setup
800
tcEH
Chip Enable Hold
400
tcos
Chip Deselect
800
Power-Up Timing(3) Symbol tpuR tpuw
Parameter Power-Up to Read Operation Power-Up to Write or Store Operation
Max. 200
5
Write Cycle
SK CYCLE# SK
Units MHz
ns ns ns ns ns ns �s ns ns ns
Units �s ms
Read Cycle
0121-2
0121-3
Note: (3) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
2-13
X24C44, X24C441
NONVOLATILE OPERATIONS
Operation
STORE
RECALL
: Softwar.e� Instruction
Hardware Recall
1
Software Recall
1
Hardware Store
0
Software Store
1
0
NOP(4)
1
RCL
1
NOP(4)
1
STO
Array Recall Limits Symbol tRee tReP tRez
Parameter Recall Cycle Time Recall Pulse Width(5) Recall to Output in High Z
Min. �' 2
500
Recall Timing
Write Enable Latch State
x x
SET SET
Max.
500
Previous Recall Latch
State
x x
SET SET
Units �s ns ns
-----tRcp-------. ----+----
DO
Store Cycle Limits Symbol tsT tsTP tsTZ Vee
Parameter Store Time Store Pulse Width Store to Output in High Z Store Inhibit
Store Timing
HIGHZ
Min.
Typ.(6)
2
200
3
0121-4
Max. 5
100
Units ms ns ns
v
DO
Notes: (4) NOP designates when the X24e44 is not currently executing an instruction. (5) Recall rise time must be < 10 ns. (6) Typical values ~re for TA = 25�e .and nominal supply voltage.
2-14
0121-5
X24C44, X24C441
Figure 1: RAM Read
CE
___ SK
_.
D O - - - - - - - -HIG-H-Z - - - - - - - - <
*Bit 8 of Read Instructions is Don't Care
0121-6
Figure 2: RAM Write
CE_j,L.J .-r-r-----------------------J() r(------~\__
SK
DI
Figure 3: Non-Data Operations
CE
Ill
___ SK
_.
DI --...J
TABLE 1: INSTRUCTION SET
Instruction
Format, 1211 lo
WADS (Figure 3)
1XXXXOOO
STO (Figure 3)
1XXXX001
Reserved WRITE (Figure 2) WREN (Figure 3)
1XXXX010 1AAAA011 1XXXX100
RCL (Figure 3)
1XXXX101
READ (Figure 1)
1AAAA11X
X = Don't Care A= Address
\___
0121-8
Operation Reset Write Enable Latch (Disables Writes and Stores) Store RAM Data in E2PROM NIA Write Data into RAM Address AAAA Set Write Enable Latch (Enables Writes and Stores) Recall E2PROM Data into RAM Read Data from RAM Address AAAA
2-15
X24C44, X24C441
PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X24C44 in the low power standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command.
Serial Clock (SK) The Serial Clock input is used to clock all data into and out of the device.
Data In (DI) Data In is the serial data input.
Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction.
STORE STORE LOW will initiate an internal transfer of data from RAM to the E2PROM array.
RECALL RECALL LOW will initiate an internal transfer of data from E2PROM to the RAM array.
DEVICE OPERATIONS The X24C44 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation.
Table 1 contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address (A) or don't care (X) and bits 2 through O are the operation codes. The X24C44 requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C44 will not begin to interpret the data stream until a logic one has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C44 will begin any action.
In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data.
RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. This software or hardware recall operation sets an internal "previous recall" latch. This latch is reset upon power-on and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation.
WRDS and WREN Internally the X24C44 contains a "write enable" latch. This latch must be set for either writes to the RAM or store operations to the E2PROM. The WREN instruction sets the latch and the WADS instruction resets the latch, disabling both RAM writes and E2PROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up.
STO and STORE Either the software STO instruction or a LOW on the STORE input will initiate a transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true:
1. STO instruction issued or STORE input is LOW.
2. The internal write enable latch must be set (WREN instruction issued).
3. The "previous recall" latch must be set (either a software or hardware recall operation).
Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations.
2-16
X24C44, X24C441
WRITE The write instruction contains the 4 bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten.
READ The read instruction contains the 4 bit address of the word to be accessed. Unlike the other six instructions, lo of the instruction word is a "don't care". This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an 1/0 line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle.
DO, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram).
LOW POWER MODE When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption.
SLEEP Because the X24C44 is a low power CMOS device, the SLEEP instruction implemented on the first generation NMOS device has been deleted. For systems converting from the X2444 to the X24C44 the software need not be changed; the instruction will be ignored.
WRITE PROTECTION The X24C44 provides two software write protection mechanisms to prevent inadvertent stores of unknown data.
Power-Up Condition Write Enable Latch. Upon power-up the "write enable" latch is in the reset state, disabling any store operation.
Unknown Data Store Previous Recall Latch. The "previous recall" latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid.
SYSTEM CONSIDERATIONS
Power-On Recall The X24C44 performs a power-on recall that transfers the E2PROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the "previous recall" latch. During this poweron recall operation, all commands are ignored. Therefore, the host should delay any operations with the
X24C44 a minimum 200 p.s (tpuR) after Vcc is stable.
Power-Down Data Protection Because the X24C44 is a SV only nonvolatile memory device it may be susceptible to inadvertent stores to the E2PROM array during power-down cycles. Powerup cycles are not a problem because the previous recall latch and write enable latch are reset, preventing any possible corruption of E2PROM data.
Software Power-Down Protection
If the STORE and RECALL pins are tied to Vee
through a pullup resistor and only software operations are performed to initiate stores, there is little likelihood of an inadvertent store. However, if these two lines are under microprocessor control, positive action� should be employed to negate the possibility of these control lines bouncing and generating an unwanted store. The safest method is to issue the WRDS command after a write sequence and also following store operations. Note: an internal store may take up to 5 ms; therefore, the host microprocessor should delay 5 ms after initiating the store prior to issuing the WRDS command.
Hardware Power-Down Protection (when the "write enable" latch and "previous recall" latch are not in the reset state):
Write Inhibit. Holding either RECALL LOW, CE LOW or STORE HIGH during power-down will prevent an inadvertent store.
2-17
X24C44, X24C441
Figure 4: X24C44 State Diagram
STO or WRDS CMD
or STORE
SYMBOL TABLE WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
FUNCTIONAL DIAGRAM
0121-10
ROW DECODE
CE(1)-----IM Dl(3)----<1.......-.M $1<(2) - - - - - - f - - I M
INSTRUCTION REGISTER
S'ToiiE(7) D0(4)
2-18
0121-9
FACT SHEET
256 Bit
Commercial Industrial
X24C45 X24C451
Nonvolatile Static RAM
'c1m:
16 x 16 Bit
FEATURES � AutostoreTM
-Automatically Performs a Store Operation Upon Loss of Vcc
� Single 5 Volt Supply � Ideal for use with Single Chip
Microcomputers -Minimum 1/0 Interface -Serial Port Compatible (COPSTM, 8051) -Easily Interfaced to Microcontroller Ports � Software and Hardware Control of Nonvolatile Functions � Auto Recall on Power-Up � TTL and CMOS Compatible � Low Power Dissipation -Active Current: 2 mA -Standby Current: 50 �A � 8 Pin Mini-DIP and 8 Lead SOIC Packages � High Reliability -Store Cycles: 1,000,000 -Data Retention: 100 Years
DESCRIPTION The Xicor X24C45 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit by bit with a nonvolatile E2PROM array. The X24C45 is fabricated with Xicor's Advanced CMOS Floating Gate technology.
The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 5 ms or less and a recall operation (E2PROM data to RAM) is completed in 2 �s or less.
The X24C45 also features Autostore, a user selectable feature that will automatically perform a store operation when Vee falls below a preset threshold.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years. Refer to RR-520 and RR-515 for details of endurance and data retention characteristics for Xicor nonvolatile memories.
PIN CONFIGURATION
CE
8 Vee
SK 2
7 STORE
X24C45
DI 3
6 RECALL
DO 4
5 Vss
0127-1
PIN NAMES
CE SK DI DO RECALL STORE
Vee Vss
Chip Enable Serial Clock Serial Data In Serial Data Out Recall Input Store Input
+5V
Ground
AutostoreTM is a trademark of Xicor, Inc. COPSTM is a trademark of National Semiconductor Corp.
2-19
X24C45, X24C451
PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X24C45 in the low power standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command.
Serial Clock (SK) The Serial Clock input is used to clock all data into and out of the device.
Data In (DI) Data In is the serial data input.
Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction.
STORE STORE LOW will initiate an internal transfer of data from RAM to the E2PROM array.
RECALL RECALL LOW will initiate an internal transfer of data from E2PROM to the RAM array.
DEVICE OPERATIONS The X24C45 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation.
Table 1 contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address (A) or don't care (X) and bits 2 through O are the operation codes. The X24C45 requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C45 will not begin to interpret the data stream until a logic one has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C45 will begin any action.
In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data.
RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. This software or hardware recall operation sets an internal "previous recall" latch. This latch is reset upon power-on and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation.
WRDS and WREN Internally the X24C45 contains a "write enable" latch. This latch must be set for either writes to the RAM or store operations to the E2PROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and E2PROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up.
STO and STORE Either the software STO instruction or a LOW on the STORE input will initiate a transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true:
1. STO instruction issued or STORE input is LOW.
2. The internal write enable latch must be set (WREN instruction issued).
3. The "previous recall" latch must be set (either a software or hardware recall operation).
Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations.
2-20
X24C45, X24C451
WRITE
The write instruction contains the 4 bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten.
READ
The read instruction contains the 4 bit address of the word to be accessed. Unlike the other six instructions, lo of the instruction word is a "don't care". This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an 110 line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle.
DO, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption.
AUTOSTORE The autostore instruction sets the autostore enable latch, allowing the X24C45 to automatically perform a
store operation when Vcc falls below the autostore
threshold.
WRITE PROTECTION
The X24C45 provides two software write protection mechanisms to prevent inadvertent stores of unknown data.
Power-Up Condition Write Enable Latch. Upon power-up the "write enable" latch is in the reset state, disabling any store operation.
Unknown Data Store Previous Recall Latch. The "previous recall" latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid.
SYSTEM CONSIDERATIONS
Power-On Recall The X24C45 performs a power-on recall that transfers the E2PROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the "previous recall" latch. During this poweron recall operation, all commands are ignored. Therefore, the host should delay any operations with the
X24C45 a minimum 200 �s (tpuR) after Vcc is stable.
2-21
NOTES
2-22
JiCI'
2K
Commercial Industrial
X2402 X24021
256 x 8 Bit
Electrically Erasable PROM
TYPICAL FEATURES �Internally Organized 256 x 8 � 2 Wire Serial Interface � Provides Bidirectional Data Transfer
Protocol � Eight Byte Page Write Mode
-Minimizes Total Write Time Per Byte � Self Timed Write Cycle
-Typical Write Cycle Time of 5 ms � High Reliability
-Endurance: 100,000 Writes Per Byte -Data Retention: 100 Years � 8 Pin Mini-DIP and 14 Lead SOIC Packages
PIN CONFIGURATIONS
Ao
Vee
NC
A,
TEST
Ao
At
A,
SCL
NC
A2
Vss
SDA
Vss
0035-1
NC
DESCRIPTION
The X2402 is a 2048 bit serial E2PROM, internally organized as one 256 x 8 page. The X2402 is fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories.
The X2402 features a serial interface and software protocol allowing operation on a two wire bus.
Xicor E2PR0Ms are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 100,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
NC
Vee
TEST
NC SCL
SDA
NC
0035-11
PIN NAMES
Ao to A2 Vss SDA SCL Test Vee
Address Inputs Ground Serial Data Serial Clock Input to Vss Supply Voltage
2-23
X2402, X24021
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
x2402 ................................. -1 o�c to + as�c X24021 ............................... - 65�C to + 135�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Vss ........................... -1.0V to +7V
D.C. Output Current ..................................5 mA Lead Temperature
(Soldering, 1OSeconds) ........................... 30Q�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X2402 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X24021 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2402 Limits Min. Typ.(1) Max.
X24021 Limits Min. Typ.(1) Max.
Units Test Conditions
Ice
Vcc Supply Current
20
30
20
35
mA fSCL = 100 KHz
lss
Vcc Standby Current
15
25
15
30
mA
lu
Input Leakage Current
0.1
10
0.1
10
�A V1N = GND to Vee
I Lo
Output Leakage Current
0.1
10
0.1
10
�A VouT = GND to Vee
ITP(2) V1L(4)
Test Pin Pull Down Current
16
Input Low Voltage
-1.0
30
16
0.8 -1.0
30
�A V1N =Vee
0.8
v
V1HC4) Input High Voltage
2.0
Vol Output Low Voltage
Vee +o.5 2.0 0.4
v Vee +1.0
0.4
v loL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
100,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
CAPACITANCE
--
Symbol
c11o(3)
C1NC3)
TA = 25�C, f = 1.0 MHz, Vee = 5V Test
Input/Output Capacitance (SDA) Input Capacitance (Ao. A1, A2, SCL)
Max. 8 6
Units pF pF
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage.
(2) Test pin has on chip pull down device which sinks 16 �,A (typical) to VSS�
(3) This parameter is periodically sampled and not 100% tested.
(4) V1L min. and V1H max. are for reference only and are not tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Conditions V110 = OV V1N = OV
OV to 3.0V 10 ns
1.5V 1 TTL Gate and CL= 100 pF
2-24
X2402, X24021
A.C. CHARACTERISTICS
X2402 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X24021 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
Min.
fseL
SCL Clock Frequency
0
T1
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
tsuF
Time the Bus Must be Free Before
4.7
a New Transmission Can Start
tHo:STA
Start Condition Hold Time
4.0
tLOw
Clock Low Period
4.7
tHIGH
Clock High Period
4.0
tsu:STA
Start Condition Setup Time
4.7
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
tsu:OAT
Data In Setup Time
250
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
tsu:STO
Stop Condition Setup Time
4.7
toH
Data Out Hold Time
300
Max. 100 100 3.5
1 300
Units KHz ns
�s
�s
�s �s �s �s
�s ns �s ns �s ns
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
Write Cycle Time
5
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X2402
bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Bus Timing
soA-----~ 1
IN
SDA~~~~~~~~"7'~:r------~~,-------------------
OUT~~l.lJ.~~~~!LlL~~:,___ _ _ _ _ _ _-f-~~--------------------
0035-3
Note: (5) Typical values are for TA = 25�C and nominal supply voltage.
2-25
X2402, X24021
Write Cycle Timing SCL - - - - -
STOP CONDITION
START CONDITION
X2402 ADDRESS
0035-4
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
Address (Ao, A1, A2) The Address inputs are used to set the least significant three bits of the seven bit slave address. The inputs are static, and should be tied HIGH or LOW, forming one unique address per device.
Figure 1: Data Validity
DEVICE OPERATION
The X2402 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X2402 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indication start and stop conditions. Refer to Figures 1 and 2.
SDA
DATA STABLE
0035-5
2-26
X2402, X24021
Figure 2: Definition of Start and Stop
SDA
''-~--'
SCL - - - - -....
'----+""'
START BIT
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X2402 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Stop Condition All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH.
Figure 3: Acknowledge Response from Receiver
STOP BIT
0035-6
Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
The X2402 will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X2402 will respond with an acknowledge after the receipt of each subsequent eight bit word.
l SCLFROM
MASTER
-
-
-
I
-:
t
-
\ L
.
.
.
J r
-
-
1
\
. L
.
.
.
J I I
I
r��- I ~t
8
I
9
I
I
I
I
:
:
I
DATA OUTPUT
I
~----J
I I
I I
FROM
�
I
TRANSMITTER
:
---- �
1
1
1
I
I
I
DATA OUTPUT
---------I L_I [-
FROM
RECEIVER
1
I I
I
I
I
I
I
I
I
START
ACKNOWLEDGE
0035-7
2-27
X2402, X24021
In the read mode the X2402 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X2402 will continue to transmit data. If an acknowledge is not detected, the X2402 will terminate further data transmissions and await the stop condition.
DEVICE ADDRESSING Following a start condition the bus master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X2402 this is fixed as 1010[8].
Figure 4: Slave Address
DEVICE TYPE IDENTIFIER
I o: o 1:
1: :A2:A1;Ao:R!WI
\.
j
�
DEVICE
ADDRESS
0035-8
The next three significant bits a~dress a particular device. A system could have up to eight X2402 devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs.
Figure 5: Byte Write
The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected; when set to zero a write operation is selected.
Following the start condition, the X2402 monitors the SDA bus comparing the slave address being transmit-
ted with its address (device type and state of Ao. A1
and A2 inputs). Upon a compare the X2402 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X2402 will execute a read or write operation.
WRITE OPERATIONS
Byte Write For a write operation, the X2402 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X2402 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X2402 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X2402 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
SDA LINE
BUS ACTIVITY: X2402
s
T
C!:I A\IC
wnnn
s
T
[TR31-JAlD-DCR-ES-S l-
ADDRESS
I::::::
DATA
0
p
:11::::::: IPf
A
A
A
c
c
c
K
K
K
0035-9
2-28
X2402, X24021
Figure 6: Page Write
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X2402
s
T
S
A
SLAVE
T
en:: ::: ITTJl T------ ..--�-.... ,_.._,,_ ---�- R
ADDRESS
WORD ADDRESS (n)
DATA n
DATA n + 1
DATA n + 7
0
~--�- p
CJ, 1::::::: 11::::::: 11::::::: 1
10
A
A
A
A
A
c
c
c
c
c
K
K
K
K
K
0035-10
NOTE: In this example n = XXXX XOOO(B); X = 1 or 0
Page Write The X2402 is capable of an eight byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to seven more words. After the receipt of each word, the X2402 will respond with an acknowledge.
After the receipt of each word, the three low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X2402 initiates the internal write cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave address for a write operation. If the X2402 is still busy with the write operation no ACK will be returned. If the X2402 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation.
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read.
Current Address Read Internally the X2402 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read opera-
tion would access data from address n + 1. Upon re-
ceipt of the slave address with R/W set to one, the X2402 issues an acknowledge and transmits the eight bit word. The master does not acknowledge the transfer but does generate a stop condition and the X2402 discontinues transmission. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
Figure 7: Current Address Read
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X2402
s
T
s
A
SLAVE
T
R
ADDRESS
0
T--
p
A----
C
DATA
K
0035-13
2-29
X2402, X24021
Figure 8: Random Read
s
T BUS ACTIVITY: A
SLAVE
MASTER
R
ADDRESS
WORD ADDRESS n
SLAVE ADDRESS
SDA LINE
A
BUS ACTIVITY:
c
X2402
K
0035-14
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X2402 and then by the eight bit word. The master does not acknowledge the transfer but does generate a stop condition and the X2402 discontinues transmission. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is
transmitted as with the other read modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X2402 continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge and generating a stop condition.
The data output is sequential, with the data from ad-
dress n followed by the data from n + 1. The address
counter for read operations increments all eight address bits, allowing the entire memory contents of the current 256 word page to be serially read during one operation. If more than 256 words are read, the counter "rolls over" and the X2402 continues to output data from the same 256 word page for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
Figure 9: Sequential Read
BUS ACTIVITY: SLAVE
A
A
A
MASTER
ADDRESS
C
C
C
SDA LINE BUS ACTIVITY:
=JlA - - - - 0 ,_
K
K
K
...
I : : : : : : : 11 : : : : : : : 11 : : : : : : : I
c
DATA n
DATA n+1
DATA n+2
X2402
K
s
T 0 P
- B I : : : : : : : I DATA n+x
0035-15
2-30
X2402, X24021
Figure 10: Typical System Configuration
Vee
SDA - - - -.....- - - - - -.....- - - - - -....- - - - - -....- - - - - - . . . . . . . ,
scL-..---+----1>------lf----..----+--+-----&----......-----JL--...J
MASTER TRANSMITTER/
RECEIVER
SLAVE RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/
RECEIVER
FUNCTIONAL DIAGRAM
0035-16
(8) Vee _ _ (4) Vss _ _
START CYCLE
H.V. GENERATION TIMING
& CONTROL
START STOP LOGIC
SLAVE ADDRESS REGISTER
+COMPARATOR
(3) A2 - - 1 - - - - . . 1 (2)A1
(1) Ao - - ' - - - - - -...
CONTROL LOGIC
LOAD
INC
E2PROM 32x64
64 YDEC
Dour ACK
CK PIN
DATA REGISTER
0035-2
2-31
X2402, X24021
Normalized Active Supply Current
vs. Ambient Temperature
1.4 ~---~----~ Vcc=5.0V
(.) 1.2
.9
c
lo.I
N
:<J
1.0
:I
It:
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0035-17
SYMBOL TABLE
WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
Normalized Standby Supply Current vs. Ambient Temperature
m 1.2 .J!I
c
lo.I
N
:J
1.0
<
:I
It:
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0035-18
2-32
JiCll!
4K
Commercial Industrial
X2404 X24041
Electrically Erasable PROM
512 x 8 Bit
TYPICAL FEATURES � Internally Organized as Two Pages
-Each 256 x 8 � 2 Wire Serial Interface � Provides Bidirectional Data Transfer
Protocol � Eight Byte Page Write Mode
-Minimizes Total Write Time Per Byte � Self Timed Write Cycle
-Typical Write Cycle Time of 5 ms �High Reliability
-Endurance: 100,000 Writes Per Byte -Data Retention: 100 Years � 8 Pin Mini-DIP and 14 Lead SOIC Packages
PIN CONFIGURATIONS
Ao
Vee
NC
Ao
A,
TEST
A1
X2404
A2
3
6
SCL
NC
Az
Vss
4
5
SDA
Yss
NC
0041-1
DESCRIPTION The X2404 is a 4096 bit serial E2PROM, internally organized as two 256 x 8 pages. The X2404 is fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories.
The X2404 features a serial interface and software protocol allowing operation on a two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 100,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
NC Yee
TEST
NC SCL
SDA
NC
0041-19
PIN NAMES
Ao to A2
Vss
SDA SCL Test Vee
Address Inputs Ground Serial Data Serial Clock Input to Vss Supply Voltage
2-33
X2404�, X24041
ABSOLUTE MAXIMUM RATINGS*
Temperature� Under Bias
X2404 ............................. , ... -10�C to + 85�C X24041 ............................... - 65�C to + 135�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Vss ........................... -1.0V to +7V
D.C. Output Current .........................�......... 5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended. periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X2404 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X24041 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2404 Limits Min. Typ.(1) Max.
X24041 Limits Min. Typ.{1) Max.
Units Test Conditions
Ice
Vcc Supply Current
20
30
20
35
mA fSCL = 100 KHz
lss
Vcc Standby Current
15
25
15
30
mA
lu
Input Leakage Current
0.1
10
0.1
10
�A V1N = GND to Vee
ILO
Output Leakage Current
0.1
10
0.1
10
�A VouT = GNDtoVcc
1Tp(2) Test Pin Pull Down Current
16
30
16
30
�A V1N =Vee
V1L(4) Input Low Voltage
-1.0
0.8 -1.0
0.8
v
Y1H(4) Input High Voltage
2.0
Vee +0.5 2.0
Yee+ 1.0 v
Vol Output Low Voltage
0.4
0.4
v loL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
100,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
c11o(3)
C1N(3)
Test Input/Output Capacitance (SDA) Input Capacitance (Ao, A1, A2, SCL)
Max. 8 6
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) Test pin has on chip pull down device which sinks 16 �A (typical) to Vss. (3) This parameter is periodically sampled and not 1OOo/o tested. (4) Y1L min. and Y1H max. are for reference only and are not tested.
Units pF pF
Conditions V110 = OV V1N = OV
2-34
X2404, X24041
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels
Output Load
OV to 3.0V 10 ns
1.5V 1 TTL Gate and CL= 100 pF
SYMBOL TABLE WAVEFORM
_///T ~
xxxxx
2m �K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
A.C. CHARACTERISTICS
X2404 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X24041 TA = - 40�C to + 85�C, Vcc = + 5V � 10%, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
fscL
SCL Clock Frequency
T1
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
tsuF
Time the Bus Must be Free Before a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOw
Clock Low Period
tHIGH
Clock High Period
tsu:STA
Start Condition Setup Time (for a Repeated Start Condition)
tHD:DAT tsu:DAT
Data In Hold Time Data In Setup Time
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
tsu:STO toH
Stop Condition Setup Time Data Out Hold Time
Min. 0
4.7 4.0 4.7 4.0 4.7 0 250
4.7 300
Max. 100 100 3.5
1 300
OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
Units KHz
ns
�s
�s
�s �s �s
�s
�s ns �s ns �s ns
2-35
X2404, X24041
Write Cycle Limits
symbol
Parameter
Min.
Typ.(5}
Max.
Units
twR
Write Cycle Time
5
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to �the end of the internal erase/program cycle. During the write cycle, the X2404 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
Address (Ao) Ao is unused by the X2404, however, it must be tied to Vss to ensure proper device operation.
Bus Timing
Address (A1, A2) The Address inputs are used to set the least significant two bits of the six bit slave address. The inputs are static, and should be tied HIGH or LOW, forming one unique address per device.
DEVICE OPERATION
The X2404 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X2404 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indication start and stop conditions. Refer to Figures 1 and 2.
Write Cycle Timing
SCL----SDA
STOP CONDITION
Note: (5) Typical values are for TA = 25�C and nominal supply voltage.
0041-3
START CONDITION
X2404 ADDRESS
0041-4
X2404, X24041
Figure 1: Data Validity
SDA
l I
I
I I
i1 x-I :-----.1~I
______yII ---------lII--1-II -----------~~I1'----------
SCL
'
I
I
I
I
I
I
I
I
I
DATA STABLE
DATA CHANGE
0041-5
Figure 2: Definition of Start and Stop
SDA
__, '~,....__
SCL ------+--.
'~--+-''
START BIT
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X2404 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Stop Condition All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH.
STOP IT
0041-6
Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
The X2404 will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X2404 will respond with an acknowledge after the receipt of each subsequent eight bit word.
2-37
X2404, X24041
Figure 3: Acknowledge Response from Receiver
I
I
I
r�.��-, : :
l SCL FROM
MASTER
-
.
r
-
\ L
...
.JI
\
1
.L.
.
..J
L-.1~ 8 ~ I ,-:-9-V1.: ---
:
. I
I
DATA FORUOTMPUT
l
I
~----J
.
:
I
I
I
I
I
I
TRANSMITTER
1
1
I
DATA
OUTPUT
----
1 I
I I
I
I
�-------L_j-
FROM
RECEIVER
1
I
I
i
I
I
I
I
I
I
START
ACKNOWLEDGE
0041-7
In the read mode the X2404 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X2404 will continue to transmit data. If an acknowledge is not detected, the X2404 will terminate further data transmissions and await the stop condition.
DEVICE ADDRESSING
Following a start condition the bus master must output
the address of the slave it is accessing. The most sig-
nificant four bits of the slave address are the device
type identifier (see Figure 4). For the X2404 this is fixed
as 1010[8].
�
Figure 4: Slave Address
DEVICE TYPE IDENTIFIER
PAGE SELECT
I 1 : o : 1 : o : A< A< Ao :R!WI -.DEVICE ADDRESS
0041-B
The next two significant bits address a particular device. A system could have up to four X2404 devices on the bus (see Figure 10). The four addresses are defined by the state of the A1 and A2 inputs.
The next bit of the slave address field (bit 1) is the page select bit. It is used by the host to toggle between the two 256 word pages of memory.
The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected; when set to zero a write operation is selected.
Following the start condition, the X2404 monitors the SDA bus comparing the slave address being transmitted with its address (device type and state of A1 and A2 inputs). Upon a compare the X2404 outputs an acknowledge on the SDA line. Depending on the sta,te of the R/W bit, the X2404 will execute a read or write operation.
WRITE OPERATIONS
Byte Write For a write operation, the X2404 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X2404 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X2404 begins the internal write cycle to the nonvolatiie memory. While the internai write cycle is in progress the X2404 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
2-38
X2404, X24041
Figure 5: Byte Write
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X2404
s
T
A
SLAVE
R
ADDRESS
T
lllil D
s
WORD
T
ADDRESS
DATA
0
p
I::::::: 11:::: :::I[Pf
A
A
A
c
c
c
K
K
K
0041-9
Figure 6: Page Write
BUS ACTIVITY: MASTER
SDA LINE
BUS ACnVITY: X2404
s
T
S
A
SLAVE
T
ITTJl DI T-�--- ..-�-.. ..-�-.. ...-�-.... R
ADDRESS
WORDADDRESS(n)
DATAn
DATAn+l
DATAn+7
0
I::::::: 11::::::: 11::::::: l~l::::: I G ~....-.---.. p
A
A
A
A
A
c
c
c
c
c
K
K
K
K
K
0041-10
NOTE: In this example n = XXXX XOOO(B); X = 1 or 0
Page Write The X2404 is capable of an eight byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to seven more w.ords. After the receipt of each word, the X2404 will respond with an acknowledge.
After the receipt of each word, the three low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X2404 initiates the internal write cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave address for a write operation. If the X2404 is still busy with the write operation no ACK will be returned. If the X2404 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation.
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read.
Current Address Read Internally the X2404 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read opera-
tion would access data from address n + 1. Upon re-
ceipt of the slave address with R/W set to one, the X2404 issues an acknowledge and transmits the eight bit word. The master does not acknowledge the transfer but does generate a stop condition and the X2404 discontinues transmission. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
2-39
X2404, X24041
Figure 7: Current Address Read
s
T
BUS ACTIVITY: A
SLAVE
MASTER
R
ADDRESS
SDA LINE
BUS ACnYITY: X2404
A--
C
DATA
K
0041-13
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X2404 and then by the eight bit word. The master does not acknowledge the transfer but does generate a stop condition and the X2404 discontinues transmission. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X2404 continues to output data for each acknowledge received. The read operation is terrninated by the master not responding with an acknowledge and generating a stop condition.
Figure 8: Random Read
The data output is sequential, with the data from ad-
dress n followed by the data from n + 1. The address
counter for read operations increments all eight address bits, allowing the entire memory contents of the current 256 word page to be serially read during one operation. If more than 256 words are read, the counter "rolls over" and the X2404 continues to output data from the same 256 word page for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
ENDURANCE
Xicor E2PROMs are designed and tested for applications requiring extended endurance. The process average for endurance of Xicor E2PR0Ms is approximately % million cycles, as documented in RR504, the Xicor Reliability Report on Endurance. Included in that report is a method for determining the expected endurance of the device based upon the specific application environment. RR504 and additional reliability reports are available from Xicor.
s
T BUS ACTIVITY: A
SLAVE
MASTER
R
ADDRESS
WORD ADDRESS n
SDA LINE
A
BUS ACTIVITY:
c
X2404
K
s
T
A
SLAVE
R
ADDRESS
DATA n
0041-14
2-40
X2404, X24041
Figure 9: Sequential Read
BUS ACTIVITY: SLAVE
A
A
A
MASTER
ADDRESS
C
C
C
SDA LINE
=Jl C1i � -
�
K
K
K
"'
I : : : : : : : 11 : : : : : : : 11 : : : : : : : I
BUS ACTIVITY:
A - - . .. - - - - . . - - - - - . , . - -
c
DATA n
DATA n+1
DATA n+2
X2404
K
s
T 0
G P
I : : : : : : : I
._....-"
DATA n+x
0041-15
Figure 10: Typical System Configuration
Yee
------..----------ir- SDA ~---,._-------4~-----......
SCL ......---+----4~----li----+----1---,._---+---<1..-----11----'
MASTER TRANSMITTER/
RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/
RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/
RECEIVER
FUNCTIONAL DIAGRAM
0041-16
(8) Vee _ _ (4) Vss _ _
START CYCLE
H.V. GENERATION TIMING
a CONTROL
START STOP LOGIC
SLAVE ADDRESS REGISTER
+COMPARATOR (31 A _ _ _ ___,
2
(2) A, --1----_... (1) Ao - - - - - -
CONTROL LOGIC
LOAD
INC
PIN DouT ACK
2-41
0041-2
X2404, X24041
Normalized Active Supply Current vs. Ambient Temperature
Normalized Standby Supply Current vs. Ambient Temperature
0.6 ~---~----~
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0041-17
0.6 ~---~----~
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0041-18
2-42
PRELIMINARY INFORMATION
1K
Commercial Industrial
X24C01 X24C011
Electrically Erasable PROM
liCll!
128 x 8 Bit
TYPICAL FEATURES � Low Power CMOS
-Active Current Less Than 1 mA -Standby Current Less Than 50 �A � Internally Organized 128 x 8 � 2 Wire Serial Interface -Bidirectional Data Transfer Protocol � Four Byte Page Write Mode � Self Timed Write Cycle -Typical Write Cycle Time of 5 ms �High Reliability -Endurance: 100,000 Cycles Per Byte -Data Retention: 100 Years � 8-Pin Mini-DIP and 8-Pin SOIC Packages
DESCRIPTION
The X24C01 is a CMOS 1024 bit serial E2PROM, internally organized as 128 x 8. The X24C01 features a serial interface and software protocol allowing operation on a simple two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics, and RR-520 for endurance cycling information for Xicor nonvolatile memories.
PIN CONFIGURATIONS PLASTIC
SOIC
NC
Vee
NC
NC
NC
NC
NC
NC
SCL
Vss
Vss
SDA
0107-1
Vee
NC
SCL
SDA
0107-2
PIN NAMES
NC Vss Vee SDA SCL
No Connect Ground Supply Voltage Serial Data Serial Clock
2-43
X24CO 1, X24CO 11
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias x24co1 ............................... -1 o�c to + a5�C x24co11 .............................. -65�C to+ 135�c
Storage Temperature .................... -65�C to + 150�C Voltage on any Pin with
Respect to Vss ........................... -1.0V to + 7V D.C. Output Current. ................................. 5 mA Lead Temper(lture
(Soldering, 10 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum� Ratings" may cause permanent damage to the device. This is a stress. rating only and the functional operati9n of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X24C01 TA = 0�C to + 70�C, Vee = 3V to 5.5V, unless otherwise specified. X24C01 I TA = -40�C to + 85�C, Vee = 3V to 5.5V, unless otherwise specified. Vee range for the X24C01 and X24C01 I are defined in the Ordering Information table.
Symbol
Parameter
Limits
Min.
Max.
Units
Test Conditions
Ice
lss1<1)
lss2<1)
lu ILO V1L (2) V1H<2> Vol
Vcc Supply Current
1
Vcc Standby Current
100
Vcc Standby Current
50
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
-1.0 Vee xo.7
10 10 Vee xo.3 Vee +o.5 0.4
mA SCL = CMOS Levels @ 100 KHz, SDA = Open, All Other Inputs = GND or Vee - 0.3V
�A SCL = SDA =Vee. All Other Inputs= GND or Vee. Vee= 5V �10%
�A SCL = SDA = Vee. All Other Inputs = GND or Vee. Vee = 3.3V � 10%
�A V1N = GND to Vee
�A VouT = GND to Vee
v v v loL = 2.1 mA
ENDURANCE AND DATA RETENTION
I
Parameter
I Min.
Minimum Endurance
100,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
c11o<3) ,.... '3'
Test Input/Output Capacitance (SDA)
. iI npu-- t v,..a, pac1tance (~ ~CL}'
Max. 8 6
Units pF pF
Conditions V110 = OV
=
Notes: (1) Must perform a stop command prior to measurement.
(2) V1L min. and V1H max. are for reference only and are not tested.
(3) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
Vee xo.1 to Vee xo.9
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
Vee xo.5
Output Load
1 TTL Gate and CL= 100 pF
2-44
X24CO 1, X24CO 11
A.C. CHARACTERISTICS LIMITS
X24C01 TA = 0�C to + 70�C, Vee = 3V to 5.5V, unless otherwise specified. X24C01 I TA = -40�C to + 85�C, Vee = 3V to 5.5V, unless otherwise specified.
Vee range for the X24C01 and X24C01 I are defined in the Ordering Information table.
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
fseL
SCL Clock Frequency
0
100
T1
Noise Suppression Time
Constant at SCL, SDA Inputs
100
tAA
SCL Low to SDA Data Out Valid
0.3
3.5
tsuF
Time the Bus Must Be Free Before a
New Transmission Can Start
4.7
tHD:STA
Start Condition Hold Time
4.0
tLQW
Clock Low Period
4.7
tHIGH
Clock High Period
4.0
tsu:STA
Start Condition Setup Time
4.7
tHD:DAT
Data In Hold Time
0
tsu:DAT tR
Data In Setup Time SDA and SCL Rise Time
250 1
tF
SDA and SCL Fall Time
300
tsu:STO
Stop Condition Setup Time
4.7
toH
Data Out Hold Time
300
Typical Power-Up Timing Symbol tpuR(4) tpuw(4)
Parameter Power-Up to Read Operation Power-Up to Write Operation
Max. 1 5
Bus Timing
Units KHz
ns
�s
�s
�s �s �s �s �s ns �s ns �s ns
Units ms ms
SCL
SDA IN
SDA OUT
0107-3
Note: (4) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
2-45
X24CO 1, X24CO 11
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
Write Cycle Time
5
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C01 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its word address.
Write Cycle Timing
SCL-----
SDA
STOP
CONDITION
START
CONDITION
X24C01
ADDRESS
0107-4
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.
DEVICE OPERATION The X24C01 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C01 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C01 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Notes: (5) Typical values a;e fo; TA = 25�C and nominai suppiy voitage (5V).
(6) twR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
2-46
X24CO 1, X24CO 11
Figure 1: Data Validity
____ SCL
_,{
SDA
/!
u I
I
I
I
I
lx
DATA STABLE DATA CHANGE
Figure 2: Definition of Start and Stop
\~: _____ _
I
0107-5
SCL '--.....1"--.....11:I
SDA--:\.
I
-�.....---.J
\ �/
START BIT
STOP BIT
0107-6
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C01 to place the device in the standby power mode ~fter a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 3: Acknowledge Response From Receiver
The X24C01 will respond with an acknowledge after recognition of a start condition, a seven bit word address and a R/W bit. If a write operation has been selected, the X24C01 will respond with an acknowledge after each byte of data is received.
In the read mode the X24C01 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C01 will continue to transmit data. If an acknowledge is not detected, the X24C01 will terminate further data transmissions. The master must then issue a stop condition to return the X24C01 to the standby power mode and place the device into a known state.
SCL
r�---, rl :
-
h ! \___}r
--
1
\
\
_
_
_}
I
I
r \~ \.__J 8
1 9 }--
:
:
I
,-------y------J DATA
M~ OUTPUT
:
~ - - ,
.
TRANSMITTER
:
---- -
1 I
I
I
I
;
I
:
DATA OUTPUT
:
I
-------i_I __I j-
FROM
RECEIVER
1
I
START
ACKNOWLEDGE
0107-7
2-47
X24CO 1, X24CO 11
WRITE OPERATIONS �Byte Write To initiate a write operation, the master sends a start condition followed by a seven bit word address and a write bit. The X24C01 respohds with an acknowledge, then waits for eight bits of data and then. responds with an acknowledge. The master then terminates the transfer by generating a stop conditiOn, at which time the X24C01 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the X24C01 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 4 for the address, acknowledge and data transfer sequence.
Figure 4: Byte Write
Page Write The most significant five bits of the word address define the page address. The X24C01 is capable of a four byte page write operation. It is initiated in the same manner as the byte write operation, but instead ofterminating the transfer of data after the first data byte, the master can transmit up to three more bytes. After the receipt Of each data byte, the X24C01 will respond with an acknowledge.
After the receipt of each data byte, the two low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than four data bytes prior to generating the stop condition, the address counter will "roll over" and the previously transmitted data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
s
T
S
A
WORD
T
Isl:::::: I I::::::: IEl BUS ACTIVITY SDA LINE
R ADDRESS (n) T
DATA n
0
p
BUS ACTIVITY: M
L RA
A
X24C01 s.
S/C
c
B
Bij,iK
K
0107-8
Figure 5: Page Write
s
T
S
A
W~ .
T
BUS ACTIVITY .R ADDRESS (n)
DATA n
DATA n+1
DATA n+3 0
i A SDA LINE
BUS ACTIVITY:
1:1
:
M
:
:
:
:
: I LR
I
A
:
:
:
:
:
:
:
I I A
:
:
:
:
.
:
:
:
IAr4i).}t
:
: :
: :
A
X24C01 S
S/C
C
C
C
B
BWK
K
K
K
0107-9
2-48
X24C01, X24C011
Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C01 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the word address for a write operation. If the X24C01 is still busy with the write operation no ACK will be returned. If the X24C01 has completed the write operation an ACK will be returned and the controller can then proceed with the next read or write operation.
READ OPERATIONS
Read operations are initiated in the same manner as write operations with exception that the R/W bit of the word address is set to a one. There are two basic read operations: byte read and sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
Byte Read To initiate a read operation, the master sends a start condition followed by a seven bit word address and a read bit. The X24C01 responds with an acknowledge and then transmits the eight bits of data. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 6 for the start, word address, read bit, acknowledge and data transfer sequence.
Figure 6: Byte Read
Flow 1: ACK Polling Sequence
WRITE OPERATION COMPLETED ENTER ACK POLLING
NO NO PROCEED
ISSUE STOP
PROCEED
0107-15
BUS ACTIVITY
soA LINE BUS ACTIVITY:
X24C01
s
T
S
A
WORD
T
R ADDRESS n
0
T
p
I I I EJ Isl : : : : : :
I : : : : : : :
M
L R A.......__ _ _ _ __,
s
S/C
DATA n
B
ByjK
0107-10
2-49
X24CO 1, X24CO 11
Sequential Read Sequential read is initiated in the same manner as the byte read. The first data byte is transmitted as with the byte read mode, however, the master now responds with an acknowledge, � indicating it requires additional data. The X24C01 continues to output data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.
Figure 7: Sequential Read
The data output is sequential, with the data from ad-
dress n followed by the data from n + 1. The address
counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 127) the counter "rolls over" to zero and the X24C01 continues to output data for each acknowledge received. Refer to Figure 7 _for the address, acknowledge and data transfer sequence.
BUS ACTIVITY ADDRESS
s
A
A
A
T
K c
K c
K c
.
0 P
SDA LINE ]11 :: : : : :: 11 :: : :: : : 11 :::::::IC1(1 :::::::I El
BUS ACTIVITY: X24C01
RA
/c
DATA n
WK
DATA n+1
DATA n+2
DATA n+x
0107-11
Figure 8: Typical System Configuration
-- SDA
SCL .I
=...r.
l
MASTER TRANSMITIER/
RECEIVER
....
....
:I
.I
l
SLAVE RECEIVER
....
....
.I
I
J_
SLAVE TRANSMITIER/
RECEIVER
-- _l
_I
I
MASTER TRANSMITTER
4, � Vee
�: > :> ~ PULL-UP RESISTORS
.... =...r.. J
.I
:I
MASTER TRANSMITTER/
RECEIVER
0107-14
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120
100
c;j' c, 80 .....
0z 60 ~
Vl
i..i..i. 40 a::
20
RMIN =-Ye-e M.A-X =2.6 K.O. loL MIN
0 0 20 40 60 80 100 120
BUS CAPACITANCE (pr)
0107-13
SYMBOL TABLE WAVEFORM
xxxxx
~~
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
2-50
X24CO 1, X24CO 11
FUNCTIONAL DIAGRAM (8) Vee - (4) Vss -
(S)SDA--..........-1 START STOP LOGIC
(6) SCL
START CYCLE
H.V. GENERATION TIMING
& CONTROL
PIN
Dour
ACK
0107-12
2-51
NOTES
2-52
PRELIMINARY INFORMATION
2K
Commercial Industrial
X24C02 X24C021
Electrically Erasable PROM
256 x 8 Bit
TYPICAL FEATURES � Low Power CMOS
-Active Current Less Than 1 mA -Standby Current Less Than 50 �A �Internally Organized 256 x 8 � Self Timed Write Cycle -Typical Write Cycle Time of 5 ms � 2 Wire Serial Interface -Bidirectional Data Transfer Protocol � Four Byte Page Write Operation -Minimizes Total Write Time Per Byte � High Reliability -Endurance: 100,000 Cycles Per Byte -Data Retention: 100 Years � New Hardwire - Write Control Function
PIN CONFIGURATIONS
PLASTIC SOIC
Ao
Vee
NC
A1
WC
Ao
A2
SCL
A1
Vss
SDA
NC
A2
0120-12
Yss
NC
DESCRIPTION
The X24C02 is a 2048 bit serial E2PROM, internally organized as one 256 x 8 page. The X24C02 features a serial interface and software protocol allowing operation on a simple two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics, and RR-520 for endurance cycling information for Xicor nonvolatile memories.
SOIC
NC Vee WC NC SCL SDA NC
0120-13
PIN NAMES
Ao-A2 SDA SCL WC
Vss Vee
Address Inputs Serial Data Serial Clock Write Control Ground +5V
2-53
X24C02, X24C021
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X24C02 ............................... -10�C to + 85�C X24C021 .............................. -65�C to + 135�C Storage Temperature .................... -65�C to + 150�C
Voltage on any Pin with
Respect to Vss ........................... -1.0V to +7V
O.C. Output Current .................................. 5 mA Lead Temperature
o (Soldering, 1 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings~� may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions. for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X24C02 TA = 0�C to + 70�C, Vee = 5V � 10%, unless otherwise specified. X24C021 TA= -40�C to +85�C, Vee= 5V �10%, unless otherwise specified. Vee range for the X24C02 and X24C021 are defined in the Ordering Information table.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
Ice
Power Supply Current
1
mA SCL = CMOS Levels @ 100 KHz,
SDA = Open, All Other Inputs= GND
or Vee - 0.3V
159(1)
Standby Current
50
�.A SCL = SDA = V1H.
All Other Inputs = V1L or V1H
lu
Input Leakage Current
10
�.A V1N = GND to Vee
ILO V1L(2) V1H(2) Vol
Output Leakage Current
10
�.A Vour = GND to Vee
Input Low Voltage
-1.0
Vee xo.3
v
Input High Voltage
Vee xo.7 Vee +o.5
v
Output Low Voltage
0.4
v loL = 3 mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
100,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
CAPACITANCE TA = 25�C, f = 1 MHz, Vee = 5V
Symbol
Test
C110(3)
Input/Output Capacitance (SDA)
C1N(3)
Input Capacitance (Ao, A1, A2, SCL)
Max. 8 6
Units pF pF
Conditions
v1/0 = ov
V1N = OV
Notes: (1) Must perform a stop command prior to measurement.
(2) V1L min. and V1H max. are for reference only and are not tested.
(3) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
Vee xo.1 to Vee xo.9
Input Rise and Fall Times
10 ns
Input and Output Timing Reference Levels
Vee xo.5
Output Load
1 TTL Gate and CL= 100 pF
2-54
X24C02, X24C021
A.C. CHARACTERISTICS LIMITS
X24C02 TA = 0�C to + 70�C, Vcc = 5V � 10%, unless otherwise specified. X24C021 TA = -40�C to + 85�C, Vee = 5V � 10%, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
Min.
fscL
SCL Clock Frequency
0
T1
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA tsuF
SCL Low to SDA Data Out Valid
0.3
Time the Bus Must Be Free
Before a New Transmission
4.7
Can Start
tHD:STA
Start Condition Hold Time
4.0
tLQW
Clock Low Period
4.7
tHIGH
Clock High Period
4.0
tsu:STA
Start Condition Setup Time
4.7
tHD:DAT
Data In Hold Time
0
tsu:DAT
Data In Setup Time
250
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
tsu:STO
Stop Condition Setup Time
4.7
toH
Data Out Hold Time
300
Max. 100 100 3.5
1 300
Power-Up Timing(4) Symbol tpuR tpuw
Parameter Power-Up to Read Operation Power-Up to Write Operation
Max. 1 5
Bus Timing
Units KHz ns
�s
�s
�s �s �s �s �s ns �s ns �s ns
Units ms ms
tR
~~-:--1-1~- SCL
SDA - - I - - + - - - --_,,_-=_tS-U:DA-T IN
teuF ) - - -
SDA OUT
0120-1
Note: (4) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
2-55
X24C02, X24C021
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
Write Cycle Time
5
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C02 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Write Cycle Timing
SCL - - - - -
STOP
CONDITION
START
CONDITION
X24C02 ADDRESS
0120-2
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.
Address (Ao, A1, A2) The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to Vss or Vee as appropriate. !f actively driven, they must be driven to Vss or to Vee.
Write Control (WC) The Write Control input controls the ability to write to the device. When WC is LOW (tied to Vss) the X24C02 will be enabled to perform write operations. When WC
is HIGH (tied to Vee) the internal high voltage circuitry will be disabled and all writes will be disabled.
DEVICE OPERATION
The X24C02 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C02 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C02 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Notes: (5) Typical values are for TA = 25�e and nominal supply voltage (5V).
(6) twR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation.
2-56
X24C02, X24C021
Figure 1: Data Validity
SCL -----fV
SDA
I
u I
I
x
DATA STABLE DATA CHANGE
Figure 2: Definition of Start and Stop
\,.: _____ _
0120-15
SCL
SDA ~;I \-....._ _!
\--..,.._1.I I
START BIT
STOP BIT
0120-16
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C02 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 3: Acknowledge Response From Receiver
The X24C02 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C02 will respond with an acknowledge after the receipt of each subsequent eight bit word.
In the read mode the X24C02 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C02 will continue to transmit data. If an acknowledge is not detected, the X24C02 will terminate further data transmissions. The master must then issue a stop condition to return the X24C02 to the standby power mode and place the device into a known state.
I
I
I
SCL FROM ---: 7\
r----\
r-��� I ~: 1
MASTER
: \__J 1 \__J
B
I
9
I
I
I
I
:
:
I
DATA OUTPUT FROM
I
~----J
I
I
I
I
TRANSMITTER
:
---- �
1
DATA OUTPUT
' '
�--------I L_J-
FROM
RECEIVER
1
I
START
ACKNOWLEDGE
0120-3
2-57
X24C02, X24C021
DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave are the device type identifier (see Figure 4). For the X24C02 this is fixed as 1010 [B].
Figure 4: Slave Address
DEVICE TYPE IDENTIFIER
I 1 : 0 : 1 : 0 : A2 : A1 : AO : R/W
DEVICE ADDRESS
0120-4
The next three significant bits address a particular device. A system could have up to eight X24C02 devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs.
The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected.
Following the start condition, the X24C02 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24C02 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C02 will � execute a read or write operation.
WRITE OPERATIONS
Byte Write For a write operation, the X24C02 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X24C02 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by �generating a stop condition, at which time the X24C02 begins the. internal write cycle to the nonvolatile memory.. While the internal write cycle is in progress the X24C02 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
Figure 5: Byte Write
BUS ACTIVITY: lifASTEA
SDA LINE
s
T
s
A
SLAVE
WORD
T
R ADDRESS
ADDRESS
DATA
0
ITTllD 1:::::::11:::::::1R-
BUS ACTIVITY: X24C02
A
A
A
c
c
c
K
K
K
0120-5
Figure 6: Page Write
I BUS ACTIVITY' MASTER
SDA LINE
BUS ACTIVITY: X24C02
s
T
S
A
SLAVE
T
R
ADDRESS
WORD ADDRESS (n)
DATA n
DATA n � 1
DATA n + 15
0
Blil o , r: :::::: ::::: 1 r-2~ T ------ ------ ------ ------
-..--- p
1: : : : : : : 11 : : : : : : :
1
1 G
A
A
A
A
A
c
c
c
c
c
K
K
K
�K
K
NOTE: In this example n = xxxx 0000(8); x = 1 or 0
0120-6
2-58
X24C02, X24C021
Page Write The X24C02 is capable of a four byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. After the receipt of each word, the X24C02 will respond with an acknowledge.
After the receipt of each word, the two low order address bits are internally incremented by one. The high order six bits of the address remain constant. If the master should transmit more than four words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Acknowledge Polling The disabling of the inputs, during the internal write operation, can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C02 is still busy with the write operation no ACK will be returned. If the X24C02 has completed the write operation an ACK will be returned and the master can then proceed with the next read or write operation.
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
Flow 1: ACK Polling Sequence
WRITE OPERATION COMPLETED ENTER ACK POLLING
PROCEED
0120-17
2-59
X24C02, X24C021
Current Address Read Internally the X24C02 contains an address counter that maintains the address of the last word .accessed, incremented by one. Therefore, if the last access (either a read or write) was to address.n, the next read opera-
tion would access data from address n + 1. Upon re-
ceipt of the slave address with the R/W bit set to one, the X24C02 issues an acknowledge and transmits the eight bit word during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issu� ing the slave address with the R/W bitset to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C02 and then by the eight bit word. The master terminates this transmission by.issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer _to Figure 8 for the address, acknowledge and data transfer sequence.
Figure 7: Current Address Read
BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24C02
s
T
s
A
SLAVE
T
T - - - - R
ADDRESS
0 p
A----
C
DATA
K
0120-7
Figure 8: Random Read
BUS ACTIVITY: MASTER
SDALINE
BUS ACTIVITY: X24C02
s
s
T
T
s
A
SLAVE
R
ADDRESS
T ------
WORD ADDRESS n
------
T - - A
SLAVE
R
ADDRESS
T 0 p
A
A----
c
~
DATA n
K
0120-8
2-60
X24C02, X24C021
Sequential Read Sequential Read can be initiated as either a current address read or random access read. The first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C02 continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.
The data output is sequential, with the data from ad-
dress n followed by the data from n + 1. The address
counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter "rolls over" to O and the X24C02 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
Figure 9: Sequential Read
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24C02
SLAVE
A
A
A
ADDRESS
C
C
C
---
K
K
K
~
=J l rj) I : : : : : : : 11 : : : : : : : 11 '. '. '. '. '. : : I
cA - - - - - DATA n K
-----DATA n + 1
-----DATA n + 2
s
T
0
P
G I : : : : : : : I
------DATA n + x
0120-9
Figure 10: Typical System Configuration
Vee
- - - - - - . . J SDA---~------+------------.......
SCL-.----+----<P-----+-~~--4-----e----+-------.J_~
MASTER TRANSMITTER/
RECEIVER
SLAVE RECEIVER
MASTER TRANSMITTER/
RECEIVER
0120-10
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120
100
~
~
80
l.JJ
0z 60 ~
(/)
Vi 40
l.JJ
a::
20
= = R
Vee MAX 1.8 K.n
MIN loL MIN
0 0 20 40 60 80 100 120
BUS CAPACITANCE (pr)
0120-14
SYMBOL TABLE WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
2-61
X24C02, X24C021
FUNCTIONAL DIAGRAM
(8) Vee _ _ (4) Vss _ _
START STOP LOGIC
(6) SCL ----1'---t (3) Az - - - - -
A.,-------- (2) A, - - - - - - -
(1)
DouT ACK
START CYCLE
H.V. GENERATION TIMING
I CONTROL
CONTROL LOGIC
INC
PIN 0120-11
2-62
JliCI'
4K
Commercial Industrial
X24C04 X24C041
512 x 8 Bit
Electrically Erasable PROM
TYPICAL FEATURES � Low Power CMOS
-Active Current Less Than 1 mA -Standby Current Less Than 50 �A �Internally Organized as Two Pages -Each 256 x 8 � 2 Wire Serial Interface -Bidirectional Data Transfer Protocol � Sixteen Byte Page Write Mode -Minimizes Total Write Time Per Byte � Self Timed Write Cycle -Typical Write Cycle Time of 5 ms � High Reliability -Endurance: 100,000 Cycles Per Byte -Data Retention: 100 Years � 8 Pin Mini-DIP and 14 Pin SOIC Packages
DESCRIPTION
The X24C04 is a CMOS 4096 bit serial E2PROM, internally organized as two 256 x 8 memory banks. The X24C04 features a serial interface and software protocol allowing operation on a simple two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics and RR-520 for endurance cycling information for Xicor nonvolatile memories.
PIN CONFIGURATIONS
PLASTIC CERDIP
Ao
Vee
A1
TEST
A2
SCL
Yss
SDA
0046-1
SOIC
PIN NAMES
Ao-A2 Address Inputs
NC
NC
SDA Serial Data
Ao
Vee
SCL
Serial Clock
A1
TEST
TEST Hold at Vss
NC
NC
Vss
Ground
A2
SCL
Vee
Supply Voltage
Yss
SDA
NC
No Connect
NC
NC
0046-15
2-63
X24C04;��X24C041
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X24C04 ............................... -10�C to + 85�C X24C041 .............................. - 65�C to + 135�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Vss ........................... -1.0V to +7V
D.C. Output Current ..................................5 mA Lead Temperature
(Soldering, 1OSeconds) ........................... 300�C
*COMMENT
Stresses above those� listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X24C04 TA = 0�C to + 70�C, Vee = 3V to 5.5V, unless otherwise specified. X24C041 TA = -40�C to +85�C, Vee = 3V to 5.5V, unless otherwise specified. Vee range for the X24C04 and X24C041 are defined in the Ordering Information table.
Symbol
Ice
lss1(1) lss2<1)
lu ILO V1L(2) V1H(2) Vol
Parameter
Vcc Supply Current
Vcc Standby Current Vcc Standby Current
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
Limits
Min.
Max.
1
150
50
-1.0 Vee xo.7
10 10 Vee xo.3 Vee +0.5 0.4
Units
mA
�A
�A
�A �A
v v v
Test Conditions
SCL = CMOS Levels @ 100 KHz, SDA =Open, All Other Inputs= GND or Vee - 0.3V
SCL = SDA = Vcc. All Other
Inputs= GND or Vee. Vee= 5V � 10%
SCL = SDA = Vcc. All Other
Inputs = GND or Vee. Vee = 3.3V � 10%
V1N = GND to Vee VouT = GND to Vee
loL = 3 mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Minimum Endurance
100,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
CAPACITANCE TA = 25�C, f = 1.0 MHz, Vee = 5V
Symbol C11d3l C1N(3)
Test Input/Output Capacitance (SOA) Input Capacitance (Ao, A1, A2, SCL)
Max. 8 6
Units pF pF
Conditions V110 = OV V1N = OV
Notes: (1) Must perform a stop command prior to measurement.
(2) V1L min. and V1H max. are for reference only and are not tested.
(3) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
Vee xo.1 to Vee xo.9
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
Vee xo.5
Output Load
1 TTL Gate and CL= 100 pF
2-64
X24C04, X24C041
A.C. CHARACTERISTICS LIMITS
X24C04 TA = 0�C to + 70�C, Vee = 3V to 6V, unless otherwise specified. X24C041 TA = -40�C to + 85�C, Vee = 3V to 6V, unless otherwise specified.
Vee range for the X24C04 and X24C041 are defined in the Ordering Information table.
Read & Write Cycle Limits
Symbol
Parameter
fseL
SCL Clock Frequency
T1
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out Valid
tsuF
Time the Bus Must Be Free Before a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOw
Clock Low Period
tHIGH
Clock High Period
tsu:STA
Start Condition Setup Time (for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
tsu:DAT
Data In Setup Time
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
tsu:STO
Stop Condition Setup Time
toH
Data Out Hold Time
Min. 0
0.3 4.7 4.0 4.7 4.0 4.7 0 250
4.7 300
Max. 100 100 3.5
1 300
Power-Up Timing(4) Symbol tpuR tpuw
Parameter Power-Up to Read Operation Power-Up to Write Operation
Max. 1 5
Bus Timing
Units
KHz
ns
�s �s �s �s �s �s �s ns �s ns �s ns
Units ms ms
tR
SCL ~--1�~---~---�-----=-ts-U:DA-T~~r~
SDA IN
---1- teur )----
SDA OUT
0046-3
Note: (4) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
2-65
X24C04, X24C041
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
Write Cycle Time
5
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C04 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Write Cycle Timing
SCL-----
SDA
STOP CONDITION
START CONDITION
X24C04 ADDRESS
0046-4
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet.
Address (Ao) Ao is unused by the X24C04, however, it must be tied to Vss to insure proper device operation.
Address (A1, A2) The Address inputs are used to set the least significant two bits of the six bit slave address. These inputs can be used static or actively driven. If used statically they
must be tied to Vss or Vcc as appropriate. If driven they must be driven to Vcc or to VSS�
DEVICE OPERATION
The X24C04 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C04 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C04 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Notes: (5) Typical values are for TA = 25�C and nominal supply voltage (5V).
(6) twR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
2-66
X24C04, X24C041
Figure 1: Data Validity
____ SCL
.,(
SDA
/'
u I x:
DATA STABLE DATA CHANGE
Figure 2: Definition of Start and Stop
______ I
\,..:
0046-5
SCL SDA - - : \ ._ _ _ _/
\_-..,.-!I
START BIT
STOP BIT
0046-6
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 3: Acknowledge Response From Receiver
The X24C04 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C04 will respond with an acknowledge after the receipt of each subsequent eight bit word.
In the read mode the X24C04 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C04 will continue to transmit data. If an acknowledge is not detected, the X24C04 will terminate further data transmissions. The master must then issue a stop condition to return the X24C04 to the standby power mode and place the device into a known state.
I
I
I
i \__} SCL FROM --t! -\
MASTER
,---,_
r��- I -~ :1
1 \__}
8
I
9
I
I
I
I
DATA OUTPUT FROM
:
I
~---�J
:
I
1 I
I 1
TRANSMITTER
:
DATA OUTPUT
' I
�-----�-----L1I J--
FROM
RECEIVER
1
I
START
ACKNOWLEDGE
0046-7
2-67
X24C04, X24C041
DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C04 this is fixed as 1010[8].
Figure 4: Slave Address
DEVICE TYPE IDENTIFIER
DEVICE BANK ADDRESS SELECT
I 1 : 0 : A2 : A1 : AO : R/W
DEVICE ADDRESS
0046-8
The next two significant bits address a particular device. A system could have up to four X24C04 devices on the bus (see Figure 10). The four addresses are defined by the state of the A1 and A2 inputs.
The next bit of the slave address field (bit 1) is the bank select bit. It is used by the host to toggle between the two 256 x 8 banks of memory. This is, in effect the most significant bit for the word address.
The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected.
Following the start condition, the X24C04 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A1 and A2 inputs). Upon a correct compare the X24C04 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C04 will execute a read or write operation.
WRITE OPERATIONS
Byte Write For a write operation, the X24C04 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X24C04 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C04 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C04 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
Figure 5: Byte Write
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24C04
s
T
s
A
SLAVE
WORD
T
R ADDRESS
ADDRESS
DATA
0
I::::: :: T --"---._
8lJl CJ
11::::::: Irpr
A
A
A
c
c
c
K
K
K
0046-9
Figure 6: Page Write
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24C04
s
T
S
A
SLAVE
T
R
ADDRESS
WORDADDRESS(n)
DATAn
DATAn+1
DATAn+15
0
ihn CJ-, ES 1:::::::1 F::::l Q'[:'.9 Fl
A
A
A
A
A
c
c
c
' c
c
K
K
K
K
K
NOTE: In this example n = XXXX 0000(8); X = 1 or O
0046-10
2-68
X24C04, X24C041
Page Write The X24C04 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the X24C04 will respond with an acknowledge.
After the receipt of each word, the four low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than sixteen words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C04 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C04 is still busy with the write operation no ACK will be returned. If the X24C04 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. Refer to Flow 1.
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
Flow 1: ACK Polling Sequence
WRITE OPERATION COMPLETED ENTER ACK POLLING
PROCEED
0046-17
2-69
X24C04, X24C041
Current Address Read Internally the X24C04 contains an address counter that maintains the address of the last word accessed, incre-, mented by one. Therefore, if. the last access� (either a read or write) was to address n, the next read opera-
tion would access data from address n + 1. Upon re-
ceipt of the slave address with R/W set to one, the X24C04 issues an acknowledge and transmits the eight bit word. The read operation is terminated py the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. Af~ ter the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C04 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Figure 7: Current Address Read
BUS ACTIVITY: MASTER SDALINE BUS ACTIVITY: X24C04
s
T
s
A
SLAVE
T
T R A_ DDRES.S -
0 p
A--
C
DATA
K
0046-11
Figure 8: Random Read
BUS ACTIVITY: MASTER
SDA LINE
BUS ACnYITY: Xl4C04
SLAVE
WORD ADDRESS n
A
c
K
SLAVE ADDRESS
DATAn
0046-12
2-70
X24C04, X24C041
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C04 continues to output data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.
The data output is sequential, with the data from ad-
dress n followed by the data from n + 1. The address
counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 511), the counter "rolls over" to address O and the X24C04 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
Figure 9: Sequential Read
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24C04
SLAVE
A
A
A
~
ADDRESS
C
C
C
O
=Jl I :: :: ::: I :::: : ::I G -
I~ K
K
K
11 : : : : : : : 11 : : : : : : :
P
A--.._.
.
---.._..
..._,.--
~
DATAn
DATAn+l
DATAn+2
DATAn+x
0046-13
Figure 10: Typical System Configuration
Yee
SDA ~~~-.~~~~~-+~~~~----+-~-------------+----------------..,...J scL-....-------+---~~~----+---~~--------+-----.----------1---------------.J__J
PULL-UP RESISTORS
MASTER TRANSMITTER/
RECEIVER
SLAVE RECEIVER
0046-14
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
Vee MAX
100
RMIN = loL MIN = 1.8 K.!l
.~:=, 80
I.LI
~ 60 ~
(/) ~ 401----++--+-~-+-~-l-----l~-l
0::
20
0 ------ -0 20 40 60 80 100 120
BUS CAPACITANCE (pr)
0046-16
SYMBOL TABLE WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
2-71
X24C04, X24C041
FUNCTIONAL DIAGRAM
(8) Vee _ _ (4) Vss - -
START CYCLE
(5) SDA------
START STOP LOGIC
(6) SCL - - - - + - -
SLAVE ADDRESS REGISTER
+COMPARATOR
(31 A 2 --+---~ (2) A, - - - - - -
(1) Ao - - - - - -
CONTROL LOGIC
LOAD
INC
H.V. GENERATION TIMING
A CONTROL
PIN
Dour ACK
0046-2
2-72
16K
Commercial Industrial
X24C16 X24C161
Electrically Erasable PROM
2048 x 8 Bit
TYPICAL FEATURES � Low Power CMOS
-Active Current Less Than 1 mA -Standby Current Less Than 50 �A � Internally Organized as Eight Pages -Each 256 x 8 � 2 Wire Serial Interface � Bidirectional Data Transfer Protocol � Sixteen Byte Page Write Mode -Minimizes Total Write Time Per Byte � Self Timed Write Cycle -Typical Write Cycle Time of 5 ms � High Reliability -Endurance: 10,000 Cycles Per Byte -Data Retention: 100 Years � 8 Pin Mini-DIP and 14 Pin SOIC Packages
DESCRIPTION
The X24C16 is a CMOS 16,384 bit serial E2PROM, internally organized as eight 256 x 8 memory banks. The X24C16 features a serial interface and software protocol allowing operation on a simple two wire bus.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics, and RR-520 for endurance cycling information for Xicor nonvolatile memories.
PIN CONFIGURATIONS
PLASTIC CERDIP
Ao
Vee
A1
TEST
A2
SCL
Vss
SDA
0038-1
SOIC
NC
NC
Ao
Vee
A1
TEST
NC
NC
A2
SCL
Yss
SDA
NC
NC
0038-15
PIN NAMES
Ao-A2 SDA SCL
TEST
Vss
Vee
NC
Address Inputs Serial Data Serial Clock Hold at Vss Ground Supply Voltage No Connect
2-73
X24C 16~. X24C 161
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias
x24c1 s ............................... -1 o�c to + as�c x24c161 .............................. - ss�c to + 13s�c Storage Temperature ............... : ..... - 65�C to + 150�C
Voltage on any Pin with
Respect to Vss ........................... -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a str.ess rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X24C16 TA = 0�C to + 70�C, Vee = 3V to 5.5V, unless otherwise specified. X24C161 TA= -40�C to +85�C, Vee= 3V to 5.5V, unless otherwise specified. Vee range for the X24C16 and X24C161 are defined in the Ordering Information table.
Symbol
Parameter
Limits
Min.
Max.
Units
Test Conditions
Ice
Vcc Supply Current
lss1(1) Vcc Standby Current
1
mA SCL = CMOS Levels @ 100 KHz,
SDA =Open, All Other Inputs= GND
or Vee - 0.3V
150
�A SCL = SDA =Vee, All Other
Inputs = GND or Vee, Vee = 5V � 10%
lss2(1) Vcc Standby Current
50
�A SCL = SDA = Vcc, All Other
Inputs= GND or Vee, Vee= 3.3V � 10%
lu
Input Leakage Current
10
�A V1N = GND to Vee
ILO V1L(2) V1H(2) Vol
Output Leakage Current
10
�A VouT = GND to Vee
Input Low Voltage
-1.0
Vee xo.3
v
Input High Voltage
v Vee xo.7 Vee +o.5
Output Low Voltage
0.4
v loL = 3 mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Minimum Endurance
10,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol C11o(3)
Test Input/Output Capacitance (SDA)
C1N(3)
Input Capacitance (Ao, A1, A2, SCL)
Max. 8 6
Units pF pF
Conditions V1/0 = OV V1N = OV
Notes: (1) Must perform a stop command prior to measurement.
(2) V1L min. and V1H max. are for reference only and are not 100% tested.
(3) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
Vee xo.1 to Vee xo.9
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
Vee xo.5
Output Load
1 TTL Gate and CL= 100 pF
2-74
X24C16, X24C161
A.C. CHARACTERISTICS LIMITS X24C16 TA= 0�C to +70�C, Vee= 3V to 5.5V, unless otherwise specified. X24C161 TA = - 40�C to + 85�C, Vcc = 3V to 5.5V, unless otherwise specified. Vee range for the X24C16 and X24C161 are defined in the Ordering Information table.
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
fscL T1
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
0
100
100
tAA tsuF
SCL Low to SDA Data Out Valid
0.3
3.5
Time the Bus Must Be Free Before a
4.7
New Transmission Can Start
tHD:STA
Start Condition Hold Time
4.0
tLOw
Clock Low Period
4.7
tHIGH
Clock High Period
4.0
tsu:STA
Start Condition Setup Time
4.7
(for a Repeated Start Condition)
tHD:DAT tsu:DAT tR tF tsu:STO toH
Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
0 250
1 300 4.7 300
Power-Up Timing(4) Symbol tpuR tpuw
Parameter Power-Up to Read Operation Power-Up to Write Operation
Max. 1 5
Units KHz ns
�s �s
�s �s �s �s
�s ns �s ns �s ns
Units ms ms
Bus Timing
tR
~~:-]--t-1~- SCL
SDA - - i � - - - + - - - - - .--�--=-ts-U:DA-T IN
teur _}----
SDA OUT
0038-3
Note: (4) tpuR and tpuw are the delays required from the time Vee is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
2-75
X24C 16, X24C 161
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
Write Cycle Time
5
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C16 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Write Cycle Timing
SCL-----
SDA ----
STOP CONDITION
START CONDITION
X24C16 ADDRESS
0038-4
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet.
Address (Ao, A1, A2) The Ao, A1 and A2 inputs are unused by the X24C16, however, they must be tied to Vss to insure proper device operation.
DEVICE OPERATION The X24C16 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C16 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C16 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Notes: (5) Typical values are for TA = 25�C and nominal supply voltage (5V).
(6) twR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
2-76
X24C16, X24C161
Figure 1: Data Validity
I
I
SCL ~---~~------~
SDA
/'
: x:
DATA STABLE DATA CHANGE
Figure 2: Definition of Start and Stop
'"": _____ _
0038-5
SCL
- - SDA~
I
-.....
, _ _......,!
START BIT
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 3: Acknowledge Response From Receiver
STOP BIT
0038-6
The X24C16 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C16 will respond with an acknowledge after the receipt of each subsequent eight bit word.
In the read mode the X24C16 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C16 will continue to transmit data. If an acknowledge is not detected, the X24C16 will terminate further data transmissions. The master must then issue a stop condition to return the X24C16 to the standby power mode and place the device into a known state.
----\____/.\_lJ.l__' :
SMCALSTFERROM
TLf.\_[' :
I
:
I
I I
:
1
8
9
I
I
I
I
- - - - - D~A~TJA:UT ~-: ---J~---,�'I
TRANSMITTER
!
----- ----:
DATA OUTPUT FROM
RECEIVER
START
---------LI _J.---
1
!
ACKNOWLEDGE
0038-7
2-77
X24C 16, X24C 161
DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C16 this is fixed as 1010[8].
Figure 4: Slave Address
DEVICE TYPE IDENTIFIER
I 0 : A2 : A1 : AO : R/W
BANK
SELECT
0038-8
The next three bits of the slave address field are the page select bits. They are used by the master device to select which of the eight 256 x 8 banks of memory are to be accessed. These bits are, in effect, the three most significant bits of the word address. It should be noted, the protocol limits the size of memory to eight pages of 256 words; therefore, the protocol can support only one X24C16 per system.
The last bit of the slave address defines the operation to be performed. When set to one a read operation is
Figure 5: Byte Write
selected, when set to zero a write operation is selected.
Following the start condition, the X24C16 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct compare the X24C16 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C16 will execute a read or write operation.
WRITE OPERATIONS
Byte Write For a write operation, the X24C16 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 256 words in the selected page of memory. Upon receipt of the word address the X24C16 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C16 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C16 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
BUS ACTIVITY: MASTER
SDA LINE
s
T
s
A SLAVE
WORD
T
TR _A_ DD..R_E_S_S _
ADDRESS
DATA
0
[31Jl Cl
I:::::::
1
1
:
:
:
:
:
:
:
I
p
fi
f
BUS ACnVITY: X24C18
A
A
A
c
c
c
K
K
K
0038-9
2-78
X24C16, X24C161
Page Write The X24C16 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to fifteen more words. After the receipt of each word, the X24C16 will respond with an acknowledge.
After the receipt of each word, the four low order address bits are internally incremented by one. The high order seven bits of the word address remain constant. If the master should transmit more than sixteen words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C16 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C16 is still busy with the write operation no ACK will be returned. If the X24C16 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. Refer to Flow 1.
Figure 6: Page Write
Flow 1: ACK Polling Sequence
WRITE OPERATION COMPLETED ENTER ACK POLLING
PROCEED
0038-17
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24CUS
s
T
S
A
SLAVE
T
R
ADDRESS
WORDADDRESS(n)
DATAn
DATAn+1
DATAn+15
0
0lJl CJ I : : : : : : : I I : : : : : : : I :::::I r1~ [P] T ---�--- ..-�--.. ..-�--..... . . - � - . .
I
11 : : : : : : :
~...--�--... p
A
A
A
A
A
c
c
c
c
c
K
K
K
K
K
NOTE: In this example n = xxxx 0000(8); x = 1 or o
0038-10
2-79
X24C 16, X24C 161
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
Current Address Read Internally the X24C16 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read opera-
tion would access data from address n + 1. Upon re-
ceipt of the slave address with R/W set to one, the X24C16 issues an acknowledge and transmits the eight
bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for. the sequence of address, acknowledge and data transfer.
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C16 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Figure 7: Current Address Read
BUS ACTIVITY: MASTER
SDALINE
BUS ACTIVITY: X24C18
s
T
s
T - - A
SLAVE
R ADDRESS
T 0 p
A--
C
DATA
K
0036-11
Figure 8: Random Read
BUS ACTIVITY: MASTER
SDA LINE
IRISACTIVITY:
Xl4C1e
SLAVE
WORD ADDRESS n
A
c
K
SLAVE ADDRESS
DATAn
0036-12
2-80
X24C16, X24C161
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C16 continues to output data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.
Figure 9: Sequential Read
The data output is sequential, with the data from ad-
dress n followed by the data from n + 1. The address
counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 2047), the counter "rolls over" to O and the X24C16 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24C19
SLAVE
A
A
A
ADDRESS
C
C
C
=Jl Cl ---
K
K
K
I : : : : : : : 11 : : : : : : : 11 : : : : : : : I
A - - ... - - - . . _..-----~
~
DATA n
DATA n+1
DATA n+2
~
O
P
G I : : : : : : : I
~
DATA n+x
0038-13
Figure 10: Typical System Configuration
Vee
SDA ~--~.....-~~~~~...-~~~~~---~~~~~+-~~~~~-.....J SCL....,..~~--t~--p-~~-+~-~~~~-+-~--~---'--------l...._j
PULL-UP RESISTORS
MASTER TRANSMITTERr
RECEIVER
SLAVE RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/
RECEIVER
0038-14
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120
100
c~. 80
LL.I
(.)
z
60
~
Vl
.V....i. 40 a:::
20
= = R
Vee MAX 1.8 K.O.
MIN loL MIN
0 0 20 40 60 80 100 120
BUS CAPACITANCE (pf)
0038-16
SYMBOL TABLE WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
2-81
X24C 16, X24C 161
FUNCTIONAL DIAGRAM
(8) Vee _ _ (4) Vss - -
START CYCLE
(5) SDA---------1
START STOP LOGIC
(6) SCL _ _ _ _ ___
SLAVE ADDRESS REGISTER
+COMPARATOR
(3) (2)
A2 A,
----++----------
(1) Ao - - - - - -
CONTROL LOGIC
LOAD
INC
H.V. GENERATION TIMING
&CONTROL
PIN 0 our ACK
DATA REGISTER 0038-2
2-82
X2804A, X2804AI ........................ . X28168, X2816BI ........................ . X2816C, X2816CI ........................ . X2864A, X2864AI . . . . . . . . . . . . . . . . . . . . . . . . . X28648, X286481 . . . . . . . . . . . . . . . . . . . . . . . . . X2864H, X2864HI ........................ . X28C64, X28C641 ....................... .. X28256, X282561 . . . . . . . . . . . . . . . . . . . . . . . . . X28C256, X28C2561. . . . . . . . . . . . . . . . . . . . . . . X28C512, X28C5121....................... X28C010,X28C0101.......................
3-1 3-9 3-19 3-29 3-39 3-47 3-55 3-69 3-83 3-97 3-111
Jico,
INOVRAM* Data Sheets
Serial Products Data Sheets E2PROM Data Sheets
'ca,
4K
Commercial Industrial
X2804A X2804AI
Electrically Erasable PROM
512 x 8 Bit
FEATURES � Simple Byte Write Operation
-Internally Latched Address and Data -Self Timed Write -Noise Protected WE Pin � Reliable N-Channel Floating Gate MOS Technology � Single 5V Supply � High Reliability -Endurance: 10,000 Writes Per Byte -Data Retention: 100 Years � Byte Write Time: 10 ms Max. � Fast Access Time: 250 ns Max. � Low Power Dissipation -Active Current: 80 mA Max. -Standby Current: 50 mA Max.
PIN CONFIGURATION
A,
Vee
A,
A,
A,
NC
A,
WE
A,
OE
A,
NC
A,
C'E
Ao
110,
110.
110,
llO,
110,
110,
110,
Vss
110,
0044-1
PIN NAMES
Ao-As l/Oo-1/07 WE CE OE Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
DESCRIPTION
The Xicor X2804A is a 512 x 8 E2PROM, fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories. The X2804A is compatible with the JEDEC approved pinout for byte-wide memories.
Xicor E2PROMs are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 10,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
FUNCTIONAL DIAGRAM
Ao-As ADDRESS
INPUTS
x
BUFFERS LATCHES
ANO DECODER
y BUFFERS LATCHES
ANO DECODER
VccO-VssO--
CONTROL LOGIC
4,096-BIT
E2PROM
ARRAY
110 BUFFERS ANO LATCHES
tt ttttt
1100 -110, DATA INPUTS/OUTPUTS
0044-2
3-1
X2804A,.X28'04AI
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias�
X2804A ............................... -10�C to + 85�C � X2804AI ..........� ... ~ ................ -65�e. to + 135�e Storage Temperature ... '. ................ - 65�e to + 1so0 e
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA
o Lead Ter:nperature (Soldering, 1 Seconds) ........................... 300�e
*COMMENT
Stresses above those listed under� "Absolute Maximum Ratings~� may. cause permanent damage to the device. This is a stress r~ting only and the functiol'.lal operation of the device .at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X2804A TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X2804AI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2804A Limits
Min.
Max.
X2804AI Limits
Min.
Max.
Units
Ice
Vee Cu.rrent (Active)
80
100
mA
lss
Vcc Current (Standby)
50
60
mA
lu I Lo V1L(2) V1H(2)
Vol VoH
Input Leakage Current
10
10
�A
Output Leakage Current
10
10
�A
Input Low Voltage
-1.0'
0.8
-1.0
0.8
v
Input High Voltage
2.0 Vee +0.5 2.2 Vee +1.0
v
Output Low Voltage
0.4
0.4
v
Output High Voltage
2.4
2.4
v
Test Conditions
CE= OE= V1L All I/O's= Open Other Inputs = Vee CE = V1H1 OE = V1L All I/O's. = Open Other Inputs= Vee V1N = GND to Vee VouT = GND to Vee
loL = 2.1 mA loH = -400 �A
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
C110(1)
Input/Output Capacitance
C1N(1)
Input Capacitance
Max. 10 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Notes: (1) This parameter is periodically sampled and not 100% tested. (2) V1L min. and V1H max. are for reference only and are not tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour D1N HighZ
-
Power Active Active Standby
-
3-2
X2804A, X2804AI
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
10,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS
X2804A TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X2804AI TA = - 40�C to + 85�C, Vcc = + 5V � 10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
tRc tcE tAA toE tLz tHz(3) toLz(3) t0Hz(3) toH(3)
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change
X2804A�25 X2804Al�25 Min. Max. 250
250 250 120 10 10 100 50 10 100 20
X2804A X2804AI Min. Max. 300
300 300 120 10 10 100 50 10 100 20
X2804A-35 X2804Al�35 Min. Max. 350
350 350 135 10 10 100 50 10 100 20
X2804A�45 X2804Al�45 Min. Max. 450
450 450 150 10 10 100 50 10 100 20
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
ADDRESS
1-4------tRc-------I
-4---loE--->
DATAl/O
HIGHZ
~~---+---+----ii:
.,__tAA----+-
0044-3
Note: (3) tHz max. and toHZ max. are measured from the point when CE or OE return high (whichever occurs first) to the time when
the outputs are no longer driven. tHz min., toHz min.; tLz min. and toLZ min. are periodically sampled and are not 100% tested.
3-3
X2804A, X2804AI
Write Cycle Limits
Symbol
Parameter
twc(7) tAs tAH tcs tcH tcw t o ES t o EH twp twpH tov tos toH
Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time Chip Enable to End of Write Input Output Enable Setup Time Output Enable Hold Time Write Pulse Width Write Control Recovery Data Valid Time Data Setup Time Data Hold Time
X2804A-25 X2804Al�25 Min. Max.
10 10 120 0 0 150 10 10 150 50
1 120 15
X2804A X2804AI Min. Max.
10 10 120 0 0 150 10 10 150 50
1 135 15
X2804A�35 X2804Al�35 Min. Max.
10 10 150 0 0 175 10 10 175 50
1 175 20
X2804A-45 X2804Al�45 Min. Max.
10 10 150 0 0 230 10 10 230 50
1 230 30
Units
ms ns ns ns ns ns ns ns ns ns �s ns ns
WE Controlled Write Cycle
ADDRESS
DATAOUT ,)()()()()~-----------------------------------------H-I-G-H--Z----------------------------------------------
0044-4
Note: (7) twc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
3-4
X2804A, X2804AI
CE Controlled Write Cycle ADDRESS
Wi
..-toES_.
~�os--+ .-1DH HIGHZ
fS:SS7
;
0044-5
3-5
X2804A, X2804AI
PIN DESCRIPTIONS Addresses (Ao-As) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1107) Data is written to or read from the X2804A through the 110 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X2804A.
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2804A supports both
a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms. In order to take advantage of the typical write time as opposed to the maximum specified time, the user can poll the X2804A. The 1/0 pins are placed in the high impedance state during the internal programming cycle. Once the internal cycle is complete, the X2804A may be accessed without any limitations. Therefore, the host can poll an address with known data (preferably with zeroes), as soon as a compare is true, the X2804A is ready for another write cycle.
WRITE PROTECTION There are three features that protect the nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse typically less than 20 ns will not initiate a write cycle.
�Vee Sense-All functions are inhibited when Vee is ::;;: 3V, typically.
� Write Inhibit-Holding either OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent writes.
3-6
X2804A, X2804AI
SYSTEM CONSIDERATIONS
Because the X2804A is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X2804A has two power modes, standby and active, proper decoupling of the memory array is
of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vee and GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
SYMBOL TABLE
WAVEFORM
xxxxx
~�K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
3-7
X2804A, X2804AI
Normalized Active Supply Current vs. Ambient Temperature
Normalized Standby Supply Current vs. Ambient Temperature
~ 1.2
0
LrJ
N
:::J
1.0
<
::E
0::
0z 0.8
0.6 '-------'---------'
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0044-6
Normalized Access Time vs. Ambient Temperature
m 1.2
_(/)
0
LrJ
N
<:::J
1.0
::E
0::
0z 0.8
0.6 '----------'---------'
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0044-7
~ 1.2
0 LrJ N :::J
<
::E
0::
0 z
0.6 '---------'--------'
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0044-8
3-8
Jicom:
16K
Commercial Industrial
X2816B X2816BI
Electrically Erasable PROM
2048 x 8 Bit
FEATURES � 250 ns Access Time � High Performance Advanced NMOS
Technology � Fast Write Cycle Times
-16-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 640 ms
Typical -Effective Byte Write Cycle Time of 300 �s
Typical � DATA Polling
-Allows User to Minimize Write Cycle Time � High Reliability
-Endurance: 10,000 Writes Per Byte -Data Retention: 100 Years � Simple Byte and Page Write -Single TTL Level WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout
PIN CONFIGURATIONS
DESCRIPTION The Xicor X28168 is a 2K x 8 E2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor programmable nonvolatile memories it is a 5V only device. The X28168 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs, ROMs and EPROMs.
The X28168 supports a 16-byte page write operation, typically providing a 300 �sfbyte write cycle, enabling the entire memory to be written in less than 640 ms. The X2816B also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle.
Xicor E2PROMs are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 10,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
FUNCTIONAL DIAGRAM
0071-1
PIN NAMES
Ao-A10 1/0o-1/07 WE CE OE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
0071-2
A0-A,0 ADDRESS
INPUTS
x
BUFFERS LATCHES
ANO DECODER
16.384-BIT E'PROM ARRAY
y
BUFFERS LATCHES
ANO DECODER
110 BUFFERS ANO LATCHES
CONTROL LOGIC
1100 -110, DATA INPUTS/OUTPUTS
0071-3
3-9
X2816B, X2816BI
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias X2816B ............................... -10�c to +85�C X281681 .............................. -65�C to + 135�C
Storage Temperature .................... -65�C to + 150�C Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 10 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the op~ erational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X2816B TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X2816BI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
X2816B/X2816B-25 Limits
X2816Bl/X2816Bl-25
Limits
Units Test Conditions
Min. Typ.(1) Max. Min. Typ.(1) Max.
Ice
Vee Current (Active)
80
120
80
140 mA CE= OE= V1L
All I/O's= Open
Other Inputs = Vee
lss
Vcc Current (Standby)
45
60
45
70
mA CE = V1H. OE = VrL
All I/O's = Open
Other Inputs = Vee
lu
Input Leakage Current
10
10
�A VrN = GND to Vee
I Lo
Output Leakage Current
V1L(3) V1H(3) Vol VoH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1.0 2.0
2.4
10
0.8 -1.0 Vee +1.0 2.0
0.4 2.4
10
�A VouT =_�.ND
to Vee. CE= VrH
0.8
v
Vee +1.0 v
0.4
v loL = 2.1 mA �
v loH = -400 �A
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(2)
Power-Up to Read Operation
tpuw<2>
Power-Up to Write Operation
Typ.(1) 1 5
Units ms ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
C110<2>
Input/Output Capacitance
C1N(2)
Input Capacitance
Max. 10 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
OVto 3.0V 10 ns 1.5V
CE
OE
WE
L
L
H
L
H
L
H
x
x
Output Load
1 TTL Gate and CL= 100 pF
x
L
x
x
x
H
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) V1L min. and V1H max. are for reference only and are not tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour DrN HighZ
-
Power Active Active Standby
-
3-10
X2816B, X2816BI
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
10,000
Data Retention
100
Max.
Units Cycles/ Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS
X2816B TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X2816BI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits Symbol
Parameter
tRc tcE tAA toE tLz(4) tHz(4) toLz(4) toHz(4) toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change
X2816B-25 X2816Bl-25
Min.
Max.
250
250
250
100
10
10
60
10
10
60
10
X2816B X2816BI
Min.
Max.
300
300
300
100
10
10
80
10
10
80
10
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
ADDRESS
OE
-
-
-
-
+
-
-.
.
~�OE__. i
DATAl/O -H-I-GH-Z+ - - + - - <
0071-4
Note: (4) tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when
the outputs are no longer driven. tHz min., toHz min., tLz min. and toLZ min. are periodically sampled and are not 100% tested.
3-11
X2816B, X2816BI
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
twc(6)
---,,
� Write Cycle Time
5
10
ms
tAS
�Addre$S Setup Time
10
ns
tAH
Address Hold Time
150
ns
tcs
Write Setup Time
0
ns
tcH
Write Hold Time
0
ns
tcw
CE Pulse Width
150
ns
t o ES
OE High Setup Time
10
ns
t o EH
OE High Hold Time
10
ns
twp
WE Pulse Width
150
ns
twpH
WE High Recovery
50
ns
tov
Data Valid
300
ns
tos
Data Setup
100
ns
toH
Data Hold
15
ns
tow
Delay to Next Write
500
�s
ts LC
Byte Load Cycle
3
20
�s
WE Controlled Write Cycle
ADDRESS
0071-5
Notes: (5) Typical values are for TA = 25�C and nominal supply voltage. (6) twc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
3-12
X2816B, X2816BI
CE Controlled Write Cycle ADDRESS
~�os-... 4-IDH
Page Mode Write Cycle
0071-6
(7) OE [l/}/7 W2I Wll/ Y(jfl Wll/ Wlll '@llfj
Cf
\
l111A
l11l&
4/A
/JllA
lll1A
n.xxx r J
___ WE
(8) �ADDRESS
,,,,
1/0 XXXXXXXXX>CX x ~
BYTE 0 --BYT_E_1_
BYTE 2
_B_YT_E_n_ BYTEn+1
BYTEn+2
twc
*For each successive write within the page write operation, A4 -A10 should be the same or writes to an unknown address could occur.
0071-7
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-13
X2816B, X2816BI
DATA Polling Timing Diagram(9)
:-----+----:__ _. . .:;___[~
po:;:;_J ' 1/07 --+--<,._D_,N_=_X_>-----< Dourt:: >---""""'l.,._____"""41.
Note: (9) A polling operation by definition is a read cyele and therefore subject to read cycle timings.
0071-8
3-14
X2816B, X2816BI
PIN DESCRIPTIONS
Addresses (Ao-A10) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1107) Data is written to or read from the X28168 through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28168.
DEVICE OPERATION _Read
Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28168 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X2816B allows the entire memory to be typically written in 640 ms. Page write allows two to sixteen bytes of data to be consecutively written to the X28168 prior to the commencement of
the internal programming cycle. Although the host system may read data from any location in the system to transfer to the X28168, the destination page address of the X2816B should be the same on each subsequent strobe of the WE and CE inputs. That is, A4 through A1 o must be the same for each transfer of data to the X2816B during a page write cycle.
The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 20 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 20 �s, the internal automatic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 20 �s.
DATA Polling The X28168 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28168, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data.
WRITE PROTECTION
There are three features that protect the nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse of less than 20 ns will not initiate a write cycle.
�Vee Sense-All functions are inhibited when Vee is -:;. 3V, typically.
�Write Inhibit-Holding either OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent writes.
3-15
X2816B, X2816BI
SYSTEM CONSIDERATIONS
Because the X2816B is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X2816B has two power modes, standby and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �,F high frequency ceramic capacitor be used between Vcc and GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4. 7 JLF electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
SYMBOL TABLE
WAVEFORM
xxxxx
B�K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
3-16
X28168, X281681
Normalized Active Supply Current vs. Ambient Temperature
Normalized Standby Supply Current vs. Ambient Temperature
u 1.2 ...Y
c
LLJ
N
::J
1.0
<
::E
a::
0z 0.8
0.6 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0071-9
Normalized Access Time vs. Ambient Temperature
1.4 ~---~-----~ Vcc=5.0V
~< 1.2
c
LLJ
N
::J
1.0
<
::E
a::
0z 0.8
0.6 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0071-11
CD 1.2 ..!!>
c
LLJ
N
:<:J
1.0
:a:E::
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0071-10
3-17
NOTES
3-18
JliCll!
16K
Commercial Industrial
X2816C X2816CI
Electrically Erasable PROM
2048 x 8 Bit
FEATURES � 200 ns Access Time � High Performance Advanced NMOS
Technology � Fast Write Cycle Times
-16-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 640 ms
Typical -Effective Byte Write Cycle Time of 300 �s
Typical � DATA Polling
-Allows User to Minimize Write Cycle Time � Simple Byte and Page Write
-Single TTL Level WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout � High Reliability -Endurance: 10,000 Cycles -Data Retention: 100 Years
DESCRIPTION
The Xicor X2816C is a 2K x 8 E2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor programmable nonvolatile memories it is a 5V only device. The X2816C features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs, ROMs and EPROMs.
The X2816C supports a 16-byte page write operation, typically providing a 300 �s/byte write cycle, enabling the entire memory to be written in less than 640 ms. The X2816C also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics for Xicor nonvolatile memories.
PIN CONFIGURATIONS PLASTIC
A,
Vee
As
As
As
A,
A4
WE
A3
OE
A2
A,o
A,
CE
Ao
1101
l/Oo
110.
1/0,
I/Os
1/02
1/04
Vss
1/03
0108-1
PLCC
.t- ~ ~ ~ J! I~ ~
As
A1 Ao NC l/Oo
29 As 28 Ag 27 NC 26 NC
25 5E
24 A10
23 CE
22 1/07 21 I/Os
~~~z~~~ - N Ul (.) ""' .... II)
0108-2
PIN NAMES
Ao-Arn l/Oo-1107 WE CE OE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable
+sv
Ground No Connect
3-19
X2816C, X2816CI
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias x2s1sc ............................... -10�c to +85�C X2816CI .............................. -65�C to + 135�C
Storage Temperature .................... -65�C to + 150�C Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X2816C TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified.
X2816CI TA == - 40�C to + 85�C, Vcc = + 5V � 10%, unless otherwise specified.
Symbol Ice
lss
lu ILO V1L(2) V1H(2) Vol VoH
Parameter Vee Current (Active)
Vcc Current (Standby)
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Min.
-1.0 2.0 2.4
Limits Typ.(1)
70
Max. 110
Units mA
35
50
mA
10
�A
10
�A
0.8
v
Vee+ 1.0
v
0.4
v
v
Test Conditions
CE= OE= V1L All I/O's = Open Other Inputs = Vee CE = V1H, OE = V1L All I/O's= Open Other Inputs = Vee V1N = GND to Vee VouT = GND to Vee. CE= V1H
loL = 2.1 mA loH = -400 �A
ENDURANCE AND DATA RETENTION
Parameter
Min.
Minimum Endurance
10,000
Data Retention
100
Max.
Unit Cycles/Byte
Years
Condition Reliability Report-520 Reliability Report-515
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(3)
Power-Up to Read Operation
tpuw(3)
Power-Up to Write Operation
Typ.(1) 1 5
Units ms ms
CAPACITANCE TA = 25�C, f = 1.0 MHz, Vee = 5V
Symbol
Test
Max.
C1;o(3)
Input/Output Capacitance
10
C1N(3)
Input Capacitance
6
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) V1L min. and V1H max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.
3-20
Units pF pF
Conditions V110 = OV V1N = OV
X2816C, X2816CI
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TIL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 DouT D1N High Z
-
A.C. CHARACTERISTICS
X2816C TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X2816CI TA = -40�C to +85�C, Vee= +5V � 10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
tRe
Read Cycle Time
200
teE
Chip Enable Access Time
tAA
Address Access Time
toE
Output Enable Access Time
tLz(4)
Chip Enable to Output in Low Z
0
tHz(5)
Chip Disable to Output in High Z
0
toLz(4)
Output Enable to Output in Low Z
0
toHz(5)
Output Disable to Output in High Z
0
toH
Output Hold from Address Change
0
Max.
200 200 100
60
60
Read Cycle
Power Active Active Standby
-
Units ns ns ns ns ns ns ns ns ns
1 - - - - - - - t R c - - - - - - - - .....1
ADDRESS --�'T'-------------'I~------------' ~~~~
.._toE--+ O E - - - - - + -......
0106-4
Notes: (4) tLz min. and toLz min. are periodically sampled and not 100% tested. (5) tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min. and toHz min. are periodically sampled and not 100% tested.
3-21
X2816C, X2816CI
Write Cycle Limits Symbol twc<7> tAs tAH tcs tcH tcw toES toEH twp twPH tov tos toH tow t s LC
Parameter Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE High Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle
WE Controlled Write Cycle
Min.
10 120
0
0 150 10 10 150 50
100 15 500 3
Typ.(6)
5
Max.
10
..
1
_;_
20
Units ms ns ns ns ns ns ns ns ns ns �s ns ns �s �s
ADDRESS
DATA IN
DATAOUT )()()()()---------------------H-IG-H-Z-----------------~---------
0108-5
Notes: (6) Typical values are for TA = 25�C and nominal supply voltage.
(7) twc is .the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the
maximum time.the device requires to automatically complete the internal write operation.
.
3-22
X2816C, X2816CI
CE Controlled Write Cycle ADDRESS
~toes~
.__tos--. .-toH
0108-6
Page Mode Write Cycle
J (8) OE {///}} W2I Y/llJ vlfll Y/llJ '<lllZl tttdf
CE
\ ll1A ll1A !JA ll1lA ll1lA J.XXXX 'r
WE
---- (9) �ADDRESS
x 1/0 ~ ~---- "'---lv'j(Ji ---" ..,___,, "'+-----",___..,.__
BYTE 0 BYTE 1
BYTE 2
BYTE n
BYTE n+ 1
BYTE n+ 2
twc
0108-7
*For each successive write within the page write operation, A4-A10 should be the same or writes to an unknown address could occur.
Notes: (8) Between successive byte writes within a page write operation, OE can be strobed LOW; e.g. this can~ done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(9) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-23
X2816C, X2816CI
DATA Polling Timing Diagram(10)
ADDRESS
An
C�
f =t'- WE - + - - - - - t - O E H _ . Il _ _ - - - - \ : ;_ _ _
Dour~: �OE
1/07 ___"">----...-c. >----'l1...-----.-cp;0_j
Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
SYMBOL TABLE
WAVEFORM
~
xxxxx
}1� �K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
0108-8
OUTPUTS Will be steady
Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
X2816C, X2816CI
PIN DESCRIPTIONS
Addresses (Ao-A10) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1107) Data is written to or read from the X2816C through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X2816C.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2816C supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X2816C allows the entire memory to be typically written in 640 ms. Page write allows two to sixteen bytes of data to be consecutively written to the X2816C prior to the commencement of the internal programming cycle. Although the host system may read data from any location in the system to
transfer to the X2816C, the destination page address of the X2816C should be the same on each subsequent strobe of the WE and CE inputs. That is, A4 through A1 o must be the same for each transfer of data to the X2816C during a page write cycle.
The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 20 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 20 �s, the internal automatic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 20 �s.
DATA Polling The X2816C features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2816C, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data.
WRITE PROTECTION
There are three features that protect the nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse which is typically less than 20 ns will not initiate a write cycle.
� Vcc Sense-All functions are inhibited when Vcc is
::;;: 3V, typically.
�Write Inhibit-Holding either OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent writes. Write cycle timing specifications must be observed concurrently.
ENDURANCE
Xicor E2PROMs are designed and tested for applications requiring extended endurance.
3-25
X2816C, X2816CI
SYSTEM 'CONSIDERATIONS
Because the X2816C is frequently used in large memory arrays it is provided with a two line control architecture for both read ahd write operations. Proper usage can provide the lowest possible power dissipation and eliminate t!')e possibility of contention where multiple 1/0 pins share the ~ame bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(sr is outputting data on the bus.
Because the X2816C has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it �is recommended that a� 0.1 �F high frequency ceramic capacitor be used between Vcc and GND at each device. Depending on the size of the array, the value of the capacitor may have to be larget.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
FUNCTIONAL DIAGRAM
Ao-Aw ADDRESS
INPUTS
x
BUFFERS
LATCHES AND
DECODER
16,384-BIT E2 PROM ARRAY
y BUFFERS LATCHES
AND DECODER
CONTROL LOGIC
110 BUFFERS AND LATCHES
ll lllll
llOo-1101 DATA INPUTS/OUTPUTS
0108-3
X2816C, X2816CI
Normalized Active Supply Current vs. Ambient Temperature
Normalized Standby Supply Current vs. Ambient Temperature
0 1.2 ...Y
0
i.J
N
:<::i
1.0
::E
0::
0z 0.8
0.6 .___ _ __L__ _ _ _ ___J
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0108-9
Normalized Access Time vs. Ambient Temperature
1.4 ----~-----~ Vcc=5.0V
...~.
0 i.J N
:<::i
::E
0::
0 z
0.6 '---------'------------'
-55
+25
+125
AMBIENT TEMPERATURE {�C)
0108-11
m 1.2 ..!fl
0
i.J
N
<:::i
1.0
::E
0::
0z 0.8
0.6 '---------'------------'
-55
+25
+125
AMBIENT TEMPERATURE (oC)
0108-10
3-27
NOTES
3-28
JiCll!
64K
Commercial Industrial
X2864A X2864AI
Electrically Erasable PROM
8192 x 8 Bit
FEATURES � 250 ns Access Time � Fast Write Cycle Times
-16-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 2.6 Sec.
Typical -Effective Byte Write Cycle Time of 300 �.s
Typical � DATA Polling
-Allows User to Minimize Write Cycle Time � High Reliability
-Endurance: 10,000 Writes Per Byte -Data Retention: 100 Years � Simple Byte and Page Write -Single TTL Level WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The Xicor X2864A is a SK x 8 E2PROM, fabricated with the same reliable N-channel floating gate MOS technology used in all Xicor 5V programmable nonvolatile memories. The X2864A features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs and EPROMs.
The X2864A supports a 16-byte page write operation, effectively providing a 300 �sfbyte write and enabling the entire memory to be written in less than 2.6 seconds. The X2864A also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle.
Xicor E2PR0Ms are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 10,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
PIN CONFIGURATIONS
FUNCTIONAL DIAGRAM
0070-1
PIN NAMES
Ao-A12 !/Oo-1107 WE CE OE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable
+5V Ground No Connect
0070-2
Ao -A12 ADDRESS
INPUTS
x
BUFFERS LATCHES
ANO DECODER
65,536-BIT E2PROM
ARRAY
y
BUFFERS LATCHES
AND DECODER
CONTROL LOGIC AND TIMING
l/Oo-1101 DATA INPUTS/OUTPUTS
0070-3
3-29
X2864A, X2864AI
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X2864A ........................... ~ ... -10�c to + as�c X2864AI .............................. - ss0 c to + 13s0 c Storage Temperature .................... - 65�C to + 1so0 c
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed urider "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X2864A TA = 0�C to + 70�C; Vee = + 5V � 5%, unless otherwise specified.
X2864AI TA = -40�C to + 85�C, Vcc = + 5V � 10%, unless otherwise specified.
Symbol
Parameter
X2864A Limits X2864AI Limits Units Min. Max. Min. Max.
Test Conditions
Ice
Vee Current (Active)
140
140
mA CE= OE= V1L
All I/O's= Open
Other Inputs = Vee
lss
Vee Current (Standby)
60
70
mA CE = VIH� OE = V1L
All I/O's= Open
Other Inputs = Vee
lu ILO V1L(3) V1H(3)
Vol VoH
Input Leakage Current
10
10
�A V1N = GND to Vee
Output Leakage Current
10
10
Input Low Voltage
-1.0
0.8
-1.0
0.8
�A Vour = GND to Vee. CE = V1H
v
Input High Voltage Output Low Voltage
2.0 Vee +0.'5 2.0 Vee +1.0 v
0.4
0.4
v loL = 2.1 mA
Output High Voltage
2.4
2.4
v loH = -400 �A
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(2)
Power-Up to Read Operation
tpuw<2>
Power-Up to Write Operation
Typ.(1) 1 5
Units ms ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
c11o(2)
C1N(2)
Test Input/Output Capacitance Input Capacitance
Max. 10 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pul.se Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) V1L min. and V1H max. are for reference only and are not tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour D1N HighZ
-
Power Active Active Standby
-
3-30
X2864A, X2864AI
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
10,000
Data Retention
100
Max.
Units Cycles/ Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS X2864A TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X2864AI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
tRc tcE tAA toE tLz(4) tHz(4) toLz<4> toHz<4> toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change
X2864A�25 X2864Al-25 Min. Max. 250
250 250 100 10 10 60 10 10 60 10
X2864A X2864AI Min. Max. 300
300 300 100 10 10 80 10 10 80 10
X2864A�35 X2864Al-35 Min. Max. 350
350 350 100 10 10 80 10 10 80 10
X2864A�45 X2864Al�45 Min. Max. 450
450 450 100 10 10 100 10 10 100 10
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
ADDRESS
1'4------tRc-------1 fee---.
DATAl/O
HIGHZ
----+--+--<
0070-4
Note: (4) tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min., toHz min., tLz min. and toLz min. are periodically sampled and are not 100% tested.
3-31
X2864A, X2864AI
Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
twc<5)
Write Cycle Time
10
ms
tAs
Address Setup Time
10
ns
tAH
Address Hold Time
200
ns
tcs
Write Setup Time
0
ns
tcH
Write Hold Time
0
ns
tcw
CE Pulse Width
150
ns
t o ES
OE High Setup Time
10
ns
toEH
OE High Hold Time
10
ns
twp
WE Pulse Width
150
ns
twpH
WE High Recovery
50
ns
tov
Data Valid
300
ns
tos
Data Setup
100
ns
toH
Data Hold
20
ns
tow
Delay to Next Write
500
�s
t s LC
Byte Load Cycle
3
40
�s
WE Controlled Write Cycle
ADDRESS
�cs_.
DATAOUT )()()()()--------------------------------H-IG--H-Z-----------------------------------~
0070-5
Note: (5) twc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
3-32
X2864A, X2864AI
CE Controlled Write Cycle ADDRESS
[SSS/
J
HIGHZ
0070-6
Page Mode Write Cycle
(6) OE {{(lil Vlll Vlll '((/fl Wl2I WlZI ' W f )
CE
4/lh \ lllA lllA
lllA
llllA
AXXXX ( 5
WE
xxxxxxxxxx:::::___x ______ ---- {7} �ADDRESS 110
~,__
""!~---,___...,.._
BYTE 0 BYTE 1
BYTE 2
BYTE n
BYTE n+ 1
BYTE n+2
twc
*For each successive write within the page write operation, A4 -A12 should be the same or writes to an unknown address could occur.
0070-7
Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-33
X2864A, X2864AI
DATA Polling Timing Diagram(&)
='--A-"--XXXXXXX
~---1 -~:; f:}-
:
__
___
l/07 --+--<...-D-,N-=-X->-----c: Dourt: >---...r,1-----.-c:p;:;_j
Note: (8) A polling operation by definition is a read cycle and therefore subject to read cycle timings.
0070-8
3-34
X2864A, X2864AI
PIN DESCRIPTIONS Addresses (Ao-A12) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1107) Data is written to or read from the X2864A through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X2864A.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2864A supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X2864A allows the entire memory to be written in 2.6 seconds. Page write allows
two to sixteen bytes of data to be consecutively written to the X2864A prior to the commencement of the internal programming cycle. The destination addresses for a page write operation must reside on the same page; that is, A4 through A12 must not change.
The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive byte write cycle must begin within 20 �s of the falling edge of WE of the preceding cycle. If a subsequent WE HIGH to LOW transition is not detected within 20 �s the internal automatic programming cycle will commence.
DATA Polling The X2864A features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2864A, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data.
WRITE PROTECTION
There are three features that protect the nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse of less than 20 ns will not initiate a write cycle.
�Vee Sense-All functions are inhibited when Vee is ::::: 3V, typically.
�Write Inhibit-Holding either OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent writes.
3-35
X2864A, X2864AI
SYSTEM CONSIDERATIONS
Because the X2864A is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the. most benefit it is recommended that CE be decoded from the address bus ano be used as the primary device selection input. Both OE and WE would then. be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X2864A has two power modes, standby and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vcc and GND at each device. Depending on the size of the ar-. ray, the value of the capacitor may .have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
SYMBOL TABLE
WAVEFORM
INPUTS
Must be steady
OUTPUTS
Will be steady
xxxxx
B�K
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
3-36
X2864A, X2864AI
Normalized Active Supply Current vs. Ambient Temperature
1.4 ~---~-----~ Vcc=5.ov
0 1.2 ..!:>
.0....
N
:<J
1.0
:.E
0::
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0070-9
Normalized Access Time vs. Ambient Temperature
1.4
...~. 1.2
.0....
N
:J
1.0
<
:.E
0::
0z 0.8
Vcc=5.0V
0.6
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0070-11
Normalized Standby Supply Current vs. Ambient Temperature
1.4 ~---~--------. Vcc=5.0V
III 1.2
_VI
.0....
N
:J
1.0
<
:.E
0::
0z 0.8
0.6 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0070-10
3-37
NOTES
3-38
JiCI'
64K
Commercial Industrial
X2864B X2864BI
Electrically Erasable PROM
8192 x 8 Bit
TYPICAL FEATURES � 120 ns Access Time � High Performance Scaled NMOS
Technology � Fast Write Cycle Times
-32-Byte Page Write Operation -Byte or Page Write Cycle: 3 ms Typical -Complete Memory Rewrite: 750 ms
Typical -Effective Byte Write Cycle Time of 95 �s
Typical � DATA Polling
-Allows User to Minimize Write Cycle Time � Simple Byte and Page Write
-Single TTL Level WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout � High Reliability -Endurance: 10,000 Cycles -Data Retention: 100 Years
DESCRIPTION
The Xicor X2864B is a BK x 8 E2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor programmable nonvolatile memories it is a 5V only device. The X2864B features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs, ROMs and EPROMs.
The X2864B supports a 32-byte page write operation, effectively providing a 95 �s/byte write cycle and enabling the entire memory to be written in less than 750 ms. The X2864B also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics for Xicor nonvolatile memories.
PIN CONFIGURATIONS
PLASTIC CERDIP
NC
Vee
WE
NC
Ae
Ag
A,,
OE
A.o CE
Ao
1101
l/Oo
I/Os
1101
I/Os
1102
110,
Vss
1/03
0031-1
PLCC
PIN NAMES
Ao-A12 1/0o-1107 WE CE OE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
..... ~ (/) 0
,.,., ..... II)
oo V>zooo
::::. ::::. > ::::. ::::. ::::.
0031-2
3-39
X2864B, X2864BI
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X2864B ............................... -10�C to + 85�C X2864BI .............................. - 65�C to + 135�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X2864B TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X2864BI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
Limits
Min. Typ.{1)
Max.
Units
Test Conditions
Ice
Vee Current (Active)
80
140
mA CE= OE= V1L
All I/O's = Open
Other Inputs = Vee
lss
Vcc Current (Standby)
50
70
mA CE = V1H. OE = V1L
All I/O's= Open
Other Inputs = Vee
lu
Input Leakage Current
10
�A V1N = GND to Vee
ILO V1L(2) V1H(2)
Vol VoH
Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1.0 2.0
2.4
10
�A VouT = GND to Vee. CE= V1H
0.8
v
Vee +1.0
v
0.4
v
loL = 2.1 mA
v
loH = - 400 p.A
ENDURANCE AND DATA RETENTION
Parameter
Min.
Minimum Endurance
10,000
Data Retention
100
Max.
Unit Cycles/Byte
Years
Condition Reliability Report-520 Reliability Report-515
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(3)
Power-Up to Read Operation
tpuw(3)
Power-Up to Write Operation
Typ.{1) 1 5
Units ms ms
CAPACITANCE TA = 25�C, f = 1.0 MHz, Vee = 5V
Symbol
Test
Max.
C1/0(3)
Input/Output Capacitance
10
C1N(3)
Input Capacitance
6
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) V1L min. and V1H max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.
Units pF pF
Conditions V110 = OV V1N = OV
3-40
X2864B, X2864BI
A.C. CONDITIONS OF TEST
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
110 DouT D1N High Z
-
-
Power Active Active Standby
-
A.C. CHARACTERISTICS X2864B TA= 0�C to +70�C, Vee= +5V �5%, unless otherwise specified. X2864BI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
tRe teE tAA toE tLz(4) toLz<4l tHz(5) t0Hz<5l toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
X2864B-12 X2864Bl-12
Min. Max.
120
120
120
50
0
0
0
50
0
50
0
X2864B-15 X2864Bl-15
Min. Max.
150
150
150
70
0
0
0
50
0
50
0
X2864B-20 X2864Bl-20
Min. Max.
200
200
200
100
0
0
0
50
0
50
0
X2864B-25 X2864Bl-25
Min. Max.
250
250
250
100
0
0
0
50
0
50
0
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
ADDRESS
0031-5
Notes: (4) tLz min. and toLz min. are shown for reference only, they are periodically characterized and are not tested. (5) tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min. and toHz min. are shown for reference only, they are periodically characterized and are not tested.
3-41
X2864B, X2864BI
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(6)
Max.
twc<7>
Write Cycle Time
3
5
tAs
Address Setup Time
5
tAH
Address Hold Time
50
tcs
Write Setup Time
0
tcH
Write Hold Time
0
tcw
CE Pulse Width
100
toEs
OE High Setup Time
10
t o EH
OE High Hold Time
10
twp
WE Pulse Width
100
twPH
WE High Recovery
50
tov
Data Valid
100
tos
Data Setup
50
toH
Data Hold
5
tow
Delay to Next Write
10
ts Le
Byte Load Cycle
1
100
WE Controlled Write Cycle
ADDRESS ~J~~~~~~~~~~~~~~~~~~~~~~~~
tAS
tAH
tcs
Units ms ns ns ns ns ns ns ns ns ns �s ns ns �s �s
toEs-----twp------..i
0031-6
Notes: (6) Typical values are for TA = 25�C and nominal supply voltage. (7) twc is the minimum cycle time from the system perspective; it is the maximum time the device requires to perform the internal write operation.
3-42
X2864B, X2864BI
CE Controlled Write Cycle
ADDRESS
tAs
CE
OE WE DATA IN DATA OUT Page Write Cycle
tAH
~t
DATA VALID
tos HIGH Z
~\\\\\\\Y w~
. .~mxxxxxxx
0031-7
'<4YI (8) OE ..lLLl \{l/ \{l/
\{l/ \{l/ ~)
CE
\
US9' /1)\ /1)\ ~
WE
(9) �ADDRESS
1/0
BYTEO BYTE1
BYTE2
BYTE n
BYTE n+ 1 BYTEn+2
twc
*For each successive write within the page write operation, A5-A12 should be the same or writes to an unknown address could occur.
0031-8
Notes: (8) Between successive byte writes within a page write operation, OE can be strobed LOW; e.g., this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(9) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-43
X2864B, X2864BI
DATA Polling Timing Diagram(10)
~-----A-"----JXXXXXXX
1/0., --"'9-<
Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings. SYMBOL TABLE
WAVEFORM
xxxxx
~�K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
0031-9
OUTPUTS Will be steady
Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
3-44
X2864B, X2864BI
PIN DESCRIPTIONS Addresses (Ao-A12) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1107) Data is written to or read from the X28648 through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28648.
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28648 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3 ms.
Page Write Operation The page write feature of the X28648 allows the entire memory to be written in 750 ms. Page write allows two
to thirty-two bytes of data to be consecutively written to the X2864B prior to the commencement of the internal programming cycle. The destination addresses for a page write operation must reside on the same page; that is, As through A12 must not change.
The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to thirty-one bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s the internal automatic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide so long as the host continues to access the device within the byte load cycle time of 100 �s.
DATA Polling The X2864B features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2864B, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1107 will reflect true data.
WRITE PROTECTION
There are two features that protect the nonvolatile data from inadvertent writes.
� Vcc Sense-All functions are inhibited when Vcc is
:S::3.5V.
� Write Inhibit-Holding either OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent writes.
3-45
X28648, X286481
SYSTEM CONSIDERATIONS Because the. X2864B is frequently used in large memo~ ry arrays it is provided with a tWo line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate ~he possibility of contention where multiple 1/0 pins share the same bus,
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because .the X2864B has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the �1arger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vee and
GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it'is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
FUNCTIONAL DIAGRAM
Ao -A12 ADDRESS
INPUTS
x
BUFFERS LATCHES
AND DECODER
65,536-BIT E2PROM
ARRAY
y
BUFFERS LATCHES
AND DECODER
CONTROL LOGIC AND TIMING
llOo-1101 DATA INPUTS/OUTPUTS
0031-3
3-46
64K
Commercial Industrial
X2864H X2864HI
Electrically Erasable PROM
8192 x 8 Bit
TYPICAL FEATURES � 70 ns Access Time �High Performance Scaled NMOS
Technology � Fast Write Cycle Times
-32-Byte Page Write Operation -Byte or Page Write Cycle: 3 ms Typical -Complete Memory Rewrite: 750 ms
Typical -Effective Byte Write Cycle Time of 95 �s
Typical � DATA Polling
-Allows User to Minimize Write Cycle Time � High Reliability
-Endurance: 10,000 Writes Per Byte -Data Retention: 100 Years � Simple Byte and Page Write -Single TTL Level WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The Xicor X2864H is a high speed BK x 8 E2PROM, fabricated with Xicor's proprietary, high performance, N-channel floating gate MOS technology. Like all Xicor programmable nonvolatile memories it is a 5V only device. The X2864H features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs, and EPROMs.
The X2864H supports a 32-byte page write operation, effectively providing a 95 �sf byte write cycle and enabling the entire memory to be written in less than 750 ms. The X2864H also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle.
Xicor E2PROMs are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 10,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
PIN CONFIGURATIONS
PLASTIC CERDIP
NC
Vee
we
NC
As
As
I/Or 110& I/Os 1/04 1103
0034-1
PLCC
As Ag A11 26 NC
X2864H 2s 6E (TOP VIEW) 24 A10
23 cr
22 1/07 21 1/06
PIN NAMES
Ao-A12 l/Oo-1/07 WE CE OE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
0034-2
3-47
X2864H,X2864HI
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X2864H ............................... -10�C to + 85�C X2864HI .............................. -65�C to + 135�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 10 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed u�nder �"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X2864H TA = 0�C to + 70�C; Vee = + 5V � 5%, unless otherwise specified. X2864HI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
Limits
Min. Typ.(1)
Max.
Units
Test Conditions
Ice
Vee Current (Active)
80
150
mA CE= OE= V1L
All I/O's = Open
Other Inputs = Vee
lss
Vcc Current (Standby)
50
80
mA CE = V1H. OE = V1L
All I/O's = Open
Other Inputs= Vee
lu ILO V1L(2)
Input Leakage Current Output Leakage Current Input Low Voltage
-1.0
10
�A V1N = GND to Vee
10
�A Your = GND to Vee. CE = V1H
0.8
v
V1H(2)
Input High Voltage
2.0
VoL
Output Low Voltage
VoH
Output High Voltage
2.4
Vee +1.0 v
0.4
v
loL. = 2.1 mA
v
loH = -400 �A
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(3)
Power-Up to Read Operation
tpuw<3>
Power-Up to Write Operation
Typ.(1) 1 5
Units ms ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol C110(3)
Test Input/Output Capacitance
Cif..J(3)
Input Capacitance
Max. 10 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
o.8V and 2.ov
Output Load
1 TTL Gate and CL= 30pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) V1L min. and V1H max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour D1N HighZ
-
Power Active Active Standby
-
3-48
X2864H,X2864HI
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
10,000
Data Retention
100
Max.
Units Cycles/ Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS
X2864H TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified. X2864HI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
tRc tcE tAA toE tLz(4) toLz(4) tHz(5) toHz(5) toH
Parameter
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
X2864H-70 X2864Hl-70
Min.
Max.
70
70
70
35
0
0
0
40
0
40
0
X2864H-90 X2864Hl-90
Min.
Max.
90
90
90
45
0
0
0
40
0
40
0
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
ADDRESS --'~-------------------------i""'""------------------------
DATA 1/0 -H-IG-H-Z---------<
0034-4
Notes: (4) tLz min. and toLz min. are shown for reference only, they are periodically characterized and are not tested. (5) tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min. and toHz min. are shown for reference only, they are periodically characterized and are not tested.
3-49
X2864H,X2864HI
Write Cycle Limits
Symbol
Parameter
twc tAs tAH tcs tcH tcw toES toEH twp twPH tov tos toH tow t s LC
Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE High Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle
WE Controlled Write Cycle
X2864H�70 X2864Hl-70
Min.
Max.
5
5
50
0
0
60
10
5
-:-
60
50
100
35
5
10
1
100
X2864H-90 X2864Hl-90
Min.
Max.
5
5
50
0
0
80
10
5
80.
SQ
100
35
5
10
1
100
Units
ms ns ns ns ns ns ns ns ns ns �s ns ns �s �s
ADDRESS
tcs_.
CE --~~~~--...-.------------------...._--___..._......,......,.............._,""'-..:-..:~.+---
HIGHZ
DATAOUT )()()()()----------------------------------------------------
0034-5
3-50
X2864H,X2864HI
CE Controlled Write Cycle ADDRESS
DATA OUT Page Mode Write Cycle
HIGHZ
0034-6
(6) OE ..L2ll 'lll 'lll '<4fp 'lll 'lll ~)
CE
\
11)9' /1A /1A ~
WE
(7) �ADDRESS
1/0
BYTEO
BYTE1
BYTE2
BYTE n
BYTE n+ 1
BYTEn+2
twc
*For each successive write within the page write operation, As-A12 should be the same or writes to an unknown address could occur.
0034-7
Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW; e.g., this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-51
X2864H, X2864HI
DATA Polling Timing Diagram(&)
~......___A_"___,JXXXXXXX
SYMBOL TABLE WAVEFORM
xxxxx
~�K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
Note: (8) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
0034-8
OUTPUTS Will be steady
Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
3-52
X2864H,X2864HI
PIN DESCRIPTIONS Addresses (Ao-A12) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1/07) Data is written to or read from the X2864H through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X2864H.
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2864H supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3 ms.
Page Write Operation The page write feature of the X2864H allows the entire memory to be written in 750 ms. Page write allows two
to thirty-two bytes of data to be consecutively written to the X2864H prior to the commencement of the internal programming cycle. The destination addresses for a page write operation must reside on the same page; that is, A5 through A12 must not change.
The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to thirty-one bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the 100 �s byte load cycle time.
DATA Polling The X2864H features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2864H, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data.
WRITE PROTECTION
There are two features that protect the nonvolatile data from inadvertent writes.
�Vee Sense-All functions are inhibited when Vee is ::;;;4.0V.
� Write Inhibit-Holding OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent writes.
3-53
X2864H,X2864HI
SYSTEM CONSIDERATIONS
Because the X2864H is frequently used in large memory arrays it is provided with a two line control architecture for �both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X2864H has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vcc and
GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
FUNCTIONAL DIAGRAM
Ao -A12 ADDRESS
INPUTS
x
BUFFERS LATCHES
AND DECODER
65,536-BIT E2PROM ARRAY
v
BUFFERS LATCHES
AND DECODER
CONTROL LOGIC AND TIMING
llOo-1101 DATA INPUTS/OUTPUTS
0034-3
3-54
IiCl'
64K
Commercial Industrial
X28C64 X28C641
Electrically Erasable PROM
SK x 8 Bit
FEATURES � 120 ns Access Time � LOW Power CMOS
-60 mA Active Current Max. -200 �A Standby Current Max. � Fast Write Cycle Times -64-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 0.625 Sec.
Typical -Effective Byte Write Cycle Time: 78 �s
Typical � Software Data Protection � End of Write Detection
-DATA Polling -Toggle Bit � High Reliability -Endurance: 10,000 Cycles -Data Retention: 100 Years � Simple Byte and Page Write -Single TTL Compatible WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The Xicor X28C64 is a SK x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C64 is a 5V only device. The X28C64 features the JEDEC approved pinout for bytewide memories, compatible with industry standard RAMs.
The X28C64 supports a 64-byte page write operation, effectively providing a 78 �sfbyte write cycle and enabling the entire memory to be typically written in 0.625 seconds. The X28C64 also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C64 includes a user-optional software data protection mode that further enhances Xicor's hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics for Xicor nonvolatile memories.
PIN CONFIGURATIONS
PLASTIC CERDIP
NC
Vee
A12
WE
A1
NC
Ae
Ae
As
Ae
A.
A,,
AJ
OE
Az
A,o
A,
CE
Ao
1101
l/Oo
l/Oe
1/01
I/Os
1/02
1/04
Vss
1/03
0111-1
PLCC
.t .[ ~ ~ ~I~ uz
29 As
28 Ag
A4
27 A11
A3
26 NC
Az
X28C64 25 6E
A1 Ao 11
24 A10
23 cr
NC
22 1/07
l/Oo
21 I/Os
14 15 16 17 18 19 20
~- ~N::(/) iU zl'~"l ~""" ~Ill
0111-2
PGA
@/01
r;j/02
1/03
@)
<i}/05
@18!�6
e @Oo @Ao V55 �04 @07
A1 0
� A2 X28C64
CE
@
@1/10
(BOTTO~ VIEW)
r;/3 �A4
DE
@
@/11
c~/5 <J/12 @Vee @/9 @/8
�As
<J/7
NC 0
WE
@
NC
@
PIN NAMES
0111-3
Ao-A12 l/Oo-1/07 WE
CE
OE
Vee Vss
NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable
+5V
Ground No Connect
3-55
X28C64, X28C641
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias X28C64 ............................... -10�C to + 85�C X28C641 .............................. - 65�C to + 135�C
Storage Temperature .................... -65�C to+ 150�C Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V D.C. Output Current ..................................5 mA Lead Temperature
(Soldering, 10 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X28C64 TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified. X28C641 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Parameter
Limits Min. Typ.(1) Max.
Units
Test Conditions
lee
Vee Current (Active)
(TTL Inputs)
lss1
Vcc Current (Standby)
(TTL Inputs)
lss2
Vcc Current (Standby)
(CMOS Inputs)
60
mA CE = OE = V1L. WE = V1H
All I/O's = Open
Address Inputs = TTL Levels@ f = 5 MHz
2
mA CE = VIH� OE = V1L
All I/O's = Open, Other Inputs = V1H
100
200
�A CE = WE = Vcc - 0.3V
All I/O's= Open, Other Inputs = Don't Care
lu ILO V1L(2) V1H(2)
Vol VoH
Input Leakage Current
Output Leakage Current
Input Low Voltage
-1.0
Input High Voltage
2.0
Output Low Voltage
Output High Voltage
2.4
�10
�A V1N = GND to Vee
�10
�A VouT = GND to Vee. CE = V1H
0.8
v
Vee +1.0 v
0.4
v loL = 2.1 mA
v loH = -400 �A
ENDURANCE AND DATA RETENTION
Parameter
Min.
Minimum Endurance
10,000
Data Retention
100
Max.
Unit Cycles/Byte
Years
Condition Reliability Report-520 Reliability Report-515
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(3)
Power-Up to Read Operation
tpuw<3)
Power-Up to Write Operation
Typ.(1) 100 5
Units �s ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Test
Max.
C110(3)
Input/Output Capacitance
10
C1N(3)
Input Capacitance
6
Notes: (1) Typical values are for TA = 25�e and nominal supply voltage. (2) V1L min. and V1H max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.
Units pF pF
Conditions V110 = OV V1N = OV
3-56
X28C64, X28C641
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 DouT D1N High Z
-
Power Active Active Standby
-
-
A.C. CHARACTERISTICS X28C64 TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified. X28C641 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
tRe teE tAA toE
tLz(4) t0Lz<4> tHz(5) t0Hz<5> toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
X28C64-12 X28C641-12 Min. Max. 120
120 120 50
0
0
0
50
0
50
0
X28C64-15 X28C641-15 Min. Max. 150
150 150 70
0
0
0
50
0
50
0
X28C64-20 X28C641-20 Min. Max. 200
200 200 80
0
0
0
50
0
50
0
X28C64-25 X28C641-25 Min. Max. 250
250 250 100
Units
ns ns ns ns
0
ns
0
ns
0
50
ns
0
50
ns
0
ns
Read Cycle
ADDRESS
l~-----lRc---------1.-1 -ICE-
-loE-
0111-4
Notes: (4) tLz min. and toLz min. are shown for reference only, they are periodically characterized and are not tested. (5) tHz max. and toHz max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min. and toHz min. are shown for reference only, they are periodically characterized and are not tested.
3-57
X28C64, X28C641
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(6)
Max.
Units
twc<?>
Write Cycle Time
5
10
ms
tAs
Address Setup Time
0
ns
tAH
Address Hold Time
100
ns
tcs
Write Setup Time
0
ns
tcH
Write Hold Time
0
ns
tcw
CE Pulse Width
100
ns
toES
OE High Setup Time
10
ns
to EH
OE High Hold Time
10
ns
twp
WE Pulse Width
100
ns
twPH
WE High Recovery
200
ns
twPH2(B)
SOP WE Recovery
1
�s
tov
Data Valid
1
�s
tos
Data Setup
50
ns
toH
Data Hold
10
ns
tow
Delay to Next Write
10
�s
tsLC
Byte Load Cycle
1
100
�s
WE Controlled Write Cycle
ADDRESS
Ci ~-~:-a-.-.i.-.�.t;ci~s---+--.._---------------+--__.."+-'--."""""-"'--'--1~'-'~~+--
DATA IN
DATA VALID
; kx>ooo-
0111-5
Notes: (6) Typical values are for TA = 25�C and nominal supply voltage. (7) twc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. (8) twPH is the normal page write operation WE recovery time. twPH2 is the WE recovery time needed only after the end of issuing the three byte SOP command sequence and before writing the first byte of data to the array. Refer to Figure 4a which illustrates the twPH2 requirement.
3-58
X28C64, X28C641
CE Controlled Write Cycle ADDRESS
,,IS:SS7
_.....,. _____.______---'_tc_H__,,j~~"'--~fZZ Z\.
DATA OUT
~tos---. +-lDH HIGHZ
0111-6
Page Write Cycle
(9) OE ..LLU Y1l vu '<4YI vu vu
Cf
\
us~ /7)\ /7)\
WE
(10) �ADDRESS
1/0
BYTEO
BYTE 1
BYTE2
BYTE n
BYTE n + 1
BYTE n+ 2 twc
*For each successive write within the page write operation, A6-A12 should be the same or writes to an unknown address could occur.
0111-7
Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(10) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-59
X28C64, X28C641
DATA Polling Timing Diagram(11)
Toggle Bit Timing Diagram(11)
0111-9
l/06 _ __...,_.1
*1/06 beginning and ending state wilt vary, depending upon actual twcSYMBOL TABLE
WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
Note: (11) Polling operations are by definition read cycles and are therefore subject to read cycle timings. 3-60
0111-8
OUTPUTS Will be steady
Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
X28C64, X28C641
PIN DESCRIPTIONS Addresses (A0 -A12) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1107) Data is written to or read from the X28C64 through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28C64.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE ar~OW and OE is HIGH. The X28C64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X28C64 allows the entire memory to be written in 0.625 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28C64 prior to the commencement of the internal programming cycle. The host can fetch data from another location within the system during a page write operation (change the source address), but the page address (As through A12) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 �s.
Write Operation Status Bits The X28C64 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the 110 bus as shown in Figure 1.
Figure 1: Status Bit Assignment
oI 110 IDIlt~~~-P~~elv:J 1 I
t _ TOGGLE BIT
DATA POLLING
0111-10
DATA Polling (1/07) The X28C64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C64, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1107 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data. Note: If the X28C64 is in the protected state and an illegal write operation is attempted DATA Polling will not operate.
Toggle Bit (I/Os) The X28C64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/Os will toggle from one to zero and zero to one on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
3-S1
X28C64, X28C641
DATA POLLING 1107 Figure 2a: DATA Polling Bus Sequence
LAST
(
WRITE/r~~~~~~~~~~~~~~~~""""'fJl--~~~~~~~-t-
Wf _J
An
Figure 2b: DATA Polling Software Flow
WRITE DATA
An
An
An
An
0111-11
DATA Polling can effectively halve the time for writing to the X28C64. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.
X28C84 READY
0111-12
3-62
X28C64, X28C641
THE TOGGLE BIT I/Os Figure 3a: Toggle Bit Bus Sequence
*Beginning and ending state of 1/06 will vary.
X28C64 READY
0111-13
Figure 3b: Toggle Bit Software Flow
LAST WRITE
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C64 memories that is frequently updated. Toggle Bit testing can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for testing the Toggle Bit.
NO
READY
0111-14
3-63
X28C64, X28C641
HARDWARE DATA PROTECTION The X2BC64 provides three hardware features (compatible with X2864A) that protect nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse typically less than 20 ns will not initiate a write cycle.
� Default Vcc Sense-All write functions are inhibited when Vee is -::;,,3v.
� Write Inhibit-Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-on and power-off, maintaining data integrity.
SOFTWARE DATA PROTECTION The X28C64 offers a software controlled data protection feature. The X28C64 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once Vcc was stable.
The X28C64 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C64 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to sixty-four bytes of data.(12) Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
Note: (12) Once the three byte sequence is i~sued it ~ust be followed by a valid byte or page write operation.
3-64
X28C64, X28C641
SOFTWARE DATA PROTECTION Figure 4a: Timing Sequence-Byte or Page Write
Vee ~
ov-'
DATA ADDRESS
~
CE
AA 1555
55 OAAA
AO 1555
tWPH2
WRITES OK
BYTE OR PAGE
~(Vee)
WRITE
twe
PROTECTED
0111-15
Figure 4b: Write Sequence for Software Data Protection
WRITE DATA AA TO
ADDRESS 1555
WRITE DATA 55 TO
ADDRESS OAAA
Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28C64 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C64 will be write protected during power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE DATA AO TO
ADDRESS 1555
BYTE/PAGE LOAD ENABLED
WRITE DATA XX TO
ANY ADDRESS
WRITE LAST BYTE TO
LAST ADDRESS
AFTER twc
RE-ENTERS DATA PROTECTED STATE
0111-16
3-65
X28C64, X28C641
RESETTING SOFTWARE DATA PROTECTION Figure Sa: Reset Software Data Protection Timing Sequence
v ~
CC DATA ADDRESS ~
AA 1SSS
S5
OAAA
80 1SSS
AA 1SSS
SS OAAA
20 1SSS
=t I
STANDARD
i;1:; twc
OPERATING
MODE
Figure Sb: Software Sequence to Deactivate Software Data Protection
WRITE DATA AA TO
ADDRESS 1SSS
j_
WRITE DATA SS TO
ADDRESS OAAA
l
WRITE DATA 80 TO
ADDRESS 1S5S
l
WRITE DATA AA TO
ADDRESS 155S
l
WRITE DATA SS TO
ADDRESS OAAA
l
WRITE DATA 20 TO
ADDRESS 1SSS
0111-18
0111-17
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After twc. the X28C64 will be in standard operating mode.
Note: Once initiated, the sequence of write operations should not be interrupted.
3-66
X28C64, X28C641
SYSTEM CONSIDERATIONS
Because the X28C64 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X28C64 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the� 1arger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vcc and GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
FUNCTIONAL DIAGRAM
Ao-A12
ADDRESS INPUTS
x
BUFrERS LATCHES
AND DECODER
y BUFFERS LATCHES
AND DECODER
65,536-BIT E2PROM ARRAY
1/0 BUFFERS AND LATCHES
cr
5E
WE
Yee o-+ Ysso-+
CONTROL LOGIC AND TIMING
l/Oo-1/07 DATA INPUTS/OUTPUTS
0111-19
3-67
NOTES
3-68
,1:0,
256K
Commercial Industrial
X28256 X282561
Electrically Erasable PROM
32K x 8 Bit
FEATURES � 250 ns Access Time � Fast Write Cycle Times
-64-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 2.5 Sec.
Typical -Effective Byte Write Cycle Time: 78 �s
Typical � Software Data Protection � End of Write Detection
-DATA Polling -Toggle Bit � High Reliability -Endurance: 10,000 Writes Per Byte -Data Retention: 100 Years � Simple Byte and Page Write -Single TTL Level WE Signal -Internally Latched Address and Data -Automatic Write Timing � Upward Compatible with X2864A � JEDEC Approved Byte-Wide Pinout
PIN CONFIGURATIONS
DESCRIPTION The Xicor X28256 is a 32K x 8 E2PROM, fabricated with Xicor's proprietary, high performance, N-channel floating gate MOS technology. Like all Xicor programmable nonvolatile memories the X28256 is a 5V only device. The X28256 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs.
The X28256 supports a 64-byte page write operation, effectively providing a 78 �sf byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28256 also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28256 includes a user-optional software data protection mode that further enhances Xicor's hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance and data retention. Endurance is specified as 10,000 cycles per byte minimum and data retention is specified as 100 years minimum. Refer to Xicor reliability reports RR-520 and RR-515 for details of endurance and data retention characteristics.
FUNCTIONAL DIAGRAM
x
BUFFERS LATCHES
AND DECODER
256K-BIT E2PROM
ARRAY
PIN NAMES
0029-1
Ao-A14 l/Oo-1107 WE
CE OE
Vee
Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable
+5v
Ground No Connect
0029-2
Vee er--. Vss er--.
3-69
0029-3
X282.56, X282561
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
X28256 ................................. -10�C to +8.5�C X282561 .............................. - 65�C to + 135�C Storage Temperature .................... - 65�C td + 150�C
Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V
D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1O Seconds) ........................... 30D�C
*COMMENT
Stresses' above those� listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or arty other conditions above those indicated ih the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X28256 TA = 0�C to + 70�C, Vee = + 5V �5%, unless otherwise specified.
X282561 TA= -40�C to +85�C, Vee= +5V �5%, unless otherwise specified.
Symbol
Ice
lss�
lu ILO V1L(3) V1H(3) Vol VoH
Parameter Vee Current (Active)
Vee Current (Standby)
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Min.
-1.0 2.0 2.4
Limits Typ.(1)
60
Max. 120
35
60
10 10 0.8 Vee +o.5 0.4
Units
mA
mA
�A �A
v v v v
Test Conditions
CE= OE= V1L All I/O's= Open Other Inputs= Vee CE = V1H, OE = V1L All I/O's = Open Other Inputs = Vee V1N = GND to Vee VouT = GND to Vee, CE = V1H
loL = 2.1 mA loH = -400 �A
TYPICAL POWER-UP TIMING
Symbol
Parameter
tpuR(2) tpuw<2>
Power-Up to Read Operation Power-Up to Write Operation
Typ.(1) 100 5
Units �s ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol C11o<2> C1N(2)
Test Input/Output Capacitance Input Capacitance
Max. 10 6
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pul~e Levels
Input Rise and Fall Times
OVto 3.0V
\,
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) V1L min. and V1H max. are for reference only and are not tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 DouT D1N HighZ
-
Power Active Active Standby.
-
3-70
X28256, X282561
ENDURANCE AND DATA RETENTION
Parameter
Min.
Endurance
10,000
Data Retention
100
Max.
Units Cycles/Byte
Years
Conditions Xicor Reliability Report RR-520 Xicor Reliability Report RR-515
A.C. CHARACTERISTICS
X28256 TA = 0�C to + 70�C, Vee = + 5V � 5%, unless otherwise specified.
X282561 TA = -40�C to +85�C, Vee= +5V �5%, unless otherwise specified.
Read Cycle Limits
Symbol
tRc tcE tAA toE tLz(4) toLz(4) tHz(4) t0Hz(4) toH
Parameter
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
X28256�25 X282561�25
Min. Max.
250
250
250
100
0
0
0
80
0
80
0
X28256 X282561
Min. Max.
300
300
300
100
0
0
0
80
0
80
0
X28256�35 X282561�35
Min. Max.
350
350
350
100
0
0
0
80
0
80
0
Units
ns ns ns ns ns ns ns ns ns
Reaci Cycle
ADDRESS
..__tee--.
.__toe_....
OE ------~I
~IAA___.. 0029-4
Note: (4) tHz max. and toHZ max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min., toHz min., tLz min. and toLz min. are periodically sampled and are not 100% tested.
3-71
X28256, X282561
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Units
twc(6)
Write Cycle Time
5
10
ms
tAs
Address Setup Time
0
ns
tAH
Address Hold Time
150
ns
tcs
Write Setup Time
0
ns
tcH
Write Hold Time
0
ns
tcw
CE Pulse Width
150
ns
toES
OE High Setup Time
10
ns
toEH
OE High Hold Time
10
ns
twp
WE Pulse Width
150
ns
twpH
WE High Recovery
1
�s
tov
Data Valid
300�
ns
tos
Data Setup
100
ns
toH
Data Hold
15
ns
tow
Delay to Next Write
10
�s
ts LC
Byte Load Cycle
2
100
�s
WE Controlled Write Cycle
DATA IN
HIGHZ
DATA OUT )()()()()------------------------------------------------------------------
0029-5
Notes: (5) Typical values are for TA = 25�C and nominal supply voltage. (6) twc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
3-72
X28256, X282561
CE Controlled Write Cycle ADDRESS
~IOES_,...
DATA IN Page Write Cycle
...__los--..-IDH HIGHZ
0029-6
(7) OE {II/fl Vl2l Vl2l '<(ff; Wll Yl!ll TM / )
CE
4/A \ lll1A l11A
l11A
ll7lA
AXXXX ( 5
WE
- - - - (8) *ADDRESS
vo xxxxxxxxxx::::x x__
BYTEO BYTE 1
BYTEn+1
BYTEn+2
---twc---
0029-7
*For each successive write within the page write operation, Aa-A1 4 should be the same or writes to an unknown address could occur.
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(8) The timings shown above ar~nique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-73
X28256, X282561
DATA Polling Timing Diagram(9)
f~ W'VV -An-xxxxxxx
:--+----:___. . :;__,f:.S:}-
-I:~~)_J 1/07 __,....r<,._D_IN_=_X_>------c: Dourt:: ,____.....,______
Toggle Bit Timing Diagram(9)
0029-9
I/Os_,_..._.,
*Beginning and ending state of 1/06 will vary. Note: (9) Polling operations by,definition are read cycles and therefore are subject to read cycle timings.
0029-8
3-74
X28256, X282561
PIN DESCRIPTIONS
Addresses (Ao-A14) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (1/0o-1107) Data is written to or read from the X28256 through the 110 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28256.
DEVICE OPERATION
Read Read operations are initiated by both.OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X28256 allows the entire memory to be written in 2.5 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28256 prior to the commencement of the internal programming cycle. The host can fetch data from another location within the system during a page write operation (change the source address), but the page address (As through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 �s.
Write Operation Status Bits The X28256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the 1/0 bus as shown in Figure 1.
Figure 1: Status Bit Assignment
oo Fis I� l:'=~o i
DATA POLLING
0029-10
DATA Polling (1/07) The X28256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28256, eliminating additional interrupt inputs or external hardware. During �the internal programming cycle, any attempt to read the last byte written will produce
the complement of that data on 1/07 (i.e., write data =
Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data. Note: If the X28256 is in the protected state and an illegal write operation is attempted DATA Polling will not operate.
Toggle Bit (I/Os) The X28256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/Os will toggle from one to zero and zero to one on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
3-75
X28256, X282561
DATA POLLING 1/07 Figure 2a: DATA Polling Bus Sequence
Ci a l - - -....
An
An
Figure 2b: DATA Polling Software Flow WRITE DATA
An
An
----- X28256 READY
An
An
0029-11
DATA Polling can effectively halve the time for writing to the X28256. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.
X28256
READY
0029-12
3-76
X28256, X282561
THE TOGGLE BIT I/Os Figure 3a: Toggle Bit Bus Sequence
::J iii LAST ,--------------------1J(- - - - - - - - - -
*Beginning and ending state of I/Os will vary.
0029-13
Figure 3b: Toggle Bit Software Flow
LAST WRITE
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28256 memories that is frequently updated. Toggle Bit testing can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for testing the Toggle Bit.
NO
READY
0029-14
3-77
X28256, X282561
HARDWARE DATA PROTECTION The X28256 provides three hardware features (compatible with X2864A) that protect nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse typically less than 20 ns will not initiate a write cycle.
� Default Vee Sense-All functions are inhibited when Vee is <S.3V, typically.
�Write Inhibit-Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-on and power-off, maintaining data integrity.
SOFTWARE DATA PROTECTION The X28256 offers a software controlled data protection feature. The X28256 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once Vcc was stable.
The X28256 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28256 is also protected from inadvertent and accidental writes in the powered-on state.. That is, the software algorithm must be issued prior to writing additional data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to sixty-four bytes of data.(10) Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
Note: (1 O) Once the three byte sequence is i~sued it n:iust be followed by a valid byte or page wnte operation.
3-78
X28256, X282561
SOFTWARE DATA PROTECTION Figure 4a: Timing Sequence-Byte or Page Write
Figure 4b: Write Sequence for Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
WRITE DATA AO TO
ADDRESS 5555 BYTE/PAGE LOAD ENABLED
WRITES OK
BYTE OR
PAGE
twc
-r------ WRITE
PROTECTED
0029-15
Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28256 will be write protected during power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE LAST BYTE TO
LAST ADDRESS
AFTER twc RE-ENTERS DATA PROTECTED STATE
0029-16
3-79
X28256, X282561
RESETTING SOFTWARE DATA PROTECTION Figure Sa: Reset Software Data Protection Timing Sequence
Figure Sb: Software Sequence to Deactivate Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
WRITE DATA 55 TO
ADDRESS 2AAA
WRITE DATA 80 TO
ADDRESS 5555
0029-17
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. The next time the X28256 is powered-up the device will be in the standard operating mode.
Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE DATA 55 TO
ADDRESS 2AAA
WRITE DATA 20 TO
ADDRESS 5555
0029-18
3-80
X28256, X282561
SYSTEM CONSIDERATIONS
Because the X28256 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X28256 has two power modes, standby and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high fre-
quency ceramic capacitor be used between Vcc and
GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
SYMBOL TABLE
WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
3-81
X28256, X282561
Normalized Active Supply Current vs. Ambie.nt Temperature
1.4 .--~---,--------~ Vcc=5.0V
0 1.2 .9
.0.....
N
::i
1.0
<
:IE
~
0z 0.8
0.6 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0029-19
Normalized Standby Supply Current vs. Ambient Temperature
1.4 ,---------,--------~ Vcc=5.0V
m 1.2 .J!I
.0.....
N
::i
1.0
<
:IE
~
zO� 0.8
0.6 ~---~-----~
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0029-20
3-82
256K
Commercial Industrial
X28C256 X28C2561
Electrically Erasable PROM
"Cll!
32K x 8 Bit
FEATURES � 150 ns Access Time � LOW Power CMOS
-60 mA Active Current Max. -200 �A Standby Current Max. � Fast Write Cycle Times -64-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 2.5 Sec.
Typical -Effective Byte Write Cycle Time: 78 �s
Typical � Software Data Protection � End of Write Detection
-DATA Polling -Toggle Bit � Simple Byte and Page Write -Single TTL Compatible WE Signal -Internally Latched Address and Data -Automatic Write Timing � High Reliability -Endurance: 10,000 Cycles -Data Retention: 100 Years � Upward Compatible with X2864A � JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The Xicor X28C256 is a 32K x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C256 is a 5V only device. The X28C256 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs.
The X28C256 supports a 64-byte page write operation, effectively providing a 78 �s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The X28C256 also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C256 includes a user-optional software data protection mode that further enhances Xicor's hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Refer to RR-515 for details of data retention characteristics for Xicor nonvolatile memories.
PIN CONFIGURATIONS
PLASTIC CERDIP
A,.
Vee
A12
WE
A1
A13
A1
Ae
As
A1
A4
A11
A3
OE
A2
A10
A1
ce
Ao
1101
l/Oo
110.
1/01
I/Os
1/02
1/04
Vss
1/03
0098-1
PLCC
~; 1 "1. ~I~ .."r'
A1 Ao NC l/Oo
14 15 16 17 18 19 20
As Ag
A11 NC
5E
A10
cr
1/07 I/Os
- N C/l (.) t') -.t Ill
~~~z~~~
0098-2
<i~f01
1/02 @
1/03 @
rsj/05
@1/05
(IJ{Oo @Ao 4@Vss rsi/04 @9~
0 � A1
A2
X28C256
CE
@
@/10
(BOTTOM VIEW)
0 A3 �A4
@t"2 @3/11
@/8 As
�
<J/12
@Vee 8
@/9
G/7 A5
0
0 A14
iYE
@
@6/13
PIN NAMES
0098-21
Ao-A14 l!Oo-1107 WE CE OE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
3-83
X28C256, X28C2561
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
x2ac2ss .............................. -10�c to +as�c
x2ac2ss1 ............................. -
Storage Temperature .................... -
ss�c
65�C
to to
+ +
13s�c
150�C
Voltage on any Pin with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to + 7V
D.C. Output Current .................................. 5 mA
o Lead Temperature (Soldering, 1 Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause. permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X28C256 TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified. X28C2561 TA = -40�C to + 85�C, Vee = + 5V � 10%, unless otherwise specified.
Symbol
Parameter
Limits Min. Typ.(1) Max.
Units
Test Conditions
Ice
Vee Current (Active)
(TTL Inputs)
60
mA CE = OE = VIL� WE = V1H
All l/'.O's = Open
Address Inputs = TTL Levels@ f = 5 MHz
lss1
Vcc Current (Standby)
(TTL Inputs)
2
mA CE = V1H. OE = V1L
All I/O's = Open, Other Inputs = V1H
lss2 Vcc Current (Standby) (CMOS Inputs)
100
200
�A CE = Vee - 0.3V, OE = GND
All I/O's= Open, Other Inputs= Vee - 0.3V
lu
Input Leakage Current
10
�A V1N = GND to Vee
ILO V1L(2) V1H(2) Vol VoH
Output Leakage Current
Input Low Voltage
-1.0
Input High Voltage
2.0
Output Low Voltage
Output High Voltage
2.4
10
�A VouT = GND to Vee. CE = V1H
0.8
v
Vee +1.0 v
0.4
v loL = 2.1 mA
v loH = -400 �A
ENDURANCE AND DATA RETENTION
Parameter
Min.
Minimum Endurance
10,000
Data Retention
100
Max.
Unit Cycles/Byte
Years
Condition Reliability Report-520 Reliability Report-515
POWER-UP TIMING Symbol tpuR(3) tpuw(3)
Parameter Power-Up to Read Operation Power-Up to Write Operation
Max. 100
5
Units �s ms
CAPACITANCE TA = 25�C, f = 1.0 MHz, Vee = 5V
Symbol
C11o(3>
C1N(3)
Test Input/Output Capacitance Input Capacitance
Max. 10 6
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) V1L min. and V1H max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.
Units pF pF
Conditions V110 = OV V1N = OV
3-84
X28C256, X28C2561
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour D1N HighZ
-
Power Active Active Standby
-
A.C. CHARACTERISTICS X28C256 TA = 0�C to + 70�C, Vcc = + 5V � 10%, unless otherwise specified. X28C2561 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
tRc tcE tAA toE tLz(4) toLz(4) tHz(5) toHz(5)
toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
X28C256-15 X28C2561-15
Min. Max.
150
150
150
50
0
0
0
50
0
50
0
X28C256-20 X28C2561-20
Min. Max.
200
200
200
80
0
0
0
50
0
50
0
X28C256-25 X28C2561-25
Min. Max.
250
250
250
100
0
0
0
50
0
50
0
X28C256 X28C2561
Min. Max.
300
300
300
100
0
0
0
50
0
50
0
Units
ns ns ns ns ns ns ns ns ns
Read Cycle
1------tnc-------~1
.._tCE~
OE----- 1
0098-4
Notes: (4) tLz min. and toLz min. are shown for reference only, they are periodically characterized and are not tested. (5) tHz max. and toHZ max. are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. tHz min. and toHZ min. are shown for reference only, they are periodically characterized and are not tested.
3-85
X28C256, X28C2561
Write Cycle Limits Symbol twc(7> tAs tAH tcs tcH tcw toES
to EH
twp twPH twPH2(S) tov tos toH tow t s LC
Parameter Write Cycle Time Address Setup Time Address Holq Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE High Recovery SOP WE Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle
WE Controlled Write Cycle
Min.
0 150 0 0 100 10 10 100 200
1
50 10 10 1
Typ.(6)
5
Max. 10
1 100
Units ms ns ns ns ns ns ns ns ns ns �s �s ns ns �s �s
DATA OUT)()()()()----------------------H-IG-H-Z -------------------------~
0098-5
Notes: (6) Typical values are for TA = 25�C and nominal supply voltage. (7) twc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is� the maximum time the device requires to automatically complete the internal write operation. (8) twPH is tile normal page write operation WE recovery time. twPH2 is the WE. recovery time needed only after the end of issuing the three byte SOP command sequence and before writing the first byte of data to the array. Refer to Figure 4a which illustrates the twpH2 requirement.
3-86
X28C256, X28C2561
CE Controlled Write Cycle ADDRESS
..,._,OES_.
.__los---. ._,DH
0098-6
Page Write Cycle
� r - (9) OE [{11}7 Vl!I Wl2I '((jf!l Wl2I '@21
CE
\
Ill&
Ill&
!/!&
lllllA
l1llA
AXXXX (
'
WE
- - - - {10) �ADDRESS
110 xxxxxxxxxx:::x
x___
BYTEO BYTE1
BYTEn+1
BYTEn+2
twc---
0098-7
*For each successive write within the page write operation, A6 -A14 should be the same or writes to an unknown address could occur.
Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(10) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-87
X28C256, X28C2561
DATA Polling Timing Diagram(11)
Toggle Bit Timing Diagram
~--A-"--XXXXXXX
0098-9
*l/05 beginning and ending state will vary, depending upon actual twc.
SYMBOL TABLE
WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
Note: (11) Polling operations are by definition read cycles and are therefore subject to read cycle timings. 3-88
0098-8
OUTPUTS Will be steady
Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
X28C256, X28C2561
PIN DESCRIPTIONS
Addresses (A0-A 14) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (1/00-1107) Data is written to or read from the X28C256 through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28C256.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X28C256 allows the entire memory to be written in 2.5 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28C256 prior to the commencement of the internal programming cycle. The host can fetch data from another location within the system during a page write operation (change the source address), but the page address (As through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte� was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 �s.
Write Operation Status Bits The X28C256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the 110 bus as shown in Figure 1.
Figure 1: Status Bit Assignment
1t:_ o 110 ID~P~~'elv:~ 1 I J L - . TOGGLE BIT
DATA POLLING
0098-10
DATA Polling (1107) The X28C256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C256, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1107 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data. Note: If the X28C256 is in the protected state and an illegal write operation is attempted DATA Polling will not operate.
Toggle Bit (1106) The X28C256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/Os will toggle from one to zero and zero to one on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
3-89
X28C256, X28C2561
DATA POLLING 1/07 Figure 2a: DATA Polling Bus Sequence
X28C256
,-----. ---~ ---~ - - - - - . ,..-----... - - - - - READY
An
An
An
An
An
An
0098-11
Figure 2b: DATA Polling Software Flow
WRITE DATA
DATA Polling can effectively halve the time for writing to the X28C256. The timing diagram in Figure 2a illustrates the sequence of eivents on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.
0098-12
3-90
X28C256, X28C2561
THE TOGGLE BIT I/Os Figure 3a: Toggle Bit Bus Sequence
*Beginning and ending state of 1/06 will vary.
0098-13
Figure 3b: Toggle Bit Software Flow
LAST WRITE
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C256 memories that is frequently updated. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for testing the Toggle Bit.
NO
READY
0098-14
3-91
X28C256, X28C2561
HARDWARE DATA PROTECTION The X28C256 provides three hardware features (compatible with X2864A) that protect nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse less than 20 ns will not initiate a write cycle.
� Default Vcc Sense-All write functions are inhibited
when Vee is <S,,3V.
� Write Inhibit-Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-on and power-off, maintaining data integrity.
SOFTWARE DATA PROTECTION The X28C256 offers a software controlled data protection feature. The X28C256 is shipped� from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the .use of external circuits. The host would then have open read and write access
of the device once Vcc was stable.
The X28C256 can be automatically protected during power-up and power-down without the need for ext.ernal circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C256 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to sixty-four bytes of data.(12) Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
Note: (12) Once the three byte sequence is i~sued it ~ust be
followed by a valid byte or page wnte operation.
3-92
X28C256, X28C2561
SOFTWARE DATA PROTECTION Figure 4a: Timing Sequence-Byte or Page Write
Figure 4b: Write Sequence for Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
WRITE DATA 55 TO
ADDRESS 2AAA
WRITES
lwc
OK
BYTE OR
PAGE
WRITE PROTECTED
0098-15
Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28C256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C256 will be write protected during power-down and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE DATA AO TO
ADDRESS 5555
BYTE/PAGE LOAD ENABLED
WRITE DATA XX TO
ANY ADDRESS
WRITE LAST BYTE TO
LAST ADDRESS
AFTER twc
RE-ENTERS DATA PROTECTED STATE
0098-16
3-93
X28C256, X28C2561
RESETTING SOFTWARE DATA PROTECTION Figure Sa: Reset Software Data Protection Timing Sequence
Figure Sb: Software Sequence to Deactivate Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
0098-17
In the event the user wants to deactivate the software data protection feature for testing. or repro9ramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After twc. the X28C256 will be in standard operating mode.
Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE DATA 80 TO
ADDRESS 5555
WRITE DATA 55 TO
ADDRESS 2AAA
WRITE DATA 20 TO
ADDRESS 5555
0098-18
3-94
X28C256, X28C2561
SYSTEM CONSIDERATIONS
Because the X28C256 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit itis recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X28C256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vcc and
GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
FUNCTIONAL DIAGRAM
x
BUFFERS LATCHES
AND DECODER
256K-BIT E 2 PROM
ARRAY
Vee 0 - - Vss 0---.
0098-3
3-95
X28C256, X28C2561
Normalized Active� Supply Current vs. Ambient Temperature
1.4 ~---~----~ Vcc=5.0V
~ 1.2
0
i.J
N
:<:i
1.0
:I
Cl:
0z 0.8
0.6
-55
+25
+125
AMBIENT TEMPERATURE (CC)
0098-19
Normalized Standby Supply�current vs. Ambient Temperature
m 1.2
..!fl
0 i.J
~ 1.0 1----~~..,--------j <
:I Cl:
0z 0.8 ,___ _ __,_____ _ _ _----"'
0.6 '----...,..--'---------'
-55
+25
+125
AMBIENT TEMPERATURE (�C)
0098-20
3-96
ADVANCED INFORMATION
512K
Commercial Industrial
X28C512 X28C5121
Electrically Erasable PROM
64K x 8 Bit
FEATURES � Low Power CMOS
-50 mA Active Current Max. -500 �A Standby Current Max. � Enhanced, High Speed Page Write Operation � Fast Write Cycle Times -128-Byte Page Size -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 2.5 Sec. -Effective Byte Write Cycle Time: 39 �s � End of Write Detection -DATA Polling -Toggle Bit Testing Preferred for:
-Multiprocessor Applications -Large Memory Arrays -Interrupt Driven Systems � Software Data Protection
� Two PLCC Pinouts -X28C512-UVEPROM Replacements -X28C513-X28C256 Upgrades
� Inherent 100 + Years Data Retention
DESCRIPTION The Xicor X28C512 is a 64K x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C512 is a 5V only device.
The X28C512 supports a 128-byte page write operation, effectively providing a 39 �s/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512 also features DATA Polling and Toggle Bit testing, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512 supports the Software Data Protection option.
Xicor E2PROMs are designed and tested for applications requiring extended endurance.
PIN CONFIGURATIONS
SIDE BRAZE FLAT PACK
PLCC LCC
PLCC LCC
As A4
A2
Ao l/Oo 1/01 1/02
Yss
A14 A13 As Ag A11
6E
A10
CE
1/07 1/05 1/05 1/04 1/03
0117-1
0117-2
0117-3
PIN NAMES
Ao-A15 1/0o-1/07 WE
CE
OE
Vee Vss
NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
3-97
i'�,,;
X28C512, X28C5121
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias x2scs12 ..........................�... -"lC>�C to:+ss�c x2scs121 ........�....... , ............ -ss�c to +1wc
Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Ground ............... , ......�. -1.0V to +7V
D.C. Output Current. ............................... ~ . 5 mA Lead Temperature
(Soldering, 1o Seconds) ...........................300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Rat-
ings" m~y cause permanent damage to the device. This is a stress rating only anq the functional op~ration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING. CHARACTERISTICS X28C512 TA = 0�C to + 70�C, Vcc = + 5V � 10%, unless otherwise specified. X28C5121 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
�Parameter
_.
Limits
Min~
Max.
Units
Test Conditions
Ice
Vee Current (Active)
(ITL Inputs)
50
rilA CE = OE = V1L. WE = V1H
All I/O's :::;:�Open
Address Inputs= ITL Levels@ f = 5 MHz
lss1
Vcc Current (Standby)
(ITL IQputs)
3
mA CE = VIH� OE = V1L
All I/O's = Open, Other Inputs = V1H
lss2
.Vcc Current (Standby)
(CMOS Inputs)
500
�A CE = Vee - 0.3V, OE = V1L
All I/O's = Open, Other Inputs = Vee
lu ILO V1L(1) V1H(1)
Vol VoH
Input Leakage Current
10
�A V1N = GND toVcc
Output Leakage Current
10
�A Vour =. (3ND to Vee. CE = V1H
Input Low Voltage
-1.0
0.8
v
Input High Voltage
v 2;0 Vee +1.0
Output Low Voltage
0.4
v loL = 2.1 mA
Output High Voltage
2.4
v loH = -400 �A
POWER-UP TIMING
Symbol tpuR(2) tpuw<2>
Parameter Power-Up to Read Operation Power-Up to Write Operation
Max. 100
5
Units �s ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
c11o<2>
C1N(2)
Test Input/Output Capacitance Input Capacitance
Max. 10 10
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
- Oulpurroa:a----~- trm:-rrale.a:na+
CL= 100pF�
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Notes: (1) V1L lllin. and V1H max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour D1N HighZ
-
Power Active Active Standby
-
3-98
X28C512, X28C5121
A.C. CHARACTERISTICS
X28C512 TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified.
X28C5121 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Read Cycle Limits Symbol
Parameter
tRc tcE tAA toE tLz(3) t0Lz<3> tHz(4) toHz(4)
toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
X28C512�20 X28C5121-20
Min.
Max.
200
200
200
50
0
0
50
50
0
X28C512�25 X28C5121�25
Min.
Max.
250
250
250
50
0
0
50
50
0
Read Cycle
1------tRc------..-.1
-4--lce
-4-loe__....
OE---~--..
Units
ns ns ns ns ns ns ns ns ns
,.__tAA~
0117-4
Notes: (3) tLz min. and tou min. are periodically sampled and not 100% tested.
(4) tHz max. and toHz max. are measured from the point.when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
3-99
X28C512, X28C5121
Write Cycle Limits Symbol twc<5) tAs tAH tcs tcH tcw toES toEH twp twPH tov tos toH tow t s LC
Parameter Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE High Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle
Min.
0 50 0 0 100 10 10 100 100
50 10 10 0.20
Max. 10
1 200
Units ms ns ns ns ns ns ns ns ns ns �s ns ns �s �s
WE Controlled Write Cycle
ADDRESS
0117-5
Note: (5) twc is the minimum cycle time from the system perspective; it is the maximum time the device requires to perform the internal write operation.
3-100
X28C512, X28C5121
CE Controlled Write Cycle ADDRESS
.--toes_..
DATA VALID ......._los-----. .-toH
Page Write Cycle
0117-6
(6) OE [l/l}J Vlll Vlll '<(jf!J WZZI WZZl ~r-
Cl
r \ fl1A Ill& If/A A A l.XXXX 5
WE
- - - - (7} �ADDRESS
vo xxxxxxxxxx::::x___x ~--- ---- ~---->---+---
BYTE 0 BYTE 1
BYTE 2
BYTE n
BYTE n+ 1
BYTE n+2
twc---
0117-7
*For each successive write within the page write operation, ArA15 should be the same or writes to an unknown address could occur.
Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can~ done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
3-101
X28C512, X28C5121
DATA Polling Timing Diagram(S)
Toggle Bit Timing Diagram
0117-8
*1/06 beginning and ending state will vary. Note: (8) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
SYMBOL TABLE
WAVEFORM
xxxxx
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
0117-9
OUTPUTS Will be steady
Will change from Low to High Will change
from High to
Low Changing: State Not Known Center Line is High Impedance
3-102
X28C512, X28C5121
PIN DESCRIPTIONS
Addresses (Ao-A15) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW �to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1/07) Data is written to or read from the X28C512 through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28C512.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C512 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X28C512 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28C512 prior to the commencement of the internal programming cycle. The host can fetch data from another location within the system during a page write operation (change the source address), but the page address (A7 through A1s) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was writ~ ten. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 200 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 200 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 200 �s.
Write Operation Status Bits The X28C512 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the 1/0 bus as shown in Figure 1.
Tt I:'�::~:: Figure 1: Status Bit Assignment
VO
4
I
DATA POLLING
0117-10
DATA Polling (1/07) The X28C512 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C512, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1107 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 will reflect true data.
Toggle Bit (1/06) The X28C512 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle 1/06 will alternate between one and zero on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
3-103
X28C512, X28C5121
DATA POLLING 1/07 Figure 2a: DATA Polling Bus Sequence
LAST
WE W_RI_TEJ1~--------------------------~r-------------t-
X28C512
:E:X X X X Ao-A15
- - - ---"' ,.------ ___,...r,___"" ,---"i- READY
An
An
An
An ) ,.__An_ _ "--A_n_"i-
0117-11
Figure 2b: DATA Polling Software Flow
WRITE DATA
DATA Polling can effectively halve the time for writing to the X28C512. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.
X28C512
READY
0117-12
3-104
X28C512, X28C5121
THE TOGGLE BIT I/Os Figure 3a: Toggle Bit Bus Sequence
LAST
WRITE/r----------------------------------~P.----------------"'l'-
WE -..J
*Beginning and ending state of I/Os will vary.
X28C512
READY
0117-13
Figure 3b: Toggle Bit Software Flow
LAST WRITE
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C512 memories that is frequently updated. Toggle Bit testing can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for testing the Toggle Bit.
NO
READY
0117-14
3-105
X28C512, X28C5121
HARDWARE DATA PROTECTION The X28C512 provides three hardware features that protect nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse typically less than 10 ns will not initiate a write cycle.
� Default Vee Sense-All write functions are inhibited when Vee is ::;;;3.8V.
�Write Inhibit-Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-on and power-off, maintaining data integrity. Write cycle timing specifications must be observed concurrently.
SOFTWARE DATA PROTECTION The X28C512 offers a software controlled data protection feature. The X28C512 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once Vcc was stable.
The X28C512 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C512 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three byte enable sequence is not written to the memory array.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
3-106
X28C512, X28C5121
SOFTWARE DATA PROTECTION Figure 4a: Timing Sequence-Software Data Protect Enable Sequence Followed by Byte or Page Write
Vee f""1
ov _J
DATA ADDRESS
~
Cf
AA 5555
55 2AAA
AO 5555
WRITES OK
BYTE OR PAGE
NOTE: All other timings and control pins are per page write timing requirements.
~(Vee>
WRITE PROTECTED
0117-15
Figure 4b: Write Sequence for Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
WRITE DATA 55 TO
ADDRESS 2AAA
Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C512 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28C512 will be write protected during power-down. and after any subsequent power-up. The state of A15 while executing the algorithm is don't care.
Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE DATA AO TO
ADDRESS 5555
r----- -----,
WRITE DATA XX TO
ANY ADDRESS
WRITE LAST BYTE TO
LAST ADDRESS
OPTIONAL BYTE/PAGE LOAD OPERATION
AFTER twc
RE-ENTERS DATA PROTECTED STATE
0117-16
3-107
X28C512, X28C5121
RESETTING SOFTWARE DATA PROTECTION Figure Sa: Reset Software Data Protection Timing Sequence
Vcc
-~--------------------------------------~1~S--=i---+---
DATA AA
55
80
AA
55
20
~ twc
STANDARD OPERATING
ADDRESS 5555
2AAA
5555
5555
2AAA
5555
MODE
~
NOTE: All other timings and control pins are per page write timing requirements.
0117-17
Figure Sb: Software Sequence to Deactivate Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
I
WRITE DATA 55 TO
ADDRESS 2AAA
I
WRITE DATA' 80 TO
ADDRESS 5555
!
WRITE DATA AA TO
ADDRESS 5555
I
WRITE DATA 55 TO
ADDRESS 2AAA
j.
WRITE DATA 20 TO
ADDRESS 5555
0117-18
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After twc. the X28C512 will be in standard operating mode. The state of A15 while executing the algorithm is don't care.
Note: Once initiated, the sequence of write operations should not be interrupted.
3-108
X28C512, X28C5121
SYSTEM CONSIDERATIONS
Because the X28C512 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the X28C512 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between Vcc and GND at each device. Depending on the size of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4. 7 �F electrolytic bulk capacitor be placed between Vee and GND for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
FUNCTIONAL DIAGRAM
�,-�,. { x BUFFERS LATCHES AND DECODER
512K E2PROM ARRAY
~-��{
y
BUFFERS LATCHES
AND DECODER
1/0 BUFFERS AND LATCHES
cr
OE
WE
Vee o-+ Vsso-+
CONTROL LOGIC AND TIMING
0117-19
3-109
NOTES
3-110
FACT SHEET
1M
Commercial
X28C010
Electrically Erasable PROM
liCI'
128K x 8 Bit
FEATURES � 200 ns Access Time � LOW Power CMOS
-80 mA Active Current Typical -500 �A Standby Current Typical � Fast Write Cycle Times -128-Byte Page Write Operation -Byte or Page Write Cycle: 5 ms Typical -Complete Memory Rewrite: 5 Sec. Typical -Effective Byte Write Cycle Time: 39 �s
Typical � Software Data Protection � End of Write Detection
-DATA Polling -Toggle Bit � Simple Byte and Page Write -Single TTL Compatible WE Signal -Internally Latched Address and Data -Automatic Write Timing � JEDEC Approved Byte-Wide Pinout
PIN CONFIGURATION
DESCRIPTION
The Xicor X28C01 O is a 12SK x 8 E2PROM, fabricated with Xicor's proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable nonvolatile memories the X28C01 O is a 5V only device. The X28C01 O features the JEDEC approved pinout for byte-wide memories, compatible with industry standard EPROMs.
The X28C010 supports a 128-byte page write opera-
tion, effectively providing a 39 �s/byte write cycle and enabling the entire memory to be typically written in less than 5 seconds. The X28C010 also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. In addition, the X28C01 O includes a user-optional software data protection mode that further enhances Xicor's hardware write protect capability.
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 1O years.
FUNCTIONAL DIAGRAM
Ao-A1& ADDRESS
INPUTS
x
BUFFERS LATCHES
AND DECODER
1M�BIT E2PROM ARRAY
PIN NAMES
0084-1
Ao-A15 llOo-1107 WE
CE
OE
Vee
Vss
NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable
+5V Ground No Connect
3-111
0084-2
X28C010
PIN DESCRIPTIONS
Addresses (Ao-A16) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (1/00-1/07)
Data is written to or read from the X28C01 o through
the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the X28C010.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE
ar:.._!:OW and OE is HIGH. The X28C01 o supports both
a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, wilt automatically continue to completion, typically within 5 ms.
Page Write Operation The page write feature of the X28C010 allows the entire memory to be written in 5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28C010 prior to the commencement of the internal programming cycle. The host can fetch data from another location within the system during a page write operation (change the source address), but the page address (A7 through A1 s) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the~ling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so tong as the host continues to access the device within the byte load cycle time of 100 �s.
Write Operation Status Bits
The X28C01 O provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
1/0 bus as shown in Figure 1.
Fi I l::.l.:J i Figure 1: Status Bit Assignment
uo
5 4
I1 0
TOGGLE BIT DATA POLLING
0084-3
DATA Polling (1/07) The X28C01 O features DATA Potting as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C01 O, eliminating additional. interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1/07 wilt reflect true data. Note: If the X28C010 is in the protected state and an illegal write operation is attempted DATA Polling wilt not operate.
Toggle Bit (I/Os) The X28C010 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle 1/06 will toggle from one to zero and zero to one on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
3-112
X28C010
HARDWARE DATA PROTECTION The X28C01 O provides three hardware features that protect nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse less than 20 ns will not initiate a write cycle.
�Default Vee Sense-All functions are inhibited when Vee is s3V.
�Write Inhibit-Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-on and power-off, maintaining data integrity.
SOFTWARE DATA PROTECTION The X28C01 O offers a software controlled data protection feature. The X28C010 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once Vcc was stable.
The X28C010 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C010 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. The three byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
3-113
NOTES
3-114
X9MME, X9MMEI ........................ .
4-1
liCI'
INOVRAM* Data Sheets
Serial Products Data Sheets
IE2PROM Data Sheets
c ) E2PQTTM Data Sheets
PRELIMINARY INFORMATION
.iCll!
Commercial Industrial
X9MME X9MMEI
E2POTTM Digitally Controlled Potentiometer
FEATURES � Solid State Reliability � Single Chip MOS Implementation � Three Wire TTL Control � Operates From Standard 5V Supply � 99 Resistive Elements
-Temperature Compensated - � 20% End to End Resistance Range � 100 Wiper Tap Points -Wiper Position Digitally Controlled -Wiper Position Stored in Nonvolatile
Memory Then Automatically Recalled on Power-Up � 100 Year Wiper Position Retention � 8 Pin Mini-DIP Package � 14 Pin SOIC Package
DESCRIPTION The Xicor X9MME is a solid state nonvolatile potentiometer and is ideal for digitally controlled resistance trimming.
The X9MME is a resistor array composed of 99 resistive elements. Between each element and at either end are tap points accessible to the wiper element. The position of the wiper element on the array is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and is recalled upon a subsequent power-up.
The resolution of the X9MME is equal to the maximum resistance value divided by 99. As an example; for the X9503 (50 KO) each tap point represents 5050.
Xicor E2 products are designed and tested for applications requiring extended endurance. Refer to Xicor reliability reports for further endurance information.
PIN CONFIGURATIONS PLASTIC
INC
Vee
uio
cs
VH
VL
Yss
Vw
0039-1
SOIC
PIN NAMES
VH High Terminal of Pot
NC
NC
Vw Wiper Terminal of Pot
INC
Vee
VL Low Terminal of Pot
U/D
cs
Vss Ground
NC
NC
Vee System Power
VH
VL
U/D Up/Down Control
Yss NC
Vw
NC
INC Wiper Movement Control
cs Chip Select for Wiper
Movement/Storage
0039-12
NC No Connect
4-1
X9MME~ X9MMEI
ANALOG CHARACTERISTICS
Electrical Characteristics End to End Resistance Tolerance .................... � 20% Power Rating at 25�C
X9102� ........................................... 16mW X9103, X9503 and X9104 ......................... 10 mW Wiper Current ................................ � 1 mA Max. Typical Wiper Resistance ..................... .40fl at1 mA Typical Noise
X9102 ............. ; ............ < -120 dB/.JHz Ref: 1V . X9103, X9503 and X9104 ; ....... ; . < -95 dB/.JHz Ref: 1V
Resolution Resistance ........................................... 1�/o
Linearity Absolute Linearity(1) ............................. � 1.0 M1(2) Relative Linearity(3) ............................. � 0.2 Ml(2)
Temperature Coefficient
.:...:40�C to + 85�C
X9102 ... ,, ......................... � 600 ppml�C Typical X9103, X9503 and X9104 ........... � 300 ppml�C Typical Ratiometric Temperature Coefficient ............... � 20 ppm
Wiper Adjustabillty Unlimited Wiper Adjustment
(Volatile Mode While Chip is Selected) Nonvolatile Storage of Wiper Position
................................... 10,000 Cycles Typical
� Environmental Characteristics �
Temperature Range
�
Operating X9MME ........................0�c to + 10�c
X9MMEI : ..... :.'. ... '. ........ -.40�C to .+~.5�C
Storage .............................. -65�C to + 1so�c
Physical Characteristics Marking Includes:
Manufacturer's Trademark Resistance Value or Code Date Code
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . . . . . . . -65�C to+ 135�C
Storage Tel!!Q_erature . ,_, ................. - 65�C to + 150�C
+ Voltage on CS, INC, U/D and Vee
� �
Referenced to Ground ......�..�.. ~ ...... -1.0V to 7.0V
Voltage on VH and VL
�
Referenced to Ground� ................... -8.0V to + 8.0V Lead Temperature (Soldering, 1o Seconds) .......... + 3P0�C
Wiper Current .............................. : ...... � 1 mA
t:.V = IVH - Vd
X9102., ............ �.. , ................................4V
X9103, X9503 and X9104 ............................ 10V
*COMMENT.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those .indicated in the operational sections of this specification. is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
X9MME TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X9MMEI TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
Symbol
Ice lu V1H V1L Rw VvH(5) VvL(5) C1N(6)
Parameter
Supply Current Input Leakage Current Input High Voltage Input Low Voltage Wiper Resistance VHVoltage vL Voltage CS, INC, U/D, Input Capacitance
Min.
2.0 -1.0 -5.0 -5.0
Limits typ.(4)
25
40 .::_
Max. 35 �10
Vcc+1.o 0.8 100 +5.0 +5.0 10
Units
mA �A v v
n
v
v
pF
Test Conditions V1N = av to 5.5V,. INC, U/D, cs �1 mA
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
Absolute Linearity = (Vw(n)(actual) - Vw(n)(expected)) = � 1 Ml Max.
(2)
1 Ml
=
RrOT/99 or
VH -VL - --
=
Minimum Increment.
99
(3) Relative Linearity is utilized to determine the actual change in voltage between successive tap position when used as a potentiometer. It is a measure of the error in step size.
Relative Linearity = Vw(n+1) - [Vw(n) + Ml] = �0.2 Ml Max.
Typical values of Linearity are shown in Figures 3, 6, 9 and 12.
(4) Typical values are for TA = 25�C and nominal supply voltage.
(5) t:.V for X9102 = IVH - Vd s4V. t:N tor X9103, X9503 and X9104 = IVH - Vd s10V.
(6) This parameter is periodically sampled and not 100% tested.
4-2
X9MME, X9MMEI
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input
OVto 3.0V 10 ns 1.5V
MODE SELECTION
cs
INC
U/D
L
~
H
L
~
L
_r
H
x
A.C. CHARACTERISTICS
X9MME TA= 0�C to +70�C, Vee= +sv �10%, unless otherwise specified.
X9MMEI TA= -40�C to +85�C, Vee= +5V � 10%, unless otherwise specified.
Symbol
Parameter
Limits
Min.
Typ.(7)
tc1
CS to INC Setup
100
t10
INC High to U/D Change
100
trn
U/D to INC Setup
2.9
t1L
INC Low Period
1
t1H
INC High Period
3
tic
INC Inactive to CS Inactive
1
tcPH
CS Deselect Time
20
t1w
INC to Vw Change
100
Mode Wiper Up Wiper Down Store Wiper Position
Max. 500
Units
ns ns �s �s �s �s ms �s
A.C. Timing
let
,..-----.i~-
ul6
Note: (7) Typical values are for TA = 25�C and nominal supply voltage.
0039-3
4-3
X9MME, X9MMEI
PIN DESCRIPTIONS
VH
The high terminal of the X9MME is capable of handling
an input voltage from -5V to + 5V.
VL
The low terminal input is limited from - 5V to + 5V~
Vw
The wiper terminal series resistance is :typically less than 400. The value of the wiper is controlled by. the use of U/D and� INC.
Up/Down (U/D) The U/D input controls the direction of the wiper movement and the value of the nonvolatile counter.
Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input
Chip Select (CS) The device is selected when the CS input is LOW. The current counter value. is stored in nonvolatile memory
when CS is returned HIGH with INC HIGH;
DEVICE OPERATION
The INC, U/D and CS inputs control the movement of the wiper along the resistor array.. HIGH to LOW tran-
sitions on INC, with CS LOW, increment (UiD == HIGH)
or decrement (U/D = LOW) an internal counter. The
output of the counter is decoded to position the wiper. When CS is brought HIGH the counter value is automatically stored in the nonvolatile memory. Upon power-up the nonvolatile memory contents are restored to the counter.
With the wiper at position 99,. additional . increments
(U/D = HIGH) will not move the wiper. With the wiper at position 0, additional decrements (U/D = LOW) will
not move the wiper.
The state of U/D may be changed while CS remains LOW, allowing a gross then fine adjustment during system calibration.
If Vcc is removed while CS is LOW the contents of the
nonvolatile memory may be lost
The end to end resistance of the array will fluctuate once Vee is removed.
APPLICATIONS The combination of a digital interface and nonvolatile memory in a silicon based trimmer pot provides many application .opportunities that could not be addressed by either mechanical potentiometers or digital to analog circuits~ The X9MME addresses and solves many issues that are of concern to designers of a wide range of equipment.
Consider the possibilities:
Automated assembly line calibration versus mechanical tweaking of potentiometers.
Protection against drift due to vibration or contamination.
Eliminate precise alignment of PWB mounted potentiometers with case access holes.
Eliminate unsightly access holes on otherwise aesthetically pleasing enclosures.
Product enhancements such as keyboard adjustment of volume or _brightness control.
Front panel microproce~sor controlled calibration of test instruments.
Remote location calibration via radio, modem or LAN link.
Calibration of hard to reach instruments in aircraft or other confined spaces. �
APPLICATION CIRCUITS Application Circuit # 1
v=h.:.:
��v,
<>039-4
Approximating audio trim with external resistor.
Application Circuit # 2
VHbVw
VL
0039-5
Utilizing the X9MME as a variable resistor.
Note: Maximum Wiper Current = 1 mA.
4-4
X9MME, X9MMEI
Figure 1: Typical Frequency Response for X9102
9
6
3
,...., 0
CD
~
z< -3
(.!)
.0.... -6
N
:-:<:i
:::::E
-9
Q::
0 z
-12
-::
-15
-,
-18
-::
-21
0.01
I
0.10
T l"TTl 1.00
T 10.00
I
T
I
100.00 1000.00 10000.00
FREQUENCY IN KHz
TEST CONDITIONS Vee= 5.ov Temp.= Room Wiper@ Tap 50 VH = 0.5V RMS Normalized (0 dB @ 1 KHz) Test Circuit # 1
0039-13
Figure 2: Typical Total Harmonic Distortion for X9102
1.2--+-----+-----+----+------t-----+---
g
:0c 1.0--+-----+-----+----+------t-----+--_..,
I-
0.8--+-----+----+----+------t-----+----
0.6-+---+----+----+------+----+---1-1
TEST CONDITIONS Vee= 5.0V Temp.= Room Wiper@ Tap 50 VH = 2V RMS Test Circuit # 1
0.01
0.10
1.00
10.00 100.00 1000.00 10000.00
FREQUENCY IN KHz
0039-14
4-5
X9MME, X9MMEI
Figure 3: Typical Linearity for X9102
10
8
'j
6
4
Ill::
0
c [l
Ill::
I..l.l:..:
2 -'
.....
<.:>
z~.....
0 -
(.)
I.l.l.:.:.
-2
IL
-4
I ...
-6
-8
-10
o
1o 20
30 40 50 so .10 .80
WIPER POSITION
90 mo
TEST CONDITIONS Vee= 5.0V Temp.= Room
Test Circuit # 2
KEY: �----�=ABSOLUTE - - - = RELATIVE
0039-9
0039-15
Figure 4: Typical Frequency Response for X9103
9
6
.3
,..... 0
m ~
<z -3
<.:>
.0.... -6
N
:<:i
~
-9
Ill::
0z -12
-15
-18
-21 0.01
T 0.10
.
---
~
1-,
T 1.00
T 10.00
T
T
100.00 1000;00
FREQUENCY IN KHz
TEST CONDITIONS Vee= 5.ov Temp.= Room Wiper @ Tap 50 VH = 0.5V RMS
Normalized (0 dB @ 1 KHz) Test Circuit # 1
0039-6
4-6
X9MME, X9MMEI
Figure 5: Typical Total Harmonic Distortion for X9103
2.0
1.8
1.6
1.4
1.2
g
Q 1.0 :::c
I-
0.8
0.6
0.4
0.2
0.0 lL' T
0.01
0.10
I
1.00
.J-
6 ~ ~
T
I
I
10.00 100.00 1000.00
FREQUENCY IN KHz
TEST CONDITIONS Vee= 5.0V Temp.= Room Wiper@ Tap 50
VH = 2V RMS Test Circuit # 1
0039-7
Figure 6: Typical Linearity for X9103
10
8
6
4
~
0
~
.~ .... .....
(!)
.z~....
2
"!!_ A--J- 0
~ . l l~Vi~- ywy
JJUlfJIU1rn.:
~--
(.)
.~ ....
-2
a..
-4
-6
-a
-10 0
10 20 30 40 50 60 70 80 90 100 WIPER POSITION
TEST CONDITIONS Vee= 5.ov Temp.= Room Test Circuit # 2
KEY: ------=ABSOLUTE - - - = RELATIVE
0039-9
0039-8
4-7
X9MME, X9MMEI
Figure 7: Typical Frequency Response for X9503
9
-:
6 -:
3
--:
m 0
~
z
<
-3
C>
0 UJ
-6
N
::J
< :a:::::E:
-9
0 z
-12
-15
-18
-21 0.01
I
0.10
I
1.00
~
\J
1
\
_l
I
T
~
10.00
100.00 1000.00
TEST CONDITIONS Vee= 5.ov Temp.= Room Wiper@ Tap 50 VH = 0.5V RMS Normalized (0 dB @ 1 KHz) Test Circuit # 1
FREQUENCY IN KHz
0039-16
Figure 8: Typical Total Harmonic Distortion for X9503
2.0
1.8
1.6 """
1.4
-:
1.2
g
0 1.0
:..I.:.
0.8
0.6
0.4
0.2
1"'"
0.0 0.01
T
0.10
T
1.00
LA.
If
~
J
T
T
10.00 100.00
T
1000.00
FREQUENCY IN KHz
TEST CONDITIONS Vee= 5.0V Temp. = Room Wiper @ Tap 50 VH = 2V RMS Test Circuit # 1
0039-17
4-8
X9MME, X9MMEI
Figure 9: Typical Linearity for X9503
0::: 0 0:::
0w::: w
(.!)
uzw~
a0w:.:.:
TEST CONDITIONS Vee= 5.ov Temp.= Room Test Circuit #2
KEY: - - - - - �=ABSOLUTE - - - = RELATIVE
0039-9
0 10 20 30 40 50 60 70 80 90 100 WIPER POSITION
0039-18
Figure 10: Typical Frequency Response for X9104
9
6
3
-
,_ ,......_
0
m
3
-:
z -3
<
(.!)
--::
cw -6
N
:<J
:::::E
-9
0:::
0 z
-12
-15
-18 -,:
-21
0.01
I
0.10
T
1.00
~
~
~
\
-1,
r
I
10.00
100.00
1000.00
TEST CONDITIONS Vee= 5.0V Temp.= Room Wiper @ Tap 50 VH = 0.5V RMS Normalized (0 dB @ 1 KHz) Test Circuit # 1
FREQUENCY IN KHz
0039-19
4-9
X9MME, X9MMEI
Figure 11: Typical Total Harmonic Distortion for X9104
2.0
1.8
1.6
1.4
1.2
g
0 1.0
:..I.:.
0.8
0.6
0.4
0.2
lo..
0.0 0.01
I
0.10
TEST CONDITIONS Vee= 5.0V Temp. = Room Wiper @ Tap 50 VH = 2V RMS Test Circuit # 1
~
I
I
1.00
10.00
l
l
'vj~
I
I
I
100.00 1000.00 10000.00
FREQUENCY IN KHz
0039-20
Figure 12: Typical Linearity for X9104
TEST CONDITIONS Vee= 5.ov Temp. = Room Test Circuit #2
IX
0
IX
.I.X...
.....
(.!)
KEY:
~.z....
- - - - - - =ABSOLUTE
u
.I.X...
- - - = RELATIVE
0039-9
D..
-10--4i~.rpTTT,tmr.,rrrrr1TITrfrrrrfiTTTfTrrrtnTrfTTrrlniTfTTTTj-t-rnrpTTTtn"rr1fTTTTITITrfrrrrtiTTTfTn-ri
0 10 20 30 40 50 60 70 80 90 100
WIPER POSITION
0039-21
4-10
X9MME, X9MMEI
Test Circuit # 1
~TEST POINT Vw 0039-10
Test Circuit # 2
()VH
:~.rEST POINT
::~~~>>>==�
v W FORCE -CURRENT
-==v-L
0039-11
Standard Parts Minimum Resistance 400 400 400 400
FUNCTIONAL DIAGRAM
Wiper Increments 10.10 1010 5050 10100
Maximum Resistance 1 KO
10 KO 50KO 100 KO
Part Number X9102 X9103 X9503 X9104
7 BIT COUNTER
TRANSFER ARRAY LOGIC
NONVOLATILE MEMORY
WIPER POSITION DECODE
PROGRAMMING CONTROL AND
POWER-ON DETECT
Vee
GND-----'
Vt. 1.-------Vw
0039-2
4-11
NOTES
4-12
X88C64, X88C641 ........................ .
5-1
)lic1,
INOVRAM* Data Sheets
Serial Products Data Sheets
IE2PROM Data Sheets IE2POTTM Data Sheets
Microcontroller Peripheral Products
PRELIMINARY INFORMATION
64K
Commercial Industrial
X88C64 X88C641
E2 Micro-Peripheral
liCI'
8192 x 8 Bit
FEATURES � Concurrent Software Execution While
Writing -Dual Plane Architecture
Isolates Read/Write Functions Between Planes
Allows Continuous Execution of Code From One Plane While Writing in the Other Plane
� Multiplexed Address/Data Bus -Direct Interface to Popular 8-Bit Microcontrollers, e.g. Intel MCS�-51 Family Motorola M6801/03, M68HC11 Family
� High Performance CMOS -Fast Access Time, 120 ns -Low Power 40 mA Active 100 �A Standby
� Software Data Protection -Protect Entire Array During Power-Up/-Down
� Block Protect Register -Individually Set Write Lock Out in 1K Blocks
�Toggle Bit -Early End of Write Detection
PIN CONFIGURATION
NC A12
NC NC
WC
PSEN A/DO A/01 A/02 A/03 A/04
Yss
1
2
23
3
22
4
21
5
20
6
7 X88C64 18
8
9
16
10
15
11
12
13
Yee
WR
ALE AB A9
A11
RB
A10
cr
A/07 A/06
A/DS
0125-1
� Page Mode Write -Allows up to 32 Bytes to be Written in One Write Cycle
DESCRIPTION
The X88C64 is an BK x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X88C64 features a Multiplexed Address and Data bus allowing direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry.
The X88C64 is internally configured as two independent 4K x 8 memory arrays. This feature provides the ability to perform nonvolatile memory updates in one array and continue operation out of code stored in the other array; effectively eliminating the need for an auxiliary memory device for code storage.
The X88C64 also provides a second generation software data protection scheme called Block Protect. Block Protect can provide write lockout of the entire device or selected 1K blocks. There are 8 1K x 8 blocks that can be write protected individually in any combination required by the user. Block Protect, in addition to the Write Control input, allows the different segments of the memory to have varying degrees of alterability in normal system operation.
PIN NAMES
ALE AD0-AD7 As-A12 RD WR PSEN CE WC
Vss
Address Latch Enable Address Inputs/Data 1/0 Address Inputs Read Input Write Input Program Store Enable Input Chip Enable Write Control Ground
MCS� is a registered trademark of Intel Corporation.
5-1
X88CS4, X88C641
FUNCTIONAL DIAGRAM
A12
CONTROL
LOGIC
SOFTWARE
--------...DATA
PROTECT
A12
x
~~ A8-
A L
D E
c
H E
s
0 D E
1K BYTES
A12
1K BYTES
1K BYTES
M
u
1K BYTES
1K BYTES
x
1K BYTES
1K BYTES
1K BYTES
Y DECODE .,_-----------t------
1/0 8c ADDRESS LATCHES AND BUFFERS
0125-2
PRINCIPLES OF OPERATION
The X88C64 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X88C64 provides 8K bytes of 5-volt E2PROM which can be used either for Program Storage, Data Storage or a combination of both in systems based upon Harvard (80XX) or Von Neumann (68XX) architectures. The X88C64 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the Address/Data bus to provide a "Seamless" interface.
The interface inputs on the X88C64 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. In the. Harvard type system, the reading of data from the chip is controlled either by the PSEN or the RD signal, which essentially maps the X88C64 into both the Program and the Data Memory address map.
The X88C64 is internally organized as two independent arrays of 4K bytes of memory with the A12 input selecting which of the two blocks of memory are to be accessed. While the processor is executing code out of
one block, write operations can take place in the other block; allowing the processor to continue execution of code out of the X88C64 during a byte or page write to the device.
The X88C64 also features an advanced implementation of the Software Data Protection scheme, called Block Protect, which allows the device to be broken into 8 independent sections� of 1K bytes. Each of these sections can be independently enabled for write operations; thereby allowing certain sections of the device to be secured so that updates can only occur in a controlled environment (e.g. in an automotive application, only at an authorized service center). The desired setup configuration is stored in a nonvolatile register, ensuring the configuration data will be maintained after the device is powered down.
The X88C64 also features a Write Control input, which serves as an external control over the completion of a previously initiated page load cycle.
The X88C64 also features the industry standard 5-volt E2PROM characteristics such as byte or page mode write and toggle-bit polling.
5-2
X88C64, X88C641
PIN DESCRIPTIONS Address/Data (AD0-AD7) Multiplexed low-order addresses and data. The Addresses flow into the device while ALE is HIGH. After ALE transitions from a HIGH to LOW the addresses are latched. Once the addresses are latched these pins input data or output data depending on RD, WR, PSEN and CE.
Addresses (As-A12) High order addresses flow into the device when ALE = V1H and are latched when ALE = VIL�
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH and ALE is HIGH, the X88C64 is placed in the low power standby mode.
Program Store Enable (PSEN) When the X88C64 is to be used in a MCS-51 based system, PSEN is tied directly to the microcontroller's PSEN output.
When the X88C64 is used in any other type of system, PSEN should be tied LOW.
Read (RD) When the X88C64 is to be used in a MCS-51 based system, RD is tied directly to the microcontroller's RD output. When used with a MC6801 or MC6803 the RD input is tied directly to the E output of the microcontroller.
Write (WR) When the X88C64 is to be used in a MCS-51 based system, WR is tied directly to the microcontroller's WR output. When used with a MC6801 or MC6803 the WR input is tied directly to the R/W output of the microcontroller.
Address Latch Enable (ALE) Addresses flow through the latches to address decoders when ALE is HIGH and are latched when ALE transitions from a HIGH to LOW.
Write Control (WC) The Write Control allows external circuitry to abort a page load cycle once it has been initiated. This input is useful in applications in which a power failure or processor RESET could interrupt a page load cycle. In this case, the microcontroller might drive all signals HIGH, causing bad data to be latched into the E2PROM. If the Write Control input is driven HIGH immediately
after Write (WR) goes HIGH, the write cycle will be aborted. When WC is LOW (tied to Vss) the X88C64 will be enabled to perform write operations. When WC is HIGH normal read operations may be performed, but all attempts to write to the device will be disabled.
DEVICE OPERATION
MCS-51 Modes Mixed Program/Data Memory By properly assigning the address spaces, a single X88C64 can be used as both the Program and Data Memory. This would be accomplished by connecting all the MCS-51 control outputs to the corresponding inputs of the X88C64.
In this configuration, one plane of memory could be dedicated to Program Store and the other plane dedicated to Data Store. The Data Store can be fully protected by enabling block protect write lock out.
-b131 EA/VP
-
r 19 X1
Tu X2
39 PO.O
38 P0.1
37 P0.2
36 P0.3 P0.4 35
34 P0.5 P0.6 33 P0.7 32
21 P2.0
22 P2.1 P2.2 23 P2.3 24 P2.4 25
PSEN 29 30
ALE
R5 17 WR 16
P2.X
80C31
7 A/DO
8 A/01
9 A/02
10 A/03
11 A/04
13 A/05
14 A/06
15 A/07
21 AB
20 A9
17 A10
19 A11
2 A12
c~
H
24
Yee
6 PSEN 22
ALE
18 R5 23 WR
16 cr
X88C64
0125-3
Program Memory Mode This mode of operation is read only. The PSEN and ALE inputs of the X88C64 are tied directly to the PSEN and ALE outputs of the microcontroller. The RD and WR inputs are tied HIGH.
5-3
X88C64, X88C641
When ALE is HIGH, the AD0-AD7 and Aa-A12 addresses flow into the device. The addresses, both low and high order, are latched when ALE transitions LOW (V1L). PSEN will then go LOW and after tPLDV� valid data is presented on the AD0-AD7 pins. CE must be LOW during the entire operation.
Data Memory Mode This mode of operation allows both read and write functions. The PSEN input is tied. to V1H or to Vee through a pullup resistor. The ALE, RD and WR inputs are tied directly to the microcontroller's ALE, RD and WR outputs.
Read This operation is quite similar to the Program Memory read. A HIGH to LOW transition on ALE latches the addresses and the data will be output on the AD pins after RD goes LOW (tRLDv).
Write A write is performed by latching the addresses on the falling edge of ALE. Then WR is strobed low followed by valid data being presented at the AD0-AD7 pins. The data will be latched into the X88C64 on the rising edge of WR.
MOTOROLA MEMORY MODE
Motorola 68XX operation is slightly different. The X88C64 internal logic requires PSEN to be tied to Vss; the microcontroller's AS, E and R/W outputs tied to the X88C64 ALE, RD and WR inputs respectively.
The falling edge of AS will latch the addresses for both a read and write operation. The state of R/W output determines the operation to be performed, with the E signal acting as a data strobe.
If R/W is HIGH and CE LOW (read operation) data will be output at ADo-AD7 after E transitions HIGH. If R/W and CE are LOW (write operation) data presented at AD0-AD7 will be strobed into the X88C64 on the HIGH to LOW transition of E.
19 XTAL
uf l EXTAL
9 > ~
~ MODA
.____, MODB
PCO 9
PC1 lO
11 PC2
12 PC3
13 PC4 PCS 14 PCS 15
16 PC7 PBO 42 PB1 41 PB2 40
39 PB3 PB4 38
35 PB7
4 AS
5 E
6 R/W
68HC11
7 A/DO
8 A/D1
9 A/D2
10 A/D3
11 A/D4
13 A/DS
14 A/D6
15 A/D7
21 A8
20 A9
17 A10
19 A11
2 A12
~ C"E
Q
H
24
Yee
22 ALE
18 R- D
23 -WR
-=-~ PSEN X88C64
0125-4
5-4
X88C64, X88C641
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
xaaC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 o�c to + 85�C xaaC641 .............................. - 65�C to + 135�C Storage Temperature .................... - 65�C to + 150�C
Voltage on any Pin with
Respect to Vss ........................... -1.0V to + 7V
D.C. Output Current ..................................5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS X88C64 TA= 0�C to +70�C, Vee= +5V �10%, unless otherwise specified. X88C641 TA = -40�C to + 85�C, Vee = + 5V � 10%, unless otherwise specified.
Symbol
Parameter
Limits
Min. Typ.
Max.
Units
Test Conditions
Ice
Vcc Current (Active)
lsB1(CMOS) Vcc Current (Standby)
50
80
200
mA CE = RD = VIL� All I/O's Open, Other Inputs =Vee
�A CE = V1L -0.3V, All I/O's Open, Other Inputs = Vee -0.3V
lsB2(TTL)
lu ILQ V1L V1H Vol VoH
Vee Current (Standby)
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1.0 2.0
2.4
6
mA CE = V1H. All I/O's Open,
Other Inputs = V1H
10
�A V1N = GND to Vee
10
�A Vour = GND to Vee. RD = V1H
0.8
v
Vee +o.5
v
0.4
v loL = 3.2 mA
v loH = -400 �A
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= 5V
Symbol
Parameter
C110 C1N
Input/Output Capacitance Input Capacitance
Max. 10 6
Units pF pF
Test Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OVto 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE PSEN RD WR Mode
110
Power
Vee
x
x
x Standby High Z Standby (CMOS)
V1H
x
x
x Standby High Z Standby (TTL)
V1L
V1L
V1H V1H Read
Dour Active
V1L
V1H
V1L V1H Read
V1L V1H V1H ....r Write
....r V1H V1H V1L Write
Dour D1N D1N
Active Active Active
5-5
X88C64, X88C641
A.C. CHARACTERISTICS
X88C64 TA = 0�C to + 70�C, Vee = + 5V � 10%, unless otherwise specified. X88C641 TA= -40�C to +85�C, Vee= +5V �10%, unless otherwise specified.
PSEN Controlled Read Cycle
Symbol
Parameter
Min.
Typ.
tELLL
Chip Enable Setup Time
7
tLHLL
ALE Pulse Width
80
tAVLL
Address Setup Time
20
tLLAX
Address Hold Time
30
tpLOX
PSEN to Output in High Z
0
tPHDX
Data Hold Time
0
~c
tPHDZ
PSEN Disable to Output in High Z
0
tpLDV
PSEN Read Access Time
120
PSEN Controlled Read Timing Diagram
Max.
Units ns ns ns ns ns ns ns ns
0125-5
5-6
X88C64, X88C641
RD Controlled Read Cycle
Symbol
Parameter
tELLL
Chip Enable Setup Time
tLHLL
ALE Pulse Width
tAVLL
Address Setup Time
tLLAX tRLDX
Address Hold Time
RD to Output in High Z
tRHDX tRHDZ
Data Hold Time
RD Disable to Output in High Z
tRLDV
RD Read Access Time
RD Controlled Read Timing Diagram
Min.
Typ. 7 80 20 30 0 0 0
120
Max.
Units ns ns ns ns ns ns ns ns
CE
ALE
0125-6
5-7
X88C64, X88C641
WR Controlled Write Cycle
Symbol
Parameter
tELLL
Chip Enable Setup Time
tLHLL
ALE Pulse Width
tAVLL
Address Setup Time
tLLAX
Address Hold Time
tovwH
Data Setup Time
twHDX
Data Hold Time
twLWH
WR Pulse Width
WR Controlled Write Timing Diagram
Min.
Typ. 7 80 20 30 50 20 50
Max.
J= ~i-tELLL
CE
---'
- tLHLL
~
I
tAVLL
-tl_LA_X__,_- - - - - - - - - - - - - - - - '
Dour
tovwH _ _ ___
ADDRESS ----tWLWH _ _ _ _,
1
WR
Units ns ns ns ns ns ns ns
0125-7
5�8
X88C64, X88C641
E Controlled Read Cycle
Symbol
Parameter
PW ASH
Address Strobe Pulse Width
tASL
Address Setup Time
tAHL
Address Hold Time
tAcc
Data Access Time
toHR
Data Hold Time
tcsL PWEH
CE Setup Time
E Pulse Width
E Controlled Read Cycle
Min.
Typ.
75 20 15 120 0 7 50
Max.
~-CS-L---------------------------~
ALE
Units ns ns ns ns ns ns ns
WR(R/W)
RD (E)
---PWEH---
0125-8
5-9
X88C64, X88C641
E Controlled Write Cycle
Symbol
Parameter
PW ASH
Address Strobe Pulse Width
tASL
Address Setup Time
tAHL
Address Hold Time
tosw
Data Setup Time
toHW
Data Hold Time
tcsL PWEH
CE Setup Time
E Pulse Width
E Controlled Write Cycle
Min.
Typ.
75 20 15 50 20 7 50
Max.
~~CS-L--------------------------._J~
PW ASH
ALE
Units ns ns ns ns ns ns ns
WR(R/W}
RD (E)
---PWEH---
0125-9
5-10
X88C64, X88C641
Page Write Operation Regardless of the microcontroller employed, the X88C64 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X88C64. Each individual write within a page write operation must conform to the byte write timing requirements. The falling edge of WR
(rising edge of E) starts a timer delaying the internal programming cycle 100 �s. Therefore, each successive write operation must begin within 100 �s of the last byte written. The following waveforms illustrate the sequence and timing requirements.
Page Write Timing Sequence for WR Controlled Operation
Operation CE
ALE ADO-AD7
A8-A12
Byte 0
Byte 1
Byte 2
Lost Byte
Read ; See Notes Below
After tWC Ready For Next Write Operation
~ --'"""""''1...f '\.--l~(.l'~'"--'~'-J'---1'---------1 ~~~-~~
Page Write Timing Sequence for E Controlled Operation
Operation
Byte 0
Byte 1
Byte 2
Last Byte
Read ; See Notes Below
0125-10
After tWC Ready For Next Write Operation
ALE
ADO-AD7 A8-A12 RD(E)
WR(R/W)
0125-11
Notes: (1) For each successive write within a page write cycle As-A12 must be the same. (2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page write operation. Two responses are possible:
a. Reading from the same half plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling
operation. b. Reading from the opposite half plane being written (A12 of Read =F A1 2 of Write) true data will be returned, facilitating the use of a single memory component as both program and data store.
5-11
X88C64, X88C641
Toggle Bit Polling Because the X88C64 typical write timing is less than the specified 1O ms, Toggle Bit Polling has been provided to determine the early end of write. During the internal programming cycle 1/06 will toggle from one to zero and zero to one on subsequent attempts to read the device. When the internal cycle is complete the
Toggle Bit Polling RD/WR Control
toggling will cease and the device will be accessible for additional read or write operations. Due to the dual plane architecture, reads for polling must occur in the plane that was written; that is, the state of A12 during write must match the state of A12 during polling.
Operation
Lost Byte Written
l/06=X
l/06=X
l/06=X
l/06=X
X88C64 Ready For Next Operation
ALE ADO-AD7
A8-A12
Toggle Bit Polling E and R/W Control
Lost Byte OPERATION Written
cr
l/06=X
l/06=X
ALE
ADO-AD7 A8-A12
RD(E)
X& WR(R/W)
IXW '@/
l/06=X
l/06=X
0125-12 X88C64 Ready For Next Operation
0125-13
5-12
X88C64, X88C641
DATA PROTECTION The X88C64 provides two levels of data protection through software control. There is a global software data protection feature similar to the industry standard for E2PR0Ms and a new Block Protect write lock out protection providing a second level data security option.
Software Data Protection Software data protection (SOP) can be employed to protect the entire array against inadvertent writes during power-up/power-down operations. The X88C64 is shipped from the factory with SOP off. Enabling SOP
Setting SOP/Writing with SOP Set
Action Notes If SDP Not Set And Command Sequence Interrupted
requires the X88C64 to be written a three byte command sequence. This operation writes to an E2PROM bit, providing nonvolatile store of the user selected SOP condition. With SOP enabled, inadvertent attempts to write to the X88C64 will be blocked.
The system can still write data, but only when the write operation (page or byte) is preceded by the three byte command sequence. All write operations, both the command sequence and any data write operations must conform to the page write timing requirements.
Once SOP is set on the X88C64 it can only be reset by issuing a five byte command sequence.
Resetting SOP
Write AA to XX55
AA will be written to location XXSS
No Data Written X88C64 Protected Until Next Power-On
Perform Byte or
Page Write Operations
WAITtwc I ~
-------~ v
Exit Routine
No Data Written X88C64 SDP Set
Data Written X88C64 SDP Set
0125-14
Exit Routine
X88C64 SDP Reset BPR Unaffected
0125-15
5-13
X88C64, X88C641
Block Protect Write Lockout The X88C64 provides a second level of data security referred to as Block Protect write lockout. This is accessed through an extension of the SOP command sequence. Block Protect allows the user to lock out writes to. 1K x 8 blocks of memory. Unlike SOP which prevents inadvertent writes, but still allows easy system access to writing the memory, Block Protect will lock out all attempts unless it is specifically disabled by the host. This could be used to set a higher level of protection in a system where a portion of the memory is used for Program Store and another portion is used as Data Store.
Setting write lockout is accomplished by writing a five byte command sequence opening access to the Block Protect Register (BPR). After the fifth byte is written the user writes to the BPR selecting which blocks to protect or unprotect. All write operations, both the command sequence and writing the data to the BPR, must conform to the page write timing requirements. It should be noted that accessing the BPR automatically sets the upper level SOP. If for some reason the user does not want SOP enabled, they may reset it using the normal reset command sequence. This will not affect the state of the BPR and any 1K x 8 blocks that were set to the write lockout state will remain in the write lockout state.
Block Protect Register Format
Setting BPR Command Sequence
Write AA
to XXSS
-----(BPR Register Set Global SOP Set) Exit Routine
0125-17
MSB
LSB
BLOCK ADDRESS
0000-03FF 0400-07FF ....__ _ _ 0800-0BFF ....__ _ _ _ OCOO-OFFF ....__ _ _ _ _ 1000-13FF
--------1400-17FF . . . . _ - - - - - - - 1 8 0 0 - 1 BFF ----------1C00-1FFF
0125-16
1 = Protect, 0 = Unprotect Block Specified
5-14
X88C64, X88C641
Write AA
to XX55
No Yes
Reset SDP
(SDP Reset
------- BPR Register
Unchanged)
Exit Routine
------(BPR Register Set Global SDP Set) Exit Routine
0125-18
5-15
NOTES
5-16
XM28C010, XM28C0101 . . . . . . . . . . . . . . . . . . . XM28C020, XM28C0201 . . . . . . . . . . . . . . . . . . .
6-1 6-15
liCI'
INOVRAM* Data Sheets ISerial Products Data Sheets IE2PROM Data Sheets IE2POTTM Data Sheets
Microcontroller Peripheral Products
c:) Memory Subsystems
PRELIMINARY INFORMATION
1Megabit Module
XM28C010
Electrically Erasable PROM
lil:ll!
128K x 8 Bit
FEATURES �High Density 1Megabit (128K x 8) E2PROM
Module
� Access Time of 250 ns at - 55�C to + 125�C
� Base Memory Component: Xicor CMOS X28C256
� JEDEC Standard 32-Pin 600 Mil Wide Ceramic Side Braze Package
�Pin Compatible with the X28C010 1Megabit Monolithic CMOS E2PROM
� Fast Write Cycle Times Supported by: -Internal Program Cycle 10 ms Max. -64-Byte Page -DATA Polling -Toggle Status Bit
� High Rel Module Available with: -100% MIL-STD-883 Compliant Components -100% Screening and MIL-STD-883 Processing of Modules
� Software Data Protection
PIN CONFIGURATION
DESCRIPTION The XM28C010 is a high density 1Megabit E2PROM comprised of four X28C256 32K x 8 LCCs mounted on a co-fired multilayered ceramic substrate. The
XM28C01 O is configured 128K x 8 bit and features the
JEDEC approved pinout for byte-wide memories, compatible with the monolithic X28C010.
The XM28C01 O is available in commercial, industrial and military temperature ranges. The military temperature range module is built with MIL-STD-883 Class B microcircuit components. In addition, after being assembled all High Rel modules undergo 100% screening.
The XM28C01 O supports a 64-byte page write operation, this, combined with DATA Polling or Toggle Bit testing, effectively provides a 78 �s/byte write cycle, enabling the module memory array to be rewritten in 1O seconds.
The XM28C01 O will also support Software Data Protection, a user-optional method of protecting data during power transitions.
The XM28C01 O provides the same high endurance and data retention as the base memory components.
FUNCTIONAL DIAGRAM
X28C256 .....---~,. Ao-A14
l/Oo-1/07 0� ViE CE
0091-1
PIN NAMES
Ao-A16 l/Oo-1/07 WE
CE
OE
Vee Vss
NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
l/Oo-1/07 "~--~~, � OE - - - - + - . - + - WE - - - - + - - e - CE
6-1
l/Oo-1/07 OE WE CE
0091-2
XM28C010
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -65�C to+ 135�C Storage Temperature .................... - 65�C to + 150�C Voltage on any Pin with
Respect to Ground ........................ -1.0V to + 7V D.C. Output Current .................................. 5 mA Lead Temperature
(Soldering, 1o Seconds) ........................... 300�C
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS
XM28C010 TA= 0�C to +75�C, Vee= +sv �10%, unless otherwise specified. XM28C0101 TA= -40�C to +85�C, Vee= +SV �10%, unless otherwise specified. XM28C01 OM TA = -55�C to + 125�C, Vee = + 5V � 10%, unless otherwise specified.
Symbol
Parameter
Limits
Min.
Max.
Units
Test Conditions
Ice
Vee Current (Active)
(TTL Inputs)
70
mA CE = OE = VIL� WE = V1H
All I/O's= Open, 1 Device Active
Address Inputs = TTL Levels@ f = 5 MHz
lss1
Vcc Current (Standby)
(TTL Inputs)
15
mA CE = V1H. OE = V1L
All I/O's = Open, Other Inputs = V1H
lss2
Vcc Current (Standby)
(CMOS Inputs)
800
�A CE = V1H, OE = V1L
All I/O's = Open, Other Inputs = Vee
lu
Input Leakage Current
10
�A V1N = GND to Vee
ILO
Output Leakage Current
10
�A VouT = GND to Vee. CE = V1H
V1L
Input Low Voltage
-1.0
0.8
v
V1H
Input High Voltage
2.0 Vee +1.0 v
Vol
Output Low Voltage
0.4
v
loL = 2.1 mA
VoH
Output High Voltage
2.4
v
loH = -400 �A
TYPICAL POWER-UP TIMING
Symbol tpuR(2) tpuw(2)
Parameter Power-Up to Read Operation Power-Up to Write Operation
Typ.(1) 100 5
Units �s ms
CAPACITANCE TA= 25�C, f = 1.0 MHz, Vee= SV
Symbol C11o(2l C1N(2)
Test Input/Output Capacitance Input Capacitance
Max. 40 24
Units pF pF
Conditions V110 = OV V1N = OV
A.C. CONDITIONS OF TEST
Input Pulse Levels OV to 3.0V
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and CL= 100 pF
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
x
x
x
L
x
x
x
H
Notes: (1) Typical values are for TA = 25�C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested.
Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit
1/0 Dour D1N HighZ
-
Power Active Active Standby
-
-
6-2
XM28C010
A.C. CHARACTERISTICS
XM28C01 O TA = 0�C to + 75�C, Vcc = + 5V � 10%, unless otherwise specified. XM28C0101 TA = -40�C to +85�C, Vee= +5V � 10%, unless otherwise specified. XM28C01 OM TA = -55�C to + 125�C, Vee = + 5V � 10%, unless otherwise specified.
Read Cycle Limits Symbol
Parameter
tRc tcE tAA toE tLz toLZ tHz(3) toHz(3) toH
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High Z Output OE High to High Z Output Output Hold from Address Change
XM28C010-25
Min.
Max.
250
250
250
100
0
0
0
100
0
100
0
XM28C010
Min.
Max.
300
300
300
100
0
0
0
100
0
100
0
Read Cycle
Units
ns ns ns ns ns ns ns ns ns
ADDRESS
DATAl/O
HIGHZ
~~~-+~-+~-�
,..__,AA__..
0091-3
Note: (3) tHz and toHz are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
6-3
XM28C010
Write Cycle Limits Symbol
Parameter
twc tAs tAH tcs tcH tcw t o ES t o EH twp twPH tov tos toH tow ts LC
Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE High Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle
WE Controlled Write Cycle
WE Controlled Write
Min.
Max.
10
0
150
25
0
125
10
10
100
1
1
50
10
10
1
100
CE Controlled Write(4)
Min.
Max.
10
0
175
0
25
100
10
35
125
1
1
50
35
10
1
100
Units
ms ns ns ns ns ns ns ns ns �s �s ns ns �s �s
ADDRESS
DATAOUT ><><><><>------------------------H-IG_H_z____________________________~
0091-4
Note: (4) Due.!Q_the inclusion of the decoder IC on board the module the WE and CE write controlled timings will vary. When utilizing the CE controllfil!_write operation all the holg__!lmings must be extended by the worst case propagation delay of the decoder. For a WE controlled write operation CE must be a minimum 125 ns to accommodate the additional setup time required.
6-4
XM28C010
CE Controlled Write Cycle ADDRESS
.._toES_.,.
~tov_.
DATA VALID
~los___.~toH
Page Write Cycle
JI
_ _!ffA CE --,~__.Ul\....___m
WE----- 1
*ADDRESS
0091-5
*For each successive write within the page write operation, A6 -A15 should be the same or writes to an unknown address could occur.
0091-6
6-5
XM28C010
DATA Polling Timing Diagram
~-----An_____XXXXXX)(
Toggle Bit Timing Diagram
0091-7
----- 1/01
*Starting and ending state of I/Os will vary, depending upon actual twc-
0091-8
6-6
XM28C010
PIN DESCRIPTIONS
Addresses (Ao-A1s) The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced (see Note 4).
Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (l/Oo-1/07) Data is written to or read from the XM28C01 O through the 1/0 pins.
Write Enable (WE) The Write Enable input controls the writing of data to the XM28C010.
DEVICE OPERATION
Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The XM28C010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5 ms (see Note 4).
Page Write Operation The page write feature of the XM28C01 O allows the entire memory to be written in 1O seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the XM28C010 prior to the commencement of the internal programming cycle. The host can fetch data from another location within the system during a page write operation (change the source address), but the page address (As through A1 s) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 �s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 �s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 �s.
Write Operation Status Bits The XM28C01 O provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the 110 bus as shown in Figure 1.
Figure 1: Status Bit Assignment
0091-9
DATA Polling (1/07) The XM28C01 O features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the XM28C01 O, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1107 (i.e., write data = Oxxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, 1107 will reflect true data. Note: If the XM28C01 O is in the protected state and an illegal write operation is attempted DATA Polling will not operate.
Toggle Bit (I/Os) The XM28C01 O also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/Os will toggle from one to zero and zero to one on subsequent attempts to read the last byte written. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations.
S-7
XM28C010
DATA POLLING 1/07 Figure 2a: DATA Polling Bus Sequence
An
An
Figure 2b: DATA Polling Software Flow
WRITE DATA
An
An
An
An
0091-10
DATA Polling can effectively halve the time for writing to the XM28C010. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine.
XM28C010
RUDY
0091-11
6-8
XM28C010
THE TOGGLE BIT 110& Figure 3a: Toggle Bit Bus Sequence
,......--------+- ) WI LAS~ T - - - - - - - - - - - - - - - - - _ _ , (
*Beginning and ending state of 1/06 will vary.
0091-12
Figure 3b: Toggle Bit Software Flow
LAST WRITE
The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple XM28C01 O memories that is frequently updated. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for testing the Toggle Bit.
NO
READY
0091-13
6-9
XM28C010
HARDWARE DATA PROTECTION
The XM28C01 o provides three hardware features that
protect nonvolatile data from inadvertent writes.
� Noise Protection-A WE pulse less than �20 ns will not initiate a write cycle.
�Default Vee Sense-All functions are inhibited when Vee is ~3V.
� Write Inhibit-Holding OE LOW will prevent an inadvertent write cycle during power-on and power-off.
SOFTWARE DATA PROTECTION The XM28C01 O does provide the Software Data Protection (SOP) feature. Because the module is comprised of four discrete X28C2S6 LCCs, the algorithm will differ from the algorithm employed for the monolithic 1Megabit X28C010.
The module is shipped from Xicor with the Software Data Protect NOT ENABLED; that is, the module will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. �The host system will then have open read and write access of the module once Vcc is stable.
The module can be automatically protected during power-up/-down without the need for external circuits by employing the SOP feature. The internal SOP circuit is enabled after the first write operation utilizing the SOP command sequence.
When this feature is employed, it will be easiest to incorporate in the system software if the module is viewed as a subsystem composed of four discrete memory devices with an address decoder (see Functional Diagram). In this manner, system memory mapping will extend onto the module. That is, the discrete
memory ICs and decoder should be considered memory board components and SOP can be implemented at the component level as described below.
SOFTWARE COMMAND SEQUENCE
A15 and A16 are used by the decoder to select one of the four LCCs. Therefore, only one of the four memory devices can be accessed at one time. In order to protect �the entire module, the command sequence must be issued separately to each device.
Enabling the software data protection mode requires the host system to issue a series of three write operations: each write operation must conform to the data and address sequence illustrated in Figures 4a and 4b. Because this involves writing to a nonvolatile bit the device will become protected after twc has elapsed. After this point in time devices will inhibit inadvertent write operations.
Once in the protected mode, authorized writes may be performed by issuing the same command sequence that enables SOP, immediately followed by the address/data combination desired. The command sequence opens the page write window enabling the host to write from one to sixty-four bytes of data. Once the data has been written, the device will automatically be returned to the protected state.
In order to facilitate testing of the devices the SOP mode can be deactivated. This is accomplished by issuing a series of six write operations: each write operation must conform to the data and address sequence illustrated in Figures Sa and Sb. This is a nonvolatile operation, and the host will have to wait a minimum twc before attempting to write new data.
6-10
XM28C010
SOFTWARE DATA PROTECTION Figure 4a: Timing Sequence-Byte or Page Write
v(Yod
WRITES OK
BYTE OR
PAGE
Figure 4b: Write Sequence for Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
*A15 & A1s select one of four devices on the module.
0091-14
Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the device will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the device will be write protected during power-down and after any subsequent power-up.
BYTE/PAGE LOAD ENABLED
WRITE LAST BYTE TO
LAST ADDRESS
AFTER twc RE-ENTERS DATA PROTECTED STATE
0091-15
6-11
XM28C010
RESETTING SOFTWARE DATA PROTECTION Figure Sa: Reset Software Data Protection Timing Sequence
YcJ ~}~ J L~~~~~~---1' JJ ~'~[ ~
DATA
AA
55
80
AA
55
CE-t ADDRESS Ao-A14� 5555
2AAA
5555
5555
2AAA
-----�..a STANDARD OPERATING MODE
*A15 & A15 select one of four devices on the module.
0091-16
Figure Sb: Software Sequence to Deactivate Software Data Protection
WRITE DATA AA TO
ADDRESS 5555
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After twc. the device will be in standard operating mode.
WRITE DATA 80 TO
ADDRESS 5555
WRITE DATA 55 TO
ADDRESS 2AAA
WRITE DATA 20 TO
ADDRESS 5555
0091-17
6-12
XM28C010
SYSTEM CONSIDERATIONS
Because the XM28C01 O is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple 1/0 pins share the same bus.
To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus.
Because the XM28C010 has two power modes, standby and active, proper decoupling of the memory array
is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 �F high frequency ceramic capacitor be used between
Vee and GND at each device. Depending on the size
of the array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7 �F electrolytic
bulk capacitor be placed between Vee and GND for
every two modules employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
SYMBOL TABLE
WAVEFORM
xxxxx
B<1K
INPUTS Must be steady
May change from Low to High
May change from High to Low
Don't Care: Changes Allowed
N/A
OUTPUTS Will be steady
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
6-13
NOTES
6-14
FACT SHEET
2Megabit
Module
XM28C020
Electrically Erasable PROM
lil:ll!
256K x 8 Bit
FEATURES � High Density 2Megabit (256K x 8) E2PROM
Module
� Access Time of 200 ns at - 40�C to + 85�C
� Base Memory Component: Xicor CMOS X28C513
� JEDEC Standard 32-Pin 600 Mil Wide Ceramic Side Braze Package
� Fast Write Cycle Times Supported by: -Internal Program Cycle 10 ms Max. -128-Byte Page -DATA Polling -Toggle Status Bit
� Software Data Protection
PIN CONFIGURATION
DESCRIPTION The XM28C020 is a high density 2Megabit E2PROM comprised of four X28C513 32K x 8 LCCs mounted on a co-fired multilayered ceramic substrate. The XM28C020 is configured 256K x 8 bit.
The XM28C020 is available in commercial and industrial temperature ranges.
The XM28C020 supports a 128-byte page write operation. This, combined with DATA Polling or Toggle Bit testing, effectively provides a 40 �s/byte write cycle, enabling the module memory array to be rewritten in 10 seconds.
The XM28C020 will also support Software Data Protection, a user-optional method of protecting data during power transitions.
The XM28C020 provides the same high endurance and data retention as the base memory components.
FUNCTIONAL DIAGRAM
X28C513 ..----./1 Ao�A14
l/Oo�l/0., OE WE CE
0126-1
PIN NAMES
Ao-A17 l/Oo-1/07
WE
CE
OE
Vee Vss
NC
Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
Ao�A15
l/Oo� 1/07 OE WE CE
A16 A11
6-15
X28C513 Ao�A14
l/Oo�l/07 OE WE CE
0126-2
NOTES
6-16
liCI'
Die Products ............................ .
7-1
I NOVRAM* Data Sheets
Serial Products Data Sheets
E2PROM Data Sheets
I E2POTTM Data Sheets
Microcontroller Peripheral Products
IMemory Subsystems
c ) IDie Products
Die Products
.iCI'
FEATURES � High Performance Advanced NMOS
Technology � 0�c to 70�C Operating Temperature � 100 Year Data Retention � 95% Yield Excluding Assembly Related
Losses � Standard Thickness Between 20 to 22 mils � Commercial Data Sheet Parameters
(except input levels) �Die Inspected to 883C 2010.7 Condition B
TEST FLOW
WAFERS FROM FABRICATION
_!
SORT TO STANDARD SORT PROGRAM
I
RETENTION BAKE
_!
SORT TO SUPER SORT PROGRAM
~
SAW & PLATE DIE
l
DESCRIPTION Xicor die products are fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor programmable nonvolatile memories, they are SV only devices.
Xicor die products are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 100 years.
Products to be shipped in die form follow the flow shown below. This insures a 95% yield (excluding assembly related losses) to the commercial data sheet with the access times per the Die Products Reference Guide. All A.C. parameters and D.C. parameters except input and output voltages are guaranteed.
Bonding diagrams, die size and other information required for use of die can be obtained from your local Xicor sales representative.
1_
OPTICAL INSPECTION
~
�WAFFLE PACK
FINISHED DIE INVENTORY
_!
CUSTOMER SEES 95% YIELD � AFTER ASSEMBLY
�EXCLUDING ASS EMBLY RELATED LOSSES
0074-1
7-1
Die Products
DIE PRODUCTS REFERENCE GUIDE
Part Number
X2804AH X2816BH X2864AH X2864BH
Organization
512 x 8 2Kx8 8Kx8 8Kx8
Page Size (Bytes)
N/A 16 16 32
Access Time (ns)
450 450 450 200
Power Requirements (mA)
Active (Max.)
Standby (Max.)
80
50
120
60
140
60
150
80
NOV RA Ms Part
Number
X2004H
Organization 512 x 8
Access Time (ns)
300
Store Cycles
100,000
Power Requirements (mA)
Active (Max.)
Standby (Max.)
100
55
Serial E2PROMs
Part Number
Organization
X2402H X2404H
256x8 512 x 8
Page Size (Bytes)
8 8
Clock Frequency
100 KHz 100 KHz
Power Requirements (mA)
Active (Max.)
Standby (Max.)
30
25
30
25
Serial NOVRAMs
Part Number
Organization
Clock Frequency
X2444H
16x 16
1 MHz
----
Digital Potentiometers Part
Number X9103H X9503H X9104H
End to End Resistance
10K!1 50K!1 100 Kn
Store Cycles
100,000
Power Requirements (mA)
I I Active
Standby
Sleep
l 15
l 10
7
Maximum Voltage (VH, VL)
�5V �5V �5V
Power Requirements (mA)
35 35 35
7-2
JliCI'
Application Notes
AN-101 Xicor NOVRAMs* Easier Than Ever to Use ........................ .
AN-103 Xicor Replaces DIP Switches and Trimmers with NOVRAM* Memories ..................... .
AN-105 The X2444 Serial NOVRAM* Teams Up with the 8051 Microcontroller Family ........................ .
AN-106 E2POTTM Digitally Controlled Potentiometer Brings Microprocessor Control to Audio Systems-Adds Features ....... .
Application Briefs
Nonvolatile Data Integrity: Inadvertent Write/ Store Elimination ....................... .
Replacing DIP Switches with Nonvolatile Technology ........................... .
Using DATA Polling in an Interrupt Driven Environment .......................... .
E2PROM Provides the Solution to Field Alterable Software ..................... .
"tov"-What is it? . . . . . . . . . . . . . . . . . . . . . . . .
Article Reprints
Understand your application in choosing NOVRAM, EEPROM ................... .
Non-volatile memories keep appliances out of the dark .............................. .
Nonvolatile Memory Gives New Life to Old Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Save volatile data during power loss ........ .
Thick Oxide Beats Thin Film in Building Big EEPROMs ............................ .
Solid-State Potentiometer ................. .
Bit Maps for Xicor Products . . . . . . . . . . . . . .
8-1
8-9
8-17
8-23
8-33 8-37 8-41 8-45 8-49
8-51 8-63 8-69 8-77 8-85 8-89 8-91
NOVRAM * Data Sheets Serial Products Data Sheets E2PROM Data Sheets E2POTTM Data Sheets Microcontroller Peripheral Products Memory Subsystems Die Products
c ) Application Notes and Briefs
AN-101
liCI'
0001-1
XICOR NOVRAMs* EASIER THAN EVER TO USE
By Applications Staff
*NOVRAM is Xicor's nonvolatile static RAM device. 8-1
Introduction
The purpose of this application note is to take the user through the internal operation of NOVRAMs as well as their external operation. These devices are finding their way into many diverse applications due to their ease of use. The major features of the XICOR family of NOVRAMs are 1) only 5 volts is required for all operations including programming, 2) only TTL signals are required and 3) all pulse widths are short ( < 450 ns).
Basically a NOVRAM is a memory device that has a static RAM overlaid with an EEPROM (Electrically Erasable Programmable ROM). The operation of the RAM is identical with other popular static RAMs such as the 2102A and the 2114. Figure 1 shows the block diagram ..Qf_!he XICOR NOVRAM family. NOVRAMs have CS and WE pins in common with their standard static RAM cousins but also have two additional control oins: STORE and RECALL. The STORE and RECALL pins control movement of data between the RAM and the EEPROM.
Figure 1) Block diagram of the XICOR NOVRAM family.
The STORE pin is used to transfer the contents of the RAM to the EEPROM in a single operation. The entire contents of the RAM are transferred with one STORE operation. After a STORE operation is completed the original data is still in the RAM as well as the EEPROM.
The RECALL pin is used to transfer the contents of the EEPROM back to the RAM. When this is done, whatever data were in the RAM prior to the RECALL
operation are totally replaced by the contents of the EEPROM. The STORE and RECALL operations function on the entire contents of the memory and not on a word by word basis. After either operation the contents of both the RAM and the EEPROM will be the same.
This may seem too good to be true; however, with XICOR's family of NOVRAMs the life of the systems designer is made even easier. Only a single five volt power supply is required for all operations including the STORE and RECALL operations. All addresses, data lines and control pins are TTL compatible and all pulse widths are short enough that most microprocessors do not require wait states. There are no high voltages or long pulse widths required which will inhibit t.he designer from designing a system with clean operation.
Technology
The XICOR NOVRAM stores its nonvolatile data during periods of power off by the absence or presence of charges on floating polysilicon gates. This is the same structure that is widely used in UV-EPROMS. The floating gate is an island of polysilicon surrounded by oxides with thicknesses of about 800 A0 . Charge can be injected or removed from the floating gate by applying electric fields of sufficient strength to cause electron tunneling through the oxides. At normal field strengths the charges are permanently trapped on the floating gate even when power is removed.
The XICOR family of NOVRAMs uses three layers of polysilicon; the second layer is the floating gate. This structure employs a phenomenon known as FowlerNordheim tunneling. This form of tunneling is described in Vol. 40 No. 1 (Jan. 1969, pg. 278) of the Journal of Applied Physics and Vol. 27 No. 9 (Nov. 1975, pg. 505) of the Applied Physics Letters. In XICOR NOVRAMs this tunneling is enhanced by the use of textured polysilicon surfaces to generate higher field strengths at the surface to enhance electron injection into the oxide. The alternative to field enhancement by textured surfaces is to use ultrathin oxide layers in order to conduct the charge. The use by XICOR of standard oxide thickness gives XICOR a very manufacturable product, thus ensuring its low cost and volume delivery.
Figure 2. shows the circuit of the NOVRAM cell containing a conventional 6 transistor static RAM cell and a floating gate EEPROM cell with 2 additional transistors to control the action of data transfer. The floating gate (POLY 2) is connected to the rest of the circuit only through capacitance. Electrons are moved to the floating gate by tunneling from POLY 1 to POLY 2 and removed by tunneling from POLY 2 to POLY 3.
The capacitance ratios are the key to the operation of the transfer of data from RAM to EEPROM. If node
0001-2
8-2
N1 is LOW, transistor 07 is turned OFF. This allows the junction between CC2 and CC3 to float. Since the combined capacitance of CC2 and CC3 are larger than CP the floating gate follows the Internal Store Voltage node. When the voltage on the floating gate is high enough electrons are tunneled from POLY 1 to POLY 2 and the floating gate is negatively charged.
centers. Figure 3 shows the pin configuration of the three different NOVRAMs.
1K a 1
Ma4
2Ha4
Yee�
INTERNAL STORE VOLTAGE
r�~ CC3rJ:y~
�~ � = t
0001-8
Figure 2) Circuit diagram of a NOVRAM cell.
If node N1 is HIGH, transistor 07 is turned ON which grounds the junction between CC2 and CC3. Since CC2 is larger than CE, CC2 holds the floating gate near ground when the Internal Store Voltage node is pulled HIGH. This creates a sufficient field between POLY 2 and POLY 3 to tunnel electrons away from the floating gate leaving it with a positive charge.
The RECALL operation also takes advantage of capacitance ratios. The value of C2 in Figure 2 is larger than that of C1 . When the external RECALL command is received, the internal power supply, VCCA, is first pulled LOW to equalize the voltage on N1 and N2. When the internal power node is allowed to rise, the node which has the lighter loading will rise more rapidly and the gain of the flip-flop will cause it to latch HIGH and the opposite node to latch LOW. If the floating gate has a positive charge C2, is connected to N2 through 08 and N2 will latch LOW. If the floating gate has a negative charge 08, is turned OFF and N1 will have the heavier loading.
The Xicor NOVRAM Family
XICOR's family of NOVRAMs contains three members with identical operating characteristics. The three parts offer the designer a choice of memory organization. The X2201A, X2210 andX2212 are organized 1024 x 1, 64 x 4 and 256 x 4 respectively. All three devices are packaged in 18 pin DIPs with 300 mil
Figure 3) Pin configuration of the XICOR NOVRAM family
0001-9
The only functional difference between the three devices is that the X2201 A has separate Data 110 lines while the two 4 bit wide parts have common 110. Additionally, the X2210 and the X2212 are pin compatible. The two unused pins on the X2210 are used for the two higher order addresses on the X2212. The control pins STORE, RECALL, CS and WE operate identically on all three parts.
Write Operation
The WRITE operation is initiated ~pplying valid addresses followed by both CS and WE going LOW. On the 300ns version access time version, at least one of these two signals must remain HIGH until the addresses are valid. CS and WE must remain LOW simultaneously for 100ns.
An easy way to look at this is to consider the internal write command as the simultaneous LOW of CS and WE. The internal write command is started by the last edge down and terminated by the first edge up. Valid addresses must overlap this internal write command. Data must be referenced to the first positive edge of CS or WE. The timing required for writing to the RAM is shown in Figure 4.
WRITE CYCLE
EARLY WRITE CYCLE
Figure 4) Timing diagram for Writing to the RAM.
0001-10 0001-3
8-3
Read Operation
The READ operation is the easiest of the four operations performed by the NOVRAM. In the case of the 300ns access time version, data will be valid at the outputs 300ns after valid addresses or 200ns after CS goes LOW, whichever is later.
Figure 5) Timing diagram for Reading from the RAM.
0001-11
Store Operation
The STORE operation is initiated by the application of an active LOW TTL pulse of 100ns or greater on the STORE pin. As long as the power supply remains within its specification for 1Oms after the beginning of the STORE pulse the contents of the RAM will have been transferred to the EEPROM in total. The STORE operation cannot be terminated once initiated except by removing the power supply. This can not be counted upon to rapidly terminate the STORE operation since the user cannot determine how far the STORE operation the device has progressed. Additionally, if the power supply drops below the specification during the 10ms the integrity of the STORE operation is not assured. Figure 6 shows the timing diagram for transferring data from the RAM to the EEPROM.
0001-12
Figure 6) Timing diagram for the STORE operation where data is transferred from the RAM to the EEPROM.
The STORE operation takes precedence over all other operations except the RECALL operation. If the RECALL operation has begun, any STORE command is ignored as long as the RECALL pin remains LOW. Once the STORE operation has started, taking the RECALL pin LOW has no effect and the STORE operation will be completed. If a READ or WRITE cycle is in progress when a STORE command is received, that cycle is terminated. The data in the selected RAM
address during an interrupted WRITE cycle would be indeterminate.
During the 10ms of the STORE operation the NOVRAM should not be accessed for any other operation as it would not be known if the internal STORE operation was completed or not. If the internal STORE operation was completed� before the 10ms and another operation command was entered, that command would be executed. However, if the internal STORE operation was not completed and another operation command was received, the later command would be ignored. During the STORE operation the outputs of the NOVRAM are in the floating state.
Recall Operation
The RECALL operation is initiated by the application of an active LOW TTL pulse of 450ns or greater on the RECALL pin. The positive going edge of this pulse determines when it is possible to read data from the RAM. Valid data from the RAM can be viewed on the outputs of the NOVRAM 750ns after the rising edge of RECALL or 300ns after application of valid addresses, whichever comes latest. FIGURE 7 shows the timing requirements for transferring data from the EEPROM to the RAM.
>--- DATA VALID
Figure 7) Timing diagram for the RECALL operation.
0001-13
The RECALL operation takes precedence over all other operations. RECALL will terminate a READ or WRITE cycle if applied in the middle of either cycle. The RECALL operation can take precedence over the STORE operation only if the RECALL command was received prior to the STORE command.
Hookingupthe NOVRAM
Now that the basics of the four NOVRAM operations have been described, we may discuss using these unique parts in a system. Let's first discuss a system in in which we connect the NOVRAMs to a 6502. We'll assume that the system powers up and down cleanly. The problem of systems where this does not occur will be dealt with later.
0001-4
8-4
The 6502 microprocessor uses memory space for 1/0 functions. The design uses one set of addresses for the READ and WRITE operations and other blocks of addresses to initiate the STORE and RECALL operations. An APPLE II* computer was used as the 6502 computer because it has address space already decoded for 1/0 functions and convenient card slots to communicate with these decoder outputs.
The RAM was placed in the address space starting at HEX address $C800 by connecting pin 20 on the APPLE II peripheral connector to the CS on the NOVRAM. This pin is activated when any of the 2048 bytes starting at $C800 are accessed. Peripheral slot 2 was selected for the NOVRAM design. On slot 2 pin 41 is activated whenever the 16 bytes located at HEX address $COAO are accessed. This address space is sent only to slot 2 and was tied to the STORE pin on the NOVRAM. PIN 1 also has a unique address space for slot 2 and was tied to the RECALL pin. This space is the 256 bytes starting at HEX address $C200.
Figure 8 shows the connections of the card to be plugged into peripheral card slot 2. Reading and writing are accomplished from the BASIC programming language by PEEK and POKE instructions to HEX addresses starting at $C800. The STORE operation is called by either a PEEK or a POKE instruction to any of the 16 addresses starting at $COAO. RECALL is initiated by accessing any of the 256 bytes starting at $C200.
APPLE II COMPUTER
.i.;..
BOARD SLOT#2 SC8H-SCFFF
ment 580 respectively. This program was written for the X2210 but it could be easily modified for the X2212 or even eight X2201 s.
SC2#-SC2FF
= = = = = = = . J RN/~----'
Ao-. .
Figure 8) Connections for operating the NOVRAM on the 110 Bus of an APPLE II computer.
The APPLESOFT* program in Table 1 demonstrates how a NOVRAM can be accessed easily. The statement 210 is a Write operation to HEX address $C200 while statement 310 is a Write to HEX address $COAO. The CS pin is activated with statement 430 and state-
*APPLE II and APPLESOFT are trademarks of Apple Computers
Table 1) An APPLESOFT BASIC program for demonstrating the four operations of NOVRAMs.
8-5
Protection Against
Inadvertent Store
The circuit described in the previous section assumes that the system is powered up and down in an orderly manner. This would mean that the microprocessor would never generate addresses unless they were part of the program. Unfortunately real systems do not operate in this ideal manner. Although the circuit described above has not produced a fault during extensive testing, the possibility exists that the hex addresses $COAO-$COAF could come up during power up, or during a brown out when the supply dropped below the operating specification, or during a power failure.
Several methods can be used to insure that the NOVRAM does not react to errors produced by the system when it is out of its operating specification. Setting the RECALL pin LOW to block a STORE operation is the easiest. Holding the STORE pin between VIH MIN and the falling power supply is another.
Most microprocessors are not totally under control for the first few cycles after power up. Their early addresses depend on what is in the registers after the System Reset pulse terminates. There is a possibility that these registers can cause one of the early addresses to be the same selected for a STORE operation. In this case the circuit shown in Figure 8 could cause the EEPROM to be written with false data during the power up operation. Figure 8 allows the STORE operation to be initiated if any of 16 addresses is selected for either a read or a write.
Although microprocessors can put out uncontrolled addresses they do not put out uncontrolled write commands. By ANOing the System Write line with the System STORE command, the NOVRAM would recognize a STORE operation only on a machine write cycle.
A potential danger in the. use of the above schemes is the fact that three state TTL gates are not under total control while the power supply is coming up. This could produce glitches on the STORE pin even though no Write command was received at the input of the gate. A more positive way to insure that the STORE pin follows the power supply as the voltage increases is to use an open collector NANO gate with one of the inputs provided by a signal that determines power supply status (Circuitry for power supply status will be covered later in this application note). If one input of an open collector NANO gate is held LOW the output transistor is turned OFF since it can not receive base current. Pulling the output of this gate to the power supply of the NOVRAM through a pullup resistor will then insure that the output follows the power supply with no glitches.
Carrying the use of a power supply status signal one step further, would be to use it to hold the RECALL pin LOW in addition to holding the STORE pin HIGH. A dir-
ect connection of this status signal to the RECALL pin is all that is necessary as shown in Figure 9. This circuit has a more positive control of the NOVRAM since it takes two actions to prevent an inadvertent STORE operation.
SystemSTORE - - - - -
+sv
2K
0001-14
Figure 9) A power supply status line held LOW can insure that both the RECALL pin is held LOW and the STORE pin is held HIGH
An example of a basic circuit to monitor the power supply status is shown in Figure 10. The output of this two-stage circuit is held LOW whenever the power supply is below 4.5 Volts. This same technique can be used with a Zener diode and an operational amplifier. The designer is cautioned to consider temperature effects.
~~~ >---------
0001-15 Figure 10) The Zener power supply detector is used in combination with the open collector on the STORE pin to provide protection against an inadvertent STORE operation during power up and power down.
Another method of power supply status is to assume that the only power supply fault which requires insuring that wrong data is not stored is the loss of the AC line voltage. Many commercially available AC line fault monitors are on the market. Two of these line fault monitors are the MID 400 Power Line Monitor from General Instrument and the SG1547 from Silicon General. Additionally, many commercially available power supplies have a power fail signal either as a standard feature or as an option.
The circuit shown in Figure 11 shows another type of power supply status detector. This circuit is a low cost solution but it should be used only to take the RECALL
0001-5
8-6
pin LOW because it does not provide adequate drive for a TTL gate..
we>--------'
�>-------....J
0001-16
Figure 11) Another form of power supply status detector to drive the RECALL pin LOW when the supply drops below 4.5Volts.
Some other schemes to protect against inadvertent STORE operations are the use of jumpers, cables and/or switches. The STORE signal is transmitted through the jumper or switch which is normally open unless it is desired to change the data in the EEPROM. During normal operation the only component attached to the STORE pin is a resistor to the power supply.
A more comprehensive discussion of power supply status circuitry can be found in XICOR's Ap Note #102. This note covers those requirements that STORE data at power failure.
Applications
Most microprocessor systems have need for some form of nonvolatile memory to store important data such as:
1) Calibration constants 2) Set-up configuration information 3) User system ID 4) Changeable programs/firmware 5) System status 6) Accounting information 7) Error conditions Th~ types of equipment that are today being designed to include NOVRAMs vary through the complete line of electronic equipment. Some of these systems are: 1) Computer peripherals/terminals etc. 2) Automatic tellers/transaction terminals 3) Point-of-sale terminals 4) Smart scales 5) Vending machines and games (i.e. arcade
games, slot machines)
6) Meters (i.e. utilities, taxi, gas pumps) 7) Process control 8) Robots 9) Instruments (musical, medical, test, avionics) 10) Communications 11) Transducers/load cells 12) Automotive: odometers. engine control 13) Office equipment: copiers, word processors 14) Military products Some of the competitive products being replaced by NOVRAMs in systems are: 1) DIP switches 2) Thumbwheel switches 3) CMOS with batteries 4) EAROM 5) EEPROM 6) Potentiometers
One should let his imagination soar when thinking applications for these unique NOVRAMs. XICOR is always interested in application ideas that represent both normal and off-beat uses of these NOVRAMs. Any ideas sent to XICOR will be greatly appreciated.
0001-6
8-7
NOTES
8-8
AN-103
lil:ll!
0002-1
XICOR REPLACES DIP SWITCHES AND TRIMMERS
WITH NOVRAM* MEMORIES
By Applications Staff
*NOVRAM is Xicor's nonvolatile static RAM device. 8-9
Introduction
The desire to replace mechanical components in electronic systems for purposes of increased reliability, lower costs and ease of maintainability has spread to DIP switches and trimming potentiometers or trimmers. The component that makes this replacement possible is the NOVRAM memory from Xicor. The . NOVRAM memory is a device that has two memories in parallel, a standard static RAM and a nonvolatile electrically erasable programmable read only memory (EEPROM). The EEPROM portion of the NOVRAM memory holds data that is equivalent to the settings of the now obsolete DIP switches and trimmers.
What Is A NOVRAM Memory?
A NOVRAM memory, as stated previously, is two memories in a single unit. The standard static RAM has a nonvolatile EEPROM cell associated with each RAM cell. Figure 1 shows a block diagram of a typical NOVRAM memory.
RECALL. The STORE pin is used to transfer the entire contents of the RAM to the EEPROM as a sing~ block. This operation is performed in parallel. The RE ALL
pin is used to transfer the entire contents of the EE PROM back to the RAM. At the end of either operation the contents of the two memories are identical.
Access to the EEPROM data is through the RAM portion. To alter the contents of the EEPROM, the data must first be written into the RAM and then transferred
to the EEPROM with a Store operation. To use the contents of the EEPROM in the system, perform a Recall operation and then the contents of the RAM
may be read. Once data is stored in the EEPROM, the RAM can be used as an entirely separate and independent memory. Some users put configuration data into the EEPROM and then use the RAM as a separate scratchpad.
Besides these operational features, the NOVRAM memory has some unique electrical features. These devices are the world's easiest-to-use nonvolatile components in that they operate with only a single 5-
volt power supply, simple TTL level pulses and short
pulse widths ( < 450 ns). Even for operations such as
the Store operation, which takes 10 ms to complete, it only requires a low level TTL pulse of 100 ns or greater to initiate. During the remaining time, the NOVRAM memory is not on the bus, which frees the microprocessor and the bus for other tasks. Complete details of the operation of NOVRAM memories can be found in the individual data sheets and application note AN101.
Figure 1) NOVRAM memory block diagram.
There are two additional pins on a NOVRAM memory device that do not appear on an ordinary static RAM. These two pins are called STORE and
Replacing DIP Switches With NOVRAM Memories
DIP switches and thumbwheel switches have been used in systems to provide alterable, nonvolatile data. Some uses of this data are to set up configuration parameters and to provide calibration constants. The apparent low cost of these components is one of their attractive features. The drawback is that costs of these components do not end with installation.
The biggest cost of these mechanical, nonvolatile components is in post-installation service. A simple change of a DIP switch setting can require a technician to visit the equipment, disassemble the unit, throw the switch and reassemble the equipment. This could easily run the total use costs to well over 10 times the installed cost. A solution to the problems presented by DIP switches is to use a NOVRAM memory to hold valuable configuration or calibration data. In addition to a lower-cost, easier, and more secure method of changing data, NOVRAM memories cost less at the installed level.
0002-2
8-10
The disadvantages of using DIP switches in modern electronic systems accumulate through each step of the manufacturing process. The first stage of NOVRAM memory advantages starts right at system concept and design. Since the density of NOVRAM memories is significantly greater (up to 1024 switches in a single low-cost DIP package), more functional options can be added to enhance the total value of the system. Features such as electronic unit type signature can be added for a small software cost, with no extra components. No special access needs to be provided to change the NOVRAM memory, as all changes can be made from a keyboard or over phone lines. This can not be said for DIP switches, which require disassembly or special doors or hatches to provide access.
At incoming inspection it is difficult to completely test a package of DIP switches for all possible combinations, or even as individual switches. The NOVRAM memory, on the other hand is tested by automatic test equipment both quickly and thoroughly. The NOVRAM memories are 100% tested by Xicor and can be further tested at whatever levels the user desires, including the quick testing of all the options that were designed into the equipment. In the case of the DIP switch, this would require manually setting each option, rather than have the final system test equipment take care of the task.
The assembly operation is made more difficult when trying to wave solder or clean a board containing DIP switches. These operations can cause contamination in the degreasing step. This is true, even on the components that have tape or other cover for protection, as these are extra items to handle or become lost. Again, the NOVRAM memory exhibits none of these problems in that they are in sealed packages like the rest of the semiconductor components that make up the bulk of the system.
Once the system is in the field, the advantages of the NOVRAM memory are further enhanced. The basic reliability improvement of semiconductors over mechanical components is well known. Equipment warranties can be enforced since there is no need for a customer to open the equipment. The greatest advantage of all comes in service. No longer is it necessary for a technician to travel to the users site to change the setting on DIP switches as this can be accomplished over a phone hookup.
In addition to all of the above cost savings and system benefits in using NOVRAM memories, the basic component cost is also very low. Figure 2 shows a typical interface for DIP switches in a microprocessor system. Each package of 8 switches requires a decoder port and 8 diodes to provide isolation from other switches.
Figure 2) Typical DIP switch interface for multiple packages.
An octal buffer and 8 pull up resistors are required for any quantity of switch packages in a given system. Matrix schemes could be applied to reduce the decoder ports at the cost of more buffers but, by then, the costs will be much greater than those of using NOVRAM memories.
Th~ as~embly costs include incoming inspection, ~andllng, inventory, board real estate, and final inspection. These costs are variable depending on volume and other factors.
The interface of a NOVRAM memory to a microprocessor is shown in Figure 3.
Figure 3) The typical NOVRAM memory interface requires only 3 decoder ports for any number of switches up to 1024.
This setup requires 3 decoder ports for any number of switches up to 1024 and then starts adding a single port for each additional package of 256 or 1024 switches.
The plot in Figure 4 shows that system costs using NOVRAM memories remain constant as the equivalent packages of DIP switches required are increased. These costs include the costs of all associated components, assembly and testing.
t;
0
_,(.)
e ~
1 2 34 5 6 7 N
- - - X2210 64 1. 4 NOVAAM MEMORY -OIPSWITCH
Figure 4) Relative costs of using NOVRAM memories as opposed to DIP switches as a function of packages of 8 switches required.
0002-3
8-11
The plot shows that whenever the required number of DIP switch packages of 8 switches exceeds 1. the NOVRAM approach is lower in cost at the systems level.
The cost of using DIP switches rises constantly as the number of required packages increases. An actual cost crossover occurs between 1 and 2 packages of 8 switches. Designers can derive their actual costs by calculating the two approaches based on the costs at their firm. These costs should include, in addition to the component costs, all costs associated with incoming inspection, warehousing, assembly and system tests. One will find that the crossover between 1 and 2 packages of 8 switches is consistent and favors the NOVRAM memory approach.
Where And Why Trimmers Are Used
The trimming potentiometer or trimmer is a 3terminal device that can be connected in many different configurations. The purpose of the trimmer in the analog circuit is to make a fine adjustment of a current or a voltage. This current or voltage is then used in analog circuits to compensate for component variations in frequency, gain. offset, voltage or current.
Like the DIP switch, the trimmer appears quite inexpensive when one considers only the purchased price. In actuality it can be one of the most expensive components on the card when the costs of field calibration are taken into consideration. It takes only one service call (considered by some to cost approximately $200) due to a changed setting caused by vibration, humidity or even well-intentioned user tampering, to run the cost of using the trimmer to high levels. In addition, the trimmer requires equipment disassembly and the skilled use of a screwdriver. This skill adds to the cost of owning the equipment.
Taking an 'all costs considered' approach is one way manufacturers are reducing the cost of equipment� ownership as a function of performance. Although the end customer wants equipment that is low in purchase price and service costs while delivering a high level of performance, they will purchase a more expensive piece of equipment if they believe that the service costs and possible downtime will be reduced.
The functions of the trimmer can be duplicated quite well by a NOVRAM memory combined with a Digitalto-Analog Converter (DAC). A DAC is a device that delivers a voltage at the output that is a function of a digital signal at the input. In a microprocessor system, this is a variable voltage source that is under the
control of the program. While the DAC cannot exactly duplicate the 3 terminals of the trimmer: the circuit can be modified to provide equivalent results.
The NOVRAM memory provides settings for the DAC that are free from problems of humidity and vibration, as well as holding onto those settings during times of no power. Once the NOVRAM memory/DAG combination is in the circuit. the calibration can be made automatic by closing the loop since all mechanical adjustments are eliminated. A self-calibrating system can eliminate all expensive service calls for recalibration.
Duplicating The Function Of The Trimmer
This section will demonstrate a few simple concepts for using a NOVRAM memory and a DAC in combination to modify important circuit parameters. As previously mentioned. a trimmer adjusts small variations of frequency, gain, offset, voltage or current. By properly interfacing the output voltage of a DAC in the analog circuit, these functions can be easily duplicated.
The first example shown will demonstrate how to effect a small adjustment in voltage that can be used as a reference or for some other need. Figure 5 shows an operational amplifier connected to provide a small amount of trim to the output. The 9.9k and 100 ohm resistors provide a division by 100 of the DAC output.
1KO
Vo=-V1+~
Figure 5) The DAC output provides up to 100 millivolts of trim for the operational amplifier output voltage.
If the DAC can be adjusted from Oto 10 volts, this voltage divider provides an offset of up to 100 millivolts. The operational amplifier offset adds this amount to the output, providing up to 100 millivolts of reference voltage trim:
The next example will show how to provide a small offset for a fixed gain amplifier: Figure 6 shows the operational amplifier connected as an inverting amplifier with a gain of 10.
0002-4
8-12
100KO
- 5V --'VY'.---.
Figure 6) The DAC output provides an offset of 0.5 volt for a fixed gain
amplifier.
The fixed gain is established by the 1Kand 10K resistors. As the DAC output is varied from 0 through 10 volts, this voltage, combined with the - 5 volts, reduces the amplifier output by 1/10 of the difference. This gives a fixed offset of up to 0.5 volt in either direction.
The third example will show a different use of a DAC to change the operational amplifier gain. This example uses a CMOS DAC with the ladder network in the amplifier feedback loop.
A short course in CMOS DACs is in order at this time. Figure 7 shows a simple 3-switch CMOS DAC.
v�., (-8 VOLTS)
r-
1
I R I I R
I I 2R
IL.:: __ _
Vo = 0 VOLTS TO + 7 VOLTS IN STEPS OF 1 VOLT
Figure 7) A simplified 3-switch CMOS DAC.
The outputs of a CMOS DAC are in the form of current. The sum of the two output currents is always a constant. In the case of Figure 7, this sum is 'Va x VREFIR. Both current outputs must look into a ground potential. In Figure 7 the lour1 pin is tied to the summing junction of an operational amplifier while the lour2 pin is tied to system ground. The internally provided feedback resistor should be used with an amplifier since its temperature coefficient is identical to the other resistors on the DAC chip. The DAC switches are operated by standard 5 volt logic levels. The . amplifier output in Figure 7 will vary from 0 to 7 volts 1n 1 volt increments depending on the setting of switches SO, S1 and S2. These switches in the 'up' position add 1, 2 and 4 volts, respectively, to the amplifier output. In the positions shown, the amplifier output is 7 volts.
Figure 8 shows the CMOS DAC of Figure 7 in a slightly different configuration.
2R
1-v, " > - - - - - - + - - - V o =
WHERE X = DIGITAL CODE(1-n
Figure 8) A CMOS DAC used in the amplifier feedback loop to adjust the amplifier gain.
The ladder network provides the feedback to the amplifier while the internal feedback resistor is used as the input resistor. If one goes through the equations,
the result for Figure 8 is VO= VI x 81 x , where x is
the digital code for the switch settings from 1 to 7. The circuit gain runs from a low of 8 '7 for the switches in the indicated position, to a gain of 8 when SO is high
and the other switches are low. Table 1 shows a listing of the gains obtainable.
S2
S1
so
GAIN
L
L
H
8
L
H
L
4
L
H
H
22'3
H
L
L
2
H
H
-H
L H H
H L H
,,,,Pis
1''3
Table 1) Gains of the circuit in Figure 5 as a function of the switch settings.
Analog Circuit Examples
This section will present some actual circuit examples for using a NOVRAM memory combined with a DAC. The circuits that appear in this section have been built and tested. The concepts presented may be useful to stimulate ideas which will help to solve the reader's system problems and may even be of immediate use. Figure 9 shows how the NOVRAM memory/ DAC combination provides a voltage or a current for the application.
DACReference UnputVoltage)
Figure 9) A NOVRAM memory DAC combination provides a voltage or a
current to correct analog circuits.
0002-5
8-13
It is, of course, possible for a single NOVRAM memory to provide the address setting for multiple DACs. The DAC size used is selected for the user's application, depending on the accuracy and resolution required. There are even multiple DACs available in a single package such as the SAB 3013 from Philips for more cost sensitive applications.
Tuneable Crystal Oscillator
The first application example of a NOVRAM memory used in combination with a DAC is that of a quartz crystal oscillator. These circuits find application in many areas, including aviation and nautical navigation, as well as time measuring due to high stability The oscillator is normally trimmed with a small padding capacitor in shunt or series with the crystal. This trim is used to 'pull' the resonance point of the crystal by a few parts per million (PPM) to set the operating frequency of the circuit. The capacitor may have to be adjusted in the field to retrim for the aging effects of the crystal and its associated circuitry.
The circuit in Figure 10 uses a NOVRAM memory/ DAC combination to provide the trim voltage for a varactor.
4096. 3690.
3280.
2870. ~ 0 2460. 0
:aw;.; 2050.
g 1640.
1230.
820.
410.
-6 -12 -18 -23 -30 -36 -42 -48 -54 -60 NEGATIVE FREQUENCY SHIFT IN PPM
Figure 11) Tuning range of the tuneable crystal oscillator of Figure 10.
The frequency shift is down so it is recommended to specify the crystal approximately 25 PPM higher than the desired frequency. Initial trimming and re-trimming is easily accomplished by changing the DAC address settings as stored in the NOVRAM memory.
Software Programmable Voltage Reference
Many systems (such as DVMs, test equipment, data acquisition systems and most forms of measurement and control apparatus) require a voltage reference that places a limit on total system performance. Figure 12 shows how a NOVRAM memory/DAG combination can provide a means of adjusting the ouput of a precision 10 volt reference.
�= : =CRYSTAL -10Mhz 1% Film type
Figure 10) Tuneable crystal oscillator.
A varactor is a diode whose capacitance is a function of the applied voltage. This varactor in series with the crystal provides the actual trim function. The fixed operating point for the varactor is supplied through the 100K resistor. Variable bias for the diode is supplied by the DAC through the 470K resistor. Figure 11 shows that a 50 PPM frequency trim range is achievable with the 12-bit DAC used.
� = 1% FILM TYPES
� � =VISHAY, INC. TYPE S-102
+ =POLYSTYRENE CAPACITOR
Figure 12) Software programmable voltage reference.
0002-6
8-14
An LM399A 6.95 volt reference is used in a�bootstrap configuration to supply bias to the LF412 amplifier which in turn drives the LM399A. The 100K resistor insures start-up. The reference supplies bias to the LM11 amplifier, which supplies the circuit's output.
The NOVRAM memory/DAC-1000 combination supplies an offset voltage for the LM11 of 1 millivolt full scale in 1 microvolt increments. The 0.1 �F capacitor insures dynamic stability and low noise at the LM11 output. To calibrate the output to within 1 microvolt, one sets the DAC to half scale and selects the feedback resistor of the LM11 until the output is within a few hundred microvolts of the desired value. Then the RAM portion of the NOVRAM memory is exercised, providing new inputs for the DAC until the desired value is achieved. This setting is then stored in the EEPROM portion of the NOVRAM memory. If a wider trim range is desired, the 1 megohm resistor can be reduced, but this degrades the setpoint resolution appropriately
Self-Calibrating, Interchangeable Probe Thermometer
A standard industrial temperature sensor with high linearity and long term stability is obtained using platinum resistance temperature detectors (RTDs). The RTD is specified in terms of its resistance at 0� centigrade (as this is a function of the manufacturing process), while the gain slope is relatively constant from unit to unit. A constant gain amplifier with an offset to compensate for the changing impedance at 0� centigrade is shown in Figure 13.
10.00 VOLTS
OUTPUT 0-5 VOLTS
= o-so�c
RPLATINUM =ROSEMOUNT, INC. TYPE 118MA �FILM TYPES 1% TOLERANCE ""FILM TYPES .1% TOLERANCE
The NOVRAM memory/DAC combination is used to modify the offset voltage of the amplifier to allow full interchangeability of probes in the field.
The plantinum RTD shown has a � 3 % tolerance at
0�C ( � 7.5�C) and is driven with a 1 milliampere
constant current source by placing it in the feedback loop of the LF412 amplifier. The constant current is provided by the 10 volt reference IC. The amplifier output will be a linear function of the sensed temperature at the RTD. The 1 �F capacitor limits noise pickup and also insures that the RTD, a wirewound device with parasitic inductance, does not cause amplifier oscillations. The second half of the LF412 provides a fixed gain to the signal.
The 90.9K resistor provides a current to the summing junction of the amplifier to move beyond the correction for the worst case sensor. The NOVRAM memory/DAC pair then pull enough current from the summing junction to correct for the inserted RTD. Over a 0�C to 55�C range, this circuit is accurate to
within � 0.25�C while allowing the use of probes with
a � 7.5�C tolerance specification.
Automatic Scale Calibration
The scale normally does not worry about a zerolevel reading from its sensor, since it may have a wide variety of items on the platform such as wrapping paper or containers. An algorithm is usually required to automatically zero the scale before loading the material into the container. The transducer used in scale applications has a large variation in gain slope which must be corrected before shipping the scale or when changing the load cell. Figure 14 shows a circuit for providing these necessary corrections for the gain slope of the sensor.
-15V
VAEFINPUT
(FULL SCALE REFERENCE) FORTHEA-D
�=1% Film type
��= Typical-e-NationalControls.lnc. Type 3220 Scale ptatlonn Gain= 2.2mV per wit of applied excitation (15Vrecommendedl �10% Z1N=350n
Figure 13) Self-calibrating, interchangeable probe thermometer.
Figure 14) Automatic scale calibration. 8-15
0002-7
The transducer shown, combined with the fixed gain amplifier, can produce outputs of 7.424 volts to 9.075 volts for full load depending Qn the transducer selected. To bring this result to the required value, the NOVRAM memory/DAG combination is used to vary the reference of an analog-to-digital converter. Since the DAG and the platform bridge are driven from the same supply, the measurement is ratiometric and no stable voltages are necessary. As the -15 volt supply changes, the readout on the display will not vary. To calibrate a new platform, the scale is first zeroed out using the internal algorithm and then a fixed known weight is added to the platform. Then the NOVRAM memory/DAG unit is exercised until the correct readout is obtained. This calibration can be called from the scale's keyboard. Security for this adjustment can be in a software access code which is also stored in the NOVRAM memory.
Gain Trimming For Photomultiplier Tube
The last example handles gain variations in a slightly different manner. The gain of a photomultiplier tube varies over time, temperature and power supply for a given input level. The output is a current from a high impedance source. A circuit to trim the changing gain is shown in Figure 15.
fine resolution is to use an 8-bit DAG connected as shown in Figure 8 in place of the DAG arrangement of Figure 15. If the feedback resistor of the left-hand amplifier is changed to 50K, very fine tuning (around a voltage gain of 2) is possible. This gain of 2 is established when the DAG is set for midrange of the digital value which gives a fine tuning range.
Conclusion
This application note has shown how the NOVRAM memory can be used to replace commonly used mechanical components such as trimmers and DIP switches. This replacement improves reliability and reduces service costs for recalibration and resetting. In addition, actual equipment costs can be reduced.
Once a single NOVRAM memory is in the system, it is easy to include additional features in the unused portions. For example, a system designer could use a NOVRAM memory to replace DIP switches used for configuration data and then place calibration data for DAGs in the unused memory. If even more unused space exists, storage of other desired data such as ID numbers or a service log would be possible.
The possible uses of NOVRAM memories are limitless. The designer is encouraged to build upon the ideas presented by this application note.
I I I
Figure 15) Gain trimming for photomultiplier tubes
This current is converted to a voltage by the amplifier on the left side of the figure. For a full scale current of 100 �A, the output voltage of this amplifier is 12 volts. This voltage output is used as the reference input for a NOVRAM memory/8-bit DAG combination which amplifies the reference from 1/255 through 1 depending on DAG setting. This gain can be varied in steps of 1/256. The currents out of the photomultiplier tube are normally accurate to only 1% once the calibration is complete. Some applications, however, may require smaller steps in resolution. If this is the case, one could use a 10-bit DAG. Another method of obtaining
8-16
0002-8
Jico,
AN-105
15
rG-- --,
I12
I 11
I
I
13 1
I
HOST
I
SERIAL
I 1 14
INTERFACE
8051
IL ____JI
8052
74HC367
PX.X P3.1
P3.0
1 CE
_11_ _ __ 2 SK
10
3
- - - - - DI
4 DO
X2444 8
Yee 7
STORE RECALL 6
5 Yss
+SY
0003-1
THE X2444 SERIAL NOVRAM* TEAMS UP WITH
THE 8051 MICROCONTROLLER FAMILY
Add scratch pad RAM and nonvolatile parameter store via the 8051 serial port and still maintain full use of the serial port as a UART.
Application from Rick Orlando Written by Richard Palm
*NOVRAM is Xicor's nonvolatile static RAM device.
8-17
INTRODUCTION
The X2444 is a 256 bit serial NOVRAM internally configured as sixteen 16-bit words of RAM overlaid bit for bit with a nonvolatile E2PROM. The X2444 has the standard hardware RECALL and STORE inputs plus the ability to perform these same operations under software control, thereby freeing two microcontroller port pins for other tasks. The serial interface allows the X2444 to be packaged in a low cost space saving 8-pin mini DIP.
When teamed with the 8051 family of microcontrollers, the X2444's small physical size, software instruction set and serial interface make it an ideal parameter store and scratch pad memory while maintaining full use of the 8051 serial port as a UART.
SCOPE
This application note describes interfacing the X2444 with the 8051 family of microcontrollers. Emphasis will be placed on the timing considerations of the interface, and explaining the modifications to the instruction words for normal device operation. This note assumes the reader has access to a Xicor Data Book and Intel Microcontro/ler Handbook.
SERIAL PORT OPERATION
Port 3 on the 8051 provides a serial port that can be used in two basic configurations, full duplex and half duplex. This note examines the half duplex (mode 0) operation in interfacing to the X2444. Port 3 pin 1 (P3.1) is the clock output for both transmit and receive modes and Port 3 pin O (P3.0) is used for bidirectional data transfers.
The clock output frequency is 1/12 of the XTAL oscillator input frequency. To simplify timing calculations this note will assume an input frequency of 12 MHz resulting in a symmetrical 1 MHz output on P3.1.
The P3.1 and P3.0 pins when inactive (neither transmitting nor receiving) are always a logic 1 (HIGH). When a data transfer commences P3.1 will be LOW during machine cycle states S3, S4 and S5 and will be HIGH during states S6, 51 and S2. When transmitting, data is shifted out on P3.0 during S6P2 (state 6 phase 2) LSB first. When receiving, data is sampled during S5P2. Refer to Figure 1 for the basic 8051 serial port timing.
8051j2444 PIN/ PIN
I I I S6
s1
S2
~ I M I ~ I S6 I ~
XTAL2
P3.1/SK P3.0/DI
14
---
~v-
1/FsK
(1 �.S)
,_
l
1-KL (500 ns)
_.._1_
..._-
__..
I (50ls0KHns)
l
to. (916 ns)
--- ....
-~
tDH (84 ns)
P3.0/DO
x
Figure 1. 12 MHz 8051 Serial Port Mode 0 and X2444 Timing
___,.
x
j.-S5P2 DATA TAKEN
0003-2
8-18
HARDWARE CONNECTIONS
The X2444 directly interfaces with the 8051 with no external circuitry required. DI and DO of the X2444 are both tied to P3.0, SK is tied to P3.1, CE is tied to any free port pin configured as an output and STORE and RECALL are tied to Vee (see Figure 2).
8051 8052
PX.X 11
P3.1 10
P3.0
+5V
X2444
CE
Vee 8
STORE
SK 3
RECiU &
DI
DO
Vss
SYSTEM CHARACTERISTICS
Under normal operating conditions the X2444 expects CE to transition LOW to HIGH when SK is LOW in order that the first bit of data can be clocked into the X2444 on the first rising edge of SK. The data is sampled to see if it is "O" (a don't care state) or a "1" which is recognized as an instruction start. The 8051, however, places both P3.1 and P3.0 in the HIGH state when not actively transmitting. THIS IS OK. The X2444 internally gates CE and SK; therefore, toggling the port pin controlling CE to a HIGH effectively generates the first rising edge of SK, and also clocks in the HIGH present at P3.0 (DI).
What this does is clock a "1" into the X2444 indicating the start of an instruction prior to any shifting operation by the 8051 serial port. This will require dropping the leading "1" from the instruction. See Table 1 for the WAS/IS conditions for the equivalent instructions to be used by the 8051 .
Figure 2. Basic Configuration
X2444 OPERATIONS REVIEW
The X2444 is a serial device and in this application all chip functions are handled via the software instructions. The 8051 transmits data LSB first but the instruction format for the X2444 shows the instruction to be transmitted MSB first. This requires a simple transposition of the instruction, MSB for LSB. The memory is effectively a FIFO, so the data to be stored need not be transposed.
Internally the X2444 increments a bit (clock) counter. This is used to indicate the end of an instruction and if a read or write instruction is received, to increment a bit position pointer. This pointer enables individual RAM cells for writing and reading. The counter for the pointer increments from zero to fifteen. If CE remains HIGH and SK continues to clock, the counter will rollover from fifteen to zero. The word address does not increment; therefore, during a write operation if SK continues to clock and CE is HIGH, a 25th rising clock edge (8 edges
for instruction + 16 edges for the data word + 1)
would cause bit position zero to be overwritten.
INSTRUCTION
WAS
WADS STO SLEEP WRITE WREN RCL READ�
7 6 54 3 2 10
xxxx0 0 0 xxxx0 0 1 1 xxxx0 1 0
AA A A 0
x x x x 1 1 xxxx1 0 1 x 1 A A A A 1 1
7 6 5
x0 0 x1 0 x0 1 x1 1 x0 0 x1 0 f x1
IS
43 2 10
0 xxxx 0 xxxx 0 xxxx
0 AA A A
1 xxxx 1 xxxx
1 A AAA
�Note: bit 7 of the READ command should be a "1" to avoid bus contention.
Table 1. Reconfigured Instruction Format
The 8051 will still generate eight rising clock edges on P3.1 for each byte loaded into the shift register (SBUF), effectively providing the X2444 with nine clocks for the first byte. For the single byte instructions the ninth clock and data are ignored by the X2444. Refer to Figure 3 for the single byte instruction timing.
0003-3
8-19
8051152 I 2444 PIN I PIN
l/OJCE P3.1/SK
I
'CLK1
P3.0/DI
INSTRUCTION START
L_
EFFECTIVE DATA XFER
Figure 3. Single Byte Instructions
WRmNG
Writing to the RAM array is straightforward. The write instruction is issued by the 8051 in the same manner as the single byte instructions. The MSB (eighth bit) of the instruction byte is clocked in on the equivalent ninth clock rising edge. This bit is recognized as the first data bit transfer and is initially written into the addressed word's bit position zero. The 8051 will continue to transmit two more bytes of actual data. The LSB (bit "O") of the first byte will be physically located in bit position "1" and all subsequent bits will also be offset by one. The MSB (sixteenth data bit) of the word will be written into bit position zero, overwriting the last bit of the instruction byte. Refer to Figure 4 for the sequence of operations.
READING
Reading data back from the RAM array is quite similar. The X2444 begins to shift data out during the instruction cycle (more on this later). After the instruction is shifted out, the 8051 must turn around P3.0 and configure it as an input. CE and SK are static during this period and the DO output will remain unchanged until after the rising edge of the first 8051 receive data clock. Therefore, the first data shifted into the 8051 will be from bit position "1 ", equivalent to the LSB originally written. Refer to Figure 5 for the sequence of operations.
8051/ 2444 PIN PIN
PX X/CE - - \
FIRST DATA
� ~Kl_ ~ - - -SH'.:.'"6~
�-��~
P3.1/$K ~~~ITADD --- R ---E -~ROS LLOS VER
JllST~~~
START
P3.0IDI
2 3
s e
g 10 11 12 13 1� 15 o~~A=S:
EFFECTIVE WRITE INSTRUCTION
Figure 4. Write Cycle Sequence
-c PX.X/CE CLK1 P3.1/SK
Figure 5. Read Cycle Sequence
THROW AWAY
8-20
NOT RECOGNIZED
0003-4
BUS CONTENTION
There will not be any bus contention for single byte instructions or the write command. However, for the Read command there could be contention. While the 8051 is still shifting out the instruction byte the X2444 begins to output data on the same line. Refer to Figure 5, just after the falling edge of clock eight.
The 8051 shifts out data at S6P2. If the data changes state from "O" to "1" a high current enhancement FET is turned on for two 8051 system clock cycles. This is used to provide a fast rise time. At the end of this two cycle period, the enhancement FET is turned off and the output is held HIGH by a depletion mode FET that essentially looks like a resistor pullup (Refer to Intel's Microcontro/ler Handbook [1984] pages 6-6 and 6-7). Note that the high drive circuit is enabled only for data state changes from "O" to "1 "; therefore, if the output is already a "1" and another "1" is shifted out on P3.0, the high drive will not be turned on. This depletion FET can source a maximum of 250�A if the port pin is grounded.
The instruction table indicates that bit seven for the READ instruction should be a "1 ". The reaso�n for this is to guarantee that the high drive period is off before the X2444 begins to output data. If bit seven were a "O'', the 8051 would turn on the high drive circuit to return P3.0 to the inactive state, possibly generating a high current contention problem with the DO output of the X2444. Figure 6 illustrates the timing involved during clock eight. The high drive period of the 8051 is turned off well before the X2444 begins to output data.
VERSATILITY
The DO output of the X2444 is always in the high impedance state unless it is outputting data in response to a READ command. Therefore, the serial port of the 8051 need not be dedicated solely to a serial memory interface.
Figure 7 illustrates the versatility this affords. This figure depicts the basic system components required in a remote location controller. Notice that the 8051 serial port has access to both the X2444 and through the use of the CE control line maintains full use of the serial port as a UART. Therefore, it can receive downloaded parameters from a host, re-enable the serial port for X2444 communication, then store the data either temporarily in the X2444 RAM array or permanently in the X2444 E2PROM array.
f"G:- 1-5-i
121
111
....----,~
I
____ 13 1
------L~
J
8051
8052
74HC367
X2444
PX.X t---+--+---- CE
P3.1 11
2 SK
P3.0 10
3 DI
4 DO
Vee 8
STORE 7
--6 RECALL
Vss
HOST SERIAL INTERFACE
+5V
Figure 7. Shared Serial Port
~ P3.t/SK
CLK8
HIGH DRIVE PERIOD
l-1
P3.0 CHANGE FROM
__ { ( P3.0/DI
--------------.1t'"",.___ P3.0/00
~I------- ___..
._
OUTPUT TO INPUT
z 8051 DEPLETION MODE FET PULLUP ONLY _ _ _ _ _)),__ _H_ IGH_ _ __
HIGH Z
)>-------- --1J _
WORST CASE CONTENTION
.(. , 1-f-------
..___ _ _ _ _ _ _ __./..__ _ _
Figure 6. Worst Case Bus Contention
0003-5
8-21
CONCLUSION
This application note has shown that with no extra hardware the X2444 interfaces directly with the 8051 family �of microcontrollers, providing a nonvolatile memory store and scratch pad memory and
maintaining full 8051 UART capabilities. It is the ideal solution for applications where extra memory is required but few port pins are available for implementation.
0003-6
8-22
AN-106
'Cll!
VOLUME
TREBLE
0073-10
E2POTTM DIGITALLY CONTROLLED POTENTIOMETER
BRINGS MICROPROCESSOR CONTROL TO AUDIO SYSTEMS-
ADDS FEATURES
By Jeff Randall
E2POTTM is a trademark of Xicor, Inc.
8-23
INTRODUCTION
Control of most audio circuits is still accomplished the same way it has been for the� last fifty years or so. From the volume control knob to the sliders on an equalizer, the control is human, the feedback is through the ears, and the control element is the mechanical potentiometer. Microprocessors have. entered nearly every other segment of electronics, and as they enter the audio segment, they slam headlong into the mechanical potentiometer.
While this article focuses on microprocessor control of conventional audio circuits through the use of digitally controlled potentiometers, it should become clear how these devices can be applied to many other applications as well.
Figure 2, utilizes two linear taper potentiometers to control the gain of an active filter. In this configuration, the potentiometer replaces a portion of both the input and feedback resistors. By moving the position of the wiper, both resistors change in opposite directions.
R2
R1
VIN 0-.....VV\,_....l\J"""'.,._.J\/'IJ'\I-~
CONVENTIONAL AUDIO CONTROL
A look at conventional methods for audio control should help to illustrate the situation:
Designs incorporating mechanical potentiometers are still found in the majority of audio applications. For example, the volume control on most car stereos is a rotary potentiometer. Volume control circuits generally resemble Figure 1. In this design, the potentiometer is used to control the signal reaching a fixed gain amplifier section. A potentiometer in this application would likely have a logarithmic taper, since volume is a logarithmic function.
AUDIO TAPER POTENTIOMETER
Figure 1: Conventional Potentiometer Volume Control
0073-1
Tone controls can vary from single pot and capacitor circuits to complex active filters. The Baxandall filter network has been the workhorse of the audio industry for years. This design, illustrated in
Figure 2: Baxandall Tone Control Circuit
0073-2
Graphic equalizers are one of the fastest growing modes of audio control. A graphic equalizer contains a group of band pass filters, usually seven. Each filter has a potentiometer controlling the gain to that band pass. Potentiometers generally appear as sliders on the face of the equalizer.
A typical graphic equalizer schematic is shown in Figure 3. EQs are used to compensate for the imperfections of a listening environment by boosting or cutting gain at specific frequencies. By using a spectrum analyzer and a "pink" noise generator, the response of an audio system can be customized for a particular room or concert hall. This is accomplished by inputting a desired response to the system-generally flat across the audio band, with some attenuation at higher frequencies, often referred to as "pink" noise. The equalizer is then adjusted until the system output, displayed on the spectrum analyzer, closely matches the pink noise input.
This process of matching a system to a room is often referred to as environmental calibration. It is a process requiring the listener to read the display of the spectrum analyzer and manually adjust the potentiometer/sliders of the equalizer.
8-24
BAND Re ~
2 ____IC:,1 __
Ro
3 ---- ---L1
4 ---- ----
5 ---------
6 ---------
7 .,____~ """,_,__..
OUTPUT
Figure 3: Graphic Equalizer Configuration
0073-3
The heart of the control of each of the circuits described earlier is the mechanical potentiometer. Automated control of these devices is a challenge. Clearly, microprocessor control of these functions is desirable. The control elements utilized for automated control are discussed below.
AUTOMATED CONTROL ELEMENTS
While these devices are primarily used for industrial control applications, motorized potentiometers offer a relatively straightforward approach to simple audio control circuits. In these devices, a DC reference voltage, or a digital signal representing position is input to a small motor assembly that is linked to a rotary potentiometer. Drawbacks to this type of system are numerous, including noise caused by the motor assembly as well as the increased space and power requirements of placing a motor on an audio PC board.
DIA converters can also be used to control and manipulate analog circuit functions, but introduce more complexity. These devices are the choice of high fidelity digital audio controls due to their high precision. But for the analog circuit designer, they can be a little intimidating. For example, one way to control volume with DIA converters is illustrated in Figure 4. In this circuit, the signal is sampled with a AID converter, manipulated by a microprocessor, and returned to the analog world with a DIA converter. This design entails sampling, real-time processing, as well as AID and DIA conversions. Not only may the analog designer be faced with portions of his circuit that may be unfamiliar, the results may be overkill.
A/D
K
v,
INPUT
Figure 4: Volume Control Using DIA Conversion
0073-4
An array of resistors with a wiper tap that can be selected with digital control offers many advantages of the microprocessor world without the complexity of DIA conversion. These are referred to as digitally controlled potentiometers. Logic circuits, counters, and memory circuits are often teamed up with resistor arrays to accomplish an approximation of potentiometer control. Recently, a few manufacturers have introduced devices which incorporate many of these functions in one device. Examples are Xicor's X9MME, Toshiba's T09169AP, and National's LMC835.
The Toshiba and National parts are designed around specific audio applications and are distinctively different from the Xicor device. They incorporate features that lend well to audio designs, but are not intended for general purpose potentiometer replacement. Moreover, they offer only a limited number of wiper positions.
Xicor's X9MME combines a single 99 position potentiometer with three line digital controls. Figure 5 contains a functional diagram, pin description and mode selection for the device. In addition to the internal counter circuitry for wiper position control, this part also incorporates nonvolatile memory to retain wiper position. It has been designed as a digitally controlled replacement for the mechanical potentiometer. With its conventional three terminal potentiometer design, it integrates easily into existing analog designs.
8-25
Functional Diagram
U/D
INC
7 BIT COUNTER
Cs
TRANSFER ARRAY LOGIC
NONVOLATILE MEMORY
WIPER POSITION DECODE
Mode Selection
cs INC U/D Mode
L ~ H Wiper Up
L ~ L Wiper Down
_r H
x Store Wiper
Position
PROGRAMMING CONTROL AND
POWER-ON DETECT
Vee
GND-----'
Vt_
'---------Vw
0073-5
Pin Configuration
0073-6 Figure 5: The X9MME Digitally Controlled Potentiometer
To illustrate digital control of potentiometer circuits, the X9MME from Xicor was used to replace mechanical potentiometers in a well known audio circuit. The following should demonstrate the ease of designing with the X9MME as well as the advantages of microprocessor control in. audio circuits.
THE X9MME IN AN AUDIO CIRCUIT
The Baxandall tone control circuit is the basis for the designs shown here. The following sections will discuss the principles behind the Baxandall circuit
Pin Names
VH
High Terminal of Pot
Vw
Wiper Terminal of Pot
VL
Low Terminal of Pot
Vss
Ground
Vee
System Power
U/D
Up/Down Control
INC
Wiper Movement Control
cs
Chip Select for Wiper
Movement/Storage
and then walk through the design utilizing the X9MME. Special design considerations for the X9MME will be discussed, and the performance and operation will be evaluated.
The Baxandall circuit, its response, and equations for gains and filter frequencies are shown in Figure 6. This circuit contains two active filters whose gain is controlled by two potentiometers. Figure 7 illustrates the bass portion of the circuit. The maximum gain of this circuit is at low frequencies, where the capacitors in the circuit can be considered to be open circuits. The capacitors have been omitted for clarity. (The treble portion of the circuit, not illustrated here, follows along similar lines.)
8-26
Schematic
o-1 ..... VIN
rvv~t---t�~--..... ~~""'.-411~""",.....~""'---.
C4
System Frequency Response
0073-7
1 FLB = 27T R1C1
Avs = 1 + ~ R1
FHB = 27T (R1 + R3 + 2R5) C3
AVT = 1 + 2R5 + R1
R3
Figure 6: Active Audio Preamplifier
log F
0073-8
With the addition of another potentiometer on the output of the Baxandall network, the system represents a single channel of an audio preamplifier. The circuit contains three potentiometers which control volume, treble and bass. These pots would appear as knobs on the face of a home or car stereo, to be adjusted by hand to control and shape the sound reaching the amplifier and speakers.
- Avs -R-1 - + R-2 I I R1
Maximum Bass Boost
Figure 7: Bass Portion ofActive Preamp Circuit
0073-9
8-27
Neglecting the digital control lines and 5V power for the X9MME, the circuit is shown in Figure 8. The X9MME will replace bass, treble and volume potentiometers. Note that this does not alter analog design considerations.
It should be noted that R2 and R4 are both linear taper pots. Since the X9MME is also a linear taper pot, it is a direct replacement. Ry, the volume potentiometer, is specified as an audio taper pot, since it is used for volume control. By placing a small resistor from wiper to low on any linear pot, as shown in Figure 9, an audio taper can be approximated. In this case a resistor of one-tenth the total pot resistance is a close approximation of an audio pot (EDN Nov. 13, 1986).
This circuit is designed to have a gain of one across the entire audio range, with the potential for a boost or cut of 20 dB at the frequencies selected by the designer.
THE DESIGN
The design chosen is intended for car stereo applications. It should therefore operate from a single ended, 12V supply and adapt well to speakers that
are commonly used in automobiles. Considering the limited bass response of most car speakers, the bass boost or cut should not be so low that the speakers cannot reproduce the sound.
The desired circuit would operate from a 12V power supply, have a � 20 dB boost or cut at 100 Hz (bass) and 1O KHz (treble). The available resistor values for the X9MME are 1OK, 50K, and 1OOK. The following steps outline the design:
1. R2 = 50 Kn (arbitrary, X9503)
The design must start somewhere. This value was actually determined after running through the design a couple of times and comparing the values determined for the potentiometers with those available.
2. Avs = 1 + R1 /R2; for 20 dB (10),
R1 = R2/9 = 5.6 Kn
The bass portion of the circuit must have a maximum boost of 20 dB. This is determined with the bass pot all the way to the input side. A quick look at Figure 8 will illustrate this.
Figure 8: Active Preamp with Bass, Treble and Volume Controls
TREBLE
0073-10
.
For Audio
Taper,
Use Rz
=
1R0.
0073-11
Figure 9: Utilizing External Resistors to Va!JI Potentiometers Trim (EON Nov. 13)
8-28
0.8
0.7
.f 0.6
~ 0.5
::>
>o 0.4 i--i--i--t--7r--.~~h"-1i-#-1#-i
0.3 i--t--t--7r---7'~i--llll'""-1~'--#1---j
0.2 1--~~1�-:~F-:i~f-7'1~--I
WIPER TRAVEL
0073-12
3. FL = 100 Hz, FLB = 1 KHz
1
1
C1 = - - - -
27T FLsR 1 27T(1000)(5.6K)
= 2.84 x 10-a F
Here, the formulas for the cutoff frequencies of the active filters are broken down to determine the element values to use.
4. Rs = 2.2 Kn (arbitrary)
5. AvT = 1 + R1 + 2R5 = 10,
R3
R1 + 2R5
R3 = g = 1.1K
Use 1 Kn
Here, the maximum treble gain is calculated in similar fashion to the maximum bass gain.
1
1
6.C3=
=1.6x10-a
277' FHR3 27T(1 OK)(1 K)
7. R4 2: 10 (R3 + R1 + 2R5) = 110 Kn
Use 100 Kn
8. Rv = 1o Kn (arbitrary)
The circuit with the X9MME inserted is shown in Figure 10. These are the values that were used in lab experiments and for demonstration purposes.
It should be noted that some considerations in the design had to be altered when the X9MME was inserted into the circuit. The X9MME is a source of high frequency noise. There are internal voltage generators on the device which are used to operate switches internally as well as to store information into the device's nonvolatile memory. The principle noise frequencies begin at approximately 150 KHz, and while this is beyond the audio range, it can still be a source of problems in the circuit. For this reason, capacitors were added around the X9MME to filter noise. These are included in Figure 10.
DIGITAL CONTROL
The digital control lines of the X9MME are INC, CS, and U/D. CS (chip select) allows the wiper to be moved. U/D (Up/Down) determines the direction in which the wiper will move, and INC (increment) initiates movement on its falling edge. CS is also used to store the wiper position in nonvolatile memory. When CS is returned high, a store operation is commenced.
When initially designing with the part, it was helpful to assemble a simple switch system for controlling the parts. A 555 timer was used to generate a fairly slow clock pulse and connected through a momentary switch to the increment pin of each X9MME. With pull up resistors on each digital line, a
grounding switch was connected to U/D and anoth-
er to CS. To move the wiper up, CS was set to
100K.O.
O.o1 �E.C'"l
X9103 10K.O.
6
-""""--""'""-_V\11_ .:r.0.001 �F
Figure 10: E2PREAMP with Three X9MME-No Digital Controls Shown
8-29
8.0. 0073-13
ground, U/D to 5V and INC pulsed with the clock. Each step of the clock produced a 1% change in wiper position. Figure 11 illustrates the switching network that was utilized for controlling all three X9MMEs.
This initial procedure allowed the analog portion of the design to be separated from the digital. Once the circuit was functioning adequately with the switch network controlling the X9MMEs, microprocessor interface was relatively simple.
MICROPROCESSOR INTERFACE
With three devices on the board, 9 control lines are required. To simplify interface to an 8 bit microprocessor, the INC lines for all three parts were connected to the same pin.
The pin configuration used for interface to the 6502 microprocessor system is as follows:
A1 A5 A5
A4
A3
A2
A1
Ao
NC INC CS1 U/01 CS2 U/02 CS3 U/03
#1 =Volume
#2 =Bass
#3 =Treble
To move the wiper of a given pot, that pot's CS is brought low, the U/D for the appropriate pot is asserted H or L depending on the direction of wiper movement, and INC is toggled. For example, to increase the volume the following two patterns are alternated to the port connected to the E2PREAMP.
NC INC CS1 U/01 CS2 U/02 CS3 U/03
0
0
1
1
1
1
1
0
1
1
1
1
1
Note that CS has been selected, U/D set to 1 and INC toggled. Bass and treble settings are altered in a similar manner.
0.1 �.F
LM 555CN
.I.0.1 �.F
100 K.O. 2M.O.
INC
0 UP
_( DOWN
SEi
v
B
Figure 11: Switch Network for Manual Operation
8-30
VOLUME BASS TREBLE
0073-14
The microprocessor system used in the lab consists of a 6502 based keyboard monitor. The controlling program scans the keyboard for a recognized ASCII character which transfers control to the specified subroutine. For any given input, the appropriate increment is toggled 1Otimes before returning to the controlling program.
An example of a volume, bass, or treble adjusting program follows:
LOX #00 0333 LOA 0006
STA AOOO JSR E02C LOA 0007 STA AOOO JSR E02C INX CPX 0008 BNE 0333 RTS
Load counter with zero Load accumulator with first
pattern Output pattern 5 ms wait Load 2nd pattern
Compare counter to 1O
In addition to the adjustment subroutines, an initialization subroutine can also be called up. This subroutine sets the volume to zero and bass and treble to 50%. This is used to reset the controls. It would be used only during installation of the system.
This first section of the one time initialization program sets all pots to zero.
LOX #00 0111 LOA 0000
STA AOOO JSR E02C LOA 0001 STA AOOO JSR E02C INX CPX 0008 BNE 0111
Load counter with zero Load accumulator with first
pattern (80h) Output pattern 5 ms wait Load 2nd pattern (COh)
Compare counter to 100
This section sets the bass and treble pots to 50% and returns control to the controlling routine.
LOX # 00 012C LOA 0003
STA AOOO JSR E02C LOA 0004 STA AOOO JSR E02C INX CPX 0005 BNE 0333 ATS
Load counter with zero Load accumulator with first
pattern (85h) Output pattern 5 ms wait Load 2nd pattern (F5h)
Compare counter to 50
OPERATION AND PERFORMANCE
The E2PREAMP circuit operates much like many sophisticated home stereo systems today. All controls are digital switches-in this case, a keyboard for demonstration purposes only. There are no moving parts beyond the switches, and the entire system is relatively free from problems with vibration or jarring (potential hazards in mechanical pot systems).
Keys 1 through 6 on the" keyboard represent the up down controls for the circuit. By depressing 1, the volume is increased by 1Osteps. Key 2 decreases volume in the same way; 3 is treble up; 4 is treble down; 5 is bass up; 6 is bass down. The I key calls the initialization routine. Beyond allowing control of step size and the auto zero or initialize function, the present system does not take advantage of the versatility of microprocessor control.
Performance of the system was nearly identical to the same circuit with mechanical potentiometers. The X9MME is quiet to -65 dB below a 1V signal, which is fair for audio quality devices. For audiophile quality, this number should be around -120 dB, but in car stereo or communication equipment applications this device works adequately.
Aside from the obvious advantage of a lack of moving parts, the ability to choose step size in adjusting the controls has shown to be the most useful added feature. Ten steps per adjustment proved to be an easy value with which to work.
Having demonstrated the ability of the X9MME to replace mechanical potentiometers in analog circuits, more complex circuits may now be considered. With microprocessor control, advanced circuit design and digital control simply becomes an extension of the principles discussed so far.
Microprocessor control of this and other analog circuits is simple when utilizing a digitally controllable potentiometer. The gain of the entire circuit, or the boost or cut. of a given frequency range is instantly alterable via microprocessor commands. Once control is assumed by the microprocessor, any parameter of the analog circuit that is controllable by a potentiometer is available to the programmer.
For example, the graphic equalizerI spectrum analyzer combination discussed earlier can easily be automated once microprocessor control is assumed. By controlling the position of potentiometers that control the gain of the individual equalizer bands, the system frequency response can be calibrated to any room or listening environment. Here is
8-31
just one scenario: A "Calibration" �button is depressed on the equalizing circuit. This .activates a "pink" noise generator which sends a short burst of sound to the system. The spectrum analyzer in the system then decides which frequencies require adjustment, changes the positions �on the �appropriate potentiometers, and the system is. calibrated. No sliders need to be adjusted; no separate (and expensive) spectrum analyzer; moreover, a relatively unsophisticated user can now perform an accurate environmental calibration of the system.
A simpler version of an auto calibration circuit could be incorporated into home and car stereos �as a one time only installation adjustment. The scenario would be as follows. When a� car stereo is first installed, the installer would push the calibration button on the back of the unit. This would adjust a compensation circuit, separate from the main .tone controls. The settings would then remain in the nonvolatile memory� of the digital pots until the system were upgraded or installed into another car. Thus the same unit would be customized for different speakers, different amplifiers, and even different auto interiors.
X9MME ADVANCED FEATURES
The Xicor device utilized in this design is suitable for audio applications, but it is a general purpose device that may be even better suited for other analog applications.
'The X9MME has 99 steps across its range. In most audio applications, this high resolution is inaudible. However, when used in auto zero and balancing circuits, this resolution is invaluable.
The device's nonvolatile memory may be of limited use in some of the. applications mentioned here, since a listener may not want to retain previous audio settings. But when used in a once-only calibratiOn circuit, the nonvolatile memory eliminates any need for preventing a customer from changing the factory settings of a mechanical potentiometer. In a television cable decoder, for example, potentiometers abound. If cable companies used nonvolatile digital potentiometers in place of mechanical pots, the incessant headache of having to make adjustments because of jarred equipment or tampering could be eliminated.
The X9MME's convenient packaging and inherent digital control characteristics can be used to advantage on the assembly line. Manufacturing of devices requiring manual adjustment of potentiometers is always limited by the speed of the laborers and equipment used to set the pots. In addition, units often must remain partially assembled, or allow access holes for screwdriver adjustment of pots. The X9MME's conventional 8 pin DIP package can be automatically inserted with handlers used for other DIP. devices, and trimmed to an appropriate value with an assembly line computer or by an internal microprocessor.
CONCLUSION
Microprocessor control of analog circuits is now easier than ever. The X9MME from Xicor is more than a simple DAC. Not only can this device be used as a precision voltage source, it can replace any resistive element in nearly any analog circuit. Without altering existing analog circuit designs, the designer now has the ability to manipulate analog circuit functions with the digital potentiometer as his control element.
REFERENCES
1. Giles, Martin, et al, Audio/Radio Handbook, Santa Clara, CA: National Semiconductor, 1980.
2. Gray, Paul R., Meyer, Robert G., Analysis and Design of Analog Integrated Circuits, Toronto, Canada: John Wiley and Sons, 1984; pp. 635700.
3. Rumreich, Mark, "Resistors Provide Nonlinear Pot Tapers", EDN November 13, 1986, pp. 292, 293.
4. Stremler, Ferrel G., Introduction to Communication Systems, Reading, MA: Addison-Wesly Publishing Co., 1982; pp. 93.
5. National Semiconductor Corp., "Product Data Sheet, LMC835", April, 1984.
6. Toshiba Corp., "Product Data Sheet, TC9169APTC9170AP" June 1985.
8-32
1 1 T1
: liClll!
I I I I
(
l_j 1J_ -'lt!~~
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NONVOLATILE DATA INTEGRITY: INADVERTENT WRITE/STORE ELIMINATION
By Applications Staff
Xicor's nonvolatile memory products are backed by designed-in protection features which ensure data integrity. These include:
� Onboard Vcc Sensor All operations inhibited when Vee~ 3.0V.
� Noise Filter A feature which blocks noise spikes on control lines.
� Orderly Power Transition The device will not self-generate inadvertent write/store operations.
� Write/Store Inhibited Control Pins Multi-pin write/store command signal requirements provide both data security and design flexibility.
New Design Features
� Software Write Protection
� Previous Recall Latch
� Command Sequence
With Xicor nonvolatile memories, data is maintained through power-on, power-off, power-down, system crash, and the entire range of system conditions when some simple design rules are observed. Often nonvolatile system designers are frustrated by inadvertent system command signals during power-up and power-down operations. Being nonperiodic in nature, these elusive culprits can lead the designers to the false conclusion that the memory device is malfunctioning. This, however, is rarely the case. The system is more often sending an unintended write/store command. This problem can be easily resolved as shown in this application brief.
GIG01 Going to Sleep
Just as a person falling asleep at the wheel can inadvertently command his vehicle into an undesirable situation, digital systems transitioning from normal operation to a power-off state or vice versa can distribute random data, addresses, and control signals along the way.
Since Xicor nonvolatile memories accurately and reliably store data as instructed, data stored at powerdown will be impeccably retained and available upon power-up. (That's nonvolatile GIGO.)
Protection-Conscious Design
Data integrity is a major criterion with Xicor products and several superb features were designed into Xicor's memories to ensure it.
� Vee Sensor An onboard sensor establishes a threshold supply voltage of 3.0V below which write operations on E2PROMs and store operations on NOVRAMs are blocked. Above this voltage, write and store operations are available and therefore must be protected from unplanned instructions.
� Orderly Supply Transitions As a system powers up or down, the possibility of unintentional, internally generated control signals increases dramatically. The Xicor nonvolatile memory family has designed-in protection to eliminate self-generated write/store commands.
� Noise Filter An additional feature designed into Xicor's E2PROM family is a noise filter to prevent glitches on the WE line from initiating a write cycle. This feature filters pulses of less than 20ns duration insuring noise spikes are not misconstrued as write commands.
0027-1
8-33
� Write/Store Inhibit Control Pins Xicor nonvolatile memories require combinational control pin conditions in order to execute a write/store command. By disallowing any one of the required pin conditions, the user can prevent unplanned nonvolatile data changes so that data integrity is maintained.
The lntersil4 ICL 8211 programmable voltage reference is an inexpensive 8-pin mini DIP which will sense a selected voltage threshold and outputa logic "O" when the supply is below that threshold. Conversely, as the sensed voltage rises above the selected threshold, the 8211 outputs a logic "1" following its supply voltage level.
Write/Store Pin Conditions
AiiiAY~2
x
L H
ST6iiE
H
x
L
STORE CAPABILITY
STORE OPERATION DISABLED
ARRAY RECALL BLOCKS STORE INITIATION (SEE FOOTNOTE 2)
STORE OPERATION EXECUTEo3
Figure 1: X2200 NOVRAM Family
Solution 11-"Hold�High" Protection The second method of data protection during
power supply transitions is to keep the NOVRAM STORE pin (or the WE and/or CE pins in the E2PROM family) near the power supply voltage. By preventing the low condition of these pins which is necessary for a write or store operation, inadvertent stores will be eliminated.
Vee
CE
OE
WE
x
x
H
x
L
x
H
x
x
L
H
L
� Hard to control during power cycling.
Figure 2: E2PROM Family
WRITE CAPABILITY -~WRITE INHIBIT�
(OE) WRITE INHIBIT
(CEJ WRITE INHIBIT
WRITE OPERATION EXECUTEo3
External Hardware Implementations
Solution 1-"Holc:t-Low" Protection
The simplest solution is to pull the OE (or ARRAY RECALL) to a logic "O" whenever the supply voltage is below the (5.0-10%) system threshold.
91KO 30KO
Vee
R
8
NOVRAM
J:2P~OM
8211
OE (OR
3
4t---------~ARRAY
5
RECALL)
91KO 30KO
NOVRAM
R E2P~OM
CEOR ir-----a WE (OR
STORE)
CE or WE (OR STORE) Figure 4: "Hold-High" Protection
The graph in Figure 5 shows the performance of the lntersil ICL 8211. The top plot is . a sawtooth which is connected to "5V supply" as shown in the Solution I and Solution II schematic diagrams. The bottom plot is the output of the ICL 8211. Note that when the supply is above 4.50V, the ICL 8211 output tracks it at logic "1". When the supply sawtooth is below 1.56V, the ICL 8211 output tracks the power supply. However, since the Xicor memory family has internal protection inhibiting write/store operations when Vcc is below 3V, no inadvertent write/stores will occur in this range. In the critical range between 3V, where internal protection stops, and 4.SV, where normal operation begins, the ICL 8211 insures a OV output.
pp RESET OE
(OR ARRAY RECALL)
Figure 3: "Hold-Low" Protection
0027-2
8-34
Figure 5: lntersil /CL 8211 Programmable Voltage Reference/Supply and Output Waveforms
As an alternate approach to the 8211 , some
designers may prefer to incorporate the SGS L487.
This device is a 500 mA precision 5V voltage
regulator which includes an open collector power-on,
power-off reset output pin, which can protect the
nonvolatile memories just as the 8211 does. The
timing diagram in Figure 6 shows the voltage on this
reset output pin as the supply voltage transitions
through power-up and power-down.
K s.oov 4.16V----I-~--
,-------- 4.65V
vOUT
I
:
:::-=rr:L _- ' ______.? I
: '
V11ESET
l
o.oov--
I
~ ... 1--
Figure 6: SGS L487 Precision Voltage Regulator/Output and Reset Waveforms
New Protect Features
Serial Device Protection X2444 A Previous Recall latch and Write Enable latch
have been incorporated in the X2444 Serial NOVRAM.
Upon power-up, both latches will be in the reset state. Both latches must be set in order to enable either a write RAM operation or store to E2PROM operation.
A recall operation copies data from the E2PROM array into the RAM array. This operation places known data in all RAM locations and sets the previous recall latch. This prevents the user from inadvertently writing one word to RAM and performing a store operation with unknown data in all other locations.
The WREN instruction sets the Write Enable latch, enabling (if the Previous Recall latch is set) write and store operations. The WADS instruction resets the latch, disabling write and store operations.
Therefore, total data integrity can be maintained through the use of software commands. The device is inherently protected during power-up and, through proper software control, is protected during powerdown.
X2404 Serial E2 PROM Due to the nature of the software protocol involved
in writing to the X2404, inadvertent stores are highly unlikely. During power-up or power-down the possibility of the bus duplicating the start condition, slave address and transmitting data successfully is so remote as to be unmeasurable.
Software Write Protection Future E2PROM products will contain a register
which is accessible through a software sequence algorithm. This feature provides the user control in selecting the level of write protection required by their application. Refer to the X28256 data sheet for details.
Figure 7 indicates the write protection features incorporated in all Xicor products.
0027-3
8-35
GENERIC DEVICE TYPE
X2201A X2210 X2212 X2001 X2004 X2444 X2804A X2816A X2816B X2864A X2664B X2864H X28256 X28C256 X2404 X24C04 X24C16
8
0
F
T c
I
p
w 0
N
R
A
M
N
8
H
E
I
E y
R M
E
A
0
I
v 8
c
E
c
L
8
I
F
I
0
T
u
G p E
c
8
N
p
D
R
0
8
T
E
f. R N
0
8
I
0 E
N
E
L TR
T
R
E
Q
E cu
c
T
E
N 8
T EA
E cT
R 0
A L
I
N
0 c
E
R TE
L
L
N
E
xxx x
x xx x
xxx x
xxx x
x x x x
xxx xx x x x x
x x x x
xxx x x x x x
xxx x
xxx x
x x x x
x
x x x x
x
xxx x
x
xxx x
x
xxx x
x
Figure 7: Product Protection Matrix
Footnotes 1 GIGO is an acronym popular in the computer world for "Garbage In Garbage Out". 2 ARRAY RECALL blocks all control inputs but does not halt a store in process. 3 These are the only conditions allowing nonvolatile data change. 4 See lntersil ICL 8211, ICL 8212 Programmable voltage reference data sheet in lntersil Data. Book.
0027-4
8-36
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REPLACING DIP SWITCHES WITH NONVOLATILE TECHNOLOGY
By Rick Orlando
One of the most prevalent applications for small nonvolatile memories is that of replacing DIP switches. The advantages of the nonvolatile memories is clear. They take up less room, are easier to use, and lend themselves to automated board assembly. 256 bits of information, or the equivalent of 32, 8-bit DIP switches can be implemented in a single package.
Xicor's new X2444 Serial NOVRAM adds yet another feature-low cost. When coupled with the serial device's minimal interface requirements, the X2444 takes DIP switches head on, and is obviously the cost/performance leader. The purpose of this brief is to describe how easy it is to replace a DIP switch with an X2444 NOVRAM.
DIP Switch Interface
There are two common types of DIP switch interfaces.
1/0 Port
The first uses an 1/0 port with internal pullup resistors. Figure 1a shows a typical circuit that could be
used either with a single chip microcomputer or with
an 1/0 port on a microprocessor bus. In either case, the internal pullups present a logic "1" to the input as long as the DIP switch is open. To use an X2444 Serial NOVRAM in the DIP switch socket, one only needs to tie pins 14, 15, and 16 of the 16-pin socket
to Vee� One then plugs an X2444 part in the uppermost
half of the socket, and the circuit becomes that shown in Figure 1b. Vee. STORE, and RECALL are tied hard to 5 volts, so that all nonvolatile operations are controlled through software. The four interface lines from the X2444 are connected to the four least significant 1/0 lines of the port.
+5
1/0 PORT1
�c
DI RECALL
DD
Vss
a) Figure t. Microcomputer with Internal Pullups
8-37
b)
0006-1
No Internal Pullups
The second type of interface uses ports which do not have internal pullups. In this instance, the X2444 can be plugged into the top section of the pullup resistor socket, with a jumper from pin 13 of the 16-pin site to ground, for the V55 on the serial part.
Again, Vee. STORE, and RECALL are tied to +5V through the connections used for the resistor pack. The DIP switch socket simply remains empty. See Figure 2.
+S
+S
l
r
--.....,....-._-_
1/0 PORT1
�c
~~~~~~~-+-+--+-__..-----+--
-....__ -....__
1/0
PORT~
�c
Figure 2. Microcomputer without Internal Pullups
Both of these implementations free up four more 110 lines to be used elsewhere. They also require the same software to drive the X2444.
Assume that the processor is a 6801 with the X2444 replacing a DIP switch. The procedure "INIT" initializes the port (see Section 1, "X2444 Driver Program for 6801 ").
Serial output is accomplished by loading the data to be output into the A Accumulator. A loop routine then shifts a bit into the carry, sets the serial data out (Data in for X2444) to either a "1" or "O" depending upon the state of the carry and toggles the clock.
(See Section 2 Procedure "SHIFT1" of X2444 Driver Program for further details).
The serial input is performed by a loop which examines the state of the serial data in, (Data out for X2444) sets the carry accordingly, shifts the carry into the accumulator and toggles the clock. (See Section 3 Procedure "SHIFTIN" of X2444 Driver Program for further details).
The complete software is as follows, and it occupies about 100 bytes of code. As one can see, the X2444 is indeed a value replacement for DIP switches.
0006-2
8-38
...............�.........�..........................................���......
6801 X2"1"1"1 DRIVER
ASSUME THAT PORTl IS USED AS THE 2"1"1"1 INTERFACE
PORT1 'S REGISTERS ARE LOCATED AS FOLLOWS
DATA DIREC"fION
HEX 0000
f'ORT
HEX 0002
PORH
X2"1"1"1
I/O 0
SERIAL. CLOCK
SERIAL CLOCK
I/O 1 I/O 2
SERIAL OUT SERIAL. IN
SERIAL IN
SERIAL our
I/O 3
2"1"1"1 SELECT
CHIP SELECT
COMMANDS ARE PASSED TO THE XZ'l'l'I ROUTINE E:Y A PARAMETER IN THE
A ACCUMULATOR, WHILE THE ADDRESS IF NEEDED IS PASSED ON THE STACI<
SERIAL. DATA IN OR our USES THE TEMPORARY LOCATION TEMf'1,
WHICH IS A SIXTEEN E:IT WORSD, THE XZ't'l'I COMMANDS ARE ENCRYPTED AS
FOLLOWS.
COMMAND CODE
:rnsTRUCTION
OPCOOE
0
READ
1AAAA11X
1
WRITE
1AAAA011
RESET WRITE ENAE:L.E 11111000
STORE
11111001
SLEEP
11111010
:.1
SET WRITE ENAE:LE
11111100
......................................................................... l1
RECALL.
11111101
"1 "s ARE USED 'INSTEAD OF DON'T CARE TO DISTINGUISH E:ETWEEN DATA AND
NON DATA OPERATIONS,
DIRECTION!
,EQU
00 �
PDRTl
� EOU
02.
IEMf'l
.EClU
OBOH iRAM STORAGE FOR DATA
COUNT
,EQU
082H ;coUNTER VARIAE:LE
DATUM
,EQU
OB'tH lOATA STORAGE
ADDRESS
,EOIJ
086H ;ADDRESS STORAGE
;E.R.R.O.R.D.A.T.A.......�...,E.O..U............0.8.8.H.....;.E.R.R.O.R�.D.A.TA......................
;
PROCEDURE INIT
.------
;��������!~;;.::~;;~~:;.!~!!!:~;;:;.!~;.~;:::.!~!;:~:;;��.�������.�������������.)
I Section 1
-------
~
J:Nl:T
LOAA STAA
CLRA
�1E:H D:lRECTIONl
; E:=lOll.r I/O Or1 AND ~~ DlJTPUTS, 2 INPUT ; WRITE TO DATA OIRECHON REGISTER
;SET CE TO O<INACT:lVE>, DOUT ANO St( TU ll
STAA
PORTl
;AND STORE JN DATA PORT
RTS
;
;���������S�H�IF�T�E��R��R�O�U�T�T�l'I�F�-��S�H�I�F�T�l������������������������������������������������:
�..................�.......................................................... THIS ROUTINE TAKES THE DATA IN THE A ACCUMULATOR AND CLOCl(S IT HOST SIGNIFICANT BIT FIRST INTO THE XZ't't'I, THE FLOW IS SHIFT A BIT , TOGGLE
; THE SERIAL OUTPUT<6801 > ACCORDING TO STATEr ANO TOGGLE SERIAL. CLOCI( ;
Section 2
~ I I Section 3
SHl:FlCIU"l l...DAB
tOEI.
; LOAD nu:: Brr COUNT WITH 8
STAB
COUNT
;STORE IN CUIJNTE.R
SHIFTl ROLA
; SIUFT BIT INTO CARl':Y E:Il
LDAE:
t1'1H
;wE SET DATA OUT �To ZEROr WHILE bE"TTING CHI.P
BCC
TRANS
; ENABLE , SERIAL.. Cl..OCI( IS l...DW,
nF BIT 1:s A ZEROr THEN TRANSMIT
ORAB
�02H
;1F IT IS A ONE� THEN SET DATA UUI
TRANS
STAE:
PORT!
;SIORE THE DATA INTO THE PORT
ORAB
�Ol.H
; ANO SET THE CL.OCt( FOR A TRANSITTON
STAB
f'ORT1
; E:Y WRITING A 1 TO SERIAL. Cl..OCt(
ANOE:
t1AH
HffEP THE DATA VALIDr BUT SET SI< TO ZERO
STAB
f'ORTl
;AND STORE IN THE PORT
L.OAE:
t1'tH
; TOGGLE CLOCI( DOWN, SET DOUT TO 0 ' f:UT l(EEP
STAB
PORT1
; XZ't't't SELECTED
DEC E:NE
COUNT StllFTl
; OECREMENT THE BIT COUNTER
HF COUNT J:s NOT ZEROr TRANSMIT NEXl Brr
ROLA
HiNE MORE RfflATE TO PRESERVE :INSTRUCTION
;����������RT�S�>10k���������������iR�F�T�U��R�N��F�R�O�M���S�U�B�R�O��U�T�I�N�E������������������������ SHIFTIN ROUTINE
THIS SUBROUTINE SliIFTS IN 8 BITS OF DATA INTO THE A ACCUMULATOR FROM THE
X2"1"1"1, THE METHOD IS TD ENTER WITH TtlE Cl..OCI< LOWr TOGGLE THE SERIAL.. CLOCl(r
..�.......................................................................... EXAMINE THE INPUT OATAr AND SHIFT IT INTO THE A ACCUMULATOR, TH1:S IS DONE
B TIMES, THE ROUTINE IS EXITED WHH THE CHIP DESELECTED' AND THE BYTE
; READ FROM THE CHIP IN THE A ACCUMULATOR
; SHIFTIN LDAE:
�a.
;LOAD THE E:IT COUNT
BTAE:
COUNT
; AND STORE IT :rN THE COUNTER
; AT THIS POINT THE x:>.'t'l'I SHOULD E:E SELECTED
; THEREFORE, WE DO NOT NEED TO SELE.CT CHIP
NEXT
LDAE:
tO'I
;MASf( E::ll FOR I/O 2 OF PORT
FHTE:
PORTl
;cHECI( TO SEE :IF l:Nf'lll IS A ONE DR ZERO
CLC
; CL.EAR THE CARRY
BEQ
CL.OCI(
HF IT IS A ZEROr LEAVE CARRY AT 0
SEC
; OTHERWISE SET CARRY TO LOAD INTO A
CUlCH
LOAE:
t15H
;sENO A CLOCI( TO XZ'l't'lrE:IJT l(EEP CHIP SELECT HIGH
STAB
f'ORTl
; E:Y WRITING A 1 TO SERIAL CLOCH OUTPUT
SHIFT
LOAE:
t1'tH
. ; SET UP TO CLEAR CL.OCt( r E:UT HEEP X2'1"1'1 SELECTED
STAB
PORTl
;ANO STORE
ROLA
;ROTATE CARRY INTO LSE: OF ACCUMULATOR A
DEC
COUNT
; DECREMENT COUNTER
BNE
NEXT
; IF NOT ZERO r THEN WE ARE NOT DONE, GET NEXT
RTS
IAND RETURN FROM SUE:ROUTINE
0006-3
8-39
; ...........�...�......�......................................................
;
X2111 DRIVER ROUTINE
....................��....................................................... ; IT IS ASSUMED l"HAT THE INSTRUCTION IS PASSED IN THE A ACCUMULATOR. AN
; ADDRESS� IF NEEDED� IS PASSED ON THE STACt(<CURRENT Sf'-2>
; DATA TO BE READ OR WRITTEN WILL BE HELD IN TEl'lf'1 ;
, .
DRIVE
Cl'IPA
HFBH
; CHECK TO SEE IF IT IS READ OR WRITE
BGE
NONOATA
;IF NOT, THEN BRANCH AROUND
TSX
; TRANSFER STACt: TO INDEX REGISTER
DRAA
2,x
;THE ADDRESS SHOULD BE Sf'+2
JSR
SHIFTOUT
; OUTPUT THE INSTRUCTION
ANDA
H'tH
;CHECK TO SEE IF IT IS A READ OR WRITE
BNE
RD
;IF AC3l=1� IT IS A READ
WRT
LDAA
TEMf'l
HF IT IS A WRITE, GET THE Fl:RST BYTE
JSR
S H I F T OUT
; WRITE THE FIRST BYTE
LDAA
TEMf'1+1
; GET THE SECOND BYTE
JSR
S H I F T OUT
; WRITE THE SECOND BYTE
BRA
DONE
; WRITE INSTRUCTION COMPLETE
RD
JSR
SHIFTIN
; GET THE FIRST BYTE
STAA
TEMP1
; STORE IN TEMF'l
JSR
SHIFTIN
; GET THE SECOND BYTE
STAA
TEMP1+1
.STORE IN TEMf'1+1
BRA
DONE
; READ COMPLETE
NONDATA JSR
SHIFTOUT
; OUTPUT THE INSTRUCT:I:ON
DONE
Ct.RA
STAA
PORTl.
;DESELECT THE X2't11 E�Y MAt<ING CS 0
..�..��..�.��......�....�...�....�.�.........................�.��..........�.. ;����������R�T�S��������������������������;�R��E�T�U�R�N��F�R�O�M���S�U�B��R�O�U�T�I�N�E�'311:���������������> l'IAIN INSTRUCTl:ON ROUTINES���� COULD BE MACROS
;;����~�������������������������������������������������������������������������
READ ROIJHNE:
;�������������������������������*���������������������������������������������� ; ASSUl'IES THAT THE ADDRESS IS IN THE A ACCUMULATOR, DATA :rn LEFT IN X REGISTER
READ
ASLA
; SHIFT THE ADDRESS ~~ T:[MES TO L[NE TT
ASLA
; UP wrrn THE INSTRUCTION FTEL[)
ASLA
F'SHA
; PUSH ADDRESS ON THE S l"ACV
LDAA
�087H
; LOAD :CNSTRUC llON TNTO A ACCUMlJL.ATOf~
,JSR
DRIVE
; PERFORM INSTRUCTION
LOX
TEMP1
; GET THE RESULT IN HiE INDEX REGIS TEI~
f'ULA
; CLEAN UP THE STACf(
RTS
;AND RETURN
;��������������������������*���������������������������������������������������
WffflE ROIJITNE
; ASSUMES THAT THE ADDRESS IS IN THE A ACCUMULAHlR, DATA TO WRITE IS IN THE
; X REGISTER.
;��������������������������������������������������������������������*�������*� ; ALSO CALLS SET WRJ:TE: ENABLE LATCH ROUITNE<SWREN> lO ENABLE rHE WRJ:TE OPERATION
WRITE
ASLA
; bHIFT THE ADDFtEf:>S J ITMES
ASLA
ASLA
F'SHA
; PUSH AODRE!>S ONTO THE SI ACt(
,JSR
SWREN
; SET !HE WRITE ENABLE LA rcH
LDAA
�oK~H
; LOAD WRITE INSTRUC n:oN
STX
TEMPl
;STORE DATA IN TEMF'l
dSR
DRIVE
; PERFORM INSTRUC I :CON
PULA
;CLEAN UP STACI-:
R;�W�R�E�N�����RL�DT�AS�A��������O��F�B�H�����������;�L�O�A�D��H�i�F��IN�S�T�R�l�.I�C�T�T�O�N������������*�����������
,JSR
DRIVE
; AND EXECUTE
S;�TO��R�E�����RL�DT�AS�A��������O��F�9�H�����������H�.�O�A�D�*TH�E��:�I:�N�S�T�R�U�C�T�IO�N�������������������������
JSR
DRIVE
;f'ERFROM OPERATION
S;�LE��E�P�����RL.�TD�SA�A��������O��F�A�H�����������;;�LAO�N�AD�D�R�EH�TI�UE�R-N:J�:N�S�T�R�U�C�T�I�O�N�����������*������������
0006-4
8-40
r
TI I I
: ~iCO~
Jl l l
USING DATA POLLING IN AN INTERRUPT DRIVEN ENVIRONMENT
By Rick Orlando
The use of interrupt driven system design has become increasingly popular in many applications. Interrupt driven systems usually can. achieve higher performance and improved user friendliness. An interrupt driven system can perform a variety of tasks while waiting for a certain condition to occur, rather than constant\;: looping and waiting for the occurrence. Writing to E PROMs is no exception. Since the devices take a relatively long period to complete a Write Cycle, the system could perform a variety of tasks in the meantime.
DATA Polling was introduced on the X2864A to allow notification to the processor of Write Cycle completion. The manner in which it works is quite simple. The processor first writes a byte of data into the E2PROM. Any subsequent reads to any location of the chip will produce the complement of the data last written (hence, the name DATA Polling) until the E2PROM's internal Write Cycle is complete. At this point, reads to any location in the E2PROM will result in the valid data at that location. It can be seen that one can simply write a byte, and then perform frequent compares of the data in the location just written. The data will not be correct until the chip has completed its internal Write Cycle, and the Data circuitry is disabled.
In applications where the processor does not have anything to do during the Write Cycle, the software can simply perform compare loops until the Write Cycle is complete, and then write the next byte. In applications which are more processing time limited, a test loop can be placed in the main program loop, which will check the status of a previous Write Cycle on each pass through the main or outermost software loop. Almost all microprocessor applications software has such a top level loop. DATA Polling is obviously adequate in these environments.
The interrupt intensive applications may not have a main control loop nor can they usually afford the processing time for the processor to sit and loop until the Write Cycle is complete. In these applications, it would be ideal if the Write Cycle completion notification could be interrupt controlled. Although it is not obvious, DATA Polling can be used in these applications as well.
It should be noted that the whole reason for Write Cycle notification is because the typical write times for the E2PROMs are substantially shorter than the specified maximums. The magnitude of the delta between the typical and the maximum values determines the importance of the Write Cycle notification. One can easily see that if the maximum Write Cycle time and the typical were equal, one would only have to time a fixed interval for each Write Cycle, either from a software loop or a hardware timer. The hardware timer would generate an interrupt 10 msec after the Write Cycle was initiated, and the next byte could be written. Keep in mind that the discussion of write times for E2PROMs are in terms of msec rather than the �,sec in which the processor executes instructions. A few �,secs here or there are not important when compared to the Write Cycle time of about 10 msec.
DATA Polling does not require any additional hardware interface in order to be used. It is an exclusively software oriented method for determining Write Cycle completion. Even in an interrupt environment, no additional circuitry is required, since all of the interface to the chip occurs through the data and address bus.
0007-1
8-41
�In order to use DATA Polling in an interrupt driven
system, one only needs a time-based interrupt generator. This could be a programmable timer or even something as simple as an AC frequency interrupt. The key is that the processor does not check to see if the device has completed the Write Cycle until the interrupt occurs. The interrupt routine simply compares the data last written to the E2PROM to the data coming from the E2PROM. If the two match, the device can be written again. If not, the processor simply returns.from the interrupt routine to where it was and continues processing until the next interrupt. The interrupt source is maskable .which prevents the overhead of servicing the periodic interrupt during the intervals when a write has not been performed.
A programmable timer or counter is the most elegant solution. Figure 1 shows the hardware configuration of a typical system with the E2 PROM and the programmable timer on the bus. It should be noted that no unusual circuitry is needed from the E2PROM socket, which preserves its usefulness as a truly universal socket. The timer interrupt output drives one of the processor's interrupt lines. Many systems already have such a timer on the bus, and as a result require no additional hardware changes to implement this method.
6800
.----~INT MICROPROCESSOR 1 ' - r - - - - .
PROGRAMMABLE TIMER
,,,__ _ _ A
l"'"---.d
d
X2864A E2PROM
B ROM
The software implementation is rather simple. Figure 2 shows an example of how it might be done using a 6800 microprocessor and a simple timer. The timer control and data registers are mapped into the memory locations described in the initial header along with the temporary RAM variables, which are used� to store the last data written and its address.
The write routine (WEEPROM) initially checks to see if the E2PROM is ready to perform a write. If not, it simply exits with an error code to show that the write has not taken place. If the write is performed, the timer is loaded with the initial count for 4 msec, and the timer interrupt is enabled. The processor then goes off and performs its normal duties until the interrupt takes place. At that point, the interrupt routine (CKEEP) is entered. It first checks for the proper data that was written to see if the write is complete, using DATA Polling. If it is, the ready flag is set, and the routine is exited. If not, the counter is loaded with a smaller increment, such as 500 �.sec until the chip's Write Cycle is completed. This essentially allows the majority of the Write time to pass (4 msec) before the processor checks at the more frequent interval of every 500 �sec.
Five hundred �.sec has been chosen in this example for the interrupt granularity. The value used for a particular application should be chosen based upon the actual system requirements.
One can see that this implementation is rather easy and can be performed with hardware that already may exist in the system. By using the periodic interface approach, the system has the advantage of using an interrupt driven write algorithm, while maintaining only a software interface to the E2PROM. Most of the "bookkeeping" sections of the example code are the same as one would use with any method of write termination notification. The end result of using DATA Polling in an interrupt environment is optimization of the Write Cycle period as well as preservation of the pinout of the universal 28-pin socket for expansion through the 256K bit level for E2 PROMs.
RAM
Figure 1: Hardware Configuration of a Typical System with the E2PROM and the Programmable Timer on the Bus
0007-2
8-42
PAGE - 1 OATA_coo Fi le: lDATA_CDOE. TEXT
0000: Current memory 0000: 0000: 0000: 0000: 0000: 0000: 0000: 0100 0000: 0000: 0102 0000: 010:3 0000: 010"1 0000: 0106 0000: 0107 0000: 01013 0000: 0000: FtlOO: FOOO: FOOO:
FOOO: FOOO: FOOO: FOOO: FOOO:
r ooo:
FOOO: C6 00 Foo;�: Fl 0101
* � z7 Foo~_;;:
Hl07: Ct. 00 F009: F7 IJ106 FOOC: 20 FOOE: A/ 01) FOUi: F.:7 O:L03 F01:3: Ff� 010"1 F016: C6 th F01Bi F/ OlOu F01E: i C6 00 Fill.Di Fl OU!! Hl20: Ft. 0:108 ro;>.::i: F7 0102 Fll26: OF F027: 3';> Fll2B: FO;>.B: F028: F028i
~ 1.IA~H:
1� 11;:.n: n1;�0:
FO;~B:
F02f.l:
Fo2a: E:6 oun
F02Bl FE 0111'1 F02E l Al 00
available:
CODE FOR DATA POLLING IN INTERRUPT ENVIRONMENT� 6900 VEli."SION
;....................,.f'R..O.C..D.A.T.A�_C.O..Q.E..................................
SAMPLE CODE FOR USING DATA POL.L:X:NG IN INTERRUPT ENVIRONl'IENT
; THIS CODE SHOWS AN EXAMPLE OF HOW TO USE DATA POLL.ING IN A
i;�l�:N�T�E�R�R�U�P�T��D�R�I�V�EM�NE�M�WO�R�RY�IT�LE�O�MC�A�OO�TE�IO�N�S��������������������������������������
rIMER .ECllJ
0100H ;LOCATION OF llMER DATA REGISTER<COUNT DOWN VALUE>
; l 6 E:IT VALUE< 2 E:YTES >
CTIMER .EllU
01.02ti ; rrMER CONTROL. REGISTER
L.ASTA
.H~U
OlO~IH lRAM LOCATION FOR LAST WRITTEN DATA
lTMF'
.EUU
Olll'IH ; RAM LOCATION FOR LAST ADDRESS WRITTEN
ERROR .EDU
0106H ; Ef~ROR FL.AG FOR WRITE
READY .EDU
0107H ; MEMORY READY FOR NEXT WRITE FLAG
....�.......�.�.......................................�............. CONFIG .EllU
OlOBH ; TIMER CONFIGURATION E:Yff
.ORG OFOOOH ;
EEF'ROM WRITE ROUTINE
nus ROUTINE WRITES A E:YTE OF DATA PASSED IN THE A ACCUMULATOR INTO
rHF EEf'ROM Al LOCATION HlINTED TO BY THE VALUE IN THE X INDEX REGISTER,
rHE ROUTINE: THEN l:NITIALIZES THE DATA IN THE COUNTER TO "1096r SINCE THE TIMER
COUNTS AT A l. MHZ FRE:ClUENCY. nu:s MIU. TIME OUT THE INITIAL "' MSEC OF THE WRI
WR:ITE CYCLE. THE RD\Jr:tNE THEN ENABLES THE :rNTERRUPTS AN RETURNS CONTROL TO
;*************������������������������������������������������������� rHE CALU:NG ROUT:rNE
WEEPF<OM LDAB
4'00H
; COMPARE TO SEE IF THE MEMORY IS READY FOR WRITE
CMPB
REAOY ;cHECt( MEMORY LOCATION READY
BEU
WRIH: ; IF READY THEN WRITE
LDAB
tllOH
HlTHERWISE Sf! THE ERROR FLAG
~3TAB
l:.Rl~OR
; AND STORE IT l.N ERROR
WF<.UI
BRA STAA
EX:n
o.x
lAND EXIl lWRITE THE DATA IN A TO LOCATION X
~:i-~AA
LA!:>TA lSlURE DATA IN RAM AT LASTA
STX
IFMI"
i AND STORE l.JJC;\ llON IN EEPROM AT TEMP
LDAF:
t,10H
iLOAD THE FIRS.I [:YH: OF "1096 HEX INTO E: ACCUMULATOR
STAB
lIMER ; WRITE TO TIMEh: DATA REGISl ER
LDAE::
4'00H
; LOAD THE SECOND BYTE OF "1096 HEX
;:;TAB
rIMER<�l ; STORE IN THE I.. Sf: DF Tl:MER REGISTER
LOAB b l AB CL!
CDNf'lG CTlMEf<
; GE I THE TIMER INITIALIZATION CODE
; fflORE rr IN THE n:MER CONTROL. REGISTER ; CLEAR INTERRUf� r MAst; TO L.ET TIMER INTERRUPT
;m::TURN FROM SIJE:ROUrINE
; ****lk****�***************************-W*****************�����������Z�'C� CHECt( EEl"ROM ROUTINE HHS f~DIJl lNE CHECl<B TO SEE IF THE EE.F'ROM :rn DONE. IT IS ENTERREI>
; EVER~ llME !HA 1 THF I H l FRRUPT IS \;ENH~H' ED. FROM !HE 'IME.R. . n cu~��ARES
FIE l>i'd(, A�1 1.UC..Ai.I:CIN iLMf�� JN 1Hf. u:.J�1.1..1M W.1 IH lH[ DATA THAT IS ST ED IN
.�.�.�.......��.....�..����...............�.........��..�....����..��. ; LR:3fo') LOCATION :rn h'!\M. IF THE COMPr.f: rsnN FAILS' THEN THE EEPRDM s NOT
; DONF YET , AON THF TIMER IS RESET TU TIME 112 MSECCOR 512 USEC>, THE
; ROIJHNE IS THEN EX:l:TEO. ;
Cf(EEF'
L.DAA LOX CMPA
LASTA !EMF' 0, X
;GET THE LAST DATA WRITTEN ; GET THE ADDRESS FOR THE BYTE IN EEPROM ; COMPARE TO SEE IF THE WRITE IS COMPLETE
PAGE - 2 DATA��COD File: :DATA_CODE.TEXT
F030: 26 **
F03Z: 86 00 F0:3"ti l'.:7 (i1 fl/
F0'.37: 20 **
F0:39: 8t> O~'. F03E:: !':7 OlOO F03E: 86 00 FO"tO: E:7 0101 FO"t3: 3B FO"t"t: FO"t"t:
CODE FOR DATA POLLING IN INTERRUPT ENVIRONMENT, 6800 VERSION
BNE LDAA
REINIT HF NOT EQUAL REINITIALIZE THE TIHER
too
; SET THE READY FL.AG
STAA
READY ; AND STORE IT IN READY
BRA
RET
;AND RETURN FROM SUE:ROUTINE
RETNrr U>AA
tOZH
; LOAD THE FIRST E:YTE FOR COUNTER
STAA
TIMER ;WRITE TO TIMER DATA REGISTER
LC>AA
�OOH
; LOAD THE: SECOND BYTE
STAA
TIMER+1 ;WRITE TO LSE: OF TIMER DATA REGISTER
RET
RTI
; RETURN FROH INTERRUPT
;*********************************************************************
.END
SYME:OL.TABL.E DUMP
CODE FOR DATA POLLl:NG :rN INTERRUPT ENVIRONMENT� <!.800 VERSION
AE: -� Absoh1te RF - Ref PE: -� F'L�b1 ic
LB - Label OF - Def F'V -� Private
UD - Undefined F'R - Proc CS -- Cons ts
MC - Hacro FC - Fl�nc RS - Residents
Cf{EEP LAST A WEE PROM
LE: F028: AE: 0103: LE: FOOO:
CONFIG READY WRITE
AE: 0108: AE: 01071 LE: FOOE:
CTIMER REINIT
AE: 010 2 : DATA_COD PR ----- : ERROR
LE: F039: RET
LE: FO"t3: TEMF'
AE: 0106: EXIT AE: 0104: TIMER
LE: F027 AB 0100
Figure 2: Software Implementation for 6800 Microprocessor and a Simple Timer
8-43
0007-3
NOTES
8-44
I I lT
: lieu~
l l l J
E2PROM PROVIDES THE SOLUTION TO FIELD ALTERABLE SOFTWARE
By Rick Orlando
The advent of the 5-volt E2PROM has brought about many changes in the manner in which the designer views his software. Such devices allow for in-field reprogrammability, which greatly reduces the cost and impact of software changes or upgrades. The 5 volt E2PROM allows the designer the capability to completely upgrade or change his software from a remote location rather than through the replacement of the system ROMs or EPROMs, a costly and inconvenient method at best. Complete infield programmability requires that the entire program store of the system be implemented in E2PROM. An alternative is a "hybrid" system.
A "hybrid" approach refers to a design which utilizes both EPROMs or ROMs in conjunction with E2PROMs to yield a design which features the best of both approaches: the low cost of a full ROM implementation, while maintaining the flexibility of a full E2PROM approach.
The secret to this approach is to analyze the software requirements of the end system from two distinct levels. That of the machine code routines which perform the simple tasks, and that of the higher level routines which call the lower level routines to perform an algorithm. The order in which the low level routines are called is determined by the higher level routines or program flow. This "TopDown" programming approach is more efficient and structured, and is the basis for many high level languages. The fact that it can be used in machine language coding should not come as a surprise to designers, since the decomposition of a complex task into many simple tasks is quickly learned in programming, even if it is not called "structured programming" per se. The decomposition of the end task can sometimes lead to many different levels of program structure, but for the simplicity of discussion, this brief will limit itself to the most simple approach, that of two level program structure.
The lower level code consists of the machine
dependent routines such as that required to fetch a character from an 1/0 link. The buffering of multiple characters from this link might also be a low level routine. The interpretation of the buffered character string will be implemented in the higher level code, since it simply calls the lower level routines and determines the action to take based upon their results.
A basic example is that of the executing of multiple character command entered by the operator from a keyboard. The lowest level routine simply gets a character from the keyboard if a key is depressed. The next level of the software "buffers" the input to make the system more "user-friendly". This routine looks at the input string, eliminates misplaced blanks or other characters, and forms a character string which the high level program can understand. As a result, the "parsing" task is broken into three distinct levels.
The first involves the inputting of a single character from the keyboard into a character buffer. The second level continually calls the first routine until an end-ofinput character is detected (such as a Carriage Return). The top most level of the code takes the parsed command and determines if it is a valid command by searching a table of valid commands. If the command is valid, the address of the routine to execute is fetched out of the table, and the processor performs a jump. Most of the input processing is handled at the lowest level, thereby reducing the overhead in the outermost routine.
As more and more of the processing tasks are pushed "down" into low level routines, the main procedure in the high-level segment becomes very short and simple. In fact, it can be reduced to a simple list of jump-to-subroutine instructions. This structured approach not only eases the software development task, but it also minimizes the debugging time required for the software since it is built upon other routines which have already been debugged.
0008-1
8-45
If one completely decomposes the task to be
performed by a particular segment of the systems main program, it becomes a list of procedure calls to
lower level segments. This method lends itself very well to a system which can use E2PROM. Since the "outermost" program store is quite compact, it can be implemented in E2PROM while the majority of the
machine code in the lower levels can be implemented
in ROM or EPROM. Changes to the software then
become as simple as changing the jump location in the E2PROM, and the order of execution of the lower level routines can be altered in such a manner.
Using this method, one can also reserve a section of the E2PROM for low-level "patch" alterations to
the software. If a low level routine is found to be in error or needs updating, the new version of the
machine code is loaded into the reserved section of the E2PROM. The jump instructions in the high level code in the E2PROM are simply changed to "jumps" to the new routine now residing in the E2PROM as
opposed to the old routine in the ROM or EPROM. Figure 1 shows a typical memory map where the E2PROM is used to store the high-level routines
which perform a variety of jump to subroutines to control the program flow. The low level machine
language routines are stored in the EPROM as shown. Figure 2 shows how a patch is made to
ROM
q"GET CHARACTER" ROUTINE
"PARSE" ROUTINE
i------
141 COMMAND #1 ROUTINE
COMMAND #2 ROUTINE
LOW LEVEL ROUTINES
"COMMAND" ROUTINE
VALID CHARACTER UST
VALID COMMAND UST
HIGH-LEVEL ROUTINES
"PATCH" AREA
SAMPLE ENTRY
COMMAND-"GO"
kJ "G" "O" "CR" ADDRESS COMMAND#1
replace the old routine in EPROM called "PARSE" with a new version loaded into the E2PROM. The jump-to-subroutine addresses in the E2PROM are updated to point to the new routine in E2PROM. The actual update or "patch" can be performed remotely, thereby eliminating the need for in field EPROM replacements for both the remedying of software bugs as well as the upgrading of systems in the field to take advantage of new features or capabilities.
Since both the valid character and the valid command tables reside in the E2PROM, new entries can be made to allow for additional command selection. New command character strings are simply added to the valid command list. The low-level code for the new command can either be loaded into the E2PROM patch area or utilize routines which already exist in the ROM or EPROM. The appropriate address is appended to the new command string.
If an error is discovered in an existing command, the valid command list is updated to point to the new command routine which is loaded into the patch area of the E2PROM. Figure 3 depicts the memory map after such a change has been made.
ROM
E2PROM
"GET CHARACTER" ROUTINE (OLD) PARSE ROUTINE (OLD)
COMMAND #1 (OLD)
COMMAND#2
LOW LEVEL ROUTINES
l4i rl
COMMAND ROUTINE
SAMPLE ENTRY
VALID CHARACTER UST
VALID COMMAND UST
COMMAND-"GO"
~�"O" 'CR"
ADDRESS
HIGH-LEVEL ROUTINE
COMMAND #1
~
NEW"PARSE"
NEW COMMAND #1
PATCH AREA
Figure 3: Memory Map After New Command Patch
Figure 1: Memory Map Original Configuration
ROM
,.... t - - "GET CHARACTER" ROUTINE (OLD) PARSE ROUTINE (OLD) COMMAND #1 ROUTINEj4,
COMMAND #2 ROUTINE
LOW LEVEL ROUTINES
....:
"COMMAND" ROUTINE
VALID CHARACTER UST
VALID COMMAND UST
HIGH-LEVEL ROUTINES
NEW"PARSE" ROUTINE
PATCH AREA
SAMPLE ENTRY
vCOMMAND-"GO" "G" "0" "CR" ADDRESS COMMAND#1
Figure 2: Memory Map After Routine Patch
Ultimate flexibility can be attained through a complete E2PROM design. It can also be shown that a minimal amount of E2PROM can add great flexibility to the system not only in terms of software alteration, but also in its intrinsic ability to store user alterable parameters such as configuration data. The actual ratio of EPROM to E2PROM must be determined based upon the systems' requirements. The advantage of the "hybrid" approach is that it requires that only the "top level" portion of the code be resident in E2PROM, and as such is usually limited to a series
of procedure calls, which are very code efficient.
In the cases where the software is to be updated remotely, perhaps through the use of a modem, certain factors must be considered. The key point is that while the processor is executing programs in the E2PROM, it is unadvisable to write into that particular device. The reason for this is that while the device is performing the write cycle, any reads, such an
opcode fetch, will result in a high impedance bus.
8-46
0008-2
The important issue is that the download of the new code must not reside in the E2PROM to be modified.
This can be accomplished in two different ways.
The first implements the download program segment in the low level ROM or EPROM. In this case, the actual instructions will be present from the memory throughout the download sequence. Figure 4 shows such an approach where the download software is
kept in the ROM. This routine writes the new bytes into the E2PROM and then enters a software loop to time out the E2PROM write cycle.
ROM
"DOWNLOAD" ROUTINE "TIMING" ROUTINE
LOW LEVEL ROUTINES
PROCEDURE TO BE MODIFIED
Figure 4: Memory Map-Download and Timing Resident in ROM
In some applications, this method may not be adequate, especially if the actual download routine is to be modified. In these cases, this program segment must be stored in the E2PROM, and hence, cannot be directly executed from the E2PROM to be modified. In this situation, a possible approach is to copy the download program segment from the E2PROM into RAM. The program then jumps to the RAM location, where the copy of the old code resides. This RAM routine loads the new program segment into the proper E2PROM locations, timing out the necessary E2PROM write cycle. Once the download is complete, the program executing out of the RAM then jumps back to the main program, and the download routine section of the E2PROM will contain the new code. Figure 5 shows the various stages of this operation in terms of the contents of the various memories and the program execution flow.
RAM
SYSTEM STACK AND DATA STORAGE
"00-LOAO" ROUTINE
"TIMING" ROUTINE
PROCEDURE TO BE MODIFIED
Figure Sa: Memory Map Prior to Download
RAM
SYSTEM STACK AND DATA STORAGE
"DO-LOAD" ROUTINE
"TIMING" ROUTINE
"DO-LOAD" ROUTINE
"TIMING" ROUTINE
PROCEDURE TO BE MODIFIED
Figure 5b: Memory Map Download Routine Transferred to RAM
RAM
SYSTEM STACK AND DATA STORAGE
E2PROM
"DO~OAD" ROUTINE
"TIMING" ROUTINE
NEW VERSION OF PROCEDURE
Figure 5c: Memory Map RAM Erased After Transfer Complete
As one can see, the "hybrid" approach to software design, utilizing a combination of both E2PR0Ms and ROMs or EPROMs, can result in a system which exhibits the advantages of the field alterability of E2PROMs. As the cost of the development and maintenance of the system software becomes more dominant in the overall cost of the system, such methods as those presented in this brief will become more commonplace in system design.
0008-3
8-47
NOTES
8-48
T TTT
: liCB~
l l l l
"tov"-WHAT IS IT?
By Richard Palm
E2PROMs, RAMs and EPROMs all being memory devices have similar specifications. However, one of the specifications unique to E2PROMs is tov (Data Valid Time).
The E2PROM requires a relatively lengthy period of time to tunnel charge onto or off of the floating gate to complete the write cycle. This time is specified as twc- In order to more closely emulate RAM write timing, Xicor introduced "self timed" write operations. Xicor E2PROMs latch the address on the falling edge of WE or CE, whichever occurs last, and latch data on the rising edge of WE or CE, whichever occurs first. The falling edge of the write operation not only latches the address of the byte (or page) to be written but also starts a number of internal timers that control the programming cycle.
In page mode, subsequent WE/CE falling edges will restart the timers. But it is these timers that require specifying t0 v.
In most microprocessor based systems, tov can be ignored because twp will be less than tov- However, in applications employing slower microprocessors and microcontrollers twp might be quite long. The actual internal programming cycle could begin before either CE or WE returned high, thereby missing valid data even though tos was met.
Once the internal timers initiate the programming cycle, the I/Os will be disabled. Therefore, valid data must be present on the bus before the I/Os are disabled. As an example, refer to Figure 1 illustrating the sequence of events.
DATA
Figure 1: External/Internal Timing
I
VALID DATA
0060-1
8-49
tov is the maximum time to elapse from the falling edge of WE or CE (whichever occurs first) before valid data have to be presented to the E2PROM.
How does this impact your design? The following timing diagrams cover the three possibilities. Notice that in all the examples toH must still be met.
-------twp~ t o y - - - - - -
DATA tos-----toH
Example 1: If twp is equal to or greater than twp min but less than tov, then tos and toH must be met.
0060-2
twp> toy
twp < toy + tos
WE/CE DATA
t
i E.~ toH::F
Example 2: If twp is greater than tov but less than tov plus tos then tos and toH must be met.
0060-.3
WE/CE
- - - - - t w p > toy+ tos - - - - - . i
DATA ----toy---�1
Example 3: If twp is greater than tov plus tos then tov and toH must be met.
0060-4
In summary, the data must be valid on the bus for the worst case timing parameters; whether that is tov or tos and always valid for toH�
Glossary
tov
Data Valid Time
twc
Write Cycle Time
tos
Data Setup
twp
WE Pulse Width
toH
Data Hold
8-50
iCOP
Understand your application in choosing NOVRAM, EEPROM
Richard Orlando, Xicor Inc., Milpitas, CA
As appeared in EON Magazine May 12, 1983
8-51
Understand your application in choosing NOVRAM, EEPROM
Examining how NOVRAMs and EEPROMs serve various applications illustrates the memory devices' capabilities and simplifies device selection.
Richard Orlando, Xicor Inc
If your system design calls for electrically erasable nonvolatile data storage, you can simplify the selection of semiconductor memory for that task by choosing from among four basic types-NOVRAM, EEPROM, EAROM and battery-backed CMOS RAM. Assuming that you've examined the system-level tradeoffs among these memory types (EDN, April 14, pg 135) and have narrowed your choice to the first two, use the information presented here to understand the detailed tradeoffs and design considerations underlying NOVRAM and EEPROM use. In some application classes, either memory type functions adequately; in others, you have a clearcut choice. And in still others, consider taking advantage of both-an approach that often results in cost reductions and enhanced features.
NOVRAMs use multiple technologies
First, however, understand how each memory type works. Nonvolatile static RAM (NOVRAM) combines two memory technologies on one monolithic chip. In Fig 1, the NOVRAM shown contains lk bits of static RAM and lk bits of electrically erasable PROM (EEPROM). The device comprises cells that in turn each contain one cell of each memory type, rather than housing two separate memory arrays (see box, "Anatomy of a NOVRAM cell").
In this NOVRAM, data gets read and written exactly as in a standard static RAM. In addition, the Store signal transfers each RAM cell's data into a shadowing EEPROM cell; EEPROM-stored data gets reloaded into the RAM via the Recall signal. Note that the EEPROM-cell portion is accessible only through the RAM portion.
One of this device type's most powerful features is its ability to transfer the entire RAM contents into
nonvolatile storage in one operation, initiated by bringing the TTL-compatible Store. LOW. The operation takes less than 10 msec, and once data is stored in this manner, only another store operation can alter it-even if the chip loses power.
Generating Store in the event of a power failure therefore saves the RAM contents, subject only to power remaining on the chip for the next 10 msec. RAM data can also be changed without disturbing the shadowing EEPROM, allowing the system to manipulate two separate groups of data. EEPROMs offer greater density, fewer features
EEPROM, your other major memory choice, resembles UV-erasable EPROM. Unlike EPROM, however, it can be written electrically in circuit; it needs no prior erasure by exposure to ultraviolet radiation.
First-generation EEPROMs are merely electrically
ARRAY RECALL
Fig 1-Nonvolatile static RAM (NOVRAM) is organized so that each static-RAM bit is overlaid on a bit of nonvolatile electrically erasable PROM (EEPROM).
8-52
Careful analysis simplifies the EEPROM vs NOVRAM choice
alterable ROMs (EAROMs). They're reprogrammable only after an entire memory array (or at least one page) is electrically erased. Similarly, second-generation devices require erasure of individual bytes before programming. Third-generation EEPROMs, however, automatically and internally erase a to-be-written byte as part of the write cycle; they also contain much of the required voltage-generating and pulse-shaping functions on chip.
Two examples of third-generation EEPROMs currently in production are the Intel 2817 and the Seeq 5213. The 2817 latches the data to be written and eliminates the need for prewrite erasure. However, it requires an external high-voltage supply as well as a timing capacitor for deriving internal timing signals.
TABLE 1-EEPROM/NOVRAM COMPARISONS
Density (bits) Price (1k level) Cost/bit
NOVRAM (X2212)
1024 $9.00 $00088
EEPROM (X2816A)
16,384 $23.00 $0.0014
The 5213 generates the high voltage on chip but requires external latches that hold the data and address valid during erase and write operations.
Fourth-generation EEPROMs are characterized by
Anatomy of a NOVRAM cell
NOVRAM-cell operation depends on a phenomenon termed FowlerNord hei m tunneling. In the NOVRAM, a layer of oxide isolates a gate from an underlying section of polysilicon. Applying a large positive voltage to this floating gate while holding the underlying polysilicon near ground programs the gate.
Specifically, electrons attracted to the floating gate's significantly higher potential tunnel across the separating oxide. As a result, the floating gate acquires a net negative charge from the tunneled electrons.
The cell is erased in a similar manner: The floating gate is held at a low potential while the potential of the top polysilicon layer is raised; the electrons then tunnel across the oxide from the floating gate to the neighboring polysilicon sandwich.
The EEPROM technology employed in Xicor's NOVRAM uses a 3-layer polysilicon sandwich that, when coupled with a 6-transistor static-RAM cell, results in the NOVRAM circuit shown in Fig A. The state of the static-RAM cell determines whether the EEPROM
cell is programmed or erased during a store cycle.
Capacitance ratios are the key to the data transfer from RAM to EEPROM. If node N1 is LOW, 01 is turned off, allowing the junction between capacitors C3 and C4 to
float. Because the combined capacitance of C3 and C4 is larger than Cp, the floating gate follows the Store-node voltage. When the voltage on the floating gate is sufficiently high, electrons tunnel from POLY1 to POLY2, and the
Fig A-A NOVRAM cell consists of two sections: a 6-transistor RAM and a shadowing 2-transistor EEPROM.
8-53
on-chip generation of all high-voltage and wave-shaping functions in addition to their use of on-chip latches and self-timing features. Their byte-write requirements are identical to those of static RAM except that the EEPROM write cycle, once initiated by normal staticRAM timings, takes as long as 10 msec. Once a byte-write operation begins, the EEPROM is self supporting, freeing the processor and all external circuitry for other tasks. Read timing to the EEPROM is identical to that of a standard EPROM, RAM or ROM.
An important feature of a fourth-generation EEPROM� is its compatibility with currently used RAM, EPROM and ROM. An EPROM- or ROM-based system needs only an additional Write Enable line to
each socket to provide retrofitting for EEPROM. This control line allows the changing of data tables and program store without removing the component from the system, as required with EPROMs.
Choosing between NOVRAM and EEPROMs
Many application requirements can be satisfied by either of the two memory types. However, note that although NOVRAM is the most versatile in terms of features and capabilities, the price you pay for its greater intelligence is increased cell size.
Specifically, a fourth-generation EEPROM's cell is small and simple, allowing much higher density storage than in a NOVRAM. The EEPROM is also more efficient as memory-array area increases, thanks to the
gate becomes negatively charged.
If node N, is HIGH, 01 turns on,
grounding the junction between C3 and C4. C3, larger than CE, holds the floating gate near ground when the Store node gets pulled HIGH. This action creates a sufficiently large field between POLY2 and POLY3 to tunnel electrons away from the floating gate, leaving it with a positive charge.
The recall operation also depends on capacitance ratios. C2 is larger than C,. When the cell receives the external Recall command, the internal power supply (VccA) first goes LOW to equalize the voltages on N, and N2. When V ccA is allowed to rise, the node with the lighter capacitive load rises more rapidly. The flip flop's gain causes the lightly loaded node to latch HIGH and the opposite side to latch LOW. If the floating gate has a positive charge, C2 is connected to N2 through 0 8, and N2 latches LOW. If the floating gate has a negative charge, 0 8 gets turned off and N, experiences the heavier loading.
A major task in the development of the NOVRAM was to reduce the
ON-CHIP
GEN~~,.,TOR
y~-- o,, o,,
~' r NONOVERLAPPING
---�.��.r ,.wJ,.U,cu, rl C2
CLOCK
GENERATOR
,_~2_- - - - - -
32-STAGE CHARGE PUMP
Fig B-A 32-stage charge pump internally generates a NOVRAM's high Store voltage,
sv. allowing the device's NOVRAM and EEPROM sections to operate from
amplitude and simplify the waveform of external voltages needed tor programming or erasure. Earlier devices required carefully shaped pulses with amplitudes exceeding 20V.
The first step in the cell design was to reduce the internal voltage level presented to the cell to initiate electron tunneling. The voltage magnitude required for programming a floating gate is related to the intensity of the electric field generated at the oxide-polysilicon interface by that voltage.
Electric-field strength at the oxide-polysilicon interface can be
increased by using an extremely
thin oxide, on the order of 1ooA. A
second technique uses textured polysilicon to locally enhance the field at the surface and achieve Fowler-Nordheim tunneling. It achieves better data retention.
Once the internal voltage-level requirement was reduced, a key achievement in device design was the on-chip generation of the highvoltage pulses needed to program or erase an individual cell. A Store-voltage generator {Fig B) provides the solution; it uses a 32 - stage capacitor/transistor charge pump.
8-54
Each NOVRAM cell combines RAM and EEPROM
TABLE 2-EEPROMINOVRAM DATA-CAPTURE SPEEDS
Byte-Write Time Store Time Total Time
NOVRAM
(X2212)
256 x 1 11sec 10 msec
10.26 msec
EEPROM
(X2816A)
256 x 10 msec 0
2.56 sec
decrease in the relative proportion of support-circuitry area required. Therefore, EEPROMs are more likely to be the device of choice if your application needs large amounts of memory.
The larger cell size and more extensive on-chip support that gives NOVRAM its added capabilities also results in a higher cost per bit, which might not be justified in applications that don't require all of a NOVRAM's features. Consider, for example, the cost-per-bit comparison between the X2212 256x4-bit NOVRAM and the X2816A 2kx8-bit EEPROM (Table 1): NOVRAM cost per bit is more than six times greater than that of EEPROM.
However, cost-per-bit ratios can be deceiving for systems requiring a minimum amount of nonvolatile memory. Lower density nonvolatile memories often are more cost effective in a NOVRAM configuration. The smallest NOVRAM currently available, the 64x4 X2210, is also the least expensive 5V device.
Another selection factor to consider is the required write time. An EEPROM requires a relatively long write time (10 msec/byte max), while NOVRAM write
time is that of a typical static RAM. Therefore, NOVRAMs are more suited for applications requiring frequent memory-data changes, while EEPROMs most suit applications calling for infrequent memory writes.
A NOVRAM is also better suited to data-capture applications. Table 2 compares two 256 x 4-bit NOVRAMs organized in a byte-wide configuration with a 2kx8 EEPROM in terms of the time needed to store 256 bytes of information. These times assume a 1-�sec/byte max processor write-cycle time. You can see that the NOVRAM's single-store operation makes it much faster. A NOVRAM system can update and store 10,000 bytes of data in the time needed to store two bytes of EEPROM information.
Another important NOVRAM feature is the device's ability to initiate and complete a nonvolatile store of data under external-signal control. This feature can be a key decision criterion in real-time applications such as power-fail re-entrant systems.
Both types serve power-fail-tolerant controllers
As noted, however, many applications can profitably use either device type. One common application in this class centers on retaining important system information in the event of a power loss. In most systems, power failures require reinitialization of the entire system, necessitating the temporary loss of system operation. In real-time control applications, this loss of control can cause expensive and sometimes dangerous failures of the process or equipment being controlled.
Such an application's main requirement is therefore some type of nonvolatile storage upon power failure. A prime consideration in this type of environment is the storage of a fixed amount of data upon receipt of an
POWER FAIL 6809 �P
ADDRESS DECODE
ADDRESS DATA
SYSTEM ROM
POWER-ON RESET
POf!TA
sroRe
.256x4 NO\IRAM D7.4
RECALL
Fig 2-ln this controller, a NOVRAM retains the �P state in the event of a power failure.
8-55
GENERAL� PURPOSE
1/0
5rORE
256X4 NOVRAM D3.0
RECAiI
;****t:*t:***t:****t:*******~t:*t::t:*t:*t:*******t:***t:********~~***************~ ; flt�~ E::<AMPLE OF THE POl.1.IEF.:-DOl1.lt�4 At~D POl.�.IEP-Ot�~ CODE FOR THE 6::::o�~::t USI t�Ki
; THE t�)1.,.1F.'.AM FOR PF.:OCESSOP STATUS STOF.:ACiE.
;***********~::~f<****************t::t::t::t::t:***t:**~****~*~t:****t:*~***~t:*~*****
; LOCATIC~ DEFINITIONS
t�lUF.:AML.O
.EDU
OOOOH
t�l'..IF:f-iMHI
.EQU
WJRAMLO + 256.
; THE t�IOUF'.fli"1 IS LOCATEC:i fH THE E:OTTOM OF THE t:.:::~J'3 ME:�lOF:'/ t'IAF'
[�I FT'/
.EOU
rf.IF.'.AMHI nE::::T E:','TE FOP PO!..IEF<'. FAIL. cotmITIOt�~
CIL.U:OTf::'
::::TACK
� E!)U .EDU
t�41..'F:AMHI-6 ;:3TACf:: POitHEP tmt41.)0LAT ILE LOCATiot�~ t~!.JPRMHI-7 ;F'F.'.OCE:::::::.op :::.TACK E:EGit�4t�4ll"4Cl LOCATIOt�4
TEMPl
TEl"1F'2 TEMF'3
F'CIF'.TA
� EDU � EOU � EC!U .E@J
NUF'.AMH I -1 .: I MPOPTRt-H F'FOCES:::: PAF.'.At�1ETER::-. rlUF.:At'IHI --2
t4UPF11"1HI-3
;L~:ATIC~ C1; DATA REGISTER FOR PORT
� OF'.iJ C:F:::OOH + ; :�t: :�f: :t: :t::t: :t: :t:: t: :t: :t: :�t: :-f: :t: :t: :f: :t: :-t: :t: :t: :t: :t: :f<:t: :t: :t::t: :t: :t:: t::t: :t: :t: :i�: :-t<:t: :t::t: :t::t: >t:: f: :t: :t: :i�::t: :t::�t: :t: :t::t: :t::�t::t: :t::t::t::t: :t::t::t::t:*:t::t: :t::t::t::t:
PC~ER FAILL~E ROUTINE
; :t::t::t::t::t::t::t::t::t::t::t::t::t::t::t::t::+::f.:t::t::�t::+::t::t::+::t::t::t::f::�t::t::t::t::t::t::t::t::t::t::t::t::�f::t::t::-t::t::t::t::t::i�::t::+::t::t::t::t::+::t::�l<:t::f::t::�t::t::t::t::t::t::t:
PFAIL
STS
OLDSlK ;WRITE CVRRENT STACK FVINTER INTO NC~RAM
flT -r HIS PO I HT.. THE F'Ol.JEF: FAIL. It-HEF.'.PUPT HAS PUSHED ALL OF THE
CUF:F'.EJH ' 'AL..UES UF THE Pr'CtCE'.:'.SOF'. ~'.EG I ::::TEF::~:. otno THE STACI<. THE
�~:.TiiCI:" i:-:�onnEF'. r-�onn~~: �ro THE:::::::: UALUES.
LDA
~0A5H ;L~~D ACCL~ULATOR WITH POWEP FAIL FLAG
�:::TA
DIF.'.T'/ ;STORE FL.AG rn tmUPAM
U1A
#00.
=1.�JF'.ITHlCi A 0 TO THE PORT GEHEr.;~ATES
STA
POPTA
;A STORE SIG~~L TO THE NC~RAl"1
LOOP
BRA
LOOP
;SIT F~D WAIT L~ITIL POWER DISAPPEARS
+ .~ . r.. +: :+: :+: .+: :1 'f. :+: :t:: f: :t: :t: .+:. t: :t::t: :+: :-f: :t: :+: :f:: t: :t: ,,_, :t: :-f: :+: :+: :t: :t::t: :t: :+: :+: :t: :t: :+: .i�: :t: =�t==+= :t::t: :+::+::+: :t: :r-::+::+<:t::+<:t::t::t::t> =+< :t::t::t: :t<:t::t::t::t::t::+::+:
F~~ER-C~ RESET ROLITINE
J~ :t: :t: :t::t:: t: :t: :t: :t:: f: :t: :t: :t: :+: :t: :t::�f< :t: :t: :t: :t::t: :t: :i.::t:: f: :f::t::t: :t: :t::+: ;.f::t::t::t::t::t: :t: :t: :t::t::t::t: :t::t::t::t> :+< :t: ;.f::�f<:t::t;:t::t::t::t::t::t::f::t::t::t< :t::t::t::t::t::+<
F'E'.3ET
LDFI
#OFFH ;SET ALI_ OUTF'UTS TO A II 1"
STA
PORTA ;WRITE TO FURT TO KEEP STORE HIGH
LDA
DIRTY ;LOAD FLAG TO SEE IF PC~ER FAILED
Cl1PFi
#Off::�)H ;IT WILL BE A 0A5H IF IT DID
E:l�JE LDR
HllT #OOH
;IF NOT DO NORMAL INITIALIZATION
;CLEAR THE PC~ER FAILURE FLAG
:::TR
DIPT'/ ; Itl THE t�mUF:Al�l
L[�R STR
#OOH
~JRTH
.;Atl[:o 1~Il.JE Fl STOPE SIGt�lAL
;TU STOR~ THE NEW FLAG
LDf'.I
#OFFH ; F:E:::ET F-'OFT
LDS
OL[ 1:C::Tf::: ;LOi::1D OLD ::::TACY UALUES
F:TI
::F:ETURt�4 FRC!l"I F'Ol.1IER FAIL ItHEF~RUPT
I~�IIT ~tl0Rf'1AL ItlITIALIZ:iTIC!t~ CODE
� OF'Cl OFFCH � 1.1.ICIF.'.[:� pn:1 I L.
� 1.t.ICF.D PE::OET
. Et~[:,
;PDl.�IEF: FAIL.URE HHEF.'.F'UPT l)ECTOR
;PC~ER-ON PESET I~TERRUPT VECTOR
Fig 3-A power-failure-tolerant controller's 6809-�P assembly-language routines handle both failure store and recovery. NOVRAM handles the stack and other temporary storage.
8-56
NOVRAM doubles as bootstrap and global memory
external Power Fail signal. You can use an EEPROM for this purpose if the processor has sufficient time to recognize the power failure and respond by writing the data into memory. Otherwise, a NOVRAM is the device of choice because it captures data in one nonvolatile store operation.
Fig 2 shows a simple controller that uses a NOVRAM to retain the state of a �P in the event of a power failure. The Power Fail signal generates a �P interrupt, and the NOVRAM stores the contents of all RAM including the �P stack.
Upon interrupt acknowledgement, the �P registers are pushed onto the stack as program control branches to the interrupt routine (Fig 3). The routine writes the current stack pointer and a test byte to the NOVRAM, signifying that a power failure has occurred, and then generates a Store signal. The power supply is designed to ensure that the Vc level remains above 4.5V for 10 msec after it generates the Power Fail signal.
Once power is restored, the Power-On Reset signal generates a Recall signal to the NOVRAM. The power-on routine in the �P checks the state of the test byte to see if a process was interrupted by a power failure. If so, the stack pointer gets loaded with the address of the saved processor state, a return from interrupt is executed, and the process resumes.
NOVRAM stores terminal configurations
An application in which NOVRAM is the device of choice lies in the storage of terminal-configuration information, consisting of such parameters as baud rate, data format and parity method. The conventional
approach to this task (Fig 4) stores data in DIP switches on a pc board somewhere in the terminal; the user must have a terminal manual handy for decoding switch settings to change any of the preset features.
One alternative uses menu-driven configuration modes to set the terminal and a NOVRAM to store the terminal-configuration parameters. The user can easily change the configuration information for specific tasks and retain this data until the terminal loses power.
Upon power-up, a set of predefined default parameters stored in the NOVRAM's EE PROM section goes to RAM, and the terminal is configured. The NOVRAM also allows the user to change default parameters for subsequent sessions by transferring the modified RAM data to EEPROM-in either a general or privileged user environment. The NOVRAM's ability to manipulate two sets of data proves important here because the terminal software operates on the data in the NOVRAM's RAM section, regardless of whether the terminal is in the default configuration or a userentered one.
In Fig 4's conventional approach, an 8-section DIP switch holds the configuration information. If a switch position is open, the pull-up resistor causes a ONE to appear at the buffer input; a closed switch denotes a ZERO. Decoding the buffer's address and reading the data provides the switch information. If the system needs more than eight bits, the design requires additional switches, resistors, buffers and logic.
If a block of memory addresses is reserved for configuration information, the granularity of the address decoding increases with the number of DIP
�P RESET
DATA ADDRESS
SYSTEM MEMORY
CRT REFRESH RAM AND CONTROL
5V
OCTAL ~-STATE BUFFER
POWER-ON RESET
ADD RES~ DECODE
KEYBOARD AND 1/0
Fig 4-A conventional terminal configuration uses an 8-section DIP switch to program the terminal's operating parameters.
8-57
In-system data modifications make EEPROMs more versatile than EPROMs
switches required. And you can change the default data only by altering individual switch positions.
The NOVRAM implementation of this system (Fig 5) permits the storage of lk bits of configuration information in one 18-pin X2212. If you reserve an 8k memory-address block for configuration storage, the NOVRAM requires only a single chip-select decode. The only restriction in this arrangement is that four parameter bits get read simultaneously, rather than eight. Note that storing the same amount of information using the conventional approach calls for 128 DIP switches and octal buffers, 1024 resistors and sufficient address decoding to provide 128 separate locations within the 8k field-an address granularity of 64.
A terminal user employs the keyboard to enter operational parameters. into the NOVRAM. The user enters a configuration mode when the terminal is in the off-line or local mode. A menu display shows the current terminal configuration; the user moves the cursor and/or strikes a control key to alter the current values. Once the configuration is established, the user exits the configuration mode, and the terminal operates according to the new parameters. The user can also change the default parameters by entering a control signal that places the new configuration mode in the NOVRAM's EEPROM sedion.
In this application, very few terminals would ever require the NOVRAM's full storage capacity for
configuration information. You could therefore employ the unused portion to store other operational and maintenance parameters.
NOVRAM loader provides reusable memory
A system that employs a bootstrap loader during initialization is another prime NOVRAM application candidate. Examples of such applications include single-chip �Cs operating in external-memory modes and full-blown systems requiring the maximum allowable memory space. A common approach to this requirement stores the bootstrap program in ROM or EPROM. However, the program occupies memory space that might be used for other purposes during system operation. Because most initialization routines use a relatively small amount of memory space, this approach can be particularly wasteful in space-limited systems.
As an alternative, you can preprogram the bootstrap into the EEPROM section of a NOVRAM. Upon reset, the system generates a Recall signal to the NOVRAM, loading the bootstrap into RAM. The bootstrap program executes, and the NOVRAM RAM section then becomes free for other uses. This design feature even allows bootstrap-program alteration via external control for servicing or software updates.
Fig 6 shows a simple disk-oriented system that uses NOVRAM as a bootstrap memory. After booting, the NOVRAM becomes a global RAM. The device-and
SYSTEM MEMORY
1-A_D.D..R. ,_E_s_s+---+-l'----4 ~~C~RRiT~~
uP CONTROL
6502 "p
DATA ADDRESS
DISK SUBSYSTEM
AND DMA
SYSTEM RAM
Fig ~Replacing a DIP switch with a NOVRAM results in greater versatility for programming terminal operating parameters.
Fig &-This disk-oriented system uses two NOVRAMs as bootstrap memory. Once loading is complete, the NOVRAM functions as global RAM.
8-58
;*********~***************~***************~****~~****~*~**~***********~ THIS PPOGPAM SEGMEtH DEl'10t�6TPATES THE OPEPATION OF A S'�,'STEt�l l.1.IHICH
USE::: A E:OOTSTF:1~1F' PPOGRAM PF'.ELOADE[:� I tffO THE t�lOJ..JF:AM ��� 5 EEPROM. UPOt~
POlilEF'--Ot�J RESET .. THI:::: E:OOT IS F:ECALLE(:� nno THE EEPF:ot�1�.. s r;::AM. THE
F:OOTSTF:'AF' PORGf;:Af'l Cot�JF I GUPES THE :::.'/STEM.� AND THEtJ USES THE t�Kfl,.tfr:AM ... S
PAM ~1::: F'.EGULAP F.'.liM. THE t�JOUF.'.AM IS LOCATED AT THE BOTTOM OF THE
,:;,5(12�.. s MEMOF''.1 MAP :::;;o THAT THE HIGHE:::T L.OCATIOtJS CA~j CONTAW THE
PROCESSOR~s INTERRUPT UECTORS. ACTUAL LORDI~~ o~ THE C~ERATING
�:::,'/STEM rnTO MAW ME:J-101?'/ I:::. ACCOl'lF'LISHED E:',' ::::i Dt�lfi COtJTPOLLEF:'..� l.1IHICH
LOADS THE PROGRAM FRC~ THE DI~�.
;*****~~*****~*************~~~*~*~*~***~******~*~***~**~*~**~**********
[11ADATA
.EQU
0C000H ;OMA DATA REGISTER
L:.1'1flCTF:L
� EOU
OC001H ;DMf1 C:Ct-ffF'.OL. REGI:::::TEF:~
F'POCiRRM
� EOU
OCCOOH
;STFIRT
OF
PROGF'.Al�1
l�lEt�iOF.'.
11
1
� OPG
OFFOOH
; TH IS F'ROCiRAM SECT J C1~-~ IS u:1ADED HiTD THE EEF'F'.Ot�l SEC TI Ot�J OF THE
; t�Krt..IF'.AM. At~D IS PECALLH� UF'OtJ F'Ol1.IEf;::--UF�.
BOOT
Uo:;
#0FF":--I ;LOAD THE ;::: rnDE>=: F~EGISTEF.: l�IITH FF
1. �-�
; TF'.fltt:.FEI? TO STACK F'OHffEF.'. AT 1211 FF
COl��W I(jl_lf;::
TH Is CODE :~::Eel I Ut�J CUt�JF I CiURE:::: THE DMA cotn F.'.OLLEF.: �'
AND SETS THE INITIAL. LOAD LOCATION AT 0200H, SO
THAT F'F'.OGRAM DATFI 1.�.II L.L NOT OUEF'l.1.IP ITE THE ST AU<.
SF.~Ef::
THI:; CODE SECT I otJ TELLS THE DMA cm�HF.'OLLEF.: l.1.IHAT
DISK SECTirnJ IT SH~JLD GET THE PROGR~1 FF~~- AS
l.1.IELL. RS HOl�.1 MUCH DATA TO L.CAD.
CiO
LDA
#01.
01 IN THE D~~ CC~TROL REGISTER
WILL INDICBTE DISK DATA LORDI~~
DMFtDFtTfi STORE IN THE DMA CC~TROL PEGISTER
#OA5H TEST
1..ll?ITE TO TEST E:'/TE TO '.;IGtHF',' E:OOT
IF 1.olE ::::EE 1'.:f #OA'.:oH.� i.1JE ARE rn BOOT
LOOP
LOOF'
LOOP UtH IL C�i'lA Cot-HPOLLEF'. I tHEF'.PUPTS
=:t: :t: :t::t::t: :t: :t: :t: :-~: :+� :t::-f:: f::i�: :+: :+: :t: :t: :t: :t: :+: :t::t: :t: :t::t: :+: �t: :t: :t: :t::+: :t: :+:: f: +:t< :t< :t: :t: :t::-f::t: :t::t::t::t::-j< :t: :�f<:f::t::t: :t::t: :t: :t::t::t: :t::t::t: :t::t::t::+: :+:
tii'1I FF<:c:;�i Dl�lR HHEF'.l?UF'T 11.IILL_ '.'ECTOR HEPE. THIS F'.OUTHJE CHECf=:S THE
:�;TATU�::-: Ft<'Ot�I THE L:.ISf<� ::::uE:S','STEt-1 FltJD DMA CDt-HF.:OLLEP TO HJSUPE THAT
THE REQUESTED DATA HAS BEEN .LOADED. rn~:E A SUD:ESSFUL BOOT HAS
T11KF.Jl PL.ACE. THE :;'/STEM CAt�J CHAt�JCiE THE t�IMI UECTOF.: :::rncE THE t�mui;:AM
t�-IC:ll.1.I FUtJCTIOt�J::: A'.3 A F.:ECiULFW F:At-1. + + ;: +: :t: :t: :t::f::f: :j�: :i�: :t: :t: :t:: t: :t: :t: :t: :t: :+: :+:: f: :t: :t: :+: :j: :t: :+. :t::t: :t: :t::t: :+: :t: :t: :+: :t: :+: :t: .+: :t< :t: .+: :t: :t::t::�t::t::-t::t::t: :t::t: :�t< :-~: :t: :t: :t::+: :~:t< :t: :t::t::t::t::t:
H 1n::~'F:UF'T
LDA
[ 11�11=1cTF:L CHEU< TO SEE IF THE DES I RED PF:OGPAM
HliS E:EHJ :::::ucCESSFULL'/ LOfiDE[1 � IF so .. ALL. 1_,J I U_ BE ZEROES E><CEF'T D~:1 li.IH I CH
WILL BE SET TO SIGNIFY THAT AN
CMF'
#01
I~TERRUPT WAS GIUEN.
APE 11.IE LOADED-::�
E:tJE
E:OOT
1F ~-mT . 1.olE . HAUE At�J EF:F:OF: . RE -BOOT.
~DA
TEST
GET TEST ENTE TO SEE IF IN A E:OCTT.
CMF'
#DASH
IF SO. TEST 8\'TE l\IILL BE A5 HE>::.
E:ED
PF.'.Ot~F.:Af'l
At�JD JUMP TO PF'.OGRflM BEG Itlt-H t�JG.
EVi;::oR
;ctTHEF.'.l.1.11 SE 1.dE HFtUE 1'.:ft~ EF:F.:OR.
TEST
.E~TE
00.
; A ZERO IS ::~ORED IN TEST INITIALLY �
� OF:Ci
OFFFAH
t�lMI F.:E::::ET
� lolOVi� � l.dCIF.'.[.1
HHEF.:F.:UF'T; HMI 1.�.1I LL GO T Ct S\'STEf'l START ROUT I ME �
E:Ctl'.11
; POl1IE~:--rn~ PE'.::ET 1.i.IILL CAUSE AUTO BOOT.
Fig 7-A 6502-�.P assembly-language boot routine is located temporarily in NOVRAM, which forms the highest 256 bytes of memory in this system.
8-59
Use EEPROM if data changes are byte size and infrequent
hence the bootstrap routine-is in the highest memory segment so it can hold all the interrupt vectors. �Ps such as the 6502 and 6800 use these locations for reset and interrupt pointers.
In the bootstrap program (Fig 7), the reset vector for the 6502 �P points to the boot routine. Fig 6's two NOVRAMs reside in the highest 256 bytes of the address map. Upon power-up, the NOVRAM's EEPROM section gets loaded into the device's RAM section. The �P then initializes the stack pointer, and the DMA controller begins a data transfer from the disk. A test byte gets set to show that a boot process is under way.
Once the DMA transfer begins, the �P loops until an interrupt signifies that the operation is complete. The �,P vectors to the interrupt-handling routine, which determines if a valid DMA has occurred. If an error has occurred, the program causes a jump to location Program, where the first byte of the loaded program resides. The NOVRAM RAM is then free for general use. Note that you must take care not to accidentally overwrite the interrupt and reset vectors, located in the highest memory locations.
EEPROM stores controller parameters
Turn now to some applications in which an EEPROM is the device of choice. One such task is the storage of coefficients in PID (proportional integral-differential) controllers.
Modern control applications such as the PID algorithm are characterized by two basic qualities. First, they are computationally intense. Second, their ability to precisely control a set condition is based on their knowledge of the effects of their outputs. This knowledge results from deriving the various controller coefficients via calculations: Each controller output must be calculated with reference to the previously defined term.
If a PID system loses power, it must resynthesize all data before it approaches the level of performance exhibited before the power loss. The data tables for each control task are fairly large and require a substantial amount of memory. Therefore, a controller might use EEPROM for algorithm-coefficient storage.
Note also that most PID-controller deviations result from the sensitivity of the system's sensors as well as the response time and accuracy of the control outputs. These variables might change in a particular unit but are usually the same when power returns to the controller; they need only be updated occasionally as the system runs. An EEPROM's slow write time and fast read time make it ideally suited for this infrequentwrite application.
Finally, note that parameters stored in EEPROM are
Fig 8-A self-learning video game uses EEPROM to change difficulty levels after play is completed.
available to the system whenever it's runningwhether programmed into the system during initialization or resulting from previous system operation. An EEPROM implementation of such a system thus results in shorter system-interrupt recovery time as well as self-recalibration upon component replacement.
Self-learning video games use EEPROMs Another potential EEPROM application centers on
the storage of self-teaching or self-modifying code, through which a process or algorithm can tailor itself based on the results of previous executions. Such applications are characterized by updates to program storage, which usually occur relatively infrequently. This high read-to-write ratio of memory access, as well as the densities required in the program store. generally dictate an EEPROM implementation.
An example of this application category is a selflearning video game (Fig 8). Such a game's success depends largely on its ability to keep a player interested by continually increasing the level of challenge after repeated plays.
At the end of a certain period (Fig 9), the game analyzes the scores and modifies its program (including timing loops and difficulty factors) to present a more complex play to the next group of players. The learning algorithm also makes the game easier to play under
8-60
certain conditions, preventing unwarranted increases make the game progressively more difficult to play.
in difficulty.
These routines get bypassed in the initial program
The initial game code includes several routines that execution by always-executable branch instructions. At
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Fig 9-Written in 6809-�.P assembly language, this self-learning video-game program changes branch instructions based on previously obtained scores.
8-61
EEPROM and NOVRAM could team up in some cases
the end of each play, the system determines from the score whether to make the algorithm more difficult. If so, it eliminates some of the branches around difficult parts of the game software. A simple table stores all of these branches. Other features, including speed parameters and energy levels, can also be stored to make the game more difficult as scores improve. Storing them in EEPROM provides the additional advantage of easy updates and changes in the basic table.
EEPROM and NOVRAM team up
As a final example, consider how you might combine EEPROM and NOVRAM in an automobile navigational system that could direct a driver to a location within a specific city or area. Proponents of this approach envision beacons located throughout an area, notifying each in-car computer of the car's current location. Provided with this information, a local electronic map and the desired destination, the computer would direct the driver along the most efficient route.
Data-storage requirements would be extensive, implying the use of EEPROM. After all, the system must not only be programmed with a map of the area roads but must also be able to select between many possible alternatives based upon continuously changing factors such as time of day and known construction areas. Using EE PROM would allow the car's driver to load the navigational computer upon entering a location such as a filling station.
A NOVRAM would also prove critical to this application. It would contain rapidly changing current information, which would get transferred to the NOVRAM's EEPROM section upon reaching a destination. The approach allows power removal from the system while the car is parked, eliminating battery
drain. Restarting the vehicle would transfer the
current data from the NOVRAM's EEPROM section
back to its RAM section.
Fig 10 shows how the hardware could be implement-
ed. Map information, stored in EEPROM, gets changed
as necessary via the map-download controller, a serial
interface over which the data is transmitted. The
transmission rate is low because the map data is
written into EEPROM, which specs a slow write cycle.
The system has two main interfaces-to the driver
and to the vehicle. The former consists of a keyboard
for input and a CRT for display of the map and other
information. The latter receives data such as mileage
and speed so that the system can monitor the driver's
progress along a given route.
EDN
Author's biography
Richard Orlando is product marketing manager at Xicor (Milpitas, CA), where his duties include product development. He is a member of the IEEE Computer Society, the ACM, Tau Beta Pi and Eta Kappa Nu. Rick holds a BS degree in computer-systems engineering from the University of Massachusetts at Amherst. His interests include research in the areas of distributed processing, reconfigurable processor architectures and �P applications.
Article Interest Quotient (Circle One) High 476 Medium 477 Low 478
SYSTEM ROM
EE PROM MAP
MEMORY
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KEYBOARD CRT INDICATORS
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t--D-AT+A -----1----------+----------+-t
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SERIAL INPUT
POWER-ON RESET
RECALL NOVRAM CURRENT-LOCATION STORAGE -
SYSTEM RAM
LOCATION DETECTION RECEIVER
AUTO INTERFACE
ODOMETER SPEEDOMETER
Fig 10--A hypothetical automobile navigational system uses EEPROM to store extensive map information and NO�VRAM to handle rapidly changing current-location information.
8-62
ElECTROnlH In DESllin
Non-volatile memories keep appliances out of the dark
Richard Orlando, Xicor Inc., Milpitas, CA
Appliance design has undergone a revolution in recent years. The advent of the low-cost, single-chip microcomputer has opened many applications for these small computers in the appliance market. Initial applications were based upon new types of appliances where digital control was a necessity. Today one sees even the venerable "white goods" using single-chip microcomputers to add features and capabilities to the end products. With this migration to digital control, a need for non-volatile memory has developed, and many new non-volatile memory devices have been made available to the designer.
Appliance control applications have gone through an orderly evolution. The design methods of the past used electromechanical devices, such as switches, relays, mechanical timers and, of course, wafer switches. The requirements of older appliances could be easily satisfied by these devices. Washing machines, for example, using multiplane wafer switches driven by a simple timer could initiate, time and terminate the different cycles of the laundry washing process. And the electronic range allowed simple electromechanical timing of a cooking cycle.
Since the appliance industry has
been subject to the whims and attitudes of the consumer, the desi.red capabilities of appliances have grown as a function of added features. A simple example is the evolution of the home stove controller: first, accurate control over cooking temperature, then the ability to turn off the oven after a programmed time, and, finally, the complete programmable oven �that not only turns itself off after a programmed time has elapsed, but also initiates the cooking cycle at a certain time of day.
The increased capabilities of the appliances coupled with the availability of low-cost, single-chip micro-
8-63
ELHTRODIC5 ID DESIGD
computers has led to the final step in the evolution, that of full digital control. The use of the microcomputer as a control mechanism allows the designer increased flexibility, reliability and precision in the control process, not easily attainable with the older design methods. Decreased development costs are also possible since a flexible digital controller can be used in a variety of different products, or models of the same product.
Microcomputer designs were not free of their own unique problems, however. The microcomputer interface required to perform the actual control functions was somewhat complex. New issues had to be addressed in terms of product reliability, since the semiconductor devices introduced different failure modes than those exhibited by electromechanical devices. The microcomputer also had a major disadvantage over prior design techniques due to its inherent volatile nature: when the power was removed from the appliance, the microcomputer not only stopped functioning, it lost any data it had maintained based upon the current state of the system.
One advantage that the older electromechanical timers possessed
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was that if the power went off to the appliance, the control system would maintain the state it was in when the power was interrupted. When the power was restored to the appliance, it would continue from where it left off. One can easily appreciate the irritation of a homemaker who, having left a roast in the oven, returns from errands to find that it had not resumed cooking after a blackout. Emergence of non-volatility
With many appliance designs, there is a definite need to prevent such untoward situations. Some type of non-volatility is a necessity in appliance design. Since the cost of the appliance is a great concern, this non-volatility must be cost-effective. One of the earlier approaches was that of battery backup on the microcomputer itself, or on a separate CMOS memory in the system. The disadvantages of this approach are based simply on the limitations of batteries and the cost of implementation. Unfortunately, there were not many alternatives until now.
The past five years have seen a remarkable evolution in the emergence of semiconductor non-volatile memories. Unlike the battery backup of the data in either on-board or external RAM, these devices were able to retain data without the external power, in a manner similar to that of an EPROM. The main difference between these devices and the EPROM was their ability to be
"rewritter in-circuit, as opposed to being removed from the circuit, erased, and then "reprogrammed" before they were put back into the circuit.
Unfortunately, these early devices were expensive and difficult to use. They required multiple "programming" voltages, extensive support circuitry, and were quite unreliable. These devices, for the most part, were organized for microprocessor "bus" applications, and as such required too many Ilo lines for efficient interfacing to single-chip microcomputers, where Ilo lines are a precious commodity.
The development of Sv floatinggate, NMOS non-volatile memories eliminated many of the disadvantages of semiconductor non-volatile devices. These devices not only decreased the support circuitry required for their use, but increased the reliability of the devices. Unfortunately, these devices were also designed for "bus" applications and were relatively expensive due to
their large densities (>lK bits). A need was recognized in the appliance and other industries for an inexpensive and reliable non-volatile memory designed exclusively for interfacing to single-chip microcomputers.
The Xicor X2444 answers this need. The device is a low-cost 16 x 16 non-volatile static RAM (NOVRAM for short) which features serial interface designed for interfacing to a single-chip microcomputer with a minimum requirement for both Ila
RECALL STORE Vee Vss
SERIAL CLOCK SERIAL DATA IN SERIAL DATA OUT RECALL STORE +5V GROUND
8-64
ELEnRODIES ID DESlliR
lines and software. Housed in an eight-pin mini-DIP, the X2444 provides inexpensive non-volatile data storage for both operational and configuration parameters. Its low cost (less than $4.00 in unit quantities) makes it the least expensive non-volatile storage on the market, even rivalling the DIP switch in unit cost, while providing the equivalent of 32 DIP switches in terms of data capacity. The NOVRAM concept
The NOVRAM idea is not new. Xicor invented this type of memory more than three years ago. The concept is quite simple. Figure 1 shows a block diagram of the X2444. It consists of a 256-bit (16 x 16) static RAM with a 256-bit 5v E2PROM array overlaid bit for bit in a "shadow" type manner. Two signals, STORE and RECALL, control the transfer of data between the E2PROM array and the static RAM. The STORE function replicates the data which is currently in the RAM into the non-volatile E2PROM array. In a similar manner, the RECALL function transfers the non-volatile data in the E2PROM array into the RAM. One can see that by simply performing a STORE during power failure, the data is then retained in the non-volatile E2PROM , and can be restored to the RAM using the RECALL once power is returned to the system.
The X2444's serial interface method is ideal for microcomputer applications. Figure 2 shows the pinout and signal designation for the X2444. The four-line serial interface consists of a Chip Select (cs), a Serial Clock (sc), a Data In (DI) line, and a Data Out (Do) line. The Data In and Data Out timings are designed to allow the implementation of a single Serial Data line by typing both Data In and Data Out to a single Ilo line from the microcomputer, reducing the Ilo lines to three. All data transfer to and from the X2444 are performed over this serial interface by either synchronous 8-bit instructions or 16-bit data operations. The X2444 has two external pins, STORE and RECALL, for performing the non-volatile
operations via hardware control in the event of power failure. The X2444 also includes distinct STORE and RECALL instructions over the serial interface to allow only software control over the non-volatile operations.
The serial interface is accomplished using discrete "bit-banging" from the single-chip micro. An instruction is performed by loading an accumulator with the proper bit pattern, and shifting it out through an Ilo line while toggling the serial clock low and then high again between each bit.
The software for this interface is simple, and an example of a 6801 implementation is shown in Figure 3. The software assumes that the X2444 is connected to bits 0, 1, 2 and 3 of the 6801 Ilo Port 1. The interconnect between the 6801 and the X2444 is shown in Figure 4. The three main parts of the software segment are three subroutines, SHIFTIN' SHIFTOUT and DRIVE. The SHIFTOUT routine takes the eight bits of data in the A accumulator, and shifts it out through Bit 1 of Port 1. Between each data bit output the clock is toggled. This routine is used for either instruction or data output to the X2444.
The SHIFTIN subroutine gives the X2444 eight clock cycles, and shifts the data from the X2444 into the A accumulator. This routine is used only in the READ instruction. The DRIVE subroutine actually provides the driver to interpret the desired operation and issue the proper sequence of commands to the X2444. It should be noted that this sample interface uses the softwarecontrolled STORE and RECALL commands and leaves the X2444 STORE and RECALL inputs tied to Vee. E.g. . . . microwave oven controller
One of the newest appliances in the consumer environment is the microwave oven. This also proves to be an ideal example for the application of a non-volatile memory.
The microwave oven started with a control mechanism which was no
more than the simple electromechanical timer borrowed from electric ranges. Since the microwave oven cooks in times which are orders-of-magnitude faster than a conventional stove, it became apparent that an accurate and precise control mechanism was needed. The microwave was one of the first appliances to embrace full digital control using a single-chip microcomputer.
Figure 5 shows a typical microwave oven control system based upon the 6801 microcomputer. The user interface includes a keyboard, alarm and display, while the oven interface includes the magnetron control, door interlock, and an optional temperature probe. Nonvolatile memory has been added to the system design through the use of an X2444. The interface method to the 6801 and the driving software are similar to that above. The key difference to note is the addition of an external signal to drive the STORE input. This allows the controller to automatically store the data in the RAM into the E2PROM upon PowerFailure. The circuitry in the power supply senses a loss of power by monitoring either the ac or unregulated de levels. Once a power failure has been detected, the power supply circuitry pulls the STORE input low. The power supply circuitry need only ensure that Vcc is held valid to the X2444 for 10 msec, and all of the data in the RAM will be stored into the E2PROM array. Upon Power-onReset, the 6801 issues a RECALL command to the X2444, and all of the data is restored.
The remainder of the microwave control circuitry is fairly standard. A
4 x 4 keyboard provides an input
mechanism for the user, while the status indicators and display provide visual feedback. A two-line magnetron control allows the use of variable power levels in the cooking process. Timing is performed using the 6801's internal 16-bit timer which is driven off the 60-Hz reference from the power supply. Standard features include a safety door
8-65
ELEETROnlH IR DESlliO
interlock and alarm. Optional features are provisions for a temperature probe for magnetron control or temperature-based cooking algorithms. The a-d converter used for temperature sensing has a serial interface similar to that of the X2444, and is placed on the same serial bus. Distinct chip selects enable the X2444 or the a-d converter to be accessed. Many such devices are currently on the market including the new TLC540 from Texas Instruments.
The X2444's non-volatile memory serves many functions in this application. Frequently used recipes or cooking sequences can be stored so that the microwave will sequence through a complex cooking algorithm automatically. The X2444's ability to store the data currently in the RAM into the E2PROM is very useful here. As the cooking process takes
place, the 6801 keeps a copy of the preset time and power setting in the X2444's RAM. As cooking time elapses, a location in the X2444 is updated to show the elapsed time. In the event of a power failure, the current values of these variables are automatically stored into the E2PROM section of the X2444. Once power is restored to the microwave, the data in the E2PROM is loaded into the RAM section of the X2444, and cooking continues from where it was interrupted. Intelligence can be added to the control algorithm to compensate for the continued cooking (due to retained heat) that occurs after the power outage.
The X2444's unique NOVRAM architecture makes such an application feasible. Since current E2PROM technology has limitations on the number of times that the non-volatile data
can be changed, one would not want to change the contents of the E2PROM each time the timer was incremented. If one were to use a typical E2PROM with a write limitation of 10,000 writes, the device would be worn out in a relatively short period of time at a write rate of one per second. Instead, the X2444 allows the system to update the E2PROM section
of the chip only in the event of a power failure while using the unlimited RAM write capability of the X2444 every time the counter value changes.
The X2444's can also be used for a variety of other purposes in microwave design. As was mentioned earlier, one can save development time and money if a universal controller is designed. Many different models could use the same controller simply by adding circuitry
8-66
0000: c.~0:.~0J
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1983 Minimal Driver for X2111� 6801 Version 3,0
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2141 SELECT
CHIP SELECT
COMMANDS ARE PASSED TO THE X2141 ROUTINE E:Y A PARAMETER IN THE
FOLLOWS, COMMAND CODE 0
INSTRUCTION READ
OPCODE 1AAAA11X
1004: 1F 1005: 97 02 100;'1�1 ~:
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:to.a1
1008:
1008:
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CODE AS OF AUGUST 22� 1983 Minima�! Driver for X2141� 6801 Version 3.0
101E:: 07 02 1010: C6 14 U1FI
ui11 102�u
1026:
1027: 39 1020: 102EH
10Z8t
102.SI
STAB LDAE:
F'ORT1 t11H
;AND STORE IN THE PORT HOGGLE CLOCf{ DOWN, SET DOLJT TO 0 ' E:UT f{EEf'
;RETURN FROM SLJE:ROIJTINE
'*****************************************************************************
8-67
ELEn1on11s 1n DESllin
external to the 6801 microcomputer. Configuration information can be stored in the X2444 at time of manufacture which the 6801 can then determine upon Power-on-Reset to control the features and functions of its particular microwave. Additional X2444s can be added on the serial bus as user or model options. These optional X2444s require only an additional chip select, and can be used for such features as increased recipe storage or operational modes. The X2444's non-volatile memory also can be used for calibrating the temperature probe and storing the response time of the magnetron to allow quick calibrations or more complex and precise temperaturecontrol algorithms.
General applications There are many other areas in the
appliance field which are natural applications for the X2444. Since most electronic appliance controllers utilize the single-chip microcomputer, the X2444's serial bus is the ideal solution their non-volatile storage needs.
"User-programmable" parameters such as favorite stations, cooking algorithms or preset time-of-day events all make the appliances more "user-friendly" especially if these parameters are retained in the event of power loss. System configuration parameters can be stored in the x2444 to allow the design of appliances in a modular fashion, substantially reducing development costs while
increasing the reliability of each new product. System status saved in the X2444 in the event of a power failure is restored upon Power-On so that the system can complete interrupted tasks as well as ensure that the appliance is left in a safe and stable state.
The availability of the new 5V non-volatile memories allows the appliance designer to add more features and capabilities for a minimum cost. Whether it be used for power-failure data storage, or as user set-up information, the X2444 will make appliance designs less complex, more cost-effective, more
fault-tolerant, and easier to use. O
Reprinted from DESIGN NEWS, October 1983
� 1983 by CAHNERS PUBLISHING COMPANY
8-68
NONVOLATILE MEMORY GIVES NEW LIFE TO OLD DESIGNS
Terminals and other equipment can be made more flexible,
and product life can be extended by upgrading and
customizing with NOVRAMs and EEPROMs.
by Richard Orlando, xicor. inc., Milpitas. ca1it.
The recent appearance of low cost, 5-V nonvolatile memories has led to design applications that can be broken into two distinct classes. One class uses nonvolatile memory to store such data as configuration or calibration parameters. This information can be updated and then stored in the device for access on power-up. The second application uses nonvolatile memory for program storage. Here, the nonvolatile memory's main advantage is that content can be updated or changed remotely, rather than by device replacement.
Unfortunately, many end products completed prior to the availability of these devices are threatened by newer designs. The latter take advantage of the added flexibility and features afforded by nonvolatile memory. There are, however, ways to add nonvolatile memory to existing designs without a major redesign.
For example, consider the schematic of an intelligent terminal design, which will be used to illustrate methods that improve the flexibility of almost any microprocessor-based design (Fig 1). Here, the 6800 processor is the source of the "intelligence" in
Richard Orlando is product marketing manager at Xicor, 851 Buckeye Ct, Milpitas, CA 95035. He holds a BS in computer systems engineering from the University of Massachusetts at Amherst.
the design. The serial communication channel is through a 6551 asynchronous communication interface adapter (ACIA), which features an onchip baud rate generator. A 2716 erasable PROM is the program store for the 6800, and the two 2114 RAMs provide 1 Kbyte each of buffer, stack, and parameter storage. The keyboard is an ASCII-encoded type whose inputs are fed through one port of a 6821 peripheral interface adapter (PIA). The other port of the 6821 receives the dual inline package (DIP) switch settings for such user-defined operational parameters as baud rate, parity, and protocol selections.
Video control is provided by a 68045 (or 6845) CRT controller. The display RAM interface is set up as a tightly coupled, shared RAM interface. The timing
8-69
Fig 1 The original terminal design has dual inline package (DIP) switch settings that must be read by the processor. They are then parsed to determine setup parameters invoked from the terminal program contained in the EPROM.
is such that the CRT controller only accesses the data in the display RAM during the bus "dead" time of the 6800. This allows the processor to access the data in the display RAM at any time, regardless of the state of the CRT controller. The CRT controller can access the RAM transparent to the processor, and thus can relieve the processor of any access arbitration tasks.
Improving the design Although the design serves its initial purpose,
several areas, which will make it more flexible and possibly extend the life of the product, can be improved. Intended for use in a variety of applications, the original design relies primarily on software for its characteristics and "feature set." Simple changes to the erasable PROM containing the 6800's software allow such terminal "customization." This approach is adequate when end-user needs are known prior to manufacture. However, if a user wants to upgrade an existing terminal, someone must perform a costly EPROM change in the field. The same penalty applies to the manufacturer who wishes to �~upgrade" the software of the existing units in the field, in order to increase performance or to eliminate possible errors.
The second area in need of improvement is the DIP switch used for the input of user-definable parameters. It creates many manufacturing problems, since most DIP switches cannot be
handled by automated assembly equipment, such as insertion machines and wave solderers. Additionally, because someone must manually toggle the switch through a sequence of positions in order to fully test the boards, DIP switches slow down automated board testing. Also, to change parameters, a DIP switch requires the terminal user to remove an access panel and manipulate switch toggles while referring to a manual. As the range of user-definable parameters expands to include such features as emulation modes, the problem becomes even more awkward.
In the example terminal, added features and
enhancements can be made in two ways. The first
involves replacing the DIP switch with an X2443 serial NOVRAM, which is used to store user-defined setup and configuration parameters. The second replaces the EPROM with an electrically erasable PROM.
The NOVRAM, a 256-bit serial device, is organized as 16 words of 16 bits each. All communication between the device and the processor is done in a bit-serial fashion using the data in input, data out output, and the synchronous clock lines. shown in Fig 2. All operations are controlled by the microprocessor through the serial interface. Read and write operations are executed through the transmission of a specific 8-bit instruction code with an
embedded address of the word to be accessed. In the write operation, the processor follows the write command with 16 bits of data to be written. In the
8-70
read operation, the processor supplies the read instruction, and then gives the X2443 16 clock cycles, which the device uses to output the data to be read. The NOVRAM also includes several non-data types of instructions to control the nonvolatile operation of the part, the part's power consumption, and the write/store lockout feature.
The X2443 is designed to interface with single-chip microcomputers when the main consideration is minimizing 110 lines and software overhead. This device also works well in microprocessor-based designs requiring upgrading with minimal design changes. It consists of a serial static RAM overlaid or "shadowed" bit-for-bit with a 5-V EEPROM array, as shown in Fig 2. The execution of a store operation, either from the input STORE or by the execution of the software store instruction, transfers the current contents of the SRAM en masse into the nonvolatile EEPROM array. In a similar manner, the execution of a recall operation, via the RECALL
input, transfers the contents of the nonvolatile EEPROM array into the SRAM array. On power-up, the contents of the EEPROM array are automatically loaded into the RAM array for a default configuration.
When using the X2443 to replace an existing DIP switch, it is advantageous to drop the NOVRAM into the existing switch "footprint." Fig 3 shows the simple conversion of the existing site or socket (a) to accept the X2443 (b). Four of the eight 6821 110 lines used to read the DIP switch are already mapped into pins 1 through 4 of the NOVRAM.These lines originally input the current settings of the DIP switches, but can be configured through the 6821 's data direction register to serve as the three outputs and one input needed for interfacing the NOVRAM. Since hardware STORE and RECALL signals are not needed in this application, they are simply tied to VCC� All nonvolatile operations occur through software control, whose requirements are relatively
Fig 3 Within both the original DIP interface (a) and the X2443 implementation (b), the interface is serial. Therefore, only the clock, enable, data input, and data output lines need to be used.
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Fig 4 When using a header for a parsing program used with the DIP switch configuration, the possible parameters are limited to 8 bits, and an elaborate software routine is needed to interpret them.
to make switch operation straightforward in the user's manual.
Replacing the DIP switch with the NOVRAM has several significant advantages. The 256-bit nonvolatile storage leaves adequate room for storing an "image" of all interface circuit registers. Thus, the parsing problem of the DIP switch implementation is eliminated. Even the control registers that do not need to be user-programmable can benefit from this imaging, since they can be changed remotely in the field for hardware or software updates. This method simplifies field upgrading when compared with the usual method of storing these register images in the program store ROM or EPROM.
New images can either be down-loaded remotely or loaded through a diagnostic mode using a directconnect RS-232 interface. Examples of where this capability is beneficial are numerous, and include changing interface protocols, data formats, or other hardware, interface, or networking options.
The use of the device for storing setup parameters also allows a more user-friendly operator interface. Software in the original design includes routines that allow random placement of the cursor or text through the use of a "go to X-Y" routine. It
becomes a fairly trivial task to implement a menudriven setup mode. After entering a certain escape sequence, the user is placed in the configuration mode, which presents an English menu.
The return key increments the cursor position to the next setup area where the current setting is displayed, and the spacebar key increments that setting through all possible choices. Once the user has set up the parameters for a particular session, depressing the escape key writes the current settings into the RAM section of the NOVRAM. With this operation, the user can set up a temporary configuration without changing the default parameters in the EEPROM section of the NOVRAM. Default settings are changed only when the user executes a certain control sequence (such as control x and then the escape). In some applications, it may be desirable to allow only certain users to change these default parameters before entering a special code.
straightforward (as described). With this software in place, the communication between the processor and the device simply becomes a series of reads or writes to the appropriate serial device locations.
The original design only allowed eight userdefinable inputs, since only one DIP switch is used in the terminal. The meaning of the various input conditions is shown in the DIP switch map portion of the program header in Fig 4. Since the single 8-bit input is used for so many functions, parsing the input byte into the appropriate setup parameters requires an extensive piece of code. The problem with this implementation is the extensive software required
Replacing the DIP switch with the NO VRAM allows increased design flexibility, as well as reduced manufacturing and testing costs.
Since the X2443 has a much larger capacity than actually needed for this application, the remainder of the nonvolatile storage can hold such data as serial number of the individual unit, revision level, and hardware configuration diagnostic parameters. Otherwise, it can be reserved for future expansion. The Table shows a sample address map for the
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device, with the associated data stored in each of the 16-bit locations. The end results of replacing the DIP switch with the NOVRAM are increased design flexibility, as well as reduced manufacturing and testing costs.
Program storage considerations The second aspect of improving the terminal
design involves the program store for the 6800 microprocessor. The original design uses a 2716 EEPROM since the software requirements for the terminal are not extensive. The feature set of the X2816A EEPROM makes the replacement easier because EEPROMs of the X2816A generation incorporate high voltage generation, address and data latching, and the write-cycle timing circuitry on the memory chip. During read operations, the device functions just like the 2716 EPROM in its use of chip enable (CE) and output enable (OE) signals. During a write operation, the X2816A latches the addresses on the bus during the high to low transition of the write enable (WE) signal, and then latches the data to be written on the rising edge of the WE signal.
The duration of this signal is not important, since the EEPROM only uses it to initiate the write cycle; the timing for the write operation is generated onchip. The processor needs only to ignore the EEPROM for 10 ms during the write cycle, and the device does the rest. The latched and self-timed nature of the X2816A allows it to be placed in a 16-K SRAM socket and be read and written with the same signals used for the SRAM.
The read operation of the X2816A is the same as that of the 2716 EPROM, so this part of the EEPROM operation is of no concern. The only changes required to the existing circuitry involve the write operation. The first change allows the processor to write to the EEPROM, and the second protects the EEPROM from unwanted write operations during power-up and power-down.
The memory map for the original design was not very full, so only large blocks of the address map
are decoded for each memory device and 110 chip on the bus. The 2716 logically resides at addresses F800 through FFFF since the 6800 reset vectors must be included. The physical decoding for the 2716 includes the adrlress range of FOOO-FFFF since only the microprocessor's two most significant address lines Al5 and Al4 are used for the decoding.
Since line Al4 is used to drive the OE line of the 2716, the EPROM is selected whenever Al5 is a logical one. Possible conflict with the system RAM residing at 8000-81FF is avoided by restricting the processor's access to the 2716 in the logical F800-FFFF range. Since the processor can now read and write to the logical address range of the 2716 socket, the CE must also be derived from the Al5 and Al4 address lines. And, since CE is active low and the address line is active high, a simple NAND gate will suffice (Fig 5). Luckily, an extra NAND gate in the
Fig 5 The EEPROM control logic uses the processor's high order address lines to map the device into the proper address range and enable it at the same time.
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technique requires that all accesses to the EEPROM be made in the logical address range of F800-FFFF to avoid bus contention with the system RAM.
Discussion of the circuitry needed for the OE signal also must include another important issue: ensuring that the chip does not experience an accidental write cycle during power-up or powerdown. Even though the chance of CE and WE going low during power-up or power-down is rather remote, the possibility must be eliminated.
0
The EEPROM simplifies write protection by including an onchip voltage sensor that monitors the Vee input level and automatically disables writes from occurring when Vee falls below 3 V. Also, a noise filter on the WE input prevents a write from being initiated by a low spike. Functional interaction of the control inputs on the chip allows a low level on the OE to disable any write operations regardless of the state of the CE and WE inputs. By holding OE low while Vee is between 3 and 4.75 V, inadvertent write cycles are inhibited.
The power supply must be modified to generate an active low signal whenever vcc is below a specific level. This signal disables the write operation during both power-up and power-down. Because this signal is wire-ANDed with the control signal driving the OE signal, all writes to the chip are disabled when Vee is below the 4.75-V limit.
Fig 6 Address maps for updating EEPROM software are kept in EEPROM (a) and copied to RAM (b) when needed.
design can be used as an inverter. The inverter used for the CE is no longer needed, and therefore can replace the NAND gate. The inverter on Al4 must remain intact since it is used in the 2114 RAM decode circuit.
The WE line for the X2816A EEPROM can be derived from the composite RAM write signal used for the 2114 RAMs. This signal is the logical OR or the R/W output from the 6800 and the Phase 1 clock signal. This qualification of the R/W line ensures that the addresses are valid on the high to low transition of the WE signal. Therefore, they can be latched into the EEPROM. This ORing connection also guarantees that the data to be written is valid on the rising edge of the composite WE signal. The OE signal on the EEPROM can simply be driven from the complement of the R/W signal from the processor. This
Software modification Once hardware changes have been made, in-
factory modifications and in-field modifications must be addressed in order to take full advantage of an X2816A. In-factory modifications can be handled in many ways. If the terminal configuration is known at assembly time, the appropriate software can be loaded into the EEPROM through the use of a standard PROM programmer. However, this method does not take full advantage of the features of the in-circuit reprogrammability inherent in the X2816A. A more advanced approach also makes automated board testing easier.
For example, the EEPROM can be initially installed with a diagnostic program for testing the completed terminal board with an automated test system. Once the board has been tested, the tester controls the 6800 processor by holding it in a quiescent state such as reset or halt. The tester then assumes control over the terminal bus and writes the actual terminal software into the EEPROM. This greatly reduces the overhead required to manufacture a variety of different configurations or "models" on a single assembly line. In-line programming also allows for the verification of the EEPROM write operation and control circuitry.
The real advantages of the EEPROM surface when it comes to modifying software in the field. In this case, the terminal is placed in a down-load mode,
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and the software revision is loaded through the RS-232 interface, either from a service "box" or remotely via a modem. The X2816A allows the terminals in the field to be called over phone lines for loading new operating software, thereby greatly reducing the cost and impact of a software update.
Although full-featured EEPROMs such as the X2816A simplify this task significantly, there remains one software issue to be resolved. While the EEPROM is performing its internal write cycle, it is unavailable for further writes or reads. For example, the processor, executing out of a program stored in the EEPROM, might perform a write cycle to the chip and then fetch the next instruction. Since the X2816A is occupied with its internal write cycle, the next instruction fetch will yield a high impedance bus. The processor will take this data as its next instruction and enter the "catch fire and die" mode of operation.
To avoid this situation, a very compact routine fetches the byte to be written into the EEPROM from a given location, writes the byte into the EEPROM, and then enters a timing loop to wait the 10-ms period required to complete the write. Since the RS-232 interface supports full handshaking, there is no chance of overrun from the down-loaded data. This routine is initially loaded into the EEPROM, but it is never executed from this device. Instead, another
"copy to RAM" routine copies the routine from EEPROM into RAM, from which it is executed.
Since the terminal has 1 Kbyte of RAM capacity, there is ample room for storing such a routine during the EEPROM write cycle. Fig 6 shows address maps for both the EEPROM (a) and the RAM (b) prior to and during the execution of the EEPROM write routine. This method works especially well with the 6800 since its architecture is that of a von Neumann machine, and can therefore execute program segments out of the memory space reserved for RAM data storage.
In-field terminal upgradeability has two important benefits. If the terminal software is upgraded or revised after the unit is sold, the new software can be added to the existing units in the field at minimal cost. This method also eases the addition of optional hardware in the field, since the new software supporting the hardware option can be down-loaded instead of replacing the terminal EPROM.
Reprinted with permission from Computer Design-October 1, 1984 issue.
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NOTES
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A CAHNEKS PUBLICATION
ELECTRONIC TECHNOLOGY FOR ENGINEERS AND ENGINEERING MANAGERS
Save volatile
data during
power loss
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Save volatile data during power loss
Nonvolatile-storage devices give you a medium in which to store data during power loss. By combining these devices with power-sensing circuits and supplying the necessary control signals) you can design a system that transfers data securely between volatile and nonvolatile memory during power loss.
Xicor, Inc.
To protect volatile data during power loss, you need to transfer that data reliably to nonvolatile memory during the transient and return it to RAM after power is restored. A system that performs this function includes two subsystems. The first reports power status, indicating when power is lost and when it is restored; the second handles the data transfer, using the powerstatus signal to generate the appropriate store and retrieve commands.
nize the power loss and generate a power-loss signal promptly, giving the storage subsystem enough time to effect the data transfer. In fact, in some systems, you may have to complete your transfer within a single write cycle to ensure a reliable transfer.
Your first step in designing the sensing subsystem is to choose a sensing point. You could use the 5V regulator's output as a sensing point, but this output will not indicate power loss as quickly as will either the ac input line to the power supply or the unregulated de voltage supplied to the regulator.
To sense ac loss on the power supply's ac input line, you can monitor either the input or the output to the power transformer. If you monitor the transformer's input side, you must electrically decouple the sensing circuit's signal from the system's de portions (by using optoelectronic isolators, for example). If you monitor
-----------------------5.SV
DC supecv -----------------~~V"
I..
10 mSEC
STORE PULSELJ
Sense power failure
To transfer data reliably after power loss, a system must have enough time to copy data from RAM to nonvolatile memory before the supply voltage drops below a certain level. The sensing circuit must recog-
NOTE: MINIMUM RELIABLE WRITE VOLTAGE=4.5V
Fig 1-The system characterized by this timing diagram 11111st detect a power loss early enough to allow it to generate a store pulse JO 111sec before the de supply drops to 4.5V.
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Fig 2-This zero-crossing detector monitors power-supply status at the transformer's ac output. The two diodes isolate the detector from the main power supply's unregulated de bus.
POWER FAIL
DELAY
Once you've chosen a sensing point, you must choose a detector. If you've chosen to detect ac loss, consider one of the following four methods. The first is a low-cost zero-crossing detector (Fig 2), in which two diodes isolate the detector circuit from the filter capacitor (CF) that's ahead of the _regulator. When a power loss occurs, the full wave's rectified ac drops to zero, inhibiting base current to transistor Q1. This causes Q1's output to go high, thereby generating an interrupt signal at point B.
+5V
NOW GOOD
R, 2k
TO INTERRUPT
Fig 3-ln a typical p..P system that tests for power loss, once the processor receives an interrupt indicating a power loss, the system initiates a subroutine that tests for a true power loss. The subroutine first produces a delay ofabout 2 rnsec; then the system looks again at the power detector's output. If that output is still asserted, the system decides that the power loss is real and sends a store pulse to the
nonvolatile RAM.
(a) A
2 x4N25
the output side, you must isolate the detector circuit from the main power supply's filtered unregulated de circuit, because that circuit's response to a line fault is slow. To isolate the circuit, you can use either a separate transformer tap or two extra diodes between the bridge and the detector.
Alternatively, you can use the unregulated de voltage ahead of the regulator as a sensing point. The regulator maintains its regulated output as long as its input voltage remains within a certain range. To make sure that the system will have time to respond to a power loss, you should set your trip point below the normal input voltage. This allows you to send your store signal early enough to ensure a reliable transfer to nonvolatile memory. Consider, for example, the timing diagram in Fig 1 and assume that the minimum reliable write voltage of the memory in the system it characterizes is 4.5V. Because this system's de supply drops to 4.5V 10 msec after initiation of the store pulse, the system must complete a write operation to nonvolatile memory within this 10-msec period.
B (b)
-+l ~
WITHOUT CAPACITOR
DELAY
(c)
Fig 4-You can connect a detector like this one, (which contains optoelectronic isolators with their diodes connected back-to-back) directly to the ac line through a resistor (a). The circuit produces an output pulse that can interrupt a �P each time the input waveform crosses zero, or every 8.3 rnsec (b). Instead of allowing the sensor to interrupt the �P every 8.3 rnsec, you can feed these pulses first to a 555 timer that's confiqured as a missing-pulse detector. It issues an interrupt only when the input pulse train is interrupted (c).
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To ensure that you)ll be able to transfer data reliably from RAM to EEPROM)
you need to maintain powerfor at least 10
msec after a power loss.
When it receives an interrupt, the system initiates a subroutine that tests for a true power loss (Fig 3). The subroutine delays the store signal for about 2 msec and then looks at the detector again. If the output is still high, the system decides that the power loss is real, and it sends a store pulse to the nonvolatile RAM. Resistor R2in Fig 2 limits the transistor base current.
Capacitor C1 is essential in this circuit because it tilters the power supply's half-cycle pulses before they're applied to Qi. (If you were to fail to tilter these pulses, the �P would receive an interrupt signal every 8.3 msec, whether or not a power loss had occurred. Without Ci, as much as 25% of your available processor time would be spent responding to false interrupts generated by the power-loss detector.) The value that you choose for C1 depends on the power supply's holdup time, the values of R1 and R2, and the delay that you want between the loss of ac and the triggering of the store signal.
Use optoisolators
The second technique for sensing ac power loss uses two optoelectronic isolators between the detector and the ac power line (Fig 4a). This technique produces a positive output pulse at each zero crossing on the ac line, or at 8.3-msec intervals (Fig 4b). The problem with Fig 4a's circuit is that the interrupt signal occupies the �P's time while the rest of the system is resampling the detector's output. To solve this problem, you can add a missing-pulse detector similar to the one &hown in Fig 4c.
A third detector that relies on direct ac-line connection uses General Instrument's MID 400 power-line monitor. When you use this device, you need to add only two resistors to ensure a clean interrupt signal
(Fig 5). You can adjust turn-on and turn-off delays by adding a capacitor across R2.
The fourth detector (Fig 6) uses a CMOS Schmitt trigger as a full~wave, low-voltage, missing-pulse detector. To avoid latch-up, and possible damage to the CMOS circuits, you must make sure that the input voltage to the CMOS Schmitt trigger does not exceed the 5V supply voltage. You can meet this requirement by inserting a resistor between the Schmitt trigger and the bridge's output. To obtain narrow pulse widths from the first gate, keep the ac input voltage as high as possible. Ra and C1determine the output's delay, which must be longer than the first gate's pulse width. Sensing de power loss
If you've decided to sense de loss instead of ac loss, you don't have to worry about capacitor delays or missing pulses. Consider the sensor in Fig 7a, for instance. The sensor generates a negative interrupt pulse when it senses de loss; it uses a zener diode to set the trigger point. On one hand, you should set the
AC
A
20V
B
c
2 mSEC
=:=J /f..--oELAY
D (b)
I
Fig 5-To incorporate the MID 400 detector in your sensing subsystem, you need to add only two external resistors that you connect directly to the ac line. You can control the on and offdelays at the output by connecting a capacitor across Rt�
Fig 6-:-When you use two Schmitt triggers to detect ac loss (a), the delay produced by RJ and C, must be longer than the first gate's onfput pulse width. The .timing diagram (b) shows the circuit waveforms.
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+SV SUPPLY
10V
2k R2
(a)
":'
RAW DC 10V
2k R,
(b)
":'
+SV SUPPLY TRIP POINT= 14.JV
R2 ":'
RAW DC
R, 20k
+SV SUPPLY
R, 6k
TO INTERRUPT
(c)
":'
":'
":'
Fig 7-Using zener diodes you can configure a power-supply detector circuit to produce either a negative (a) or a positive (b) interrupt pulse when the trigger point is reached. You can configure the op amp
shown in c to produce either a positive or a negative output pulse
polarity.
trigger point as high as possible (to allow the circuit to sense the power loss as early as possible). On the other hand, you must still set the trigger point low enough to fall below the lower boundary of the supply's upper unregulated limit (to prevent false triggering). Remember that the diode's voltage rating should equal the desired trip-point voltage minus the 0. 7V base-emitter drop.
In the de detector circuit shown in Fig 7b, when the unregulated de voltage drops, a pnp transistor turns on and produces a positive pulse. Here, the zener diode's rating is equal to the trip-point voltage minus 5V, plus 0. 7V for the base-emitter drop.
The circuit in Fig 7c trips when the de level at R1's and R2's junction drops to the zener's voltage rating. You can provide either a positive or a negative interrupt signal, depending on the operational amplifier's input configuration.
To ensure that the regulator operates long enough to perform a reliable transfer to nonvolatile memory once a store pulse is sent, you need to use a large filter capacitor. The capacitance depends on the desired trip point, the lowest input voltage to the regulator, and the load. For example, a system with a 10-msec transfer time, a 300-mA load, a 15V trip point, and a minimum regulator input of 7V requires a 375-�F capacitor; you can derive the capacitor's value from the equation i=Cdv/dt.
Once you've chosen a sensing point and a sensing circuit, the next step is to develop a subsystem that uses the power-status signal to generate save and
POWER FAIL
6809 �P
ADDRESS DECODE
ADDRESS DATA
POWER-ON RESET
PORTA
SYSTEM ROM
GENERALPURPOSE
110
Fig 8-This industrial controller's storage architecture uses a NOVRAM as both the volatile and nonvolatile system storage elements. 8-81
Monitoring the ac line in front ofthe main supplfs power transformer gives you the fastest warning ofa power loss.
restore signals. These signals tell the storage subsystem to transfer data from RAM to nonvolatile memory during power loss and return data to RAM after power has been restored.
The type of system you design will depend largely on the type of nonvolatile storage that you plan to use with that system. For instance, you could use batterybacked RAM, or you could use a NOVRAM like the one used in the industrial controller shown in Fig 8. The industrial-controller design takes advantage of the nonvolatile RAM's ability to transfer data between RAM and EEPROM in a 10-msec single write cycle (see box, "NOVRAM architecture").
The nonvolatile RAM provides both the system storage (RAM portion) and the nonvolatile program storage (EEPROM portion) for power losses. The �P supplies a low-going TTL store signal (100-nsec min duration) to the nonvolatile RAM's store input. During the 10 msec that the nonvolatile RAM requires to complete its data transfer, you must keep the power supply's voltage within the specified operating toler-
ance. Once the system initiates a store cycle, the store cycle can't be terminated.
When the system loses power, the sensor sends a power-failure-detection interrupt to the �P. Once the processor acknowledges the interrupt, it branches to an interrupt routine that writes the current stack pointer and a test byte to the nonvolatile RAM (to signify that a power failure .has occurred) and generates a store signal. The power supply holds Vcc above 4.5V for 10 msec after it generates the power-fail signal. During the store operation, the nonvolatile RAM 1/0 lines maintain high impedance, allowing the �P to complete other tasks. After the system completes a store operation, it must drive the store input high before performing subsequent store operations.
When power is restored, the power-on-reset routine sends a recall signal to the nonvolatile RAM. The routine in the �P then checks the nonvolatile RAM's test byte to see if the previous process had been interrupted by a power failure. If so, the processor saves the current processor state and loads the address
NOVRAM architecture
A NOVRAM (nonvolatile RAM) is a memory device comprising a static RAM overlaid bit for bit with an EEPROM (electrically erasable programmable ROM). A typical nonvolatile RAM, the Xicor X2212; contains 2k bit.:;; organized as a conventional lkbyte static RAM overlaid with a lk-byte EEPROM.
The operation of the RAM portion is identical to that of other static RAMs. However, in addition to CS (chip select) and WE (write enable) pins, nonvolatile RAMs also have store and recall pins that control data transfers between the RAM and EEPROM. Because the pulse widths of the control and data inputs are less than 450 nsec, most �P-based systems don't require wait states during the data transfers.
A store operation transfers the entire RAM contents to the EEPROM in a single 10-msec write cycle. After the NOVRAM completes the store operation, the original data will reside in hoth the RAM and the EEPROM.
The NOVRAM uses a recall operation to transfer data in the EEPROM to the RAM, replacing the RAM's prior content. Instead of moving data on a wordby-word basis, store and recall operations transfer the entire content of the memory simultaneously.
NOVRAMs don't require highvoltage pulses or high-voltage supplies: The devices operate from a single 5V power source and have no battery backup. All inputs and outputs are TTL compatible. The RAM portion's
cycle time is 300 nsec, and the common data input/output is 4 bits wide.
On-chip protection
A built-in Vcc sensor protects the NOVRAM from spurious signals often initiated during power-up and power-down. The sensor establishes a threshold supply voltage of 3V. When the supply voltage falls below 3V, store operations to the EEPROM and write operations to the nonvolatile RAM are blocked.
A noise filter built into the EEPROM prevents glitches on the WE line from initiating a write cycle. This filter makes the device ignore pulses of less than 20 nsec so that noise spikes will not be interpreted as write commands.
8-82
An alternative to monitoring ac power at the power transformer is monitoring the unregulated de power to the regulator.
of the saved processor state onto the stack. It then
executes a return from interrupt and resumes the
+SV
previously interrupted process.
Fig 9-By NANDing the store, WE, and power-status signals you can protect the NOVRAM from false store commands. In this cot~f1guration, all three inputs must be true for a store operation to occur.
R 91k
30k
(a)
91k
30k
CE OR WE (OR STORE)
(b)
Fig 10-ln a hold-low protection scheme (a), a nonvolatile memory's array-recall pin is pulled to logical zero when the supply voltage falls below 5V. In hold-high protection (b), when power is lost, either the WE or CE pins are held high.
Beware false commands
One of the biggest obstacles you'll face in deriving reliable store and save signals will be to avoid false store commands. Because most �P-based systems don't operate in ideal environments, they often generate false signals during power-ups, power-downs, brownouts, and power failures. However, these signals are generally nonperiodic in nature, so the system usually recognizes them as by-products of a faulty memory device and disregards them.
Sometimes, however, these signals are periodic and turn out to be unintended write/store commands. After a system reset, for example, the �P's erratic behavior may cause the registers that usually contain the system information to contain false write-store commands instead. Therefore, when the system addresses those registers, those registers issue a false store command.
You can use several system techniques to avoid these errant commands. (For a discussion of on-chip protection features, see box, "NOVRAM architecture.") One technique for protecting the NOVRAM from errant commands takes advantage of the fact that even though most �Ps can issue spurious addresses, they don't usually issue false write commands. By ANDing the system write command with the system store command, you can make sure that the nonvolatile RAM will respond to a store signal only during a write cycle.
Nevertheless, glitches can still appear at the store pin during power up, even if no write command is received at any of the 3-state TTL gate inputs. One way to solve this problem is to use an open-collector NAND gate, one of whose inputs indicates the power supply's status (Fig 9). This method ensures that the st6re pin's voltage follows the power supply's voltage as the voltage increases.
If you hold one NAND gate's open-collector input low, the output transistor is turned off. Pulling the gate's output voltage to the nonvolatile RAM's power supply through a pullup resistor ensures that the output follows the power supply with no glitches. You can also use the power supply's status signal to hold the recall pin low and the store pin high. This technique gives you better control over the nonvolatile RAM because it uses two conditions to prevent an inadvertent store operation. All you need to do is to connect the status signal directly to the recall pin.
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Two additional methods of preventing unintentional nonvolatile data changes during power transitions are hold-low and hold-high protection. When you use holdlow protection (Fig lOa), the array recall pin is pulled to logical zero whenever the supply voltage falls below the 5V-10% threshold. The Intersil ICL8211, an 8-pin
miniature DIP, provides the voltage reference and gives a zero output whenever the supply falls below its threshold. When the sensed voltage rises above the selected threshold, the device produces a logical one.
(Fig lOb) gives an example of hold-high protection. ICL8211 keeps the voltage on the nonvolatile RAM's store pin (or the WE or CE pins) near the power supply's voltage level. This blocks the low pin voltage that's necessary for a write or store operation.
The power-supply output that ICL8211 senses is a sawtooth waveform. ICL8211's output is a logical 1 while the supply output is above 4.5 volts. Below 3V, the nonvolatile RAM's internal protection circuitry prevents inadvertent writes or stores. In the critical unprotected range between 3 and 4.5V, ICL8211 provides a zero output to prevent writes or stores.
An alternative to ICL8211 in these applications is the
SGS L487. The SGS L487 is a 500-mA precision 5V
voltage regulator that includes an open-collector power-
on/power-off reset output pin that protects nonvolatile
memory the same way the ICL8211 does.
Other schemes that protect systems from inadver-
tent store operations employ jumpers, cables, and
switches. You transmit the store signal through a
jumper or switch that you hold open unless you're
changing data in the EEPROM. During normal opera-
tion, the only component attached to the store pin is a
resistor to the power supply.
llDll
Author's biography
Christoplwr Lopes is an applications engineer at Xicor (Milpitas, CA), wlwre his duties include system-level evaluation, product-application development, and customer technical assistance. A member oftlw IEEE, Chris holds a BS in electrical and electronic engineering from California State University at Sacramento and is currently enrolled in tlw MBA program at tlw University of Santa Clara. He enjoys windsurfing, skiing, and tennis.
Reprinted from EON February 21, 1985 �1985 CAHNERS PUBLISHING COMPANY
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REPRINTED FROM
Electronics@
THICK OXIDE BEATS THIN FILM IN BUILDING BIG EEPROMS
8-85
THICK OXIDE BEATS THIN FILM IN BUILDING BIG EEPROMS
XICOR USES IT TO SOLVE 3-D SCALING PROBLEMS IN 256-K CHIPS
B y abandoning the conventional thinfilm route to fabricating high-density
horizpntally and fi:om 600 to 800 A down to 400 A vertically.
The thick oxide enabled Xicor's designers to form a basic
electrically erasable
EEPROM cell with a triple-poly
programmable read-only mem-
structure that puts the pro-
ories, Xicor Inc. may have
gramming portion atop the
overcome the problems that
erase mechanism. This result-
have kept the parts from
ed in horizontal cell dimensions
climbing above the 64-K densi-
smaller than the thin-oxide
ty level. The Milpitas, Calif.,
structure.
company employed a conserva-
Another factor in the small-
tive 2-�.m process and standard
er size was the use of a propri-
off-the-shelf 5x stepper litho-
etary textured thick-oxide sur-
graphic equipment to build a
face on the programming ele-
256-K EEPROM.
ments. The textured surface's
The key to doing this was
electrical potential per unit
the use of' a thick oxide and a
area is greater than conven-
unique triple-polysilicon float-
tionally used smooth surfaces,
ing-gate cell, says William
producing cells that are inher-
Owen, Xicor's vice president of
ently smaller than comparable
research and development. The
thin-oxide cells, but with the
process is inherently more reli-
same effect. The oxide can be
able and easier to scale to sub-
shaved off without affecting
micron dimensions, he claims,
cell reliability, making vertical
although it was more difficult
scaling relatively easy.
for the Xicor engineers to mas-
The first 256-K EEPROM
ter. They were less familiar
fabricated with the 2-�.m pro-
with it than with the thin-oxide
cess is the 32-K-by-8-bit n-MOS
double-poly technology derived
X28256. It features a chip area
from EPROM manufacture.
of about 64,000 mils2 (Fig. 1),
Conventionally used thin-ox-
equal in size to many thin-ox-
ide floating gates are relative- 1. SMALL DIE. Equivalent in size to many thin-oxide 64-K parts, ide 64-K parts fabricated using
ly easy to manufacture, but Xicor's 256-K EEPROM die measures about 64,000 mils2�
1.5-�m design rules, and half
cannot be scaled down easily
the size of thin-oxide 256-K EE-
without introducing significant reliability problems. This un- 1 PROMs designed with 1- to 1.2-�m geometries. Soon to follow
pleasant consequence of the laws of physics is one reason will be a CMOS version, the X28C256. Both parts feature 150-
many EEPROM houses are having difficulty moving to densi- ns access times and support 64-byte page-write operations. A
ties beyond 64-K to the 256-K level. To do so requires pushing write cycle takes 31 �.s per byte, enabling the entire memory
minimum line widths on the oxides down to 1 �m using to be written in less than 1 second.
advanced photolithography.
In Xicor's triple-poly cell (Fig. 2), the floating gate sits
"The problem with scaling EEPROMs lies in the fact that it between the upper and lower poly layers, forming the thick-
is necessary to scale in three dimensions-in the vertical as oxide tunnel structures for erasure and programming. Com-
well as horizontal directions," says Owen. "To achieve 256-K pared with the 80- to 120-�m2 cells of conventional 1-�.m thin-
densities, not only must thin-oxide EEPROMs be scaled from 2 oxide designs, the electrically erasable cell in Xicor's 2-�m
or 3 �m down to 1 to 1.5 �m in the horizontal direction, but 256-K parts measure only 68 �m2� 0
from 90 to 100 A down to about 70 to 80 A in the vertical The programming tunnel mechanism occurs between the
direction." To achieve similar densities in its 256-K EEPROM, first and second floating-gate poly layers; the erase tunneling
Xicor found it necessary only to scale down from 3 to 2 �m action occurs between the second and third (Fig. 3, left). As
in the thin-oxide approach, a selection transistor isolates the
TECHNOLOGY TO WATCH is a regular feature of Electron- selected cell on a column while a capacitor develops, through
ics that provides readers with exclusive, in-depth reports on capacitive coupling, enough voltage across a tunneling device
important technical innovations from companies around to make electrons tunnel on and �off the floating gate. This
the world. It covers significant technology, processes, and voltage is sensed by a MOS transistor, whose gate is formed
developments incorporated in major new products.
by the second poly layer.
Electronics/May 12, 1986
8-86
COLUMN
WORD LINE - - - - - - e - - - - - - - - - - t
SELECT TRANSISTOR
ERASE TUNNELING THIRD POLYSILICON LAYER
_________ COUPLING DEVICE------...:'------------'
CAPACITOR
----j 1-- - I - - - - - - 1...___ SECOND POLY LAYER
~~~~~ti~ G ~.---F-1R-S-T-PO_L_Y_L_A-YE_R_ __,
DEVICE
FLOATING GATE
FLOATING-GATE
SENSE TRANSISTOR
cation techniques, Xicor exploits this phenomenon to build EEPROM transistors using thicker silicon dioxide layers that can still discharge the floating gate. Because the oxidation is a well controlled step, the properties of the emitters are exceptionally regular. They are shaped so that the electric field increases at the crest of the hills, substantially enhancing the emission of electrons.
The poly electrodes are separated by
oxide layers about 500 to 800 A thick.
Without the hillocks, Xicor says, 100 V would need to be applied to produce effective tunnel current. With the textured surfaces, the voltage required for tunnel-
-2. T-RIP-LE-PO-LY-. K-ey-to t-he-sm-all -die-are-a i-s a-un-ique-tr-iple--po-ly f-loa-ting--ga-te-cel-l. T-he-gat�e, ignegneisraotendlye1a0siltyo o2n0 cVh,iplowwitehnoanugihntteornbael
between the upper and lower poly layers, performs erasure and programming.
charge-pump circuit.
The coupling capacitor's size also con-
Because capacitance increases linearly as oxide thickness de- tributes to the smaller cell area. To induce tunneling, the
creases, tunnel devices made with very thin oxides-80 to 100 floating-gate voltage is raised or lowered through capacitive
A thick-rate 5 to 10 times higher than tunnel devices made coupling to a bias-voltage supply. To avoid excessively high
with 500- to 800-A-thick oxides. Consequently, cells using thin bias voltages, efficient coupling to the floating gate must be
oxide have to push photolithography requirements to the limit achieved by making the coupling capacitance much higher
of available equipment and processes in order to make the thin- than all other floating-gate capacitances combined. These oth-
oxide tunneling devices as small as possible. The� coupling ca- er capacitances include that of the MOS sense transistor, and
pacitor, which must be made from a thicker, nontunneling especially that of the tunnel devices.
oxide, ends up relatively large to obtain efficient coupling.
To electrically program a cell, electrons must tunnel onto
In contrast, thick-oxide tunnel devices inherently have very the floating gate. In Xicor's triple-poly enhanced-emission cell,
low capacitance. Therefore they can be made with reasonable this is accomplished by applying a bias voltage to the coupling
feature sizes and still produce a small cell with good coupling- capacitor to capacitively pull the floating gate high and devel-
capacitor efficiency. Since the feature sizes used in the tunnel op a voltage across the program tunneling device. When this
devices are compatible with the lithography requirements of voltage reaches the tunnel voltage, electrons tunnel from the
the rest of the cell, they can be readily scaled down as ad- first poly level's surface through the programming device to
vances in lithography technologies become available for the second-level floating gate. When the applied voltages are
manufacturing.
brought back to normal reading levels, the programmed float-
What makes this structure work is its surface, which Xicor ing gate carries a negative voltage because of the extra elec-
describes as textured with hillocks (Fig. 3, right). Also called trons on it. When read, the MOS floating-gate sense transistor
asperities, these odd-looking features were at first considered is turned off by the negative voltage and a 0 is produced at
an undesirable side effect of MOS processing, and occur be- the EEPROM's output.
cause oxidation progresses faster along some crystal direc- To electrically erase a cell, electrons must tunnel off the
tions than others. Because crystal orientation is random in floating gate. In Xicor's triple-poly cell, this is done by capaci-
deposited poly, there are points on the surface of an integrat- tively coupling the second poly level's floating gate low while
ed circuit where oxide growth is enforced. The temperature of the third poly level's word line, which forms the other end of
the oxide controls the size and shape of the hillocks.
the erase tunneling device, is brought high. When the voltage
Through the use of carefully designed and controlled fabri- across the erase tunneling device reaches the tunnel voltage,
3. TUNNELS AND TEXTURE. In Xicor's cell design, programming by tunneling action occurs between layers 1 and 2 and erasure between layers 2 and 3 (left). The thick-oxide cell approach uses a "textured" floating gate surface to enhance electron emission.
FLOATING GATE
PROGRAM AND ERASE LINE
THIRD LEVEL p-SILICON SUBSTRATE
+V
. _ _ .�(.~.------_~___,
Electronics/May 12, 1986
8-87
electrons tunnel from the second poly floating gate to the maximum read voltage, a textured surface requires a lower
third poly word line. When the applied voltages are brought programming voltage than a planar thin-oxide structure, lead-
back to normal reading levels, this erased floating gate has a ing to better scaling.
net positive voltage because of the lack of electrons on its With regard to endurance, recent data on Xicor's EEPROMs
surface. When read, the MOS floating-gate sense transistor is indicates an expected failure-in-time rate of 0.015% per 1,000
turned on by this positive voltage and a 1 is produced at the hours, or 150 FIT, in systems requiring 10,000 data changes
EEPROM's output.
per byte over a 10-year period, says Owen. "Thus for many
Other advantages of the thick-oxide approach, says Owen, applications, the endurance-related fallout is actually similar
include improved data retention and endurance, or the number to or lower than other semiconductor-related failure rates."
of data changes a nonvolatile memory can sustain before the To achieve 1-Mb densities, Owen believes that although it
first bit fails. Because the floating gates in the Xicor design will require moving to 1-�m geometries horizontally, only a
are completely surrounded by thick thermal oxides, similar to few "tens of angstroms" reduction will be necessary in the
an EPROM, data retention is excellent even at very high vertical direction. "In thin-oxide EEPROMs, this is a reduction
temperatures. "In fact, the only way retention can be mea- of 10% to 15% down to the operational limits of the floating-
sured on the thick-oxide devices is by subjecting them to gate mechanism," he says. By comparison, Xicor's thick-oxide
temperatures over 300�C for several weeks," Owen says. "If approach requires a reduction on the order of a few percent-
these measurements are extrapolated, the typical retention age points. "Moreover, the scaling is well within the limits of
for a Xicor EEPROM is more than 2 million years at 125�C." the Xicor cell design," he says. "As a matter of fact, we think
But for the record, the company is much more conservative, we can continue to scale for several generations before we
guaranteeing data retention of only 100 years at 125�C.
run into any of the problems our competitors are running into
The data-retention advantages of the textured thick-oxide with thin-oxide EEPROMs."
D
approach are retained-or
even improved-as devices are scaled, he says. This is
XICOR: FROM LONG SHOT TO LEADER
due to the fact that lower Life is sweet these davs for
programming voltages are Raphael Klein. Julius Blank,
needed in order to scale the William Owen III, and Wal-
memory properly, so isolation lace E. Tchon, who all helped
widths and device channel found Xicor Inc. in 1978. But
lengths can be reduced in thev can recall the time when
both the memory array and the. Milpitas, Calif., compa-
in the peripheral circuitry. nv's chance of survival was However, for a typical part, c~nsidered a long shot.
which stores data in 3 ms "The problem was that few
and must retain it for 10 in the industry thought we
years, the tunneling current had a technological edge ex-
under storage and reading cept us," says Owen, vice
conditions must be reduced president of research and de- COMING UP ROSES. The commitment to thick-oxide EEPROMs finally
by at least 1011 than under velopment. "There was Intel starts paying off for Xicor lnc.'s Tchon {left), Blank, Klein, and Ow.en.
programming conditions be- Corp., with its thin-oxide ap-
cause the retention time is proach to fabricating electri- $500,000 as well as a $10 mil- holds two patents.
1011 times longer than the cally erasable programmable lion lease guarantee.
Owen, who joined the com-
storage time.
read-only memories, and Third, the company contin- pany to direct its develop-
For planar nontextured there was Xicor, with the ues to dominate the market it ment of advanced memories
tunneling structures, this is a thick-oxide approach. Every- created, 5-V-onlv EEPROMs. in 1978, holds an MS in elecdiffi.cult design constraint be- body seemed to be going the Sales have gro\~n from $2.8 trical engineering and previ-
cause the slope of the cur- thin-oxide route." All that is million in 1982 to $39 million ouslv worked at Intel. As a
rent voltage curve-that is, changing now.
in 1984. Estimates for 1986 process engineer and senior
the relationship between the First of all, it is becoming range as high as $55 million. design manager, he was in-
current and voltage of the clear that the company is at Finally, Xicor had profit- volved in the development
tunneling device-is fixed. least a generation ahead of able operations during al! and design of Intel's HMOS
This means that the maxi- its competition with its thick- four quarters of 1984 plus Ql memory products.
mum allowable read voltage oxide approach. While every- of 1985. It owns about 507< Strategic planning vice
drops with the programming one else is pushing to 1-�m of the market for 5-V EE- president Tchon, who joined
voltage on a volt-for-volt ba- geometries to achieve 256-K PROMs and Novrams, static Xicor to aid in the develop-
sis, not proportionately.
products, Xicor is coasting random-access memories ment of its initial memories,
On the other hand, a tex- along with a relatively con- backed by nonvolatile EE- is now principally involved it1
tured-surface
tunneling servative 2 �m to achieve the PROM cells.
business planning, patent ac-
structure has a much steeper same density.
Klein, now chief financial tivity, and investor relations.
current-voltage curve; that is, Second, thin-oxide advocate officer and chairman of the With an MS in physics, Tchon
for each increment of change Intel has entered into a long- board, is a graduate physicist holds 10 patents. Before Xi-
in one voltage, there is an term agreement with Xicor from the Israeli Institute of cor, he held engineering pos-
amplified increment of for joint development of ad- Technology and performed in tions at Honeywell Informa-
change in the other. In addi- vanced EEPROMs. The deal a variety of technical man- tion Systems and Intel.
tion, the curve is not fixed, also calls for mutual second- agement positipns at Fair- Blank, one of the original
which means the relationship sourcing of EEPRO.Ms and child, Intel, Monolithic Memo- eight founders of Fairchild
:Ji- between th.e current and volt- related products. :\s part of ries, and National Semicon- Semiconductor Corp. in 1957,
age can be tailored to yield the agreem~nt with Iiitel, Xi- dnctor before starting Xicor has been a member of the
steeper curves if necessary. cor has received $6.5 millio1; a~: i'.s firRt president. He co.r board of directors since
I This means that for a given and may receive an additional
its founding.
L-�-�------��------~-------------'--------------'--�
------
Reprinted from ELECTRONICS, May 12, 1986, copyright 1986 by McGraw-Hill, Inc. with all rights reserved. AddHional reprints may be ordered by calling Electronics Reprint Department (609) 426-5494.
8-88
A PENTON/IPC PUBLICATION
TECH BRIEFS
SOLID-STATE POTENTIOMETER
RICHARD PALM Applications Engineer Xicor Inc. Milpitas, CA
Potentiometers play a vital role in circuit design, yet they have a
number of problems. Their settings can change when exposed to vibration. They are difficult to use with automatic insertion and soldering equipment. And trimming must be done by hand.
A solid state potentiometer solves these problems. Packaged in an eight-pin minidip, an electrically
X9MME functional block diagram
U/0
INC
7 Bit counter
cs
Transfer Array logic
Nonvolatile memory
Wiper position decode
Programming, control and power-on
detect
Gnd _ _ _ ___.
L--------Vw
erasable (E2) device called the X9MME digitally controls resistance trimming. The device has three-wire TTL control and operates from a standard 5-V power supply. Packaged in the dip is a 99-resistor array. Tap points are between the resistive elements and at the ends of the array. A tap point can be connected to the wiper output Vw.
Because the resistive elements are all equal, each has 1/99 the total resistance of the array. In a voltage divider application, moving the wiper up or down the array produces a linear output on Vw, with a resolution of 1%.
The tap point on the array is selected with three TTL inputs on the digital portion of the device. These inputs control a seven-bit up/down counter. To move the wiper tap point, the "chip select" line must be activated (CS = LOW), the wiper direction selected (U/D, up = HIGH, down = LOW), and a clock pulse provided to the INC input. Counter output is decoded to select one of 100 tap points.
Mechanical potentiometers essentially have a nonvolatile memory; resistance does not change until the wiper is moved. In the X9MME, seven bits of nonvolatile E2 memory retain the resistance value. When the device is deselected after a wiper position change, the counter output is stored in memory. If power is re-
8-89
TECH BRIEFS
moved and subsequently �restored, the �nonvolatile memory contents are transferred to the counter and the last stored wiper position decoded. Wiper position retention is 100years.
The manufacturing and test cost of equipment produced in high volumes can be reduced when solid state pots are used. Because automatic insertion equipment can be used, the device is soldered and cleaned just like other electronic components. This eliminates special handling and cleaning steps. During board testing, automatic
test equipment (ATE) can check the device and set wiper position. Hand operations are� reduced, and the cost of supplemental test equipment is eliminated.
Operator convenience can also be of prime concern in circuit design. If the equipment operator or field technician �must access the pot to make adjustments, the design process is complicated. The X9MME, in contrast, can be placed anywhere in the circuit and still be controlled through keyboards or a microprocessor.
As an example of how circuitry
can be simplified, consider a hypothetical car radio system. Control might be by miniature rocker switches� mounted on the steering wheel. The switch sense and. 7-bit parallel-in-serial-out circuit could be implemented in either discrete TTL circuits or as a standard cell or programmable logic device. The microcontroller interface would be two wires, one for the shift clock and another for the interrupt and data transfer. The microcontroller actuates off/on, AM/FM selection, and tuning. Six port lines control volume, bass, treble and balance. �
Microprocessor controlled radio
AM FM Station select Volume
Switch sense and 7-bitPISO
circuitry
Tuner circuits
cs
INC
U/D Microcontroller
1/0
cs 1/0 - - - - - t - - - t - - - 1
1/0 - - - - - + - - + - - I INC
1/0 -----1----1 U/D
1/0
1/0
cs
fNC 1/0 1/0
U/0
Input 1 Input 2 VH -----'--~ Zener voltage Vw 1---+---">FV'J"--.._--I Vol VL
VH Vw
VL
DC operated
tone/volume/
balance circuit
VH Vw VL
Data
CLK
Two wire interface
es VH
INC Vw U/D VL
Output 1 Output 2
I I
Copyright� 1986 by Penton Publishing, Inc.. Cleveland, Ohio 44114
8-90
)li1:0,
1K
X2201 A Product Bit Map
Nonvolatile Static RAM
On the following pages are individual device bit maps. These bit maps are supplied to aid in the development of test programs.
1024 x 1 Bit
0 0 0 0 0 0 0 0 0 1 0 00 10 0 0 0 1 1 00 00 0 0 1 0 1 001 0 0 0 1 1 1 0 100 0 0 100 1 0 010 0 011 01 00 01 01 0 1 1 1 0 0 1 1 1 1
0 0 0 0 0 0 0 1 1 0 0 1 0 100 1 1 10 10 0 0 10 1 0 1 1 0 0 1 1 1 1 0 0 0 100 1
0 1 0 0 1 1 1 1 1 0 0 10 1 1 1 0 1 1 1 1 1
0 1010 1010 10 10101 00 1100 1100110011 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Yo= As Y1 = A4
Y2 = A1 Y3 = Aa Y4 =Ag
0 10 10 10 10 10 10 10 00 1100 1 1001100 1 0 00 0 1 111000 0 1 11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1
Each Square Equals One Bit.
Address to XY Key Ag As A1 As A5 A4 A3 A2 A1 Ao y 4 Yo y 2 X1 Xo y 1 y 3 X2 X3 X4
8-91
256 Bit
X221 OProduct Bit Map Nonvolatile Static RAM
64 x 4 Bit
1/0
1/0
--~~~~~~--~~~~~~--X2X1Xo--~~~~~~--~~~~~~--
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 A4 Aa As 3 4 3 4 3 4 3 4 3 4 3 4 3 4 3 4
0 0 0
i---1--t--+-+-+-+--t--t--t----r--+--+--+--t--+--t
i---1~--t--+--+-+-+-+--t--t--t----r--+--+---+--i
.__.,f---+----l---+-+-+--+--+--+--+--1----1--4---+---l---lo o 1 i---1~--t--+-+-+-+--+--t---+--t----r--+--+---+--i
.__.,f---+----l---+-+-+--+--+--+--+--1----1--4---+---l---I 0 1 0 l---lf----4----1---+-+-+--+--+--+--+--+----l----l---+---l---I
t---ii---1--t--+-+-+-+--+---+--t--+--l--+--+---+--i 0 1 1 l---lf----4----1---+-+-+-+--+--+--+--+--l--l--+---l---I 0 0
i---;~--t--+-+-+-+--+--+---+--+--1---1---+---+--i
0 1
i---;~--t--+-+-+-+--+--+--t--t----r--+--+---+--i
of--if--i--+--+--+-+-+-+-+--+--+--+---+--+--1--1
1 L-...J'--1--L--'---'--'----'--'--'--'--'---'--'--L---'--'
0 1 0 1 0 1 0 Yo= A2 1 0 0 1 1 0 0 Y1 = A1 1 1 1 0 0 0 0 Y2 =Ao
0 10 10 10 100 1100 1 1 1 0 0 0 0
Each Square Equals One Bit.
Address to XY Key
As A4 As A2 A1 Ao Xo X2 X1 Yo Y1 Y2
8-92
1K
X2212 Product Bit Map
256 x 4 Bit
Nonvolatile Static RAM
1/0
1/0
--~~~~~~--~~~~~~-X4X3X2X1Xo--~~~~~~---~~~~~~-
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 A1 A4 Aa As As 3 4 3 4 3 4 3 4 3 4 3 4 3 4 3 4
0 0 0 0 0 1--+-+-+----+--+---+---+--+--+--+-+-+-+--'f--l--t
~-+--+-+-+--+--1-+-+--+--+--+--+--+--+-+--l
0 0 0 0 1 1--+-+-+----+--+---+---+--+--+--+-+-+-+--f--l--t
~-+--+--+-+--+--1-+-+--+--+--+--+--+--+-+--l
0 0 0 10
1--+-+--+---+--+---+---+--+--+--+--+-+-+--tf--l--t
~-+--+--+-+--t--i-+--+-+--+--+--+--+--+-+--l
1---->--+-+--+---+--+---+--+---+-t--1-+-+--+---+-~o o o 1 1,___.--+_____________._-+-._...--+-+--+---+-~
0 0 1--+-+-+----+--+---+---+--+--+--+-+-+-+--lf--l--t 0 0
1--+-+-+--+--+----l--+--+--+-+--l-+-+--+--+-~
0 0
1--+-+-+--+--+----1--+--+--+-t--i--+-+--+---+-~
0 0 ~-+--+--+-+--+--1-+-+--+--+--+--+--+--+-+--l
0 1 ~-+--+--+-+-+-+--+--1--+-+-+--+---+---+--+-1
1 0 r-+--+--+--+--+-+-+--f--1-+-+-+--+---+--+-~
1--+-+--+---+--+---+--+--+--+--+--+-+-+--tf--l--t 0
0
1
1
1 ~-+--+--+--+-+-+--t--i--+-+-+--+--+--+--+-1
0 1000
t-+-+-+---t---+---+--+--+-+-t--i--+--+-+---+-~
r-+--+--+--+-+-T--t--i-+-+-+--+--+---+--+--t
0 1 0 0 1 1--+-+-+--+--+--+--+--+--+-+--1-+-+--+--+-~
r---1--+--+-+-+--1--+-+-+---+--+--+--+-+-+--t
0 10 10
1--+-+-+--+--+----l--+--+-+-+--t--+-+--+---+-~
~-+--+--+--+-+-+--+--1-+-+-+--+---+---+--+-1
0
t-+-+-+---t--+---+--+--+-+-t--i-+--t---t---+-~
1 0
1
1 r--+--+--+-+-+--t--+-+--+---+--+--+--+--+-+--t
0
t-+-+-+---t--+---+--+--+-+-+--t--+--+-+---+-~
1 0 0 r--+--+--+-+-+--t--+-+--+---+--+--+--+--+-+--t
1---->--+-+--+---+--+---+--+---+-t--1-+-+--+---+-~o
o 1 t--t-+-+--+---+--+---+--+--+-+--<-+-+-+--+-~
1---->-t--+--+---+--+---+--+---+-+--t-+-+--+---+-~o 1
1 o+--1-+-+--+---+--+--+--+-+-+--t-+-+---+--+-~
0 1111
1--+-+-+--+--+----l--+--+-+-+--t--+-+--+--+-~
~---1--+--+-+-+--t--+-+--+---+---+--+--+--+-+--t
1 0 0 0 0
t-+-+-+--+--+---+--+--+-+-t--t--+--+-+---+-~
r--+--+--+-+-+--t--+-+--+---+---+--+--+--+-+--t
1 0 0 0 1
1--+-+-+---t--+---+--+--+-+-t--1--+--t--+---+-~
~--+--+--+-+-t--1--+-+--+---+---+--+--+--+-t--1
>----+-t--+--+---+--+---+--+--+-t--1--+--+--+---+-~1 o o 1 o+--1-+-+--+---+---+--+--+-+-+--t-+-+----+--+-~
1 0 0 1 1
1--+-+-+--+---+--+--+--+-+-+--t-+-+--+--+-~
~-+--+--+-+-+--t-+-+--+--+---+--+--+-+-+--t
0 100
f--1--+--t--+---+--+--+--+-+-+--t--+-+--+---+-~
0 1 0 1
f--1--+--t--+---+--+--+--+-+-+--t--+-+--+---+-~
o 1 1 o,_.-+-+--+--+--+---+--+--+-+--<-+-+-+---+-~
0 1 1 1+--1-+-+--+---+----l--+--+-+-+--t-+-+----+--+-~
0 0 0 +--1-+-+--+---+----l--+--+-+-+--t-+-+--+--+-~
0 0 1 +--1-+-+--+--+--+--+--+-+-+--t-+-+--+--+-~
0 10 f--1--+--t--+--+--+--+--+-+-+--t--+-+--+---+-~
0 1 1t--1--+-+--+---+--+---+--+--+-+--<-+-+--+---+-~
o o+--1-+-+--+---+----l--+--+-+-+--t-+-+----+--+-~
1
1--+-+--+--+--+--+--+--+-+--+--1-+-+--+---+-~
0 1 ~-+--+--+-+--+--t-+-+--+--+----1---+--+--+-+--t
1 1 1 1 0
1--+-+-+--+--+---+--+--+--+--+-+-+-+--lf--l--t
~-+--+--+-+-+--1-+-+--+---+----l--+--+-+-+--l
._.___.____,__.__.__.__.__.___,__....._,__.__.__.__._~
1
1
1
1
1
~_.__.___.___.__....._,__.__._~__._~~~_,__~
0 10 10 10 100 1100 1 1 1 0 0 0 0
Yo= A2 Y1 = A1
Y2 =Ao
0 1 0 10 10 100 1100 1 1 10 0 0 0
Each Square Equals One Bit.
Address to XY Key Ao
8-93
1K
X2001 Product Bit Map
128 x 8 Bit
Nonvolatile Static RAM
1/0
1/0
01010101010101012323232323232323
01010 10 00 1100 1 00 00 111
0 101010 00 1100 1 0 0 0 0 1 1 1
X3 X2 X1 Xo A5A5A4A3
0 0 0 0 0 0 0 1 0 0 10 0 0 1 1 0 100 0 10 1 0 110 0 111 1 0 0 0 1 0 0 1
0 10 0 1 1 1 1 0 0 10 1 1 1 0 1 1 1 1
Yo= A1 Y1 = A2 Y2 =Ao
54545~54545454547676767676767676
010 1010 100 110 0 1110 00 0
0 10 10 10 100 1100 1 1 10 0 0 0
Each Square Equals One Bit.
Address to XY Key
As A5 A4 A3 A2 A1 Ao X3 X2 X1 Xo Y1 Yo Y2
8-94
4K
X2004 Product Bit Map
512 x 8 Bit
Nonvolatile Static RAM
X5X4X3X2 X1 Xo
~~~~~~~~1_/o~~~~~~~~~AaA7A5A5A4A3 ~~~~~~~~v_o~~~~~~~~~
01010101010101012323232323232323
54545454545454547676767676767676
000000
000001
0000 10
0000 11
000 100
000 0 1 0 0 0 10
000 1 11
0 0 10 0 0
0 0 10 0 1
0 0 10 10
0 0 10 1 1 00 1 00
00 1 0 1
0 0 1 1 10
00 11 11
LI\
LI\
\j
\j
_N
ll\
\j
\j
LN
_N
\j
\f
ll\
\f
~
J\
J\
l'l
l'l
j\
j\
l'l
I"
1 100 00
10 0 0 1
10 0 10
1 10 0 1 1
1 10 1 0 0
1 10 1 0 1
1 10 10
110 11
10 0 0
10 0 1
1 1 10 10
1 1 10 1 1
1 1 1 1 0 0
0 1
1 0
1111 11
J\.
j\
I"
l'f
J\
r-i-
~
010101010101010 001100110011001 0000111100001111
Yo=A1 Y1 =Az Yz =Ao
0 10 10 0 1 1 1 10
0 10 10 0 0 0 0
10 10 10 10 10 0 1 10 0 1110 0 0 0
0025-8
Each Square Equals One Bit.
Address to XY Key As A1 A5 As A4 A3 A2 A1 Ao X5 X4 X3 X2 X1 Xo y 1 Yo y 2
8-95
4K
X2404 Product Bit Map
512 x 8 Bit
Electrically Erasable PROM
LSB 00 PAGE 0 08 32 ROWS 10 18
FO F8
BYTE Xo BYTE X8
_N
f'f
MSB
00 01 02 03 04 05 06 07
08 09 OA OB OC OD OE OF
10 11 12 13 14 15 16 17
18 19 1A 18 1C 10 1E 1F
.N
.N
N"
N"
FO F1 F2 F3 F4 F5 F6 F7
F8 F9 FA FB FC FD FE FF
PAGE 1 SAME AS
PAGE 0
Each Square Equals One Byte.
0025-1
8-96
4K
X2804A Product Bit Map
512 x 8 Bit
Electrically Erasable PROM
X4 X3 X2 X1 Xo A4A5A5 A1 As
000 00 000 0
0 0 0
000 0
00 00
00 0 1
0 0
1
0 0
0
..J\
N"
0 0
0
~~
N""r-r-
00000000 0000 1111 00110011 0 10 10 10 1
Each Square Equals One Byte. Byte Map
0
Y3=A3 Y2=A2 Y1 =A1 Yo=Ao
1111111 0000111 0011001 0 10 10 10 1
0025-2
Address to XY Key As A? A6 A5 A4 A3 A2 A1 Ao Xo X1 X2 X3 X4 Y3 Y2 Y1 Yo
8-97
16K
X2816B Product Bit Map
2048 x 8 Bit
Electrically Erasable PROM
X5 X4 X3 X2 X1 Xo A10A9 Aa As As A1
0 0
00 00
0 1 1 1
1 0
00 01
00 10
00 11
0 100
0 1 0 1
0 1 10
01 11
10 00
10 0 1
10 10
10 11
1 1 0 0
110 1
11 10
11 11
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000 11111111 0000 11110000 1111 0011001100110011 0 10 10 10 10 10 10 10 1
Y4=A4 Y3=A3 Y2=A2 Y1 =A1 Yo=Ao
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00000000 11111111 0000111100001111 0011001100110011 0 10 10 10 10 10 10 10 1
Each Square Equals One Byte.
Byte Map
1110011101 111021110311104 J 110511105 J 1101 I
Address to XY Key A10 Ag A0 A1 A5 A5 A4 A3 A2 A1 Ao X5 X4 X3 Xo X1 X2 Y4 Y3 Y2 Y1 Yo
0025-4
8-98
64K
X2864A Product Bit Map
8192 x 8 Bit
Electrically Erasable PROM
~ ~
X7 Xs X5 X4 X3 X2 X1 Xo A12 A11A10A9 As As As A1
0 0
0000 00
0 1 11
1 0
0000 0 1
0 000 10
0000 11
000 100
000 10 1 0 0 0 1 10
000 1 11
0 0 10 00
0 0 10 0 1
0 0 10 10
0 0 10 1 1
00 1100
~
~
10 0 0 0
100 0 1
1 10 0 10
1 10 0 1 1
1 10 1 0 0
1 10 1 0 1
1 10 1 10
10 1 1 1
1 10 0 0
1 110 0 1
1 1 10 10
1 1 10 1 1
1 1 1 1 0 0
111 01
1 1 10
111 11
.__.__.__l.j\'\j
~['!
~ ~
0000000000000000 0000000011111111 0000111100001111 0011001100110011 0101010101010101
Y4=A4 Y3=A3 Y2=A2 Y1 =A1 Yo=Ao
11 11111111 111111 0000000011111111 0000111100001111 0011001100110011 0101010101010101
Each Square Equals One Byte.
Byte Map
l l l l l l l !1100 1101 l!02 l/03 l/04 l!Os l/05 ll07 J
Address to XY Key Ao Yo
0025-5
8-99
64K
X2864B Product Bit Map
8192 x 8 Bit
Electrically Erasable PROM
00000001 00000010 00000011
, l/Oo 1/01 , 1/02 , 1/03 :
�COLUMNS�COLUMNS�COLUMNS�COLUMNS� :(32 COLs):(32 COLs):(32 COLs):(32 COLS):
BINARY
(256 ROWS)
� �
I
, 1/04 , I/Os , I/Os : 1/07 ,
1COLUMNS�COLUMNS�COLUMNS 1COLUMNS� :(32 COLs):(32 COLs):(32 COLs):(32 COLS):
11111100 1111110 1 11111110 1 1 1 1 1 1 1 1
Y4=A4 00 00 00 00 00 00 00 00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y3=A3 00 00 00 00 1 1 1 1 1 1 1 1 00 00 00 00 1 1 1 1 1 1 1 1 Y2=A2 1 1 1 1 00 00 00 00 1 1 1 1 1 1 1 1 00 00 00 00 1 1 1 1 Y1 =A1 1 1 00 1 1 00 00 1 1 00 1 1 1 1 00 1 1 00 00 1 1 00 1 1 Yo=Ao 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
0025-6
Address to XY Key
Ao
Yo
8-100
256K
X28256 Product Bit Map Electrically Erasable PROM
32K x 8 Bit
~~84 :173~\11~~~~ ----r---1
000000000 000000001 000000010 000000011
,I
l/Oo
1/01
1/02
1/03
1COLUMNS 1COLUMNS 1COLUMNS 1COLUMNS I
:(64 COLs):(64 COLs):(64 COLS):(64 COLS):
BINARY
(512 ROWS)
�
' 1/04
I/Os
I/Os ' 1/07 '
1COLUMNS1COLUMNS1COLUMNS1COLUMNS1
:(64 COLs):(64 COLs):(64 COLs):(64 COLS):
111 1111 00 111111101 11111111 0 111111111
Y5 =As 00 00 00 00 )
Y4=A4 00 00 00 00
Y3=A3 00 0 0 00 00
Y2 =A2 00 00 1 1 1 1) Y1 =A1 00 1 1 00 1 1 )
l Yo=Ao 0 1 0 1 0 1 0 1
BINARY (64 COLUMNS)
L_ 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
2 1 1 1 1 1 1 1 1
) 00 00 1 1 1 1 ) 0 0 1 100 1 1
l 0 10 10 10 1
Address to XY Key A14 A13 A12 A11 A10 Ag As A? As As A4 A3 A2 A1 Ao Xs X7 Xs X5 X4 X3 X2 X1 Xo Y5 Y4 Y3 Y2 Y1 Yo
8-101
0025-7
NOTES
8-102
RR-502A NOVRAM* Reliability Report .....
RR-504 Endurance of Xicor E2PROMs and NOVRAMs* ................. .
RR-505 X2816A/X2804A Reliability Report
RR-506A Byte-Wide NOVRAM* (X2001 I X2004) Reliability Report . . . . . .
RR-507A X2864A Reliability Report ....... .
RR-508 X2404 Reliability Report ........ .
RR-509 X2816B Reliability Report........
RR-511 X28C64/X28C256 Reliability Report . . . . . . . . . . . . . . . . . . . . . .
RR-513 X28256 Reliability Report... . . . . .
RR-515 Data Retention in Xicor E2PROM Memory Arrays .............. .
RR-516 Latch-Up Considerations in Xicor CMOS Processes . . . . . . . . . . . . .
RR-518 X24C01 Reliability Report. . . . . . . .
Determining System Reliability from E2PROM Endurance Data . . . . . . . . . . . . . . . . . . . . . . . .
Radiation-Induced Soft Errors and Floating Gate Memories . . . . . . . . . . . . . . . . . . . . . . . . .
Endurance Model for Textured Poly Floating Gate Memories . . . . . . . . . . . . . . . . . . . . . . . . .
The Prediction of Textured Poly Floating Gate Memory Endurance . . . . . . . . . . . . . . . . . . . . .
Comparison and Trends in Today's Dominant E2 Technologies . . . . . . . . . . . . . . . . . . . . . . . .
New Ultra-High Density Textured Poly-Si Floating Gate E2PROM Cell . . . . . . . . . . . . . .
Reliability Comparison of Flotox and Textured Poly E2PR0Ms . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
9-23 9-33
9-45 9-59 9-73 9-81
9-89 9-101
9-109
9-113 9-123
9-131
9-135
9-141
9-14 7
9-155
9-161
9-163
.il:I'
NOVRAM * Data Sheets
Serial Products Data Sheets
E2PROM Data Sheets
E2POTTM Data Sheets Microcontroller Peripheral Products Memory Subsystems
Die Products
Application Notes and Briefs Product and Technology Reliability Reports
RR-502A
liCI'
0075-1
NOVRAM* RELIABILITY
REPORT
By John Caywood and Reliability Engineering Staff
*NOVRAM is Xicor's nonvolatile static RAM device. 9-1
INTRODUCTION
This report is an accumulation of reliability testing data taken on the Xicor X221 O and X2212 NOVRAM memories. In these memories, each memory bit integrates one bit of static RAM and one bit of electrically erasable-programmable ROM (E2PROM) into one cell. The controls STORE and RECALL cause the data to be transferred in parallel from all RAM bits into the associated E2PROM bits and back again. These devices, which exemplify
Xicor's innovative technology, require only a 5V power supply and TTL level signals for all operations, including STORE and RECALL. Both devices employ the same design and processes and are organized 64 x 4 and 256 x 4 for the X221 O and X2212, respectively. Figure 1 shows the pinout for the two parts, as well as for the X2201 A (1 K x 1) NOVRAM. Figure 2 shows the logic diagram. The bit maps for the three devices shown in Figures 3-5 illustrate the physical location of the various address bits.
Ao A1 A2 A, A., Dau1 STORE
WE
Vss
Vee
NC
As
Ao
A,
Ar
Az
Ao
A1
Ao
o,.
AmmimlY
Cs
Ao
Cs
Vss STORE
Vee
A1
NC
A.,
As
A,
110.
Az
110,
A1
110,
Ao
Cs
WE
Vss
mm 10 ARRAY
PIN NAMES
Ao-Ag
1/01-1/04 WE
cs
ARRAY RECALL STORE
Vee Vss NC
Address Inputs Data Input/Output Write Enable Chip Select Array Recall Store +5V Ground No Connect
Figure 1: X2201A, X2210, and X2212 pin assignment drawings.
Vee Ae As 110, 110, 110. 1101
WE
ARRAY
RECAiI
0075-2
9-2
ROW SELECT
STORE
ARRAY RECALL
E---- CONTROL LOGIC IINPUT DATA .
CONTR~
COLUMN l/OCIRCUITS
+-Vee +-Vss
Figure 2: Functional diagram of X2212 memory.
0075-3
9-3
X4 X3 X2 X1 Xo
Ao A1 A2 ~As
0 0 0 0 0
0 0 0 0
0 0 0
0
0 0 0 1 1
0 0
0 0
00 0
00 110
0 0 1 1 1
0
0 0 0
0
0 0 1
0
0
0
0
0
1
0
0 0
0
0 1
0
0
0 1 1 1 1
0 0 0 0
0 0 0
0 0
0
0 0 1 1
0
0 0
0 01
0
0
0
1
0 0 0
0 0
0
0
0
1
1 0 0
0
0
010 10 10 10 1010 10 1 00 1100 1100 1100 11 000011110000 1111 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Each square equals one bit.
Figure 3: X2201A physical address map.
Yo= As Y1 = A4 Y2 = A1 Y3 = Aa Y4 =Ag
0 10 10 10 10 10 10 10 0 0 1100 1100 1100 1 00 00 11110000 111 00 0 00 00 0 1 11 1111 11111111111 1111
1/0
1/0
X2 X1 Xo 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 A4A3A5 3 4 3 4 3 4 3 4 3 4 3 4 3 4 3 4
l---l---l---+--+--+----l---+---l-+---1---1---+--+--+----l---I 0 0 0 l---l---+--+--+--+----l---+---lf--1---1---+--+--+--+---+---I
1---1---1---+--+--+----l---+---l-+---l---+--+--+--+--+--I 0 0 1 1--+--+--+--+--+--+--t---lf--t--+--+--+--+--+--+--t
t--+-+--+--t--+--+--+----1~r--+-+--+--t--+--+--10
oi--+-+--t--+--+--+--+----1r-t--+-+--t--+--+--+---1
1---1---1---+--+--+----1---+---1-1---1---1---+--+--+----1---10
11---1---+--+--+--+----1---+---1f--+---l---+--+--+--+---+---1
0 0 1---1---+--+--+--+----l---+---lf--+---l---+--+--+--+--+---I 0
0
1
0
1
0
1
0 Yo= A2
1
0
0
1
1
0
0 Y1 = A1
1
1
1
0
0
0
0 Y2 =Ao
Each square equals one bit.
Figure 4: X2210 physical address map.
9-4
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1/0
1/0
0 10 1010 100 1100 1 1 1 0 0 0 0 Each square equals one bit.
Figure 5: X2212 physical address map.
Yo= A2 Y1 =A1
Y2 =Ao
0 10 1010 100 110 0 1 1 1 0 0 0 0
9-5
TECHNOLOGY
Xicor NOVRAM memories store their nonvolatile data on electrically isolated polysilicon gates. These gates are islands of polysilicon surrounded by about
aooA of Si02, one of the best insulators known.
This is similar to the structure used in UV light erasable PROMs (UVEPROMs).
Electrons once trapped on the floating (isolated) gates will remain there unless they receive a large energy input from an outside source (e.g., an ultraviolet photon in the case of UVEPROMs), or until a sufficiently high electric field is applied to distort the energy bands sufficiently to allow Fowler-Nordheim tunneling to occur.1
Fowler-Nordheim tunneling, which will be discussed in more detail later in this report, is the mechanism employed to charge and discharge the floating storage gate of Xicor's NOVRAM memories. The storage gate is formed in the second of three layers of polysilicon as illustrated in Figure 6. Electrons move to the floating gate by tunneling from POLY 1 to POLY 2. When the high fields which are used to cause the desired tunneling are not present, the electrons remain trapped on POLY 2.
As Figure 6 illustrates, the NOVRAM memory cell is a conventional six transistor static RAM cell to which a floating gate E2PROM cell containing two transistors has been added. During the normal READ/WRITE operations, memory array power supply (VccA) is fixed at the positive supply level (nominally 5V) and the Internal Store Voltage is fixed at ground. Only the six transistors of the static
VccA
RAM cell are effective and the operation is exactly that of a conventional six transistor static RAM.
The RECALL operation depends on capacitance ratios. The value of C2 in Figure 6 is larger than that of C1. When the external RECALL command is received, the memory array power supply (VccA) is initially pulled low to equalize the voltages on nodes N1 and N2. These nodes equalize quickly to VccA through the depletion transistors 01 and 0 2. When VccA is then allowed to rise, the node with the lighter capacitive loading will rise more quickly and turn on the pull down transistor on the opposing side, which will keep the more slowly rising node clamped low. If the floating gate is charged positively, Os is
c turned on, which connects C2 to N2. Thus N1, which
is loaded by the smaller capacitor 1, rises more rapidly, causing the latch to set with N1 high and N2 low. If the floating gate is charged negatively, Os is turned off, which isolates C2 from N2 and allows N2 to rise more rapidly than N1. Thus the latch is set with N2 high and N1 low. During the RECALL operation the Internal Store Voltage remains at ground.
The STORE operation also utilizes capacitance differences to transfer data from RAM to E2PROM. When node N1 is low, transistor 0 7 is turned off. This allows the junction between capacitors CC2 and CC3 to float. Since the combined capacitance of CC2 and CC3 is larger than that of Cp. the capacitor between POLY 1 and POLY 2, the floating gate follows the potential of the Internal Store Voltage. Thus when the Internal Store Voltage becomes high (several times Vee), a sufficient field exists between POLY 1 and POLY 2 to cause electron tunneling and the floating gate is charged negatively.
INTERNAL STORE VOLTAGE
_r I ::L.
CC3r cJ.
01
:~1::C~e I
C,~
~C2
0075-7 Figure 6: Schematic diagram of an NOVRAM memory cell showing how a standard six-transistor static RAM cell is merged with a floating gate �2PR0Mcel/.
9-6
When node N1 is high, transistor 07 is turned on
which grounds the junction between CC2 and CC3. Since the capacitance of CC2 is larger than that of CE, the capacitor formed between POLY 2 and POLY 3, CC2 holds the floating gate near ground when the Internal Store Voltage goes high. In this case the high field exists between POLY 2 and POLY 3 and electrons tunnel from POLY 2 to POLY 3, which discharges the floating gate.
The Internal Store Voltage is at ground except during the STORE operation. Moreover, during the STORE operation all bits are stored simultaneously, which is possible because the RAM bit associated with each E2PROM bit acts as a data latch.
TUNNELING PHYSICS
Because the innovative aspects of NOVRAM and E2PROM memories revolve around the nonvolatile storage procedure, it seems appropriate to discuss the storage phenomenon in more detail. As mentioned previously, the storage occurs via a tunneling mechanism first described by Fowler and Nordheim in 1928 and subsequently named after them.1 The basic idea is illustrated in Figure 7. The energy difference between the conduction and valence bands in Si is about 1.1 eV; the energy difference between those bands in Si02, is approximately 9eV. When the two materials are joined, the conduction band in Si02 is 3.25eV above that in Si. The differences in valence band energies is even larger (approximately 4eV). Since the thermal energy of an electron averages only 0.025eV at room temperature, the chances of an electron in silicon gaining enough thermal energy to surmount the barrier and enter the conduction band in Si02 is exceedingly small. This case is illustrated in Figure 7.
Si
SIO,
T
3.25eV
J_ e e e CONDUCTION BAND
Si
sio,
4.7eV
J_
0075-8
Figure 7: Energy band diagrams of the Si/Si02 system in the neutral state {a), and during the store operation {b).
Fowler and Nordheim pointed out that in the presence of a high electric field, the energy bands will be distorted as illustrated in Figure 7b. Under these conditions there is a small but finite probability that an electron in the conduction band in the silicon will tunnel through the energy barrier and emerge in the conduction band of the Si02, as illustrated in Figure 7a.
Fowler-Nordheim emission was observed early in this century for the case of electrons being emitted from metals into vacuum, and in 1969 Lenzlinger and Snow observed this phenomenon for the SiSi02 system.2 The Fowler-Nordheim current increases exponentially with applied field and becomes readily observable (i.e., J - 10-6 A/cm2) for the Si-Si02 system in which the Si surface is smooth for fields on the order of 1O MVI cm.
It has been known for some time that "enhanced" electron emission currents could be observed for Si-Si02 systems for which the Si surface has a texture. (Texture in this context means that the Si surface has features on the order of a few hundred angstroms.)3-5 These enhanced currents occur at applied fields with values smaller than one quarter of those necessary for the same current from a smooth surface. It has been thought that the enhanced emission occurs because of locally enhanced fields near the top regions of the features on the surface.
Lewis attempted to model Fowler-Nordheim tunneling from a textured surface by calculating current from a number of hemispheres set in a plane.6 Attempts to quantitatively fit experimentally observed currents with this model have not been very successful. Hu, et al, for example, found that to fit their data to existing theory it was necessary to assume an energy barrier of approximately 1eV between conduction bands in Si and Si02.7 Even with this assumption, the fit was poor because the measured current increased more rapidly than the calculated values, as is illustrated in Figure 8.
Because of the importance of tunneling to the operation of its products, Xicor decided to adequately characterize and model tunnel emission from textured polycrystalline silicon (poly) surfaces. One avenue of exploration was to characterize the physical topology of the tunneling structure. Figure 9 is a scanning electron micrograph (SEM) of the emitting (top) surface of a layer of polysilicon from which the oxide has been removed for clarity. As shown in the micrograph, this surface is composed of a densely packed array of features reminiscent of a cobblestone street. A count of these features on SEM photos of material from several lots determined that
9-7
there is an average of about 50 features per square micron. A transmission electron microscope (TEM) cross-section of a tunneling structure is shown in Figure 10. This photo demonstrates the conformal nature of the structure. The top surface of the prior deposition of polysilicon is formed into a series of "hillocks" 200-300A high and 1000-1500A across the base. The free surface of the oxide grown on this silicon replicates the silicon surface. Thus, polysilicon deposited atop the prior polysilicon layer subsequent to oxidation has dimples on its undersurface occurring over the already existing "hillocks".
The topology of the polysilicon surfaces causes the electric field lines to no longer be parallel as in the case of parallel emitting and collecting surfaces, but rather to diverge and converge in response to the local topology as is illustrated in Figure 11. As shown, the field lines converge near surfaces of positive curvature (i.e., bumps) and diverge near surfaces of negative curvature (i.e., dimples). Since Fowler-Nordheim tunneling depends exponentially on the electric field at the surface of the polysilicon, a good model of the electron emission requires an accurate knowledge of the field over the complete surface.
10-3 . - - - - - - - - - - - - - - - - - - - - ,
10-4
0075-10 Figure 9: Scanning electron microscope (SEM) photograph of top emitting textured poly surface with oxide removed. The 0.5 �-long bar gives the scale.
10-s
10-6
N' E 10-1
~...
10-8
10-s
10-10
"""CALCULATED POINTS <l>e=0.9eV
TAKEN FROM: HU ET AL (1979)
10-11 L---L-__._ ____.__ ___.__ __ . __ ___.__ ____,
13
14
15
16
17
18
19
VA(VOLTS)
0075-9
Figure 8: Current vs. applied voltage for current from textured poly surface
emitted through 1760A of thermal Si02 compared with calculations based on previously available theory.
0075-1 Figure 10: Transmission electron microscope (TEM) photograph of a cross-section through a textured tunneling structure. The one micron-long arrow shows the scale.
9-8
Si
I I I I
I I I
I I
I
I
I
I I
I I
: I
I
I
I
I
I
I
I
I
I
I
Si
0075-11 Figure 11: Sketch illustrating the manner in which field lines converge near convex feature and diverge near concave feature.
Until recently, this field problem was one of the
unsolved problems of mathematical physics. (It is
classically known as the "lightning rod problem".)
Roger Ellis, a member of the Xicor staff, has solved this problem.a The technique used differential ge-
ometry to transform Euclidean space into a space in which the field lines were parallel. The electrostatics
problem was solved in this space and the solution transformed back into the original space. The tunnel
current was found to be described in a spherical co-
ordinate system by the equation:
[ J J ] - q3 E-2 exp {-4(2m)112<f>83t2} ds ] em.itt.ing
_ s 8?Th<f>s
3hqE
(1)
Jcollecting -
[
s ds collecting
where the electric field, E, is given by
]% E
=
~(S2
)
VA
-
~(S1)
[
(dd�r2)
+
1
;:2
d~
d�
(2)
and
~ =~ detcei>
1~1 d�
d�
is the curvature of the surface at which the field is
evaluated. 9
This expression has several interesting proper-
ties. One is that the field depends on the difference
of the curvatures of the emitting and collecting sur-
faces. Another is that the electric field also depends
on the derivative of the curvature of the emitting
surface.
To verify the accuracy of this expression, the cur-
rent-voltage (J-V) characteristics of a textured poly-
silicon tunnel structure were experimentally deter-
mined and compared with those predicted by equa-
tion (1 ). Because of the field enhancement on the
bumps, a higher current is expected at a given ap-
plied voltage polarity which causes electron emis-
sion from the bumps than for that polarity which
causes emission from the dimples. Thus, by analogy with a diode, the polarity with the bumps negative (higher current emitted) is called the forward bias direction and the other polarity is called the reverse bias direction.
Figure 12 shows the results of comparing experimental and calculated values for the forward bias condition. As can be seen, theory and experiment agree within about 20% over seven orders of magnitude in current. The parameters used in calculating the predicted currents were not arbitrarily chosen. The value of the oxide/silicon conduction band barrier, <f>s, was taken to be 3.15eV as measured by Weinberg.10 The feature density (50�)2 and the bump base and height are typical of those seen on SEMs and TEMs such as Figures 9 and 10, respectively. The dashed line in Figure 12 is the current which would be predicted if the top (i.e., collecting) electrode were flat rather than dimpled. This illustrates the effect of the collecting surface curvature on the field at the emitting surface.
OMEASURED POINTS 6
~ 7
~
.... 8
faf:i
� 9
0
g 10 I 11
12
COLLECTING
j_ SURFACE
T 9
90A
......------. ~
_i. EMITTING SURFACE
3601
T
~s 1
i- 14001--i
17 19 21 23 25 APPLIED VOLTAGE (VOLTS)
0075-12 Figure 12: Forward tunneling characteristic comparing the measured data with curves calculated for a concave and a planar collecting surface.
To further verify equation (1), the reverse bias current was measured on the same device used for the forward bias case. The results are compared with the predicted current in Figure 13. This shows about 20% agreement over eight orders of magnitude in current with the same parameters used as in calculating the forward bias case. Clearly, the model does an excellent job of predicting the measured current.
9-9
- - CALCULATED� ,,,,,.$iPLANAR_,,
I
6
I
I
I
en
Q.
:sE. 8
aaIzw-:: 9
:::>
(.)
CJ 10 0
..J I
11
I
I
I
I I
OMEASURED POINTS
NUMBER: 50/~
lox:
1000
-e=
3.15eV
COLLECTING
_i
SURFACE
90A T ........-----.. ~
i EMITTING SURFACE
12
360l ~
T i-1400l-i s,
13_ _ _ _ __.__ _ ..__~
30
32
34
36
APPLIED VOLTAGE (VOLTS)
0075-13
Figure 13: Reverse tunneling characteristic comparing the measured data
with curves calculated for a concave and planar emitting surface.
Several points of interest can be observed in Figure 13. One point is that at a voltage at which the forward current is saturating (25V), the reverse current is unobservable (extrapolation of the measured current predicts ~ 10 - 27A). Another point is that the current emission predicted from a flat top surface is greater than that predicted from a dimpled top surface. Moreover, the current emitted from a flat top surface decreases more slowly with decreasing voltage than that from a dimpled flat surface. This latter fact is important for data retention as will be discussed in the next section.
In summary, Xicor is able to accurately model the tunnel current emitted from textured poly surfaces through Si02 layers. The magnitude of the tunnel current as well as its voltage dependence are dependent upon the surface topology. Thus, we have the means to optimize the emission characteristics. Lastly, the asymmetric nature of the tunnel emission makes possible cell designs which are better adapted to particular requirements than is possible with symmetric tunnel characteristics-just as a diode offers more design possibilities than does a resistor.
DATA RETENTION
As was suggested in the previous. section, textured poly tunneling structures have a significant advantage in data retention, in comparison with those employing flat surfaces and thin oxides. One basis
for this advantage is illustrated in Figure 14, in which the current-voltage (J-V) characteristics of a tunneling device which employs a thin oxide between planar surfaces is compared with a tunneling device which employs a thick oxide between textured silicon surfaces. For this comparison we match the currents in the high current region since most memories are designed to program in about the same time period ( ~ 1O ms). As can be seen, the same current can be obtained from a smooth surface with 125A thick tunnel oxide or from a textured surface with an 825A thick tunnel oxide. Note however, that at lower values of applied voltage typical of read and storage conditions, the current emitted from a textured surface is approximately four orders of magnitude lower than that from a smooth surface.
These differences may become even more significant as devices are scaled. It is clear that, in order to scale the memory properly, lower programming voltages are needed so that the isolation widths and device channel lengths can be reduced both in the memory array and in the peripheral circuitry. However, for a typical part which stores data in 3 ms and must retain it for 1O years, the tunneling current under storage and reading conditions must be at least 1011 times smaller than under programming conditions because the retention time is 1011 times
10-6
10-a
5N' 10-10
l
s 10-12
i 1Q-14
10-16
10-1a
"TEXTURED SURFACE
lox=
e2sl
BASE: 600l
HEIGHT: 300l
NUMBER: 70/�2
11
13
15
17
19
21
0075-14 Figure 14: Comparison of calculated tunneling J-V curves for emission from a planar and a textured structure. The devices were designed to have the same emission in the high current regime where programming takes place.
9-10
longer than the storage time. Actually, for a margin, one would design for a difference in currents of 1013 to 1Q14. For planar surface tunneling structures, this may be a difficult design constraint because the slope of the J-V curve is fixed, which means that the maximum allowed read voltage drops with the programming voltage on a volt-forvolt basis, not proportionately. On the other hand, textured surface tunneling structures, in their current manifestation, have a steeper J-V characteristic than planar ones and the J-V characteristic of a textured structure can be tailored to yield a steeper curve if desired. This means that for a given maximum read voltage, a textured structure requires a lower programming voltage which leads to better scaling.
To verify the excellent data retention expected of Xicor NOVRAMs, a study was carried out to measure data loss as a function of temperature. Figure 15 shows log cumulative data loss vs. log time for 100 samples of X221 O's at each of three temperatures. Data loss is defined as occurring when the first bit in the array loses data. As shown in Figure 15, high temperatures were required to obtain appreciable data loss in experimentally useful times. Note that even at 300�C, 2000 hours ( - 3 months) are required to begin to see data loss. Figure 16 shows the result of calculating failure rates based on these results and plotting vs. inverse temperature. Since the rates fall in a straight line, we can extract an activation energy and extrapolate to lower temperatures (see the next section for a discussion of activation energies). The result is that the experimental value of the activation energy is 1.7eV and the mean time for data loss for this mechanism (which we believe to be the fundamental loss mechanism for this technology) is 3 million years for data retention at 125�C.
104
32s�c
EA=1.7eV
3x106 YEARS AT 12s�c 10 20 30 40 50 60 70 80 90 95
% CUMULATIVE FAILURES
0075-15
Figure 15: Log cumulative data loss vs. log time for three storage
temperatures on samples of 100 X2210's. Data loss is defined to occur
when the first bit in an array loses data.
~
J: 20
0
o0 . ~ g:s 10 w ~ a: w
~ 5
...I
~
2
EA=1.7 � 0.1eV
MTBF = 3,000,000 YEARS AT 125�C
250�
300� 350� 400� TEMPERATURE (�C)
0075-16 Figure 16: Log data loss rate vs. inverse temperature for X2210's.
ENDURANCE
The endurance of Xicor NOVRAMs is monitored on a regular basis. Figure 17 shows typical endurance data on 100 units of X2212 from five endurance monitor lots plotted on an extreme value distribution. All of the units tested exceeded the 1,000 data changes/bit limit specified for this device.
'' ''
' '
1M :: ::::: ~:;:::::::::: ::: ~::::::::::::::::::::::::::::: :~::::::::::
1:-
-:::-:i-
:
~
.:t::
-~ -~
1:;:: -----
:
-
:: --
:-::-:;:-:-.
:
-
c:
--
:
-
:::::::: ---- -- -
:
-
:
-
:
-
:::::: - ----
: -
:::::::: ---- -- -
:
-
: :-
c
-
:
-
:
-
::::::: ------
:
-
I- _l_I_ j"-j � ;- - - - -- -- -,-,- - � � -- - - -- -- -- - -- � � -- -- -.- -.--.-- � � -�- - - �-
:::::::;:;:;:::::::::::J;L~~~~~~:~: ~::::::: :; ::::::::::
: ::: : : LLLLuJ.u.LL;", TYPE X2212
:
: : : : : : ~ 1OOK :: ::::: ~: :,7:::::: ::: ~:: :C::::::::::::::::::::::::::~::::::::::
~
~~= ~:::::::: ~:::::::::::::::::::::::::::::: ~::::::::::
,--,-,-,-i-i�--------,-,-------------------------------.-----------
:- -:- ;- ;- - -:�:�~
-------
' '~ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -'~ - - - - - - - - - -
''
'
1OK :: ::::: ~: ~:;::::: : : ::: ~::::::::::::::::::::::::::::: :~::::::::::
:~? :~ ~ l~ l~ ~ ~ ~ ~ ~~fl~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~:~~~~~~~~~~~
'-�'-'-L-1.-1.----- ---�-L----------------��-------------'-----------
:- -:-:- -:- 1 10 I! I
It
I
~ - ~ - ~ - - - - - - - :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -:- - - - - - - - - - -
'' ''
' '
1K.1 I 1 I 5 I 37 157
99
.5 2 10
50
CUMULATIVE PERCENT
Figure 17: Extreme value distribution plot of X2212.
0075-20
9-11
BASIC RELIABILITY CONCEPTS
There are several concepts basic to most reliability work. One is the long established observation that failure rates follow the bathtub-shaped curve illustrated in Figure 18. There is an infant mortality region characterized by a rapidly declining failure rate as the "weak" parts are eliminated from the population, a random failure characterized by an invariant or slowly declining failure rate, and a wearout region characterized by an increasing failure rate as the units reach the end of life.
elevated temperature where they are high enough to be conveniently measured and extrapolated back to lower operating temperatures where the failure rates may be so low as to require an inconveniently large number of device� hours to measure. The relationship which allows one to translate failure rates from one temperature to �another is known as the Arrhenius relation. Figure 19 illustrates this relation for a number of common values of activation energy.
INFANT MORTALITY
FAILURE RATE
RANDOM FAILURES
WEAROUT
LOG TIME
0075-17 Figure 18: Illustration of bathtub curve of failure rates showing regions in which infant mortality, random failures, and wearout mechanisms dominate the failure rate.
Each region of the failure rate curve has specific failure modes which predominate. For example, the infant mortality region is dominated by failures which arise from manufacturing defects. Table I gives a summary of common failure mechanisms and stresses which may be used to accelerate the failure rates of the various mechanisms which have been culled from the literature.11-14
The classic parameter used to accelerate failure rates is temperature. It is known that a very broad class of failure mechanisms have a temperature dependence proportional to exp (- Ea/kT) where Ea is called the activation energy, k is Boltzmann's constant, and T is the absolute temperature. This is true because a number of basic physical phenomena such as diffusion rates and chemical reaction rates have this dependence: The. significance of this is that if the activation energy is known for the failure mechanisms in question, then the failure rates arising from these mechanisms can be measured at
a:
.0...
~u;; z
0
Ei
.aw..:.
w
(.) 10-3
~
10-2
10
250 200 150
100
50
25
TEMPERATURE (�C)
0075-18 Figure 19: Acceleration factor vs. temperature calculated for various activation energies from Arrhenius relation.
RELIABILITY TESTING
Five types of tests were conducted to establish the reliability of the devices:
1) High temperature dynamic lifetest. 2) Data retention bake. 3) High temperature reverse bias. 4) Lifetest monitor. 5) Environmental.
These tests are discussed after Table I.
9-12
Failure Mechanism
Type
Activation Energy
Detection Method
Ionic
Infant/
Contamination Random/
Wearout
1.0eV
High Temp. Bias
Surface Charge
Wearout 0.5-1.0eV High Temp. Bias
Polarization Wearout 1.0eV
High Temp. Bias
Electromigration
Wearout
1.0eV High Temp. Operating Life
Microcracks Random
-
Temperature Cycling
Oxide Rupture
Infant/ Random
0.3eV High Temp. Operating Life
Silicon Defects
Infant/ Random
0.3eV
High Temp. Bias
Oxide Defect Infant/ Leakage Random
0.6eV High Temp. Operating Life
Electron Wearout
-
Trapping In
Oxide
Table I: MOS failure mechanisms.
Low Temp., High Voltage Operating Life
High Temperature Dynamic Lifetest
This is the usual data from which failure rate predictions are made. For this to be a valid predictor of failure rate, the parts must function as they would in normal operation. Thus, overly elevated temperatures at which the unit does not function internally are to be avoided since this may lead to overly optimistic predictions.
Xicor gathers this data at 125�C ambient which is within the known operating range of the units under test. The stimulus pattern consists of recalling a known pattern, writing an all one's pattern over the recalled pattern bit by bit, reading the all one's pattern, writing its complement, reading the complement and then beginning over again.
The units in lifetest are tested at 168, 500, 1000, and 2000 hours to verify that they are still within specification. The first step of the readout tests is to recall the information stored in the nonvolatile section of memory to verify that the previously stored pattern is still retained. If so, the memory is completely exercised over voltage including verification of the STORE function. Finally, the predetermined pattern is restored to memory for the next lifetest period.
Data Retention Bake
This test is sometimes referred to as a storage bake. The term "data retention bake" better describes the principal function it serves in the case of electrically programmable nonvolatile memories which is to measure how fast charge leaks away from the floating gate.
In this test, a pattern which represents all floating gates charged positive is stored and the devices are baked at 250�C for the cerdip (ceramic dual-in-line) package and 150�C for plastic (dual-in-line) package with no bias applied. At intervals the memory is removed from bake, and the nonvolatile data recalled and checked for accuracy. The data is not restored at readouts in order to ascertain the worst case retention. Since Xicor warrants cycling endurance of various values, this test was performed on parts specified for 1000 cycle endurance which had performed 1000 complete data alterations, as well as on parts which had not received this treatment.
HTRB
HTRB stands for High Temperature Reverse Bias, a term which originated with bipolar circuits, in which case the test reverse biased the junctions of all of the input stages. For MOS circuits, a better term would be high temperature static bias. In this
stress, which Xicor carries out at 150�C, Vss is
grounded and a static positive voltage is applied to
all of the inputs and outputs, as well as to Vee. This
has the effect of applying a static bias equal to the power supply across the gate oxides of the circuit transistors. This stress is intended to expose failures which might occur as a result of drift of mobile ionic contaminants or latent defects in the gate oxides.
9-13
It is known that many defects are accelerated by voltage as well as temperature. For example, it has been shown by Crook that the failure rate of oxide defects increases 107 times per MV/cm increase in the electric field.15 For this reason, HTRB stresses were conducted with both 5.5V and 7.5V bias applied to the units under test.
Lifetest Monitor
In order to assure a continuous supply of the highest quality and reliability possible to our customers, a weekly lifetest monitor is maintained.
This monitor is used at Xicor for two purposes. First, it is used to monitor the infant mortality rate which is an indicator of manufacturing defects. If an unusually high failure rate were to be observed, a corrective action could be taken before defective units are shipped to customers. Secondly, a long term failure rate is also monitored. This establishes a way to ensure that long term reliability is maintained.
Each week approximately 250 units of X2212 devices are placed in a dynamic lifetest at 125�C for 168 hours. Also, monitor units of the first week of each period remain in dynamic lifetest for up to 1000 �hours.
Package Environmental Tests
MIL-M-35810 and MIL-STD-883, Method 5005, Group C and D have been the guide for environmental testing for the cerdip package. Table II lists
the tests, the test conditions and test results. All lots passed the 883 qualification criteria.
Because of the nature of the plastic package, additional tests were done. These tests are 85�C/85% RH (both biased and unbiased) lifetest, temp cycling (200 cycles) and saturated storage test at 2 ATM (autoclave).
RESULTS
Tables IIIA and 111 B exhibit the results of dynamic lifetest of X221 O and X2212 in cerdip package and plastic package, respectively. Table lllA shows ze.ro failure result in 6 x 105 device hours on 1700 units of X221 O and X2212. Table 1118 shows two failure
results in 1.7 x 106 device hours on 5055 units of
X221 o and X2212. The causes of the failures were
also listed in Table 1118. In addition, Table 1118 includes lifetest monitor data since plastic units are used.
Tables IVA and IVB show the results of 150�C static lifetest at 5.5V for cerdip and plastic. No failures were detected on both package types, out of 121 units for cerdip and 245 units for plastic.
Tables VA and VB show the results of 150�C static lifetest at 7.5V applied bias. Increasing Vee from 5.5V to 7.5V increases the field across the gate ox-
ide from 6.875 x 105 V/cm to 9.375 x 105 Vlcm.
According to Crook this increase in field should accelerate the failure rate by about 56 times. In cerdip, one failure was observed at the 48 hour readout. For oxide breakdown, out of 250 units tested in plastic, no failures were seen.
9-14
Test Temp. Cycling
MIL-STD-883 Test Method
1005
Constant Acceleration
2001
Seal -Fine -Gross
Lead Integrity
1014 2004
Seal -Fine -Gross
Thermal Shock
1014 1011
Temp. Cycling
1010
Moisture Resistance
Seal -Fine -Gross
Internal Water Vapor Content
Mechanical Shock
1004 1014
1018 2002
Vibration Variable Frequency
Constant Acceleration
Seal -Fine -Gross
Salt Atmosphere
Seal -Fine -Gross
Adhesion of Lead Finish
2007 2001 1014
1009 1014
2025
Lid Torque
2024
Table II: Environmental test for 18-lead cerdip package.
Conditions
Test Condition C
(10 cycle, -65�C to + 125�C}
Test Condition E (30,000g, Y1 axis only) Test Condition B
(5 x 10-s cc/min)
Test Condition C Test Condition 82 (Lead Fatigue)
Test Condition B Test Condition C Test Condition B
(15 cycles, -55�C to + 125�C}
Test Condition C (100 cycles)
Test Condition B Test Condition C 5,000 ppm max. water content at 100�C Test Condition B (1500g peak, 3 axis) Test Condition A (20g peak, 3 axis) Test Condition E
Test Condition B Test Condition C Test Condition A
Test Condition B Test Condition C
LTPD 15
15 15
-
15
15 15
-
Accept #
0/15
0/15
0/15
0/3 or1/5 0/15
0/15
0/15 (#of leads from 3 devices)
0/5
Results 0/175
0/175
0/175 0/175 0/213
0/213 1/213 0/203
0/203
0/203
0/203 0/203
016
0/192
0/192
0/192
0/192 0/192 0/144
0/144 0/144 0/18
0/15
9-15
Lot#
48 Hrs.
# Fail
#In
168 Hrs.
# Fail
#In
1 (2212)
0
403
0
383
2 (2212)
0
350
0
324
3 (2212)
0
338
0
334
4 (2210)
0
294
0
284
5 (2210)
0
315
0
312
Totals
0
1700
0
1637
Table lllA: Stress dynamic lifetest at 125'C--Cerdip package.
500 Hrs.
# Fail
#In
0
99
0
99
0
99
0
99
0
99
0
495
1000 Hrs.
# Fail
#In
0
97
0
98
0
98
0
97
0
98
0
488
Total Hours
1.3 x 105 1.2 x 105 1.2 x 105 1.2 x 105 1.2 x 105 6.0 x 105
Lot#
48 Hrs. # Fail #In
168 Hrs. # Fail #In
1 (2212)
0
575
0
573
2 (2212)
2lal
570
0
565
3 (2212)
0
577
0
577
4 (2210)
0
573
0
570
5 (2212)
0
570
0
570
6 (Monit.)
0
2190
0
2183
Totals
2
5055
0
5038
[a) = one x-decoder failure due to blown oxide 0.3eV one word line failure due to blown oxide 0.3eV
Table 1118: Stress dynamic lifetest at 125'C-plastic package.
500 Hrs.
# Fail #In
0
99
0
99
0
99
0
99
0
99
0
297
0
792
1000 Hrs.
# Fail #In
0
97
0
98
0
96
0
99
0
99
0
297
0
786
2000 Hrs.
#Fail #In
0
97
0
98
0
96
0
98
0
98
--
0
487
Total Hours
2.5 x 105 2.5 x 105 2.5 x 105 2.5 x 105 2.5 x 105 5.1 x 105 1.7 x 106
Lot#
48 Hrs. # Fail #In
168 Hrs. #Fail #In
1 (2212)
0
25
0
23
2 (2212)
0
25
0
25
3 (2212)
0
25
0
23
4 (2210)
0
25
0
25
5 (2210)
0
25
0
25
Totals
0
125
0
121
Table IVA: Stress 5.5V HTRB at 150'C--Cerdip package.
500 Hrs.
#Fail #In
0
23
0
25
0
23
0
25
0
25
0
121
1000 Hrs.
#Fail #In
0
23
0
25
0
23
0
25
0
25
0
121
2000 Hrs.
#Fail #In
0
23
0
25
0
23
0
25
0
25
0
121
Total Hours
44896 48800 44896 48800 48800 2.4X 105
Lot#
48 Hrs.
#Fail
#In
168 Hrs.
# Fail
#In
500 Hrs.
# Fail
#In
1 (2212)
0
50
0
49
0
49
2 (2212)
0
50
0
50
0
50
3 (2212)
0
50
0
50
0
50
4 (2210)
0
50
0
50
0
50
5 (2212)
0
50
0
49
0
47
Totals
0
250
0
248
0
246
Table IVB: Stress 5.5V HTRB at 150'C-plastic package.
9-16
1000 Hrs.
# Fail
#In
0
49
0
49
0
50
0
50
0
47
0
245
Total Hours
46648 47100 47600 47600 44984
2.3 x 105
Lot#
48 Hrs.
# Fail
#In
168 Hrs.
#Fail
#In
1 (2212)
0
25
0
25
2 (2212)
1 [a]
25
0
24
3 (2212)
0
25
0
25
4 (2210)
0
25
0
25
5 (2210)
0
25
0
25
Totals
1
125
0
124
[a] = Blown oxide 0.3eV Table VA: Stress 1.SV HTRB at 15C!'C-plastic package.
500 Hrs.
# Fail
#In
0
25
0
24
0
25
0
25
0
25
0
124
1000 Hrs.
#Fail
#In
0
25
0
24
0
25
0
25
0
25
0
124
Total Hours
23800 22848 23800 23800 23800 1.2 x 105
Lot#
48 Hrs.
# Fail
#In
168 Hrs.
#Fail
#In
1 (2212)
0
50
0
48
2 (2212)
0
50
0
50
3 (2212)
0
50
0
50
4 (2210)
0
50
0
50
5 (2212)
0
50
0
48
Totals
0
250
0
246
Table VB: Stress 1.SV HTRB at 15C!'C-plastic package.
Tables VIA, VIB, VllA and VllB show the results of 250�C and 150�C retention bake for cerdip and plastic, respectively. Retention bake was done both before and after 1000 data change cycles on units that are rated for 1000 data change cycles. At 150�C no failures were detected before nor after 1000 data changes on a total of 125 units for 1000 hours. At 250�C, the data on uncycled devices shows 3 units failed from 250 units for 2000 hours. The data on cycled devices shows 4 units failed from 125 units for 2000 hours. These results do not have statistically significant difference in overall failure rate. Close examination shows a tendency for the cycled failures to be more scattered, while uncycled failures are more concentrated at 1000 and 2000 hour
500 Hrs.
# Fail
#In
0
48
0
50
0
50
0
50
0
48
0
246
1000 Hrs.
#Fail
#In
0
48
0
48
0
50
0
50
0
48
0
244
Total Hours
45696 46600 47600 47600 45696
2.3 x 105
readouts. This kind of data should not be surprising, as an oxide defect, which had been accelerated by the high electric field, became manifest during store operation. The retention failure rate for 1000 hours at 250�C is at the range of 1% to 2%, which is about half of that previously reported for EPROMs.16 Retention data reported for other E2PROM technologies would indicate that the present NOVRAM retention results are greatly superior.17
Tables VIII and IX represent 85/85 lifetest with and without voltage bias, respectively. As indicated by the data, no failures were observed in both the 5.5V biased and the unbiased groups for a total of
5 x 105 device hours.
Lot#
48 Hrs. # Fail #In
168 Hrs. # Fail #In
1 (2212) 0
50
0
50
2 (2212) 0
50
0
50
3 (2212) 0
50
0
50
4 (2210) 0
50
0
50
5 (2210) 0
50
0
50
Totals
0
250
0
250
Table VIA: Stress bake at 25C!'C-cerdip package.
500 Hrs.
# Fail #In
0
50
0
50
0
50
0
50
0
50
0
250
9-17
1000 Hrs.
#Fail #In
0
49
0
50
1
50
0
50
0
49
1
248
2000 Hrs.
# Fail #In
0
48
1
47
1
48
0
50
0
49
2
242
Total Hours
95100 94600 95600 97600 96100 4.8 x 105
Lot #
48 Hrs.
I
#Fail
#In
168 Hrs.
I
#Fail
#In
1 (2212)
0
25
0
25
2 (2212)
0
25
0
25
3 (2212)
0
25
0
25
4 (2210)
0
25
0
25
5 (2212)
0
25
0
25
Totals
0
125
0
Table VIB: Stress retention bake at 15(J'C-plastic package.
125
500 Hrs.
I
#Fail
#In
0
25
0
25
0
25
0
25
0
25
0
125
1000 Hrs.
#Fail
#In
0
25
0
25
0
25
0
25
0
25
0
125
Total Hours
23800 23800 23800 23800 23800 1.2 x 1Q5
Lot#
48 Hrs. #Fail #In
168 Hrs. # Fail #In
1 (2212) 0
25
0
25
2 (2212)
0
25
0
25
3 (2212)
1
25
0
24
4 (2210) 0
25
0
25
5 (2210) 0
25
0
25
Totals
1
125
0
124
Table VI/A: 25(J'C Retention bake-cycled cerdip unit.
500 Hrs.
#Fail #In
1
24
0
25
0
24
0
25
0
25
1
123
1000 Hrs.
# Fail #In
0
23
0
25
1
24
0
25
0
25
1
122
2000 Hrs.
# Fail #In
1
23
0
25
0
23
0
25
0
25
1
121
Total Hours
45468 48800 45848 48800 48800 2.4 x 1Q5
Lot#
48 Hrs.
# Fail
#In
168 Hrs.
# Fail
#In
1 (2212)
0
25
0
25
2 (2212)
0
25
0
25
3 (2212)
0
25
0
25
4 (2210)
0
25
0
25
5 (2212)
0
25
0
25
Totals
0
125
0
125
Table V/18: f5(J'C Retention bake-cycled plastic unit
500 Hrs.
# Fail
#In
0
25
0
25
0
25
0
25
0
25
0
125
1000 Hrs.
# Fail
#In
0
25
0
25
0
25
0
25
0
25
0
125
Total Hours
23800 23800 23800 23800 23800 1.2 x 105
Lot#
500 Hrs.
# Fail
#In
1 (2212)
0
50
2 (2212)
0
50
3 (2212)
0
50
4 (2210)
0
50
5 (2212)
0
50
Totals
0
250
Table VIII: Biased 85185-plastic units with Vee= 5V.
1000 Hrs.
#Fail
#In
0
50
0
50
0
50
0
50
0
50
0
250
Total Hours
41600 41600 41600 41600 41600
2.1 x 105
9-18
Lot#
500 Hrs. #Fail
1 (2212)
0
2 (2212)
0
3 (2212)
0
4 (2210)
0
5 (2212)
0
Totals
0
Table IX Biased 85185--plastic units with Vee= OV.
#In 50 50 50 50 50 250
1000 Hrs.
# Fail
#In
0
50
0
50
0
50
0
50
0
50
0
250
Total Hours
41600 41600 41600 41600 41600 2.1 x 1Q5
Lot#
1 (2212) 2 (2212) 3 (2212) 4 (2212) 5 (2210) Totals
Table X� Temperature cycles (method 1010)-plastic package.
# Fail 0 0 0 0 0 0
200Cycles
#In 50 50 50 50 50 250
Lot#
1 (2212) 2 (2212) 3 (2212) 4 (2210) 5 (2212)
48 Hrs.
#Fail
#In
0
25
0
25
0
25
0
25
0
25
168 Hrs.
# Fail
#In
0
25
0
25
0
25
0
25
0
25
Totals
0
125
0
Table XI: Dynamic life/est at 1fl'C-plastic packaged units.
125
Figure 20 shows a bar graph of the autoclave results for plastic package. Cumulative failures steadily increased for the first 400 hours with sharp increase at approximately 500 hours. Figure 20 shows the 500 hour mark for the plastic package in the 24 % range. The discrepancy between autoclave and 85�C/85% RH lifetest results can be explained by the two causes of failure. During the saturated storage (autoclave), failure rate is dependent on the galvanically induced ionic currents flowing in a layer of water on the surface of the die. This layer of water is accumulated after plastic has debonded from the die which causes corrosion to concentrate on the bonding pad. The 85�C/85% RH lifetest produced more widespread corrosion due to phosphorous in the passivations, and debonding is not a pre-
500 Hrs.
# Fail
#In
0
25
0
25
0
25
0
25
0
25
0
125
1000 Hrs.
# Fail
#In
0
25
0
25
0
25
0
25
0
25
0
125
Total Hours
23800 23800 23800 23800 23800
1.2 x 1Q5
requisite for this type of failure.21, 22 Since corrosion on the bonding pad i.s only one of the failure modes which can occur in 85�C/85% RH lifetest, it would be a better indicator for normal operation.21
Table X shows the result of the temperature cycling for plastic packages. No failures were observed. The test used 200 temperature cycles for
+ 125�C to -65�C, air to air. (MIL-STD-883, Method
1010) indicates that the plastic packaged device would perform very well under normal temperature variations.
Table XI shows the results (no failures) of low temperature dynamic lifetest. The lack of failures indicates that typical semiconductor failure modes are not a factor in this technology.
9-19
M---~~~~~~~~~~~~~~~~~~~~-,
32
30
ffi 28
a: 26
3 24
if 22
~ 20
i 18
w 16
w~ 14
~ 12
::i
::>
10
0 8
6
4
2
0..L.~...-~-l!i~Ha._-r-....u1~92::..L.-r-...IL2~88:.L-.,..-~384f-L.-r___..4~8~0'--,...--5~76-
Figure 20: Pressure pot result.
NUMBER OF PRESSURE POT HOUR
0075-19
CALCULATION OF PREDICTED FAILURE RATE
There is no simple, one-step formula for inferring a predicted failure rate from the experimental data.
eInrsgtyeamd~stthebefatirlueraetsedofdeifafecrhenintldyi.viTdhueal faircsttivsatetiponi~ento-
calculate the equivalent device hours at the ambient temperature of interest, utilizing the Arrhenius relationship discussed earlier. This calculation should be carried out for every mechanism observed or expected. For example, the calculation fo~ the 0.3eV activation energy oxide rupture mechanism should be carried out whether this failure mechanism is observed or not, since this mechanism is always anticipated in MOS integrated circuits. The extrapolation should be carried out utilizing the junction temperature at the ambient temperature of interest and not the ambient temperature itself. The upper confidence limit is then calculated for the failure rate for each activation energy. The upper confidence limits for the various activation energies are then summed for a total failure rate prediction. The meaning of the "upper confidence level" is that with a certainty, or probability, of a certain level we can say that the true value is less than the stated value. Thus, the confidence level rate calculated is non-zero even for the case where no failures are observed because we can't be sure that there will be none.
Two calculations were performed to separate short term failure rates (infant mortality) and long term failure rate (expected failure rate). This was done to obtain a better picture of the expected failure rates.
Long term failure rates are tabulated in Table XII based on the data in Tables 111-V. Voltage acceleration is applied for the 0.3eV activation energy failure mode typical of oxide breakdown. No voltage a~cel eration is applied to the 0.6eV and 1.0eV failure modes because the dependence for these has not been established. These data lead to a predicted long term failure rate in plastic of 39 FIT (0.0039%/
1ooo hr) at 60% UCL at 70�C ambient and 18 FIT
(0.0018%/1000 hr) at 60% UCL at 55�C ambient. In cerdip the corresponding values are 85 FIT (0.0085%/1000 hr) at 60% UCL at 70�C ambient and 45 FIT (0.0045%/1000 hr) at 60% UCL at 55�C ambient. From these numbers, it should not be concluded that the parts are more reliable in plastic than in cerdip but rather that since there are more hours in plastic than cerdip the uncertainty is reduced and hence the UCL (upper confidence level) is lower. The best single point estimate of the reliability of the part is probably obtained by combining the data on the units in plastic and cerdip packages. This leads to estimated failure rate of 39 FIT (0.0039%/1000 hr) at 70�C ambient and 60% UCL and 16 FIT (0.0016%/1000 hr) at 55�C ambient and 60% UCL.
The above calculations of long term failure rates were done excluding the data for the first 48 hours
9-20
PLASTIC
Activation Hours at Energy 125�C
Hours at
c 1so0
Expected 60% UCL
Expected 60% UCL
Number of
Failures
Equivalent Hours at 70�C
Value of Failure Rate
at 70�C
Failure Rate at
10�c
Equivalent Value of
Hours at 55�C
Failure Rate at 55�C
Failure Rate at
55�C
0.3eV 1.75X106 4.91 x 105 0 9 ..31 x 107*
-
9.8 1.40 x 108 -
7
0.6eV 1.75X106 4.91 x 105 0 3.94 x 107
-
26 8.86 x 107 -
10
1.0eV 1.75X106 4.91 x 105 0 3.07 x 108
-
3 1.19 x 109 -
1
Total
-
39
-
18
CERDIP
Activation Hours at Energy 125�C
Hours at Number Equivalent
Expected Value of
60% UCL Failure
Equivalent
Expected Value of
60% UCL Failure
c 1so0
of Failures
Hours at 70�C
Failure Rate Rate at
Hours at 55�C
Failure Rate
Rate at
at 70�C
70�C
at 55�C
55�C
0.3eV 6.05 x 105 3.66 x 105 1 4.86 x 107*
-
41 7.45 x 107 -
27
0.6eV 6.05 x 105 3.66 x 105 0 2.26 x 107
-
40 5.30 x 107 -
17
1.0eV 6.05 x 105 3.66 x 105 0 2.11 x 108
-
4 8.75 x 108 -
1
Total
-
85
-
45
�o.3eV equivalent hours includes voltage acceleration for 7.5eV stress. Table XII: Long term failure rate (not including 48 hr data point).
of dynamic lifetest. (Note: all units going into other tests received this stress as a preconditioning.) The short term failure fraction, sometimes called infant mortality percentage, can be estimated from these data in Tables lllA, 1118. In cerdip, no failures were observed from 1700 units. In plastic, there were 2 failures in 5055 units or 396 ppm. If the data from all packages is combined, a single point estimate is 296 ppm.
These results show that Xicor NOVRAMs have attained failure rates comparable, if not better, to those reported by major suppliers of standard volatile memory products.18-20
SUMMARY
The data presented in this reliability report show that the data retention of Xicor's NOVRAM technology is excellent. Even at a high temperature (300�C), only about 2% lose data in 1000 hours. Theoretical grounds for expecting this result are discussed. Two calculations were done, one for short term (48 hours) failure rate and one for long term expected failure rate. These show an overall long term failure rate of 16 FIT at 55�C, 60% UCL and
an infant mortality of less than 300 ppm. The cerdip packaging employed is shown to be capable of passing the Group D qualification requirements of MIL-STD-883, Method 5005. Finally, the plastic packaging employed shows excellent 85�C/85% RH result.
REFERENCES
1. R.H. Fowler and L. Nordheim, Proceedings of the Royal Society of London, A119, pp. 173-181 (1928).
2. M. Lenzlinger and E.H. Snow, Journal of Applied Physics, 40, pp. 278-283 (1969).
3. D.J. Di Maria and D.R. Kerr, Applied Physics Letters, 27, pp. 505-507 (1975).
4. R.M. Anderson and D.R. Kerr, Journal of Applied Physics, 48, pp. 4834-4836 (1977).
5. H.R. Huff et al, Journal of the Electrochemical Society, 127, pp. 2483-2488 (1980).
6. T.J. Lewis, Journal of Applied Physics, 26, pp. 1405-1410 (1955).
9-21
7. C. Hu et al, Applied Physics Letters, 35, pp. 189191 (1979).
8. R.K. Ellis, IEEE Electron Device Letters, EDL-13, pp. 330-333 (1982).
9. R.K. Ellis, H.A.R. Wegener, and J.M. Caywood, International Electron Devices Meeting Technical Digest, pp. 749-752 (1982).
10. Z. Weinberg, Solid State Electronics, 20, pp. 11-18 (1977).
11. G.L. Schnable and R.S. Keen Jr., IEEE Trans. on Electron Devices, ED16, pp. 322-332 (1969).
12. S.R. Hofstein, Solid State Electronics, 10, pp. 657 (1967).
13. J.R. Black, Proc. 6th Reliability Physics Symposium, pp. 148-153 (1967).
14. R.E. Shiner et al, Proc. 18th Reliability Physics Symposium, pp. 238-243 (1980).
15. Dwight L. Crook, 17th Annual Reliability Physics Symposium, pp. 1-7 (1979).
16. B. Euzent et al, Proc. 19th Annual Reliability Physics Symposium, pp. 11-16 (1981).
17. R.E. Shiner et al, Proc. 21st Annual Reliability Physics Symposium, pp. 248-256 (1983).
18. Bruce Euzent, "2115/2125 N-Channel Silicon Gate MOS 1K Static RAMs" Intel Reliability Report RR-14, (1976).
19. Chieh Lin Ping, "Reliability of N-Channel Metal Gate MOS/LSI Microcircuits" National Semiconductor, (1982).
20. Bruce Euzent and Stuart Rosenberg, "HMOS Reliability" Intel Reliability Report RR-18, (1978).
21. R.P. Merrett, J.P. Bryant, and R. Studd, Proc. 21st Annual Reliability Physics Symposium, pp. 73-81 (1983).
22. K. Tsubosaki, et al, 21st Annual Reliability Physics Symposium, pp. 83-89 (1983).
This report is based on data collected through February, 1985.
9-22
RR-504
'co,
510
: :
10M
CUMULATIVE PERCENT 99
L
0 G 1M
c
y
c
L
~~~~�~--~---~---~----~---~---~---~---~----~----~-----~----~----~----~----~----~----~----~----~--�-~---~----~----tr�~---~---~---~---~---~---~---:���
E
s
: I
TYPE 2816A ~
100K
-1
0
REDUCED VARIATE
5 0076-1
ENDURANCE OF
XICOR E2PROMs
AND NOVRAMs*
By H.A. Richard Wegener
*NOVRAM is Xicor's nonvolatile static RAM device.
9-23
INTRODUCTION
Endurance is a property unique to nonvolatile memories. It describes the ability of the nonvolatile memory section of the chip to sustain repeated data changes without failure. Such a data change occurs when a stored "1" is changed into a "O", or when a stored "O" is changed into a "1 ". Continual changes from "1" to "O" to "1" to "O" are called writeerase cycling, or just cycling.
In this work, endurance will first be defined. A quantitative method for characterizing ~n~urance is described and applied to the characterization of endurance as a function of temperature and time between store events. Data on the endurance of a selection of Xicor's products is presented. Finally, the application of this information to the calculation of system failure rates is describ~d. A gen~ral problem in discussions of endurance 1s that various people mean different things when they speak of endurance. One meaning which has been used is that endurance is the number of nonvolatile data changes to a "typical" cell before the cell dielectric fails or the programming window closes. Figure 1 sho.ws such data for a typical Xicor E2PROM cell showing that after greater than 107 data changes the ?ell s.till has good margin with respect to the 50 �A. tnp point of our sense amplifier. Many other suppliers have presented similar data. Unfortunately this data is of little help to the user who doesn't buy one "typical" cell, but rather an array containing a large number of cells, some of which will not be typical.
Xicor's definition of the endurance of an individual memory is that the limit of endurance is reached
fwohrenn~rumnadleropcoenradtiitoionn, sthsepefcirifsiet dbibtyotnheadnaytachsihpeeist
found to be in error after a required data change. This limit of endurance, or endurance for short, is expressed in terms of cycles. By this definition then, endurance (in cycles) is the number of data changes per bit that occurred without error before the first failure took place.
When a nonvolatile memory chip is operating within a given application, it can be expected that some bits on that chip will experience more data changes than other bits, unless particular attention
ERASED Bil
l
1zw-
~ 50 :::> 0
~
0
PROGRAMMED BIT
0
'------..1...----...i..----...i.------------...
1112
11>3
104
1115
108
107
WRITE (CYCLES)
0076-2 Figure 1: �2PROM cell current vs. write/erase cycles. 50 �A is the trip point of the cell.
has been paid to even out their use throughout the chip. Within a given chip the endurances of i~~i vidual bits have a small range of values, and 1t 1s pure chance whether a highly cycled bit has an endurance on the high end or the low end of that distribution.
Xicor's approach to this problem is that the lowest the worst case endurance on any given cell in the' array, defines the endurance of that chip. In order to test for the bit that causes the worst case endurance, each bit on that chip must be subjected to the same number of data changes during cycling. When the first bit on that chip fails, all other bits have been cycled without failure at least the same number of times. While these other bits may have much higher endurance limits, the endurance of the chip under test is defined as that of the one worst case bit.
Knowledge of the statistical distribution of the worst case bit from each of thousands of devices makes the endurance of a given chip statistically predictable. We have found that our endurance d~ta fit a known statistical distribution - it is the logarithmic "Extreme Value" distribution. Its properties, and the handling of cycling data to derive its parameters for a given lot, are described in Appendix A.
9-24
The Measurement of Endurance
1 510
CUMULATIVE PERCENT 99
1 510
I II
CUllULAT1VE PERCENT 99
L
g-b,,,.,b.,,.,b:b-::~~:1:.:-:-:-::=-::-=:==:=;-~~~~E:~
c
y
c
L E
s~~~~i:t:F::::::::::::::~::::::E::j:~~
L
g~~Y,J~t;-j~~:n::::::::::::::::::::::r:::::::~
c
y
c
L E
s-1..~~:':";";~~~-;;::E::::::::::::~:i::::'::::
-1
0
2
4
5
REDUCED VARIATE
0076-3 Figure 2: Typical endurance plots of two lo~s of Xicor X221~ NOVRAMs. The upper horizontal axis gives the cumulative percent of failures.
The graph in Figure 2 shows the plots of endurances of two different lots of Xicor's X2212 NOVRAMs. This graph is an example of endurance plotted using an extreme value ?istribut~on. The meaning of the lower horizontal axis, the l~near extreme value variate, is explained in Appendix A. The upper horizontal axis, however, has intuitive appeal. It is the cumulative failure percentage. The plots are well distributed around a straight line. This indicates that they originate from an Extreme Valu~ di~tribu tion. They differ somewhat in slope (which 1s the measure of spread, or dispersion of the distribution). They are also offset in the vertical dire~ti~n, ~hic.h indicates that the maximum of each d1stnbut1on 1s different. Since the cycles are plotted as their logarithms this difference is about 40%.
lmpiicit in this discussion is the assumption that the endurance performance of lots can be described as the result of a relatively small sample. This has been proven correct experimentally a~d has been used to establish correlation between different pieces of equipment used for the determination of endurance. A successful application of this is shown in Figure 3.
-1
4
5
REDUCED VARIATE
0076-4 Figure 3: Correlation between endurance data obtained by Xicor and by one of Xicor's customers for Lot ZAA204. Each test is based on 28 data points. Most of Xicor's points are coincident with the customer's so that they are hidden.
The graph in Figure 3 shows the outcon:1e of an endurance correlation exercise between X1cor and one of its customers. The first set of points (black squares) was established from a 30-device sal'!1ple of X2212s from lot ZAA204 cycled out at X1cor. Overlying most of these original points are a second set (open squares) which were generated by endurance measurements on a separate 30-device sample from the same lot at the facility of the customer. It can be seen that the signatures of the two samples match faithfully, except at both extreme~. At the left hand side, the difference can be explained by the increased scatter of any distribution at its extremes. At the right hand side, a slight difference was introduced when the customer stopped cycling before the last three devices had failed. Even if it is assumed that the match would not have improved by further cycling, the agreement for 27 out of 3.0 points, or between 5% and 95% of the sample, 1s excellent.
9-25
ENDURANCE VARIABLES
The existence of an inherent limit to endurance is a universal property of nonvolatile semiconductor memories. Regardless of the materials used and of the details of the cell design or the semiconductor manufacturer, there is a measurable upper limit to the number of data changes that such a memory cell can sustain and still meet the data retention specification. The exact number of cycles, however, is dependent on all the elements that go into the construction and operation of a given cell design.
The reason for an endurance limit arises from the basic physics of nonvolatile semiconductor memories. All such memories depend on the highly nonlinear conduction properties of the solid-state dielectrics employed to form the memory cells. At high electric fields, these dielectrics permit a predictable current to pass from one electrode to another. This is used to program or erase such a device. At low electric fields, essentially no electron is transmitted. Therefore charges transferred at high fields to locations isolated by this type of dielectric will remain there indefinitely. But during the transfer of charge at high fields, a very small fraction of the electrons passing through becomes trapped in the dielectric. The many thousands of times that this happens during the life of a memory contribute more and more trapped charge, creating an electric retarding potential in the dielectric, until the device cannot function as a memory any more. Then its endurance limit is reached.
The nonvolatile cells used in Xicor memories make use of the special characteristics of its microtextured surface. The many tiny regions of gently curved features are particularly effective as non-linear conduction elements. As a result of the combination of surface curvature and thick oxide, they require relatively low voltages for programming, and provide excellent retention of data. The physics of the programming process as well as the excellent data retention measured for Xicor memories have been described in a recent publication.1
If all these features were identical, if the thickness of the dielectric over them were the same, and if the details of the high voltage generator on the chip were precisely reproducible, then every device on the same silicon wafer, and in the same manufacturing lot would have identical endurance limits. In the real world, there are small variations in the results of the intricate fabrication steps of the silicon chip. These give rise to a range of endurance values for all the nonvolatile memory cells on the same chip.
Additional small variations will occur from chip to chip over the whole silicon wafer, and from wafer to wafer. All of these define the details of the distribution that describes the endurances of all the memory cells in a device lot. Once the chips have been fabricated, the average and the dispersion of this distribution have been fixed by the interaction of cell design and the fabrication process with its small variations. These are the fixed internal parameters of endurance. The dispersion is an indicator of the process variation.
There are, however, variations that can be superimposed on the fixed characteristics by the conditions that accompany the normal use of the nonvolatile memory devices. The temperature of operation is one of these. Both the details of the charge transfer process in the nonvolatile memory cell, and the operation of the high voltage generating circuit should be affected in some way by this condition. Another externally controlled parameter is the frequency of the cycling process. At the end of a storage cycle the newly trapped electrons are in a relatively high free energy state. Longer periods between cycles give these charges and their environment more time to relax into a lower energy state. This should also affect the measured endurance parameters.
The control of these external parameters is essential when exact correlation of endurance data must be obtained. Their knowledge is also important to optimize performance and predict reliability in any application.
The Effect of Temperature on Endurance
The endurance of a lot of nonvolatile memories can be described concisely by the constants defining its statistical distribution. For the simple "Extreme Value" distribution pertinent here, these constants are its mode and its dispersion. This distribution can be used to assist in the characterization of endurance.
Five 20-device samples from the same lot of X2212 NOVRAMs were subjected to continuous data changes, each at a different temperature, until all devices had failed. The temperature levels were
- 55�C, �-10�C, + 25�C, + ?0�C, and + 125�C. The
delay between data changes for all devices was one second. The endurances of individual devices were plotted in the form of a probability plot, as shown in Figure 4.
1XICOR Reliability Report RR-502A.
9-26
1 5 10
50 57 CUMULATIVE PERCENT
99
REDUCED VARIATE
0076-5 Figure 4: The effect of temperature on endurance: the endurance doubles tor every increase in temperature by 50'C.
The y-axis gives the logarithm of the number of cycles that each unit had at the end of its endurance. The straight lines shown were least-squares fitted to each set of data. The correlation coefficients for lines ranged from 97% to 99%. The results can be summarized as follows:
1) There is an increase in the endurance with increasing temperature.
2) The dispersion is essentially constant at and below room temperature and increases somewhat above room temperature.
Over the range of the data, the logarithm of the endurance is linearly related with temperature. The coefficient is 0.00621�C, but as a simple rule, the endurance doubles for every increase of temperature by 50�C.
The Effect of Data Change Delay on Endurance
The baseline values of endurance can also be modified by the length of the delay between consecutive data changes.
In the determination of the endurance of a lot there is a premium on getting the job done as rapidly as possible. This means that only minimum delays can be added between STORE signals. Typically, the devices in a lot of our current NOVRAMs have endurances between 10,000 and 100,000 cycles.
The time to cycle a lot of devices will be 3 hours if the last device to fail had an endurance as low as 100,000 cycles for delays between data changes of 0.1 second even if all devices are cycled in parallel. This total cycling time increases to 28 hours for a delay of 1 second, to 12 days for a delay of 1O seconds, and 120 days for a delay of 100 seconds. Even a 1000 second delay is at the low end of the type of write frequency to be expected in most applications, and this would take in excess of three years to document. For this reason we have limited the experimental work on the effect on lot endurances to delays of 0.1, 1, 10, and 100 seconds. The shortest delay could not be reduced much below 100 ms, since that is the time required by the microprocessor which was used in the test to handle addressing, reading and recording data of the many devices tested simultaneously.
Four 20-device samples were taken from the same lot of X2212 NOVRAMs and then they were cycled until all devices had failed. The endurance of each device was recorded. Each of the four samples had one of the four different data change delays in its cycling program. The data are summarized in Figure 5. Individual data points were not recorded on this graph, since there was much confusing overlap where the data point from the samples overlay each other. Instead, the points were replaced with least-squares fitted straight lines. The correlation coefficients for these lines were between 97 and 99%.
CUMULATIVE PERCENT
g L
~ c
L
~
-1
3
4
REDUCED VARIATE
0076-6 Figure 5: The effect of data change delay on endurance: the maximum of the distribution is unchanged, but it becomes tighter as the delay increases.
9-27
The results can be best expressed in terms of the constants of the distributions obtained:
1) The mode of the distribution .did not change for the four orders of magnitude of delay tested. This is shown by the fact that the individual lines c::ross near 37% of the cumulative frequency.
2) The slope of the distribution decreased 15% per decade of cycles with each order of increase in delay. At first sight, this might appear to be a small change. But in the terms of the definition of endurance, they are quite important for many applications. This is because the endura.nce change in the region where the majority of the units have failed is irrelevant. The important region is that in which� only a few per cent or less have failed. In this region, the effect of the longer time between store events at a constant endurance level is to decrease the fraction failing by an order of magnitude or more!
Endurance Status of XICOR Memories
Figure 4 and 5 lack vertical scales because they are intended to show general tendencies. The actual endurance observed on Xicor memories vary from product to product because of differences in cell design and to a lesser amount from lot to lot because of small processing variations. There is also a general tendency for the endurance to improve with time as a result of refinements in design and processing technique.
To give the user a sense of the status of endurance of Xicor memories as of the date of this report, distribution measurements for several product types are reported here. All of this data measured at 25�C and rapid cycling rates. Figure 6 shows the endurance data measured on a lot of X2816As. The process average for this lot is about 500,000 cycles with the 5% point on the curve appearing at 200,000 cycles. In Figure 7 the measured endurance distribution of a lot of X2443s (a 256 bit serial NOVRAM) is displayed. For this device the process average was - 80,000 cycles and the 5% point appears at 30,000 cycles. The measured endurance distribution of a lot of X2212s is shown in Figure 8. This product exhibits a process average of about 100,000 cycles and the 5% point appears at 40,000 cycles.
The data reported here are intended as a status report. As we further refine our products and increase. the endurance, we intend to issue updates to this report.
-
1 510
I II I II
L 0 G tll
c
y
c
L
E s
tOOK
-1
3
4
5
REDUCED VARIATE
0076-1 Figure 6: Endurance data from a lot of Xicor X2816A �2PROMs.
1 510
99
I II I II
c
y
c
L
E s
-1
0
3
REDUCED VARIATE
0076-7 Figure 7: Endurance data from a lot of Xicor X2443 Serial NOVRAMs.
9-28
1 510
: ::
CUMULATIVE PERCENT 99
c
y
c
L
s E
-1
0
3
REDUCED VARIATE
0076-8 Figure 8: Endurance data from a lot of Xicor X2212 NOVRAMs.
QUALITY ASSURANCE APPLICATIONS
One problem any supplier of nonvolatile memory faces is how to define endurance and how to assure that the parts reaching the customer actually satisfy the endurance specification. This task is akin to assuring the lifetime of a light bulb. If the light bulb is specified to have a 1000 hour life, one can verify that the bulb lasts 1000 hours by burning it for that period. However, one now knows only that the bulb lasted 1000 hours, not that it will last another 1000 hours. The statistical technique discussed in this report allows Xicor to perform this difficult an~ _ex~ct ing task. What a Xicor endurance spec1f1cat1on means is that for any lot of memories shipped, fewer than 5% of the units will cease to cycle before the specified limit when cycled at room temperature and at the maximum frequency allowed by the specification. Xicor continually samples production lots to assure that this criterion is met.
Let's look at what this means in a typical application. Assume that the Xicor memory is used in an electronic system which contains a number of other components so that the average chip temperature is 50�C and that the average delay between store
events is some minutes. Examination of Figure 3 shows that raising the chip temperature from 25�C to 50�C would decrease the fraction of units not exceeding the endurance value from 5% to 0.03%. For data change delays of 100 seconds and longer, the fraction of the lot not meeting the nominal endurance value further decreases to 0.001 % or less.
Of course, in a given application the predicted behavior may be better or worse than that worked out in the previous example. However, the information supplied here should be sufficient for the user to compute the expected endurance failure rate in a particular application.
One last consideration is how endurance failures affect the overall device failure rate. Here again, the calculation is a little application-sensitive, but for simplicity assume that the system is designed to last 105 hours ( - 12 years) and that the device performs nonvolatile writes roughly uniformly over this period. If the application is designed to use the specified number of cycles over the life of the part, the additional endurance-related failure rate is the cumulative failed fraction divided by the time. For our previous example, this works out to 0.001 %/ 105 hours or 10-5%/1000 hours (0.1 FIT). As this illustrates, in most well-designed systems the endurance-related failures of Xicor products do not significantly increase the overall device failure rate.
In all discussions of endurance in this work NOVRAMs and E2PROMs have been treated as if they behave the same. From a physical view of the nonvolatile storage element this is correct. However, there are two properties of the NOVRAM cell which may cause it to have significantly enhanced endurance in certain applications. One factor is that the NOVRAM allows the user to store data in the volatile latch during normal operation and only transfer data to the nonvolatile element prior to power down. In applications which require a high frequency of data changes but only relatively infrequent power interruptions this may be very useful. A second if less obvious factor, is that unlike the E2PR0Ms which automatically erase each byte prior to each write, the NOVRAMs only transfer electrons in the case of a change in nonvolatile data. This means that only those cells in which nonvolatile data is altered use up endurance. In some applications this fact can be used to greatly increase effective endurance of the memory.
9-29
SUMMARY
A method of characterizing endurance which is of general applicability has been described here. This method has been applied to the characterization of endurance as a function of temperature and time between store events. The meaning of Xicor's endurance specification is defined in the framework of this method. Based on the above, the fraction of Xicor product which is predicted to fail to store prior to attaining the specified endurance is predicted to be less than 0.001 % in a typical system in which the devices experience a 50�C ambient temperature.
APPENDIX A
The Mathematics of Endurance Characterization
The mathematical characterization of endurance data arises most elegantly from the definition of endurance. In an individual device, the endurance is the minimum number of data changes that all memory cells can sustain until one cell gives rise to an erroneous output (due to a permanent change in its characteristics). The extreme characteristic from a fixed set of possible values forms a well-known distribution called the Extreme Value distribution. This distribution is independent of the distribution within that fixed set of values. Since by definition, the endurance of a chip containing 1024 memory cells is that of the cell with the minimum endurance, it can be expected that the endurances of the chips from the same device type will have the Extreme value distribution.
The formulations of the Extreme Value distribution are given in Table I. On the left hand side are the entries for the Extreme Value distribution, and
on the right hand side the corresponding entries for the Normal distribution.
The cumulative probability <I> is defined by a fraction of 1. It defines, towards one side of a distribution, the fraction of the population <I> that has a smaller value than the variate at that fraction, and towards the other side, the complement of that fraction which has a larger value than the variate at that fraction. This is quite often expressed as "fraction with more than . . . " or "fraction with less than ... ". It can be seen that the cumulative probability of the Extreme Value distribution <l>Ev has a much simpler functional relationship with its variate Y than the equivalent <l>N with its variate Z of the Normal distribution. The Extreme Value variate Y is related by two constants to the distributed property X. One constant is the maximum of the distribution U, and the other the dispersion 1/a. The Extreme Value distribution is not symmetrical around its maximum (as the Normal distribution is). Instead, one side is stretched out more than the other. If the low cumulative probability fraction is on the narrower end, the maximum of that distribution is located at the value of 0.366, or 37%.
This is typical of the distributions of low extremes, and this is the distribution used for endurance values from NOVRAM chips of the same device type. There is one more empirical observation: it is not the number of cycles, but the logarithm of the number of cycles that has the form of the Extreme Value distribution. The X in the expression for the variate then is the logarithm of the observed cycles of individual chip endurances, a is the dispersion of the distribution of these endurances, and U is the observed or interpolated value of the log of the endur-
ance at <I> = 0.366.
The extraction of these two constants from the data could be a complex calculational procedure, but by linearizing the variate Y, it becomes as simple as plotting a straight line. The approach is summarized in Table II.
Statistic Cumulative Probability Variate Maximum Dispersion Table I: Mathematica/ deftm. t.1.ons.
Extreme Value
<l>Ev = EXP(-EXP (-Y)
Y = a(X-U) U at <I> = 0.37
1/a
Normal Distribution
f <l>N = ~ (2)-%EXP(-T2/2) dT 00
Z = (X-M)/<T Mat <I>= 0.50
CT
9-30
<l>i =EXP (-EXP-Yi) Yi= a (Xi - U) = -LN (-LN <l>i)
Xi= U+ (1/a) (-LN (-LN<l>i)) BUT Xi= LOG CYi U = LOGCYm
LOG CYi = LOG CYm + (1/a) (LV) CYi = endurance of parti
CYm = maximum of distribution (1 I a) = slope of line
(LV) = ( - LN (- LN<l>i))
Table II: Linearized plot.
The first line states once more the cumulative probability relationship between <I> and Y, and the second line the linear relationship between Y and X. The third line shows that the value of Y can be calculated from the double natural logarithm of <I>. The fourth line expresses the second line as a function of X, and substitutes its functional relationship with <I>. Identification of X with the logarithm of an individual observation, and U with the logarithm of the maximum of the distribution of cycles then leads to the seventh line which states the desired linear relationship. A typical plot is shown in Figure 9. There is clearly a straight line relationship. The value of the maximum occurs at <I> = 37%, and the slope of the line is the value of 1I a.
1 510
99
I II I II
L 0
G.....,,,......,..:-:-i:-=:=-:1~=-=-=-=~~~==-===-===~=r=~~
c
y
c
L
E s
-1
0
2
5
REDUCED VARIATE
0076-9 Figure 9: Straight line plot of the logarithm of endurance cycles vs. the reduced variate.
There remains one more problem, and that is how to associate the correct value of <I> with a given observed endurance. This is accomplished by taking all the endurances from a group of devices and writing them down in the order of increasing cycles (this is called "ranking"). Looking at the data in this way, any given endurance represents the borderline between a fraction of the lot that is higher than anything preceding it, and lower than anything following it. The approximate value of that fraction is found by assigning consecutive rank numbers to the ordered endurances: 1 to the lowest, 2 to the second lowest, and so on, until the highest endurance ends up with the rank equal to the total number of devices tested in that group. Dividing the rank numbers by the total number of the devices in the group then yields the "fraction lower than ... ". A slightly more exact value for <I> is found by the formula <I> (i - 1/2)/N, where i is the rank number and N the total number of devices tested.
Raw Data (CY)
Ranked Data (CYi)
Rank (i)
Plotting Position (<l>i = (i-0.5)/n)
129.50
7.31
1
35.95
12.10
2
21.95
12.10
3
7.31
12.10
4
31.95
16.85
5
19.65
19.65
6
60.75
21.95
7
33.95
22.45
8
22.45
22.95
9
85.75
31.45
10
12.10
31.95
11
22.95
33.95
12
12.10
35.95
13
79.25
48.25
14
52.75
52.75
15
209.50
60.75
16
16.85
79.75
17
12.10
85.75
18
48.25
129.50
19
31.45
290.50
20
0.025 0.075 0.125 0.175 0.225 0.275 0.325 0.375 0.425 0.475 0.525 0.575 0.625 0.675 0.725 0.775 0.825 0.875 0.925 0.975
PLOT LOG (CYi) vs. - LN( - LN<l>i)
Table !II: Data preparation.
This report is based on data collected through February, 1984.
9-31
NOTES
9-32
RR-505
liCll!
0077-1
X2816A/X2804A RELIABILITY REPORT
By Reliability Engineering Staff
9-33
INTRODUCTION
The X2804A and X2816A are electrically erasable programmable read only memories (E2PR0Ms) organized 512 x 8 and 2K x 8 respectively. These memories operate on a single 5V power supply for all operations. Figure 1 provides pinouts for the two parts; Figure 2 shows the functional block diagram for the X2816A; Figures 3 and 4 illustrate the physical location of the various address bits. The thermal resistance table, burn-in circuit and a timing diagram are included in Appendix A for your reference.
A,
Vee
A,
A&
Aa
Ao
As
NC
As
A,
WE
A,
A3
OE
A3
A,
NC
A,
A,
CE
A,
Ao
110,
1100
1106
110,
llOs
110,
110,
Vss
1103
0077-2 Figure 1: X2804A and X2816A Pin configurations.
Ao-A10 ADDRESS INPUTS
x BUFFERS LATCHES
AND DECODER
y BUFFERS LATCHES
AND DECODER
YccO---. Yss0--.
Figure 2: X2816A Functional block diagram.
CONTROL LOGIC
16,384-BIT E2PROM ARRAY
l/OBUFFERS AND LATCHES
ll ltlll
l/Oo-11<>7 DATA INPUTS/OUTPUTS
0077-4
Vee Aa
Ao
WE
OE
llO, llO, llO,
'��
l/03
0077-3
9-34
X4 X3 X2 X1 Xo A4AsAs A1 As
000 00
000 0 0 0 0 0 0 0 10
00 100
00 0
0 0
0 0
0
J\
N 0 0
0
~
1Nr-
0
00000000 0000 1111 00110011 0 10 10 10 1
Y3=A3 Y2=A2 Y1 =A1 Yo=Ao
Each square equals one byte.
111 11 11 0000111 0 0 1 10 0 1 0 10 10 10 1
0077-5
Figure 3: X2804A Physical bit map.
X5X5X4X3X2 X1 Xo A10A9 A4 As As A7 As
00000 00
00000 0
0 0 0 0 0
00000 0
0000 00
0000 0 0 0 0 0
0 0 0 0
0
0 0 0 10 0 0
0 0 0 10 0
0 0 0 10 1
0 0 0 10 10
0 0 0
0 0
0 0 0
0
10 0
0 0 0 1 1 10
J\ \f
1 10 0 0
11 0 0
0
10 0
11 100
1 1
0
1 1 1 1
1 1
11 1 1 1 10
1\r-'-
~
00000000 0000 1111 00 1100 1 1 0 10 10 10 1
Y3=A3 Y2=A2 Y1 =A1 Yo=Ao
Each square equals one byte.
1 1 1 1 1 1 1 1 0000 1111 00 1100 1 1 0 10 10 10 1
0077-6
Figure 4: X2816A Physical bit map.
9-35
TECHNOLOGY
Xicor E2PR0Ms are manufactured using a triple polysilicon N-channel process. Data is stored as the presence of positive or negative charge on the second level polysilicon which acts as a gate .to a sense transistor. This second level ROlysilicon is a floating gate surrounded by - 750A of thermally grown oxide. Charge is transferred to and from the floating gate through a quantum mechanical effect known as Fowler-Nordheim tunneling. This phenomenon has been described in detail in recent Xicor publications.1.2,3
Xicor's process employs a textured polysilicon. This creates a textured surface between the polysilicon and the tunneling �oxides, resulting .in a sharp decrease in tunneling current with a decrease in voltage allowing the use of thick tunneling oxides. This in turn results in lower leakage currents from the floating gate during static store periods and during read operations. Recent Xicor publications describe the excellent data retention that can be expected from this technology.3 For both the X2804A and X2816A Xicor specifies a data retention of 100 years.
RELIABILITY STUDY AND RESULTS
This report is based on data collected using the X2816A. The X2804A is a smaller version of the X2816A, produced by using the design of the X2816A with three-quarters .of the array and two address buffers removed. Thus, reliability studies were focused on the X2816A. The X2816A has four times the memory and approximately twice the active silicon area; therefore, it is the more sensitive reliability indicator.
Before Xicor qualifies any new product it is subjected to a series of accelerating stresses and tests. These tests are designed to accelerate any degradation a device may experience over the course of a normal lifetime in order to uncover any design or process flaws. Because package type has an affect on device reliability, complete qualification of the X2816A involved both plastic and cerdip units. In addition, Xicor runs ongoing monitors of those products in production. This assures high reliability standards for all product shipped by Xicor.
The stresses used to establish reliability data are as follows:
1) High temperature dynamic lifetest. 2) Data retention bake.
3) High temperature high voltage stress. 4) Environmental testing. A short description of these tests and the results obtained are presented in the following report.
Dynamic .Lifetest
Failure modes typically encountered in MOS semiconductor devices can be accelerated if the device is operated at elevated temperatures. The dynamic lifetest aims to accelerate any failure modes a device may exhibit by operating the device in its most common mode at high temperature.
For the X2816A, the dynamic lifetest consisted of continually reading a known data pattern stored in the device, while it was subjected to a temperature
of +125�C. Each unit was then tested for data re-
tention and complete functionality after 168, 500, 1000 and 2000 hours of dynamic lifetest. The results of the tests are shown in Table I.
Data Retention Bake
The purpose of this stress is to measure and ensure a device's ability to retain correct data. Technologies using floating gate structures to retain charge will all have a greater tendency to loose this charge at higher temperatures.
This test is conducted by storing a checkerboard pattern in the devices under test and then baking
the devices at + 150�C for plastic units and at + 250�C for cerdip units. The pattern is verified after
48, 168, 500, 1000 and 2000 hours of bake. In most cases a group is split and retention evaluated on units that have been precycled (10,000 erase/write cycles) and units that have not been cycled. This provides a base to study the affect (if any) of writing to an E2PROM on data retention. The results of the tests are shown in Tables II and Ill.
High Temperature High Voltage Stress
The high temperature high voltage test is a derivative of the high temperature reverse bias test used
to evaluate bipolar circuits. In this test Vss is
grounded while all inputs and Vcc are maintained at high voltage while being baked. The stress is intended to expose failures due to mobile ionic contaminants, electrical overstress and latent gate oxide defects.
9-36
Lot#
168 Hrs.
#Fail
#In
1C
0
159
2C
0
152
3C
0
75
4C
0
388
5C
1 [a]
387
1P
1 [b]
410
2P
0
389
3P
0
214
Totals
2
2174
[a] Ionic contamination: leV [b] Retention failure: 0.6eV Note: C = Cerdip
P = Plastic
Table I: 12S'C Dynamic lifetests results.
500 Hrs.
# Fail
#In
0
84
0
93
0
75
0
99
0
126
0
51
0
76
0
15
0
619
1000 Hrs.
#Fall
#In
0
84
0
93
0
75
1 [a]
99
0
126
0
51
0
76
0
15
1
619
2000 Hrs.
# Fail
#In
0
84
1 [a]
93
0
75
0
98
0
-
0
51
0
76
0
15
1
492
Total Hours
1.8 x 105 2.0 x 105 1.5 x 1Q5 2.5 x 105 1.7 x 1Q5 1.6 x 105 2.0 x 105 6.3 x 104 1.4 x 106
Lot#
48 Hrs. #Fail #In
168 Hrs. #Fail #In
500 Hrs. #Fail #In
1
0
50
0
50
0
50
2*
0
24
0
24
0
24
3
0
20
0
20
0
20
4*
0
55
0
55
0
55
Totals
0
149
0
149
0
149
*Denotes units that received 10,000 erase/write cycles prior to retention tests.
Table II: 250'C Cerdip unit, retention bake test results.
1000 Hrs.
# Fail #In
0
50
0
24
0
20
0
55
0
149
2000 Hrs.
#Fail #In
0
50
0
24
0
20
0
55
0
149
Total Hours
1.0 x 1Q5 4.8 x 104 4.0 x 104 1.1 x 105 3.0 x 105
Lot#
48 Hrs. # Fail #In
168 Hrs. # Fail #In
500 Hrs. #Fail #In
1
0
51
0
51
0
51
2
0
25
1 [a]
25
0
24
3*
0
76
0
76
0
76
Totals
0
152
0
152
0
151
[a] Data retention failure: 0.6eV *Denotes units that received 10,000 erase write/cycles prior to retention test.
Table Ill: 150'C Plastic unit retention bake test results.
1000 Hrs.
#Fail #In
0
51
0
24
0
76
0
151
2000 Hrs.
#Fail #In
0
51
0
24
0
76
0
151
Total Hours
1.0 x 105 4.8 x 1Q4 1.5 x 1Q5 3.0 x 1Q5
9-37
This test was conducted on the X2816A at 5.5V
and + 150"G. Data retention and functionality were
verified after 48, 168, 500, 1000 and 2000 hours. The results of the test are shown in Table IV.
ENVIRONMENTAL TESTING
Environmental tests are designed to determine a device's resistance to extreme or changing environ-
ments. Due to the inherent differences between plastic and cerdip devices, different reliability stresses are applied to evaluate the individual package.
Cerdip
The standard tests for cerdip encapsulated devices are defined by MIL-STD-883, Method 5005, Group C and D. The results and conditions of these tests on typical Xicor products are listed in Tables V and VI.
Lot#
48 Hrs. #Fail #In
168 Hrs. # Fail #In
1C
0
25
0
25
2C
0
25
0
25
3C
0
51
0
51
4C
0
25
0
25
1P
0
52
0
52
2P
0
51
0
51
3P
0
15
0
14
Totals
0
244
0
243
[a) Oxide breakdown: 0.3eV
Note: C = Cerdip P = Plastic
Table IV: High temperature high voltage stress test results.
500 Hrs.
# Fail #In
0
25
0
25
0
51
0
25
1 [a]
52
0
51
0
13
1
242
1000 Hrs.
# Fail #In
0
25
0
25
0
51
0
25
0
51
0
51
0
13
0
241
2000 Hrs.
#Fail #In
0
25
0
25
0
51
0
25
0
51
0
51
2[a]
13
2
241
Total Hours
5.0 x 104 5.0 x 104 1.0 x 105 5.0 x 104 1.0 x 1Q5 1.0 x 105 2.7 x 104 4.8 x 105
Test
883 Test Method
Temperature Cycling
1010
Constant Acceleration
2001
Seal Fine Gross
1014
Table V.� Group C, die related tests.
Conditions
Test Condition C
(10 cycles -65�C to + 125�C)
Test Condition E (30,000g Y1 axis)
Test Condition B Test Condition C
LTPD 15 15 15
Accept #
0/15
0/15
0/15
Results 0/34 0/34
0/34 0/34
9~38
Test
Lead Integrity Seal
Fine Gross Thermal Shock
883 Test Method
2004 1014
1011
Temperature Cycle
1010
Moisture Resistance Seal
Fine Gross
Mechanical Shock
1004 1014
2002
Variable Frequency Vibration
Constant Acceleration
Seal Fine Gross
Salt Atmosphere
Seal Fine Gross
Internal Water Vapor
2007 2001 1014
1009 1014
1018
Adhesion of Lead Finish
2025
Lid Torque
2024
Table VI: Group D, package related tests.
Conditions
Test Condition 82
Test Condition B Test Condition C Test Condition B
(15 cycles -55�C to + 125�C)
Test Condition C
(1 Ocycles - 65�C to + 125�C)
Test Condition B Test Condition C Test Condition B (15009 peak 3 axis) Test Condition A (29g peak 3 axis) Test Condition E
Test Condition B Test Condition C Test Condition A
Test Condition B Test Condition C 5,000 ppm Max. Water Content at 100�C
LTPD 15 15
15 15 15 15
15 15 15 15
15 15
-
15
-
Accept #
0/15 0/15
0/15 0/15 0/15 0/15
0/15 0/15 0/15 0/15
0/15 0/15
0/3 or1/5 0/15
0/5
Results 0/15
0/15 0/15 0/34
0/34
0/34
0/34 0/34 0/34
0/34
0/34
0/34 0/34 0/43
0/43 0/42 0/5
0/15 0/5
9-39
Plastic
Some of the tests used to evaluate cerdip packages do not apply to plastic packages. Tests such as seal, internal water vapor content and lid torque do not apply because plastic packages are not hermetically sealed and do not have lids. Other tests such as vibration and acceleration do not apply because the die in plastic packages are completely embedded in plastic and are not susceptible to such mechanical failures. Plastic packages, however, may be more susceptible to other failure modes. Due to the considerable difference in expansion coefficients between plastic and silicon, plastic devices may be more susceptible to temperature cycling failures. Plastic package devices may also be more susceptible to moisture. Therefore, the plastic units were subjected in greater numbers to more stringent tests.
Temperature Cycling
Plastic packaged devices were subjected to 1000 temperature cycles per MIL-STD-883 Method 1010 Condition C. The results of this test are shown in Table VII.
Lot#
168 Cycles
#Fail #In
500 Cycles
# Fail #In
1
0
57
0
57
2
0
59
0
59
3
0
30
0
30
Totals 0 146 0 146
Table VII: Temperature cycling test results.
1000 Cycles
#Fail #In
0 57
0
59
0
30
0 146
85�C/85% Relative Humidity and Autoclave Tests
Because plastic encapsulated devices may be more susceptible to moisture related failures they are subjected to environmental tests at 85�C with 85% relative humidity (both powered-on and powered-off). Three additional sample lots were subjected to autoclave tests (pressure pot) at two atmospheres. These stresses test for corrosion, electrolytic failure modes and passivation integrity. The results of these tests are presented in Tables VlllA, VlllB and IX.
Lot#
168 Hrs.
#Fail
#In
1
0
52
2
0
52
3
0
15
Totals
0
119
Table VII/A: 85185 Test results, Vee= + 5.5V.
85/85 Vee= +5.5V
500 Hrs.
# Fail
#In
0
52
0
51
0
15
0
118
1000 Hrs.
# Fail
#In
0
52
0
49
0
15
0
116
Total Hours
5.2 x 104 5.0 x 104 1.5 x 104 1.2 x 105
85/85 Vee= ov
Lot#
168 Hrs.
#Fail
#In
500 Hrs.
# Fail
#In
1000 Hrs.
#Fail
#In
Total Hours
1
0
52
0
52
0
47
5.0 x 104
2
0
52
0
51
0
47
4.9 x 104
3
0
15
0
15
0
15
1.5 x 104
Totals
0
146
0
146
0
146
1.1 x 105
Table V/118: 85185 Test results, Vee= OV.
Note: In both 85/85 tests, each pin was alternately biased to + 5V and OV to provide an electrical potential between adjacent metal lines.
9-40
Lot#
48 Hrs.
# Fail
#In
1
0
40
2
0
34
3
0
20
Totals
0
94
Table IX� Autoclave test results.
144 Hrs.
# Fail
#In
0
40
0
33
0
20
0
93
240 Hrs.
# Fail
#In
0
40
0
33
0
17
0
90
Total Hours
9.6 x 103 7.9 x 103 4.4 x 103 2.2 x 104
Prediction Of Failure Rates
Accelerated testing allows one to identify possible
design and process flaws. It also makes it possible
to predict failure rates under normal operating con-
ditions. All failure mechanisms are accelerated to
some degree by voltage or temperature or both.
The degree to which any given failure mode is ac-
celerated is known as the activation energy. Knowl-
edge of a failure mode's activation energy allows
one to predict the rate at which that failure mode
will occur under normal operating conditions. If the
activation energy is not known it can be determined
experimentally.4 Four typical failure mechanisms of
the technology employed by Xicor and their corre-
sponding activation energies are:
Oxide breakdown
0.3eV
Leaky oxides
0.6eV
Ionic contamination
1.0eV
Table X presents the predicted failure rates for these activation energies. The results are based on the test data presented in Tables I and IV.
The failure rates predicted are for both plastic and cerdip devices. Such a prediction is valid because all the failure modes found or expected are common to both plastic and cerdip devices. The predicted failure rate is depicted as the "60% upper confidence level" failure rate per 1000 device hours. This means that there is a 60% probability the actual failure rate will be below the rate computed. Sometimes predictions are expressed in FIT units. To convert from the given values to FIT, multiply by 10,000.
A more representative value for the failure rate can be given by the "best estimate". This value gives the most likely failure rate based on the given data. Table XI presents the best estimate values.
Activation Energy
Number of
Failures
0.3eV
3
0.6eV
2
1.0eV
3
Totals
8
Table X� 60% UCL failure rate pred1ct1ons.
Equivalent Hours at
70�C
1.3X107
4.0 x 1Q8 6.3 x 1Q8
60% UCL Failure Rate Per 1000 Hrs.
at 70�C
0.0310
0.0008
0.0007
0.0325
Equivalent Hours at 55�C
2.1 x 107 1.0 x 109 2.8 x 109
60% UCL Failure Rate Per 1000 Hrs.
at 55�C
0.0200
0.0003
0.0002
0.0205
9-41
Activation Energy
Number of
Failures
EquI'valent Hours at
70�C
0.3eV
3
0.6eV
2
1.0eV
3
Totals
8
Table XI: Best estimate failure rate predictions.
1.3 x 107 4.0 x 108 6.3 x 1Q8
Best Estimate Failure Rate Per 1000 Hrs.
at 70�C
0.0280
0.0007
0.0006
0.0293
Equivalent Hours at 55�C
2.1 x 107 1.0 x 109 2.8 x 109
Best Estimate Failure Rate Per 1000 Hrs.
at 55�C
0.0170
0.0003
0.0001
0.0174
Based on these values it can be seen that the expected failure rate for the X2816A and X2804A is 0.0293% per 1000 hours at 70�C (293 FIT) and 0.0174% per 1000 hours at 55�C (174 FIT).
Endurance
Xicor uses two tests to evaluate the endurance of its E2PROMs. One test utilizes special test modes to enable all bits in a unit to be changed simultaneously. This test is used to measure the ultimate endurance of a sample of units. For reasons discussed in RR-510, this test tends to give a somewhat pessimistic estimate of trapping limited endurance and a slightly optimistic estimate of oxide breakdown limited endurance. Figure 5 shows the endurance distribution from a twenty piece sample from a lot of X2816A showing the intrinsic endurance. In order to monitor the oxide defects, which appear as infant mortality endurance failures, Xicor conducts a test in which the memory is written sequentially 10,000 times on byte-by-byte basis. Two failures were observed on a sample of 300 units from several diffusion lots in this test. As is shown in RR-510, these failures are expected to contribute approximately 1O FIT to the failure rate in typical applications.
SUMMARY
The technology used in producing the X2816A and X2804A are reviewed. The reasons for expecting excellent data retention are presented. A comprehensive set of data covering a variety of stresses are presented. Finally, failure rate predictions are provided.
I
I I
t
I
I 1
I
1M :..:.:. ~ _ _; _________:_ ~. __ .. _________________ . __ . __ .. ~ .... ____ __
,--,-,-r- -1---------,-r------------------------------r----------
: : :::: :: : : : :: :: ::::: ~ : :!::::::::::: t::::::::::::::::::::::::::::::::::::::::::
:::::::~: :::~:~.::~~+:~ ~:~:~:
::f: :: :: ::: ::
I:::�� :�� II
I
1--1-1-r-1--1-1-r-
1--1-1-1--
,I --1 ,-1,1 -,-
1I --1I-I1-I,.-
-T�--------1-r------------------------------r---------�t�--------1-r------------------------------.-----------.i.---------�-1-------------------------------i-----------iI �--------1I -I ,------------------------------rI ----------
�TI ���-��---I 1I -,.---�--�����������-------------Ir-----���--�
: :: : :
: :
TYPE X281 SA :
10K :::::::~: :~::::: :::::~::::::::::::::::::::::::::::::~::::::::::
T ~~~I~~ I~~~~ ~ ~? ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
11__11_111.L_ .1I ---�� ...It.IL.-------------�-��������-------1I--------���
1. _1_1_ !. - - ~ - - - - - - � _I_ I � � � - - - - - - - - - � - - - - - - - - - - - - - - - I- - - -
1K.1 I1 I 5 I 37 I57
99
.5 2 10
50
CUMULATIVE PERCENT
0077-9 Figure 5: An extreme value distribution of endurance monitor on units cycled in mass mode.
REFERENCES
1. R.K. Ellis, IEEE Electron Device Letters 13 (1982): pp. 330-333.
2. R.K. Ellis, H.A.R. Wegener and J. Caywood, International Electron Devices Meeting Technical Digest (1982): pp. 749-752.
3. J. Caywood and Reliability Engineering Staff, NOVRAM Reliability Report, Xicor publication RR-502A (1985).
4. D.S. Peck and O.D. Trap, Accelerated Testing Handbook, Technical Associates Publication.
This report is based on data collected through January, 1986.
9-42
APPENDIX A
Package Type
Product Plastic
Cerdip
LCC
OJc OJA OJc OJA OJc OJA
X2804A 50.0 81.0 20.5 36.0 -
-
X2816A 45.0 72.5 18.0 32.0 5.5 53.5 Thermal Resistance Table: 8JC and 8JA expressed in �c per watt
1.0�F
A1
As As "4 "3
A2 A1
Ao
PS-2
A1
Yee
As
Ae
As
Ag
"4
WE
A3
OE
A2
A1o
X2804A/2816A
A1
CE
Ao
1/07
l/Oo
I/Os
1101
I/Os
1102
1/04
Vss
1/03
Note A: CLK-1: Rows 1, 3, 5 ... (odd rows-CEA) CLK-2: Rows 2, 4, 6 ... (even rows-CEs) Such that: CLK-2 = CLK-1
Note B: (1) WE must always be hardwired to Vee (Pin 24) at device as shown. (2) All resistors: 1% metal film 1/4W (3) 1/0 pull-up: 2.0 Kn 1/0 pull-down: 1.4 Kn (4) Socket-to-socket isolation as shown. (5) Pin 19 (A10) and Pin 22 (Ag) are no connects (NC) for the X2804A.
X2804A/2816A (DIP) Burn-in circuit
0077-7
9-43
sEEAfrN-Ad~-~��I_V_h_
_
_
_
_
_
_
_v-1
V\_
----
CEA --1I
(CLK-1)
L I --
J C-Ee
I
(CLK�3>-
-~~K~djpO--lji-f1--u--
.
.
-q-10 -1
,;!l._;..l-!-�--1__.l
1
I
-
"
I
1 �-I I-'� I
1 '--
J- __
! : 1
0
8 10 12 16 20 24 28 30 32 36 40
TIME(�SEC)
Notes: (1) Ao-A10: binary sequencing address cycle: 40 �s. (2) WE disabled (tied to Vee at device). (3) V1N Low: 0.4V V1N High: 5.0V (4) Vee: 5.50V (5) X2804A: Ao-As X2816A: Ao-A10
X2804A/2816A (DIP) Burn-in timing diagram.
0077-8
9-44
RR-506A
J(iCI'
BYTE-WIDE NOVRAM*
(X2001/X2004) RELIABILITY REPORT
*NOVRAM is Xicor's nonvolatile static RAM device.
9-45
INTRODUCTION
This report is a summary of the reliability studies conducted .by Xicor to quality the X2001 /X2004 family of byte-wide NOVRAMs. The NOVRAM family consists of a static RAM memory array superimposed on a nonvolatile E2PROM memory array. The X2001 is configured as 128 x 8 bit and the X2004 is configured as 512 x 8 bit.
Reliability data was collected using the X2004 as the test device. However, the entire NOVRAM family shares similar circuitry throughout and devices are manufactured employing the same process criteria. Therefore, results gathered for the X2004 are directly applicable to the X2001 through similarity.
Figure 1 provides pinouts for both the X2001 and the X2004. Figure 2 shows the functional block diagram for the X2004 and Figures 3 and 4 illustrate the physical location of the various address bits for
both devices. A thermal resistance table, burn-in circuit schematic and timing diagram are included as additional reference information in Appendix A.
NE
Vee
NC
NC
WE
A1
A7
NC
Ao
As
As
A.
As
NC
A�
~
NC
A2
A3
OE
A,
A2
NC
Ao
A1
EE
uo.
Ao
1107
uo,
1105
llOt
1105
Yu
1104
Vss
1103
0078-7
Figure 1: X2004 and X2001 pin configurations.
Vee NC
NC
W!' lJE
iiil ?I"
llO, llOa llOs
uo. uo.
0078-8
NONVOLATILE E2PROM
~-ARRMAEM~ORYY -~/~7
AJ
'I
0 - I- STORE
A� ?"----
As
As
y
A1- .,L__
As-
~
ROW SELECT
STATIC RAM MEMORY ARRAY
vCl- I-
ARRAY RECALL
CE
6E-
STORE
ARRAY RECALL
l/Oe - - - - - r t - 1 ' ' -.'.,__.
1/01 ----..-++@...,_1>---I
1----
1/02 -----l-4--1--11-1'>---I INPUT
1/03 ----.-1.-l-4-1--11--::'>f ---I CONTROL
1---1----
COLUMN 1/0 CIRCUITS
1/04 ---...++4-14--l'>----<
DATA
1-----
I/Os --~1--1-++.1-+l--<-j::I'>'>------< I--
I-----
I/Os ----,...+~1-+++-1--lr>---1
1107 ----.--++-1-1+4-l-+1--"!:f> l -~---
filri- COLUMN SELECT
111
/1
Figure 2: X2004 functional block diagram.
9-46
0078-9
1/0
,.--~~~~~~~~~~~~~~~~~~--.
01010101010101012323232323232323
XsX"4X3 X2 X1 Xo As A1 A5 As A" A3
1/0
,--~~~~~~~~~~~~~~~~~~--.
54545454545454547676767676767676
0000 00
0000 0 1
0000 0
0 0 0 0 000 00
0 0 0 0 0 0
0 1 0
0001 11
0 0 10 0 0
0 0 10 0 1
0 0 10 10
00 0 11
0 0
0 0
0 0
0
00 1
0
00 11 11
l1'
l1'
'I
'I
_N 'I
~
l1'
l1'
'I
'I
l1'
'I
~
_j\
~
_j\
~
" ~
~
00 00
1 100 0 1
1 10 0 0
1 100 1
1 10 1 0 0
0 10 1 0 1 10
1 10 1 1 1
1 1 10 0 0
1 1 10 0 1
1 1 10 0
1 1 10 1 1 11 11 0 0
1 1
0 1
1 1
1 0
1111 11
_j\
~
_j\
~
_j\
~
_J\
~
0 10 10 10 10 10 10 10 1
0 0 1 10 0
0 0 1 10 0
0000 1
0 0 0 0
Each square equals one bit.
Yo=A1 Y1 =A2 Y2=Ao
10 10 10 10 0 0 1 10 0 10 0 0 0
0 10 10 10 00 1 10 0 0 0 0 0
0078-5
Figure 3: X2004 physical bit map.
9-47
1/0
1/0
01010101010101012323232323232323
X3 X2 X1 Xo As As A4 Aa
0 0 0 0
0 0 0
0 0
0
0 0
0
0 0
0
0 1
0
0
0
1 1
0 0 0
0 0
0 10
0 11
0 0
0 1
0
54545454545454547676767676767676
0 10 10 10 0 0 1100 1 0 000 1 11
0 10 10 10 0 0 1 10 0 1 0000 111
Each square equals one bit. Figure 4: X2001 physical bit map.
Yo= A1 Y1 = A2 Y2 =Ao
0 10 10 10 100 1 10 0 1 110 00 0
0 1010 10 10 0 1 10 0 1110 000
TECHNOLOGY
The X2001 /X2004 family is fabricated using N-channel floating gate MOS technology. The memory cell schematic is illustrated in Figure 5. It is comprised of a conventional six transistor static RAM cell and an E2PROM cell. This marriage of two
types of memories allows the NOVRAM to operate as a standard SRAM and provide nonvolatile storage of data. Data may be transferred in parallel from RAM into E2PROM (store operation) or from E2PROM into RAM (recall operation). Detailed device operation and timing requirements are contained in the Xicor Data Book.
Vee�
INTERNAL
STORE VOLTAGE
::f. CC3r_[y a, c~
~ Ce I
c,~
~c,
Figure 5: Schematic diagram of a NOVRAM memory cell.
0078-2
9-48
The E2PROM portion of the memory cell employs a proprietary textured poly technology-see Figure 6. Data is stored as the presence or absence of charge on the second level polysilicon which in turn acts as a gate for the read-out transistor. This sec-
ond level polysilicon is surrounded by ~ sooA of
Si02, electrically isolating it from the other layers, and allowing storage of charge on the second level polysilicon. In the E2PROM cell, charge is transferred on or off this storage gate in a controlled manner by means of a quantum mechanical phenomenon called Fowler-Nordheim tunneling.1
POLYSILICON (POLY 1)
� Semiconductor reliability pertains to several failure modes common to all semiconductors such as oxide rupture and microcracks. These are generally process related failure mechanisms.
� Endurance is the ability of a nonvolatile memory device to sustain repeated data changes.
Semiconductor failures and endurance failures can be further categorized as infant mortality failures, early life failures, random failures and end-oflife, or wearout, failures. These failures fit the classic bathtub curve illustrated in Figure 7. Xicor production test flows are designed to eliminate infant mortality failures and reduce the incidence of early life failures. All devices employed in the reliability study were selected from units that had completed the standard test flow in order to ascertain failure rates that might be experienced after shipment to a customer.
Figure 6: �2PROM cell structure.
0078-3
Charge transfer occurs only during store operations. The floating gate is either programmed by electron tunneling from Poly 1 to Poly 2, or erased by electron tunneling from Poly 2 to Poly 3. In order to extend endurance of the E2PROM cell, no charge transfer will occur if the state of the RAM cell and E2PROM are already the same.
Nonvolatile Memory Reliability Concerns
E2PROMs are unique semiconductors when examined from a reliability viewpoint. Most LSI semiconductor devices, such as microprocessors, are evaluated solely for semiconductor reliability; generic nonvolatile memories such as EPROMs or ROMs are evaluated for semiconductor reliability and data retention; but E2PROMs must be evaluated for semiconductor reliability, data retention and endurance.
� Data retention refers to the capability of a nonvolatile memory to retain valid data under worst case conditions.
INFANT MORTALITY
WEAROUT
RANDOM
TIME
Figure 7: Illustration of bathtub curve of failure rates.
0078-4
Retention
This test is sometimes referred to as storage bake, but Xicor prefers the term "data retention bake" because this better describes the principal function it serves in the case of electrically programmable nonvolatile memories.
In this test an erase pattern, or a charge that is the opposite of the state that would be read when the gate is at equilibrium, is stored on the floating gate of the E2PROM cells. The devices are then baked at 250�C with no bias applied. At intervals the memory is removed from bake and the nonvolatile data is recalled and verified. The data is not restored to the E2 array after the readouts in order to ascertain the worst case retention capability.
9-49
Lot#�
48 Hrs.
168 Hrs.
#Fail #In �#Fail #In
1
0
24
0
24�
2
0
30
0
30
3
0
50
0
50
4
0
50
0
50
5
0
50
0
50
Totals 0 204 0 204
Table I: 25C!'C data retention bake test results.
500 Hrs.
#Fail #In
0
24
0
30
0
50
0
50
0
50
0 204
1000 Hrs.
# Fail #In
0
24
0
30
0
50
0
50
0
50
0 204
1500 Hrs.
# Fail #In
0
24
0
30
0
50
0
50
0
50
0 204
2000 Hrs. Total
--�-�---
# Fail #In
Hours
0
24 48000
0
30 60000
0
50 100000
0
50 100000
0
50 100000
0 204 408000
Xicor has experimentally determined the activation energy (Ea) for the data loss mechanism of the E2 cell to be 1.7 eV. The mean time to data loss for this mechanism, which we believe to be the fundamental data loss mechanism of this technology, is 3 million years at 125�C. Table I illustrates the results of the data retention tests performed on the X2004.
Semiconductor Reliability
Table II is a compilation of MOS failure mechanisms and the normal test methods used to accelerate failures caused by each mechanism. The acceleration of failures is required in order to collect statistically useful data in the most expeditious manner.
High Temperature LifE!test
This test employs elevated temperatures to accelerate failure types related to infant mortality and random failures. Data is gathered at 125�C ambient temperature.
An erase pattern is initially stored in the E2PROM memory array and the RAM is sequentially addressed and written with alternating patterns of ones and zeroes. RAM is read after each write. Full AC and DC testing is done at 48, 168, 500, 1000, 1500 and 2000 hours to insure device functionality. After each of the first five tests the E2 array is once again erased and the devices continue the lifetest. The resultS of the tests are shown in Table Ill.
High Temperature Reverse Bias
This test is performed at 150�C, with the GND pin tied to OV and all other pins tied to Vee- Two sepa-
rate tests are performed; the first is with Vcc at
5.5V and the second is with Vee at 7.5V. This test is performed to expose failures which might occur as the result of the drift of mobile ions or latent defects in the gate oxides. The results of these tests are shown in Tables IV and V.
Failure Mechanism
Type
Activation Energy
Detection Method
Ionic
Infant/
Contamination Random/
Wearout
1.0eV
High Temp. Bias
Surface Charge
Wearout 0.5-1.0eV High Temp. Bias
Polarization Wearout 1.0eV
High Temp. Bias
Electromigration
Microcracks
Wearout Random
0.55eV
-
High Temp. Operating Life
Temperature Cycling
Contact Electromigration
Wea rout
0.9eV
High Temp. Bias/ High Temp.
Operating Life
Oxide Rupture
Infant/ 0.3eV Random
High Temp. Operating Life
Silicon Defects
Infant/ 0.3eV Random
High Temp. Bias
Oxide Defect Infant/ 0.6eV Leakage Random
High Temp. Operating Life
Electron Trapping in
Oxide
Wearout
0.06eV
Low Temp. High Voltage Operating Life
Table II: MOS failure mechanisms and test acceleration test methods.
9-50
Lot# 1
48 Hrs. #Fail #In 1[a] 131
168 Hrs. # Fail #In
0 130
500 Hrs. # Fail #In
0 81
2
0 187 0 187 0 112
3
0 206 0 206 0 101
4
0 105 0 105 0
0
5
0 189 0 189 1[a] 84
6
0 229 0 229 0 54
7
0 229 0 229 0 55
8
0 238 0 238 1[b] 63
Totals 1 1514 0 1513 2 550
[a] 1 unit-single bit oxide breakdown, Ea = 0.3eV [b] 1 unit-ionic contamination, Ea = 1.OeV
Table Ill: High temperature dynamic lifetest results.
1000 Hrs. #Fail #In
0 81 0 112 0 101 0 0 0 82 0 54 0 55 0 62 0 547
1500 Hrs. # Fail #In
0 81 0 112 0 100 0 0 0 82 0 52 0 55 0 62 0 544
2000 Hrs.
# Fail #In
0 81
0 112
0 100
0
0
0 82
0 52
0 55
0 62
0 544
Total Hours
170280 236600 218640 17640 182640 135400 139232 153900 1254332
Lot#
48 Hrs.
168 Hrs.
500 Hrs.
# Fail #In # Fail #In #Fail #In
1
0 25 0 25 0 25
2
0 15 0 15 0 15
3
0 15 0 15 0 15
4
0 15 0 15 0 15
5
0 15 0 15 0 15
6
0 25 0 25 0 25
7
0 25 0 25 0 25
8
0 25 0 25 0 25
Totals 0 160 0 160 0
Table IV: High temperature reverse bias lifetest results at 5.511.
160
1000 Hrs. #Fail #In
0 25 0 15 0 15 0 15 0 15 0 25 0 25 0 25 0 160
1500 Hrs. # Fail #In
0 24 0 24 0 25 0 73
2000 Hrs. # Fail #In
0 24 0 24 0 25 0 73
Total Hours
25000 15000 15000 15000 15000 49000 49000 50000 233000
Lot#
48 Hrs. # Fail #In
168 Hrs. # Fail #In
3
0
15
0
15
4
0
15
0
15
5
0
15
0
15
Totals
0
45
0
45
Table V.� High temperature reverse bias lifetest results at 7.511.
500 Hrs.
# Fail #In
0
15
0
15
0
15
0
45
1000 Hrs.
# Fail #In
0
15
0
15
0
15
0
45
Total Hours
15000 15000 15000 45000
9-51
Failure Rate Calculation and Reliability Prediction
High temperature lifetest and high temperature reverse bias data are used to calculate the failure rates. If we ignore the infant mortality failures (failures before 48 hours burn-in), we can then calculate the failure rate for the useful life of the device as follows:
Number of failures Failure Rate (Ts) = - - - - - -
Device hours (Ts)
Ts = Stress temperature
The above equation will be useful only to calculate the failure rate at the stress temperature under which the tests were performed. In most cases, the actual operating temperature of the device will be much lower; therefore, the equation needs to be modified to reflect the failure rate at the operating temperature. The failure rate for a given activation energy is calculated as follows:
Failure Rate (Td)i =
Where:
Failure Rate (Td) = Failure rate at temperature Td
DH(Ts) = Device hours at stress temperature
TAF(Ts.Td) = Temperature acceleration factor from Ts --. Td
i = A given activation energy
Ni = Number of failures for activation energy i
Ts = Stress temperature
Td = Desired temperature
VAF(Vs,Vd) = Voltage acceleration factor
from Vs__. Vd
Vs = Stress voltage
Vd = Desired voltage (5.5V)
The voltage acceleration factor is 1 for all failure mechanisms except TDDB (time dependent dielectric breakdown where Ea = 0.3eV). This can be calculated using Crook's equation:2
Where:
Es = Field (stress) = Vs/T0x
Ed = Field (desired) = Vd/T0x
Eet = Field constant = 0.062 Mv/cm Tox = Oxide thickness
The temperature acceleration factor for a given activation energy can be calculated using the Arrhenius equation:
TAF(Ts,Td) = exp[(Ea/K) (1/T8 - 1/Td)]
Where:
Ea = Activation energy (eV)
K = Boltzmann's constant (8.63 x 10-s eVl�K)
Ts = Stress temperature (junction) in �K
Td = Desired temperature (junction) in �K
The above equation is valid for only one .activation energy. To predict the total failure rate for the device at the desired temperature the calculated failure rates for each activation energy must be summed.
Total Failure Rate (Td) =
L TAF(Ts~~d)i DH(Ts) X
X VAF(V8 ,Vd)i
i
Using the above equation, we calculated the fail-
ure rate based on the experimental results. These
calculations are summarized in Table VI. We have
also included in that table a 60% upper confidence
level (UCL) calculation. This indicates that, with a
60% confidence, the actual failure rate will be below
that calculated. The equation below is used to de-
termine the 60% UCL.
Total Failure Rate (Td) =
"'
X2(1 -CL) (2N + 2)
~ 2 x DH(Ts) x TAF(Ts,Td)i X VAF(Vs,Vd)
i
Where:
X = The chi-square function
CL = The confidence limit (60%)
2N + 2 = The degrees of freedom
9-52
Ea in
eV
Total Device Hours
# of Fails
Equivalent Device Hours
@125�C
@150�C
@55�C
@70�C
0.3 1.18 x 106 2.78 x 105 1 2.91 x 107 1.97 x 107 0.6 1.18 x 106 2.78 x 105 0 4.65 x 107 2.15 x 107 1.0 1.18 x 106 2.78 x 105 1 5.38 x 108 1.34 x 108
Totals
2
Note: FIT x 0.0001 = failure rate per thousand hours.
Table VI: Summary of semiconductor failure rate calculations.
Calculated Failure Rate
FIT
@55�C @70�C
35
51
0
0
2
7
37
58
60% UCL Failure Rate FIT
@55�C 70 20 4 94
@70�C 105 43 14 162
In calculating the data presented in Table VI we used the actual junction temperature and not ambient temperature. We also made the conservative assumption of including the oxide leakage failure rate (Ea = 0.6eV). This failure mechanism should be included whether observed or not, since it is always anticipated in E2PROM technology. Had we only considered observed failures, as many vendors do, the 60% UCL failure rate at 70�C and 55�C would have been 119 and 74 FIT respectively versus the more conservative calculation of 162 and 94 FIT.
The results in Table VI are long term failure rates and were determined by excluding data for the first 48 hours of the dynamic lifetest. Infant mortality can be calculated from the data contained in Table Ill. There was one failure out of 1514 units tested.
Infant mortality rates and long term failure rates indicate Xicor's byte-wide NOVRAMs have attained failure rates comparable to, if not better than, those reported by semiconductor suppliers of standard volatile memory products. 5,6, 7
Endurance
A key factor in memory system reliability is the ability of the device.to sustain repeated data changes. In the static RAM portion of the NOVRAM there are only typical semiconductor reliability factors to consider. However, the E2 array is subject to limitations on the number of data changes a cell may undergo (its limit of endurance). Xicor considers the endurance limit of a memory is reached when the first single bit failure occurs. This limit of endurance
is expressed as the number of data changes the entire array can sustain before a single bit fails to change.
The endurance test employed is to alternately store all ones and zeroes in the memory array. The array is verified after each data change. Upon detection of the first single bit failure, the number of cycles the device endured is recorded.
Figure 8 contains the data for a typical monitor lot of X2004. The data is displayed in an extreme value distribution plot. Further details on endurance cycling and performance can be found in Xicor publications RR-504: Endurance of Xicor E2PROMs and NOVRAMs; and RR-510: Endurance of Nonvolatile Memories.
1M :__ :_:_ ~_; _; _________:_: _______________________ . _____ .c _________ _ ,--i-1-r-r-r�--------1-r------------------------------r----------
:~ I~! ~1 ~1~ ~~~ ~~~ ~~:~!~ ~~ ~ ~~~~~~~~ ~� ~ ~~~~~ ~~~ ~~! ~ ~ ~ ~!~~ ~~ ~
'
'
10K :__:_:_;_;_; ________:_; ______________________________ :__________ _
1,------,-1---,--1r----r1--r�-1�-r-------------- ---------1.----r-r------------------------------------------------------------------------------------------,,---------------------------------
11, _-_-1,_,1,-_11i_-_rI!-..r!I.-
_____ r-----
-
-
--I,' --I ',----------------------------------�----------------------------1'I --------------
---
-
-
1__1_1_1,._1._1 ________l_L------------------------------L----------
1 It I
I
I
I I
l
1__,_._,__ t_t _____ - - - ' - ' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ' - - - - - - - - - - -
1 !It I I
I I
I
I 111 l I
I I
I
''
'
1K.1 11 I 5 I 37 J 57
99
.5 2 10
50
CUMULATIVE PERCENT
Figure B: Extreme value distribution plot for X2004.
0078-12
9-53
Low Temperature Dynamic Lifetest
In addition to the preceding tests which pertain to standard failures related to nonvolatile memories, Xicor undertook a test to determine if hot electron trapping was of concern to this device family. The low temperature dynamic lifetest is functionally identical to the high temperature dynamic lifetest but with the ambient temperature at - 40�C. This test is intended to detect hot electron trapping in the gate oxide. As can be seen by the test results in Table VII, there was no indication of hot electron trapping in these devices.
Environmental Testing
This group of tests is performed on plastic packages to insure that excessive humidity and ambient vapors will not cause failures and to insure that temperature cycling will have no adverse effects on the materials used.
The three major failure modes for plastic packaged devices under moisture test are:
� Mobile Ions-Ions on the passivation glass are made more mobile by humidity. If enough charge transfer occurs, a device parameter could be altered, or a parasitic transistor could be introduced, degrading device performance.
� Chemical Corrosion-Phosphorous is commonly used in small quantities in passivation and under metalization layers. Phosphorous, when combined with water molecules, produces phosphoric acid which may etch away aluminum lines.
� Electrolytic Corrosion-When a voltage potential exists between two adjacent metal lines under enhanced surface conditions, such as presence of moisture, an electrolytic corrosion process may be triggered. This condition could result in an open metal line.
Autoclave and 85�C/85% relative humidity tests are conducted to test for these failure modes.
Autoclave
Autoclave, or pressure pot testing, subjects a device to a two atmosphere steam environment. This test will accelerate mobile ion drift, chemical corrosion, and to some extent, electrolytic corrosion. The test results are summarized in Table VIII.
Lot#
48 Hrs.
168 Hrs.
# Fail #In #Fail #In
2
0
30
0
30
3
0
25
0
25
4
0
25
0
25
5
0
25
0
25
Totals 0
105
0
105
Table VII: Low temperature dynamic lifetest results.
500 Hrs.
# Fail #In
0
30
0
25
0
25
0
25
0 105
1000 Hrs.
# Fail #In
0
30
0
25
0
25
0
25
0
105
1500 Hrs.
#Fail #In
0
30
0
25
0
25
0
25
0 105
2000Hrs.
# Fail #In
0
30
0
25
0
25
0
25
0
105
Total Hours
60000 50000 50000 50000 210000
Lot#
48 Hrs.
144 Hrs.
#Fail #In #Fail #In
6
0
48
0
48
7
0
49
0
49
8
0
50
0
50
Totals 0
147
0
147
[a] 2 units-open pins, chemical corrosion
Table VIII: Autoclave test results.
240 Hrs.
#Fail #In
0
48
0
49
0
50
0
147
336 Hrs.
#Fail #In
0
48
0
49
2[a] 50
2
147
432 Hrs.
#Fail #In
0
48
0
49
0
48
0
145
528 Hrs.
# Fail #In
0
48
0
49
0
48
0
145
Total Hours
25344 25872 26016 77232
9-54
85�C and 85% Relative Humidity
85/85 testing is performed to determine the life exp~c~ancy ~f devices in high temperature and high hum1d1ty environments. This test will accelerate the three environmental failure modes. It is an especially good test for detecting electrolytic corrosion. . 85(85 tests can be performed in two ways. The
first 1s by supplying voltage to Vcc with all other pins alternately biased at OV and + 5V. In this meth-
od, heat generated by power dissipation can reduce the relative humidity on the die surface to as low as 45%. The second method is to test the device with
Vcc at OV and all other pins alternately biased at OV and + 5V. This provides a potential between metal
lines and insures maximum humidity at the die surface. The second method is more stringent and is the method used to test the X2004. The results of the test are listed in Table IX.
Lot#
168 Hrs.
500 Hrs.
# Fail #In # Fail #In
6
0 50 0 50
7
0 50 0 50
8
0 50 0 50
Totals 0 150 0
Table IX 8S'Cl85% test results.
150
1000 Hrs. # Fail #In
0 50 0 50 0 50 0 150
Temperature Cycling
This test subjects the devices to temperature ex-
tremes of - 65�C to + 165�C. This test is performed
to stress the package to detect poor bond wire attachment, and to determine if there is a potential problem due to thermal mismatch between the die and the package material that could cause device failure. The results of this test are tabulated in Table
x.
Lot# 168 Cycles 500 Cycles #Fail #In # Fail #In
6
0 50 0 50
7
0 50 0 50
8
0 50 0 50
Totals 0 150 0 150
Table X- Temperature eye/mg test results.
1000 Cycles #Fail #In
0 50 0 50 0 50 0 150
Lifetest Monitor
. In order t? ensure the continuous supply of the
h1g~e~t q~ahty and most reliable product possible, a periodic hfetest monitor system is maintained. This monitor systematically samples current production material, and subjects it to stress testing designed to induce failures.
This monitor serves a dual purpose. First, it is
t? us~d mo~it~r the device infant mortality rate
which 1s an indicator of process or manufacturing defects. If an unusually high failure rate were to be observed, corrective action could be initiated before defective units were ever shipped to the customer. Second, long term failure rates can also be monitored. This establishes a method to track and maintain long term reliability.
Table XI shows monitor results for dynamic life-
tests at + 125�C from 1987 through 1988.
48 Hrs.
168 Hrs. 500 Hrs. 1000 Hrs.
# # %# # %# # %# # % In Fail Fail In Fail Fail In Fail Fail In Fail Fail
686 3 0.44 296 0 0.00 296 1 0.34 295 0 0.00
Table XI: DL T monitor results from 1987 through 1988.
SUMMARY
The data presented here shows excellent data retention characteristics. Reliability testing shows no retention failures. The X2001 /X2004 family exhibits low semiconductor failure rates and high end-of-life endurance figures. The endurance characteristic of the X2004 is typically over 100,000 cycles. Inherent data retention is in excess of 100 years.
9-55
REFERENCES
1. R.H. Fowler and L. Nordheim, Proceedings of the Royal Society of London, A119, (1928); pp. 173181.
2. Dwight L. Crook, 17th Annual Reliability Symposium, (1979); 1-7.
3. H.A.R. Wegener, Endurance of Xicor E2PROMs and NOVRAMs, (XicC>r, 1984).
4. Bruce Euzent, 2115/2125 N-Channel Silicon Gate MOS 1K Static RAMs, (1976) Intel Reliability Report RR-14.
5. Chieh Lin Ping, Reliability of N-Channel Metal Gate MOS/LSI Microcircuits, (1982), National Semiconductor.
6. Bruce Euzent and Stuart Rosenberg, HMOS Reliability, (1978), Intel Reliability Report RR-18.
This report is based on data collected through March, 1989.
9-56
APPENDIX A
Package Type
Product Plastic
Cerdip
LCC
OJc OJA OJc OJA OJc OJA
X2001 42.7 77 19.5 34.5 - -
X2004 39.5 64.3 16.5 33.5 5.0 46.5 Thermal Resistance Table: 8Jc and OJA expressed in �c per watt.
1.0�F
, - - - - - - Ao-Aa)(
1 CEA
(CLK-1) ' " - - - - - - - - - - "
I
A1-+--------1 A& - + - - - - - - I I As-+--------1 A.t-+--------1
A3-+--------< A2--+--------1 Al-+------< Ao -+---=---..,...,...,,.,....-1
4
12 16 20 24 28 32 36 40
TIME(�SEC)
Notes: (1) Ao-Aa: binary sequencing cycle period: 40 �s.
(2) NE disabled (tied to Vee at device).
(3) Low state: 0.4V max. High state: 5.0V typ. Vee: 5.50V
0078-11
X2004 (DIP) Burn-in timing diagram.
0078-10
Note A:
CLK-1: Rows 1, 3, 5, ... (odd rows = CE-A) CLK-2: Rows 2, 4, 6, ... (even rows = CE-8) CLK-2 = CLK- 1
Note B: (1) NE (Pin 1) must be hardwired to Vee (Pin 28) at device as shown.
(2) All resistors: 1% metal film 1/4W
(3) All I/O's:
(4) Socket-to-socket isolation as shown. X2004 (DIP) Burn-in circuit
0078-13
9-57
NOTES
9-58
lien,
RR-507A
0079-1
X2864A
RELIABILITY REPORT
By Troy Kaysser
and Lori J. Purvis
9-59
INTRODUCTION
The X2864A is a 64K bit electrically erasable programmable read only memory, E2PROM, organized BK x 8. This memory operates on a single 5V power supply for all operations. Figure 1 provides the 64K pin� configuration; Figure 2 shows th.e functional block diagram; Figure 3 illustrates the physical location of� the various address bits. The thermal resistance table, burn-in circuit and a timing diagram are include in Appendix A for� your reference.
The X2864A is manufactured using Xicor's rugged, textured poly technology. Xicor has shipped more than 20 milli9n memories manufactured with this technology. Because the X2864A is a mature part which has been in volume production for some time, this report contains data from the production reliability monitor as well as reliability qualification data.
NC
A,
AG llOo 110, 1102
Vss Figure�t: X2864A Pin configuration.
Ao -A12 ADDRESS
INPUTS
Figure 2: X2864A Functional block diagram.
x
BUFFERS LATCHES
AND DECODER
65,536-BIT E2PROM ARRAY
y
BUFFERS LATCHES
AND DECODER
CONTROL LOGIC AND TIMING
l/Oo-1101 DATA INPUTS/OUTPUTS
0079-10
Vee
WE
NC
Ae At An OE A.o
~ 1101 1101 llOs 1104 1103
0079-9
9-60
----1.N\f
,....,.......,. N"
X7 Xs X5 X4 X3 Xz X1 Xo A12 A11A1 oAg As As As A1
0000 00
0000 0 1 0000 10 0000 11 000 100 000 10 1 00 0 1 10 000 1 11 00 10 00 0 0 10 0 1 00 10 10 00 10 1 1 00 1100
J\~
t-.N"~
0 0 0 1 11 1 0
~
t-. N
It-.~ ~
0000000000000000 00000000 1111111 0 00 0 1 1110000 1111 0011001100110011 0 10 10 10 10 10 10 10 1
Each square equals one byte. Figure 3: X2864A Physical bit map.
Y4=A4 Y3=A3 Yz=Az Y1 =A1 Yo=Ao
1111111111111 11 0000000011111111 0000111100001111 0011001100110011 0 10 10 10 10 10 10 10 1
0079-11
9-61
In the next section the operation of the textured poly E2PROM cell is described. The remainder of the report covers experiments designed to probe the reliability of the part beginning with the two attributes unique to E2PROMs: data retention and endurance. The data show that at 55�C retention contributes approximately 1 FIT to the device failure rate while endurance contributes about 1O FIT in a typical application. After the E2PROM specific experiments, standard accelerated lifetest and accelerated package tests are reported in order to complete the study on this component. These results are used to predict operating failure rate. The predicted result is 50 FIT at 55�C, 60% UCL.
TEXTURED POLY E2PROM CELL
The cross sectional structure of a �textured poly cell is shown in Figure 4. It consists of 3 layers of poly with overlap forming three transistors in series. The floating gate transistor is in the middle formed by poly 2. The floating gate is surrounded by silicon dioxide for high retention. Programming is achieved by electrons tunneling from poly 1 to poly 2 and erase is achieved by electrons tunneling from poly 2 to poly 3.
steered high, the large voltage drop occurs between poly 1 and poly 2 causing electiOns to tunnel from poly 1 onto the floating gate charging it negative.
DATA RETENTION
Textured poly tunneling structures have a significant advantage in data retention in comparison with those employing flat surfaces and thin oxides. One basis for this advantage is illustrated in Figure 5, in which the current-voltage .(J-V) characteristics of a tunneling device which employs a thin oxide between planar surfaces and, a tunneling device which employs a thick oxide between textured silicon surfaces, are compared. For this comparison we match the currents in the high current region since most memories are designed to program in about the same time period ( - 1O ms). As can be seen, the same current can be obtained from a smooth surface with 125A thick tunnel oxide or from a textured surface with an 825A thick tunnel oxide. Note however, that at lower values of applied voltage typical of read and storage conditions, the current emitted from a textured surface is approximately four orders of� magnitude .lower than that from a smooth surface.
10-4
COMMON DESIGN POINT FOR 1ms WRITE 10-6
0079-2 Figure 4: Cross sectional.structure of a textured poly memory cell.
In reading the datum stored in the cell the poly 3 select transistor is enabled; �The . current flow through the cell is determined by the charge state of the poly 2 floating gate. If it is charged positively when the bit is selected, current flows through the cell which is sensed as a "1 ". If it is charged negatively, a "O" results. During writing the poly 3 is set to a high voltage (> 20V). The poly 2 floating gate is capacitatively steered either high� or low. If the floating gate is steered low, the large voltage drop occurs between poly 2 and poly 3 causing electrons to tunnel off the floating gate, leaving it in a positively charged erase state. If the floating gate is
10-s
~
E 10-10
~ .
CL
E
..,.!!10-12
f 10-14
~ TEXTURED SURFACE
lox= BASE:
825A
600A
HEIGHT: 300A
NUMBER: 70/�2
11
13
15
17
19
21
VA (VOLTS)
0079-3
Figure 5: Comparison of calculated tunneling J-V curves for emission from a planar and a textured structure. The devices were designed to have the
same emission in the high current regime where programming takes
place.
9-62
These differences may become even more significant as devices are scaled. It is clear that, in order to scale the memory properly, lower programming voltages are needed so that the isolation widths and device channel lengths can be reduced both in the memory array and in the peripheral circuitry. However, for a typical part which stores data in 3 ms and must retain it for 1O years, the tunneling current under storage and reading conditions must be at least 1011 times smaller than under programming conditions because the retention time is 1011 times longer than the storage time. Actually, for margin, one would design for a difference in currents of 101 s to 1014. For planar surface tunneling structures, this may be a difficult design constraint because the slope of the J-V curve is fixed, which means that the maximum allowed read voltage drops with the programming voltage on a volt-for-volt basis, not proportionately. On the other hand, textured surface tunneling structures, in their current manifestation, have a steeper J-V characteristic than planar ones and the J-V characteristic of a textured structure can be tailored to yield a steeper curve if desired. This means that for a given maximum read voltage, a textured structure requires a lower programming voltage which leads to better scaling.
To verify the excellent data retention expected of Xicor memories, a study was carried out to measure data loss as a function of temperature. Figure 6 shows log cumulative data loss vs. log time for 100 samples of X2210's at each of three temperatures. Data loss is defined as occurring when the first bit in the array loses data. As shown in Figure 6, high temperatures were required to obtain appreciable
10'
325�C
102 5 10
20 304050607080
EA=1.7eV
3x106 YEARS AT 12s�c 90 95
% CUMULATIVE FAILURES
0079-4 Figure 6: Log cumulative data loss vs. log time for three storage temperatures on samples of 100 X2210's. Data loss is defined to occur when the first bit in an array loses data.
data loss in experimentally useful times. Note that even at 300�C, 2000 hours ( - 3 months) are required to see data loss. Figure 7 shows the result of calculating failure rates based on these results and plotting vs. inverse temperature. Since the rates fall on a straight line, we can extract an activation energy and extrapolate to lower temperatures. The result is that the experimental value of the activation energy is 1.7eV and the mean time for data loss for this mechanism (which we believe to be the fundamental loss mechanism of this technology) is 3 million years for retention at 125�C.
100
50
~
:c 20
0
o0 .
~c 10
w ~ a: w
� 5
...I
~
2
EA=1.7� 0.1eV
MTBF =3,000,000 YEARS
AT 12s0 c
250�
300� 350� 400� TEMPERATURE (�C)
0079-5 Figure 7: Log data loss rate vs. inverse temperature for X2210's.
Although this retention data was based on small NOVRAMs*, it applies equally to Xicor E2PROMs which share common floating gate storage mechanisms and processes with the NOVRAMs. In fact, the real cause for retention failures observed in E2PR0Ms is not the intrinsic mechanism reported above, but single bit data loss arising from the same oxide defects which have been observed in EPROMs and shown to have an activation energy of 0.6eV.1
In order to investigate the probability of occurrence of the extrinsic oxide defect data retention failures, a topological checkerboard pattern was written into samples of X2864A devices from a number of lots. These devices were stored at elevated temperatures with periodic readouts to verify to data integrity. The hermetic packaged devices were stored at 250�C while the tests on the plastic encapsulated devices were conducted at 150�C because
*NOVRAM is Xicor's nonvolatile static RAM device.
9-63
Package Type PLCC
PDIP
Totals
Lot ID
48 Hrs.
01 0 27
02 0 28
01 0 50
02 �o 50
03 0 50
0 205
1so0 c
168 Hrs.
500 Hrs.
0 27 0 27 0 28 0 28 0 50 0 50 0 50 0 50 0 50 0 50 0 205 0 205
1000 Hrs.
0 27 0 28 0 50 0 50 0 50 0 205
1500 Hrs.
0 27 0 28 0 50 0 50 0 50 0 205
2000 Hrs.
0 27 0 28 0 50 0 50 0 50 0 205
Package
Lot
Type
ID
Cerdip
01
02
03
04
05
Monitor
Totals
[a) = Cracked die
[b] = Single bit retention failure: 0.6eV
Table I: Data retention bake.
48 Hrs.
0
50
0
50
0
50
0
50
0
50
0
350
0
600
2so0 c
168 Hrs.
0
50
0
50
0
50
0
50
0
50
0
350
0
600
500 Hrs.
0
50
0
50
0
50
0
50
0
50
0
350
0
600
1000 Hrs.
0
50
0
50
0
50
1 [a]
50
0
50
1 [b]
350
2
600
the plastic epoxy molding compound won't survive 250�C storage. The data from this test are displayed in Table I. The results show very good data integrity. This is in line with a recent. report which indicated that E2PROMs have a lower incidence of oxide defects than EPROMs.2 This is probably because the multiple high voltage writes which occur during an E2PROM manufacturing flow provide an effective screen for many oxide defects which would otherwise appear as retention failures.
ENDURANCE
Endurance is defined as the ability of a nonvolatile memory to withstand repeated nonvolatile data changes while remaining within specification. As is discussed in more detail in Xicor reliability report RR-510, endurance in Xicor's E2PROMs is limited by two effects, electron trapping in the tunnel
oxide and. oxide breakdown. Electron trapping in the tunnel oxide is the major failure mechanism in the endurance range of more than - 1Q5 data changes. Oxide breakdown tends to be the major failure mechanism for devices which have endurance of less than - 1Q5 data changes.
Xicor uses two tests to evaluate the endurance of its E2PROMs. One test utilizes special test modes to enable all bits in a unit to be changed simultaneously. This test is used to measure the ultimate endurance of a sample of units. For reasons discussed in RR-510, this test tends to give a somewhat pessimistic estimate of trapping limited endurance �and a slightly optimistic estimate of oxide breakdown limited endurance. Figure 8 shows an endurance distribution sample from a broad range of X2864A material. In order to accurately monitor the oxide defects, which appear as infant mortality endurance failures, Xicor conducts a test in. which
9-64
each page is written to 10,000 times on a page-bypage basis. Figure 9 shows the distribution of failures found from a sample of 1034 units coming from at least 10 runs. As shown in RR-51 O these failures are expected to contribute approximately 1O FIT to the failure rate in typical applications.
I
ti I
I
I
'11 '
' I
10M :__:_:_:_:_: ________:_: ______________________________ : _________ _
i i l ,--,-,-r--r-r----- ---,-r------------------------------r�---------
:~? ~ ~ ~ ~ ~ ~ ~ ~ ~ ~:~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~:~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
,__ ,_,_ .. _.. _.. _____ ---1-1-------------------------------'-----------
_LJJ.J.WU-w..-���.. � : � ,__,_,_,__!._i _____ ---''-' '-------------------------------�'----------' I
! !ffll~c;I'TI~ ! ! ! 1Ml'-:--::':"'="-':-:-~-:-:--:-:�-:-,..,...--,--:-::=:dd:"'-~------,-,-:-:-,,..,.-,--,-::-::-::c~~-------,-,,...,
: n 100K
: :: ~ : : ::::::e; :; :;: : :::
:
:
: :
:::;:
:
::
::
::
TYPE
: : :::
X2864A
:: :: :: ::
:
:
:
::
::
:::~::::
::
::
:
:
~ J~ ~ ~ 1~1~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~:~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
1��1.1.L.L.L----- ___t.L------------------------------'-----------
1 .I I I
I
I
I I
I
I --I-I--I --I --I ----- ---t,-I ,-------------------------------,I -----------
'' ''
' '
10K.1 I 1 I 5 I 37 157
99
.5 2 10
50
CUMULATIVE PERCENT
0079-6 Figure 8: An extreme value distribution of endurance monitor on units cycled in mass mode.
~
-f'
lL _lJ
lL
102
.01
0.1
CUMULATIVE FAILURES (3)
0079-7 Figure 9: Cumulative failures occurring at less than 10K writes/page of complete memory for a sample of 1034 X2864A chosen from more than 10 diffusion lots.
In order to accelerate device failure rate, Xicor runs high and low temperature dynamic lifetests and a high temperature reverse bias test. High temperature dynamic lifetest accelerates the vast majority of the failure mechanisms which might effect these products. The exceptional mechanism is hot electron trapping in the gate oxide for which the worst case is at low temperature. Test pattern studies show that hot electron trapping is not expected to be a problem in the X2864A technology which uses relatively conservative transistors of 3 microns gate length and 750A gate oxide thickness in the periphery. To verify this prediction, units were operated dynamically for 1000 hours at - 40�C. The data for this stress are exhibited in Table II and show no failures as expected.
The procedure that Xicor uses in dynamic lifetest is to load a topological checkerboard pattern into the units. The units are continuously read at temperature while the addresses are incremented in a binary sequence. At each readout the data integrity is first verified and then all parameters and functions (read and write) are verified across the specified voltage range. Finally the checkerboard pattern is reloaded and the units returned to the stress. The procedure in HTRB stress is similar except that during the stress all pins are biased high.
Package Lot
500 Hrs.
1000 Hrs.
Type
ID
#Fail #In # Fail #In
Cerdip 01, 2, 3 0
75
0
75
Q4
0
25
0
25
Q5
0
25
0
25
Totals
0 125 0 125
Table II: - 40' C dynamic lifetest.
The data for these stresses are exhibited in Tables Ill and IV. In these tables the data are segregated by package type for each of the several types tested. This data was collected over the period June 1986 through March 1987.
LIFETESTS
In addition to the endurance and data retention tests specifically targeted at properties unique to nonvolatile memories, Xicor conducts the standard battery of product life and package integrity tests.
9-65
Package Lot
48 Hrs.
Type
ID
#Fail #In
PDIP
05
3[a] 102
06
0
102
07
0
102
Monitor
0
3966
PLCC Cerdip
03
0
500
04
1[cl 912
01,2,3 1[d] 4997
04
0
874
05
0 1282
Monitor
0
1498
Totals
5 14335
[a] = Ionic contamination 1.OeV [b] = Data retention 0.6eV [c] = Marginal V1N [d] = Cracked die
Table Ill: 125'C dynamic lifetest.
168 Hrs.
# Fail #In
0
99
0
102
0
102
0 3962
0
446
0
843
0 4997
0
874
0 1280
1[a] 1492
1 14197
500 Hrs.
#Fail #In
-
-
-
-
-
-
0
640
-
-
-
-
0 300
0
100
0
100
2[a] 240
2 1380
1000 Hrs.
#Fail #In
-
-
-
-
--
1[b] 560
-
-
-
-
0 300
0
95
1[a] 97
0 238
2 1290
1500 Hrs.
#Fail #In
--
--
-
-
-
-
--
-
-
0 294
0
95
0
97
-
-
0 486
2000 Hrs. #Fail #In
- .-
--
--
-
--
0 294
0
94
0
95
--
0 483
Package
Lot
48 Hrs.
Type r-
PLCC
ID
#Fail
#In
03
0
52
PDIP
01
-
02
-
03
-
Cerdip
01
-
02
-
03
-
-
04
-
-
05
-
Totals
L .�.
0
52
[a] = Ionic contamination 1.0eV
Table IV: t5(J'C static lifetest
168 Hrs.
#Fail
#In
1 [a]
52
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
52
500 Hrs.
#Fail
#In
-
-
4[a]
25
0
25
0
25
0
45
0
45
0
45
0
45
1 [a]
45
5
300
1000 Hrs.
# Fail
#In
-
0
21
0
24
0
24
0
45
0
45
0
45
1 [al
45
0
44
1
293
PACKAGE INTEGRITY TESTING
The tests Xicor employs to ascertain the integrity of the packages differ between hermetic and plastic encapsulated devices. For hermetic devices Xicor follows the tests specified in MIL-STD-883C, Method 5005 for group C & D evaluation of packaged devices. Tables V and VI contain the results for Cerdip and LCC packages, respectively.
For plastic encapsulated devices the military standard tests are not really applicable. Instead Xicor uses autoclave and 85/85 stresses to test for corrosion effects in the non-hermetic plastic packages.
Xicor also makes extensive use of temperature cycling to test for die cracking or lead shear which might arise as a result of the mismatch of thermal expansion coefficients which exists between the epoxy molding compound and the silicon die. The autoclave tests are conducted by storing units in steam at 2 atmospheres (15 PSIG) and 121�C. The 85/85 tests are conducted with all inputs and outputs biased at 5V. These are conducted both with
Vcc powered and unpowered since there is some
uncertainty as to which case is worst. The tempera-
ture cycling is done between -65�C and + 150�C in
compliance with MIL-STD-883C, method 1010, condition C. The results are exhibited in Tables VII, VIII, and IX and show very good results.
9-66
Test Temperature Cycling
Constant Acceleration
Seal -Fine -Gross Lead Integrity
Seal -Fine -Gross Thermal Shock
Temperature Cycling
Moisture Resistance Seal -Fine -Gross Internal Water Vapor Content Mechanical Shock
Vibration Variable Frequency
Constant Acceleration Seal -Fine -Gross Salt Atmosphere Seal -Fine -Gross Adhesion of Lead Finish
Method 1005 2001 1014
2004 1014
1011 1010 1004 1014
1018 2002 2007 2001 1014
1009 1014
2025
Conditions Test Condition C
(10 cycles, - 65�C to + 125�C)
Test Condition E (30,000 y, Y1 axis only) Test Condition B
(5 x 10-7 cc/min)
Test Condition C Test Condition 82 (Lead Fatigue)
Test Condition B Test Condition C Test Condition B
(15 cycles, -55�C to + 125�C)
Test Condition C (100 cycles)
Test Condition B Test Condition C 5,000 ppm Maximum Water Content at 100�c Test Condition B (1500 g peak, 3 axis) Test Condition A (20g peak, 3 axis) Test Condition E
Test Condition B Test Condition C Test Condition A
Test Condition B Test Condition C
Lid Torque
2024
Table V.� Environmental test for 28-lead cerdip package.
LTPD 15
15 15
-
15
15 15
Accept# 0/15
0/15
0/15
013 or1/5 0/15 0/15 0/15 0/15 0/15 0/15
0/15 (#of leads from 3 devices)
Results 0/120
0/120
1/120 0/119 0/60
0/60 1/60 0/172
0/172
0/172
1/171 0/171 0/12
0/197
0/197
0/197
4/197 2/193 0/102
0/102 0/102 0/45
0/15
9-67
Test Lead Integrity
Method 2004
Seal -Fine -Gross
Thermal Shock
1014 1011
Temperature Cycling
1010
Moisture Resistance
Seal -Fine -Gross
Internal Water Vapor Content
Mechanical Shock
1004 1014
1018 2002
Vibration Variable Frequency
2007
Constant Acceleration
2001
Seal -Fine -Gross
1014
Salt Atmosphere
1009
Seal -Fine -Gross
1014
Table VI: Environmental test for 32-pad LCC package.
Conditions Test Condition 82 (Lead Fatigue)
Test Condition B Test Condition C Test Condition B
(15 cycles, -55�C to + 125�C)
Test Condition C (100 cycles)
Test Condition B Test Condition C 5,000 ppm Maximum Water Content at 100�C Test Condition B (1500 g peak, 3 axis) Test Condition A (20g peak, 3 axis) Test Condition E
Test Condition B Test Condition C Test Condition A
Test Condition B Test Condition C
LTPD 15 15
-
15
15
Accept# R_e_s_u_l_t_s__, -��-���
1/15
0/45
1/15
0/3 or1/5 0/15
0/15
0/45 0145 0/120
0/120
0/120
0/120 0/120
0/9
0/120
0/120
0/120
0/120 0/120 0/83
0/83 0/83
48 Hrs.
#Fail #In
Monitor
0
1577
01
0
80
02
0
80
Table VII: Autoclave.
96 Hrs.
#Fail #In
0
1577
0
80
0
80
192 Hrs.
#Fail #In
--
0
80
0
80
288 Hrs.
#Fail #In
--
0
78
0
80
384 Hrs.
#Fail # In
--
0
78
0
79
521 Hrs.
#Fail #In
--
0
78
0
79
9-68
Vee= 5.5V
Vee= ov
500 Hrs. 1000 Hrs. 500 Hrs. 1000 Hrs.
# Fail #In #Fail #In #Fail #In #Fail #In
01 0 99 0 99 0 98 0 95
02 0 99 0 97 0 99 0 99
03 0 99 0 99 0 99 0 99
04 0 99 0 99 0 98 0 98
05 0 90 0 90 0 90 - -
05 0 110 0 110 0 111 0 110
Table VIII: 85185.
Package Lot 200Cycles 500Cycles 1000 Cycles
Type
ID #Fail #In #Fail #In # Fail #In
PDIP
01 0 80 0 78 1 78
02 0 80 0 80 0 80
03 0 78 0 78 0 78
04 0 78 0 77 0 77
05 0 78 0 78 0 78
Monitor 0 623 0 623 -
-
Totals
0 1017 0 1014 1 391
Table IX- Temperature cycle.
FAILURE RATE PREDICTION
It has been long observed that failure rates follow a bathtub shaped curve. There is an infant mortality region characterized by a rapidly declining failure rate as "weak" parts are eliminated from the populations, a random failure region characterized by an invariant or slowly declining failure rate, and a wearout region characterized by an increasing� failure rate as the units reach end-of-life. Xicor, and most other conscientious manufacturers, designs processes so that end intrinsic wearout failures are never seen over the normal life of the part and develops manufacturing flows to minimize the number of weak parts which are produced.
The classic parameter used to accelerate failure rates is temperature. It is known that a very broad
class of failure mechanisms have a temperature dependence proportional to exp(-E8 /kT) where Ea is called the activation energy, k is Boltzmann's constant, and T is the absolute temperature. This is true because a number of. basic physical phenomena such as diffusion rates and chemical reaction rates have this dependence. If the activation energy is known for the failure mechanisms in question, then the failure rates arising from these mechanisms can be measured at elevated temperature and extrapo~ lated back to lower operating temperatures. The relationship which allows one to translate failure rates from one temperature to another is known as the Arrhenius relation. Figure 10 illustrates this relation for a number of common values of activation energy.
10-a
10c7
a: 10-6 ~ ~u; 10-s
z
0
Ei 10-4
.aww..:.
() 10-3
~
10-2
10
250 200 150
100
50
25
TEMPERATURE (�C)
0079-8
Figure 10: Acceleration factor vs. temperature calculated for various
activation energies from Arrhenius relation.
�
There is no simple, one-step formula for inferring a predicted failure rate from the experimental data. Instead, the failures of each individual activation energy must be treated differently. The first step is to calculate the equivalent device hours at the ambient
9-69
Activation Device Hr. Energy at 125�C
0.3eV 5.097 x 106 0.6eV 5.097 x 106 1.0eV 5.097 x 106
Totals
Table X- Failure rate calculation.
Equivalent Hr. at 55�C
2.504 x 107 1.242 x 108 1.068 x 109
Equivalent Hr. at 70�C
1.716X107
5.806 x 107 2.971 x 108
Failures
0 1 4
60% UCL55�C
36 16 5 57
Failure Rates (FIT)
60% Best Est UCL 70�C 55�C
54
28
34
13
17
4
105
45
Best Est 70�C 41 29 15 85
temperature of interest, utilizing the Arrhenius relationship discussed earlier. This calculation should be carried out for every mechanism observed or expected. For example, the calculation for the 0.3eV activation energy oxide rupture mechanism should be carried out whether this failure mechanism is observed or not, since this mechanism is always anticipated in MOS integrated circuits. The extrapolation should be carried out utilizing the junction temperature at the ambient temperature of interest and not the ambient temperature itself. The upper confidence limit is then calculated for the failure rate for each activation energy. The upper confidence limits for the various activation energies are then summed for a total failure rate prediction. The meaning of the "upper confidence level" is that with a certainty, or probability, of a certain level we can say that the true value is less than the stated value. Thus, the confidence level rate calculated is non-zero even for the case where no failures are observed because we can't be sure that there will be none. This procedure is discussed in more detail in RR-506.
The infant mortality failure fraction is calculated from the 48 hour, 125�C burn-in data. This corresponds to the failure expected in the first several weeks of operating life. The data shows that 5 units failed out of 14,335 units tested for an infant failure fraction of 0.03% or 349 ppm.
The long term (random)-failure rate is estimated from the 125�C dynamic lifetest data in Table X. These calculations sum the data from all package types tested. The results show the predicted failure rate at 55�C 60% UCL to be 50 FIT (or 0.0050%/ 1000 Hr). One FIT is one failure in 1Q9 hours. Even
though these calculations are based on over 5 million device-hours at 125�C, the failure rate is still dominated by the gate oxide failure mechanism which was not observed. If this mechanism were to be excluded, the predicted failure rate would drop approximately in half.
SUMMARY
In this paper, the physical operation of Xicor E2PROMs is discussed in some detail. Data on data retention and endurance of the X2864A are presented which show that they are expected to contribute about 1 FIT and 1O FIT, respectively, to the device failure rate. Data based on dynamic lifetest is used to estimate the operating failure rate. The best estimate of the long term failure rate based on this data is 39 FIT at 55�C. The infant mortality failure fraction based on 48 hour, 125�C dynamic burn-in is 349 ppm. Data is also presented on the package integrity of this device in Cerdip, LCC, PDIP, and PLCC. The data shows the Xicor X2864A to be a very reliable device.
REFERENCES
1. R.E. Shiner, et al, Proc. 18th Reliability Physics Symposium, pp. 238-243 (1980).
2. N. Mielke, A. Fazio and H. Liou, Proc. 25th Reliability Physics Symposium (1987).
This report is based on data collected through March 1987.
9-70
APPENDIX A
Package Type
Product X2864A
Plastic
J OJc OJA
l 39.5 64.3
Cerdip
I OJc OJA I 16.5 35
LCC
I oJc OJA l 5.0 46.0
Thermal Resistance Table: 8JC and 8JA expressed in �C per watt.
1.0 �F
NC+--------1 A12+--------t I Ar+--------1 As+--------1 As+--------1 A4+--------t
Aa+--------1 A2+--------t A1+--------1 Ao+---.,,..-.,....,....,=-1
Ao-~~~---------------K=~
--1I
CEA
L I
(CLK-1)
--
J - I
CEe (CLK�!>_
rI --
�
1! . ~_ LK~d~-1i--1-.01..-.1,1_-!1-�o____-1.111-1.0 -1 r-1 o ~I --
1
I II
I
I
I
I I I
I
I
0
8 10 12 16 20 24 28 30 32 36 40
TIME(�SEC)
0079-13
Notes: (1) Ao-A12: binary sequencing address cycle: 40 �.s.
(2) WE disabled (tied to Vee at device).
(3) V1N Low: 0.4V
(4) Vee: s.sov
V1N High: 5.0V
X2864A {DIP) Burn-in timing diagram.
Note A:
CLK-1: Rows 1, 3, 5 ... (odd rows-CEA) CLK-2: Rows 2, 4, 6 ... (even rows-CEs) Such that: CLK-2 = CLK-1
0079-12
Note B: (1) WE must always be hardwired to Vee (Pin 28) at device as shown.
(2) All resistors: 1% metal film 1/4W
(3) 1/0 pull-up 2.00 Kn II 0 pull down: 1.40 Kn
(4) Socket-to-socket isolation as shown.
X2864A (DIP) Burn-in circuit.
9-71
NOTES
9-72
RR-508
liCI'
X2404 RELIABILITY
REPORT
By Julie Segal
9-73
INTRODUCTION
The X2404 is a 4096 bit serial E2PROM organized as two 256 x 8 bit pages. This memory operates on a single 5V power supply for all operations. Figure 1 provides the pin configuration; Figure 2 shows the functional block diagram; Figure 3 illustrates the physical location of the various address bits. The thermal resistance table, burn-in circuit and a timing diagram are included in Appendix A for your reference.
(8) Vee _ _
(4) Vss - -
Vss
4
Figure 1: X2404 Pin configuration.
Vee TEST
SCL
5
SDA
START CYCLE
H.V. GENERATION TIMING
& CONTROL
0080-3
START STOP LOGIC
(6) SCL--e--+--4
'SLAVE ADDRESS REGISTER
+COMPARATOR
(3lA2-----
- - + - - - - (2) A, --+----~
(1) Ao
CONTROL LOGIC
LOAD
INC
PIN DouT ACK
Figure 2: X2404 Functional block diagram.
0080-4
9-74
LSB
00 PAGE 0 08 32 ROWS 10
18
BYTE Xo
BYTE x8
...1' 'l
MSB
00 01 02 03 04 05 06 07
08 09 OA OB oc OD OE OF
10 11 12 13 14 15 16 17
18 19 1A 1B 1C 10 1E 1F
__1'
"J"
__1' "\I
FO
F6 F7
F8
FE FF
s::~~~ I PAGE 0
L-~~~~~~~~~~~~~___J
0080-5 Each square equals one byte.
Figure 3: X2404 Physical bit map.
Xicor is an experienced producer of E2PROMs with over fourteen million devices in the field. This and previous experience with the development of NOVRAMs has given Xicor a leading position in nonvolatile memory technology.
TECHNOLOGY
The X2404 is fabricated in a triple polysilicon N-channel floating gate MOS technology. Data is stored as the presence of positive or negative charge on the second level polysilicon which acts ~s a gate of a memory t~ansistor. This floating gate 1s surrounded by - 750A of thermally grown oxide, one of the best electrical insulators known. Charge is transferred to and from the floating gate through a quantum mechanical effect known as FowlerNordheim tunneling. This phenomenon has been described in detail in recent publications.1,2,3
RELIABILITY STUDY AND RESULTS
The reliability studies and results presented here are those of the X2404 in a plastic package.
Before Xicor qualifies any new product it is subjected to a series of accelerated stresses and tests. These tests are designed to accelerate any degradation a device may experience over the course of a normal lifetime so as to uncover any design or process flaws.
In addition, Xicor runs ongoing monitors of those products in production. This assures high reliability standards for all product shipped by Xicor.
The stresses used to establish reliability data are as follows:
1) High temperature dynamic lifetest. 2) Data retention bake. 3) High temperature high voltage stress. 4) Environmental testing. A short description of these tests and the results obtained are presented in the following report.
Dynamic Lifetest
Most failure modes encountered in MOS devices are accelerated if the device is operated at elevated temperatures. Thus the dynamic lifetest aims to accelerate any failure modes a device may exhibit by operating the device in its most common mode at high temperature.
For the X2404, the dynamic lifetest consisted of continually reading the devices at a temperature of 125�C. A known pattern was stored in the devices prior to the beginning of the test. Each unit was tested for data retention and complete functionality after 48, 168, 500, 1000, 1500 and 2000 hours of dynamic lifetest.
The results of the dynamic lifetest are shown in Table I for samples pulled from five lots of plastic devices. As indicated in the table, all samples were subjected to 168 hours of burn-in. One hundred units from each sample lot were then put on continuing test, with the results as shown.
9-75
48 Hrs.
168 Hrs.
Lot#
# Fail #In #Fail #In
A
0 880 0 880
B
1[a] 1000 0 999
c 2la] [b) 999 1 [a] 997
D
0 999 0 999
E
0 998 0 997
Totals 3 4876 1 4872
[a] Oxide breakdown [b] Metallization defect Table I: Dynamic lifetest@ 125'.C, test results.
500 Hrs. #Fail #In
0 100 0 100 1[a] .100 0 100 0 100 1 500
1000H rs. # Fail #In
0 100 0 100 0 97 0 100 0 100 0 497
1500 Hrs # Fail #In
0 100 0 100 0 97 0 100 0 100 0 497
2000 Hrs # Fail #In
0 100 0 100 0 97 0 100 0 100 0 497
T0 ta1. Hours
3.3 x 105 3.5 x 105 3.5 x 105 3.5 x 105 3.5 x 105 1.7 x 106
Data Retention
The purpose of this stress is to measure and ensure a device's ability to retain data. This test is run at elevated temperatures because floating gate structures will have a .greater tendency to lose charge (data change) at higher temperatures. Because the X2404 cell is similar to �that of the X2864A, we expect similiar excellent data retention. Refer to Xicor publication, X2864A Reliability Report, RR-507A.4
High Temperature High Voltage Stress
The high temperature high voltage stress test is a derivative of the high temperature reverse bias tests
used to evaluate bipolar circuits. In this test Vss is
grounded while all inputs and Vcc are maintain~d.at
high voltage while being baked. The .str~s~ 1s intended to expose failures due to mobile 1ornc contaminants, electrical overstress and latent gate oxide defects. The temperature for this test is 150�C
+ with the bias voltage set at 5.5V. Data retention
and functionality were verified after 500, 1000, 1500, and 2000 hours. The results of the tests are listed in Table II.
500 Hrs. 1000 Hrs. 1500 Hrs. 2000 Hrs. Total Lot# # Fail #In #Fail #In #Fail #In # Fail #In Hours
A 0 50 0 50 0 50 0 50 1 x 105 B 0 50 0 50 0 50 0 50 1 x 105 c 0 50 0 50 0 50 0 50 1 x 105 D 0 50 o. 50 0 50 0 50 1 x 105 E 0 50 0 50 0 50 0 50 1 x 105 !Totals 0 250 0 250 0 250 0 250 5 x 105
Table II: 150'C High temperature high voltage test results.
ENVIRONMENTAL TESTING
Environrriental tests are designed to determine a
device's resistance to extreme or changing environ-
ments. Presented here is the reliability data on plas-
tic packaged device!;.
.
.
Due to the considerable difference in expansion
vcio~eefsficiceannts
between plastic and silicon, plastic debe susceptible to temperature ,cycling
damage. Therefore, plastic units were subjected to
a more stringent test for this condition than that re-
quired for MIL-STD-8838 group D testing. Table Ill
illustrates the test results of units that had been
subjected to one thousand temperature cycles as
defined by MIL-STD-883 test condition C (i.e.,
-65�C to + 150�C).
9-76
168Cycles 500 Cycles Lot#
# Fail #In # Fail #In
A
0 100 0 100
B
0 100 0 100
c
0 100 0 100
D
0 100 0 100
E
0 100 0 100
Totals 0 500 0
Table Ill: Temperature cycling test results.
500
1000 Cycles # Fail #In
0 100 0 100 0 100 0 100 0 100 0 500
85�C and 85% Relative Humidity and Autoclave Tests
In addition, plastic encapsulated devices may be susceptible to moisture. For this reason five sample lots of plastic units were stressed at 85�C with 85% relative humidity (both powered and unpowered) and five additional sample lots were subjected to autoclave tests. (pressure pot) at two atmospheres. These stresses test for corrosion, electrolytic failure modes and passivation integrity. The results of these tests are presented in Tables IV and V.
168 Hrs. 500 Hrs. 1000 Hrs. Total
Lot# # Fail #In # Fail #In # Fail #In
Hours
A 0 50 0 50 0 49 4.5 x 104
B
0 50 0 50 0 50 5.0 x 104
c
0 50 1[c] 50 0 49 4.5 x 104
D
0 50 0 50 0 50 5.0 x 104
E
0 50 0 50 0 50 5.0 x 104
Totals 0 250 1 250 0 248 2.4 x 105
[c] Leaky oxide Table /VA: 85185 Test results with Vee= +5.0V.
168 Hrs. 500 Hrs. 1000 Hrs. Total
Lot# #Fail #In #Fail #In # Fail #In
Hours
A 0 50 0 50 0 50 5.0 x 104
B
0 50 0 50 0 50 5.0 x 104
c
0 50 0 50 0 50 5.0 x 104
D
0 50 0 50 0 50 5.0 x 104
E
0 50 0 50 0 50 5.0 x 104
Totals 0 250 0 250 0 250 2.5 x 105
Table /VB: 85185 Test results with Vee= OV.
NOTE: In both 85/85 tests, each pin was alternately
biased to + 5V and OV to provide an electrical po-
tential between adjacent metal lines on the die.
48 Hrs. Lot#
# Fail #In
A
0 100
B
0 100
c
0 100
D
0 100
E
0 100
Totals 0 500
[c] Leaky oxide
Table v.� Autoclave test results.
144 Hrs. # Fail #In
0 100 0 100 0 100 0 100 1[c] 100 1 500
240 Hrs.
# Fail #In
0 100
0 100
0 100
0 100
0
99
0 499
336 Hrs.
#Fail #In
0 100 1[cl 100
0
99
0 100
0
99
1 498
432 Hrs.
#Fail #In
0 100
0
99
0
99
0 100
0
99
0 497
528 Hrs.
# Fail #In
0 100
0
99
0
99
0 100
0
99
0 497
Total Hours
5.3 x 104 5.3 x 104 5.3 x 104 5.3 x 104 5.2 x 104 2.6 x 105
9-77
PREDICTION OF FAILURE RATES
As mentioned previously, accelerated testing al-
lows one to identify possible design and process
flaws. It also makes it possible to predict long term
failure rates under normal operating conditions.*
All failure mechanisms are accelerated to some
degree by voltage or temperature or both. The de-
gree to which any given failure mode is accelerated
is known as the activation energy or simply as the
acceleration factor. Thus knowledge of a failure
mode's activation energy allows one to predict the
long term failure rate for that failure mode under
normal operating conditions. If the activation energy
is not known it can be determined experimentally.
Four typical failure mechanisms of the technology
employed by Xicor and their corresponding activa-
tion energies are:
Oxide breakdown
0.3eV
Electromigration
0.55eV
Leaky oxides
0.6eV
Ionic contamination
1.0eV
Table VI contains the predicted long term failure
rates for these activation energies. The results are
based on the dynamic lifetest and HTRB data pre-
sented in the previous sections.
Activation Energy
Number of
Failures
Equivalent Hours at 55�C
60% UCL Failure Rate Per
1000 Hrs. at 55�C
0.3eV
2 1.5 x 107 0.0210
0.55eV
0 8.6 x 107 0.0015
0.6eV
0
1.2 x 108 0.0008
1.0eV
0 2.2 x 109 0.0000
Table VI: Predicted long term failure rates.
0.0233 Total
*NOTE: The infant mortality failure rate, based on 3 failures out of 4867 units tested after the first 48 hours of burn-in at 125�C is 0.06%. 48 hours of 125�C burn-in is equivalent to a few hundred to approximately 1000 hours of system operating ti~e, depending on failure mode and system operating temperature.
The failure rates predicted are for plastic devices. The predicted failure rate in percent is depicted as the "60% upper confidence level failure rate per 1000 device hours.'' This means that there is a 60% probability that the actual failure rate will be below the rate calculated. Sometimes predictions are expressed in FIT units. To convert from the given values to FITs, simply multiply the failure rate per 1000 hours operation by 10,000.
A more representative value for the failure rate can be given by the best estimate. This value gives the most likely failure rate based on the given data as shown in Table VII.
Activation Energy
Number of
Failures
Equivalent Hours at
55�C
B.E. Failure Rate Per 1000 Hrs. at 55�C
0.3eV
2
1.5X107 0.0158
0.55eV
0 8.6 x 107 0.0008
0.6eV
0
1.2 x 108 0.0006
1.0eV
0 2.2 x 109 0.0000
Table VII: Best estimate long term failure rates.
0.0172
Total
Based on these values it can be seen that the expected long term failure rate for the X2404 is 0.0172% per 1000 hours at 55�C.
ENDURANCE
Endurance of the X2404 is generally limited to electron trapping in the tunnel oxide. Figure 4 shows the extreme value distribution observed for endurance on this part as measured by simultaneously changing all bits from a "1 " state to its complement and back.
9-78
?~ ~ l~ l~ ~ ~ ~ ~ ~ ~ ~ ~!~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1M,_,_-_,_-,,~-~r----r---r--~----------~-:---~,~--r-----------------------------------------------------------------------------------~-~-~ _,_,_.__ ... _ ... _ _ _ _ _ _ _ _ _ ,_._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .! _ _ _ _ _ _ _ - - - - - - - - - -
-1-1-r-T�r---------1-r------------------------------ ----------1-1-r-T�r---------1-r------------------------------ ----------�-�-1--.i.-.i.---------�-1------------------------------- ----------1,1 -1,-.-I ;-I ,---------l ,I-,------------------------------ ----------
-1-1-r-T�r---------1-,------------------------------- ----------
-I,I-,I-.-I-;-I ;-----
_t_I_ .. _ .. _... _____
111
I
I
-1-1-1- - -I - -I - - - - -
---I,-I ,-----------------------------� � .1 . L - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I I
_ _ _ lI _II_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - - - - - - - - -
-------------------
----------
1K.111151
37157
99
.5 2 10
50
CUMULATIVE PERCENT
0080-2 Figure 4: An extreme value distribution of endurance monitor on units cycled in mass mode.
SUMMARY
The technology used in producing the X2404 was reviewed. A comprehensive set of data covering a variety of stresses were presented and described. Finally, failure �predictions were provided.
REFERENCES
1. R.K. Ellis, IEEE Electron Device Letters 13 (1982): 330-333.
2. R.K. Ellis, H.A.R. Wegener and J. Caywood, International Electron Devices Meeting Technical Digest (1982): 749-752.
3. J. Caywood and Reliability Engineering Staff, NOVRAM Reliability Report, Xicor publication RR-502A (1985).
4. T. Kaysser and L. Purvis, X2864A Reliability Report, Xicor publication RR-507A (1987).
This report is based on data collected through May, 1986.
APPENDIX A
Product X2404
Package Type: Plastic
8Jc
I
OJA
43.0
l
84.0
Thermal Resistance Table: 8Jc and 8JA expressed in �C per watt.
+SV
X2404 Burn-in circuit.
X2404
}
1--~-+--"""-...-~~
1.SkO
REF. BURN-IN TIMING DIAGRAM
9-79
0080-6
X2404 Burn-in timing diagram and program flow.
ISSUE START COMMAND AND
SLAVE ADDRESS
14�S
CLOCK OUT BYTE AND
ACKNOWLEDGE 255TIMES
20�.S
READ LAST BYTE ISSUE
STOP COMMAND
COMPLEMENT AO
_!i....--- I
LOOP
~
0080-7
9-80
RR-509
lil:I'
0081-1
X2816B
RELIABILITY REPORT
By Steven K. Fong
9-81
INTRODUCTION
The X28168 is a 16K bit electrically erasable programmable read only memory (E2PROM) organized 2K x 8. It is an enhancement of the X2816A which incorporates DATA Polling and 16 byte page mode writing to decrease the write time needed to write data into the whole part~ and it operates on a single 5V power supply for all operations. It utilizes the same proven thick oxide, textured poly technology as�other Xicor nonvolatile memory products. Further information about the memory cell and tunneling physics may be found in references 1-4. Figure 1 provides the pin configuration; Figure 2 shows the functional block diagram; Figure 3 illustrates the physical location of the various address bits. The thermal resistance table, burn-in circuit and a timing diagram are included in Appendix A for your reference.
Ao
llOo 110, 1102 Vss
Figure 1: X2816B pin configuration.
Vee Aa Ag WE
OE
A10
CE
1107 1106
110~
1/04 1103
0081-2
Ao-A10 ADDRESS
INPUTS
Figure 2: Functional block diagram.
x
BUFFERS LATCHES
AND
DECODER
16,384-BIT PPROM ARRAY
y BUFFERS LATCHES
AND DECODER
CONTROL LOGIC
110 BUFFERS AND LATCHES
ll lllll
1100-1101 DATA INPUTS/OUTPUTS
0081-3
9-82
X5 X4 X3 X2 X1 Xo A10A9 Aa As As A7
0 0
00 00
0 1 1 1
1 0
00 01
0 0 10
00 11
0 100
0 10 1 0 1 10
0 1 11
10 0 0
10 0 1
10 10
10 1 1
1 1 0 0
110 1
1 1 10
11 11
0000000000000000 00000000 11111111 0 000 1 11 10000 1111 0011001100110011 0 10 10 10 10 10 10 10 1
Each square equals one byte. Figure 3: X28168 bit map.
Y4=A4 Y3=A3 Y2=A2 Y1 =A1 Yo=Ao
1111111111111111 00000000 11111111 00 00 111100 00 11 11 0011001100110011 0 10 10 10 10 10 10 10 1
0061-4
RELIABILITY STUDY AND RESULTS
Before Xicor qualifies any new product, it is subjected to a series of accelerated stresses and tests. These tests are designed to accelerate any degradation a device may experience over the course of a normal lifetime in order to uncover any design or process flaws. Because package type has an effect on device reliability, complete qualification of the X2816B involved both plastic and cerdip units. Since this device is very similar to the Xicor X2864A in design and technology, the reliability data found in the reliability report for X2864A (RR-507A) may be used to extend the results reported here.
In addition, Xicor runs ongoing monitors of those products in production. This assures high reliability standards for all product shipped by Xicor.
The stresses used to establish reliability data are as follows:
1) High temperature dynamic lifetest. 2) Data retention bake. 3) High temperature high voltage stress. 4) Environmental testing. 5) Endurance. A short description of these tests and the results contained are presented in this report.
9-83
Dynamic Lifetest
Most failure modes encountered in MOS devices �
can be accelerated if the device is operated at .an
elevated temperature. Thus, the dynamic lifetest
aims to accelerate any failure mode a device may
exhibit by operating the device in its most common
mode at high temperature.
�
For the X2816B, the dynamic lifetest consists of
continually reading a known data pattern stored in
the device while it is subjected to a temperature of
125�C. Each� unit was then tested for data retention
and complete functionality after 168, 500, 1000,
1500 and 2000 hours of dynamic lifetest. The result
of the test is shown in Table I (no failures were
found).
Data Retention
The purpose of this stress is to measure and ensure a device's ability to retain correct data. Floating gate structures are more likely to lose charge at high temperatures. For example, 48 hours at 250�C or 1ooo hours at 150�c are equivalent to about 15 years at 55�C for an activation energy of 0.6eV. This is the energy for oxide defects which demonstrate floating gate memory data� retention failures.
This test is conducted by storing a checkerboard pattern in the devices and baking the device at 150�C for plastic devices and 250�C for cerdip devices. The pattern is verified after 48, 168, 500, 1000, 1500 and 2000 hours. The results of this test are listed in Table II (no �failures were found).
Lot#
168 Hrs. # Fail #In
500 Hrs. # Fail #In
1P
0
360
0
100
2C
0
360
0
100
3C
0
360
0
100
4C
0
280
0
0
Totals
0
1360
0
300
Note: C = Cerdip
P = Plastic
Table I: Dynamic lifetest at 125'C test results.
1000 Hrs.
#Fail #In
0
100
0
99
0
100
0
0
0
299
1500 Hrs.
#Fail #In
0
99
0
98
0
100
0
0
0
297
2000 Hrs.
#Fail #In
0
99
0
95
0
100
0
0
0
294
Total Hours
2.426 x 105 2.397 x 105 2.435 x 105 4.704 x 104 7:729 x 105
48 Hrs.
168 Hrs.
500 Hrs.
1000 Hrs.
Lot#
#Fail #In #Fail #In #Fail #In #Fail #In
1 p
0
20
0
20
0
20
0
20
1 c
0
30 0 30 0
30 0 30
2C
0
50
0
50
0
50
0
50
3C
0
50 0 50 0
50 0 50
.Totals 0 150 0 150 0 150 0 150
Note: C = Cerdip P = Plastic
Table II: Retention bake test results, 250'C tot cerdip devices and 150'C for plastic devices.
1500 Hrs.
# Fail #In
0
19
0
30
0
50
0 50
0 149
2000 Hrs.
# Fail #In
0
19
0
30
0
50
0 50
0 149
Total Hours
3.9 x 104 6 x 104
1x104
1 x 104 1.19 x 105
9-84
Lot#
1 p
1 c
500 Hrs.
# Fail
#In
0
10
0
35
1000 Hrs.
# Fail
#In
0
10
0
35
2P
0
7
0
7
2C
0
38
0
38
3C
0
45
0
45
Totals
0
135
0
135
Note: C = Cerdip P = Plastic
Table Ill" 15fJ'C high temperature high voltage test result.
1500 Hrs.
# Fail
#In
0
10
0
35
0
7
0
38
0
45
0
135
2000 Hrs.
# Fail
#In
0
7
0
35
0
7
0
38
0
45
0
132
Total Hours
1.85 x 104 7 x 104
1.4 x 104 7.6 x 104
9 x 104 2.68 x 105
High Temperature High Voltage Stress
The high temperature high voltage stress is intended to expose failures due to mobile ionic contaminants, electrical overstress and latent gate oxide defects. In this test, Vss is grounded while all inputs and Vee are maintained at high voltage.
The temperature for this test is 150�C with the
bias voltage set at + 5.5V. Data retention and com-
plete functionality were verified after 500, 1000, 1500 and 2000 hours. The result of the test is listed in Table Ill (no failures were found).
Environmental Testing
Environmental testing is designed to determine a device's resistance to extreme or changing environment. Due to the inherent differences between plastic and cerdip devices, different reliability stresses are applied to evaluate the individual package types.
Some of the tests used to evaluate cerdip packages, such as hermeticity, internal water vapor content, and lid torque, do not apply because the plastic packages are not hermetically sealed. (For reliability data on the 24-pin cerdip package, see the X2816A/X2804A Reliability Report RR-505).
Other tests, such as vibration and acceleration, do not apply because the die in a plastic package is completely embedded in plastic and is not susceptible to such mechanical failure. Plastic packages may be susceptible to other failure modes. Due to the considerable difference in expansion coefficients between plastic and silicon, plastic devices are considerably more susceptible to temperature
failures. Table IV shows the result of units subjected to one thousand temperature cycles as defined by MIL-STD-883 test condition C.
Lot# 250Cycles 500Cycles # Fail #In # Fail #In
1 p
0 78 0 78
2P
0 78 0 78
3C
0 78 0 78
Totals 0 234 0 234
Note: C = Cerdip
P = Plastic
Table IV: Temperature cycling test results.
1000 Cycles
# Fail #In
0 78
0 78
0
77
0 233
Prediction of Failure Rates
Accelerated testing identifies possible design and
process flaws. It also predicts failure rates under
normal operating conditions. Most failure mecha-
nisms in this report are accelerated by voltage, tem-
perature or both. The degree to which any given fail-
ure mode is accelerated may be predicted by activa-
tion energy. If the activation energy is not known, it
can be determined experimentally. Four typical fail-
ure mechanisms of Xicor technology and their cor-
responding activation energies are:
1) Oxide Breakdown
0.3eV
2) Electromigration
0.55eV
3) Leakage Oxide
0.6eV
4) Ionic Contamination
1.0eV
Table V presents the predicted failure rates for
these activation energies. The results are based on
the test data presented in Tables I and Ill.
9-85
Activation Energy
Number of
Failures
0.3eV
0
0.55eV
0
0.6eV
0
1.0eV
0
Totals
0
Table II." 60% UCL failure rate predictions.
Equivalent Hours at 70�C
4.495 x 106 1.626 x 107 2.206 x 107
1.914X108
60% UCL Failure Rate per 1000 Hours
at 70�C
0.0205
0.0056 0.0042
0.0005 0.0308
Equivalent Hours at 55�C
6.986 x 106 3.659 x 107 5.130 x 107 8.184 x 100
60% UCL Failure Rate per 1000 Hours
at 55�C
0.0132 0.0025 0.0018
0.0001 0.0176
The failure rate predictions presented here are for both plastic and cerdip devices. Such predictions are valid because all the failure. modes found or expected are common for both plastic and cerdip devices. Xicor has defined failure rate as the "60% upper confidence level" failure rate per 1000 device hours. This means that there is a 60% probability the actual failure rate will be below the rate computed. Sometimes predictions are expressed in FIT units. To convert from the previously named value to FIT, multiply by 10,000. For a more detailed discussion on confidence limits and reliability failure rate calculations, see Xicor Reliability Report RR-506.
A more representative� value for the failure rate can be given by the "best estimate". This value gives the most likely failure rate based on the given data. Table VI presents the best estimate values.
Table VI shows that the expected failure rate for the X28168 is 0.0229% per 1000 hours at 70�C
which is 229.0 FIT and 0.0134% per 1000 hours at 55�C which is 134 FIT. Since no failure was observed in any of the ac.celerated lifetests, the failure rate calculated above should be considered an upperbound which is limited by the size of the database.
Endurance
Endurance of the X2816B is generally limited by trapping of electrons in the tunnel oxide during tunneling as discussed in RR-510. Figure 5 shows the distribution observed for endurance on this part as measured by simultaneously changing all bits from one state to its complement and back. Additionally, a sample of 51 O units had the data in every bit altered 10,000 times on a page by page basis. The results showed a failure rate of 1% in the first 10,000 cycles.
Activation Energy
Number of
Failures
Equivalent Hours at 10�c
0.3eV 0.55eV 0;6eV 1.0eV
0
4.495.X 106
0
1.626 x 107
0
2.206 x 107
0
1.914 x 108
Totals
0
Table VI: Best estimate failure rate predictions.
Best Estimate Failure Rate per 1000 Hours
at 70�C
O.Q151
0.0042 0.0032 0.0004
0.0229
Equiv~lent
Hours at 55�C
6.986 x 106 3.654 x 107 5.130 x 107 8.184 x 100
Best Estimate Failure Rate per 1000 Hours
at 55�C
0.0100
0.0019 0.0014
0.0001 0.0134
9-86
1M _:_:____________:_~ __ _
2-,-,- - - ---------,-r--~ ~ ~~~~~~=~)~~~ .....- - - -
-.- �- -�- -- - - -- -- - - - - - -- - -- -- - - -
--------------------- ----------
lK.1 1115 I 37 157
99
.5 2 10
50
CUMULATIVE PERCENT
0081-5 Figure 5: An extreme value distribution of endurance monitor on units cycled in mass mode.
SUMMARY
Data presented in this report shows that the X2816B is highly reliable. Further data is being collected to better predict the failure rates for this part.
REFERENCES
1. J. Caywood, NOVRAM Reliability Report, Xicor Publication RR-502A (1985).
2. R.K. Ellis, H.A.R. Wegener and J. Caywood, "Electron Technology in Non-Planar Floating Gate Memory Structure", 1982 IEDM Digest, pp. 749-752.
3. S.K. Lai, V.K. Dham and D. Guterman, "Comparison and Trends in Today's Dominant E2 Technologies", 1986 IEDM Digest, pp. 580-583.
4. D. Guterman, B. Houck, L. Starnes and B. Yeh, "New Ultra-High Density Textured Poly-Si Floating Gate E2PROM Cell", 1986 IEDM Digest, pp. 826-828.
9-87
APPENDIX A
Package Type
Product X2816B
Plastic
OJc ] OJA
t 5o.o 81.0
Cerdip OJc OJA 20.5 36.0
LCC
I oJc OJA -l -
Thermal Resistance Table: 8JC and 8JA expressed in �C per watt.
1.0�F
A4--+------t I
____ Aa--+------1 I
~_....._
Ao-4-----1 I PS�2 --+---.JVV'v-1 r-l
D<::: Ao-A10=~)i( - - - - - - 1
CEA --1
(CLK-1)
- JI CEe
(CLK�!>.
L --
1 __
1
-1........_1_�__ -
-1 +j l=-1.0
r-1 0 -11-1.0
J-1 (OCELK'!t
-r-
1_1
I
I I I
I
I
I
0
8 10 12 16 20 24
II . -I r-1 0 .
1
I I I
I
28 30 32 36
n-11 --
II
I
40
TIME(�SEC)
0081-7 Notes: (1) Ao-A10: binary sequencing address cycle: 40 �.s.
(2) WE disabled (tied to Vee at device). (3) V1N Low: 0.4V V1N High: 5.0V (4) Vee: 5.50V
X2816B (DIP) Burn-in timing diagram.
GND-'"..._-------------------'
0081-6 Notes: (A) CLK-1: Rows 1, 3, 5 ... (odd rows-CEA)
CLK-2: Rows 2, 4, 6 ... (even rows-CEs) Such that: CLK-2 = CLK-1 (B) 1. WE must always be hardwired to Vee (Pin 24) at de-
vice as shown. 2. All resistors:
1% metal film 1/4W 3. ii 0 pull-up. 2..0 Kn 1/0 pull-down: 1.4 Kn 4. Socket-to-socket isolation as shown.
X2816B (DIP) Burn-in circuit.
9-88
)lic1,
RR-511
0114-1
X28C64/X28C256
RELIABILITY REPORT
9-89
INTRODUCTION
The X28C64 and X28C256 are nonvolatile bytewide E2PROMs configured as 8K x 8 and 32K x 8 respectively. Both devices are compliant with the
Vee
A14
Vee
Wl
A12
WE
NC
A1
A13
JEDEC approved pinout for byte-wide memories.
Both devices operate on a single 5V power supply
As
and feature byte or 64-byte page write, DATA Poll-
At
Ae
A&
At
As
A,,
A4
Aa Ag
A,,
ing, Toggle Bit and Software Data Protect opera-
Al
OE
A3
OE
tions.
AJ
The memories are fabricated using Xicor's propri-
A,
A,o
A2
CE
A1
A10
ce
etary textured poly technology. They are designed
Ao
l/01
Ao
1101
for applications requiring extended endurance and UOo
1101
l/Oo
1/0&
data retention characteristics greater than 100 uo,
I/Os
1/01
I/Os
years.
l/02
l/04
1102
1/04
Through rigorous environmental and electrical Yss
l/03
Vss
1/03
stress testing, the reliability of these devices has been well characterized. This report is a presenta-
0114-2
tion of the data accumulated in testing these devic-
Figure 1: X28C64 andX2BC256 DIP pin configurations.
es and supporting information needed to fully utilize
the parts.
Figure 1�shows the DIP pin configurations for both
the X28C64 and the X28C256; Figure 2 shows the
functional block diagram for the X28C256; and Fig-
ures 3 and 4 illustrate the physical location of the
address bits.
Ao-A14
ADDRESS
INPUTS
x
BUFFERS LATCHES
AND DECODER
y BUFFERS LATCHES
AND DECODER
256K-BIT E2PROM ARRAY
1/0 BUFFERS AND LATCHES
CE OE
WE
Vee a--.
Vss~
Figure 2: X2BC256 functional block diagram.
CONTROL LOGIC AND TIMING
llOo-1101 DATA INPUTS/OUTPUTS
0114-4
9-90
~----.-:162~\~~~
0000000 0000001 0000010 0000011 0000110 0000111 0000100 0000101
l/Oo 1/01 1/02 1/03
1 COLUMNS 1 COLUMNS 1 COLUMNS 1 COLUMNS I :(64 COLs):(64 COLs):(64 COLs):(64 COLS):
BINARY
(128 ROWS)
�
1/04 I/Os I/Os 1/07
1 COLUMNS 1 COLUMNS 1 COLUMNS 1 COLUMNS 1 :(64 COLs):(64 COLs):(64 COLs):(64 COLS):
1 11 1 000 111100 1 1111010 11110 11 1 1 1 1 1 10 1111111 1 1 1 1 10 0
111110 1
D Y5=A5 00 00 00 00
Y4=A4 00 00 00 00 Y3=A3 00 00 00 00 Y2=A2 00 00 1 1 1 1 ) Y1 =A1 00 1 1 00 1 1 )
Yo=Ao 0 1 0 1 0 1 0 1 l
BINARY (64 COLUMNS)
l 11111111
L_ 1 1 1 1 1 1 1 1
) 11111111
) 00 00 1 1 1 1
} 0 0 1 100 1 1
~
l
0 10 10 10 1
Address to XY Key
A12 A11 A10 Ag As A1 As As A4 A3 A2 A1 Ao Xs X5 X4 X3 X2 X1 Xo Y5 Y4 Y3 Y2 Y1 Yo
Figure 3: X2BC64 physical bit map.
0114-5
9-91
---------~-~~~~-:~ _____ ____
000000000
000000001
000000010
000000011
000000110
000000111
000000100
000000101
�
l/Oo
1/01
1/02
1/03
:
1/04
I/Os
I/Os
1/07
1 COLUMNS 1COLUMNS 1 COLUMNS 1 COLUMNS I BINARY ICOLUMNS 1 COLUMNS 1 COLUMNS 1 COLUMNS 1
. :(64 COLs):(64 COLS):(64 COLs):(64 COLS): (512 ROWS) :(64 COLs):(64 COLs):(64 COLs):(64 COLS): �
�
111111000
111111001
111111010
111111011
111111110
111111111
111111100
111111101
...._~~~~~~"""-~~--'---~~---'
Ys=As 00 00 00 00[)
Y4=A4 00 00 00 00
Y3=A3 00 00 00 00 Y2=A2 00 00 1 1 1 1)
Y1 =A1 00 1 1 00 1 1 )
l Yo=Ao 0 1 0 1 0 1 0 1
BINARY (64 COLUMNS)
1 11111111 1 1 1 1 1 1 1 1
2_ 1 1 1 1 1 1 1 1
' 00 00 1 1 1 1 00 1 1 00 1 1
)_ 0 1 0 1 0 1 0 1
Address to XY Key
Au A13 A12 A11 A10 Ag As A1 As As A4 A3 A2 A1 Ao Xs X7 Xs Xs X4 X3 X2 X1 Xo Y5 Y4 Y3 Y2 Y1 Yo
Figure 4: X28C256 physical bit map.
0114-6
9-92
RELIABILITY STUDIES AND RESULTS
Before Xicor qualifies a process, it is subjected to accelerated stress testing to characterize potential reliability hazards. The major failure mechanisms that exist are: electromigration in contacts and interconnects, threshold voltage degradation due to hot carriers, corrosion damage due to moisture, and oxide failures due to E2PROM operation.
Once these failure mechanisms are characterized and understood, then a product designed using this process must meet further constraints in circuit layout, ESD protection and latch-up protection. These parameters can be varied to further enhance .process reliability in the product.
The device is subjected to a series of tests intended to accelerate device degradation and uncov-
er flaws in processing or manufacturing. MIL-M38510 and MIL-STD-883C, Method 5005, Groups A, B, C and D criteria have been the guide for electrical testing, environmental stress testing and package reliability testing.
A summary of product reliability testing and considerations includes the following:
High Temperature High Voltage Dynamic Lifetest
This test consists of continually reading a device
at elevated temperature. Vcc is set between 5.25V
and 6.5V, and the device address is incremented in a binary sequence every 25 �s. Its purpose is to uncover. latent oxide defects and failures by inducing electrical overstress. The data is shown in Tables I and II.
Lot#
168 Hrs. # Fail #In
500 Hrs.
1000 Hrs.
1500 Hrs.
2000 Hrs. Vee
# Fail #In # Fail #In #Fail #In # Fail # In
Device Hours
1C
0
111
0 111 0 111 0 111 0 111 6.5 222000
2C
1 2oolal 0 199 0 199 0 199 0 199 6.5 398168
3C
0
138
0
80
0
80
0
78
5.25 128888
4C
0
173
0
80
0
80
0
80
0
80 5.25 175624
5C
1 75[b]
0
74
0
74
0
74
0
74 5.25 148168
6C
0
177
0
80
0
80
5.25 96296
7C
1 180[C] 0 100 0 100 0 100 0 100 5.25 213440
8C
0
258
0 160 0 160 0 158 0 158 5.25 334560
Totals 3 1312 0 884 0 884 0 800 0 722
1717144
[a] EOS damage due to latch-up [b] Oxide defect: 0.6eV [c] Contact electromigration: 0.9eV
Table I: X2BC256 high temperature high voltage dynamic lifetest data. (+ 125'C, 5.25V-6.5V)
Lot#
10 20
168 Hrs. # Fail #In
0 253 0 342
500 Hrs. #Fail #In
0 100 0 100
1000 Hrs. #Fail #In
0 100 0 100
30
0 483 0 100 0 100
40
0 418
0
80
1 80[b]
50
0 288 0 100 0 100
Totals 0 1784 0 480 1 480
[a] Unrelated test failure: broken lead [b] Ionic contamination: 1eV
Table II: X28C64 high temperature high voltage dynamic lifetest data. (+ 125'C, 5.25V)
1500 Hrs. # Fail #In
0 99[a] 0 100 0 100 0 78[a]
0 377
9-93
2000 Hrs.
# Fail #In
0
99
0 100
0 100
0 78lal
0 377
Vee
5.25V 5.25V 5.25V 5.25V 5.25V
Device Hours
224704 240656 264344 214784 131632 1076120
High Temperature Data Retention Bake
This test induces data retention failures by simulating accelerated storage times. Various aspects of retention as it pertains to reliability are discussed more fully in Xicor publication RR-515: Data Retention in Xicor E2PROMs.
The test is also useful in investigating failures caused by mechanical stress (e.g. bond wire lifting).
The data for this test is presented in Table Ill.
Low Temperature Lifetest
This test is performed at - 40�C and is used to detect hot electron trapping in the. gate oxide. These are energetic electrons which exceed the thermal ambient. Data is presented in Table IV.
Temperature Cycling
This test is designed to promote device failure due to a thermal mismatch between the package and die. The devices are cycled between - 65�C
and + 150�C in an air-to-air environment with 1O
minute dwell cycles. This data is shown in Table V.
Lot#
Device
48 Hrs.
168 Hrs.
#Fail #In #Fail #In
1 X28C256 0 80 0 80
2 X28C256 0
61
0
61
3 X28C64 0 25 0 25
4 X28C64 0 25 0 25
5 X28C64 0 25 0 25
6 X28C64 0 25 0 25
Totals
0 241 0 241
[a] Oxide defect: 0.6eV
Table Ill: X28C64/X2BC256 data retention bake results. (+25(J'C)
500 Hrs. # Fail #In
0 80 0 61 0 25 0 25 0 25 0 25 0 241
1000 Hrs. #Fail #In
0 80 0 61 0 25 0 25 0 25 0 25 0 241
1500 Hrs.
# Fail #In
0 80
0 61
1 25[a]
0 25
0 25
0
25
1 241
2000 Hrs. #Fail #In
0 80 0 61 0 24 0 25 0 25 0 25 0 240
Lot#
A B
c
D E Totals
Device
X28C256 X28C256 X28C64 X28C64 X28C64
500 Hrs.
# Fail
#In
0
33
0
67
0
25
0
25
0
24
0
174
Table IV: X28C64/X2BC256 low temperature lifetest data. (-4(J'C, 5.25V)
1000 Hrs.
# Fail
#In
0
33
0
67
0
25
0
25
0
24
0
174
1500 Hrs.
#Fail
#In
0
33
0
67
0
25
0
25
0
24
0
174
2000 Hrs.
#Fail
#In
0
33
0
67
0
25
0
25
0
24
0
174
9-94
Lot#
Device
1
2 3 4 Totals
X28C256 X28C256 X28C256 X28C64
Table V.� Temperature cycling data.
(-65'C to + 15(J'C)
250Cycles
# Fail
#In
0
40
0
50
0
50
0
25
0
165
500Cycles
#Fail
#In
0
40
0
50
0
50
0
25
0
165
1000 Cycles
#Fail
#In
0
40
0
50
0
50
0
25
0
165
Endurance Cycling to End-ofLife
Figure 5 shows device endurance results obtained by changing the data in the entire array to the opposite logic state via mass mode cycling. Device endurance is also characterized by page mode cycling. In this method, each byte or 64-byte page is changed sequentially. This data is presented in Figure 6. Further details on endurance cycling are provided in Xicor publication RR-510: Endurance of Nonvolatile Memories.
Xicor specifications call for a failure rate of less than 1% for 10,000 data changes per bit. Typically, Xicor devices perform far in excess of this.
Latch-Up Considerations
Latch-up is an inherent fabrication problem in CMOS devices due to the fact that during processing, parasitic bipolar transistors are created in addition to the desired MOS FETs. Design rules to reduce this susceptability have been developed and are incorporated into Xicor CMOS devices. Further details may be found in Xicor publication RR-516: Latch-up Considerations in Xicor CMOS Processes.
ESD Evaluation
ESD testing is done in accordance with requirements specified in MIL-STD-883C, Method 3015.6, Notice 7. This document provides guidelines for testing semiconductor devices to human body model discharges.
The X28C64 and X28C256 are compliant to Class
2 ( > 2000V) sensitivity protection.
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----
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L 100K :__:_:_~ _ ______:_~ ____ -~ ::<~-~ _x_~~~~~- ________ _
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H~~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
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1�K.1 111 5 I
37 157
99
.5 2 10
50
CUMULATIVE PERCENT
0114-7 Figure 5: Endurance value distribution plots for X28C64 and X2BC256 cycled in mass mode.
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CUMULATIVE PERCENT
0114-8
Note: Page mode cycling stopped at 7 million cycles for the X28C64 and 1.5 million cycles for the X28C256 to free cycling equipment for other tests.
Figure 6: Endurance value distribution plot for X2BC64 cycled in page mode.
9-95
Prediction of Failure Rates
Failure rate calculation is easy once the basis for calculation is established. Most semiconductor failures are accelerated to some degree by temperature or voltage, or both. The classic parameter used to accelerate failure rates is temperature. The degree to which any given failure mode is accelerated by temperature is known as the activation energy or as the temperature acceleration factor.
The temperature dependence of a particular failure mechanism can be derived from the Arrhenius model as follows:
Tat= Exp (Ea X (~ - ~)) k T1 T2 where:
Tat = Temperature acceleration factor
Ea = Activation energy required to initiate the failure mechanism
k = Boltzmann's constant
T1 = Operating temperature
T2 = Stress temperature
Knowledge of a particular failure mode's activa-
tion energy allows one to predict long-term failure
rates under normal operating conditions. If the acti-
vation energy is not known, it can be determined
experimentally.
Typical failure mechanisms and their correspond-
ing activation energies are:
Oxide Breakdown
0.3eV
Electromigration
0.55eV
Oxide Defect
0.6eV
Contact Electromigration1 0.9eV
Ionic Contamination
1.0eV
For time dependent dielectric breakdown, voltage
acceleration also plays a part.2 A voltage accelera-
tion factor may be computed using the following
model:
where:
Vat=
Exp
(
Es-:- Ed) Eet
Vat = Voltage acceleration factor
Es = Stress electric field = VsfTox (voltage over oxide thickness)
Ed = Operating electric field
Eet = Field constant = 0.062 MVI cm
The voltage acceleration factor is dependent on the electric field and must be calculated for the particular voltage stress and oxide thickness where the failure occurred.
The data presented here is translated into failure rates occurring at normal operating conditions of T = 55�C (where T is the junction temperature), and Vee = 5.5V. The power dissipation on-chip raises
the junction temperature by Ice x Vcc x 6JA,
where 6 JA� the thermal coefficient, is equal to 23�C/W. Since the X28C64 and the X28C256 are both CMOS devices, the power dissipation is very low.
Xicor nonvolatile memory failures follow the classic bathtub curve shown in Figure 7.
INFANT MORTALITY
FAILURE RATE
RANDOM FAILURES
WEAROUT
LOG TIME
0114-9 Figure 7: Illustration of bathtub curve of failure rates showing regions in which infant mortality, random failures, and wearout mechanisms dominate the failure rate.
Each region of this failure rate curve has specific failure modes which predominate. For example, the infant mortality region is dominated by failures which arise from processing defects. In production, test flows are designed to eliminate these infant mortality failures by screening, which reduces the incidence of early life failures.
9-96
The random failure region, which is the invariant bottom of the curve, is used to find the constant FIT rates calculated in Tables VI and VII. Failure rates are calculated separately for each activation energy, and the total failure rate is obtained by adding the individual numbers. Reliability predictions are then based on an exponential distribution of each failure mode. Since the failures are random in time, they follow the Poisson distribution function, and the failure rate is constant. The consequence of this is that the failure rates for each failure mode are additive, which makes the distribution calculation mathematically tractable. Predicted failure rates are calculated from actual failure rates by making a probability estimation based on the Chi-Square Distribution. By definition, a 60% confidence level means that there is a 60% probability that the failure rate is normally distributed around the calculated number.
End-of-life endurance is found to be dependent on array size, process technology and memory cell design. For reliability purposes, the end-of-life of a device is taken to be the end-of"life of the weakest bit. The mechanism for this failure is known to be oxide trap-up, and can be fitted to an extreme value distribution. Typical end-of-life cycling for the X28C256 is 5,000,000. For the X28C64, the typical end-of-life cycling figure is 2,000,000 cycles. For page mode cycling, the typical figures are greater than 3 million for the X28C64 and greater than 1.5 million for the X28C256. Thus, extremely low failure rates can be expected in typical applications, even at 100,000 or more cycles.
Activation Energy
Number of
Failures
Equivalent Hours at 70�C
0.3eV
0
4.4 x 1Q6
0.55eV
0
1.4 x 107
0.6eV
0
1.8 x 107
0.9eV
0
7.3 x 107
1.0eV
1
1.2 x 10s
Totals
1
Table VI: 60% UCL failure rate predictions for X2BC64.
60% UCL Failure Rate per 1000 Hours
at 70�C 0.0200 0.0065 0.0050 0.0013 0.0017 0.0345
Equivalent Hours at 55�C
7 x 106 3.3 x 107 4.5 x 107 2.9 x 10s 5.5 x 10s
60% UCL Failure Rate per 1000 Hours
at 55�C
0.0130 0.0028 0.0020 0.0003 0.0004 0.0185
Activation Energy
Number of
Failures
Equivalent Hours at 70�C
0.3eV
0
7 x 106
0.55eV
0
2.3 x 107
0.6eV
1
2.9 x 107
0.9eV
1
1.2 x 10s
1.0eV
0
1.9 x 1Q8
Totals
2
Table VII: 60% UCL failure rate predictions tor X28C256.
60% UCL Failure Rate per 1000 Hours
at 70�C 0.0130 0.0040 0.0070 0.0017 0.0005 0.0262
Equivalent Hours at 55�C
1.1 x 107 5.3 x 107 7.2 x 107 4.7 x 10s 8.8 x 10s
60% UCL Failure Rate per 1000 Hours
at 55�C
0.0085 0.0018 0.0028 0.0004 0.0002 0.0137
9-97
Failure rate predictions based on this data show a negligible infant mortality rate out in the field (due to extensive pre-shipment screening), and predicted long-term failure rates of 185 FITs for the X28C64 and 137 FITs for the X28C256 at 55�C with a 60% UCL. These numbers are representative of the smaller samples typically available for data analysis and not of the much larger numbers available in production runs.
Reliability Monitors
To maintain Xicor's quality standards, current production material is systematically sampled and subjected to the same type of stresses and testing used in the qualification procedures. This serves to enlarge the Reliability Department's statistical data base. Failure analysis is performed on material samples and results are published as part of Xicor's ongoing monitor program.
SUMMARY
The data presented here shows that the X28C64 and X28C256 are both extremely reliable products. Product reliability testing shows low semiconductor failure rates and high end-of-life endurance figures. Inherent data retention in these devices is in excess of 100 years.
These conclusions are based on monitor and device analysis data accumulated over the relatively short lifetimes of these devices. As production continues, more data is obtained through the ongoing reliability monitor system, increasing the number of candidate devices, and improving the ability to make statistical inferences. All FIT rate methods and calculations used here give conservative values.
REFERENCES
1. D.L. Crosthwait, Characteristics of Al-Si Interface Reactions.
2. D.L. Crook, 17th Annual Reliability Physics Symposium (1979): 1-7.
3. Norman 8. Fuqua, Reliability Engineering for Electronic Design.
This report is based on data collected through August, 1989.
9-98
APPENDIX A
Package Type
Product Plastic
Cerdip
LCC
OJc OJA OJc OJA OJc OJA X28C64 35 85 6.3 47 10.4 125
X28C256 4 64 4.3 43.7 8.9 118
Thermal Resistance Table: 8Jc and OJA expressed in �c per watt.
0.1 �F
(SEE NOTE4) A14--4------c:::i A12------� A1-------~1 A5--4------c:::i AA 4 _s_-_ - -_-_-_ - �,
A3--4------c:::i
AA1 _2_-_--_-_--_1,
Ao--4------c:::i
PS2-4'~--'\IV'w-r,
,~ 1 - - - - - A13 (SEE NOTE4) c:::i-----As ...- - - - A g I ..- - - - A 1 1 c:::i-----eLK 2 rJ.----A10 I ..- - - - e L K 1
330.n 330.n 330.n 330.n 330.(l
Notes: (1) WE must always be hardwired to Vee (pin 28) at device as shown. (2) All resistors: 1% metal film 1/4W
(3) I I 0 pull-up: 3300
(4) Pin 1 (A14) and Pin 26 (A13) are no connects for X28C64.
X28C641X28C256 {DIP) Burn-in circuit.
0114-10
~ Ao-A14
x
x:::'
(See Note5} ~--------------� '"�- - - - - - - - - - - - - - 1
--:-i.. ==i CE
Ii.�- ,,__--17 �sec - - - �... 8 �sec
(Clk1) :
.
"�----------
L
OE 'I
(Clk 2)
I.=._--_-=_13_�._se_c__�,.1 � 13 �sec :::::t________.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Time (�sec}
Notes: (1) Ao-A14: binary sequence every 25 JJ-S. (2) WE disabled (tied to Vee at device). (3) V1N Low: ,,;: 0.8V V1N High: ?: 2.4V (4) Vee: 5.5V (5) X28C64: address pins Ao-A12 are utilized.
X28C64/X28C256 {DIP) Burn-in timing diagram.
9-99
0114-11
NOTES
9-100
RR-513
X28256 RELIABILITY
REPORT
9-101
INTRODUCTION
The X28256 is a 32K x 8 electrically erasable programmable read only memory (E2PROM) which operates on a single 5V power supply for all operations. The device is compliant with the JEDEC approved pinout for byte-wide memories, and features a 64-byte page write operation, DATA Polling, Tog� gle Bit, and Software Data Protect capabilities.
The X28256 is fabricated using Xicor's proprietary, high performance, textured poly MOS technology. It is designed for applications requiring extended endurance and data retention characteristics greater than 100 years.
The X28256 has been well characterized through the years by means of accelerated environmental and electrical stress testing. This report provides the results of the tests used to demonstrate the reliability of the X28256 and a brief summary of the tests themselves.
Figure 1 shows the DIP pin configuration for the X28256; Figure 2 shows the functional block diagram for the device; and Figure 3 illustrates the physical location of the address bits.
A14 A12 A1 Ae As A4
A1 Ao l/Oo 1101
Figure 1: X28256 DIP pin configuration.
Vee WE A13 Aa As A11 OE A10
CE
1101 I/Os I/Os 1/04
1/03
0116-2
Ao-A14
ADDRESS
INPUTS
x
BUFFERS LATCHES
AND DECODER
y BUFFERS LATCHES
AND DECODER
256K-BIT E2 PROM ARRAY
110 BUFFERS AND LATCHES
CE OE
WE
vcc 0------.
Vss 0------.
Figure 2: X28256 functional block diagram.
CONTROL LOGIC AND TIMING
llOo-1101 DATA INPUTS/OUTPUTS
0116-3
9-102
- -.- - - . ~~84 :173~\11~~~~
000000000 000000001 000000010 000000011
I l/Oo I 1/01 I 1/02 : 1/03 I �COLUMNS�COLUMNS�COLUMNS�COLUMNS I :(64 COLs):(64 COLs):(64 COLs):(64 COLS):
� �
BINARY (512 ROWS)
� �
I 1/04 I I/Os : I/Os I 1/07 I �COLUMNS�COLUMNS�COLUMNS�COLUMNS� :(64 COLs):(64 COLs):(64 COLs):(64 COLS):
111111100 111111101 111111110 111111111
...___~~--~~~_.__~~~--~~---
Y5=A5 00 00 00 00[)
Y4=A4 00 00 00 00 Y3=A3 00 00 00 00 Y2=A2 00 00 1 1 1 1) Y1 =A1 00 1 1 00 1 1 )
Yo=Ao 0 1 0 1 0 1 0 1 )_
BINARY (64 COLUMNS)
1 11111111 l 11111111 2 1 1 1 1 1 1 1 1
00 00 1 1 1 1 00 1 1 00 1 1 l 0 10 10 10 1
Address to XY Key
Ao
Yo
Figure 3: X28256 physical bit map.
0116-4
9-103
TECHNOLOGY
A cross section of Xicor's textured poly floating gate cell is shown in Figure 4. Cell programming is achieved by electrons tunneling from poly 1 (the cathode) to poly 2 (the floating gate). Erasure is achieved by electrons tunneling from poly 2 to poly 3 (the anode). Tunneling is a quantum mechanical electron transport phenomena that is induced by high voltages generated directly on the chip.
During a write, poly 1, which is common to the whole array is brought low. The poly 2 floating gate is capacitively steered either to a high voltage (approximately 16V) for programming, or to OV for an erase. A high voltage (> 20V) is then applied to poly 3. If poly 2 is steered high, a large voltage drop occurs between poly 1 and poly 2, causing FowlerNordheim tunneling of electrons onto the floating gate. This results in a low voltage on poly 2 which is the program state. If an erase is desired, poly 2 is capacitively steered low, causing the large voltage drop to occur across poly 3 and poly 2. This causes electrons to tunnel off poly 2 onto poly 3, leaving the floating gate with a net positive voltage.
In order to perform a read, the poly 3 select transistor is first enabled. The charge on the selected floating gate controls a MOS transistor which determines the path of the current coming from the sensing circuitry. If the floating gate is charged positively (erased), current flows through the cell, and a "1" is sensed. If the floating gate is charged negatively (programmed), the current path through the cell is cut off, and the datum is read as a "O".
POLYSILICON (POLY 1)
0116-5 Figure 4: Cross sectional structure of a textured poly memory cell
RELIABILITY STUDY AND RESULTS
Xicor subjects its devices to various accelerated tests and stresses. These stresses are designed to accelerate any degradation a device may experience during its normal lifetime. The following stresses were used to establish reliability data and failure rate characteristics for the X28256: 1) High temperature dynamic lifetest 2) High temperature high voltage test 3) Data retention bake 4) Environmental stresses
The following sections briefly describe these tests and present the accumulated reliability data associated with the tests.
High Temperature Dynamic Lifetest
Most failure mechanisms encountered in semiconductor devices are accelerated at high temperatures. These failure mechanisms have a temperature dependence proportional to exp (-Ea/KT), where Ea is the activation energy of the particular failure mechanism, K is Boltzmann's constant, and T is the absolute temperature. The mathematical relationship is given by the Arrhenius equation. By testing at elevated temperatures and measuring failure rates, it is possible to extrapolate down to normal operating temperatures and predict the associated failure rates at these lower temperatures.
The high temperature dynamic lifetest consists of continually reading the devices at an ambient tem-
perature of + 125�C and a Vcc between 5.25V and
5.5V, while incrementing the addresses in a binary sequence. A known pattern is stored in the devices prior to insertion into dynamic lifetest. Each unit is tested for data retention and complete functionality after 48, 168, 500, 1000, 1500 and 2000 hours of dynamic lifetest. This is an effective stress for catching many types of semiconductor failures.
The results of the dynamic lifetest are shown in Table I for lots consisting of hermetically sealed ceramic DIPs (dual in-line package), and LCC (leadless chip carrier) packaged devices.
9-104
Lot#
01 02 03 04 05 (LCC) Totals
48 Hrs. #Fail #In
0 57 0 65 0 163 0 228
0 369
0 882
168 Hrs. #Fail #In
0 57 0 65 0 163 0 228
0 369
0 882
500 Hrs. #Fail #In
0 18 0 65 0 163 0 158
0 369
0 773
1000 Hrs. # Fail #In
0 18 0 65 0 163 0 158
0 369
0 773
1500 Hrs. #Fail #In
0 18 0 65 0 163 0 158
0 404
2000Hrs. # Fail #In
0 18 0 65 0 163 0 158
0 404
Total Device Hours
4.25 x 104 1.30 x 105 3.26 x 105 3.02 x 105
3.69 x 105
1.17 x 106
Table I: X28256 high temperature lifetest data. (+ 125'C, 5.25V)
High Temperature High Voltage Test
In this test Vss is grounded and all other pins including Vee are held at 5.5V. The devices are
stressed in an ambient temperature of + 150�C.
This stress is designed to catch failures related to ionic contamination, oxide defects and electrical overstress. Data retention and complete functionality are tested at 500 and 1000 hours. Table 11 contains the results of this testing.
Lot#
01 02 Totals
500 Hrs.
# Fail #In
0 283
0
19
0 302
1000 Hrs.
#Fail #In
0 283
0
19
0 302
Total Device Hours
2.8 x 105 1.9 x 104 3.0 x 105
Table II: X28256 high temperature high voltage lifetest data. (+ 15(J'C, 5.5V)
Data Retention Bake
This test consists of an unbiased bake ( + 250�C)
with a known pattern programmed into the part. The devices are removed periodically and checked for the proper data. After initial programming, array readings are taken at 48, 168, 500, 1000 and 2000 hours. This test is performed because high temperatures will cause any latent oxide defects to leak charge off the floating gate. Retention bake data is found in Table Ill.
Environmental Stresses
Environmental stresses are applied to the devices to ensure that they will continue to operate properly even during changing or extreme environments. The thermal stress test identifies failure mechanisms which are caused by differing coefficients of thermal expansion in the composition of the packaged devices: lead frame, bond wires, die and package. Temperature cycling data was taken for hermetically sealed devices using MIL-STD-883C, Group D, Method 1010, Condition C specifications. The devic-
es were cycled between - 65�C and + 150�C. The
results of this testing for 250, 500 and 1000 temperature cycles are found in Table IV.
Lot#
01 02 Totals
48 Hrs.
#Fail #In 0 18 0 65 0 83
168 Hrs.
#Fail #In 0 18 0 65 0 83
500 Hrs.
# Fail #In 0 18 0 65 0 83
1000 Hrs.
# Fail #In
0
18
0 65
0 83
1500 Hrs. #Fail #In
0 18
0
18
2000 Hrs. # Fail #In
0 18
0 18
Total Device Hours
3.6 x 104 6.5 x 1Q4
1.01 x 105
Table Ill: X28256 data retention bake results. (+25(J'C)
9-105
Lot#
01 02 03 Totals
250Cycles
#Fail #In 0 45 0 45 0 45 0 135
500Cycles
#fail #In 0 45 0 45 0 45 0 135
1000Cycles
# Fail #In 0 45 0 45 0 45 0 135
Table IV: X28256 temperature cycling data.
(-6S'C to + 150'C)
ENDURANCE
The endurance of a device is a measure of the ability of a nonvolatile memory to sustain repeated data changes. When the first single bit in the array is not capable of changing data states, the endurance limit has been reached. For the X28256, the endurance is limited by electron trapping in the tunnel oxide. This is because electrons get trapped in the silicon dioxide and accumulate, increasing the applied potential necessary for tunneling.
I
11 I
I I
I I
I
I
ti I
I I
11
I
lW !! !!!!! l!1:1 ~ ~ ~ !!!!~ !:!t!!!!!:!! !!? !!!!!!!~ !!!!!!!~ !~ !!! !! !!!!!
�:----�:--�:--1~---.iP. .-.T.. -__-_-_-_-_-_-_-_-',-_!1.-. _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _- _-_-_- _-_-_-_-:.-.. -__- _- _- _- _- _-_-_- -_
I,__ I,_I,_I!.._IJ._!I _________1 ,_!1._ ______________________________ I,__________ _
I
II I
I I
IL
I
~ 100K ::::::::::"~:::;:�:::;:::;::::::::::::::::::~::::;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::~::::::::::::::::::::::
~
:: ::::: ~:::::::::::: ::: ~::::::::::::::::::::::::::::: :~:::::: :: : :
,--,-,-i-1-;---------,-;------------------------------,-----------
11 -1-111-1�I r-IT�T�-----1-1--1-r------------------------------Ir-----------
: :: : : :
: :
TYPE X28256
:
10K :: :::::~::::::::: : : :::~:: :: : : : : : : : : : : : : : : : : : : : : : : : : : :~: :: : : : : : : : :: =:=:= ~: f: f::::: : : =:= ~::::::::::::::::::::::::::::: =:=::::::::::
:: ::::: ~ : ~ :~ ::::: ::::: :: ::::::::::::::::::::::: ::::::::: ::::::::::
1__1_1_L-l..I. ..... ---'-'-------------------------------L----------
:- -:-:- 1 II I
I
I
I I
I
~ - ~ - ~ - - - - - - - -:- :- - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - :- - - - -- - - - - -
t
11 I
It
I I
I
1K ' ''' ' '
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99
�5 2 10
50
CUMULATIVE PERCENT
0116-6
Note: Endurance cycling stopped at 1 million data changes to free cycling equipment for other tests.
Figure 5: Extreme value distribution plot tor X28256.
To measure endurance, the data in the array is alternately changed from erased to programmed states. The number of cycles necessary for the first single bit to fail is recorded for each unit in the sample. An extreme� value distribution plot is shown in Figure 5.
PREDICTION OF FAILURE RATES
As previously stated, stress testing makes it pos-
sible to accelerate failure rates. Failure rates at nor-
mal operating temperatures can then be predicted.
Most failure mechanisms associated with this de-
vice are accelerated by temperature, voltage or
both. Each failure mode has an associated activa-
tion energy (Ea). Four typical failure mechanisms
and their activation energies are:
Oxide Breakdown
0.3eV
Electromigration
0.55eV
Oxide Defect
0.6eV
Ionic Contamination 1.0eV
If the activation energy for a particular failure
mode is not known, it can be experimentally deter-
mined. Using the Arrhenius relation, Rate = R0 exp (-Ea/KT), we can relate the observed failure rate
at the elevated ambient temperature with the pre-
dicted failure rate at normal operating temperatures.
A detailed discussion of the pertinent calculations
can be found in Xicor publication RR-506A: Byte-
Wide NOVRAM (X2001 /X2004) Reliability Report.
Table V gives the predicted long-term failure rates
calculated for temperatures of + 55�C and + 70�C.
Both Best Estimate and 60% Upper Confidence
Level (UCL) failure rates are given. The Best Esti-
mate gives the most likely failure rate for the given
data, and the 60% UCL failure rate means that
there is a 60% probability that the true failure rate
will be less than the calculated value.
FIT rates can be obtained by multiplying the fail-
ure rates by 104. Therefore, the FIT rate at + 55�C is 172, and at + 70�C it is 305.
9-106
Activation Energy
0.3eV 0.55eV 0.6eV 1.0eV Totals
Number of
Failures 0 0 0 0 0
Equivalent Hours at 70�C
4.68 x 106 1.52 x 107 1.92 x 107 1.24 x 108 1.48 x 108
60% UCL Failure Rate per 1000 Hours at 70�C 0.0190 0.0060 0.0048 0.0007 0.0305
Equivalent Hours at
55�C
7.49 x 106 3.55 x 107 4.83 x 107 5.77 x 108 6.32 x 108
60% UCL Failure Rate per 1000 Hours at 55�C 0.0125 0.0026 0.0019 0.0002 0.0172
Table V: 60% UCL failure rate predictions for X28256.
SUMMARY
This reliability report presents descriptions of basic cell operation, specific tests and stresses used to determine the reliability of the X28256, and the data collected from these tests.
The data presented here shows that the X28256 is an extremely reliable memory device. Product reliability testing shows low semiconductor failure
rates, high end-of-life endurance figures, and the ability to successfully resist device degradation under conditions of environmental stress. Inherent data retention in these devices is in excess of 100 years.
This report is based on data collected through June, 1989.
9-107
APPENDIX A
Package Type
Product
Cerdip
LCC
X28256
f OJc OJA
2.5
23.0
f OJc OJA
2.0
47.0
Thermal Resistance Table: Bjc and 8ja expressed in �c per watt.
1.0 �F
A14+-------1 A12+-------1 A7+-------1 A5+-------1 A5+-------1 44+-------1
A3+-------1 A2+-------t I A1+-------t
~~:~I ..____ _ _ _ _I~==
CEA --1
(CLK-1)
L --
I" Ir-- J - I CEa
r'-
(CLK-,!>.
~LK-!t1~1-1_.o_-.{.J. " IT~
0
awn ~ ~ ~ a~~ M ~
TIME(�SEC)
0116-8
Notes: (1) Ao-A14: binary sequencing address cycle: 40 �s. (2) WE disabled (tied to Vee atdevice). (3) V1N Low: 0.4V V1N High: 5.0V (4) Vee: 5.50V
X28256 (DIP) Burn-in timing diagram.
0116-7
Note A: CLK-1: Rows 1, 3, 5 ... (odd rows-CEA) CLK-2: Rows 2, 4, 6 ... (even rows-CEs) Such that: CLK-2 = CLK-1
Note B: (1) WE must always be hardwired to Vee (Pin 28) at device as shown.
(2) All resistors: 1% metal film 1/4W
(3) 1/0 pull-up: 2.00 Kn 1/0 pull-down: 1.40 Kn
(4) Socket-to-socket isolation as shown.
X28256 (DIP) Burn-in circuit
9-108
RR-515
J(il:O'
100
50
Vi'
0::
:::c 20
0
q 0
Lt.I 1<C( 0:: Lt.I
~ 5
...J
~
2
50% FAILURE POINT ~
EA = 1.7 :t 0.1 eV
= MTBF 3,000,000 YEARS
AT 12s0 c
250� 300� 350� 400� TEMPERATURE (�C)
0119-1
DATA RETENTION IN XICOR E2PROM MEMORY ARRAYS
H. A. Richard Wegener
9-109
INTRODUCTION
In Xicor nonvolatile memory devices, data consists of ones and zeroes stored in the memory array in the form of charge retained on a floating gate. During the course of normal operation charges r:nay be added to or lost from the floating gate. The time elapsed between the original transfer of electrons by the act of programming or erasing, and the first erroneous read-out from that memory cell is called retention. The operating conditions during the time period considered may vary widely. Only those conditions permitted by the data sheet need to be considered in its definition. The memory device under consideration may be a single transistor, or it may be a large array of memory cells embedded in peripheral circuitry to function as an E2PROM. In either case, the first repeatable malfunction of one single memory cell during read-out defines the end of the retention of that particular device.
The intrinsic retention in Xicor E2PROMs is calculated to be many millions of years. However, defects introduced during the manufacture of the memory device may cause the retention to be less than the ideal intrinsic characteristic.
Retention is therefore a reliability problem, and its criterion is its failure rate. Xicor guarantees a failure rate expressed as "5 FITs at 55�C, 60% upper confidence limit". The meaning of this statement, and the reasons leading to it are explained in the paragraphs following this introduction. In most details, they are based on the section on Retention in the forthcoming IEEE Standard on Floating Gate Arrays.
FLOATING GATE RETENTION: A. �CAPACITOR DISCHARGE PROBLEM
a .Charge stored on floating gate may be thought
of as charge residing on one plate of a capacitor, separated from the other plate by the intervening dielectric. Even when all surrounding conductors are grounded, the potential due to the stored charges will cause a very slow discharge through the operation of the Fowler-Nordheim tunneling mechanism. Retention can be modeled and predicted by the expression:
tR = {C/AB} * EXP (B/Vt),
where tR is the retention time, C is the capacitance of the floating gate, Vt is the effective voltage due to the stored charge at which failure occurs, and A and B are constants of the Fowler-Nordheim equation.
When measured values for all the variables on the right-hand side of the equation are substituted, retention times well in excess of several million years are obtained. This long term retention is an intrinsic property of Xicor's proprietary floating gate memory technologies, and can be expected as a feature of all Xicor memory cells.
At high temperatures, electrons will also be transferred by Schottky emission, which is dependent on temperature, activation energy, and applied field. This mechanism is described by the Schottky-Richardson equation, which has the form describing the forward current in a Schottky diode. It is this mechanism that gives rise to a temperature dependence of retention, and a measurable activation energy of 1.7eV. With intrinsic retention times exceeding millions of years in the operating temperature range, it is clear that real time retention data cannot be measured. Only under extremely high accelerating temperature conditions can retentions on the order of months be measured. These measurements can then be translated into retention times of approximately 50 billion years at 55�C.
In rare and isolated instances, physical process defects can occur in a memory cell. These defects may give rise to new values for the cell variables and thus result in shorter retention times for the affected cell. Activation energies of 0.6-0.8eV have been measured for such defects.
Retention in Integrated Circuits
The distinctions between retention in a single memory cell and in an integrated system such as a memory device are threefold: First, there are typical�1y .�a large number of cells in any memory device. Since a data retention failure is determined by the first cell to fail, data retention in the device is statistically dependent on both the number of cells and their distribution.
Second, being part of a larger system, the cells are exposed to a more varied set of operating conditions. This is due to the diverse needs of the system represented by the chip, and not the simple requirements of a single cell.
Third, the presence of a very large number of cells increases the probability that one of them will contain a defect. In high density E2PROMs it can therefore be expected that retention (the failure of the first cell) will have a component, however small, that is determined by the defect density inherent in the technology. Structural defects which give rise to infant failures can be eliminated by production
9-110
screens. However, the ultimate retention failure rate is caused by statistical defects inherent in any given oxide process.
The Reliability Aspects of Retention
The specification of retention is a way of specifying the life expectancy of the data stored in a memory device. The concern for retention is with failures occurring in three phases of the devices' life cycle: a. early in life (infant mortality); b. random failure rate during normal use; and c. the intrinsic failures near the end of life. This can be illustrated by the typical aspects of the classic "bathtub curve", shown in Figure 1.
INFANT MORTALITY
FAILURE RATE
RANDOM FAILURES
WEA ROUT
LOG TIME
0119-2 Figure 1: Illustration of bathtub curve of failure rates showing regions in which infant mortality, random failures and wearout mechanisms dominate.
Infant mortality cases are screened out by specific tests before shipment of the product. Some will fail during initial write-erase operations. Some are found by an accelerated voltage stress. Others are caught during a 48 hour storage at 150�C. The last are eliminated by a combination of endurance cycling and retention bake. A constant random failure rate is an indication that infant mortality cases have been eliminated. Since infant mortality failures are screened out during normal testing, they need not be considered a system (end user) reliability problem.
Intrinsic retention failures at the end of device life are determined by the structural design, technology and processing of the memory cell. These failure rates give rise to data retention times many orders of magnitude larger than equipment lifetimes. Successful measurements of intrinsic retention values have required temperatures of 300, 325 and 340�C to determine mean intrinsic retention times of 3000, 90, and 330 hours respectively, and an activation energy of 1.7eV. These translate into retention
times of 1.2 million years at 125�C, 3.6 billion years at 70�C and 50 billion years at 50�C. This was demonstrated in Xicor's Reliability Report RR-502A.
The high accelerating conditions make an exact linear extrapolation to normal temperatures difficult with major additional work. Thus, this type of analysis serves mainly to confirm the very large retention times predicted for floating gates obeying FowlerNordheim tunneling laws.
This leaves the specification of the random failure rate during normal use as the most practical measure of data integrity. A common measure of the random failure rate is given by the number of failures per 1000 device hours, or the percentage of failures per 1000 hours, both of which can be expressed as FITs ([Number of failures x 1E9]/[Number of devices x Number of hours tested]). Since a random failure rate has to be determined under accelerated temperature conditions, the specification must include the temperature to which the accelerated data have been normalized. In addition, a confidence level must be included which (by standard statistical techniques) weights the failure rate estimate according to the number of data points used in deriving it.
Xicor's Specification of Retention
The Xicor specification for retention is a failure rate of "5 FITs (upper bound at the 60% confidence level) at 55�C". This follows the practice established for (UV erasable) EPROMs, which is a floating gate memory technology with a fifteen year data base.
The value of 5 FITs represents a mean time to failure of 25,000 device years. Another way of expressing this is as a failure rate for a specified reten-
tion time. For a 1o year retention, the failure rate is
0.044%. For comparison, typical (UV erasable) EPROM
products have retention failure rates of 20 FITs. The lower failure rate of E2PR0Ms is due to the fact that their internal high voltage capability acts to cause immediate failures due to defects that would not be affected by the lower voltages in UV erasable EPROMs.
The retention specification as given, includes the failure rate stated as failure units ("FITs"), the temperature at which it is valid, and the statistical confidence level valid for the stated failure rate. For its significance in typical commercial applications and for easy comparison with similar EPROM data, Xicor has chosen 55�C as the reference temperature.
9-111
This is the temperature to which the �data taken at accelerated temperatures are normalized. The normalization is performed by the accepted use of the Arrhenius equation, and an activation energy of 0.6eV. Failure rates at other temperatures� can also be calculated from the specification given at 55�C, with the help of the same Arrhenius equation and the activation energy of 0.6eV.
The use of a confidence level follows standard reliability practice. When only a few data points (retention failures per year) are recorded, there is a finite chance that they were the result of fluctuations that will make the measured failure rate appear better than the true average. Multiplying the experimental failure rate by the proper factor increases it enough to ensure that it will include 30% of the data that are larger than the average. When this factor has been used, the failure rate is reported at the "60% confidence level (upper bound)". In principle, the choice of a confidence level (expressed as a percentage) is somewhat arbitrary. However, once a given level has been defined, the failure rate stated under its condition can be converted to the value proper for any other level. The 60% level chosen for this specification has the advantages of simplicity and industry acceptance.
The Determination of Retention Failure Rate
For the measurement of retention failure rates, the acceleration required is somewhat reduced~ The activation energy of the mechanism involved in the random failure of floating gate retention has been determined to be near 0.6eV in both (UV erasable) EPROMs and in E2PROMs. In order to confirm a failure rate to be equal to or lower than 5 FITs (upper bound at 60% confidence level, at 55�C), at least 75 devices must be stored for 1000 hours (6 weeks) at 250�C. For zero failures at 60% confi-
dence level: 1I(75*1000) = 13,333 FITs. When this
is divided by 2, 724 to extrapolate from 250�C to
55�C the result is 5 FITs. This high temperature necessitates ��the use of ceramic packages. Plastic packages are limited to a temperature of 150�C. At that temperature, a much larger number of devicehours is necessary to confirm a rate of 5 FITs.
The actual retention failure rate is determined by a test called the "Retention Bake". The devices are stored unpowered at high temperature with a preset (typically checkerboard) data pattern. Devices in plastic packages are stored at 150�C, and ceramic package devices are stored at 250�C. They are then read from time to time. The failures are analyzed, and some are identified as retention failures.
SUMMARY
The time of retention for data in a Xicor E2PROM memory cell is inherently on the order of millions of years. This can be projected theoretically on the basis of a closed form mathematical expression for charge loss that has been verified experimentally. This can also be confirmed by extrapolating experimentally obtained data at high temperatures to normal operating temperatures.
The exact knowledge of this intrinsic retention would be unimportant if every device met its true design and production characteristics. It is the rare presence of defects that introduces the small probability of lower retention times. Retention is therefore a reliability problem, and Xicor has approached it as such.
The failure rates as a function of time have the typical aspects of the bathtub curve. Potential "infant mortality" failures are eliminated by a sequence of screening steps. The "end-of-life" failures are expected to occur a few million years hence. The one characteristic of interest that remains is the "random" failure rate. This failure rate is determined experimentally from Retention Bake data. Based on this experimental data Xicor guarantees retention failure rate of 5 FITs at 55�C at the upper bound of the 60% confidence limit.
9-112
�1:1,
RR-516
0115-1
LATCH-UP CONSIDERATIONS IN XICOR CMOS PROCESSES
9-113
INTRODUCTION
Latch-up is an inherent problem in CMOS devices due to the fact that during processing, MOS FETs are not the only structures fabricated. Parasitic bipolar transistors are also created which act as siliconcontrolled rectifiers (SCRs). Since latch-up is inherent in the process, all CMOS devices can be forced into the latched state. The focus in designing CMOS devices is to reduce latch-up susceptibility under normal, and sometimes harsh, operating conditions. Design methods used by Xicor to reduce this susceptibility will be discussed.
CELL STRUCTURES AND LATCH-UP
The structures of interest for Xicor's 1.8 �m and 1.4 �m CMOS processes are illustrated in Figure 1.
The vertical PNP transistor has its emitter and col-
lector formed by the P+ source/drain diffusion and
the P type substrate respectively. Its base is N-well. In the lateral transistor, (the NPN), the base is a P
type substrate with the emitter formed by N +
source/drain diffusion and an N-well collector. These two bipolar transistors are cross-coupled with common base-collector regions. Under normal bias conditions, the complementary PNP and NPN transistors remain in the high impedance state, which is referred to as the blocking state. Latch-up can be initiated only when one of the bipolar transistors becomes active. If current flows through any of the parasitic resistors and causes a sufficient voltage drop across the base-emitter junction, one of the parasitic bipolar transistors can be turned on. This forward bias condition of the junction allows collector current to flow. The collector current that flows across the base-emitter resistor of the second parasitic bipolar transistor can cause a sufficient voltage drop to turn on this second transistor.
P+ SUBSTRATE
1.8 ,.._m CMOS process
0115-2
P+ SUBSTRATE 1.4 ,.._m CMOS process
Vss
Vee
Vee
0115-3
Figure 1: Xicor CMOS processes.
Vee Process equivalent circuit
9-114
0115-4
If the current gain of the two transistors and the values of the parasitic resistors are high enough, a regenerative condition is created between the complementary bipolar transistors, where each continues to drive the other. The current in both transistors will increase until either the self limiting condition is reached or the device is destroyed. This high current, low impedance state of the SCA is known as "latch-up".
Latch-up can be destructive to the device when the metal lines are blown or the junctions are melted, or it can be nondestructive. In the second case, the chip can be restored to the blocking state by a power-down and power-up sequence.
CAUSES OF LATCH-UP
There are numerous ways in which latch-up can be triggered. The most common ways are during: power-up; supply overvoltage; and pin overvoltage and undervoltage. These conditions are discussed below.
Power-Up
Latch-up can occur when the pins of the device are driven high before the supply voltage has been applied to the circuit. This situation can occur when an unpowered circuit board or device is plugged into a system that is already under power.
Figures 2 and 3 illustrate the test set-ups for both the slow power-up and the fast power-up tests. Results of these tests are presented in Tables I and II.
- - - - - mA - - - - . Ice MEASUREMENT
Vee
DUT
+
VsuPPLY
TOINP+U6TVPOINLTSS _ _ _ _GN,.._ o ___.
OUTPUT PINS TO +6 VOLTS
Block diagram
0115-5
Ice MEASUREMENT
5 VOLTS -----------1------------1------------r-----------1-----------4 VOLTS -----------1------------!------------1------------'
3 VOLTS -----------(----------i------------' 2 VOLTS -----------1------------:
1 VOLT
VsuPPLY
Figure 2: Slow power-up test set-up.
~35 ms-j-10 ms t6.5 mst6.5 ms~
Typical timing diagram
RISE TIME
0115-6
9-115
Characteristics: Test conditions:
Maximum Ice: Latch-up condition:
Ice latch-up current due to input and output pins in an overvoltage condition during power-on ramp.
All inputs and data outputs equal to Vee + 1V minimum. Vcc ramps from OV to 5V in 1V steps, ramp rate is less than or equal to 0.2V/ms.
80 mA
Ice 2 80 mA
Temp: +25�C
Ice (in �A)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 650 750 613
X28C010
1.4�m 85 2.3mA 70
Temp: -55�C
Ice (in �A)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 860 900 800
X28C010
1.4 �m 330 2.8mA 290
Temp: + 125�C
Ice (in �A)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 530 540 520
X28C010
1.4 �m 300 2.0mA 65
Table I: Results of slow power-up test.
_ _ _ __, mA " " - - - - -
Vee
OUT
Ice MEASUREMENT
+
VsuPPLY
INPUT PINS TO GND
GND OUTPUT PINS TO GND
Block diagram
Ice MEASUREMENT
0115-7
VsuPPLY
Figure 3: Fast power-up test set-up.
0 VOLT�-----------' -] 150ns
Typical timing diagram
9-116
0115-8
Characteristics: Test conditions:
Maximum Ice: Latch-up condition:
Ice latch-up current induced by hot socketing.
All inputs and data outputs equal to OV. Vee ramps from OV to 6V in 200 ns or less.
100 mA
Ice 2 100 mA
Temp: +25�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 8.5 9.9 8.0
X28C010
1.4�m 13.0 16.4 11.1
Temp: -55�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 11.5 13.2 10.5
X28C010
1.4�m 16.0 19.9 14.6
Temp: + 125�C
lcc(in mA)
Product Type Process Typ. Max.
X28C64,C256 1.8�m 7.0 1oolal
X28C010
1.4 �m 11.0 13.6
[al Latch-up induced only for conditions where Vee ;;>: 5V
Min. 5.8 9.9
Table II: Results of fast power-up test.
Supply Overvoltage
A supply voltage exceeding the absolute maximum rating can cause an internal junction to break down or produce a substrate current that triggers latch-up.
Figure 4 illustrates the test set-up for the supply overvoltage test. The results of this test are presented in Table Ill.
- - - - - - 1 mA 1-----.
Ice MEASUREMENT
Vee
OUT
+
VsuPPLY
INPUT PINS
GND
TO VsuPPLY
OUTPUT PINS TO OPEN
0115-9
Block diagram
" " N' l 15 vorn ----------nn-------------v
Ice MEASUREMENT
4.5 VOLTS --------------:--~
__/!, 0 VOLT ______
: :
~ :-- N : :
: :
: :
~ ~1ms 1 ms : :
VsuPPLY
-::-1ms::
:: -! !-3ms
! r- -j -j r- -j I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1.3 s
~ 4. 1 s
1.6 s
Typical timing diagram
0115-10
Figure 4: Supply overvoltage test set-up.
9-117
Characteristics: Test conditions:
Maximum Ice: Latch-up condition:
Ice latch-up current due to supply overvoltage.
All inputs are tied to supply. All data outputs are open. The unit is powered up to 4;5V, then 15V is applied to the Vcc pin. Measurement is done at 4.5V Vee. after the 15V pulse.
100 mA
Ice 2: 100 mA
Temp: +25�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64, C256 1.8�m 7.15 8.00 6.25
X28C010
1.4�m 11.5 12.2 10.5
Temp: -55�C
Product Type X28C64,C256 X28C010
Process 1.8�m 1.4 �m
lcc(in mA) Typ. Max. 8.10 9.56 10.1 97.0[a]
Min. 7.02 151 �A
Temp: + 125�C
Ice (in mA)
Product Type Process Typ. Max.
X28C64, C256 1.8�m 4.00 100[a]
X28C010
1.4 �m 12.5 96.0[b]
[a] Latch-up induced for overvoltage ~ 14V [b] Latch-up induced for overvoltage ~ 13V
Min. 3.31 7.08
Table Ill: Results of supply overvoltage test.
Pin Overvoltage and Undervoltage
Ringing, or noise glitches on the 1/0 pins, can create a transient forward bias condition at the 110 junction. If the transistor is part of a susceptible latch loop, latch-up could result.
Figures 5 and 6 illustrate the test set-ups for both the pin overvoltage and the pin undervoltage tests. Results of these tests are presented in Tables IV and V.
Characteristics:
Ice latch-up current due to pin in overvoltage condition.
Test conditions:
Untested inputs tied to supply of 4.5V. Untested outputs are open. Triggered voltage of + 15V (with max. 100 mA) is applied to pin under test.
Maximum Ice:
100 mA
Latch-up condition: Ice 2: 100 mA
Temp: +25�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64, C256 1.8 �m 7.30 7.70 5.30
X28C010
1.4 �m 11.0 13.1 10.0
Temp: -55�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8 �m 8.00 8.90 6.60
X28C010
1.4 �m 8.00 9.50 7.40
Temp: + 125�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8 �m 3.90 3.95 3.60
X28C010
1.4 �m 14.5 15.6 11.7
Table IV: Results of pin overvoltage test.
9-118
------1 mA ----
Ice MEASUREMENT
PIN UNDER TEST
OUT
+ VsuPPLY
INPUT PINS TO VsuPPLY
GND OUTPUT PINS TO OPEN
Block diagram
0115-11
'cc MEASUREMENT
-_! 1 ms - ; _:__-_ _ _ _ _ _ _ 1 ms r::,
~:,::~ �����������������,�1.�2I.�9���s�.:��
VsuPPLY
:~
0 VOLT------------""'
Figure 5: Pin overvoltage test set-up.
Typical timing diagram
0115-12
------1 mA ----
Ice MEASUREMENT
PIN UNDER TEST
OUT
+ VsuPPLY
INPUT PINS TO VsuPPLY
GND OUTPUT PINS TO OPEN
Block diagram
0115-13
r-- 1ms-;
'cc MEASUREMENT ;....__ 1 ms
4.5 VOLTS------------------:---~!::::________...,....._
0 VOLT���--�-
VsuPPLY
0 VOLT-------
-~!'""!"---
::2--.9-.s.:: -10 VOLTS ------------------~--i------i-
: : : : 1 ms -i
: : --: !-1ms:
:: ::
:
Typical timing diagram
VTRIGGER
0115-14
Figure 6: Pin undervoltage test set-up.
9-119
Characteristics:
Ice latch-up current due to input/output pins in undervoltage condition.
Test conditions:
Untested inputs tied to supply of 4.5V. Untested outputs are open. Triggered voltage of -1 OV (with max. -100 mA) is applied to pin under test.
Maximum Ice:
100 mA
Latch-up condition: Ice ~ 100 mA
Temp: +25�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 6.0 6.5 5.1
X28C010
1.4 �m 10.5 12.3 10.1
Temp: -55�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 6.5 7.6 5.3
X28C010
1.4 �m 15.0 22.3 11.4
Temp: + 125�C
lcc(in mA)
Product Type Process Typ. Max. Min.
X28C64,C256 1.8�m 3.8 4.3 2.9
X28C010
1.4 �m 10.0 32.8 9.6
LATCH-UP SUSCEPTIBILITY IN XICOR CMOS PRODUCTS
In order to increase the immunity of its CMOS products against latch-up, Xicor employs several methods in its product design. These include:
1) Negative substrate bias: A -3.5V Vss generator prevents transient forward biasing of the baseemitter junction of the SCR.
2) Large spacing between the N + diffusion area and the N-well during processing eliminates the potential for the parasitic NPN to be active.
3) An epitaxial layer on a low resistivity substrate reduces the parasitic resistance, and lowers the gain of the lateral transistor.
4) Guard rings around the diffusion area reduce substrate current and substrate resistance.
5) All input and output buffers are connected only to N + diffusions. No connections to P + diffusions (P-channel source or drain) are made.
TESTING FOR LATCH-UP
Xicor characterizes the latch-up susceptibility of its 1.8 �m and 1.4 �m CMOS devices by following specifications defined in MIL-M-385101750. These test procedures are recommended by the JEDEC JC-40-2 CMOS Logic Standardization Committee. The X28C64 and X28C256 were used to test the 1.8 �m process, while the X28C01 O was used to test the 1.4 �m process.
Table V.� Results of pin undervoltage test.
9-120
CONCLUSION
Data accumulated from the various stress tests show that Xicor's CMOS products exhibit excellent latch-up immunity. These CMOS devices are carefully designed and fabricated under the design and process rules which were discussed previously. This ensures that Xicor products operate in the blocking state even under harsh operating conditions.
REFERENCES
1. R. R. Troutman, "Latch-Up in CMOS Technology", Kluwer Academic Publisher, Massachusetts (1986).
2. L. A. Glasser, D. W. Doberpuhl, "The Design and Analysis of VLSI Circuits", Addison-Wesley Publishing Company, Inc., (1983).
3. N. H. E. Weste, K. Eshraghian, "Principles of CMOS VLSI Design: A System's Perspective", Addison-Wesley Publishing Company, Inc., (1983).
4. A. G. Lewis, "Latch-Up Suppression in Fine-Dimension Shallow P-Well CMOS Circuits", IEEE Trans. Electronic Devices, vol. ED-31, No. 10, October 1984.
5. A. Ochoa, Jr., "A Discussion of the Role of Distributed Effect in Latch-Up", IEEE Trans. Nuclear Science, vol. NS-28, No. 6, December 1981.
6. "Latch-Up in CMOS Integrated Circuits", EIA JEDEC JC-40-2 CMOS Logic Standardization Committee, 1987.
7. Military Specification, MIL-M-385101750.
This report is based on data collected through June, 1989.
9-121
NOTES
9-122
RR-518
ENDURANCE PROBABILITY CHART Data Changes as log(Cycles)
10 r::::-.::::::::::;::-_=::==:p:::::::::::;:::.:==::::;:---~F=r-=-~~-:r:=j=;--��~:=.::F::::::::-~�---.::t
:---~~�'_-_-_-_:-:_-:j 1-�----+---�Jfi=i_ ~Z-f-1
1M :~_:= - ~=~ - :=~-~ g~~-�.��3.�����~.~-~-~'.-~~.� ~. ~- =L�.-1:_t�i,-~-i,.~.:=~.Li
: .��._f~._--_--_--.-,'_-_-~_----_ -~-:',- ----��-.- i-------~.-----------;--~--+---t-----i -�
+----1--1-..-:-:~.~
_ _ __ ~=-==-�--+
-~-~-. . _... --
..
. .
--+--+_____ +�-�----�-t�---------�,,�;_!_--_-,.--..;.--_-_--_+,;.-----+----+----+-.-..-..-_-_+~,_-_-+__-.+__-..,......_--..�.:...___.._+_-.._+._-_-,.+-+--+---!i
___.;.-:__._____, .L--~:
Cumulative Percent
0122-1
X24C01 RELIABILITY
REPORT
9-123
INTRODUCTION The X24C01 Is a 1'024-bit .serial E2PROM, internally organized as thirty-two 4-byte pages. Like all Xicor products, the X24C01 employs Xicor's Textured Poly Floating Gate technology, which has been
demonstrated to be the optimum technology for
full featured nonvolatile memories.
Reliability Studies and Results
At Xicor, all new products are subjected to a series of tests before the device is qualified. In these tests, the device is stressed at elevated voltages and high and low temperatures. The purpose of these tests Is to accelerate standard semiconductor infant mortality failures and any potential defects that may occur as random failures during the device's normal useful lifetime. These data are then used to predict semiconductor failure rates under normal operating conditions.
In addition, Xlcor has undertaken� studies to determine characteristics unique to nonvolatile memories, such as retention and endurance. This report also Includes a group of standard environ. mental tests to Insure reliable operation under all extremes. Explained below are the tests and stresses to which the X24C01 was subjected.
High Temperature Dynamic Life Test
In the High Temperature Dynamic Life Test, (DLT) the device array is first written with a topological
checkerboard pattern. It Is then subjected to a temperature of 125�C at 5.5V In a continuous sequential read mcx:Je. All units are tested for retention and functionality at readouts at 48 hours, 168 hours, 500 hours, 1000 hours and 2000 hours.
This test is designed to accelerate early life failures, (first 48 Hours) and to uncover latent defects that would be seen as random failures during the normal useful lifetime. These data, along with the HTHV data are used to predict actual field reliability for the device. The DLT test results are shown in Table 1.
In addition, all units submitted to the tests and stresses that follow, are first subjected to DLT for 168 hours. The test lots are then divided, with some units continuing DLT and the balance split among other tests.
High Temperature High Voltage (HTHV)
The purpose of this stress is to accelerate failures due to mobile ionic contamination, electrical overstress and latent gate oxide defects. In this stress, a static bias is established throughout the circuit by applying 5.SV to all pins while Vss is held at
ground in an ambient temperature of 15o0 c. The
units are stressed for 1000 hours, with readouts occurring at 48 hours, 168 hours 500 hours and 1000 hours. The results of the tests are shown in Table 2.
Lot#
1 2 3 4
5
6 Totals
48 Hours 168 Hours
IN Fail In Fail
905 1(b) 904
0
979 0 979 0
1036 11Df 1035 0
1000 0 1000 0
996
0
996 2(cT
189 0 189 0
5105 2 5103 2
500 Hours
In Fail 150 0 143 0 149 0 150 1(a) 149 0 49 0 790 1
1000 Hours
In Fail 150 0 143 0 149 0 149 0 149 0 49 0 789 0
2000 Hours
In Fail
150 0
143 0
149 0
149 0
149 0
49
0
789 0
Total Device Hours*
383 280 379,456 397,168 393,300 392,488 112,448 2,058,140
Note:
a. Ionic Contamination b. oxide breakdown c. Leaky Select Transistor
* Device-hours excludes the first 48 hours
= = Table 1. X24C01 Dynamic Life Test. Vee s.sv and TA 12s�c
0122-2
Lot#
1 2 3 4 5 6 Totals
168 Hours
In
Fail
35
0
48
0
50
0
48
0
52
0
25
0
258
0
Note: b. oxide breakdown
500 Hours
In Fail
35
0
48
0
50
0
48
0
52
0
25
0
258
0
1000 Hours
In Fail
35
0
48
0
50
0
48
0
52
0
25
0
258
0
Total Device Hours
35..1..000 48000 50,000 48_,_000 52,000 25,000 258,000
Table 2. X24C01 High Temperature High Voltage Test. Vee = 5.5V and TA= + 150�C
Failure Rate Calculation
Determining The Failure Rate Unit
If there is one failure in 20,000 devices in 1000 hours, the failure rate will be:
1 failure 20,000 devices x 1000 hours
= 5 x 10-
a
The failure rate of a device is calculated in FIT (failure unID. One FIT is defined as one failure in
1o9 device-hours. Thus, the above failure rate is:
= 5x10-8 x 109ta1'/Ures
109 device- hours
50 F/Ts
As previously mentioned, the results from the DLT and HTHV tests allow one to predict the long-term failure rates for the device under normal operating temperature and voltage conditions.
Acceleration Factors
Each failure mechanism accelerated by temperature is associated with an activation energy Ea. the reaction rate at which a process is accelerated by temperature is given by the Arrhenius equation4:
R = Ro exp (- ; ; )
Where:
Ea = Activation Energy
T = Absolute Temperature k = Boltzmann's Constant = 8.62 x 10 eVl�K
For a given activation energy, where t1 and t2 are the times to failure at the normal operating temperature of T1 and the stress temperature T2, respectively, then the relationship between the times to failure is :
-Ea
TAF = !.!_ = exp
t2
kT2 - Ea
=
exp
{kEa x
( 1
T1
-
T12) }
exp kT1
Where:
TAF = Temperature Acceleration Factor T1 = Operating Temperature T2 = Stress Temperature
Knowledge of a particular failure mode's activation energy allows one to predict long-term failure rates under normal operating conditions.
Typical failure mechanisms and their corresponding activation energies are:
Oxide Breakdown Metal Electromigration Oxide Defect Silicon Electromigration Ionic Contamination
0.30eV 0.55eV 0.6eV 0.90eV 1.0eV
9-125
0122-3
Ealn eV
0.30 0.55 0.60 0.90 1.00
Total Device Hours
@+125�C 1@+150�C 2.058E+6 2.58E+5 2.058E+6 2.58E+5 2.058E+6 2.58E+5 2.058E+6 2.58E+5 2.058E+6 2.58E+5
#of Fails
0 0 2 0 1 3
Equivalent Device Hours
Calculated Failure Rate
Jl=ITI
60% UCL Failure Rate
1Fffi
@+ss0 c @+10�c l@5s0 cI@10�c l@ss0 cI@7o0 c
1.682E+7 1.08E+7 0
0 59.46 92.90
8.472E+7 3.60E+7 0
0 11.80 27.74
1.183E+8 4.66E+7 16.89 42.93 25.34 64.40
9.082E+8 2.24E+8 0
0 1.101 4.459
1.816E+9 3.84E+8 0.550 2.605 1.101 5.210
17.45 45.54 98.82 194.7
Notes:
1. One FIT = 1 failure In 109 device-hours. To convert to failure rate percent per 1000 hours
divide FITs by 10,000
'
2. Failures from 48 hour DLT are excluded, since such failures are considered infant mor-
talities and are minimized by extensive screening prior to shipment.
Table 3. Summary of Semiconductor Failure Calculations for the X24C01.
For time dependent gate oxide breakdown (Ea = 0.3eV), there Is also a voltage acceleration factor fVAF) given by Crook's equatlon5, as follows:
VAF = exp (-EEs --1-Ed)
where: Vs
Es = stress field =-:;;-
�ox
Ed = operating field = ~d �ox Tox = Gate Oxide
Et = Field Constant = 0.062MV/cm
Table 3 contains the .results of these calculations. Also included In the table Is the 60% upper confidence level (UCL) calculation. This indicates that with a 60% confidence the actual failure rate will be below that calculated. We also made the conservative assumption of including the Oxide Breakdown, Metal and Silicon Electromigration ( Ea = 0.30, Ea = 0.55eV and Ea = 0.90eV respectively)
failure rates. These failure mechanisms should be
included whether they were observed or not, since
they could be anticipated.
Data Retention Bake
Data stored in E2PR0Ms are associated with the absence or presence of electrical charge stored on the floating gate. A device is considered to have failed if the charge leaks off the floating gate. A floating gate at equilibrium ( + and - charges are equal) will be read as one or zero depending on the sense amp circuitry.
Therefore, in order to test for leakage, a charge is placed on the floating gate such that when the cell
is read it will be opposite to that read at equilibrium. After being written with the specified pat-
tern, the units are baked for 2000 hours at 1so�C, with readouts occurring at 500 hours, 1000 hours and 2000 hours. The results of the tests are shown In Table 4. A retention FIT rate calculation was also performed and is shown in Table 5. It should� be noted: based on Xicor studies on data reten-
oo tion of all its memories Xlcor specifies 1 +
years data retention. For details on data retention In Xicor memories refer to Reliability Report RR515.
0122-4
9-126
Lot#
1 2 3 4 5 Totals
48 Hours
IN Fail 34 0 34 0 34 0 34 0 34 0 170 0
168 Hours
In Fail
34
0
34 0
34
0
34 0
34 0
170 0
500 Hours
In Fail 34 0 34 0 34 0 34 0 34 0 170 0
1000 Hours
In Fail
34 0
34 0
34 0
34
0
34 0
170 0
2000 Hours
In Fail
34 0
34 0
34
0
34
0
34 0
170 0
Total Device Hours* 68000 68000 68,000 68000 68000 68,000 340 000
Table 4. Data Retention Bake@ 1so0 c
Ea in eV
Total Device Hours
@_+125�C __@_+ 1so�C
0.60
0
3.40E+5
Totals
#of Fails
0 0
Equivalent Device Hours
Calculated Failure Rate
_(_FITl
60% UCL Failure Rate
J.FITl
_@_+55�C __@_+ 70�C l@55�C l.@_10�c l@_ss0 c l@_10�c
4.077E+7 1.60E+7 0
0 24.53 62.35
0
0 24.53 62.35
Table 5. Data Retention Failure Rate Calculations
Extended Endurance and Data Retention
Devices must retain correct data after long-term operation. A stress called endurance/retention is designed to examine a device's performance at retaining data after repeated write cycles to all memory locations. In this test, all units are subject to 100,000 write cycles, followed by a static bake at + 150�C. After the bake the devices are tested for data retention and functionality. The results of the test are shown in Table 6 below.
Lot#
3 4 5 Totals
100 K Cycle
In
Fail
50
0
32
0
49
0
131
0
168 Hours@
150�C
In Fail
50
0
32
0
49
0
131
0
Table 6. Endurance/Data Retention
End of Life Endurance
Long-term operational life of a device is also measured by how long it can endure repetitive data changes. This is the purpose of endurance testing. In this test the units are subject to continual data changes until the first bit in its array is read incorrectly. There are two major methods of cycling: block or mass mode, where the entire array is changed in one cycle; and page cycling, where each physical row is cycled in one operation, requiring 32 write operations to cycle the entire array one time. The data shown in the endurance probability chart in Figure 1 were collected by page cycling.
This probability chart is a tool developed by Xicor to fit the endurance limit of the weakest bit in the entire array to an extreme value distribution. The ability of Xicor to use this method is a result of the Textured Poly Floating Gate technology employed. This technology has one prevalent failure mechanism, trap-up, which is the diminishing cell program margins due to electrons trapping in the tunneling oxides.
0122-5
9-127
ENDURANCE PROBABILITY CHART
Data Changes as Log(Cycles)
�--:::---��..�-:�--'"=::::�-���-�-�-��-
sure temperature cycling will not have detrimental effects on the combination of materials used.
�-�-----�-�-----�-�--~-
-'---+-...,.--;~�-..........~'--
0.1 0.2 0.5
2
10 15 20 30 40 50607080 9095 99 99.9
Cumulative Percent
Figure 1.Typlcal X24C01 Lot Endurance
Low Temperature Dynamic Life Test
As geometries of semiconductor memories are scaled down, hot electron trapping in the gate oxides has been detected in other technologies. In order to determine if hot electron trapping could impact the reliability of the X24C01, a Low Temperature Dynamic Life test was performed. This test is functionally identical to the DLT test, but with the ambient temperature set at -40�C. The test results in Table 7 indicate hot electron trapping is not a concern with the X24C01.
The three major failure modes for plastic packaged devices under moisture test are:
- Mobile Ions - Ions on the passivation glass are made more mobile by humidity. If enough charge transfer occurs, a device parameter could be altered or a parasitic transistor could be introduced, degrading device performance.
- Chemical Corrosion - Phosphorous Is commonly used In the passivation and under metalization layers. Sufficient phosphorous, when combined with water molecules, produces phosphoric acid which may etch away aluminum lines.
- Electrolytic Corrosion - When a voltage potential exists between two adjacent metal lines under enhanced surface conditions, (presence of moisture) an electrolytic corrosion process may be triggered. This condition could result in an open metal line.
Autoclave
Autoclave or pressure pot testing subjects a device to a 2 atmosphere steam environment. This test will accelerate mobile ionic drift, chemical corrosion and to some extent electrolytic corrosion. The test results are summarized in Table 8.
Lot#
48 Hours 96 Hours 144 Hours
Device Hours
Lot# 168 Hours
In Fail
1
50
0
2
52
0
3
50
0
4
50
0
5
50
0
6
25
0
Totals 277 0
500 Hours
In Fail
50
0
52
0
50
0
50
0
50
0
25 0
2n 0
1000 Hours
In Fail
50
0
52
0
50
0
50
0
50
0
25 0
2n 0
Device Hours
50,000 52,000 50,000 50,000 50,000 25,000 2nooo
1 2 5 Totals
In Fail In Fail In Fail 52 0 52 0 52 0 52 0 52 0 52 0 52 0 52 0 52 0 156 0 156 0 156 0
Table 8. Steam Autoclave
85�C/85% Relative Humidity Stress
7488 7488 7488 22464
Table 7. Low Temperature Dynamic Life Test ENVIRONMENTAL STRESSES
85/85 testing is performed to determine life expectancy of devices in high temperature and high humidity environments. This test will accelerate all three environmental failure modes. It is an especially good test for detecting electrolytic corrosion.
This group of tests is performed on plastic packages to insure that excessive humidity and ambient vapors will not cause failures and also to in-
85/85 tests can be performed In two ways. The
first is by supplying voltage to Vcc with all other pins alternately biased at OV and + 55.V. The
0122-6
9-128
second method Is to test the device with Vee at
ov ov and all other pins alternately biased at and
+5.5V. This provides a potential between metal lines and Insures maximum humidity at the die surface. Results of these tests are shown lnTables 9
and 10.
Lot#
1 2 5 Totals
500 Hours
In
Fail
52
0
52
0
52
0
156
0
1000 Hours
In
Fail
52
0
52
0
52
0
156
0
Device Hours
52,000 52,000 52,000 156,000
Table 9 � 85/85 (power off)
Lot#
1 2 5 Totals
500 Hours 1000 Hours 2000 Hours
In Fail In Fail In Fail 52 0 52 0 52 0 52 0 52 0 52 0 52 0 52 0 52 0 157 1 156 0 156 0
Device Hours
104,000 104 500 104,000 312,500
Temperature Cycling
This test subjects the devices to temperature ex-
tremes of -65�C to + 150�C. this test Is performed
to stress the package to detect poor bond wire attachment and to determine if there is a potential problem due to thermal mismatch between the die and the package material that could cause device failures. The results of these tests are tabulated in Table11
Lot#
1 2 3 4 5 6 Totals
250 Cycles
in Fail 52 0 52 0 52 0 52 0 52 0 24 0 284 0
500 Cycles
In Fail 52 0 52 0 52 0 52 0 52 0 24 0 284 0
1000 _Qy_cles
In Fail 52 0 52 0 52 0 52 0 52 0 24 0 284 0
Device Hours
52,000 52,000 52,000 52,000 52,000 24,00 284,000
Table 11. Temperature Cycling -65�C to
+ 150�C
Table 10. 85/85 (power on)
CONCLUSION
The X24C01 has been demonstrated to be a highly reliable semiconductor memory. The semiconductor FIT rate is well below the industry average for a comparable device. Xicor specifies the X24C01 as having an endurance of 100.000 cycles
and data retention of 100 + years. The additional
environmental data indicates that the combination of process technology and assembly techniques provides a highly reliable device under all environmental conditions.
0122-7
9-129
NOTES
9-130
I I I I
liClll!
1j j j
DETERMINING SYSTEM RELIABILITY FROM E2PROM ENDURANCE DATA
By Richard Palm
Xicor has published numerous reliability reports regarding data retention and endurance; however, the relationship of this data to system reliability warrants further analysis and discussion. This paper will discuss two methods for determining the affect of endurance on system reliability. The first method will use actual data collected on the X2816A and the second method will use data collected on the X2864A.
Definition of Terms
Endurance - is the ability of a nonvolatile memory to sustain repeated data changes.
Endurance Failure (Level) - is the limit of endurance, expressed in number of write cycles, when the first bit of any memory device or memory system is found to be in error after a required data change.
� Data retention refers to the capability of a nonvolatile memory device to retain valid data under worst case conditions.
� Endurance is the ability of a nonvolatile memory device to sustain repeated data changes.
Xicor reliability reports, RR502A and RR504, detail these three categories for Xicor devices. Reliability is easily deduced for semiconductor failures and data retention. The affect of endurance on reliability is not so straightforward.
Because endurance screening is a destructive procedure, Xicor performs endurance life tests on a sample basis. The data collected from these tests are then plotted onto an extreme value distribution graph to determine the endurance distribution for a particular lot of devices.
Write Cycle - to reduce testing time Xicor uses a test method whereby the entire array of the device under test is written in a single write cycle. Therefore, all references to "write cycle" equate to every bit in the entire array (device or system array) being written.
Using the Extreme Value Distribution Data
Cumulative Failure (Probability) - the percentage of parts not expected to attain a particular goal; i.e., endurance level.
Note: all endurance data used in this report were collected at a cycling frequency of one cycle per
1OOms and at + 25�C.
Background
There are three reliability categories for nonvolatile memories: semiconductor, data retention and endurance.
� Semiconductor reliability pertains to several failure modes common to all semiconductor devices such as oxide rupture and micro-cracks.
Figure 1 is an extreme value distribution graph for twenty X2816A devices and Table 2 (located on the last page) is the raw data used to generate the straight line shown.
� In this sample lot the lowest ranked device (# 1) exceeded 279,000 write cycles before the first bit failure occurred; however, the graph extends to the left to show that only ~ .01 % of all devices from this manufacturing lot will fail before 200,000 cycles.
� The maximum of the extreme value distribution occurs at the 37% cumulative probability point (statistically, 37% of all devices will fail to reach this endurance level), indicating that the predicted most probable endurance of devices in this lot is 460,000 cycles.
0018-1
9-131
2M
IM BOOK &OOK
400K
~ 300K
200K
,,_.
~
~
Vl
""""'
100K BOK
60K
40K 30K
20K !OK
w
Q 0
::t
:czw:t
0001 001 .01 .05 .1 .20 .37 .57 .70 .80 .90
.97
99
PROBABILITY OF FAILURE
Figure 1: Extreme Value Distribution Graph for One Twenty Piece Lot of X2816As
Reliability data are generally stated in terms of percent failures per 1000 hrs. This can be easily derived from the extreme value graph in a two step procedure.
The system design parameters for this example are chosen as follows: the lifetime of the system is five years; and each X2816A will experience 250,000 write cycles over the lifetime of the system.
� The first� step determines the failure rate per 1000 write cycles using the formula W = C/E where:
W = failure rate in %/1000 write cycles
E = endurance level chosen for the system (250,000 write cycles) divided by 1000.
C == cumulative failure rate at E (in this case .5%).
Therefore W = .5%/250 = .002%/1000 write
cycles.
� Converting this to percent failures per 1000 hours
requires t1. = � W x A where:
H = failure rate in %/1000 hrs.
W = failure rate in %/1000 write cycles A = number of write cycles per hour. (i.e., 2.5 x 105
cycles/5 years)
In our case, H = .002 x 5.7 = .0114%/1000hrs. In the above example the entire X2816A is being rewritten at the rate of 5.7 times every hour. In some applications this could occur, but generally the frequency is much lower. Using the same graph and arbitrarily choosing the lowest cumulative failure rate depicted at 200,000 write cycles and performing the same calculations, the percent failures per 1000 hrs. drops dramatically.
W = .01/200 = .00005%/1000 write cycles
H = .00005 x 4.56 == .00022%/1000 hrs.
Predicting System Endurance Reliability Within Design Constraints
This next example is based on data collected on the X2864A. The system requirements for which the data were collected are defined as follows: the life expectancy of the system is ten years; the number of write cycles is 10,000. Therefore, Xicor cycled five lots of. approximately three 'hundred devices each, for 10,000 write cycles. The data were collected by cycling the devices every 100ms at -25�C. Table 1 summarizes the data collected.
LOT#
1 2 3 4 5
TOTAL
#OFUNITS
297 295 295 298 299
1484
#OFFAILURES
4 2 4 6 6
22
%FAILURES
1.35 0.68 1.36 2.01 2.01
1.48
Table 1: Raw Data From Cycling X2864A Devices 10,000 Times
The overall failure rate of devices unable to reach 10,000 write cycles is .1 .48%. How does this relate to system reliability?
� The system is defined as having a life expectancy of ten years or 87.6 x 103 hours.
� The failure rate in percent per 1000 hours is determined by dividing the percent of parts unable to reach 10,000 write cycles by system's life expectancy in thousands of hours.
Therefore, reliability based on endurance for this system is:
1.5%/87.6 = 0.017%/1000 hrs.
0018-2
9-132
Temperature
RR504 describes in detail the affect of temperature on endurance. In general, this report shows that for every 50�C rise in temperature the endurance rate doubles. The data collected for the above examples was taken at + 25�C. Therefore, for systems operating at a more common + 40�C the endurance will improve. Figure 2 illustrates the case for the X2816A.
� The line labeled + 25�C is the same as that in Figure 1.
� The added line is for the predicted increase in
endurance at + 40�C.
� The cumulative failure rate at 250,000 write cycles moves from .5% to less than .01 % and the endurance reliability increases as follows: W = .01%/250 = .00004%/1000 write cycles H = .00004% x 5.7 = .0002%/1000 hrs.
The failure rate for the X2864A sample lots can be expected to decrease by a factor of ~ 1.30, for the
increase in operating temperature from + 25�C to
+40�C; yielding a failure rate of .013%/1000 hrs. vs. the unfactored .017%/1000 hrs.
Frequency of Writing
Xicor reliability report RR504 describes device operation and the affects of frequency of writing to a device. Figure 3 is a copy of a graph in RR504, depicting the relationship of write cycle frequency on the endurance of a Xicor nonvolatile memory.
There are two key relationships illustrated by the graph in Figure 3.
� As the frequency of writing decreases the slope of the plotted line, the extreme value, decreases.
� Although the most probable endurance (the 37% cumulative failure point) does not show appreciable change, the decreasing slope is significant in the region most concerned with predicting reliability, the .01 % to 5% region (shaded area of Figure 3).
It is in this region that a system's reliability is determined. Arbitrarily choosing the .1% probability of failure point, Figure 3 shows:
� A write cycle frequency of 1 per 100 seconds increases the endurance level by a factor of 2 over a write cycle frequency of 1 per 100 milliseconds.
0018-5
1~g~ ~=t:=i=t=i==t==i==t=!:==f===f==~
60KL.....J..-1--l--l--+--1--+-+~I---+~~-+~~~
40KL.....J..-1--l---+--+--t--+-+~1---+~~-+~~~ 30KL.....J..-1--+--+--+--t--+--+~1---+~~-+~~~
w z 20Kl-l--l--l--l--+--1--+--+~1---+~~-+~~~
8 ~
10KL.....J..-1..--L...J..._...i_;~=-~~~__._.......L..~-'-~~-'-~---'
.0001 .001 .01 .05 .1 .20 .37 .57 .70 .80 .90
.97
.99
PROBABILITY OF FAILURE
Figure 2: Affect of Ambient Temperature on Endurance
� .
~-- --
/
.z-
""7
z 7
0.1 SECOND/
./"
~ KECONDS
w z
0 0
~
~
~
.0001 .001 .01 .05 .1 .20 .37 .57 .70 .80 .90
PROBABILITY OF FAILURE
.97
.99
Figure 3: Affect of Write Cycle Frequency on Endurance
0018-3
9-133
Conclusion
This paper has illustrated two methods for determining system reliability based on endurance. In the examples given, the failure rates due to endurance are well below industry standards for semiconductor failures.
Additionally, by factoring in the affects of both temperature and frequency of writing, the end1,nance failure rates for the X2816A system and X2864A system may be predicted specifically for the user's application.
DEVICE RANK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
THOUSANDS OF WRITE CYCLES
297 315 355 365 400 410 450 450 510 572 620 620 650 680 800 820 940 952 992 1400
Table 2: Ranked Endurance Data for Twenty Pieces of X2816A Devices
0018-4
9-134
liCI'
RADIATION-INDUCED SOFT ERRORS AND
FLOATING GATE
MEMORIES
J. M. Caywood & Reliability Engineering Staff
ABSTRACT
A new failure mechanism which may be induced in floating gate memories by ionizing radiation is discussed. This mechanism, which is designated a "firm error", is modeled in some detail. Calculations which show that the MTBF for alpha particles emit-
ted by ceramic packaging materials is > 100,000
years are verified experimentally. The effect of device scaling on this mechanism is also discussed.
INTRODUCTION
Ionizing radiation incident on floating gate nonvolatile memories can give rise to three types of observable effects. The radiation may induce damage in the peripheral circuitry (hard errors); it may cause upset of the sense/readout circuitry (soft errors); or it may cause data loss by transfer of charge from the floating gate. The first of these groups of effects is common to all MOS circuitry and has been investigated extensively over many years. 1 The second group of effects was first observed in dynamic RAMs and has since also been observed in static RAMs and microprocessors.2-5
The third effect, on �which this paper will concentrate, is qualitatively different than the "soft errors" which are observed in volatile RAMs. In the soft error case, thermalized carriers are collected from relatively long (-10�m) distances in the Si substrate which can result in efficient collection of the charges generated by an alpha particle (-50%)4 � In the case to be discussed here, the carriers collected on the floating gate may come from two sources. One source is carriers created by the ionizing radiation in the Si02 which lies between the floating gate and another electrode or the substrate when they are at a different potential. The second source is electrons excited in the floating gate which have enough kinetic energy to surmount the potential barrier between the conduction bands in Si and Si02 � As will be developed in this paper, these effects are relatively inefficient (<1%). Unlike soft errors which are caused by a single ionizing particle, charge transfer to a floating gate is cumulative so that effects of many ionizing events occurring over an extended period of time must be considered.
To differentiate this phenomenon from soft errors which, if they occur in floating gate memories, are dependent upon the design of the readout circuitry and are temporary read errors which can be corrected by re-reading the floating gate, and from hard errors which render all or part of the memory inoperable, we shall call it "firm error". This firm error has the operational characteristics that it causes a read error which cannot be corrected by re-reading the floating gate, but it can be corrected by re-writing the cell or cells in question to provide a completely functional memory.
MODELING THE CHARGE TRANSFER
Figure 1a shows a typical cross-section through a floating gate memory structure where the + and signs indicate that electron-hole pairs are created along the track. Figure 1b shows a potential diagram of the same structure. Clearly electron-hole pairs created in the oxides on both sides of the floating gates will drift apart and tend to discharge the gate. Similarly electrons injected from the floating gate into either oxide will discharge the gate. The problem can therefore be broken into that of computing the charge created in the oxide and that of estimating the charge injected from the Si into the oxide.
1a.
a
2a.
Si
I I
I I
tox1DE2:
I
I
FLOATING
GATE
0019-7
Figure 1: Cross section and potential diagram of a typical floating gate memory transistor; a) the cross section is cut through in the direction of current flow; b) the potential diagram is shown for the case that the floating gate is programmed and the access gate grounded.
0019-1
9-135
INJECTION OF CHARGE
FROM Si INTO Si02
Emission of excited electrons from Si into Si02 is a complex process. Some of the phenomena occurring are illustrated schematically in Figure 2. Hot electrons created by the ionizing particle may be scattered by acoustic or optical phonons, other electrons, or the surface itself. The requirement for electrons to reach the surface with sufficient crystal momentum, K, normal to the surface to surmount the barrier (Kf /2m*><l>B where K1- is the component of
K normal to the surface, m* is the effective mass,
and <l>B is the barrier height between the conduction bands in Si and Si02).6 Phonon scattering may be
considered to be elastic since the phonon energies
are small with respect to the barrier height. However,
an electron scattering off another electron may .lose
up to one-half of its kinetic energy. Hence, electron-
electron scattering rapidly thermalizes hot elec-
trons. 7 The escape length of electrons is long for
energies near the fermi level but drops rapidly and
forms a broad U between 20 A and 5 A� over the
o moo energy range 1 eV to
eV.8 Escape depths of
25 A and 12 A are reported for electrons 5.8 eV and
11 eV above the valence band maximum,
respectively.
9
10
�
photons incident on clean Si.11 By integrating the
EDCs and dividing by the incident photon energy,
the yields in terms of electrons emitted per electron
volt of incident photon energy are found to be 6. 7 x 10-4, 8.9 x 10-4 , and 8.7 x 10�4 for photons with
energies of 8.6 eV, 10.2 eV, and 11.8 eV, respec-
tively. For lower energy photons, the yields drop
precipitously. 6 It length, 1/a, in
is Si
known is 80
that the optical
A for 12 eV
apbhsootorpntsi.o1n2
Moreover, the electron escape depth at 11 eV is 12
A. 10 This implies that one factor limiting the yield is
that most of the electrons generated within the bulk
of the Si relax via electron-electron an estimate that a charged particle
syciealdttser1in0g-3.
Thus elec-
trons for every electron-v9lt of energy lost within 80
A of the surface is probably an upper bound for
emission from silicon into a vacuum.
10.2eV hv=11.8eV
\
) L~ECTR~OBNARRSCIAE~RRl4G S102
Figure 2: Schematic illustration of scattering process which contributes to small escape depth of electrons from Si.
The ideal situation would be to have electron yield curves as a function of energy for various charged particles of interest incident upon a biased oxidized silicon surface. Unfortunately, we lack such a complete data base, so we shall estimate the yields from data on optically stimulated emission. Figure 3 shows energy distribution curves (EDCs) for three photon energies plotted versus the energy of the states from which the electrons are excited for
Figure 3: These energy distribution curves give electron yield vs. the energy of the initial state for photons incident on clean Si. (Data from Spicer, ref. 11 ).
Because the barrier between the conduction band in Si and the conduction band of Si02 is -0.9 eV lower� than that between the conduction band of silicon and the vacuum level, the yield in the Si/Si02 system should be higher than that estimated above.6�13 The magnitude of the yield increase can be estimated two ways. Callcott measured the effect of applying 0.16 monolayer of Cs to a Si surface. He found that the vacuum barrier was lowered by 1 eV and the photon yield was increased by 2.6 times. 14 Another estimate comes from the observation that for 6 eV photons, Powell reports -13 times higher quantum yield for the Si/Si02 system than does Broudy for the Si/vacuum system.6 �13 Since Powell applied a field of 3 x 106V/cm (-5x that present in a typical floating gate memory), the barrier between Si and Si02 was lowered by 0.45 eV. This implies that
0019-2
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the ratio of the Powell and Broudy results is clearly an overestimate of the yield enhancement. Based on these data, we shall use 1Ox as a generous estimate of the magnitude of the yield increase between the Si/Si02 system and the Si/vacuum system. Our estimate of the yield of electrons emitted over the Si/Si02 barrier as a result of an incident ionizing particle is 10-2 electrons for each eV of energy lost within 80 A of the Si/Si02 interface.
COLLECTION OF CHARGE GENERATED IN THE Si02
The experimental evidence for collection of charge generated within Si02 is much more direct than for charge injected from the Si/Si02 interface. Measurements of Srour, Curtis, and Chiu show that the collection efficiency of electron-hole pairs generated by 4-5 keV electrons in Si02 varies from very low at low fields to -20% at 5 x 105 V/cm to -100% at 5 x 106 V/cm. 15 From calculations based on these measurements, Ausman and Mclean have deduced that one electron pair is created for each 18 eV lost in the Si02 .16 Since typical fields occurring in floating gate memory devices during read or storage operations are 5 x 105 V/cm, we shall assume that one pair is created for each 18 eV of energy lost in the oxide and that 20% of the charges created are collected at the electrodes.
ENERGY DEPOSITED FROM IONIZING RADIATION
Ionizing radiation can be generally separated into that involving massless particles (X-ray, Gammarays, etc.) and those which have mass (mesons, electrons, protons, atomic ions, etc.). The absorption cross-sections of the massless particles are quite small and decrease with increasing energy. For example, the Ka line of Mo occurring at 20.03 keV has a mass absorption coefficientof-4cm2/g. 17 This means that approximately 1mm of Si is required to absorb 63% of the energy of a Mo X-ray beam. Since the cross-section is proportional to the cube of the wavelength, high energy photons lose even less energy per unit of length traveled through a solid. Because of this, it is expected that large fluences of X-rays would be required to transfer significant charge from the gate of floating gate memory.
For particles with mass, the stopping crosssection varies in a systematic way. This is illustrated
in Figure 4 where we have plotted calculated energy loss rates in silicon for particles of differing mass using the Bethe-Bloch formalism. 18 As can be seen, for each mass particle, there is a peak in the curve of stopping power vs. energy which shifts to higher energy and becomes larger as the particle mass increases. Because of the log-log nature of the plot shown in Figure 4, it implies that there will be a high density of carriers created at the end of the particle track. This feature is called the Bragg peak.
Since the charge generation rate is maximum for particles with energies in the neighborhood of the Bragg peak, it is illuminating to calculate the charge transferred from a fairly conventional floating gate for two of the particles shown in Figure 4.
Alpha particles are known to be the chief cause of soft errors in volatile memories so their effect will be calculated. The other particle we will consider is an A1 ion, both for itself, since it may be generated as a result of muon capture by Si, and as a proxy for both the Si recoil ions which may be generated in various nuclear reactions and Mg which may also result from muon capture. 19�20
103 o~
>
~
Fe
102 wcc: 3:
Al 101 Qa..
cz.::J
c
10�
aZS..:
Q
I-
Cl)
10 102 103 104 ENERGY (MeV)
Figure 4: Energy loss rates vs. particle energy for particles with various masses calculated from Bethe�Bloch theory.
The Bragg peak for a's in Si occurs for particle energies in the neighborhood of 0.5 MeV. The energy loss rate for a's in Si is -28 eV/A in this range.21 The energy loss rate for a compound such
0019-3
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as Si02 can be found from Bragg's rule which postulates the linear additivity of the energy loss crosssections of the constituents of the compound, viz.
E(Xm Y n) = m E(x) + nE(y)
1.0 cx/cm2 � hr., the integral over the approximation will be taken to be 1 a/cm2 � hr.
Applying this to Si02 we find that the energy loss
risat~e1f0o.r 6aelpVh/aA.p2a2 rSticimleislairncaSlic0u2lantieoanrsthfoer
Bragg peak Al ions give
approximate loss rates of 300 eV/A and 110 eV/A
for Si and Si02, respectively. Putting all of this together in the context of Figure
1, we can see that the total charge collected per
incident particle should be given by:
a = No/t) I dox1 ( dE)
dp
P 18
case dx Si02
+ y
Si-Si02
Aesc J[ ( dE )
case dx Si
d
P
+
( ddXE
) Si
]
d
P
+ lJox(e) f dox2 ( dE )
d
18
case dx Si02 P
where llox is the field dependent collection efficiency for pairs generated in the oxide, d0 x1 and d0 x2 are the thicknesses of the first and second oxides, Aesc is the effect escape depth for electrons generated in the Si, 0 is the angle of the particle path to the normal,
Ysi-sio2 is the yield (for normal incidence), and the integrals over path are needed because dE/dx is a function of energy and hence position.
SAMPLE CALCULATION
As one example, let's calculate the probability of a floating gate device similar to those in current production being upset by alpha particles emanating from the packaging material. We will assume that the floating gate poly measures 5� x 14� x 0.4�, that the transistor gate size is 5� x 5�, that the gate oxide and interpoly oxides are both 1000 A thick and that the field oxide is 1�m thick. We also assume that there is 2� of Si02 deposited after the access gate is defined.
Figure 5 shows the al~ha particle spectrum measured by Meieran et al. 3 The alpha spectrum is a result of the decay change of thorium and uranium which are present in the alumina which is used for hermetic packaging as trace impurities. For simplicity of calculation, we shall approximate this spectrum as two superimposed step functions. The high energy step begins at 8.6 MeV and the lower energy step at 7 MeV, the high and low energy steps have the relative weights of 3 to 7. Since it is known that the total emission rate of alumina ranges from 0.1 to
U :cc.a.:..c.)..
LI0
=aw:
::z::&:::.
0 2
Mev~
Figure 5: Spectrum of alpha particle emission rate vs. particle energy from an alumina lid. (Data from Meieran et al, ref. 23).
The maximum charge transfer which can occur as
a result of a single particle is caused by a particle
coming in at such an angle that the complete path
length is within the gate oxide. (This requires that
0>88.85�. However, e<89.43� because for larger
angles, the path length of the overglass is so long
that no particles get through. Moreover, at e=89�,
the particle energy must be greater than 6.8 MeV to
penetrate the glass.) If such a particle were to hit a
cell so that 5� of path length lay within the cell it
could lose ~1.4 MeV. This implies a transfer of
15,550 electrons. The gate which is under consider-
ation requires ~450,000 electrons to charge the
state (assuming internal 2 V margin) or about 30 of
these pathological alphas. Because the number of
pathological alphas needed is > 1, we can turn to a
calculation of the average energy loss/particle.
We make the simplifying assumptions that the
fraction of particles lost in the overglass from each of
the two step functions contributing to the energy
spectrum is given by the ratio of the path length in
the overglass to the range of the highest energy
particle in the step function, and that the energy loss
rate in the effective charge collection region is that
for 1 MeV. The first assumption causes an underes-
timation in the particles stopped in the overglass,
and the second overestimates the energy contrib-
uted to charge generation. Under these assump-
tions the charge transferred from the floating gate by
N0 alpha particles is given by: emax
01 = 2No L ri Lt ( _Q� )j Ci I sine [1- 13/cose] de
i j ' dx
o cose
0019-4
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where ri are the relative contribution of the two com-
ponents in the spectrum; ij is the effective path
length for charge generation; Ci is the conversion factor from energy loss to collected charges; l3i is the fraction lost in the overglass; and 0max is taken to be the angle whose tangent is the gate length divided by the sum of the gate electrode and gate oxide thicknesses.
F~om this, one can find that the average alpha particle causes 580 electrons to be transferred from the ~loating gat~. This means that about 750 alpha particles must hit the gate to change its state. . The problem becomes that of finding the probability that at least one cell has been hit 750 times, given that the average cell has been hit n times. For!unately, the numbers are large enough that we can mvok~ t~e l~w of large numbers and approximate the d1stnbut1on as normal with variance \In. If the array contains m cells then the probability that at least one cell is hit ncrit times is given by:
0
=
~ m
(x:i e
z
-t2/2dt
<
_!!!_ ~
z
1T
e-z212
when z = (ncrit - n) I ~
as long as 0<1.24 If n = 500, then 0 < 1.84 x 10-13 for a 16K chip
and 0<5.1 x 10-12 for a 64K chip. For the chip size and alpha flux assumed, the expected period for the average alpha count per cell to reach 500 is 7 x 108 hours. Given the approximations we have made, this probably understates the actual time by about an order of magnitude.
Turning briefly to carriers created by Al ions, we note that very few ions have energies in excess of 3 MeV. 19 Since this energy is below the Bragg peak for Al in Si, the ions stop fairly quickly. Nonetheless, the maximum energy loss rate is -120 eV/A in Si02. Since the maximum energy of the Al ions is -3 MeV, the maximum charge which would be collected from this ion is about 30,000 electrons which is still small enough that we can use normal statistics. Because of the small cross section for creation of these energetic ions, we can neglect this mode of charge generation for devices operating in normal terrestrial environments.
SCALING
The effect of scaling on the firm error rate on floating gate devices is interesting because it is very different from that which occurs in volatile memories. If we assume that both lateral and vertical dimensions are scaled by a factor X, then the storage capaci-
tance decreases as x. However, since the charge
collection is dominated by generation in the oxide, it decreases like A3 . If the voltage margin decreases
like A, the expected time for upset increases as x, if
the voltage margin is held constant, the expected
time for upset increases like x2� Thus, scaling should
decrease the firm error rate.
EXPERIMENTAL RESULTS
To verify the theoretical results presented here,
floating gate nonvolatile memories have been
exposed to two types of radiation: gamma rays, rep-
resenting massless particles, and alpha particles,
representing massed particles. Table I gives the
results. The devices tested contained a checker-
board pattern to look for firm error sensitivity for ei-
ther bias of the floating gate.
As can be seen, no firm errors could be observed.
The gamma radiation caused the devices to fail to �
meet the output leakage specification after 12,000
RAD. Measurement of the threshold of the output
transistors showed that the thresholds had dropped
from -o. 7V to -ov.
The alpha particle fluence to which these devices
were exposed was approximately that which would
be seen after 200,000 years o:/cm2� hr) or 2,000,000 years
in in
a dirty a clean
(p0a.1ckoa:g/cem2(1�
hr). These results are in good agreement with the
predictions.
Radiation Type
Gamma Radiation
Alpha Radiation
Energy/ quantum
58.6 keV
5.3 MeV
TABLE I
Integrated Surface Flux
12,000 RAD 2.6 x 109 o:/cm2
#Units Tested
10
5
#Firm Errors
0
0
Part Type X2212 X2816
0019-5
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SUMMARY
The question of "firm" errors in floating gate nonvolatile memories has been treated. A firm error is defined as a change of data occurring as the result of transfer of charge from the floating gate by ionizing radiation. The rate of charge transport by various forms of ionizing radiation is discussed. The case of alpha particles is worked out in some detail as an example. Experimental results of exposure of units to gamma and alpha radiation are shown which support the theoretical predictions. The units in test survived exposure to 12,000 RADs and 2.6 x 109 cx/cm2 without firm errors. The alpha fluence is equivalent to that emitted by a typical ceramic package in about a million years.
REFERENCES
1. e.g., Roger Freeman and Andrews HolmesSiedle, IEEE Trans. Nucl. Sci. NS 25, 1216 (1978); J.M. Aitken, J. Electronic Mat. 9, 639 (1980).
2. T.C. May and M.H. Woqds, Proc. 16th Annual International Reliability Physics Symp., 33 (1978).
3. D.S. Yaney, J.T. Nelson, & L.L. Vanskike, IEEE Trans. ED26, 10 (1979).
4. C.M. Hsieh, P.C. Murley & R.R. O'Brien, Proc. 19th Annual Reliability Physics Symp., 38 (1981 ).
5. R.P. Capece, Electronics 52, Mar. 15, p.85 (1979).
6. R.M. Broudy, Phys. Rev. 81, 3430 (1970).
7. For more sophisticated treatments of electron emission from solids cf. Leon Sutton, Phys. Rev. Lett. 24, 386 (1970); C.N. Bergland and W.E. Spicer, Phys. Rev. 136, A1030 (1964); Sven Tougaard and Peter Sigmund, Phys. Rev. B 25, 4452 (1982).
8. Lindau and W.E. Spicer, J. Electron Spectroscopy and Related Phenomena 3, 409 (1974).
9. G.W. Gobeli and F.G. Allen, Phys. Rev. 127, 141 (1962).
10. W.E. Spicer, J. Physique 34, C6 (1973).
11. W.E. Spicer, in "Optical Properties of Solids -New Developments", ed. 8.0. Seraphin, p.658, North-Holland: Amsterdam (1976).
12. H.R. Phillips and H. Ehrenreich, Phys. Rev. 129, 1550 (1963).
13. R.J. Powell, J. Appl. Phys. 40, 5093 (1969).
14. TA Callcott, Phys. Rev. 161, 746 (1968).
15. J.R. Srour, O.L. Curtis, Jr., and K.Y. Chiu, IEEE Trans. on Nuclear Science NS-21, 73 (1974).
16. G.A. Ausman, Jr. and F.B. Mclean, Appl. Phys. Lett. 26, 173 (1975).
17. Robert B. Leighton, "Principles of Modern Physics", pp. 421-425, McGraw-Hill, New York (1959).
18. Hans A. Bethe and Julius Ashkin, in "Experimental Nuclear Physics", ed. E. Segre, John Wiley, New York (1953).
19. J.F. Ziegler and L.A. Langford, Science 206, 776 (1979).
20. E.L. Petersen, IEEE Trans. on Nuclear Science NS 27, 1494 (1980).
21. W.K. Chu and D. Powers, Phys. Rev. 187, 479 (1969).
22. J.E.E. Baglin & J.F. Ziegler, J. Appl. Phys. 45, 1413 (1974).
23. E.S. Meieran, P.C. Engel, & T.C. May, Proc. 17th Annual Relfability Physics Symp., p.13 (1979).
24. Marvin Zelen and Norman C. Severo, in Handbook of Mathematical Function, eds. Milton Abramowitz and Irene A. Stegun, p.926, National Bureau of Standards (1964).
0019-6
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ENDURANCE MODEL FOR TEXTURED POLY FLOATING GATE MEMORIES
H.A. Richard Wegener
ABSTRACT
Textured Poly Floating Gate (TPFG) memories are beginning to dominate the commercial market. This is due to many of its inherent strengths. One of these is the consistency of its endurance. Its predictability is here developed theoretically. Starting with a model of emission from bumps based on the radial solutions of LaPlace's and Poisson's equation in spherical coordinates and the use of an Extreme Value distribution for the bump radii, an expression for charge build-up at constant current fits experimental data very well. This charge build-up is proportional to fluence. When these results are used in a model for continuous data changes, an expression is developed that relates endurance exponentially to a ratio of internal voltages.
INTRODUCTION
The basic features of the TPFG technology have been described in previous publications (1-4). The action of three polysilicon levels in charging and discharging the floating gate is shown in Figure 1.
Charging
The Floating Gate
Programming
Discharging The Floating Gate
Figure 1: TPFG Cell Operation
Electron emission occurs only from a lower poly layer towards an upper poly layer. The oxide layers in between are in the 55 to 75 nm range, compared
to the 8 to 11 nm required for the other common floating gate technology. The reason is simple: the surfaces of the poly layers are textured to form many small bump-like features, whose curved surfaces enhance applied fields by factors of 4 to 5. The modeling of these fields is an important part of the analysis to follow.
ENDURANCE
The term endurance has become accepted for a property common to all current nonvolatile memory technologies. It describes the number of data changes that a memory device can sustain without failure. In MNOS technologies, the failure is sometimes an inability to maintain the memory state for the required retention time; in thin oxide floating gate technologies it is often the breakdown of the fragile dielectric. In the TPFG technology, the end of endurance is generally caused by "trap-up", which prevents the transfer of charge to the floating gate. Trap-up is caused by the accumulation of trapped negative charge in the dielectric due to the repeated passage of current. These charges create a potential that opposes the potential necessary for tunneling. When this opposing potential reaches the voltage supplied on the chip, tunneling can no longer occur, resulting in the end of endurance. This paper describes a model for trapped charge build-up in TPFG devices.
FIELD MODEL
Electron emission by Fowler-Nordheim tunneling requires the knowledge of the field at the surface of the bump. This model assumes a bump with a spherical tip, which permits the use of solutions of LaPlace's and Poisson's equations in spherical coordinates. It is further assumed that the emitting surface (cathode) is radially conformal with the collecting electrode (anode), so that only the radial parts of both equations need to be employed. This leads to a solution of the form
(1) Ee= -Vc/[Rc(1-Rc/Ra)J + (cr/K) Act (1-Rct!Ra)/[Rc (1-Rc!Ra)J
where E is the field, R the radius, K the dielectric permittivity, cr a charge density per unit area, subscript c denotes a quantity at the cathode, and subscript a is a quantity at the anode. The first term describes the field in a dielectric free of charge, and the second has been cast in a form that the trapped charge distribution can be described by its charge density cr located at the centroid radius Act.
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FORMALISM FOR TRAP GENERATION
There is a body of experimental data for parallel plate structures (5,6) that clearly indicates that the amount of trapped charge is proportional to the amount of charge that has passed through as current:
(2) a, = b {J J dt} (4 71' R2c) (s/4)
where a, is the charge trapped, and I J dt is the
current density that passed through the dielectric integrated over time (termed "fluence"). The quantity b is the ratio of trapped charge to fluence. The second bracket converts charge density into charge, and (s/4) is the fraction of a full sphere that actually emits electrons. When this charge is concentrated at the centroid raduis Rd, then
(3) ad = (a) (4 71' R2d) (s/4)
Equating a, with ad. solving for a, substituting into eq (1 ), identifying the denominator of the secono term.of eq (1) as Va. and approximating Rd with Ra/2 results in
(4) Va = {J J dt} (b/K) (R2c1Ra)
FORMALISM FOR VARIATION OF BUMP SHAPES
All of the preceding derivations require two perfect concentric spherical shells to be applicable. To account for deviations from sphericity, and the distribution in the sizes of real bumps, as many as four constants might be necessary. But as a first approach it was decided to view the bumps as a distribution of perfectly spherical surfaces of limited area, with the hope that the dispersion parameter of the distribution of spherical radii would absorb the effects of contour variations. The distribution chosen was the Extreme Value distribution (7-9). Its sampling function has the form (10)
(5) Rei = Rm - BB{log [-log (i- 0.5) /k]}
where Rm is the radius at the maximum of the distribution (tlie mode), BB is the dispersion parameter, k is the number of samples chosen, and i is the rank number� of the particular item of k samples chosen.
CONSTANT CURRENT CHARACTERISTICS OF "TPFG" MEMORY TEST STRUCTURES
TPFG memory devices are operated by linear voltage ramps, which result in a forced constant current through the dielectric. A useful concept in this mode of operation is the "tunnel voltage" Vrn. which is the voltage that must be applied to sustain a specific constant current. For purposes of characterization, simple test structures are subjected to a set of forced constant currents, and the tunnel voltage Vrn is recorded vs fluence. Such a characteristic is shown in Figure 2.
18t----+--+--+--+------t---+----,-----+-::------j
~1=10�5 amps
16t----+--+--+--+------t--7-=--.l-:-:c-::--r_-----7"!
1=10-6 ampY'
7 y Voltage VTu 14 1----+--+---+--+-_.,..--+::::oo~+-J...-'l-I_.,.=1q.o--1a_m__,ps
to Maintain
,
r::::::::7'
Constant 12 1------+---+--+------..,.-1-------co_..,.=-./____,~1-=~10--1-e-am-ps~
Current I
..+--- ...J...--'
10~-+---+_--_~.-,"."-""--:-:I=:1-0�-9 +am--ps--+---+---1
3x10�8 10-7 3x10�7 10�6 3x10�6 10-5 3x10�5
Fluence (fldt) in Coulombs
Figure 2: Tunnel Voltage vs. Fluence at Constant Current. Lines are experimental data, solid circles are calculated from eq (8).
With representative bump radii chosen by the sampling function the field at bump i is
(6) Eci = [-VTUi + VaiJI[ Rei (1-Rc/Rai)], where
(7) Vai = {I JFNi .it} (b/K) (R2c/Rai)�
Fluence is now expressed by its sum over time increments. The measured current is the sum of the currents from the number of all individual bumps G. The current density emitted by tunneling must be multiplied by the active spherical surface area. This leads to
k (8) I= (G/k) I (4 71'R2ci) (s/4) JFNio where
i=1
(9) JFNi = A E2ci exp �B/Eci�
0020-2
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The initial modeling was done with a program in BASIC on a personal computer. The area of the structure was 0.1 mm2 , the number of bumps per square micrometer was 50, the oxide thickness was
59 nm, which translated into a value for Rai=Rci +
59 nm. Following (11) the Fowler-Nordheim constants were set at A=6.5E-7 amps - cm/V2 - sec and
B=2.52E + 8V/cm. The dielectric permittivity was
K=3.5E-13. The best fit was obtained for Rm=15.4 nm, 88=4.8 nm, b-2.0E-8, and s=0.03. The calculated values are shown as circles against the continuous experimental data on Figure 2. The value Rm is consistent with values obtained from T.E.M. crosssections, the calculated dispersion has an analog in the estimated dispersion of bump base diameters, and b agrees very well with data presented at IEDM81 (6) for parallel plate structures. There is now a good basis for describing the processes occurring in TPFG memories. A pertinent example is shown in Figure 3. Here a constant current plot was calculated as a function of the number of samples representing the same distribution. While it is an indication that, indeed, 1024 samples are necessary to accurately depict conduction at fluences as low as 1E-8, it also clearly shows that during the latter part of the life of the devices, all those different bumps can be represented by bumps of the same radius Rm. This should make the prediction of endurance somewhat less complex.
VOLTAGE-TIME RELATIONSHIPS DURING PROGRAM-ERASE CYCLING
This analysis is based on the assertion that trapup is the cause of the end of endurance. Since the build-up of traps is the result of current through the tunnel dielectric, this analysis is concerned only with the time interval during which tunneling occurs. As an aid to understanding, reference may be made to Figure 4.
Voltage vM at
Cathode
Vru Vru0
Figure 4: Voltage vs. Time Relationships at Floating Gate
30
28
26
Calculated Voltage VTu 24
at Constant 22 Number
Current
"l_Bumps
20
1 18
16 ~16
14 ~rss
Ffo24
]
1
I v I
EZ I
....--
10 9 10 8 10 7 10-6 10-5 10-4 10-3 10-2
Fluence (Jldt) in Coulombs
Figure 3: Effect of Number of Samples k on Calculated Tunnel Voltage
The heavy line describes the (absolute) potential at the cathode (which may be poly 1 or poly 2) during the course of the first ramp to be applied to an untested structure. When the tunnel voltage VTUo is reached, a current flows that remains constant until the maximum voltage (internal to the tunnel structure) VM, is reached. The constant current is indicated by a superimposed plot in broken lines referenced to the right. When VM is reached, the voltage stays constant for a "flat top" period. During this time, the current decreases exponentially, since any transferred charge reduces the tunnel potential. Since tunnel current flows during this first pulse, its fluence gives rise to trapped charge, which in turn causes an opposing voltage V0 . Therefore, during the second pulse, the net potential on the cathode is reduced by V0 . This can be indicated by a second ramp offset downwards by V0 . The tunnel voltage for the same constant current is then reached later, and the time to reach the end of the ramp is shorter. As cycling proceeds, the time interval during which tunneling occurs becomes shorter and shorter. This simple picture neglects one important element of endurance cycling: each cycle of one polarity must be followed by a cycle of the opposite polarity. The charge stored during the previous cycle affects the
0020-3
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potential of the cathode during the following .cycle. The amount of charge stored during each cycle can be picked off Figure 4 by looking at it in another way. Instead of offsetting all succeeding ramps, one may consider them all superimposed, and recognize that the tunnel voltage VTU increases with each cycle. Then the tunnel voltage can be viewed as the sum of Vruo and V0 . Conversely, the charge transferred to the floating gate VFG is the difference between VM and VTu�
ENDURANCE MODEL
The change in Vru per programming pulse on one bump is
(10) d VTu/dn= ava = {JFN at} (b/K) (R2c1Ra)
where at is the total time during which current flows.
(11) at = (VFGe + VFTe + VMp - VTup + VFTp)/r,
where r is the ramp rate dV/dt, subscript prefers to the programming step, and e to the erase step. VFGe + VFTe is the floating gate voltage left over from the erase step. VFTp is the charge added to VFGp during flat top. From previous analysis, VFGe = VMe - Vrue + VFTe� Let the structure be symmetrical so that all subscripts are interchangeable. Eq (11) be can now be written
(12) dVTu/d n = cx(VM-Vru+ VFT) where
(13) = Q'. 2b JFN R2c/K r Ra
Integrating (12),. setting VTu = VTuo when n=O, setting VM-VTu .+ VFT = VMs when n = N, and rearranging, results in
(14) N = (1/cx) [1 n (VM+ VF1 � Vru0 )/VMsJ.
Here N is endurance expressed as the number of data changes before trap-up, and VMs is the minimum voltage on the floating gate to be sensed as the correct state.
Near the end of endurance, according to Figure 3, after a fluence of about 1E-4 coulombs has been accumulated, the build-up of traps follows a path as if all� bumps had the same radius Rm. This permits the exact substitution for Re and Ra in Eq (13), and the calculation of VTuo in Eq (14) with the help of Eq (9). VFT can be calculated exactly, depending on flat top time and floating gate capacitance; it is of the order of O.1-0.3 volts. VMdepends strictly on internal voltages and coupling ratios. VMs depends on coupling ratios, the threshold voltage of the floating gate transistor, the minimum voltage required to accomplish sensing at the circuit sensing device. Memory cells operating within real circuits require
the establishment of both programming and erase voltage quantities to fit in Eq (14). Endurance distributions as a function of temperature have been recorded. experimentally for specific TPFG products (12). Their modes are consistent with tunneling currents as determined from the measured ramp rates in circuits operating at different temperatures.
CONCLUSION
There are three major results of this calculation. First, it indicates that textured surface emission can be modeled adequately by spherical geometrics, if modified by the dispersion of an Extreme Value distribution of the bump radii. Second, it confirms that TPFG memories are a part of the same universe as other silicon-to-silicon-dioxide tunneling structures, exhibiting the same mode of trapping (proportional to fluence), with a trapping ratio (b=2E-8) that is essentially identical to that for parallel plate structures. Finally, on the basis of these results, a model for TPFG endurance based on charge buildup has been developed that appears well supported by experimental results.
ACKNOWLEDGEMENTS
The author would like to thank Daniel Guterman for many clarifying discussions and important experimental data, David Scott for his work in obtaining endurance data, and Roberto Tam for his timely help in programming.
REFERENCES
1. J. Drori, S. Jewell-Larsen, R. Klein, W. Owen, A. Simko, W. Tchon; "A Single 5-Volt Supply Nonvolatile Static RAM"; 1984 IEEE lnternatl. Solid State Circuits Conf. Technical Digest 24, pp 148-9 (1981 ).
2. S. Jewell-Larsen, I. Nojima, R. Simko; "A 5-Volt RAM-like Triple Polysilicon EEPROM"; Proc. 2nd Annual Phoenix Cont., pp 508-11 (1983). IEEE Catalog No. 83CH1864-8.
3. R.K. Ellis; "Fowler-Nordheim Emission from Non-Planar Surfaces"; IEEE Electron Device Letters, EDL-11, pp 330-2 (1982).
4. R.K. Ellis, H.A.R. Wegener, J.M. Caywood; "Electron Tunneling in Non-Planar Floating Gate Memory Structures"; IEEE IEDM82 Digest, pp 749-50 (1982).
0020-4
9-144
5. D.R. Wolters, J.F. Verwey; Springer Series in ElectroPhysics 7, p 111 (1981 ).
6. M. Liang, C. Hu; "Electron Trapping in Very Thin Thermal Silicon Dioxides"; IEEE IEDM81 Digest, pp 396-9 (1981 ).
7. B. Epstein, R. Brooks; 'The Theory of Extreme Values and its Implications in the Study of the Dielectric Strength of Paper Capacitors"; J. Appl. Phys. 19, pp 544-50 (1948).
8. P. Rosin, E. Rammler; "The Laws Governing the Fineness of Powdered Coal"; J. of the Fuel Inst. 7, p 29 (1933).
9. E.J. Gumbel; "The Statistics of Extremes"; New York, NY, Columbia University Press, (1958).
10. J.R. King; "Frugal Sampling Schemes"; Tamworth, NH, Technical and Engineering Aids for Management, (1980).
11. J. Maserjian; "Tunneling in Thin MOS Structures"; J. Vac. Sci. Technol. 11, pp 9961003 (1974).
12. H.A.R. Wegener; "Endurance of Xicor E2PROMs and NOVRAMs"; Xicor Reliability Report RR504 (1984).
0020-5
9-145
NOTES
9-146
THE PREDICTION OF TEXTURED POLY FLOATING GATE MEMORY ENDURANCE
By H.A. Richard Wegener & Daniel C. Guterman
BACKGROUND
The Textured Poly Floating Gate (TPFG) memory is one of the three major nonvolatile semiconductor memories currently in use. Details of its device theory and its use have appeared in previous publications.1-4 Its nonvolatile memory cell employs three layers of polysilicon as shown in Figure 1. The most important feature of this cell is its ability to transfer electrons to and from the floating gate through oxide thicknesses of the order of 55 nm to 75 nm, in contrast to other nonvolatile memory technologies that must have dielectrics as thin as 10 nm surrounding their floating gate. The thick dielectric in the TPFG memory cell has proven its advantage in manufacturability and reliability. This advantage is made possible by the presence of a textured surface, whose curved features generate a field enhancement that permits Fowler-Nordheim emission at reasonable voltages. These features have the shape of bumps on the poly surface. The modeling of emission from these surfaces formed the major part of a recent paper.5 Its results were that these bumps can be approximated by spherical caps on the tip of truncated cones, so that the fields can be found using Laplace's equation in spherical coordinates. From S.E.Ms and T.E.Ms these bumps were known to have a range of sizes. It was found that a simple two-parameter Extreme Value distribution of the cap radii was a sufficient description to get a good fit of model and experimental data over five orders of magnitude of constant current, and eight orders of magnitude of fluence. 5
ENDURANCE
Endurance is a characteristic common to all current nonvolatile semiconductor memory technologies. It describes the number of program-erase cycles that a memory device can sustain without
FLOATING GATE STRUCTURE
~ ERASE ~-TI~ GATE
LINE
,.
�
PROGRAMMING
~ ~ERASING
0021-1 Figure 1: The nonvolatile part of a NOVRAM* cell is shown schematically with the permanently grounded poly 1 at right, the floating gate formed by poly 2 in the middle, and poly 3, also seNing as the program/erase line, at the left. To program, poly 2 is coupled capacitively to a positive potential,� this results in strong coupling of the floating gate to poly 3, and a high potential between poly 1 and 2. To erase, poly 2 is coupled capacitively to ground; this results in a high potential between the floating gate and poly 3.
failure. In other nonvolatile technologies, the failure modes may involve dielectric breakdown or loss of retention. In TPFG memories, failure is particularly graceful: The addressed bit cannot respond sufficiently to a data change. This is due to the fact that in this technology, the end of endurance is caused by trap-up. Trap-up is the result of the accumulation of trapped negative charge in the dielectric that is caused by the repeated passage of current. The endurance limit is reached when the potential due to this trapped charge grows so large that it suppresses the Fowler-Nordheim tunneling to the extent that insufficient charge is transferred to change the state of the floating gate. The modeling of endurance then simply involves the modeling of the build-up of the negative charge as a function of the number of pulses of Fowler-Nordheim current through the dielectric.
DESCRIPTION OF ENDURANCE MODEL
A first step is the derivation of the voltage VQ, which is the voltage due to the trapped charge that opposed the voltage necessary for tunneling Vru. The spherical cap model permits the use of Poisson's equation in spherical coordinates. As shown in reference (5), Va is calculated for a charge density defined by a spherical shell with a centroid radius Rd. An educated guess approximates Rd with one half of the anode radius Ra. The
*NOVRAM is Xicor's nonvolatile static RAM device.
9-147
generation of charge density, following the results of previous workers 6, 7 is made proportional to fluence (the time integral of current density f Jdt) by the trapping ratio b. This results in
Va= [JJdt] (b/K) (R2c/Ra)
(1)
where K is the dielectric permittivity, and Re the radius of the (emitting) cathode surface.
Inspection of Figure 2 will help in understanding what happens during a single (erase) pulse. The ordinate shows the voltage on the program/erase electrode, the abscissa the time during a pulse. The voltage changes linearly with time as shown, at a ramp rate r = dVI dt. This ramp rate is proportional to the current put out by the charge pump on the chip. As the voltage between floating gate and program/erase electrode increases, a voltage Vru is reached where Fowler-Nordheim tunneling is initiat-
ed. The tunneling current is exactly r x CFG, where
CFG is the capacitance of the floating gate. Since the pump current is constant, Vru will be clamped at a value that keeps the tunnel current constant, but the voltage due to the charge transferred to the floating gate, VFG, will rise until the ramp is limited at a maximum voltage VM. At this point, the tunnel current will fall off rapidly, since any charge transferred will reduce the potential between floating gate and program/erase electrode. In the following analysis, the charge transferred after VM is reached will be set to zero. The time, At, during which constant current flows through the dielectric is defined by the tunnel voltage Vru at the beginning, and VM at the end. During this time, electrons will be trapped in the dielectric, in proportion to the fluence
J x At.
The next pulse will therefore encounter an increased opposing potential AV0 , because of the trapped charge generated during the preceding pulse. The ramp voltage at which tunneling starts is now increased by this voltage, the net charge transferred to the floating gate is decreased, and the time At during which constant current flows is also decreased. During endurance cycling, the polarities of the pulses are alternated, so that an erase is followed by a program pulse. The (program) ramp following an erase pulse now encounters a potential due to charge transferred during the preceding pulse. This potential adds to that of the new ramp, so that the tunnel voltage is reached sooner, and constant current flows longer until VM is reached. In fact, if the structure is symmetrical for both program and erase conditions, the time during which constant current flows is exactly twice that for a single ramp starting with zero charge on the floating gate.
Vru Vruo
VOLTAGE AT
CATHODE "'-------,=,..----1'---,--,---;--__J
0021-2 Figure 2: The voltage at the floating gate as a function of time is shown for one particular erase pulse. The voltage (due to displacement) changes linearly with time until the tunnel voltage Vru is reached. Tunneling at constant current clamps the voltage at that value, resulting in a voltage !!. VFG due to charge transfer. The trapped charge due to previous erase
cycles gives rise to an opposing potential Vo
MATHEMATICAL MODEL OF SINGLE CELL ENDURANCE
For the purpose of analysis, the floating gate is considered a mosaic of pieces, each containing one emitting bump of cathode radius Rei. All quantities with subscript i refer to one such representative piece. Setting the tunnel voltage at Vruo when no charge exists in the dielectric:
VM - VruOi = Vai + VFGi
(2)
Atj = VFG/r = (VM - VruOi - Vaj)/r
(3)
From Eq(1 ), the trapped charge in the dielectric after an erase and a program pulse is
AQi = 2 (b/K) (Rci2/Rai) JFNiAti
(4)
This can be expressed as the rate of charge trapping per program/erase cycle n:
dVai/dn = ai (VM - Vruoi - Vai), where
(5)
ai = 2 (b/K)(Rci2/Rai) JFN/r
(6)
Integrating Eq(5), and setting Vai equal to zero at
n = 0, results in
In [(VM - VruOi)/(VM - Vruoi - VQj)] = Uj n (7)
Substituting Eq(2) into Eq(7) and solving for VFGi
VFGi = (VM - VruOi) exp (- Ujn)
(8)
The transition from the individual bump mosaic pieces to the full floating gate comes from the argument that the floating gate voltage is really the sum of the charge contributions Qi from small amounts of current Ii emitted by all bumps, divided by the floating gate capacitance CFG:
VFG = ~Qi/CFG = [~liAtj]/CFG
(9)
(10)
9-148
the Fowler-Nordheim JFNi current is
JFNi = A Eci2 exp ( - B/Ecj),
(11)
the field at the emitting bump is
Eci = (-VTUi + VQi)IRci[1 - (Rc/Rai)]
(12)
the cathode radius
Rei = RM - BB [In - In (i - 0.5)/G]
(13)
Summing all bumps i from 1 to the total number of bumps G results in the complete expression for the dependence of the floating gate voltage due to tunneled electrons VFG� on the number of endurance cycles n:
VFG = (1 /r CFG) ~41T Rci2 (s/4) JFNi
(14)
x (VM - VTUOi) exp (-ain)
The quantities after JFNi are the result of replacing ati in Eq(9) by Eqs(3) and (8). It now remains to define the end of endurance. Clearly, it arrives when the floating gate voltage is insufficient to establish the required logic level. The end of single cell endurance (n = Ne) occurs when the floating gate
voltage reaches a defined value (VFG = VFGM) that
is the boundary of that level.
SINGLE CELL ENDURANCE DATA
The test pattern used to characterize endurance is the nonvolatile part of a Xicor NOVRAM cell shown in Figure 3. The dimensions of the test cell are identical to those in a NOVRAM memory array. The advantage of this cell is that all voltages can be applied directly to this cell. Cycling is achieved by applying a ramp between ground and VM. VFG is read out by applying the same control voltage sweep simultaneously to ground, VM and P/E control. This couples to the floating gate and when a voltage equal and opposite to VFG is reached, the (floating) gate on the sense transistor will indicate zero charge. Upon increasing the control voltage sufficiently the floating gate potential is increased by the threshold voltage of the transistor, turning on the sense line. This value of the control gate is then recorded, generating the plot shown in Figure 4. The ordinate shows the value of the control voltage necessary to turn on the sense transistor. Since VFG is positive in the erase state, a negative control voltage must be applied. Therefore, the lower branch of the window plot represents the erase state. When VFG approaches the threshold voltage of the transistor, its reaction becomes indeterminate, and the limit of the endurance of the cell is reached. (n = Ne when VFG = VT). This situation is
indicated when the applied control voltage is exactly zero. Inspection of Figure 4 shows that the end of the endurance for that particular cell occurred at a number of cycles normalized to a value of 100. The same factor of normalization was applied to all data quoted here in order to prevent possible confusion with results from individual products, or with published specifications.
c~~ ~ac. . ~ T~
0021-3
Figure 3: This shows the circuit schematic of the nonvolatile part of a NOVRAM cell Two transistors are shown in addition to the elements in
Figure 1. Transistor 0 7 controls the access to the junction used for capacitive steering of write and erase operations, and transistor Os
senses the voltage on the floating gate. VFG can be measured by turning 0 7 on hard, and finding the control voltage that must be supplied simultaneously to poly 1, poly 3, and capacitor CC2, in order to cause a
specified current to pass through Os.
NOVRAM CELL ENDURANCE DATA
10
,-----..,.
5823 #24 BOTTOM
--------,--,------.---,-1--
,-
---
---
-,
68f~-=--l+=-=-=-+l-~-:-~:~:~-~"t'-.-------t--~+--1--~----Jl-~t--+-----tj
~ COGNATTREOL
4 2 i---t-~t-----t-----1t--~J~-_::--1r--~
VO~AGEO-r2-t-----+----+~-1-------+----+--+------1+t---~-~+l-~--------1t+--.-,-.-,-_-~J�
-4t---+---t--+----+._.L'.'.!,.L----t---l -61---+--+--~~v~,L'__--1---1--ll~+-~
~ -81--i--=~~i--:�:..J:..+---i'---I--~-~
-1._Q5 -4 -3 -2 -1
1 2
NORMALIZED LOG (NUMBER OF CYCLES)
0021-4 Figure 4: This is a plot of the charge transferred to the floating gate of a single NOVRAM cell as a function of the logarithm of the number of program/erase cycles. The actual floating gate voltage is the negative value of the control voltage minus the threshold voltage of Os.
RELATIONSHIP OF SINGLE CELL DATA TO LOT ENDURANCE
The number of program-erase cycles at a control voltage of zero was determined for a number of single cell structures from the same wafer lot. The results were plotted on log normal probability paper.
9-149
The results can be seen on Figure 5. Careful reading of the abscissa will establish its relationship with the usual chart. In effect, the scale has been extended on the low probability side of the distribution, and for simplicity of notation, the cumulative proba~ilities have been marked as their base ten logarithms. In a few selected locations near the right hand side, the equivalent percentage values were given in brackets. The single cell data points are on either side of the 50% line of the chart. The slope of the best fit straight line defines the dispersion of the distribution.
RELATIONSHIP OF SINGLE CELL DATA TO LOT ENDURANCE
-9-8-7-6 -5 -4 -3 -2
-.3 -.05 -.004
(1%) (10%) (50%) (90%) (99%)
CUMULATIVE PROBABILITY
0021-5 Figure 5: This shows the Log Normal probability plot of individual single cell endurance data. The right half of the plot is quite standard, as marked by typical cumulative percentages. The left half represents an extension of the standard chart to much lower probabilities, in order to permit predictions for specific members of a much larger population.
In order to relate these results to the endurance of a commercial lot of NOVRAMs, the definition of the endurance of an integrated circuit with an array of memory cells should be recalled. This definition states that the limit of the endurance of a chip is reached when the first cell fails, after having sustained the same number of data changes as every other cell on that chip. If that chip has 1024 memory cells, then the cell with the lowest endurance limit of these 1024 cells defines the endurance of that chip. The cumulative probability for this is 1/1024. Any chip with 1024 cells can be expected to have that endurance. The number of cycles at the cumulative probability of 1/1024 therefore represents the average endurance of a chip from a given lot. The lowest endurance on a wafer of chips is caused by the cell with the lowest endurance on that wafer. If there are, say, 850 chips per wafer, then the cumulative probability of this endurance limit is 1/(1024
x 850). Looking now at a full 50 wafer lot, the low-
est endurance of that lot has a cumulative probabili-
ty of 1/(1024 x 850 x 50). The plotting of ranked
data on probability paper requires "plotting posi-
tions" that result in about half the calculated cumulative probability values8 for the lowest value used. In order to be consistent with the plotted data points, the cumulative probability for the average chip endurance from the 50 wafer lot is 0.0005, and this is indicated by an arrow of Figure 5. Similarly, the lowest possible chip endurance on that wafer lot is 1E-8.
COMPARISON OF SINGLE CELL PROJECTION WITH COMMERCIAL LOT DATA
The endurance of individual arrays from a commercial lot can be described by a statistical distribution and its parameters. Since the endurance of an array is determined by the lowest endurance of a fixed number of cells, an Extreme Value distribution describes the distribution of the lowest endurances of all the arrays, and therefore, of the arrays within a lot.9 This applies regardless of the distribution of the endurances of individual cells within the same array. It is an empirical fact that it is the logarithm of the number of cycles that has the Extreme Value distribution, 1o very similar to the Log Normal distribution frequently found for data from electronic devices. Lot data can be handled simply by the use of Extreme Value probability paper. Available charts are designed for maximum extreme values. For minimum extreme values, such as the lowest endurance of an array, these charts can be used by substituting the complement for the cumulative probability of an observation in order to determine the plotting position. Instead of <f>, (1 - <f>) is used to determine the abscissa. Figure 6 is based on these considerations.
The abscissa is labeled by the complement values, which results in the reversal of the slopes of the straight line describing the distribution. The ordinate is Gust as Figure 4) in terms of the logarithm of the normalized endurance. Since the distribution is described by a straight line in this coordinate system, it requires only two points to define its locus. These two points were determined in the previous section: the endurance of the average array, and the minimum endurance of the lot. The difference from Figure 5 (aside from the distribution function) is that the definitions of the cumulative probability values have changed. In terms of an individual cell, the cumulative probability of the endurance of an array is related to 1/1024; in terms of the array, the cumulative probability is the expected average of individual array units. For the (maximum) Extreme Value distribution .this is 0.57; since the shape of the
9-150
distribution has not changed, the use of the complement does not apply and the value of the (log of) endurance on Figure 5 at the larger arrow is entered on Figure 6 at cf> = 0.57. Similarly, the minimum endurance of an array from a 50 wafer lot is now asso-
ciated with a cumulative probability of 0.5/(50 x
850) a value increased by a factor of 1024 over the corresponding single cell value (see preceding section). The cumulative probability for the minimum (array) endurance of a lot is therefore 1.2E - 5, to be plotted at the 0.99999 position. A straight line drawn through this point and the array average establishes the projected distribution of array endurances. This graphical technique of deriving lot endurances from single cell data will be supplemented by an equivalent mathematical approach in the Appendix.
How good is the fit to actual data? Endurances from a typical monitor of that general time slot in NOVRAM production are shown on Figure 6. The fit is not fortuitous: there are dozens of lot data with almost identical slopes over a range of roughly a factor of 0.5 to 2. Confidence limits (95%) from the single cell data permit a scatter twice as large.
ENDURANCE FROM SINGLE CELL VS. COMMERCIAL LOT DATA
fi3 g1.0r--i-!::�~-+---1---+---+-
(.)
~
~ 0.11--t----i----J--t-----+-----+----+-------+-----l ~
.01 .10 .37 .70 .90
.990 .9990
CUMULATIVE PROBABILITY (I-ct)
0021-6 Figure 6: This is a Log Extreme Value probability plot of the endurance of a lot of X2212 NOVRAMs. The points are measured values, the straight line represents endurances predicted from the single cell data shown in Figure 5.
CONSTANT CURRENT TESTING
The determination of endurance is a very time consuming process. In single cell data taking, typically tens to hundreds of millions of cycles are required. This routinely takes on the order of days to accomplish. For product endurance prediction, about twenty cells are needed, requiring simultaneous testing for any semblance of monitoring effi-
ciency. A much more rapid method of evaluation has been in use for some time. It depends on the observation of the time necessary to reach some predetermined tunnel voltage, when a constant current is forced through the test structure. An empirical factor correlates observed time with observed product endurance. Test times are on the order of ten to ten thousand seconds, depending on conditions used. Inspection of Eq(8) explains the reason for this. The time at during which constant current flows is proportional to VFG (Eq(3)). It is therefore exponentially decreasing with the number of writeerase cycles. Since the data ramp takes the same amount of time, whether current flows through the dielectric or not, the time consumed increases linearly with the number of cycles, while the limiting process decreases exponentially. A constant current test adds the periods of current flow without pauses, reaching the condition for the trap-up limit of endurance in a minimum of time.
MATHEMATICAL RELATIONSHIP BETWEEN ENDURANCE AND CONSTANT CURRENT DATA
The work described in reference (5) proved that the constant current data can be modeled by bumps whose size have the proper distribution. Since this requires the addition of the contributions of thousands of bumps, the number of different bump radii necessary for a good fit was studied. It was found that at low fluences, a large number was necessary, but after a sufficient amount of charge has passed through the dielectric, the contributions from different bumps had nearly equalized, so that only a few bump radii were a sufficient description. After high fluences, a single bump, representative of the maximum of the distribution of radii, could predict the tunnel voltage necessary to maintain a constant forced current. Since the end of endurance is brought about by high tunnel voltages after large fluences, this condition applies very well and is used in the following analysis. When, in Eq(14), Rei is replaced by RM, the summation sign is replaced by a multiplication by G. Then the factor to the left of,
and including, JFNi becomes l/(r x CFQ). But I = r
x CFQ, so that, when Rei becomes RM,
Ne = (1 I aM) ln[(VM - VTUoM)IVFGMl
(15)
9-151
Substituting r ><�� at (see Eq(3)) for the voltage term in parentheses in Eq(5), multiplying by dn and integrating results in
fdVai = airJatidn
(16)
The integral of at with respect to the number of cycles is, of course the total time of constant current flow through the dielectric. At the endurance limit, Vafi = VM - VTUOi - VFGMi,' and the integral of time intervals is equal to the total time of constant current.flow to the instant of the end of endurance, tNi� Again invoking th,e asymptotic limit of all Rci's becoming.RM,
tN = (VM - VrnoM - VFGM)/r aM
(17)
Solving Eq(17) for aM and substituting in Eq(15) results in the expression for endurance as calculated from constant current data
Ne = [r tN/(VM - VTUOM - VFMG)] .
(18)
x ln[(VM - VTUoM)IVFGM1
Conversely, the elapsed time at constant current
tN equivalent to endurance Ne is obtained by inter-
changing those two quantities in Eq(18). An esti~
mate of the time advantage is obtained by realizing
that in cycling, a minimum time of 2. x VM/r is
consumed per. cycle. Since typically, some time,
both analog and digital, is spent in the transition
from programming to erasing, this minimum time is
doubled.
�
� �
Therefore the elapsed time to reach the end �of endurance by cycling tee. is closer to
tee = 4 Ne VM/r
(19)
Substituting pertinent values, one can find that tN
is approximately tee/50.
�
EXPERIMENTAL CORRELATION OF CONSTANT CURRENT WITH CYCLING DATA
Textured poly capacitor test patterns from the same wafers that had� been used to obtaill the single cell cycling data displayed in Figure 5 were subjected to forced constant current conditions; and their tunnel voltages were recorded as a function of time. An automated test system exists to perform this test on a routine basis. When �tunnel voltage was plotted vs time, the data for ten such structures
resulted in Figure 7. According to Eq(17),� when Vat = VTU - Vruo = VM - Vruo - VFGM� then the end of endurance is reached. This condition .is indicated by the horizontal line at that voltage. The time tN to reach that can be read off the graph and converted into equivalent cycles by Eq(18). These endurances can then be plotted on a graph similar to that used in Figure 6.
9 V111 =V.-VTU&M-VF611
7
TUNNEL VOLTAGE VS. TIME AT CONSTANT CURRENT
SECONDS 2 4 6 8 10 12 14 16 18
0021-7 Figure 7.' This is a record of tunnel voltage (expressed as trap-up voltage) vs time.� The end of endurance is reached when the tunnel voltage reaches a value V01- The time associated with that voltage can be read off this chart.
The area of the constant current structure was eight hundred times that of the single cell capacitors. Since. its behavior is dominated by the highest current features, it is set equal to the endurance of the 400th lowest cell. This has been chosen as the average endurance of the lot of constant current devices. The fit in Figure 8 indicates good correlation between the two methods of determining endurance. This means that product endurances can be legitimately predicted from constant current data. Test times on the order of ten seconds are short enough for the E-test stage of wafer evaluation: they clearly permit the prediction of product endurance; But as increasing knowledge leads to an improvement in endurance, this time is expected to increase by several orders of magnitude. Eq(17) indicates a predictable acceleration technique. All that is needed is to increase the level of constant current, measure time to reach� the voltage of the en~ durance limit, and insert that value onto Eq(17). In addition, the value of r must be adjusted to reflect the new current value,. according tor= l/CFQ. Finally, a secondary adjustment must be made to the value of VruoM by calculation. Another method would be to increase the area of the constant current device to bring more low endurance features into play.
9-152
ENDURANCE FROM SINGLE CELL VS. CONSTANT CURRENT DATA
~> 1.0F=t-&-loo:::d-+---+----1------4-
(.)
; �.1~+--+----+--+----1--~,___;..J__.___J
::!!:
�CAL UED
FROM I
CONSTANT
CURRENT DATA
.01 .10 .37 .70 .90
.990 .9990 .9999 .99999
CUMULATIVE PROBABILITY (1-<I>)
0021-8
Figure B: This is again a Log Extreme Value probability plot. The points
are those calculated from the times measured via Figure 7. The straight
line represents the endurance predicted from the single cell data in Figure
~
.
SUMMARY
We have described a coherent body of understanding and data that permits the prediction of product endurance, and the use of devices for accelerated testing, from first principle device models. This fortunate circumstance arises from the advantageous technological feature of textured poly tunneling, namely that there is one, and only one, mechanism that is prevalent in determining the end of endurance.
This one mechanism is trap-up, the build-up of negative charge in the dielectric in proportion to the fluence of the tunnel current. The model for window closure and for single cell endurance flows naturally from this concept. The predictability of accelerated tests is also the result of this single unifying mechanism. The relationship with product endurance follows from basic statistical considerations.
ACKNOWLEDGMENTS
The authors would like to express their appreciation for the general support given to this work by Xicor management and staff. In particular, thanks are due to Yupin K. Fong and Kurt B. Raab for their effective help in the software development and for the performance of the measurements of the individual test structures.
APPENDIX
Mathematical Formulation for Lot Endurance from Single Cell Data
The approach taken here is simply to translate
the graphical operations �performed in preceding
sections into symbols. Underlying its simplicity are
the operations leading to the design of probability
papers. They begin by translating the cumulative
distribution of a variable into a linear function of that
variable. The single cell endurances have the form:
<Pc = 1/2 + (1 /2) {1 - exp [BELOW]}
(A 1)
BELOW = [-(7T/2) (In Ne - In Nc)2/CT2]
where <Pc is the _Eumulative probability of single cell endurance Ne, Ne is the average cell endurance, and CT its standard deviation. The function form chosen is an approximation 11 to the normal distribution function. It is chosen here because it could be inverted most simply into a form linear in Ne, since the intent is to make the operations more transparent to the reader. The same operations could be performed by using the exact integral formulation of the cumulative probability of the normal distribution. Expressing Eq(A1) as a linear function of In Ne
In Ne = In Ne - CT x Fe, where
(A2)
Fe = {(-7T/2) In [<f>c (1-<Pc)JJ112
(A3)
Eq(A2) relates any single cell endurance Ne to its probability factor Fe and via Eq(A3), to its cumula"" tive probability <f>c. The lowest endurance NcA expected from an array of cells is defined by
In NcA = In Ne - CT x FcA. where
(A4)
<PcA = [1I (#cells/array)]
An equation like Eq(A4) can be set up for the minimum endurance of a wafer lot NcM. where <PcM = [1/(#cells/wafer lot)]. For the lot endurances, an equivalent scheme is set up:
In NA= In NA - (1/a) X FA, where
(A5)
FA = In [-In (1 - <f>A)]
(A6)
Now NA is the endurance of an array (or chip), NA is the modal endurance of the lot, and FA is the probability factor derived from the Extreme Value distribution. Incidentally, FA is exact and not an
9-153
approximation. In analogy to Eq(A4), the average array endurance NAA has the form
In NAA = In NA - (1/a) X FAA
(A7)
The value of <f>AA for the average of the distribu".' tion must be 0.43, in order that its complement becomes 0.57, the locus of the average of the (maximum) Extreme Value distribution. The minimum en-
durance of the lot has the same subscript as Eq(A7), except that subscript AM is substituted for
AA The probability factor FAM is based on <f>AM =
[1I (#arrays/wafer lot)]. It will be realized that NeA = NAA� and NeM = NAM� Therefore two simultaneous equations can be solved for NA (the lot average), and 1I a (the lot dispersion), in terms of single
cell parameters:
1la = <T x [(FeM - FeA)/(FAM - FAA)},
(A8)
and
In NA= In Ne - <T x [(FcA x FAM - FAA (A9)
X FeM)/(FAM - FAA)]
Expressing Eq(A5) in terms of single cell parameters results in
In NA = In Ne - <T x {[FeA<FAM - FA)
(A10)
. - FcA(FAA - FA)]l(FAM - FAA)}
In this way, the individual endurances expected from a commercial lot NA can be predicted from the size of the lot tested, which determines FA� the single cell constants Ne and <r, and chip size details of that product, which convert the F's with double subscripts into specific constants.
REFERENCES
1. J. Drori, S. Jewell-Larsen, R. Klein, W. Owen,
R. Simko, W. Tchon; "A Single 5-Volt Supply Non-Volatile Static RAM"; 1981: IEEE lntn'I Solid State Circuits Conf. Technical Digest 24, pp. 148-9 (1981).
2. S. Jewell-Larsen, I. Nojima, R. Simko; "A 5-Volt RAM-like Triple Polysilicon EEPROM"; Proc. 2nd Annual Phoenix Conf., pp. 508-11 (1983). IEEE Catalog No. 83CH1864-8.
3. R.K. Ellis; "Fowler-Nordheim Emission from Non-Planar Surfaces"; IEEE Electron Device Letters, EDL-11, pp. 330-2 (1982).
4. R.K. Ellis, H.A.R. Wegener, J.M. Caywood; "Electron Tunneling in Non-Planar Floating Gate Memory Structures"; IEEE IEDM82 Digest, pp. 749-50 (1982).
5. H.A.R. Wegener; "Endurance Model for Textured Poly Floating Gate Memories"; IEEE IEDM84 Digest, pp. 480-83 (1984).
6. D.R. Wolters, J.F. Verwey; "Springer Series in ElectroPhysics 7"; p. 111 (1981).
7. M. Liang, C. Hu; "Electron Trapping in Very Thin Thermal Silicon Dioxides"; IEEE IEDM81 Digest, pp. 396-9 (1981).
8. J.R. King; "Frugal Sampling Schemes"; Tamworth, NH, Technical and Engineering Aids for Management, (1980).
9. H.A.R. Wegener; "Endurance of Xicor E2PR0Ms and NOVRAMs"; Xicor Reliability Report RR504 (1984).
10. E.J. Gumbel; "The Statistics of Extremes"; New York, NY Columbia University Press, (1958).
11. Eds. Milton Abramowitz & Irene A. Stegun; "Handbook of Mathematical Functions';; Natl. Bureau Standards, Applied Mathematics Series-55, p. 933 (1964).
9-154
liCI'
COMPARISON AND TRENDS IN TODAY'S DOMINANT E2 TECHNOLOGIES
By S.K. Lai & V.K. Dhamlntel Corporation Daniel C. GutermanXicor, Inc.
ABSTRACT
This paper reviews the three dominant E2 technologies today, namely the two floating gate approaches of thin tunnel oxide and oxide on textured poly and the dual dielectric approach of MNOS. It evaluates each approach with respect to cell design, operation, manufacturability, compatibility with established process technologies and reliability. It follows with a comparison of the technologies in the areas of development entry cost, scaling and reliability. After a review of the market place, this paper concludes with a projection of the requirements of E2 technologies to support full function, commodity E2 memories (E2PROM) as well as low cost microcontrollers and ASIC (Application Specific Integrated Circuits).
INTRODUCTION
Electrically alterable nonvolatile semiconductor memory has been an area of active research for many years, with the promise that it will be the ultimate silicon memory. The first floating gate memory was proposed in 19671 and MNOS memories were reported at about the same time.2 In 1980, the first 16K E2PROMs using MNOS3 as well as floating gate technologies on FLOTOX4 were reported, while textured poly E2PR0Ms were reported in 1983.5 However, after all these years of development in the laboratory and volume manufacturing, E2PROMs have yet to become a high volume, widely used memory component compared to EPROMs, the closest equivalent memory with lower functionality. There are many reasons given for the limited growth, ranging from the higher cost of E2PROM based products to poorly understood reliability of
� 1986 IEEE. Reprinted, with permission, from INTERNATIONAL ELECTRON DEVICE MEETING, IEDM, Los Angeles, CA, December 7-10, 1986.
these components. In this paper, we will focus on the technology factors by comparing the three dominant E2 technologies to date, and giving our own viewpoint on the development in the market place.
DESCRIPTION OF TECHNOLOGIES
FLOTOX (FLOating gate Tunnel OXide)
The cross sectional structure of a FLOTOX cell is shown in Figure 1a. It consists of a floating gate transistor with a thin oxide grown over the drain region. The floating gate is surrounded completely by high quality silicon dioxide, giving its superior retention characteristics. Programming (electrons into floating gate) is achieved by taking the control gate to high voltage while erase (electrons out of floating gate) is achieved by grounding the control gate and taking the drain to high voltage. Because the program and erase coupling conditions are different, they have different design considerations. Electron transfer is through Fowler-Nordheim tunneling mechanism using electric field higher than 10 MVI cm. The IV slope of tunneling is so steep that there is insignificant tunneling under normal read conditions for more than ten years. In order for the cell to properly operate in an array, it has to be isolated by a select transistor. Two cycles are required to load the correct data. All cells in a byte are first programmed, and then selected cells are erased using the drain for data control. The manufacturing process for FLOTOX is an extension of the EPROM technology, which in turn is an extension of the standard single poly silicon gate technology. The critical� step in the process is the growth of high
quality thin ( < 12 nm) tunnel oxide. For reliability,
the dominant failure mechanism for FLOTOX is the breakdown of the tunnel oxide due to defects under the high field stress of the program/erase cycles, resulting in a leaky oxide.6
Textured Poly Cell
The cross sectional structure of a textured poly cell is shown in Figure 1b. It consists of 3 layers of poly with overlap forming three transistors in series. The floating gate transistor is in the middle formed by poly 2. Again, the floating gate is surrounded by silicon dioxide for high retention. Programming is
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FLOTOX DEVICE STRUCTURE
FIELD OXIDE
Figure ta: Cross sectional structure of a FLOTOX memory cell.
achieved by electrons tunneling from poly 1 to poly 2 and erase is achieved by electrons tunneling from pol~ 2_ to. poly 3. The program and erase coupling ~gain 1s different. The poly 3 is taken to high voltage m both cases, and the element which tunnels is determined by the voltage applied from the drain and coupled to the floating gate through the channel region. The final data state is determined by the data state on the drain: this is a "direct write" cell with no need to clear before write as is required in the FLOTOX cell. This is possible because there are two active tunnel elements. The tunneling process is fundamentally still Fowler-Nordheim tunneling, with enhancement of local electric field due to the geometrical effect of fine texture at the poly surface. The electric field enhancement factor is in the range of 3 to 5, allowing much thicker oxides (60 nm to 100 nm) to be used. No extra transistor is required in an array since the poly 3 transistor serves the function of select� transistor, giving a much more compact cell layout. The manufacturing process for textured poly is again an extension of the EPROM process with the addition of an extra layer of poly. The critical process step in this process is the growth of the tunnel oxide on poly. Because thicker oxides are used, oxide� breakdown is less of a prob~ lem compared to FLOTOX. The dominant failure ~echan.ism in a te:xtured poly cell is electron trapping which results m memory window closure. 7
0022-2 Figure 1b: Cross sectional structure of a textured poly memory cell.
0022-1
MNOS (Metal Nitride� Oxide Silicon) Cell
The cross sectional structure of a MNOS cell is shown in Figure 1c. It consists of a single transistor with a dielectric stack of silicon nitride on top of a thin layer of oxide (1.5 nm to 2.0 nm) on silicon. Typically, the transistor resides in a well so that the channel potential can be controlled. Unlike the floating gate, charge is stored in discrete traps in the bulk of nitride. Because of the discrete nature of traps, charge transfer has to occur over the large area of the channel region. This is different from floating gate devices where charge transfer can occur over a small area removed from the channel region. On the other hand, any dielectric defect fatal to floating gates will only discharge local traps in MNOS. Programming is achieved by applying high voltage to the top gate whereas erase can be achieved by grounding the top gate and taking the well to high voltage. The program and erase� coupling is symmetrical. Because of the very thin oxide, charge is being leaked off continuously due to the internal field, giving an ever diminishing window. In an array, select transistor is required to operate the cell properly. The select transistor may be separate3 or integratedB in which case a more compact cell layout can be realized. Two cycles are again required to load the correct data. Furthermore, the well potential has to be controlled during data change, which makes the array operation more complex. The manufacturing process for MNOS is an extension of single poly silicon gate technology. The memory transistor is fabricated after the first poly periphery transistors are formed to maintain the integrity of the dual dielectric storage element. The
9-156
z
<
c0::
N+
NITRIDE
N-SUBST
Figure tc: Cross sectional structure of a MNOS memory ce/lB
important steps include thin oxide growth, nitride deposition and post nitride temperature cycles. The biggest reliability concern is cell retention and its degradation with cycling.9
COMPARISON
The three different approaches have their technical merit and difficulties. Any one of these technologies can be made to work if they are given sufficient effort and focus. As a result, other considerations ranging from "comfort factors" to compatibility with available technologies tend to determine the choice.
Development Entry Cost
Entry cost is the amount of extra effort required to bring up a new technology. To an EPROM manufacturer, it is relatively easy to take the FLOTOX approach. The cell concept is simple and the tunnel oxide process is a straight forward variation of a standard high quality oxide furnace cycle. This is why the majority of companies have opted for this approach for their E2 effort. The textured poly approach, on the other hand, depends on a tunneling process which is not generally understood and is believed to require tighter process control. The cell concept is more complex and the use of three layers of poly imply higher wafer cost. These factors have limited the popularity of developing this approach. Finally, MNOS approach requires the mastering of a number of difficult process steps. The growth and control of the ultra thin oxide, as well as the quality of nitride are critical issues. As a result, despite gaining initial momentum, MNOS has not achieved dominance as an E2 technology.
0022-3
Scaling
There are many factors that determine the size of a memory cell, and generally cell design represents finding the optimum compromise of a number of tradeoffs. Furthermore, as these technologies approach fundamental physical or practical material limits, scaling will become increasingly difficult. For FLOTOX, there is large area requirement for layout of the two transistors plus the tunnel oxide area, dictated by minimum design rules. The select transistor is limited by high voltage. Given the high oxide capacitance of thin tunnel oxide, large poly to poly area is required for the sense transistor. Scaling of the tunnel dielectric is also limited by direct tunneling at 6 nm and yield and reliability issues at 8 nm to 10 nm. Typically, relatively high voltages (15V to 20V) are required to operate the cell. As a result, FLOTOX cell does not scale well.
In the case of textured poly, the three poly layers are integrated resulting in a compact layout. Cell size is limited more by lithographic registration of poly layers than by ability to resolve space between poly lines as is the case with FLOTOX. Furthermore, the thick tunnel oxide requires smaller coupling capacitor area to give the required coupling. Given the same performance and reliability requirement, it is estimated that a textured poly cell is about a factor of two smaller compared to a FLOTOX cell for a given generation of technology. Textured poly does require higher operating voltage (> 20V) and thus needs a high voltage technology to support it. Finally, scaling of the poly oxide involves more than thinning down the oxide as the field enhancement factor changes with oxide thickness.
The basic MNOS memory cell can be very small and highly scaleable. The select transistors, wheth-
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er separated3 or integrated,8 will limit scaling. However, in either case, the cell size is better than FLOTOX, and competitive with triple poly for a given generation of technology. One major problem is the requirement of well voltage control. Full byte function is only possible with separate well, giving a large effective cell size. Page function8 can be used to partially circumvent the well problem but limits endurance. For oxide thicknesses, there is little or no room to scale the ultra thin tunnel oxide, so most of the emphasis has been on scaling the nitride. Charge leakage from the scaled nitride to top gate has been solved by oxidizing the nitride to give a MONOS stack. Low program and erase voltages have been demonstrated at the expense of smaller operating window.
Reliability
One general problem for E2PROM is the limited information on the reliability of the technologies due to sample size or correlation problems. For floating gate technologies, there is no intrinsic problem with data retention, and because the technologies are designed to handle high voltage, there is very low failure rate due to normal 5V operation. Reliability problems occur during program and erase cycles in part because very high voltages are used. For FLOTOX, there is random single bit failure due to oxide defect resulting in a leaky oxide that loses charge over time (see Figure 2). For textured poly, the average electric field across the tunnel oxide is 3 to 5 times lower compared to FLOTOX. As a result, oxide breakdown failure is reduced significantly. On the other hand, there are more electron traps in the oxide, and the impact of electron trapping is magnified by the 3 to 5 times field enhancement factor. Consequently, electron trapping is the dominant failure mechanism, showing up as a failure to program or erase. The failure can be projected real time with margining techniques and since trapping is an intrinsic property, failure probability can be easily projected. In MNOS, charge retention is the dominant reliability issue (see Figure 3). The charge loss process is time dependent, resulting in continuous loss of cell margin and performance. The degradation based on short term data is difficult to predict. The ultra thin oxide is stressed by electric field comparable to FLOTOX and retention is further degraded with program and erase cycles. So far, wide variation in retention and endurance are being reported based on limited sampling.9
0022-4 Figure 2: Endurance of 3 E2 Technologies: FLOTOX and textured poly processed at Intel (16K arrays), MNOS data from Hitachi {prorated to 16K).
e o.s
>
~ 0.6
8
~ 0.4
0.2
10
103
1o4
TIME(sec)
0022-5 Figure 3: Data Retention: Floating gate, no intrinsic charge retention problem; MNOS, continuous charge loss and window closure tending to become worse after cycling.
THE MARKET PLACE
Though E2PROMs have been available for the last five years, their usage has not grown to the volumes projected. A host of new and established companies have become active in the field, but lack of technology and product feature standardization, together with high cost and reliability concerns have limited the growth in the market place. The major issues for 16K have been 5V only, address/data latch vs no latch, ready/busy vs data polling, 24 pin vs 28 pin, 1 ms vs 1O ms program, self timed vs user timed, with and without Vcc lockout and 1OK vs 1 Million cycles endurance. Byte vs page function and page size are issues at 64K density level. In addition, one can choose oxynitride vs oxide for FLOTOX, textured poly vs FLOTOX for floating gate, and MNOS vs floating gate for E2. The reliability claims are difficult to understand and verify due to the link of failure to endurance cycling. Different
9-158
methods are used in reliability evaluation, and no standard exists to allow a meaningful comparison. For example, high temperature cycling is worse case for FLOTOX but may be best case for textured poly. Nevertheless, there has been continued growth in the E2PROM market, sustained by a wide, diversified application base. The driving force is end-user, in-the-field customization capability offered to microprocessor based products, which is either unavailable, unreliable or not cost effective using other techniques. As a result, standards are now established following 5V-only RAM-like functionality, and the cost and density gap to competing solutions continues to close.
FUTURE TRENDS
There are two major driving forces in the development of E2 technologies for the future. One of them is high density memories, requiring small memory cell size for the lowest cost per bit. The second requirement is low density nonvolatile memories in microcontrollers and programmable logic type applications. In the latter case the absolute cell size is not as important as process simplicity and low cost of the overall technology. MNOS based E2 memories will continue to be used in low density memory as well as military applications requiring high radiation tolerance. However, it has only enjoyed limited popularity for use in high density memory and the trend will continue. A majority of companies have opted for FLOTOX as their first E2 technology because of the simple device physics and the low entry cost for development. Recently, many Japanese companies have announced 64K E2PROMs based on FLOTOX for the smart card market. A number of companies have applied FLOTOX in ASIC and programmable logic array applications. In fact, some have developed single poly versions of FLOTOX for synergy with random logic technology. However, for stand alone high density E2 memories, FLOTOX will be increasingly limited by defect oxide breakdown problems,1o giving unacceptable failure rate above the 64K level, unless thicker oxides or new dielectrics can be used in new approaches. Error correction codes can also be used but at the expense of additional die cost.11 Finally, textured poly inherently gives a smaller memory cell and suffers least from the oxide breakdown problem. Electron trapping is an intrinsic property that can be predicted and easily screened. Consequently, textured poly technology is expected to be most reliable and cost effective for 256K and above densities, while the higher cost of a three layer poly process may limit its use in logic applications.
The nonvolatile memory technology is an ever evolving field. Memories12,13,14 based on hybrid operation of programming by EPROM and erase by tunneling have gained interest. The erase function is generally limited to the full array and thus it is called FLASH erase. Recent approaches offer cell size and technology complexity comparable to EPROMs, and the functionality of electrical erase. If such technologies are proven to be reliable and manufacturable, they will fill the need of a special market segment and become another major force in the developing nonvolatile memory market.
SUMMARY
We have reviewed the three dominant E2 technologies today. MNOS is used in low density memories as well as military applications, but enjoyed only limited popularity for high density memories. FLOTOX has been the most popular approach because of its simplicity and is most suited for low density memories and programmable logic type application. Textured poly gives the smallest memory cell size and is the most cost effective and reliable approach for high density memories.
REFERENCES
1. D. Kahng and S.M. Sze, "A Floating Gate and Its Application to Memory Devices", Bell Syst. Tech. J., 46, 1283 (1967).
2. H.A.R. Wegener et al., "The Variable Threshold Transistor, a New Electrically Alterable Nondestructive Read-Only Storage Device", presented at the IEEE Electron Devices Meeting, Washington, D.C., 1967.
3. T. Hagiwara et al., "A 16 Kbit Electrically Erasable PROM Using n-Channel Si-Gate MNOS Technology", IEEE J. of Solid State Circuits, SC-15, 346 (1980).
4. W.S. Johnson et al., "A 16 Kbit Electrically Erasable Nonvolatile Memory", ISSCC Tech. Digest, p. 152 (1980).
5. S. Jewell-Larsen et al., "A 5 Volt RAM-like Triple Poly Silicon EEPROM", Proc. 2nd Annual Phoenix Conf., p. 508 (1983).
6. R.E. Shiner et al., "Characterization and Screening of Si02 Defects in EEPROM Structures", 21st Annual Proc. Reliability Physics, p. 248 (1983).
9-159
7. H.A.R. Wegener, "Endurance Model for Textured Poly Floating Gate Memories", IEDM Tech. Digest, p. 480 (1984).
8. A. Lancaster et al., "A 5V-Only EEPROM with lr;iternal Program/Erase Control", ISSCC Tech. Digest, p. 164 (1983).
9. W.D. Brown, "MNOS Technology-Will it Survive?", Solid State Tech., p. 77 (July 1979).
1o. A. Bagles, "Characteristics and Reliability of
100A Oxides", 21st Annual Proc. Reliability Physics, p. 152 (1983).
11. S. Mehrotra et al., "A 64 Kb CMOS EEPROM with On-Chip ECC", ISSCC Tech. Digest, p. 142 (1984).
12. D. Guterman et al., "Electrically Alterable HotElectron Injection Floating Gate MOS Memory Cell with Series Enhancement Transistor", IEDM Tech. Digest, p. 340 (1978).
13. F. Masuoka et al., "A New Flash E2PROM Cell Using Triple Polysilicon Technology", IEDM Tech. Digest, p. 464 (1984).
14. S. Mukherjee et al., "A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM", IEDM Tech. Digest, p. 616 (1985).
9-160
�c1,
NEW ULTRA-HIGH DENSITY TEXTURED POLY-Si FLOATING GATE E2PROM CELL
By D. Guterman, B. Houck,
L. Starnes and B. Yeh
This paper describes a new, highly scaled cell structure, the smallest full function E2PROM cell reported to date. It utilizes the textured triple-poly-si technology, exploiting the high degrees of structural and functional integration, to achieve a cell size of 31 �2. A top view of the cell, built with 1.2 micron rules is shown in Figure 1, with cell cross-section and equivalent circuit shown in Figures 2 and 3, respectively.
POLY3
BITUNE CONTACT-...
METAL/ BIT LINE
Figure 1: Cell top view.
GROUND DIFFUSKlN
POLY 2 fillt\00
GATE
0023-1
Figure 2: Cell cross-section.
0023-2
POLY 3
INORD LINE
lUNNEIJNG
I
l.!~~T -iE1:_t_L ___I __J
1'
COMMON POLY1
Figure 3: Cell equivalent circuit.
0023-3
� 1986 IEEE. Reprinted, with permission, from INTERNATIONAL ELECTRON DEVICE MEETING, IEDM, Los Angeles, CA, December 7-10, 1986.
Very small memory cell size is achieved by exploiting the vertical integration of the three poly layers to form a merged gate single transistor cell. This cell is made possible through the dual functions incorporated within various key components; specifically, (1) the poly 3 element, which functions as both word line select transistor and erase tunneling anode (2) the poly 1 electrode which serves the dual role of cell ground isolation transistor and programming cathode during write operation, and (3) the poly 2 floating gate transistor whose channel region establishes both the floating gate charge-conditional current path for reading and the input-dataconditional steering capacitor for writing. Charge transport to and from the floating gate is through Fowler-Nordheim tunneling, established by the geometrically enhanced fields at the textured poly inter~a.ces. between poly-si layers. This allows tunneling m1ect1on and transport to occur across oxides of
thickness greater than sooA at voltages less than 15V. In comparison to ultrathin (1 ooA) E2PROM
technologies, the thicker interpoly oxides result in lower parasitic capacitance of the tunneling element, improved dielectric reliability because of the 3-Sx lower average fields in the oxide, and an easier path to oxide scaling.
Because of the simultaneous incorporation of the poly 2 to 1 programming and poly 3 to 2 erase tunneling elements, data storage is a direct, single pass operation, involving the following sequence (see Table I). First the poly 1 line, common to the entire array, is brought low, cutting off the conduction path from bit line through the cell to array ground. Next, the bit lines. are set up to either OV for an erased state or about 16V for a programmed state. Finally, the poly 3�word line is ramped up to about 22V in 1 ms to drive the nonvolatile charge transport. To erase, the bit line is grounded, whereupon the channel under poly 2 capacitively steers the floating gate towards ground. This induces sufficient voltage across the poly 3/2 tunneling element to remove electrons from the floating gate. When the bit line is high for programming, the channel potential steers the floating gate positively. This
TABLE I: OPERATING CONDITIONS
Operation
Bit Line
Poly3 Poly 1
Standby
2V
0
5V
Read
2V
5V
5V
Write Erased State
0
-22v Low
Programmed State -16V
9-161
induces sufficient voltage across the poly 2/1 tunneling element to inject electrons onto the floating gate.
Following up on the present 256K product experience, a number of fundamental factors are incorporated into the technology to maintain a high degree of reliability with scaling. Dielectric integrity and excellent charge retentivity is preserved through the use of thick, high quality thermal Si02 dielectrics, throughout. Direct write cell operation provides shorter write time by eliminating the unconditional clear before write. As in previous floating gate E2PR0Ms, 5V-only capability via on-chip voltage multiplication is possible because of the efficient Fowler-Nordheim tunneling' mechanisim.
Small test arrays of the 31 �2 cell, shown in the SEM views of Figure 4, have been built and operated successfully for endurances of 1 million writes. Figure 5 shows a representative extended endurance plot, demonstrating erased state cell currents of greater than 40 �A and programmed cells having thresholds of greater than 5V, thereby remaining in cutoff.
Figure 4a: Cell SEM top view.
Figure 4b: Cell SEM cross-section.
0023-5
ENDURANCE DATA LOT# BD230001S/04 X130/1
�E1~r==I 40r-~
j ~:OJ...����� .. �J .......I.......I......I......I.......I.......
g g 0 g
�
~
Number of write c~les g �'
0023-6
Figure 5: E2PROM cell test endurance data.
0023-4
In conclusion, this paper reports the smallest full function E2PROM cell described to date. Small size is a result of a cell in which elements serve multiple functions and a technology which is conducive to scaling. This approach will serve as foundation for developing future generation E2PROMs beyond today's 256K density.
9�162
Jico,
RELIABILITY COMPARISON OF FLOTOX AND TEXTURED POLY E2PROMs
By Neal Mielke-Intel Corporation Lori J. Purvis & H.A. Richard WegenerXicor, Inc.
SUMMARY
FLOTOX and Textured Poly E2PROMs share the excellent retention and lifetest performance of the more common EPROM. In particular, retention failures add only about 20 FIT to lifetest failure rates in the 100 FIT range. The lifetest failure rates compare favorably with those of simple static logic products, because these high voltage devices have no oxide breakdown problems during 5V operation. FLOTOX endurance is limited entirely by oxide breakdown, overwhelmingly of the tunnel oxide. Window closing, caused by electron trapping, occurs but does not cause failure in well-designed products.
The Textured Poly approach offers a reliability tradeoff: less oxide breakdown but more window closing. This tradeoff becomes favorable at higher densities. This is because oxide breakdown, being a defect mechanism, worsens with increasing memory size and with scaling of oxide thickness. Window closing is an intrinsic mechanism that does not worsen dramatically with higher density. The two failure mechanisms-oxide breakdown and window closing-should be treated separately in reliability evaluations because they have different dependencies on cycling, temperature and retention bakes.
RETENTION CHARACTERISTICS
The E2PROM retention is at least as good as the EPROM retention, as shown in Table I. The 0.2% failing for the I 2817A represents only 20 FIT added to the failure rate. All retention failures are at most only a few bits out of the memory array. Intrinsic retention limitations simply do not exist on these technologies; most bits have essentially unlimited retention.
Excellent retention is expected with these technologies for two reasons:
1) The stored charge on the floating gate is contained by the 3.2eV energy barrier which exists at the Si-Si02 interface. This barrier height is quite high, comparable to the barriers preventing dopant atoms from redistributing.
2) The oxide layers, even with FLOTOX, are thick enough to prevent carriers from tunneling off the floating gate during low voltage operation.
LIFETEST PERFORMANCE
TABLE II: LIFETEST COMPARISONS OF INTEL E2PROM, EPROM AND STATIC LOGIC
Product(s) Technology
125�C Lifetest Predicted Failure Rate (55�C, in FIT)
Breakdown Retention Total
2817A
FLOT OX
0
27256
EPROM
0
21148,
HMOS-11
110
8088, etc.
36
70
22
63
0
120
The failure rates predicted from lifetest in Table II compare favorably with those of EPROMs, which in
TABLE I: RETENTION COMPARISON OF INTEL EPROM AND E2PROM, AND XICOR E2PROM
Product
I 2764A I 2817A X2864G
Technology
EPROM FLOTOX Textured Poly
Sample
1800 550 350
Temp
250�C 150�C 250�C
48Hrs
0.9%* 0.0% 0.0%*
% Fail in Retention Bake
168 Hrs
500 Hrs
1.1% 0.0% 0.0%
2.0% 0.2% 0.0%
1000 Hrs
-
0.2%* 0.3%
*Represents ~ 15 Years at 55�C (EA = 0.6eV).
9-163
turn compare favorably with those of non-floating gate technologies. E2PROMs compare favorably with EPROMs because they are very similar technologies. It is only during endurance cycling that E2PROM operation differs significantly from EPROM operation. EPROMs and E2PROMs compare favorably with static logic devices because the nonvolatile devices are built on high voltage technologies and are operated during product testing at high voltages. This all but guarantees that there will be no oxide breakdown failures during 5V operation. Static logic devices generally are dominated by oxide breakdown. In addition to the Intel data above, NEC has reported that 65% of field failures from 1976 to 1979 were due to oxide failure.
ENDURANCE CHARACTERISTICS
99.99 ....-----..-----..---------. 99.9 t----+----+----------1 99.5 t----+----+----------1 99.0 t-----t-----1--------1
95.0 t----+----+---J...------1 90.0 t----+----+----7._+--t I- 80.0 t----+----+----<lr______,
~ 60.0 t-----+----+---=-:.._L____,
ffi 40.0 t----+----t--L~:I----<_io.--------1
a.. 20.0
z~
~:~ ~ 10.0 t - - - FLOTOX....:: L ---+rExTURED
0.5 ~
POLY--1
0.1 t - = = - - t - - - - - 1 - - - - - - - 1
O.Q1 ....___ _.....___ _.....___ _____.
103
CYCLES
0024-1 Figure 1: Percent fail vs. number of cycles at room temperature for FLOTOX (2816A, 2817A) and Textured Poly (2864).
FLOTOX endurance, as shown in Figure 1, has a single broad distribution of failures. Textured Poly endurance has a low level defect tail followed by a sharp wearout beyond 150K cycles. The curves imply that the Textured Poly approach offers a tradeoff under which a lower defect tail can be had at the expense of some wearout endurance. There are 3 primary failure mechanisms represented in Figure 1:
1) Tunnel Oxide Breakdown-the dominant FLOTOX mechanism, also responsible for part of the Textured Poly defect tail.
2) Gate Oxide Breakdown-responsible for the remainder of the Textured Poly defect tail.
3) Window Closing-the cause of Textured Poly wearout.
These three mechanisms will be discussed in turn.
ENDURANCE: TUNNEL OXIDE BREAKDOWN
A typical FLOTOX or Textured Poly cell can be cycled over a million times without oxide failure or any degradation in retention characteristics. Occasional defective tunnel oxides will eventually break down under the high electric field ( ~ 1O MVI cm) necessary for tunneling. When this occurs, the defective cell will either become stuck to one logic state (if the oxide is truly shorted) or fail to retain charge (if the oxide is only leaky). Generally, the oxide breakdown increases gradually with cycling-a bit becomes leaky slowly, then faster, and eventually it becomes stuck. Tunnel oxide breakdown is responsible for about half of the Textured Poly defect tail. It displays the same characteristics as FLOTOX.
ENDURANCE: GATE OXIDE BREAKDOWN
Both E2PROM types require high voltages to program and erase. This puts high stress on MOS gate oxides both in the cell and in the� 1ogic circuitry using high voltage. This high stress causes defective gate oxides to break down. Typical symptoms are a row or column failure or failure of the entire device. This failure mechanism is responsible for the remainder of the Textured Poly defect tail.
Although more common on Textured Poly than on FLOTOX because of somewhat higher voltages, the overall oxide breakdown failure rate of Textured Poly (tunnel oxide plus gate oxide) is still significantly lower than that of FLOTOX.
ENDURANCE: WINDOW CLOSING
During endurance cycling, some of the electrons tunneling through the tunnel oxides become trapped there. The resulting negative oxide charge inhibits further tunneling. The effect of this electron trapping
9-164
is that with further cycling a cell requires higher and
higher voltages to program and erase. This mecha-
nism is responsible for the entire wearout region of
the Textured Poly curve but is non-existent in the
FLOTOX curve.
.
In Figure 2 Textured Poly shows a dramatically
higher rate of trap-up. As a result, window closing is
the dominant wearout mechanism of Textured Poly,
whereas it is an issue of FLOTOX only if the circuit
design is marginal.
10.0
9.0
8.0
>a.. 7.0
<l 6.0
0.:
::::> 5.0
a<aI.::.
4.0
t- 3.0
2.0
1.0
101 102 103 104 105
CYCLES
0024-2 Figure 2: Trap-up vs. cycles for Textured Poly (2864) and FLOTOX (2816A). Trap-up is measured in terms of the increase in programming
voltage a Vp necessary to program the cell.
TRAP-UP/BREAKDOWN TRADE OFF
wyw TEXTURED POLY:
FLOTOX:
Tox =sooj
Figure 3: FLOTOX and Textured Poly structures.
0024-3
Trap-up is greater in the Textured Poly approach because:
1) The trapping probability for a single electron is proportional to No- Tox. which for the same trap density N and cross-section o- is greater for Textured Poly, since Tox is greater.
2) The effect of the trapped charge is multiplied by the same field acceleration factor responsible for the field enhancement used for tunneling.
3) There is less field induced detrapping because the average electric field is lower.
Tunnel oxide breakdown is less frequent in the Textured Poly approach because:
1) The tunnel oxides are thicker and therefore are less sensitive to microscopic defects.
2) The high electric field responsible for tunneling occurs only in the region of oxide near texture points; the bulk of the oxide sees only low field stress.
The trap-up/breakdown tradeoff is fundamental to the Textured Poly approach.
BENEFITS OF THE TRADEOFF
Trap-up is an intrinsic mechanism, determined by trap density, trap cross-section, and initial window size. There is some variation from cell to cell in these parameters, causing some to fail somewhat earlier than others, but the distribution is relatively tight. As a result, trap-up endurance becomes only slightly worse with increasing memory size.
In contrast, oxide breakdown is a defect mechanism, and the failure rate is proportional to the defect density and the memory size. As a result, FLOTOX endurance will always become proportionately worse with increasing memory size unless defect density is continually improved. In addition, scaling FLOTOX implies scaling the tunnel oxide thickness, making the oxide even more sensitive to defects.
For this reason, there is a crossover in reliability between FLOTOX and Textured Poly, with the Textured Poly tradeoff becoming favorable at high densities. Excellent endurance even at high densities is possible with the Textured Poly approach because the defect tail, being only low level, can be screened.
9-165
fail to program correctly. The remainder are cases of oxide degradation and suffer reduced retention instead. As a result, retention bakes must be performed after cycling on FLOTOX in order to adequately detect cycling failures:
CYCLE
TEST FOR CORRECT PROGRAM/ERASE
100 150
TEMPERATURE 0 c
0024-4 Figure 4: Comparison of median endurance for FLOTOX (2816A) and Textured Poly (2212) as a function of cycling temperature.
FLOTOX failure, due to tunnel oxide breakdown, is accelerated by cycling temperature (EA 0.18eV), as shown in Figure 3. Textured Poly failure, due to window closing, is decelerated by cycling temperature (EA - - 0.11 eV). Whereas it is well known that temperature accelerates oxide breakdown, it also accelerates detrapping of electrons and therefore extends Textured Poly endurance.
A reliability evaluation of these two products performed at 50�C would detect equivalent median endurances, but an evaluation performed at room tem-
perature would favor FLOTOX by about 5 x and one
at 125�C would favor Textured Poly by about 1Ox. This temperature acceleration holds true for the median endurance, but the Textured Poly defect tail is due to oxide breakdown and will tend to behave more like the FLOTOX data.
EFFECT OF BAKES
In many FLOTOX endurance evaluations, less than half of the oxide breakdown failures actually
72 - HOUR 150�C RETENTION BAKE
TEST FOR RETAINED DATA
0024-5
In order to take intermediate readouts (after, say, 2K and 5K cycles), the flow of test/bake/test may be repeated at each readout. This worst-case flow for FLOTOX may be best-case for Textured Poly, however, because high temperature retention bakes cause electrons to detrap significantly, reversing prior window closing and therefore increasing measured endurance.
SUGGESTED ENDURANCEEVALUATION METHODOLOGY
The best way to measure E2PROM endurance is to run separate evaluations for the two dominant failure mechanisms: window closing and oxide breakdown.
9-166
Window Closing
SMALL SAMPLE or MEMORY DEVICES
(20)
CYCLE 1K TIMES
TEST FOR PROGRAM/ERASE
REPEAT TO >100K CYCLES
EXTRAPOLATE WEAROUT CURVE TO DESIRED ENDURANCE LIMIT ( 1OK)
TO DETERMINE FAILURE RATE
Oxide Breakdown
LARGE SAMPLE or MEMORY DEVICES
(>100)
0024-6
1OK PROGRAM/ERASE CYCLES
TEST FOR PROGRAM/ERASE
WRITE TO NON-EQUILIBRIUM STATE
PERFORM RETENTION BAKE
(72 - HOUR 1so0 c OR LONGER)
These flows will work for either FLOTOX or Textured Poly. Intermediate readouts may be performed in the oxide breakdown flow, but the test/bake/verify sequence should be repeated at each readout.
ALTERNATIVE EVALUATION METHODOLOGIES
Single-cell endurance data are sometimes presented by manufacturers. This approach will overestimate endurance by orders of magnitude because of the importance of oxide defects and even cell-tocell variations in trap-up. It might be possible to conclude from single-cell data that a certain FLOTOX cell is "superior" to a certain Textured Poly cellbut a 256K E2PROM constructed with the Textured Poly cell might be several times more reliable.
Worse yet, test pattern data from oxide capacitors are sometimes presented, without backup product data, to "prove" that a certain oxide is "superior" to another. Only product data can reliably be used to compare E2PROM product endurance. Small samples are useful in measuring wearout (median endurance), but large samples are necessary for measuring defect-related tails to the distribution.
CONCLUSION
The non-endurance-related reliability of FLOTOX and Textured Poly E2PROMs are similar and comparable to EPROMs and simple logic devices. Textured Poly offers a tradeoff between oxide breakdown and window closing which is beneficial at high densities. Reliability evaluations should distinguish between the two dominant E2PROM failure mechanisms: Namely, oxide breakdown and window closing.
VERIFY CORRECT DATA
0024-7
9-167
NOTES
9-168
1i1:1,
Ordering Information . . . . . . . . . . . . . . . . . . . . . . Packaging Information . . . . . . . . . . . . . . . . . . . . . Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1 10-15 10-29
NOVRAM * Data Sheets
I Serial Products Data Sheets
IE2PROM Data Sheets
E2POTTM Data Sheets
Microcontroller Peripheral Products
Memory Subsystems
Die Products
Application Notes and Briefs
Product and Technology Reliability Reports Ordering Information and Package Drawings
Ordering Information
X2201A: 1024 x 1 NOVRAM
X2201A
Device-------~
X /X
TLL
Store Cycles
Blank = 10,000
Package
D = 18-Lead Cerdip
X2210: 64 x 4 NOVRAM Device
X2210
T
1L X X /X Store Cycles Blank = 10,000 15 = 50,000 /10 = 100,000
Temperature Range
Blank = 0�C to + 70�C I = -40�C to + 85�C
~---Package
P = 18-Lead Plastic DIP D = 18-Lead Cerdip
X2210A: 64 x 4 NOVRAM
X2210A
Device-------~
X X
TLL Temperature Range Blank = 0�C to + 70�C
Package P = 18-Lead Plastic DIP D = 18-Lead Cerdip
10-1
Ordering Information
X2212: 256 x 4 NOVRAM
Device
X2212
T
X X /X
LStore Cycles Blank = 10,000 /5 = 50,000 /10 = 100,000
Temperature Range Blank = 0�C to + 70�C
I = -40�C to + 85�C
~---Package
P = 18-Lead Plastic DIP D = 18-Lead Cerdip
X2212A: 256 x 4 NOVRAM
X2212A
Device-------~
X X
TLL Temperature Range Blank = 0�C to + 70�C
Package P = 18-Lead Plastic DIP D = 18-Lead Cerdip
X22C10: 64 x 4 CMOS NOVRAM
X22C10
Device------~
X X
TL1_ Store Cycles Blank = 1,000,000
Temperature Range Blank = 0�C to + 70�C I = -40�C to +85�C
.____ _ _ Package P = 18-Lead Plastic DIP D = 18-Lead Cerdip
10-2
Ordering Information
X22C11: 64 x 4 CMOS NOVRAM
Device
X2001: 128 x 8 NOVRAM
Device
X2004: 512 x 8 NOVRAM
Device
X22C11
Lx x
Store Cycles
Blank = 1,000,000
Temperature Range
Blank = 0�C to + 70�C I = -40�C to +85�C
Package
P = 18-Lead Plastic DIP D = 18-Lead Cerdip
X2001
I
Lx x -X
ABlcacneks=s
Time 300 ns
-25 = 250 ns
-20 = 200 ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to + 85�C
Package
P = 24-Lead Plastic DIP
X2004
Lx x -X
ABlcacneks=s
Time 300 ns
-25 = 250 ns
-20 = 200 ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to + 85�C
Package
D = 24-Lead Cerdip J = 32-Lead PLCC
10-3
Ordering Information
X2444: 16 x 16 Serial NOVRAM
x2444� x x
Device-------T__.
LTemperature Range Blank = 0�C to + 70�C I = -40�C to + 85�C
Package
P = 8-Lead Plastic DIP
D = 8-Lead Cerdip
S = 8-Lead SOIC
X24C44: 16 x 16 CMOS Serial NOVRAM
X24C44
Device---------'
X X
LTemperature Range Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 8-Lead Plastic DIP
D = 8-Lead Cerdip
S = 8-Lead SOIC
X24C45: 16 x 16 CMOS Serial NOVRAM
X24C45
Device _ _ _ _ _ _ ____,
X X
LTemperature Range Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 8-Lead Plastic DIP
D = 8-Lead Cerdip
S = 8-Lead SOIC
10-4
Ordering Information
X2402: 256 x 8 Serial E2PROM Device
X2404: 512 x 8 Serial E2PROM Device
X2402
T
x x
LTemperature Range Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 8-Lead Plastic DIP D = 8-Lead Cerdip S = 14-Lead SOIC
X2404
T
x x
LTemperature Range Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 8-Lead Plastic DIP D = 8-Lead Cerdip S = 14-Lead SOIC
10-5
Ordering Information
X24C01: 128 x 8 CMOS Serial E2PROM
X24C01
Device------~
X X -X
1LvccRange Blank = 5V � 10%, 100,000 Cycles
L 3.5 = 3.5V to 5.5V, 10,000 Cycles 3 = 3.3V � 10%, 10,000 Cycles
Temperature Range Blank = 0�C to + 70�C I= -40�C to +85�C
._____ _ _ Package P = 8-Lead Plastic DIP S = 8-Lead SOIC
Part Mark Convention
X24C01
X - Blank = 8-Lead SOIC P = 8-Lead Plastic DIP
x
L Blank = 5V � 10%, 0�C to + 70�C
I= 5V � 10%, -40�C to +85�C B = 3.5V to 5.5V, 0�C to + 70�C C = 3.5V to 5.5V, -40�C to + 85�C D = 3.3V � 10%, 0�C to + 70�C E = 3.3V �10%, -40�Cto +85�C
10-6
Ordering Information
X24C02: 256 x 8 CMOS Serial E2PROM
X24C02
Device--------'
X X �X
LVccRange Blank= 5V � 10%, 100,000 Cycles 3.5 = 3.5V to 5.5V, 10,000 Cycles 3=3.3V�10%, 10,000 Cycles
Temperature Range
Blank = 0�C to + 70�C I = -40�C to+ 85�C
.____ _ _ Package
P = 8-Lead Plastic DIP 58 = 8-Lead 501C 514 = 14-Lead 501C
Part Mark Convention
X24C02
X - Blank = 8-Lead 501C P = 8-Lead Plastic DIP 5 = 14-Lead 501C
x
L Blank == 5V � 10%, 0�C to + 70�C
I= 5V � 10%, -40�C to +85�C B = 3.5V to 5.5V, 0�c to + 10�c C = 3.5V to 5.5V, -40�C to + 85�C D = 3.3V � 10%, 0�c to + 70�C E = 3.3V �10%, -40�Cto +85�C
10-7
Ordering Information
X24C04: 512 x 8 CMOS Serial E2PROM
X24C04 Device--------'
X X -X
L~~~~~n~~ � 10%, 100,000 Cycles 3.5 = 3.5V to 5.5V, 10,000 Cycles 3 = 3.3V � 10%, 10,000 Cycles
Temperature Range Blank = 0�C to + 70�C
I= -40�C to +85�C
~---Package
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC
Part Mark Convention
X24C04
X - Blank = 8-Lead SOIC P = 8-Lead Plastic DIP S = 14-Lead SOIC
x
L Blank = 5V � 10%, 0�c to + 70�C
I = 5V � 10%, -40�C to +85�C B = 3.5V to 5.5V, 0�C to + 10�c C = 3.5V to 5.5V, -40�C to + 85�C D = 3~3V � 10%, 0�C to+ 70�C E = 3.3V �10%, -40�Cto +85�C
10-8
Ordering Information
X24C 16: 2K x 8 CMOS Serial E2PROM
X24C16
Device ______=r___.
X X -X
L~~~:~"~~ �10% 3.5 = 3.5V to 5.5V 3 = 3.3V �10%
Temperature Range Blank = 0�C to + 70�C I = -40�C to+ 85�C
~---Package
P = 8-Lead Plastic DIP S14 = 14-Lead SOIC
Part Mark Convention
X24C16
X - P = 8-Lead Plastic DIP S = 14-Lead SOIC
x
L Blank = 5V � 10%, 0�c to + ?0�C I= 5V � 10%, -40�C to +85�C B = 3.5V to 5.5V, 0�C to + 70�C C = 3.5V to 5.5V, -40�C to + 85�C D = 3.3V � 10%, 0�c to + ?0�C E = 3.3V � 10%, -40�C to + 85�C
10-9
Ordering Information
X2804A: 512 x 8 E2PROM
X2804A
Device------~
X X -X
1_ Access Time
Blank = 300 ns
-25 = 250 ns -35 = 350 ns -45 = 450 ns
'----Temperature Range Blank = 0�C to + 70�C
I = -40�C to + 85�C
~---Package
P = 24-Lead Plastic DIP D = 24-Lead Cerdip
X2816B: 2K x 8 E2PROM
Device
X2816C: 2K x 8 E2PROM
Device
X2816B
=1
x x -x
LAccess Time Blank = 300 ns -25 = 250 ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to +85�C
~---Package
P = 24-Lead Plastic DIP J = 32-Lead PLCC
D = 24-Lead Cerdip
X2816C
=1
X X -X
T 1_ Access Time
L-20 = 200ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to +85�C
~---Package
P = 24-Lead Plastic DIP J = 32-Lead PLCC
10-10
Ordering Information
X2S64A: SK x S E2PROM
X2864A Device _ _ _ _ _ ____.
X X -X
L Access Time
Blank = 300 ns -25 = 250 ns
-35 = 350 ns -45 = 450 ns
~--Temperature Range Blank = 0�C to + 70�C I= -40�C to +85�C
...__ _ _ Package
P = 28-Lead Plastic DIP D = 28-Lead Cerdip J = 32-Lead PLCC
X2S64B: SK x 8 E2PROM
X2864B Device--------'
X X -X
L Access Time
-12 = 120 ns -15 = 150 ns
-20 = 200 ns
-25 = 250 ns
~--Temperature Range Blank = 0�C to + 70�C I = -40�C to + 85�C
...____ _ _ Package
P = 28-Lead Plastic DIP D = 28-Lead Cerdip J = 32-Lead PLCC
X2864H: SK x 8 E2PROM
X2864H Device--------'
X X -X
LAccess Time -70 = 70 ns -90 = 90 ns
Temperature Range Blank = 0�C to + 70�C I = -40�C to +85�C
.___ _ _ Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
10-11
Ordering Information
X28C64: SK x 8 CMOS E2PROM Device
X28256: 32K x 8 E2PROM Device
X28C256: 32K x 8 CMOS E2PROM Device
X28C64 x x -x L_ Access Time
-12 = 120 ns -15 = 150 ns -20 = 200 ns -25 = 250 ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 28-Lead Plastic DIP D = 28-Lead Cerdip J = 32-Lead PLCC
X28256 x x -x
I
L_ Access Time
-20 = 200 ns
-25 = 250 ns
Blank = 300 ns
-35 = 350 ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 28-Lead Plastic DIP D = 28-Lead Cerdip J = 32-Lead PLCC
X28C256 x x -X L_ Access Time
-15 = 150 ns -20 = 200 ns -25 = 250 ns Blank = 300 ns
Temperature Range
Blank = 0�C to + 70�C I = -40�C to + 85�C
Package P = 28-Lead Plastic DIP D = 28-Lead Cerdip J = 32-Lead PLCC
10-12
Ordering Information
X28C512: 64K x 8 CMOS E2PROM
X28C512
Device------~
X X -X
L ~~c:s~J~~= -15 = 150 ns -20 = 200 ns
Temperature Range Blank = 0�c to + 70�C I = -40�C to +85�C
.____ _ _ Package P = 32-Lead Plastic DIP
D = 32-Lead Cerdip
J = 32-Lead PLCC
X28C010: 128K x 8 CMOS E2PROM
X28C010
Device------~
X X -X
LAccess Time -15 = 150 ns -20 = 200 ns
Temperature Range
Blank = 0�C to + 70�C
I = -40�C to +85�C
~---Package
D = 32-Lead Cerdip
C = 32-Lead Sidebraze
X9MME: E2POT 1K, 10K, SOK, 100K Ohms
x x
LTemperature Range Blank = 0�C to + 70�C I = - 40�C to + 85�C
Package D = 8-Lead Cerdip P = 8-Lead Plastic DIP S = 14-Lead SOIC
,____ _ _ Device X9102 = 1 Kn X9103 = 10 Kn X9503 = 50 Kn X9104 = 100 Kn
10-13
Ordering Information
X88C64: 8K x 8 CMOS Peripheral E2PROM
X88C64
Device------~
X X
LTemperature Range Blank = 0�C to + 70�C I= -40�Cto +85�C
Package
D = 24-Lead Cerdip
P = 24-Lead Plastic DIP
XM28C010: 128K x 8 CMOS E2PROM Memory Module
XM28C010 Device _ _ _ _ _ ____,
X �X
LAccess Time -25 = 250 ns Blank = 300 ns
Temperature Range Blank = 0�C to + 70�C
I = -40�C to + 85�C
XM28C020: 128K x 8 CMOS E2PROM Memory Module
XM28C020 Device--------'
X �X
LAccess Time -25 = 250 ns Blank = 300 ns
Temperature Range Blank = 0�C to + 70�C I= -40�Cto +85�C
10-14
Packaging Information
8�LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
I
1
0.150 (3.80) 0.228 (5.80)
PIN 1 INDEX ,,___________0_.1,5,_8(l4.00) 0.244r.20)
~ ~ 0.014 (0.35)
0.019 (0.49)
-- 0.010 (0.25) x 450
0.020 (0.50)
00-50
t-
' 0.027
(0.683)
-lI
__J_
1I- ~
0.0075 (0.19) 0.010(0.25)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
PSE008
10-15
Packaging Information
&..LEAD PLASTIC DUAL IN..LINE PACKAGE TYPE P
0.092 (2.34) DIA. NOM.
PIN 1 INDEX
I
0.255 (6.47) 0.245 (6.22)
_ J _ t::;::t::;::::;::;::::;:::::;:
1- 0.060 ( 1.52) 0.020(0.51)
j 0
.015 (0.3 MAX.
8)
l
_
-
-
-
0- 0..33~- 2~5~~(-8!..26-~5~).
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
PPI008
10-16
Packaging Information
8-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
~ 0.055 ( 1.40)
0.044 ( 1.12)
-l t::::;::=\:::::;:::;::::::::;:::;::::::::r=;:::::I 0.200 (5 .08)
SEATING PLANE
0.200 (5.08) 0.125 (3.18)
-i 0.110 (2.79)
0.090 (2.29) TYP. 0.100 (2.54)
0.140 (3.56)
j
L
o.060c1.52) 0.015 (0.38)
j I
1--
0.070 (1.78)
-- 0.030 (0,76) TYP. 0.060 (1.52)
0.023 (0.58)
-- 0.014 (0.36)
TYP. 0.017 (0.43)
r: ~:~~~ ~~:~~~ j
I;;P.0.311 (7.9; I
TYP. 0.010 (0.25)
HDIOOB
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
10-17
Packaging Information
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPES
I
1
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244r.20)
PIN 1 INDEX IJ------------',l_J
~ ~ 0.014(0.35)
0,019 (0.49)
_ _ l _ .r:==;=:=;::=:;=;:::==;=:;==;;::::::;:=:::::;=;r==;:=;==;:=:;:=1�
0.053 ( 1.35)
t t --~-~0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.010 (0.25)
0
I--- 0.020 (0.50) x 45
-----r __l 0.0075 (0.19)
-1 0~027 (0.683) I 11 --
0.01 o co.2s)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
PSE014
10-18
Packaging Information
18�LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.905 (22.99) i--.----- 0.895(22.73)-----i�1
I
0.255 (6.47)
PIN 1 INDEX 0
0.245 (6.22)
~:::::;::::::::; _ l
PIN 1
.____ _ _ 0.800 ( 2 0 . 3 2 ) - - - REF �
,_ 0.060 (1.52) 0.050 (1.27)
SEATING
! PLANE
0.150 (3.81) 0.125 (3.18)
--i 0.110 (2.79) ,__
0.090 (2.29)
-l ........,.___..,........,......,...._,.......,.---.-1 0. 130 ( 3 .30)
0.120 (3.05)
L 0.020(0.51)
------ 0.062 (1.57) 0.058 ( 1.47)
0.015 (0.38)
--11-- 0.020 (0.51)
0.016 (0.41)
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
PPI018
10-19
Packaging Information
18-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
0.960 (24.38) ------- 0.880(22.35)-----�1
I
0.310 (7.87)
0.220 (5.59)
____....._......_..... _J_
PIN 1
~ O.OB~.03)
------0.800 (20.32)----
REF.
SEATING~-..........PLANE
t 0.200 (5.08)
0.125 (3.18)
--i 0.110(2.79)
1--
0.090 (2.29)
TYP. 0.100 (2.54)
........- - -
10.200 (5.08)
_ _ _ _.........._ .........._, 0.140(3.56)
L 0.060(1.52)
0.070 (1.78) -- 0.0-30-(0-.7~6)
TYP. 0.060 (1.52)
-11-- 0.015 (0.38) 0.023 (0.58)
0.014 (0.36) TYP. 0.018 (0.46)
j 0.325 (8.26)
--- 0.290 (7.37)
TYP. 0.311 (7.9; I
TYP. 0.010 (0.254)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
HDI018
10-20
Packaging Information
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
I
0.550 ( 13.97)
0.535 (13.59)
PIN 1 INDEX ~:;::::;:::;:~:;::;:::;:~:::;:::;:::::;:::;::::;:::;::::;::;:::::;::;:~_J_
.------1.100 (27.94)-------1 REF.
1- 0.080 (2.03) 0.065 (1.65)
--I
j.- 0.110 (2.79)
0.090 (2.29)
._ 0.062 (1.57) 0.058 (1.47)
-i - 0.625 (15.87) LI 0.600 ( 15.24)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
PPI024
10-21
Packaging Information
24-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
._____ 1.290(32.77) ____~�1 r 1.235 (31.37)
I
0.610 (15.49)
0.500 (12.79)
_ __..__._l
PIN 1
----1.100(27.94)---..-i REF.
~ 0.098 (2.49)
0.040 (1.02)
--i 0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
-l ____,_ _ _ _ _ ___., 00..212450 ((53..7526))
L 0.075(1.91)
0.015 (0.38)
1--
0.070 ( 1.78)
.... 0.030 (0.76) TYP. 0.060 (1.52)
-.J 1.... 0.023 (0.53) 0.014 (0.36) TYP. 0.018 (0.46)
j 0.620 (15.75)
- 0.590(14.19)
TYP. 0.614(15.6~ I
TYP. 0.010(0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
HDI024
10-22
Packaging Information
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
I
0.550 ( 13.97)
0.510 (12.95)
PIN 1 INDEX ~======~==~_l
---------1.300 (33.02)-------' REF'.
~ 0.085(2.16)
0.040 (1.02)
--1
j... 0.110(2.79) 0.090 (2.29)
... _0.062 (1.57) ____;;......____:; 0.050 ( 1.27)
j - 0.610(15.49) 0.590 (14.99) .-�
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
PPI028
10-23
Packaging Information
28�LEAD HERMETIC DUAL IN�LINE PACKAGE TYPE D
1.490 (37.85) 1.-�-----1.435(36.45)------�1
I
0.610 (15.49)
0.500 (12.70)
._.....__..__........__ _l_
PIN 1
-----1.300 (33.02)------1 REF.
~ 0.100 (2.54)
0.035 (0.89)
- 0.225 (5.72)
SEATING ~-.....-...,......,.----....--
l PLANE
0.200 (5.08) 0.125 (3.18)
1 _ ___,..._....,......,.._........,.......- 0.140 (3.56)
L 0.060(1.52)
0.015 (0.38)
--i 0.110 (2.79)
0.090 (2.29)
0.070 ( 1.78)
~ -- 0.030 (0.76)
TYP. 0.055 (1.40)
--11-- 0.026 (0.66) 0.014 (0.36) TYP. 0.018 (0.46)
TYP. 0.018 (0.46)
- 0.620(15.75)~
0.590 (14;99)
TYP. 0.614 (15.60)
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
HDI02B
10-24
Packaging Information
32-LEAD SIDE BRAZE PACKAGE TYPE C
I
0.610(15.49)
~N1 ~oa ~0~~~~~~~~~~~~~~~~~~~~~~~~ ~23
PIN 1
1-- 0.10~2.54)
_J__
0.200 (5.08) 0.125(3.18)
t __,
i-- 0.100(2.54)
0.095 (2.41) TYP. 0.100 (2.54)
-
0.070(1.78) -- 0.030 (0.76) TYP. 0.050 (1.27)
0.620(15.75)---j
o.s9o c14.99>:::i., I
l0.225 (5.72) 0.088 (2.24)
l--SEATING PLANE 0.060 ( 1.52)
' I ~ 0.026 (0.66) 0.015 (0.38)
-- 0.014 (0.36) TYP. 0.018 (0.46)
I I I I I
,,I ,,I
TYP. 0.01 o(0.25)~1 1--
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
OCJ032
10-25
Packaging Information
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
- 0.420 ( 10.67)-
0.050 ( 1.27) TYP.
t
_i
-t 0.021 (0.53)
SEATING PLANE-:I: 0.004 LEAD
CO- PLANARITY
Ll I --I -- 0.045 (1.14) x 45�
.____ 0.495 (12.57)
0.485 (12.32) TYP. 0.490 (12.45)
0.453 (11.51)
0.013 (0.33) TYP. 0.017 (0.43)
0.015 (0.38) 0.095 (2.41)
0 060 (1 52) --
.
�
0.140 (3.56)
___,__ 0.447 (11.35)
0.100 (2.45)
TYP. 0.450 (11.43)
TYP. 0.136 (3.45)
0.300 (7.62)
0.048 ( 1.22)
l REF.
-----'-_ _ _ _ _o_.o__,4_2 ( 1.07)
t - ,..,...--.~-"""r'�~-1
t 0.595 ( 15.11)
0.585 (14.86)
ITYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89) TYP. 0.550 (13.97)
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
10-26
PJG032
Packaging Information
32-PIN DUAL-IN-LINE PACKAGE CERAMIC LEADLESS CHIP CARRIERS ON SIDE BRAZED CERAMIC SUBSTRATE
PIN 1 - - - - - - - - - - (14.06.0604:1:1::.0.4106) - - - - - - - - - - - � '
-11- .018 :I: .002 (.46 :I: .05) 1.500 :I: .008
(38.10 :I: .38)
TOL. NON. ACCUM.
I .010t1N .140
'(.25) . (3.56) MIN. .100:1: .005
~ (2.54:1:.13) TYP.
.010+-..000012
(.25~�g;)
~ .soo:1:.010 I
(15.24 :I: .25)--l
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
CEAA32
10-27
Packaging Information
32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
-1~t----- 1.650 ( 41.90) - - - - -.~.1.
PIN 1
I
0.610 (15.49)
0.500 (12.70)
--.---.---~_j_
- - - - - - - 1 . 5 0 ( 38. 10) -----1~1 REF:
I 0.100 (2.54)
... 0.035 (0.89)
+i 0.110 (2.79)
0.090 (2.29)
I+
TYP. 0.018 (0.46)
t 0.225 (5.72)
----.....----..............----........-- .. 0. 140 ( 3. 5 6)
L 0~060 (1.52)
0.070 (1.78) ... 0.030 (0.76) TYP. 0.055 (1.40)
0.015 (0.38)
11 0.026 (0.66)
+I ... 0.014(0.36)
TYP. 0.018 (0.46)
TYP. 0.010(0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
HDI032
10-28
Sales Offices
U.S. Sales Offices
International Sales Offices
Northeast Area Xicor, Inc. 83 Cambridge Street Unit 1D Burlington, Massachusetts 01803 Phone:617/273-2110 Fax: 617/273-3116
Southeast Area Xicor, Inc. 201 Park Place Suite 203 Altamonte Springs Florida 32701 Phone:407/767-8010 Fax:407/767-8912
Mid-Atlantic Area Xicor, Inc. 50 North Street Danbury, Connecticut 06810 Phone:203/743-1701 Fax:203/794-9501
North Central Area Xicor, Inc. 953 North Plum Grove Road Suite D Schaumburg, Illinois 60173 Phone:708/605-1310 Fax: 708/605-1316
South Central Area Xicor, Inc. 9330 Amberton Parkway Suite 137 Dallas, Texas 75243 Phone:214/669-2022 Fax:214/644-5835
Southwest Area Xicor, Inc. 4141 MacArthur Boulevard Suite 205 Newport Beach, California 92660 Phone:714/752-8700 Fax:714/752-8634
Northwest Area Xicor, Inc. 2700 Augustine Drive Suite 219 Santa Clara, California 95054 Phone:408/292-2011 Fax:408/980-9478
Northern Europe Area
Xicor Ltd. Hawkins House 14 Black Bourton Road Carterton Oxford OX8 3QA United Kingdom Phone: (44) 993/844.435 Telex: (851) 838029 Fax: (44) 993/841.029
Southern Europe Area
Xicor GmbH Technopark Neukeferloh Bretonischer Ring 15 D-8011 Grasbrunn bei Muenchen West Germany Phone: (49) 89/461.0080 Telex: (841) 5213883 Fax: (49) 89/460.5472
Xicor Sari 27 Avenue de Fontainebleau 94270 Le Kremlin Bicetre France Phone: (33) 1/46.71.49.00 Telex: (842) 632160 Fax: (33) 1I49.60.03.32
Japan Area
Xicor Japan K.K. Suzuki Building, 4th Floor 1-6-8 Shinjuku, Shinjuku-ku Tokyo 160, Japan Phone: (81) 3/225.2004 Fax: (81) 3/225.2319
Asia/Pacific Area Xicor, Inc. 851 Buckeye Court Milpitas, California 95035 USA Phone: 408/432-8888 TWX: 910-379-0033 Fax: 408/432-0640
( ) = Country Code
10-29
Xicor, Inc. 851 Buckeye Court Milpitas, CA 95035
(408) 432-8888 TWX 910-379-0033 FAX (408) 432-0640
Printed in U.S.A. Stock No. 200-519