6. Reset controller with manual reset switch (SW2) and voltage supervision. 7. Measurement of device current on VDDIO, VDDA, and VDDD using jumpers J6, J8, and J10 respectively. 8. Samtec connector interface (J21 and J22) for connecting to the baseboard CYTVII-B-E-BB. The Traveo II baseboard has the following features: 1.
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CYTVII-B-E-1M-176-CPU Evaluation Board User Guide
CYTVII-B-E-1M-176-CPU
Evaluation Board User Guide
Document Number. 002-22883 Rev. *C
Cypress Semiconductor 198 Champion Court
San Jose, CA 95134-1709 www.cypress.com
Copyrights
Copyrights
© Cypress Semiconductor Corporation, 2018-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device" means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, FRAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Disclaimer of Schematics and Layouts: This material constitutes a reference design. CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO. THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all changes.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
2
Contents
1. Introduction
4
1.1 Precautions and Warnings...........................................................................................4
2. Overview
5
2.1 Functional Overview ....................................................................................................7
3. Operation
8
4. Connections and Settings
10
A. Schematics of CPU Board
17
B. Component Assembly on CPU Board
36
C. Schematics of Base Board
38
D. Component Assembly on Base Board
55
Revision History
57
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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1. Introduction
This user guide provides instructions to use the CYTVII-B-E-1M-176-CPU and CYTVII-B-E-176-SO evaluation boards, collectively referred to as 'CPU board' in this document. This is an evaluation platform for the CYT2B78CABES Traveo II device. The board can be used standalone for basic validation or in combination with the CYTVII-B-E-BB Traveo II baseboard (available separately from Cypress). This document assumes that you will work with the combination (CPU board + baseboard), and provides guidance to use features of the evaluation platform. The Device Port Pin Connections on Baseboard and CPU board schematic used in this document is for CYTVII-B-E-1M-176CPU Rev C and Rev 1.0 boards and CYTVII-B-E-176-SO Rev C and Rev 1.0 boards only.
1.1
Precautions and Warnings
The evaluation board must be handled by qualified personnel who are aware of the capabilities of the boards. You must ensure your own safety arising from electrical hazards and other sources. You must carefully handle the board, which is a delicate PCB, and ensure that it is not subjected to bending or other stresses.
The CPU board is shipped with a 12 V DC power adapter. This adapter can be plugged into the AC mains supply anywhere in the world and is designed to receive 100-240 V AC V @ 50/60 Hz. While powering the board, you must connect only the power adapter supplied with the evaluation board and not any other part.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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2. Overview
Figure 2-1 shows the CYTVII-B-E-176-SO board. Insert a Traveo II device into the IC socket (marked in red) while the evaluation board is powered OFF. Figure 2-1. CYTVII-B-E-176-SO Board
A variant of the CPU board (CYTVII-B-E-1M-176-CPU) is also available, where the Traveo II device is soldered directly onto the PCB. Functionally, the CYTVII-B-E-1M-176-CPU and CYTVII-B-E-176SO boards are identical, except that the device can be easily replaced in the latter. Figure 2-3 shows the CYTVII-B-E-1M-176-CPU mounted on baseboard.
Another variant of the CPU board is available which has 100-pin socket mounted on it. The CPU board referred as a CYTVII-B-E-1M-100-SO board.
The CPU board is meant to be used along with a Traveo II baseboard (CYTVII-B-E-BB). The baseboard brings out all important interface connections such as CAN, LIN, SPI EEPROM, CXPI, and Flexray, and can be used in conjunction with several CPU boards of the Traveo II family. Figure 2-2 shows the baseboard.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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Figure 2-2. Traveo II Base board (CYTVII-B-E-BB)
Overview
Two Samtec connectors on the CPU board and corresponding mating connectors on the baseboard are used to connect signals across the two boards. When put together, the boards appear as shown in Figure 2-3.
Figure 2-3. Combination of CPU Board and TVII Base Board
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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Overview
2.1
Functional Overview
The CPU board has the following features:
1. One Traveo II device, either soldered or mounted on a socket (U4).
2. PMIC to generate the 5 V and 3.3 V output depending on the Jumper J23 selection, which powers the CPU board and the baseboard (if connected).
3. Programming interface (JTAG-20, MiniProg3, SWD, and IDC-20, Mictor trace port) to connect several programming tools such as IAR I-jet, Green Hills GHS, MiniProg.
4. USB-UART interface for terminal logging (J12).
5. One user switch (SW3) and one user LED (LED5) for standalone operation without the baseboard.
6. Reset controller with manual reset switch (SW2) and voltage supervision.
7. Measurement of device current on VDDIO, VDDA, and VDDD using jumpers J6, J8, and J10 respectively.
8. Samtec connector interface (J21 and J22) for connecting to the baseboard CYTVII-B-E-BB.
The Traveo II baseboard has the following features: 1. Six CAN-FD transceivers based on TJA1057GT (Dual connectors P6, P7, P8). 2. Four CAN-FD transceivers based on TJA1145T, with SPI-based transceiver configuration (Dual
connectors P9, P10). 3. Six LIN transceivers based on TJA1021T (Dual connectors (Dual connectors P3, P4, P5). 4. Two Flexray transceivers based on TJA1081TS (Dual connector P2). 5. One CXPI transceiver based on S6BT112A01 (Connector P1). 6. One SPI EEPROM 25LC320A (U9). 7. Five user switches (SW1 through SW5), 10 user LEDs (USER_LED0 through USER_LED9) and
one potentiometer (POT1) for analog input. 8. Pin headers to access all I/Os of the TVII device (when a CPU board is connected to the base-
board). 9. Samtec connector interface (J38 and J84) for connecting to a CPU board.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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3. Operation
This section describes the operation of the CPU board and the baseboard. It is assumed that you have connected the CPU board to the baseboard using the Samtec interface and inserted a TVII device into the IC socket (applicable to SO boards only). The following method can be used to operate the CPU board and the baseboard. 1. For socketed CPU board, ensure that the device is inserted into the socket. Remove the four
screws on the socket using the screwdriver provided in the box and open the socket cover. If the device is not present, place one carefully using a vacuum picker or a pair of tweezers. 2. Ensure that the pin 1 of the device is near the arrow mark (near C14) as shown in Figure 3-1. You must also ensure that the angle of placing the device is such that the pins on all four sides of the LQFP package match well with the socket pins. Align the device slightly if required. Figure 3-1. Orientation of Device when Inserted in Socket
3. Put the socket cover and fix the four screws such that the socket cover tightly sits on the socket base.
4. A 12V wall adapter board is supplied along with the CPU board. Connect the 12 V wall adapter to the barrel connector marked "12V DC" on the CPU board. Connect its plug to a mains socket using one of the four plug adapters provided in the white box (depending on the geographical location and the socket type available).
5. Ensure that jumpers J23 (default 5 V: J23_1 and J23_2), J5, J6, J8, J10 (current measurement jumpers) are inserted on the CPU board. You can select the 3.3 V power rails for CPU board by shorting J23_2 and J23_2 as per their application or hardware setup.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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Operation
6. Turn ON the mains supply to the wall adapter. Turn ON the switch SW1 on the CPU board. The LED labelled PWR should light up.
7. Connect an appropriate programming tool to one of the programming interfaces (J17, J18, J19, J20). Programming tool options are: GHS Trace on J20 IAR I-jet on J18 or J19 MiniProg3 on J19
8. Install the appropriate programming IDE on a PC. The programming IDE (GHS Multi, IAR EWB, CYP, and so on) should be able to detect a device (read the device ID) and to load a firmware HEX file (.sreg) into the device flash successfully. As part of the release package, various firmware examples compiled in several programming IDEs are available. Some examples use specific transceivers on the baseboard.
9. To start with, use the LED blink example provided with the release package to test the functioning of the board.
10. Connect a USB-mini cable to J12 and the other end to a PC. Open Tera Term or your preferred terminal logging application and set the appropriate port and baud rate (typically 115,200 baud, 8, N, 1). Ensure that jumpers J11 and J13 are inserted on the CPU board. Some firmware examples provide data logs from the device or ask for user inputs over the terminal.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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4. Connections and Settings
Ensure that the following jumpers are inserted on the baseboard to use each transceiver on the baseboard with respective firmware examples which activate each functionality of the device.
1. CAN0.0 from the device uses the CAN0 and CAN6 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard. (connect jumpers J70, J71, J72 for CAN0 and J94, J109, J110, J105, J104, J106 and J103 for CAN6)
2. CAN0.1 from the device uses the CAN1 and CAN7 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard.(connect jumpers J66, J67, J68 for CAN1 and J97, J95, J101, J96, J98, J99 and J100 for CAN7)
3. CAN0.2 from the device uses the CAN2 and CAN8 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard.(connect jumpers J81, J82, J83 for CAN2 and J111, J112, J113, J115, J116, J118 and J117 for CAN8)
4. CAN1.0 from the device uses the CAN3 and CAN9 transceiver on the baseboard. These transceivers are selectable through jumpers on baseboard.(connect jumpers J76, J77, J78 for CAN3 and J114, J131, J125, J121, J122, J123 and J124 for CAN9)
5. CAN1.1 from the device uses the CAN4 transceiver on the baseboard (connect jumpers J91, J92, J93)
6. CAN1.2 from the device uses the CAN5 transceiver on the baseboard (connect jumpers J86, J87, J88)
7. LIN0 from the device uses the LIN0 transceiver on the baseboard (connect jumpers J58, J59, J60, J63)
8. LIN1 from the device uses the LIN1 transceiver on the baseboard (connect jumpers J51, J52, J53, J56)
9. LIN2 from the device uses the LIN2 transceiver on the baseboard (connect jumpers J37, J39, J40, J43)
10. LIN3 from the device uses the LIN3 transceiver on the baseboard (connect jumpers J30, J31, J32, J35)
11. LIN4 from the device uses the LIN4 transceiver on the baseboard (connect jumpers J22, J23, J24, J27)
12. LIN6 from the device uses the LIN5 transceiver on the baseboard (connect jumpers J10, J16, J17, J20)
13. EEPROM on the baseboard is enabled by connecting jumpers J47, J48, J49.
14. The user switch functionality is enabled by connecting jumper J102.
15. The potentiometer functionality is enabled by connecting jumper J89.
In addition, power is supplied to the baseboard by connecting jumper J80 in the '5V' position and must always be connected. Once a specific functionality is chosen by connecting the jumpers listed above, ensure that the appropriate firmware is loaded onto the device. Incorrect firmware can result in port pins being configured incorrectly leading to bus contention and damage to hardware. For example, if you connect jumpers related to CAN0.0, you must ensure that firmware configures the related ports as CAN pins. Contact Cypress technical support for firmware examples.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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Connections and Settings
Apart from these interface transceivers that can be used for specific functions, all pins of the device are also accessible on the baseboard using pin headers JP1 through JP12.
The device port pins are connected to pin headers on the baseboard as listed in Table 4-1. Table 4-1. Device Port Pin Connections on Baseboard
Port Pin
Pin Function
Access Pin on
Baseboard
P0.0
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO/ LIN1_RX
JP6.15
P0.1
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI/ LIN1_TX
JP6.14
P0.2
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/ LIN1_EN/CAN0_1_TX
JP6.9
P0.3
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX
JP6.8
P1.0 PWM_12/PWM_13_N/TC_12_TR0/TC_13_TR1/SCB0_SCL/SCB0_MISO
JP8.4
P1.1 PWM_11/PWM_12_N/TC_11_TR0/TC_12_TR1/SCB0_SDA/SCB0_MOSI
JP8.3
P1.2 PWM_10/PWM_11_N/TC_10_TR0/TC_11_TR1/SCB0_CLK/TRIG_IN[0]
JP8.6
P1.3 PWM_8/PWM_10_N/TC_8_TR0/TC_10_TR1/SCB0_SEL0/TRIG_IN[1]
JP8.5
P10.0
PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/SCB4_RX/SCB4_MISO/ TRIG_IN[18]
JP9.16
P10.1
PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ TRIG_IN[19]
JP9.15
P10.2 PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK JP6.13
P10.3 PWM_31/PWM_30_N/TC_31_TR0/TC_30_TR1/SCB4_CTS/SCB4_SEL0
JP6.16
P10.4 PWM_32/PWM_31_N/TC_32_TR0/TC_31_TR1/SCB4_SEL1/ADC[1]_0
JP6.17
P10.5 PWM_33/PWM_32_N/TC_33_TR0/TC_32_TR1/SCB4_SEL2/ADC[1]_1
JP1.7
P10.6 PWM_34/PWM_33_N/TC_34_TR0/TC_33_TR1/ADC[1]_2
JP1.8
P10.7 PWM_35/PWM_34_N/TC_35_TR0/TC_34_TR1/ADC[1]_3
JP1.13
P11.0 ADC[0]_M
JP9.6
P11.1 ADC[1]_M
JP9.5
P11.2 ADC[2]_M
JP9.8
P12.0 PWM_36/PWM_35_N/TC_36_TR0/TC_35_TR1/CAN0_2_TX/TRIG_IN[20]/ADC[1]_4 JP10.8
P12.1
PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/LIN6_EN/CAN0_2_RX/TRIG_IN[21]/ ADC[1]_5
JP10.7
P12.2
PWM_38/PWM_37_N/TC_38_TR0/TC_37_TR1/EXT_MUX[1]_EN/LIN6_RX/ ADC[1]_6
JP1.9
P12.3 PWM_39/PWM_38_N/TC_39_TR0/TC_38_TR1/EXT_MUX[1]_0/LIN6_TX/ADC[1]_7 JP1.10
P12.4 PWM_40/PWM_39_N/TC_40_TR0/TC_39_TR1/EXT_MUX[1]_1/ADC[1]_8
JP10.13
P12.5 PWM_41/PWM_40_N/TC_41_TR0/TC_40_TR1/EXT_MUX[1]_2/ADC[1]_9
JP1.14
P12.6 PWM_42/PWM_41_N/TC_42_TR0/TC_41_TR1/ADC[1]_10
JP2.18
P12.7 PWM_43/PWM_42_N/TC_43_TR0/TC_42_TR1/ADC[1]_11
JP2.17
P13.0
PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/EXT_MUX[2]_0/SCB3_RX/ SCB3_MISO/ADC[1]_12
JP10.4
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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Connections and Settings
Table 4-1. Device Port Pin Connections on Baseboard (continued)
Port Pin
Pin Function
Access Pin on
Baseboard
P13.1
PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/EXT_MUX[2]_1/SCB3_TX/ SCB3_SDA/SCB3_MOSI/ADC[1]_13
JP10.3
P13.2
PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/ SCB3_SCL/SCB3_CLK/ADC[1]_14
JP10.16
P13.3
PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS/ SCB3_SEL0/ADC[1]_15
JP1.5
P13.4 PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/SCB3_SEL1/ADC[1]_16
JP6.4
P13.5 PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/SCB3_SEL2/ADC[1]_17
JP2.7
P13.6
PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/SCB3_SEL3/TRIG_IN[22]/ ADC[1]_18
JP2.11
P13.7 PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/TRIG_IN[23]/ADC[1]_19
JP2.15
P14.0
PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/SCB2_RX/SCB2_MISO/ CAN1_0_TX/ADC[1]_20
JP3.12
P14.1
PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/SCB2_TX/SCB2_SDA/SCB2_MOSI/ CAN1_0_RX/ADC[1]_21
JP3.14
P14.2
PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/SCB2_RTS/SCB2_SCL/SCB2_CLK/ LIN6_RX/ADC[1]_22
JP1.11
P14.3
PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/SCB2_CTS/SCB2_SEL0/LIN6_TX/ ADC[1]_23
JP7.8
P14.4 PWM_52/PWM_51_N/TC_52_TR0/TC_51_TR1/SCB2_SEL1/LIN6_EN/ADC[1]_24 JP7.12
P14.5 PWM_53/PWM_52_N/TC_53_TR0/TC_52_TR1/SCB2_SEL2/ADC[1]_25
JP7.16
P14.6 PWM_54/PWM_53_N/TC_54_TR0/TC_53_TR1/TRIG_IN[24]/ADC[1]_26
JP7.17
P14.7 PWM_55/PWM_54_N/TC_55_TR0/TC_54_TR1/TRIG_IN[25]/ADC[1]_27
JP3.3
P15.0 PWM_56/PWM_55_N/TC_56_TR0/TC_55_TR1/ADC[1]_28
JP3.5
P15.1 PWM_57/PWM_56_N/TC_57_TR0/TC_56_TR1/ADC[1]_29
JP3.7
P15.2 PWM_58/PWM_57_N/TC_58_TR0/TC_57_TR1/ADC[1]_30
JP3.9
P15.3 PWM_59/PWM_58_N/TC_59_TR0/TC_58_TR1/ADC[1]_31
JP3.11
P16.0 PWM_60/PWM_59_N/TC_60_TR0/TC_59_TR1/PWM_H_0
JP3.13
P16.1 PWM_61/PWM_60_N/TC_61_TR0/TC_60_TR1/PWM_H_0_N
JP3.15
P16.2 PWM_62/PWM_61_N/TC_62_TR0/TC_61_TR1/PWM_H_1
JP3.17
P16.3 PWM_62/PWM_62_N/TC_62_TR0/TC_62_TR1/PWM_H_1_N
JP4.3
P17.0 PWM_61/PWM_62_N/TC_61_TR0/TC_62_TR1/CAN1_1_TX
JP11.8
P17.1
PWM_60/PWM_61_N/TC_60_TR0/TC_61_TR1/PWM_H_2/SCB3_RX/SCB3_MISO/ CAN1_1_RX
JP11.7
P17.2
PWM_59/PWM_60_N/TC_59_TR0/TC_60_TR1/PWM_H_2_N/SCB3_TX/ SCB3_SDA/SCB3_MOSI
JP2.3
P17.3
PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/ SCB3_CLK/TRIG_IN[26]
JP4.5
P17.4
PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]
JP4.11
P17.5 PWM_56/PWM_57_N/TC_56_TR0/TC_57_TR1/SCB3_SEL1
JP3.10
P17.6 PWM_M_4/PWM_56_N/TC_M_4_TR0/TC_56_TR1/SCB3_SEL2
JP3.8
P17.7 PWM_M_5/PWM_M_4_N/TC_M_5_TR0/TC_M_4_TR1
JP3.6
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
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Connections and Settings
Table 4-1. Device Port Pin Connections on Baseboard (continued)
Port Pin
Pin Function
Access Pin on
Baseboard
P18.0
PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/PWM_H_0/SCB1_RX/ SCB1_MISO/FAULT_OUT_0/ADC[2]_0
JP3.18
P18.1
PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/PWM_H_0_N/SCB1_TX/ SCB1_SDA/SCB1_MOSI/
FAULT_OUT_1/ADC[2]_1
JP3.16
P18.2
PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/PWM_H_1/SCB1_RTS/ SCB1_SCL/SCB1_CLK/ADC[2]_2
JP9.17
P18.3
PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3
JP4.4
P18.4
PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4
JP9.18
P18.5
PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/ TRACE_DATA_1/ADC[2]_5
JP12.4
P18.6
PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/PWM_H_3/SCB1_SEL3/ CAN1_2_TX/TRACE_DATA_2/ADC[2]_6
JP11.6
P18.7
PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/PWM_H_3_N/CAN1_2_RX/ TRACE_DATA_3/ADC[2]_7
JP11.5
P19.0
PWM_M_3/PWM_50_N/TC_M_3_TR0/TC_50_TR1/TC_H_0_TR0/SCB2_RX/ SCB2_MISO/FAULT_OUT_2
JP7.9
P19.1
PWM_26/PWM_M_3_N/TC_26_TR0/TC_M_3_TR1/TC_H_0_TR1/SCB2_TX/ SCB2_SDA/SCB2_MOSI/FAULT_OUT_3
JP7.13
P19.2
PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/TC_H_1_TR0/SCB2_RTS/ SCB2_SCL/SCB2_CLK/TRIG_IN[28]
JP6.5
P19.3
PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/TC_H_1_TR1/SCB2_CTS/SCB2_SEL0/TRIG_IN[29]
JP6.10
P19.4 PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/TC_H_2_TR0/SCB2_SEL1
JP3.4
P20.0 PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/TC_H_2_TR1/SCB2_SEL2/LIN5_RX JP7.4
P20.1 PWM_49/PWM_30_N/TC_49_TR0/TC_30_TR1/TC_H_3_TR0/LIN5_TX
JP7.5
P20.2 PWM_48/PWM_49_N/TC_48_TR0/TC_49_TR1/TC_H_3_TR1/LIN5_EN
JP4.14
P20.3
PWM_47/PWM_48_N/TC_47_TR0/TC_48_TR1/SCB1_RX/SCB1_MISO/ CAN1_2_TX
JP4.15
P20.4
PWM_46/PWM_47_N/TC_46_TR0/TC_47_TR1/SCB1_TX/SCB1_SDA/SCB1_MOSI/ CAN1_2_RX
JP5.8
P20.5 PWM_45/PWM_46_N/TC_45_TR0/TC_46_TR1/SCB1_RTS/SCB1_SCL/SCB1_CLK JP5.9
P20.6 PWM_44/PWM_45_N/TC_44_TR0/TC_45_TR1/SCB1_CTS/SCB1_SEL0
JP5.7
P20.7 PWM_43/PWM_44_N/TC_43_TR0/TC_44_TR1/SCB1_SEL1
JP5.6
P2.0
PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/SCB7_RX/SCB0_SEL1/SCB7_MISO/ LIN0_RX/CAN0_0_TX/ SWJ_TRSTN/TRIG_IN[2]
#NA
P2.1
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA/SCB0_SEL2/ SCB7_MOSI/LIN0_TX/ CAN0_0_RX/TRIG_IN[3]
JP1.4
P2.2
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL/SCB0_SEL3/ SCB7_CLK/LIN0_EN/TRIG_IN[4]
JP1.6
P2.3
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/LIN5_RX/ TRIG_IN[5]
JP10.11
P2.4 PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/SCB7_SEL1/LIN5_TX/TRIG_IN[6]
JP8.8
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
13
Connections and Settings
Table 4-1. Device Port Pin Connections on Baseboard (continued)
Port Pin
Pin Function
Access Pin on
Baseboard
P2.5 PWM_2/PWM_3_N/TC_2_TR0/TC_3_TR1/SCB7_SEL2/LIN5_EN/TRIG_IN[7]
JP8.7
P21.0 PWM_42/PWM_43_N/TC_42_TR0/TC_43_TR1/SCB1_SEL2/WCO_IN
#N/A
P21.1 PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT
#N/A
P21.2 PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN #N/A
P21.3 PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT
#N/A
P21.4 PWM_38/PWM_39_N/TC_38_TR0/TC_39_TR1/HIBERNATE_WAKEUP[0]
JP5.5
P21.5 PWM_37/PWM_38_N/TC_37_TR0/TC_38_TR1/LIN0_RX
JP1.3
P21.6 PWM_36/PWM_37_N/TC_36_TR0/TC_37_TR1/LIN0_TX
JP5.10
P21.7 PWM_35/PWM_36_N/TC_35_TR0/TC_36_TR1/LIN0_EN/CAL_SUP_NZ/RTC_CAL JP5.18
P22.0
PWM_34/PWM_35_N/TC_34_TR0/TC_35_TR1/SCB6_RX/SCB6_MISO/ CAN1_1_TX/TRACE_DATA_0
JP4.6
P22.1
PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/ CAN1_1_RX/TRACE_DATA_1
JP4.8
P22.2
PWM_32/PWM_33_N/TC_32_TR0/TC_33_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK/ TRACE_DATA_2
JP4.10
P22.3
PWM_31/PWM_32_N/TC_31_TR0/TC_32_TR1/SCB6_CTS/SCB6_SEL0/TRACE_DATA_3
JP4.12
P22.4 PWM_30/PWM_31_N/TC_30_TR0/TC_31_TR1/SCB6_SEL1/TRACE_CLOCK
JP5.11
P22.5 PWM_29/PWM_30_N/TC_29_TR0/TC_30_TR1/SCB6_SEL2/LIN7_RX
JP5.12
P22.6 PWM_28/PWM_29_N/TC_28_TR0/TC_29_TR1/LIN7_TX
JP5.13
P22.7 PWM_27/PWM_28_N/TC_27_TR0/TC_28_TR1/LIN7_EN
JP5.14
P23.0
PWM_M_8/PWM_27_N/TC_M_8_TR0/TC_27_TR1/SCB7_RX/SCB7_MISO/ CAN1_0_TX/FAULT_OUT_0
JP5.15
P23.1
PWM_M_9/PWM_M_8_N/TC_M_9_TR0/TC_M_8_TR1/SCB7_TX/SCB7_SDA/ SCB7_MOSI/CAN1_0_RX/FAULT_OUT_1
JP5.16
P23.2
PWM_M_10/PWM_M_9_N/TC_M_10_TR0/TC_M_9_TR1/SCB7_RTS/SCB7_SCL/ SCB7_CLK/FAULT_OUT_2
JP5.17
P23.3
PWM_M_11/PWM_M_10_N/TC_M_11_TR0/TC_M_10_TR1/SCB7_CTS/SCB7_SEL0/FAULT_OUT_3/TRIG_IN[30]
JP7.10
P23.4
PWM_25/PWM_M_11_N/TC_25_TR0/TC_M_11_TR1/SCB7_SEL1/TRIG_DBG[0]/ SWJ_SWO_TDO/TRIG_IN[31]
JP4.7
P23.5 PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SCB7_SEL2/SWJ_SWCLK_TCLK #N/A
P23.6 PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS
#N/A
P23.7
PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/ EXT_CLK/HIBERNATE_WAKEUP[1]
JP4.9
P3.0 PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/SCB6_RX/SCB6_MISO/TRIG_DBG[0] JP10.14
P3.1
PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/ TRIG_DBG[1]
JP11.4
P3.2
PWM_M_3/PWM_0_N/TC_M_3_TR0/TC_0_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK
JP8.10
P3.3 PWM_M_2/PWM_M_3_N/TC_M_2_TR0/TC_M_3_TR1/SCB6_CTS/SCB6_SEL0 JP8.9
P3.4 PWM_M_1/PWM_M_2_N/TC_M_1_TR0/TC_M_2_TR1/SCB6_SEL1
JP8.12
P3.5 PWM_M_0/PWM_M_1_N/TC_M_0_TR0/TC_M_1_TR1/SCB6_SEL2
JP8.11
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
14
Connections and Settings
Table 4-1. Device Port Pin Connections on Baseboard (continued)
Port Pin
Pin Function
Access Pin on
Baseboard
P4.0
PWM_4/PWM_M_0_N/TC_4_TR0/TC_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/ SCB5_MISO/ LIN1_RX/TRIG_IN[10]
JP8.14
P4.1
PWM_5/PWM_4_N/TC_5_TR0/TC_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/ SCB5_MOSI/LIN1_TX/TRIG_IN[11]
JP8.13
P4.2
PWM_6/PWM_5_N/TC_6_TR0/TC_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/ SCB5_CLK/LIN1_EN/TRIG_IN[12]
JP8.16
P4.3
PWM_7/PWM_6_N/TC_7_TR0/TC_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/ CAN0_1_TX/TRIG_IN[13]
JP8.15
P4.4 PWM_8/PWM_7_N/TC_8_TR0/TC_7_TR1/SCB5_SEL1/CAN0_1_RX
JP8.18
P5.0 PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2/LIN7_RX
JP11.3
P5.1 PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/LIN7_TX
JP10.15
P5.2 PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1/LIN7_EN
JP10.18
P5.3 PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1/LIN2_RX
JP2.5
P5.4 PWM_13/PWM_12_N/TC_13_TR0/TC_12_TR1/LIN2_TX
JP8.17
P5.5 PWM_14/PWM_13_N/TC_14_TR0/TC_13_TR1/LIN2_EN
JP10.6
P6.0
PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/ LIN3_RX/ADC[0]_0
JP2.9
P6.1
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1
JP2.10
P6.2
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/ CAN0_2_TX/ADC[0]_2
#NA
P6.3
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/ CAN0_2_RX/ CAL_SUP_NZ/ADC[0]_3
#NA
P6.4 PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4 JP2.14
P6.5 PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5 JP2.16
P6.6 PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6 JP10.5
P6.7 PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7
JP11.11
P7.0
PWM_M_4/PWM_3_N/TC_M_4_TR0/TC_3_TR1/SCB5_RX/SCB5_MISO/LIN4_RX/ ADC[0]_8
JP12.3
P7.1
PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9
JP12.6
P7.2
PWM_M_5/PWM_15_N/TC_M_5_TR0/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ADC[0]_10
JP12.5
P7.3
PWM_16/PWM_M_5_N/TC_16_TR0/TC_M_5_TR1/SCB5_CTS/SCB5_SEL0/ ADC[0]_11
JP10.10
P7.4 PWM_M_6/PWM_16_N/TC_M_6_TR0/TC_16_TR1/SCB5_SEL1/ADC[0]_12
JP10.9
P7.5 PWM_17/PWM_M_6_N/TC_17_TR0/TC_M_6_TR1/SCB5_SEL2/ADC[0]_13
JP10.12
P7.6 PWM_M_7/PWM_17_N/TC_M_7_TR0/TC_17_TR1/TRIG_IN[16]/ADC[0]_14
JP11.12
P7.7 PWM_18/PWM_M_7_N/TC_18_TR0/TC_M_7_TR1/TRIG_IN[17]/ADC[0]_15
JP11.9
P8.0 PWM_19/PWM_18_N/TC_19_TR0/TC_18_TR1/LIN2_RX/CAN0_0_TX
JP6.12
P8.1
PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/ ADC[0]_16
JP6.11
P8.2 PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17 JP2.8
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
15
Connections and Settings
Table 4-1. Device Port Pin Connections on Baseboard (continued)
Port Pin
Pin Function
P8.3 PWM_22/PWM_21_N/TC_22_TR0/TC_21_TR1/TRIG_DBG[0]/ADC[0]_18 P8.4 PWM_23/PWM_22_N/TC_23_TR0/TC_22_TR1/TRIG_DBG[1]/ADC[0]_19 P9.0 PWM_24/PWM_23_N/TC_24_TR0/TC_23_TR1/ADC[0]_20 P9.1 PWM_25/PWM_24_N/TC_25_TR0/TC_24_TR1/ADC[0]_21 P9.2 PWM_26/PWM_25_N/TC_26_TR0/TC_25_TR1/ADC[0]_22 P9.3 PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/ADC[0]_23 VCCD VCCD VDDA VDDA VDDD VDDD VDDIO VDDIO VREFH VREFH VREFL VREFL VSSA VSSA / VSSD / VSSIO/ Ground XRES XRES
Access Pin on
Baseboard JP11.10 JP9.9 JP9.12 JP9.11 JP9.14 JP9.13 #NA JP1.17 JP1.15 JP1.16 #NA #NA JP1.19 JP12.16
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
16
A. Schematics of CPU Board
This appendix contains the schematics of TVII-B-E-1M board.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
17
Figure A-1. Block Diagram of CPU Board
5
4
3
2
SYSTEM ARCHITECTURE
D
BOARD TO BOARD CONNECTOR-1
(180 PIN SAMTEC CONNECTOR)
Schematics of CPU Board
1
D
POWER SUPPLY
(PMIC 5V OUTPUT) C (LDO 3V3 OUTPUT)
PROGRAM/DEBUG INTERFACE
(JTAG,SWD,ETM)
B
A
5
TVII-B-E-1M-B0 DEVICE
BOARD TO BOARD CONNECTOR-2
(180 PIN SAMTEC CONNECTOR)
4
3
USB TO UART TRANSCEIVER
(Data Only)
C
RESET CONTROLLER
WITH RESET BUTTON
GPIO B 1 I/O SWITCH 1 I/O LED
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :BLOCK DIAGRAM
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
SPPD
Date: 2
Monday, April 01, 2019
Sheet
2 o f 20
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
18
Figure A-2. Power Architecture
5
4
POWER ARCHITECTURE
D
12V POWER INPUT
VCC_12V
Schematics of CPU Board
3
2
1
D
BOARD TO BOARD CONNECTOR-2
C B A
5
PMIC(5V,1A) VCC
4
BOARD TO BOARD CONNECTOR-1
C
TRAVEO II MCU
UART TO USB CONVERTER
USB_VIN USB CONNECTOR
B
DEBUG INTERFACE
ARM ETM MICTOR, ARM STANDARD JTAG, CORTEX DEBUG + ETM, CORTEX DEBUG
RESET CONTROLLER
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :POWER ARCHITECTURE
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
SPPD
Date: Monday, April 01, 2019 2
Sheet
3 o f 20
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
19
Figure A-3. 5V Power Input
5
4
3
2
12V POWER INPUT
D
J3 1 3 2
CON_PWRJACK3_RAPC722
VCC12V_EXT
1
SW1 2
F1
1
2
1.6A
500SSP1S2M2QEA
D2
FUSE_122V
1
B120-13
1
ZENER_12V
D3 SMAJ12CA
C25
+
C24
C23
100uF_25V 47uF 1uF
FL2 1
4A 30E VCC_12V TP4
2
BLM21PG300SH1D
THRU HOLE
C22 0.1uF
C21 0.1uF
3
2
C
Schematics of CPU Board
1
D
HDR_1X2 HDR_1X2 HDR_1X2
J16
J1
J2
2 1 2 1 2 1
TP8 5002
C
12V to 5V PMIC
VCC_12V
VCC_12V
VCCOUT
B VCC_PMIC
R15 DNI 0E
C18 10uF
C60 0.1uF
MODE
U1 3 PVIN
6 ENA
7 MODE
SYNC 11 SYNC
R13 R5
RT R3
12 RT
PGND1 PGND2
VIN 5
C10 0.1uF
C3 4.7uF
VCC 8
VOUT 14
FB 13
BST 4
LX1 LX2
2 15
PG 10
C6 BST
LX1 L1 LX2
PG R4
0.1uF 2.2uH
1M_1%
S6BP201A1AST2B000
17 EP
9 GND
1 16
A
0E
0E
22K
VCC_PMIC
C2 22uF
C1 22uF
VCC_PMIC
5
4
3
B
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :5V POWER INPUT
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
SPPD
Date: Monday, April 01, 2019
Sheet
4 o f 20
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
20
Schematics of CPU Board
Figure A-4. 3V3 LDO Regulator
5
4
3
2
1
D
D
3V3 LDO REGULATOR
C
C
VCC_12V
VCC_PMIC VCC VCC_LDO
U12
VCC_LDO
J23
C61 10 uF
3 IN
OUT 2
1 GND
NCP1117DT33T5G
C62 22 uF
C64 0.1uF
1 2 3
3 Pin Jumper
B
B
VCC
LD2
2
1
TP5
LTST-C150GKT
THRU HOLE
LED5V R21
220E
A
5
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :3V3 LDO REGULATOR
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
SPPD
Date: 2
Monday, April 01, 2019
Sheet
5 o f 20
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
21
Figure A-5. Debug Interface
Schematics of CPU Board
5
DEBUG INTERFACE
CORTEX DEBUG
D VCC
C47 0.1uF
J19
1 3 5 7 9
2 SWDIO_TMS 4 SWCLK_TCLK 6 SWO_TDO 8 SWDOE_TDI 10 NRST_CORTEX10
CON_BOX_2X5_M
C
4
SRST_MICTOR SWO_TDO SWCLK_TCLK SWDIO_TMS SWDOE_TDI TRSTN
3 VCC
R83 R75 R89 R77 R74 R73 DNI DNI DNI 10K 10K 10K 10K 10K 10K
R88 R85 R91 R78 R86 R84 DNI DNI DNI DNI DNI DNI 10K 10K 10K 10K 10K 10K
2
ARM ETM MICTOR
R76 DNI 0E
R87
20E
J17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
R72
39 40 41 42 43
10K CON_MICTOR_2X19_F
1
R57
20E TRACE_CLOCK
VCC
R59
0E
R58
0E
R63 R55
TRACE_DATA_3 TRACE_DATA_2 TRACE_DATA_1
VCC
10K TRACE_CTL TRACE_DATA_0
10K
D C45 0.1uF
TP9 THRU HOLE
C
ARM STANDARD JTAG VCC
TRSTN
SWDOE_TDI
B
SWDIO_TMS
SWCLK_TCLK
SWO_TDO SRST_IDC20
R61 C46
R64
0.1uF
J20
0E
0E
1
2
3
4
5
6
7
8
R51
20E
9
10
11
12
13
14
15
16
17
18
19
20
R81 R82
CON_BOX_2X10_M
10K 10K
A
SRST_IDC20
R79
0E CPU_XRES {6,7,14,18}
R80
0E TRSTN
DNI
NRST_CORTEX20 R70
0E CPU_XRES {6,7,14,18}
R69
0E TRSTN
DNI
5
4
VCC CORTEX DEBUG + ETM
C48 0.1uF
J18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NRST_CORTEX20
CON_BOX_2X10_M
SWDIO_TMS {14,19} SWCLK_TCLK {14,19} SWO_TDO {14,19} SWDOE_TDI {14,19}
TRACE_CLOCK {13,19} TRACE_DATA_0 {14,19} TRACE_DATA_1 {14,19} TRACE_DATA_2 {14,19} TRACE_DATA_3 {14,19}
TRSTN
LTST-C150GKT
1
2
VCC R49 220E LD6 B
NRST_CORTEX10 R67
0E
R68
0E
DNI
CPU_XRES {6,7,14,18} TRSTN {9,19}
SRST_MICTOR
R92
0E CPU_XRES {6,7,14,18}
R90
0E TRSTN
DNI
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :DEBUG INTERFACE
Size Document Number
A4
6239956
Drawn By
VJYM
Date: Monday, April 01, 2019 2
Approved By
SPPD
Sheet
6 o f 20
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
22
Figure A-6. UART to USB & RESERT
Schematics of CPU Board
5
4
3
2
1
USB TO UART TRANSCEIVER
VCC
OVERLAP THE VCCIO_USB PADS OF R25 & R26
R25
DNI VCCIO_USB
VCC_USB
FL4
600E
USB_VIN
0E
D
R26
0E
1
2
D
DEFAULT CLOSE
C26
C27
C28 C29
C34
HDR_1X2
4.7uF 0.1uF
0.1uF 4.7uF
10000pF
{12,16} UART_SCB3_RX {12,16} UART_SCB3_TX
C
VCCIO_USB
R30
J11
1
2
R23
1K
1
2
J13
HDR_1X2 DEFAULT CLOSE
R98
0E
R27
0E
R99
0E
DNI
R97
0E
DNI
TXD RXD
CTS RTS
DTR DSR
U5
1 5
TXD RXD
11 3
CTS# RTS#
2 9
DTR# DSR#
DCD 10 DCD#
RI
6 RI#
VCCIO 4 VCC 20
USBDP USBDM
15 16
USBDP USBDM
USBDM 1 USBDP 4
L2
2
90E 3 VCCIO_USB
USBDM_CONN USBDP_CONN
J12
CON_MUSB-B_5_F
1 2 3 4 5
VBUS D- SH1 D+ SH2 ID GND
SH1 SH2
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
23 22 13 14 12 8 27 28
TXLED 1LD3 RXLED
1LD4
LTST-C150GKT 2 R22
LTST-C150GKT 2 R24 TP6
THRU HOLE
220E 220E
1
FL3 C
600E
2
DNI
4.7K RST_UART
R31
DNI
7 18 21
RST_UART
R28
0E
DNI
19 RESET# 26 DNU
GND GND GND
VCCD 17
VCCD
NC1 NC2
24 25
CY7C65213-28PVXI
C30
R29
0E
DNI
1uF
10K
RESET CONTROLLER
B VCC
SW2
VCC R14
PLACE NEAR SENSE PIN
C11 1000pF
U2
5 6
C7 PLACE NEAR VCC VDD PIN
0.1uF R9
DEFAULT CLOSE J9
HDR_1X2
2
4
SENSE VDD
RST_SWR20
10K
VCC
100E_1%
RST_MR
RST_MR3 MR
C13
R19 22K
CT 4 CT
RESET 1
1
10K RST_OUT
2 1
CPU_XRES {6,14,18}
LTST-C150GKT
2 GND
1
3
A
SD05C-01FTG
D1 2
1
0.1uF
C15 DNI
0.1uF
TPS3808G50DBVT
2
LD1 R8
220E
VCC
5
4
3
B
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :UART TO USB & RESET
Size Document Number
A4
6239956
Drawn By
VJYM
Date: Monday, April 01, 2019 2
Approved By
Rev
SPPD
C
Sheet
7 o f 20
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
23
Figure A-7. GPIO, Clock, and Filter
5
4
RC FILTER
{11} GPIO_038
D
TPS5
R39
0E
C40 DNI
0.1uF
GPIO_082 {16}
{11} GPIO_040
3 TPS7
R44
0E
C42 DNI
0.1uF
GPIO_084 {16}
Schematics of CPU Board
2
1
TPS4
{11} BB_CAN2_TXD_N
R40
0E
BB_CAN2_TXD {16}
C43 DNI
0.1uF
D
{11} GPIO_039
R45
C41 DNI
0.1uF
TPS6
0E
GPIO_083 {16}
TPS3
{11,18} BB_CAN2_RXD_N
R32
0E
C38 DNI
0.1uF
BB_CAN2_RXD {16}
C
C
The return path from Capacitor, must be wired to the VSSA
ECO & WCO
C9 10pF 4
C8 10pF
1
3
ECI/BTB {8,14} Y2
2 16.000MHz
ECO/BTB {8,14}
B
{8,14} WCI/BTB {8,14} WCO/BTB
C4 12pF
2
Y1
3
1
4
32.768KHz
C5 12pF
{8,14} ECI/BTB
Damping resistor, need to be tuned
R16 DNI 0E
J7
2
3
1
4
5
CON_MCXJACK5_F
{8,14} WCO/BTB TPS1
{8,14} WCI/BTB
{8,14} ECI/BTB {8,14} ECO/BTB
R11 DNI 0E R12 DNI 0E R18 DNI 0E R17 DNI 0E
CPU_WCO_IN {18} CPU_WCO_OUT {18} CPU_ECO_IN {18} CPU_ECO_OUT {18}
B
TPS2
4
PUSH BUTTON
SW3
2
VCC R47
DEFAULT CLOSE HDR_1X2
J14
USER LED
DEFAULT CLOSE HDR_1X2
2 1
R48
20E 10K GPIO_SW
J15
LD5
2 1
A
C44
GPIO_018 {10,16,19} {10,16,19} GPIO_023
GPIO_LED
2
1 R46
1K
1
3
PTS810 SJG 250 SMTR LFS
0.1uF
LTST-C150GKT
5
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :GPIO,CLOCK AND FILTER
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
SPPD
Date: 2
Monday, April 01, 2019
Sheet
8 o f 20
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
24
Figure A-8. LQFP-176 P1
5
{18} BB_LIN1_RX
D
{18} BB_LIN1_TX
{17,18} BB_LIN1_SLP
{17,18} BB_CAN1_TXD
{17,18} BB_CAN7_TXD
{17,18} BB_CAN1_RXD
{17,18} BB_CAN7_RXD
{16} GPIO_001
{16} GPIO_002
{16} GPIO_003 {16} GPIO_004
{6,19} TRSTN
{18} BB_LIN0_TX
{18} BB_LIN0_SLP
C
{16} BB_CAN2_S
{16} GPIO_005
{16} GPIO_006
{16} BB_CAN3_S {16} BB_CAN6_WAKE
{16} GPIO_007 {16} GPIO_008
{16} GPIO_009
{16} GPIO_010
{16} GPIO_011
B
{16} GPIO_012
{16} GPIO_013
{16} GPIO_014
{16} GPIO_015
A 5
Schematics of CPU Board
4
3
2
1
U4A
2 P0.0_PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO/LIN1_RX
3 P0.1_PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI/LIN1_TX
D
4 P0.2_PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/LIN1_EN/CAN0_1_TX
5 P0.3_PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/CAN0_1_RX
6 P1.0_PWM_12/PWM_13_N/TC_12_TR0/TC_13_TR1/SCB0_SCL/SCB0_MISO
7 P1.1_PWM_11/PWM_12_N/TC_11_TR0/TC_12_TR1/SCB0_SDA/SCB0_MOSI
8 P1.2_PWM_10/PWM_11_N/TC_10_TR0/TC_11_TR1/SCB0_CLK/TRIG_IN[0]
9 P1.3_PWM_8/PWM_10_N/TC_8_TR0/TC_10_TR1/SCB0_SEL0/TRIG_IN[1]
10 P2.0_PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]
11 P2.1_PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3]
12 P2.2_PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4]
13 P2.3_PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/SCB7_CTS/SCB7_SEL0/LIN5_RX/TRIG_IN[5]
C
14 P2.4_PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/SCB7_SEL1/LIN5_TX/TRIG_IN[6]
15 P2.5_PWM_2/PWM_3_N/TC_2_TR0/TC_3_TR1/SCB7_SEL2/LIN5_EN/TRIG_IN[7]
16 P3.0_PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/SCB6_RX/SCB6_MISO/TRIG_DBG[0]
17 P3.1_PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/TRIG_DBG[1]
18 P3.2_PWM_M_3/PWM_0_N/TC_M_3_TR0/TC_0_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK
19 P3.3_PWM_M_2/PWM_M_3_N/TC_M_2_TR0/TC_M_3_TR1/SCB6_CTS/SCB6_SEL0
20 P3.4_PWM_M_1/PWM_M_2_N/TC_M_1_TR0/TC_M_2_TR1/SCB6_SEL1
21 P3.5_PWM_M_0/PWM_M_1_N/TC_M_0_TR0/TC_M_1_TR1/SCB6_SEL2
24 P4.0_PWM_4/PWM_M_0_N/TC_4_TR0/TC_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/SCB5_MISO/LIN1_RX/TRIG_IN[10]
25 P4.1_PWM_5/PWM_4_N/TC_5_TR0/TC_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN1_TX/TRIG_IN[11]
B
26 P4.2_PWM_6/PWM_5_N/TC_6_TR0/TC_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN1_EN/TRIG_IN[12]
27 P4.3_PWM_7/PWM_6_N/TC_7_TR0/TC_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/CAN0_1_TX/TRIG_IN[13]
28 P4.4_PWM_8/PWM_7_N/TC_8_TR0/TC_7_TR1/SCB5_SEL1/CAN0_1_RX
LQFP_176_1M_B0
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P1
Size Document Number
A4
6239956
Drawn By
VJYM
Approved By
Rev
SPPD
C
Date: Monday, April 01, 2019
Sheet
9 o f 20
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
25
Figure A-9. LQFP-176 P2
5
D
{16} BB_CAN7_WAKE
{17} BB_CAN8_WAKE
{17} BB_CAN9_WAKE
{18} BB_LIN2_RX
{16} GPIO_016 {16} GPIO_017
{19} BB_LIN3_RX
{19} BB_LIN3_TX
{17,19} BB_LIN3_SLP
{17,19} BB_CAN8_TXD
{17,19} BB_LIN4_RX
{17,19} BB_CAN8_RXD
C
{19} BB_LIN4_TX
{8,16,19} BB_LIN4_SLP
{8,16,19} GPIO_018 {16} GPIO_019
{17} GPIO_020
{18} BB_CAN_SPI1_MISO
{18} BB_CAN_SPI1_MOSI {18} BB_CAN_SPI1_CLK
{16} BB_CAN_SPI1_SS0
{16} BB_CAN_SPI1_SS1
{16} BB_CAN_SPI1_SS2
B
{17} GPIO_021
{17} GPIO_022 {17,18} BB_CAN0_TXD {17,18} BB_CAN6_TXD
{17,18} BB_LIN2_TX {17,18} BB_CAN0_RXD {17,18} BB_CAN6_RXD {8,16,19} BB_LIN2_SLP
{8,16,19} GPIO_023
A 5
Schematics of CPU Board
4
3
2
1
U4B
29 P5.0_PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2/LIN7_RX
D
30 P5.1_PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/LIN7_TX
31 P5.2_PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1/LIN7_EN
32 P5.3_PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1/LIN2_RX
33 P5.4_PWM_13/PWM_12_N/TC_13_TR0/TC_12_TR1/LIN2_TX
34 P5.5_PWM_14/PWM_13_N/TC_14_TR0/TC_13_TR1/LIN2_EN
35 P6.0_PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/LIN3_RX/ADC[0]_0
36 P6.1_PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/LIN3_TX/ADC[0]_1
37 P6.2_PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK/LIN3_EN/CAN0_2_TX/ADC[0]_2
38 P6.3_PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SCB4_CTS/SCB4_SEL0/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3
39 P6.4_PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SCB4_SEL1/LIN4_TX/ADC[0]_4
C
40 P6.5_PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SCB4_SEL2/LIN4_EN/ADC[0]_5
41 P6.6_PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6
42 P6.7_PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7
48 P7.0_PWM_M_4/PWM_3_N/TC_M_4_TR0/TC_3_TR1/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_8
49 P7.1_PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_9
50 P7.2_PWM_M_5/PWM_15_N/TC_M_5_TR0/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ADC[0]_10
51 P7.3_PWM_16/PWM_M_5_N/TC_16_TR0/TC_M_5_TR1/SCB5_CTS/SCB5_SEL0/ADC[0]_11
52 P7.4_PWM_M_6/PWM_16_N/TC_M_6_TR0/TC_16_TR1/SCB5_SEL1/ADC[0]_12
53 P7.5_PWM_17/PWM_M_6_N/TC_17_TR0/TC_M_6_TR1/SCB5_SEL2/ADC[0]_13
54 P7.6_PWM_M_7/PWM_17_N/TC_M_7_TR0/TC_17_TR1/TRIG_IN[16]/ADC[0]_14
B
55 P7.7_PWM_18/PWM_M_7_N/TC_18_TR0/TC_M_7_TR1/TRIG_IN[17]/ADC[0]_15
56 P8.0_PWM_19/PWM_18_N/TC_19_TR0/TC_18_TR1/LIN2_RX/CAN0_0_TX
57 P8.1_PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/ADC[0]_16
58 P8.2_PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17
LQFP_176_1M_B0
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P2
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
Rev
SPPD
C
Date: Monday, April 01, 2019
Sheet
10 o f 20
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
26
Figure A-10. LQFP-176 P3
5
{17} GPIO_024
D
{16} GPIO_025
{16} GPIO_026
{16} GPIO_027
{16} GPIO_028
{16} GPIO_029
{16} GPIO_030
{16} GPIO_031
{18} GPIO_032
{18} GPIO_033
{18} GPIO_034
C
{18} GPIO_035
{18} GPIO_036
{18} GPIO_037
{8} GPIO_038
{8} GPIO_039
{8} GPIO_040
{8} BB_CAN2_TXD_N
{8,18} BB_LIN5_SLP {8,18} BB_CAN2_RXD_N
{18} BB_LIN5_RX
{18} BB_LIN5_TX
B
{16} BB_CAN4_S
{16} BB_USER_BUTTON_4 {18} GPIO_041
{19} GPIO_042
{19} GPIO_043
A 5
Schematics of CPU Board
4
3
2
1
U4C
59 P8.3_PWM_22/PWM_21_N/TC_22_TR0/TC_21_TR1/TRIG_DBG[0]/ADC[0]_18
60 P8.4_PWM_23/PWM_22_N/TC_23_TR0/TC_22_TR1/TRIG_DBG[1]/ADC[0]_19
D
61 P9.0_PWM_24/PWM_23_N/TC_24_TR0/TC_23_TR1/ADC[0]_20
62 P9.1_PWM_25/PWM_24_N/TC_25_TR0/TC_24_TR1/ADC[0]_21
63 P9.2_PWM_26/PWM_25_N/TC_26_TR0/TC_25_TR1/ADC[0]_22
64 P9.3_PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/ADC[0]_23
65 P10.0_PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/SCB4_RX/SCB4_MISO/TRIG_IN[18]
66 P10.1_PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/TRIG_IN[19]
67 P10.2_PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/SCB4_RTS/SCB4_SCL/SCB4_CLK
68 P10.3_PWM_31/PWM_30_N/TC_31_TR0/TC_30_TR1/SCB4_CTS/SCB4_SEL0
69 P10.4_PWM_32/PWM_31_N/TC_32_TR0/TC_31_TR1/SCB4_SEL1/ADC[1]_0
70 P10.5_PWM_33/PWM_32_N/TC_33_TR0/TC_32_TR1/SCB4_SEL2/ADC[1]_1
C
71 P10.6_PWM_34/PWM_33_N/TC_34_TR0/TC_33_TR1/ADC[1]_2
72 P10.7_PWM_35/PWM_34_N/TC_35_TR0/TC_34_TR1/ADC[1]_3
73 P11.0_ADC[0]_M
74 P11.1_ADC[1]_M
75 P11.2_ADC[2]_M
80 P12.0_PWM_36/PWM_35_N/TC_36_TR0/TC_35_TR1/CAN0_2_TX/TRIG_IN[20]/ADC[1]_4
81 P12.1_PWM_37/PWM_36_N/TC_37_TR0/TC_36_TR1/LIN6_EN/CAN0_2_RX/TRIG_IN[21]/ADC[1]_5
82 P12.2_PWM_38/PWM_37_N/TC_38_TR0/TC_37_TR1/EXT_MUX[1]_EN/LIN6_RX/ADC[1]_6
83 P12.3_PWM_39/PWM_38_N/TC_39_TR0/TC_38_TR1/EXT_MUX[1]_0/LIN6_TX/ADC[1]_7
84 P12.4_PWM_40/PWM_39_N/TC_40_TR0/TC_39_TR1/EXT_MUX[1]_1/ADC[1]_8
B
85 P12.5_PWM_41/PWM_40_N/TC_41_TR0/TC_40_TR1/EXT_MUX[1]_2/ADC[1]_9
86 P12.6_PWM_42/PWM_41_N/TC_42_TR0/TC_41_TR1/ADC[1]_10
87 P12.7_PWM_43/PWM_42_N/TC_43_TR0/TC_42_TR1/ADC[1]_11
LQFP_176_1M_B0
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P3
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
Rev
SPPD
C
Date: Monday, April 01, 2019
Sheet
11 o f 20
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
27
Figure A-11. LQFP-176 P4
5
{7,16} UART_SCB3_RX
{7,16} UART_SCB3_TX
D
{16,19} BB_CAN5_S
{16,19} BB_USER_LED6
{18,19} BB_LIN0_WAKE {18,19} BB_USER_LED7
{18} BB_LIN1_WAKE
{18} BB_USER_LED8
{18} BB_LIN2_WAKE {18} BB_USER_LED9
{19} BB_LIN3_WAKE
{19} BB_USER_BUTTON_1
{19} BB_LIN4_WAKE
{19} BB_USER_BUTTON_2 {17,19} BB_CAN3_TXD
{17,19} BB_CAN9_TXD {17,19} BB_CAN3_RXD
{17,19} BB_CAN9_RXD
{18,19} BB_LIN5_WAKE
{18,19} BB_USER_BUTTON_3
{19} BB_USER_LED5
C
{19} GPIO_044
{19} GPIO_045
{19} GPIO_046
{19} GPIO_047
{19} GPIO_048
{19} GPIO_049 {19} GPIO_050
{19} GPIO_051
{19} GPIO_052
{19} GPIO_053
B
{19} GPIO_054
{19} GPIO_055
{17} BB_CAN4_TXD
{17} BB_CAN4_RXD
A 5
Schematics of CPU Board
4
3
2
U4D
90 P13.0_PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12 91 P13.1_PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13 92 P13.2_PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14 93 P13.3_PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15 94 P13.4_PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/SCB3_SEL1/ADC[1]_16 95 P13.5_PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/SCB3_SEL2/ADC[1]_17 96 P13.6_PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18 97 P13.7_PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/TRIG_IN[23]/ADC[1]_19 98 P14.0_PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/SCB2_RX/SCB2_MISO/CAN1_0_TX/ADC[1]_20 99 P14.1_PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/SCB2_TX/SCB2_SDA/SCB2_MOSI/CAN1_0_RX/ADC[1]_21 100 P14.2_PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/SCB2_RTS/SCB2_SCL/SCB2_CLK/LIN6_RX/ADC[1]_22 101 P14.3_PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/SCB2_CTS/SCB2_SEL0/LIN6_TX/ADC[1]_23 102 P14.4_PWM_52/PWM_51_N/TC_52_TR0/TC_51_TR1/SCB2_SEL1/LIN6_EN/ADC[1]_24 103 P14.5_PWM_53/PWM_52_N/TC_53_TR0/TC_52_TR1/SCB2_SEL2/ADC[1]_25 104 P14.6_PWM_54/PWM_53_N/TC_54_TR0/TC_53_TR1/TRIG_IN[24]/ADC[1]_26 105 P14.7_PWM_55/PWM_54_N/TC_55_TR0/TC_54_TR1/TRIG_IN[25]/ADC[1]_27 106 P15.0_PWM_56/PWM_55_N/TC_56_TR0/TC_55_TR1/ADC[1]_28 107 P15.1_PWM_57/PWM_56_N/TC_57_TR0/TC_56_TR1/ADC[1]_29 108 P15.2_PWM_58/PWM_57_N/TC_58_TR0/TC_57_TR1/ADC[1]_30 109 P15.3_PWM_59/PWM_58_N/TC_59_TR0/TC_58_TR1/ADC[1]_31 112 P16.0_PWM_60/PWM_59_N/TC_60_TR0/TC_59_TR1/PWM_H_0 113 P16.1_PWM_61/PWM_60_N/TC_61_TR0/TC_60_TR1/PWM_H_0_N 114 P16.2_PWM_62/PWM_61_N/TC_62_TR0/TC_61_TR1/PWM_H_1 115 P16.3_PWM_62/PWM_62_N/TC_62_TR0/TC_62_TR1/PWM_H_1_N 116 P17.0_PWM_61/PWM_62_N/TC_61_TR0/TC_62_TR1/CAN1_1_TX 117 P17.1_PWM_60/PWM_61_N/TC_60_TR0/TC_61_TR1/PWM_H_2/SCB3_RX/SCB3_MISO/CAN1_1_RX
LQFP_176_1M_B0
1 D C B
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P4
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
Rev
SPPD
C
Date: Monday, April 01, 2019
Sheet
12 o f 20
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
28
Figure A-12. LQFP-176 P5
5
{18,19} BB_USER_LED4
{18,19} BB_SPI0_WP {19} GPIO_056
D
{19} GPIO_057
{19} GPIO_058
{19} GPIO_059
{19} GPIO_060
{19} BB_SPI0_MISO
{19} BB_SPI0_MOSI
{16} BB_SPI0_CLK
{6,19} TRACE_CLOCK
{16} BB_SPI0_SS
{18,19} GPIO_061
{18,19} BB_SPI0_HOLD
C
{17} BB_CAN5_TXD
{17} BB_CAN5_RXD
{19} BB_USER_LED3
{19} BB_USER_LED2
{18,19} BB_CAN0_S
{18,19} BB_USER_BUTTON_5
{16,18} BB_CAN1_S (12,21,2{136) ,18} BB_USER_LED0
{19} GPIO_062
{19} GPIO_063
{19} GPIO_064
{19} GPIO_065
B
{19} GPIO_066
{19} GPIO_067
{19} GPIO_068
{19} GPIO_069
A 5
Schematics of CPU Board
4
3
2
1
U4E
118 P17.2_PWM_59/PWM_60_N/TC_59_TR0/TC_60_TR1/PWM_H_2_N/SCB3_TX/SCB3_SDA/SCB3_MOSI
119 P17.3_PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]
120 P17.4_PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]
D
121 P17.5_PWM_56/PWM_57_N/TC_56_TR0/TC_57_TR1/SCB3_SEL1
122 P17.6_PWM_M_4/PWM_56_N/TC_M_4_TR0/TC_56_TR1/SCB3_SEL2
123 P17.7_PWM_M_5/PWM_M_4_N/TC_M_5_TR0/TC_M_4_TR1
124 P18.0_PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
125 P18.1_PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/ADC[2]_1
126 P18.2_PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/PWM_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/ADC[2]_2
127 P18.3_PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/TRACE_CLOCK/ADC[2]_3
128 P18.4_PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_DATA_0/ADC[2]_4
129 P18.5_PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
130 P18.6_PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/PWM_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_6
C
131 P18.7_PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/PWM_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_7
134 P19.0_PWM_M_3/PWM_50_N/TC_M_3_TR0/TC_50_TR1/TC_H_0_TR0/SCB2_RX/SCB2_MISO/FAULT_OUT_2
135 P19.1_PWM_26/PWM_M_3_N/TC_26_TR0/TC_M_3_TR1/TC_H_0_TR1/SCB2_TX/SCB2_SDA/SCB2_MOSI/FAULT_OUT_3
136 P19.2_PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/TC_H_1_TR0/SCB2_RTS/SCB2_SCL/SCB2_CLK/TRIG_IN[28]
137 P19.3_PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/TC_H_1_TR1/SCB2_CTS/SCB2_SEL0/TRIG_IN[29]
138 P19.4_PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/TC_H_2_TR0/SCB2_SEL1
139 P20.0_PWM_30/PWM_29_N/TC_30_TR0/TC_29_TR1/TC_H_2_TR1/SCB2_SEL2/LIN5_RX
140 P20.1_PWM_49/PWM_30_N/TC_49_TR0/TC_30_TR1/TC_H_3_TR0/LIN5_TX
141 P20.2_PWM_48/PWM_49_N/TC_48_TR0/TC_49_TR1/TC_H_3_TR1/LIN5_EN
142 P20.3_PWM_47/PWM_48_N/TC_47_TR0/TC_48_TR1/SCB1_RX/SCB1_MISO/CAN1_2_TX
B
143 P20.4_PWM_46/PWM_47_N/TC_46_TR0/TC_47_TR1/SCB1_TX/SCB1_SDA/SCB1_MOSI/CAN1_2_RX
144 P20.5_PWM_45/PWM_46_N/TC_45_TR0/TC_46_TR1/SCB1_RTS/SCB1_SCL/SCB1_CLK
145 P20.6_PWM_44/PWM_45_N/TC_44_TR0/TC_45_TR1/SCB1_CTS/SCB1_SEL0
LQFP_176_1M_B0
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P5
Size Document Number
Drawn By
Approved By
Rev
A4
6239956
VJYM
SPPD
C
Date: Monday, April 01, 2019
Sheet
13 o f 20
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
29
Figure A-13. LQFP-176 P6
Schematics of CPU Board
5
4
3
2
1
U4F
{19} GPIO_070
146 P20.7_PWM_43/PWM_44_N/TC_43_TR0/TC_44_TR1/SCB1_SEL1
{8} WCI/BTB
147 P21.0_PWM_42/PWM_43_N/TC_42_TR0/TC_43_TR1/SCB1_SEL2/WCO_IN
D
{8} WCO/BTB
R10
0E
148 P21.1_PWM_41/PWM_42_N/TC_41_TR0/TC_42_TR1/WCO_OUT
D
{8} ECI/BTB
149 P21.2_PWM_40/PWM_41_N/TC_40_TR0/TC_41_TR1/TRIG_DBG[1]/EXT_CLK/ECO_IN
{8} ECO/BTB
150 P21.3_PWM_39/PWM_40_N/TC_39_TR0/TC_40_TR1/ECO_OUT
{19} GPIO_071
151 P21.4_PWM_38/PWM_39_N/TC_38_TR0/TC_39_TR1/HIBERNATE_WAKEUP[0]
{6,7,14,18} CPU_XRES
152 XRES
{18} BB_LIN0_RX
157 P21.5_PWM_37/PWM_38_N/TC_37_TR0/TC_38_TR1/LIN0_RX
{19} GPIO_072
158 P21.6_PWM_36/PWM_37_N/TC_36_TR0/TC_37_TR1/LIN0_TX
{18} GPIO_073
159 P21.7_PWM_35/PWM_36_N/TC_35_TR0/TC_36_TR1/LIN0_EN/CAL_SUP_NZ/RTC_CAL
{6,19} TRACE_DATA_0
160 P22.0_PWM_34/PWM_35_N/TC_34_TR0/TC_35_TR1/SCB6_RX/SCB6_MISO/CAN1_1_TX/TRACE_DATA_0
{6,19} TRACE_DATA_1
161 P22.1_PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN1_1_RX/TRACE_DATA_1
C
{6,19} TRACE_DATA_2
162 P22.2_PWM_32/PWM_33_N/TC_32_TR0/TC_33_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK/TRACE_DATA_2
C
{6,19} TRACE_DATA_3
163 P22.3_PWM_31/PWM_32_N/TC_31_TR0/TC_32_TR1/SCB6_CTS/SCB6_SEL0/TRACE_DATA_3
{19} GPIO_074
164 P22.4_PWM_30/PWM_31_N/TC_30_TR0/TC_31_TR1/SCB6_SEL1/TRACE_CLOCK
{19} GPIO_075
165 P22.5_PWM_29/PWM_30_N/TC_29_TR0/TC_30_TR1/SCB6_SEL2/LIN7_RX
{19} GPIO_076
166 P22.6_PWM_28/PWM_29_N/TC_28_TR0/TC_29_TR1/LIN7_TX
{19} GPIO_077
167 P22.7_PWM_27/PWM_28_N/TC_27_TR0/TC_28_TR1/LIN7_EN
{19} GPIO_078
168 P23.0_PWM_M_8/PWM_27_N/TC_M_8_TR0/TC_27_TR1/SCB7_RX/SCB7_MISO/CAN1_0_TX/FAULT_OUT_0
{18} GPIO_079
169 P23.1_PWM_M_9/PWM_M_8_N/TC_M_9_TR0/TC_M_8_TR1/SCB7_TX/SCB7_SDA/SCB7_MOSI/CAN1_0_RX/FAULT_OUT_1
{18} GPIO_080
170 P23.2_PWM_M_10/PWM_M_9_N/TC_M_10_TR0/TC_M_9_TR1/SCB7_RTS/SCB7_SCL/SCB7_CLK/FAULT_OUT_2
{19} BB_USER_LED1
171 P23.3_PWM_M_11/PWM_M_10_N/TC_M_11_TR0/TC_M_10_TR1/SCB7_CTS/SCB7_SEL0/FAULT_OUT_3/TRIG_IN[30]
{6,19} SWO_TDO
172 P23.4_PWM_25/PWM_M_11_N/TC_25_TR0/TC_M_11_TR1/SCB7_SEL1/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31]
B
B
{6,19} SWCLK_TCLK
173 P23.5_PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SCB7_SEL2/SWJ_SWCLK_TCLK
{6,19} SWDIO_TMS
174 P23.6_PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS
{6,19} SWDOE_TDI
175 P23.7_PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/EXT_CLK/HIBERNATE_WAKEUP[1]
A 5
LQFP_176_1M_B0
VCC R6
{6,7,14,18} CPU_XRES
4.7K
R7 C49
DNI 1nF
4.7K
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P6
Size Document Number
A4
6239956
Drawn By
VJYM
Date: Monday, April 01, 2019
2
Approved By
Rev
SPPD
C
Sheet
14 o f 20
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
30
Figure A-14. LQFP-176 P7
5
PROCESSOR POWER
2
1
4 DEFAULT CLOSE
HDR_1X2
J10
CPU_BB_VDDD
3
On each VDDIO/VSSIO pin pair a 10uF and a 0.1uF is required
D
C56 +
C51 +
C50
C57
DEFAULT CLOSE CPU_BB_VDDA
HDR_1X2
10uF_16V 10uF_16V0.1uF 0.1uF
1
2
J8
C59
C58
+ 0.1uF
4.7uF_20V
DEFAULT CLOSE HDR_1X2
VCC
FL1
30E
VCC_FL
J5
2 1
1
2
C
BLM21PG300SH1D
CPU_BB_VDDIO
C52
C55
+
4.7uF_20V 0.1uF
C35 +
4.7uF_20V
C31 0.1uF
DEFAULT CLOSE HDR_1X2
J6
C53 C54 +
4.7uF_20V 0.1uF
C32 + 4.7uF_20V
C33 0.1uF
1
2
On each VDDIO/VSSIO pin pair a 4.7uF and a 0.1uF
C19 +
C20
is required
4.7uF_20V
0.1uF
B
Schematics of CPU Board
2
1
U4G
43 VDDD 153 VDDD
VSSD VSSD VSSD
46 154 155
D
78 VDDA
VSSA 77
22 VDDD
VSSD 1
C
44 VDDIO_1
VSSD 23
88 VDDIO_2
VSSD 45
110 VDDD
VSSD 89
132 VDDD
VSSD 111
176 VDDD
VSSD 133
B
ANALOG REFERENCE
{15} VREFH_N {15} VREFL_N A
5
C37 0.1uF
C14 +
C16
4.7uF_20V
0.1uF TP7
CPU_VCCD
47 156
VCCD VCCD
LQFP_176_1M_B0
VREFL VREFH
76 79
VREFL_N {15} VREFH_N {15}
R41 0E DNI
CPU_VREFH {16} CPU_BB_VDDA
R38
0E
C39 +
2.2uF_16V
R43
0E
4.7uF capacitor needs to be placed near pin 156
C12 C17 C36 Place one 0.1uF capacitor near each
4.7uF 0.1uF 0.1uF of the VCCD pins
TEST POINTS
CPU_BB_VDDD
CPU_BB_VDDIO
CPU_BB_VDDA
R42DNI 0E
CPU_VREFL {16}
TP3
TP1
TP2
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :LQFP-176 P7
Size Document Number
A4
6239956
Drawn By
VJYM
Date: Monday, April 01, 2019 2
Approved By
Rev
SPPD
C
Sheet 1
15 o f 20
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
31
Figure A-15. Board to Board Connector- J22A
5
4
BOARD TO BOARD CONNECTOR
This connects to J84 on the TVII Base board
D
C
{8,10,19} GPIO_018
{8,10,19} GPIO_023 {8} GPIO_082 {8} GPIO_083 {8} GPIO_084
{15} CPU_VREFL
{15} CPU_VREFH
B
{11} GPIO_025
{11} GPIO_026
{11} GPIO_027 {11} GPIO_028 {11} GPIO_029 {11} GPIO_030
{11} GPIO_031
J22A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
3
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
BB_USER_BUTTON_4 {11} BB_USER_LED0 {13,18(}12,18,23) BB_SPI0_SS {13} BB_SPI0_CLK {13}
GPIO_001 {9} GPIO_002 {9} GPIO_003 {9} GPIO_004 {9}
GPIO_005 {9} GPIO_006 {9}
GPIO_007 {9} GPIO_008 {9} GPIO_009 {9} GPIO_010 {9}
GPIO_011 {9} GPIO_012 {9} GPIO_013 {9} GPIO_014 {9}
GPIO_015 {9} GPIO_016 {10}
UART_SCB3_RX {7,12} UART_SCB3_TX {7,12} GPIO_017 {10} GPIO_019 {10} BB_CAN2_TXD {8} BB_CAN2_RXD {8} BB_CAN_SPI1_SS0 {10} BB_CAN_SPI1_SS1 {10} BB_CAN_SPI1_SS2 {10} BB_CAN2_S {9} BB_CAN3_S {9} BB_CAN4_S {11} BB_CAN5_S {12,19} BB_CAN6_WAKE {9} BB_CAN7_WAKE {10}
Schematics of CPU Board
1 D
C
B
181 182 183 184 185 186
181 182 183 184 185 186
A 5
CON_PMC_2X90_F
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :B TO B CONNECTOR- J22A
Size Document Number
A4
6239956
Drawn By
VJYM
Date: Monday, April 01, 2019 2
Approved By
Rev
SPPD
C
Sheet 1
16 o f 20
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
32
Figure A-16. Board to Board Connector- J22B
5
4
BOARD TO BOARD CONNECTOR
This connects to J84 on the TVII Base board
D
{10,18} BB_CAN6_TXD {10,18} BB_CAN6_RXD
{9,18} BB_CAN7_TXD {9,18} BB_CAN7_RXD
{10,19} BB_CAN8_TXD {10,19} BB_CAN8_RXD
{12,19} BB_CAN9_TXD {12,19} BB_CAN9_RXD
C
B
A 5
{10} GPIO_020 {10} GPIO_021 {10} GPIO_022 {11} GPIO_024
4
Schematics of CPU Board
3
J22B
91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179
91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180
2
1
Place R100 closer to the Samtec Connector J22
VBTOB_3.3V
VCC_LDO
VBTOB_3.3V
R100
0E
D
BB_CAN8_WAKE {10} BB_CAN9_WAKE {10} BB_CAN5_TXD {13} BB_CAN5_RXD {13} BB_CAN4_TXD {12} BB_CAN4_RXD {12}
C
B
187 188 189 190 191 192
187 188 189 190 191 192
CON_PMC_2X90_F 3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :B TO B CONNECTOR- J22B
Size Document Number
A4
6239956
Drawn By VJYM
Approved By SPPD
2
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
33
Figure A-17. Board to Board Connector- J21A
5
4
BOARD TO BOARD CONNECTOR
This connects to J38 on the TVII Base board
D
VBTOB_5V
J21A
C B
{9,17} BB_CAN1_RXD {9,17} BB_CAN1_TXD {13,16} BB_CAN1_S {10,17} BB_CAN0_RXD {10,17} BB_CAN0_TXD
{11} GPIO_032 {9} BB_LIN1_TX {9} BB_LIN1_RX
{11} GPIO_033 {11} GPIO_034
{14} BB_LIN0_RX {9} BB_LIN0_TX
{12,19} BB_LIN0_WAKE {9} BB_LIN0_SLP {11} GPIO_035 {11} GPIO_036 {11} GPIO_037 {11} GPIO_041
{11} BB_LIN5_RX {11} BB_LIN5_TX {12,19} BB_LIN5_WAKE {8,11} BB_LIN5_SLP {10} BB_LIN2_RX {10,17} BB_LIN2_TX {12} BB_LIN2_WAKE
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
Schematics of CPU Board
3
2
1
VCC_12V
Place R1 closer to Samtec Connector J22
VBTOB_5V
VCC_PMIC
R1
0E
D
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 GND 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
BB_USER_LED8 {12}
BB_USER_LED9 {12}
BB_CAN0_S {13,19}
BB_LIN1_WAKE {12} BB_LIN1_SLP {9,17}
Place R96,R95,R94,R93 closer to respective
CPU_BB_VDDD
CPU pins
R96
0E DNI BB_SPI0_WP {13,19}
CPU_BB_VDDA CPU_BB_VDDIO
R95
0E DNI
R94
0E DNI
R93
0E DNI
BB_SPI0_HOLD {13,19} BB_CAN_SPI1_MISO {10}
BB_CAN_SPI1_MOSI {10} BB_CAN_SPI1_CLK {10}
CPU_WCO_IN {8} CPU_WCO_OUT {8} CPU_ECO_IN {8} CPU_ECO_OUT {8}
R2
0E
CPU_XRES {6,7,14}
GPIO_073 {14} GPIO_080 {14} GPIO_079 {14}
C B
181 182 183 184 185 186
181 182 183 184 185 186
A 5
CON_PMC_2X90_F
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
A
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :B TO B CONNECTOR- J21A
Size Document Number
A4
6239956
Drawn By
VJYM
Date: Monday, April 01, 2019 2
Approved By
Rev
SPPD
C
Sheet
18 o f 20
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
34
Figure A-18. Board to Board Connector- J21B
5
4
BOARD TO BOARD CONNECTOR
This connects to J38 on the TVII Base board
D
{8,10,16} BB_LIN2_SLP {10} BB_LIN3_RX {10} BB_LIN3_TX
{12} BB_LIN3_WAKE {10,17} BB_LIN3_SLP
{10,17} BB_LIN4_RX {10} BB_LIN4_TX
{12} BB_LIN4_WAKE
{8,10,16} BB_LIN4_SLP {11} GPIO_042 {11} GPIO_043 {12} GPIO_046 {12} GPIO_045
{12} GPIO_044 {13,18} GPIO_061
{13} BB_SPI0_MISO
{14} BB_USER_LED1
{13} BB_USER_LED2
C
{13} BB_USER_LED3
{13,18} BB_USER_LED4
{12} BB_USER_LED5
{12,16} BB_USER_LED6
{12,18} BB_USER_LED7
{12} BB_USER_BUTTON_1 {12} BB_USER_BUTTON_2 {12,18} BB_USER_BUTTON_3
{13} BB_SPI0_MOSI {13,18} BB_USER_BUTTON_5
{12} GPIO_047
{12} GPIO_048
{12} GPIO_049
{12} GPIO_050
B
{12} GPIO_051
{12} GPIO_052
{12} GPIO_053
{12} GPIO_054
A
5
4
Schematics of CPU Board
3
2
1
J21B
91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179
91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180
92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180
R53 R50 R62
R65
R66 R52 R71 R54 R60 R56
GPIO_078 {14} GPIO_077 {14} GPIO_076 {14} GPIO_075 {14} GPIO_074 {14}
GPIO_072 {14} GPIO_068 {13} GPIO_067 {13} GPIO_069 {13}
0E DNI 0E DNI
0E DNI
GPIO_070 {14} GPIO_071 {14}
SWDIO_TMS {6,14} SWCLK_TCLK {6,14} GPIO_066 {13} GPIO_065 {13} TRSTN {6,9}
0E DNI
GPIO_064 {13} GPIO_063 {13} GPIO_062 {13} GPIO_060 {13} GPIO_059 {13} GPIO_058 {13}
BB_CAN3_TXD {12,17} BB_CAN3_RXD {12,17} TRACE_DATA_3 {6,14}
GPIO_057 {13}
0E DNI 0E DNI 0E DNI 0E DNI 0E DNI
0E DNI
TRACE_DATA_2 {6,14} SWDOE_TDI {6,14} TRACE_DATA_1 {6,14} SWO_TDO {6,14} TRACE_DATA_0 {6,14} GPIO_056 {13}
TRACE_CLOCK {6,13} GPIO_055 {12}
D C B
187 188 189 190 191 192
187 188 189 190 191 192
CON_PMC_2X90_F 3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
CYPRESS SEMICONDUCTOR © 2019
SCH Title : CYTVII-B-E-1M-B0-176-CPU-BOARD
Page Title :B TO B CONNECTOR- J21B
Size Document Number Drawn By
A4
6239956
VJYM
Approved By
SPPD
Date: Monday, April 01, 2019 2
Sheet
19 o f 20
1
A
Rev
C
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
35
B. Component Assembly on CPU Board
This appendix shows the top and bottom assembly of the PCB. Figure B-1. Top Assembly of the PCB
ART FILM - PASSY
J1
J2
R1 R2
LD1
R8 J9
R9
SW2
R14 U2
C13
R20
C7 C11
C15
R19
D1
C14
C16
R6
R7
1 100 R17 76
J7
TPS2
C8 C12 C17
TPS1 Y2
C4 R10 C9 R12 R16
R18
Y1
C5 R11
U4 75
C20
TP1
J6
TP2 J8
TP3
J10
C19
U3
25
51
C33
C32
50 R42 R43 R41
26
C35 C31 C44 R47
C36 TP7
J14 R48
SW3
C37 C39
C40
R39
TPS5
TPS6
R45
C41 C42 R44
TPS7 J15
R38
R46 LD5
C43
C38
R40
R32
TPS3 TPS4
J3
J5 J23 C1
FL1
C2
R3 R5
R4
LD2
L1
U1
C3
C60 C10
F1
C6
R13
TP4
R15
C18
C23
C22
C21 FL2
D2
D3
C24
C25 R23
TP5
R25
R26
R27 J11
R28 R29
U5
FL3
SW1
R21 R22 R24
LD3
LD4
C28
C29 C30
C27
C26
J13 TP6
R30
R31
L2
J12
FL4
C34
R60
R58
R56 R57 R55 R59
C45 R63
J16 J17
R78
R77
R72
R76
R73
R83
R87
R84
TP9
R88
R89
R90
R91 R92
R65 R71 R69 R70 R67 R68
R49
C46 R52 R53 R50
R51 R54 LD6
C48 C47
R61
R62
TP8
J18
J19
R20
R64
R66
R74
R75
R86
R85
R79 R80 R81 R82
PRIMARY_ASSEMBLY
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
36
Figure B-2. Bottom Assembly of the PCB
Component Assembly on CPU Board
J21
ART FILM - SASSY
PCB - EDGE
R96 R95 R94 C57 R93 C55 C50 C58 C54 R97 R98 C64
R99
C62 U12 C61
C51 C49
C59 C53
C56 C52
ART FILM - SASSY SECONDARY_ASSEMBLY
R100 J22
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
37
C. Schematics of Base Board
This appendix contains the schematics of the Base board on which CPU Board is mounted.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
38
Figure C-1. Block Diagram of Base Board
5
4
D
3
2
BOARD TO BOARD CONNECTORS (QTH-090-03-L-D-A)
Schematics of Base Board
1 D
C B A
5
C
POWER INPUTS (12V, 5V & 3.3V) FROM CPU OR ADAPTER BOARD
TRAVEO II EVM BASE BOARD
4
3
USER LED'S
B
PUSH-BUTTON
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :BLOCK DIAGRAM
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
3 o f 18
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
39
Figure C-2. BTOB Connector-01
5
BTOB CONNECTOR-01
TP6 D
TP7 TP8 TP9
TP10
TP11
TP12
C
17 BB_PWM_1 17 BB_PWM_2 17 BB_PWM_3 17 BB_PWM_4 17 BB_PWM_5 17 BB_PWM_6 17 BB_PWM_7 17 BB_ADC_2 17 BB_ADC_3 17 BB_ADC_4 17 BB_ADC_5 17 BB_ADC_6 17 BB_ADC_7 17 BB_ADC_8
B
J84A
1 3 5
1 3
7 9 11 13 15
5 7 9 11 13
17 19 21
15 17 19
23 21
25 27
23 25
29 31 33
27 29 31
35 37
33 35
39 37
41 43 45
39 41 43
47 49 51 53 55
45 47 49 51 53
57 59 61
55 57 59
63 61
65 67 69 71
63 65 67 69
73 71
75 77
73 75
79 77
81 83 85 87
79 81 83 85
89 87
89
181 182 183 184 185
186
4
2 4
2 4 6
6 8 10 12 14
8 10 12 14 16
16 18 20
18 20 22
22 24
24 26
26 28
28 30 32
30 32 34
34 36
36 38
38 40
40 42 44
42 44 46
46 48 50 52 54
48 50 52 54 56
56 58 60
58 60 62
62 64
64 66 68 70
66 68 70 72
72 74
74 76
76 78
78 80
80 82 84 86
82 84 86 88
88 90
90
CON_PMC_2X90_M
3
BB_USER_BUTTON_4 16,17 BB_USER_LED0 16,18 SPI0_SS 15,17 SPI0_CLK 15,17
BB_EXP1_GPIO_1 18 BB_EXP1_GPIO_2 18 BB_EXP1_GPIO_3 18 BB_EXP1_GPIO_4 18
BB_EXP1_GPIO_5 18 BB_EXP1_GPIO_6 18
BB_EXP1_GPIO_7 18 BB_EXP1_GPIO_8 18 BB_EXP1_GPIO_9 18 BB_EXP1_GPIO_10 18
BB_EXP1_GPIO_11 18 BB_EXP1_GPIO_12 18 BB_EXP1_GPIO_13 18 BB_EXP1_GPIO_14 18
BB_EXP1_GPIO_15 18 BB_EXP1_GPIO_16 18
8 CAN6_TXD 8 CAN6_RXD 8 CAN7_TXD 8 CAN7_RXD 9 CAN8_TXD 9 CAN8_RXD 9 CAN9_TXD 9 CAN9_RXD
TP13
TP14
UART1_RX 17
UART1_TX 17 UART1_RTS 17 UART1_CTS 17
CAN2_TXD 6,17 CAN2_RXD 6,17
CAN_SPI1_SS0 8,17 CAN_SPI1_SS1 8,17 CAN_SPI1_SS2 9,17 CAN2_S 6,17 CAN3_S 6,17 CAN4_S 7,17 CAN5_S 7,17 CAN6_WAKE 8,17 CAN7_WAKE 8,17
TP15
17 DEBUG_GPIO_1 17 DEBUG_GPIO_2 17 DEBUG_GPIO_3 17 DEBUG_GPIO_4
Schematics of Base Board
2
1
P_3V3
J84B
91 93 95
91 93
97 99 101
95 97 99
92 94
92 94 96
96 98 100
98 100 102
CAN8_WAKE 9,17 CAN9_WAKE 9,17
CAN5_TXD 7,17 CAN5_RXD 7,17
D
103 105
101 103
107 105
102 104
104 106
106 108
CAN4_TXD 7,17 CAN4_RXD 7,17
109 107
108 110
111 109 113 111 115 113
110 112 112 114 114 116
117 115
119 121
117 119
116 118
118 120
120 122
TP16
123 121
122 124
125 127
123 125
124 126
126 128
129 127
128 130
131 133 135
129 131 133
130 132 134
132 134 136
TP17
137 139 141
135 137 139
136 138 140
138 140 142
C
143 141
142 144
145 143 147 145
144 146 146 148
TP18
149 147
148 150
151 149 153 151 155 153
150 152 152 154 154 156
157 159 161
155 157 159
156 158 160
158 160 162
TP19
163 161
162 164
165 167
163 165
164 166
166 168
169 167
168 170
171 173 175
169 171 173
170 172 174
172 174 176
TP20
177 175
176 178
179 177 179
178 180 180
190 191 192
187 188 189
B CON_PMC_2X90_M
191 192
187 188 189 190
182 183 184 185 186
181
P_3V3 SML-P12YTT86 LD13
VCC_3V3
J80 HDR_1X3Default 1-2
FL3
VCC_3V3
VCC_5V
VDD_IO_W
VDD_IO
3 2 1
R21
1K
1
2
1
2
FL4
5%
0402
1
2
C9
C8 600E
C10
10uF
0.1uF
0.1uF
600E
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :BTOB CONNECTOR-01
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
4 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
40
Figure C-3. BTOB Connector-02
Schematics of Base Board
5
BTOB CONNECTOR-02
P_5V
J38A
D
6,17 CAN1_RXD
6,17 CAN1_TXD
6,17 CAN1_S
6,17 CAN0_RXD
6,17 CAN0_TXD 17 BB_ADC_9
10,17 LIN1_TXD 10,17 LIN1_RXD
17 BB_ADC_10
17 BB_ADC_11
13 FRA_RXD
13 FRA_TXD 13 FRA_TXEN 13 FRA_STBN 13 FRA_EN 13 FRA_ERRN
13 FRA_WAKE 14 FRB_RXD
14 FRB_TXD 14 FRB_TXEN 14 FRB_STBN 14 FRB_EN 14 FRB_ERRN
C
14 FRB_WAKE
10,17 LIN0_RXD
10,17 LIN0_TXD 10,17 LIN0_WAKE 10,17 LIN0_SLP 15,17 CXPI_RXD
15,17 CXPI_TXD 15,17 CXPI_SELMS 15,17 CXPI_NSLP 12,17 LIN5_RXD
12,17 LIN5_TXD 12,17 LIN5_WAKE 12,17 LIN5_SLP 11,17 LIN2_RXD
11,17 LIN2_TXD 11,17 LIN2_WAKE
1
3 5 7 9 11
1 3 5 7 9
13 15 17
11 13 15
19 21 23
17 19 21
25 27 29 31 33
23 25 27 29 31
35 33
37 39
35 37
41 39
43 45 47 49
41 43 45 47
51 49
53 55 57
51 53 55
59 61 63 65 67
57 59 61 63 65
69 71 73
67 69 71
75 73
77 79 81 83
75 77 79 81
85 83
87 89
85 87
89
B
181 182 183
185 186
4
3
P_12V
2
2 4 6 8 10
4 6 8 10 12
12 14 16
14 16 18
18 20 22
20 22 24
24 26 28 30 32
26 28 30 32 34
34 36
36 38
38 40
40 42
42 44 46 48
44 46 48 50
50 52
52 54 56
54 56 58
58 60 62 64 66
60 62 64 66 68
68 70 72
70 72 74
74 76
76 78 80 82
78 80 82 84
84 86
86 88
88 90
90
CON_PMC_2X90_M
BB_USER_LED8 16,17 BB_EXP2_GPIO_1 18 BB_EXP2_GPIO_2 18
BB_USER_LED9 16,17 CAN0_S 6,17 LIN1_WAKE 10,17 LIN1_SLP 10,17 SUPPLY_INH 14,17
SPI0_WP 15,17 BB_HPMC_2 17 BB_HPMC_1 17 BB_HPMC_3 17 BB_HPMC_4 17
SPI0_HOLD 15,18 CAN_SPI1_MISO 8,9,18
CAN_SPI1_MOSI 8,9,18 CAN_SPI1_SCK 8,9,18
BB_BOARD_RSTX_SET
BB_BOARD_RSTX
11,17 LIN2_SLP 11,17 LIN3_RXD
11,17 LIN3_TXD 11,17 LIN3_WAKE 11,17 LIN3_SLP 12,17 LIN4_RXD
12,17 LIN4_TXD 12,17 LIN4_WAKE 12,17 LIN4_SLP
17 BB_I2C1_SDA 17 BB_I2C1_SCL
15,18 CXPI_CLK 18 BB_GPIO_37TP2 TP4
18 BB_ADC_1 15,18 BB_ADC_POT
15,18 SPI0_MISO
16,18 16,18 16,18 16,18 16,18 16,18 16,18
BB_USER_LED1 BB_USER_LED2 BB_USER_LED3 BB_USER_LED4 BB_USER_LED5 BB_USER_LED6 BB_USER_LED7
TP3
BB_GPIO_48 18 BB_GPIO_49 18 BB_GPIO_50 18 BB_GPIO_51 18
16,17 16,17 16,17
BB_GPIO_52 18 BB_GPIO_53 18
16,17
BB_GPIO_54 18
BB_GPIO_55 18
BB_GPIO_56_RESET 18 BB_PWM_8 18
BB_PWM_9 18
BB_PWM_10 18
BB_EXP2_GPIO_3 18
BB_EXP2_GPIO_4 18
BB_EXP2_GPIO_5 18
TP1
BB_USER_BUTTON_1 BB_USER_BUTTON_2 BB_USER_BUTTON_3
15,18 SPI0_MOSI BB_USER_BUTTON_5
18 DEBUG_GPIO_5 18 DEBUG_GPIO_6 18 DEBUG_GPIO_7 18 DEBUG_GPIO_8 18 DEBUG_GPIO_9 18 DEBUG_GPIO_10 18 DEBUG_GPIO_11 18 DEBUG_GPIO_12
2
1
J38B
91
93 95 97 99 101
91 93 95 97 99
92
92 94 96 98 100
94 96 98 100 102
BB_EXP2_GPIO_6 18
D
BB_EXP2_GPIO_7 18
BB_EXP2_GPIO_8 18
BB_EXP2_GPIO_9 18
BB_EXP2_GPIO_10 18
103 105 107
101 103 105
109 111 113
107 109 111
102 104 106
104 106 108
108 110 112
110 112 114
BB_EXP2_GPIO_11 18 BB_EXP2_GPIO_12 18 BB_EXP2_GPIO_13 18 BB_EXP2_GPIO_14 18
115 113
114 116
117 119 121
115 117 119
116 118 120
118 120 122
BB_EXP2_GPIO_15 18 BB_EXP2_GPIO_16 18
123 121
125 123
127 129
125 127
131 129
133 135
131 133
122 124
124 126
126 128
128 130
130 132
132 134
134 136
DEBUG_GPIO_21 5 DEBUG_GPIO_22 5 DEBUG_GPIO_23 18 DEBUG_GPIO_24 18 DEBUG_GPIO_25 5
137 139
135 137
141 139
136 138
138 140
140 142
UART0_RX 18 UART0_TX 18
C
143 145 147
141 143 145
142 144 146
144 146 148
UART0_RTS 18 UART0_CTS 18
SPI2_MISO 18
149 151 153
147 149 151
148 150 152
150 152 154
SPI2_MOSI 18 SPI2_CLK 18 SPI2_SS 18
155 157
153 155
159 161 163
157 159 161
165 163
167 169 171 173
165 167 169 171
175 173
177 179
175 177
179
154 156
156 158
158 160 162
160 162 164
164 166
166 168 170 172
168 170 172 174
174 176
176 178
178 180
180
CAN3_TXD 6,18 CAN3_RXD 6,18 DEBUG_GPIO_26 18 TP5 DEBUG_GPIO_27 18
DEBUG_GPIO_13 18 DEBUG_GPIO_14 18 DEBUG_GPIO_15 18 DEBUG_GPIO_16 18 DEBUG_GPIO_17 18 DEBUG_GPIO_18 18 DEBUG_GPIO_19 18 DEBUG_GPIO_20 18
192
189 190 191
187
CON_PMC_2X90_M
B
189 188
185 184
190 191 192
187 188
186
181 182 183 184
R2 5%
P_5V
SML-P12YTT86 LD1
1K
1
2
0402
FL1 1
C1 10uF
C2 600E 0.1uF
VCC_5V
2
R3
5%
C3 0.1uF
SML-P12YTT86 LD2
1K
1
2
0402
P_12V
C4 10uF
FL2 1
C5 600E 0.1uF
VBAT
2
C6 0.1uF
VDD_IO
R101 4.7K_1% BB_I2C1_SDA DNI
R102 4.7K_1% BB_I2C1_SCL DNI
J132
Default closed
J133
J134
A
Default closed
Default closed
1 2
DEBUG_GPIO_21 5 DEBUG_GPIO_21_W 18
1 2
DEBUG_GPIO_22 5 DEBUG_GPIO_22_W 18
1 2
DEBUG_GPIO_25 5 DEBUG_GPIO_25_W 18
HDR_1X2
HDR_1X2
HDR_1X2
5
4
3
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :BTOB CONNECTOR-02
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
5 o f 18
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
41
Figure C-4. CAN-FD_0 to 3
Schematics of Base Board
5
4
3
VDD_IO
CAN_FD_0
2 VDD_IO
1
CAN_FD_1
D
J72
J70
HDR_1X2HDR_1X2
C52
+
C53
CON_DSUB_9_MM
J68
J66
HDR_1X2HDR_1X2
C50 +
C51
CON_DSUB_9_MM
D
Default Closed
22uF_20V 0.1uF
A5
SH2
A9
Default Closed
22uF_20V
0.1uF
B5
SH4
B9
A4
B4
1
2
2 1
1
2
2 1
U13
A8
U12
B8
5,17 CAN0_TXD 5,17 CAN0_RXD
CAN0_TXD_W CAN0_RXD_W
1 4
TXD RXD
CANH CANL
7 6
A3
CAN0_H_WR98 0E CAN0_H
A7
CAN0_L_WR99 0E CAN0_L
A2
A6
5,17 CAN1_TXD 5,17 CAN1_RXD
CAN1_TXD_W CAN1_RXD_W
1 4
TXD RXD
CANH CANL
7 6
B3
CAN1_H_WR94 0E CAN1_H
B7
CAN1_L_WR95 0E CAN1_L
B2
B6
5,17 CAN0_S
CAN0_S_W
8S
NC 5
J69 HDR_1X2
A1
SH1
5,17 CAN1_S
CAN1_S_W
8S
NC 5
J65 HDR_1X2
B1
SH3
2 GND VCC 3 2 1
2 GND VCC 3 2 1
2
1
2
1
Default Closed
R97
TJA1057GT
10K
Default Open
P6A
J71 HDR_1X2
C
CAN0_H CAN0_L
R100 120E
Default Closed
R93 TJA1057GT 10K
Default Open
P6B
J67 HDR_1X2
CAN1_H
R96 120E CAN1_L
C
VDD_IO
CAN_FD_2
VDD_IO
CAN_FD_3
J83
J81
HDR_1X2HDR_1X2
C56 +
C57
CON_DSUB_9_MM
J78
J76
HDR_1X2HDR_1X2
C54 +
C55
CON_DSUB_9_MM
Default Closed
22uF_20V
0.1uF
A5
SH2
A9
Default Closed
22uF_20V
0.1uF
B5
SH4
B9
A4
B4
1
2
2 1
1
2
2 1
U15
A8
U14
B8
A3
B3
B
4,17 CAN2_TXD
4,17 CAN2_RXD
CAN2_TXD_W CAN2_RXD_W
1 4
TXD RXD
CANH CANL
7 6
CAN2_H_WR108 0E CAN2_H A7 CAN2_L_WR109 0E CAN2_L A2
A6
5,18 CAN3_TXD 5,18 CAN3_RXD
CAN3_TXD_W CAN3_RXD_W
1 4
TXD RXD
CANH CANL
7 6
CAN3_H_WR104 0E CAN3_H B7 CAN3_L_WR105 0E CAN3_L B2
B6
B
4,17 CAN2_S
CAN2_S_W
8S
NC 5
J79 HDR_1X2
A1
SH1
4,17 CAN3_S
CAN3_S_W
8S
NC 5
J75 HDR_1X2
B1
SH3
2 GND VCC 3 2 1
2 GND VCC 3 2 1
2
1
2
1
Default Closed
J82 HDR_1X2
R107 10K
TJA1057GT
CAN2_H
Default Open
P7A
CAN2_L
R110 120E
Default Closed
J77 HDR_1X2
R103 TJA1057GT 10K
CAN3_H
Default Open
P7B
CAN3_L
R106 120E
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :CAN-FD_0 TO 3
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
6 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
42
Figure C-5. CAN-FD_4 to 7
Schematics of Base Board
5
4
3
VDD_IO
CAN_FD_4
2 VDD_IO
1
CAN_FD_5
D
J93
J91
HDR_1X2HDR_1X2
C62 +
C63
CON_DSUB_9_MM
J88
J86
HDR_1X2HDR_1X2
C58 +
C59
CON_DSUB_9_MM
D
Default Closed
22uF_20V
0.1uF
A5
SH2
A9
Default Closed
22uF_20V
0.1uF
B5
SH4
B9
A4
B4
1
2
2 1
1
2
2 1
U17
A8
U16
B8
3
GND VCC
4,17 CAN4_TXD 4,17 CAN4_RXD
CAN4_TXD_W CAN4_RXD_W
1 4
TXD RXD
CANH CANL
7 6
A3 CAN4_H_WR117 0E CAN4_H A7 CAN4_L_WR118 0E CAN4_L A2
A6
4,17 CAN5_TXD 4,17 CAN5_RXD
CAN5_TXD_W CAN5_RXD_W
1 4
TXD RXD
CANH CANL
7 6
B3 CAN5_H_WR112 0E CAN5_H B7 CAN5_L_WR113 0E CAN5_L B2
B6
4,17 CAN4_S
CAN4_S_W
8S
NC 5
J90 HDR_1X2
A1
SH1
4,17 CAN5_S
CAN5_S_W
8S
NC 5
J85 HDR_1X2
B1
SH3
2 GND VCC 3 2 1
2
1
2
2
1
Default Closed
R116 10K
TJA1057GT
Default Open
P8A
2 1
J92 HDR_1X2
C
CAN4_H CAN4_L
R119 120E
Default Closed
R111 10K
TJA1057GT
Default Open
P8B
J87 HDR_1X2
CAN5_H
R114 120E CAN5_L
C
B
B
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :CAN-FD_4 TO 7
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
7 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
43
Figure C-6. CAN-FD_6 & 7
Schematics of Base Board
5
4
3
2
1
VCC_5V
VDD_IO VBAT
CAN_FD_6
J109 J94
HDR_1X2HDR_1X2
Default Closed D
2 1
1
2
4 CAN6_TXD 4 CAN6_RXD
8,9 CAN_SPI1_MOSI_W 8,9 CAN_SPI1_MISO_W 8,9 CAN_SPI1_SCK_W
4,17 CAN6_WAKE
CAN6_TXD_W 1 CAN6_RXD_W 4
CAN_SPI1_MOSI_W 11
CAN_SPI1_MISO_W
6
CAN_SPI1_SCK_W
8
CAN_SPI1_SS0_W
14
CAN6_WAKE_W 9
U18
TXD RXD
SDI SDO
SCK
SCSN
WAKE
3 VCC VIO 5
10 BAT
CON_DSUB_9_MM
A5
SH2
A9
A4
A8
CANH
13 12
CANL
CAN6_H_WR126 0E CAN6_L_WR125 0E
A3 CAN6_H A7 CAN6_L A2
A6
A1
SH1
INH 7
P9A CAN6_INH_W R120 0E CAN6_INH 14
2 GND
R124 10K
TJA1145T
1
2
VCC_5V
VDD_IO VBAT
CAN_FD_7
J95
J97
HDR_1X2HDR_1X2
Default Closed
2 1
1
2
4 CAN7_TXD 4 CAN7_RXD
8,9 CAN_SPI1_MOSI_W 8,9 CAN_SPI1_MISO_W 8,9 CAN_SPI1_SCK_W
4,17 CAN7_WAKE
CAN7_TXD_W 1 CAN7_RXD_W 4
CAN_SPI1_MOSI_W 11
CAN_SPI1_MISO_W
6
CAN_SPI1_SCK_W
8
CAN_SPI1_SS1_W
14
CAN7_WAKE_W 9
U19
TXD RXD
SDI SDO
SCK
SCSN
WAKE
3 VCC VIO 5 BAT 10
CON_DSUB_9_MM
B5
SH4
B9
D
B4
B8
CANH
13 12
CANL
CAN7_H_WR129 0E CAN7_L_WR128 0E
B3 CAN7_H B7 CAN7_L B2
B6
B1
SH3
INH 7
P9B CAN7_INH_W R121 0E CAN7_INH 14
2 GND
R127 10K
TJA1145T
1
2
HDR_1X2 J110
VDD_IO
J106 Default closed
CAN_SPI1_SCK 5,8,9,18
HDR_1X2 J101
VDD_IO
C
Default closed
R132
J105
CAN_SPI1_SS0 4,17 4.7K_1%
J103 Default closed
CAN_SPI1_MISO 5,8,9,18
1
2
CAN_SPI1_SCK_W
Default closed J96
R122 CAN_SPI1_SS1 44,.177K_1%
J99 Default closed
1
CAN_SPI1_MISOJ1050,8,9,18 Default closed 1
CAN_SPI1_SCK 5,8,9,18
C
1
2
CAN_SPI1_MISO_W
2
CAN_SPI1_SCK_W
1
2
CAN_SPI1_MISO_W
1
2
CAN_SPI1_SS0_W
HDR_1X2 J108
2
CAN_SPI1_SS1_W
J107
HDR_1X2
HDR_1X2
HDR_1X2 Default Open
HDR_1X2
HDR_1X2
HDR_1X2
HDR_1X2 Default Open
2 1
2 1
J104 Default closed
CAN_SPI1_MOSI 5,8,9,18
1
2
CAN_SPI1_MOSI_W
CAN6_H CAN6_L
R130 120E
J98 Default closed
CAN_SPI1_MOSI 5,8,9,18
1
2
CAN_SPI1_MOSI_W
CAN7_H CAN7_L
R131 120E
HDR_1X2 B
VDD_IO
VCC_5V
VBAT
C68 + C66
0.1uF
22uF_20V
C69 0.1uF
C79 4.7uF
C77 0.1uF
HDR_1X2
VDD_IO
VCC_5V
VBAT
B
C70 + C67
0.1uF
22uF_20V
C71 0.1uF
C80 4.7uF
C78 0.1uF
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :CAN-FD_6 & 7
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
8 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
44
Figure C-7. CAN-FD_8 & 9
Schematics of Base Board
5
4
3
2
1
VCC_5V
VDD_IO VBAT
CAN_FD_8
J113 J112
HDR_1X2HDR_1X2
Default Closed D
2 1
1
2
4 CAN8_TXD 4 CAN8_RXD
8,9 CAN_SPI1_MOSI_W 8,9 CAN_SPI1_MISO_W 8,9 CAN_SPI1_SCK_W
4,17 CAN8_WAKE
2
1
CAN8_TXD_W 1 CAN8_RXD_W 4
CAN_SPI1_MOSI_W 11
CAN_SPI1_MISO_W
6
CAN_SPI1_SCK_W
8
CAN_SPI1_SS2_W
14
CAN8_WAKE_W 9
U21
TXD RXD
SDI SDO
SCK
SCSN
WAKE
R138 10K
TJA1145T
2 GND
3 VCC VIO 5 BAT 10
CON_DSUB_9_MM
A5
SH2
A9
A4
A8
CANH
13 12
CANL
CAN8_H_WR140 0E CAN8_L_WR139 0E
A3 CAN8_H A7 CAN8_L A2
A6
A1
SH1
7 INH
P10A CAN8_INH_W R134 0E CAN8_INH 14
VCC_5V
VDD_IO VBAT
CAN_FD_9
J131 J114 HDR_1X2HDR_1X2 Default Closed
2 1
1
2
4 CAN9_TXD 4 CAN9_RXD
8,9 CAN_SPI1_MOSI_W 8,9 CAN_SPI1_MISO_W 8,9 CAN_SPI1_SCK_W
4,17 CAN9_WAKE
CAN9_TXD_W 1 CAN9_RXD_W 4
CAN_SPI1_MOSI_W 11
CAN_SPI1_MISO_W
6
CAN_SPI1_SCK_W
8
CAN_SPI1_SS2_W
14
CAN9_WAKE_W 9
U20
TXD RXD
SDI SDO
SCK
SCSN
WAKE
3 VCC VIO 5 BAT 10
CON_DSUB_9_MM
B5
SH4
B9
D
B4
B8
CANH
13 12
CANL
CAN9_H_WR137 0E CAN9_L_WR136 0E
B3 CAN9_H B7 CAN9_L B2
B6
B1
SH3
7 INH
P10B CAN9_INH_W R133 0E CAN9_INH 14
2 GND
R135 10K
TJA1145T
1
2
HDR_1X2 J111
VDD_IO
J118 Default closed
CAN_SPI1_SCK 5,8,9,18
HDR_1X2 J125
VDD_IO
C
Default closed
R141
J115
CAN_SPI1_SS2 44,.97,K1_71%
J117 Default closed
CAN_SPI1_MISO 5,8,9,18
1
2
CAN_SPI1_SCK_W
Default closed J124
R144 CAN_SPI1_SS2 44,.97,K1_71%
J121 Default closed
1
CAN_SPI1_MISOJ1253,8,9,18 Default closed 1
CAN_SPI1_SCK 5,8,9,18
C
1
2
CAN_SPI1_MISO_W
2
CAN_SPI1_SCK_W
1
2
CAN_SPI1_MISO_W
1
2
CAN_SPI1_SS2_W
HDR_1X2 J119
2
CAN_SPI1_SS2_W
J120
HDR_1X2
HDR_1X2
HDR_1X2 Default Open
HDR_1X2
HDR_1X2
HDR_1X2
HDR_1X2 Default Open
2 1
2 1
J116 Default closed
CAN_SPI1_MOSI 5,8,9,18
1
2
CAN_SPI1_MOSI_W
CAN8_H CAN8_L
R143 120E
J122 Default closed
CAN_SPI1_MOSI 5,8,9,18
1
2
CAN_SPI1_MOSI_W
CAN9_H CAN9_L
R142 120E
HDR_1X2 B
VDD_IO
VCC_5V
VBAT
C85 + C82
0.1uF
22uF_20V
C86 0.1uF
C90 4.7uF
C88 0.1uF
HDR_1X2
VDD_IO
VCC_5V
VBAT
B
C83 + C81
0.1uF
22uF_20V
C84 0.1uF
C89 4.7uF
C87 0.1uF
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :CAN-FD_8 & 9
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
9 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
45
Figure C-8. LIN INTERFACE_0 to 1
Schematics of Base Board
5
4
3
2
1
LIN0_INTERFACE
J58 HDR_1X2 Default Closed
VBAT
CON_DSUB_9_MM
LIN1_INTERFACE
J51 HDR_1X2 Default Closed
VBAT
CON_DSUB_9_MM
1
2
1
2
LIN_VS D26
A5
SH2
1
2
A9
D
A4
1N4002-T
A8 A3
C47 + C46
LIN0_BUS
A7
22uF_20V
A2
0.1uF
VDD_IO
A6
A1
SH1
LIN_VS D23
B5
SH4
1
2
B9
B4
D
1N4002-T
B8 B3
C43 + C42
VDD_IO
LIN1_BUS
B7
22uF_20V
B2
0.1uF
B6
B1
SH3
Default Open J59
R92 1K D25
1
2
R89
J60
J63
4.7K_1% HDR_1X2HDR_1X2
P5A
Default Open J52
R87 1K D24
1
2
R84 4.7K_1%
J53
J56
HDR_1X2HDR_1X2
P5B
1
2
C48
1N4148W-7-F
1000pF
U11
2
1
2 1
1
Default closed
2
7 VBAT
HDR_1X2
LIN0_WAKE_N 3 WAKE_N
4
TXD RXD
1
LIN0_TXD_W LIN0_RXD_W
LIN0_TXD 5,17 LIN0_RXD 5,17
HDR_1X2
LIN0_BUS
6 LIN
INH 8
R88 0E
LIN0_INH 14
C
C49 220pF
LIN0_EN
2 SLP_N
TJA1021T/20/C
C44 1000pF
1N4148W-7-F U10
2
1
2 1
Default closed
VBAT 7
LIN1_WAKE_N 3 WAKE_N
4
TXD RXD
1
LIN1_TXD_W LIN1_RXD_W
LIN1_TXD 5,17 LIN1_RXD 5,17
LIN1_BUS
6 LIN
INH 8
R83 0E
LIN1_INH 14
C45 220pF
LIN1_EN
2 SLP_N
TJA1021T/20/C
C
5 GND
5 GND
J57
VBAT
J44
VBAT
1 2 LIN0_BUS_W 3
R11 0E
LIN0_BUS
1 2 LIN1_BUS_W 3
R7 0E
LIN1_BUS
VDD_IO
J61 Default Closed HDR_1X2
R91 4.7K_1%
HDR_1X3
J62 HDR_1X2 Default Closed
VDD_IO
R90 4.7K_1%
VDD_IO
J54 HDR_1X2
Default Closed
R86 4.7K_1%
HDR_1X3
J55 HDR_1X2
VDD_IO
R85 4.7K_1%
1
2
2 1
1
2
2 1
B
5,17 LIN0_WAKE
LIN0_WAKE_N
5,17 LIN0_SLP
LIN0_EN
5,17 LIN1_WAKE
LIN1_WAKE_N
5,17 LIN1_SLP
LIN1_EN B
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :LIN INTERFACE_0 TO 1
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
10 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
46
Schematics of Base Board
Figure C-9. LIN INTERFACE_2 to 3
5
4
3
2
1
LIN2_INTERFACE
J37 HDR_1X2 Default Closed
VBAT
CON_DSUB_9_MM
LIN3_INTERFACE
J30 HDR_1X2
Default Closed
VBAT
CON_DSUB_9_MM
1
2
1
2
LIN_VS D21
A5
SH2
D
1
2
A9
A4
A8
1N4002-T
A3
C37 + C36
VDD_IO
LIN2_BUS
A7
22uF_20V
A2
0.1uF
A6
A1
SH1
LIN_VS D14
B5
SH4
1
2
B9
D
B4
B8
1N4002-T
B3
C33 + C32
VDD_IO
LIN3_BUS
B7
22uF_20V
B2
0.1uF
B6
B1
SH3
Default Open J39
1 2
HDR_1X2
C
R77 1K D22
1
2
C38 1000pF
1N4148W-7-F U8 LIN2_WAKE_N 3 WAKE_N
LIN2_BUS
6 LIN
C39 220pF
LIN2_EN
2 SLP_N
7 VBAT
TXD
4 1
RXD
INH 8
R73 4.7K_1%
J40
J43
HDR_1X2HDR_1X2
P4A
Default closed
2 1
1
2
LIN2_TXD_W LIN2_RXD_W
R72 0E
LIN2_TXD 5,17 LIN2_RXD 5,17
LIN2_INH 14
TJA1021T/20/C
Default Open J31
1 2
HDR_1X2
R71 1K D16
1
2
R68
J32
J35
4.7K_1% HDR_1X2HDR_1X2
P4B
C34 1000pF
1N4148W-7-F U7
2
1
2 1
Default closed
VBAT 7
LIN3_WAKE_N 3 WAKE_N
TXD
4 1
RXD
LIN3_TXD_W LIN3_RXD_W
LIN3_TXD 5,17 LIN3_RXD 5,17
LIN3_BUS
6 LIN
INH 8
R67 0E
LIN3_INH 14
C35 220pF
LIN3_EN
2 SLP_N
C
TJA1021T/20/C
5 GND
5 GND
J36
VBAT
J28
VBAT
1 2 LIN2_BUS_W 3
R6 0E
LIN2_BUS
1 2 LIN3_BUS_W 3
R5 0E
LIN3_BUS
VDD_IO
HDR_1X3
VDD_IO
VDD_IO
HDR_1X3
VDD_IO
J41 Default Closed HDR_1X2
R75 4.7K_1%
J42 HDR_1X2 Default Closed
R74 4.7K_1%
J33 HDR_1X2 Default Closed
R70 4.7K_1%
J34 HDR_1X2
Default Closed
R69 4.7K_1%
1
2
2 1
1
2
2 1
B 5,17 LIN2_WAKE
LIN2_WAKE_N
5,17 LIN2_SLP
LIN2_EN
5,17 LIN3_WAKE
LIN3_WAKE_N
5,17 LIN3_SLP
LIN3_EN
B
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :LIN INTERFACE_2 TO 3
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
11 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
47
Figure C-10. LIN INTERFACE_4 to 5
Schematics of Base Board
5
4
3
2
1
LIN4_INTERFACE
J22 HDR_1X2
Default Closed
VBAT
CON_DSUB_9_MM
LIN5_INTERFACE
J10 HDR_1X2
Default Closed
VBAT
CON_DSUB_9_MM
1
2
1
2
LIN_VS D9
A5
SH2
D
1
2
A9
A4
A8
1N4002-T
A3
C29 + C28
VDD_IO
LIN4_BUS
A7
22uF_20V
A2
0.1uF
A6
A1
SH1
LIN_VS D7
B5
SH4
1
2
B9
D
B4
B8
1N4002-T
B3
C24 + C25
VDD_IO
LIN5_BUS
B7
22uF_20V
B2
0.1uF
B6
B1
SH3
Default Open J23
1 2
HDR_1X2
C
R66 1K D10
1
2
C30 1000pF
1N4148W-7-F U6 LIN4_WAKE_N 3 WAKE_N
LIN4_BUS
6 LIN
C31 220pF
LIN4_EN
2 SLP_N
5 GND
VBAT 7
TXD
4 1
RXD
INH 8
R63
J24
J27
4.7K_1% HDR_1X2HDR_1X2
P3A
Default closed
2 1
1
2
LIN4_TXD_W LIN4_RXD_W
R62 0E
LIN4_TXD 5,17 LIN4_RXD 5,17
LIN4_INH 14
TJA1021T/20/C
J21
1 2 3
VBAT
LIN4_BUS_W
R4 0E
LIN4_BUS
Default Open J16
1 2
HDR_1X2
R61 1K D8
1
2
R58
J17
J20
4.7K_1% HDR_1X2HDR_1X2
P3B
C26 1000pF
1N4148W-7-F U5
2
1
2 1
Default closed
7 VBAT
LIN5_WAKE_N 3 WAKE_N
TXD
4 1
RXD
LIN5_TXD_W LIN5_RXD_W
LIN5_TXD 5,17 LIN5_RXD 5,17
LIN5_BUS
6 LIN
INH 8
R57 0E
LIN5_INH 14
5 GND
C27 220pF
LIN5_EN
2 SLP_N
C
TJA1021T/20/C
J15
VBAT
1 2 LIN5_BUS_W 3
R1 0E LIN5_BUS
VDD_IO
HDR_1X3
VDD_IO
VDD_IO
HDR_1X3
VDD_IO
Default Closed
J25 HDR_1X2
R65 4.7K_1%
J26 HDR_1X2 Default Closed
R64 4.7K_1%
J18 HDR_1X2
Default Closed
R60 4.7K_1%
Default Closed
J19 HDR_1X2
R59 4.7K_1%
2 1
1
2
1
2
2 1
B 5,17 LIN4_WAKE
LIN4_WAKE_N
5,17 LIN4_SLP
LIN4_EN
5,17 LIN5_WAKE
LIN5_WAKE_N 5,17 LIN5_SLP
LIN5_EN
B
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :LIN INTERFACE_4 TO 5
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
12 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
48
Figure C-11. Flexray-01 & RESET
5
4
3
2
FLEXRAY INTERFACE -01
VDD_IO VBAT
D
Place C67, C68, C69 &C70 close to pin
16 VCC VIO 3 VBAT 11
5 FRA_TXD 5 FRA_RXD
5 FRA_TXEN
R47 0E R49 0E
R48 0E
5 FRA_STBN 5 FRA_WAKE
5 FRA_EN
R50 0E R25 0E R45 0E
FRA_TXD_W FRA_RXD_W FRA_TXEN_W
FRA_BGE FRA_STBN_W
FRA_WAKE_N FRA_EN_W
U3
4 6
TXD
RXD
5 9
TXEN RXEN
7 BGE
8 STBN
12 WAKE
2 EN
TJA1081TS
ERRN 10
INH 1
BP BM
15 14
FRA_ERRN_W R34
FRA_INH_W R46
FRA_BP_W FRA_BM_W
0E FRA_ERRN 5 0E FRA_INH 14
1
2
L2 4
3 4000E
FRA_BP FRA_BM
HDR_1X3
13 GND
3
C
2 1
DNI R23 0E
CON_DSUB_9_MM
A5
SH2
A9
A4
A8
A3
A7
A2
A6
A1
SH1
P2A
VDD_IO
R41 R36 R39 R32
10K
FRA_EN_W
10K FRA_STBN_W
10K
FRA_BGE
10K
FRA_WAKE
VDD_IO
C22 4.7uF
VBAT
C14 0.1uF
C12 4.7uF
Default 1-2 J7
C15 0.1uF
L4 180nH
C21 0.1uF
R30 100E
R28 1M
RESET
SW6
1
3
2
4
7914J-1-000E
Schematics of Base Board
1
VDD_IO
D
C7 0.1uF
U1
4 MR
VCC 5
3 RESET
GND GND
LM3724IM5-4.63/NOPB
R13
10K
J64
BB_RST_NP 2 1
HDR_1X2
1 2
C
B
B
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :FLEXRAY-01 & RESET
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
13 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
49
Figure C-12. Flexray-02 & INH
5
4
3
FLEXRAY INTERFACE-02
VDD_IO VBAT
Place C72, C73, C74 & C75 close to pin
D
16 VCC VIO 3
11 VBAT
5 FRB_TXD 5 FRB_RXD
5 FRB_TXEN
R53 0E R55 0E
R54 0E
5 FRB_STBN 5 FRB_WAKE
5 FRB_EN
R56 0E R26 0E R51 0E
FRB_TXD_W FRB_RXD_W FRB_TXEN_W
FRB_BGE FRB_STBN_W FRB_WAKE_N FRB_EN_W
U4
4 6
TXD RXD
5 9
TXEN
RXEN
7 BGE
8 STBN
12 WAKE
2 EN
TJA1081TS
13 GND
ERRN 10 1
INH 15
BP 14 BM
FRB_ERRN_W R33
FRB_INH_W R52
FRB_BP_W FRB_BM_W
0E FRB_ERRN 5 0E FRB_INH 14 L1
1
2
4000E
4
3
FRB_BP
FRB_BM
HDR_1X3
3 2 1
DNI R22 0E
CON_DSUB_9_MM
B5
SH4
B9
B4
B8
B3
B7
B2
B6
B1
SH3
P2B
C VDD_IO
R40
10K
FRB_EN_W
VDD_IO
VBAT
Default 1-2 J8
L3 180nH
R29 100E
R35
10K FRB_STBN_W
R38
10K
FRB_BGE
R31
10K
FRB_WAKE
C23 4.7uF
C18 0.1uF
C13 4.7uF
C19 0.1uF
R27
C20
1M
0.1uF
Schematics of Base Board
2
1
SUPPLY_INH
VDD_IO
J73 HDR_1X2
Default Closed
2 1
R20 4.7K_1% DNI
10 LIN0_INH 10 LIN1_INH 11 LIN2_INH 11 LIN3_INH 12 LIN4_INH 12 LIN5_INH 13 FRA_INH 14 FRB_INH
8 CAN6_INH 8 CAN7_INH 9 CAN8_INH 9 CAN9_INH
2
D17 2
D15 2
D20 2
D12 2
D11 2
D13 2
D19 2
D18 2
D4 2
D1 2
D2 2
D3
1SUPPLY_INH_W
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F 1
1N4148W-7-F
D SUPPLY_INH 5,17
C
R76 20K
B
B
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :FLEXRAY-02 & INH
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
14 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
50
Figure C-13. CXPI, EEPROM & POT
Schematics of Base Board
5
4
3
2
1
CXPI_INTERFACE
VDD_IO
CXPI_VS
J6 HDR_1X2 Default Closed
2 1
D5
1
2
VBAT
EEPROM INTERFACE
2
2 1
2 1
C16 +
C11
D6
1N4002-T
D
22uF_20V
1N4148W-7-F
J11
J14
R42
0.1uF
CON_DSUB_9_M
1
HDR_1X2HDR_1X2 4.7K_1%
Default Closed
5
11
R24
9
2 1 2 1
1K
4
8
7 BAT
5,17 CXPI_TXD 5,17 CXPI_RXD
CXPI_TXD_W CXPI_RXD_W
CXPI_CLK_W
CXPI_NSLP_W
U2
4
1
TXD RXD
3 CLK
2 NSLP
6 BUS
CXPI_BUS
C17 220pF
3
7
2
6
1
10
CXPI_SELMS_W 8 SELMS
P1
S6BT112A01
5 GND
VDD_IO D
J48
J47
J49
HDR_1X2HDR_1X2 HDR_1X2
Default Closed
2 1
2 1
1
2
5,18 SPI0_MOSI 4,17 SPI0_CLK 4,17 SPI0_SS
SPI0_MOSI_W SPI0_CLK_W SPI0_SS_n_W SPI0_WP_n SPI0_HOLD_n
U9
5 SI 6 SCK 1
CS 3 WP 7 HOLD
25LC320A
4 VSS
8 VCC
C40 10uF
C41 0.1uF
J50 HDR_1X2
Default closed
SO 2
SPI0_MISO_W
SPI0_MISO 5,18
C
J12
1 2
CXPI_CLK 5,18
VDD_IO
CXPI_CLK_W R43
4.7K_1%
J13
1 2
CXPI_NSLP 5,17
VDD_IO
CXPI_NSLP_W R44
4.7K_1%
J9
CXPI_SELMS 5,17
VDD_IO
1
2
CXPI_SELMS_W R37
4.7K_1%
Default closed
J46 HDR_1X2 Default Open
5,18 SPI0_HOLD
2
1
Default closed HDR_1X2
Default closed HDR_1X2
HDR_1X2
VDD_IO
R81 10K
J45 HDR_1X2 Default Open
SPI0_HOLD_n
5,17 SPI0_WP
R79
10K
DNI
VDD_IO
R82
10K
SPI0_SS_n_W
C VDD_IO
R80 10K
SPI0_WP_n
R78 10K DNI
B POTENTIOMETER
J89 HDR_1X2
ANALOG_VCC
VDD_IO
B ANALOG_VCC
5,18 BB_ADC_POT
2 1
R115 5%
C60 0.1uF
1K 0402
1
3
POT1
PTV09A-4015U-B103
SH2 2
SH1
FL5
1
C61 0.1uF 600E
2
C64 0.1uF
C65 33pF
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
A
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :CXPI, EEPROM & POT
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
15 o f 18
5
4
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
51
Figure C-14. USER_LED & PUSHBUTTON
Schematics of Base Board
5
4
3
2
1
USER_LED INTERFACE
NOTE: 5-RED & 5-GREEN LED COLOR
4,18 BB_USER_LED0
R16 0E BB_USER_LED0_W LD9 2
1LTST-C150GKT
RA3 1K
8
1
5,18 BB_USER_LED4
R10 0E BB_USER_LED4_W LD5 2
1LTST-C150GKT
RA2 1K
8
1
5,18 BB_USER_LED1
R17 0E BB_USER_LED1_W LD10 2
1LTST-C150GKT
7
2
6
3
5,18 BB_USER_LED5
R12 0E BB_USER_LED5_W LD6 2
1LTST-C150GKT
7
2
6
3
D
5,18 BB_USER_LED2
R18 0E BB_USER_LED2_W LD11 2
1LTST-C150GKT
5
4
5,18 BB_USER_LED6
R14 0E BB_USER_LED6_W LD7 2
1LTST-C150GKT
5
4
D
5,18 BB_USER_LED3
R19 0E BB_USER_LED3_W LD12 2
1LTST-C150GKT
5,18 BB_USER_LED7
R15 0E BB_USER_LED7_W LD8 2
1LTST-C150GKT
5,17 BB_USER_LED8 5,17 BB_USER_LED9
R8 0E BB_USER_LED8_W LD3 2 R9 0E BB_USER_LED9_W LD4 2
1LTST-C150GKT 1LTST-C150GKT
RA1 8 7 6 5
1K 1 2 3 4
USER_BUTTON INTERFACE VDD_IO C
8 7 6 5
10K
10K
R123
1 2 3 4 RA4
5,17 BB_USER_BUTTON_1 5,17 BB_USER_BUTTON_2 5,17 BB_USER_BUTTON_3 4,17 BB_USER_BUTTON_4 5,17 BB_USER_BUTTON_5
B
J102 Default Closed
1
2
3
4
5
6
7
8
9
10
BB_USER_BUTTON_1_W BB_USER_BUTTON_2_W BB_USER_BUTTON_3_W BB_USER_BUTTON_4_W BB_USER_BUTTON_5_W
HDR_2X5
RA5 16 15 14 13 12 11 10 9
1100E 2 3 4 5 6 7 8
C76 0.1uF
C75 0.1uF
C74 0.1uF
C73 0.1uF
C72 0.1uF
A
5
4
3
2
SW1
3
1
4
2
C
7914J-1-000E SW2
3
1
4
2
7914J-1-000E SW3
3
1
4
2
7914J-1-000E SW4
B
3
1
4
2
7914J-1-000E SW5
3
1
4
2
7914J-1-000E
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :USER_LED&PUSHBUTTON
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet 1
16 o f 18
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
52
Figure C-15. Pin Header Section-01
5
4
3
PIN HEADER SECTION -01
VCC_3V3
VCC_5V
JP9
1
2
D
4 BB_PWM_2 4 BB_PWM_4 4 BB_PWM_6 4 BB_ADC_2 4 BB_ADC_4 4 BB_ADC_6 4 BB_ADC_8
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BB_PWM_1 4 BB_PWM_3 4 BB_PWM_5 4 BB_PWM_7 4 BB_ADC_3 4 BB_ADC_5 4 BB_ADC_7 4
4,15 SPI0_CLK
19
20
SPI0_SS 4,15
HDR_2X10
VCC_3V3
VCC_5V
JP11
C
4,8 CAN7_WAKE 4,7 CAN5_RXD
4,7 CAN4_RXD 4 DEBUG_GPIO_3 4 DEBUG_GPIO_1 5,16 BB_USER_BUTTON_2 5,16 BB_USER_BUTTON_5 4,16 BB_USER_BUTTON_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CAN6_WAKE 4,8
CAN5_TXD 4,7 CAN4_TXD 4,7 DEBUG_GPIO_4 4
DEBUG_GPIO_2 4 BB_USER_BUTTON_1 5,16 BB_USER_BUTTON_3 5,16
HDR_2X10
VCC_5V
VCC_3V3
JP2
B
1
2
5,15 SPI0_WP 5,11 LIN2_RXD
3
4
5
6
7
8
SUPPLY_INH 5,14 LIN2_TXD 5,11
5,11 LIN2_WAKE 5,11 LIN3_RXD
9
10
11
12
LIN2_SLP 5,11 LIN3_TXD 5,11
5,11 LIN3_WAKE 5,12 LIN4_RXD
13
14
15
16
LIN3_SLP 5,11 LIN4_TXD 5,12
5,12 LIN4_WAKE 5 BB_I2C1_SCL
17
18
19
20
LIN4_SLP 5,12 BB_I2C1_SDA 5
HDR_2X10
A
5
4
3
Schematics of Base Board
2
1
VCC_3V3
VCC_5V
JP10
1
2
4 UART1_TX 4 UART1_CTS
4,6 CAN2_RXD
3
4
5
6
7
8
9
10
UART1_RX 4
UART1_RTS 4 CAN2_TXD 4,6
D
4,8 CAN_SPI1_SS1 4,6 CAN2_S
4,7 CAN4_S
4,9 CAN8_WAKE
11
12
13
14
15
16
17
18
19
20
CAN_SPI1_SS0 4,8 CAN_SPI1_SS2 4,9 CAN3_S 4,6
CAN5_S 4,7
CAN9_WAKE 4,9
HDR_2X10
VCC_5V
VCC_3V3
JP6
1
2
5,10 LIN1_SLP
3
4
5
6
LIN1_WAKE 5,10
C
5,6 CAN0_S 5,16 BB_USER_LED8
7
8
9
10
BB_USER_LED9 5,16 CAN1_RXD 5,6
5,6 CAN1_TXD 5,6 CAN0_RXD
5 BB_ADC_9 5,10 LIN1_RXD
5 BB_ADC_11
11
12
13
14
15
16
17
18
19
20
CAN1_S 5,6 CAN0_TXD 5,6 LIN1_TXD 5,10
BB_ADC_10 5
HDR_2X10
VCC_5V
VCC_3V3
JP1
1
2
B
5,10 LIN0_RXD
3
4
5
6
LIN0_TXD 5,10
5,10 LIN0_WAKE 5,15 CXPI_RXD 5,12 LIN5_RXD
7
8
9
10
11
12
LIN0_SLP 5,10 CXPI_TXD 5,15 LIN5_TXD 5,12
5,12 LIN5_WAKE
13
14
LIN5_SLP 5,12
5,15 CXPI_SELMS 5 BB_HPMC_2 5 BB_HPMC_1
15
16
17
18
19
20
CXPI_NSLP 5,15 BB_HPMC_3 5 BB_HPMC_4 5
HDR_2X10
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :PIN HEADER SECTION-01
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
17 o f 18
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
53
Figure C-16. Pin Header Section-02
5
4
PIN HEADER SECTION -02
VCC_5V
JP7
1
2
D
5 UART0_RX
3
4
5
6
5 UART0_RTS
5,16 BB_USER_LED7 5,16 BB_USER_LED3
5,15 BB_ADC_POT
5,16 BB_USER_LED2 5,16 BB_USER_LED6
5,15 CXPI_CLK
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC_3V3
UART0_CTS 5 UART0_TX 5
BB_USER_LED5 5,16 BB_USER_LED1 5,16 BB_ADC_1 5 BB_USER_LED4 5,16 BB_GPIO_37 5 BB_USER_LED0 4,16
HDR_2X10
VCC_3V3
VCC_5V
JP12
C
5,8,9 CAN_SPI1_MISO
1
2
3
4
5
6
SPI0_HOLD 5,15
5,8,9
CAN_SPI1_SCK 5 BB_GPIO_49 5 BB_GPIO_51
5 BB_GPIO_53 5 BB_GPIO_55
5 BB_PWM_8
5 BB_PWM_10
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CAN_SPI1_MOSI 5,8,9 BB_GPIO_48 5 BB_GPIO_50 5
BB_GPIO_52 5 BB_GPIO_54 5
BB_GPIO_56_RESET 5 BB_PWM_9 5
HDR_2X10
VCC_3V3
VCC_5V
JP8
1
2
B
4 BB_EXP1_GPIO_2 4 BB_EXP1_GPIO_4 4 BB_EXP1_GPIO_6 4 BB_EXP1_GPIO_8 4 BB_EXP1_GPIO_10 4 BB_EXP1_GPIO_12 4 BB_EXP1_GPIO_14 4 BB_EXP1_GPIO_16
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
BB_EXP1_GPIO_1 4 BB_EXP1_GPIO_3 4 BB_EXP1_GPIO_5 4 BB_EXP1_GPIO_7 4 BB_EXP1_GPIO_9 4 BB_EXP1_GPIO_11 4 BB_EXP1_GPIO_13 4 BB_EXP1_GPIO_15 4
HDR_2X10
A
5
4
Schematics of Base Board
3
2
1
VCC_5V
VCC_3V3
JP3
1
2
5 DEBUG_GPIO_5 5 DEBUG_GPIO_6 5 DEBUG_GPIO_7 5 DEBUG_GPIO_8 5 DEBUG_GPIO_9 5 DEBUG_GPIO_10 5 DEBUG_GPIO_11 5 DEBUG_GPIO_12
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SPI2_MISO 5
SPI2_MOSI 5 SPI2_CLK 5 SPI2_SS 5 CAN3_TXD 5,6 CAN3_RXD 5,6
SPI0_MOSI 5,15 SPI0_MISO 5,15
D
HDR_2X10
VCC_5V
VCC_3V3
JP4
1
2
5 DEBUG_GPIO_20 5 DEBUG_GPIO_18 5 DEBUG_GPIO_16 5 DEBUG_GPIO_14 5 DEBUG_GPIO_27 5 DEBUG_GPIO_25_W 5 DEBUG_GPIO_23 5 DEBUG_GPIO_21_W
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DEBUG_GPIO_19 5 DEBUG_GPIO_17 5 DEBUG_GPIO_15 5 DEBUG_GPIO_13 5 DEBUG_GPIO_26 5 DEBUG_GPIO_24 5 DEBUG_GPIO_22_W 5
C
HDR_2X10
VCC_5V
VCC_3V3
JP5
1
2
B
5 BB_EXP2_GPIO_2 5 BB_EXP2_GPIO_16 5 BB_EXP2_GPIO_14 5 BB_EXP2_GPIO_12 5 BB_EXP2_GPIO_10
5 BB_EXP2_GPIO_8 5 BB_EXP2_GPIO_6 5 BB_EXP2_GPIO_4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
BB_EXP2_GPIO_1 5 BB_EXP2_GPIO_15 5 BB_EXP2_GPIO_13 5 BB_EXP2_GPIO_11 5 BB_EXP2_GPIO_9 5 BB_EXP2_GPIO_7 5 BB_EXP2_GPIO_5 5 BB_EXP2_GPIO_3 5
HDR_2X10
CYPRESS SEMICONDUCTOR 198 CHAMPION COURT SAN JOSE, CA 95134 (408) 943-2600
A
CYPRESS SEMICONDUCTOR © 2019
SCH Title : TRAVEO II BASE BOARD
Page Title :PIN HEADER SECTION-02
Size Document Number Drawn By
Approved By
Rev
B
BALA K SHANTANU
A
Date: Wednesday, November 20, 2019
Sheet
18 o f 18
3
2
1
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
54
D. Component Assembly on Base Board
This appendix shows the top and bottom assembly of the PCB. Figure D-1. Top Assembly of the PCB
ART FILM - TASY
P3
J21
J22
P4
J28
J30
J36
J37
J44
P5
J51
J57
J58
J65
P2
J7
J8
J10
J11
R1 R4
R5
R6
R7 R11
P1 JP1
J6
J14
J9
J12
J13
J11
J19
J18
J17
J20
J26
J25
J24
J27
J16
J23
J31
J32
J33
J34
J35
JP6
R8
R9
R10
R12
J39
J40
J41
J42
J43
J49
J48
J47
J46
J50
J55
J54
J53
J56
J52
J62
J61
J59
J66
J60
J63
J68
J67
J73
J72
J71
J70
J45
RA3
RA2
RA1
LD3 LD4 LD5 LD6 LD7 LD8
LD9 LD10 LD11 LD12
R14
R15
R16
R17
R18
R19
JP2
JP3
JP4
JP5
R2 LD1 LD2 R3
TP2 TP4 TP3
J132 J133 J134
C1 C2
FL1 C3
J38
C4 C5 FL2 C6
JP7
J107
J119
J120
P10
J108
J91
J86
J81
J76
R101 R102 J77
J78
J83
J82
D1
J87
J88
R20
D2
D3
D4
J93
J92
J101
J97
J95
J99
J100
J98
J96
J103
J106
J104
J105
J94
J109
J110
J112
J113
J111
J117
J118
J116
J115
J121 J114
J123 J131
J122 J125
J124
TP9 TP10 TP11 TP12 TP7 TP8
J80 TP5
J89
TP6
J84
C8 C9
FL3 C10
P0T1
J102 RA5
RA4
SW2
SW3
SW4
SW5
SW6
J64 SW1
JP8
JP9
JP10
LD13 R21 LD16 LD17 LD18 LD19 LD13 LD15 LD14
JP11
LD20
JP12
P6
J69
J75
J79
P7
J85
J90
P8
P9
ART FILM - TASY
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
55
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
56
ART FILM - BASY
R13
R144 R141
R135
C89
C87
U20
R142
R136 R137
R138 C90
C88 U21
R139 R140
C83 C84
C85 C86
R143
U1
C7
R131 C82 R134
R130 C81 R133
R129
R128
C78
C80
R127
R126
R125
C77
C79
R124
U19
U18
C72 C73 C74 C75 C76 C64 FL5 C65
R122 R132
R119
C60 R123
R115
R114
R110
R106
R100
R96
R37
FL4
R80 D20 D19 D18 D17 D15 D13 D12 D11
R42
C61
R44
U2
R24 D6
R43
R59
R64
R69
R74
R85
R90
R120
C68C69 C66
R121
C70 C71 C67
U17
R118 R117 R116
C63 C62
C59 C58
C57 C56
U16
R113 R112 R111
U15
R109 R108 R107
U14
R105 R104 R103
C55 C54
C53 C52
U13
R99 R98
R97
C51 C50
U12
R95 R94
R93
R91
C49
R92 D25
D26
C48
U11
R88 R89
C46 C47
C45
R87 D24
C44
D23
U10
R86
R83 R82 R84
C42 C43
C41 C40
R79
R81
U9
C39
R77 D22 C38
D21
U8
R75
R72 R73
C36 C37
R60
R33
R51
U4
R54 R53
R55
R56
C28 C29
R65
C32 C33
R70
R40 R38 R35
R31 C17
R34
C35
R71 D16
C34
D14
U7
R67 R68
C31
R66 D10
C30
D9
U6
C27 R61 D8
C26 U5
R57
R46 C22
C24 C25
R58
R62 R63
R50
R49
R48 R47
R45
U3
R41 R39 R36
R32
R52 C23 R26
R29
C20 R27 D7
L3
R25
C12 C15
C14 L2
C13 C19
L1 C18
R23
D5 R22
C11 C16
R76 R78
R30
C21 R28
Figure D-2. Bottom Assembly of the PCB
ART FILM - BASY
Component Assembly on Base Board
Revision History
Document Revision History
Document Title: CYTVII-B-E-1M-176-CPU Evaluation Board User Guide
Document Number: 002-22883
Revision ECN# Issue Date
Description of Change
**
6186303 05/25/2018 New user guide for TVII CPU board.
Sunset Review
*A
6501207 03/05/2019
TVII-B-E-1M-176-CPU board user guide updated as per Rev C board designs. 1. Added 5 V and 3.3 V selectable power supply for CPU board using J23.
2.CPU board to base board pin connection are updated in Table 4-1.
Updated content in section 1. Introduction and 2. Overview.
Updated Figure 2-1 and Figure 3-1.
*B
6759586 12/23/2019 Updated A. Schematics of CPU Board, B. Component Assembly on CPU Board, C.
Schematics of Base Board, and D. Component Assembly on Base Board with text
searchable content.
*C
6785957 01/24/2020
Fixed Figure A-12. Updated content in section 2. Overview.
CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
57
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