AN332 Rev. 1.2 5 3. Terminology SEN—Serial enable pin, active low; used as device select in 3-wire and SPI operation and address selection in 2-wire operation. SDIO—Serial data in/data out pin. SCLK—Serial clock pin. RST or RSTb—Reset pin, active low RCLK—External reference clock GPO—General purpose output CTS—Clear to send
autotuning, and a value of 1–191 indicates a manual override. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit ...
2. Overview. This family of products is programmed using commands and responses. To perform an action, the system controller writes a command byte and associated...
AN332 Si47XX PROGRAMMING GUIDE 1. Introduction This document provides an overview of the programming requirements for the Si4704/05/06/07/1x/2x/3x/4x/84/85 FM transmitter/AM/FM/SW/LW/WB receiver. The hardware control interface and software commands are detailed along with several examples of the required steps to configure the device for various modes of operation. 2. Overview This family of products is programmed using commands and responses. To perform an action, the system controller writes a command byte and associated arguments, causing the device to execute the given command. The device will, in turn, provide a response depending on the type of command that was sent. Section "4. Commands and Responses" on page 6 and Section "5. Commands and Properties" on page 7 describe the procedures for using commands and responses and provide complete lists of commands, properties, and responses. The device has a slave control interface that allows the system controller to send commands to and receive responses from the device using one of three serial protocols (or bus modes): 2-wire mode (I2C and SMBUS compatible), 3-wire mode, or SPI mode. Section "6. Control Interface" on page 226 describes the control interface in detail. Section "7. Powerup" on page 234 describes options for the sequencing of VDD and VIO power supplies, selection of the desired bus mode, provision of the reference clock, RCLK, and sending of the POWER_UP command. Section "8. Powerdown" on page 241 describes sending the POWER_DOWN command and removing VDD and VIO power supplies as necessary. Section "9. Digital Audio Interface" on page 242 describes the digital audio format supported and how to operate the device in digital mode. Section "10. Timing" on page 245 describes the CTS (Clear to Send) timing indicating when the command has been accepted and in most cases completed execution, and the STC (Seek/Tune Complete) timing indicating when the Seek/Tune commands have completed execution. Section "11. FM Transmitter" on page 251 describes the audio dynamic range control, limiter, pre-emphasis, recommendations for maximizing audio volume for the FM transmitter. Section "12. Programming Examples" on page 255 provides flowcharts and step-by-step procedures for programming the device. Rev. 1.2 5/20 Copyright © 2020 by Silicon Laboratories AN332 AN332 Table 1. Product Family Function FM Transmitter FM Receiver AM Receiver SW/LW Receiver WB Receiver RDS High Performance RDS RPS SAME Digital Input Digital Output Embedded FM antenna AEC-Q100 Qualified Package Size (mm) Part Number General Description Si4700 FM Receiver 4x4 Si4701 FM Receiver with RDS 4x4 Si4702 FM Receiver 3x3 Si4703 FM Receiver with RDS 3x3 Si4704 FM Receiver Si4705 FM Receiver with RDS Si47063 High Performance RDS Receiver Si47073 WB Receiver with SAME 1 3x3 2 3x3 3x3 3x3 Si4708 FM Receiver 2.5x2.5 Si4709 FM Receiver with RDS Si47104 FM Transmitter 2.5x2.5 3x3 Si4711 FM Transmitter with RDS Si47124 FM Transmitter with RPS 3x3 3x3 Si4713 FM Transmitter with RDS & RPS Si47204 FM Transceiver 3x3 3x3 Si4721 FM Transceiver with RDS 3x3 Si4730 AM/FM Receiver 3x3 Si4731 AM/FM Receiver with RDS Si47325 AM/SW/LW/FM Receiver with RDS 2 3x3 SOIC16 Si4734 AM/SW/LW/FM Receiver 3x3 Si4735 AM/SW/LW/FM Receiver with RDS 2 3x3 Si4736 AM/FM/WB Receiver 3x3 Notes: 1. Digital Output is available in Si4704-D60 and later. 2. High Performance RDS is available in Si4705/31/35/85-D50 and later, Si4732. 3. Si4706, Si4707, and Si474x are covered under NDA. 4. There is an errata for the digital audio input for Si4710-B30, Si4712-B30, and Si4720-B20. A patch is available to enable digital audio input for these devices. Please contact Silicon Labs to request a patch. 5. Si4732-A10 has the same firmware FMRX component and AM_SW_LW RX component as that of Si4735-D60, so Si4732-A10 is considered as the most recent revision as D60, and the Si4735-D60 related descriptions in Appendix A and Appendix B also apply to Si4732-A10 if not specified. 2 Rev. 1.2 AN332 Table 1. Product Family Function (Continued) Si4737 AM/FM/WB Receiver with RDS 3x3 Si4738 FM/WB Receiver 3x3 Si4739 Si47403 Si47413 Si47423 Si47433 Si47443 Si47453 Si47493 FM/WB Receiver with RDS AM/FM Receiver AM/FM Receiver with RDS AM/LW/SW/FM/WB Receiver AM/LW/SW/FM/WB Receiver with RDS AM/LW/SW/FM Receiver AM/LW/SW/FM Receiver with RDS High-Performance RDS Receiver 3x3 4x4 4x4 4x4 4x4 4x4 4x4 4x4 Si4784 FM Receiver 3x3 Si4785 FM Receiver with RDS 2 3x3 Notes: 1. Digital Output is available in Si4704-D60 and later. 2. High Performance RDS is available in Si4705/31/35/85-D50 and later, Si4732. 3. Si4706, Si4707, and Si474x are covered under NDA. 4. There is an errata for the digital audio input for Si4710-B30, Si4712-B30, and Si4720-B20. A patch is available to enable digital audio input for these devices. Please contact Silicon Labs to request a patch. 5. Si4732-A10 has the same firmware FMRX component and AM_SW_LW RX component as that of Si4735-D60, so Si4732-A10 is considered as the most recent revision as D60, and the Si4735-D60 related descriptions in Appendix A and Appendix B also apply to Si4732-A10 if not specified. Rev. 1.2 3 AN332 TABLE OF CONTENTS Section Page 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4. Commands and Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5.1. Commands and Properties for the FM/RDS Transmitter (Si4710/11/12/13/20/21) . . .7 5.2. Commands and Properties for the FM/RDS Receiver (Si4704/05/06/2x/3x/4x/84/85) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3. Commands and Properties for the AM/SW/LW Receiver (Si4730/31/32/34/35/36/37/40/41/42/43/44/45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.4. Commands and Properties for the WB Receiver (Si4707/36/37/38/39/42/43) . . . . 174 5.5. Commands and Properties for the Stereo Audio ADC Mode (Si4704/05/30/31) . . 208 6. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.1. 2-Wire Control Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.2. 3-Wire Control Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 6.3. SPI Control Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7. Powerup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.1. Powerup from Device Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.2. Powerup from a Component Patch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 8. Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 10. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 11. FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.1. Audio Dynamic Range Control for FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 251 11.2. Audio Pre-emphasis for FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.3. Audio Limiter for FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.4. Maximizing Audio Volume for FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 12. Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.1. Programming Example for the FM/RDS Transmitter . . . . . . . . . . . . . . . . . . . . . . 255 12.2. Programming Example for the FM/RDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . 273 12.3. Programming Example for the AM/LW/SW Receiver . . . . . . . . . . . . . . . . . . . . . . 295 12.4. Programming Example for the WB/SAME Receiver . . . . . . . . . . . . . . . . . . . . . . . 305 Appendix A--Comparison of the Si4704/05/3x-B20, Si4704/05/3x-C40, and Si4704/05/3x-D60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Appendix B--Si4704/05/3x-B20/-C40/-D60 Compatibility Checklist . . . . . . . . . . . . . . . . 318 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 4 Rev. 1.2 AN332 3. Terminology SEN--Serial enable pin, active low; used as device select in 3-wire and SPI operation and address selection in 2-wire operation. SDIO--Serial data in/data out pin. SCLK--Serial clock pin. RST or RSTb--Reset pin, active low RCLK--External reference clock GPO--General purpose output CTS--Clear to send STC--Seek/Tune Complete NVM--Non-volatile internal device memory Device--Refers to the FM Transmitter/AM/FM/SW/LW/WB Receiver System Controller--Refers to the system microcontroller CMD--Command byte COMMANDn--Command register (16-bit) in 3-Wire mode (n = 1 to 4) ARGn--Argument byte (n = 1 to 7) STATUS--Status byte RESPn--Response byte (n = 1 to 15) RESPONSEn--Response register (16-bit) in 3-Wire mode (n = 1 to 8) Rev. 1.2 5 AN332 4. Commands and Responses Commands control actions, such as power up, power down, or tune to a frequency, and are one byte in size. Arguments are specific to a given command and are used to modify the command. For example, after the TX_TUNE_FREQ command, arguments are required to set the tune frequency. Arguments are one byte in size, and each command may require up to seven arguments. Responses provide the system controller status information and are returned after a command and its associated arguments are issued. All commands return a one byte status indicating interrupt state and clear-to-send the next command. Commands may return up to 15 additional response bytes. A complete list of commands is available in "5. Commands and Properties". Table 2 shows an example of tuning to a frequency using the TX_TUNE_FREQ command. This command requires that a command and three arguments be sent and returns one status byte. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS), or response (RESP). The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. Table 2. Using the TX_TUNE_FREQ Command Action CMD ARG1 ARG2 ARG3 STATUS Data 0x30 0x00 0x27 0x7E 0x80 Description TX_TUNE_FREQ Set Station to 101.1 MHz (0x277E = 10110 with 10 kHz step size) Reply Status. Clear-to-send high. Properties are special command arguments used to modify the default device operation and are generally configured immediately after power-up. Examples of properties are TX _PREEMPHASIS and REFCLK_FREQ. A complete list of properties is available in Section "5. Commands and Properties". Table 3 shows an example of setting the REFCLK frequency using the REFCLK_FREQ property by sending the SET_PROPERTY command and five argument bytes. ARG1 of the SET_PROPERTY command is always 0x00. ARG2 and ARG3 are used to select the property number, PROP (0x0201 in this example), and ARG4 and ARG5 are used to set the property value, PROPD (0x8000 or 32768 Hz in the example). Table 3. Using the SET_PROPERTY Command Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x02 0x01 0x80 0x00 0x80 Description SET_PROPERTY REFCLK_FREQ 32768 Hz Reply Status. Clear-to-send high. The implementation of the command and response procedures in the system controller differs for each of the three bus modes. Section "6. Control Interface" on page 226 details the required bit transactions on the control bus for each of the bus modes. 6 Rev. 1.2 AN332 5. Commands and Properties There are four different components for these product families: 1. FM Transmitter component 2. FM Receiver component 3. AM/SW/LW component 4. WB component The following four subsections list all the commands and properties used by each of the component. 5.1. Commands and Properties for the FM/RDS Transmitter (Si4710/11/12/13/20/21) The following two tables are the summary of the commands and properties for the FM/RDS Transmitter component applicable to Si4710/11/12/13/20/21. Table 4. FM/RDS Transmitter Command Summary Cmd Name Description Available In 0x01 POWER_UP Power up device and mode selection. Modes include FM transmit and analog/digital audio interface configuration. All 0x10 GET_REV Returns revision information on the device. All 0x11 POWER_DOWN Power down device. All 0x12 SET_PROPERTY Sets the value of a property. All 0x13 GET_PROPERTY Retrieves a property's value. All 0x14 GET_INT_STATUS Read interrupt status bits. All 0x15 PATCH_ARGS* Reserved command used for patch file downloads. All 0x16 PATCH_DATA* Reserved command used for patch file downloads. All 0x30 TX_TUNE_FREQ Tunes to given transmit frequency. All 0x31 TX_TUNE_POWER Sets the output power level and tunes the antenna capacitor. All 0x32 TX_TUNE_MEASURE Measure the received noise level at the specified frequency. Si4712/13/20 /21 0x33 TX_TUNE_STATUS Queries the status of a previously sent TX Tune Freq, TX Tune Power, or TX Tune Measure command. All 0x34 TX_ASQ_STATUS Queries the TX status and input audio signal metrics. All 0x35 TX_RDS_BUFF Queries the status of the RDS Group Buffer and loads new data into buffer. Si4711/13/21 0x36 TX_RDS_PS Set up default PS strings. Si4711/13/21 0x80 GPIO_CTL Configures GPO1, 2, and 3 as output or Hi-Z. All except Si4710-A10 0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high). All except Si4710-A10 *Note: Commands PATCH_ARGS and PATCH_DATA are only used to patch firmware. For information on applying a patch file, see "7.2. Powerup from a Component Patch" on page 236. Rev. 1.2 7 AN332 Table 5. FM Transmitter Property Summary Prop Name Description Default Available In 0x0001 0x0101 0x0103 0x0201 0x0202 0x2100 0x2101 0x2102 0x2103 0x2104 0x2105 0x2106 0x2107 GPO_IEN DIGITAL_INPUT _FORMAT1 DIGITAL_INPUT _SAMPLE_RATE1 REFCLK_FREQ REFCLK_PRESCALE TX_COMPONENT_ENABLE TX_AUDIO_DEVIATION TX_PILOT_DEVIATION TX_RDS_DEVIATION2 TX_LINE_INPUT_LEVEL TX_LINE_INPUT_MUTE TX_PREEMPHASIS TX_PILOT_FREQUENCY Enables interrupt sources. Configures the digital input format. Configures the digital input sample rate in 1 Hz steps. Default is 0. Sets frequency of the reference clock in Hz. The range is 31130 to 34406 Hz, or 0 to disable the AFC. Default is 32768 Hz. Sets the prescaler value for the reference clock. Enable transmit multiplex signal components. Default has pilot and L-R enabled. Configures audio frequency deviation level. Units are in 10 Hz increments. Default is 6825 (68.25 kHz). Configures pilot tone frequency deviation level. Units are in 10 Hz increments. Default is 675 (6.75 kHz) Configures the RDS/RBDS frequency deviation level. Units are in 10 Hz increments. Default is 2 kHz. Configures maximum analog line input level to the LIN/RIN pins to reach the maximum deviation level programmed into the audio deviation property TX Audio Deviation. Default is 636 mVPK. Sets line input mute. L and R inputs may be independently muted. Default is not muted. Configures pre-emphasis time constant. Default is 0 (75 µs). Configures the frequency of the stereo pilot. Default is 19000 Hz. 0x0000 0x0000 0x0000 0x8000 0x0001 0x0003 0x1AA9 0x02A3 0x00C8 0x327C 0x0000 0x0000 0x4A38 All All except Si4710-A10 All except Si4710-A10 All All All All All Si4711/13/21 All All All All Notes: 1. Digital Audio Input feature (property DIGITAL_INPUT_FORMAT and DIGITAL_INPUT_SAMPLE_RATE) is supported in FMTX component 2.0 or later. 2. RDS feature (command TX_RDS_BUFF, TX_RDS_PS and RDS properties 0x2103, 0x2C00 through 2C07) is supported in FMTX component 2.0 or later. 3. Limiter feature (LIMITEN bit in TX_ACOMP_ENABLE and property TX_LIMITER_RELEASE_TIME) is supported in FMTX component 2.0 or later. 8 Rev. 1.2 AN332 Table 5. FM Transmitter Property Summary (Continued) Prop Name Description Default Available In 0x2200 0x2201 0x2202 0x2203 0x2204 0x2205 0x2300 0x2301 0x2302 0x2303 0x2304 0x2C00 TX_ACOMP_ENABLE3 TX_ACOMP_THRESHOLD TX_ACOMP_ATTACK_TIME TX_ACOMP_RELEASE_TIME TX_ACOMP_GAIN TX_LIMITER_RELEASE_TIME3 TX_ASQ_INTERRUPT_SOURCE TX_ASQ_LEVEL_LOW TX_ASQ_DURATION_LOW TX_ASQ_LEVEL_HIGH TX_ASQ_DURATION_HIGH TX_RDS_INTERRUPT_SOURCE2 Enables audio dynamic range control and limiter. Default is 2 (limiter is enabled, audio dynamic range control is disabled). Sets the threshold level for audio dynamic range control. Default is 40 dB. Sets the attack time for audio dynamic range control. Default is 0 (0.5 ms). Sets the release time for audio dynamic range control. Default is 4 (1000 ms). Sets the gain for audio dynamic range control. Default is 15 dB. Sets the limiter release time. Default is 102 (5.01 ms) Configures measurements related to signal quality metrics. Default is none selected. Configures low audio input level detection threshold. This threshold can be used to detect silence on the incoming audio. Configures the duration which the input audio level must be below the low threshold in order to detect a low audio condition. Configures high audio input level detection threshold. This threshold can be used to detect activity on the incoming audio. Configures the duration which the input audio level must be above the high threshold in order to detect a high audio condition. Configure RDS interrupt sources. Default is none selected. 0x0002 0xFFD8 0x0000 0x0004 0x000F 0x0066 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 All All All All All All except Si4710-A10 All All All All All Si4711/13/21 Notes: 1. Digital Audio Input feature (property DIGITAL_INPUT_FORMAT and DIGITAL_INPUT_SAMPLE_RATE) is supported in FMTX component 2.0 or later. 2. RDS feature (command TX_RDS_BUFF, TX_RDS_PS and RDS properties 0x2103, 0x2C00 through 2C07) is supported in FMTX component 2.0 or later. 3. Limiter feature (LIMITEN bit in TX_ACOMP_ENABLE and property TX_LIMITER_RELEASE_TIME) is supported in FMTX component 2.0 or later. Rev. 1.2 9 AN332 Table 5. FM Transmitter Property Summary (Continued) Prop 0x2C01 Name TX_RDS_PI2 Description Default Available In Sets transmit RDS program identifier. 0x40A7 Si4711/13/21 0x2C02 0x2C03 0x2C04 0x2C05 0x2C06 0x2C07 TX_RDS_PS_MIX2 TX_RDS_PS_MISC2 TX_RDS_PS_REPEAT_COUNT2 TX_RDS_PS_MESSAGE_COUNT2 TX_RDS_PS_AF2 TX_RDS_FIFO_SIZE2 Configures mix of RDS PS Group with RDS Group Buffer. Miscellaneous bits to transmit along with RDS_PS Groups. Number of times to repeat transmission of a PS message before transmitting the next PS message. Number of PS messages in use. RDS Program Service Alternate Frequency. This provides the ability to inform the receiver of a single alternate frequency using AF Method A coding and is transmitted along with the RDS_PS Groups. Number of blocks reserved for the FIFO. Note that the value written must be one larger than the desired FIFO size. 0x0003 0x1008 0x0003 0x0001 0xE0E0 0x0000 Si4711/13/21 Si4711/13/21 Si4711/13/21 Si4711/13/21 Si4711/13/21 Si4711/13/21 Notes: 1. Digital Audio Input feature (property DIGITAL_INPUT_FORMAT and DIGITAL_INPUT_SAMPLE_RATE) is supported in FMTX component 2.0 or later. 2. RDS feature (command TX_RDS_BUFF, TX_RDS_PS and RDS properties 0x2103, 0x2C00 through 2C07) is supported in FMTX component 2.0 or later. 3. Limiter feature (LIMITEN bit in TX_ACOMP_ENABLE and property TX_LIMITER_RELEASE_TIME) is supported in FMTX component 2.0 or later. 10 Rev. 1.2 AN332 Bit STATUS D7 CTS D6 ERR Table 6. Status Response D5 D4 D3 X X X D2 RDSINT D1 ASQINT D0 STCINT Bit Name Function Clear to Send. 7 CTS 0 = Wait before sending next command. 1 = Clear to send next command. Error. 6 ERR 0 = No error 1 = Error 5:3 Reserved Values may vary. RDS Interrupt. 2 RDSINT 0 = RDS interrupt has not been triggered. 1 = RDS interrupt has been triggered. Signal Quality Interrupt. 1 ASQINT 0 = Signal quality measurement has not been triggered. 1 = Signal quality measurement has been triggered. Seek/Tune Complete Interrupt. 0 STCINT 0 = Tune complete has not been triggered. 1 = Tune complete has been triggered. Rev. 1.2 11 AN332 5.1.1. Commands and Properties for the FM/RDS Transmitter Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with Function = 15 (query library ID). The device will return the response, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with Function = 2 (transmit) and the patch may be applied. Only the STATUS byte will be returned in the response stream in transmit mode. The POWER_UP command configures the state of DIN (pin 13), DFS (pin 14), and RIN (pin 15) and LIN (pin 16) for analog or digital audio modes and GPO2/INT (pin 18) for interrupt operation. The command configures GPO2/INT interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g., FM TX to FM RX), issue the POWER_DOWN command to stop the current function; then, issue POWER_UP to start the new function. Note: Delay at least 500 ms between powerup command and first tune command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 2), Seven (FUNC = 15) Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit 1 7 1 6 1 5 Name CTSIEN GPO2OEN PATCH Function CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. GPO2 Output Enable. 0 = GPO2 output disabled, (Hi-Z). 1 = GPO2 output enabled. Patch Enable. 0 = Boot normally 1 = Copy non-volatile memory to RAM, but do not boot. After CTS has been set, RAM may be patched 12 Rev. 1.2 AN332 ARG Bit 1 4 1 3:0 2 7:0 Name XOSCEN FUNC[3:0] OPMODE[7:0] Function Crystal Oscillator Enable. 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crys- tal and OPMODE = 01010000). See Si47xx Data Sheet Application Schematic for external BOM details. Function. 01, 314 = Reserved. 2 = Transmit. 15 = Query Library ID. Application Setting 01010000 = Analog audio inputs (LIN/RIN) 00001111 = Digital audio inputs (DIN/DFS/DCLK) Response (to FUNC = 2, TX) Bit D7 D6 D5 D4 STATUS CTS ERR X X Response (to FUNC = 15, Query Library ID) D3 D2 D1 D0 X RDSINT ASQINT STCINT Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 D6 D5 D4 D3 D2 D1 D0 CTS ERR X X X RDSINT ASQINT STCINT PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] Function Final 2 digits of part number. Firmware Major Revision. Firmware Minor Revision. Reserved, various values. Reserved, various values. Chip Revision. Library Revision. Rev. 1.2 13 AN332 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Eight Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESP5 RESP6 PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 8 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] Function Final 2 digits of Part Number Firmware Major Revision Firmware Minor Revision Patch ID High Byte Patch ID Low Byte Component Major Revision Component Minor Revision Chip Revision 14 Rev. 1.2 AN332 Command 0x11. POWER_DOWN Moves the device from powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: In FMTX component 1.0 and 2.0, a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 DIN, DFS, RIN, LIN = HiZ Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 0 0 0 1 0 D2 D1 D0 0 0 1 Response Bit D7 D6 D5 D4 STATUS CTS ERR X X D3 D2 D1 D0 X RDSINT ASQINT STCINT Rev. 1.2 15 AN332 Command 0x12. SET_PROPERTY Sets a property shown in Table 5, "FM Transmitter Property Summary," on page 8. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. See Figure 30, "CTS and SET_PROPERTY Command Complete tCOMP Timing Model," on page 246 and Table 49, "Command Timing Parameters for the FM Transmitter," on page 247. Available in: All Command Arguments: Five Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] PROPDH[7:0] PROPDL[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 Response Bit STATUS Name Reserved PROPH[7:0] PROPL[7:0] PROPDH[7:0] PROPDL[7:0] Function Always write to 0. Property High Byte. This byte in combination with PROPL is used to specify the property to modify. See Section "5.1.2. FM/RDS Transmitter Properties" on page 31. Property Low Byte. This byte in combination with PROPH is used to specify the property to modify. See Section "5.1.2. FM/RDS Transmitter Properties" on page 31. Property Value High Byte. This byte in combination with PROPVL is used to set the property value. See Section "5.1.2. FM/RDS Transmitter Properties" on page 31. Property Value Low Byte. This byte in combination with PROPVH is used to set the property value. See Section "5.1.2. FM/RDS Transmitter Properties" on page 31. D7 D6 D5 D4 CTS ERR X X D3 D2 D1 D0 X RDSINT ASQINT STCINT 16 Rev. 1.2 AN332 Command 0x13. GET_PROPERTY Gets a property shown in Table 5, "FM Transmitter Property Summary," on page 8. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 Response Name Reserved PROPH[7:0] PROPL[7:0] Function Always write to 0. Property Get High Byte. This byte in combination with PROPL is used to specify the property to get. Property Get Low Byte. This byte in combination with PROPH is used to specify the property to get. Bit D7 D6 D5 STATUS CTS ERR X RESP1 X X X RESP2 RESP3 D4 D3 X X X X PROPDH[7:0] PROPDL[7:0] D2 RDSINT X D1 ASQINT X D0 STCINT X RESP Bit 1 7:0 2 7:0 3 7:0 Name Reserved PROPDH[7:0] PROPDL[7:0] Function Reserved, various values. Property Value High Byte. This byte in combination with PROPVL will represent the requested property value. Property Value High Byte. This byte in combination with PROPVH will represent the requested property value. Rev. 1.2 17 AN332 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command should be called after any command that sets the STCINT, ASQINT, or RDSINT bits. When polling this command should be periodically called to monitor the STATUS byte, and when using interrupts, this command should be called after the interrupt is set to update the STATUS byte. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 0 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT 18 Rev. 1.2 AN332 Command 0x30. TX_TUNE_FREQ Sets the state of the RF carrier and sets the tuning frequency between 76 and 108 MHz in 10 kHz units and steps of 50 kHz. For example 76.05 MHz = 7605 is valid because it follows the 50 kHz step requirement but 76.01 MHz = 7601 is not valid. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 49, "Command Timing Parameters for the FM Transmitter," on page 247. Available in: All Command arguments: Three Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 FREQH[7:0] FREQL[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 Response Bit STATUS Name Reserved FREQH[7:0] FREQL[7:0] Function Always write to 0. Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in units of 10 kHz. The valid range is from 7600 to 10800 (76108 MHz). The frequency must be a multiple of 50 kHz. Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in units of 10 kHz. The valid range is from 7600 to 10800 (76108 MHz). The frequency must be a multiple of 50 kHz. D7 D6 D5 D4 CTS ERR X X D3 D2 D1 D0 X RDSINT ASQINT STCINT Rev. 1.2 19 AN332 Command 0x31. TX_TUNE_POWER Sets the RF voltage level between 88 dBµV and 115 dBµV in 1 dB units. Power may be set as high as 120 dBµV; however, voltage accuracy is not guaranteed. A value of 0x00 indicates off. The command also sets the antenna tuning capacitance. A value of 0 indicates autotuning, and a value of 1191 indicates a manual override. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 49, "Command Timing Parameters for the FM Transmitter," on page 247. Available in: All Command arguments: Four Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFdBµV[7:0] ANTCAP[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 4 7:0 Response Bit STATUS Name Reserved Reserved RFdBµV[7:0] ANTCAP[7:0] Function Always write to 0. Always write to 0. Tune Power Byte. Sets the tune power in dBµV in 1 dB steps. The valid range is from 88 115 dBµV. Power may be set as high as 120 dBµV; however, voltage accuracy is not guaranteed. Antenna Tuning Capacitor. This selects the value of the antenna tuning capacitor manually, or automatically if set to zero. The valid range is 0 to 191, which results in a tuning capacitance of 0.25 pF x ANTCAP. D7 D6 D5 D4 CTS ERR X X D3 D2 D1 D0 X RDSINT ASQINT STCINT 20 Rev. 1.2 AN332 Command 0x32. TX_TUNE_MEASURE Enters receive mode (disables transmitter output power) and measures the received noise level (RNL) in units of dBµV on the selected frequency. The command sets the tuning frequency between 76 and 108 MHz in 10 kHz units and steps of 50 kHz. For example 76.05 MHz = 7605 is valid because it follows the 50 kHz step requirement but 76.01 MHz = 7601 is not valid. The command also sets the antenna tuning capacitance. A value of 0 indicates autotuning, and a value of 1191 indicates a manual override. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 49, "Command Timing Parameters for the FM Transmitter," on page 247. Available in: Si4712/13/20/21 Command arguments: Four Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 FREQH[7:0] FREQL[7:0] ANTCAP[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 4 7:0 Response Bit STATUS Name Reserved FREQH[7:0] FREQL[7:0] ANTCAP[7:0] Function Always write to 0. Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in units of 10 kHz. In FM mode the valid range is from 7600 to 10800 (76108 MHz). The frequency must be a multiple of 50 kHz. Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in units of 10 kHz. In FM mode the valid range is from 7600 to 10800 (76108 MHz). The frequency must be a multiple of 50 kHz. Antenna Tuning Capacitor. This selects the value of the antenna tuning capacitor manually, or automatic if set to zero. The valid range is 0191. D7 D6 D5 D4 CTS ERR X X D3 D2 D1 D0 X RDSINT ASQINT STCINT Rev. 1.2 21 AN332 Command 0x33. TX_TUNE_STATUS Returns the status of the TX_TUNE_FREQ, TX_TUNE_MEASURE, or TX_TUNE_POWER commands. The command returns the current frequency, output voltage in dBµV (if applicable), the antenna tuning capacitance value (0191) and the received noise level (if applicable). The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 INTACK ARG Bit 1 7:1 1 0 Name Reserved INTACK Function Always write to 0. Seek/Tune Interrupt Clear. If set this bit clears the seek/tune complete interrupt status indicator. Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 CTS X X D6 ERR X X D5 D4 D3 D2 D1 D0 X X X RDSINT ASQINT STCINT X X X X X X READFREQH[7:0] READFREQL[7:0] X X X X X X READRFdBµV[7:0] READANTCAP[7:0] RNL[7:0] 22 Rev. 1.2 AN332 RESP 1 2 3 4 5 6 7 Bit Name Function 7:0 Reserved Returns various data. Read Frequency High Byte. 7:0 READFREQH[7:0] This byte in combination with READFREQL returns frequency being tuned. 7:0 READFREQL[7:0] Read Frequency Low Byte. This byte in combination with READFREQH returns frequency being tuned. 7:0 Reserved Returns various data. 7:0 READRFdBµV[7:0] Read Power. Returns the transmit output voltage setting. 7:0 READANTCAP [7:0] Read Antenna Tuning Capacitor. This byte will contain the current antenna tuning capacitor value. Read Received Noise Level (Si4712/13 Only). This byte will contain the receive level as the response to a TX Tune Mea- 7:0 RNL[7:0] sure command. The returned value will be the last RNL measurement (or 0 if no measurement has been performed) for the TX Tune Freq and TX Tune Power commands. Rev. 1.2 23 AN332 Command 0x34. TX_ASQ_STATUS Returns status information about the audio signal quality and current FM transmit frequency. This command can be used to check if the input audio stream is below a low threshold as reported by the IALL bit, or above a high threshold as reported by the IALH bit. The thresholds can be configured to detect a silence condition or an activity condition which can then be used by the host to take an appropriate action such as turning off the carrier in the case of prolonged silence. The thresholds are set using the TX_ASQ_LEVEL_LOW and TX_ASQ_LEVEL_HIGH properties. The audio must be above or below the threshold for greater than the amount of time specified in the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH properties for the status to be detected. Additionally the command can be used to determine if an overmodulation condition has occurred or the limiter has engaged, as reported by the OVERMOD bit, in which case the host could reduce the audio level to the part. If any of the OVERMOD, IALH, or IALL bits are set, the ASQINT bit will also be set. The ASQINT bit can be routed to a hardware interrupt via the GPO_IEN property. Clearing the IALH or IALL interrupts will result in the TX_ASQ_DURATION_LOW or TX_ASQ_DURATION_HIGH counters being rearmed, respectively, to start another detection interval measurement. The command clears the ASQINT interrupt bit and OVERMOD, IALH, and IALL bits when the INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE. Available in: All Command arguments: One Response bytes: Four Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 INTACK ARG Bit 1 0 Name INTACK Function Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears ASQINT, OVERMOD, IALDH, and IALDL. 24 Rev. 1.2 Response Bit D7 D6 D5 STATUS CTS ERR X RESP1 X X X RESP2 X X X RESP3 X X X RESP4 AN332 D4 D3 X X X X X X X X INLEVEL[7:0] D2 D1 RDSINT OVERMOD X X ASQINT IALH X X D0 STCINT IALL X X RESP Bit 1 2 1 1 1 0 2 7:0 3 7:0 4 7:0 Name OVERMOD IALH IALL Reserved Reserved INLEVEL[7:0] Function Overmodulation Detection. 0 = Output signal is below requested modulation level. 1 = Output signal is above requested modulation level. Input Audio Level Threshold Detect High. 0 = Input audio level high threshold not exceeded. 1 = Input audio level high threshold exceeded. Input Audio Level Threshold Detect Low. 0 = Input audio level low threshold not exceeded. 1 = Input audio level low threshold exceeded. Returns various values. Returns various values. Input Audio Level. The current audio input level measured in dBfs (2s complement notation). Rev. 1.2 25 AN332 Command 0x35. TX_RDS_BUFF Loads or clears the RDS group buffer FIFO or circular buffer and returns the FIFO status. The buffer can be allocated between the circular buffer and FIFO with the TX_RDS_FIFO_SIZE property. A common use case for the circular buffer is to broadcast group 2A radio text, and a common use case for the FIFO is to broadcast group 4A real time clock. The command clears the INTACK interrupt bit when the INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: TX_RDS_BUFF is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Command arguments: Seven Response bytes: Five Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 1 0 1 FIFO 0 0 0 0 LDBUFF MTBUFF INTACK RDSBH[7:0] RDSBL[7:0] RDSCH[7:0] RDSCL[7:0] RDSDH[7:0] RDSDL[7:0] ARG Bit 1 7 1 6:3 1 2 1 1 1 0 2 7:0 Name FIFO Reserved LDBUFF MTBUFF INTACK RDSBH[7:0] Function Operate on FIFO. If set, the command operates on the FIFO buffer. If cleared, the command operates on the circular buffer. Always write to 0. Load RDS Group Buffer. If set, loads the RDS group buffer with RDSB, RDSC, and RDSD. Block A data is generated from the RDS_TX_PI property when the buffer is transmitted. Empty RDS Group Buffer. If set, empties the RDS group buffer. Clear RDS Group buffer interrupt. If set this bit clears the RDS group buffer interrupt indicator. RDS Block B High Byte. This byte in combination with RDSBL sets the RDS block B data. 26 Rev. 1.2 AN332 ARG Bit 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 Response Name RDSBL[7:0] RDSCH[7:0] RDSCL[7:0] RDSDH[7:0] RDSDL[7:0] Function RDS Block B Low Byte. This byte in combination with RDSBH sets the RDS block B data. RDS Block C High Byte. This byte in combination with RDSCL sets the RDS block C data. RDS Block C Low Byte. This byte in combination with RDSCH sets the RDS block C data. RDS Block D High Byte. This byte in combination with RDSDL sets the RDS block D data. RDS Block D Low Byte. This byte in combination with RDSDH sets the RDS block D data. Bit D7 D6 D5 D4 STATUS CTS ERR X X RESP1 X X X RDSPSXMIT RESP2 RESP3 RESP4 RESP5 D3 D2 X RDSINT CBUFXMIT FIFOXMIT CBAVAIL[7:0] CBUSED[7:0] FIFOAVAIL[7:0] FIFOUSED[7:0] D1 ASQINT CBUFWRAP D0 STCINT FIFOMT RESP Bit 1 7:5 1 4 1 3 1 2 1 1 1 0 2 7:0 3 7:0 4 7:0 5 7:0 Name Reserved RDSPSXMIT CBUFXMIT FIFOXMIT CBUFWRAP FIFOMT CBAVAIL[7:0] CBUSED[7:0] FIFOAVAIL[7:0] FIFOUSED[7:0] Function Values may vary. Interrupt source: RDS PS Group has been transmitted. Interrupt source: RDS Group has been transmitted from the FIFO buffer. Interrupt source: RDS Group has been transmitted from the circular buffer. Interrupt source: RDS Group Circular Buffer has wrapped. Interrupt source: RDS Group FIFO Buffer is empty. Returns the number of available Circular Buffer blocks. Returns the number of used Circular Buffer blocks. Returns the number of available FIFO blocks. Returns the number of used FIFO blocks. Rev. 1.2 27 AN332 Command 0x36. TX_RDS_PS Loads or clears the program service buffer. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: TX_RDS_PS is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Command arguments: Five Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 1 1 0 0 0 0 PSID[4:0] PSCHAR0 [7:0] PSCHAR1 [7:0] PSCHAR2 [7:0] PSCHAR3 [7:0] ARG Bit 1 7:5 1 4:0 2 7:0 3 7:0 4 7:0 5 7:0 Response Bit STATUS Name Reserved PSID[4:0] PSCHAR0[7:0] PSCHAR1[7:0] PSCHAR2[7:0] PSCHAR3[7:0] Function Always write to 0. Selects which PS data to load (023) 0 = First 4 characters of PS0. 1 = Last 4 characters of PS0. 2 = First 4 characters of PS1. 3 = Last 4 characters of PS1. ...22 = First 4 characters of PS11. 23 = Last 4 characters of PS11. RDS PSID CHAR0. First character of selected PSID. RDS PSID CHAR1. Second character of selected PSID. RDS PSID CHAR2. Third character of selected PSID. RDS PSID CHAR3. Fourth character of selected PSID. D7 D6 D5 D4 CTS ERR X X D3 D2 D1 D0 X RDSINT ASQINT STCINT 28 Rev. 1.2 AN332 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (high or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 1. GPIO_CTL is fully supported in FMTX component 3.0 or later. Only bit GPO3OEN is supported in FMTX comp 2.0. 2. The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Name Reserved GPO3OEN GPO2OEN GPO1OEN Reserved Function Always write 0. GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. Always write 0. Bit D7 D6 D5 D4 STATUS CTS ERR X X D3 D2 X RDSINT D1 ASQINT D0 STCINT Rev. 1.2 29 AN332 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Note: GPIO_SET is fully-supported in FMTX comp 3.0 or later. Only bit GPO3LEVEL is supported in FMTX comp 2.0. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Bit D7 CMD 1 ARG1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Bit STATUS Name Reserved GPO3LEVEL GPO2LEVEL GPO1LEVEL Reserved Always write 0. GPO3 Output Level. 0 = Output low (default). 1 = Output high. GPO3 Output Level. 0 = Output low (default). 1 = Output high. GPO3 Output Level. 0 = Output low (default). 1 = Output high. Always write 0. Function D7 D6 D5 D4 CTS ERR X X D3 D2 X RDSINT D1 ASQINT D0 STCINT 30 Rev. 1.2 5.1.2. FM/RDS Transmitter Properties AN332 Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RDSINT, ASQINT, and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading the this property and modified by writing this property. This property may only be set or read when in powerup mode. The default is no interrupts enabled. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 RDSREP ASQREP STCREP CTSIEN ERRIEN 0 0 0 RDSIEN ASQIEN STCIEN Bit 15:11 10 9 8 7 6 5:3 2 1 0 Name Reserved RDSREP ASQREP STCREP CTSIEN ERRIEN Reserved RDSIEN ASQIEN STCIEN Function Always write to 0. RDS Interrupt Repeat. (Si4711/13/21 Only) 0 = No interrupt generated when RDSINT is already set (default). 1 = Interrupt generated even if RDSINT is already set. ASQ Interrupt Repeat. 0 = No interrupt generated when ASQREP is already set (default). 1 = Interrupt generated even if ASQREP is already set. STC Interrupt Repeat. 0 = No interrupt generated when STCREP is already set (default). 1 = Interrupt generated even if STCREP is already set. CTS Interrupt Enable. 0 = No interrupt generated when CTS is set (default). 1 = Interrupt generated when CTS is set. After PowerUp, this bit will reflect the CTSIEN bit in ARG1 of PowerUp Command. ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. Always write to 0. RDS Interrupt Enable (Si4711/13/21 Only). 0 = No interrupt generated when RDSINT is set (default). 1 = Interrupt generated when RDSINT is set. Audio Signal Quality Interrupt Enable. 0 = No interrupt generated when ASQINT is set (default). 1 = Interrupt generated when ASQINT is set. Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when STCINT is set (default). 1 = Interrupt generated when STCINT is set. Rev. 1.2 31 AN332 Property 0x0101. DIGITAL_INPUT_FORMAT Configures the digital input format. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: DIGITAL_INPUT_FORMAT is supported in FMTX component 2.0 or later. Available in: All except Si4710-A10 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 IFALL IMODE[3:0] IMONO ISIZE[1:0] Bit Name Function 15:8 Reserved Always write to 0. DCLK Falling Edge. 7 IFALL 0 = Sample on DCLK rising edge (default). 1 = Sample on DCLK falling edge. Digital Mode. 0000 = default 6:3 IMODE[3:0] 0001 = I2S Mode. 0111 = Left-justified mode. 1101 = MSB at 1st DCLK rising edge after DFS Pulse. 1001 = MSB at 2nd DCLK rising edge after DFS Pulse. Mono Audio Mode. 2 IMONO 0 = Stereo audio mode (default). 1 = Mono audio mode. Digital Audio Sample Precision. 00 = 6 bits (default) 1:0 ISIZE[1:0] 01 = 20 bits 10 = 24 bits 11 = 8 bits 32 Rev. 1.2 AN332 Property 0x0103. DIGITAL_INPUT_SAMPLE_RATE Configures the digital input sample rate in 1 Hz units. The input sample rate must be set to 0 before removing the DCLK input or reducing the DCLK frequency below 2 MHz. If this guideline is not followed, a device reset will be required. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. TX_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_INPUT_SAMPLE_RATE is supported in FMTX component 2.0 or later. Available in: All except Si4710-A10 Default: 0x0000 Units: 1 Hz Step: 1 Hz Range: 0, 32000-48000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name DISR[15:0] Bit Name Function Digital Input Sample Rate. 15:0 DISR 0 = Disabled. Required before removing DCLK or reducing DCLK frequency below 2 MHz. The range is 3200048000 Hz. Rev. 1.2 33 AN332 Property 0x0201. REFCLK_FREQ Sets the frequency of the REFCLK from the output of the prescaler. (Figure 1 shows the relation between RCLK and REFCLK.) The REFCLK range is 31130 to 34406 Hz (32768 ±5% Hz) in 1 Hz steps, or 0 (to disable AFC). For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz REFCLK. The reference clock frequency property would then need to be set to 32500 Hz. RCLK frequencies between 31130 Hz and 40 MHz are supported, however, there are gaps in frequency coverage for prescaler values ranging from 1 to 10, or frequencies up to 311300 Hz. Table 7 summarizes these RCLK gaps. PIN 9 RCLK 31.130 kHz 40 MHz Prescaler Divide by 1-4095 REFCLK 31.130 kHz 34.406 kHz Figure 1. REFCLK Prescaler Table 7. RCLK Gaps Prescaler 1 2 3 4 5 6 7 8 9 10 RCLK Low (Hz) 31130 62260 93390 124520 155650 186780 217910 249040 280170 311300 RCLK High (Hz) 34406 68812 103218 137624 172030 206436 240842 275248 309654 344060 The RCLK must be valid 10 ns before and 10 ns after sending the TX_TUNE_MEASURE, TX_TUNE_FREQ, or TX_TUNE_POWER commands. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 32768 Hz. Available in: All Default: 0x8000 (32768) Units: 1 Hz Step: 1 Hz Range: 3113034406 34 Rev. 1.2 AN332 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF[15:0] Bit Name Function Frequency of Reference Clock in Hz. 15:0 REFCLKF[15:0] The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 ±5%), or 0 (to disable AFC). Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before and 10 ns after sending the TX_TUNE_MEASURE, TX_TUNE_FREQ, or TX_TUNE_POWER commands. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 14095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLK SEL RCLKP[11:0] Bit 15:13 12 11:0 Name Reserved RCLKSEL REFCLKP[11:0] Function Always write to 0. RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. Prescaler for Reference Clock. Integer number used to divide the RCLK frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 ±5%), or 0 (to disable AFC). Rev. 1.2 35 AN332 Property 0x2100. TX_COMPONENT_ENABLE Individually enables the stereo pilot, left minus right stereo and RDS components. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is stereo pilot and left minus right stereo components enabled. Available in: All Default: 0x0003 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 RDS LMR PILOT Bit Name Function 15:3 Reserved Always write 0. RDS Enable (Si4711/13/21 Only). 2 RDS 0 = Disables RDS (default). 1 = Enables RDS to be transmitted. Left Minus Right. 1 LMR 0 = Disables Left Minus Right. 1 = Enables Left minus Right (Stereo) to be transmitted (default). Pilot Tone. 0 PILOT 0 = Disables Pilot. 1 = Enables the Pilot tone to be transmitted (default). Property 0x2101. TX_AUDIO_DEVIATION Sets the transmit audio deviation from 0 to 90 kHz in 10 Hz units. The sum of the audio deviation, pilot deviation and RDS deviation should not exceed regulatory requirements, typically 75 kHz. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 6825, or 68.25 kHz. Available in: All Default: 0x1AA9 (6825) Units: 10 Hz Step: 10 Hz Range: 09000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name TXADEV[15:0] Bit Name Function Transmit Audio Frequency Deviation. 15:0 TXADEV[15:0] Audio frequency deviation is programmable from 0 Hz to 90 kHz in 10 Hz units. Default is 6825 (68.25 kHz). Note that the total deviation of the audio, pilot, and RDS must be less than 75 kHz to meet regulatory requirements. 36 Rev. 1.2 AN332 Property 0x2102. TX_PILOT_DEVIATION Sets the transmit pilot deviation from 0 to 90 kHz in 10 Hz units. The sum of the audio deviation, pilot deviation and RDS deviation should not exceed regulatory requirements, typically 75 kHz. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 675, or 6.75 kHz. Available in: All Default: 0x02A3 (675) Units: 10 Hz Step: 10 Hz Range: 09000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name TXPDEV[15:0] Bit Name Function Transmit Pilot Frequency Deviation. 15:0 TXPDEV[15:0] Pilot tone frequency deviation is programmable from 0 Hz to 90 kHz in 10 Hz units. Default is 675 (6.75 kHz). Note that the total deviation of the audio, pilot, and RDS must be less than 75 kHz to meet regulatory requirements. Property 0x2103. TX_RDS_DEVIATION Sets the RDS deviation from 0 to 7.5 kHz in 10 Hz units. The sum of the audio deviation, pilot deviation and RDS deviation should not exceed regulatory requirements, typically 75 kHz. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 200, or 2 kHz. Available in: Si4711/13/21 Default: 0x00C8 (200) Units: 10 Hz Step: 10 Hz Range: 09000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name TXRDEV[15:0] Bit Name Function Transmit RDS Frequency Deviation. 15:0 TXRDEV[15:0] RDS frequency deviation is programmable from 0 Hz to 90 kHz in 10 Hz units. Default is 200 (2 kHz). Note that the total deviation of the audio, pilot, and RDS must be less than 75 kHz to meet regulatory requirements. Rev. 1.2 37 AN332 Property 0x2104. TX_LINE_INPUT_LEVEL Sets the input resistance and maximum audio input level for the LIN/RIN pins. An application providing a 150 mVPK input to the device on RIN/LIN would set Line Attenuation = 00, resulting in a maximum permissible input level of 190 mVPK on LIN/RIN and an input resistance of 396 k. The Line Level would be set to 150 mV to correspond to the TX audio deviation level set by the TX_AUDIO_DEVIATION property. An application providing a 1 VPK input to the device on RIN/LIN would set Line Attenuation = 11, resulting in a maximum permissible input level of 636 mVPK on LIN/RIN and an input resistance of 60 k. An external series resistor on LIN and RIN inputs of 40 k would create a resistive voltage divider that would keep the maximum line level on RIN/LIN below 636 mVPK. The Line Level would be set to 636 mVPK to correspond to the TX audio deviation level set by the TX_AUDIO_DEVIATION property. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default input level and peak line level is 636 mVPK with an input impedance of 60 k. Available in: All Default: 0x327C Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 LIATTEN[1:0] 0 0 LILEVEL[9:0] Bit 15:14 13:12 11:10 9:0 Name Reserved LIATTEN[1:0] Reserved LILEVEL[9:0] Function Always write to 0. Line Attenuation. 00 = Max input level = 190 mVPK; input resistance = 396 k 01 = Max input level = 301 mVPK; input resistance = 100 k 10 = Max input level = 416 mVPK; input resistance = 74 k 11 = Max input level = 636 mVPK; input resistance = 60 k(default) Always write to 0. Line Level. Maximum line amplitude level on the LIN/RIN pins in mVPK. The default is 0x27C or 636 mVPK. 38 Rev. 1.2 AN332 Property 0x2105. TX_LINE_INPUT_MUTE Selectively mutes the left and right audio inputs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIMUTE RIMUTE Bit Name 15:2 Reserved Always write to 0. Mutes L Line Input. 1 LIMUTE 0 = No mute (default) 1 = Mute Mutes R Line Input. 0 RIMUTE 0 = No mute (default) 1 = Mute Function Property 0x2106. TX_PREEMPHASIS Sets the transmit pre-emphasis to 50 µs, 75 µs or off. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 75 µs. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMPE[1:0] Bit Name Function 15:2 Reserved Always write to 0. FM Pre-Emphasis. 00 = 75 µs. Used in USA (default) 1:0 FMPE[1:0] 01 = 50 µs. Used in Europe, Australia, Japan 10 = Disabled 11 = Reserved Rev. 1.2 39 AN332 Property 0x2107. TX_PILOT_FREQUENCY This property is used to set the frequency of the stereo pilot in 1 Hz steps. The stereo pilot is nominally set to 19 kHz for stereo operation, however the pilot can be set to any frequency from 0 Hz to 19 kHz to support the generation of an audible test tone. The pilot tone is enabled by setting the PILOT bit (D0) of the TX_COMPONENT_ENABLE property. When using the stereo pilot as an audible test generator it is recommended that the RDS bit (D2) be disabled. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x4A38 (19000) Units: 1 Hz Step: 1 Hz Range: 019000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FREQ[15:0] Bit Name Function Stereo Pilot Frequency 15:0 FREQ Sets the frequency of the stereo pilot in 1 Hz steps. Range 0 Hz19000 Hz (default is 0x4A38 or 19 kHz). Property 0x2200. TX_ACOMP_ENABLE Selectively enables the audio dynamic range control and limiter. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is limiter enabled and audio dynamic range control disabled. Note: LIMITEN bit is supported in FMTX component 2.0 or later. Reset this bit to 0 in FMTX component 1.0. Available in: All Default: 0x0002 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIMITEN ACEN Bit Name Function 15:2 Reserved Always write to 0. Audio Limiter. 1 LIMITEN 0 = Disable 1 = Enable (default) Transmit Audio Dynamic Range Control Enable. 0 ACEN 0 = Audio dynamic range control disabled (default) 1 = Audio dynamic range control enabled 40 Rev. 1.2 AN332 Property 0x2201. TX_ACOMP_THRESHOLD Sets the threshold for audio dynamic range control from 0 dBFS to 40 dBFS in 1 dB units in 2's complement notation. For example, a setting of 40 dB would be 65536 40 = 65496 = 0xFFD8. The threshold is the level below which the device applies the gain set by the TX_ACOMP_GAIN property, and above which the device applies the compression defined by (gain + threshold) / threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0xFFD8, or 40 dBFS. Available in: All Default: 0xFFD8 (40) Units: 1 dB Step: 1 dB Range: 40 to 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name THRESHOLD[15:0] Bit Name Function Transmit Audio Dynamic Range Control Threshold. 15:0 THRESHOLD[15:0] Range is from 40 to 0 dBFS in 1 dB steps (0xFFD80x0). Default is 0xFFD8 (40 dBFS). Rev. 1.2 41 AN332 Property 0x2202. TX_ACOMP_ATTACK_TIME Sets the time required for the device to respond to audio level transitions from below the threshold in the gain region to above the threshold in the compression region. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0.5 ms, or 0. Available in: All Default: 0x0000 Range: 09 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 ATTACK[3:0] Bit Name Function 15:4 Reserved Always write to 0. Transmit Audio Dynamic Range Control Attack Time. 0 = 0.5 ms (default) 1 = 1.0 ms 2 = 1.5 ms 3 = 2.0 ms 3:0 ATTACK[3:0] 4 = 2.5 ms 5 = 3.0 ms 6 = 3.5 ms 7 = 4.0 ms 8 = 4.5 ms 9 = 5.0 ms 42 Rev. 1.2 Property 0x2203. TX_ACOMP_RELEASE_TIME AN332 Sets the time required for the device to respond to audio level transitions from above the threshold in the compression region to below the threshold in the gain region. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1000 ms, or 4. Available in: All Default: 0x0004 Range: 04 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 RELEASE[2:0] Bit Name Function 15:3 Reserved Always write to 0. Transmit Audio Dynamic Range Control Release Time. 0 = 100 ms 2:0 RELEASE[2:0] 1 = 200 ms 2 = 350 ms 3 = 525 ms 4 = 1000 ms (default) Property 0x2204. TX_ACOMP_GAIN Sets the gain for audio dynamic range control from 0 to 20 dB in 1 dB units. For example, a setting of 15 dB would be 15 = 0xF. The gain is applied to the audio below the threshold set by the TX_ACOMP_THRESHOLD property. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 15 dB or 0xF. Available in: All Default: 0x000F (15) Units: 1 dB Step: 1 dB Range: 020 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name GAIN[5:0] Bit Name Function 15:6 Reserved Always write to 0. Transmit Audio Dynamic Range Control Gain. 5:0 GAIN[5:0] Range is from 0 to 20 dB in 1 dB steps. Default is 15. Rev. 1.2 43 AN332 Property 0x2205. TX_LIMITER_RELEASE_TIME Sets the time required for the device to respond to audio level transitions from above the limiter threshold to below the limiter threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 5.01 ms, or 102. Note: TX_LIMITER_RELEASE_TIME is supported in FMTX component 2.0 or later. Available in: All except Si4710-A10 Default 0x0066 (102) Step: 1 Range: 52000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name LIMITERTC[15:0] Bit Name Sets the limiter release time. 5 = 102.39 ms 6 = 85.33 ms 7 = 73.14 ms 8 = 63.99 ms 10 = 51.19 ms 13 = 39.38 ms 17 = 30.11 ms 25 = 20.47 ms 51 = 10.03 ms 15:0 LMITERTC[15:0] 57 = 8.97 ms 64 = 7.99 ms 73 = 7.01 ms 85 = 6.02 ms 102 = 5.01 ms (default) 127 = 4.02 ms 170 = 3.00 ms 255 = 2.00 ms 510 = 1.00 ms 1000 = 0.50 ms 2000 = 0.25 ms Function 44 Rev. 1.2 AN332 Property 0x2300. TX_ASQ_INTERRUPT_SELECT This property is used to enable which Audio Signal Quality (ASQ) measurements trigger ASQ_INT bit in the TX_ASQ_STATUS command. OVERMODIEN bit enables ASQ interrupt by the OVERMOD bit, which turns on with overmodulation of the FM output signal due to excessive input signal level. IALHIEN and IALLIEN bits enable ASQ interrupt by the IALH and IALL bits, which report high or low input audio condition. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERMODIEN IALHIEN IALLIEN Bit Name Function 15:3 Reserved Always write to 0. Overmodulation Detection Enable. 2 OVERMODIEN 0 = OVERMOD detect disabled (default). 1 = OVERMOD detect enabled. Input Audio Level Detection High Threshold Enable. 1 IALHIEN 0 = IALH detect disabled (default). 1 = IALH detect enabled. Input Audio Level Detection Low Threshold Enable. 0 IALLIEN 0 = IALL detect disabled (default). 1 = IALL detect enabled. Rev. 1.2 45 AN332 Property 0x2301. TX_ASQ_LEVEL_LOW This property sets the low audio level threshold relative to 0 dBFS in 1 dB increments, which is used to trigger the IALL bit. This threshold can be set to detect a silence condition in the input audio allowing the host to take an appropriate action such as disabling the RF carrier or powering down the chip. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0000 and the range is 0 to 70. Available in: All Default: 0x0000 Units: 1 dB Step: 1 dB Range: 70 to 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 IALLTH[7:0] Bit Name Function 15:8 Reserved Always write to 0. Input Audio Level Low Threshold. 7:0 IALLTH[7:0] Threshold which input audio level must be below in order to detect a low audio condition. Specified in units of dBFS in 1 dB steps (70 .. 0). Default is 0. Property 0x2302. TX_ASQ_DURATION_LOW This property is used to determine the duration (in 1 ms increments) that the input signal must be below the TX_ASQ_LEVEL_LOW threshold in order for an IALL condition to be generated. The range is 0 ms to 65535 ms, and the default is 0 ms. Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Units: 1 ms Step: 1 ms Range: 065535 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name IALLDUR[15:0] Bit Name Function Input Audio Level Duration Low. 15:0 IALLDUR[15:0] Required duration the input audio level must fall below IALLTH to trigger an IALL inter- rupt. Specified in 1mS increments (065535 ms). Default is 0. 46 Rev. 1.2 AN332 Property 0x2303. TX_ASQ_LEVEL_HIGH This property sets the high audio level threshold relative to 0 dBFS in 1 dB increments, which is used to trigger the IALH bit. This threshold can be set to detect an activity condition in the input audio allowing the host to take an appropriate action such as enabling the RF carrier after an extended silent period. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0000 and the range is 0 to 70. Available in: All Default: 0x0000 Units: 1 dB Step: 1 dB Range: 70 to 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 IALHTH[7:0] Bit Name Function 15:8 Reserved Always write to 0. Input Audio Level High Threshold 7:0 IALHTH[7:0] Threshold which input audio level must be above in order to detect a high audio condition. Specified in units of dBFS in 1 dB steps (70 .. 0). Default is 0. Rev. 1.2 47 AN332 Property 0x2304. TX_ASQ_DURATION_HIGH This property is used to determine the duration (in 1 ms increments) that the input signal must be above the TX_ASQ_LEVEL_HIGH threshold in order for a IALH condition to be generated. The range is 0 to 65535 ms, and the default is 0 ms. Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Units: 1 ms Step: 1 ms Range: 065535 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name IALHDUR[15:0] Bit Name Function Input Audio Level Duration High. 15:0 IALHDUR[15:0] Required duration the input audio level must exceed IALHTH to trigger an IALH inter- rupt. Specified in 1 ms increments (0 65535 ms). Default is 0. 48 Rev. 1.2 AN332 Property 0x2C00. TX_RDS_INTERRUPT_SOURCE Configures the RDS interrupt sources. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_INTERRUPT_SOURCE is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 RDS RDS RDS- RDS RDS- PSXMIT CBUFXMIT FIFOXMIT CBUFWRAP FIFOMT Bit Name Function 0 = Do not interrupt (default). 4 RDSPSXMIT 1 = Interrupt when a RDS PS Group has been transmitted. The interrupt occurs when a PS group begins transmission. 0 = Do not interrupt (default). 3 RDSCBUFXMIT 1 = Interrupt when a RDS Group has been transmitted from the Circular Buffer. The interrupt occurs when a group is fetched from the buffer. 0 = Do not interrupt (default). 2 RDSFIFOXMIT 1 = Interrupt when a RDS Group has been transmitted from the FIFO Buffer. The interrupt occurs when a group is fetched from the buffer. 0 = Do not interrupt (default). 1 RDSCBUFWRAP 1 = Interrupt when the RDS Group Circular Buffer has wrapped. The interrupt occurs when the last group is fetched from the buffer. 0 = Do not interrupt (default). 0 RDSFIFOMT 1 = Interrupt when the RDS Group FIFO Buffer is empty. The interrupt occurs when the last group is fetched from the FIFO. Rev. 1.2 49 AN332 Property 0x2C01. TX_RDS_PI Sets the RDS PI code to be transmitted in block A and block C (for type B groups). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PI is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x40A7 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSPI[15:0] Bit Name Function 15:0 RDSPI[15:0] Transmit RDS Program Identifier. RDS program identifier data. Property 0x2C02. TX_RDS_PS_MIX Sets the ratio of RDS PS (group 0A) and circular buffer/FIFO groups. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_MIX is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0003 Range: 06 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 RDSPSMIX[2:0] Bit Name Function 15:3 Reserved Always write to 0. Transmit RDS Mix. 000 = Only send RDS PS if RDS Group Buffer is empty 001 = Send RDS PS 12.5% of the time 2:0 RDSPSMIX[2:0] 010 = Send RDS PS 25% of the time 011 = Send RDS PS 50% of the time (default) 100 = Send RDS PS 75% of the time 101 = Send RDS PS 87.5% of the time 110 = Send RDS PS 100% of the time 50 Rev. 1.2 AN332 Property 0x2C03. TX_RDS_PS_MISC Configures miscellaneous RDS flags. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_MISC is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x1008 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSD3 RDSD2 RDSD1 RDSD0 FORCEB RDSTP RDSPTY[4:0] RDSTA RDSMS 0 0 0 Bit Name Function Dynamic PTY code. 15 RDSD3 0 = Static PTY (default). 1 = Indicates that the PTY code is dynamically switched. Compressed code. 14 RDSD2 0 = Not compressed (default). 1 = Compressed. Artificial Head code. 13 RDSD1 0 = Not artificial head (default). 1 = Artificial head. Mono/Stereo code. 12 RDSD0 0 = Mono. 1 = Stereo (default). Use the PTY and TP set here in all block B data. 11 FORCEB 0 = FIFO and BUFFER use PTY and TP as when written (default). 1 = FIFO and BUFFER force PTY and TP to be the settings in this property. 10 RDSTP Traffic Program Code (default = 0). 9:5 RDSPTY[4:0] Program Type Code (default = 0). 4 RDSTA Traffic Announcement Code (default = 0). Music/Speech Switch Code. 3 RDSMS 0 = Speech. 1 = Music (default). 2:0 Reserved Always write to 0. Rev. 1.2 51 AN332 Property 0x2C04. TX_RDS_PS_REPEAT_COUNT Sets the number of times a program service group 0A is repeated. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_REPEAT_COUNT is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0003 Range: 1255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSPSRC[7:0] Bit Name Function 15:8 Reserved Always write to 0. Transmit RDS PS Repeat Count. 7:0 RDSPSRC[7:0] Number of times to repeat transmission of a PS message before transmitting the next PS message. Property 0x2C05. TX_RDS_PS_MESSAGE_COUNT Sets the number of program service messages through which to cycle. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_MESSAGE_COUNT is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0001 Range 112 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 RDSPSMC[3:0] Bit Name Function 15:4 Reserved Always write to 0. 3:0 RDSPSMC[3:0] Transmit RDS PS Message Count. Number of PS messages to cycle through. Default is 1. 52 Rev. 1.2 AN332 Property 0x2C06. TX_RDS_PS_AF Sets the AF RDS Program Service Alternate Frequency. This provides the ability to inform the receiver of a single alternate frequency using AF Method A coding and is transmitted along with the RDS_PS Groups. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_PS_AF is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0xE0E0 Range: 0xE0000xE0CC Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSAF[15:0] Bit Name Function Transmit RDS Program Service Alternate Frequency. 0xE101 = 1 AF @ 87.6 MHz 0xE102 = 1 AF @ 87.7 MHz 15:0 RDSAF[15:0] ... 0xE1CB = 1 AF @ 107.8 MHz 0xE1CC = 1 AF @ 107.9 MHz 0xE0E0 = No AF exists (default) Rev. 1.2 53 AN332 Property 0x2C07. TX_RDS_FIFO_SIZE Sets the RDS FIFO size in number of blocks. Note that the value written must be one larger than the desired FIFO size. The number of blocks allocated will reduce the size of the Circular RDS Group Buffer by the same amount. For instance, if RDSFIFOSZ = 20, then the RDS Circular Buffer will be reduced by 20 blocks. The minimum number of blocks which should be allocated is 4. This provides enough room for a single group of any type (xA or xB) to be transmitted. Groups xA require 3 Blocks, Groups xB require 2 Blocks as block C' is always the same as the RDS PI code. Before setting this value, determine the available blocks through the TX_RDS_FIFO command, as the buffer size may vary between versions or part numbers. The guaranteed minimum FIFO size, however, is 53 blocks. The RDS FIFO and the RDS Circular Buffer should be emptied with the TX_RDS_FIFO command prior to changing the size of the FIFO. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Note: TX_RDS_FIFO_SIZE is supported in FMTX component 2.0 or later. Available in: Si4711/13/21 Default: 0x0000 Units: blocks Step: 3 blocks Range: 0, 4, 7, 1054 Note: Actual maximum FIFO size returned by the TX_RDS_BUFF command is larger, however, this is 53 blocks is the guaranteed FIFO size. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSFIFOSZ[7:0] Bit Name 15:8 Reserved Always write 0. 7:0 RDSFIFOSZ[7:0] Transmit RDS FIFO Size. 0 = FIFO disabled (default) Function 54 Rev. 1.2 AN332 5.2. Commands and Properties for the FM/RDS Receiver (Si4704/05/06/2x/3x/4x/84/85) Tables 8 and 9 summarize the commands and properties for the FM/RDS Receiver component applicable to Si4704/05/06/2x/3x/4x/84/85. Table 8. FM/RDS Receiver Command Summary Cmd Name Description Available In 0x01 POWER_UP Power up device and mode selection. All 0x10 GET_REV Returns revision information on the device. All 0x11 POWER_DOWN Power down device. All 0x12 SET_PROPERTY Sets the value of a property. All 0x13 GET_PROPERTY Retrieves a property's value. All 0x14 GET_INT_STATUS Reads interrupt status bits. All 0x15 PATCH_ARGS* Reserved command used for patch file downloads. All 0x16 PATCH_DATA* Reserved command used for patch file downloads. All 0x20 FM_TUNE_FREQ Selects the FM tuning frequency. All 0x21 FM_SEEK_START Begins searching for a valid frequency. All 0x22 FM_TUNE_STATUS Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START command. All 0x23 0x24 FM_RSQ_STATUS FM_RDS_STATUS Queries the status of the Received Signal Quality (RSQ) of the current channel. Returns RDS information for current channel and reads an entry from RDS FIFO. All Si4705/06, Si4721, Si474x, Si4731/32/35/37/ 39, Si4785 0x27 FM_AGC_STATUS Queries the current AGC settings 0x28 FM_AGC_OVERRIDE Override AGC setting by disabling and forcing it to a fixed value 0x80 GPIO_CTL Configures GPO1, 2, and 3 as output or Hi-Z. 0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high). All All All except Si4730-A10 All except Si4730-A10 *Note: Commands PATCH_ARGS and PATCH_DATA are only used to patch firmware. For information on applying a patch file, see "7.2. Powerup from a Component Patch" on page 236. Rev. 1.2 55 AN332 Prop 0x0001 0x0102 0x0104 0x0201 0x0202 0x1100 0x1102 0x1105 0x1106 0x1107 Table 9. FM/RDS Receiver Property Summary Name GPO_IEN Description Enables interrupt sources. Default 0x0000 DIGITAL_OUTPUT_ FORMAT Configure digital audio outputs. 0x0000 DIGITAL_OUTPUT_ SAMPLE_RATE Configure digital audio output sample rate. 0x0000 REFCLK_FREQ REFCLK_PRESCALE FM_DEEMPHASIS Sets frequency of reference clock in Hz. The range is 31130 to 34406 Hz, or 0 to disable the AFC. Default is 32768 Hz. Sets the prescaler value for RCLK input. Sets deemphasis time constant. Default is 75 µs. 0x8000 0x0001 0x0002 FM_CHANNEL_FILTER Selects bandwidth of channel filter applied at the demodulation stage. 0x0001 0x0000 FM_BLEND_STEREO_ THRESHOLD FM_BLEND_MONO_ THRESHOLD FM_ANTENNA_INPUT Selects bandwidth of channel filter applied at the demodulation stage. Sets RSSI threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo set this to 0. To force mono set this to 127. Default value is 30 dBµV. Selects the antenna type and the pin to which it is connected. 0x0031 0x001E 0x0000 Available In All Si4704-D60 and later, Si4705/06, Si4721/31/32/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Si4704-D60 and later, Si4705/06, Si4721/31/32/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 All All All except Si4749 Si4706, Si4749, Si4705/31/35/85-D50, and later, Si4732 Si4704/30/34/84-D50 and later Si470x/2x, Si473x-C40 and earlier Si470x/2x, Si473x-C40 and earlier Si4704/05/06/20/21 56 Rev. 1.2 AN332 Table 9. FM/RDS Receiver Property Summary (Continued) Prop 0x1108 0x1200 0x1201 0x1202 0x1203 0x1204 0x1205 0x1206 0x1207 0x1300 0x1301 0x1302 0x1303 Name FM_MAX_TUNE_ ERROR FM_RSQ_INT_ SOURCE FM_RSQ_SNR_HI_ THRESHOLD FM_RSQ_SNR_LO_ THRESHOLD FM_RSQ_RSSI_HI_ THRESHOLD FM_RSQ_RSSI_LO_ THRESHOLD Description Sets the maximum freq error allowed before setting the AFC rail (AFCRL) indicator. Default value is 20 kHz. Configures interrupt related to Received Signal Quality metrics. Sets high threshold for SNR interrupt. Sets low threshold for SNR interrupt. Sets high threshold for RSSI interrupt. Sets low threshold for RSSI interrupt. FM_RSQ_MULTIPATH_HI_ Sets high threshold for mul- THRESHOLD tipath interrupt. FM_RSQ_MULTIPATH_ Sets low threshold for mul- LO_THRESHOLD tipath interrupt. FM_RSQ_BLEND_ THRESHOLD Sets the blend threshold for blend interrupt when boundary is crossed. Sets the attack and decay FM_SOFT_MUTE_RATE rates when entering and leav- ing soft mute. Configures attenuation slope during soft mute in dB attenuFM_SOFT_MUTE_SLOPE ation per dB SNR below the soft mute SNR threshold. Default value is 2. FM_SOFT_MUTE_ MAX_ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. Default is 16 dB. FM_SOFT_MUTE_ SNR_THRESHOLD Sets SNR threshold to engage soft mute. Default is 4 dB. Default 0x001E 0x0014 0x0000 0x007F 0x0000 0x007F 0x0000 0x007F 0x0000 0x0081 0x0040 0x0002 0x0010 0x0004 Available In All All others All All All All All Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85 -D50, and later, Si4732 Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85 -D50, and later, Si4732 All except Si4749 Si4706/07/20/21/84/85-B20 and earlier, Si4704/05/3x- C40 and earlier Si4704/05/06/3x-C40 and later, Si4732, Si4740/41/42/43/44/45 All except Si4749 All except Si4749 Rev. 1.2 57 AN332 Table 9. FM/RDS Receiver Property Summary (Continued) Prop 0x1304 0x1305 0x1400 0x1401 0x1402 0x1403 0x1404 0x1500 0x1501 0x1502 0x1503 0x1700 Name FM_SOFT_MUTE_ RELEASE_RATE FM_SOFT_MUTE_ ATTACK_RATE FM_SEEK_BAND_ BOTTOM FM_SEEK_BAND_TOP FM_SEEK_FREQ_ SPACING FM_SEEK_TUNE_ SNR_THRESHOLD FM_SEEK_TUNE_ RSSI_TRESHOLD Description Sets soft mute release rate. Smaller values provide slower release, and larger values provide faster release. The default is 8192 (approximately 8000 dB/s) Sets soft mute attack rate. Smaller values provide slower attack, and larger values provide faster attack. The default is 8192 (approximately 8000 dB/s) Sets the bottom of the FM band for seek. Default is 8750 (87.5 MHz). Sets the top of the FM band for seek. Default is 10790 (107.9 MHz). Selects frequency spacing for FM seek. Default value is 10 (100 kHz). Sets the SNR threshold for a valid FM Seek/Tune. Default value is 3 dB. Sets the RSSI threshold for a valid FM Seek/Tune. Default value is 20 dBµV. Default 0x2000 0x2000 0x222E 0x2A26 0x000A 0x0003 0x0014 FM_RDS_INT_SOURCE Configures RDS interrupt behavior. 0x0000 FM_RDS_INT_FIFO_ COUNT Sets the minimum number of RDS groups stored in the receive FIFO required before RDSRECV is set. 0x0000 FM_RDS_CONFIG Configures RDS setting. 0x0000 Sets the confidence level FM_RDS_CONFIDENCE threshold for each RDS block. FM_AGC_ATTACK_RATE Sets the AGC attack rate. Larger values provide slower attack and smaller values provide faster attack. The default is 4 (approximately 1500 dB/s). 0x1111 0x0004 Available In Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85 -D50 and later, Si4732 Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85 -D50 and later, Si4732 All All All All All Si4705/06, Si4721, Si431/32/35/37/39, Si4741/43/45/49 Si4705/06, Si4721, Si431/32/35/37/39, Si4741/43/45/49 Si4705/06, Si4721, Si431/32/35/37/39, Si4741/43/45/49 Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85 -D50 and later, Si4732 Si474x 58 Rev. 1.2 AN332 Table 9. FM/RDS Receiver Property Summary (Continued) Prop 0x1701 0x1800 0x1801 0x1802 0x1803 0x1804 0x1805 Name Description FM_AGC_RELEASE_RATE Sets the AGC release rate. Larger values provide slower release and smaller values provide faster release. The default is 140 (approximately 43 dB/s). FM_BLEND_RSSI_ STEREO_THRESHOLD Sets RSSI threshold for stereo blend. (Full stereo above threshold, blend below threshold.) To force stereo, set this to 0. To force mono, set this to 127. Default value is 49 dBV. FM_BLEND_RSSI_MONO_ THRESHOLD Sets RSSI threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo, set this to 0. To force mono, set this to 127. Default value is 30 dBV. FM_BLEND_RSSI_ ATTACK_RATE Sets the stereo to mono attack rate for RSSI based blend. Smaller values provide slower attack and larger values provide faster attack. The default is 4000 (approximately 16 ms). FM_BLEND_RSSI_ RELEASE_RATE Sets the mono to stereo release rate for RSSI based blend. Smaller values provide slower release and larger values provide faster release. The default is 400 (approximately 164 ms). FM_BLEND_SNR_ STEREO_THRESHOLD Sets SNR threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set this to 0. To force mono, set this to 127. Default value is 27 dB. Sets SNR threshold for mono blend (Full mono below FM_BLEND_SNR_MONO_ THRESHOLD threshold, blend above threshold). To force stereo, set this to 0. To force mono, set this to 127. Default value is 14 dB. Default 0x008C 0x0031 0x001E 0x0FA0 0x0190 0x001B 0x000E Available In Si474x Si4706-C30 and later, Si4740/41/42/43/44/45, Si4705/31/35/85-D50 and later, Si4732 Si4706-C30 and later, Si4740/41/42/ 43/44/45, Si4705/31/35/85 -D50 and later, Si4732 Si4706-C30 and later, Si4740/41/42/ 43/44/45, Si4705/31/35/85 -D50 and later, Si4732 Si4706-C30 and later, Si4740/41/42/ 43/44/45, Si4705/31/35/85 -D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Rev. 1.2 59 AN332 Table 9. FM/RDS Receiver Property Summary (Continued) Prop 0x1806 0x1807 0x1808 Name Description Default FM_BLEND_SNR_ATTACK_ RATE Sets the stereo to mono attack rate for SNR based blend. Smaller values provide slower attack and larger values provide faster attack. The default is 4000 (approximately 16 ms). 0x0FA0 FM_BLEND_SNR_ RELEASE_RATE Sets the mono to stereo release rate for SNR based blend. Smaller values provide slower release and larger values provide faster release. The default is 400 (approximately 164 ms). 0x0190 Sets multipath threshold for stereo blend (Full stereo FM_BLEND_MULTIPATH_ STEREO_THRESHOLD below threshold, blend above threshold). To force stereo, set this to 100. To force mono, set this to 0. Default value is 20. 0x0014 Available In Si4740/41/42/ 43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35 /84/85-D50 and later, Si4732 Si4740/41/42/ 43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35 /84/85-D50 and later, Si4732 Si4740/41/42/ 43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 0x1809 Sets Multipath threshold for mono blend (Full mono FM_BLEND_MULTIPATH_- above threshold, blend below MONO_THRESHOLD threshold). To force stereo, set to 100. To force mono, set to 0. The default is 60. 0x003C Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 0x180A Sets the stereo to mono attack rate for Multipath FM_BLEND_MULTIPATH_ ATTACK_RATE based blend. Smaller values provide slower attack and larger values provide faster attack. The default is 4000 (approximately 16 ms). 0x0FA0 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 60 Rev. 1.2 AN332 Table 9. FM/RDS Receiver Property Summary (Continued) Prop 0x180B 0x180C 0x1900 0x1901 0x1902 0x1903 0x1904 0x1A00 0x1A01 0x1A02 0x1A03 Name Description Sets the mono to stereo release rate for Multipath FM_BLEND_MULTIPATH_ RELEASE_RATE based blend. Smaller values provide slower release and larger values provide faster release. The default is 40 (approximately 1.64 s). FM_BLEND_MAX_STEREO_SEPARATION Sets the maximum amount of stereo separation FM_NB_DETECT_ THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor. Default value is 16. FM_NB_INTERVAL Interval in micro-seconds that original samples are replaced by interpolated clean samples. Default value is 24 µs. FM_NB_RATE Noise blanking rate in 100 Hz units. Default value is 64. FM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator Default value is 300. FM_NB_DELAY Delay in micro-seconds before applying impulse blanking to the original samples. Default value is 133. FM_HICUT_ SNR_HIGH_ THRESHOLD Sets the SNR level at which hi-cut begins to band limit. Default value is 24. FM_HICUT_ SNR_LOW_THRESHOLD Sets the SNR level at which hi-cut reaches maximum band limiting. Default value is 15. FM_HICUT_ ATTACK_RATE Sets the rate at which hi-cut lowers the cut-off frequency. Default value is 20000 (approximately 3 ms) FM_HICUT_ RELEASE_RATE Sets the rate at which hi-cut increases the cut-off frequency. Default value is 20. (approximately 3.3 s) Default 0x0028 0x0000 0x0010 0x0018 0x0040 0x012C 0x00AA 0x0018 0x000F 0x4E20 0x0014 Available In Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si474x Si4742/43/44/45 Si4742/43/44/45 Si4742/43/44/45 Si4742/43/44/45 Si4742/43/44/45 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Rev. 1.2 61 AN332 Prop 0x1A04 0x1A05 0x1A06 0x4000 0x4001 Table 9. FM/RDS Receiver Property Summary (Continued) Name Description FM_HICUT_ MULTIPA- Sets the MULTIPATH level at TH_TRIGGER THRESH- which hi-cut begins to band OLD limit. Default value is 20. FM_HICUT_ MULTIPATH_END_ THRESHOLD Sets the MULTIPATH level at which hi-cut reaches maximum band limiting. Default value is 60. FM_HICUT_ CUTOFF_FREQUENCY RX_VOLUME RX_HARD_MUTE Sets the maximum band limit frequency for hi-cut and also sets the maximum audio frequency. Default value is 0 (disabled). Sets the output volume. Mutes the audio output. L and R audio outputs may be muted independently. Default 0x0014 0x003C 0x0000 0x003F 0x0000 Available In Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 All except Si4749 All except Si4749 62 Rev. 1.2 AN332 Bit STATUS Table 10. Status Response for the FM/RDS Receiver D7 D6 D5 CTS ERR X D4 D3 D2 X RSQINT RDSINT D1 D0 X STCINT Bit Name Function Clear to Send. 7 CTS 0 = Wait before sending next command. 1 = Clear to send next command. Error. 6 ERR 0 = No error 1 = Error 5:4 Reserved Values may vary. Received Signal Quality Interrupt. 3 RSQINT 0 = Received Signal Quality measurement has not been triggered. 1 = Received Signal Quality measurement has been triggered. Radio Data System (RDS) Interrupt (Si4705/21/31/32/35/37/39/85 Only). 2 RDSINT 0 = Radio data system interrupt has not been triggered. 1 = Radio data system interrupt has been triggered. 1 Reserved Values may vary. Seek/Tune Complete Interrupt. 0 STCINT 0 = Tune complete has not been triggered. 1 = Tune complete has been triggered. Rev. 1.2 63 AN332 5.2.1. FM/RDS Receiver Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the response, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 0 (FM Receive) and the patch may be applied (See Section "7.2. Powerup from a Component Patch" on page 236). The POWER_UP command configures the state of ROUT (pin 13, Si474x pin 15, Si4732 pin 16) and LOUT (pin 14, Si474x pin 16, Si4732 pin 1) for analog audio mode and GPO2/INT (pin 18, Si474x pin 20, Si4732 pin 3) for interrupt operation. For the Si4705/21/31/32/35/37/39/84/85-B20, the POWER_UP command also configures the state of GPO3/DCLK (pin 17, Si474x pin 19, Si4732 pin 2), DFS (pin 16, Si474x pin 18, Si4732 pin 1), and DOUT (pin 15, Si474x pin 17, Si4732 pin 16) for digital audio mode. The command configures GPO2/INT interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g. FM RX to AM RX or FM RX to FM TX), issue POWER_DOWN command to stop current function; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tune command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 0), Seven (FUNC = 15) Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit 1 7 1 6 1 5 Name CTSIEN GPO2OEN PATCH Function CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. GPO2 Output Enable. 0 = GPO2 output disabled. 1 = GPO2 output enabled. Patch Enable. 0 = Boot normally. 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched. 64 Rev. 1.2 AN332 ARG Bit 1 4 1 3:0 2 7:0 Name XOSCEN FUNC[3:0] OPMODE[7:0] Function Crystal Oscillator Enable. Note: Set to 0 for Si4740/41/42/43/44/45/49 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crys- tal and OPMODE=00000101). See Si47xx Data Sheet Application Schematic for external BOM details. Function. 0 = FM Receive. 114 = Reserved. 15 = Query Library ID. Application Setting. 00000000 = RDS output only (no audio outputs) Si4749 only 00000101 = Analog audio outputs (LOUT/ROUT). 00001011 = Digital audio output (DCLK, LOUT/DFS, ROUT/DIO) (Si4704/05/21/31/35/37/39/41/43/45/84/85 FMRX component 2.0 or later with XOSCEN = 0) 10110000 = Digital audio outputs (DCLK, DFS, DIO) (Si4704/05/21/31/35/37/39/41/43/45/84/85 FMRX component 2.0 or later with XOSCEN = 0). 10110101 = Analog and digital audio outputs (LOUT/ROUT and DCLK, DFS, DIO) (Si4704/05/21/31/35/37/39/41/43/45/84/85 FMRX component 2.0 or later with XOSCEN = 0). Response (FUNC = 0, FM Receive) Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT Response (FUNC = 15, Query Library ID) Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESERVED[7:0] RESP5 RESERVED[7:0] RESP6 CHIPREV[7:0] RESP7 LIBRARYID[7:0] RESP Bit 1 7:0 2 7:0 Name PN[7:0] FWMAJOR[7:0] Function Final 2 digits of part number (HEX). Firmware Major Revision (ASCII). Rev. 1.2 65 AN332 3 7:0 FWMINOR[7:0] Firmware Minor Revision (ASCII). 4 7:0 RESERVED[7:0] Reserved, various values. 5 7:0 RESERVED[7:0] Reserved, various values. 6 7:0 CHIPREV[7:0] Chip Revision (ASCII). 7 7:0 LIBRARYID[7:0] Library Revision (HEX). Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Fifteen (Si4705/06 only), Eight (Si4704/2x/3x/4x) Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP10 RESP11 RESP12 RESP13 RESP14 RESP15 D7 CTS D6 ERR D5 D4 D3 D2 D1 D0 X X RSQINT RDSINT X STCINT PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] Reserved Reserved Reserved Reserved Reserved CID[7:0] (Si4705 only) 66 Rev. 1.2 AN332 RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 8 7:0 15 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] CID[7:0] Function Final 2 digits of Part Number (HEX). Firmware Major Revision (ASCII). Firmware Minor Revision (ASCII). Patch ID High Byte (HEX). Patch ID Low Byte (HEX). Component Major Revision (ASCII). Component Minor Revision (ASCII). Chip Revision (ASCII). CID (Si4705/06 only). Command 0x11. POWER_DOWN Moves the device from powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: In FMRX component 1.0, a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 ROUT, LOUT, DOUT, DFS = HiZ Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 1 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT Rev. 1.2 67 AN332 Command 0x12. SET_PROPERTY Sets a property shown in Table 9, "FM/RDS Receiver Property Summary," on page 56. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. See Figure 30, "CTS and SET_PROPERTY Command Complete tCOMP Timing Model," on page 246 and Table 50, "Command Timing Parameters for the FM Receiver," on page 248. Available in: All Command Arguments: Five Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] PROPDH[7:0] PROPDL[7:0] ARG 1 2 3 4 5 Bit Name Function 7:0 Reserved Always write to 0. 7:0 PROPH[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to modify. 7:0 PROPL[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to modify. 7:0 PROPDH[7:0] Property Value High Byte. This byte in combination with PROPDL is used to set the property value. 7:0 PROPDL[7:0] Property Value Low Byte. This byte in combination with PROPDH is used to set the property value. 68 Rev. 1.2 AN332 Command 0x13. GET_PROPERTY Gets a property as shown in Table 9, "FM/RDS Receiver Property Summary," on page 56. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 Response Name Reserved PROPH[7:0] PROPL[7:0] Function Always write to 0. Property High Byte. This byte in combination with PROPL is used to specify the property to get. Property Low Byte. This byte in combination with PROPH is used to specify the property to get. Bit D7 D6 D5 STATUS CTS ERR X RESP1 0 0 0 RESP2 RESP3 D4 D3 D2 D1 D0 X RSQINT RDSINT X STCINT 0 0 0 0 0 PROPDH[7:0] PROPDL[7:0] RESP Bit 1 7:0 2 7:0 3 7:0 Name Reserved PROPDH[7:0] PROPDL[7:0] Function Always returns 0. Property Value High Byte. This byte in combination with PROPDL represents the requested property value. Property Value High Byte. This byte in combination with PROPDH represents the requested property value. Rev. 1.2 69 AN332 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command should be called after any command that sets the STCINT, RDSINT, or RSQINT bits. When polling this command should be periodically called to monitor the STATUS byte, and when using interrupts, this command should be called after the interrupt is set to update the STATUS byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be set when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Bit CMD Response D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 0 Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 D1 D0 X RSQINT RDSINT X STCINT Command 0x20. FM_TUNE_FREQ Sets the FM Receive to tune a frequency between 64 and 108 MHz in 10 kHz units. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 50, "Command Timing Parameters for the FM Receiver," on page 248. FM: LO frequency is 128 kHz above RF for RF frequencies < 90 MHz and 128 kHz below RF for RF frequencies > 90 MHz. For example, LO frequency is 80.128 MHz when tuning to 80.00 MHz. Note: For FMRX components 2.0 or earlier, tuning range is 76108 MHz. Note: Fast bit is supported in FMRX components 4.0 or later. Note: Freeze bit is supported in FMRX components 4.0 or later. Available in: All Command arguments: Four Response bytes: None 70 Rev. 1.2 Command Bit CMD ARG1 ARG2 ARG3 ARG4 AN332 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 FREEZE FAST FREQH[7:0] FREQL[7:0] ANTCAP[7:0] ARG Bit 1 7:1 1 1 1 0 2 7:0 3 7:0 4 7:0 Response Name Reserved FREEZE FAST FREQH[7:0] FREQL[7:0] ANTCAP[7:0] Function Always write to 0. Freeze Metrics During Alternate Frequency Jump. If set will cause the blend, hicut, and softmute to transition as a function of the associated attack/release parameters rather than instantaneously when tuning to alternate station. FAST Tuning. If set, executes fast and invalidated tune. The tune status will not be accurate. Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in 10 kHz. In FM mode the valid range is from 6400 to 10800 (64108 MHz). Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in 10 kHz. In FM mode the valid range is from 6400 to 10800 (64108 MHz). Antenna Tuning Capacitor (valid only when using TXO/LPI pin as the antenna input). This selects the value of the antenna tuning capacitor manually, or automatically if set to zero. The valid range is 0 to 191. Automatic capacitor tuning is recommended. Note: When tuned manually, the varactor is offset by four codes. For example, if the varactor is set to a value of 5 manually, when read back the value will be 1. The four codes (1pf) delta accounts for the capacitance at the chip. Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT Rev. 1.2 71 AN332 Command 0x21. FM_SEEK_START Begins searching for a valid frequency. Clears any pending STCINT or RSQINT interrupt status. The CTS bit (and optional interrupt) is set when it is safe to send the next command. RSQINT status is only cleared by the RSQ status command when the INTACK bit is set. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STCINT bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 50, "Command Timing Parameters for the FM Receiver," on page 248. Available in: All Command arguments: One Response bytes: None Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 1 0 0 0 0 SEEKUP WRAP 0 0 ARG Bit 1 7:4 1 3 1 2 1 1:0 Response Bit STATUS Name Reserved SEEKUP WRAP Reserved Function Always write to 0. Seek Up/Down. Determines the direction of the search, either UP = 1, or DOWN = 0. Wrap/Halt. Determines whether the seek should Wrap = 1, or Halt = 0 when it hits the band limit. Always write to 0. D7 D6 D5 CTS ERR X D4 D3 D2 D1 D0 X RSQINT RDSINT X STCINT 72 Rev. 1.2 AN332 Command 0x22. FM_TUNE_STATUS Returns the status of FM_TUNE_FREQ or FM_SEEK_START commands. The command returns the current frequency, RSSI, SNR, multipath, and the antenna tuning capacitance value (0-191). The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 CANCEL INTACK ARG Bit 1 7:2 1 1 1 0 Response Name Reserved CANCEL INTACK Function Always write to 0. Cancel seek. If set, aborts a seek currently in progress. Seek/Tune Interrupt Clear. If set, clears the seek/tune complete interrupt status indicator. Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 CTS BLTF D6 ERR X D5 D4 D3 D2 X X RSQINT RDSINT X X X X READFREQH[7:0] READFREQL[7:0] RSSI[7:0] SNR[7:0] MULT[7:0] READANTCAP[7:0] (Si4704/05/06/2x only) D1 X AFCRL D0 STCINT VALID Rev. 1.2 73 AN332 RESP Bit Name Function 1 7 BLTF Band Limit. Reports if a seek hit the band limit (WRAP = 0 in FM_START_SEEK) or wrapped to the original frequency (WRAP = 1). 1 6:2 Reserved Always returns 0. 1 1 AFCRL AFC Rail Indicator. Set if the AFC rails. 1 0 VALID Valid Channel. Set if the channel is currently valid as determined by the seek/tune properties (0x1403, 0x1404, 0x1108) and would have been found during a Seek. Read Frequency High Byte. 2 7:0 READFREQH[7:0] This byte in combination with READFREQL returns frequency being tuned (10 kHz). Read Frequency Low Byte. 3 7:0 READFREQL[7:0] This byte in combination with READFREQH returns frequency being tuned (10 kHz). 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte contains the receive signal strength when tune is complete (dBµV). 5 7:0 SNR[7:0] SNR. This byte contains the SNR metric when tune is complete (dB). 6 7:0 MULT[7:0] Multipath. This byte contains the multipath metric when tune is complete. Multipath indicator is available only for Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85 -D50 and later, and Si4732. 7 7:0 READANTCAP [7:0] Read Antenna Tuning Capacitor (Si4704/05/06/2x only). This byte contains the current antenna tuning capacitor value. 74 Rev. 1.2 AN332 Command 0x23. FM_RSQ_STATUS Returns status information about the received signal quality. The commands returns the RSSI, SNR, frequency offset, and stereo blend percentage. It also indicates valid channel (VALID), soft mute engagement (SMUTE), and AFC rail status (AFCRL). This command can be used to check if the received signal is above the RSSI high threshold as reported by RSSIHINT, or below the RSSI low threshold as reported by RSSILINT. It can also be used to check if the signal is above the SNR high threshold as reported by SNRHINT, or below the SNR low threshold as reported by SNRLINT. For the Si4706/4x, it can be used to check if the detected multipath is above the multipath high threshold as reported by MULTHINT, or below the multipath low threshold as reported by MULTLINT. If the PILOT indicator is set, it can also check whether the blend has crossed a threshold as indicated by BLENDINT. The command clears the RSQINT, BLENDINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT, MULTHINT, and MULTLINT interrupt bits when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 INTACK ARG Bit 1 0 Response Name INTACK Function Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears RSQINT, BLENDINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT, MULTHINT, MULTLINT. Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 CTS BLENDINT X PILOT D6 ERR X X D5 D4 D3 D2 D1 D0 X X RSQINT RDSINT X STCINT MULTHINT MULTLINT SNRHINT SNRLINT RSSIHINT RSSIILINT X X SMUTE X AFCRL VALID STBLEND[6:0] RSSI[7:0] SNR[7:0] MULT[7:0] FREQOFF[7:0] Rev. 1.2 75 AN332 RESP Bit Name Function Blend Detect Interrupt. 1 7 BLENDINT 0 = Blend is within the Blend threshold settings. 1 = Blend goes above or below the Blend threshold settings. Multipath Detect High (Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85-D50 and later and Si4732 only). 1 5 MULTHINT 0 = Detected multipath value has not exceeded above the Multipath high threshold. 1 = Detected multipath value has exceeded above the Multipath high threshold. Multipath Detect Low (Si474x, Si4706-C30 and later and 1 4 MULTLINT Si4704/05/30/31/34/35/84/85-D50 and later and Si4732 only). 0 = Detected multipath value has not fallen below the Multipath low threshold. 1 = Detected multipath value has fallen below the Multipath low threshold. SNR Detect High. 1 3 SNRHINT 0 = Received SNR has not exceeded above SNR high threshold. 1 = Received SNR has exceeded above SNR high threshold. SNR Detect Low. 1 2 SNRLINT 0 = Received SNR has not fallen below SNR low threshold. 1 = Received SNR has fallen below SNR low threshold. RSSI Detect High. 1 1 RSSIHINT 0 = RSSI has not exceeded above RSSI high threshold. 1 = RSSI has exceeded above RSSI high threshold. RSSI Detect Low. 1 0 RSSILINT 0 = RSSI has not fallen below RSSI low threshold. 1 = RSSI has fallen below RSSI low threshold. 2 3 SMUTE Soft Mute Indicator. Indicates soft mute is engaged. 2 1 AFCRL AFC Rail Indicator. Set if the AFC rails. 2 0 VALID Valid Channel. Set if the channel is currently valid and would have been found during a Seek. 3 7 PILOT Pilot Indicator. Indicates stereo pilot presence. 3 6:0 STBLEND[6:0] Stereo Blend Indicator. Indicates amount of stereo blend in% (100 = full stereo, 0 = full mono). 4 7:0 RSSI[7:0] Received Signal Strength Indicator. Contains the current receive signal strength (0127 dBµV). 5 7:0 SNR[7:0] SNR. Contains the current SNR metric (0127 dB). Multipath (Si474x, Si4706-C30 and later and Si4704/05/30/31/34/35/84/85-D50 6 7:0 MULT[7:0] and later and Si4732 only). Contains the current multipath metric. (0 = no multipath; 100 = full multipath) 7 7:0 FREQOFF[7:0] Frequency Offset. Signed frequency offset (kHz). 76 Rev. 1.2 AN332 Command 0x24. FM_RDS_STATUS Returns RDS information for current channel and reads an entry from the RDS FIFO. RDS information includes synch status, FIFO status, group data (blocks A, B, C, and D), and block errors corrected. This command clears the RDSINT interrupt bit when INTACK bit in ARG1 is set and, if MTFIFO is set, the entire RDS receive FIFO is cleared (FIFO is always cleared during FM_TUNE_FREQ or FM_SEEK_START). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in power up mode. The FIFO size is 25 groups for FMRX component 2.0 or later, and 14 for FMRX component 1.0. Notes: 1. FM_RDS_STATUS is supported in FMRX component 2.0 or later. 2. MTFIFO is not supported in FMRX component 2.0. Available in: Si4705/06, Si4721, Si474x, Si4731/32/35/37/39, Si4785 Command arguments: One Response bytes: Twelve Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 1 0 0 0 0 0 0 0 STATUSONLY MTFIFO INTACK ARG 1 1 1 Bit Name Function Status Only. Determines if data should be removed from the RDS FIFO. 0 = Data in BLOCKA, BLOCKB, BLOCKC, BLOCKD, and BLE contain the oldest 2 STATUSONLY data in the RDS FIFO. 1 = Data in BLOCKA will contain the last valid block A data received for the current station. Data in BLOCKB will contain the last valid block B data received for the current station. Data in BLE will describe the bit errors for the data in BLOCKA and BLOCKB. Empty FIFO 1 MTFIFO 0 = If FIFO not empty, read and remove oldest FIFO entry. 1 = Clear RDS Receive FIFO. Interrupt Acknowledge 0 INTACK 0 = RDSINT status preserved. 1 = Clears RDSINT. Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 X X RDSNEWBLOCKB RDSNEWBLOCKA X RDSSYNCFOUND RDSSYNCLOST RDSRECV RESP2 X X X X X GRPLOST X RDSSYNC Rev. 1.2 77 AN332 Bit D7 D6 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 BLEA[1:0] D5 D4 D3 D2 RDSFIFOUSED[7:0] BLOCKA[15:8] BLOCKA[7:0] BLOCKB[15:8] BLOCKB[7:0] BLOCKC[15:8] BLOCKC[7:0] BLOCKD[15:8] BLOCKD[7:0] BLEB[1:0] BLEC[1:0] D1 D0 BLED[1:0] RESP Bit Name Function 1 5 RDSNEWBLOCKB RDS New Block B. 1 = Valid Block B data has been received. 1 4 RDSNEWBLOCKA RDS New Block A. 1 = Valid Block A data has been received. 1 2 RDSSYNCFOUND RDS Sync Found. 1 = Found RDS synchronization. 1 1 RDSSYNCLOST RDS Sync Lost. 1 = Lost RDS synchronization. 1 0 RDSRECV RDS Received. 1 = FIFO filled to minimum number of groups set by RDSFIFOCNT. 2 2 GRPLOST Group Lost. 1 = One or more RDS groups discarded due to FIFO overrun. 2 0 RDSSYNC RDS Sync. 1 = RDS currently synchronized. RDS FIFO Used. Number of groups remaining in the RDS FIFO (0 if empty). If non-zero, 3 7:0 RDSFIFOUSED BLOCKA-BLOCKD contain the oldest FIFO entry and RDSFIFOUSED decre- ments by one on the next call to RDS_FIFO_STATUS (assuming no RDS data received in the interim). 4 7:0 BLOCKA[15:8] RDS Block A. Block A group data from oldest FIFO entry if STATUSONLY is 0. Last valid 5 7:0 BLOCKA[7:0] Block A data if STATUSONLY is 1 (Si4749, Si4706-C30 and later and Si4705/31/35/85-D50 and later and Si4732 only). 6 7:0 BLOCKB[15:8] RDS Block B. Block B group data from oldest FIFO entry if STATUSONLY is 0. Last valid 7 7:0 BLOCKB[7:0] Block B data if STATUSONLY is 1 (Si4749, Si4706-C30 and later and Si4705/31/35/85-D50 and later and Si4732 only). 8 7:0 BLOCKC[15:8] RDS Block C. 9 7:0 BLOCKC[7:0] Block C group data from oldest FIFO entry. 78 Rev. 1.2 RESP Bit 10 7:0 11 7:0 12 7:6 12 5:4 12 3:2 12 1:0 Name BLOCKD[15:8] BLOCKD[7:0] BLEA[1:0] BLEB[1:0] BLEC[1:0] BLED[1:0] Function RDS Block D. Block D group data from oldest FIFO entry. RDS Block A Corrected Errors. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. RDS Block B Corrected Errors. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. RDS Block C Corrected Errors. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. RDS Block D Corrected Errors. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. AN332 Rev. 1.2 79 AN332 Command 0x27. FM_AGC_STATUS Returns the AGC setting of the device. The command returns whether the AGC is enabled or disabled and it returns the LNA Gain index. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Two Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 1 1 1 Response Bit D7 D6 D5 STATUS CTS ERR X RESP1 X X X RESP2 X X X D4 D3 D2 D1 D0 X RSQINT RDSINT X STCINT X X X X READ_RFAGCDIS READ_LNA_GAIN_INDEX[4:0] RESP Bit Name Function 1 0 READ_RFAGCDIS This bit indicates whether the RF AGC is disabled or not 0 = RF AGC is enabled 1 = RF AGC is disabled These bits returns the value of the LNA GAIN index 0 = Minimum attenuation (max gain) 2 4:0 READ_LNA_GAIN_INDEX 1 25 = Intermediate attenuation 26 = Maximum attenuation (min gain) Note: The max index is subject to change 80 Rev. 1.2 AN332 Command 0x28. FM_AGC_OVERRIDE Overrides AGC setting by disabling the AGC and forcing the LNA to have a certain gain that ranges between 0 (minimum attenuation) and 26 (maximum attenuation). This command may only be sent when in powerup mode. Available in: All Command arguments: Two Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 1 0 0 0 ARG1 X X X X X X X RFAGCDIS ARG2 X X X LNA_GAIN_INDEX[4:0] ARG 1 2 Bit Name Function This bit selects whether the RF AGC is disabled or not 0 RFAGCDIS 0 = RF AGC is enabled 1 = RF AGC is disabled These bits set the value of the LNA GAIN index 0 = Minimum attenuation (max gain) 4:0 LNA_GAIN_INDEX 1 25 = Intermediate attenuation 26 = Maximum attenuation (min gain) Note: the max index is subject to change Response Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 D1 D0 X RSQINT RDSINT X STCINT Rev. 1.2 81 AN332 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (high or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 1. GPIO_CTL is fully supported in FMRX component 2.0 or later. Only bit GPO3OEN is supported in FMRX component 1.0. 2. The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Name Reserved GPO3OEN GPO2OEN GPO1OEN Reserved Function Always write 0. GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. Always write 0. Bit D7 D6 D5 D4 STATUS CTS ERR X X D3 D2 X RDSINT D1 ASQINT D0 STCINT 82 Rev. 1.2 AN332 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Note: GPIO_SET is fully-supported in FMRX component 2.0 or later. Only bit GPO3LEVEL is supported in FMRX component 1.0. Available in: All except Si4710-A10 Command arguments: One Response bytes: None Command Bit D7 CMD 1 ARG1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Name Reserved GPO3LEVEL GPO2LEVEL GPO1LEVEL Reserved Always write 0. GPO3 Output Level. 0 = Output low (default). 1 = Output high. GPO2 Output Level. 0 = Output low (default). 1 = Output high. GPO1 Output Level. 0 = Output low (default). 1 = Output high. Always write 0. Function Bit D7 D6 D5 D4 STATUS CTS ERR X X D3 D2 X RDSINT D1 ASQINT D0 STCINT Rev. 1.2 83 AN332 5.2.2. FM/RDS Receiver Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RSQINT, RDSINT (Si4705/21/31/32/35/37/39/41/43/45/85 only), and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading this property and modified by writing this property. This property may only be set or read when in powerup mode. Errata:RSQIEN is non-functional on FMRX component 2.0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 RSQREP RDSREP 0 STCREP CTSIEN ERRIEN 0 0 RSQIEN RDSIEN 0 STCIEN Bit 15:12 11 10 9 8 7 6 5:4 3 2 1 0 Name Reserved RSQREP RDSREP Reserved STCREP CTSIEN ERRIEN Reserved RSQIEN RDSIEN Reserved STCIEN Function Always write to 0. RSQ Interrupt Repeat. 0 = No interrupt generated when RSQINT is already set (default). 1 = Interrupt generated even if RSQINT is already set. RDS Interrupt Repeat (Si4705/21/31/35/37/39/41/43/45/85-C40 and Si4732 Only). 0 = No interrupt generated when RDSINT is already set (default). 1 = Interrupt generated even if RDSINT is already set. Always write to 0. STC Interrupt Repeat. 0 = No interrupt generated when STCINT is already set (default). 1 = Interrupt generated even if STCINT is already set. CTS Interrupt Enable. After PowerUp, this bit reflects the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set. 1 = Interrupt generated when CTS is set. ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. Always write to 0. RSQ Interrupt Enable. 0 = No interrupt generated when RSQINT is set (default). 1 = Interrupt generated when RSQINT is set. RDS Interrupt Enable (Si4705/21/31/35/37/39/41/43/45/85-C40 and Si4732 Only). 0 = No interrupt generated when RDSINT is set (default). 1 = Interrupt generated when RDSINT is set. Always write to 0. Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when STCINT is set (default). 1 = Interrupt generated when STCINT is set. 84 Rev. 1.2 AN332 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Available in: Si4704-D60 and later, Si4705/06, Si4721/31/32/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 Note: DIGITAL_OUTPUT_FORMAT is supported in FM receive component 2.0 or later. Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 7 OFALL 6543 OMODE[3:0] 2 OMONO 1 0 OSIZE[1:0] Bit Name Function 15:8 Reserved Always write to 0. Digital Output DCLK Edge. 7 OFALL 0 = use DCLK rising edge 1 = use DCLK falling edge Digital Output Mode. 0000 = I2S 6:3 OMODE[3:0] 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse Digital Output Mono Mode. 2 OMONO 0 = Use mono/stereo blend (per blend thresholds) 1 = Force mono Digital Output Audio Sample Precision. 0 = 16-bits 1:0 OSIZE[1:0] 1 = 20-bits 2 = 24-bits 3 = 8-bits Rev. 1.2 85 AN332 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. The over-sampling rate must be set in order to satisfy a minimum DCLK of 1 MHz. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before the DCLK/DFS is removed. FM_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_OUPTUT_SAMPLE_RATE is supported in FM receive component 2.0 or later. Available in: Si4704-D60 and later, Si4705/06, Si4721/31/32/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 (digital audio output disabled) Units: sps Range: 3248 ksps, 0 to disable digital audio output Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 3248 ksps. 0 to disable digital audio output. 86 Rev. 1.2 AN332 Property 0x0201. REFCLK_FREQ Sets the frequency of the REFCLK from the output of the prescaler. The REFCLK range is 31130 to 34406 Hz (32768 ±5% Hz) in 1 Hz steps, or 0 (to disable AFC). For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz REFCLK. The reference clock frequency property would then need to be set to 32500 Hz. RCLK frequencies between 31130 Hz and 40 MHz are supported, however, there are gaps in frequency coverage for prescaler values ranging from 1 to 10, or frequencies up to 311300 Hz. The following table summarizes these RCLK gaps. PIN 9 RCLK 31.130 kHz 40 MHz Prescaler Divide by 1-4095 REFCLK 31.130 kHz 34.406 kHz Figure 2. REFCLK Prescaler Table 11. RCLK Gaps Prescaler 1 2 3 4 5 6 7 8 9 10 RCLK Low (Hz) 31130 62260 93390 124520 155650 186780 217910 249040 280170 311300 RCLK High (Hz) 34406 68812 103218 137624 172030 206436 240842 275248 309654 344060 The RCLK must be valid 10 ns before sending and 20 ns after completing the FM_TUNE_FREQ and FM_SEEK_START commands. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 32768 Hz. Available in: All Default: 0x8000 (32768) Units: 1 Hz Step: 1 Hz Range: 3113034406 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF[15:0] Bit Name Function Frequency of Reference Clock in Hz. 15:0 REFCLKF[15:0] The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 ±5%), or 0 (to disable AFC). Rev. 1.2 87 AN332 Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before sending and 20 ns after completing the FM_TUNE_FREQ and FM_TUNE_START commands. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 14095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLK SEL REFCLKP[11:0] Bit 15:13 12 11:0 Name Reserved RCLKSEL REFCLKP[11:0] Function Always write to 0. RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. Prescaler for Reference Clock. Integer number used to divide clock frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC). 88 Rev. 1.2 AN332 Property 0x1100. FM_DEEMPHASIS Sets the FM Receive de-emphasis to 50 or 75 µs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 75 µs. Available in: All except Si4749 Default: 0x0002 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEMPH[1:0] Bit Name Function 15:2 Reserved Always write to 0. FM De-Emphasis. 10 = 75 µs. Used in USA (default) 1:0 DEEMPH[1:0] 01 = 50 µs. Used in Europe, Australia, Japan 00 = Reserved 11 = Reserved Property 0x1102. FM_CHANNEL_FILTER Selects bandwidth of channel filter applied at the demodulation stage. Default is automatic which means the device automatically selects proper channel filter. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: Si4706, Si4749, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x0001 (Si4706, Si4749, Si4705/31/35/85-D50 and later, Si4732) 0x0000 (Si4704/30/34/84-D50 and later) Range: 04 Note: Automatic channel filter setting is not supported in FMRX component 3.0. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FMCHFILT[15:0] Bit Name Function 0 = Automatically select proper channel filter. 1 = Force wide (110 kHz) channel filter. 15:0 FM_CHANNEL_FILTER 2 = Force narrow (84 kHz) channel filter. 3 = Force narrower (60 kHz) channel filter. 4 = Force narrowest (40 kHz) channel filter. Rev. 1.2 89 AN332 Property 0x1105. FM_BLEND_STEREO_THRESHOLD Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 49 dBµV. Available in: Si470x/2x, Si473x-C40 and earlier Default: 0x0031 Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 STTHRESH[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM Blend Stereo Threshold. 6:0 STTHRESH RSSI threshold below which the audio output goes into a blend mode. Above this threshold the audio output is in full stereo. Specified in units of dBµV in 1 dB steps (0127). Default is 49 dBµV. Property 0x1106. FM_BLEND_MONO_THRESHOLD Sets RSSI threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 30 dBµV. Available in: Si470x/2x, Si473x-C40 and earlier Default: 0x001E Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MONOTHRESH[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM Blend Mono Threshold. 6:0 MONOTHRESH RSSI threshold below which the audio output goes into full mono mode. Above this threshold the audio output is in blend or full stereo. Specified in units of dBµV in 1 dB steps (0127). Default is 30 dBµV. 90 Rev. 1.2 AN332 Property 0x1107. FM_ANTENNA_INPUT Selects what type of antenna and what pin it is connected to. Default is 0 which means the antenna used is a headphone (long) antenna and it is connected to the FMI pin. Setting the FMTXO bit to 1 means that the antenna used is an embedded (short) antenna and it is connected to the TXO/LPI pin. Note: To assure proper tuning, the FM_TUNE_FREQ command should be issued immediately after this property is changed. Available in: Si4704/05/06/20/21 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMTXO Bit Name Function 15:1 Reserved Always write to 0 Selects what type of antenna and which pin it is connected to: 0 FMTXO 0 = Use FMI pin for headphone (long) antenna 1 = Use TXO/LPI pin for embedded (short) antenna Property 0x1108. FM_MAX_TUNE_ERROR Sets the maximum freq error allowed before setting the AFC rail indicator (AFCRL). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20 kHz. Note: For FMRX components 2.0 or earlier, the default is set to 30 kHz. For best seek performance, set FM_MAX_TUNE_ER- ROR to 20 kHz. Available in: All Default: 0x001E (Si473x-B20 and earlier) 0x0014 (all others) Units: kHz Step: 1 Range: 0255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 FMMAXTUNEERR[7:0] Bit Name Function 15:8 Reserved Always write to 0. FM Maximum Tuning Frequency Error. 7:0 FMMAXTUNEERR Maximum tuning error allowed before setting the AFC Rail Indicator ON. Specified in units of kHz. Default is 20 kHz. Rev. 1.2 91 AN332 Property 0x1200. FM_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Name 0 0 0 0 0 0 0 0 BLENDIEN 0 MULT HIEN D4 MULTLIEN D3 D2 D1 D0 SNRHIEN SNRLIEN RSSIHIEN RSSILIEN Bit Name Function 15:8 Reserved Always write to 0. Interrupt Source Enable: Blend. 7 BLENDIEN Enable blend as the source of interrupt which the threshold is set by FM_R- SQ_BLEND_THRESHOLD. 6 Reserved Always write to 0. Interrupt Source Enable: Multipath High (Si4706-C30 and later, Si474x and 5 MULTHIEN Si4704/05/30/31/34/35/84/85-D50 and later and Si4732 only). Enable Multipath high as the source of interrupt which the threshold is set by FM_RSQ_- MULTIPATH_HI_THRESHOLD. Interrupt Source Enable: Multipath Low (Si4706-C30 and later, Si474x and 4 MULTLIEN Si4704/05/30/31/34/35/84/85-D50 and later and Si4732 only). Enable Multipath low as the source of interrupt which the threshold is set by FM_RSQ_- MULTIPATH_LO_THRESHOLD. Interrupt Source Enable: SNR High. 3 SNRHIEN Enable SNR high as the source of interrupt which the threshold is set by FM_RSQ_SN- R_HI_THRESHOLD. Interrupt Source Enable: SNR Low. 2 SNRLIEN Enable SNR low as the as the source of interrupt which the threshold is set by FM_R- SQ_SNR_LO_THRESHOLD. Interrupt Source Enable: RSSI High. 1 RSSIHIEN Enable RSSI high as the source of interrupt which the threshold is set by FM_R- SQ_RSSI_HI_THRESHOLD. Interrupt Source Enable: RSSI Low. 0 RSSILIEN Enable RSSI low as the source of interrupt which the threshold is set by FM_R- SQ_RSSI_LO_THRESHOLD. 92 Rev. 1.2 AN332 Property 0x1201. FM_RSQ_SNR_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the SNR is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127dB. Available in: All Default: 0x007F Units: dB Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRH[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM RSQ SNR High Threshold. 6:0 SNRH Threshold which triggers the RSQ interrupt if the SNR is above this threshold. Specified in units of dB in 1 dB steps (0127). Default is 127 dB. Property 0x1202. FM_RSQ_SNR_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the SNR is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dB Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRL[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM RSQ SNR Low Threshold. 6:0 SNRL Threshold which triggers the RSQ interrupt if the SNR is below this threshold. Specified in units of dB in 1 dB steps (0127). Default is 0 dB. Rev. 1.2 93 AN332 Property 0x1203. FM_RSQ_RSSI_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the RSSI is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dBµV. Available in: All Default: 0x007F Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 RSSIH[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM RSQ RSSI High Threshold. 6:0 RSSIH Threshold which triggers the RSQ interrupt if the RSSI is above this threshold. Specified in units of dBµV in 1 dB steps (0127). Default is 127 dBµV. Property 0x1204. FM_RSQ_RSSI_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the RSSI is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dBµV. Available in: All Default: 0x0000 Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 RSSIL[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM RSQ RSSI Low Threshold. 6:0 RSSIL Threshold which triggers the RSQ interrupt if the RSSI is below this threshold. Specified in units of dBµV in 1 dB steps (0127). Default is 0 dBµV. 94 Rev. 1.2 AN332 Property 0x1205. FM_RSQ_MULTIPATH_HI_THRESHOLD Sets the high threshold which triggers the RSQ interrupt if the Multipath level is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The value may be the threshold multipath percent (0100), or 127 to disable the feature. Available in: Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x007F Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 000 MULTH[6:0] Bit Name Function 15:7 Reserved Always write to 0. 6:0 MULTH FM RSQ Multipath High Threshold. Threshold which triggers the RSQ interrupt if the Multipath is above this threshold. Default is 127. Property 0x1206. FM_RSQ_MULTIPATH_LO_THRESHOLD Sets the low threshold which triggers the RSQ interrupt if the Multipath level is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The default is 0. Available in: Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x0000 Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 000 MULTL[6:0] Bit Name Function 15:7 Reserved Always write to 0 6:0 MULTL FM RSQ Multipath Low Threshold. Threshold which triggers the RSQ interrupt if the Multipath is below this threshold. Default is 0. Rev. 1.2 95 AN332 Property 0x1207. FM_RSQ_BLEND_THRESHOLD Sets the blend threshold for blend interrupt when boundary is crossed. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1%. Available in: All except Si4749 Default: 0x0081 Units: % Step: 1 Range: 0100 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 PILOT BLEND[6:0] Bit Name Function 15:8 Reserved Always write to 0. Pilot Indicator. 7 PILOT This bit has to be set to 1 (there has to be a pilot present) in order for FM_RSQ_BLEND_THRESHOLD to trigger an interrupt. Without a pilot tone, the part is always in full mono mode and never goes into blend. FM RSQ Blend Threshold. 6:0 BLEND This is a boundary cross threshold. If the blend cross from above to below, or the other way around from below to above this threshold, it will trigger an interrupt. Specified in units of % in 1% steps (0100). Default is 1%. Property 0x1300. FM_SOFT_MUTE_RATE Sets the attack and decay rates when entering and leaving soft mute. Later values increase rates, and lower values decrease rates. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0040. Available in: Si4706/07/20/21/84/85-B20 and earlier, Si4704/05/3x-C40 and earlier Default: 64 Step: 1 Range: 1--255 Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00000000 SMRATE[7:0] 96 Rev. 1.2 AN332 Property 0x1301. FM_SOFT_MUTE_SLOPE Configures attenuation slope during soft mute in dB attenuation per dB SNR below the soft mute SNR threshold. Soft mute attenuation is the minimum of SMSLOPE x (SMTHR SNR) and SMATTN. The recommended SMSLOPE value is CEILING(SMATTN/SMTHR). SMATTN and SMTHR are set via the FM_SOFT_MUTE_MAX_ATTENUATION and FM_SOFT_MUTE_SNR_THRESHOLD properties. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The default soft mute slope property setting is 2 dB/dB in supported devices. The soft mute slope is not configurable in Si4704/05/3x-B20 devices (those with FMRX component 2.0) and is 2 dB/dB. The soft mute slope is not configurable in Si4710/20-A10 devices (those with FMRX component 1.0), and is 0 dB/dB (disabled). Available in: Si4704/05/06/3x-C40 and later, Si4732, Si4740/41/42/43/44/45 Default: 0x0002 Range: 063 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 SMSLOPE[7:0] Property 0x1302. FM_SOFT_MUTE_MAX_ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 16 dB. Available in: All except Si4749 Default: 0x0010 Units: dB Step: 1 Range: 031 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 SMATTN[4:0] Bit Name Function 15:5 Reserved Always write to 0. FM Soft Mute Maximum Attenuation. 4:0 SMATTN Set maximum attenuation during soft mute. If set to 0, then soft mute is disabled. Speci- fied in units of dB in 1 dB steps (031). Default is 16 dB. Rev. 1.2 97 AN332 Property 0x1303. FM_SOFT_MUTE_SNR_THRESHOLD Sets SNR threshold to engage soft mute. Whenever the SNR for a tuned frequency drops below this threshold, the FM reception will go in soft mute, provided soft mute max attenuation property is non-zero. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 4 dB. Available in: All except Si4749 Default: 0x0004 Units: dB Step: 1 Range: 015 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 SMTHR[3:0] Bit Name Function 15:4 Reserved Always write to 0. FM Soft Mute SNR Threshold. 3:0 SMTHR Threshold which will engage soft mute if the SNR falls below this. Specified in units of dB in 1 dB steps (015). Default is 4 dB. Property 0x1304. FM_SOFT_MUTE_RELEASE_RATE Sets the soft mute release rate. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Release Rate (dB/s) = RELEASE[14:0]/1.024 Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x2000 Range: 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 RELEASE[14:0] 98 Rev. 1.2 AN332 Property 0x1305. FM_SOFT_MUTE_ATTACK_RATE Sets the soft mute attack rate. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Attack Rate (dB/s) = ATTACK[14:0]/1.024 Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x2000 Range: 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 ATTACK[14:0] Softmute Gain (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 x = 0x1301: FM_SOFT_MUTE_SLOPE (0-63 dB/dB) y = 0x1302: FM_SOFT_MUTE_MAX_ATTENUATION (0-31 dB) z = 0x1303: FM_SOFT_MUTE_SNR_THRESHOLD (0-15 dB) -18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SNR (dB) x=2, y=16, z=4 (Default) x=4, y=16, z=4 x=2, y=4, z=4 Figure 3. Softmute Gain (dB) x=2, y=16, z=13 Rev. 1.2 99 AN332 Property 0x1400. FM_SEEK_BAND_BOTTOM Sets the bottom of the FM band for seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 87.5 MHz. Available in: All Default: 0x222E Units: 10 kHz Step: 50 kHz Range: 64108 MHz Note: For FMRX components 2.0 or earlier, range is 76108 MHz. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FMSKFREQL[15:0] Bit Name Function FM Seek Band Bottom Frequency. 15:0 FMSKFREQL Selects the bottom of the FM Band during Seek. Specified in units of 10 kHz. Default is 8750 (87.5 MHz). 100 Rev. 1.2 AN332 Property 0x1401. FM_SEEK_BAND_TOP Sets the top of the FM band for seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 107.9 MHz. Available in: All Default: 0x2A26 Units: 10 kHz Step: 50 kHz Range: 64108 MHz Note: For FMRX components 2.0 or earlier, range is 76108 MHz. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FMSKFREQH[15:0] Bit Name Function FM Seek Band Top Frequency. 15:0 FMSKFREQH Selects the top of the FM Band during Seek. Specified in units of 10 kHz. Default is 10790 (107.9 MHz). Property 0x1402. FM_SEEK_FREQ_SPACING Selects frequency spacing for FM seek. There are only 3 valid values: 5, 10, and 20. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 100 kHz. Available in: All Default: 0x000A Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 SKSPACE[4:0] Bit Name Function 15:5 Reserved Always write to 0. FM Seek Frequency Spacing. 4:0 SKSPACE Selects the frequency spacing during Seek function. Specified in units of 10 kHz. There are only 3 valid values: 5 (50 kHz), 10 (100 kHz), and 20 (200 kHz). Default is 10. Rev. 1.2 101 AN332 Property 0x1403. FM_SEEK_TUNE_SNR_THRESHOLD Sets the SNR threshold for a valid FM Seek/Tune. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 3 dB. Available in: All Default: 0x0003 Units: dB Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SKSNR[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM Seek/Tune SNR Threshold. 6:0 SKSNR SNR Threshold which determines if a valid channel has been found during Seek/Tune. Specified in units of dB in 1 dB steps (0127). Default is 3 dB. Property 0x1404. FM_SEEK_TUNE_RSSI_THRESHOLD Sets the RSSI threshold for a valid FM Seek/Tune. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20 dBµV. Available in: All Default: 0x0014 Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SKRSSI[6:0] Bit Name Function 15:7 Reserved Always write to 0. FM Seek/Tune Received Signal Strength Threshold. 6:0 SKRSSI RSSI threshold which determines if a valid channel has been found during seek/tune. Specified in units of dBµV in 1 dBµV steps (0127). Default is 20 dBµV. 102 Rev. 1.2 AN332 Property 0x1500. FM_RDS_INT_SOURCE Configures interrupt related to RDS. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: Si4705/06, Si4721, Si4731/32/35/37/39, Si4741/43/45/49 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Name 0 0 0 0 0 0 0 000 RDSNEWBLOCKB D4 D3 D2 RDSNEWBLOCKA 0 RDSSYNCFOUND D1 D0 RDSSYNCLOST RDSRECV Bit Name Function 15:6 Reserved Always write to 0. RDS New Block B Found (Si4706, Si474x, and Si4705/31/35/85-D50 and later, and 5 RDSNEWBLOCKB Si4732 only) If set, generate an interrupt when Block B data is found or subsequently changed. RDS New Block A Found (Si4706,Si474x and Si4705/31/35/85-D50 and later, and 4 RDSNEWBLOCKA Si4732 only) If set, generate an interrupt when Block A data is found or subsequently changed 3 Reserved Always write to 0. 2 RDSSYNCFOUND RDS Sync Found. If set, generate RDSINT when RDS gains synchronization. 1 RDSSYNCLOST RDS Sync Lost. If set, generate RDSINT when RDS loses synchronization. RDS Received. 0 RDSRECV If set, generate RDSINT when RDS FIFO has at least FM_RDS_INT_FIFO_COUNT entries. Property 0x1501. FM_RDS_INT_FIFO_COUNT Sets the minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set. The maximum value is 25 for FRMX component 2.0 or later, and 14 for FMRX component 1.0. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Default is 0. Note: FM_RDS_INT_FIFO_COUNT is supported in FMRX component 2.0 or later. Available in: Si4705/06, Si4721, Si4731/32/35/37/39, Si4741/43/45/49 Default: 0x0000 Range: 025 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSFIFOCNT[7:0] Bit Name Function Rev. 1.2 103 AN332 7:0 RDSFIFOCNT RDS FIFO Count. Minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set. Property 0x1502. FM_RDS_CONFIG Configures RDS settings to enable RDS processing (RDSEN) and set RDS block error thresholds. When a RDS Group is received, all block errors must be less than or equal the associated block error threshold for the group to be stored in the RDS FIFO. If blocks with errors are permitted into the FIFO, the block error information can be reviewed when the group is read using the FM_RDS_STATUS command. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x0000. Note: FM_RDS_CONFIG is supported in FMRX component 2.0 or later. Available in: Si4705/06, Si4721, Si4731/32/35/37/39, Si4741/43/45/49 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name BLETHA[1:0] BLETHB[1:0] BLETHC[1:0] BLETHD[1:0] 0 0 0 0 0 0 0 RDSEN Bit 15:14 13:12 11:10 9:8 0 Name BLETHA[1:0] BLETHB[1:0] BLETHC[1:0] BLETHD[1:0] RDSEN Function Block Error Threshold BLOCKA. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. Block Error Threshold BLOCKB. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. Block Error Threshold BLOCKC. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. Block Error Threshold BLOCKD. 0 = No errors. 1 = 12 bit errors detected and corrected. 2 = 35 bit errors detected and corrected. 3 = Uncorrectable. RDS Processing Enable. 1 = RDS processing enabled. 104 Rev. 1.2 Recommended Block Error Threshold options: 2,2,2,2 = No group stored if any errors are uncorrected. 3,3,3,3 = Group stored regardless of errors. 0,0,0,0 = No group stored containing corrected or uncorrected errors. 3,2,3,3 = Group stored with corrected errors on B, regardless of errors on A, C, or D. AN332 Property 0x1503. FM_RDS_CONFIDENCE Selects the confidence level requirement for each RDS block. A higher confidence requirement will result in fewer decoder errors (% of blocks with BLE<3 that contains incorrect information) but more block errors (% of blocks with BLE=3). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x1111. Available in: Si4706-C30 and later, Si474x, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x1111 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name X X X X CONFIDENCEB[3:0] CONFIDENCEC[3:0] CONFIDENCED[3:0] Bit Name Function 11:8 CONFIDENCEB Selects decoder error rate threshold for Block B. 7:4 CONFIDENCEC Selects decoder error rate threshold for Block C. 3:0 CONFIDENCED Selects decoder error rate threshold for Block D. Property 0x1700. FM_AGC_ATTACK_RATE Sets the AGC attack rate. Larger values provide slower attack and smaller values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 4 (approximately 1500 dB/s). AGC Attack Rate (dB/s) = A-----T----T----A6----0C---0--K-0------7---:--0---- Nominal "6000" is based on 50 source impedance and will vary with source impedance. In most systems, an exact value is not important. However, to calculate for a different source impedance, perform the following steps: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 0 to 1. Record last RF level with index equal 0. 3. Increase RF level until AGC index reaches 20. Record RF level with index equal 20. 4. Replace "6000" in rate equation with "(RF20 RF0)/0.00667". Available in: Si4740/41/42/43/44/45/49 Default: 0x0004 Step: 4 Range: 4248 Rev. 1.2 105 AN332 Note: Was property 0x4100 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 ATTACK[7:0] Property 0x1701. FM_AGC_RELEASE_RATE Sets the AGC release rate. Larger values provide slower release and smaller values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 140 (approximately 43 dB/s). AGC Release Rate (dB/s) = R-----E-----L---E---6--A-0---S0---0-E-------7---:--0---- Nominal "6000" is based on 50 source impedance and will vary with source impedance. In most systems, an exact value is not important. However, to calculate for a different source impedance, perform the following steps: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 0 to 1. Record last RF level with index equal 0. 3. Increase RF level until AGC index reaches 20. Record RF level with index equal 20. 4. Replace "6000" in rate equation with "(RF20 RF0)/0.00667". Available in: Si4740/41/42/43/44/45/49 Default: 0x008C Step: 4 Range: 4248 Note: Was property 0x4101 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RELEASE[7:0] Property 0x1800. FM_BLEND_RSSI_STEREO_THRESHOLD Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set to 0. To force mono, set to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 49 dBV. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x0031 Units: dBV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 STRTHRESH[6:0] 106 Rev. 1.2 AN332 Property 0x1801. FM_BLEND_RSSI_MONO_THRESHOLD Sets RSSI threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 30 dBV. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x001E Units: dBV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 MONOTHRESH[6:0] Property 0x1802. FM_BLEND_RSSI_ATTACK_RATE Sets the stereo to mono attack rate for RSSI based blend. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 4000 (approximately 16 ms). ATTACK[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x0FA0 Step: 1 Range: 0 (disabled), 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0] Rev. 1.2 107 AN332 Property 0x1803. FM_BLEND_RSSI_RELEASE_RATE Sets the mono to stereo release rate for RSSI based blend. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 400 (approximately 164 ms). RELEASE[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4706-C30 and later, Si4740/41/42/43/44/45, Si4704/05/30/31/34/35/84/85-D50 and later, Si4732 Default: 0x0190 Step: 1 Range: 0 (disabled), 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE[15:0] 100 x = 0x1800: FM_BLEND_RSSI_STEREO_THRESHOLD (0-127 dBuV) 90 y = 0x1801: FM_BLEND_RSSI_MONO_THRESHOLD (0-127 dBuV) 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 RSSI (dBuV) x=49, y=30 (Default) x=60, y=30 x=49, y=20 Figure 4. RSSI Blend Stereo % 108 Rev. 1.2 AN332 Property 0x1804. FM_BLEND_SNR_STEREO_THRESHOLD Sets SNR threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo, set this to 0. To force mono, set this to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 27 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x001B Units: dB Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 STRTHRESH[6:0] Property 0x1805. FM_BLEND_SNR_MONO_THRESHOLD Sets SNR threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo, set to 0. To force mono, set to 127. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 14 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x000E Units: dB Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 MONOTHRESH[6:0] Rev. 1.2 109 AN332 Property 0x1806. FM_BLEND_SNR_ATTACK_RATE Sets the stereo to mono attack rate for SNR based blend. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 4000 (approximately 16 ms). ATTACK[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0FA0 Step: 1 Range: 0 (disabled), 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0] Property 0x1807. FM_BLEND_SNR_RELEASE_RATE Sets the mono to stereo release rate for SNR based blend. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 400 (approximately 164 ms). RELEASE[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0190 Step: 1 Range: 0 (disabled), 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE[15:0] 110 Rev. 1.2 AN332 Stereo % 100 x = 0x1804: FM_BLEND_SNR_STEREO_THRESHOLD (0-127 dB) 90 y = 0x1805: FM_BLEND_SNR_MONO_THRESHOLD (0-127 dB) 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 SNR (dB) x=30, y=14 (Default) x=40, y=14 x=30, y=20 Figure 5. SNR Blend Property 0x1808. FM_BLEND_MULTIPATH_STEREO_THRESHOLD Sets Multipath threshold for stereo blend (Full stereo below threshold, blend above threshold). To force stereo, set to 100. To force mono, set to 0. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0014 Step: 1 Range: 0100 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 STRTHRESH[6:0] Rev. 1.2 111 AN332 Property 0x1809. FM_BLEND_MULTIPATH_MONO_THRESHOLD Sets Multipath threshold for mono blend (Full mono above threshold, blend below threshold). To force stereo, set to 100. To force mono, set to 0. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 60. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x003C Step: 1 Range: 0100 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 MONOTHRESH[6:0] Property 0x180A. FM_BLEND_MULTIPATH_ATTACK_RATE Sets the stereo to mono attack rate for Multipath based blend. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 4000 (approximately 16 ms). ATTACK[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0FA0 Step: 1 Range: 0 (disabled), 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0] 112 Rev. 1.2 AN332 Property 0x180B. FM_BLEND_MULTIPATH_RELEASE_RATE Sets the mono to stereo release rate for Multipath based blend. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 40 (approximately 1.64 s). RELEASE[15:0] = 65536/time, where time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0028 Step: 1 Range: 0 (disabled), 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE[15:0] Stereo % 100 x = 0x1808: FM_BLEND_MP_STEREO_THRESHOLD (0-100 %) 90 y = 0x1809: FM_BLEND_MP_MONO_THRESHOLD (0-100 %) 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Multipath (%) x=20, y=60 (Default) x=30, y=60 x=20, y=80 Figure 6. MP Blend Rev. 1.2 113 AN332 Property 0x180C. FM_BLEND_MAX_STEREO_SEPARATION Sets the maximum allowable stereo separation. The default is 0, disabling the feature so that there is no limit on stereo separation. Available in: Si474x Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX_SEP[2:0] Bit Name Function 15:3 Reserved Always write to 0. 2:0 MAX_SEP Maximum Stereo Separation. 0 = disabled (default) 1 = 12 dB of separation, maximum 2 = 15 dB of separation, maximum 3 = 18 dB of separation, maximum 4 = 21 dB of separation, maximum 5 = 24 dB of separation, maximum 6 = 27 dB of separation, maximum 7 = 30 dB of separation, maximum 114 Rev. 1.2 AN332 Property 0x1900. FM_NB_DETECT_THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 16 dB. To disable the noise blanker feature, set the FM_NB_DETECT_THRESHOLD property (0x1900) to 0. Available in: Si4742/43/44/45 Default: 0x0010 Range: 090 Note: Was property 0x4106 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_DETECT_THRESHOLD [15:0] Property 0x1901. FM_NB_INTERVAL Interval in micro-seconds that original samples are replaced by interpolated clean samples. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 24 µs. Available in: Si4742/43/44/45 Default: 0x0018 Range: 848 Note: Was property 0x4107 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_INTERVAL [15:0] Property 0x1902. FM_NB_RATE Noise blanking rate in 100 Hz units. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 64 (6400 Hz). Available in: Si4742/43/44/45 Default: 0x0040 Range: 164 Note: Was property 0x4108 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_RATE [15:0] Rev. 1.2 115 AN332 Property 0x1903. FM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 300 (465 Hz). Bandwidth (Hz) = NB_IIR_FILTER[15:0] x 1.55 Available in: Si4742/43/44/45 Default: 0x012C Range: 3001600 Note: Was property 0x4109 in FW2.B. Bit D15 D14 D13 D12 D11 Name D10 D9 D8 D7 D6 NB_IIR_FILTER [15:0] D5 D4 D3 D2 D1 D0 Property 0x1904. FM_NB_DELAY Delay in micro-seconds before applying impulse blanking to the original samples. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 170 µs. Available in: Si4742/43/44/45 Default: 0x00AA Range: 125219 Note: Was property 0x410A in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_DELAY [15:0] 116 Rev. 1.2 Si4742/43 FM Impulse Noise Blanker AN332 Blanker Input time LPF IIR Output FM_NB_IIR_FILTER: adjusts LPF FM_NB_DELAY FM_NB_DETECT_THRESHOLD time FM_NB_INTERVAL Blanker Output FM_NB_RATE: sets maximum repeat rate NB is allowed to fire. Figure 7. FM Noise Blanker time Rev. 1.2 117 AN332 Property 0x1A00. FM_HICUT_SNR_HIGH_THRESHOLD Sets the SNR level at which hi-cut begins to band limit. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 24 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0018 Range: 0127 Note: Was property 0x180C in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 0 SNR_HIGH[6:0] Property 0x1A01. FM_HICUT_SNR_LOW_THRESHOLD Sets the SNR level at which hi-cut reaches maximum band limiting. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 15 dB. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x000F Range: 0127 Note: Was property 0x180D in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 0 SNR_LOW[6:0] Property 0x1A02. FM_HICUT_ATTACK_RATE Sets the rate at which hi-cut lowers the transition frequency. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 20000 (approximately 3 ms). ATTACK[15:0] = 65536/time, were time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x4E20 Range: 0 (disabled), 132767 Note: Was property 0x180E in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name ATTACK[15:0] 118 Rev. 1.2 AN332 Property 0x1A03. FM_HICUT_RELEASE_RATE Sets the rate at which hi-cut increases the transition frequency. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 20 (approximately 3.3 s). RELEASE[15:0] = 65536/time, were time is the desired transition time in ms. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0014 Range: 0 (disabled), 132767 Note: Was property 0x180F in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE[15:0] Property 0x1A04. FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD Sets the MULTIPATH level at which hi-cut begins to band limit. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 20%. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x0014 Range: 0100 Note: Was property 0x1810 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 000 MULT_TRIGGER[6:0] Property 0x1A05. FM_HICUT_MULTIPATH_END_THRESHOLD Sets the MULTIPATH level at which hi-cut reaches maximum band limiting. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 60%. Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default: 0x003C Range: 0100 Note: Was property 0x1811 in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 000 MULT_END[6:0] Rev. 1.2 119 AN332 Property 0x1A06. FM_HICUT_CUTOFF_FREQUENCY Sets the maximum band limit frequency for hi-cut and also sets the maximum audio frequency. The CTS bit (optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 0(disabled). Available in: Si4740/41/42/43/44/45, Si4704/05-D50 and later, Si4706-C30 and later, Si4730/31/34/35/84/85-D50 and later, Si4732 Default 0x0000 Range: 07 (maximum band limit frequency for Hi-Cut) 07 (maximum audio frequency) Note: Was property 0x1812 in FW2.B. The maximum audio frequency was not programmable in FW2.B. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 Name 0 0 0 0 0 0 0 0 0 D6 D5 D4 MAXIMUM AUDIO FREQ[2:0] D3 D2 D1 D0 0 FREQUENCY[2:0] Bit 6:4 2:0 Name MAXIMUM AUDIO FREQUENCY[2:0] FREQUENCY[2:0] Function Maximum Audio Frequency. 0 = Maximum Audio transition frequency = Max Audio BW 1 = Maximum Audio transition frequency = 2 kHz 2 = Maximum Audio transition frequency = 3 kHz 3 = Maximum Audio transition frequency = 4 kHz 4 = Maximum Audio transition frequency = 5 kHz 5 = Maximum Audio transition frequency = 6 kHz 6 = Maximum Audio transition frequency = 8 kHz 7 = Maximum Audio transition frequency = 11 kHz Frequency. 0 = Hi-Cut disabled 1 = Hi-cut transition frequency = 2 kHz 2 = Hi-cut transition frequency = 3 kHz 3 = Hi-cut transition frequency = 4 kHz 4 = Hi-cut transition frequency = 5 kHz 5 = Hi-cut transition frequency = 6 kHz 6 = Hi-cut transition frequency = 8 kHz 7 = Hi-cut transition frequency = 11 kHz 120 Rev. 1.2 AN332 Hi-Cut Filter Transition Frequency (kHz) 16 14 12 10 8 6 4 w = 0x1A00: FM_HICUT_SNR_HIGH_THRESHOLD (0-127 dB) 2 x = 0x1A01: FM_HICUT_SNR_LOW_THRESHOLD (0-127 dB) y = 0x1A06: FM_HICUT_CUTOFF_FREQ[2:0] (0-7) z = 0x1A06: MAXIMUM AUDIO FREQ[6:4] (0-7) 0 0 2 4 6 8 10 12 14 w=24, x=15, y=0, z=0 (Default) 16 18 20 22 24 26 28 SNR (dB) w=24, x=15, y=1, z=0 30 32 34 36 38 40 w=30, x=15, y=1, z=0 Figure 8. HiCut Controlled by SNR Metric 9 8 Hi-Cut Filter Transition Frequency (kHz) 7 6 5 4 3 2 w = 0x1A00: FM_HICUT_SNR_HIGH_THRESHOLD (0-127 dB) x = 0x1A01: FM_HICUT_SNR_LOW_THRESHOLD (0-127 dB) 1 y = 0x1A06: FM_HICUT_CUTOFF_FREQ[2:0] (0-7) z = 0x1A06: MAXIMUM AUDIO FREQ[6:4] (0-7) 0 0 2 4 6 8 10 12 14 w=24, x=15, y=0, z=6 (Default) 16 18 20 22 24 26 28 SNR (dB) w=24, x=15, y=1, z=6 30 32 34 36 38 40 w=30, x=15, y=1, z=6 Figure 9. HiCut Controlled by SNR Metric with Maximum Audio Frequency 8 kHz Rev. 1.2 121 AN332 Hi-Cut Filter Transition Frequency (kHz) 16 14 w = 0x1A04: FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD (0-100 %) x = 0x1A05: FM_HICUT_MULTIPATH_END_THRESHOLD (0-100 %) y = 0x1A06: FM_HICUT_CUTOFF_FREQ[2:0] (0-7) z = 0x1A06: MAXIMUM AUDIO FREQ[6:4] (0-7) 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 Multipath (%) w=20, x=60, y=0, z=0 (Default) w=20, x=60, y=1, z=0 80 90 100 w=30, x=60, y=1, z=0 Figure 10. HiCut Controlled by Multipath Metric 9 Hi-Cut Filter Transition Frequency (kHz) 8 w = 0x1A04: FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD (0-100 %) 7 x = 0x1A05: FM_HICUT_MULTIPATH_END_THRESHOLD (0-100 %) y = 0x1A06: FM_HICUT_CUTOFF_FREQ[2:0] (0-7) z = 0x1A06: MAXIMUM AUDIO FREQ[6:4] (0-7) 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 Multipath (%) w=20, x=60, y=0, z=6 (Default) w=20, x=60, y=1, z=6 80 90 100 w=30, x=60, y=1, z=6 Figure 11. HiCut Controlled by Multipath Metric with Maximum Audio Frequency 8 kHz 122 Rev. 1.2 AN332 Property 0x4000. RX_VOLUME Sets the audio output volume. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 63. Available in: All except Si4749 Default: 0x003F Step: 1 Range: 063 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 VOL[5:0] Bit Name Function 15:6 Reserved Always write to 0. 5:0 VOL Output Volume. Sets the output volume level, 63 max, 0 min. Default is 63. Property 0x4001. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may be muted independently. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is unmute (0x0000). Available in: All except Si4749 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name 15:2 Reserved Always write to 0. 1 LMUTE Mutes L Audio Output. 0 RMUTE Mutes R Audio Output. Function Rev. 1.2 123 AN332 5.3. Commands and Properties for the AM/SW/LW Receiver (Si4730/31/32/34/35/36/37/40/41/42/43/44/45) AM (Medium Wave), SW (Short Wave), and LW (Long Wave) use the same AM_SW_LW component, thus the commands and properties for these functions are the same. For simplicity reason, the commands and properties only have a prefix AM instead of AM_SW_LW. The main difference among AM, SW, and LW is on the frequency range. The common frequency range and spacing for AM/SW/LW are: SW AM in US AM in Asia LW 2.3 MHz to 23 MHz in 5 kHz frequency spacing 520 kHz to 1.71 MHz in 10 kHz frequency spacing 522 kHz to 1.71 MHz in 9 kHz frequency spacing 153 kHz to 279 kHz in 9 kHz frequency spacing Tables 12 and 13 summarize the commands and properties for the AM/SW/LW Receiver components applicable to Si473x/4x. Table 12. AM/LW/SW Receiver Command Summary Cmd Name Description Available In 0x01 POWER_UP Power up device and mode selection. All 0x10 GET_REV Returns revision information on the device. All 0x11 POWER_DOWN Power down device. All 0x12 SET_PROPERTY Sets the value of a property. All 0x13 GET_PROPERTY Retrieves a property's value. All 0x14 GET_INT_STATUS Read interrupt status bits. All 0x15 PATCH_ARGS* Reserved command used for patch file downloads. All 0x16 PATCH_DATA* Reserved command used for patch file downloads. All 0x40 AM_TUNE_FREQ Tunes to a given AM frequency. All 0x41 AM_SEEK_START Begins searching for a valid frequency. All 0x42 AM_TUNE_STATUS Queries the status of the already issued AM_TUNE_FREQ or AM_SEEK_START command. All 0x43 AM_RSQ_STATUS Queries the status of the Received Signal Quality (RSQ) for the current channel. All 0x47 AM_AGC_STATUS Queries the current AGC settings. All 0x48 AM_AGC_OVERRIDE Overrides AGC settings by disabling and forcing it to a fixed value. All 0x80 GPIO_CTL Configures GPO1, 2, and 3 as output or Hi-Z. All 0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high). All *Note: Commands PATCH_ARGS and PATCH_DATA are only used to patch firmware. For information on applying a patch file, see "7.2. Powerup from a Component Patch" on page 236. 124 Rev. 1.2 AN332 Prop 0x0001 Table 13. AM/SW/LW Receiver Property Summary Name GPO_IEN Description Enables interrupt sources. 0x0102 DIGITAL_OUTPUT_ FORMAT Configure digital audio outputs 0x0104 DIGITAL_OUTPUT_ SAMPLE_RATE Configure digital audio output sample rate 0x0201 0x0202 0x3100 0x3102 Sets frequency of reference clock in Hz. The range REFCLK_FREQ is 31130 to 34406 Hz, or 0 to disable the AFC. Default is 32768 Hz. REFCLK_PRESCALE Sets the prescaler value for RCLK input. AM_DEEMPHASIS Sets deemphasis time constant. Can be set to 50 µs. Deemphasis is disabled by default. Selects the bandwidth of the channel filter for AM AM_CHANNEL_FILTER1 reception. The choices are 6, 4, 3, 2, 2.5, 1.8, or 1 (kHz). The default bandwidth is 2 kHz. 0x3103 AM_AUTOMATIC_ VOLUME_CONTROL_ MAX_GAIN Sets the maximum gain for automatic volume control. Default 0x0000 0x0000 0x0000 0x8000 0x0001 0x0000 0x0003 0x1543 0x7800 Available In All Si4705/06, Si4731/35/37/39, Si4730/34/36/38- D60 and later, Si4732, Si4741/43/45, Si4784/85 Si4705/06, Si4731/35/37/39, Si4730/34/36/38- D60 and later, Si4732, Si4741/43/45, Si4784/85 All All All All Si473x-C40 and later, Si4732 Si474x 0x3104 AM_MODE_AFC_SW_ PULL_IN_RANGE Sets the SW AFC pull-in range. 0x21F7 Si4734/35-C40 and later, Si4732, Si4742/43/44/45 0x3105 AM_MODE_AFC_SW_ LOCK_IN_RANGE Sets the SW AFC lock-in. 0x2DF5 Si4734/35-C40 and later, Si4732, Si4742/43/44/45 Configures interrupt related to Received Signal 0x3200 AM_RSQ_INTERRUPTS Quality metrics. All interrupts are disabled by 0x0000 All default. Notes: 1. The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later devices and Si4732 devices and Si474x devices (AM_SW_LW component 3.0 or later). The 2.5 kHz option is supported on Si473x-C40 and later devices and Si4732 devices (AM_SW_LW component 5.0 or later). 2. Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command. Rev. 1.2 125 AN332 Table 13. AM/SW/LW Receiver Property Summary (Continued) Prop Name Description 0x3201 0x3202 0x3203 0x3204 0x3300 AM_RSQ_SNR_HIGH_ THRESHOLD Sets high threshold for SNR interrupt. AM_RSQ_SNR_LOW_ THRESHOLD Sets low threshold for SNR interrupt. AM_RSQ_RSSI_HIGH_ THRESHOLD Sets high threshold for RSSI interrupt. AM_RSQ_RSSI_LOW_ THRESHOLD Sets low threshold for RSSI interrupt. AM_SOFT_MUTE_RATE Sets the attack and decay rates when entering or leaving soft mute. The default is 278 dB/s. 0x3301 AM_SOFT_MUTE_ SLOPE Sets the AM soft mute slope. Default value is a slope of 1. Default 0x007F Available In All 0x0000 All 0x007F All 0x0000 All 0x0040 0x0002 All Si4730/31/34/35/ 36/37-B20 and earlier, Si4740/41/42/43/ 44/45-C10 and earlier 0x3302 AM_SOFT_MUTE_MAX_ Sets maximum attenuation during soft mute (dB). ATTENUATION Set to 0 to disable soft mute. Default is 8 dB. 0x0001 0x0010 All others Si4730/31/34/35/ 36/37-B20 and earlier, Si4740/41/42/43/ 44/45-C10 and earlier 0x0008 All others 0x3303 AM_SOFT_MUTE_SNR_ Sets SNR threshold to engage soft mute. Default is THRESHOLD 8 dB. 0x000A Si4730/31/34/35/ 36/37-B20 and earlier, Si4740/41/42/43/ 44/45-C10 and earlier 0x0008 All others 0x3304 AM_SOFT_MUTE_ RELEASE_RATE Sets softmute release rate. Smaller values provide slower release, and larger values provide faster release. The default is 8192 (approximately 8000 dB/s). 0x2000 Si4740/41/42/43/ 44/45 Notes: 1. The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later devices and Si4732 devices and Si474x devices (AM_SW_LW component 3.0 or later). The 2.5 kHz option is supported on Si473x-C40 and later devices and Si4732 devices (AM_SW_LW component 5.0 or later). 2. Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command. 126 Rev. 1.2 AN332 Table 13. AM/SW/LW Receiver Property Summary (Continued) Prop Name Description Default Available In 0x3305 AM_SOFT_MUTE_ ATTACK_RATE Sets software attack rate. Smaller values provide slower attack, and larger values provide faster attack. The default is 8192 (approximately 8000 dB/s). 0x2000 Si4740/41/42/43/ 44/45 0x3400 AM_SEEK_BAND_ BOTTOM Sets the bottom of the AM band for seek. Default is 520. 0x0208 All 0x3401 AM_SEEK_BAND_TOP2 Sets the top of the AM band for seek. Default is 1710. 0x06AE All 0x3402 AM_SEEK_FREQ_ SPACING Selects frequency spacing for AM seek. Default is 10 kHz spacing. 0x000A All Sets the SNR threshold for a valid AM Seek/Tune. If 0x3403 AM_SEEK_SNR_ THRESHOLD the value is zero then SNR threshold is not considered when doing a seek. Default value is 0x0005 All 5 dB. Sets the RSSI threshold for a valid AM Seek/Tune. If 0x3404 AM_SEEK_RSSI_ THRESHOLD the value is zero then RSSI threshold is not considered when doing a seek. Default value is 0x0019 All 25 dBµV. 0x3702 AM_AGC_ATTACK_ RATE Sets the number of milliseconds the high peak detector must be exceeded before decreasing gain. Default value is 4 (approximately 1400 dB/s). 0x0004 Si4740/41/42/43/ 44/45 0x3703 0x3705 Sets the number of milliseconds the low peak AM_AGC_RELEASE_RA detector must not be exceeded before increasing TE the gain. Default value is 140 (approximately 40 dB/s). AM_FRONTEND_AGC_ Adjusts AM AGC for frontend (external) attenuator CONTROL and LNA. (Si4740/41/42/43/44/45 only) 0x008C Si4740/41/42/43/ 44/45 0x130C Si4740/41/42/43/ 44/45 0x3900 AM_NB_DETECT_ THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor. Default value is 12. 0x000C Si4742/43/44/45 0x3901 AM_NB_INTERVAL Interval in micro-seconds that original samples are replaced by interpolated clean samples. Default value is 55 µs. 0x0037 Si4742/43/44/45 0x3902 AM_NB_RATE Noise blanking rate in 100 Hz units. Default value is 64. 0x0040 Si4742/43/44/45 0x3903 AM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator. Default value is 300. 0x012C Si4742/43/44/45 Notes: 1. The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later devices and Si4732 devices and Si474x devices (AM_SW_LW component 3.0 or later). The 2.5 kHz option is supported on Si473x-C40 and later devices and Si4732 devices (AM_SW_LW component 5.0 or later). 2. Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command. Rev. 1.2 127 AN332 Table 13. AM/SW/LW Receiver Property Summary (Continued) Prop Name Description Default Available In 0x3904 0x4000 AM_NB_DELAY RX_VOLUME Delay in micro-seconds before applying impulse blanking to the original samples. Default value is 172. Sets the output volume. 0x00AC Si4742/43/44/45 0x003F All 0x4001 RX_HARD_MUTE Mutes the L and R audio outputs. 0x0000 All Notes: 1. The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later devices and Si4732 devices and Si474x devices (AM_SW_LW component 3.0 or later). The 2.5 kHz option is supported on Si473x-C40 and later devices and Si4732 devices (AM_SW_LW component 5.0 or later). 2. Component 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command. 128 Rev. 1.2 AN332 Bit STATUS Table 14. Status Response for the AM/SW/LW Receiver D7 D6 D5 D4 D3 D2 D1 CTS ERR X X RSQINT X X D0 STCINT Bit Name Function Clear to Send. 7 CTS 0 = Wait before sending next command. 1 = Clear to send next command. Error. 6 ERR 0 = No error 1 = Error 5:4 Reserved Values may vary. Received Signal Quality Interrupt. 3 RSQINT 0 = Received Signal Quality measurement has not been triggered. 1 = Received Signal Quality measurement has been triggered. 2:1 Reserved Values may vary. Seek/Tune Complete Interrupt. 0 STCINT 0 = Tune complete has not been triggered. 1 = Tune complete has been triggered. Rev. 1.2 129 AN332 5.3.1. AM/SW/LW Receiver Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the response, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 1 (AM/SW/LW Receive) and the patch may be applied. See Section "7.2. Powerup from a Component Patch" on page 236 for more information. The POWER_UP command configures the state of ROUT (pin 13, Si4732 pin 16) and LOUT (pin 14, Si4732 pin 1) for analog audio mode and GPO2/INT (pin 18, Si4732 pin 3) for interrupt operation. For the Si4731/32/35/37, the POWER_UP command also configures the state of GPO3/DCLK (pin 17, Si4732 pin 2), DFS (pin 16, Si4732 pin 1), and DOUT (pin 15, Si4732 pin 16) for digital audio mode. The command configures GPO2/INT interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g. AM/SW/LW RX to FM RX), issue POWER_DOWN command to stop current function; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tune command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 1), Seven (FUNC = 15) Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit 1 7 1 6 1 5 Name CTSIEN GPO2OEN PATCH Function CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. GPO2 Output Enable. 0 = GPO2 output disabled (Hi-Z). 1 = GPO2 output enabled. Patch Enable. 0 = Boot normally 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched. 130 Rev. 1.2 AN332 ARG Bit 1 4 1 3:0 2 7:0 Name XOSCEN FUNC[3:0] OPMODE[7:0] Function Crystal Oscillator Enable. 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crystal and OPMODE = 00000101). See Si473x Data Sheet Application Schematic for external BOM details. Function. 0 = Reserved. 1 = AM/SW/LW Receive. 214 = Reserved. 15 = Query Library ID. Application Setting 00000101 = Analog audio outputs (LOUT/ROUT). 00001011 = Digital audio output (DCLK, LOUT/DFS, ROUT/DIO)(Si4731/32/35/37 only with XOSCEN = 0) 10110000 = Digital audio outputs (DCLK, DFS, DIO) (Si4731/35/37 only with XOSCEN = 0). 10110101 = Analog and digital audio outputs (LOUT/ROUT and DCLK, DFS, DIO) (Si4731/35/37 only with XOSCEN = 0). Response (to FUNC = 1, AM Receive) Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 X RSQINT X D1 D0 X STCINT Response (to FUNC = 15, Query Library ID) Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 D6 D5 CTS ERR X D4 D3 D2 X RSQINT X PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] D1 D0 X STCINT RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] Function Final 2 digits of part number (HEX). Firmware Major Revision (ASCII). Firmware Minor Revision (ASCII). Reserved, various values. Reserved, various values. Chip Revision (ASCII). Library Revision (HEX). Rev. 1.2 131 AN332 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Eight Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 Response Bit D7 D6 D5 D4 D3 D2 STATUS CTS ERR X X RSQINT X RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESP5 RESP6 PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] D1 D0 X STCINT RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 8 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] Function Final 2 digits of Part Number (HEX). Firmware Major Revision (ASCII). Firmware Minor Revision (ASCII). Patch ID High Byte (HEX). Patch ID Low Byte (HEX). Component Major Revision (ASCII). Component Minor Revision (ASCII). Chip Revision (ASCII). 132 Rev. 1.2 AN332 Command 0x11. POWER_DOWN Moves the device from powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: In AMRX component 1.0, a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, GPIO3 = 0 ROUT, LOUT, DOUT, DFS = HiZ Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 1 Response Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 X RSQINT X D1 D0 X STCINT Rev. 1.2 133 AN332 Command 0x12. SET_PROPERTY Sets a property shown in Table 13, "AM/SW/LW Receiver Property Summary," on page 125. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. See Figure 30, "CTS and SET_PROPERTY Command Complete tCOMP Timing Model," on page 246 and Table 51, "Command Timing Parameters for the AM Receiver," on page 249. Available in: All Command Arguments: Five Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] PROPDH[7:0] PROPDL[7:0] ARG 1 2 3 4 5 Bit Name Function 7:0 Reserved Always write to 0. Property High Byte. 7:0 PROPH[7:0] This byte in combination with PROPL is used to specify the property to modify. See Section "5.3.2. AM/SW/LW Receiver Properties" on page 147. Property Low Byte. 7:0 PROPL[7:0] This byte in combination with PROPH is used to specify the property to modify. See Section "5.3.2. AM/SW/LW Receiver Properties" on page 147. Property Value High Byte. 7:0 PROPDH[7:0] This byte in combination with PROPDL is used to set the property value. See Section "5.3.2. AM/SW/LW Receiver Properties" on page 147. Property Value Low Byte. 7:0 PROPDL[7:0] This byte in combination with PROPDH is used to set the property value. See Section "5.3.2. AM/SW/LW Receiver Properties" on page 147. 134 Rev. 1.2 AN332 Command 0x13. GET_PROPERTY Gets a property shown in Table 13, "AM/SW/LW Receiver Property Summary," on page 125. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 Response Name Reserved PROPH[7:0] PROPL[7:0] Function Always write to 0. Property High Byte. This byte in combination with PROPL is used to specify the property to get. Property Low Byte. This byte in combination with PROPH is used to specify the property to get. Bit D7 D6 D5 STATUS CTS ERR X RESP1 0 0 0 RESP2 RESP3 D4 D3 D2 X RSQINT X 0 0 0 PROPDH[7:0] PROPDL[7:0] D1 D0 X STCINT 0 0 RESP Bit 1 7:0 2 7:0 3 7:0 Name Reserved PROPDH[7:0] PROPDL[7:0] Function Always returns 0. Property Value High Byte. This byte in combination with PROPDL represents the requested property value. Property Value High Byte. This byte in combination with PROPDH represents the requested property value. Rev. 1.2 135 AN332 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command should be called after any command that sets the STCINT or RSQINT bits. When polling this command should be periodically called to monitor the STATUS byte, and when using interrupts, this command should be called after the interrupt is set to update the STATUS byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be set when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 0 Response Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 X RSQINT X D1 D0 X STCINT Command 0x40. AM_TUNE_FREQ Tunes the AM/SW/LW receive to a frequency between 149 and 23 MHz in 1 kHz steps. In AM only mode, the valid frequency is between 520 and 1710 kHz in 1 kHz steps. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 51, "Command Timing Parameters for the AM Receiver," on page 249. AM: LO frequency is 45 kHz above RF for RF frequencies < 1000 kHz and 45 kHz below RF for RF frequencies > 1000 kHz. For example, LO frequency is 945 kHz when tuning to 900 kHz. Note: FAST bit is supported in Si473x-C40 and later devices and Si4732 devices and Si474x devices (AMRX component 3.0 or later). ANTCAP bits are supported in AMRX component 2.0 or later (all devices except Si4730-A10). Available in: All Command arguments: Five Response bytes: None Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST 136 Rev. 1.2 AN332 ARG2 ARG3 ARG4 ARG5 FREQH[7:0] FREQL[7:0] ANTCAPH[15:8] ANTCAPL[7:0] ARG Bit Name Function 1 7:1 Reserved Always write to 0. 1 0 FAST FAST Tuning. If set, executes fast and invalidated tune. The tune status will not be accurate. Tune Frequency High Byte. 2 7:0 FREQH [7:0] This byte in combination with FREQL selects the tune frequency in kHz. In AM/SW/LW mode, the valid range is from 149 to 23000 (149 kHz23 MHz). In AM only mode the valid range is from 520 to 1710 (5201710 kHz). Tune Frequency Low Byte. 3 7:0 FREQL [7:0] This byte in combination with FREQH selects the tune frequency in kHz. In AM/SW/LW mode, the valid range is from 149 to 23000 (149 kHz23 MHz). In AM only mode the valid range is from 520 to 1710 (5201710 kHz). Antenna Tuning Capacitor High Byte. This byte in combination with ANTCAPL selects the tuning capacitor value. If both 4 15:8 ANTCAPH [15:8] bytes are set to zero, the tuning capacitor value is selected automatically. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 16143. Automatic capacitor tuning is recom- mended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. Antenna Tuning Capacitor Low Byte. This byte in combination with ANTCAPH selects the tuning capacitor value. If both 5 7:0 ANTCAPL [7:0] bytes are set to zero, the tuning capacitor value is selected automatically. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 16143. Automatic capacitor tuning is recommended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. Response Bit STATUS D7 D6 D5 D4 D3 D2 CTS ERR X X RSQINT X D1 D0 X STCINT Rev. 1.2 137 AN332 Command 0x41. AM_SEEK_START Initiates a seek for a channel that meets the RSSI and SNR criteria for AM. Clears any pending STCINT or RSQINT interrupt status. RSQINT is only cleared by the RSQ status command when the INTACK bit is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STCINT bit if it is already set. See Figure 29, "CTS and STC Timing Model," on page 246 and Table 51, "Command Timing Parameters for the AM Receiver," on page 249. Note: ANTCAP bits are supported in AMRX component 2.1 or later. Available in: All Command arguments: Five Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 0 0 0 0 1 ARG1 0 0 0 0 SEEKUP WRAP 0 0 ARG2 0 0 0 0 0 0 0 0 ARG3 0 0 0 0 0 0 0 0 ARG4 ARG5 ANTCAPH[15:8] ANTCAPL[7:0] 138 Rev. 1.2 AN332 ARG 1 1 1 1 2 3 4 5 Bit Name Function 7:4 Reserved Always write to 0. 3 SEEKUP Seek Up/Down. Determines the direction of the search, either UP = 1, or DOWN = 0. Wrap/Halt. 2 WRAP Determines whether the seek should Wrap = 1, or Halt = 0 when it hits the band limit. 1:0 Reserved Always write to 0. 7:0 Reserved Always write to 0. 7:0 Reserved Always write to 0. Antenna Tuning Capacitor High Byte. This byte in combination with ANTCAPL selects the tuning capacitor value. If both bytes are set to zero, the tuning capacitor value is selected automati- 15:8 ANTCAPH[15:8] cally. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 16143. Automatic capacitor tuning is recommended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. Antenna Tuning Capacitor Low Byte. This byte in combination with ANTCAPH selects the tuning capacitor value. If both bytes are set to zero, the tuning capacitor value is selected automati- 7:0 ANTCAPL[7:0] cally. If the value is set to anything other than 0, the tuning capacitance is manually set as 95 fF x ANTCAP + 7 pF. ANTCAP manual range is 16143. Automatic capacitor tuning is recommended. Note: In SW mode, ANTCAPH[15:8] needs to be set to 0 and ANTCAPL[7:0] needs to be set to 1. Response Bit STATUS D7 D6 D5 D4 D3 D2 CTS ERR X X RSQINT X D1 D0 X STCINT Rev. 1.2 139 AN332 Command 0x42. AM_TUNE_STATUS Returns the status of AM_TUNE_FREQ or AM_SEEK_START commands. The commands returns the current frequency, RSSI, SNR, and the antenna tuning capacitance value (06143). The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: AFCRL bit does not work properly on AMRX component 2.1 or earlier. Available in: All Command arguments: One Response bytes: Seven Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 CANCEL INTACK ARG Bit 1 7:2 1 1 1 0 Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 Name Reserved CANCEL INTACK Function Always write to 0. Cancel seek. If set, aborts a seek currently in progress. Seek/Tune Interrupt Clear. If set, clears the seek/tune complete interrupt status indicator. D7 CTS BLTF D6 ERR X D5 D4 D3 X X RSQINT X X X READFREQH[7:0] READFREQL[7:0] RSSI[7:0] SNR[7:0] READANTCAPH [15:8] READANTCAPL [7:0] D2 D1 D0 X X STCINT X AFCRL VALID 140 Rev. 1.2 AN332 RESP Bit Name Function 17 BLTF Band Limit. Reports if a seek hit the band limit (WRAP = 0 in AM_START_SEEK) or wrapped to the original frequency (WRAP = 1). 1 6:2 Reserved Always returns 0. 11 AFCRL AFC Rail Indicator. Set if the AFC rails. 10 VALID Valid Channel. Set if the channel is currently valid and would have been found during a seek. Read Frequency High Byte. 2 7:0 READFREQH[7:0] This byte in combination with READFREQL returns frequency being tuned (kHz). Read Frequency Low Byte. 3 7:0 READFREQL[7:0] This byte in combination with READFREQH returns frequency being tuned (kHz). 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte contains the receive signal strength when tune is completed (dBµV). 5 7:0 SNR[7:0] SNR. This byte contains the SNR metric when tune is completed (dB). Read Antenna Tuning Capacitor High Byte. 6 7:0 READANTCAPH [15:8] This byte in combination with READANTCAPL returns the current antenna tuning capacitor value. The tuning capacitance is 95 fF x READANTCAP + 7 pF. Read Antenna Tuning Capacitor Low Byte. 7 7:0 READANTCAPL [7:0] This byte in combination with READANTCAPH returns the current antenna tuning capacitor value. The tuning capacitance is 95 fF x READANTCAP + 7 pF. Rev. 1.2 141 AN332 Command 0x43. AM_RSQ_STATUS Returns status information about the received signal quality. The commands returns RSSI and SNR. It also indicates valid channel (VALID), soft mute engagement (SMUTE), and AFC rail status (AFCRL). This command can be used to check if the received signal is above the RSSI high threshold as reported by RSSIHINT, or below the RSSI low threshold as reported by RSSILINT. It can also be used to check if the signal is above the SNR high threshold as reported by SNRHINT, or below the SNR low threshold as reported by SNRLINT. The command clears the RSQINT, SNRHINT, SNRLINT, RSSIHINT, and RSSILINT interrupt bits when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note: AFCRL bit does not work properly on AMRX component 2.1 or earlier. Available in: All Command arguments: One Response bytes: Five Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 INTACK ARG Bit 1 0 Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 Name INTACK Function Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears RSQINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT D7 CTS X X X D6 D5 ERR X X X X X X X D4 D3 D2 X RSQINT X X SNRHINT SNRLINT X SMUTE X X X X RSSI[7:0] SNR[7:0] D1 X RSSIHINT AFCRL X D0 STCINT RSSIILINT VALID X 142 Rev. 1.2 AN332 RESP Bit 1 3 1 2 1 1 1 0 2 3 2 1 2 0 4 7:0 5 7:0 Name SNRHINT SNRLINT RSSIHINT RSSILINT SMUTE AFCRL VALID RSSI[7:0] SNR[7:0] Function SNR Detect High. 0 = Received SNR has not exceeded above SNR high threshold. 1 = Received SNR has exceeded above SNR high threshold. SNR Detect Low. 0 = Received SNR has not exceeded below SNR low threshold. 1 = Received SNR has exceeded below SNR low threshold. RSSI Detect High. 0 = RSSI has not exceeded above RSSI high threshold. 1 = RSSI has exceeded above RSSI high threshold. RSSI Detect Low. 0 = RSSI has not exceeded below RSSI low threshold. 1 = RSSI has exceeded below RSSI low threshold. Soft Mute Indicator. Indicates soft mute is engaged. AFC Rail Indicator. Set if the AFC rails. Valid Channel. Set if the channel is currently valid and would have been found during a seek. Received Signal Strength Indicator. Contains the current receive signal strength (dBµV). SNR. Contains the current SNR metric (dB). Command 0x47. AM_AGC_STATUS Returns the AM AGC setting of the device. The command returns whether the AGC is enabled or disabled and it returns the gain index. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in power up mode. Available in: All Command arguments: None Response bytes: Two Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 1 1 Response Bit STATUS RESP1 RESP2 D7 CTS X D6 ERR X D5 D4 D3 D2 X X RSQINT X X X X X AMAGCNDX[7:0] D1 D0 X STCINT X AMAGCDIS Rev. 1.2 143 AN332 RESP Bit 1 0 2 7:0 Name AMAGCDIS AMAGCNDX Function AM AGC Disable This bit indicates if the AGC is enabled or disabled. 0 = AGC enabled. 1 = AGC disabled. AM AGC Index This byte reports the current AGC gain index. 0 = Minimum attenuation (max gain) 1 36+ATTN_BACKUP = Intermediate attenuation 37+ATTN_BACKUP = Maximum attenuation (min gain) Note: The max index is subject to change. See Property 0x3705 AM_FRONTEND_AGC_CONTROL for details on ATTN_BACKUP. Command 0x48. AM_AGC_OVERRIDE Overrides the AM AGC setting by disabling the AGC and forcing the gain index that ranges between 0 (minimum attenuation) and 37+ATTN_BACKUP (maximum attenuation). The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in power up mode. Available in: All Command arguments: Two Response bytes: None Command Bit CMD ARG1 ARG2 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 AMAGCDIS AMAGCNDX[7:0] ARG Bit 1 0 2 7:0 Response Bit STATUS Name AMAGCDIS AMAGCNDX Function AM AGC Disable This bit selects whether the AGC is enabled or disabled. 0 = AGC enabled. 1 = AGC disabled. AM AGC Index If AMAGCDIS = 1, this byte forces the AGC gain index. 0 = Minimum attenuation (max gain) 1 36+ATTN_BACKUP = Intermediate attenuation 37+ATTN_BACKUP = Maximum attenuation (min gain) *Note: The max index is subject to change. See Property 0x3705 AM_FRONTEND_AGC_CONTROL for details on ATTN_BACKUP. D7 D6 D5 CTS ERR X D4 D3 D2 X RSQINT X D1 D0 X STCINT 144 Rev. 1.2 AN332 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (high or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 1. GPIO_CTL is supported in AM_SW_LW component 2.0 or later. 2. The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Name Reserved GPO3OEN GPO2OEN GPO1OEN Reserved Function Always write 0. GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. Always write 0. Bit D7 D6 D5 D4 STATUS CTS ERR X X D3 D2 X RDSINT D1 ASQINT D0 STCINT Rev. 1.2 145 AN332 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Note: GPIO_SET is supported in AM_SW_LW component 2.0 or later. Available in: All Command arguments: One Response bytes: None Command Bit D7 CMD 1 ARG1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Bit STATUS Name Reserved GPO3LEVEL GPO2LEVEL GPO1LEVEL Reserved Always write 0. GPO3 Output Level. 0 = Output low (default). 1 = Output high. GPO2 Output Level. 0 = Output low (default). 1 = Output high. GPO1 Output Level. 0 = Output low (default). 1 = Output high. Always write 0. Function D7 D6 D5 D4 CTS ERR X X D3 D2 X RDSINT D1 ASQINT D0 STCINT 146 Rev. 1.2 AN332 5.3.2. AM/SW/LW Receiver Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RSQINT, and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading this property and modified by writing this property. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 RSQREP 0 0 STCREP CTSIEN ERRIEN 0 0 RSQIEN 0 0 STCIEN Bit 15:12 11 10:9 8 7 6 5:4 3 2:1 0 Name Reserved RSQREP Reserved STCREP CTSIEN ERRIEN Reserved RSQIEN Reserved STCIEN Function Always write to 0. RSQ Interrupt Repeat. 0 = No interrupt generated when RSQINT is already set (default) 1 = Interrupt generated even if RSQINT is already set Always write to 0. STC Interrupt Repeat. 0 = No interrupt generated when STCINT is already set (default) 1 = Interrupt generated even if STCINT is already set CTS Interrupt Enable. After PowerUp, this bit reflects the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set 1 = Interrupt generated when CTS is set ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default) 1 = Interrupt generated when ERR is set Always write to 0. RSQ Interrupt Enable. 0 = No interrupt generated when RSQINT is set (default) 1 = Interrupt generated when RSQINT is set Always write to 0. Seek/Tune Complete Interrupt Enable. 0 = No interrupt generated when STCINT is set (default) 1 = Interrupt generated when STCINT is set Rev. 1.2 147 AN332 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Note: DIGITAL_OUTPUT_FORMAT is supported in AM_SW_LW component 2.0 or later. Available in: Si4705/06, Si4731/32/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 7 OFALL 6 5 4 32 OMODE[3:0] 0 1 0 OSIZE[1:0] Bit Name Function 15:8 Reserved Always write to 0. Digital Output DCLK Edge. 7 OFALL 0 = use DCLK rising edge 1 = use DCLK falling edge Digital Output Mode. 0000 = I2S 6:3 OMODE[3:0] 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse 2 Reserved Always write to 0. Digital Output Audio Sample Precision. 0 = 16-bits 1:0 OSIZE[1:0] 1 = 20-bits 2 = 24-bits 3 = 8-bits 148 Rev. 1.2 AN332 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The over-sampling rate must be set in order to satisfy a minimum DCLK of 1 MHz. The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before DCLK/DFS is removed. AM_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_OUTPUT_SAMPLE_RATE is supported in AM_SW_LW component 2.0 or later. Available in: Si4705/06, Si4731/32/35/37/39, Si4730/34/36/38-D60 and later, Si4741/43/45, Si4784/85 Default: 0x0000 (digital audio output disabled) Units: sps Range: 3248 ksps, 0 to disable digital audio output Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 3248 ksps. 0 to disable digital audio output. Rev. 1.2 149 AN332 Property 0x0201. REFCLK_FREQ Sets the frequency of the REFCLK from the output of the prescaler. The REFCLK range is 31130 to 34406 Hz (32768 5% Hz) in 1 Hz steps, or 0 (to disable AFC). For example, an RCLK of 13MHz would require a prescaler value of 400 to divide it to 32500 Hz REFCLK. The reference clock frequency property would then need to be set to 32500 Hz. RCLK frequencies between 31130 Hz and 40 MHz are supported, however, there are gaps in frequency coverage for prescaler values ranging from 1 to 10, or frequencies up to 311300 Hz. The following table summarizes these RCLK gaps. PIN 9 RCLK 31.130 kHz 40 MHz Prescaler Divide by 1-4095 REFCLK 31.130 kHz 34.406 kHz Figure 12. REFCLK Prescaler Table 15. RCLK Gaps Prescaler 1 2 3 4 5 6 7 8 9 10 RCLK Low (Hz) 31130 62260 93390 124520 155650 186780 217910 249040 280170 311300 RCLK High (Hz) 34406 68812 103218 137624 172030 206436 240842 275248 309654 344060 The RCLK must be valid 10 ns before and 10 ns after completing the WB_TUNE_FREQ command. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AGC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is 32768 Hz. Available in: All Default: 0x8000 (32768) Units: 1 Hz Step: 1Hz Range: 31130-34406 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF[15:0] 150 Rev. 1.2 AN332 Bit Name Function 15:0 REFCLKF[15:0] Frequency of Reference Clock in Hz. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC). Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before sending and 20 ns after completing the AM_TUNE_FREQ and AM_SEEK_START commands. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 14095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLK SEL RCLKP[11:0] Bit 15:13 12 11:0 Name Reserved RCLKSEL RCLKP[11:0] Function Always write to 0. RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. Prescaler for Reference Clock. Integer number used to divide the RCLK frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406* Hz (32768 ±5%), or 0 (to disable AFC). *Note: For shortwave frequencies, choose a prescalar value such that you can limit the REFCLK frequency range to 31130 32768* Hz. Rev. 1.2 151 AN332 Property 0x3100. AM_DEEMPHASIS Sets the AM Receive de-emphasis to 50 µs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is disabled. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEMPH Bit Name 15:1 Reserved Always write to 0. AM De-Emphasis. 0 DEEMPH 1 = 50 µs. 0 = Disabled. Function Property 0x3102. AM_CHANNEL_FILTER Selects the bandwidth of the AM channel filter. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 2 kHz bandwidth channel filter. Note: The 1 kHz option, 1.8 kHz option, and 100 Hz high-pass Line Noise Rejection filter are supported on Si473x-C40 and later devices and Si4732 devices and Si474x devices (AM_SW_LW component 3.0 or later). The 2.5 kHz option is supported on Si473x-C40 and later devices and Si4732 devices (AM_SW_LW component 5.0 or later). Available in: All Default: 0x0003 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 AMPLFLT 0 0 0 0 AMCHFLT[03:0] Bit Name Function 15:9 Reserved Always write to 0. 8 AMPLFLT Enables the AM Power Line Noise Rejection Filter 7:4 Reserved Always write to 0. 152 Rev. 1.2 AN332 AM Channel Filter. Selects the bandwidth of the AM channel filter. The following choices are available: 0 = 6 kHz Bandwidth 1 = 4 kHz Bandwidth 3:0 AMCHFILT 2 = 3 kHz Bandwidth 3 = 2 kHz Bandwidth 4 = 1 kHz Bandwidth 5 = 1.8 kHz Bandwidth 6 = 2.5 kHz Bandwidth, gradual roll off 715 = Reserved (Do not use) Rev. 1.2 153 AN332 Property 0x3103. AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN Sets the maximum gain for automatic volume control. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 16 dB. The maximum AVC gain affects audio output level, especially under weak signal conditions. It amplifies the signal as well as noise. When a signal is very weak (needs a lot of gain) then the maximum gain will be applied, and may make the noise too harsh for the listener, even the soft mute functions. The user can reduce the noise further by adjusting the maximum AVC gain. The property allows the user to optimize the trade-off between maintaining output level and suppressing noise. Note: The maximum AVC gain is not configurable in Si473x-B20 devices (FMRX component 2.1 and earlier), and is 90.3 dB. This would be equivalent to AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN property value 0x7800, which is the maximum value. Available in: Si473x-C40 and later, Si4732, Si474x Default: 0x1543 (Si473x-C40 and later, Si4732) 0x7800 (Si474x) Step: 1 Range: 0X1000 ~ 0x7800 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 AVC_MAXGAIN [14:0] Bit Name Function 15 Reserved Always write to 0. Automatic Volume Control Max Gain. Maximum gain for automatic volume control. 14:0 AVC_MAXGAIN The max gain value is given by AVC_MAXGAIN = g * 340.2 where g is the desired maximum AVC gain in dB. Minimum of 12 dB is recommend when SOFTMUTE is enabled. Property 0x3104. AM_MODE_AFC_SW_PULL_IN_RANGE Sets the SW AFC pull-in or tracking range. The value PULL_IN_RANGE is relative to the tuned frequency and is specified as 1/(PPM×106). For example to program a pull-in range of 115 ppm, PULL_IN_RANGE = 1/(115×106) = 8695. The command is complete when the CTS bit (and optional interrupt) is set. Available in: Si4734/35-C40 and later, Si4732, Si4742/43/44/45 Default: 0x21F7 (115 ppm) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SWPIR[15:0] 154 Rev. 1.2 AN332 Bit Name Function 15:0 SWPIR[15:0] SW Pull-In Range The SW pull-in range expressed relative to the tuned frequency. Property 0x3105. AM_MODE_AFC_SW_LOCK_IN_RANGE Sets the SW AFC lock-in or capture range. The value LOCK_IN_RANGE is relative to the tuned frequency and is specified as 1/( PPM×106). For example to program a lock-in range of 85 ppm, LOCK_IN_RANGE = 1/(85×106) = 11765. The command is complete when the CTS bit (and optional interrupt) is set. Available in: Si4734/35-C40 and later, Si4732, Si4742/43/44/45 Default: 0x2DF5 (85 ppm) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SWPIR[15:0] Bit Name Function 15:0 SWPIR[15:0] SW Pull-In Range The SW lock-in range expressed relative to the tuned frequency. Property 0x3200. AM_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 SNRHIEN SNRLIEN RSSIHIEN RSSILIEN Bit Name Function 15:4 Reserved Always write 0. Interrupt Source Enable: SNR High. 3 SNRHIEN Enable SNR high as the source of interrupt which the threshold is set by AM_RSQ_SN- R_HI_THRESHOLD. Interrupt Source Enable: SNR Low. 2 SNRLIEN Enable SNR low as the as the source of interrupt which the threshold is set by AM_R- SQ_SNR_LO_THRESHOLD. Rev. 1.2 155 AN332 1 RSSIHIEN 0 RSSILIEN Interrupt Source Enable: RSSI High. Enable RSSI low as the source of interrupt which the threshold is set by AM_RSQ_RSSI_HI_THRESHOLD. Interrupt Source Enable: RSSI Low. Enable RSSI low as the source of interrupt which the threshold is set by AM_RSQ_RSSI_LO_THRESHOLD. 156 Rev. 1.2 AN332 Property 0x3201. AM_RSQ_SNR_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the SNR is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dB. Available in: All Default: 0x007F Units: dB Step: 1 Range: 0127 Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 00 SNRH[6:0] Bit Name Function 15:7 Reserved Always write to 0. AM RSQ SNR High Threshold. 6:0 SNRH Threshold which triggers the RSQ interrupt if the SNR goes above this threshold. Specified in units of dB in 1 dB steps (0127). Default is 0 dB. Property 0x3202. AM_RSQ_SNR_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the SNR is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dB Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 SNRL[6:0] Bit Name Function 15:7 Reserved Always write to 0. AM RSQ SNR Low Threshold. 6:0 SNRL Threshold which triggers the RSQ interrupt if the SNR goes below this threshold. Specified in units of dB in 1 dB steps (0127). Default is 0 dB. Rev. 1.2 157 AN332 Property 0x3203. AM_RSQ_RSSI_HI_THRESHOLD Sets high threshold which triggers the RSQ interrupt if the RSSI is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127 dB. Available in: All Default: 0x007F Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 RSSIH[6:0] Bit Name Function 15:7 Reserved Always write to 0. AM RSQ RSSI High Threshold. 6:0 RSSIH Threshold which triggers the RSQ interrupt if the RSSI goes above this threshold. Specified in units of dBµV in 1 dB steps (0127). Default is 0 dBµV. Property 0x3204. AM_RSQ_RSSI_LO_THRESHOLD Sets low threshold which triggers the RSQ interrupt if the RSSI is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0 dB. Available in: All Default: 0x0000 Units: dBµV Step: 1 Range: 0127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 00 RSSIL[6:0] Bit Name Function 15:7 Reserved Always write to 0. AM RSQ RSSI Low Threshold. 6:0 RSSIL Threshold which triggers the RSQ interrupt if the RSSI goes below this threshold. Specified in units of dBµV in 1 dB steps (0127). Default is 0 dBµV. 158 Rev. 1.2 AN332 Property 0x3300. AM_SOFT_MUTE_RATE Sets the attack and decay rates when entering or leaving soft mute. The value specified is multiplied by 4.35 dB/s to come up with the actual attack rate. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default rate is 278 dB/s. Available in: All Default: 0x0040 Actual Rate: SMRATE x 4.35 Units: dB/s Step: 1 Range: 1255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SMRATE[15:0] Bit Name Function AM Soft Mute Rate. 15:0 SMRATE Determines how quickly the AM goes into soft mute when soft mute is enabled. The actual rate is calculated by taking the value written to the field and multiplying it with 4.35 dB/s. The default rate is 278 dB/s (SMRATE[15:0] = 0x0040). Property 0x3301. AM_SOFT_MUTE_SLOPE Configures attenuation slope during soft mute in dB attenuation per dB SNR below the soft mute SNR threshold. Soft mute attenuation is the minimum of SMSLOPE x (SMTHR SNR) and SMATTN. The recommended SMSLOPE value is CEILING(SMATTN/SMTHR). SMATTN and SMTHR are set via the AM_SOFT_MUTE_MAX_ATTENUATION and AM_SOFT_MUTE_SNR_THRESHOLD properties. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default slope is 1 dB/dB for AMRX component 5.0 or later and 2 dB/dB for AMRX component 3.0 or earlier. Available in: All Default: 0x0002 (Si4730/31/34/35/36/37-B20 and earlier, Si4740/41/42/43/44/45-C10 and earlier) 0x0001 (all others) Units: dB/dB Range: 15 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 00 0 0 0000000 SMSLOPE[3:0] Bit Name Function Rev. 1.2 159 AN332 15:4 Reserved Always write to 0. AM Slope Mute Attenuation Slope. 3:0 SMSLOPE[3:0] Set soft mute attenuation slope in dB attenuation per dB SNR below the soft mute SNR threshold. Property 0x3302. AM_SOFT_MUTE_MAX_ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default attenuation is 8 dB for AMRX component 5.0 or later and 16 dB for AMRX component 3.0 or earlier. Available in: All Default: 0x0010 (Si4730/31/34/35/36/37-B20 and earlier, Si4740/41/42/43/44/45-C10 and earlier) 0x0008 (all others) Units: dB Step: 1 Range: 063 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 00 0 0 00000 SMATTN[5:0] Bit Name Function 15:6 Reserved Always write to 0. AM Soft Mute Max Attenuation. 5:0 SMATTN Maximum attenuation to apply when in soft mute. Specified in units of dB. Default maximum attenuation is 8 dB. Property 0x3303. AM_SOFT_MUTE_SNR_THRESHOLD Sets the SNR threshold to engage soft mute. Whenever the SNR for a tuned frequency drops below this threshold the AM reception will go in soft mute, provided soft mute max attenuation property is non-zero. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default SNR threshold is 8 dB for AMRX component 5.0 or later and 10 dB for AMRX component 3.0 or earlier. Available in: All Default: 0x000A (Si4730/31/34/35/36/37-B20 and earlier, Si4740/41/42/43/44/45-C10 and earlier) 0x0008 (all others) Units: dB Step: 1 Range: 063 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 00000 SMTHR[5:0] 160 Rev. 1.2 AN332 Bit Name Function 15:6 Reserved Always write to 0. AM Soft Mute SNR Threshold. 5:0 SMTHR The SNR threshold for a tuned frequency below which soft mute is engaged provided the value written to the AM_SOFT_MUTE_MAX_ATTENUATION property is not zero. Default SNR threshold is 8 dB. Property 0x3304. AM_SOFT_MUTE_RELEASE_RATE Sets the soft mute release rate. Smaller values provide slower release and larger values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Release Rate (dB/s) = RELEASE[14:0]/1.024 Available in: Si4740/41/42/43/44/45 Default: 0x2000 Range: 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 RELEASE[14:0] Rev. 1.2 161 AN332 Property 0x3305. AM_SOFT_MUTE_ATTACK_RATE Sets the soft mute attack rate. Smaller values provide slower attack and larger values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 8192 (approximately 8000 dB/s). Attack Rate (dB/s) = ATTACK[14:0]/1.024 Available in: Si4740/41/42/43/44/45 Default: 0x2000 Range: 132767 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 ATTACK[14:0] Softmute Gain (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 x = 0x3301: AM_SOFT_MUTE_SLOPE (0-63 dB/dB) y = 0x3302: AM_SOFT_MUTE_MAX_ATTENUATION (0-63 dB) z = 0x3303: AM_SOFT_MUTE_SNR_THRESHOLD (0-255 dB) -18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SNR (dB) x=2, y=16, z=10 (Default) x=4, y=16, z=10 x=2, y=4, z=10 Figure 13. AM Softmute SNR x=2, y=16, z=13 162 Rev. 1.2 AN332 Property 0x3400. AM_SEEK_BAND_BOTTOM Sets the lower boundary for the AM band in kHz. This value is used to determine when the lower end of the AM band is reached when performing a seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 520 kHz (0x0208). Available in: All Default: 0x0208 Units: kHz Step: 1 kHz Valid Range: 14923000 kHz Recommended Range: AM in US: AM in Asia: SW: LW: 5201710 kHz 5221710 kHz 230023000 kHz 153279 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name AMSKFREQL[15:0] Bit Name Function AM Seek Band Bottom. Specify the lower boundary of the AM band when performing a seek. The seek either 15:0 AMSKFREQL stops at this limit or wraps based on the parameters of AM_SEEK_START command that was issued to initiate a seek. The default value for the lower boundary of the AM band is 520 kHz. Rev. 1.2 163 AN332 Property 0x3401. AM_SEEK_BAND_TOP Sets the upper boundary for the AM band in kHz. This value is used to determine when the higher end of the AM band is reached when performing a seek. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1710 kHz (0x06AE). Available in: All Default: 0x06AE Note: Firmware 1.0 incorrectly reports 0x06B9 (1721 kHz) as default for AM_SEEK_BAND_TOP. After POWER_UP command is complete, set AM_SEEK_BAND_TOP to 0x06AE (1710 kHz) using the SET_PROPERTY command. Units: kHz Step: 1 kHz Valid Range: 14923000 kHz Recommended Range: AM in US: AM in Asia: SW: LW: 5201710 kHz 5221710 kHz 230023000 kHz 153279 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name AMSKFREQH[15:0] Bit Name Function AM Seek Band Top. Specify the higher boundary of the AM band when performing a seek. The seek either 15:0 AMSKFREQH stops at this limit or wraps based on the parameters of AM_SEEK_START command that was issued to initiate a seek. The default value for the upper boundary of the AM band is 1710 kHz. 164 Rev. 1.2 AN332 Property 0x3402. AM_SEEK_FREQ_SPACING Sets the frequency spacing for the AM Band when performing a seek. The frequency spacing determines how far the next tune is going to be from the currently tuned frequency. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default frequency spacing is 10 kHz. Available in: All Default: 0x000A Units: kHz Valid Values: 1 (1 kHz), 5 (5 kHz), 9 (9 kHz), and 10 (10 kHz). Recommended Value: AM in US: AM in Asia: SW: LW: 10 (10 kHz) 9 (9 kHz) 5 (5 kHz) 9 (9 kHz) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 000 0 0 AMSKSPACE[3:0] Bit Name Function 15:4 Reserved Always write to 0. AM Seek Frequency Spacing. 3:0 AMSKSPACE Sets the frequency spacing when performing a seek in the AM band. The default fre- quency spacing is 10 kHz. Rev. 1.2 165 AN332 Property 0x3403. AM_SEEK_TUNE_SNR_THRESHOLD Sets the SNR threshold for a valid AM Seek/Tune. If the value is zero, then SNR is not used as a valid criteria when doing a seek for AM. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default threshold is 5 dB. Available in: All Default: 0x0005 Units: dB Step: 1 Range: 063 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 000 AMSKSNR[5:0] Bit Name Function 15:6 Reserved Always write to 0. AM Seek/Tune SNR Threshold. 5:0 AMSKSNR SNR Threshold which determines if a valid channel has been found during Seek/Tune. Specified in units of dB in 1 dB steps (063). Default threshold is 5 dB. Property 0x3404. AM_SEEK_TUNE_RSSI_THRESHOLD Sets the RSSI threshold for a valid AM Seek/Tune. If the value is zero then RSSI is not used as a valid criteria when doing a seek for AM. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 25 dBµV. Available in: All Default: 0x0019 Units: dBµV Step: 1 Range: 063 Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 000 AMSKRSSI[5:0] Bit Name Function 15:6 Reserved Always write to 0. AM Seek/Tune Received Signal Strength Threshold. 5:0 AMSKRSSI RSSI Threshold which determines if a valid channel has been found during Seek/Tune. Specified in units of dBµV in 1 dBµV steps (063). Default threshold is 25 dBµV. 166 Rev. 1.2 AN332 Property 0x3702. AM_AGC_ATTACK_RATE Sets the AGC attack rate. Large values provide slower attack, and smaller values provide faster attack. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 4 (approximately 1400 dB/s). AGC Attack Rate (dB/s) = A-----T----T----A5----6C---0--K-0------7---:--0---- Nominal "5600" is based on Silabs' AM antenna dummy and Si474xEVB reference design and may vary with source impedance and design changes. In most systems, an exact value is not important. However, to calculate for a different source impedance and/or design: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 19 to 20. Record last RF level with index equal 19. 3. Increase RF level until AGC index reaches 39. Record RF level with index equal 39. 4. Replace "5600" in rate equation with "(RF39 RF19)/0.00667". Available in: Si4740/41/42/43/44/45 Default: 0x0004 Step: 4 Range: 4248 Notes: 1. Was property 0x4102 in FW2.C. 2. For FW2.E, attack rate may be faster than programmed depending on initial and final RF levels. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 ATTACK [7:0] Rev. 1.2 167 AN332 Property 0x3703. AM_AGC_RELEASE_RATE Sets the AGC release rate. Larger values provide slower release, and smaller values provide faster release. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 140 (approximately 40 dB/s). AGC Release Rate (dB/s) = R-----E-----L---E--5---A6---0-S---0-E-----[-7----:-0----] Nominal "5600" is based on Silabs' AM antenna dummy and Si474xEVB reference design and may vary with source impedance and design changes. In most systems, an exact value is not important. However, to calculate for a different source impedance and/or design: 1. Drive antenna input with desired source impedance (via antenna or antenna dummy). 2. Increase RF level until AGC index changes from 19 to 20. Record last RF level with index equal 19. 3. Increase RF level until AGC index reaches 39. Record RF level with index equal 39. 4. Replace "5600" in rate equation with "(RF39 RF19)/0.00667". Available in: Si4740/41/42/43/44/45 Default: 0x008C Step: 4 Range:4248 Note: Was property 0x4103 in FW2.C. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 00 0 RELEASE [7:0] Property 0x3705. AM_FRONTEND_AGC_CONTROL Adjusts the AM AGC for external front-end attenuator and external front-end cascode LNA. This property contains two fields: MIN_GAIN_INDEX and ATTN_BACKUP. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0x130C (MIN_AGC_INDEX=19 and ATTN_BACKUP=12). Available in: Si4740/41/42/43/44/45 Default: 0x130C Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name MIN_GAIN_INDEX[7:0] ATTN_BACKUP[7:0] MIN_GAIN_INDEX impacts sensitivity and U/D performance. Lower values improve sensitivity, but degrade far away blocker U/D performance. [Note: Values below 19 have minimal sensitivity improvement.] Higher values degrade sensitivity, but improve U/D. With MIN_GAIN_INDEX=19 and Si4743 EVB reference design, the Si474x provides sensitivity of 28dBuV typical and U/D exceeding 55dB on far away blockers. With MIN_GAIN_INDEX=24, the Si474x provides sensitivity of 34dBuV typical and U/D approaching 70dB on far away blockers. The recommended MIN_GAIN_INDEX optimization procedure is: 1. Determine source impedance and AM antenna dummy. 168 Rev. 1.2 AN332 2. Determine sensitivity RF input and SINAD requirements. 3. Set frequency to 1000kHz. 4. With source impedance in #1 and RF input in #2, adjust MIN_GAIN_INDEX until SINAD requirements are achieved with minimum necessary margin. 5. Program this value into Si474x MIN_GAIN_INDEX as part of initialization after POWERUP command. ATTN_BACKUP insures the AGC gain indexes are monotonic and is used when the external attenuator is engaged via GPO1/AGC2. The actual attenuation achieved depends on the source impedance or AM antenna dummy. Since AGC gain implementation is subject to change, the optimum value is best determined with specific antenna and board design. The recommend ATTN_BACKUP optimization procedure is: 1. Determine source impedance and AM antenna dummy. 2. Determine maximum RF input and associated SINAD requirements. 3. Set frequency to 1710kHz. 4. With ATTN_BACKUP set to 12 (default), disable the AGC at AMAGCNDX=47 using AM_AGC_OVERRIDE command. 5. With source impedance in #1 and RF input in #2, adjust attenuator impedance until SINAD requirements are achieved with minimum necessary margin. For Si4743EVB Rev 1.3, C7 (1200pF) attenuates against passive antenna sources and R8 (1 ohm) attenuates against active (50 ohm) sources. 6. Enable the AGC using AM_AGC_OVERRIDE. 7. Sweep the RF input from 0 to 126 dBuV and then from 126 to 0 dBuV in 1 dB steps and observe the AMAGCNDX at each RF level using AM_AGC_STATUS command. 8. If AMAGCNDX is observed to oscillate at any RF level, increase ATTN_BACKUP by 1 and repeat from step 7. 9. If AMAGCNDX is observed not to oscillate at any RF level, decrease ATTN_BACKUP by one and repeat from step 7. 10. Add one to smallest ATTN_BACKUP for which no oscillations are observed and program this value into Si474x ATTN_BACKUP as part of initialization after POWERUP command. Table 16. Recommended Values for MIN_GAIN_INDEX and ATTN_BACKUP with FW2.E and later, Si4743EVB Rev 1.3 and Various AM Antenna Dummies AM Antenna Dummy 50 /15 pF/62 pF (Silabs) 50 /40 pF/40 pF 50MN Series Active (50 ) MIN_GAIN_INDEX 19 19 19 19 ATTN_BACKUP 12 12 12 20 Rev. 1.2 169 AN332 Property 0x3900. AM_NB_DETECT_THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 12 dB. Available in: Si4742/43/44/45 Default: 0x000C Range: 090 Note: Was property 0x4105 in FW2.C. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_DETECT_THRESHOLD [15:0] Property 0x3901. AM_NB_INTERVAL Interval in micro-seconds that original samples are replaced by sample-hold clean samples. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 55 µs. Available in: Si4742/43/44/45 Default: 0x0037 Range: 15110 Note: Was property 0x4106 in FW2.C. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_INTERVAL [15:0] Property 0x3902. AM_NB_RATE Noise blanking rate in 100 Hz units. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 64 (6400 Hz). Available in: Si4742/43/44/45 Default: 0x0040 Range: 164 Note: Was property 0x4107 in FW2.C. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_RATE [15:0] 170 Rev. 1.2 AN332 Property 0x3903. AM_NB_IIR_FILTER Sets the bandwidth of the noise floor estimator. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 300 (465 Hz). Bandwidth (Hz) = NB_IIR_FILTER[15:0] x 1.55 Available in: Si4742/43/44/45 Default: 0x012C Range: 3001600 Note: Was property 0x4108 in FW2.C. Bit D15 D14 D13 D12 D11 Name D10 D9 D8 D7 D6 NB_IIR_FILTER [15:0] D5 D4 D3 D2 D1 D0 Property 0x3904. AM_NB_DELAY Delay in micro-seconds before applying impulse blanking to the original samples. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read in POWERUP mode. The default is 172 µs. Available in: Si4742/43/44/45 Default: 0x00AC Range: 125219 Note: Was property 0x4109 in FW2.C. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name NB_DELAY [15:0] Rev. 1.2 171 AN332 Blanker Input time LPF IIR Output AM_NB_IIR_FILTER: adjusts LPF AM_NB_DELAY AM_NB_DETECT_THRESHOLD time AM_NB_INTERVAL Blanker Output AM_NB_RATE: sets maximum repeat rate NB is allowed to fire. Figure 14. AM Noise Blanker time Property 0x4000. RX_VOLUME Sets the audio output volume. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 63. Available in: All Default: 0x003F Step: 1 Range: 063 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 VOL[5:0] Bit Name Function 15:6 Reserved Always write to 0. 5:0 VOL Output Volume. Sets the output volume level, 63 max, 0 min. Default is 63. 172 Rev. 1.2 AN332 Property 0x4001. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may not be muted independently. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is unmute (0x0000). Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name Function 15:2 Reserved Always write to 0. 1 LMUTE Mutes both L and R Audio Outputs. 0 RMUTE Mutes both L and R Audio Outputs. Rev. 1.2 173 AN332 5.4. Commands and Properties for the WB Receiver (Si4707/36/37/38/39/42/43) The following two tables are the summary of the commands and properties for the Weather Band Receiver component applicable to Si4707/36/37/38/39/42/43. Table 17. WB Receiver Command Summary Cmd Name Description Available In 0x01 POWER_UP Power up device and mode selection. All 0x10 GET_REV Returns revision information on the device. All 0x11 POWER_DOWN Power down device. All 0x12 SET_PROPERTY Sets the value of a property. All 0x13 GET_PROPERTY Retrieves a property's value. All 0x14 GET_INT_STATUS Reads interrupt status bits. All 0x15 PATCH_ARGS* Reserved command used for patch file downloads. All 0x16 PATCH_DATA* Reserved command used for patch file downloads. All 0x50 WB_TUNE_FREQ Selects the WB tuning frequency. All 0x52 WB_TUNE_STATUS Queries the status of previous WB_TUNE_FREQ or WB_SEEK_START command. All 0x53 WB_RSQ_STATUS Queries the status of the Received Signal Quality (RSQ) of the current channel All 0x54 WB_SAME_STATUS Retrieves Specific Area Message Encoding (SAME) information and acknowledges SAMEINT interrupts. Si4707 0x55 WB_ASQ_STATUS Queries the status of the 1050 kHz alert tone in Weather Band. All 0x57 WB_AGC_STATUS Queries the current AGC settings All 0x58 WB_AGC_OVERRIDE Override AGC setting by disabling and forcing it to a fixed value All 0x80 GPIO_CTL Configures GPO1, 2, and 3 as output or Hi-Z All 0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high) All *Note: Commands PATCH_ARGS and PATCH_DATA are only used to patch firmware. For information on applying a patch file, see "7.2. Powerup from a Component Patch" on page 236. 174 Rev. 1.2 AN332 Table 18. WB Receive Property Summary Prop 0x0001 0x0102 0x0104 0x0201 0x0202 0x5108 0x5200 0x5201 0x5202 0x5203 0x5204 0x5403 0x5404 0x5500 0x5600 0x4000 0x4001 Name Description GPO_IEN Enables interrupt sources. DIGITAL_OUTPUT_ FORMAT Configure digital audio outputs. DIGITAL_OUTPUT_ SAMPLE_RATE Configure digital audio output sample rate. REFCLK_FREQ Sets frequency of reference clock in Hz. The range is 31130 to 34406 Hz, or 0 to disable the AFC. Default is 32768 Hz. REFCLK_PRESCALE Sets the prescaler value for RCLK input. WB_MAX_TUNE_ERROR Sets the maximum freq error allowed before setting the AFC_RAIL indicator. Default value is 10 kHz. WB_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. WB_RSQ_SNR_HI_THRESHOLD Sets high threshold for SNR interrupt. WB_RSQ_SNR_LO_THRESHOLD Sets low threshold for SNR interrupt. WB_RSQ_RSSI_HI_THRESHOLD Sets high threshold for RSSI interrupt. WB_RSQ_RSSI_LO_THRESHOLD Sets low threshold for RSSI interrupt. WB_VALID_SNR_THRESHOLD Sets SNR threshold to indicate a valid channel WB_VALID_RSSI_THRESHOLD Sets RSSI threshold to indicate a valid channel WB_SAME_INTERRUPT_SOURCE Configures SAME interrupt sources. WB_ASQ_INT_SOURCE Configures interrupt related to the 1050 kHz alert tone RX_VOLUME Sets the output volume. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may not be muted independently. Default Available In 0x0000 All 0x0000 Si4737/39/43 0x0000 Si4737/39/43 0x8000 All 0x0001 All 0x000A All 0x0000 0x007F 0x0000 0x007F 0x0000 0x0003 0x0014 0x0000 0x0000 0x003F 0x0000 All All All All All All All Si4707 All All All Rev. 1.2 175 AN332 Bit STATUS Table 19. Status Response for the WB Receiver D7 D6 D5 CTS ERR X D4 D3 D2 X RSQINT SAMEINT D1 ASQINT D0 STCINT Bit Name Function Clear to Send. 7 CTS 0 = Wait before sending next command. 1 = Clear to send next command. Error. 6 ERR 0 = No error 1 = Error 5:4 Reserved Values may vary. Received Signal Quality Interrupt. 3 RSQINT 0 = Received Signal Quality measurement has not been triggered. 1 = Received Signal Quality measurement has been triggered. SAME Interrupt (Si4707 Only). 2 SAMEINT 0 = SAME interrupt has not been triggered. 1 = SAME interrupt has been triggered. Audio Signal Quality Interrupt. 1 ASQINT 0 = Audio Signal Quality measurement has not been triggered. 1 = Audio Signal Quality measurement has been triggered. Seek/Tune Complete Interrupt. 0 STCINT 0 = Tune complete has not been triggered. 1 = Tune complete interrupt has been triggered. 176 Rev. 1.2 AN332 5.4.1. WB Receiver Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the response, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 3 (WB Receive) and the patch may be applied. The POWER_UP command configures the state of ROUT (pin 13), LOUT (pin 14) for analog audio mode. For Si4743 component 2A or higher, the POWER_UP command also configures the state of GPO3/DCLK (pin 19), DFS (pin 18), and DOUT (pin 17) for digital audio mode. The command configures GPO2/INT~ interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/IRQ is driven high during normal operation and low for a minimum of 1 s during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. To change function (e.g., WB RX to FM RX), issue POWER_DOWN command to stop current function; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tune command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC=3), Seven (FUNC=15) Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] Rev. 1.2 177 AN332 Arg Bit Name Function 1 7 CTSIEN CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. 1 6 GPO2OEN GPO2 Output Enable. 0 = GPO2 output disabled. 1 = GPO2 output enabled. 1 5 PATCH Patch Enable. 0 = Boot normally 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched 1 4 XOSCEN Crystal Oscillator Enable. 0 = Use external RCLK (crystal oscillator disabled) 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768kHz crystal and OPMODE = 00000101) 1 3:0 FUNC[3:0] See Si47xx Data Sheet Application Schematic for external BOM details. Function. 3 = WB Receive. 02, 414 = Reserved 15 = Query Library ID. 2 7:0 OPMODE[7:0] Application Setting 00000101 = Analog audio outputs (LOUT/ROUT) 00001011 = Digital audio output (DCLK, LOUT/DFS, ROUT/DIO) 10110000 = Digital audio outputs (DCLK, DFS, DIO) (Si4743 component 2.A or higher with XOSCEN = 0) 10110101 = Analog and digital outputs (LOUT/ROUT and DCLK, DFS, DIO) (Si4743 component 2.A or higher with XOSCEN = 0) 178 Rev. 1.2 Response (FUNC = 3, WB Receive) Bit STATUS D7 D6 D5 CTS ERR X Response (FUNC = 15, Query Library ID) Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 D6 D5 CTS ERR X AN332 D4 D3 D2 D1 D0 X RSQINT SAMEINT ASQINT STCINT D4 D3 D2 X RSQINT SAMEINT PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] D1 ASQINT D0 STCINT RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] Function Final 2 digits of part number (HEX). Firmware Major Revision (ASCII). Firmware Minor Revision (ASCII). Reserved, various values. Reserved, various values. Chip Revision (ASCII). Library Revision (HEX). Rev. 1.2 179 AN332 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Eight Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 PN[7:0] RESP2 FWMAJOR[7:0] RESP3 FWMINOR[7:0] RESP4 RESP5 RESP6 PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] RESP7 CMPMINOR[7:0] RESP8 CHIPREV[7:0] RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 8 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] Function Final 2 digits of Part Number Firmware Major Revision Firmware Minor Revision Patch ID High Byte Patch ID Low Byte Component Major Revision Component Minor Revision Chip Revision 180 Rev. 1.2 AN332 Command 0x11. POWER_DOWN Moves the device form powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 ROUT, LOUT, DOUT, DFS = Hiz. Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 0 0 0 1 0 D2 D1 D0 0 0 1 Response Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 D1 D0 X RSQINT SAMEINT ASQINT STCINT Command 0x12. SET_PROPERTY Sets a property shown in Table 18, "WB Receive Property Summary," on page 175. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command Arguments: Five Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] PROPVH[7:0] PROPVL[7:0] Rev. 1.2 181 AN332 Arg Bit Name Function 1 7:0 Reserved Always write to 0. 2 7:0 PROPH[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to modify. 3 7:0 PROPL[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to modify. 4 7:0 PROPVH[7:0] Property Value High Byte. This byte in combination with PROPVL is used to set the property value. 5 7:0 PROPVL[7:0] Property Value Low Byte. This byte in combination with PROPVH is used to set the property value. Command 0x13. GET_PROPERTY Gets a property as shown in Table 18, "WB Receive Property Summary," on page 175. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 PROPGH[7:0] PROPGL[7:0] Arg Bit 1 7:0 2 7:0 3 7:0 Name Reserved PROPGH[7:0] PROPGL[7:0] Function Always write to 0. Property High Byte. This byte in combination with PROPL is used to specify the property to get. Property Low Byte. This byte in combination with PROPH is used to specify the property to get. 182 Rev. 1.2 Response Bit D7 D6 D5 STATUS CTS ERR X RESP1 0 0 0 RESP2 RESP3 AN332 D4 D3 X RSQINT 0 0 PROPVH[7:0] PROPVL[7:0] D2 SAMEINT 0 D1 ASQINT 0 D0 STCINT 0 RESP Bit 1 7:0 2 7:0 3 7:0 Name Reserved PROPVH[7:0] PROPVL[7:0] Function Always returns 0. Property Value High Byte. This byte in combination with PROPVL will represent the requested property value. Property Value High Byte. This byte in combination with PROPVH will represent the requested property value. Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command should be called after any command that sets the STCINT, RSQINT, SAMEINT (Si4707 only), or ASQINT bits. When polling this command should be periodically called to monitor the status byte, and when using interrupts, this command should be called after the interrupt is set to updated the status byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: One Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 0 Response Bit D7 D6 D5 STATUS CTS ERR X D4 D3 D2 D1 D0 X RSQINT SAMEINT ASQINT STCINT Rev. 1.2 183 AN332 Command 0x50. WB_TUNE_FREQ Sets the WB Receive to tune the frequency between 162.4 MHz and 162.55 MHz in 2.5 kHz units. For example 162.4 MHz = 64960 and 162.55 MHz = 65020. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. The optional STC interrupt is set when the command completes. The STCINT bit is set only after the GET_INT_STATUS command is called. This command may only be sent when in powerup mode. The command clears the STC bit if it is already set. Available in: All Command arguments: Three Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 FREQH[7:0] FREQL[7:0] Arg Bit 1 7:0 2 7:0 3 7:0 Name Reserved FREQH[7:0] FREQL[7:0] Function Always write to 0. Tune Frequency High Byte. This byte in combination with FREQL selects the tune frequency in kHz. In WB mode the valid range is from 64960 to 65020 (162.4162.55 MHz). Tune Frequency Low Byte. This byte in combination with FREQH selects the tune frequency in kHz. In WB mode the valid range is from 64960 to 65020 (162.4162.55 MHz). 184 Rev. 1.2 AN332 Command 0x52. WB_TUNE_STATUS Returns the status of WB_TUNE_FREQ. The commands returns the current frequency, and RSSI/SNR at the moment of tune. The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Five Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 INTACK Arg Bit 1 7:1 1 0 Response Name Reserved INTACK Function Always write to 0. Seek/Tune Interrupt Clear. If set this bit clears the seek/tune complete interrupt status indicator. Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 D7 CTS X D6 ERR X D5 D4 D3 D2 D1 D0 X X RSQINT SAMEINT ASQINT STCINT X X X X AFCRL VALID READFREQH[7:0] READFREQL[7:0] RSSI[7:0] SNR[7:0] Rev. 1.2 185 AN332 Data Bit Name Function 1 7:2 Reserved Always returns 0. 1 1 AFCRL AFC Rail Indicator. This bit will be set if the AFC rails. 1 0 VALID Valid Channel. Confirms if the tuned channel is currently valid. 2 7:0 READFREQH[7:0] Read Frequency High Byte. This byte in combination with READFREQL returns frequency being tuned. 3 7:0 READFREQL[7:0] Read Frequency Low Byte. This byte in combination with READFREQH returns frequency being tuned. 4 7:0 RSSI[7:0] Received Signal Strength Indicator. This byte will contain the receive signal strength at the tuned frequency. 5 7:0 SNR[7:0] SNR. This byte will contain the SNR metric at the tuned frequency. Command 0x53. WB_RSQ_STATUS Returns status information about the received signal quality. The commands returns the RSSI, SNR, and frequency offset. It also indicates whether the frequency is a currently valid frequency as indicated by VALID, and whether the AFC is railed or not as indicated by AFCRL. This command can be used to check if the received signal is above the RSSI high threshold as reported by RSSIHINT, or below the RSSI low threshold as reported by RSSILINT. It can also be used to check if the received signal is above the SNR high threshold as reported by SNRHINT, or below the SNR low threshold as reported by SNRLINT. The command clears the STCINT interrupt bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Seven Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 INTACK Arg Bit 1 0 Name INTACK Function Interrupt Acknowledge 0 = Interrupt status preserved. 1 = Clears RSQINT, SNRHINT, SNRLINT, RSSIHINT, RSSILINT 186 Rev. 1.2 Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 CTS X X X X AN332 D6 D5 ERR X X X X X X X X X D4 D3 X RSQINT X SNRHI NT X X X X RSSI[7:0] ASNR[7:0] X X FREQOFF[7:0] D2 SAMEINT SNRLINT X X X D1 ASQINT RSSIHI NT AFCRL X X D0 STCINT RSSIILINT VALID X X Data Bit 1 3 1 2 1 1 1 0 2 1 2 0 4 7:0 5 7:0 7 7:0 Name SNRHINT SNRLINT RSSIHINT RSSILINT AFCRL VALID RSSI[7:0] SNR[7:0] FREQOFF[7:0] Function SNR Detect High. 0 = Received SNR has not exceeded above SNR high threshold. 1 = Received SNR has exceeded above SNR high threshold. SNR Detect Low. 0 = Received SNR has not exceeded below SNR low threshold. 1 = Received SNR has exceeded below SNR low threshold. RSSI Detect High. 0 = RSSI has not exceeded above RSSI high threshold. 1 = RSSI has exceeded above RSSI high threshold. RSSI Detect Low. 0 = RSSI has not exceeded below RSSI low threshold. 1 = RSSI has exceeded below RSSI low threshold. AFC Rail Indicator. This bit will be set if the AFC rails. Valid Channel. Confirms if the channel is currently valid. Received Signal Strength Indicator. This byte will contain the receive signal strength at the tuned frequency. SNR. This byte will contain the SNR metric at the tuned frequency. Frequency Offset. Signed frequency offset in kHz. Rev. 1.2 187 AN332 Command 0x54. WB_SAME_STATUS Retrieves SAME information, acknowledges SAMEINT interrupts and clears the message buffer. The command indicates whether the start of message, end of message or preamble is detected and if the header buffer is ready. The state of the decoder, message length, and 8 bytes of the message buffer with corresponding confidence level is returned. The byte at address 0 will be the first byte following the header block identifier "ZCZC", typically "-" (Dash). Each byte has an associated confidence metric ranging from 0 (low confidence) to 3 (high confidence). Available in: Si4707 Command Arguments: Two Response Bytes: Thirteen Command Bit CMD ARG1 ARG2 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 CLRBUF INTACK READADDR[7:0] Arg Bit Name Function 1 7:2 Reserved Always write to 0. Clear Buffer 1 1 CLRBUF 0 = Message Buffer preserved. 1 = Clears the contents of the SAME Message Buffer. Clears the contents of the SAME Message Buffer if set. The buffer will always be cleared during WB_TUNE_FREQ. If the buffer is not cleared then each message received will be combined with the previously received message to increase the certainty of the message content. After receipt of an End-of-Message, this buffer must be cleared by the user. To prevent different headers from being combined into an incorrect message, the user must clear the buffer before a new header is transmitted. As there is no indication that a new header is about to be transmitted, the user must rely on other events to indicate when to clear the buffer. The buffer should be cleared after receipt of three headers, after the end-of-message marker, when the 1050 Hz alert tone has been detected or 6 seconds after the reception of the last header was completed and no new preamble has been detected. Once the buffer has been cleared, it will remain empty until the next start-of-message is received. Alternatively, the user may clear the buffer after each header is received and rely on a traditional best 2-of-3 voting method. In this case, no message combining is performed. 1 0 INTACK Interrupt Acknowledge 0 = Interrupt status preserved. 1 = Clears SAMEINT. Byte in the message buffer to start reading from. Note that 8 bytes will always 2 [7:0] READADDR[7:0] be returned, however the WB_SAME_STATUS:MSGLEN will report the total length of the message and the user must disregard bytes past this length. 188 Rev. 1.2 Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 RESP13 D7 CTS X D6 ERR X CONF7[1:0] CONF3[1:0] AN332 D5 D4 X X X X CONF6[1:0] CONF2[1:0] D3 D2 RSQINT SAMEINT EOMDET SOMDET STATE[7:0] MSGLEN[7:0] CONF5[1:0] CONF1[1:0] DATA0[7:0] DATA1[7:0] DATA2[7:0] DATA3[7:0] DATA4[7:0] DATA5[7:0] DATA6[7:0] DATA7[7:0] D1 ASQINT PREDET D0 STCINT HDRRDY CONF4[1:0] CONF0[1:0] RESP Bit 1 3 1 2 1 1 1 0 2 [7:0] 3 [7:0] Name EOMDET SOMDET PREDET HDRRDY STATE[7:0] MSGLEN[7:0] Function End Of Message Detected 1 = End of message is detected. Start Of Message Detected 1 = start of message is detected. Preamble Detected 1 = Preamble is detected. Header Buffer Ready 1 = Header buffer is ready. State Machine Status 0 = End of message. 1 = Preamble detected. 2 = Receiving SAME header message. 3 = SAME header message complete. SAME Message Length SAME Message length in bytes. This length excludes the preamble and the header code block identifier "ZCZC". If message combining is used, the value reported is the length of the longest message received. Rev. 1.2 189 AN332 RESP Bit 4 [7:6] 4 [5:4] 4 [3:2] 4 [1:0] 5 [7:6] 5 [5:4] 5 [3:2] 5 [1:0] 6 [7:0] 7 [7:0] 8 [7:0] 9 [7:0] 10 [7:0] 11 [7:0] 12 [7:0] 13 [7:0] Name CONF7[1:0] CONF6[1:0] CONF5[1:0] CONF4[1:0] CONF3[1:0] CONF2[1:0] CONF1[1:0] CONF0[1:0] DATA0[7:0] DATA1[7:0] DATA2[7:0] DATA3[7:0] DATA4[7:0] DATA5[7:0] DATA6[7:0] DATA7[7:0] Function Confidence Metric for DATA7 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA6 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA5 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA4 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA3 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA2 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA1 represented as a number between 0 (low) and 3 (high). Confidence Metric for DATA0 represented as a number between 0 (low) and 3 (high). Byte of message read at address, READADDR + 0 Byte of message read at address, READADDR + 1 Byte of message read at address, READADDR + 2 Byte of message read at address, READADDR + 3 Byte of message read at address, READADDR + 4 Byte of message read at address, READADDR + 5 Byte of message read at address, READADDR + 6 Byte of message read at address, READADDR + 7 190 Rev. 1.2 AN332 Command 0x55. WB_ASQ_STATUS Returns status information about the 1050kHz alert tone in Weather Band. The commands returns the alert on/off Interrupt and the present state of the alert tone. The command clears the ASQINT bit when INTACK bit of ARG1 is set. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Two Command Bit CMD ARG1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 INTACK Arg Bit 1 7:1 Name Reserved Always write to 0. Function 1 0 Response Bit STATUS RESP1 RESP2 INTACK D7 CTS X X D6 ERR X X Interrupt Acknowledge 0 = Interrupt status preserved. 1 = Clears ASQINT, ALERTOFF_INT, ALERTON_INT D5 D4 D3 D2 D1 D0 X X RSQINT SAMEINT ASQINT STCINT X X X X ALERTOFF_INT ALERTON_INT X X X X X ALERT Rev. 1.2 191 AN332 Data Bit 1 1 1 0 2 0 Name ALERTOFF_INT ALERTON_INT ALERT Function ALERTOFF_INT. 0 = 1050 Hz alert tone has not been detected to be absent since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. 1 = 1050 Hz alert tone has been detected to be absent since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. ALERTON_INT. 0 = 1050 Hz alert tone has not been detected to be present since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. 1 = 1050 Hz alert tone has been detected to be present since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK = 1. ALERT. 0 = 1050 Hz alert tone is currently not present. 1 = 1050 Hz alert tone is currently present. Command 0x57. WB_AGC_STATUS Returns the AGC setting of the device. The command returns whether the AGC is enabled or disabled. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: One Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 1 1 1 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 X X X X X X X READ_RFAGCDIS RESP Bit 1 0 Name READ_RFAGCDIS Function This bit indicates whether the RF AGC is disabled or not 0 = RF AGC is enabled. 1 = RF AGC is disabled. 192 Rev. 1.2 AN332 Command 0x58. WB_AGC_OVERRIDE Overrides AGC setting by disabling the AGC and forcing the LNA to have a certain gain that ranges between 0 (minimum attenuation) and 26 (maximum attenuation). This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 1 0 0 0 ARG1 X X X X X X X RFAGCDIS ARG 1 1 Bit Name 7:1 Reserved 0 RFAGCDIS Response Bit STATUS D7 CTS D6 ERR Function Always write to 0. This bit selects whether the RF AGC is disabled or not 0 = RF AGC is enabled. 1 = RF AGC is disabled. D5 D4 D3 D2 D1 X X RSQINT SAMEINT ASQINT D0 STCINT Rev. 1.2 193 AN332 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (high or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Notes: 1. The use of GPO2 as an interrupt pin will override this GPIO_CTL function for GPO2. 2. GPO1 is not configurable as an output for Si4740/41/42/43/44/45. Available in: All Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Bit STATUS Name Reserved GPO3OEN GPO2OEN GPO1OEN Reserved D7 CTS D6 ERR Function Always write 0. GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. Always write 0. D5 D4 D3 D2 X X RSQINT SAMEINT D1 ASQINT D0 STCINT 194 Rev. 1.2 AN332 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Available in: All Command arguments: One Response bytes: None Command Bit D7 CMD 1 ARG1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Bit STATUS Name Reserved GPO3LEVEL GPO2LEVEL GPO1LEVEL Reserved Always write 0. GPO3 Output Level. 0 = Output low (default). 1 = Output high. GPO2 Output Level. 0 = Output low (default). 1 = Output high. GPO1 Output Level. 0 = Output low (default). 1 = Output high. Always write 0. Function D7 D6 D5 CTS ERR X D4 D3 D2 X RSQINT SAMEINT D1 ASQINT D0 STCINT Rev. 1.2 195 AN332 5.4.2. WB Receiver Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/IRQ interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, RSQINT, SAMEINT (Si4707 only), ASQINT, and STCINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading the this property and modified by writing this property. This command may only be sent when in powerup mode. Errata:RSQIEN is non-functional on WB component 2.0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 00 RSQREP SAMEREP ASQREP STCREP CTSIEN ERRIEN RSQIEN SAMEIEN ASQIEN STCIEN Bit 15:12 Name Reserved 11 RSQREP 10 SAMEREP 9 ASQREP 8 STCREP 7 CTSIEN 6 ERRIEN 5:4 Reserved Function Always write to 0. RSQ Interrupt Repeat. 0 = No interrupt generated when RSQINT is already set (default). 1 = Interrupt generated even if RSQINT is already set. SAME Interrupt Repeat (Si4707 Only). 0 = No interrupt generated when SAMEINT is already set (default). 1 = Interrupt generated even if SAMEINT is already set. ASQ Interrupt Repeat. 0 = No interrupt generated when ASQINT is already set (default). 1 = Interrupt generated even if ASQINT is already set. STC Interrupt Repeat. 0 = No interrupt generated when STCINT is already set (default). 1 = Interrupt generated even if STCINT is already set. CTS Interrupt Enable. After PowerUp, this bit will reflect the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set. 1 = Interrupt generated when CTS is set. ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. Always write to 0. 196 Rev. 1.2 Bit Name Function RSQ Interrupt Enable 3 RSQIEN 0 = No interrupt generated when RSQINT is set (default). 1 = Interrupt generated when RSQINT is set. SAME Interrupt Enable (Si4707 Only). 2 SAMEIEN 0 = No interrupt generated when SAMEINT is set (default). 1 = Interrupt generated when SAMEINT is set. ASQ Interrupt Enable 1 ASQIEN 0 = No interrupt generated when ASQINT is set (default) 1 = Interrupt generated when ASQINT is set Seek/Tune Complete Interrupt Enable. 0 STCIEN 0 = No interrupt generated when TCINT is set (default) 1 = Interrupt generated when TCINT is set AN332 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Available in: Si4737/39/43 Default: 0x0000 Note: DIGITAL_OUTPUT_FORMAT is supported in WBRX component 3.0 or later. Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 7 OFALL 6543 OMODE[3:0] 2 OMONO 1 0 OSIZE[1:0] Bit Name Function 15:8 Reserved Always write to 0. Digital Output DCLK Edge. 7 OFALL 0 = use DCLK rising edge 1 = use DCLK falling edge Digital Output Mode. 0000 = I2S 6:3 OMODE[3:0] 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse Digital Output Mono Mode. 2 OMONO 0 = Use mono/stereo blend (per blend thresholds) 1 = Force mono Digital Output Audio Sample Precision. 0 = 16-bits 1:0 OSIZE[1:0] 1 = 20-bits 2 = 24-bits 3 = 8-bits Rev. 1.2 197 AN332 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. The over-sampling rate must be set in order to satisfy a minimum DCLK of 1 MHz. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before the DCLK/DFS is removed. WB_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property. Note: DIGITAL_OUPTUT_SAMPLE_RATE is supported in WBRX component 3.0 or later. Available in: Si4737/39/43 Default: 0x0000 (digital audio output disabled) Units: sps Range: 3248 ksps, 0 to disable digital audio output Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 3248 ksps. 0 to disable digital audio output. 198 Rev. 1.2 AN332 Property 0x0201. REFCLK_FREQ Sets the frequency of the REFCLK from the output of the prescaler. The REFCLK range is 31130 to 34406 Hz (32768 5% Hz) in 1 Hz steps, or 0 (to disable AFC). For example, an RCLK of 13MHz would require a prescaler value of 400 to divide it to 32500 Hz REFCLK. The reference clock frequency property would then need to be set to 32500 Hz. RCLK frequencies between 31130 Hz and 40 MHz are supported, however, there are gaps in frequency coverage for prescaler values ranging from 1 to 10, or frequencies up to 311300 Hz. The following table summarizes these RCLK gaps. PIN 9 RCLK 31.130 kHz 40 MHz Prescaler Divide by 1-4095 REFCLK 31.130 kHz 34.406 kHz Figure 15. REFCLK Prescaler Table 20. RCLK Gaps Prescaler 1 2 3 4 5 6 7 8 9 10 RCLK Low (Hz) 31130 62260 93390 124520 155650 186780 217910 249040 280170 311300 RCLK High (Hz) 34406 68812 103218 137624 172030 206436 240842 275248 309654 344060 The RCLK must be valid 10 ns before and 10 ns after completing the WB_TUNE_FREQ command. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AGC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is 32768 Hz. Available in: All Default: 0x8000 (32768) Units: 1 Hz Step: 1 Hz Range: 31130-34406 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF[15:0] Rev. 1.2 199 AN332 Bit Name Function 15:0 REFCLKF[15:0] Frequency of Reference Clock in Hz. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC). Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 1023 in 1 unit steps. For example, an RCLK of 13MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before and 10 ns after completing the WB_TUNE_FREQ command. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AFC operation. The RCLK may be removed or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 1-4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLK SEL REFCLKP[11:0] Bit 15:13 12 11:0 Name Reserved RCLKSEL REFCLKP[11:0] Function Always write to 0. RCLKSEL. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. Prescaler for Reference Clock. Integer number used to divide clock frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 +/5%), or 0 (to disable AFC). 200 Rev. 1.2 AN332 Property 0x5108. WB_MAX_TUNE_ERROR Sets the maximum freq error allowed before setting the AFC_RAIL indicator.The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 10 kHz. Available in: All Default: 0x000A Units: kHz Step: 1 Range: 015 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WBMAXTUNEERR[15:0] Bit Name Function 15:0 WBMAXTUNEERR WB Maximum Tuning Frequency Error. Maximum tuning error allowed before setting the AFC Rail Indicator ON. Specified in units of kHz. Default is 10 kHz. Property 0x5200. WB_RSQ_INT_SOURCE Configures interrupt related to Received Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name X X X X X X XX X XXX SNRHIEN SNRLIEN RSSIHIEN RSSILIEN Rev. 1.2 201 AN332 Bit Name Function 3 SNRHIEN Interrupt Source Enable: Audio SNR High. Enable SNR high as the source of interrupt which the threshold is set by WB_RSQ_SNR_HI_THRESHOLD. 2 SNRLIEN Interrupt Source Enable: Audio SNR Low. Enable SNR low as the as the source of interrupt which the threshold is set by WB_RSQ_SNR_LO_THRESHOLD. 1 RSSIHIEN Interrupt Source Enable: RSSI High. Enable RSSI high as the source of interrupt which the threshold is set by WB_RSQ_RSSI_HI_THRESHOLD. 0 RSSILIEN Interrupt Source Enable: RSSI Low. Enable RSSI low as the source of interrupt which the threshold is set by WB_RSQ_RSSI_LO_THRESHOLD. Property 0x5201. WB_RSQ_SNR_HI_THRESHOLD Sets high threshold which will trigger the RSQ interrupt if the Audio SNR is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127dB. Available in: All Default: 0x007F Units: dB Step: 1 Range: 0-127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SNRH[15:0] Bit Name Function 15:0 SNRH WB RSQ Audio SNR High Threshold. Threshold which will trigger the RSQ interrupt if the Audio SNR is above this threshold. Specified in units of dB in 1 dB steps (0...127). Default is 127dB. 202 Rev. 1.2 AN332 Property 0x5202. WB_RSQ_SNR_LO_THRESHOLD Sets low threshold which will trigger the RSQ interrupt if the Audio SNR is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0dB. Available in: All Default: 0x0000 Units: dB Step: 1 Range: 0-127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SNRL[15:0] Bit Name Function 15:0 SNRL WB RSQ Audio SNR Low Threshold. Threshold which will trigger the RSQ interrupt if the Audio SNR is below this threshold. Specified in units of dB in 1 dB steps (0...127). Default is 0dB. Property 0x5203. WB_RSQ_RSSI_HI_THRESHOLD Sets high threshold which will trigger the RSQ interrupt if the RSSI is above this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 127dB. Available in: All Default: 0x007F Units: dBµV Step: 1 Range: 0-127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSSIH[15:0] Bit Name Function 15:0 RSSIH WB RSQ RSSI High Threshold. Threshold which will trigger the RSQ interrupt if the RSSI is above this threshold. Specified in units of dB in 1 dB steps (0...127). Default is 127dB. Rev. 1.2 203 AN332 Property 0x5204. WB_RSQ_RSSI_LO_THRESHOLD Sets low threshold which will trigger the RSQ interrupt if the RSSI is below this threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0dB. Available in: All Default: 0x0000 Units: dBµV Step: 1 Range: 0-127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSSIL[15:0] Bit Name Function 15:0 RSSIL WB RSQ RSSI Low Threshold. Threshold which will trigger the RSQ interrupt if the RSSI is below this threshold. Specified in units of dB in 1 dB steps (0...127). Default is 0dB. Property 0x5403. WB_VALID_SNR_THRESHOLD Sets the SNR threshold which the WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel valid if the received SNR is at or above this value. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 3dB. Available in: All Default: 0x0003 Units: dBµV Step: 1 Range: 0-127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WB_VALID_SNR_THRESHOLD[15:0] Bit Name Function 15:0 WB_VALID_S WB Valid SNR Threshold. NR_THRESH SNR value at or above which WB_RSQ_STATUS and WB_TUNE_STATUS will OLD consider the channel VALID. Specified in units of dB in 1 dB steps (0...127). Default is 3 dB. 204 Rev. 1.2 AN332 Property 0x5404. WB_VALID_RSSI_THRESHOLD Sets the RSSI threshold which the WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel valid if the received RSSI is at or above this value. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 20dB. Available in: All Default: 0x0014 Units: dBµV Step: 1 Range: 0-127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WB_VALID_RSSI_THRESHOLD [15:0] Bit Name Function 15:0 WB_VALID_RSSI_ WB Valid RSSI Threshold. THRESHOLD RSSI value at or above which WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel VALID. Specified in units of dB in 1 dB steps (0...127). Default is 20 dB. Property 0x5500. WB_SAME_INTERRUPT_SOURCE Configures the SAME interrupt sources. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: Si4707 Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 000000 EOMDET SOMDET PREDET HDRRDY Bit Name Function 15:4 Reserved Always write to 0. 3 EOMDET Enable EOMDET as the source of SAME Interrupt. 2 SOMDET Enable SOMDET as the source of SAME Interrupt. 1 PREDET Enable PREDET as the source of SAME Interrupt. 0 HDRRDY Enable HDRRDY as the source of SAME Interrupt. Rev. 1.2 205 AN332 Property 0x5600. WB_ASQ_INT_SOURCE Configures interrupt related to the 1050kHz alert tone. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name X X X X X X XXXXXX X X ALERTOFF_IEN ALERTON_IEN Bit Name Function 1 ALERTOFF_IEN Interrupt Source Enable: Alert OFF. Enable 1050kHz alert tone disappeared as the source of interrupt. 0 ALERTON_IEN Interrupt Source Enable: Alert ON. Enable 1050kHz alert tone appeared as the source of interrupt. Property 0x4000. RX_VOLUME Sets the audio output volume. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 63. Available in: All Default: 0x003F Step: 1 Range: 0-63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name VOL[15:0] Bit Name Function 15:0 VOL Output Volume. Sets the output volume level, 63 max, 0 min. Default is 63. 206 Rev. 1.2 AN332 Property 0x4001. RX_HARD_MUTE Mutes the audio output. L and R audio outputs may not be muted independently. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is unmute (0x0000). Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name Function 15:2 Reserved Always write to 0. 1 LMUTE Mutes both L and R Audio Outputs. 0 RMUTE Mutes both L and R Audio Outputs. Rev. 1.2 207 AN332 5.5. Commands and Properties for the Stereo Audio ADC Mode (Si4704/05/30/31) The following two tables are the summary of the commands and properties for the Stereo Audio ADC component applicable to Si4704/05/30/31-D62. Table 21. Stereo Audio ADC Mode Command Summary Cmd Name Description Devices 0x01 POWER_UP Power-up device and mode selection. Modes include operational function and audio interface configuration All 0x10 GET_REV Returns the revision information on the device. All 0x11 POWER_DOWN Power-down device. All 0x12 SET_PROPERTY Sets the value of a property. All 0x13 GET_PROPERTY Retrieves a property's value. All 0x14 GET_INT_STATUS Read interrupt status bits. All 0x15 PATCH_ARGS* Reserved command used for patch file down-loads. All 0x16 PATCH_DATA* Reserved command used for patch file down-loads. All 0x61 AUX_ASRC_START Starts sampling rate conversion. All 0x65 AUX_ASQ_STATUS Reports audio signal quality metrics. All 0x80 GPIO_CNTL Configures GPO1, 2, and 3 as output or Hi-Z All 0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high). All *Note: Commands PATCH_ARGS and PATCH_DATA are only used to patch firmware. For information on applying a patch file, see "7.2. Powerup from a Component Patch" on page 236. Table 22. Stereo Audio ADC Mode Property Summary Prop Name 0x0001 0x0102 GPO_IEN DIGITAL_OUTPUT_ FORMAT 0x0104 DIGITAL_OUTPUT_ SAMPLE_RATE 0x0201 REFCLK_FREQ 0x0202 REFCLK_PRESCALE 0x6600 AUX_ASQ_INTERRUPT_SOURCE Description Enables interrupt sources. Configure digital audio outputs. Configure digital audio output sample rate. Sets the frequency of the reference clock in Hz. The range is 31130 to 34406 Hz. Sets prescaler value for the reference clock. Configure ASQ Interrupt source. Default 0x0000 0x0000 0x0000 0x8000 0x0001 0x0000 Available In All All All All All All 208 Rev. 1.2 AN332 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CTS ERR X X X X ASQINT X Bit Name Function 7 CTS Clear to Send. 0 = Wait before sending next command. 1 = Clear to send next command. 6 ERR Error. 0 = No error 1 = Error 5:2 Reserved Values may vary. 1 ASQINT Audio Signal Quality Interrupt. 0 = Audio signal quality interrupt has not been triggered. 1 = Audio signal quality interrupt has been triggered. 0 Reserved Values may vary. Rev. 1.2 209 AN332 5.5.1. Stereo Audio ADC Mode Commands Command 0x01. POWER_UP Initiates the boot process to move the device from powerdown to powerup mode. The boot can occur from internal device memory or a system controller downloaded patch. To confirm that the patch is compatible with the internal device library revision, the library revision should be confirmed by issuing the POWER_UP command with FUNC = 15 (query library ID). The device returns the response, including the library revision, and then moves into powerdown mode. The device can then be placed in powerup mode by issuing the POWER_UP command with FUNC = 4 (AUX Input) and the patch may be applied (See Section "7.2. Powerup from a Component Patch" on page 236). The POWER_UP command configures the state of LIN (pin 15) and RIN (pin 16) for analog audio inputs and GPO2/INT (pin 18) for interrupt operation. POWER_UP command also configures the state of GPO3/DCLK (pin 17), DFS (pin 14), and DOUT (pin 13) for digital audio mode. The command configures GPO2/INT interrupts (GPO2OEN) and CTS interrupts (CTSIEN). If both are enabled, GPO2/INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt. The CTSIEN bit is duplicated in the GPO_IEN property. The command is complete when the CTS bit (and optional interrupt) is set. Note: To change function (e.g. FM RX to AUX IN or AUX IN to AM RX), issue POWER_DOWN command to stop current function; then, issue POWER_UP to start new function. Note: Delay at least 500 ms between powerup command and first tune command to wait for the oscillator to stabilize if XOSCEN is set and crystal is used as the RCLK. Available in: All Command Arguments: Two Response Bytes: None (FUNC = 0), Seven (FUNC = 15) Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 0 0 0 0 1 ARG1 CTSIEN GPO2OEN PATCH XOSCEN FUNC[3:0] ARG2 OPMODE[7:0] ARG Bit 1 7 1 6 1 5 Name CTSIEN GPO2OEN PATCH Function CTS Interrupt Enable. 0 = CTS interrupt disabled. 1 = CTS interrupt enabled. GPO2 Output Enable. 0 = GPO2 output disabled. 1 = GPO2 output enabled. Patch Enable. 0 = Boot normally. 1 = Copy NVM to RAM, but do not boot. After CTS has been set, RAM may be patched. 210 Rev. 1.2 AN332 ARG Bit 1 4 1 3:0 2 7:0 Name XOSCEN FUNC[3:0] OPMODE[7:0] Function Crystal Oscillator Enable. Note: Set to 0 for Si4740/41/42/43/44/45/49 0 = Use external RCLK (crystal oscillator disabled). 1 = Use crystal oscillator (RCLK and GPO3/DCLK with external 32.768 kHz crys- tal and OPMODE=00000101). See Si47xx Data Sheet Application Schematic for external BOM details. Function. 03 = Reserved. 4 = AUX IN. 514 = Reserved. Application Setting. 01011011 = Digital audio outputs (DCLK, DFS, DIO) Response (FUNC = 4, AUX IN) Bit STATUS D7 D6 D5 D4 D3 CTS ERR X X X D2 D1 D0 X ASQINT X Response (FUNC = 15, Query Library ID) Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 D7 D6 D5 CTS ERR X D4 D3 D2 X X X PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] D1 D0 ASQINT X RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] RESERVED[7:0] RESERVED[7:0] CHIPREV[7:0] LIBRARYID[7:0] Function Final 2 digits of part number (HEX). Firmware Major Revision (ASCII). Firmware Minor Revision (ASCII). Reserved, various values. Reserved, various values. Chip Revision (ASCII). Library Revision (HEX). Rev. 1.2 211 AN332 Command 0x10. GET_REV Returns the part number, chip revision, firmware revision, patch revision and component revision numbers. The command is complete when the CTS bit (and optional interrupt) is set. This command may only be sent when in powerup mode. Available in: All Command arguments: None Response bytes: Fifteen (Si4705 only), Eight (Si4704/3x) Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 Response Bit STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP10 RESP11 RESP12 RESP13 RESP14 RESP15 D7 CTS D6 ERR D5 D4 D3 D2 D1 D0 X X X X ASQINT X PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] Reserved Reserved Reserved Reserved Reserved CID[7:0] (Si4705 only) RESP Bit 1 7:0 2 7:0 3 7:0 4 7:0 5 7:0 6 7:0 7 7:0 8 7:0 15 7:0 Name PN[7:0] FWMAJOR[7:0] FWMINOR[7:0] PATCHH[7:0] PATCHL[7:0] CMPMAJOR[7:0] CMPMINOR[7:0] CHIPREV[7:0] CID[7:0] Function Final 2 digits of Part Number (HEX). Firmware Major Revision (ASCII). Firmware Minor Revision (ASCII). Patch ID High Byte (HEX). Patch ID Low Byte (HEX). Component Major Revision (ASCII). Component Minor Revision (ASCII). Chip Revision (ASCII). CID (Si4705 only). 212 Rev. 1.2 AN332 Command 0x11. POWER_DOWN Moves the device from powerup to powerdown mode. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond. The device will only respond when a POWER_UP command is written. GPO pins are powered down and not active during this state. For optimal power down current, GPO2 must be either internally driven low through GPIO_CTL command or externally driven low. Note: The following describes the state of all the pins when in powerdown mode: GPIO1, GPIO2, and GPIO3 = 0 DOUT, DFS, RIN, LIN = HiZ Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 1 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X X X X Rev. 1.2 213 AN332 Command 0x12. SET_PROPERTY Sets a property shown in Table 22, "Stereo Audio ADC Mode Property Summary," on page 208. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. See Figure 30, "CTS and SET_PROPERTY Command Complete tCOMP Timing Model," on page 246 and Table 53, "Command Timing Parameters for the Stereo Audio ADC Mode," on page 250. Available in: All Command Arguments: Five Response bytes: None Command Bit CMD ARG1 ARG2 ARG3 ARG4 ARG5 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] PROPDH[7:0] PROPDL[7:0] ARG 1 2 3 4 5 Bit Name Function 7:0 Reserved Always write to 0. 7:0 PROPH[7:0] Property High Byte. This byte in combination with PROPL is used to specify the property to modify. 7:0 PROPL[7:0] Property Low Byte. This byte in combination with PROPH is used to specify the property to modify. 7:0 PROPDH[7:0] Property Value High Byte. This byte in combination with PROPDL is used to set the property value. 7:0 PROPDL[7:0] Property Value Low Byte. This byte in combination with PROPDH is used to set the property value. 214 Rev. 1.2 AN332 Command 0x13. GET_PROPERTY Gets a property as shown in Table 22, "Stereo Audio ADC Mode Property Summary," on page 208. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: Three Response bytes: Three Command Bit CMD ARG1 ARG2 ARG3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 PROPH[7:0] PROPL[7:0] ARG Bit 1 7:0 2 7:0 3 7:0 Response Name Reserved PROPH[7:0] PROPL[7:0] Function Always write to 0. Property High Byte. This byte in combination with PROPL is used to specify the property to get. Property Low Byte. This byte in combination with PROPH is used to specify the property to get. Bit D7 D6 D5 STATUS CTS ERR X RESP1 0 0 0 RESP2 RESP3 D4 D3 X X 0 0 PROPDH[7:0] PROPDL[7:0] D2 D1 D0 X ASQINT X 0 0 0 RESP Bit 1 7:0 2 7:0 3 7:0 Name Reserved PROPDH[7:0] PROPDL[7:0] Function Always returns 0. Property Value High Byte. This byte in combination with PROPDL represents the requested property value. Property Value High Byte. This byte in combination with PROPDH represents the requested property value. Rev. 1.2 215 AN332 Command 0x14. GET_INT_STATUS Updates bits 6:0 of the status byte. This command should be called after any command that sets the ASQINT bit. When polling this command should be periodically called to monitor the STATUS byte, and when using interrupts, this command should be called after the interrupt is set to update the STATUS byte. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be set when in powerup mode. Available in: All Command arguments: None Response bytes: None Command Bit CMD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 0 Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X X ASQINT X Command 0x61. AUX_ASRC_START Starts sample rate conversion in signal processing module. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The ERR bit (and optional interrupt) is set if an invalid argument is sent. Note that only a single interrupt occurs if both the CTS and ERR bits are set. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 1 0 0 0 0 1 Response Bit D7 D6 D5 D4 D3 STATUS CTS ERR X X X D2 D1 D0 X ASQINT X 216 Rev. 1.2 AN332 Command 0x65. AUX_ASQ_STATUS Returns status information about audio signal quality. The command returns the input signalLEVEL. This command can be used to detect if a signal overload condition is present indicated by OVERLOADINT. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. Available in: All Command arguments: One Response bytes: Three Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 1 0 0 1 0 1 ARG1 0 0 0 0 0 0 0 INTACK ARG Bit 1 0 Response Bit STATUS RESP1 RESP2 RESP3 Name INTACK Interrupt Acknowledge. 0 = Interrupt status preserved. 1 = Clears ASQINT Function D7 D6 D5 CTS ERR X X X X X X X D4 D3 D2 X X X X X X X X X LEVEL[7:0] D1 ASQINT X X D0 X OVERLOADINT OVERLOAD RESP Bit Name Function Audio Signal Overload Interrupt. 1 0 OVERLOADINT 0 = Audio Input Signal overload has not been detected. 1 = Audio Input Signal overload has been detected. Audio Signal Overload. 2 0 OVERLOAD 0 = Audio Input Signal overload is not present. 1 = Audio Input Signal overload is present. Audio Input Signal Level. 3 7:0 LEVEL[7:0] Line input audio level indicator in FS. Range: 128 to 127 Rev. 1.2 217 AN332 Command 0x80. GPIO_CTL Enables output for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output (Hi-Z or active drive) by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit. The state (high or low) of GPO1, 2, and 3 is set with the GPIO_SET command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup mode. The default is all GPO pins set for high impedance. Note: The use of GPO2 as an interrupt pin and/or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and/or GPO3 respectively. Available in: All Command arguments: One Response bytes: None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Name Reserved GPO3OEN GPO2OEN GPO1OEN Reserved Function Always write 0. GPO3 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO2 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. GPO1 Output Enable. 0 = Output Disabled (Hi-Z) (default). 1 = Output Enabled. Always write 0. Bit D7 D6 D5 D4 D3 D2 STATUS CTS ERR X X X X D1 D0 ASQINT X 218 Rev. 1.2 AN332 Command 0x81. GPIO_SET Sets the output level (high or low) for GPO1, 2, and 3. GPO1, 2, and 3 can be configured for output by setting the GPO1OEN, GPO2OEN, and GPO3OEN bit in the GPIO_CTL command. To avoid excessive current consumption due to oscillation, GPO pins should not be left in a high impedance state. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is all GPO pins set for high impedance. Available in: All Command arguments: One Response bytes: None Command Bit D7 CMD 1 ARG1 0 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit 1 7:4 1 3 1 2 1 1 1 0 Response Name Reserved GPO3LEVEL GPO2LEVEL GPO1LEVEL Reserved Always write 0. GPO3 Output Level. 0 = Output low (default). 1 = Output high. GPO2 Output Level. 0 = Output low (default). 1 = Output high. GPO1 Output Level. 0 = Output low (default). 1 = Output high. Always write 0. Function Bit D7 D6 D5 D4 D3 D2 STATUS CTS ERR X X X X D1 D0 ASQINT X Rev. 1.2 219 AN332 5.5.2. Stereo Audio ADC Mode Properties Property 0x0001. GPO_IEN Configures the sources for the GPO2/INT interrupt pin. Valid sources are the lower 8 bits of the STATUS byte, including CTS, ERR, and ASQINT bits. The corresponding bit is set before the interrupt occurs. The CTS bit (and optional interrupt) is set when it is safe to send the next command. The CTS interrupt enable (CTSIEN) can be set with this property and the POWER_UP command. The state of the CTSIEN bit set during the POWER_UP command can be read by reading this property and modified by writing this property. This property may only be set or read when in powerup mode. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 ASQIEN 0 CTSIEN ERRIEN 0 0 0 0 ASQIEN 0 Bit 15:10 9 8 7 6 5:2 1 0 Name Reserved ASQREP Reserved CTSIEN ERRIEN Reserved ASQIEN Reserved Function Always write to 0. ASQ Interrupt Repeat. 0 = No interrupt generated when ASQINT is already set (default). 1 = Interrupt generated even if ASQINT is already set. Always write to 0. CTS Interrupt Enable. After PowerUp, this bit reflects the CTSIEN bit in ARG1 of PowerUp Command. 0 = No interrupt generated when CTS is set. 1 = Interrupt generated when CTS is set. ERR Interrupt Enable. 0 = No interrupt generated when ERR is set (default). 1 = Interrupt generated when ERR is set. Always write to 0. ASQ Interrupt Enable. 0 = No interrupt generated when ASQINT is set (default). 1 = Interrupt generated when ASQINT is set. Always write to 0. 220 Rev. 1.2 AN332 Property 0x0102. DIGITAL_OUTPUT_FORMAT Configures the digital audio output format. Configuration options include DCLK edge, data format, force mono, and sample precision. Available in: All Default: 0x0000 Bit 15 14 13 12 11 10 9 8 Name 0 0 0 0 0 0 0 0 7 OFALL 6543 OMODE[3:0] 2 OMONO 1 0 OSIZE[1:0] Bit Name Function 15:8 Reserved Always write to 0. Digital Output DCLK Edge. 7 OFALL 0 = use DCLK rising edge 1 = use DCLK falling edge Digital Output Mode. 0000 = I2S 6:3 OMODE[3:0] 0110 = Left-justified 1000 = MSB at second DCLK after DFS pulse 1100 = MSB at first DCLK after DFS pulse Digital Output Mono Mode. 2 OMONO 0 = Use mono/stereo blend (per blend thresholds) 1 = Force mono Digital Output Audio Sample Precision. 0 = 16-bits 1:0 OSIZE[1:0] 1 = 20-bits 2 = 24-bits 3 = 8-bits Rev. 1.2 221 AN332 Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE Enables digital audio output and configures digital audio output sample rate in samples per second (sps). When DOSR[15:0] is 0, digital audio output is disabled. The over-sampling rate must be set in order to satisfy a minimum DCLK of 1 MHz. To enable digital audio output, program DOSR[15:0] with the sample rate in samples per second. The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset. The sample rate must be set to 0 before the DCLK/DFS is removed. Available in: All Default: 0x0000 (digital audio output disabled) Units: sps Range: 3248 ksps, 0 to disable digital audio output Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DOSR[15:0] Bit Name Function 15:0 DOSR[15:0] Digital Output Sample Rate. 32, 44.1, and 48 ksps. 0 to disable digital audio output. 222 Rev. 1.2 AN332 Property 0x0201. REFCLK_FREQ Sets the frequency of the REFCLK from the output of the prescaler. The REFCLK range is 31130 to 34406 Hz (32768 ±5% Hz) in 1 Hz steps, or 0 (to disable AFC). For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz REFCLK. The reference clock frequency property would then need to be set to 32500 Hz. RCLK frequencies between 31130 Hz and 40 MHz are supported, however, there are gaps in frequency coverage for prescaler values ranging from 1 to 10, or frequencies up to 311300 Hz. The following table summarizes these RCLK gaps. PIN 9 RCLK 31.130 kHz 40 MHz Prescaler Divide by 1-4095 REFCLK 31.130 kHz 34.406 kHz Figure 16. REFCLK Prescaler Table 23. RCLK Gaps Prescaler 1 2 3 4 5 6 7 8 9 10 RCLK Low (Hz) 31130 62260 93390 124520 155650 186780 217910 249040 280170 311300 RCLK High (Hz) 34406 68812 103218 137624 172030 206436 240842 275248 309654 344060 The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 32768 Hz. The RCLK must be valid 10 ns before sending and 20 ns after completing the AUX_ASRC_START command. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times. Available in: All Default: 0x8000 (32768) Units: 1 Hz Step: 1 Hz Range: 3113034406 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF[15:0] Bit Name Function Rev. 1.2 223 AN332 Frequency of Reference Clock in Hz. 15:0 REFCLKF[15:0] The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 ±5%), or 0 (to disable AFC). Property 0x0202. REFCLK_PRESCALE Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK must be valid 10 ns before sending and 20 ns after completing the AUX_ASRC_START command. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed or reconfigured at other times.The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in powerup mode. The default is 1. Available in: All Default: 0x0001 Step: 1 Range: 14095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLKSEL REFCLKP[11:0] Bit 15:13 12 11:0 Name Reserved RCLKSEL REFCLKP[11:0] Function Always write to 0. 0 = RCLK pin is clock source. 1 = DCLK pin is clock source. Prescaler for Reference Clock. Integer number used to divide clock frequency down to REFCLK frequency. The allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or 0 (to disable AFC). 224 Rev. 1.2 AN332 Property 0x6600. AUX_ASQ_INTERRUPT_SOURCE Configures interrupt related to Audio Signal Quality metrics. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This property may only be set or read when in power up mode. The default is 0. Available in: All Default: 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Name 0X0000 D1 D0 OVER LOADINT Bit Name Function 15:2 Reserved Always write to 0. 1:0 OVERLOADINT Interrupt Source Enable: Overload 0 = Disable audio signal overload detection interrupt 1 = Enable audio signal overload detection interrupt Rev. 1.2 225 AN332 6. Control Interface The bus mode is selected by sampling the state of the GPO1 and GPO2/INT pins on the rising edge of RST. The GPO1 pin includes a 1 M internal pull-up resistor that is connected while RST is low, and the GPO2/INT pin includes an internal 1 M pull-down resistor that is connected while the RST pin in low. Therefore, it is only necessary for the system controller to actively drive pins if a mode other than the default 2-wire mode is required, as shown in Table 24. After bus mode selection is complete, the device is placed in powerdown mode. The minimum setup time for GPO1 and GPO2 before RST = 1 is 30 ns when actively driven by the system controller and 100 µs if the internal 1 M resistor is allowed to set the default GPO1 (high) and GPO2 (low). Refer to the Si471x data sheet for specific reset timing requirements. Table 24. Bus Mode Selection Bus Mode 3-wire SPI 2-wire GPO2/INT 0 1 (must drive) 0 GPO1 0 (must drive) 1 1 In powerdown mode, all circuitry is disabled except for the device control interface. The device comes out of powerdown mode when the POWER_UP command is written to the command register. Once in powerup mode, the device accepts additional commands, such as tuning, and the setting of properties, such as power level. The device will not accept commands while in powerdown mode, with the exception of the powerup command. If the system controller writes a command other than POWER_UP when in powerdown mode, the device does not respond, and a reset is required. Setting the RST pin low places the device in reset mode. In reset mode, all circuitry is disabled including the device control interface; registers are set to their default settings, and the control bus is disabled. 6.1. 2-Wire Control Interface Mode Figures 17 and 18 show the 2-wire Control Interface Read and Write Timing Parameters and Diagrams, respectively. Refer to the Si471x data sheet for timing parameter values. tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF SCLK 70% 30% SDIO 70% 30% START tr:IN tHD:DAT tSU:DAT tf:IN, tf:OUT STOP START Figure 17. 2-wire Control Interface Read and Write Timing Parameters 226 Rev. 1.2 AN332 SCLK SDIO A6-A0, R/W D7-D0 D7-D0 START ADDRESS + R/W ACK DATA ACK DATA ACK STOP Figure 18. 2-wire Control Interface Read and Write Timing Diagram 2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the system controller drives an 8-bit control word serially on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a seven-bit device address followed by a read/write bit (read = 1, write = 0). The device acknowledges the control word by driving SDIO low on the next falling edge of SCLK. Although the device responds to only a single device address, this address can be changed with the SEN pin (note that the SEN pin is not used for signaling in 2-wire mode). When SEN = 0, the seven-bit device address is 0010001b. When SEN = 1, the address is 1100011b. For write operations, the system controller next sends a data byte on SDIO, which is captured by the device on rising edges of SCLK. The device acknowledges each data byte by driving SDIO low for one cycle on the next falling edge of SCLK. The system controller may write up to 8 data bytes in a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments. Writing more than 8 bytes results in unpredictable device behavior. For read operations, after the device has acknowledged the control byte, it will drive an eight-bit data byte on SDIO, changing the state of SDIO on the falling edges of SCLK. The system controller acknowledges each data byte by driving SDIO low for one cycle on the next falling edge of SCLK. If a data byte is not acknowledged by the system controller, the transaction will end. The system controller may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the status byte and response data from the device. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. Table 25 demonstrates the command and response procedure implemented in the system controller to use the 2wire bus mode. In this example the TX_TUNE_FREQ command is demonstrated. Table 25. Command and Response Procedure - 2-Wire Bus Mode Action CMD ARG1 ARG2 ARG3 STATUS Data 0x30 0x00 0x27 0x7E 0x80 Description TX_TUNE_FREQ Set Station to 101.1 MHz (0x277E = 10110 with 10 kHz step size) Reply Status. Clear-to-send high. Rev. 1.2 227 AN332 To send the TX_TUNE_FREQ command and arguments, the system controller sends the START condition, followed by the 8-bit control word, which consists of a seven-bit device address (0010001b SEN = 0 or 1100011b SEN = 1) and the write bit (0b) indicated by ADDR+W = 00100010b = 0x22. In this example, SEN = 0 resulting in the control word ADDR+W = 00100010b = 0x22. If instead SEN = 1, the resulting control word would be ADDR+W = 11000110b = 0xC6. The device acknowledges the control word by setting SDIO = 0, indicated by ACK = 0. The system controller then sends the CMD byte, 0x30, and again the device acknowledges by setting ACK = 0. The system controller and device repeat this process for the ARG1, ARG2, and ARG3 bytes. Commands may take up to seven argument bytes, and this flexibility should be designed into the 2-wire bus mode implementation. Alternatively, all seven argument bytes may be sent for all commands, but unusual arguments must be 0x00. Unpredictable device behavior will result if more than seven arguments are sent. START ADDR+W ACK CMD ACK ARG1 ACK ARG2 ACK ARG3 ACK STOP START 0x22 0 0x30 0 0x00 0 0x27 0 0x7E 0 STOP To read the status and response from the device, the system controller sends the START condition, followed by the eight-bit control word, which consists of the seven bit device address and the read bit (1b). In this example, SEN = 0 and the write control word is ADDR+R = 00100011b = 0x23. If SEN = 1, the write control word would be ADDR+R = 11000111b = 0xC7. The device acknowledges the control word by setting ACK = 0. Next the system controller reads the STATUS byte. In this example, the STATUS byte is 0x00, indicating that the CTS bit, bit 8, has not been set. The response bytes are not ready for reading and that the device is not ready to accept another command. The system controller sets SDIO = 1, indicated by NACK = 1, to signal to the device the 2-wire transfer will end. The system controller should set the STOP condition. This process is repeated until the STATUS byte indicates that CTS bit is set, 0x80 in this example. START START ADDR+R 0x23 ACK 0 STATUS 0x00 NACK 1 STOP STOP When the STATUS byte returns CTS bit set, 0x80 in this example, the system controller may read the response bytes from the device. The controller sets ACK = 0 to indicate to the device that additional bytes will be read. The RESP1 byte is read by the system controller, followed by the system controller setting ACK = 0. This is repeated for RESP2. RESP3 is read by the system controller followed by the system controller setting NACK = 1, indicating that RESP3 is the last byte to be read. The system controller then sets the STOP condition. Responses may be up to 15 bytes in length (RESP1RESP15) depending on the command. It is acceptable to read all 15 response bytes. However, unused response bytes return random data and must be ignored. Note that the TX_TUNE_FREQ command returns only the STATUS byte and response bytes are shown only for completeness. START ADDR+R ACK STATUS ACK RESP1 ACK RESP2 ACK RESP3 NACK STOP START 0x23 0 0x80 0 0x00 0 0x00 0 0x00 1 STOP 228 Rev. 1.2 AN332 6.2. 3-Wire Control Interface Mode Figures 19 and 20 show the 3-wire Control Interface Read and Write Timing Parameters and Diagrams, respectively. Refer to the Si471x data sheet for timing parameter values. SCLK 70% 30% tS SEN 70% 30% tHSDIO tS tHIGH tLOW tHSEN SDIO 70% 30% A6-A5, A7 R/W, A0 A4-A1 D15 D14-D1 D0 Address In Data In Figure 19. 3-Wire Control Interface Write Timing Parameters SCLK 70% 30% tS SEN 70% 30% tHSDIO tS tCDV tHSEN tCDZ 80% SDIO 20% A6-A5, A7 R/W, A0 A4-A1 D15 D14-D1 D0 Address In ½ Cycle Bus Data Out Turnaround Figure 20. 3-Wire Control Interface Read Timing Parameters 3-wire bus mode uses the SCLK, SDIO and SEN pins. A transaction begins when the system controller drives SEN low. Next, the system controller drives a 9-bit control word on SDIO, which is captured by the device on rising edges of SCLK. The control word is comprised of a three bit chip address (A7:A5 = 101b), a read/write bit (write = 0, read = 1), the chip address (A4 = 0), and a four bit register address (A3:A0). For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turnaround. Next, the device drives the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the device drives the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the system controller sets SEN = 1, then pulses SCLK high and low one final time. SCLK may either stop or continue to toggle while SEN is high. In 3-wire mode, commands are sent by first writing each argument to register(s) 0xA10xA3, then writing the command word to register 0xA0. A response is retrieved by reading registers 0xA80xAF. Rev. 1.2 229 AN332 Table 26. Register Map for 3-Wire Mode 3w Addr Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0h COMMAND1 CMD ARG1 A1h COMMAND2 ARG2 ARG3 A2h COMMAND3 ARG4 ARG5 A3h COMMAND4 ARG6 ARG7 A4h Reserved1 Reserved Reserved A5h Reserved2 Reserved Reserved A6h Reserved3 Reserved Reserved A7h Reserved4 Reserved Reserved A8h STATUS/ RESPONSE1 CTS ERR RSDIN RDSIN ASQIN STCIN T T T T RESP1 A9h RESPONSE2 RESP2 RESP3 AAh RESPONSE3 RESP4 RESP5 ABh RESPONSE4 RESP6 RESP7 ACh RESPONSE5 RESP8 RESP9 ADh RESPONSE6 RESP10 RESP11 AEh RESPONSE7 RESP12 RESP13 AFh RESPONSE8 RESP14 RESP15 In 3-wire mode, the control registers are accessed as 16-bit entities (2 byte). In Table 26, the full 8-bit 3-wire address is shown, including the chip's fixed base address (A7:A4 = 1010b). The first two bytes in a command stream uses register COMMAND1. The CMD byte occupies register COMMAND1[15:8], while ARG1 occupies register COMMAND1[7:0]. Commands with an odd number of bytes must have the lower 8 bits of the register containing the final argument byte filled with 0x00. Registers which are not specified by the command must either not be written, or must be filled with 0x0000 (user's discretion). Writing register COMMAND1 causes the command to execute. As a consequence, all registers containing applicable argument bytes must be written (in any order) prior to writing register COMMAND1. For example, when sending the SET_PROPERTY command, write registers COMMAND2..COMMAND3 first, then register COMMAND1. Note that ARG1 is part of register COMMAND1 and must be written at the same time as CMD. The contents of registers STATUS/RESPONSE1..RESPONSE8 are not valid until the CTS bit (STATUS/RESPONSE1[15]) is set. RESPONSE1[13:8] is updated after sending the GET_INT_STATUS command. Response bytes which are not specified in the response byte stream are not guaranteed to be 0x00 and should be ignored. For example, GET_PROPERTY has 4 bytes of response data in registers RESPONSE1..RESPONSE2. The contents of registers RESPONSE3..RESPONSE8 are meaningless and not guaranteed to be 0x0000. Likewise, for commands which have an odd number of response bytes, or a single status byte, the least significant byte (bits 7:0) of the final register is meaningless, and not guaranteed to be 0x00. Table 27 demonstrates the command and response procedure implemented in the system controller to use the 3wire bus mode. In this example the TX_TUNE_FREQ command is demonstrated. Table 27. Command and Response Procedure--3-Wire Bus Mode Action CMD ARG1 ARG2 ARG3 STATUS Data 0x30 0x00 0x27 0x7E 0x80 Description TX_TUNE_FREQ. Set Station to 101.1 MHz (0x277E = 10110 with 10 kHz step size) Reply Status. Clear-to-send high. 230 Rev. 1.2 AN332 To send the TX_TUNE_FREQ command and arguments, the system controller sets SEN = 0. Next, the controller drives the 9-bit control word on SDIO, consisting of the device address (A7:A5 = 101b), the write bit (0b), the device address (A4 = 0), and the register address for the COMMAND2 register (A3:A0 = 0001b). The control word is followed by a 16-bit data word, consisting of ARG2 followed by ARG3. The system controller then sets SEN = 1 and pulses the SCLK high and then low one final time. For commands requiring additional arguments, in the COMMAND3 (ARG3, ARG4) and COMMAND4 (ARG5, ARG6) registers, the system controller would send these next. SEN 1 0 CTL 101000001b ARG2 0x27 ARG3 0x7E SEN 0 1 SCLK Pulse Next the system controller initiates the command by setting SEN = 0 and driving the 9-bit control word on SDIO, consisting of the device address (A7:A5 = 101b), the write bit (0b), the device address (A4 = 0), and the register address for the COMMAND1 register (A3:A0 = 0000b). The control word is followed by a 16-bit data word, consisting of the CMD byte followed by ARG1 byte. The system controller then sets SEN = 1 and pulses the SCLK high and then low one final time. SEN 1 0 CTL 101000000b CMD 0x30 ARG1 0x00 SEN 0 1 SCLK Pulse To read the status and response from the device, the system controller sets SEN = 0. Next, the controller drives the 9-bit control word 101101000b on SDIO, consisting of the device address (A7:A5 = 101b), the read bit (1b), the device address (A4 = 0), and the register address for the STATUS/RESPONSE1 register (A3:A0 = 1000b). The control word is followed by a 16-bit data word, consisting of STATUS followed by RESPONSE1. The system controller then sets SEN = 1 and pulses the SCLK high and then low one final time. In this example, the STATUS byte is 0x00, indicating that the CTS bit, bit 8, has not been set and that the response bytes are not ready for reading and that the device is not ready to accept another command. RESP1 will be random until the CTS bit is set. This process should be repeated until the STATUS byte indicates that CTS bit is set, 0x80 in this example. SEN 1 0 CTL 101101000b STATUS 0x00 RESP1 0x00 SEN 0 1 SCLK Pulse When the STATUS byte indicates that the CTS bit has been set, 0x80 in this example, the system controller may read the RESPONSE bytes from the device in any order. SEN 1 0 CTL 101101000b STATUS 0x80 RESP1 0x00 SEN 0 1 SCLK Pulse Rev. 1.2 231 AN332 6.3. SPI Control Interface Mode Figures 21 and 22 show the SPI Control Interface Read and Write Timing Parameters and Diagrams, respectively. Refer to the Si471x data sheet for timing parameter values. SCLK 70% 30% SEN 70% 30% tS tS tHIGH tLOW tHSDIO tHSEN SDIO 70% 30% C7 C6C1 C0 D7 D6D1 D0 Control Byte In 8 Data Bytes In Figure 21. SPI Control Interface Write Timing Parameters SCLK 70% 30% SEN 70% 30% SDIO 70% or GPO1 30% tS tS C7 C6C1 tCDV tHSDIO C0 D7 tHSEN D6D1 tCDZ D0 Control Byte In Bus Turnaround 16 Data Bytes Out Figure 22. SPI Control Interface Read Timing Parameters SPI bus mode uses the SCLK, SDIO and SEN pins for read/write operations. The system controller can choose to receive read data from the device on either SDIO or GPO1. A transaction begins when the system controller drives SEN = 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO. The device captures the data on rising edges of SCLK. The control byte must have one of five values: 0x48 = write a command (controller drives 8 additional bytes on SDIO) 0x80 = read a response (device drives one additional byte on SDIO) 0xC0 = read a response (device drives 16 additional bytes on SDIO) 0xA0 = read a response (device drives one additional byte on GPO1) 0xE0 = read a response (device drives 16 additional bytes on GPO1) For write operations, the system controller must drive exactly 8 data bytes (a command and arguments) on SDIO after the control byte. The data is captured by the device on the rising edge of SCLK. 232 Rev. 1.2 AN332 For read operations, the controller must read exactly one byte (STATUS) after the control byte or exactly 16 data bytes (STATUS and RESP1RESP15) after the control byte. The device changes the state of SDIO (or GPO1, if specified) on the falling edge of SCLK. Data must be captured by the system controller on the rising edge of SCLK. Keep SEN low until all bytes have transferred. A transaction may be aborted at any time by setting SEN high and toggling SCLK high and then low. Commands will be ignored by the device if the transaction is aborted. Table 28 demonstrates the command and response procedure that would need to be implemented in the system controller to use the SPI bus mode. In this example the TX_TUNE_FREQ command is demonstrated. Action CMD ARG1 ARG2 ARG3 STATUS Table 28. Command and Response Procedure - SPI Bus Mode Data 0x30 TX_TUNE_FREQ Description 0x00 0x27 Set Station to 101.1 MHz 0x7E (0x277E = 10110 with 10 kHz step size) 0x80 Reply Status. Clear-to-send high. To send the TX_TUNE_FREQ command and arguments, the system controller sets SEN = 0, sends the control byte 0x48, followed by the CMD byte and seven argument bytes, ARG1-ARG7, followed by setting SEN = 1. Note that all seven argument bytes must be sent by the controller or the command will fail. Unused arguments must be written as 0x00. SEN 1 0 CTL 0x48 CMD 0x30 ARG1 0x00 ARG2 0x27 ARG3 0x7E ARG4 0x00 ARG5 0x00 ARG6 0x00 ARG7 0x00 SEN 0 1 To read the status and response from the device, the system controller sets SEN = 0 and sends the control byte 0x80 to read the response on SDIO (or the control byte 0xA0 to read the response on GPO1). Next the system controller reads the STATUS byte. In this example, the STATUS byte is 0x00, indicating that the CTS bit, bit 8, has not been set and that the response bytes are not ready for reading. The device is not ready to accept another command. The system controller sets SEN = 1 to end the transfer. This process should be repeated until the STATUS byte indicates that CTS bit is set, 0x80 in this example. SEN 1 0 CTL 0x80 STATUS 0x00 SEN 0 1 When the STATUS byte indicates that the CTS bit has been set, 0x80 in this example, the system controller may read the response bytes from the device. To read the status and response from the device, the system controller sets SEN = 0 and sends the control byte 0xC0 to read the response on SDIO (or the control byte 0xE0 to read the response on GPO1). Note that all 16 response bytes must be read from the device. Unused response bytes are random and should be ignored. Note that the TX_TUNE_FREQ command returns only the STATUS byte and RESP1RESP15 bytes are shown only for completeness. SEN CTL STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 RESP13 RESP14 RESP15 SEN 1 0 0xC0 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0 1 Rev. 1.2 233 AN332 7. Powerup There are two procedures for booting the device to move it from powerdown mode to the powerup mode. The first and most common is a boot from internal device memory. The second is a boot from a firmware patch that is written from the system controller to the device. To power up the device: 1. Supply VDD and VIO while keeping the RST = 0. The minimum VDD and VIO rise time is 25 µs, and VDD and VIO must be stable 250 µs before setting RST = 1. Power supplies may be sequenced in any order. RST is in the VIO supply domain and therefore RST = 0 must be maintained before VIO is supplied. 2. Set GPO1 and GPO2 for the desired bus mode. The minimum setup time for GPO1 and GPO2 before RST = 1 is 30 ns when actively driven by the system controller and 100 µs if the internal 1 M resistor is allowed to set the default GPO1 (high) and GPO2 (low). 3. Set RST = 1. 4. Write POWER_UP to the command register. The POWER_UP command instructs the device to boot from internal memory, see Section "7.1. Powerup from Device Memory", or from a firmware patch sent from the system controller, see Section "7.2. Powerup from a Component Patch". After CTS = 1, the device is ready to commence normal operation and accept additional commands. The POWER_UP command configures the state of DIN (pin 13, Si4732 pin 16), DFS (pin 14, Si4732 pin 1), and RIN (pin 15 on Si471x/2x and pin 16 on Si4704/05/3x-D62) and LIN (pin 16 on Si471x/2x and pin 15 on Si4704/05/3x-D62) for analog or digital audio modes and GPO2/INT for interrupt operation. Prior to this command these pins are set to high impedance. The GPIO_CTL and GPIO_SET commands configure the state of GPO2/INT and GPO3. Prior to this command these pins are set to high impedance. 5. Provide RCLK. Note that the RCLK buffer is in the VIO supply domain and may therefore be supplied at any time after VIO is supplied. The RCLK must be valid 10 ns before any command that enables the TX carrier, such as the TX_TUNE_FREQ command, and for 10 ns after any command that disables the carrier, such as the TX_TUNE_POWER command with a value of 0x00. The RCLK is required for proper AGC operation when the carrier is enabled. The RCLK may be removed or reconfigured when the carrier is disabled. VDD >25 us >250 us VIO RSTB RCLK Control Bus >10 ns >10 ns POWER_UP Command Figure 23. Device Power Up Timing TX_TUNE FREQ Command 234 Rev. 1.2 AN332 7.1. Powerup from Device Memory Table 29. Using the POWER_UP Command for the FM Transmitter Action CMD ARG1 ARG2 RESP1 Data 0x01 0x02 0x50 0x80 Description POWER_UP Set to FM Transmit. Set to Analog Line Input. Reply Status. Clear-to-send high. 1. Send the POWER_UP command by writing the CMD field with value 0x01. 2. Send argument 1 of the power up command 0x02 (no patch, CTS and GPO2 interrupts disabled, FM transmit selected). Optionally various interrupts such as the CTS interrupt can be enabled by varying this argument, see Section "5. Commands and Properties". 3. Send argument 2 of the power up command 0x50 (analog input selected) 4. Poll the CTS bit until it has been set high, or until a CTS interrupt is received if CTS interrupt is enabled. Table 30. Using the POWER_UP command for the FM Receiver Action CMD ARG1 ARG2 STATUS Data 0x01 0x00 0x05 0x80 Description POWER_UP Set to FM Receive. Set to Analog Out. Reply Status. Clear-to-send high. 1. Send the POWER_UP command by writing the CMD field with value 0x01. 2. Send ARG1, 0x00 (no patch, CTS and GPO2 interrupts disabled, FM receive selected). Optionally various interrupts such as the CTS interrupt can be enabled by varying this argument, see Section "5. Commands and Properties". 3. Send ARG2, 0x05 (analog output is selected) 4. Poll the CTS bit until it has been set high, or until a CTS interrupt is received (if CTS interrupt is enabled). Table 31. Using the POWER_UP Command for the AM/SW/LW Receiver Action CMD ARG1 ARG2 STATUS Data 0x01 0x01 0x05 0x80 Description POWER_UP Set to AM/SW/LW Receive. Set to Analog Out. Reply Status. Clear-to-send high. 1. Send the POWER_UP command by writing the CMD field with value 0x01. 2. Send ARG1, 0x01 (no patch, CTS and GPO2 interrupts disabled, AM/SW/LW receive selected). Optionally various interrupts such as the CTS interrupt can be enabled by varying this argument, see Section "5. Commands and Properties". 3. Send ARG2, 0x05 (analog output selected) 4. Poll the CTS bit until it has been set high, or until a CTS interrupt is received (if CTS interrupt is enabled). Rev. 1.2 235 AN332 Table 32. Using the POWER_UP Command for the FM Transmitter Action CMD ARG1 ARG2 STATUS Data 0x01 0x03 0x05 0x80 Description POWER_UP Set to Weather Band Receive. Set to Analog Out. Reply Status. Clear-to-send high. 1. Send the POWER_UP command by writing the CMD field with value 0x01. 2. Send ARG1, 0x03 (no patch, CTS and GPO2 interrupts disabled, weather band receive selected). Optionally various interrupts such as the CTS interrupt can be enabled by varying this argument. See Section "5. Commands and Properties". 3. Send ARG2, 0x05 (analog output selected). 4. Poll the CTS bit until it has been set high or until a CTS interrupt is received (if CTS interrupt is enabled). 7.2. Powerup from a Component Patch The device has the ability to receive component patches from the system controller to modify sections or all of the device memory. 7.2.1. Patching Capabilities In order to support interim updates to the device component, patches can be applied to the component by the system controller via a download mechanism. Patches can be provided by Silicon Laboratories to customers to address field issues, errata, or adjust device behavior. Patches are unique to a particular device firmware version and cannot be generated by customers. Patches can be used to replace a portion of the component (to address errata for example) or to download an entirely new component image (to allow a customer to test a new component release on their device prior to receiving programmed parts). Patches are tagged with a unique identification to allow them to be tracked and are encrypted requiring the customer to use a tag when downloading to allow the Si47xx to decrypt the patch. Prior to downloading a partial patch, the user must confirm that the device contains the correct firmware and library to support the patch. 7.2.1.1. Examples An FM transmitter component patch for Si471x firmware 2.0 with library R4 does not support Si471x firmware 1.0 with library R0. For a programmatic indication, the POWER_UP command can be used to confirm the device library and firmware version. For a visual indication, the marking on the device can be used to confirm the firmware version. Tables 33 through 38 summarize the library and firmware mapping and compatibility. Table 33. Si4704/05 Firmware, Library, and Component Compatibility Part # Si4704/05-B20 Si4704/05-C40 Si4704/05-D50 Si4704/05-D60 Si4704/05-D62 Firmware 2.0 4.0 5.0 6.0 6.2 Library R8 R10 R11 R11 R11 FMRX Component 2.0 5.0 7.0 7.0 7.0 AUXIN Component N/A N/A N/A N/A 1.0 236 Rev. 1.2 AN332 Table 34. Si4706 Firmware, Library, and Component Compatibility Part # Si4706-B20 Si4706-C30 Si4706-D50 Firmware 2.0 3.0 5.0 Library R8 R10 R11 FMRX Component 3.0 5.1 7.0 Table 35. Si4707 Firmware, Library, and Component Compatibility Part # Si4707-B20 Firmware 2.0 Library R9 WBRX Component 1.0 Table 36. Si4710/11/12/13 Firmware, Library, and Component Compatibility Part # Si4710-A10 Si4710/11/12/13-A20 Si4710/11/12/13-B30 Si4710/11/12/13-B31 Firmware 1.0 2.0 3.0 3.1 Library R0 R4 R8 R8 FMTX Component 1.0 2.0 3.0 3.1 Table 37. Si4720/21 Firmware, Library, and Component Compatibility Part # Si4720-A10 Si4720/21-B20 Firmware 1.0 2.0 Library R4 R8 FMTX Component 2.0 3.0 FMRX Component 1.0 2.0 Table 38. Si4730/31 Firmware, Library, and Component Compatibility Part # Firmware Si4730-A10 1.0 Si4730/31-B20 2.0 Si4730/31-C40 4.0 Si4730/31-D50 5.0 Si4730/31-D60 6.0 Si4730/31-D62 6.2 Library R4 R9 R10 R11 R11 R11 FMRX Component 1.0 2.0 6.0 7.0 7.0 7.0 AM_SW_LW RX Component 1.0 2.0 5.0 6.0 6.0 6.0 AUXIN Component N/A N/A N/A N/A N/A 1.0 Table 39. Si4740/41/42/43/44/45 Firmware, Library, and Component Compatibility Part # Si4740/41-C10 Si4742/43-C10 Si4744/45-C10 Firmware 1.0 1.0 1.0 Library R10 R10 R10 FMRX Component 4.0 4.0 4.0 AMRX Component 3.0 3.0 3.0 WBRX Component N/A 3.0 N/A Rev. 1.2 237 AN332 Table 40. Si4749 Firmware, Library, and Component Compatibility Part # Si4749-C10 Firmware 1.0 Library R10 FMRX Component 4.0 Table 41. Si4734/35 Firmware, Library, and Component Compatibility Part # Si4734/35-B20 Si4734/35-C40 Si4734/35-D50 Si4734/35-D60 Firmware 2.0 4.0 5.0 6.0 Library R9 R10 R11 R11 FMRX Component 2.0 6.0 7.0 7.0 AM_SW_LWRX Component 2.1 5.0 6.0 6.0 Table 42. Si4736/37 Firmware, Library, and Component Compatibility Part # Si4736/37-B20 Si4736/37-C40 Firmware 2.0 4.0 Library R9 R10 FMRX Component 2.0 6.0 AM_SW_LWRX Component 2.0 5.0 WBRX Component 1.0 5.0 Table 43. Si4738/39 Firmware, Library, and Component Compatibility Part # Si4738/39-B20 Si4738/39-C40 Firmware 2.0 4.0 Library R9 R10 FMRX Component 2.0 6.0 WBRX Component 1.0 5.0 Table 44. Si4784/85 Firmware, Library, and Component Compatibility Part # Si4784/85-B20 Si4784/85-D50 Firmware 2.0 5.0 Library R8 R11 FMRX Component 2.0 7.0 Table 45. Si4732 Firmware, Library, and Component Compatibility Part # Si4732-A10 Firmware 1.0 Library R11 FMRX Component 7.0 AM_SW_LWRX Component 6.0 238 Rev. 1.2 AN332 7.2.2. Patching Procedure Patching is accomplished by sending a series of commands to the device. These commands are sent in the same manner as any other device commands and can be sent over any of the command busses (2-wire, 3-wire, SPI). The first command that is sent to the device is the POWER_UP command to confirm that the patch is compatible with the internal device library revision. The device moves into the powerup mode, returns the reply, and moves into the powerdown mode. The POWER_UP command is sent to the device again to configure the mode of the device and additionally is used to start the patching process. When applying the patch, the PATCH bit in ARG1 of the POWER_UP command must be set to 1 to begin the patching process. Once the POWER_UP command is sent and the device is placed in patch mode, the patch file can be sent to the device. The patch file typically has a .csg extension. It is formatted into 8 columns, consisting of a leading command (0x15 or 0x16), and 7 arguments. The controlling system must send each line of 8 bytes, wait for a CTS, then send the next set of 8, etc., until the entire patch has been sent. An example showing the first few lines and final line of a patch file is shown below. The patch download mechanism is verified with a checksum embedded in the patch download. If the checksum fails, the part issues an error code, ERR (bit 6 of the one byte reply that is available after each 8-byte transfer), and halts. The part must be reset to recover from this error condition. The following is an example of a patch file. # Copyright 2006 Silicon Laboratories, Inc. # Patch generated 21:09 August 09 2006 # fmtx version 0.0 alpha 0x15,0x00,0x0B,0x1D,0xBB,0x14,0xC4,0xA1 0x16,0x98,0x81,0xD9,0x71,0xED,0x0E,0xAC . . [up to 1979 additional lines] . . 0x15,0x00,0x00,0x00,0x00,0x00,0x49,0xFD A full memory patch requires 15856 bytes of system controller memory, however, most patches require significantly less memory. In 2-wire mode, a full memory patch download requires approximately 500 ms at a 400 kHz clock rate. The following is an example of the commands required to boot the device from powerdown mode using the patch file in the previous example. The device has completed the boot process when the CTS bit is set high after the last byte in the file is transferred and is ready to accept additional commands and proceed with normal operation. Table 46 provides an example of using the POWER_UP command with patching enabled. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. Rev. 1.2 239 AN332 Table 46. Example POWER_UP Command with Patching Enabled Action CMD ARG1 ARG2 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 CMD ARG1 ARG2 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS Data 0x01 0xCF 0x50 0x80 0x0D 0x32 0x30 0x00 0x00 0x41 0x04 0x01 0xE2 0x50 0x80 0x15 0x00 0x0B 0x1D 0xBB 0x14 0xC4 0xA1 0x80 0x16 0x98 0x81 0xD9 0x71 0xED 0x0E 0xAC 0x80 0x15 0x00 0x00 0x00 0x00 0x00 0x49 0xFD 0x80 Description POWER_UP Set to Read Library ID, Enable Interrupts. Set to Analog Line Input. Reply Status. Clear-to-send high. Part Number, HEX (0x0D = Si4713) Firmware Major Rev, ASCII (0x32 = 2) Firmware Minor Rev, ASCII (0x30 = 0) Reserved Reserved Chip Rev, ASCII (0x41 = revA) Library ID, HEX (0x04 = library 4) POWER_UP Set to FM Transmit, set patch enable, enable interrupts. Set to Analog Line Input. Reply Status. Clear-to-send high. Reserved for Patch. Reply Status. Clear-to-send high. Reserved for Patch. Reply Status. Clear-to-send high. . . [up to 1979 additional lines] . Reserved for Patch. Reply Status. Clear-to-send high. 240 Rev. 1.2 AN332 8. Powerdown The procedure for moving the device from powerup to powerdown modes requires writing the POWER_DOWN command. Table 47. Using the POWER_DOWN command Action CMD STATUS Data Description 0x11 POWER_DOWN 0x80 Reply Status. Clear-to-send high. To Power Down the device and remove VDD and VIO (optional): 1. Write TX_TUNE_POWER to the command register to disable the carrier. 2. Set RCLK = 0 (optional). Note that the RCLK buffer is in the VIO supply domain and may therefore be supplied at any time that VIO is supplied. The RCLK must be valid 10 ns before and 10 ns after sending the TX_TUNE_MEASURE, TX_TUNE_FREQ, and TX_TUNE_POWER commands. In addition, the RCLK must be valid at all times when the carrier is enabled for proper AGC operation. The RCLK may be removed or reconfigured at other times. The RCLK is required for proper AGC operation when the carrier is enabled. The RCLK may be removed or reconfigured when the carrier is disabled. 3. Write POWER_DOWN to the command register. Note that all register contents will be lost. 4. Set RST = 0. Note that RST must be held high for 10 ns after the completion of the POWER_DOWN command. 5. Remove VDD (optional). 6. Remove VIO (optional). Note that VIO must not be removed without removing VDD. Unexpected device operation may result. VDD VIO RSTB RCLK Control Bus >10 ns >10 ns TX_TUNE POWER Command POWER_DOWN Command Figure 24. Device Power Down Timing Rev. 1.2 241 AN332 9. Digital Audio Interface The digital audio interface operates in slave mode and supports 3 different audio data formats: I2S Left-Justified DSP Mode In I2S mode, the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order down to the LSB. The Left Channel is transferred first when the DFS is low, and the Right Channel is transferred when the DFS is high. In Left-Justified mode, the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order down to the LSB. The Left Channel is transferred first when the DFS is high, and the Right Channel is transferred when the DFS is low. In DSP mode, the DFS becomes a pulse with a width of 1 DCLK period. The Left Channel is transferred first, followed right away by the Right Channel. There are two options in transferring the digital audio data in DSP mode: the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge. In all audio formats, depending on the word size, DCLK frequency and sample rates, there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word. The number of audio bits can be configured for 8, 16, 20, or 24 bits. (IFALL = 1) INVERTED DCLK (IFALL = 0) DCLK I2S (IMODE = 0000) DFS DIN/DOUT LEFT CHANNEL 1 DCLK 1 DCLK 1 2 3 MSB n-2 n-1 n LSB 1 2 MSB Figure 25. I2S Digital Audio Format RIGHT CHANNEL 3 n-2 n-1 n LSB (IFALL = 1) INVERTED DCLK (IFALL = 0) DCLK Left-Justified (IMODE = 0110) DFS DIN/DOUT LEFT CHANNEL RIGHT CHANNEL 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 26. Left-Justified Digital Audio Format (IFALL = 0) DCLK DFS (IMODE = 1100) DIN/DOUT (MSB at 1st rising edge) DIN/DOUT (IMODE = 1000) (MSB at 2nd rising edge) 1 DCLK 1 MSB LEFT CHANNEL RIGHT CHANNEL 2 3 n-2 n-1 n 1 2 3 n-2 n-1 LEFT CHANNEL LSB MSB RIGHT CHANNEL 1 2 3 n-2 n-1 n 1 2 3 n-2 MSB LSB MSB Figure 27. DSP Digital Audio Format n LSB n-1 n LSB 242 Rev. 1.2 AN332 There are two additional properties each for FM Transmitter and AM/FM/SW/LW Receiver associated with using digital audio input/output. Note that digital audio is not supported in WB Receiver. For FM Transmitter: 1. Property 0x0101: DIGITAL_INPUT_FORMAT 2. Property 0x0103: DIGITAL_INPUT_SAMPLE_RATE For AM/FM/SW/LW Receiver: 1. Property 0x0102: DIGITAL_OUTPUT_FORMAT 2. Property 0x0104: DIGITAL_OUTPUT_SAMPLE_RATE The procedure for using a digital audio is as follow: 1. When the device is powered up, the default value for DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE is 0 (disable digital audio in/out). 2. User then must supply DCLK and DFS prior to setting the DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE property. 3. This procedure can be applied anytime after the chip is powered up. 4. User may also change or disable DCLK/DFS during operation. Prior to changing or disabling DCLK/DFS, user has to set the DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE property to 0. After changing or re-enabling DCLK/DFS, user then can set the sample rate property again. 5. The property DIGITAL_INPUT_FORMAT and DIGITAL_OUTPUT_FORMAT does not have a condition, thus it can be set anywhere after power up. Notes: 1. Failure to provide DCLK and DFS prior to setting the sample rate property may cause the chip to go into an unknown state and user must reset the chip. 2. The DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE is the audio sampling rate (DFS rate) and is valid between 32kHz and 48kHz. The following table is a programming example of how to use digital audio. Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Table 48. Digital Audio Programming Example Data 0x12 0x00 0x01 0x03 or 0x04 0xBB 0x80 0x80 Description Action: POWER UP CHIP (look at respective programming example of power up in digital mode). Action: User can send other commands or properties here. Action: Supply DCLK and DFS. SET_PROPERTY DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE Sample rate = 0xBB80 = 48000Hz Reply Status. Clear-to-send high. Rev. 1.2 243 AN332 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Table 48. Digital Audio Programming Example 0x12 0x00 0x01 0x01 or 0x02 0x00 0x00 0x80 SET_PROPERTY DIGITAL_INPUT_FORMAT or DIGITAL_OUTPUT_FORMAT Mode: I2S, stereo, 16bit, sample on rising edge of DCLK Reply Status. Clear-to-send high. Action: User can send other commands or properties here. 0x12 0x00 0x01 0x03 or 0x04 0x00 0x00 0x80 Action: User needs to change or disable DCLK/DFS. SET_PROPERTY DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE Sample rate = 0 (disable digital audio) Reply Status. Clear-to-send high. Action: User now is allowed to change or disabling DCLK/DFS. 0x12 0x00 0x01 0x03 or 0x04 0xBB 0x80 0x80 Action: DCLK/DFS has been changed or re-enabled. SET_PROPERTY DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE Sample rate = 0xBB80 = 48000Hz Reply Status. Clear-to-send high. Action: User can send other commands or properties here. 244 Rev. 1.2 AN332 10. Timing There are two indicators: CTS (Clear to Send) and STC (Seek/Tune Complete) to indicate that a command has been accepted and execution completed by the part. After sending every command, the CTS bit will be set indicating that the command has been accepted by the part and it is ready to receive the next command. The CTS bit, on most commands, also indicates that the command has completed execution. These commands are: 1. POWER_UP, POWER_DOWN, GET_REV, GET_PROPERTY, GPIO_CTL, GPIO_SET 2. On FM Transmitter component: TX_TUNE_STATUS, TX_ASQ_STATUS, TX_RDS_BUFF, TX_RDS_PS 3. On FM Receive component: FM_TUNE_STATUS, FM_RSQ_STATUS, FM_RDS_STATUS 4. On AM/SW/LW Receive component: AM_TUNE_STATUS, AM_RSQ_STATUS 5. On WB Receive component: WB_TUNE_STATUS, WB_RSQ_STATUS, WB_ASQ_STATUS The CTS timing model is shown in Figure 28 and the timing parameters for each command are shown in Table 49. Control Bus COMMAND GPO2/ INT tCTS tINT Figure 28. CTS Timing Model In addition to CTS bit, there are a few commands (e.g. TX_TUNE_FREQ or FM_TUNE_FREQ) that use the STC bit to indicate that the command has completed execution. It is highly recommended that user waits for the STC bit before sending the next command. When interrupt is not used, user can poll the status of this STC bit by sending the GET_INT_STATUS command until the STC bit has been set before sending the next command. Commands that use STC bit to indicate execution has been completed: 1. On FM Transmitter component: TX_TUNE_FREQ, TX_TUNE_POWER, TX_TUNE_MEASURE 2. On FM Receive component: FM_TUNE_FREQ, FM_SEEK_START 3. On AM/SW/LW Receive component: AM_TUNE_FREQ, AM_SEEK_START 4. On WB Receive component: WB_TUNE_FREQ The CTS and STC timing model is shown in Figure 29 and the timing parameters for each command are shown in Table 49. Rev. 1.2 245 AN332 Control Bus COMMAND GPO2/ INT tCTS tINT tINT tSTC Figure 29. CTS and STC Timing Model The SET_PROPERTY command does not have an indicator telling when the command has completed execution, rather the timing is guaranteed and it is called tCOMP. The CTS and SET_PROPERTY command completion timing model tCOMP is shown in Figure 30 and the timing parameters for each command are shown in Table 49. Control Bus COMMAND GPO2/ INT tCTS tINT tCOMP Figure 30. CTS and SET_PROPERTY Command Complete tCOMP Timing Model 246 Rev. 1.2 AN332 Table 49. Command Timing Parameters for the FM Transmitter Command POWER_UP POWER_DOWN GET_REV GET_PROPERTY GET_INT_STATUS PATCH_ARGS PATCH_DATA TX_ASQ_STATUS TX_RDS_BUFF TX_RDS_PS TX_TUNE_STATUS TX_TUNE_FREQ TX_TUNE_MEASURE TX_TUNE_POWER SET_PROPERTY GPIO_CTL GPIO_SET tCTS 110 ms 300 µs tSTC -- -- -- -- -- -- -- -- -- -- -- 100 ms 100 ms 20 ms -- -- -- tCOMP -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 ms -- -- tINT 1 µs Rev. 1.2 247 AN332 Table 50. Command Timing Parameters for the FM Receiver Command POWER_UP tCTS tSTC tCOMP tINT 110 ms -- -- POWER_DOWN -- -- GET_REV -- -- GET_PROPERTY -- -- GET_INT_STATUS -- -- PATCH_ARGS -- -- PATCH_DATA -- -- FM_RSQ_STATUS FM_RDS_STATUS -- 300 µs -- -- -- 1 µs FM_TUNE_STATUS FM_TUNE_FREQ FM_SEEK_START -- -- 60 ms1 -- 60 ms2 -- SET_PROPERTY -- 10 ms FM_AGC_STATUS -- -- FM_AGC_OVERRIDE -- -- GPIO_CTL -- -- GPIO_SET -- -- Notes: 1. tSTC for FM_TUNE_FREQ / FM_SEEK_START commands is 80 ms on FMRX component 2.0 and earlier. 2. tSTC is seek time per channel. Total seek time depends on bandwidth, channel spacing, and number of channels to next valid channel. Worst case seek time complete for FM_SEEK_START is: F----M-----_----S----E----E----K----_---B---F-A--M--N---_-D---S--_--E-T---E-O---K-P---_---F----RF----ME----Q-_---S-_---SE----PE----AK----C_----BI--N--A--G--N----D----_----B----O----T----T----O----M---- + 1 tSTC for USA FM: 1----0---7---9----0-2----0----8----7---5---0-- + 1 60 ms = 6.2 s 248 Rev. 1.2 AN332 Table 51. Command Timing Parameters for the AM Receiver Command tCTS tSTC tCOMP tINT POWER_UP 110 ms -- -- POWER_DOWN -- -- GET_REV -- -- GET_PROPERTY -- -- GET_INT_STATUS -- -- PATCH_ARGS -- -- PATCH_DATA AM_RSQ_STATUS -- 300 µs -- -- 1 µs -- AM_TUNE_STATUS -- -- AM_TUNE_FREQ 80 ms -- AM_SEEK_START 80 ms* -- SET_PROPERTY -- 10 ms GPIO_CTL -- -- GPIO_SET -- -- *Note: tSTC is seek time per channel. The worst-case seek time per channel is 200 ms.Total seek time depends on bandwidth, channel spacing, and number of channels to next valid channel. Worst case seek time complete for AM_SEEK_START is: A----M------_---S----E----E----K----_---B---A-A---M-N----_-D--S--_--E-T---E-O---K--P--_----F---R-A----ME----Q-_---S_----SE----PE----AK----C_---B-I--N-A---G-N-----D----_---B----O-----T----T---O-----M--- + 1 tSTC for USA AM: 1----7---1----0-1---0-----5---2----0- + 1 200 ms = 24.0 s Rev. 1.2 249 AN332 Table 52. Command Timing Parameters for the WB Receiver Command POWER_UP POWER_DOWN GET_REV GET_PROPERTY GET_INT_STATUS PATCH_ARGS PATCH_DATA WB_RSQ_STATUS WB_ASQ_STATUS WB_TUNE_STATUS WB_TUNE_FREQ SET_PROPERTY WB_AGC_STATUS WB_AGC_OVERRIDE GPIO_CTL GPIO_SET tCTS 110 ms 300 µs tSTC -- -- -- -- -- -- -- -- -- -- 250 ms -- -- -- -- -- tCOMP -- -- -- -- -- -- -- -- -- -- -- 10 ms -- -- -- -- tINT 1 µs Table 53. Command Timing Parameters for the Stereo Audio ADC Mode Command POWER_UP POWER_DOWN GET_REV GET_PROPERTY GET_INT_STATUS AUX_ASRC_START AUX_ASQ_STATUS GPIO_CTL GPIO_SET SET_PROPERTY tCTS 110 ms 300 µs tCOMP -- -- -- -- -- -- -- -- -- 10 ms tINT 1 µs 250 Rev. 1.2 AN332 11. FM Transmitter The FM Transmitter audio signal chain involves Audio Dynamic Range Control, Pre-emphasis and Limiter function. Understanding what these three function blocks do in the signal chain will help user in maximizing the volume out of the FM Transmitter. 11.1. Audio Dynamic Range Control for FM Transmitter The audio dynamic range control can be used to reduce the dynamic range of the audio signal. Audio dynamic range reduction increases the transmit volume by decreasing the peak amplitudes of audio signals and increasing the root mean square content of the audio signal. In other words, it amplifies signals below the threshold by a fixed gain and compresses audio signals above the threshold by the ratio of Threshold/(Gain + Threshold). Figure 31 shows an example transfer function of an audio dynamic range controller with the threshold set at 40 dBFS and a Gain = 20 dB relative to an uncompressed transfer function. Input [dBFS] 90 80 70 60 50 40 30 20 10 0 Compression 2:1 dB 10 Threshold = 40 dB 20 M = 1 No 30 Compression 40 50 Output [dBFS] M = 1 60 Gain = 20 dB 70 80 90 Figure 31. Audio Dynamic Range Transfer Function For input signals below the threshold of 40 dBFS, the output signal is amplified or gained up by 20 dB relative to an uncompressed signal. Audio inputs above the threshold are compressed by a 2 to 1 dB ratio, meaning that every 2 dB increase in audio input level above the threshold results in an audio output increase of 1 dB. In this example, the input dynamic range of 90 dB is reduced to an output dynamic range of 70 dB. The FM Transmitter includes digital audio dynamic range control with programmable gain, threshold, attack rate, and release rate. The total dynamic range reduction is set by the gain value and the audio output compression above the threshold is equal to Threshold/(Gain + Threshold) in dB. The gain specified cannot be larger than the absolute value of the threshold. This feature can also be disabled if audio compression is not desired. Figure 32 shows the time domain characteristics of the audio dynamic range controller. The attack rate sets the speed with which the audio dynamic range controller responds to changes in the input level, and the release rate sets the speed with which the audio dynamic range controller returns to no compression once the audio input level drops below the threshold. When using the audio dynamic range control, care must be taken to configure the device such that the sum of the threshold and gain is zero, or less, as not to distort or overmodulate. Rev. 1.2 251 AN332 Threshold Audio Input Audio Output Attack Release time time Figure 32. Time Domain Characteristics of the Audio Dynamic Range Controller 11.2. Audio Pre-emphasis for FM Transmitter Pre-emphasis and de-emphasis are techniques used to improve the signal-to-noise ratio of an FM stereo broadcast by reducing the effects of high-frequency noise. A pre-emphasis filter is applied to the broadcast to accentuate the high audio frequencies and a de-emphasis filter is used by the receiver to attenuate high frequencies and restore a flat frequency response. Depending on the region, a time constant of either 50 or 75 µs is used. The frequency response of both of these filters is shown in Figure 33. For a 75 µs filter, a 15 kHz tone is amplified by ~17 dB. For a 50 µs filter, a 15 kHz tone is amplified by ~13.5 dB. The pre-emphasis time constant is programmable to off, 50 or 75 µs and is setting the TX_PREEMPHASIS property. When using the pre-emphasis filter, care must be taken to account for amplification at high frequencies as not to distort or overmodulate. Preemphasis Filter Transfer Function 20 75 us 50us 15 dB 10 5 0 0 3 6 9 12 15 Frequency (kHz) Figure 33. Pre-emphasis Filter Response 252 Rev. 1.2 AN332 11.3. Audio Limiter for FM Transmitter A limiter is available to prevent overmodulation by dynamically attenuating the audio level such that the maximum audio deviation does not exceed the level set by the TX_AUDIO_DEVIATION property. The limiter is useful when trying to maximize the audio volume, minimize receiver-generated distortion and prevent overmodulation that may result in violating FCC and ETSI modulation limits. The OVERMOD bit is set by the device when the peak voltage prior to the limiter exceeds the level set by the TX_AUDIO_DEVIATION property. When the limiter is enabled, the OVERMOD bit is an indication that the limiter has dynamically attenuated the audio level. The limiter attack time is instantaneous (within on sample period) and the release time is adjustable with the TX_LIMITER_RELEASE_TIME property. Note: Limiter is enabled by default. 11.4. Maximizing Audio Volume for FM Transmitter The audio input chain is shown in Figure 34: LILEVEL LIATTEN ACEN ACTHRESH ACATTACK ACRELEASE ACGAIN PREEMPH LIMITEN FROM INPUT PGA ADC COMPRESSOR PRE-EMPHASIS LIMITER TO MODULATOR INLEVEL IALDH IALDL Figure 34. Audio Input Chain OVERMOD To maximize audio volume: 1. Set the input line attenuation, line level and audio deviation. The input line attenuation should be set to the lowest setting that is above the maximum level provided by the audio source, either 190, 301, 416 or 636 mVPK. The line level should be set to the maximum source audio level plus headroom. When the limiter is enabled, 2 dB of headroom is recommended. 2 dB of headroom is recommended so that the limiter will not be engaged the entire time it is enabled. When the limiter is disabled and 50 µs pre-emphasis is selected, 13.5 dB of headroom is required. When the limiter is disabled and 75 µs pre-emphasis is selected, 17 dB of headroom is required. Table 54 summarizes these settings: Table 54. Line Input Headroom Pre-emphasis Limiter On (dB) Limiter Off (dB) Off 0 0 50 µs 0 13.5 75 µs 0 17 Rev. 1.2 253 AN332 The audio deviation should be set as high as possible, with the constraint that the sum of the audio, pilot and RDS deviation must be 75 kHz or less. Typical settings are 66.25 kHz audio deviation, 6.75 kHz pilot deviation and 2 kHz RDS deviation. Example 1: An application providing a 150 mVPK input to the device on RIN/LIN would set Line Attenuation = 00, resulting in a maximum permissible input level of 190 mVPK on LIN/RIN and an input resistance of 396 k. With 50 µs pre-emphasis and the limiter disabled, the Line Level would be set to 150 mVPK and the source level would be adjusted down by 13.5 dB to 30 mVPK to compensate for pre-emphasis. With the limiter enabled, the input source can be maintained at 150 mVPK, but the line level should be set at 188 mVPK to give 2 dB headroom. Example 2: An application providing a 1 VPK input to the device on RIN/LIN would set Line Attenuation = 11, resulting in a maximum permissible input level of 636 mVPK on LIN/RIN and an input resistance of 60 k. An external series resistor on LIN and RIN inputs of 58 k would create a resistive voltage divider that would keep the maximum line level on RIN/LIN below 509 mVPK to give a 2 dB headroom. With input signal at 509 mVPK, 75 µs preemphasis and the limiter enabled, the Line Level can be set to 636 mVPK. 2. Enable the audio dynamic range control In general the greater the sum of threshold and gain, the greater the perceived audio volume. The following examples demonstrate minimal and aggressive compression schemes. When using the audio dynamic range control, care must be taken to configure the device such that the sum of the threshold and gain is zero, or less, as not to distort or overmodulate. In practice, the sum of the threshold and gain will be less than zero to minimize the possibility for distortion. Example 1 (minimal compression): SETPROPERTY: TX_ACOMP_THRESHOLD = 40 dBFS SETPROPERTY: TX_ACOMP_ATTACK_TIME = 5 ms SETPROPERTY: TX_ACOMP_RELEASE_TIME = 100 ms SETPROPERTY: TX_ACOMP_GAIN = 15 dB Example 2 (aggressive compression): SETPROPERTY: TX_ACOMP_THRESHOLD = 15 dBFS SETPROPERTY: TX_ACOMP_ATTACK_TIME = 0.5 ms SETPROPERTY: TX_ACOMP_RELEASE_TIME = 1000 ms SETPROPERTY: TX_ACOMP_GAIN = 5 dB 254 Rev. 1.2 AN332 12. Programming Examples This section contains the programming example for each of the function: FM Transmit, FM Receive, AM/SW/LW Receive, and WB Receive. Before each of the example, an overview of how to program the device is shown as a flowchart. Silicon Labs also provides the actual software (example code) and it can be downloaded from mysilabs.com as AN332SW. 12.1. Programming Example for the FM/RDS Transmitter The following flowchart is an overview of how to program the FM/RDS transmitter. RESET CHIP STATE: POWER DOWN Power Up Yes With Patch? No POWER UP with GPO2OEN bit enabled (command 0x01) Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) Library ID Compatible No w/ patch? Yes POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) CHIP STATE: POWER UP Check Chip/FW/Comp rev GET_REV (command 0x10) Contact Silabs For verification Chip/FW/Comp No Rev are correct? Yes Contact Silabs For verification Rev. 1.2 255 AN332 Use all default Yes Settings? No Use Interrupt? Yes No Set INT settings (property 0x0001) Use GPO? Yes No Set RCLK settings (property 0x0201, 0x0202) Set GPO (command 0x80, 0x81) Set FM Transmit Frequency (command 0x30) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33) Set Transmit Power (command 0x31) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33) CHIP STATE: TRANSMITTING 256 Rev. 1.2 Mono/Stereo? Stereo Mono Disable Stereo components (property 0x2100) Set Pilot Deviation & Freq (property 0x2102, 0x2107) Enable Stereo components (property 0x2100) Set Audio Deviation (property 0x2101) Transmit RDS? Yes (Si4711/13/21 only) No Disable RDS components (property 0x2100) Set RDS Deviation (property 0x2103) Enable RDS components (property 0x2100) Set RDS properties (property 0x2C00-0x2C07) Send RDS PS Group Type0 (command 0x36) No Send any other RDS Group Type 1-15? Yes Send RDS Group Type 1-15 (command 0x35) Rev. 1.2 AN332 257 AN332 258 Preemphasis? Yes No Disable Preemphasis (property 0x2106 = 2) Enable Preemphasis (property 0x2106) Compressor? Yes No Disable Compressor (property 0x2200) Enable Compressor Settings (property 0x2200-04) Limiter? Yes No Disable Limiter (property 0x2200) Enable Limiter Settings (property 0x2200, 05) Set FM Transmit Frequency (command 0x30) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33) Set Transmit Power (command 0x31) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set (command 0x33) CHIP STATE: TRANSMITTING Query TX_TUNE_STATUS (command 0x33) Rev. 1.2 Analog/Digital Audio Input? Analog Digital Set audio format (property 0x0101) Clock must be available on DCLK/DFS pin Set ANALOG input settings (0x2104) Enable digital audio by setting DFS sample rate (property 0x0103) Monitor Audio Signal Yes Quality (ASQ)? No Set ASQ settings (property 0x2300 - 0x2304) Query TX_ASQ_STATUS (command 0x34) Optional: Mute or Unmute Audio based on ASQ status (property 0x2105) Want to find an empty channel Yes Using RPS? (Si4712/13/2x only) No Send TX_TUNE_MEASURE (command 0x32) Do host processing On returned RPS value To find empty channels CHIP STATE: Received (Idle) Set FM Transmit Freq and/or Power CHIP STATE: TRANSMITTING AN332 LOOP from start_freq to end_freq until DONE Rev. 1.2 259 AN332 Need to change DCLK/DFS Yes Rate? (digital only) No Disable digital audio by setting DFS sample rate to 0 (property 0x0103) Change DCLK/DFS rate or Disable DCLK/DFS DCLK/DFS has been changed or re-enabled Enable digital audio by setting DFS sample rate (property 0x0103) Repeat any of the instructions above after POWER_UP state To change settings Change Chip Function Yes To FM Receive? (Si472x only) No No TRANSMISSION DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Send POWER_UP For FM Receive (command 0x01) CHIP STATE: POWER UP (FM Receive) Go back to the very first POWER DOWN state to POWER UP the chip in FM Transmit Look at FM Receive Flowchart Table 55 provides an example of programming for the FM/RDS Transmitter. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). For SET_PROPERTY commands, the property (PROP) and property data (PROPD) are indicated. The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. Note that in some cases the default properties may be acceptable and no modification is necessary. Refer to Section "5. Commands and Properties" on page 7 for a full description of each command and property. Note: If hardware interrupts are required, the GPO2OEN flag (0x40 ARG1) must be set in the POWER_UP command. 260 Rev. 1.2 AN332 Action CMD ARG1 ARG2 STATUS CMD ARG1 ARG2 STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Table 55. Programming Example for the FM/RDS Transmitter Data 0x01 0xC2 0x0F 0x80 0x01 0xC2 0x50 0x80 0x12 0x00 0x21 0x04 0x21 0x5E 0x80 0x10 0x00 0x80 0x0D 0x32 0x30 0xE4 0xD6 0x32 0x30 0x41 0x12 0x00 0x00 0x01 0x00 0xC1 0x80 Description Action: To power up in analog mode, go to "Powerup in Analog Mode" (bypass "Powerup in Digital Mode"). Powerup in Digital Mode POWER_UP (See Table 28 for patching procedure) Set to FM Transmit. Enable interrupts. Set to Digital Audio Input Reply Status. Clear-to-send high. Action: Go to "Configuration" (bypass "Powerup in Analog Mode" section). Powerup in Analog Mode POWER_UP (See Table 28 for patching procedure) Set to FM Transmit. Enable interrupts. Set to Analog Line Input Reply Status. Clear-to-send high. SET_PROPERTY TX_LINE_INPUT_LEVEL Input Range = 419mVPK, 74k Max peak input level = 350mVPK = 0x15E Reply Status. Clear-to-send high Configuration GET_REV Reply Status. Clear-to-send high. Part Number, HEX (0x0D = Si4713) Firmware Major Rev, ASCII (0x32 = 2) Firmware Minor Rev, ASCII (0x3 = 0) Patch ID MSB, example only Patch ID LSB, example only Component Firmware Major Rev, ASCII (0x32 = 2) Component Firmware Minor Rev, ASCII (0x30 = 0) Chip Rev, ASCII (0x41 = revA) SET_PROPERTY GPO_IEN Set STCIEN, ERRIEN, CTSIEN Reply Status. Clear-to-send high. Rev. 1.2 261 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 0x12 0x00 0x02 0x02 0x01 0x90 0x80 0x12 0x00 0x21 0x05 0x00 0x00 0x80 0x12 0x00 0x21 0x06 0x00 0x01 0x80 0x12 0x00 0x21 0x07 0x4A 0x38 0x80 0x12 0x00 0x21 0x01 0x1A 0xA9 0x80 SET_PROPERTY Description REFCLK_FREQ REFCLK = 32500 Hz Reply Status. Clear-to-send high. SET_PROPERTY RCLK_PRESCALE Divide by 400 (example RCLK = 13 MHz, REFCLK = 32500 Hz) Reply Status. Clear-to-send high. SET_PROPERTY TX_LINE_INPUT_LEVEL_MUTE Sets Left and Right channel mute. Reply Status. Clear-to-send high. SET_PROPERTY TX_PREEMPHASIS 50 µs Reply Status. Clear-to-send high. SET_PROPERTY TX_PILOT_FREQUENCY Sets the pilot or tone generator frequency. Reply Status. Clear-to-send high. SET_PROPERTY TX_AUDIO_DEVIATION 68.25 kHz = 6825d = 0x1AA9 Reply Status. Clear-to-send high. 262 Rev. 1.2 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 ARG3 ARG4 STATUS CMD ARG1 ARG2 ARG3 STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x21 0x02 0x02 0xA3 0x80 0x31 0x00 0x00 0x73 0x00 0x80 0x30 0x00 0x27 0x7E 0x80 0x14 0x81 0x33 0x01 0x80 0x00 0x27 0x7E 0x00 0x73 0xAB 0x00 0x12 0x00 0x21 0x00 0x00 0x03 0x80 SET_PROPERTY Description TX_PILOT_DEVIATION 6.75 kHz = 675d = 0x2A3 Reply Status. Clear-to-send high. Tuning TX_TUNE_POWER Set transmit voltage to 115 dBµV = 115d = 0x73 Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. TX_TUNE_FREQ Set frequency to 101.1 MHz = 10110d = 0x277E Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. TX_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Frequency = 0x277E = 10110d = 101.1 MHz Transmit voltage = 0x73 = 115d = 115 dBµV Tuning capacitor = 191 (range = 0191) Received noise level = 0x00 SET_PROPERTY TX_COMPONENT_ENABLE Enable (Stereo) LMR and Pilot Reply Status. Clear-to-send high. Action: In analog mode, go to "Audio Dynamic Range Control (Compressor) and Limiter" (bypass "Input Settings in Digital Mode"). Input Settings in Digital Mode Action: Ensure that DCLK and DFS are already supplied. Rev. 1.2 263 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data Description 0x12 0x00 0x01 0x03 0xBB 0x80 0x80 0x12 0x00 0x01 0x01 0x00 0x00 0x80 SET_PROPERTY DIGITAL_INPUT_SAMPLE_RATE Sample rate = 48000 Hz = 0xBB80 Reply Status. Clear-to-send high. SET_PROPERTY DIGITAL_INPUT_FORMAT Mode: I2S, stereo, 16bit, sample on rising edge of DCLK. Reply Status. Clear-to-send high. Action: The rest of the programming is the same as analog. Audio Dynamic Range Control (Compressor) and Limiter 0x12 0x00 0x22 0x01 0xFF 0xD8 0x80 0x12 0x00 0x22 0x04 0x00 0x0F 0x80 0x12 0x00 0x22 0x03 0x00 0x04 0x80 0x12 0x00 0x22 0x02 0x00 0x02 0x80 SET_PROPERTY TX_ACOMP_THRESHOLD Threshold = 40 dBFS = 0xFFD8 Reply Status. Clear-to-send high. SET_PROPERTY TX_ACOMP_GAIN Gain = 15 dB = 0xF Reply Status. Clear-to-send high. SET_PROPERTY TX_ACOMP_RELEASE_TIME Release time = 1000 ms = 4 Reply Status. Clear-to-send high. SET_PROPERTY TX_ACOMP_ATTACK_TIME Attack time = 1.5 ms = 2 Reply Status. Clear-to-send high. 264 Rev. 1.2 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x22 0x00 0x00 0x03 0x80 0x12 0x00 0x22 0x05 0x00 0x0D 0x80 0x12 0x00 0x23 0x01 0x00 0xCE 0x80 0x12 0x00 0x23 0x02 0x27 0x10 0x80 0x12 0x00 0x23 0x03 0x00 0xEC 0x80 0x12 0x00 0x23 0x04 0x13 0x88 0x80 SET_PROPERTY Description TX_ACOMP_ENABLE Enable the limiter and compressor. Reply Status. Clear-to-send high. SET_PROPERTY TX_LIMITER_RELEASE_TIME Sets the limiter release time to 13 (39.38 ms) Reply Status. Clear-to-send high. SET_PROPERTY TX_ASQ_LOW_LEVEL 50 dB = 0x00CE Reply Status. Clear-to-send high. SET_PROPERTY TX_ASQ_DURATION_LOW 10000 ms = 0x2710 Reply Status. Clear-to-send high. SET_PROPERTY TX_ASQ_HIGH_LEVEL 20 dB = 0x00EC Reply Status. Clear-to-send high. SET_PROPERTY TX_ASQ_DURATION_HIGH 5000 ms = 0x1388 Reply Status. Clear-to-send high. Rev. 1.2 265 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 CMD ARG1 ARG2 ARG3 ARG4 STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 CMD ARG1 ARG2 ARG3 ARG4 STATUS Data Description 0x12 0x00 0x23 0x00 0x00 0x07 0x80 0x14 0x82 SET_PROPERTY TX_ASQ_INTERRUPT_SELECT Enable overmodulation, high and low thresholds. Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. ASQINT = 1. Note: Allow sufficient time after configuring audio thresholds before checking status. This example assumes no audio input. 0x34 0x01 0x80 0x01 0x27 0x7E 0xC9 TX_ASQ_STATUS Clear ASQINT Reply Status. Clear-to-send high. Low flag set. Read Frequency (MSB) Read Frequency (LSB) Input Level (dBFS) = 0xC9 = 55 dB Received Noise Level (Si4712/13/20/21 Only) 0x32 0x00 0x27 0x7E 0x00 0x80 0x14 0x81 0x33 0x01 0x80 0x00 0x27 0x7E 0x00 0x00 0xAB 0x32 TX_TUNE_MEASURE Set frequency to 101.1 MHz = 10110d = 0x277E Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. TX_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Frequency = 0x277E = 10110d = 101.1 MHz Transmit Voltage = 0x00 = 0 dBµV (off) Tuning capacitor = 191 (range = 0191) Received Noise Level = 0x32 = 50d = 50 dBµV Tuning 0x31 0x00 0x00 0x73 0x00 0x80 TX_TUNE_POWER Set transmit voltage to 115 dBµV = 115d = 0x73 Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. 266 Rev. 1.2 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 ARG3 STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x30 0x00 0x27 0x7E 0x80 0x14 0x81 0x33 0x01 0x80 0x00 0x27 0x7E 0x00 0x73 0xAB 0x32 0x12 0x00 0x21 0x01 0x19 0xE1 0x80 0x12 0x00 0x21 0x03 0x00 0xC8 0x80 0x12 0x00 0x2C 0x00 0x00 0x01 0x80 0x12 0x00 0x2C 0x01 0x40 0xA7 0x80 TX_TUNE_FREQ Description Set frequency to 101.1 MHz = 10110d = 0x277E Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. TX_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Frequency = 0x277E = 10110d = 101.1 MHz Transmit voltage = 0x73 = 115d = 115 dBµV Tuning capacitor = 191 (range = 0191) Received noise level = 0x32 (last value) RDS (Si4711/13/21 Only) SET_PROPERTY TX_AUDIO_DEVIATION 66.25 kHz = 6625d = 0x19E1 Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_DEVIATION (Si4711/13/21 Only) 2 kHz = 200d = 0xC8 Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_INTERRUPT_SOURCE (Si4711/13/21 Only) RDS FIFO MT Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_PI (Si4711/13/21 Only) Sets the RDS PI Code Reply Status. Clear-to-send high. Rev. 1.2 267 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x2C 0x02 0x00 0x03 0x80 0x12 0x00 0x2C 0x03 0x10 0x08 0x80 0x12 0x00 0x2C 0x04 0x00 0x03 0x80 0x12 0x00 0x2C 0x05 0x00 0x03 0x80 0x12 0x00 0x2C 0x06 0xE1 0x02 0x80 0x12 0x00 0x2C 0x07 0x00 0x04 0x80 SET_PROPERTY Description TX_RDS_PS_MIX (Si4711/13/21 Only) Sets 50% mix of group 1A (program service) and other buffer/FIFO groups. Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_PS_MISC (Default) (Si4711/13/21 Only) Sets RDSD0 (stereo) and RDSMS (music). Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_PS_REPEAT_COUNT (Si4711/13/21 Only) Sets program service repeat count to 3. Reply Status. Clear-to-send high. SET PROPERTY TX_RDS_PS_MESSAGE_COUNT (Si4711/13/21 Only) Sets PS message count to 3. Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_PS_AF (Si4711/13/21 Only) Sets alternative frequency to 87.7 MHz. Reply Status. Clear-to-send high. SET_PROPERTY TX_RDS_FIFO_SIZE (Si4711/13/21 Only) Sets FIFO size to 3 blocks (value must be one larger than fifo size). Reply Status. Clear-to-send high. 268 Rev. 1.2 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS Data 0x36 0x00 0x53 0x49 0x4C 0x41 0x80 0x36 0x01 0x42 0x53 0x20 0x20 0x80 0x36 0x02 0x53 0x49 0x34 0x37 0x80 0x36 0x03 0x31 0x58 0x20 0x20 0x80 0x36 0x04 0x52 0x44 0x53 0x20 0x80 0x36 0x05 0x44 0x45 0x4D 0x4F 0x80 Description TX_RDS_PS (Si4711/13/21 Only) PSID = 0 Set text "SILA" Complete text is "SILABS SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_PS (Si4711/13/21 Only) PSID = 1 Set text "BS" Complete text is "SILABS SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_PS (Si4711/13/21 Only) PSID = 2 Set text "SI47" Complete text is "SILABS SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_PS (Si4711/13/21 Only) PSID = 3 Set text "1X" Complete text is "SILABS SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_PS (Si4711/13/21 Only) PSID = 4 Set text "RDS" Complete text is "SILABS SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_PS (Si4711/13/21 Only) PSID = 5 Set text "DEMO" Complete text is "SILABS SI471X RDS DEMO" Reply Status. Clear-to-send high. Rev. 1.2 269 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS Data 0x35 0x06 0x20 0x00 0x53 0x49 0x4C 0x49 0x80 0x35 0x04 0x20 0x01 0x43 0x4F 0x4E 0x20 0x80 0x35 0x04 0x20 0x02 0x4C 0x41 0x42 0x4F 0x80 0x35 0x04 0x20 0x03 0x52 0x41 0x54 0x4F 0x80 0x35 0x04 0x20 0x04 0x52 0x49 0x45 0x53 0x80 Description TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF and MTBUFF Set Group 2A, Text Location 0 Set text "SILI" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 1 Set text "CON" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 2 Set text "LABO" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 3 Set text "RATO" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 4 Set text "RIES" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. 270 Rev. 1.2 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS Data 0x35 0x04 0x20 0x05 0x20 0x53 0x49 0x34 0x80 0x35 0x04 0x20 0x06 0x37 0x31 0x58 0x20 0x80 0x35 0x04 0x20 0x07 0x52 0x44 0x53 0x20 0x80 0x35 0x04 0x20 0x08 0x44 0x45 0x4D 0x4F 0x80 0x35 0x84 0x40 0x01 0xA7 0x0B 0x2D 0x6C 0x80 Description TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 5 Set text "SI4" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 6 Set text "71X" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 7 Set text "RDS" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set LDBUFF Set Group 2A, Text Location 8 Set text "DEMO" Complete text is "SILICON LABORATORIES SI471X RDS DEMO" Reply Status. Clear-to-send high. TX_RDS_BUFF (Si4711/13/21 Only) Set FIFO and LDBUFF Set Group 4A (real time clock) Set time Sunday 2/18/2007 12:53 (GMT -6:00) Reply Status. Clear-to-send high. Rev. 1.2 271 AN332 Table 55. Programming Example for the FM/RDS Transmitter (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 CMD STATUS Data 0x12 0x00 0x21 0x00 0x00 0x07 0x80 0x14 0x84 0x35 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x5E 0x1E 0x03 0x00 0x11 0x80 SET_PROPERTY Description TX_COMPONENT_ENABLE (Si4711/13/21 Only) Enable (Stereo) LMR, Pilot and RDS. Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. RDSINT = 1 TX_RDS_BUFF (Si4711/13/21 Only) Clear RDSINT Reply Status. Clear-to-send high. No FIFO Overflow. Circular buffer available = 94 Circular buffer used = 30 FIFO available = 0 FIFO used = 3 POWER_DOWN Reply Status. Clear-to-send high. The device sets the CTS bit (and optional interrupt) to indicate that it is ready to accept the next command. The CTS bit also indicates that the POWER_UP, GET_REV, POWER_DOWN, GET_PROPERTY, GET_INT_STATUS, and TX_TUNE_STATUS commands have completed execution. When performing a TX_TUNE_FREQ, TX_TUNE_POWER, or TX_TUNE_MEASURE CTS will indicate that the device is ready to accept the next command even though the operation is not complete. GET_INT_STATUS or hardware interrupts should be used to query for the STC bit to be set prior to performing other commands. Use TX_TUNE_STATUS to clear the STC bit after it has been set. 272 Rev. 1.2 12.2. Programming Example for the FM/RDS Receiver The following is a flowchart showing the overview of how to program the FM/RDS Receiver. RESET AN332 CHIP STATE: POWER DOWN Power Up Yes With Patch? No POWER UP with GPO2OEN bit enabled (command 0x01) Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) Library ID Compatible No w/ patch? Yes POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) CHIP STATE: POWER UP Check Chip/FW/Comp rev GET_REV (command 0x10) Contact Silabs For verification C hip/FW /C om p No Rev are correct? Yes Contact Silabs For verification Rev. 1.2 273 AN332 Use all default Yes Settings? No Use Interrupt? Yes No Use GPO? Yes No Set RCLK settings (property 0x0201, 0x0202) Set INT settings (property 0x0001) Set GPO (command 0x80, 0x81) Digital output mode? (Si4705/06/21/31/32/35/ Yes 37/39/41/43/45/84/85 only) No Set audio format (property 0x0102) Clock must be available on DCLK/DFS pin Enable digital audio by setting DFS sample rate (property 0x0104) LPI pin for embedded (short) Which pin is used For the antenna? (Si4704/05/06 only) antenna Set FM_ANTENNA_INPUT (property 0x1107 = 1) FMI pin for headphone (long) antenna Set FM_ANTENNA_INPUT (property 0x1107 = 0) Set FM Tune Frequency (command 0x20) Use GET_INT_STATUS (command 0x14) or hardware interrupts Until STC bit is set Call FM_TUNE_STATUS With INTACK bit set (command 0x22) CHIP STATE: RECEIVING FM 274 Rev. 1.2 S e t D ee m p h asis (property 0x1100 ) S et M on o /S te re o B le nd se ttin gs (property 0x1800 0x180 B ) S e t S o ft M ute S e ttin g s (property 0 x1301 0x1303 ) S e t V o lu m e (property 0x4000 ) S et M ute/U nm ute (property 0x4001 ) S et M ax Tune E rror (property 0x1108 ) S et FM Tune Frequency (com m and 0x20) U se G E T _IN T_S TA TU S (com m and 0x14) or h ard w a re in te rrup ts U n til S T C b it is se t C all F M _ T U N E _S T A T U S W ith IN T A C K b it se t (com m and 0x22) C H IP S TA TE : R E C E IV IN G F M Q uery FM _TU N E_STA TU S (com m and 0x22) N o t a p p lic a b le to S i4 7 4 9 Rev. 1.2 AN332 275 AN332 Receive RDS? Yes (Si4706/31/32/35/41/43/ 45/49 only) No Disable RDS in FM_RDS_CONFIG (property 0x1502) Set FM_RDS_INT_SOURCE (property 0x1500) Set FM_RDS_INT_FIFO_COUNT (property 0x1501) Set FM_RDS_CONFIG & enable RDS (property 0x1502) Received RDS Interrupt or poll RDSINT from GET_INT_STATUS Read RDS data with FM_RDS_STATUS (command 0x24) Process RDS data on the host LOOP until RDS FIFO is empty 276 Rev. 1.2 AN332 M onitor R eceived S ignal Q uality (R S Q )? Yes No S et R S Q settings (property 0x1200 - 0x1207) Q uery FM _R SQ _STATU S (com m and 0x23) O ptional: D o som ething based on FM _R SQ _STATU S SEEK next V alid channel? No Yes C H IP STA TE: R EC EIVIN G FM S et S E E K settings (property 0x1400-1404) Send FM_SEEK_START (com m and 0x21) SCAN FM Band F or valid channels? No Yes C H IP STA TE: R EC EIVIN G FM S et S E E K settings (property 0x1400-1404) Send FM _SEEK_START (com m and 0x21) U se G ET _IN T_STA TU S (com m and 0x14) or hardw are interrupts until S T C bit is set C all F M _T U N E _S T A TU S w ith IN T A C K bit set (com m and 0x22) S tore valid channels In the H ost LO O P until reaches end of FM band or back to the original Channel Rev. 1.2 277 AN332 Repeat any of the instructions above after POWER_UP state To change settings Need to change DCLK/DFS Rate? Yes (digital only) No Disable digital audio by setting DFS sample rate to 0 (property 0x0104) Change DCLK/DFS rate or Disable DCLK/DFS DCLK/DFS has been changed or re-enabled Change Chip Function to AM/SW/LW/WB Receive (Si4740/41/42/ 43/44/45) ? Yes No No RECEIVE FM DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Enable digital audio by setting DFS sample rate (property 0x0104) Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Send POWER_UP For FM Transmit or AM/SW/ LW Receive or WB Receive (command 0x01) CHIP STATE: POWER UP (FM Transmit or AM/SW/LW Receive or WB Receive) Go back to the very first POWER DOWN state to POWER UP the chip in FM Receive Look at FM Transmit Or AM/SW/LW Receive Or WB Receive Flowchart 278 Rev. 1.2 AN332 Table 56 provides an example for the FM/RDS Receiver. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). For SET_PROPERTY commands, the property (PROP) and property data (PROPD) are indicated. The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. In some cases the default properties may be acceptable and no modification is necessary. Refer to Section "5. Commands and Properties" for a full description of each command and property. Table 56. Programming Example for the FM/RDS Receiver Action Data Powerup in Digital Mode CMD ARG1 ARG2 STATUS 0x01 0xC0 0xB0 0x80 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS 0x12 0x00 0x01 0x04 0xBB 0x80 0x80 0x12 0x00 0x01 0x02 0x00 0x00 0x80 Powerup in Analog Mode CMD ARG1 ARG2 STATUS 0x01 0xC0 0x05 0x80 Configuration CMD STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 0x10 0x80 0x1F 0x32 0x30 0x85 0xC5 0x32 0x30 0x42 Description POWER_UP Set to FM Receive. Enable interrupts. Set to Digital Audio Output Reply Status. Clear-to-send high. Action: Ensure that DCLK and DFS are already supplied SET_PROPERTY DIGITAL_OUTPUT_SAMPLE_RATE Sample rate = 48000 Hz = 0xBB80 Reply Status. Clear-to-send high. SET_PROPERTY DIGITAL_OUTPUT_FORMAT Mode: I2S, stereo, 16bit, sample on rising edge of DCLK. Reply Status. Clear-to-send high. Action: Go to Configuration (bypass "Powerup in analog mode" section). The rest of the programming is the same as analog. POWER_UP Set to FM Receive. Enable interrupts. Set to Analog Audio Output Reply Status. Clear-to-send high. GET_REV Reply Status. Clear-to-send high. Part Number, HEX (0x1F = 31 dec. = Si4731) Firmware Major Rev, ASCII (0x32 = 2) Firmware Minor Rev, ASCII (0x30 = 0) Patch ID MSB, example only Patch ID LSB, example only Component Firmware Major Rev, ASCII (0x32 = 2) Component Firmware Minor Rev, ASCII (0x30 = 0) Chip Rev, ASCII (0x42 = revB) Rev. 1.2 279 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x00 0x01 0x00 0xC9 0x80 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 0x12 0x00 0x02 0x02 0x01 0x90 0x80 0x12 0x00 0x40 0x00 0x00 0x3F 0x80 0x12 0x00 0x11 0x00 0x00 0x01 0x80 0x12 0x00 0x40 0x01 0x00 0x00 0x80 SET_PROPERTY Description GPO_IEN Set STCIEN, ERRIEN, CTSIEN, RSQIEN Reply Status. Clear-to-send high. SET_PROPERTY REFCLK_FREQ REFCLK = 32500 Hz Reply Status. Clear-to-send high. SET_PROPERTY REFCLK_PRESCALE Divide by 400 (example RCLK = 13 MHz, REFCLK = 32500 Hz) Reply Status. Clear-to-send high. SET_PROPERTY RX_VOLUME Output Volume = 63 Reply Status. Clear-to-send high. SET_PROPERTY FM_DEEMPHASIS 50 µs Reply Status. Clear-to-send high. SET_PROPERTY RX_HARD_MUTE Enable L and R audio outputs Reply Status. Clear-to-send high. 280 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x18 0x00 0x00 0x31 0x80 0x12 0x00 0x18 0x01 0x00 0x1E 0x80 0x12 0x00 0x11 0x08 0x00 0x28 0x80 0x12 0x00 0x12 0x00 0x00 0x8F 0x80 0x12 0x00 0x12 0x01 0x00 0x1E 0x80 0x12 0x00 0x12 0x02 0x00 0x06 0x80 SET_PROPERTY Description FM_BLEND_RSSI_STEREO_THRESHOLD Threshold = 49dB µV = 0x0031 Reply Status. Clear-to-send high. SET_PROPERTY FM_BLEND_RSSI_MONO_THRESHOLD Threshold = 30 dBµV = 0x001E Reply Status. Clear-to-send high. SET_PROPERTY FM_MAX_TUNE_ERROR Threshold = 40 kHz = 0x0028 Reply Status. Clear-to-send high. SET_PROPERTY FM_RSQ_INT_SOURCE Enable blend, SNR high, SNR low, RSSI high and RSSI low interrupts. Reply Status. Clear-to-send high. SET_PROPERTY FM_RSQ_SNR_HI_THRESHOLD Threshold = 30 dB = 0x001E Reply Status. Clear-to-send high.Clear-to-send high. SET_PROPERTY FM_RSQ_SNR_LO_THRESHOLD Threshold = 6 dB = 0x0006 Reply Status. Clear-to-send high. Rev. 1.2 281 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x12 0x03 0x00 0x32 0x80 0x12 0x00 0x12 0x04 0x00 0x18 0x80 0x12 0x00 0x12 0x07 0x00 0xB2 0x80 0x12 0x00 0x13 0x02 0x00 0x0A 0x80 0x12 0x00 0x13 0x03 0x00 0x06 0x80 0x12 0x00 0x14 0x00 0x22 0x6A 0x80 SET_PROPERTY Description FM_RSQ_RSSI_HI_THRESHOLD Threshold = 50 dBµV = 0x0032 Reply Status. Clear-to-send high. SET_PROPERTY FM_RSQ_RSSI_LO_THRESHOLD Threshold = 24 dBµV = 0x0018 Reply Status. Clear-to-send high. SET_PROPERTY FM_RSQ_BLEND_THRESHOLD Pilot = 1, Threshold = 50% = 0x0032 Reply Status. Clear-to-send high. SET_PROPERTY FM_SOFT_MUTE_MAX_ATTENUATION Attenuation = 10 dB = 0x000A Reply Status. Clear-to-send high. SET_PROPERTY FM_SOFT_MUTE_SNR_THRESHOLD Threshold = 6 dB = 0x0006 Reply Status. Clear-to-send high. SET_PROPERTY FM_SEEK_BAND_BOTTOM Bottom Freq = 88.1 MHz = 0x226A Reply Status. Clear-to-send high. 282 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 ARG3 ARG4 STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 Data 0x12 0x00 0x14 0x01 0x2A 0x26 0x80 0x12 0x00 0x14 0x02 0x00 0x14 0x80 0x12 0x00 0x14 0x03 0x00 0x06 0x80 0x12 0x00 0x14 0x04 0x00 0x14 0x80 0x20 0x00 0x27 0xF6 0x00 0x80 0x14 0x81 0x22 0x01 0x80 0x01 0x27 0xF6 0x2D 0x33 0x00 0x00 SET_PROPERTY Description FM_SEEK_BAND_TOP Top Freq = 107.9 MHz = 0x2A26 Reply Status. Clear-to-send high. SET_PROPERTY FM_SEEK_FREQ_SPACING Freq Spacing = 200 kHz = 0x0014 Reply Status. Clear-to-send high. SET_PROPERTY FM_SEEK_TUNE_SNR_THRESHOLD Threshold = 6 dB = 0x0006 Reply Status. Clear-to-send high. SET_PROPERTY FM_SEEK_TUNE_RSSI_THRESHOLD Threshold = 20 dBµV = 0x0014 Reply Status. Clear-to-send high. FM_TUNE_FREQ Set frequency to 102.3 MHz = 0x27F6 Set antenna tuning capacitor to auto. Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. FM_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Valid Frequency. Frequency = 0x27F6 = 102.3 MHz RSSI = 45 dBµV SNR = 51 dB Antenna tuning capacitor = 0 (range = 0191) Rev. 1.2 283 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action Data Description CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 CMD ARG1 STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 0x23 0x01 0x80 0x00 0x01 0xD9 0x2D 0x33 0x00 0x00 0x21 0x0C 0x80 0x14 0x81 0x22 0x01 0x80 0x01 0x28 0x6E 0x22 0x2C 0x00 0x00 FM_RSQ_STATUS Clear RSQINT Reply Status. Clear-to-send high. No blend, SNR high, low, RSSI high or low interrupts. Soft mute is not engaged, no AFC rail, valid frequency. Pilot presence, 89% blend RSSI = 45 dBµV SNR = 51 dB Freq offset = 0 kHz FM_SEEK_START Seek Up and Wrap. Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. FM_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Valid Frequency. Frequency = 0x286E = 103.5 MHz RSSI = 34 dBµV SNR = 44 dB Antenna tuning capacitor = 0 (range = 0191) RDS (Si4706/31/32/35/41/43/45/49 Only) CMD ARG1 ARG2(PROP) ARG3(PROP) ARG4(PROPD) ARG5(PROPD) STATUS CMD ARG1 ARG2(PROP) ARG3(PROP) ARG4(PROPD) ARG5(PROPD) STATUS 0x12 0x00 0x15 0x00 0x00 0x01 0x80 0x12 0x00 0x15 0x01 0x00 0x04 0x80 SET_PROPERTY FM_RDS_INT_SOURCE Enable RDSRECV interrupt (set RDSINT bit when RDS has filled the FIFO by the amount set on FM_RDS_INTERRUPT_FIFO_COUNT Reply Status. Clear-to-send high SET_PROPERTY FM_RDS_INT_FIFO_COUNT Set the minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set Reply Status. Clear-to-send high 284 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 ARG2(PROP) ARG3(PROP) ARG4(PROPD) ARG5(PROPD) STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x12 0x00 0x15 0x02 0xEF 0x01 0x80 0x14 0x84 0x24 0x01 0x84 0x01 0x01 0x17 0x40 0xA7 0x20 0x00 0x53 0x49 0x4C 0x49 0x00 0x24 0x01 0x80 0x01 0x01 0x16 0x40 0xA7 0x00 0x0C 0xE1 0x02 0x53 0x49 0x00 SET_PROPERTY Description FM_RDS_CONFIG Set Block Error A,B,C,D to 3,2,3,3 Enable RDS Reply Status. Clear-to-send high GET_INT_STATUS Reply Status. Clear-to-send high. RDSINT = 1 FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. RDS interrupt (RDSINT) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x17 = 23. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2000 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0000b = 0 (char 1,2,3,4) Block C: 0x5349 SI Block D: 0x4C49 LI BLE: 0 (No Error) Current RT: "SILI" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x16 = 22. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 00b = 0 (char 1,2) Block C (ignored) Block D: 0x5349 SI BLE: 0 (No Error) Current PS: "SI" Complete Scrolling PS: "SILABS RDS DEMO" Rev. 1.2 285 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x15 0x40 0xA7 0x20 0x01 0x43 0x4F 0x4E 0x20 0x00 0x24 0x01 0x80 0x01 0x01 0x15 0x40 0xA7 0x00 0x09 0xE1 0x02 0x4C 0x41 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x15 = 21. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2001 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0001b = 1 (char 5,6,7,8) Block C: 0x434F CO Block D: 0x4E20 N BLE: 0 (No Error) Current RT: "SILICON" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x15 = 21 (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 01b = 1 (char 3,4) Block C (ignored) Block D: 0x4C41 LA BLE: 0 (No Error) Current PS: "SILA" Complete Scrolling PS: "SILABS RDS DEMO" 286 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x14 0x40 0xA7 0x20 0x02 0x4C 0x41 0x42 0x4F 0x00 0x24 0x01 0x80 0x01 0x01 0x14 0x40 0xA7 0x00 0x0A 0xE1 0x02 0x42 0x53 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x14 = 20. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2002 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0002b = 2 (char 9,10,11,12) Block C: 0x4C41 LA Block D: 0x424F BO BLE: 0 (No Error) Current RT: "SILICON LABO" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x14 = 20. (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 10b = 2 (char 5,6) Block C (ignored) Block D: 0x4253 BS BLE: 0 (No Error) Current PS: "SILABS" Complete Scrolling PS: "SILABS RDS DEMO" Rev. 1.2 287 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x13 0x40 0xA7 0x20 0x03 0x52 0x41 0x54 0x4F 0x00 0x24 0x01 0x80 0x01 0x01 0x13 0x40 0xA7 0x00 0x0B 0xE1 0x02 0x20 0x20 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x13 = 19. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2003 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0003b = 3 (char 13,14,15,16) Block C: 0x5241 RA Block D: 0x544F TO BLE: 0 (No Error) Current RT: "SILICON LABORATO" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x13 = 19. (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 11b = 3 (char 7,8) Block C (ignored) Block D: 0x2020 " " BLE: 0 (No Error) Current PS: "SILABS" Complete Scrolling PS: "SILABS RDS DEMO" 288 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x12 0x40 0xA7 0x20 0x04 0x52 0x49 0x45 0x53 0x00 0x24 0x01 0x80 0x01 0x01 0x12 0x40 0xA7 0x00 0x0C 0xE1 0x02 0x52 0x44 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x12 = 18. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2004 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0004b = 4 (char 17,18,19,20) Block C: 0x5249 RI Block D: 0x4553 ES BLE: 0 (No Error) Current RT: "SILICON LABORATORIES" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x12 = 18. (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 00b = 0 (char 1,2) Block C (ignored) Block D: 0x5244 RD BLE: 0 (No Error) Current PS: "RDLABS Scrolling PS: "SILABS RDS DEMO" Rev. 1.2 289 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x11 0x40 0xA7 0x20 0x05 0x20 0x53 0x49 0x34 0x00 0x24 0x01 0x80 0x01 0x01 0x10 0x40 0xA7 0x00 0x09 0xE1 0x02 0x53 0x20 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x11 = 17. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2005 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0005b = 5 (char 21,22,23,24) Block C: 0x2053 S Block D: 0x4934 I4 BLE: 0 (No Error) Current RT: "SILICON LABORATORIES SI4" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x10 = 16. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 01b = 1 (char 3,4) Block C (ignored) Block D: 0x5320 S BLE: 0 (No Error) Current PS: "RDS BS" Complete Scrolling PS: "SILABS RDS DEMO" 290 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x0F 0x40 0xA7 0x20 0x06 0x37 0x31 0x58 0x20 0x00 0x24 0x01 0x80 0x01 0x01 0x0E 0x40 0xA7 0x00 0x0A 0xE1 0x02 0x44 0x45 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0F = 15. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2006 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0006b = 6 (char 25, 26, 27, 28) Block C: 0x3731 71 Block D: 0x5820 x BLE: 0 (No Error) Current RT: "SILICON LABORATORIES SI471x " FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0E = 14. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000A Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 10b = 2 (char 5, 6) Block C (ignored) Block D: 0x4445 DE BLE: 0 (No Error) Current PS: "RDS DE" Complete Scrolling PS: "SILABS RDS DEMO" Rev. 1.2 291 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x0E 0x40 0xA7 0x20 0x07 0x52 0x44 0x53 0x20 0x00 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x00 0x0B 0xE1 0x02 0x4D 0x4F 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0E = 14. (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2007 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0007b = 7 (char 29,30,31,32) Block C: 0x5244 RD Block D: 0x5320 S BLE: 0 (No Error) Current RT: "SILICON LABORATORIES SI471x RDS" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0D = 13. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 11b = 3 (char 7,8) Block C (ignored) Block D: 0x4D4F MO BLE: 0 (No Error) Current PS: "RDS DEMO" Complete Scrolling PS: "SILABS RDS DEMO" 292 Rev. 1.2 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 +STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 Data 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x20 0x08 0x44 0x45 0x4D 0x4F 0x00 0x24 0x01 0x80 0x01 0x01 0x0C 0x40 0xA7 0x00 0x0C 0xE1 0x02 0x53 0x49 0x00 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0D = 13. (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2008 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0008b = 8 (char 33,34,35,36) Block C: 0x4445 DE Block D: 0x4D4F MO BLE: 0 (No Error) Current RT: "SILICON LABORATORIES SI471x RDS DEMO" FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0C = 12. Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x000C Group Type: 0A (Program Service PS) PTY: 00000b (Undefined) Address code: 00b = 0 (char 1,2) Block C (ignored) Block D: 0x5349 SI BLE: 0 (No Error) Current PS: "SIS_DEMO" Complete Scrolling PS: "SILABS RDS DEMO" Rev. 1.2 293 AN332 Table 56. Programming Example for the FM/RDS Receiver (Continued) Action CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD STATUS Data 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x20 0x09 0x0D 0x00 0x00 0x00 0x00 0x11 0x80 Description FM_RDS_STATUS Clear RDS interrupt. Reply Status. Clear-to-send (CTS) high. Seek/Tune Complete (STCINT) high. Interrupt source: RDS received. RDS Synchronized. No lost data. RDS FIFO Used: 0x0C = 12. (FIFO receives another group while querying) Block A: 0x40A7 PI Code: 0x40A7 (KSLB). Block B: 0x2009 Group Type: 2A (Radio Text RT) PTY: 00000b (Undefined) Address code: 0009b = 9 (char 37,38,39,40) Block C: 0x0D00 `RET' `NUL' (end of RT) Block D: 0x0000 `NUL' `NUL' BLE: 0 (No Error) Current RT: "SILICON LABORATORIES SI471x RDS DEMO" - continue sending FM_RDS_STATUS until FIFO empty POWER_DOWN Reply Status. Clear-to-send high. The device sets the CTS bit (and optional interrupt) to indicate that it is ready to accept the next command. The CTS bit also indicates that the POWER_UP, GET_REV, POWER_DOWN, GET_PROPERTY, GET_INT_STATUS, FM_TUNE_STATUS, and FM_RSQ_STATUS commands have completed execution. When performing a FM_TUNE_FREQ or FM_SEEK_START CTS will indicate that the device is ready to accept the next command even though the operation is not complete. GET_INT_STATUS or hardware interrupts should be used to query for the STC bit to be set prior to performing other commands. Use FM_TUNE_STATUS to clear the STC bit after it has been set. 294 Rev. 1.2 12.3. Programming Example for the AM/LW/SW Receiver The following flowchart shows an overview of how to program the AM/LW/SW receiver. RESET CHIP STATE: POWER DOWN AN332 Power Up Yes With Patch? No POWER UP with GPO2OEN bit enabled (command 0x01) Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) Library ID Compatible No w/ patch? Yes POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) CHIP STATE: POWER UP Check Chip/FW/Comp rev GET_REV (command 0x10) Contact Silabs For verification Chip/FW/Comp No Rev are correct? Yes Contact Silabs For verification Rev. 1.2 295 AN332 Use all default Yes Settings? No Use Interrupt? Yes No Set INT settings (property 0x0001) Use GPO? Yes No Set RCLK settings (property 0x0201, 0x0202) Set GPO (command 0x80, 0x81) Digital output mode? Yes (Si4731/32/35/37/41/43/ 45 only) No Set DIGITAL output settings (property 0x0102, 0x0104) Set AM Tune Frequency (command 0x40) Use GET_INT_STATUS (command 0x14) or hardware interrupts Until STC bit is set Call AM_TUNE_STATUS With INTACK bit set (command 0x42) CHIP STATE: RECEIVING AM / SW / LW 296 Rev. 1.2 S et A M _D E E M P H A S IS (property 0x3100 ) S et A M _C H A N N E L _ F ILT E R (property 0x3102 ) S e t S o ft M u te S e ttin g s (property 0 x3301- 3303 ) S e t V o lu m e (property 0x4000 ) S et M u te /U n m u te (property 0x4001 ) S et A M Tune Frequency (com m and 0x40) U se G E T _ IN T _ S T A T U S (com m and 0 x14 ) or h a rd w a re in te rru p ts U n til S T C b it is se t C a ll A M _ T U N E _ S T A T U S W ith IN T A C K b it se t (com m and 0x42) C H IP S T A T E : R E C E IV IN G A M / S W / L W Q uery A M _TU N E _S TA TU S (com m and 0x42) Rev. 1.2 AN332 297 AN332 298 Monitor Received Yes Signal Quality (RSQ)? No Set RSQ settings (property 0x3200 - 0x3204) Query AM_RSQ_STATUS (command 0x43) Optional: Do something based on AM_RSQ_STATUS SEEK next Yes Valid channel? No Set SEEK settings (property 0x3400-3404) SEND AM_SEEK_START (COMMAND 0X41) CHIP STATE: RECEIVING AM / SW / LW SCAN AM/SW/LW Band Yes For valid channels? No Set SEEK settings (property 0x3400-3404) Send AM_SEEK_START (command 0X41) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call AM_TUNE_STATUS With INTACK bit set (command 0x42) Store valid channels In the Host CHIP STATE: RECEIVING AM / SW / LW LOOP until reaches end of AM band or back to the original channel Rev. 1.2 AN332 Repeat any of the instructions above after POWER_UP state To change settings Change Chip Function To FM Receive or Yes Weather Band? No No RECEIVE AM / SW / LW DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Go back to the very first POWER DOWN state to POWER UP the chip in AM / SW / LW Receive Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Send POWER_UP For FM Receive or Weather Band (command 0x01) CHIP STATE: POWER UP (FM Receive or Weather Band) Look at FM Receive or Weather Band Flowchart Rev. 1.2 299 AN332 Table 57 provides an example of programming the AM/LW/SW receiver. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). For SET_PROPERTY commands, the property (PROP) and property data (PROPD) are indicated. The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. Note that in some cases the default properties may be acceptable and no modification is necessary. Refer to Section "5. Commands and Properties" for a full description of each command and property. Table 57. Programming Example for the AM/LW/SW Receiver Action Data Powerup in Digital Mode CMD ARG1 ARG2 STATUS 0x01 0xC1 0xB0 0x80 Description POWER_UP Set to AM/LW/SW Receive. Enable interrupts. Set to Digital Audio Output Reply Status. Clear-to-send high. CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS 0x12 0x00 0x01 0x04 0xBB 0x80 0x80 0x12 0x00 0x01 0x02 0x00 0x00 0x80 Powerup in Analog Mode CMD ARG1 ARG2 STATUS 0x01 0xC1 0x05 0x80 Configuration Action: Ensure that DCLK and DFS are already supplied SET_PROPERTY DIGITAL_OUTPUT_SAMPLE_RATE Sample rate = 48000 Hz = 0xBB80 Reply Status. Clear-to-send high. SET_PROPERTY DIGITAL_OUTPUT_FORMAT Mode: I2S, stereo, 16bit, sample on rising edge of DCLK. Reply Status. Clear-to-send high. Action: Go to Configuration (bypass "Powerup in analog mode" section). The rest of the programming is the same as analog. POWER_UP Set to AM/LW/SW Receive. Enable interrupts. Set to Analog Audio Output Reply Status. Clear-to-send high. 300 Rev. 1.2 AN332 Table 57. Programming Example for the AM/LW/SW Receiver (Continued) Action CMD STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x10 0x80 0x1F 0x32 0x30 0x85 0xC5 0x32 0x30 0x42 0x12 0x00 0x00 0x01 0x00 0xC1 0x80 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 0x12 0x00 0x02 0x02 0x01 0x90 0x80 0x12 0x00 0x40 0x00 0x00 0x3F 0x80 0x12 0x00 0x31 0x02 0x00 0x01 0x80 Description GET_REV Reply Status. Clear-to-send high. Part Number, HEX (0x1F = 31 dec. = Si4731) Firmware Major Rev, ASCII (0x32 = 2) Firmware Minor Rev, ASCII (0x30 = 0) Patch ID MSB, example only Patch ID LSB, example only Component Firmware Major Rev, ASCII (0x32 = 2) Component Firmware Minor Rev, ASCII (0x30 = 0) Chip Rev, ASCII (0x42 = revB) SET_PROPERTY GPO_IEN Set STCIEN, ERRIEN, CTSIEN Reply Status. Clear-to-send high. SET_PROPERTY REFCLK_FREQ REFCLK = 32500 Hz Reply Status. Clear-to-send high. SET_PROPERTY REFCLK_PRESCALE Divide by 400 (example RCLK = 13 MHz, REFCLK = 32500 Hz) Reply Status. Clear-to-send high. SET_PROPERTY RX_VOLUME Output Volume = 63 Reply Status. Clear-to-send high. SET_PROPERTY AM_CHANNEL_FILTER 4 kHz Bandwidth = 0x01 Reply Status. Clear-to-send high. Rev. 1.2 301 AN332 Table 57. Programming Example for the AM/LW/SW Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x31 0x00 0x00 0x01 0x80 0x12 0x00 0x32 0x00 0x00 0x08 0x80 0x12 0x00 0x32 0x01 0x00 0x0A 0x80 0x12 0x00 0x32 0x02 0x00 0x0A 0x80 0x12 0x00 0x32 0x03 0x00 0x1E 0x80 0x12 0x00 0x32 0x04 0x00 0x0A 0x80 SET_PROPERTY Description AM_DEEMPHASIS 50 µs Reply Status. Clear-to-send high. SET_PROPERTY AM_RSQ_INTERRUPTS Interrupt when SNR higher than RSQ SNR threshold Reply Status. Clear-to-send high. SET_PROPERTY AM_RSQ_SNR_HIGH_THRESHOLD 10 dB = 0x0A Reply Status. Clear-to-send high. SET_PROPERTY AM_RSQ_SNR_LOW_THRESHOLD 10 dB = 0x0A Reply Status. Clear-to-send high. SET_PROPERTY AM_RSQ_RSSI_HIGH_THRESHOLD 30 dBµV = 0x1E Reply Status. Clear-to-send high. SET_PROPERTY AM_RSQ_RSSI_LOW_THRESHOLD 10 dBµV = 0x0A Reply Status. Clear-to-send high. 302 Rev. 1.2 AN332 Table 57. Programming Example for the AM/LW/SW Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Data 0x12 0x00 0x33 0x02 0x00 0x0A 0x80 0x12 0x00 0x33 0x03 0x00 0x09 0x80 0x12 0x00 0x34 0x00 0x02 0x08 0x80 0x12 0x00 0x34 0x01 0x06 0xAE 0x80 0x12 0x00 0x34 0x02 0x00 0x0A 0x80 0x12 0x00 0x34 0x03 0x00 0x0B 0x80 SET_PROPERTY Description AM_SOFT_MUTE_MAX_ATTENUATION 10 dB attenuation = 0x0A Reply Status. Clear-to-send high. SET_PROPERTY AM_SOFT_MUTE_SNR_THRESHOLD 9 dB = 0x09 Reply Status. Clear-to-send high. SET_PROPERTY AM_SEEK_BAND_BOTTOM 520 kHz = 0x0208 Reply Status. Clear-to-send high. SET_PROPERTY AM_SEEK_BAND_TOP 1710 kHz = 0x06AE Reply Status. Clear-to-send high. SET_PROPERTY AM_SEEK_FREQ_SPACING 10 kHz = 0x000A Reply Status. Clear-to-send high. SET_PROPERTY AM_SEEK_SNR_THRESHOLD 0x000B = 11 dB Reply Status. Clear-to-send high. Rev. 1.2 303 AN332 Table 57. Programming Example for the AM/LW/SW Receiver (Continued) Action CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS CMD STATUS CMD ARG1 STATUS CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 CMD STATUS Data 0x12 0x00 0x34 0x04 0x00 0x2A 0x80 0x40 0x00 0x03 0xE8 0x00 0x00 0x80 0x14 0x81 0x41 0x0C 0x80 0x14 0x81 0x42 0x01 0x80 0x01 0x03 0xE8 0x2A 0x1A 0x0D 0x95 0x43 0x01 0x80 0x00 0x01 0x00 0x2A 0x1A 0x11 0x80 SET_PROPERTY Description AM_SEEK_RSSI_THRESHOLD 0x002A = 42 dBµV Reply Status. Clear-to-send high. AM_TUNE_FREQ Set frequency to 1000 kHz = 0x03E8 Automatically select tuning capacitor Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. AM_SEEK_START Seek up and wrap at band boundary Reply Status. Clear-to-send high. GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. AM_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Channel is valid, AFC is not railed, and seek did not wrap at AM band boundary Frequency = 0x03E8 = 1000 kHz RSSI = 0x2A = 42d = 42 dBµV SNR = 0x1A = 26d = 26 dB Value the antenna tuning capacitor is set to. 0x0D95 = 3477 dec. AM_RSQ_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. No SNR high, low, RSSI high, or low interrupts. Channel is valid, soft mute is not activated, and AFC is not railed RSSI = 0x2A = 42d = 42 dBµV SNR = 0x1A = 26d = 26 dB POWER_DOWN Reply Status. Clear-to-send high. 304 Rev. 1.2 AN332 The device sets the CTS bit (and optional interrupt) to indicate that it is ready to accept the next command. The CTS bit also indicates that the POWER_UP, GET_REV, POWER_DOWN, GET_PROPERTY, GET_INT_STATUS, AM_TUNE_STATUS, and AM_RSQ_STATUS commands have completed execution. When performing a AM_TUNE_FREQ or AM_SEEK_START CTS will indicate that the device is ready to accept the next command even though the operation is not complete. GET_INT_STATUS or hardware interrupts should be used to query for the STC bit to be set prior to performing other commands. Use AM_TUNE_STATUS to clear the STC bit after it has been set. 12.4. Programming Example for the WB/SAME Receiver The following flowchart is an overview of how to program the WB (Weather Band) Receiver. RESET CHIP STATE: POWER DOWN Power Up Yes With Patch? No POWER UP with GPO2OEN bit enabled (command 0x01) Check Chip Library ID POWER_UP with FUNC=15 (command 0x01) Library ID Compatible No w/ patch? Yes POWER_UP with Patch and GPO2OEN bits enabled (command 0x01) Send Patch Data (command 0x15, 0x16) CHIP STATE: POWER UP Check Chip/FW/Comp rev GET_REV (command 0x10) Contact Silabs For verification Chip/FW/Comp No Rev are correct? Yes Contact Silabs For verification Rev. 1.2 305 AN332 Use all default Yes Settings? No Use Interrupt? Yes No Use GPO? Yes No Set RCLK settings (property 0x0201, 0x0202) Set INT settings (property 0x0001) Set GPO (command 0x80, 0x81) Set WB Tune Frequency (command 0x50) Use GET_INT_STATUS (command 0x14) or hardware interrupts until STC bit is set Call WB_TUNE_STATUS with INTACK bit set (command 0x52) CHIP STATE: RECEIVING WB 306 Rev. 1.2 S et W B M ax T une E rror (property 0x5108 ) S e t W B V a lid S N R T h re s h o ld (property 0x5403 ) S e t W B V a lid R S S I T h re s h o ld (property 0x5404 ) S e t V o lu m e (property 0x4000 ) S et M ute/U nm ute (property 0x4001 ) S et W B T une F requency (com m and 0x50) U se G E T _IN T _S T A T U S (com m and 0x14) or h a rd w a re in te rru p ts u n til S T C b it is s e t C a ll W B _ T U N E _ S T A T U S w ith IN T A C K b it s e t (com m and 0x52) C H IP S T A T E : R E C E IV IN G W B Q uery W B _TU N E _S TA TU S (com m and 0x52) AN332 Rev. 1.2 307 AN332 Monitor Received Yes Signal Quality (RSQ)? No Set RSQ settings (property 0x5200 - 0x5204) Query WB_RSQ_STATUS (command 0x53) Optional: Do something based on WB_RSQ_STATUS Monitor Alert Tone Yes (ASQ)? No Set ASQ int source (property 0x5600) Query WB_ASQ_STATUS (command 0x55) Optional: Do something based on WB_ASQ_STATUS Monitor SAME? Yes No Set SAME int source (property 0x5500) Query WB_SAME_STATUS (command 0x54) No Comlete Message Received? Yes Optional: Do something based on WB_SAME_STATUS 308 Rev. 1.2 AN332 Repeat any of the instructions above after POWER_UP state To change settings Change Chip Function Yes To AM or FM? No No RECEIVE WB DONE? Yes Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Go back to the very first POWER DOWN state to POWER UP the chip in WB Receive Send POWER_DOWN (command 0x11) CHIP STATE: POWER DOWN Send POWER_UP For AM or FM Receive (command 0x01) CHIP STATE: POWER UP (AM or FM Receive) Look at AM or FM Receive Flowchart Rev. 1.2 309 AN332 For detailed information on SAME processing, please refer to the following flow chart: Start Set GPO_IEN for SAME and ALERT Tone Interrupts = 0x06 Configure SAME Interrupts for HDR_RDY, EOM_DET, and PRE_DET WB_SAME_INTERRUPT Source = 0x0B Tune to WB Channel WB_TUNE_FREQ Disable Timer Set HDR_COUNT = 0 Check Interrupt Status GET_INT_STATUS SAME_INT or ASQ_INT = 1? No Yes No TIMER > 6 SEC? Yes Clear SAME buffer, Disable timer, and SET_HDR.COUNT = 0 Call WB_SAME_STATUS INT_ACK = 1 EOM_DET = 1? No Yes PRE_DET = 1? Yes No HDR_RDY = 1 at this point Message Length /8 INT TYPE? SAME_INT ASQ_INT Increment HDR_COUNT Get Message and Process WB_SAME_STATUS No HDR_COUNT = 3? Yes Reset Timer 310 Rev. 1.2 AN332 Table 58 provides an example for the WB Receiver. The table is broken into three columns. The first column lists the action taking place: command (CMD), argument (ARG), status (STATUS) or response (RESP). For SET_PROPERTY commands, the property (PROP) and property data (PROPD) are indicated. The second column lists the data byte or bytes in hexadecimal that are being sent or received. An arrow preceding the data indicates data being sent from the device to the system controller. The third column describes the action. Note that in some cases the default properties may be acceptable and no modification is necessary. Refer to Section "5. Commands and Properties" for a full description of each command and property. Action CMD ARG1 ARG2 STATUS CMD STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS Table 58. Programming Example for the WB/SAME Receiver Data 0x01 0xC3 0x05 0x80 0x10 0x80 0x25 0x30 0x41 0x13 0x36 0x30 0x41 0x42 0x12 0x00 0x00 0x01 0x00 0xC7 0x80 0x12 0x00 0x02 0x01 0x80 0x00 0x80 0x12 0x00 0x02 0x02 0x00 0x01 0x80 Description POWER_UP Set to weatherband receive. Enable interrupts. Set to Analog Out. Reply Status. Clear-to-send high. GET_REV Reply Status. Clear-to-send high. Part Number, HEX (0x25 = 37 dec. = Si4737) Firmware Major Rev, ASCII (0x30 = 0) Firmware Minor Rev, ASCII (0x41 = A) Patch ID MSB, example only Patch ID LSB, example only Component Firmware Major Rev, ASCII (0x30 = 0) Component Firmware Minor Rev, ASCII (0x41 = A) Chip Rev, ASCII (0x42 = revB) SET_PROPERTY GPO_IEN Set STCIEN, ERRIEN, CTSIEN, ASQIEN, SAMEIEN Reply Status. Clear-to-send high. SET_PROPERTY REFCLK_FREQ REFCLK = 32768 Hz Reply Status. Clear-to-send high. SET_PROPERTY REFCLK_PRESCALE Divide by 1 Reply Status. Clear-to-send high. Rev. 1.2 311 AN332 Table 58. Programming Example for the WB/SAME Receiver (Continued) CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 (PROP) ARG3 (PROP) ARG4 (PROPD) ARG5 (PROPD) STATUS CMD ARG1 ARG2 ARG3 STATUS 0x12 0x00 0x40 0x00 0x00 0x3F 0x80 0x12 0x00 0x40 0x01 0x00 0x00 0x80 0x12 0x00 0x54 0x03 0x00 0x06 0x80 0x12 0x00 0x54 0x04 0x00 0x14 0x80 0x12 0x00 0x56 0x00 0x00 0x01 0x80 0x12 0x00 0x55 0x00 0x00 0x01 0x80 0x50 0x00 0xFD 0xC0 0x80 SET_PROPERTY RX_VOLUME Output Volume = 63 Reply Status. Clear-to-send high. SET_PROPERTY RX_HARD_MUTE Enable L and R audio outputs Reply Status. Clear-to-send high. SET_PROPERTY WB_VALID_SNR_THRESHOLD Threshold = 06 dB = 0x0006 Reply Status. Clear-to-send high. SET_PROPERTY WB_VALID_RSSI_THRESHOLD Threshold = 20 dBµV = 0x0014 Reply Status. Clear-to-send high. SET_PROPERTY WB_ASQ_INTERRUPT_SOURCE Interrupt when alert tone is present. Reply Status. Clear-to-send high. SET PROPERTY WB_SAME_INTERRUPT_SOURCE (Si4707 only) Interrupt when header is ready. Reply Status. Clear-to-send high. WB_TUNE_FREQ Set frequency to 162.4 MHz = 0xFDC0 Frequency is set in units of 2500 Hz. Reply Status. Clear-to-send high. 312 Rev. 1.2 AN332 CMD STATUS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 CMD ARG1 STATUS RESP1 CMD STATUS CMD ARG1 ARG2 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 CMD STATUS Table 58. Programming Example for the WB/SAME Receiver (Continued) 0x14 0x81 0x52 0x01 0x80 0x01 0xFD 0xC0 0x22 0x17 0x55 0x01 0x80 0x02 0x14 0x84 0x54 0x01 0x00 0x80 0x0F 0x00 0xFE 0xFF 0x2D 0x57 0x58 0x52 0x2D 0x56 0x4F 0x57 0x11 0x80 GET_INT_STATUS Reply Status. Clear-to-send high. STCINT = 1. WB_TUNE_STATUS Clear STC interrupt. Reply Status. Clear-to-send high. Valid Frequency. Frequency = 0xFDC0 = 162.4 MHz RSSI = 34 dBµV SNR = 23 dB WB_ASQ_STATUS Reply Status. Clear-to-send high. Alert tone is not present. SAME (Si4707 Only) GET_INT_STATUS Reply Status. Clear-to-send high. SAMEINT = 1. WB_SAME_STATUS Clear SAME interrupt. Begin reading message from byte 0. Reply Status. Clear-to-send high. Message flags set. State = End of message. Message length 254 bytes. Data confidence level = high. Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Note: This command should be called repeatedly with the readaddr[7:0] incremented by 8 each time until all 254 bytes (in this example) are returned. The buffer should then be cleared as described in the WB_SAME_STATUS:CLRBUF bit description. POWER_DOWN Reply Status. Clear-to-send high. The device sets the CTS bit (and optional interrupt) to indicate that it is ready to accept the next command. The CTS bit also indicates that the POWER_UP, GET_REV, POWER_DOWN, GET_PROPERTY, GET_INT_STATUS, WB_TUNE_STATUS, WB_ASQ_STATUS, and WB_RSQ_STATUS commands have completed execution. When performing a WB_TUNE_FREQ CTS will indicate that the device is ready to accept the next command even though the operation is not complete. GET_INT_STATUS or hardware interrupts should be used to query for the STC bit to be set prior to performing other commands. Use WB_TUNE_STATUS to clear the STC bit after it has been set. Rev. 1.2 313 AN332 APPENDIX A--COMPARISON OF THE Si4704/05/3X-B20, Si4704/05/3X-C40, AND Si4704/05/3X-D60 This appendix describes the configuration, command, and property differences between silicon and firmware revisions of the Si4704/05/3x-B20, Si4704/05-3x-C40, and Si4704/05/3x-D60 devices. Each revision is referred to by its die revision and firmware revision suffix according to Table 1. For a more detailed configuration reference, consult "AN332: Si47xx Programming Guide". Table 59. Die Revision and Firmware Revision Table Part Number Si4704-B20-GM/GU Si4705-B20-GM/GU Si4730-B20-GM/GU Si4731-B20-GM/GU Si4734-B20-GM/GU Si4735-B20-GM/GU Si4704-C40-GM/GU Si4705-C40-GM/GU Si4730-C40-GM/GU Si4731-C40-GM/GU Si4734-C40-GM/GU Si4735-C40-GM/GU Si4704-D60-GM/GU Si4705-D60-GM/GU Si4730-D60-GM/GU Si4731-D60-GM/GU Si4734-D60-GM/GU Si4735-D60-GM/GU Function FM Receiver FM RDS Receiver AM/FM Receiver AM/FM RDS Receiver AM/SW/FM Receiver AM/SW/FM RDS Receiver FM Receiver FM RDS Receiver AM/FM Receiver AM/FM RDS Receiver AM/SW/FM Receiver AM/SW/FM RDS Receiver FM Receiver FM RDS Receiver AM/FM Receiver AM/FM RDS Receiver AM/SW/FM Receiver AM/SW/FM RDS Receiver Die Revision B B B B B B C C C C C C D D D D D D Firmware Die Revision + Firmware Revision Revision Suffix 20 -B20 20 -B20 20 -B20 20 -B20 20 -B20 20 -B20 40 -C40 40 -C40 40 -C40 40 -C40 40 -C40 40 -C40 60 -D60 60 -D60 60 -D60 60 -D60 60 -D60 60 -D60 314 Rev. 1.2 AN332 Each of the following subsections describes the differences between revisions for groups of properties and/or commands. Each property is listed as PROPERTY_NAME (number) = default (supported revisions). Hexadecimal values are immediately preceded by "0x"; all other numeric values are decimal. AM, FM, and WB errata on -B20 have been addressed in -C40 and/or -D60 devices. The -D60 is the most recent revision and offers advanced features not available in the -C40 and -B20 revisions. FM Properties And Commands The properties and commands in this section are related to FM mode. FM Mode Max Tune Error (0x110x Properties) FM_MODE_MAX_TUNE_ERROR (0x1108) = 30 (-B20), 20 (-C40, -D60) Maximum tune error in kHz is stored in property 0x1108. It has a default setting of 30 kHz in -B20, and a default setting of 20 kHz in -C40 and -D60. It should be noted that 20 kHz has been recommended for best performance even on -B20 devices through AN332. FM RSQ Interrupt Configuration (0x120x Properties) FM_RSQ_MULTIPATH_HIGH_THRESHOLD (0x1205 ) = 127 (-D60) FM_RSQ_MULTIPATH_LOW_THRESHOLD (0x1206 ) = 0 (-D60) Properties 0x1205 and 0x1206 are only available on -D60 parts. FM Soft Mute Configuration (0x130x Properties) FM_SOFT_MUTE_SLOPE (0x1301) = 2 (-C40, -D60) The target soft mute target attenuation - up to a set maximum attenuation level - is calculated as the difference between the soft mute threshold and the received SNR multiplied by a property value called the FM_SOFT_MUTE_SLOPE. In -C40 and -D60, the default slope is 2 dB/dB. In in -B20, the slope is not configurable through a property, but is also 2 dB/dB. Stereo Blend Thresholds (0x110x, 0x180x Properties) FM_BLEND_STEREO_THRESHOLD (0x1105) = 49 (-B20, -C40) FM_BLEND_MONO_THRESHOLD (0x1106) = 30 (-B20, -C40) FM_BLEND_RSSI_STEREO_THRESHOLD (0x1800) = 49 (-D60) FM_BLEND_RSSI_MONO_THRESHOLD (0x1801) = 30 (-D60) FM_BLEND_RSSI_ATTACK_RATE (0x1802) = 4000 (-D60) FM_BLEND_RSSI_RELEASE_RATE (0x1803) = 400 (-D60) FM_BLEND_SNR_STEREO_THRESHOLD (0x1804) = 27 (-D60) FM_BLEND_SNR_MONO_THRESHOLD (0x1805) = 14 (-D60) FM_BLEND_SNR_ATTACK_RATE (0x1806) = 4000 (-D60) FM_BLEND_SNR_RELEASE_RATE (0x1807) = 400 (-D60) FM_BLEND_MULTIPATH_STEREO_THRESHOLD (0x1808) = 20 (-D60) Rev. 1.2 315 AN332 FM_BLEND_MULTIPATH_MONO_THRESHOLD (0x1809) = 60 (-D60) FM_BLEND_MULTIPATH_ATTACK_RATE (0x180A) = 4000 (-D60) FM_BLEND_MULTIPATH_RELEASE_RATE (0x180B) = 40 (-D60) In -B20 and -C40, FM stereo blend is only determined by RSSI based on blend thresholds set in 0x1105 and 0x1106. In -D60 devices, a series of advanced blend properties have been added to improve the user experience under dynamic signal conditions. To accommodate for this change, RSSI based threshold properties were relocated respectively to properties 0x1800 and 0x1801. 0x1800 and 0x1801 have the same default values as 0x1105 and 0x1106. Additional advanced blend features include stereo blending based on SNR and multipath thresholds. For each set of thresholds, separate blend attack (into mono) and release (into stereo) rates may be set. Each of the factors is independently evaluated, and any may trigger a blend into mono at its given threshold and rate. To remove any of the advanced blend factors from consideration; set the corresponding blend thresholds to min value of 0 for SNR based blend (0x1804/0x1805), and set the corresponding blend thresholds to max value of 100 for multipath based blend (0x1808/0x1809). FM Commands Some parameters and returned values are only applicable to -D60 parts. These are: multipath indicator returned by the FM_TUNE_STATUS command and the MULTIPATH_DETECT_HIGH and MULTIPATH_DETECT_LOW parameters of the FM_RSQ_STATUS command. In -C40 and -D60 devices, the RDSSYNC bit of the response to an FM_RDS_STATUS command may be incorrectly set. A patch is available only for -D60 devices. 316 Rev. 1.2 AN332 AM Properties The properties and commands in this section are related to AM mode. AM Mode Configuration (0x310x Properties) AM_MODE_AVC_MAX_GAIN (0x3103) = 0x1543 (-C40, -D60) AM_MODE_AFC_SW_PULL_IN_RANGE (0x3104) = 8695 (-C40, -D60) AM_MODE_AFC_SW_LOCK_IN_RANGE (0x3105) = 11765 (-C40, -D60) AM_MODE_AVC_MAX_GAIN is available in -C40 and -D60 devices with a default max gain of 16 dB. In -B20, the AVC gain is set at maximum and not available through a property. To make -C40 or -D60 behave as -B20, set AM_MODE_MAX_GAIN to 0x7800. AM shortwave AFC range properties are available in -C40 and -D60 devices (supported by Si4734/35 devices only). The default values of these properties provide similar behavior to the behavior of -B20 devices. However, in -B20 devices, these properties are not available through the programming API. AM Soft Mute Configuration (0x330x Properties) AM_SOFT_MUTE_SLOPE (0x3301) = 2 (-B20), 1 (-C40, -D60) AM_SOFT_MUTE_MAX_ATTENUATION (0x3302) = 16 (-B20), 8 (-C40, -D60) AM_SOFT_MUTE_SNR_THRESHOLD (0x3303) = 10 (-B20), 8 (-C40, -D60) Settings for Audio Soft Mute Soft mute is active when SNR falls below the given AM_SOFT_MUTE_SNR_THRESHOLD. When active, the output audio will be decreased at a set rate until the target soft mute attenuation is achieved. In -B20 devices the threshold is 10 dB, whereas in -C40 and -D60 devices it is 8 dB. The target soft mute target attenuation - up to a set maximum attenuation level - is calculated as the difference between the soft mute threshold and the received SNR multiplied by a scalar value called the soft mute slope. The default value of this property is 1 dB/dB in -C40 and -D60. In -B20, the value used is 2 dB/dB. The maximum soft mute attenuation level is 10 dB in -B20. In -C40 and -D60 devices, the maximum level can be set by a property AM_SOFT_MUTE_MAXIMUM_ATTENUATION, which has a default value of 8 dB. The soft mute default changes in -C40 and -D60 have been made to improve weak signal listening experience. Rev. 1.2 317 AN332 APPENDIX B--Si4704/05/3X-B20/-C40/-D60 COMPATIBILITY CHECKLIST This appendix describes the configuration differences between hardware revisions of Si4704/05/3x devices. It describes how to achieve backwards compatibility between systems designed for Si4704/05/3x-B20, -C40, and D60 device hardware revisions. It is not intended as a complete reference to Si4704/05/3x configuration. For an indepth configuration reference, consult "AN332: Si47xx Programming Guide". In this appendix, each revision is referred to by its die revision and firmware revision suffix according to the following table. Table 60. Die Revision and Firmware Revision Table Part Number Si4704-B20-GM/GU Si4705-B20-GM/GU Si4730-B20-GM/GU Si4731-B20-GM/GU Si4734-B20-GM/GU Si4735-B20-GM/GU Si4704-C40-GM/GU Si4705-C40-GM/GU Si4730-C40-GM/GU Si4731-C40-GM/GU Si4734-C40-GM/GU Si4735-C40-GM/GU Si4704-D60-GM/GU Si4705-D60-GM/GU Si4730-D60-GM/GU Si4731-D60-GM/GU Si4734-D60-GM/GU Si4735-D60-GM/GU Function FM Receiver FM RDS Receiver AM/FM Receiver AM/FM RDS Receiver AM/SW/FM Receiver AM/SW/FM RDS Receiver FM Receiver FM RDS Receiver AM/FM Receiver AM/FM RDS Receiver AM/SW/FM Receiver AM/SW/FM RDS Receiver FM Receiver FM RDS Receiver AM/FM Receiver AM/FM RDS Receiver AM/SW/FM Receiver AM/SW/FM RDS Receiver Die Revision B B B B B B C C C C C C D D D D D D Firmware Revision 20 20 20 20 20 20 40 40 40 40 40 40 60 60 60 60 60 60 Die Revision + Firmware Revision Suffix -B20 -B20 -B20 -B20 -B20 -B20 -C40 -C40 -C40 -C40 -C40 -C40 -D60 -D60 -D60 -D60 -D60 -D60 Hexadecimal values are immediately preceded by "0x"; all other numeric values are decimal. 318 Rev. 1.2 AN332 To Achieve Similar Performance in SI4704/05/3X-D60 to SI4704/05/3X-C40 The -D60 devices have a more advanced feature set than -C40 devices. This section describes a step-by-step procedure to achieve similar performance from -D60 devices to that of -C40 devices by modifying or disabling some of the advanced features. FM Receiver Mode There is a debug feature that remains active in Si4704/05/3x-D60 firmware which can create periodic noise in audio. Silicon Labs recommends you disable this feature by sending the following bytes (shown here in hexadecimal form): 0x12 0x00 0xFF 0x00 0x00 0x00 In Si4704/05/3x-D60 devices, the FM_BLEND_RSSI_STEREO_THRESHOLD property is no longer at address 0x1105. Use address 0x1800 instead. In Si4704/05/3x-D60 devices, the FM_BLEND_RSSI_MONO_THRESHOLD property is no longer at address 0x1106. Use address 0x1801 instead. To disable the SNR-based stereo blend, set both the FM_BLEND_SNR_STEREO_THRESHOLD property (0x1804) and the FM_BLEND_SNR_MONO_THRESHOLD property (0x1805) to 0. To disable the multipath-based stereo blend, set both the FM_BLEND_MULTIPATH_STEREO_THRESHOLD property (0x1808) and the FM_BLEND_MULTIPATH_MONO_THRESHOLD property (0x1809) to 100 (0x64). AM Receive Mode Si473x-D60 devices are compatible with Si473x-C40 devices in AMRX mode. WB Receive Mode There are no Si473x-D60 devices which support WBRX mode. To Achieve Similar Performance in SI4704/05/3X-D60 to SI4704/05/3X-B20 The -D60 devices have a more advanced feature set than -B20 devices. This section describes a step-by-step procedure to achieve similar performance from -D60 devices to that of -B20 devices by modifying or disabling some of the advanced features. FM Receiver Mode There is a debug feature that remains active in Si4704/05/3x-D60 firmware which can create periodic noise in audio. Silicon Labs recommends you disable this feature by sending the following bytes (shown here in hexadecimal form): 0x12 0x00 0xFF 0x00 0x00 0x00 In Si4704/05/3X-D60 devices, the FM_BLEND_RSSI_STEREO_THRESHOLD property is no longer at address 0x1105. Use address 0x1800 instead. In Si4704/05/3X-D60 devices, the FM_BLEND_RSSI_MONO_THRESHOLD property is no longer at address 0x1106. Use address 0x1801 instead. To disable the SNR-based stereo blend, set both the FM_BLEND_SNR_STEREO_THRESHOLD property (0x1804) and the FM_BLEND_SNR_MONO_THRESHOLD property (0x1805) to 0. To disable the multipath-based stereo blend, set both the FM_BLEND_MULTIPATH_STEREO_THRESHOLD property (0x1808) and the FM_BLEND_MULTIPATH_MONO_THRESHOLD property (0x1809) to 100 (0x64). Rev. 1.2 319 AN332 AM Receive Mode Set the AM_MODE_AVC_MAX_GAIN property (0x3103) to 0x7800. Set the AM_SOFT_MUTE_THRESHOLD property (03303) to 10. Set the AM_SOFT_MUTE_SLOPE property (0x3301) to 2 Set the AM_SOFT_MUTE_MAX_ATTENUATION property (0x3302) to 16. WB Receive Mode There are no Si473x-D60 devices which support WBRX mode. To Achieve Similar Performance in Si4704/05/3X-C40 to Si4704/05/3X-B20 This section describes a step-by-step procedure to achieve performance from -C40 devices that is similar to that of -B20 devices. FM Receiver Mode Si473x-C40 devices are compatible with Si473x-B20 devices in FMRX mode. AM Receive Mode Set the AM_MODE_AVC_MAX_GAIN property (0x3103) to 0x7800 (maximum). Set the AM_SOFT_MUTE_THRESHOLD property (0x3303) to 10 (db). Set the AM_SOFT_MUTE_SLOPE property (0x3301) to 2 (dB/dB). Set the AM_SOFT_MUTE_MAX_ATTENUATION property (0x3302) to 16 (dB). WB Receive Mode Si473x-C40 devices are compatible with Si473x-B20 devices in WBRX mode. 320 Rev. 1.2 AN332 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated Product Matrix in Table 1. Added Si4706 FM and High-Performance RDS Receiver support. Added Si4707 WB/SAME Receiver support. Added Si4740/41 multipath, blend, and AGC properties. Added Si4749 High-Performance RDS Receiver support. Updated Firmware, Library, and Component Compatibility tables. Added Command Timing Parameters for the WB Receiver. Updated FM Transmitter maximum audio volume recommendations. Revision 0.2 to Revision 0.3 Added notes to AM/SW/LW Receiver Reference Clock section. Removed Si4706/07/4xrelated material. Updated product matrix in Table 1. Revision 0.3 to Revision 0.4 Added Si4704/05/30/31/34/35/36/37/38/39-C40 receiver support and additional AM properties. Added Si4784/85-B20 receiver support. Updated product matrix in Table 1. Updated with corrections to couple commands and properties. Revision 0.4 to Revision 0.41 Minor edits. Revision 0.41 to Revision 0.5 Combined information in AN332 Rev. 0.41 and AN344 Rev. 0.4 into AN332 Rev. 0.5. Added information for Si47xx-D50 and Si47xx-D60 parts. Revision 0.5 to Revision 0.6 Added Appendix A and Appendix B. Revision 0.6 to Revision 0.7 Added FM_BLEND_MAX_STEREO_SEPARATION property Revision 0.7 to Revision 0.8 Corrected pin numbers of LIN and RIN for Si4704/05/3x-D60 parts. Added more explanations to property 0x1900 and 0x3103. Added AUXIN Components in Tables 33, 38, and 41. Revision 0.8 to Revision 0.9 Added Si4732 AM/SW/LW/FM RDS Receiver support. Revision 0.9 to Revision 1.0 Removed information about AUXIN components. Added notes to powerup command section. Revision 1.0 to Revision 1.1 Added Si4704/05/30/31-D62 part information. Removed AUXIN components from Si4704/05/30/31/34/35-D60 parts. Revision 1.1 to Revision 1.2 Added information that Digital Output is available in Si4704-D60 and later. Added errata for the digital audio input for three devices: Si4710-B30, Si4712-B30, Si4720-B20. Rev. 1.2 321 Smart. Connected. Energy-Friendly. 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