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RoHS Compliant 4GB DDR3 1.35V SO-DIMM Product Specifications January 14, 2014 Version 1.1 Apacer Technology Inc. 1F., No.32, Zhongcheng Rd., Tucheng Dist., New Taipei City 236, Taiwan Tel: +886-2-2267-8000 Fax: +886-2-2267-2261 www.apacer.com Table of Contents General Description .......................................................................................................2 Ordering Information .....................................................................................................2 Key Parameters ..............................................................................................................2 Specifications:................................................................................................................3 Features: ......................................................................................................................... 4 Pin Assignments.............................................................................................................5 Pin Descriptions .............................................................................................................7 Functional Block Diagram.............................................................................................8 Absolute Maximum Ratings ..........................................................................................9 DRAM Component Operating Temperature Range.....................................................10 Operating Conditions ...................................................................................................11 Mechanical Drawing....................................................................................................12 ©Apacer Technology Inc. 1 General Description Apacer 78.B2GCZ.4000C is a 512M x 64 DDR3 SDRAM (Synchronous DRAM) SO-DIMM. This high-density memory module consists of 8 pieces 512M x 8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM. The module is a 204-pins small-outlined, dual in-line memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. The following provides general specifications of this module. Ordering Information Part Number 78.B2GCZ.4000C Bandwidth 12.8 GB/sec Speed Grade Max Frequency CAS Latency 1600 Mbps 800 MHz CL11 Density 4GB Organization 512M x 64 Key Parameters Component 512M x8*8 Rank 1 MT/s Grade tCK (min) CAS latency tRCD (min) tRP (min) tRAS (min) tRC (min) CL-tRCD-tRP DDR3-1066 -CL7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 -CL9 1.5 9 13.5 13.5 36 49.5 9-9-9 DDR3-1600 -CL11 1.25 11 13.75 13.75 35 48.75 11-11-11 Unit ns tCK ns ns ns ns tCK ©Apacer Technology Inc. 2 Specifications: On-DIMM thermal sensor : No Organization: 512 words x 64 bits, 1 rank Integrating 8 pieces of 4G bits DDR3 SDRAM sealed in FBGA Package: 204-pin socket type small outline dual in-line memory module (SO-DIMM) PCB: height 30.0mm, lead pitch 0.6 mm (pin), lead-free (RoHS compliant) Power supply VDD: 1.35V (+0.1V ~ -0.067V) Serial Presence Detect (SPD) Eight Internal banks for concurrent operation (components) Interface: SSTL_13 Burst lengths (BL): 8 and 4 with Burst Chop (BC) CAS Latency (CL): 6, 7, 8, 9, 10, 11 CAS Write Latency (CWL): 5, 6, 7, 8 Supports auto pre-charge option for each burst access Supports auto-refresh/self-refresh Refresh cycles: 7.8 at 0 TC +85 ©Apacer Technology Inc. 3 Features: Double-date-rate architecture: 2 data transfers per clock cycle The high-speed data transfer is realized by the 8-bits prefetch pipelined architecture. Bi-directional differential data strobe (DQS and /DQS) is transmitted / received with data for capturing data at the receiver DQS: edge-aligned with data for read; center-aligned with data for write Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Data mask (DM) for writing data Posted CAS by programmable additive latency for enhanced command and data bus efficiency On-Die-Termination (ODT) for improved signal quality: Synchronous ODT/Dynamic ODT/Asynchronous ODT Multi-Purpose Register (MPR) for temperature read out ZQ calibration for DQ drive and ODT Programmable Partial Array Self-Refresh (PASR) /Reset pin for power-up sequence and reset function SRT range: normal/extended, auto/manual self-refresh Programmable output driver impedance control ©Apacer Technology Inc. 4 Pin Assignments Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Pin name VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2 VSS DQ18 Pin No. 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 Pin name DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12(BC) A9 VDD A8 A5 VDD A3 A1 VDD CK0 /CK0 Pin No. 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 Pin name VDD A10(AP) BA0 VDD /WE /CAS VDD A13 /CS1 VDD NC VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin No. 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 Pin name DQ42 DQ43 VSS DQ48 DQ49 VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT ©Apacer Technology Inc. 5 Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Pin name VSS DQ4 DQ5 VSS /DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 /RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 Pin No. 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 Pin name VSS DQ28 DQ29 VSS /DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15(NC) A14(NC) VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 /CK1 Pin No. 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 Pin name VDD BA1 /RAS VDD /CS0 ODT0 VDD ODT1 NC VDD VREFCA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS Pin No. 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 Pin name DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS /EVENT SDA SCL VTT ©Apacer Technology Inc. 6 Pin Descriptions Pin Name Description Ax* SDRAM address bus BAx SDRAM bank select DQx DIMM memory data bus /RAS SDRAM row address strobe /CAS SDRAM column address strobe /WE SDRAM write enable /CSx SDRAM Chip select lines CKEx SDRAM clock enable lines CKx SDRAM clock input /CKx SDRAM Differential clock input DQSx SDRAM data strobes(positive line of differential pair) /DQSx SDRAM data strobes(negative line of differential pair) DMx SDRAM input mask SCL Clock input for serial PD SDA Data input/output for serial PD SAx Serial address input VDD Power for internal circuit VDDSPD Serial EEPROM positive power supply VREFDQ SDRAM I/O reference supply VREFCA SDRAM command/address reference supply VSS Power supply return(ground) VTT SDRAM I/O termination supply /RESET Set DRAM to known state ODTx On-die termination control lines NC Spare pins(no connect) /EVENT An output of the thermal sensor to indicate critical module temperature *IC Component Composition: 128Mx8 256Mx8 512Mx8 1024Mx8 A0~A13 A0~A14 A0~A15 A0~A15 ©Apacer Technology Inc. 7 Functional Block Diagram S0 RAS CAS WE CK0 CK0 CKE0 ODT0 A[0:N]\BA[0:N] DQS0 DQS0 DM0 DQ [0:7] DQS2 DQS2 DM2 DQ [16:23] DQS4 DQS4 DM4 DQ [32::39] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D0 DQS1 DQS1 DM1 DQ [8:15] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D4 SCL SCL SA0 A0 (SPD) SA1 A1 A2 WP SDA CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D1 DQS3 DQS3 DM3 DQ [24:31] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D2 DQS5 DQS5 DM5 DQ [40:47] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D5 DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D6 Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK0 CK1 CK1 S1 ODT1 CKE1 EVENT RESET Vtt SPD / TS D0-D7 D0-D7 D0-D7 D0-D7, SPD, Temp sensor D0-D7 D0-D7 Terminated at near card edge NC NC NC Temp Sensor D0-D7 V1 D4 V2 D5 V3 D6 V4 D7 Vtt CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] Vtt DQS6 DQS6 DM6 DQ [48::55] CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] CS RAS CAS WE CK CK CKE ODT A[0:N]\BA[0:N] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D3 DQS7 DQS7 DM7 DQ [56::63] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D7 V1 D0 V2 D1 V3 D2 V4 D3 Address and Control lines NOTES 1. DQ wiring may differ from that shown however ,DQ, DM, DQS, and DQS relationships are maintained as shown Vtt Vtt VDD ©Apacer Technology Inc. 8 Absolute Maximum Ratings Parameter Symbol Description Units Voltage on VDD pin relative to Vss VDD - 0.4 V ~ 1.975 V V Voltage on VDDQ pin relative to Vss VDDQ - 0.4 V ~ 1.975 V V Voltage on any pin relative to Vss VIN, VOUT - 0.4 V ~ 1.975 V V Storage Temperature TSTG -55 to +100 Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6 x VDDQ, when VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. . ©Apacer Technology Inc. 9 DRAM Component Operating Temperature Range Symbol TOPER Parameter Normal Operating Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units Notes 1,2 1,3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported during operation, the DRAM case temperature must be maintained between 0 - 85 under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range. ©Apacer Technology Inc. 10 Operating Conditions Recommended DC Operating Conditions - DDR3L (1.35V) operation Symbol Parameter Rating Min. Typ. Max. VDD Supply Voltage 1.283 1.35 1.45 VDDQ Supply Voltage for Output 1.283 1.35 1.45 Units V V Notes: 1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation. ©Apacer Technology Inc. 11 Mechanical Drawing Front side 2.00 Min 21.15 9.00 (DATUM -A-) Component area (Front) Unit: mm 3.80 Max 4x Full R 6.00 1 203 4.00 Min 2.15 Back side 2.45 21.00 B A 39.00 67.60 63.60 C 2.45 D 1.00 ± 0.10 2.15 2 204 4.00 20.00 30.00 Component area (Back) Detail A (DATUM -A-) Detail B 0.60 FULL R 1.65 2.55 Min 0.35 Max 0.45 ± 0.03 Detail C 3.00 1.35 4.00 ± 0.10 3.00 1.00 ± 0.10 Detail D Contact pad 0.2 Max 0.35 Max (All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) ©Apacer Technology Inc. 12 Revision History Revision Date Description 0.9 08/28/2012 Official release 1.0 08/29/2012 release 1.1 07/23/2013 Changed headquarters address Remark ©Apacer Technology Inc. 13 Global Presence Taiwan (Headquarters) U.S.A. Japan Europe China India Apacer Technology Inc. 1F., No.32, Zhongcheng Rd., Tucheng Dist., New Taipei City 236, Taiwan R.O.C. Tel: +886-2-2267-8000 Fax: +886-2-2267-2261 amtsales@apacer.com Apacer Memory America, Inc. 386 Fairview Way, Suite102, Milpitas, CA 95035 Tel: 1-408-518-8699 Fax: 1-408-935-9611 sa@apacerus.com Apacer Technology Corp. 5F, Matsura Bldg., Shiba, Minato-Ku Tokyo, 105-0014, Japan Tel: 81-3-5419-2668 Fax: 81-3-5419-0018 jpservices@apacer.com Apacer Technology B.V. Science Park Eindhoven 5051 5692 EB Son, The Netherlands Tel: 31-40-267-0000 Fax: 31-40-267-0000#6199 sales@apacer.nl Apacer Electronic (Shanghai) Co., Ltd 1301, No.251,Xiaomuqiao Road, Shanghai, 200032, China Tel: 86-21-5529-0222 Fax: 86-21-5206-6939 sales@apacer.com.cn Apacer Technologies Pvt Ltd, # 535, 1st Floor, 8th cross, JP Nagar 3rd Phase, Bangalore 560078, India Tel: 91-80-4152-9061 sales_india@apacer.com ©Apacer Technology Inc. 14Acrobat Distiller 8.0.0 (Windows)