Versal ACAP Packaging and Pinouts Architecture Manual
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Versal ACAP Packaging and Pinouts Architecture Manual
Describes the packaging and pinout specifications for the Versal™ ACAPs.
mechanical, VC, VM, AI Core, Prime, VB, VS, VY, VF
Architecture Manual. AM013 (v1.0) July 16, ... Manual (AM010). ... included in the Laird Technologies material safety data sheet (MSDS).
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Versal ACAP Packaging and Pinouts
Architecture Manual
AM013 (v1.0) July 16, 2020
Revision History
Revision History
The following table shows the revision history for this document.
Initial release.
Section
7/16/2020 Version 1.0 N/A
Revision Summary
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Overview......................................................................................................6
Introduction to Versal ACAP.......................................................................................................6 Package and Pinout Overview................................................................................................... 8 Device/Package Combinations.................................................................................................. 8 Gigabit Transceiver Channels by Device/Package.................................................................. 9 Differences from Previous Generations................................................................................. 11 User I/O Pins by Device Package.............................................................................................11 Pin Definitions............................................................................................................................13 Footprint Compatibility between Packages........................................................................... 16
Chapter 2: Die Level Bank Numbering and Device Diagrams............. 28
Die Level Bank Numbering Overview..................................................................................... 28 Device Diagrams Overview...................................................................................................... 31 VC1802 Bank Diagram Overview............................................................................................. 32 VC1902 Bank Diagram Overview............................................................................................. 34 VM1802 Bank Diagram Overview............................................................................................ 36
Chapter 3: Package Files...........................................................................................39
About ASCII Package Files........................................................................................................39 Package Specifications Designations......................................................................................40 ASCII Pinout Files.......................................................................................................................41
Chapter 4: Device Diagrams................................................................................... 42
VIVA1596 Package--VC1802.....................................................................................................43 VIVA1596 Package--VC1902.....................................................................................................44 VFVC1760 Package--VM1802................................................................................................... 45 VSVD1760 Package--VC1802................................................................................................... 46 VSVD1760 Package--VC1902................................................................................................... 47 VSVD1760 Package--VM1802.................................................................................................. 48 VSVA2197 Package--VC1802....................................................................................................49 VSVA2197 Package--VC1902....................................................................................................50
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VSVA2197 Package--VM1802...................................................................................................51
Chapter 5: Mechanical Drawings......................................................................... 52
VIVA1596 Package--VC1802 and VC1902............................................................................... 54 VFVC1760 Package--VM1802................................................................................................... 55 VSVD1760 Package--VC1802, VC1902, and VM1802............................................................. 56 VSVA2197 Package--VC1802, VC1902, and VM1802..............................................................57
Chapter 6: Package Marking.................................................................................. 58
Chapter 7: Packing and Shipping.........................................................................59
Chapter 8: Soldering Guidelines........................................................................... 60
Sn/Pb Reflow Soldering............................................................................................................ 61 Pb-Free Reflow Soldering......................................................................................................... 62 Peak Package Reflow Temperatures.......................................................................................64 Post Reflow/Cleaning/Washing...............................................................................................66 Conformal Coating.................................................................................................................... 66 Strain Gauge Measurement.....................................................................................................67 Solder Paste............................................................................................................................... 67 Component Placement............................................................................................................. 68
Chapter 9: Recommended PCB Design Rules for BGA..............................70
Stencil......................................................................................................................................... 71
Chapter 10: Edge Bonding Guidelines............................................................... 74
Edge Bonding Implementation............................................................................................... 74 Edge Bond Removal.................................................................................................................. 77
Chapter 11: Thermal Specifications....................................................................78
Support for Thermal Models....................................................................................................78
Chapter 12: Thermal Management Strategy................................................ 80
Flip-Chip Packages.................................................................................................................... 80 System Level Heat Sink Solutions............................................................................................81 Thermal Interface Material...................................................................................................... 81 Heat Sink Removal.................................................................................................................... 85 Measurement Debug................................................................................................................87
Chapter 13: Heat Sink Guidelines for Bare-die VB Packages............... 88
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Heat Sink Attachments............................................................................................................. 88 Types of Heat Sink Attachments..............................................................................................89 Heat Sink Attachment Process Considerations..................................................................... 90
Chapter 14: Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages................................................................................... 93
Lidless Flip-Chip Packages....................................................................................................... 93
Appendix A: Additional Resources and Legal Notices............................. 95
Xilinx Resources.........................................................................................................................95 Documentation Navigator and Design Hubs.........................................................................95 References..................................................................................................................................96 Please Read: Important Legal Notices................................................................................... 97
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Chapter 1: Overview
Chapter 1
Overview
Introduction to Versal ACAP
VersalTM adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAP hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. Versal ACAPs are enabled by a host of tools, software, libraries, IP, middleware, and frameworks to enable all industry-standard design flows.
Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform to combine software programmability and domain-specific hardware acceleration with the adaptability necessary to meet today's rapid pace of innovation. The portfolio includes six series of devices uniquely architected to deliver scalability and AI inference capabilities for a host of applications across different markets--from cloud--to networking--to wireless communications-- to edge computing and endpoints.
The Versal architecture combines different engine types with a wealth of connectivity and communication capability and a network on chip (NoC) to enable seamless memory-mapped access to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Engines for adaptive inference and advanced signal processing compute, and DSP Engines for fixed point, floating point, and complex MAC operations. Adaptable Engines are a combination of programmable logic blocks and memory, architected for high-compute density. Scalar Engines, including Arm� CortexTM-A72 and Cortex-R5F processors, allow for intensive compute tasks.
The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines that deliver over 100x greater compute performance than current server-class of CPUs. This series is designed for a breadth of applications, including cloud for dynamic workloads and network for massive bandwidth, all while delivering advanced safety and security features. AI and data scientists, as well as software and hardware developers, can all take advantage of the highcompute density to accelerate the performance of any application.
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Chapter 1: Overview
The Versal Prime series is the foundation and the mid-range of the Versal platform, serving the broadest range of uses across multiple markets. These applications include 100G to 200G networking equipment, network and storage acceleration in the Data Center, communications test equipment, broadcast, and aerospace & defense. The series integrates mainstream 58G transceivers and optimized I/O and DDR connectivity, achieving low-latency acceleration and performance across diverse workloads.
The Versal Premium series provides breakthrough heterogeneous integration, very highperformance compute, connectivity, and security in an adaptable platform with a minimized power and area footprint. The series is designed to exceed the demands of high-bandwidth, compute-intensive applications in wired communications, data center, test & measurement, and other applications. Versal Premium series ACAPs include 112G PAM4 transceivers and integrated blocks for 600G Ethernet, 600G Interlaken, PCI Express� Gen5, and high-speed cryptography.
The Versal architecture documentation suite is available at: https://www.xilinx.com/versal.
Navigating Content by Design Process
Xilinx� documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:
� System and Solution Planning: Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:
� Device/Package Combinations � Footprint Compatibility between Packages � Chapter 2: Die Level Bank Numbering and Device Diagrams
� Board System Design: Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. Topics in this document that apply to this design process include:
� Chapter 1: Overview describes the architecture, package resources, and footprint compatibility between packages.
� Device Diagrams Overview, Chapter 3: Package Files, and Chapter 4: Device Diagrams describes the package pinouts in textual and graphical format.
� Chapter 5: Mechanical Drawings includes the physical dimensions for each package. � Chapter 6: Package Marking and Chapter 7: Packing and Shipping. � Chapter 8: Soldering Guidelines, Chapter 9: Recommended PCB Design Rules for BGA, and
Chapter 10: Edge Bonding Guidelines provide PCB implementation information.
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Chapter 1: Overview
� Chapter 11: Thermal Specifications, Chapter 12: Thermal Management Strategy, Chapter 13: Heat Sink Guidelines for Bare-die VB Packages, and Chapter 14: Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages include guidelines for overall thermal management.
Package and Pinout Overview
This section describes the packages and pinouts for various organic flip-chip 0.80 mm, 0.92 mm, and 1.00 mm pitch BGA packages.
IMPORTANT! All standard packages are lead-free (signified by an additional V in the package name). All devices supported in a particular package are footprint compatible. Each device is split into I/O banks to allow for flexibility in the choice of I/O standards. See the Versal ACAP SelectIO Resources Architecture Manual (AM010). The flip-chip assembly materials for the Versal devices are manufactured using ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than 0.002 alpha-particles per square centimeter per hour. IMPORTANT! All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Device/Package Combinations
The following table shows the size and BGA pitch of the Versal device packages. All packages are available with eutectic BGA balls. For these packages, the Pb-free signifier in the package name is a Q.
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Chapter 1: Overview
Table 1: Package Specifications
Packages
Description
SFVB625 VBVA1024 VFVB1024 VFVB1369 VSVE1369 VSVA1596
VIVA1596
VFVA1760 VFVC1760 VSVD1760 VSVA2197 VSVA2785
Super-fine pitch with forged lid Fine pitch bare-die Fine pitch with forged lid Fine pitch with forged lid Fine pitch lidless with stiffener ring Fine pitch lidless with stiffener ring Overhang fine pitch lidless with stiffener ring Fine pitch with forged lid Fine pitch with forged lid Fine pitch lidless with stiffener ring Fine pitch lidless with stiffener ring Fine pitch lidless with stiffener ring
Package Type
BGA
Package Specifications
Pitch (mm)
Size (mm)
LSC Ball Grid Size (balls)
0.8
21 � 21
�
0.92
31 � 31
4 � 4
31 � 31
4 � 4
35 � 35
5 � 5
35 � 35
5 � 5
37.5 � 37.5
5 � 5
40 � 40
6 � 6
40 � 40 40 � 40 40 � 40 45 � 45 50 � 50
6 � 6 6 � 6 6 � 6 7 � 7 9 � 9
IMPORTANT! Packages with land-side capacitors (LSC) include a region of the BGA matrix where the BGA balls are replaced with capacitors. The LSC Ball Grid Size column in Table 1 describes the size of the LSC region in terms of the number of BGA balls replaced by capacitors. Therefore, packages with LSCs have fewer balls than the package name implies (for example, the VSVA2197 has 7 x 7 = 49 fewer balls than the implied 2197 balls).
Gigabit Transceiver Channels by Device/ Package
The following table lists the quantity of gigabit transceiver channels for the Versal devices. There is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins for the GTY or GTM channels in all devices. All packages are available with eutectic BGA balls where the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 2: Serial Transceiver Channels (GTY and GTM) by Device/Package
Device
VM1102 VC1352 VC1502
Package
SFVB625 VBVA1024
GTY Channels
4 8 8
GTM Channels
0 0 0
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Chapter 1: Overview
Table 2: Serial Transceiver Channels (GTY and GTM) by Device/Package (cont'd)
Device
VM1102 VM1302 VM1402 VM1302 VM1402 VM1502 VM1302 VM1402 VC1352 VC1702 VC1502 VC1502 VC1702 VC1802 VC1902 VM1302 VM1402 VM2602 VM1502 VM1802 VM2602 VM2902 VM1802 VC1802 VC1902 VM1802 VM2502 VC1502 VC1802 VC1902
Package
VFVB1024
VFVB1369
VFVF1369 VSVE1369 VSVG1369 VSVA1596 VIVA1596 VFVA1760
VFVC1760
VSVD1760 VSVD1760 VSVA2197 VSVA2197
GTY Channels
12 16 16 24 24 16 8 8 8 24 24 32 16 32 32 24 24 8 44 44 8 8 24 24 24 44 16 44 44 44
GTM Channels
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 0 0 40 40 0 0 0 0 16 0 0 0
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Chapter 1: Overview
Differences from Previous Generations
This section lists the differences from previous generations of the packaging and pinout specifications.
� In addition to 0.8 mm and 1.0 mm BGA ball pitch, Versal ACAP packages have 0.92 mm BGA ball pitch, signified by a package code beginning with a V.
� Some packages include land-side capacitor (LSC) technology (decoupling capacitors on the bottom side of the package, adjacent to the BGA balls). LSC array dimensions for each package are found in Chapter 5: Mechanical Drawings.
� Hardware blocks bonded to package pins have been added with VersalTM ACAPs, including XPIO, PMCMIO, and LPDMIO banks.
� I/Os in some banks on the left and right edges of the XPIO rows do not have direct access to all I/O logic resources and can only be used for DDR memory controller (DDRMC) applications.
� VRP pins, previously found in each HPIO bank, are replaced with a single IO_VR pin for each row of XPIO banks.
� VCCO voltage range for XPIO banks is 1.0V to 1.5V instead of the 1.0V to 1.8V range for HPIO banks in previous generations.
� Device diagrams showing package pinout (previously separated into I/O diagrams and power/ dedicated/multifunction diagrams, are combined into a single diagram for Versal ACAP packages.
� Package marking found on previous device generations is replaced with a 2D bar code.
User I/O Pins by Device Package
The following table lists the number of available PMC and LPD multiplexed I/Os (MIO), 3.3Vcapable high-density (HD), and 1.5V-capable high-performance (XP) I/Os and the number of HD or XP differential I/O for each device/package combination. All packages are available with eutectic BGA balls where the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 3: Available I/O Pins by Device/Package
Device
VC1352
Package
VBVA1024 VSVE1369
MIO
78 78
Total User I/O
XPIO
HDIO
378
22
378
44
Differential I/O
XPIO
HDIO
189
11
189
22
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Chapter 1: Overview
Table 3: Available I/O Pins by Device/Package (cont'd)
Device
Package
MIO
Total User I/O
XPIO
HDIO
VC1502
VBVA1024
78
378
22
VSVG1369
78
378
44
VSVA1596
78
378
44
VSVA2197
78
378
44
VC1702
VSVE1369
78
378
44
VSVA1596
78
378
44
VC1802
VIVA1596
78
378
44
VSVD1760
78
648
0
VSVA2197
78
648
44
VC1902
VIVA1596
78
378
44
VSVD1760
78
648
0
VSVA2197
78
648
44
VM1102
SFVB625
78
216
22
VFVB1024
78
216
22
VM1302
VFVB1024
78
216
22
VFVB1369
78
216
22
VFVF1369
78
324
22
VFVA1760
78
432
22
VM1402
VFVB1024
78
324
22
VFVB1369
78
324
22
VFVF1369
78
648
22
VFVA1760
78
648
22
VM1502
VFVB1369
78
378
44
VFVC1760
78
378
44
VM1802
VFVC1760
78
378
44
VSVD1760
78
648
0
VSVA2197
78
648
44
VM2502
VSVA2197
78
648
22
VM2602
VFVA1760
78
756
0
VFVC1760
78
378
0
VM2902
VFVC1760
78
378
22
Notes: 1. The maximum user I/O numbers do not include the GT serial transceiver pins.
Differential I/O
XPIO
HDIO
189
11
189
22
189
22
189
22
189
22
189
22
189
22
324
0
324
22
189
22
324
0
324
22
108
11
108
11
108
11
108
11
162
11
216
11
162
11
162
11
324
11
324
11
189
44
189
44
189
44
324
0
324
22
324
11
378
0
189
0
189
11
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Chapter 1: Overview
Pin Definitions
The following tables list the pin definitions.
SelectIO Pin Definitions
Table 4: SelectIO Pin Definitions
Pin Name
IO
GC/HDGC IO_VR
Direction
Bidirectional
Bidirectional N/A
Pin name consists of:
Description
L[1 to 24][P or N]: Differential pair number with P (positive) and N (negative) N[0 to 8]P[0 to 5]: XPHY nibble number and pin number within the nibble (NIBBLESLICE number) M[0 to number of triplets]P[0 to 161]: Triplet number and pin within the triplet [bank number]: Bank number
The XP IOB block provides resources to enable high-speed interfaces between the programmable logic (PL) and the system outside the device. The XP IOB resources are designed to accommodate the signaling needs for high-speed memory and chip-tochip interfaces that are powered between 1.0V and 1.5V. The XP IOB provides internal termination, internal reference generation, support for a diverse set of I/O standards, driver emphasis, and receiver equalization. These features allow the XP IOB to integrate with a diverse range of systems.
High-density (HD) I/O banks are resources designed to support I/O standards with voltages ranging from 1.8V to 3.3V. HD I/Os support single ended and pseudodifferential I/O bidirectional signaling operating at data rates of up to 400 Mb/s. Limited support for true differential inputs (with external termination) is also available to support LVDS and LVPECL clock inputs. HD I/O banks contain interface logic (HD IOL) that includes registers, a DPLL, and static delay lines to support asynchronous, system synchronous, and clock-based source synchronous interfaces.
Global clock (GC) inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative. Generalpurpose I/O with local interconnects must not be used for clock signals.
This pin is for the DCI voltage reference resistor, one per bank row: IO_VR_700 and IO_VR_800. Tie to VCCO_700 and VCCO_800, respectively, with a reference resistor.
Power Pin Definitions
Table 5: Power Pin Definitions
Pin Name
VCCINT VCCAUX VCC_IO VCCO (XPIO or HDIO)
Direction
N/A N/A N/A N/A
Description
Power-supply pins for the programmable logic, AI Engines, and CPM Power-supply pins for the auxiliary circuits Power-supply pins for the HDIO and XPIO banks Power-supply pins for the output drivers (per bank)
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Chapter 1: Overview
Table 5: Power Pin Definitions (cont'd)
Pin Name
VCCO_500 VCCO_501 VCCO_502 VCCO_503 VCCAUX_PMC VCC_PSFP VCC_PSLP VCC_PMC VCC_SOC VCC_RAM VCC_BATT VCC_FUSE VCCAUX_SMON GND_SMON GND RSVDGND NC
Direction
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Description
PMC MIO bank 0 power supply PMC MIO bank 1 power supply LPD MIO bank power supply PMC dedicated I/O bank power supply Auxiliary power-supply pin for the PMC Power-supply for the PS full-power domain Power-supply for the PS low-power domain Auxiliary power-supply pins for the PMC Power supply pins for NoC, NPI, and the DDR Power-supply pins for the RAM, UltraRAM, and clocking network Battery supply voltage Power-supply pins for eFUSE programming Analog supply pin for the ADC and other analog circuits in the SYSMON Ground reference pin for the ADC and other analog circuits in the SYSMON Ground Reserved pin. Tie to GND. Reserved pin. Leave floating
PMCMIO, LPDMIO, PMCDIO Pin Definitions
Table 6: PMCMIO, LPDMIO, PMCDIO Pin Definitions
Pin Name
PMC_MIO[0 to 51] LPD_MIO[0 to 25] MODE[0 to 3] ERROR_OUT
RTC_PADO RTC_PADI PUDC_B
DONE
REF_CLK
Direction
Bidirectional Bidirectional
Input Output
Output Input Input
Bidirectional
Input/Output
Description
Platform management controller (PMC) multiplexed I/O (MIO)
Low-power domain (LPD) MIO
The MIO MODE selection pins are used to select the boot mode of the device. The value of these pins is captured on the rising edge of POR_B.
The ERROR_OUT pin is open drain with a weak internal pull-up. An external pull-up is recommended. ERROR_OUT is 3-stated and pulled High when an error occurs in the device.
Real-time clock (RTC) crystal output
RTC crystal input
The pull-up during configuration (PUDC_B) pin is used to select the behavior of the XPIO or HDIO during configuration. If the PUDC_B pin is High, then the XPIO and HDIO are put into tristate mode. If the PUDC_B is Low, then internal pull-ups at each XPIO and HDIO are enabled. The PUDC_B pin does not affect the PS or PMC I/O during boot and configuration.
The DONE pin is open drain with a weak internal pull-up resistor. An external pull-up is recommended. DONE is tristated and pulled High when the boot sequence is complete.
The reference clock is required for all boot modes. The REF_CLK is also the input clock to the PMC PLL and is required for the slave boot interface software register access.
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Chapter 1: Overview
Table 6: PMCMIO, LPDMIO, PMCDIO Pin Definitions (cont'd)
Pin Name
POR_B
TCK TDI TDO TMS
Direction
Input
Input Input Output Input
Description
Active-Low POR_B pin is the global power-on reset for the Versal device. It must remain asserted Low until power is fully applied to at least the VCC_PMC, VCCAUX_PMC, and VCCO_503. When the reset is released, the PMC begins the initialization and boot process.
JTAG test clock
JTAG test data input
JTAG test data output
JTAG test mode select
GTY Transceiver Quad Pin Definitions
Table 7: GTY Transceiver Quad Pin Definitions
Pin Name
GTY_RXP, GTY_RXN GTY_TXP, GTY_TXN GTY_REFCLKP, GTY_REFCLKN GTY_AVTTRCAL GTY_RREF GTY_AVCC
GTY_AVTT
GTY_AVCCAUX
Direction
Input Output Input Input (Pad) Input (Pad) Input (Pad)
Input (Pad)
Input (Pad)
Description
GTY_RXP and GTY_RXN are the differential input pairs for each of the receivers in the GTY transceiver Quad
GTY_TXP and GTY_TXN are the differential output pairs for each of the transmitters in the GTY transceiver Quad
Configured as either reference clock input pins or as RX recovered clock output pins for the GTY transceiver Quad
Bias current supply for the termination resistor calibration circuit
Calibration resistor input pin for the termination resistor calibration circuit
GTY_AVCC is the analog supply for the internal analog circuits of the GTY transceiver Quad tile. This includes the analog circuits for the PLLs, transmitters, and receivers. Most packages have multiple groups of power supply connections in the package for GTY_AVCC. Refer to the package pin definitions to identify in which power supply group a specific GTY transceiver Quad is located. The nominal voltage is 0.88VDC.
GTY_AVTT is the analog supply for the transmitter and receiver termination circuits of the GTY transceiver Quad tile. Most packages have multiple groups of power supply connections in the package for GTY_AVTT. Refer to the package pin definitions to identify in which power supply group a specific GTY transceiver Quad is located. The nominal voltage is 1.2VDC.
GTY_VCCAUX is the analog LCPLL voltage supply for the transceivers. Most packages have multiple groups of power supply connections in the package for GTY_AVCCAUX. Refer to the package pin definitions to identify in which power supply group a specific GTY transceiver Quad is located. The nominal voltage is 1.8VDC.
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Chapter 1: Overview
SYSMON Pin Definitions
Table 8: SYSMON Pin Definitions
Pin Name
VREFP
Direction
N/A
VREFN
N/A
VP
Input
VN
Input
Description
This pin can be tied to an external 1.024V accurate reference IC for best performance of the ADC. This pin should be connected to GND_SMON if an external reference is not supplied.
This pin should be tied to the ground pin of an external 1.024V accurate reference IC for best performance of the ADC. This pin should always be connected to GND_SMON even if an external reference is not supplied.
This is the positive input terminal of the dedicated differential analog input channel (VP/VN). When not used, tie to GND_SMON.
This is the negative input terminal of the dedicated differential analog input channel (VP/VN). When not used, tie to GND_SMON.
Footprint Compatibility between Packages
Versal devices are footprint compatible only with other Versal devices with the same numerical portion of the package name and the same preceding single character alphabetic designator. For example, the VM1802-VSVD1760 is footprint compatible with the VC1902-VSVD1760, because the 1760 is preceded with a D in both package names, but not footprint compatible with the VM1802-VFVC1760. Also, the VC1502-VSVA1596 is footprint compatible with the VC1902VIVA1596, regardless of a difference in package dimensions, because the 1596 is preceded by an A in both package names. Pins that are available in one device but are not available in another device are labeled as NC in the package file of the other device.
IMPORTANT! Footprint compatibility does not necessarily imply that all pins will function in the same manner for different devices in a package.
The following table shows the footprint compatible devices available for each package. See the Versal Architecture and Product Data Sheet: Overview (DS950) for specific package letter code options. All packages are available with eutectic BGA balls. For these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 9: Footprint Compatibility
Packages
SFVB625 VBVA1024 VFVB1024 VFVB1369 VSVE1369
VM1102 VC1352 VM1102 VM1302 VC1352
Footprint Compatible Devices
VC1502 VM1302 VM1402 VC1702
VM1402 VM1502
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Chapter 1: Overview
Table 9: Footprint Compatibility (cont'd)
Packages
Footprint Compatible Devices
VFVF1369 VSVG1369
VM1302 VC1502
VM1402
VSVA1596 VIVA15961 VFVA1760
VC1502 VM1302
VC1702 VM1402
VC1802 VM2602
VC1902
VFVC1760
VM1502
VM1802
VM2602
VM2902
VSVD1760 VSVA2197
VM1802 VM1802
VC1802 VM2502
VC1902 VC1502
VC1802
VC1902
Notes:
1. While footprint compatible, the body size for the VIVA1596 is 40 mm x 40 mm, which is larger than the 37.5 mm x 37.5 mm body size for the VSVA1596 package.
Many Versal devices that are footprint compatible in a package have different I/O bank and transceiver quad numbers connected to the same package pins. Due to these differences, when migrating between devices in a specific package, the type of bank (HD vs. XP) or quad (GTY, GTYP, or GTM), whether a bank is connected or NC at the package pins, and where the bank or quad is located on the die must be taken into consideration. The following tables show how the banks and transceiver quads are numbered between devices in each package. For all groupedtogether footprint-compatible packages, the bank and quad numbers in the same column (indicated by the letters A through Z) for each device are connected to the same package pins. For example, in the VSVA2197 packages, quad 202 for the VM2502 is connected to the same pins as quad 203 for the VM1802, VC1502, VC1802, and VC1902. For a visual representation of all of this information, see Figure 1: Example Device Diagram.
Related Information I/O Bank Footprint Compatibility between Packages Transceiver Footprint Compatibility between Packages
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Chapter 1: Overview
I/O Bank Footprint Compatibility between Packages
Table 10: I/O Bank Migration
Package Device A B C D E F G H I
J
K
L
M-U AA AB AC AD AE
AF
AG
AH
AI-AU
Unbonded I/O Banks
SFVB625
VM1102 700 701 702 703
304
VBVA1024 VC1352 700 701 702 703 704 705 706
604
302, 204, 203, 202, 201, 200
VBVA1024 VC1502 700 701 702 703 704 705 706
406
306
VFVB1024 VM1102 700 701 702 703
304
VFVB1024 VM1302 700 701 702 703
306 307
800, 801, 802, 803, 804, 704, 805, 705
VFVB1024 VM1402 700 701 702 703 704 705
306 307
800, 801, 802, 803, 804, 805
VFVB1369 VM1302 700 701 702 703
306 307
800, 801, 802, 803, 804, 704, 805, 705
VFVB1369 VM1502 700 701 702 703 704 705 706
406 306
VFVB1369 VM1402 700 701 702
703 704 705
306 307
800, 801, 802, 803, 804, 805
VSVE1369 VC1352 700 701 702 703 704 705 706
604 302
204, 203, 202, 201, 200
VSVE1369 VC1702 700 701 702 703 704 705 706
608 302
208, 207, 206, 205, 204, 203, 202, 201, 200
VIVA1596
VC1802 700 701 702 703 706 707 708
406 306
704, 705, 709, 710, 711
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Chapter 1: Overview
Table 10: I/O Bank Migration (cont'd)
Package VIVA1596 VSVA1596 VSVA1596
VFVA1760 VFVA1760 VFVA1760 VFVC1760 VFVC1760 VFVC1760
VFVC1760
VSVD1760 VSVD1760 VSVD1760 VSVA2197
Device VC1902 VC1502 VC1702
VM1302 VM1402 VM2602 VM1502 VM1802 VM2602
VM2902
VM1802 VC1802 VC1902 VM2502
ABCDE F GH I
J
K
L
M-U AA AB AC AD AE
AF
AG
AH
AI-AU
Unbonded I/O Banks
700 701 702 703 706 707 708
406 306
704, 705, 709, 710, 711
700 701 702 703 704 705 706
406 306
700 701 702 703 704 705 706
608 302
208, 207, 206, 205, 204, 203, 202, 201, 200
700 701 702 703
800 801 802 803
307 306
804, 704, 805, 705
700 701 702 703 704 705
800 801 802 803 804 805 307 306
700 701 702 703 704 705 706 707
800 801 802 803 804 805
806, 807, 808, 708
700 701 702
704 705 706 703 306 406
700 701 702
703 704 705 706 306 406
707, 708, 709, 710, 711
700 701 702
703 704 705 706
800, 801, 802, 803, 804, 805, 806, 807, 707, 808, 708
700 701 702
703 704 705 706
412
800, 801, 802, 803, 804, 805, 806, 807, 707, 808, 708
700 701 702 703 704 705 706 707 708 709 710 711
306, 406
700 701 702 703 704 705 706 707 708 709 710 711
306, 406
700 701 702 703 704 705 706 707 708 709 710 711
306, 406
700 701 702 703 704 705 706 707 708 709 710 711
406
712
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Chapter 1: Overview
Table 10: I/O Bank Migration (cont'd)
Package
VSVA2197 VSVA2197 VSVA2197 VSVA2197
Device A B C D E F G H I
J
K
L
M-U AA AB AC AD AE
AF
AG
AH
AI-AU
Unbonded I/O Banks
VM1802 700 701 702 703 704 705 706 707 708 709 710 711
306 406
VC1502 700 701 702 703
704 705 706
306 406
VC1802 700 701 702 703 704 705 706 707 708 709 710 711
306 406
VC1902 700 701 702 703 704 705 706 707 708 709 710 711
306 406
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Chapter 1: Overview
Transceiver Footprint Compatibility between Packages
Table 11: Transceiver Migration � Left Side (GTM Quads are Shaded)
Package
Device
CA
CB
CC
CD
CE
CF
CG
CH
CI
CJ
CK
CL
CM
CN
CO
CP
CQ
SFVB625
XCVM1102
L
103
VBVA1024
XCVC1352
L
L
103
104
VBVA1024
XCVC1502
L
L
103
104
VFVB1024
XCVM1102
L
L
L
102
103
104
VFVB1024
XCVM1302
L
L
L
L
102
103
104
105
VFVB1024
XCVM1402
L
L
L
L
102
103
104
105
VFVB1369
XCVM1302
LS
LS
LS
LS
LN
LN
102
103
104
105
106
107
VFVB1369
XCVM1502
LS
LS
LS
LS
103
104
105
106
VFVB1369
XCVM1402
LS
LS
LS
LS
LN
LN
102
103
104
105
106
107
VSVE1369
XCVC1352
L
L
103
104
VSVE1369
XCVC1702
L
L
L
L
L
L
103
104
105
106
107
108
VIVA1596
XCVC1802
L
L
L
L
103
104
105
106
VIVA1596
XCVC1902
L
L
L
L
103
104
105
106
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Chapter 1: Overview
Table 11: Transceiver Migration � Left Side (GTM Quads are Shaded) (cont'd)
Package
Device
CA
CB
CC
CD
CE
CF
CG
CH
CI
CJ
CK
CL
CM
CN
CO
CP
CQ
VSVA1596
XCVC1502
L
L
L
L
103
104
105
106
VSVA1596
XCVC1702
L
L
L
L
103
104
105
106
VFVA1760
XCVM1302
L
L
L
L
L
L
102
103
104
105
106
107
VFVA1760
XCVM1402
L
L
L
L
L
L
102
103
104
105
106
107
VFVA1760
XCVM2602
L
L
L
L
L
L
102
103
104
105
106
107
VFVC1760
XCVM1502
L
L
L
L
103
104
105
106
VFVC1760
XCVM1802
L
L
L
L
103
104
105
106
VFVC1760
XCVM2602
L
L
L
L
L
L
102
103
104
105
106
107
VFVC1760
XCVM2902
L
L
L
L
L
L
102
103
104
105
106
107
VSVD1760
XCVM1802
L
L
L
L
103
104
105
106
VSVD1760
XCVC1802
L
L
L
L
103
104
105
106
VSVD1760
XCVC1902
L
L
L
L
103
104
105
106
VSVA2197
XCVM2502
L
L
L
L
102
103
104
105
VSVA2197
XCVM1802
L
L
L
L
103
104
105
106
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Chapter 1: Overview
Table 11: Transceiver Migration � Left Side (GTM Quads are Shaded) (cont'd)
Package
Device
CA
CB
CC
CD
CE
CF
CG
CH
CI
CJ
CK
CL
CM
CN
CO
CP
CQ
VSVA2197
XCVC1502
L
L
L
L
103
104
105
106
VSVA2197
XCVC1802
L
L
L
L
103
104
105
106
VSVA2197
XCVC1902
L
L
L
L
103
104
105
106
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Chapter 1: Overview
Table 12: Transceiver Migration � Right Side (GTM Duals are Shaded)
Package
Device BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY
SFVB625
XCVM1102
VBVA1024 VBVA1024 VFVB1024 VFVB1024
XCVC1352 XCVC1502 XCVM1102 XCVM1302
VFVB1024 XCVM1402
VFVB1369 XCVM1302
VFVB1369 XCVM1502
VFVB1369 XCVM1402
VSVE1369 XCVC1352
VSVE1369 XCVC1702
VIVA1596 XCVC1802 R
R
R
R
202 203 204 205
VIVA1596 XCVC1902 R
R
R
R
202 203 204 205
VSVA1596
VSVA1596 VFVA1760
XCVC1502 R
R
R
R
202 203 204 205
XCVC1702
XCVM1302
VFVA1760 XCVM1402
VFVA1760 XCVM2602
VFVC1760 XCVM1502 RS RS RS RS RN RN RN
VFVC1760 VFVC1760
200 201 202 203 204 205 206 XCVM1802 RS RS RS RS RN RN RN
200 201 202 203 204 205 206 XCVM2602 RS RS RS RS RN RN RN RN
200 201 202 203 204 205 206 207
VFVC1760 XCVM2902 RS RS RS RS RN RN RN RN
200 201 202 203 204 205 206 207
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Chapter 1: Overview
Table 12: Transceiver Migration � Right Side (GTM Duals are Shaded) (cont'd)
Package
Device BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY
VSVD1760 XCVM1802 R
R
VSVD1760 VSVD1760
203 204
XCVC1802 R
R
203 204
XCVC1902 R
R
203 204
VSVA2197 XCVM2502
R
R
R
R
202 203 204 205
VSVA2197 VSVA2197
XCVM1802 R
R
R
R
R
R
R
200 201 202 203 204 205 206
XCVC1502 R
R
R
R
R
R
R
200 201 202 203 204 205 206
VSVA2197 XCVC1802 R
R
R
R
R
R
R
200 201 202 203 204 205 206
VSVA2197 XCVC1902 R
R
R
R
R
R
R
200 201 202 203 204 205 206
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Table 13: Transceiver Migration � Unbonded Banks
Package
SFVB625 VBVA1024 VBVA1024 VFVB1024 VFVB1024 VFVB1024 VFVB1369 VFVB1369 VFVB1369 VSVE1369 VSVE1369 VIVA1596 VIVA1596 VSVA1596 VSVA1596 VFVA1760 VFVA1760 VFVA1760 VFVC1760 VFVC1760 VFVC1760 VFVC1760 VSVD1760 VSVD1760 VSVD1760 VSVA2197 VSVA2197
Device
XCVM1102 XCVC1352 XCVC1502 XCVM1102 XCVM1302 XCVM1402 XCVM1302 XCVM1502 XCVM1402 XCVC1352 XCVC1702 XCVC1802 XCVC1902 XCVC1502 XCVC1702 XCVM1302 XCVM1402 XCVM2602 XCVM1502 XCVM1802 XCVM2602 XCVM2902 XCVM1802 XCVC1802 XCVC1902 XCVM2502 XCVM1802
104, 102 106, 105, 206, 205, 204, 203, 202, 201, 200 107, 106 107, 106 206, 205, 204, 203, 202, 201, 200
206, 201, 200 206, 201, 200 206, 201, 200 108, 107
207, 206, 205, 204, 203, 202, 201, 200
112, 111, 110, 109, 108, 212, 211, 210, 209, 208 206, 205, 202, 201, 200 206, 205, 202, 201, 200 206, 205, 202, 201, 200 106, 206, 201, 200
Unbonded Banks
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Table 13: Transceiver Migration � Unbonded Banks (cont'd)
Package
VSVA2197 VSVA2197
Device
XCVC1502 XCVC1902
Unbonded Banks
Chapter 1: Overview
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Chapter 2
Die Level Bank Numbering and Device Diagrams
Die Level Bank Numbering Overview
Banking and Clocking Summary For each device, not all banks are bonded out in every package.
GTY and GTM Columns � One GT Quad = Four transceivers = Four GTYE5_QUAD or GTME5_QUAD primitives. � Not all GT Quads are bonded out in every package. � Also shown are quads labeled with RCAL. This specifies the location of the RCAL masters for
each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device. � The XY coordinates shown in each quad correspond to the transceiver channel number found in the pin names for that quad (as shown in the next section). � An alphabetic designator is shown in each quad. Each letter corresponds to the columns in the tables in the Transceiver Footprint Compatibility between Packages section. � The power supply group is shown in brackets [ ] for each quad.
I/O Banks � Each user XPIO bank has a total of 54 I/Os that can be used as differential (27 differential
pairs) or single-ended I/Os. All 54 pads of a bank are not always bonded out to pins. � A limited number of XPIO banks have fewer than 54 SelectIO pins. These banks are labeled as
partial. � Each user HDIO bank has a total of 22 I/Os that can be used as pseudo-differential (11
differential pairs) or single-ended I/Os. � Adjacent to each bank is a physical layer (PHY) containing clock buffers and clock
management resources
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Chapter 2: Die Level Bank Numbering and Device Diagrams
� XPIO banks are arranged in rows on the north and south of the device with adjacent PHY and clock management resources.
� XPIO banks are separated into groups of 1, 2, or 3 banks that signify how to group them when used for DDR memory controller applications.
� I/Os in some banks on the left and right edges of the XPIO rows do not have direct access to all I/O logic resources and can only be used for DDR memory controller (DDRMC) applications. These I/Os are specified in the following device diagrams, where each XPIO bank is designated by a Y (DDRMC only) or a N (access to all I/O logic resources) for each nibble (nine nibbles per bank and six I/Os per nibble). This is also specified in the DDRMC Only column of the Chapter 3: Package Files.
� Global clock (GC) pins in DDRMC Only nibbles include full access to clock management resources.
� HDIO banks are arranged in columns and separated into rows that are pitch-matched with adjacent PHY, clock management resources, and GT blocks.
� An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table 10.
Clocking � Each XPIO bank has four pairs of global clock (GC) inputs for four differential or four single-
ended clock inputs. Single-ended clock inputs should be connected to the P-side of the differential pair. � Each HDIO bank has two global clock (HDGC) inputs for two single-ended clock inputs, a pseudo-differential pair or a true-differential pair for a limited selection of I/O standards. � Clock signals are distributed through global buffers driving routing and distribution networks to reach any clock region, I/O, or GTY transceivers. � Global clock inputs can connect to MMCMs and PLLs within the XPIO bank or adjacent clock management resources
Processor Blocks � PMC MIO pins are in banks 500 and 501 � LPD MIO pins are in bank 502 � PMC dedicated pins are in bank 503
PCIe, CPM, Interlaken, and 100GE Integrated Blocks � PCIe: Integrated block for PCIe�. The PCIe blocks with an additional (Tandem) label support
tandem configuration.
� CPM: CCIX and PCIe� processor sub-system module
� ILKN: Interlaken block
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Chapter 2: Die Level Bank Numbering and Device Diagrams � MRMAC: 100G Ethernet block
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Device Diagrams Overview
The following figure shows an example diagram with a brief explanation for each component.
Figure 1: Example Device Diagram
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AA PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AB
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6 BG [R]
GTY Quad 205 X1Y5 BF [R]
GTY Quad 204 X1Y4 BE [R]
GTY Quad 203 X1Y3
BD [R] (RCAL)
GTY Quad 202 X1Y2
BC [R] (RCAL)
GTY Quad 201 X1Y1 BB [R]
GTY Quad 200 X1Y0 BA [R]
DDRMC Only (by nibble):
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
YYYYYYYYY YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
Transceiver Power Supply Group
Bank Type
Alphabetic Bank/Quad Designator. Corresponds to Columns in I/O Bank
and Transceiver Migration tables.
XPIO Bank Triplet
Boundary
Integrated Blocks and Transceiver XY Coordinates
XPIO has access to DDRMC only (Y) or full access to I/O logic resources (N), as shown for each nibble (9 nibbles per bank and 6 I/Os per nibble)
X22651-071320
The figures in this chapter show a die view of each device followed by a view with respect to each available package. The available resources by device and package are detailed in the Versal Architecture and Product Data Sheet: Overview (DS950).
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Chapter 2: Die Level Bank Numbering and Device Diagrams
VC1802 Bank Diagram Overview
Figure 2: VC1802 Banks
GTY Quad 106 X0Y6
GTY Quad 105 X0Y5 (RCAL)
GTY Quad 104 X0Y4 (RCAL)
GTY Quad 103 X0Y3
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5
GTY Quad 204 X1Y4
GTY Quad 203 X1Y3 (RCAL)
GTY Quad 202 X1Y2 (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO
XPIO
XPIO XPIO
XPIO
XPIO XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
DDRMC Only (by nibble):
YYYYYYYYY YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24037-052420
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Bank Diagram by Package for VC1802
Figure 3: VC1802 Banks in VIVA1596 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AB PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AA
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5 BD [R]
GTY Quad 204 X1Y4 BC [R]
GTY Quad 203 X1Y3
BB [R] (RCAL)
GTY Quad 202 X1Y2
BA [R] (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO Bank 700
A
XPIO Bank 701
B
XPIO Bank 702
C
XPIO Bank 703
D
XPIO Bank 704
XPIO Bank 705
XPIO Bank 706
E
XPIO Bank 707
F
XPIO Bank 708
G
XPIO Bank 709
XPIO Bank 710
XPIO Bank 711
DDRMC Only (by nibble): YYYYYYYYY
YYYYYYYYY
YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24036-052420
Figure 4: VC1802 Banks in VSVD1760 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5
GTY Quad 204 X1Y4 BB [R]
GTY Quad 203 X1Y3
BA [R] (RCAL)
GTY Quad 202 X1Y2 (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24038-052420
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Figure 5: VC1802 Banks in VSVA2197 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AA PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AB
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6 BG [R]
GTY Quad 205 X1Y5 BF [R]
GTY Quad 204 X1Y4 BE [R]
GTY Quad 203 X1Y3
BD [R] (RCAL)
GTY Quad 202 X1Y2
BC [R] (RCAL)
GTY Quad 201 X1Y1 BB [R]
GTY Quad 200 X1Y0 BA [R]
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY
YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN
YYYYYYYYY
X24039-052420
VC1902 Bank Diagram Overview
Figure 6: VC1902 Banks
GTY Quad 106 X0Y6
GTY Quad 105 X0Y5 (RCAL)
GTY Quad 104 X0Y4 (RCAL)
GTY Quad 103 X0Y3
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5
GTY Quad 204 X1Y4
GTY Quad 203 X1Y3 (RCAL)
GTY Quad 202 X1Y2 (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO
XPIO
XPIO XPIO
XPIO
XPIO XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
DDRMC Only (by nibble):
YYYYYYYYY YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24015-052420
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Bank Diagram by Package for VC1902
Figure 7: VC1902 Banks in VIVA1596 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AB PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AA
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5 BD [R]
GTY Quad 204 X1Y4 BC [R]
GTY Quad 203 X1Y3
BB [R] (RCAL)
GTY Quad 202 X1Y2
BA [R] (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO Bank 700
A
XPIO Bank 701
B
XPIO Bank 702
C
XPIO Bank 703
D
XPIO Bank 704
XPIO Bank 705
XPIO Bank 706
E
XPIO Bank 707
F
XPIO Bank 708
G
XPIO Bank 709
XPIO Bank 710
XPIO Bank 711
DDRMC Only (by nibble): YYYYYYYYY
YYYYYYYYY
YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24016-052020
Figure 8: VC1902 Banks in VSVD1760 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5
GTY Quad 204 X1Y4 BB [R]
GTY Quad 203 X1Y3
BA [R] (RCAL)
GTY Quad 202 X1Y2 (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO XPIO
XPIO XPIO
XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24035-052420
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Figure 9: VC1902 Banks in VSVA2197 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AA PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AB
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6 BG [R]
GTY Quad 205 X1Y5 BF [R]
GTY Quad 204 X1Y4 BE [R]
GTY Quad 203 X1Y3
BD [R] (RCAL)
GTY Quad 202 X1Y2
BC [R] (RCAL)
GTY Quad 201 X1Y1 BB [R]
GTY Quad 200 X1Y0 BA [R]
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY
YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN
YYYYYYYYY
X24034-052420
VM1802 Bank Diagram Overview
Figure 10: VM1802 Banks
GTY Quad 106 X0Y6
GTY Quad 105 X0Y5 (RCAL)
GTY Quad 104 X0Y4 (RCAL)
GTY Quad 103 X0Y3
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5
GTY Quad 204 X1Y4
GTY Quad 203 X1Y3 (RCAL)
GTY Quad 202 X1Y2 (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO
XPIO
XPIO XPIO
XPIO
XPIO XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
DDRMC Only (by nibble):
YYYYYYYYY YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24040-052420
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Bank Diagram by Package for VM1802
Figure 11: VM1802 Banks in VFVC1760 Package
GTY Quad 106 X0Y6 CD [LS]
GTY Quad 105 X0Y5
CC [LS] (RCAL) GTY Quad 104
X0Y4 CB [LS] (RCAL) GTY Quad 103
X0Y3 CA [LS]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AE PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AF
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
BG [RN]
GTY Quad 205 X1Y5
BF [RN]
GTY Quad 204 X1Y4
BE [RN]
GTY Quad 203 X1Y3
BD [RS] (RCAL)
GTY Quad 202 X1Y2
BC [RS] (RCAL)
GTY Quad 201 X1Y1 BB [RS]
GTY Quad 200 X1Y0 BA [RS]
XPIO XPIO
Bank 700 Bank 701
A
B
XPIO XPIO XPIO
Bank 702 Bank 703 Bank 704
C
AA
AB
XPIO
XPIO
Bank 705 Bank 706
AC
AD
XPIO XPIO Bank 707 Bank 708
XPIO
XPIO
XPIO
Bank 709 Bank 710 Bank 711
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24042-052520
Figure 12: VM1802 Banks in VSVD1760 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6
GTY Quad 205 X1Y5
GTY Quad 204 X1Y4 BB [R]
GTY Quad 203 X1Y3
BA [R] (RCAL)
GTY Quad 202 X1Y2 (RCAL)
GTY Quad 201 X1Y1
GTY Quad 200 X1Y0
XPIO XPIO
XPIO XPIO XPIO
XPIO XPIO
XPIO XPIO
XPIO XPIO XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN YYYYYYYYY
X24043-052520
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Chapter 2: Die Level Bank Numbering and Device Diagrams
Figure 13: VM1802 Banks in VSVA2197 Package
GTY Quad 106 X0Y6 CD [L]
GTY Quad 105 X0Y5
CC [L] (RCAL) GTY Quad 104
X0Y4 CB [L] (RCAL) GTY Quad 103
X0Y3 CA [L]
CPM4
LPDMIO Bank 502
PMCMIO/PMCDIO Bank 500
HDIO Bank 306
AA PCIE X0Y2
PCIE X0Y1
CPM4
CPM4
PMCDIO Bank 503
PMCMIO Bank 501
HDIO Bank 406
AB
PCIE X1Y2
MRMAC X0Y3
MRMAC X0Y2
PCIE X1Y0
MRMAC X0Y1
MRMAC X0Y0
GTY Quad 206 X1Y6 BG [R]
GTY Quad 205 X1Y5 BF [R]
GTY Quad 204 X1Y4 BE [R]
GTY Quad 203 X1Y3
BD [R] (RCAL)
GTY Quad 202 X1Y2
BC [R] (RCAL)
GTY Quad 201 X1Y1 BB [R]
GTY Quad 200 X1Y0 BA [R]
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO
XPIO XPIO
XPIO
XPIO
Bank 700 Bank 701 Bank 702 Bank 703 Bank 704 Bank 705 Bank 706 Bank 707 Bank 708 Bank 709 Bank 710 Bank 711
A
B
C
D
E
F
G
H
I
J
K
L
DDRMC Only (by nibble):
YYYYYYYYY
YYYYYYYYY
YYYYNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN NNNNNNNNN
YYYYYYYYY
X24041-052420
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Chapter 3: Package Files
Chapter 3
Package Files
About ASCII Package Files
The ASCII package files for each VersalTM ACAP include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor in fixed-width fonts. The information in each of the files includes: � Header with device/package name (family-device-package), date and time of creation,
package specification designator, and revision history � Seven columns containing data for each pin:
Pin--Pin location on the package Pin Name--The name of the assigned pin Bank--Bank number I/O Type--HDIO, XPIO, GTY, GTM, PMCMIO, PMCDIO, or LPDMIO depends on the I/O
type. For more information on the I/O type, see Versal ACAP SelectIO Resources Architecture Manual (AM010). Super logic region (SLR) number for SSI devices (not applicable for monolithic devices). XPIOPerf--Performance (HIGH, MEDIUM, or LOW) that the LPDDR4 interfaces are specified. See the device data sheet for performance definitions. DDRMC Only--For XPIO pins, YES specifies that the pin is supported for use in DDR applications only and does not include full access to XPIO logic resources. YES_PLUS_GC specifies the pin is supported for use in DDR applications and additionally has full access to clock management resources. NO specifies the pin has full access to XPIO logic resources. � Total number of pins in the package
Related Information ASCII Pinout Files
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Chapter 3: Package Files
Package Specifications Designations
Package specifications are designated as evaluation only, engineering sample, or production. Each designation is defined as follows.
Evaluation Only These package specifications are based on initial device specifications, package routability analysis and mechanical package construction. Package specifications with this designation are not stable and package pinouts are likely to change and these specifications should only be used for initial system level design feasibility.
Engineering Sample These package specifications are based on a released package design and validated with ES engineering sample (ES) devices. Package specifications with this designation are considered stable, however some pinout and mechanical specifications might change prior to the production release of the particular device. Package pinouts with this designation are to be used for PCB and Vivado� designs using ES devices.
Production These package specifications are released coincident with production release of a particular device. Customers receive formal notification of any subsequent changes.
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Chapter 3: Package Files
ASCII Pinout Files
Links to the ASCII pinout information device/package combinations are listed in the following table.
Note: All package files are ASCII files in TXT and CSV file format.
IMPORTANT! IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 14: Package/Device Pinout Files
Packages
SFVB625 VBVA1024 VFVB1024 VFVB1369 VFVF1369 VSVE1369 VSVG1369 VSVA1596 VIVA1596
VFVA1760 VFVC1760
VSVD1760
VSVA2197
VM1102 VC1352 VM1102 VM1302 VM1302 VC1352 VC1502 VC1502 VC1802
Footprint Compatible Devices
VC1502 VM1302 VM1402 VM1402 VC1702
VC1702 VC1902
VM1402 VM1502
VM1302 VM1502 Evaluation Only
VM1802
VM1402
VM1802 Engineering
Sample
VC1802
VM2602
VM2602
VM2902
Evaluation Only Evaluation Only
VC1902
VM1802
Engineering Sample
VM2502
VC1502
Evaluation Only Evaluation Only
VC1802
Engineering Sample
VC1902
Engineering Sample
Package Status
Evaluation Only Evaluation Only Evaluation Only Evaluation Only Evaluation Only Evaluation Only Evaluation Only Evaluation Only
Engineering Sample
Evaluation Only
Engineering Sample
Related Information Package Specifications Designations
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Chapter 4: Device Diagrams
Chapter 4
Device Diagrams
The diagrams in this chapter show top-view perspective of the package pinout of each VersalTM device/package combination. The following table is a cross reference to the device/package diagrams. The device diagram shows the location of each user I/O, PMCMIO, LPDMIO, PMCDIO, and GTY transceiver and the respective bank or GTY quad, as well as the location of every power pin in the package. See Package Specifications Designations for definitions of Evaluation Only, Engineering Sample, and Production device diagrams.
IMPORTANT! All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 15: Cross-Reference to Versal Device Diagrams by Package
Package
SFVB625 VBVA1024 VFVB1024 VFVF1369 VSVE1369 VSVG1369 VSVA1596 VIVA1596
VFVA1760 VFVC1760
VSVD1760
VM1102 Evaluation Only
VC1352 Evaluation Only
VM1102 Evaluation Only
VM1302 Evaluation Only
VC1352 Evaluation Only
VC1502 Evaluation Only
VC1502 Evaluation Only
VC1802 Engineering
Sample
VM1302 Evaluation Only
VM1502 Evaluation Only
VM1802 Engineering
Sample
Footprint Compatible Devices
VC1502 Evaluation Only
VM1302 Evaluation Only
VM1402 Evaluation Only
VC1702 Evaluation Only
VM1402 Evaluation Only
VC1702 Evaluation Only
VC1902 Engineering
Sample
VM1402 Evaluation Only
VM1802 Engineering
Sample
VC1802 Engineering
Sample
VM2602 Evaluation Only
VM2602 Evaluation Only
VC1902 Engineering
Sample
VM2902 Evaluation Only
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Chapter 4: Device Diagrams
Table 15: Cross-Reference to Versal Device Diagrams by Package (cont'd)
Package
VSVA2197
VM1802
Engineering Sample
Footprint Compatible Devices
VM2502 Evaluation Only
VC1502 Evaluation Only
VC1802
Engineering Sample
VC1902
Engineering Sample
VIVA1596 Package--VC1802
V
V V
V V
V
V V
Figure 14: VIVA1596 Package--VC1802 Device Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A
3
3
V
10 10 42
30 29 EO CK
PO PI DN 17
5 4 9 10
8
E
33
A
205
106
B
C
2
2
205
3 3
205
1
1
205
2
2
205
9
43 41 31 28
PU DI DO MS
18 16 6 3
9 10 8
9 8 44 40
27 26 M0 M1
M2 M3 19 15
2
7
7
6
3V0C6CO
22 106
E
11 106
3 3
106
B
2
2C
106
D
1 1
V
7768
39 32 25 18
10 9 2 1
14 7 1 5
64
00
V
1 1
D
205
106
106
E
0
0
205
F
3 3
204
0
0
205
V
56
51 45 38 33
19 17 11 8
0 20 13 8
3524
4V0C6CO
5
4 50 46
34 24 20 16
7 3 25 21
9032
E
22 105
33 105
V
3 3
105
0
0E
106
F
G
2
2
204
H
2
2
204
3
3
204
V
334
47 37 35 23
15 12 6 4
22 12 10 1
0
1
2 49 48 36
22 21 14 13
5 24 23 11
1
0
3V0C6CO
0 0
106
1 1
106
11 105
V
1 1
105
2
2G
105
H
J
1
1
204
K
V
0
0
204
1
1
204
120
4V0C6CO
0
E
00
105
0
0
J
105
3 3
K
104
L
0
0
V
204
2
2L
104
M
3
3
203
1 1
M
104
N3
3
V
203
0
0N
104
P
2
2
203
33
P
104
R
2
2
V
203
V
3
3R
103
T
1
1
203
SOC SOC
SOC SOC
22
T
104
U
1
1
V
1 1
203
205
SOC SOC
SOC SOC
G
E
11 104
V
2
2U
103
V
0
0
EE
RAM
203
RN VP
E
1 1
V
00
V
105
104
W0
0
203
V
0
0
205
VN RP
0
0
E
105
33 103
1
1W
103
Y
3
3
E
1
1
RAM
202
204
RR
1
1
V
22
Y
104
103
AA 3 3
V
0 0
202
204
0
0
E
104
11 103
V
0 0 AA
103
AB
2
2
E
1
1
RAM
202
203
1 1
103
V
00
103
AB
AC
2 2
202
AD
AE 1 1 202
AF
AG
0 0
202
AH
V
1
1
202
V
0
0
202
0 0
203 E
0 0
202 E
E 1 1 202 E
G
18 19
19 19
13 13
RAM RAM 20 21
SOC SOC
SOC
SOC SOC
SOC SOC
SOC
SOC SOC
22 22
18 18
RC
0 0
1
103
5V0C3CO
13 13 7
5
PR
AUX L P
5V0C3CO
5V0C2CO
17 25 7 0
INT
F S AUX
LP LP
5V0C2CO
17
25
11 3
INT INT
FP FP
5V0C0CO
5V0C0CO
12 24 24 11
21
F P
F P
F P
5V0C1CO
5V0C1CO
12
26 6 6
1 AC 5 AD
AE 0 AF 3 AG 2 AH
AJ
22 20
18 19
23 23
12 17
20 21
23 19
20 21
23 19
22 21
23 19 19 23
18
7V0C0CO
26
9 2 AJ
AK 22
20 21
23 21
18 12
17 22
18 23
19 20
21 23
19 22
18 23
19
19 23
21 18
15
15
7V0C0CO
9
8
AK
AL 7V0C8CO
7V0C8CO
21 23
21 18
15 15
22 14
18 13
14 14
12 13
20 20
18 13
22
21
14 14
8 10 4 AL
AM 7V0C8CO
15
15
17 13 22
16 16 14
16 14 12
17 13 16
15 12 13
16 14 14
17 13 22
20
20
16
16
7V0C0CO
10
4 AM
AN 16
12 17 13
22 20 20
14
7V0C7CO
16
15 12 17
16 15 25
17 17 16
15 12 17
13 13 17 17
3 3 1 1 AN
AP 16 14 12
25 25 26
24
25
7V0C7CO
26 24 15
7V0C6CO
7V0C6CO
26
24
25
7V0C3CO
26 24 15
12
7V0C2CO
14
15 12 12 4 2
5 5 AP
AR 14
26 26 24
26 24 25
4
7V0C7CO
26
24 25 25
26 24 8
7V0C3CO
7V0C3CO
26
24 25 25
7V0C2CO
14
15
24 4 2 0 0
AR
AT 10
8 9 11 24
7742
10 10 9 6
11
7V0C6CO
10
8
11 11 10 8
9
6
11
7V0C2CO
16 16 24 25
7V0C1CO
7V0C1CO
7V0C1CO
AT
AU 10 8 9
6 11 7 10
11 2 3 3
9 6 11 7
10 9 9 6
10 8 9 6
11 7 22 18
26 25 7 7
11 AU
AV
4226
7 10 6 11
0088
3072
3677
4337
22 18 19 26
8 6 6 11 AV
AW
4
3051
8651
4230
1423
5142
0 5 1 20
19 23 10 8
9
AW
AY
305
1899
5142
5514
0051
2051
20 21 21 23
10 9
AY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
103 GTY 104 GTY 105 GTY 106 GTY 202 GTY 203 GTY 204 GTY 205 GTY 306 HDIO 406 HDIO 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 706 XPIO 707 XPIO 708 XPIO
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
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Chapter 4: Device Diagrams
VIVA1596 Package--VC1902
V
V V
V V
V
V V
Figure 15: VIVA1596 Package--VC1902 Device Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A
3
3
V
10 10 42
30 29 EO CK
PO PI DN 17
5 4 9 10
8
E
33
A
205
106
B
C2
2
205
3 3
205
1
1
205
2
2
205
9
43 41 31 28
PU DI DO MS
18 16 6 3
9 10 8
9 8 44 40
27 26 M0 M1
M2 M3 19 15
2
7
7
6
3V0C6CO
22 106
E
11 106
3 3
106
B
2
2C
106
D
1 1
V
7768
39 32 25 18
10 9 2 1
14 7 1 5
64
00
V
1 1
D
205
106
106
E
0
0
205
F
3 3
204
0
0
205
V
56
51 45 38 33
19 17 11 8
0 20 13 8
3524
4V0C6CO
5
4 50 46
34 24 20 16
7 3 25 21
9032
E
22 105
33 105
V
3 3
105
0
0E
106
F
G2
2
204
H
2
2
204
3
3
204
V
334
47 37 35 23
15 12 6 4
22 12 10 1
0
1
2 49 48 36
22 21 14 13
5 24 23 11
1
0
3V0C6CO
0 0
106
1 1
106
11 105
V
1 1
105
2
2G
105
H
J1
1
204
K
V
0
0
204
1
1
204
120
4V0C6CO
0
E
00
105
0
0
J
105
3 3
K
104
L
0
0
V
204
2
2
L
104
M
3
3
203
1 1
M
104
N3
3
V
203
0
0N
104
P
2
2
203
33
P
104
R
2
2
V
203
V
3
3R
103
T
1
1
203
SOC SOC
SOC SOC
22
T
104
U1
1
V
1 1
203
205
SOC SOC
SOC SOC
G
E
11 104
V
2
2U
103
V
0
0
EE
RAM
203
RN VP
E
1 1
V
00
V
105
104
W0
0
203
V
0
0
205
VN RP
0
0
E
105
33 103
1
1W
103
Y
3
3
E
1
1
RAM
202
204
RR
1
1
V
22
Y
104
103
AA 3 3
V
0 0
202
204
0
0
E
104
11 103
V
0 0 AA
103
AB
2
2
E
1
1
RAM
202
203
1 1
103
V
00
103
AB
AC
2 2
202
AD
AE 1 1 202
AF
AG
0 0
202
AH
V
1
1
202
V
0
0
202
0 0
203 E
0 0
202 E
E 1 1 202 E
G
18 19
19 19
13 13
RAM RAM 20 21
SOC SOC
SOC
SOC SOC
SOC SOC
SOC
SOC SOC
22 22
18 18
RC
0 0
1
103
5V0C3CO
13 13 7
5
PR
AUX L P
5V0C3CO
5V0C2CO
17 25 7 0
INT
F S AUX
LP LP
5V0C2CO
17
25
11 3
INT INT
FP FP
5V0C0CO
5V0C0CO
12 24 24 11
21
F P
F P
F P
5V0C1CO
5V0C1CO
12
26 6 6
1 AC 5 AD
AE 0 AF 3 AG 2 AH
AJ
22 20
18 19
23 23
12 17
20 21
23 19
20 21
23 19
22 21
23 19 19 23
18
7V0C0CO
26
9 2 AJ
AK 22
20 21
23 21
18 12
17 22
18 23
19 20
21 23
19 22
18 23
19
19
23
21
18
15
15
7V0C0CO
9
8
AK
AL 7V0C8CO
7V0C8CO
21 23
21 18
15 15
22 14
18 13
14 14
12 13
20 20
18 13
22
21
14 14
8 10 4 AL
AM 7V0C8CO
15
15
17 13 22
16 16 14
16 14 12
17 13 16
15 12 13
16 14 14
17 13 22
20
20
16
16
7V0C0CO
10
4 AM
AN 16
12 17 13
22 20 20
14 7V0C7CO
16
15 12 17
16 15 25
17 17 16
15 12 17
13 13 17 17
3 3 1 1 AN
AP 16 14 12
25 25 26
24
25
7V0C7CO
26 24 15
7V0C6CO
7V0C6CO
26
24
25
7V0C3CO
26 24 15
12
7V0C2CO
14
15 12 12 4 2
5 5 AP
AR 14
26 26 24
26 24 25
4
7V0C7CO
26
24 25 25
26 24 8
7V0C3CO
7V0C3CO
26
24 25 25
7V0C2CO
14
15
24 4 2 0 0
AR
AT 10
8 9 11 24
7742
10 10 9 6
11
7V0C6CO
10
8
11 11 10 8
9
6
11
7V0C2CO
16 16 24 25
7V0C1CO
7V0C1CO
7V0C1CO
AT
AU 10 8 9
6 11 7 10
11 2 3 3
9 6 11 7
10 9 9 6
10 8 9 6
11 7 22 18
26 25 7 7
11 AU
AV
4226
7 10 6 11
0088
3072
3677
4337
22 18 19 26
8 6 6 11 AV
AW
4
3051
8651
4230
1423
5142
0 5 1 20
19 23 10 8
9
AW
AY
305
1899
5142
5514
0051
2051
20 21 21 23
10 9
AY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
103 GTY 104 GTY 105 GTY 106 GTY 202 GTY 203 GTY 204 GTY 205 GTY 306 HDIO 406 HDIO 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 706 XPIO 707 XPIO 708 XPIO
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
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Chapter 4: Device Diagrams
VFVC1760 Package--VM1802
Figure 16: VFVC1760 Package--VM1802 Device Diagram
V
V V V V V V
12
A
B
Cn n
D
Enn
F
G
3
3
206
H
J
2
2
206
K
L
0
0
206
M
N2
2
205
P
R
1
1
205
T
U
0
0
205
V
W2
2
204
Y
AA
0 0
204
AB
AC
3 3
203
AD
AE 2 2 203
AF
AG
0 0
203
AH
AJ 2 2 202
AK
AL AM
1 1
202
AN
0 0
202
AP
AR 2 2 201
AT
AU
0 0
201
AV
AW AY
2 2
200
BA
BB
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
nn
2
0315
1503
2 4 11 6
3222
4011
nn
A
nn
2403
1515
0324
11 6 0 3
2403
5
nn
B
nn
48
10 6 9 7
11 6 9 8
10 7 9 9
0588
935
nn
n nC
nn nn
2
2
206
1 1
206
3 3
205
2
2
205
0
0
205
3 3
204
1 1
204
0
0
204
2
2
203
1 1
203
3 3
202
2
2
202
0
0
202
3 3
201
1 1
201
3 3
200
1 1
200
0 0
200
345
nn
3
3
206
1
1
206
0
0
206
3
3
205
1
1
205
3
3
204
2
2
204
1
1
204
3
3
203
1
1
203
0
0
203
3
3
202
1
1
202
3
3
201
2
2
201
1
1
201
3
3
200
1
1
200
67
8 10 6 9
7 7 11 6
9 8 10 7
10 1 5 4
10 6 9 7
26 24 25
7V0C6CO
11
11
7
24 24 26 26
8 8 10 1
4
7V0C3CO
10
6
7 11
26
24
25
7V0C6CO
7V0C6CO
25
25
7V0C5CO
7V0C5CO
7V0C5CO
16
7V0C4CO
7V0C4CO
24
26
26
7V0C3CO
26 24 25 11
14 14 16 12
15 17 17 13
12
15
16
7V0C4CO
25 25 24 17
16
7V0C3CO
26
24
25
16 12 15 13
13 17 12 15
19 23 23 13
12 17 16 12
13 17 17
n
nn
D
nn
n nE
n
nn
F
nn
n
n nG
nnn
H
E
22 18 21
23 13 19 17
14 14 19 18
13 15 15 12
12 15 15 13
nn
n nJ
nn
22
18 21 23 19
18 21 20 20
21 18 14 14
14 14 22 22
19 23
n
nn
K
E
20 20 19 19
23 23 18 21
22 22 20 21
16 16 20 20
18 21 19 23
nn
n nL
nn
E
1 1
206 E
0 0
206 E
1 1
205 E
0 0
205 E
1 1
204 E
0 0
204 E
1 1
203 E
0 0
203 E
1 1
202 E
0 0
202 E
0 0
201 E
G
0
0
201
V V
VV V
VV V
VV V
VV V
VV V
VV V
VV V
V
1 1
201 E 1
1 200 E 0
0 200 E
2446
8 8 22 22
20 7 7 5
2 0 18 21
n
213
6779
10 10 9 8
5420
0
4V0C6CO
1
3
5
5
4V0C6CO
9
10 10
9
3V0C6CO
8
6
6
4
1
n nnnn
0
331
nnn
3V0C6CO
n
nn
n
SOC SOC
SOC SOC
nnn
n
n
n
n
n n
22 22 20
RAM
SOC SOC
SOC SOC
RAM
RN VP
RAM
VN RP
n
RR
n
RAM
n
SOC SOC
SOC
SOC SOC
n
RAM
SOC SOC
SOC
SOC SOC
RC AUX n
AUX L P
21 19
21
19 23
19 13
18 23
23 19
13 17
F S
L P
PR
22
21 INT
FP FP
22 21
INT INT
F P
n 0
0 106 E 0
0 105
0 0
104
0 0
103
1 1
106 E
1 1
105 E
1 1
104 E
1 1
103 E
5V0C3CO
5V0C3CO
5V0C2CO
L P
5V0C2CO
10
F P
5V0C0CO
11 9
5V0C0CO
5V0C1CO
12
F P
5V0C1CO
13
8
20 14
18 23
18 18
17 12
20 18
23 19
23 19 18 14 7
33 106
V
11 106 V
33 105
V
22 105 V
11 105
V
00 105 V
22 104
V
G
0
1
2
14 12
17 20
21 15
12 20
18 23
19 24 22 20 17
63
16
12 17 13
20 21 15
14 16 14
12 12 13 25 21
16 15 5 4
16 15 15
13 22 22
16 16 14
16 14 15
13
43 42 30 29
16
26
24
25
7V0C2CO
26 24 25
7V0C1CO
26
24
15 17 17 51 44 41
28 17 15
26 24 25
7V0C2CO
26
24
25
7V0C1CO
7V0C1CO
26 24 25
7V0C0CO
50
40 31 27 18
10
6
11
7V0C2CO
11
7422
8
25
7V0C0CO
7V0C0CO
49 45 39 32
19 14 7
10 9 6 11
10 11 7 4
1 10 8 9
6 11 7 46
33 26 20 13
3 3
106
22 106 V
00 106
3 3
105
1 1
105
3 3
104
33 104 V
11 104
00 104
V
33 103 V
22 103
V
11 103 V
00 103
M
2
2N
106
P
1
1R
106
T
0
0U
106
V
2
2W
105
Y
0 0
105
AA
AB
2 2 AC 104 AD
1 1 AE 104 AF
0 0 AG 104 AH
3 3 AJ 103 AK
2 2
103
AL AM
1 1 AN 103 AP
0 0 AR 103 AT
DN PI AU
6
EO PU PO AV
5 M0 M1 MS
AW
2
2
200
4889
7 7 10 6
3 3 1 10
9 6 11 7
47 38 34 25
12 8 4 0
DO CK AY
42
3051
9605
4230
5 1 48 37
24 21 11 9
1 M2 DI
BA
0
0
2305
1889
0542
3051
36 35 23 22
10 3 2 M3
BB
200
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
V
V V
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 200 GTY 201 GTY 202 GTY 203 GTY 204 GTY 205 GTY 206 GTY 306 HDIO 406 HDIO 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO
X24169-070120
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Chapter 4: Device Diagrams
VSVD1760 Package--VC1802
Figure 17: VSVD1760 Package--VC1802 Device Diagram
V
V V
V V
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
1
3
0
1
2
3
0
203
203
204
204
204
204
203
B
1
3
0
1
2
3
0
E
C
0
2
203
203
D
0
2
3
V0
1
V2
3
EG
203
204
204
204
204
E
3
0V
1
2E
3
F0 203
G
0
1 203
1V
2
V
203
2
49
10 16 16 14
22 22
50
H
10 26
15
14 21
20 51
J
4488
6 24 26 15 12 12
21 20
K2 2
3996
24
13
23 18
19
L0553
7 7 25 25 17 17 13 23
18 19
M0
1
N 10 10 11
1 11 11
7V1C1CO
7V1C1CO
7V1C1CO
P
8 8 11 24
26
R99
7 24 26 25
T3 6 6 7
25
U3
2 2 14 15 15 17 13 20
22 22
V50 0
16 14 17
13
20 21
W Y4 AA 2
5 1 4 16
12 12 23 18 18
21
1
4
7V1C0CO
7V1C0CO
7V1C0CO
23
19 19
4 10 10
8 26 16 16
20 22
AB 2
3 9 9 8 26
14 14 20
22
AC 0 0 3
6 24 24 12 15 15
21 21
AD
5 5 11 6
12
18 18
AE 1 1
7
11
25
25
7V0C9CO
17
17
19
23
AF 4 4 2 7
7V0C9CO
7V0C9CO
13 13
19 23
AG 3
2 10 10 8 26 26 14
16 22
AH 0 3 9
8 24
14
16 15
22 20
20
AJ
0966
24 12 12 15
21 20
22 20
AK 5 5
11 11 25 25
17
13 21
18 22
AL 1 1 7 7
7V0C8CO
7V0C8CO
7V0C8CO
17
13
23
19 18
21
AM 10
6 6 7 26
7V0C7CO
22
23 19
16 15
AN 8 10 9
7
24
26
7V0C7CO
22
20 20 19
16 14
AP
8 9 11 11
24
21 21 18
23 19 14
AR 5 5
0
3
4
25
7V0C7CO
16
15 18 23
26 24
AT 1 1 0 3
4 25
16 15 12
13 13 26
AU 2
4 10 2 2
14 14
12 17 17
10 10
AV 3 2 4
10 8 26 26
16 16 22 22
89
AW
3098
24 24 14 14
20 20 21 8
1 203
1
1 204
1
0 204
0
26
27
48 38 37 28
47 39 36
46
35 29
45 40 34 30
44 41
31
43 42 33 32
SOC SOC RAM SOC SOC
RAM
RAM
RAM SOC SOC
RAM SOC SOC
23
19 19
23 19
21 18
22
18
13 22
17 13
15
17 20
12
12
7V0C5CO
24
7V0C5CO
26
25
25
7V0C5CO
9
11 24
6 11
7
6776
PI
M0 23 13 12 0
PO CK M1 22
11 1
DI DO
21 14 10 2
MS M2 20 15
3
DN PU M3
16 9 4
EO
24 19 17 8
18 17 25 18
75
25 19 16
10 4 3 6
24
15 11 9 5
0
23 20 14 12
621
22 21
13 8 7
SOC SOC SOC SOC
RN VP VN RP RR
SOC SOC
13 19 13
SOC SOC
PR F S
RC AUX L P
5V0C3CO
5V0C3CO
L P
5V0C2CO
L P
5V0C0CO
5V0C2CO
5V0C0CO
19
19
SOC SOC
AUX
INT F P
23 23
INT INT
F P
5V0C1CO
18
22 18
F P
F P
5V0C1CO
18
17 22
18 19
22 21
20
23
17 12
20 21
19 22
21 20
23 12
20 21
23 23
13 12
18 18
15 16
15 17
13 17
12
21
14 15 16
15 12 17
17 14 14
20 21 14
14 14 12
13 13 19
21
26
16
16
7V0C3CO
26 24 25
19 23 18
24
25
7V0C4CO
7V0C3CO
7V0C3CO
26
24 25 23
18
25
7V0C4CO
4
10
997
19 19 13
7
11
7V0C4CO
4 10 8 6
7 23 23 13
11 2 2 3
8 6 11 11
18 18
V 22 106 V 00 106
V 22 105 V 00 105
V 1
1 106
E G E 1
1 103 E 0
0 103
33 106
11 106 V
33 105
11 105 V
33 104
V 0
0 106
1 1
105
0 0
105 E 1
1 104 E 0
0 104 E
11 103 V
3 3
106
1 1
106
3 3
105
1 1
105
3 3
104
22 104 V
11 104
V 00 104 V 33 103
V 22 103 V 00 103
17 13 13 25 7 7
17
25
11 1
12 12 24 24 11 6
15
26 6 9 0
15
14
26
7V0C0CO
9
2
14
7V0C0CO
10 8 8
16
16 7V0C0CO
10
33
15
25 4 2
15 16 16 25 4 2 0
24 24
7
6
21 20
26 7 11 6
20
26
7V0C1CO
11 8
22 22
7V0C1CO
7V0C1CO
8
17 25
7 7 11
17 24 25 6
11
12 12
24 9 6 3
A
B
2
2C
106
D
0
0E
106
F
2
2G
105
H
0
0
J
105
K
2
2
L
104
M
1
1N
104
P
0
0R
104
T
3
3U
103
V
2
2W
103
Y
1 1
103
AA
AB
0 0 AC 103 AD
1 5 AE
0 5 AF
3
AG
2 3 AH
4 AJ
1 4 AK
1 5 AL
5
AM
0 9 AN
9 AP
10 10 AR
1 1 AT
5
AU
0 5 AV
0 AW
AY 5 0
9 6 7 25
15 15 12 18
21 4 3 3
1699
5343
1 1 21 21
15 15 26 26
9 3 2 2 AY
BA
516
7
25
7V0C6CO
17
12 18 23 23
4051
10 8 0 5
4230
22 20 14 14
7V0C2CO
7V0C2CO
8
8
4
BA
BB
1
11
11 7V0C6CO
7V0C6CO
17
13
13
19 19 2 2
0 5 10 8
0112
0 5 5 22
20
16
16 7V0C2CO
10 10 4
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 203 GTY 204 GTY 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO 707 XPIO 708 XPIO 709 XPIO 710 XPIO 711 XPIO
X24168-070120
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Chapter 4: Device Diagrams
VSVD1760 Package--VC1902
Figure 18: OLD VSVD1760 Package--VC1902 Device Diagram
V
V V
V V
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
1
3
0
1
2
3
0
203
203
204
204
204
204
203
B
1
3
0
1
2
3
0
E
C
0
2
203
203
D
0
2
3
V0
1
V2
3
EG
203
204
204
204
204
E
3
0V
1
2E
3
F0 203
G
0
1 203
1V
2
V
203
2
49
10 16 16 14
22 22
50
H
10 26
15
14 21
20 51
J
4488
6 24 26 15 12 12
21 20
K2 2
3996
24
13
23 18
19
L0553
7 7 25 25 17 17 13 23
18 19
M0
1
N 10 10 11
1 11 11
7V1C1CO
7V1C1CO
7V1C1CO
P
8 8 11 24
26
R99
7 24 26 25
T3 6 6 7
25
U3
2 2 14 15 15 17 13 20
22 22
V50 0
16 14 17
13
20 21
W Y4 AA 2
5 1 4 16
12 12 23 18 18
21
1
4
7V1C0CO
7V1C0CO
7V1C0CO
23
19 19
4 10 10
8 26 16 16
20 22
AB 2
3 9 9 8 26
14 14 20
22
AC 0 0 3
6 24 24 12 15 15
21 21
AD
5 5 11 6
12
18 18
AE 1 1
7
11
25
25
7V0C9CO
17
17
19
23
AF 4 4 2 7
7V0C9CO
7V0C9CO
13 13
19 23
AG 3
2 10 10 8 26 26 14
16 22
AH 0 3 9
8 24
14
16 15
22 20
20
AJ
0966
24 12 12 15
21 20
22 20
AK 5 5
11 11 25 25
17
13 21
18 22
AL 1 1 7 7
7V0C8CO
7V0C8CO
7V0C8CO
17
13
23
19 18
21
AM 10
6 6 7 26
7V0C7CO
22
23 19
16 15
AN 8 10 9
7
24
26
7V0C7CO
22
20 20 19
16 14
AP
8 9 11 11
24
21 21 18
23 19 14
AR 5 5
0
3
4
25
7V0C7CO
16
15 18 23
26 24
AT 1 1 0 3
4 25
16 15 12
13 13 26
AU 2
4 10 2 2
14 14
12 17 17
10 10
AV 3 2 4
10 8 26 26
16 16 22 22
89
AW
3098
24 24 14 14
20 20 21 8
1 203
1
1 204
1
0 204
0
26
27
48 38 37 28
47 39 36
46
35 29
45 40 34 30
44 41
31
43 42 33 32
SOC SOC RAM SOC SOC
RAM
RAM
RAM SOC SOC
RAM SOC SOC
23
19 19
23 19
21 18
22
18
13 22
17 13
15
17 20
12
12
7V0C5CO
24
7V0C5CO
26
25
25
7V0C5CO
9
11 24
6 11
7
6776
PI
M0 23 13 12 0
PO CK M1 22
11 1
DI DO
21 14 10 2
MS M2 20 15
3
DN PU M3
16 9 4
EO
24 19 17 8
18 17 25 18
75
25 19 16
10 4 3 6
24
15 11 9 5
0
23 20 14 12
621
22 21
13 8 7
SOC SOC SOC SOC
RN VP VN RP RR
SOC SOC
13 19 13
SOC SOC
PR F S
RC AUX L P
5V0C3CO
5V0C3CO
L P
5V0C2CO
L P
5V0C0CO
5V0C2CO
5V0C0CO
19
19
SOC SOC
AUX
INT F P
23 23
INT INT
F P
5V0C1CO
18
22 18
F P
F P
5V0C1CO
18
17 22
18 19
22 21
20
23
17 12
20 21
19 22
21 20
23 12
20 21
23 23
13 12
18 18
15 16
15 17
13 17
12
21
14 15 16
15 12 17
17 14 14
20 21 14
14 14 12
13 13 19
21
26
16
16
7V0C3CO
26 24 25
19 23 18
24
25
7V0C4CO
7V0C3CO
7V0C3CO
26
24 25 23
18
25
7V0C4CO
4
10
997
19 19 13
7
11
7V0C4CO
4 10 8 6
7 23 23 13
11 2 2 3
8 6 11 11
18 18
V 22 106 V 00 106
V 22 105 V 00 105
V 1
1 106
E G E 1
1 103 E 0
0 103
33 106
11 106 V
33 105
11 105 V
33 104
V 0
0 106
1 1
105
0 0
105 E 1
1 104 E 0
0 104 E
11 103 V
3 3
106
1 1
106
3 3
105
1 1
105
3 3
104
22 104 V
11 104
V 00 104 V 33 103
V 22 103 V 00 103
17 13 13 25 7 7
17
25
11 1
12 12 24 24 11 6
15
26 6 9 0
15
14
26
7V0C0CO
9
2
14
7V0C0CO
10 8 8
16
16 7V0C0CO
10
33
15
25 4 2
15 16 16 25 4 2 0
24 24
7
6
21 20
26 7 11 6
20
26
7V0C1CO
11 8
22 22
7V0C1CO
7V0C1CO
8
17 25
7 7 11
17 24 25 6
11
12 12
24 9 6 3
A
B
2
2C
106
D
0
0E
106
F
2
2G
105
H
0
0
J
105
K
2
2
L
104
M
1
1N
104
P
0
0R
104
T
3
3U
103
V
2
2W
103
Y
1 1
103
AA
AB
0 0 AC 103 AD
1 5 AE
0 5 AF
3
AG
2 3 AH
4 AJ
1 4 AK
1 5 AL
5
AM
0 9 AN
9 AP
10 10 AR
1 1 AT
5
AU
0 5 AV
0 AW
AY 5 0
9 6 7 25
15 15 12 18
21 4 3 3
1699
5343
1 1 21 21
15 15 26 26
9 3 2 2 AY
BA
516
7
25
7V0C6CO
17
12 18 23 23
4051
10 8 0 5
4230
22 20 14 14
7V0C2CO
7V0C2CO
8
8
4
BA
BB
1
11
11
7V0C6CO
7V0C6CO
17
13
13
19 19 2 2
0 5 10 8
0112
0 5 5 22
20
16
16 7V0C2CO
10 10 4
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE#
EO ERROR_OUT
PO RTC_PADO
PI RTC_PADI
PU PUDC_B
DN RC PR
rDONE
REF_CLK POR_B
CK TCK
DI TDI
DO TDO
MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 203 GTY 204 GTY 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO 707 XPIO 708 XPIO 709 XPIO 710 XPIO 711 XPIO
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Chapter 4: Device Diagrams
VSVD1760 Package--VM1802
Figure 19: VSVD1760 Package--VM1802 Device Diagram
V
V V
V V
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
1
3
0
1
2
3
0
203
203
204
204
204
204
203
B
1
3
0
1
2
3
0
E
C
0
2
203
203
D
0
2
3
V0
1
V2
3
EG
203
204
204
204
204
E
3
0V
1
2E
3
F0 203
G
0
1 203
1V
2
V
203
2
49
10 16 16 14
22 22
50
H
10 26
15
14 21
20 51
J
4488
6 24 26 15 12 12
21 20
K2 2
3996
24
13
23 18
19
L0553
7 7 25 25 17 17 13 23
18 19
M0
1
N 10 10 11
1 11 11
7V1C1CO
7V1C1CO
7V1C1CO
P
8 8 11 24
26
R99
7 24 26 25
T3 6 6 7
25
U3
2 2 14 15 15 17 13 20
22 22
V50 0
16 14 17
13
20 21
W Y4 AA 2
5 1 4 16
12 12 23 18 18
21
1
4
7V1C0CO
7V1C0CO
7V1C0CO
23
19 19
4 10 10
8 26 16 16
20 22
AB 2
3 9 9 8 26
14 14 20
22
AC 0 0 3
6 24 24 12 15 15
21 21
AD
5 5 11 6
12
18 18
AE 1 1
7
11
25
25
7V0C9CO
17
17
19
23
AF 4 4 2 7
7V0C9CO
7V0C9CO
13 13
19 23
AG 3
2 10 10 8 26 26 14
16 22
AH 0 3 9
8 24
14
16 15
22 20
20
AJ
0966
24 12 12 15
21 20
22 20
AK 5 5
11 11 25 25
17
13 21
18 22
AL 1 1 7 7
7V0C8CO
7V0C8CO
7V0C8CO
17
13
23
19 18
21
AM 10
6 6 7 26
7V0C7CO
22
23 19
16 15
AN 8 10 9
7
24
26
7V0C7CO
22
20 20 19
16 14
AP
8 9 11 11
24
21 21 18
23 19 14
AR 5 5
0
3
4
25
7V0C7CO
16
15 18 23
26 24
AT 1 1 0 3
4 25
16 15 12
13 13 26
AU 2
4 10 2 2
14 14
12 17 17
10 10
AV 3 2 4
10 8 26 26
16 16 22 22
89
AW
3098
24 24 14 14
20 20 21 8
1 203
1
1 204
1
0 204
0
26
27
48 38 37 28
47 39 36
46
35 29
45 40 34 30
44 41
31
43 42 33 32
SOC SOC RAM SOC SOC
RAM
RAM
RAM SOC SOC
RAM SOC SOC
23
19 19
23 19
21 18
22
18
13 22
17 13
15
17 20
12
12
7V0C5CO
24
7V0C5CO
26
25
25
7V0C5CO
9
11 24
6 11
7
6776
PI
M0 23 13 12 0
PO CK M1 22
11 1
DI DO
21 14 10 2
MS M2 20 15
3
DN PU M3
16 9 4
EO
24 19 17 8
18 17 25 18
75
25 19 16
10 4 3 6
24
15 11 9 5
0
23 20 14 12
621
22 21
13 8 7
SOC SOC SOC SOC
RN VP VN RP RR
SOC SOC
13 19 13
SOC SOC
PR F S
RC AUX L P
5V0C3CO
5V0C3CO
L P
5V0C2CO
L P
5V0C0CO
5V0C2CO
5V0C0CO
19
19
SOC SOC
AUX
INT F P
23 23
INT INT
F P
5V0C1CO
18
22 18
F P
F P
5V0C1CO
18
17 22
18 19
22 21
20
23
17 12
20 21
19 22
21 20
23 12
20 21
23 23
13 12
18 18
15 16
15 17
13 17
12
21
14 15 16
15 12 17
17 14 14
20 21 14
14 14 12
13 13 19
21
26
16
16
7V0C3CO
26 24 25
19 23 18
24
25
7V0C4CO
7V0C3CO
7V0C3CO
26
24 25 23
18
25
7V0C4CO
4
10
997
19 19 13
7
11
7V0C4CO
4 10 8 6
7 23 23 13
11 2 2 3
8 6 11 11
18 18
V 22 106 V 00 106
V 22 105 V 00 105
V 1
1 106
E G E 1
1 103 E 0
0 103
33 106
11 106 V
33 105
11 105 V
33 104
V 0
0 106
1 1
105
0 0
105 E 1
1 104 E 0
0 104 E
11 103 V
3 3
106
1 1
106
3 3
105
1 1
105
3 3
104
22 104 V
11 104
V 00 104 V 33 103
V 22 103 V 00 103
17 13 13 25 7 7
17
25
11 1
12 12 24 24 11 6
15
26 6 9 0
15
14
26
7V0C0CO
9
2
14
7V0C0CO
10 8 8
16
16 7V0C0CO
10
33
15
25 4 2
15 16 16 25 4 2 0
24 24
7
6
21 20
26 7 11 6
20
26
7V0C1CO
11 8
22 22
7V0C1CO
7V0C1CO
8
17 25
7 7 11
17 24 25 6
11
12 12
24 9 6 3
A
B
2
2C
106
D
0
0E
106
F
2
2G
105
H
0
0
J
105
K
2
2
L
104
M
1
1N
104
P
0
0R
104
T
3
3U
103
V
2
2W
103
Y
1 1
103
AA
AB
0 0 AC 103 AD
1 5 AE
0 5 AF
3
AG
2 3 AH
4 AJ
1 4 AK
1 5 AL
5
AM
0 9 AN
9 AP
10 10 AR
1 1 AT
5
AU
0 5 AV
0 AW
AY 5 0
9 6 7 25
15 15 12 18
21 4 3 3
1699
5343
1 1 21 21
15 15 26 26
9 3 2 2 AY
BA
516
7
25
7V0C6CO
17
12 18 23 23
4051
10 8 0 5
4230
22 20 14 14
7V0C2CO
7V0C2CO
8
8
4
BA
BB
1
11
11
7V0C6CO
7V0C6CO
17
13
13
19 19 2 2
0 5 10 8
0112
0 5 5 22
20
16
16 7V0C2CO
10 10 4
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 203 GTY 204 GTY 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO 707 XPIO 708 XPIO 709 XPIO 710 XPIO 711 XPIO
X24175-070320
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Chapter 4: Device Diagrams
VSVA2197 Package--VC1802
Figure 20: VSVA2197 Package--VC1902 Device Diagram
V
V V
V V V
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
A
B
C
D
0
0
206
E
F
1
1
205
G
H2
2
204
J
K
0
0
204
L
M2
2
203
N
P
0
0
203
R
T
2
2
202
U
V
0
0
202
W
Y
2
2
201
AA
AB 0 0 201
AC
AD
2 2
200
AE
AF 0 0 200
AG
AH 2 2
AJ
3
AK 0 0
AL 5 5
AM 10
AN 8 10
2 2
206 3
3 205 0
0 205 1
1 204 3
3 203 1
1 203 3
3 202 1
1 202
3 3
206 1
1 206 2
2 205 3
3 204
0
0
204
2
2
203
0
0
203
2
2
202
2
2
206
0
0
206
2
2
205
0
0
205
2
2
204
3
3
203
1
1
203
3
3
202
1
1
202
1
1
206
3
3
205
1
1
205
3
3
204
1
1
204
3
3
206
0 0
206 E
0 0
205 E
0 0
204 E
0 0
203 E
0 0
202
E 1 1 206 E 1 1 205 E 1 1 204
1 1
203
1 1
202
1 1
201
46 45 35 34
47
36 33 26
48 44 37
27
43 38 32 28
49 42
31 29
50 41 39 30
51
40 9 10
779
10
4V0C6CO
5
6
8
8
35
64
1324
1
4V0C6CO
2
0
0
PO
EO DN 23 14
54
PI DI PU
22 15 13 6
DO M0 24 21
12 7 3
MS CK
25 20 16 11
M3 M2 M1 4
17 10 8
18
5 3 0 18
9
19 17 6
1 19 10 10
16 7 2 7
88
20 15
7
9
9
4
3V0C6CO
21 14 8 3
564
25 22
9356
0
24 23
13
10
3V0C6CO
1
2
2
0
12 11
1
0 1 2
1 1
106 E 0
0 106 E 1
1 105 E 0
0 105 E 1
1 104 E 0
0 104 E 1
1 103
22 106 V
11 106
V
00 106 V
22 105
V
00 105 V
33 104
V
22 104 V
00 104
V
33 106
3 3
106
1 1
106
33 105
11 105
1 1
105
3 3
104
11 104
33 103
0
0
202
3 3
201
3
3
E
V
n
201
2
2
201
GVV
1 1
201
1
1
E
V
n
201
0
0
201
0
0
V
V
201
3 3
200
3
3
E
V
n
200
2
2
200
1
1
V
V
200
1 1
200
1
1
E
V
n
200
0
0
200
0
0
V
V
200
4
n
4
8 10 10 26 14 16 16 22 22
20
398
26
14
21
18 20 n
9 6 6 24 24 15 15 12
21 18
1 11
7 25
7V1C1CO
12 17 23
19 23
6
1
11
7
25
7V1C1CO
7V1C1CO
13
13
17
23 19
23 19
RAM
SOC SOC SOC SOC
SOC SOC SOC SOC
RAM
RAM
RAM
SOC SOC
SOC
SOC SOC
RAM
SOC SOC
SOC
SOC SOC
13 13
19 19
20 23
19 23
0 0
103
22 103
V
3 3
103
RN VP VN RP RR
G
19
13
11 103
V
00 103
1 1
103
5V0C3CO 19 23 23 13 17 25 25
7
1
RC
PR
5V0C3CO
18
17
24
7 11
F S
L P
5V0C2CO 18 21 12 12 15 26 24 11
AUX
L P
5V0C2CO
20
21
15
26 6 9
AUX
F P
L P
22 20
16
14
14
7V0C0CO
6
9
INT F P
5V0C0CO
22
16
7V0C0CO
7V0C0CO
8
8
INT F P
5V0C1CO
5V0C0CO
13
13
15
12
12
25
10 10
INT
F P
5V0C1CO
17
15
14 25 4 4
19 19
19 19 19 17 16 16 14
24 2 2
6
26 26
22
19
21 23
21 19
17 17
22 22
22 20
23 19
23 18
13 22
19
23
26 24
3
A
B
C
2
2D
106
E
0
0F
106
G
3
3H
105
J
2
2K
105
L
0
0M
105
N
2
2P
104
R
1
1T
104
U
0
0V
104
W
2
2Y
103
AA
0 0 AB 103 AC
5 AD
1 5 AE
0 0 AF
3
AG
3 2 AH
2 AJ
4 4 AK
1 1 AL
5
AM
0 5 AN
AP
8 11 11 24
22 20 21 19 20 21 23
19 21
12 12
20 20
23 22
21 18
21 18
17 13
22 21 23 23 18 18 26 7 7 3
0 AP
AR 9 9
7 24 25 20
21
22 20
18 19
18 14
15 21
18 23
21 18
17 21
17 12
20 21 23
20
21 21
11 11 6 9 AR
AT 0 0 3 7
25 18 18 23 23 22
18 13
18 22
14 15
21 18
14 14
17 13
22 15
12 20
18
18
20
22
22
7V0C1CO
7V0C1CO
8
6 9 AT
AU 5
3
7V1C0CO
7V1C0CO
16
15 15
14 14 12
13 22 20
16 16 16
13 13 16
15 12 13
22 15 14
16 17 17
7V0C2CO
7V0C2CO
19
7V0C1CO
8
10 10
AU
AV 5 1 2
7V1C0CO
16
14
12 13 16
12 17 17
20 26 26
16 14 12
16 15 12
25 20 20
16 14 16
15
12
7V0C2CO
19 13 13
7 1 1 AV
AW
1244
14 12 13
16 15 15
7V0C8CO
7V0C7CO
7V0C7CO
24 25 14
12 17 26
24
25
7V0C5CO
26
7V0C4CO
16
14 15 12
13 23 23 17 17 7 11
5 AW
AY 4 4
10 10 16 16
17 17 26
24
25
7V0C8CO
7V0C7CO
24
25
7V0C6CO
15
15
17 26 24
7V0C5CO
26
24
7V0C4CO
7V0C4CO
14
24 25 13
18 12
11 6 5 0 AY
BA 3 2 2 8
7V0C9CO
7V0C9CO
14
22
26 24 25
7V0C8CO
7
7
5
5
7V0C6CO
26 24 25
10
10
7V0C5CO
24 25 25
26 26 24
25
7V0C3CO
18
15
12
6
0 3 BA
BB 3
9
9
8
7V0C9CO
14 20 22 10
6676
11 1
1
7V0C6CO
26 24 25 8
7777
11 4 10 8
11
7V0C3CO
7V0C3CO
21
15 9 9 3
BB
BC 0 0 6
26 12 15 15
20 10 8 9
7 6 11 3
10 8 8 9
11 8 9 6
6 6 11 4
10 8 9 11
7 21 14 14
8 2 2 BC
BD
5 5 6 26
12 17 21 21
8 9 11 11
9 3 0 10
9 6 6 11
9 6 11 11
9322
9667
16 25 10 8
4 BD
BE
1
11 24 24 17
18 18 2 3
1189
0440
7723
1198
3143
1 1 20 16
25 10 4
BE
BF
1 11
25 13 13 23
4230
10 8 4 2
2305
4230
10 8 0 1
4230
20 22 24 24
BF
BG
7 7 25
19 19 23 4
0 5 5 10
4223
5114
0 5 5 10
0552
0 5 5 22
26 26
BG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 200 GTY 201 GTY 202 GTY 203 GTY 204 GTY 205 GTY 206 GTY 306 HDIO 406 HDIO 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO 707 XPIO 708 XPIO 709 XPIO 710 XPIO 711 XPIO
X24177-070320
AM013 (v1.0) July 16, 2020 Versal ACAP Packaging and Pinouts
Send Feedback
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Chapter 4: Device Diagrams
VSVA2197 Package--VC1902
Figure 21: VSVA2197 Package--VC1902 Device Diagram
V
V V
V V V
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
A
B
C
D
0
0
206
E
F
1
1
205
G
H2
2
204
J
K
0
0
204
L
M2
2
203
N
P
0
0
203
R
T
2
2
202
U
V
0
0
202
W
Y
2
2
201
AA
AB 0 0 201
AC
AD
2 2
200
AE
AF 0 0 200
AG
AH 2 2
AJ
3
AK 0 0
AL 5 5
AM 10
AN 8 10
2 2
206 3
3 205 0
0 205 1
1 204 3
3 203 1
1 203 3
3 202 1
1 202
3 3
206 1
1 206 2
2 205 3
3 204
0
0
204
2
2
203
0
0
203
2
2
202
2
2
206
0
0
206
2
2
205
0
0
205
2
2
204
3
3
203
1
1
203
3
3
202
1
1
202
1
1
206
3
3
205
1
1
205
3
3
204
1
1
204
3
3
206
0 0
206 E
0 0
205 E
0 0
204 E
0 0
203 E
0 0
202
E 1 1 206 E 1 1 205 E 1 1 204
1 1
203
1 1
202
1 1
201
46 45 35 34
47
36 33 26
48 44 37
27
43 38 32 28
49 42
31 29
50 41 39 30
51
40 9 10
779
10
4V0C6CO
5
6
8
8
35
64
1324
1
4V0C6CO
2
0
0
PO
EO DN 23 14
54
PI DI PU
22 15 13 6
DO M0 24 21
12 7 3
MS CK
25 20 16 11
M3 M2 M1 4
17 10 8
18
5 3 0 18
9
19 17 6
1 19 10 10
16 7 2 7
88
20 15
7
9
9
4
3V0C6CO
21 14 8 3
564
25 22
9356
0
24 23
13
10
3V0C6CO
1
2
2
0
12 11
1
0 1 2
1 1
106 E 0
0 106 E 1
1 105 E 0
0 105 E 1
1 104 E 0
0 104 E 1
1 103
22 106 V
11 106
V
00 106 V
22 105
V
00 105 V
33 104
V
22 104 V
00 104
V
33 106
3 3
106
1 1
106
33 105
11 105
1 1
105
3 3
104
11 104
33 103
0
0
202
3 3
201
3
3
E
V
n
201
2
2
201
GVV
1 1
201
1
1
E
V
n
201
0
0
201
0
0
V
V
201
3 3
200
3
3
E
V
n
200
2
2
200
1
1
V
V
200
1 1
200
1
1
E
V
n
200
0
0
200
0
0
V
V
200
4
n
4
8 10 10 26 14 16 16 22 22
20
398
26
14
21
18 20 n
9 6 6 24 24 15 15 12
21 18
1 11
7 25
7V1C1CO
12 17 23
19 23
6
1
11
7
25
7V1C1CO
7V1C1CO
13
13
17
23 19
23 19
RAM
SOC SOC SOC SOC
SOC SOC SOC SOC
RAM
RAM
RAM
SOC SOC
SOC
SOC SOC
RAM
SOC SOC
SOC
SOC SOC
13 13
19 19
20 23
19 23
0 0
103
22 103
V
3 3
103
RN VP VN RP RR
G
19
13
11 103
V
00 103
1 1
103
5V0C3CO 19 23 23 13 17 25 25
7
1
RC
PR
5V0C3CO
18
17
24
7 11
F S
L P
5V0C2CO 18 21 12 12 15 26 24 11
AUX
L P
5V0C2CO
20
21
15
26 6 9
AUX
F P
L P
22 20
16
14
14
7V0C0CO
6
9
INT F P
5V0C0CO
22
16
7V0C0CO
7V0C0CO
8
8
INT F P
5V0C1CO
5V0C0CO
13
13
15
12
12
25
10 10
INT
F P
5V0C1CO
17
15
14 25 4 4
19 19
19 19 19 17 16 16 14
24 2 2
6
26 26
22
19
21 23
21 19
17 17
22 22
22 20
23 19
23 18
13 22
19
23
26 24
3
A
B
C
2
2D
106
E
0
0F
106
G
3
3H
105
J
2
2K
105
L
0
0M
105
N
2
2P
104
R
1
1T
104
U
0
0V
104
W
2
2Y
103
AA
0 0 AB 103 AC
5 AD
1 5 AE
0 0 AF
3
AG
3 2 AH
2 AJ
4 4 AK
1 1 AL
5
AM
0 5 AN
AP
8 11 11 24
22 20 21 19 20 21 23
19 21
12 12
20 20
23 22
21 18
21 18
17 13
22 21 23 23 18 18 26 7 7 3
0 AP
AR 9 9
7 24 25 20
21
22 20
18 19
18 14
15 21
18 23
21 18
17 21
17 12
20 21 23
20
21 21
11 11 6 9 AR
AT 0 0 3 7
25 18 18 23 23 22
18 13
18 22
14 15
21 18
14 14
17 13
22 15
12 20
18
18
20
22
22
7V0C1CO
7V0C1CO
8
6 9 AT
AU 5
3
7V1C0CO
7V1C0CO
16
15 15
14 14 12
13 22 20
16 16 16
13 13 16
15 12 13
22 15 14
16 17 17
7V0C2CO
7V0C2CO
19
7V0C1CO
8
10 10
AU
AV 5 1 2
7V1C0CO
16
14
12 13 16
12 17 17
20 26 26
16 14 12
16 15 12
25 20 20
16 14 16
15
12
7V0C2CO
19 13 13
7 1 1 AV
AW
1244
14 12 13
16 15 15
7V0C8CO
7V0C7CO
7V0C7CO
24 25 14
12 17 26
24
25
7V0C5CO
26
7V0C4CO
16
14 15 12
13 23 23 17 17 7 11
5 AW
AY 4 4
10 10 16 16
17 17 26
24
25
7V0C8CO
7V0C7CO
24
25
7V0C6CO
15
15
17 26 24
7V0C5CO
26
24
7V0C4CO
7V0C4CO
14
24 25 13
18 12
11 6 5 0 AY
BA 3 2 2 8
7V0C9CO
7V0C9CO
14
22
26 24 25
7V0C8CO
7
7
5
5
7V0C6CO
26 24 25
10
10
7V0C5CO
24 25 25
26 26 24
25
7V0C3CO
18
15
12
6
0 3 BA
BB 3
9
9
8
7V0C9CO
14 20 22 10
6676
11 1
1
7V0C6CO
26 24 25 8
7777
11 4 10 8
11
7V0C3CO
7V0C3CO
21
15 9 9 3
BB
BC 0 0 6
26 12 15 15
20 10 8 9
7 6 11 3
10 8 8 9
11 8 9 6
6 6 11 4
10 8 9 11
7 21 14 14
8 2 2 BC
BD
5 5 6 26
12 17 21 21
8 9 11 11
9 3 0 10
9 6 6 11
9 6 11 11
9322
9667
16 25 10 8
4 BD
BE
1
11 24 24 17
18 18 2 3
1189
0440
7723
1198
3143
1 1 20 16
25 10 4
BE
BF
1 11
25 13 13 23
4230
10 8 4 2
2305
4230
10 8 0 1
4230
20 22 24 24
BF
BG
7 7 25
19 19 23 4
0 5 5 10
4223
5114
0 5 5 10
0552
0 5 5 22
26 26
BG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 200 GTY 201 GTY 202 GTY 203 GTY 204 GTY 205 GTY 206 GTY 306 HDIO 406 HDIO 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO 707 XPIO 708 XPIO 709 XPIO 710 XPIO 711 XPIO
X24178-070320
AM013 (v1.0) July 16, 2020 Versal ACAP Packaging and Pinouts
Send Feedback
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Chapter 4: Device Diagrams
VSVA2197 Package--VM1802
Figure 22: VSVA2197 Package--VM1802 Device Diagram
V
V V
V V V
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
A
B
C
D
0
0
206
E
F
1
1
205
G
H2
2
204
J
K
0
0
204
L
M2
2
203
N
P
0
0
203
R
T
2
2
202
U
V
0
0
202
W
Y
2
2
201
AA
AB 0 0 201
AC
AD
2 2
200
AE
AF 0 0 200
AG
AH 2 2
AJ
3
AK 0 0
AL 5 5
AM 10
AN 8 10
2 2
206 3
3 205 0
0 205 1
1 204 3
3 203 1
1 203 3
3 202 1
1 202
3 3
206 1
1 206 2
2 205 3
3 204
0
0
204
2
2
203
0
0
203
2
2
202
2
2
206
0
0
206
2
2
205
0
0
205
2
2
204
3
3
203
1
1
203
3
3
202
1
1
202
1
1
206
3
3
205
1
1
205
3
3
204
1
1
204
3
3
206
0 0
206 E
0 0
205 E
0 0
204 E
0 0
203 E
0 0
202
E 1 1 206 E 1 1 205 E 1 1 204
1 1
203
1 1
202
1 1
201
46 45 35 34
47
36 33 26
48 44 37
27
43 38 32 28
49 42
31 29
50 41 39 30
51
40 9 10
779
10
4V0C6CO
5
6
8
8
35
64
1324
1
4V0C6CO
2
0
0
PO
EO DN 23 14
54
PI DI PU
22 15 13 6
DO M0 24 21
12 7 3
MS CK
25 20 16 11
M3 M2 M1 4
17 10 8
18
5 3 0 18
9
19 17 6
1 19 10 10
16 7 2 7
88
20 15
7
9
9
4
3V0C6CO
21 14 8 3
564
25 22
9356
0
24 23
13
10
3V0C6CO
1
2
2
0
12 11
1
0 1 2
1 1
106 E 0
0 106 E 1
1 105 E 0
0 105 E 1
1 104 E 0
0 104 E 1
1 103
22 106 V
11 106
V
00 106 V
22 105
V
00 105 V
33 104
V
22 104 V
00 104
V
33 106
3 3
106
1 1
106
33 105
11 105
1 1
105
3 3
104
11 104
33 103
0
0
202
3 3
201
3
3
E
V
n
201
2
2
201
GVV
1 1
201
1
1
E
V
n
201
0
0
201
0
0
V
V
201
3 3
200
3
3
E
V
n
200
2
2
200
1
1
V
V
200
1 1
200
1
1
E
V
n
200
0
0
200
0
0
V
V
200
4
n
4
8 10 10 26 14 16 16 22 22
20
398
26
14
21
18 20 n
9 6 6 24 24 15 15 12
21 18
1 11
7 25
7V1C1CO
12 17 23
19 23
6
1
11
7
25
7V1C1CO
7V1C1CO
13
13
17
23 19
23 19
RAM
SOC SOC SOC SOC
SOC SOC SOC SOC
RAM
RAM
RAM
SOC SOC
SOC
SOC SOC
RAM
SOC SOC
SOC
SOC SOC
13 13
19 19
20 23
19 23
0 0
103
22 103
V
3 3
103
RN VP VN RP RR
G
19
13
11 103
V
00 103
1 1
103
5V0C3CO 19 23 23 13 17 25 25
7
1
RC
PR
5V0C3CO
18
17
24
7 11
F S
L P
5V0C2CO 18 21 12 12 15 26 24 11
AUX
L P
5V0C2CO
20
21
15
26 6 9
AUX
F P
L P
22 20
16
14
14
7V0C0CO
6
9
INT F P
5V0C0CO
22
16
7V0C0CO
7V0C0CO
8
8
INT F P
5V0C1CO
5V0C0CO
13
13
15
12
12
25
10 10
INT
F P
5V0C1CO
17
15
14 25 4 4
19 19
19 19 19 17 16 16 14
24 2 2
6
26 26
22
19
21 23
21 19
17 17
22 22
22 20
23 19
23 18
13 22
19
23
26 24
3
A
B
C
2
2D
106
E
0
0F
106
G
3
3H
105
J
2
2K
105
L
0
0M
105
N
2
2P
104
R
1
1T
104
U
0
0V
104
W
2
2Y
103
AA
0 0 AB 103 AC
5 AD
1 5 AE
0 0 AF
3
AG
3 2 AH
2 AJ
4 4 AK
1 1 AL
5
AM
0 5 AN
AP
8 11 11 24
22 20 21 19 20 21 23
19 21
12 12
20 20
23 22
21 18
21 18
17 13
22 21 23 23 18 18 26 7 7 3
0 AP
AR 9 9
7 24 25 20
21
22 20
18 19
18 14
15 21
18 23
21 18
17 21
17 12
20 21 23
20
21 21
11 11 6 9 AR
AT 0 0 3 7
25 18 18 23 23 22
18 13
18 22
14 15
21 18
14 14
17 13
22 15
12 20
18
18
20
22
22
7V0C1CO
7V0C1CO
8
6 9 AT
AU 5
3
7V1C0CO
7V1C0CO
16
15 15
14 14 12
13 22 20
16 16 16
13 13 16
15 12 13
22 15 14
16 17 17
7V0C2CO
7V0C2CO
19
7V0C1CO
8
10 10
AU
AV 5 1 2
7V1C0CO
16
14
12 13 16
12 17 17
20 26 26
16 14 12
16 15 12
25 20 20
16 14 16
15
12
7V0C2CO
19 13 13
7 1 1 AV
AW
1244
14 12 13
16 15 15
7V0C8CO
7V0C7CO
7V0C7CO
24 25 14
12 17 26
24
25
7V0C5CO
26
7V0C4CO
16
14 15 12
13 23 23 17 17 7 11
5 AW
AY 4 4
10 10 16 16
17 17 26
24
25
7V0C8CO
7V0C7CO
24
25
7V0C6CO
15
15
17 26 24
7V0C5CO
26
24
7V0C4CO
7V0C4CO
14
24 25 13
18 12
11 6 5 0 AY
BA 3 2 2 8
7V0C9CO
7V0C9CO
14
22
26 24 25
7V0C8CO
7
7
5
5
7V0C6CO
26 24 25
10
10
7V0C5CO
24 25 25
26 26 24
25
7V0C3CO
18
15
12
6
0 3 BA
BB 3
9
9
8
7V0C9CO
14 20 22 10
6676
11 1
1
7V0C6CO
26 24 25 8
7777
11 4 10 8
11
7V0C3CO
7V0C3CO
21
15 9 9 3
BB
BC 0 0 6
26 12 15 15
20 10 8 9
7 6 11 3
10 8 8 9
11 8 9 6
6 6 11 4
10 8 9 11
7 21 14 14
8 2 2 BC
BD
5 5 6 26
12 17 21 21
8 9 11 11
9 3 0 10
9 6 6 11
9 6 11 11
9322
9667
16 25 10 8
4 BD
BE
1
11 24 24 17
18 18 2 3
1189
0440
7723
1198
3143
1 1 20 16
25 10 4
BE
BF
1 11
25 13 13 23
4230
10 8 4 2
2305
4230
10 8 0 1
4230
20 22 24 24
BF
BG
7 7 25
19 19 23 4
0 5 5 10
4223
5114
0 5 5 10
0552
0 5 5 22
26 26
BG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
I/O
# IO_L#P # IO_L#N # IO_L#P_GC # IO_L#N_GC
IO_VR # PMC_MIO # LPD_MIO
Transceiver
# RXP# # RXN# # TXP# # TXN# # REFCLKP# # REFCLKN#
AVTTRCAL G RREF E AVCC V AVTT
AVCCAUX
PMCDIO/SYSMON
M# MODE# EO ERROR_OUT PO RTC_PADO PI RTC_PADI PU PUDC_B DN DONE RC REF_CLK PR POR_B CK TCK DI TDI DO TDO MS TMS
RN VREFN RP VREFP VN VN VP VP
Power
VCCINT VCCAUX VCC_IO AUX VCCAUX_PMC F P VCC_PSFP L P VCC_PSLP INT VCC_PMC SOC VCC_SOC RAM VCC_RAM VCC_BATT F S VCC_FUSE VCCAUX_SMON GND_SMON GND R RSVDGND n NC
103 GTY 104 GTY 105 GTY 106 GTY 200 GTY 201 GTY 202 GTY 203 GTY 204 GTY 205 GTY 206 GTY 306 HDIO 406 HDIO 500 PMCMIO/PMCDIO 501 PMCMIO 502 LPDMIO 503 PMCDIO 700 XPIO 701 XPIO 702 XPIO 703 XPIO 704 XPIO 705 XPIO 706 XPIO 707 XPIO 708 XPIO 709 XPIO 710 XPIO 711 XPIO
X24176-070320
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Chapter 5: Mechanical Drawings
Chapter 5
Mechanical Drawings
This chapter provides mechanical drawings (package specifications) of the VersalTM ACAPs. The following table is a cross-reference to the mechanical drawings by device and package combination. See Package Specifications Designations for definitions of Evaluation Only, Engineering Sample, and Production mechanical drawings.
IMPORTANT! All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q. For the mechanical drawings, refer to the Pb-free version of these packages.
See the Table 18: Mechanical Drawing Dimension Definitions table for details on key dimensions/tolerances shown in each mechanical drawing.
Table 16: Cross-Reference to Versal ACAP AI Core Series Mechanical Drawings by Package
Package
VBVA1024 VSVE1369 VSVG1369 VSVA1596 VIVA1596
VSVD1760
VSVA2197
VC1352
VC1502
Devices VC1702
VC1802
VC1902
Figure 23 Engineering Sample
Figure 25 Engineering Sample
Figure 26 Engineering Sample
Figure 23 Engineering Sample
Figure 25 Engineering Sample
Figure 26 Engineering Sample
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Chapter 5: Mechanical Drawings
Table 17: Cross-Reference to Versal ACAP Prime Series Mechanical Drawings by Package
Package
SFVB625 VFVB1024 VFVB1369 VFVF1369 VFVA1760 VFVC1760
VSVD1760
VSVA2197
VM1102
VM1302
VM1402
Devices VM1502 VM1802
VM2502
Figure 24 Engineering
Sample
Figure 25 Engineering
Sample
Figure 26 Engineering
Sample
VM2602
VM2902
Table 18: Mechanical Drawing Dimension Definitions
Dimension
/ /
A A1 A2 A3 D/E D1/E1 e �b
aaa / / bbb �ddd
�eee
M
Definition
Bilateral tolerance of package sides with respect to datums A and B
Flatness tolerance of silicon die or package lid top surface
Bilateral tolerance for parallelism of silicon die or package lid top surface with respect to the seating plane datum C Thickness of package with respect to the seating plane datum C Thickness of BGA balls with respect to the seating plane datum C Thickness of package body, including stiffener ring or lid and excluding BGA balls, with respect to the seating plane datum C Distance from top of silicon die to top of stiffener ring or lid with respect to the seating plane datum C Length/width of package with respect to datums A and B Length/width of BGA matrix with respect to datums A and B BGA ball pitch measured at the center of each ball BGA ball diameter Unidirectional upward tolerance with respect to the seating plane datum C
Bilateral tolerance for parallelism of package surface with respect to the seating plane datum C BGA ball position tolerance of diameter ddd with respect to datums A and B perpendicular to the seating plane datum C in which the center of each ball must lie BGA ball position tolerance of diameter eee measured with respect to other balls within the BGA matrix in which the center of each ball must lie BGA ball matrix size
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Chapter 5: Mechanical Drawings
VIVA1596 Package--VC1802 and VC1902
Figure 23: Package Dimensions for VIVA1596 (VC1802 and VC1902)
Related Information Mechanical Drawings
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Chapter 5: Mechanical Drawings
VFVC1760 Package--VM1802
Figure 24: Package Dimensions for VFVC1760 (VM1802)
Related Information Mechanical Drawings
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Chapter 5: Mechanical Drawings
VSVD1760 Package--VC1802, VC1902, and VM1802
Figure 25: Package Dimensions for VSVD1760 (VC1802, VC1902, and VM1802)
Related Information Mechanical Drawings
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Chapter 5: Mechanical Drawings
VSVA2197 Package--VC1802, VC1902, and VM1802
Figure 26: Package Dimensions for VSVA2197 (VC1802, VC1902, and VM1802)
Related Information Mechanical Drawings
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Chapter 6: Package Marking
Chapter 6
Package Marking
The package top-markings for the XC and XA VersalTM devices are similar to the examples shown in the following figure.
Figure 27: Versal Devices Package Marking
X22638-040919
Table 19: Versal Device Marking Definition--Example
Item
Xilinx Logo Bar Code
Definition
Xilinx logo, Xilinx name with trademark, and trademark-registered status. A device-specific bar code is marked on each device.
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Chapter 7: Packing and Shipping
Chapter 7
Packing and Shipping
VersalTM devices are packed in trays. Trays are used to pack most of Xilinx surface-mount devices because they provide excellent protection from mechanical damage. In addition, they are manufactured using antistatic material to provide limited protection against ESD damage and can withstand a bake temperature of 125�C.
Table 20: Standard Device Counts per Tray and Box
SFVB625 VBVA1024 VFVB1024 VFVB1369 VSVE1369 VSVA1596 VIVA1596 VFVA1760 VFVC1760 VSVD1760 VSVA2197
Package
Maximum Number of Devices Per Tray
60
Maximum Number of Units In One Internal Box
300
12
36
12
36
12
36
12
36
12
36
IMPORTANT! All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example: VSQD1760).
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Chapter 8: Soldering Guidelines
Chapter 8
Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the solder reflow process and how each element of the process is related to the end result must be thoroughly understood.
RECOMMENDED: Xilinx recommends that customers qualify their custom PCB assembly processes using package samples.
The primary phases of the reflow process are: � Melting the particles in the solder paste � Wetting the surfaces to be joined � Solidifying the solder into a strong metallurgical bond The peak reflow temperature of a surface-mount component body should not be more than 250�C maximum (260�C for dry rework only) for Pb-free packages and 220�C for eutectic packages, and is package size dependent. For multiple BGAs in a single board and because of surrounding component differences, Xilinx recommends checking all BGA sites for varying temperatures.
The infrared reflow (IR) process is strongly dependent on equipment and loading. Components might overheat due to lack of thermal constraints. Unbalanced loading can lead to significant temperature variation on the board. These guidelines are intended to assist users in avoiding damage to the components; the actual profile should be determined by those using these guidelines. For complete information on package moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC Standard J-STD-020C.
IMPORTANT! Following the initial reflow process, devices should not be reworked more than once. Any additional rework beyond that is likely to cause irreparable damage to the device.
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Chapter 8: Soldering Guidelines
Sn/Pb Reflow Soldering
The following figure shows typical conditions for solder reflow processing of Sn/Pb soldering using IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture sensitivity of surface-mount components must be verified prior to surface-mount flow.
Figure 28: Typical Conditions for IR Reflow Soldering of Sn/Pb Solder
Temperature (�C)
2�3�C/s
T = 183�C t183
Preheat & drying dwell 120�180 s between 95�180�C (Note 2) <1�C/s
Time (s)
TMAX (body) = 225�C TMAX (leads) = 235�C Ramp down 1�3�C/s 60s < t183 < 120s Applies to lead area
X22586-032520
Notes in figure:
1. Maximum temperature range = 225�C (body). Minimum temperature range before 205�C (leads/balls).
2. Preheat dwell 95�180�C for 120�180 seconds.
3. IR reflow must be performed on dry packages.
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Chapter 8: Soldering Guidelines
Pb-Free Reflow Soldering
Xilinx uses SnAgCu solder balls for commercial-grade (XC) and automotive-grade (XA) BGA packages. In addition, suitable material are qualified for the higher reflow temperatures (250�C maximum, 260�C for dry rework only) required by Pb-free soldering processes.
Xilinx does not support soldering SnAgCu BGA packages with SnPb solder paste using a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow temperature of 220�C. At this temperature range, the SnAgCu BGA solder balls do not properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields can be compromised.
The optimal profile must take into account the solder paste/flux used, the size of the board, the density of the components on the board, and the mix between large components and smaller, lighter components. Profiles should be established for all new board designs using thermocouples at multiple locations on the component. In addition, if there is a mixture of devices on the board, then the profile should be checked at various locations on the board. Ensure that the minimum reflow temperature is reached to reflow the larger components and at the same time, the temperature does not exceed the threshold temperature that might damage the smaller, heat sensitive components.
The following tables and figure provide guidelines for profiling Pb-free solder reflow. In general, a gradual, linear ramp into a spike has been shown by various sources to be the optimal reflow profile for Pb-free solders. This profile has been shown to yield better wetting and less thermal shock than conventional ramp-soak-spike profile for the Sn/Pb system. SnAgCu alloy reaches full liquidus temperature at 235�C. When profiling, identify the possible locations of the coldest solder joints and ensure that those solder joints reach a minimum peak temperature of 235�C for at least 10 seconds. Reflowing at high peak temperatures of 260�C and above can damage the heat sensitive components and cause the board to warp. Users should reference the latest IPC/ JEDEC J-STD-020 standard for the allowable peak temperature on the component body. The allowable peak temperature on the component body is dependent on the size of the component. The table lists the peak package reflow body temperature information. In any case, use a reflow profile with the lowest peak temperature possible.
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Chapter 8: Soldering Guidelines
Table 21: Pb-Free Reflow Soldering Guidelines for Package Sizes Up to 45 mm x 45 mm
Profile Feature
Preheat ramp-up rate 30��150�C
Preheat temperature soak time 150��200�C Temperature maintained above 217�C Time within 5�C of actual peak temperature Peak temperature (lead/ball)
Maximum peak temperature (body)
Ramp-down rate Time 25�C to peak temperature
Convection, IR/Convection
2�C/s maximum 1�C/s maximum for lidless packages with stiffener ring
60�120 seconds
60�150 seconds (60�90 seconds typical)
30 seconds maximum
230�C�245�C typical (depends on solder paste, board size, component mixture)
240�C�250�C, package body size dependent (see the specific Versal ACAP Data Sheet).
2�C/s maximum
3.5 minutes minimum, 5.0 minutes typical, 8 minutes maximum
Table 22: Pb-Free Reflow Soldering Guidelines for Package Sizes Greater than 45 mm x 45 mm and Up to 55 mm x 55 mm
Profile Feature
Preheat ramp-up rate 30��150�C Preheat temperature soak time 150��190�C Temperature maintained above 217�C Maximum peak temperature (body)
Ramp-down rate 240��125�C
Convection, IR/Convection
0.5�C/s�1.5�C/s 65�70 seconds 50�60 seconds 234�C�238�C, package body size dependent (see the specific Versal ACAP Data Sheet). 1�C/s�2�C/s
Table 23: Pb-Free Reflow Soldering Guidelines for Package Sizes Greater than 55 mm x 55 mm
Profile Feature
Preheat ramp-up rate 30��150�C Preheat temperature soak time 150��190�C Temperature maintained above 217�C Maximum peak temperature (body)
Ramp-down rate 240��185�C Ramp-down rate 185��125�C
Convection, IR/Convection
0.5�C/s�1.5�C/s 76�81 seconds 77�93 seconds 231�C�240�C, package body size dependent (see the specific Versal ACAP Data Sheet). 0.7�C/s�0.8�C/s 1.6�C/s�1.75�C/s
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Chapter 8: Soldering Guidelines
Figure 29: Typical Conditions for Pb-Free Reflow Soldering
Tbody (MAX) = 240�250�C (package type dependent) See data sheet for maximum value by package type Tlead (MIN) = 230�245�C (10s minimum)
Temperature (�C)
150�200�C Preheating 60�120s
217�C
t217 Wetting time = 60�150 s
Ramp down 2�C/s max
Ramp up 2�C/s maximum 1�C/s maximum for lidless packages with stiffener ring
Time (s)
X22585-032620
Peak Package Reflow Temperatures
Table 24: Peak Package Reflow Body Temperature (Based on J-STD-020 Standard)
Package
Product Category
Peak Package Reflow Body Temperature1
JEDEC Moisture Sensitivity Level (MSL)
Mass reflow: 250�C
SFVB625
All
4
Dry rework: 260�C
VBVA1024 VFVB1024
VFVB1369
VSVE1369
VSVA1596
Mass reflow: 240�C
VIVA1596
All
4
Dry rework: 260�C
VFVA1760
VFVC1760
VSVD1760
VSVA2197 VSVA2785
Notes:
1. See the specific Versal ACAP Data Sheet for the most up-to-date specifications.
2. For devices with the Pb-free signifier in the package name (labeled as Q vs. V) use the temperatures and MSL listed for the XQ product category.
For sophisticated boards with a substantial mix of large and small components, it is critical to minimize the T across the board (<10�C) to minimize board warpage and thus, attain higher assembly yields. Minimizing the T is accomplished by using a slower rate in the warm-up and preheating stages.
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Chapter 8: Soldering Guidelines
It is also important to minimize the temperature gradient on the component, between top surface and bottom side, especially during the cooling down phase. The key is to optimize cooling while maintaining a minimal temperature differential between the top surface of the package and the solder joint area. The temperature differential between the top surface of the component and the solder balls should be maintained at less than 7�C during the critical region of the cooling phase of the reflow process. This critical region is in the part of the cooling phase where the balls are not completely solidified to the board yet, usually between the 200�C�217�C range. To efficiently cool the parts, divide the cooling section into multiple zones, with each zone operating at different temperatures.
The optimal profile must take into account the solder paste/flux used, the size of the board, the density of the components on the board, and the mix between large components and smaller, lighter components. Profiles should be established for all new board designs using thermocouples at multiple locations on the component. In addition, if there is a mixture of devices on the board, then the profile should be checked at various locations on the board, as shown in the following thermocouple pictures. Ensure that the minimum reflow temperature is reached to reflow the larger components and at the same time, the temperature does not exceed the threshold temperature that might damage the smaller, heat sensitive components.
Figure 30: Thermocouple Top
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Chapter 8: Soldering Guidelines Figure 31: Thermocouple Bottom
Post Reflow/Cleaning/Washing
Many PCB assembly subcontractors use a no-clean process in which no post-assembly washing is required. Although a no-clean process is recommended, if cleaning is required, Xilinx recommends a water-soluble paste and a washer using a deionized-water. Baking after the water wash is recommended to prevent fluid accumulation. Cleaning solutions or solvents are not recommended because some solutions contain chemicals that can compromise the lid adhesive, thermal compound, or components inside the package.
Conformal Coating
Xilinx does not have information regarding the reliability of flip-chip BGA packages on a board after exposure to any specific conformal coating process. Therefore, any process using conformal coating should be qualified for the specific use case to cover the materials and process steps.
Ruggedized XQ packages are designed to support conformal coating, with vented lids that ensure proper cleaning can occur after the etching process and prior to conformal coating.
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Chapter 8: Soldering Guidelines
RECOMMENDED: When a conformal coating is required, Parylene-based material should be used to avoid potential risk of weakening the lid adhesive used in Xilinx packages.
Strain Gauge Measurement
Strain gauge measurements are recommended to be done at each process step that has the potential to cause excessive board flexing leading to solder joint cracking. Assembly processes where strain gauge measurements are recommended include:
� PCB router (during PCB loading/unloading into fixture and during the routing process) � PTH solder assembly during top-catch loading/unloading � Press fit assembly during press base and tooling loading/unloading and during machine
pressing process � DIMM memory (during PCB loading/unloading and during insertion/removal of DIMM) � Heat-sink assembly process (during PCB loading/unloading and during entire screw assembly
process) � X-ray fixture (during PCBA loading/unloading)
Strain gauge measurements should be in the range of �500 strain. Dye and pry analysis is required to confirm if the measured strain causes solder joint cracking. It is recommended to conduct dye and pry analysis for any strain reading greater than 500 strain. To reduce the affects of strain on a device, edge bonding can be used and is recommended for larger packages. See Chapter 10: Edge Bonding Guidelines for implementation details.
Solder Paste
Solder paste consists of solder alloy and a flux system. A typical solder paste composition by volume is split between about 50% alloy and 50% flux. The metal load mass (solder alloy powder) is around 90%, with the remaining 10% mass a flux system. The primary purpose of the flux system is to remove the contaminants from the solder joints during the soldering process. The capability of removing contaminants is determined by the activation level of the type of solder paste. The preferred solder paste metal alloy has a lead-free composition (SnAgCu where Ag is 3�4% and Cu is 0.5�1%). A no-clean solder paste is preferred to eliminate any risk of improper cleaning that could leave active residue beneath the device and other BTC components. The paste must be suitable for printing the solder stencil aperture dimensions. Type 4 paste is recommended for better paste release performance. When using a solder paste, you must adhere to the handling recommendations of the paste manufacturer.
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Chapter 8: Soldering Guidelines
Component Placement
IMPORTANT! The following component placement guidelines apply to all package types included in this guide (lidded, lidless, bare-die, etc.).
Xilinx device packages must be placed accurately according to their geometry outline. Positioning packages manually via hand mounting is not recommended. Typical component placement accuracies of �50 m can be achieved using standard pick and place equipment with vision system. The PCB and components are optically checked and measured by the pick and place vision system. The pick and place machine detects the fiducial on the PCB immediately prior to the placement of the Versal device. Recognition of the packages is performed by the vision system, to ensure correct centering of the Versal device placement on the PCB pad array. BGA packages with solder balls can self-align during the reflow process because of the solder high surface tension that enables the pulling and centering of the device, and where a slight offset of the placement is still allowed. For guidance, the maximum tolerable offset of device placement is around 30% of the pad diameter on the PCB for typical non-solder mask defined pads. This means that the misalignment of solder ball device packages to the PCB pad must be better than 150 m to assure a robust mounting process. Generally, this is achievable using a wide range of modern pick and placement systems. The following setup conditions are important for the pick and placement systems:
� The pick and place nozzle type should be selected based on the dimensions of the Versal device. The nozzle needs to firmly hold the device package during the pick and place stage. The appropriate nozzle type for the device package can be chosen from the manual provided by the pick and place equipment manufacturer.
� The ball recognition capabilities of the placement system should be used and package outline centering should be avoided. This eliminates the solder ball to package edge tolerances of the package. Refer to the specific package outline drawing for details.
� To ensure the proper identification of the device package during vision recognition, prior to its placement, a suitable lighting system and the correct choice of the features of the measuring method are essential. The most suitable settings can be chosen from the manual provided by the pick and place equipment manufacturer.
� To avoid solder bridging or solder smear, ensure the proper placement force of the device package during placement on the PCB. Excessive placement force can lead to excess solder paste and cause solder bridging. However, a slight placement force can lead to insufficient solder paste contact between the device package solder balls and the solder paste, causing solder defects including open solder joints, badly centered packages, or even head-in-pillow (HIP) defects.
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Chapter 8: Soldering Guidelines
Component Pick-up Tool Consideration
For pick and place machines to place lidless and bare-die flip-chip BGAs onto PCBs, Xilinx recommends using soft tips or suction cups for the nozzles. This prevents chipping, scratching, or even cracking of the bare die.
Figure 32: Recommended Method For Using Pick-up Tools
Decoupling Capacitor
Preferred
Metal Tip
Nozzle
Soft Tips
Silicon
Substrate
Incorrect Pickup Method
Decoupling Capacitor
Metal Tip
Nozzle
Silicon
Substrate
Metal Pick Up Tip Nozzle with Soft Tips or Suction Cups is Preferred
Metal Pick Up Tip Nozzle Can Damage the Exposed Silicon
X22617-040219
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Chapter 9: Recommended PCB Design Rules for BGA
Chapter 9
Recommended PCB Design Rules for BGA
Xilinx provides the diameter of a land pad on the package side. This information is required prior to the start of the board layout so the board pads can be designed to match the component-side land geometry. The typical values of these land pads are shown in the following figure and summarized in the table. For Xilinx BGA packages, non-solder mask defined (NSMD) pads on the board are suggested to allow a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in the following figure.
Figure 33: Suggested Board Layout of Soldered Pads for BGA Packages
M L
Opening in
Solder Mask
(M)
Solder Land
Solder Mask
(L)
e
X22593-040119
Table 25: BGA Package Design Rules
Flip-Chip BGA Packages
Design Rule
Package land pad opening (SMD) Maximum PCB solder land (L) diameter Opening in PCB solder mask (M) diameter Solder ball land pitch (e)
1.0 mm Pitch
0.92 mm Pitch
0.80 mm Pitch
BGA packages, non-solder mask defined dimensions in mm (mils)
0.53 mm (20.9 mils)
0.53 mm (20.9 mils)
0.40 mm (15.7 mils)
0.53 mm (20.9 mils)
0.51 mm (20.0 mils)
0.40 mm (15.7 mils)
0.63 mm (24.8 mils)
0.61 mm (24.0 mils)
0.50 mm (19.7 mils)
1.00 mm (39.4 mils)
0.92 mm (36.2 mils)
0.80 mm (31.5 mils)
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Chapter 9: Recommended PCB Design Rules for BGA
An example of an NSMD PCB pad solder joint is shown in the following figure. The space between the NSMD pad and the solder mask, as well as the actual signal trace widths, depend on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller.
RECOMMENDED: Xilinx recommends not mixing PCB pad isolated via-in-pad plated over (VIPPO) and non-VIPPO design styles because they can cause hot-tear defects that are related to localized Z-direction thermal expansion coefficient mismatch between VIPPO and non-VIPPO vias. A VIPPO via expands less than a non-VIPPO via.
RECOMMENDED: Xilinx recommends not mixing PCB pad of solder mask defined (SMD) and non-solder mask defined (NSMD) design styles, because this can cause solder bridging defects. For violation, customers need to work with their CM to optimize the stencil design and assembly process.
RECOMMENDED: For packages with names beginning with V or L (e.g., VSVA2197 and LSVA3112), the region underneath the land-side capacitors (LSCs) should be covered by solder mask. If traces are routed on the PCB top layer within the LSC region, clearance space between the PCB traces/solder mask and the capacitors must be ensured. Typically, there is 0.13 mm of clearance between the seating plane (PCB) and the surface of the capacitors. Refer to Chapter 5: Mechanical Drawings for LSC locations and relevant dimensions for each package.
Figure 34: Example of an NSMD PCB Pad Solder Joint
BGA Package
BGA Solder Ball Solder Mask
PCB
SMD L M
Land Pad
X22596-040119
Stencil
Solder paste is applied to PCB metal pads by screen printing. The volume of the printed solder paste is determined by the stencil aperture and the stencil thickness. In most cases, the thickness of a stencil must be matched to the needs of all components on the PCB. Stencil apertures should be a circular shape. To ensure a uniform and high-solder paste transfer to the PCB, lasercut stencil, made from mostly stainless steel, is typically used. Nickel Blank stencils, referring to stencils where the entire foil is laser-cut from a sheet of pure nickel material, can also be used. However, high-quality nano-coated stencils (laser cut from stainless steel) can perform as well as or better than Nickel Blanks.
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Chapter 9: Recommended PCB Design Rules for BGA
Uniform Stencil Aperture Design � For packages with 0.92 mm ball pitch, a uniform stencil aperture opening of 19.7 mils to 20.0
mils round is recommended, matching the PCB pad size. � For packages less than 55 mm x 55 mm with 1 mm ball pitch, a uniform stencil aperture
opening of 19.7 mils to 20.0 mils round is also recommended.
Bull's Eye Stencil Recommendation Another option is to use a Bull's Eye stencil aperture, where the board land-pad diameter increases from the center of the device outward, matching the variable aperture diameter of the stencil, at a rate that depends on the warpage as a function of thermal expansion and mechanical attachment. This can vary depending on the PCB. The bull's eye offers a capture margin, because with an increased opening size with respect to the outer BGA balls, more solder paste is printed. A recommended stencil design for the bull's eye design is shown in the following figure. Similar stencil designs are recommended for packages 55 mm x 55 mm and larger with 1 mm ball pitch. The final stencil design should be based on an evaluation of the board design. Designers should work with their CM to optimize the stencil design and assembly process.
RECOMMENDED: Xilinx recommends using a 5 mil thick stencil.
RECOMMENDED: Xilinx recommends using a uniform stencil aperture opening of 19.7 mils to 20 mils round, matching the PCB pad size for packages with 0.92 mm ball pitch.
RECOMMENDED: Xilinx recommends using a uniform stencil aperture opening of 19.7 mils to 20 mils round, matching the PCB pad size for packages less than 55 mm x 55 mm with 1.0 mm ball pitch.
RECOMMENDED: Xilinx recommends using a non-uniform (bull's eye) stencil aperture opening for packages 55 mm x 55 mm and larger with 1.0 mm ball pitch.
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Chapter 9: Recommended PCB Design Rules for BGA
Figure 35: Bull's Eye Stencil Aperture
26 mils round aperture and PCB land pad at outer (10 rows perimeter) 23 mils round aperture and PCB land pad at outer (10 rows perimeter) 20 mils round aperture and PCB land pad at outer (6 rows perimeter)
X23789-071320
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Chapter 10: Edge Bonding Guidelines
Chapter 10
Edge Bonding Guidelines
The edge bonding technique uses high-adhesion adhesives dispensed along the periphery of a component, as shown in the following figure. Xilinx recommends edge bonding larger packages (55 mm x 55 mm or larger) for increased mechanical reliability.
Figure 36: Edge Bonded BGA Packages
Edge Bonding Implementation
Edge bonding is the dispensing of an epoxy material around the periphery of the package after board mount. Xilinx requires the use of the Zymet UA-2605-B edge-bonding material. Edge bonding is not intended to under fill the package or contact the solder balls. This technique allows for component rework and improves the robustness of the mounted component by controlling the expansion and warpage of the board during normal operating conditions To place the adhesive while using an in-line soldering robot, Xilinx recommends the parameters shown in the following table.
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Chapter 10: Edge Bonding Guidelines
Table 26: Process Parameters for Edge Bonding
Needle size
Process Parameter
Needle height
Needle edge spacing
Range Specification
Range: 25 - 18 gauge Recommended: 18 gauge
Range: Above the device edge midpoint, or 0 to 1.5 mm below the top surface of the device Recommended: 1.0 mm below the top surface of the device
Range: Half to three quarters of needle outer diameter (D) Recommended: Half of needle diameter (D/2), approximately 1.0 mm
D
D/2 to 3/4D
Dispense needle speed Value pressure
Range: 0.1 to 200 mm/second Recommended: 9 mm/second
Range: 20 to 60 psi Recommended: 1.2 kgf/cm� @17 psi
X23788-032520
The adhesive is dispensed along the perimeter of the assembled component at a width of 3 mm and a height of 50% to 90% the substrate height, leaving a small section at the center of each edge unbonded, as illustrated in the following figure. This is to ensure that there is an outlet for any expansion of the air during processing. Xilinx recommends centering the opening on each side with a width of 25�30% the length of the package substrate. The exact locations and size of the openings can be varied depending on the design and rework.
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Chapter 10: Edge Bonding Guidelines Figure 37: Edge Bonding Adhesive Placement Parameters
RECOMMENDED: Curing conditions are 155�C for 10 minutes.
Component Clearance Surrounding Edge Bond An adjacent component clearance surrounding the Xilinx device is necessary to have the 30� to 45� angle required for the edge bond dispenser to dispense the edge bond adhesive material. The surrounding component height and distance from the device is validated based on each unique product design layout.
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Chapter 10: Edge Bonding Guidelines
Edge Bond Removal
Edge bond material can be removed by heating to 170�180�C, and scraping using a stiff probe made of stable organic material such as a non-resinous wood or Teflon. Use a hot air blower on the edge bond area and slowly remove the edge bond adhesive from side to side. Do not use force to remove the edge bond adhesive. Excess adhesive on the PCB can be removed using a chisel-tip soldering iron, with sufficient precautions to limit damage to the PCB surface. Xilinx has successfully evaluated the application processes used by Flex and Celestica and recommends these contract manufacturers for edge bond assembly of Xilinx packages. � https://flex.com/ � https://www.celestica.com/
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Chapter 11: Thermal Specifications
Chapter 11
Thermal Specifications
VersalTM ACAPs are offered exclusively in thermally efficient flip-chip BGA packages. These flipchip packages range in pin-count from the smaller 21 � 21 mm SFVB625 to the 52.5 � 52.5 mm VSVA2197. This suite of packages is used to address the various power requirements of the Versal ACAPs. Versal devices are implemented in the 7 nm process technology. Unlike features in an ASIC, the combination of Versal ACAP features used in a user application is not known to the component supplier. Therefore, it remains a challenge for Xilinx to predict the power requirements of a given Versal device when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Versal ACAPs are supported similarly to previous products. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore, Xilinx devices do not come with preset thermal solutions. The operating conditions of your design dictate the appropriate solution.
Support for Thermal Models
Xilinx offers and supports a suite of integrated device power analysis tools to help you quickly and accurately estimate your design power requirements.
The variability of design power requirements makes it difficult to apply pre-determined thermal solutions to fit all designs. The estimated power of the device using XPE, coupled with the your operating conditions and system constraints, dictate the appropriate solution. You must establish a thermal margin to account for the impact of the following (but not limited to) variations.
� Impact of the thermal sensor accuracy � Impact of the power variation from one package to another package � Impact of the manufacturing variation between fans � Impact of the manufacturing variation between heat-sink fins � Impact of the package manufacturing variation between heat-sink flatness � Impact of the manufacturing variation of heat sink TIM contact/thickness
For example, when targeting maximum junction temperature (100�C) minus 8�C you must account for any additional system/environmental errors.
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Chapter 11: Thermal Specifications
The detailed thermal model is a direct representation of the specified FCBGA package. The model provides geometric details describing the package, specifically in regards to the lid, TIM, die, underfill, substrate, and solder balls or leads. Each specific component in the detailed model has material properties associated. When using this detailed model, several key facts must be considered:
� Two variations of the detailed thermal model are provided: Full detailed thermal model and simplified thermal model.
� The full detailed thermal model provides all the intricate geometries representing the physical package and can be used for mechanical evaluation of the device. However, it should not be used to perform thermal simulations because the detailed geometries create a large meshing size and high-computation time with little to no increase in overall accuracy.
� The simplified detailed model removes certain geometries including substrate trace layers and stiffener ring that do not have a material impact on thermal simulation accuracy and significantly increase computational time. This simplified model provides a much smaller meshing size and less computation time for simulation with less than a 5% difference in simulation accuracy from the full detailed model.
� The correct package top surface contact must be used when modeling the TIM on top of the detailed model because the top surface contact might not be the actual full package size.
� The junction temperature monitor point is at the die center by default. Junction temperature monitor points need to be positioned or added to the location of interest for your design.
� The uniform power defined in the die for the models provided is default power and does not apply to any specific cases. Power setting input is required.
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Chapter 12: Thermal Management Strategy
Chapter 12
Thermal Management Strategy
Xilinx relies on a multi-pronged approach to consuming less power and dissipating heat for systems using devices.
Flip-Chip Packages
VersalTM devices are offered in flip-chip BGA packages, which present a low thermal path. Packages primarily consist of lidless with stiffener ring variations, with the exception of the baredie packages and lidded packages incorporating a heat spreader with an additional thermal interface material (TIM), as shown in the following figure.
Figure 38: Heat Spreader with Thermal Interface Material
Thermal Interface Material (TIM)
Lid-Heat Spreader Die
Substrate
X22610-040219
Materials with high thermal conductivity and consistent process are expected to be used to deliver low thermal resistance to a heat sink, and are included in lidded packages with a heat spreader. An effort to ensure optimized package electrical return paths produces the added benefit of enhanced power and ground plane arrangement in the packages. A boost in copper density on the planes improves the overall thermal conductivity through the laminate. In addition, the extra dense and distributed via fields in the package increase the vertical thermal conductivity.
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Chapter 12: Thermal Management Strategy
System Level Heat Sink Solutions
To complete a comprehensive thermal management strategy, an overall thermal budget that includes custom or OEM heat sink solutions depends on the physical and mechanical constraints of the system. A heat-sink solution, managed by the system-level designer, should be tailored to the design and specific system constraints. This includes understanding the inherent device capabilities for delivering heat to the surface.
By considering the system's physical, mechanical, and environmental constraints, the overall thermal budget is maintained and does not exceed the device's maximum operating temperature. The heat sink is an integral part of the thermal management solution to maintain a safe operating temperature. As a result, the system-level designer must be aware of the following:
� For lidless packages, the nominal stiffener height can be different from the height of the die. Therefore, the heat sink must have an island to contact the die.
� Especially for lidless packages, Run thermal simulations of the system in worst-case environmental conditions using detailed thermal models, which accurately represent the device thermal performance under all boundary conditions.
� Consider the mechanical specifications of the package as well as the selection of the thermal interface between the die and the thermal management solution to ensure the lowest thermal contact resistance.
� The total thermal contact of the thermal interface material is determined based on parameters from the data sheet supplied by the thermal interface manufacturer.
� See the applied pressure recommendation section. Lower pressure runs the risk of poor thermal contact and higher pressure runs the risk of damaging the device; therefore, strict control of pressure is required. The use of a smart-torque tool is suggested when applying a heat sink to control the rate of short-term transient pressure as the thermal interface material (TIM) relaxes. Specifications from the TIM supplier should be taken into consideration.
� Consider all uncertainties in thermal modeling, including manufacturing variations from the thermal solutions (for example, fan airflow tolerance, heat pipe or vapor chamber performance tolerance, variation of the attachment of fins to heat sink base, and surface flatness).
Thermal Interface Material
When installing heat sinks for Versal devices, a suitable thermal interface material (TIM) must be used. This thermal material significantly aids the transfer of heat from the component to the heat sink.
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Chapter 12: Thermal Management Strategy
For lidless and bare-die flip-chip BGAs, the surface of the silicon contacts the heat sink. For lidded flip-chip BGAs, the lid contacts the heat sink. The surface size of the lidless or bare-die flip-chip BGA and lidded flip-chip BGAs are different. Xilinx recommends a different type of thermal material for long-term use with each type of flip-chip BGAs package.
Thermal interface material is needed because even the largest heat sink and fan cannot effectively cool an Versal device unless there is good physical contact between the base of the heat sink and the top of the Versal device. The surfaces of both the heat sink and the Versal device silicon are not absolutely smooth. This surface roughness is observed when examined at a microscopic level. Because surface roughness reduces the effective contact area, attaching a heat sink without a thermal interface material is not sufficient due to inadequate surface contact.
A thermal interface material such as phase-change material, thermal grease, or thermal pads fills these gaps and allows effective transference of heat between the Versal device die and the heat sink.
The selection of the thermal interface material (TIM) between the package and the thermal management solution is critical to ensure the lowest thermal contact resistance. Therefore, the following parameters must be considered.
1. The flatness of the lid and the flatness of the contact surface of the thermal solution.
2. The applied pressure of the thermal solution on the package, which must be within the allowable maximum pressure that can be applied on the package. The use of a smart-torque tool is suggested when applying a thermal solution to control the rate of short-term transient pressure as the TIM material relaxes. Specifications from the TIM supplier should be taken into consideration.
3. The total thermal contact of the thermal interface material. This value is determined based on the parameters in step 1 and step 2, which are published in the data sheet of the TIM supplier.
Types of TIM
There are many type of TIM available for sale. The most commonly used thermal interface materials are listed.
� Thermal grease � Thermal pads � Phase change material � Thermal paste � Thermal adhesives � Thermal tape
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Chapter 12: Thermal Management Strategy
Guidelines for Thermal Interface Materials
Five factors affect the choice, use, and performance of the thermal interface material (TIM) used between the device and the heat sink. Each factor is discussed in this section.
� Thermal conductivity of the material � Electrical conductivity of the material � Spreading characteristics of the material � Long-term stability and reliability of the material � Ease of application � Applied pressure from heat sink to the package through the TIM
Thermal Conductivity of the Material
Thermal conductivity is the quantified ability of any material to transfer heat. The thermal conductivity of the interface material has a significant impact on its thermal performance. The higher the thermal conductivity, the more efficient the material is at transferring heat. Materials that have a lower thermal conductivity are less efficient at transferring heat, causing a higher temperature differential to exist across the interface. To overcome this less efficient heat transfer, a better cooling solution (typically, a more costly solution) must be used to achieve the desired heat dissipation.
Electrical Conductivity of the Material
Some metal-based TIM compounds are electrically conductive. Ceramic-based compounds are typically not electrically conductive. Manufacturers produce metal-based compounds with lowelectrical conductivity, but some of these materials are not completely electrically inert. Metalbased thermal compounds are not hazardous to the Versal ACAP die itself, but other elements on the Versal device or motherboard can be at risk if they become contaminated by the compound. For this reason, Xilinx does not recommend the use of electrically conductive thermal interface material.
Spreading Characteristics of the Material
The spreading characteristics of the thermal interface material determines its ability, under the pressure of the mounted heat sink, to spread and fill in or eliminate the air gaps between the Versal device and the heat sink. Because air is a very poor thermal conductor, the more completely the interface material fills the gaps, the greater the heat transference.
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Chapter 12: Thermal Management Strategy
Long-Term Stability and Reliability of the Material The long-term stability and reliability of the thermal interface material is described as the ability to provide a sufficient thermal conductance even after an extended time or extensive. Lowquality compounds can harden or leak out over time (the pump-out effect), leading to overheating or premature failure of the Versal device. High-quality compounds provide a stable and reliable thermal interface material throughout the lifetime of the device. Thermal greases with higher viscosity are typically more resistant to pump out effects on bare-die devices.
Ease of Application A spreadable thermal grease requires the surface mount supplier to carefully use the appropriate amount of material. Too much or too little material can cause problems. The thermal pad is a fixed size and is therefore easier to apply in a consistent manner.
Applied Pressure from Heat Sink to the Package via Thermal Interface Materials Measure applied pressure using a calibrated pressure sensor on multiple locations between the device and the heat sink assembly as shown in the following figure.
Figure 39: Pressure Sensor
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Chapter 12: Thermal Management Strategy
RECOMMENDED: Xilinx recommends that the applied pressure on the package be in the range of 20 to 50 PSI for optimum performance of the TIM between the package and the heat sink. Thermocouples should not be present between the package and the heat sink, as their presence will degrade the thermal contact and result in incorrect thermal measurements. The best practice is to select the appropriate pressure (in the 20 to 50 PSI range) for the optimum thermal contact performance between the package and the thermal system solution, and the mechanical integrity of the package (with the thermal solution to pass all mechanical stress and vibration qualification tests). The use of a smart-torque tool is suggested when applying a heat sink to control the rate of short-term transient pressure as the TIM material relaxes. Specifications from the TIM supplier should be taken into consideration.
TIP: These recommendations and specifications are the same for both lidded and lidless devices.
RECOMMENDED: Xilinx recommends using dynamic mounting around the four corners of the device package. On the PCB, use a bracket clip as part of the heat sink attachment to provide mechanical package support. See the following figure.
Figure 40: Dynamic Mounting and Bracket Clips on Heat Sink Attachment
HS Base
Heat Sink
PKG
X22614-040919
Heat Sink Removal
When removing or reworking heat sinks, the phase-change material residue must be removed from the surface of the die. Laird Technologies, Inc. provides the following guidance for complete removal of the phase-change material from the component. Instructions for Removal of Phase-change Material 1. Separate the Components
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Chapter 12: Thermal Management Strategy
At room temperature, if possible, use a back and forth twisting motion to break the bond between the phase-change thermal interface material and mated components (i.e., heat sink and Versal device). See the following figure.
Figure 41: Breaking the Bond between Thermal Interface Material and Mated Components
Phase Change Thermal Interface
Material
Versal ACAP
Heat Sink
X22613-040219
For smaller components (typically 15 mm x 15 mm or less), the bond usually breaks free easily at room temperature. For larger components, in situations where minimal movement is available, or if using fragile components, heat the component (preferred) or heat sink to about 40�C�60�C before removal.
The guideline is 40�C�60�C, however, you might find that for your application, heating to 35�C is adequate. You might prefer to heat to 70�C which makes the phase-change thermal interface material very soft and the components can be easily separated.
2. Scrape Away Thick Residue
For a faster clean-up once components are separated, scrape away any large residual material amounts with a plastic spatula or a wooden tongue depressor. A clean dry rag can be used to wipe away excess material.
3. Clean Remaining Residue with Solvent
Using a clean cloth/wipe, wet it with your choice of solvent (see the following list) and wipe away any remaining residue.
� Toluene (easiest)
� Acetone (very good)
� Isoparaffinic hydrocarbon: Isopar, Soltrol (trade names) (very good)
� Isopropyl alcohol (OK)
4. Working with Laird Material
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Chapter 12: Thermal Management Strategy
Safe handling, disposal, and first-aid measures for working with phase-change material are included in the Laird Technologies material safety data sheet (MSDS). Read the MSDS before using or handling. See the Laird Technologies, Inc. website.
Measurement Debug
When performing in-system thermal testing, to ensure accurate data and not incur damage to the device, do not place a thermocouple in between the device and the heat sink. On the extreme side, it might cause additional mechanical and/or thermal stress to the device, leading to damage. Even if damage does not occur, it often leads to a thicker and or uneven thermal interface material thickness, leading to a thermal performance difference from a system without a thermocouple. To obtain the device temperature, use the System Monitor as a non-invasive means to get accurate device measurements while debugging the system.
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Chapter 13: Heat Sink Guidelines for Bare-die VB Packages
Chapter 13
Heat Sink Guidelines for Bare-die VB Packages
Heat Sink Attachments
Heat sinks can be attached to the package in multiple ways. For heat to dissipate effectively, the advantages and disadvantages of each heat sink attachment method must be considered. Factors influencing the selection of the heat sink attachment method include the package type, contact area of the heat source, and the heat sink type.
Silicon and Decoupling Capacitors Height Consideration
When designing heat sink attachments for bare-die flip-chip BGA packages, the height of the die above the substrate and also the height of decoupling capacitors must be considered (see the following figure). This is to prevent electrical shorting between the heat sink (metal) and the decoupling capacitors.
Figure 42: Cross Section of Bare-die Flip-chip BGA
Decoupling Capacitor
Silicon
Underfill
Substrate
X22615-040219
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Chapter 13: Heat Sink Guidelines for Bare-die VB Packages
Types of Heat Sink Attachments
There are six main methods for heat sink attachment. The following table lists their advantages and disadvantages.
� Thermal tape � Thermally conductive adhesive or glue � Wire form Z-clips � Plastic clip-ons � Threaded stand-offs (PEMs) and compression springs � Push-pins and compression springs
Table 27: Heat Sink Attachment Methods
Attachment Method
Thermal tape
Thermally conductive adhesive or glue
Wire form Z-clips
Plastic clip-ons
Advantages
Disadvantages
� Generally it is easy to attach and is
inexpensive
� Lowest cost approach for aluminum heat
sink attachment
� No additional space required on the PCB
� The surfaces of the heat sink and the chip
must be very clean to allow the tape to bond correctly
� Because of the small contact area, the tape
might not provide sufficient bond strength
� Tape is a moderate to low thermal
conductor that could affect the thermal performance
� Outstanding mechanical adhesion � Somewhat inexpensive, costs a little more
than tape
� No additional space required on the PCB
� Adhesive application process is challenging
and it is difficult to control the amount of adhesive to use.
� Difficult to rework
� Because of the small contact area, the
adhesive might not provide sufficient bond strength
� It provides a strong and secure mechanical � Requires additional space on the PCB for
attachment. In environments that require
anchor locations
shock and vibration testing, this type of
strong mechanical attachment is necessary.
� Easy to apply and remove. Does not cause
the semiconductors to be destroyed (epoxy
and occasionally tape can destroy the
device).
� It applies a preload onto the thermal
interface material (TIM). Preloads actually
improve thermal performance.
� Suitable for designs where space on the
� Needs a keep out area around the silicon
PCB is limited
devices to use the clip
� Easy to rework by allowing heat sinks to be � Caution is required when installing or
easily removed and reapplied without
removing clip-ons because localized stress
damaging the PCB board
can damage the solder balls or chip
� Can provide a strong enough mechanical
substrate
attachment to pass shock and vibration test
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Chapter 13: Heat Sink Guidelines for Bare-die VB Packages
Table 27: Heat Sink Attachment Methods (cont'd)
Attachment Method
Threaded stand-offs (PEMs) and compression springs
Push-pins and compression springs
Advantages
Disadvantages
� Provides stable attachments to heat source � Holes are required in the PCB taking
and transfers load to the PCB, backing
valuable space that can be used for trace
plate, or chassis
lines
� Suitable for high mass heat sinks
� Tends to be expensive, especially because
� Allows for tight control over mounting force
and load placed on chip and solder balls
holes need to be drilled or predrilled onto the PCB board to use stand-offs
� Provides a stable attachment to a heat
� Requires additional space on the PCB for
source and transfers load to the PCB
push-pin locations
� Allows for tight control over mounting force
and load placed on chip and solder balls
Heat Sink Attachment Process Considerations
After the component is placed onto the PCBs, when attaching a heat sink to the bare-die package, the factors in the following table must be carefully considered (as shown in the following figure).
Table 28: Heat Sink Attachment Considerations
Consideration(s)
Effect(s)
Recommendation(s)
In a heat sink attach process, �
what factors can cause damage to the exposed die and passive
�
capacitors?
�
Uneven heat sink placement
Uneven TIM thickness
Uneven force applied when placing heat sink placement
� Even heat sink placement
� Even TIM thickness
� Even force applied when placing heat sink
placement
Does the heat sink tilt or tip the � Uneven heat sink placement will � Careful handling not to contact the heat sink
post attachment?
damage the silicon and can cause
with the post attachment
field failures
� Use a fixture to hold the heat sink in place
with post attachment until it is glued to the
silicon
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Chapter 13: Heat Sink Guidelines for Bare-die VB Packages
Figure 43: Recommended Application of Heat Sink
Even Force
Preferred
Even Force
Incorrect Alignment
Decoupling Capacitor
Silicon Substrate
Silicon Substrate
Decoupling Capacitor
Even Force
Preferred
Even Force
Incorrect Force
Heat Sink Silicon
Substrate
Mother Board
Preferred application of heat sink 1. Heat sink is aligned parallel to silicon 2. Even bond line thickness of TIM 3. Even compressive force is applied on all sides
Silicon Substrate
Decoupling Capacitor
Improper application of heat sink can cause damage to heat sink
1. Heat sink is not aligned parallel to silicon 2. Uneven bond line thickness of TIM 3. Uneven force is applied
X22618-040219
Standard Heat Sink Attach Process with Thermal Conductive Adhesive
Prior to attaching the heat sink, theVersal device needs be surface mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent any movement during the heat sink attachment process.
2. Thermoset material (electrically non-conductive) is applied over the backside surface of silicon in a pattern using automated dispensing equipment. Automated dispensers are often used to provide a stable process speed at a relatively low cost. The optimum dispensing pattern needs to be determined by the SMT supplier.
Note: Minimal volume coverage of the backside of the silicon can result in non-optimum heat transfer
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A uniform pressure is applied over the heat sink to the backside of the silicon. As the heat sink is placed, the adhesive spreads to cover the backside silicon. A force transducer is normally used to measure and limit the placement force.
4. The epoxy is cured with heat at a defined time.
Note: The epoxy curing temperature and time is based on manufacturer's specifications.
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Chapter 13: Heat Sink Guidelines for Bare-die VB Packages
Standard Heat Sink Attach Process with Thermal Adhesive Tape
Prior to attaching the heat sink, the Versal device needs be surface mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent any movement during the heat sink attachment process.
2. Thermal adhesive tape cut to the size of the heat sink is applied on the underside of the heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to help reduce the possibility of air entrapment under the tape during application.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A uniform pressure is applied over the heat sink to the backside of the silicon. As the heat sink is placed, the thermal adhesive tape is glued to the backside of the silicon. A force transducer is normally used to measure and limit the placement force.
4. A uniform and constant pressure is applied uniformly over the heat sink and held for a defined time.
Note: The thermal adhesive tape hold time is based on manufacturer's specifications.
Push-Pin and Shoulder Screw Heat Sink Attachment Process with Phase Change Material (PCM) Application
Prior to attaching the heat sink, the Versal device needs be surface mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent any movement during the heat sink attachment process.
Note: The jig or fixture needs to account for the push pin depth of the heat sink.
2. PCM tape, cut to the size of the heat sink, is applied on the underside of the heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to help reduce the possibility of air entrapment under the tape during application.
3. Using the push-pin tool, heat sinks are applied over the packages ensuring a pin locking action with the PCB holes. The compression load from springs applies the appropriate mounting pressure required for proper thermal interface material performance.
Note: Heat sinks must not tilt during installation. This process cannot be automated due to the mechanical locking action which requires manual handling. The PCB drill hole tolerances need to be close enough to eliminate any issues concerning the heat sink attachment.
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Chapter 14: Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages
Chapter 14
Mechanical and Thermal Design
Guidelines for Lidless Flip-chip
Packages
This section discusses the challenges of thermal management including reducing device thermal resistance and optimal power dissipation without an increase in junction temperature. The lidless Versal ACAP packages target the largest devices while allowing for cooler operation temperatures (up to 10�C) with the same power dissipation. Precise mechanical design and component thermal management is vital for device and system performance. This document presents the unique thermal and mechanical design requirements for lidless devices.
Lidless Flip-Chip Packages
The Xilinx flip-chip BGA packages exhibit a low-resistance thermal path that adequately cools devices. These packages incorporate a heat spreader lid with additional thermal interface material as shown in the following figure.
Figure 44: Flip-Chip BGA Construction with Heat Spreader and Thermal Interface Material
Thermal Interface Material
Heat Spreader Lid
BGA Construction
X23792-032620
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Chapter 14: Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages
Materials with high thermal conductivity and consistent process applications deliver low thermal resistance up to the heat spreader. A parallel effort to ensure optimized package electrical return paths produces an enhanced power and ground plane arrangement in the package. A boost in copper density on the planes improves the overall thermal conductivity through the laminate. The extra density and distribution via fields in the package also increases the vertical thermal conductivity.
The lidless packages (see the following figure) offer the same package substrate design with electrical and board thermal conductivity similar to the flip-chip BGA packages. However, removing the lid (heat spreader) and the thermal interface material allows for direct contact between the external heat sink and the die. This further reduces the thermal resistance and exhibits improved thermal behaviors. The use of custom passive or active heat-sink designs is facilitated by incorporating two-phase (heat pipe, vapor chamber, or even liquid) cooling methods directly adjacent to the source of the dissipated heat on the die, which allows for a more efficient means of removing the heat from the device. Consequently, the device can operate at higher ambient temperatures while in area-constrained surroundings resulting in operational power advantages.
Figure 45: Lidless Flip-Chip BGA Construction
X23791-032620
A unique feature of lidless packages is the addition of a stiffener ring around the periphery of the package substrate, providing additional package rigidity and helping to improve the overall package coplanarity (flatness). It also serves as a guide for the heat sink solution applied to the device. For examples, see the VSVD1760 Package--VC1802, VC1902, and VM1802 or VSVA2197 Package--VC1802, VC1902, and VM1802. In the lidless packages, capacitors can be placed in the area surrounding the die. Contact with electrically conductive materials must be avoided because the die-side capacitors, which are only slightly shorter than the die height, could be electrically conductive. Any thermal and mechanical solution higher than the die must not interfere with the package stiffener. Therefore, the thermal solution must have an island, see System Level Heat Sink Solutions. For further guidelines on mechanical and thermal designs of lidless packages, refer to Mechanical and Thermal Design Guidelines for Lidless Flip-Chip Packages (XAPP1301).
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Appendix A: Additional Resources and Legal Notices
Appendix A
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.
Documentation Navigator and Design Hubs
Xilinx� Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open DocNav: � From the Vivado� IDE, select HelpDocumentation and Tutorials. � On Windows, select StartAll ProgramsXilinx Design ToolsDocNav. � At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: � In DocNav, click the Design Hubs View tab. � On the Xilinx website, see the Design Hubs page. Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
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Appendix A: Additional Resources and Legal Notices
References
These documents provide supplemental material useful with this guide: 1. Versal ACAP data sheets:
� Versal Architecture and Product Data Sheet: Overview (DS950) � Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) � Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) 2. Versal ACAP SelectIO Resources Architecture Manual (AM010)
Heat Management and Contact Information The following websites contain additional information on heat management and contact information. � Wakefield � Boyd/Aavid � Advanced Thermal Solutions � Radian Thermal Products � Thermo Cool � CTS
Interface Material Sources � Henkel � AOS Thermal Compound � Parker Chomerics � Kester
CDF Tools Refer to the following websites for CFD tools Xilinx supports with thermal models. � Mentor Flotherm � ANSYS Icepak
Thermal Modeling References The following papers are referenced for more information on thermal modeling.
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Appendix A: Additional Resources and Legal Notices
� Lemczyk, T.F., Mack, B., Culham, J.R. and Yovanovich, M.M., 1992, "Printed Circuit Board Trace Thermal Analysis and Effective Conductivity", ASME J. Electronic Packaging, Vol. 114, pp. 413 - 419.50.
� Refai-Ahmed, G. and Karimanal, K., 2003, "Validation of Compact Conduction Models of BGA Under Realistic Boundary," J. of Components and Packaging Technology, Vol. 26, No. 3, pp. 610-615.
� Sansoucy, E, Refai-Ahmed, G., and Karimanal, K., 2002, "Thermal Characterization of TBGA Package for an integration in Board Level Analysis," Eighth Intersociety on Thermal Conference Phenomena in Electronic Systems, San Diego., USA.
� Karimanal, K. and Refai-Ahmed, G., 2002, "Validation of Compact Conduction Models of BGA Under Realistic Boundary Conditions," Eighth Intersociety on Thermal Conference Phenomena in Electronic Systems, San Diego, USA.
� Karminal, K. and Refai-Ahmed, G., 2001, "Compact conduction Model (CCM) of Microelectronic Packages- A BGA Validation Study," APACK Conference on Advances in Packaging, Singapore.
Please Read: Important Legal Notices
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https:// www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.
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Appendix A: Additional Resources and Legal Notices
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or services not yet available for sale, and provided solely for information purposes and are not intended, or to be construed, as an offer for sale or an attempted commercialization of the products and/or services referred to herein.
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