Data Sheet Final - ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin Embedded Processor, Rev. E

Data Sheet Final - ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin Embedded Processor, Rev. E

ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin Embedded Processor

ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 Blackfin Embedded Processor Data Sheet (Rev. E)

Blackfin Embedded Processors | Analog Devices

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Blackfin Embedded Processor
ADSP-BF512/BF514/BF516/BF518

FEATURES
Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See Operating Conditions Qualified for Automotive Applications. See Automotive
Products 168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)
MEMORY
116K bytes of on-chip memory External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories Flexible booting options from OTP memory, external
SPI/parallel memories, or from SPI/UART host devices Code security with Lockbox secure technology One-time-programmable (OTP) memory Memory management unit providing memory protection

PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 support (ADSP-BF518 only)
Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats
2 dual-channel, full-duplex synchronous serial ports (SPORTs), supporting 8 stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC 2 memory-to-memory DMAs with external request lines Event handler with 56 interrupt inputs 2 serial peripheral interfaces (SPI) Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA 2 UARTs with IrDA support 2-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support 3-phase 16-bit center-based PWM unit 32-bit general-purpose counter Real-time clock (RTC) and watchdog timer 32-bit core timer 40 general-purpose I/Os (GPIOs) Debug/JTAG interface On-chip PLL capable of frequency multiplication

RTC

OTP

WATCHDOG TIMER

PERIPHERAL ACCESS BUS

JTAG TEST AND EMULATION

B

INTERRUPT CONTROLLER

L1 INSTRUCTION
MEMORY

L1 DATA MEMORY

DMA CONTROLLER

16

DMA CORE BUS

EXTERNAL ACCESS BUS

DMA EXTERNAL
BUS

EXTERNAL PORT FLASH, SDRAM CONTROL

BOOT ROM

COUNTER 3-PHASE PWM
TIMER7�0 TWI
SPORT1-0 RSI (SDIO)
PPI UART1�0
EMAC SPI1 SPI0

PORTS

Figure 1. Functional Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. E

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ADSP-BF512/BF514/BF516/BF518
TABLE OF CONTENTS
Features ................................................................. 1 Memory ................................................................ 1 Peripherals ............................................................. 1 Table of Contents ..................................................... 2 Revision History ...................................................... 2 General Description ................................................. 3
Portable Low Power Architecture ............................. 3 System Integration ................................................ 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 5 Event Handling .................................................... 6 DMA Controllers .................................................. 6 Processor Peripherals ............................................. 7 Lockbox Secure Technology Disclaimer ................... 11 Dynamic Power Management ................................ 11 Voltage Regulation Interface .................................. 12 Clock Signals ..................................................... 12 Booting Modes ................................................... 14 Instruction Set Description ................................... 15 Development Tools ............................................. 15

Additional Information ........................................ 16 Related Signal Chains ........................................... 16 Signal Descriptions ................................................. 17 Specifications ........................................................ 20 Operating Conditions ........................................... 20 Electrical Characteristics ....................................... 22 Absolute Maximum Ratings ................................... 25 ESD Sensitivity ................................................... 25 Timing Specifications ........................................... 26 Output Drive Currents ......................................... 49 Test Conditions .................................................. 51 Thermal Characteristics ........................................ 55 176-Lead LQFP_EP Lead Assignment ......................... 56 168-Ball CSP_BGA Ball Assignment ........................... 58 Outline Dimensions ................................................ 60 Surface-Mount Design .......................................... 61 Automotive Products .............................................. 62 Ordering Guide ..................................................... 63

REVISION HISTORY
6/20--Rev. D to Rev. E This Rev E product data sheet removes the Flash Memory section, flash memory specifications, and all obsolete models that include 16M bit SPI flash memory. These changes are reflected in the following sections: Changes to Memory ................................................. 1 Changes to Peripherals .............................................. 1 Changes to Functional Block Diagram .......................... 1 Changes to Processor Comparison ............................... 3 Changes to Power Domains ...................................... 12 Changes to Booting Modes ....................................... 14 Changes to Signal Descriptions ................................. 17 Changes to Operating Conditions .............................. 20 Changes to Electrical Characteristics ........................... 22 Changes to 176-Lead LQFP_EP Lead Assignment .......... 56 Changes to 168-Ball CSP_BGA Ball Assignment ............ 58 Changes to Ordering Guide ...................................... 63

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GENERAL DESCRIPTION
The ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 processors are members of the Blackfin� family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-ofthe-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
The processors are completely code compatible with other Blackfin processors.
Table 1. Processor Comparison

ADSP-BF512 ADSP-BF514 ADSP-BF516 ADSP-BF518

Memory (bytes)

Feature IEEE-1588 Ethernet MAC RSI TWI SPORTs UARTs SPIs GP Timers Watchdog Timers RTC PPI Rotary Counter 3-Phase PWM Pairs GPIOs
L1 Instruction SRAM L1 Instruction SRAM/Cache L1 Data SRAM L1 Data SRAM/Cache L1 Scratchpad L3 Boot ROM Maximum Speed Grade Package Options

���1 ��11 �111 1111 2222 2222 2222 8888 1111 1111 1111 1111 3333 40 40 40 40
32K 16K 32K 32K 4K 32K 400 MHz 176-Lead LQFP_EP (with Exposed Pad) 168-Ball CSP_BGA

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.

ADSP-BF512/BF514/BF516/BF518
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF51x processors are highly integrated system-on-achip solutions for the next generation of embedded network connected applications. By combining industry-standard interfaces with a high performance signal processing core, costeffective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC with IEEE-1588 support (ADSP-BF518 only), an RSI controller, a TWI controller, two UART ports, two SPI ports, two serial ports (SPORTs), nine general-purpose 32-bit timers (eight with PWM capability), 3-phase PWM for motor control, a real-time clock, a watchdog timer, and a parallel peripheral interface (PPI).
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. The compare/select and vector search instructions are also provided.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible.

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ADDRESS ARITHMETIC UNIT

DA1 32 DA0 32

I3 L3 B3

M3

I2 L2 B2

M2

I1 L1 B1

M1

I0 L0 B0

M0

32 RAB

DAG1

DAG0

SP FP P5 P4 P3 P2 P1 P0
32 PREG

TO MEMORY

SD

32

LD1

32

LD0

32

32 32

R7.H R7.L

R6.H R6.L

R5.H R5.L

R4.H R4.L

16

R3.H R3.L

8

8

8

R2.H R2.L

R1.H R1.L

BARREL

R0.H R0.L

SHIFTER

40

A0

40 40

32

32

DATA ARITHMETIC UNIT

ASTAT
16 8
40 A1

SEQUENCER
ALIGN DECODE LOOP BUFFER
CONTROL UNIT

Figure 2. Blackfin Processor Core

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).
Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information.
In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.
The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle.

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The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF51x processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. The memory map for both internal and external memory space is shown in Figure 3.

0xFFFF FFFF 0xFFE0 0000 0xFFC0 0000 0xFFB0 1000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFFA0 8000 0xFFA0 4000 0xFFA0 0000 0xFF90 8000 0xFF90 4000 0xFF90 0000 0xFF80 8000 0xFF80 4000 0xFF80 0000 0xEF00 8000 0xEF00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x08 00 0000 0x0000 0000

CORE MMR REGISTERS (2M BYTES) SYSTEM MMR REGISTERS (2M BYTES) RESERVED SCRATCHPAD SRAM (4K BYTES) RESERVED INSTRUCTION BANK C SRAM/CACHE (16K BYTES) RESERVED INSTRUCTION BANK B SRAM (16K BYTES) INSTRUCTION BANK A SRAM (16K BYTES) RESERVED DATA BANK B SRAM / CACHE (16K BYTES) DATA BANK B SRAM (16K BYTES) RESERVED DATA BANK A SRAM / CACHE (16K BYTES) DATA BANK A SRAM (16K BYTES) RESERVED BOOT ROM (32K BYTES) RESERVED ASYNC MEMORY BANK 3 (1M BYTES) ASYNC MEMORY BANK 2 (1M BYTES) ASYNC MEMORY BANK 1 (1M BYTES) ASYNC MEMORY BANK 0 (1M BYTES) RESERVED SDRAM MEMORY (16M BYTES - 128M BYTES)

Figure 3. ADSP-BF51x Internal/External Memory Map

EXTERNAL MEMORY MAP

INTERNAL MEMORY MAP

The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory.
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.
Internal (On-Chip) Memory
The ADSP-BF51x processors have three blocks of on-chip memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of 48K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed.
The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices.
The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank, and the SDRAM controller supports up to four internal SDRAM banks, improving overall performance.
The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory.
One-Time Programmable Memory
The processors have 64K bits of one-time programmable nonvolatile memory that can be programmed by the developer only once. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected.
The OTP memory allows both public and private data to be stored on-chip. In addition to storing public and private key data for applications requiring security, OTP allows developers to store completely user-definable data such as customer ID, product ID, and MAC address. Therefore, generic parts can be supplied which are then programmed and protected by the developer within this non-volatile memory.

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I/O Memory Space
The processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memorymapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.
Booting from ROM
The processors contain a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes.
EVENT HANDLING
The event controller handles all asynchronous and synchronous events to the processor. The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event.
The controller provides support for five different types of events:
� Emulation--An emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface.
� Reset--This event resets the processor.
� Nonmaskable Interrupt (NMI)--The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system.
� Exceptions--Events that occur synchronously to program flow; that is, the exception is taken before the instruction is allowed to complete. Conditions such as data alignment violations and undefined instructions cause exceptions.
� Interrupts--Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.
The event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.

Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15�7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15�14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processors. The inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities are described in the ADSP-BF51x Blackfin Processor Hardware Reference Manual "System Interrupts" chapter.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor Hardware Reference Manual "System Interrupts" chapter for the inputs into the SIC and the default mappings into the CEC.
The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events. For more information, see the ADSP-BF51x Blackfin Processor Hardware Reference Manual "System Interrupts" chapter.
DMA CONTROLLERS
The ADSP-BF51x processors have multiple independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMAcapable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.
The processors' DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to �32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly.

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Examples of DMA types supported by the DMA controller include:
� A single, linear buffer that stops upon completion
� A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer
� 1-D or 2-D DMA using a linked list of descriptors
� 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are two memory DMA channels that transfer data between the various memories of the processor system. This enables transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.
The processors also have an external DMA controller capability via dual external DMA request signals when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core.
PROCESSOR PERIPHERALS
The ADSP-BF51x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 2). The processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios.
All of the peripherals, except for the general-purpose I/O, rotary counter, TWI, three-phase PWM, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
Real-Time Clock
The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the processors. The RTC peripheral has a dedicated power supply so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.
The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state.
Connect RTC signals RTXI and RTXO with external components as shown in Figure 4.

RTXI

RTXO

R1

X1

C1

C2

SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M: NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 4. External Components for RTC
Watchdog Timer
The ADSP-BF51x processors include a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.

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If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.
The timer is clocked by the system clock (SCLK) at a maximum frequency of fSCLK.
Timers
There are nine general-purpose programmable timer units in the ADSP-BF51x processors. Eight timers have an external signal that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF signals, an external clock input to the PPI_CLK input signal, or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals.
In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
3-Phase PWM
The processors integrate a flexible and programmable 3-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction (ACIM) or permanent magnet synchronous (PMSM) motor control. In addition, the PWM block contains special functions that considerably simplify the generation of the required PWM switching patterns for control of the electronically commutated motor (ECM) or brushless dc motor (BDCM). Software can enable a special mode for switched reluctance motors (SRM).
Features of the 3-phase PWM generation unit are:
� 16-bit center-based PWM generation unit
� Programmable PWM pulse width
� Single/double update modes
� Programmable dead time and switching frequency
� Twos-complement implementation which permits smooth transition to full ON and full OFF states
� Possibility to synchronize the PWM generation to an external synchronization
� Special provisions for BDCM operation (crossover and output enable functions)
� Wide variety of special switched reluctance (SR) operating modes

� Output polarity and clock gating control
� Dedicated asynchronous PWM shutdown signal
General-Purpose (GP) Counter
A 32-bit GP counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input signal or by two edge detectors.
A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three signals have a programmable debouncing circuit.
An internal signal forwarded to the GP timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded.
Serial Ports
The ADSP-BF51x processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:
Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared.
Serial ports operate in five modes:
� Standard DSP serial mode
� Multichannel (TDM) mode � I2S mode � Packed I2S mode
� Left-justified mode
Serial Peripheral Interface (SPI) Ports
The processors have two SPI-compatible ports (SPI0 and SPI1) that enable the processor to communicate with multiple SPIcompatible devices.
The SPI interface uses three signals for transferring data: two data signals (master output-slave input�MOSI, and master input-slave output�MISO) and a clock signal (serial clock�SCK). An SPI chip select input signal (SPIxSS) lets other SPI devices select the processor, and multiple SPI chip select output signals let the processor select other SPI devices. The SPI select signals are reconfigured general-purpose I/O signals. Using these signals, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.

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The SPI port baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The DMA channel of the SPI can only service unidirectional accesses at any given time.
UART Ports
The processors provide two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminates by one, one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control through the Clear To Send (CTS) input and Request To Send (RTS) output with programmable assertion FIFO levels.
To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a programmable inter-frame space.
The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA�) serial infrared physical layer link specification (SIR) protocol.
2-Wire Interface (TWI)
The processors include a TWI module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C� bus standard. The TWI module offers the capabilities of simultaneous master and slave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two signals for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface signals are compatible with 5 V logic levels.
Additionally, the processor's TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices.
Removable Storage Interface (RSI)
The RSI controller, available on the ADSP-BF514/ADSPBF516/ADSP-BF518 processors, acts as the host interface for multi-media cards (MMC), secure digital memory cards (SD Card), secure digital input/output cards (SDIO), and CE-ATA hard disk drives. The following list describes the main features of the RSI controller.
� Support for a single MMC, SD memory, SDIO card or CEATA hard disk drive
� Support for 1-bit and 4-bit SD modes
� Support for 1-bit, 4-bit and 8-bit MMC modes
� Support for 4-bit and 8-bit CE-ATA hard disk drives

ADSP-BF512/BF514/BF516/BF518
� A ten-signal external interface with clock, command, and up to eight data lines
� Card detection using one of the data signals
� Card interface clock generation from SCLK
� SDIO interrupt and read wait features
� CE-ATA command completion signal recognition and disable
10/100 Ethernet MAC
The ADSP-BF516 and ADSP-BF518 processors offer the capability to directly connect to a network by way of an embedded fast Ethernet media access controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system.
Some standard features are:
� Support of MII and RMII protocols for external PHYs
� Full duplex and half duplex modes
� Data framing and encapsulation: generation and detection of preamble, length padding, and FCS
� Media access management (in half-duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing
� Flow control (in full-duplex operation): generation and detection of pause frames
� Station management: generation of MDC/MDIO frames for read-write access to PHY registers
� Operating range for active and sleep operating modes, see Table 39 and Table 40
� Internal loopback from transmit to receive
Some advanced features are:
� Buffered crystal output to external PHY for support of a single crystal system
� Automatic checksum computation of IP header and IP payload fields of Rx frames
� Independent 32-bit descriptor-driven receive and transmit DMA channels
� Frame status delivery to memory through DMA, including frame completion semaphores for efficient buffer queue management in software
� Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations
� Convenient frame alignment modes support even 32-bit alignment of encapsulated receive or transmit IP packet data in memory after the 14-byte MAC header

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ADSP-BF512/BF514/BF516/BF518

� Programmable Ethernet event interrupt supports any combination of:
� Selected receive or transmit frame status conditions
� PHY interrupt condition
� Wakeup frame detected
� Selected MAC management counter(s) at half-full
� DMA descriptor error
� 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value
� Programmable receive address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames
� Advanced power management supporting unattended transfer of receive and transmit frames and status to/from external memory via DMA during low power sleep mode
� System wakeup from sleep operating mode upon magic packet or any of four user-definable wakeup frame filters
� Support for 802.3Q tagged VLAN frames
� Programmable MDC clock rate and preamble suppression
� In RMII operation, seven unused signals may be configured as GPIO signals for other purposes
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The ADSP-BF518 processor includes hardware support for IEEE 1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the PTP_SYNC engine are:
� Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards
� Hardware assisted time stamping capable of up to 12.5 ns resolution
� Lock adjustment
� Programmable PTM message support
� Dedicated interrupts
� Programmable alarm
� Multiple input clock sources (SCLK, MII clock, external clock)
� Programmable pulse per second (PPS) output
� Auxiliary snapshot to time stamp external events
Ports
Because of the rich set of peripherals, the processors group the many peripheral signals to four ports--port F, port G, port H, and port J. Most of the associated pins/balls are shared by multiple signals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, generalpurpose I/O (GPIO) signals allocated across three separate GPIO modules--PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Each GPIO-capable signal shares functionality with other peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by default. Each general-purpose port signal can be individually controlled by manipulation of the port control, status, and interrupt registers.
Parallel Peripheral Interface (PPI)
The ADSP-BF51x processors provide a parallel peripheral interface (PPI) that can connect directly to parallel analog-to-digital and digital-to-analog converters, ITU-R-601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock signal, up to three frame synchronization signals, and up to 16 data signals.
In ITU-R-656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported.
Three distinct ITU-R-656 modes are supported:
� Active video only mode--The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI.
� Vertical blanking only mode--The PPI only transfers vertical blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines.
� Entire field mode--The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R-656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor's 2-D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle:
� Data receive with internally generated frame syncs
� Data receive with externally generated frame syncs
� Data transmit with internally generated frame syncs
� Data transmit with externally generated frame syncs

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ADSP-BF512/BF514/BF516/BF518

These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.
Code Security with Lockbox Secure Technology
A security system consisting of a blend of hardware and software provides customers with a flexible and rich set of code security features with Lockbox� secure technology. Key features include:
� OTP memory
� Unique chip ID
� Code authentication
� Secure mode of operation
The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets.
LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices does not guarantee that the Code Security with Lockbox Secure Technology described herein provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY.
DYNAMIC POWER MANAGEMENT
The ADSP-BF51x processors provide four operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. When configured for a 0 V core supply voltage, the processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 2 for a summary of the power settings for each mode.

Table 2. Power Settings

Mode/State PLL

Core

PLL

Clock

Bypassed (CCLK)

System Clock Core (SCLK) Power

Full On

Enabled No

Enabled Enabled On

Active

Enabled/ Yes Disabled

Enabled Enabled On

Sleep

Enabled --

Disabled Enabled On

Deep Sleep Disabled --

Disabled Disabled On

Hibernate Disabled --

Disabled Disabled Off

Full-On Operating Mode--Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.
Active Operating Mode--Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. DMA access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the full-on or sleep modes.
Sleep Operating Mode--High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity wakes up the processor. When in the sleep mode, asserting wakeup causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full on mode. If BYPASS is enabled, the processor transitions to the active mode.
System DMA access to L1 memory is not supported in sleep mode.
Deep Sleep Operating Mode--Maximum Dynamic Power Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode.
Hibernate State--Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and system blocks (SCLK). Any critical information stored internally (for example memory contents, register contents) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Writing b#00 to the FREQ bits in the VR_CTL register also causes the EXT_WAKE signal to transition low, which can be used to signal an external voltage regulator to shut down.

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ADSP-BF512/BF514/BF516/BF518

Since VDDEXT is still supplied in this mode, all of the external signals three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current.
The Ethernet module can signal an external regulator to wake up using the EXT_WAKE signal. If PF15 does not connect as a PHYINT signal to an external PHY device, it can be pulled low by any other device to wake the processor up. The processor can also be woken up by a real-time clock wakeup event or by asserting the RESET pin. All hibernate wakeup events initiate the hardware reset sequence. Individual sources are enabled by the VR_CTL register. The EXT_WAKE signal is provided to indicate the occurrence of wakeup events.
With the exception of the VR_CTL and the RTC registers, all internal registers and memories lose their content in the hibernate state. State variables may be held in external SRAM or SDRAM. The SCKELOW bit in the VR_CTL register controls whether or not SDRAM operates in self-refresh mode, which allows it to retain its content while the processor is in hibernation and through the subsequent reset sequence.
Power Savings
As shown in Table 3, the processors support up to six different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor Operating Conditions; even if the feature/peripheral is not used.

Table 3. Power Domains
Power Domain All internal logic, except RTC, Memory, OTP RTC internal logic and crystal I/O Memory logic OTP logic All other I/O

VDD Range VDDINT VDDRTC VDDMEM VDDOTP VDDEXT

The dynamic power management feature of the processor allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%.

Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations.

Power Savings Factor

=

-f--C----C---L---K---R----E---D-fCCLKNOM



 

V-V----D-D---D-D--I-I-N-N---T-T--N-R---OE---D-M--

2



 

-T----R----E---D-TNOM

 

% Power Savings = 1 � Power Savings Factor  100%
where the variables in the equations are:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
VOLTAGE REGULATION INTERFACE
The ADSP-BF51x processors require an external voltage regulator to power the VDDINT domain. To reduce standby power consumption in the hibernate state, the external voltage regulator can be signaled through EXT_WAKE to remove power from the processor core. The EXT_WAKE signal is high-true for power-up and may be connected directly to the low-true shut down input of many common regulators.
The Power Good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of the PG functionality, refer to the ADSP-BF51x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
The ADSP-BF51x processors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor CLKIN signal. When an external clock is used, the XTAL pin/ball must be left unconnected.
Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 5. A parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the CLKIN and XTAL pins/balls. The on-chip resistance between the CLKIN pin/ball and the XTAL pin/ball is in the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in Figure 5 fine tune phase and amplitude of the sine frequency.

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The capacitor and resistor values shown in Figure 5 are typical values only. The capacitor values are dependent upon the crystal manufacturers' load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range.

CLKOUT CLKBUF

BLACKFIN
TO PLL CIRCUITRY EN

560  EN

CLKIN 330 *

XTAL
FOR OVERTONE OPERATION ONLY:

18 pF *

18 pF *

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0 .
Figure 5. External Crystal Connections
A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in Figure 5. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)--use site search on "EE-168."
The CLKBUF signal is an output signal, which is a buffered version of the input clock. This signal is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 6, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable 5� to 64� multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 6�, but it can be modified by a software instruction sequence.
On-the-fly frequency changes can be done simply by writing to the PLL_DIV register. The maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT, VDDEXT, and VDDMEM, and the VCO is always permitted to run up to the frequency specified by the part's speed grade. The CLKOUT signal

ADSP-BF512/BF514/BF516/BF518

reflects the SCLK frequency to the off-chip world. It belongs to the SDRAM interface, but it functions as a reference signal in other timing specifications as well. While active by default, it can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL registers.

"FINE" ADJUSTMENT REQUIRES PLL SEQUENCING

"COARSE" ADJUSTMENT ON-THE-FLY

CLKIN

PLL 5u to 64u

VCO

� 1, 2, 4, 8 � 1 to 15

CCLK SCLK

Figure 6. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3�0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 4 illustrates typical system clock ratios.

Table 4. Example System Clock Ratios

Signal Name SSEL3�0 0010 0110 1010

Example Frequency Ratios

Divider Ratio (MHz)

VCO/SCLK VCO

SCLK

2:1

100

50

6:1

300

50

10:1

400

40

Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1�0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 5. This programmable core clock capability is useful for fast core frequency modifications.

Table 5. Core Clock Ratios

Signal Name CSEL1�0 00 01 10 11

Example Frequency Ratios

Divider Ratio (MHz)

VCO/CCLK VCO

CCLK

1:1

300

300

2:1

300

150

4:1

400

100

8:1

200

25

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ADSP-BF512/BF514/BF516/BF518

The maximum CCLK frequency not only depends on the part's speed grade (see Page 63), it also depends on the applied VDDINT voltage. See Table 9 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied VDDINT, VDDEXT, and VDDMEM voltages (see Table 11).
BOOTING MODES
The processor has several mechanisms (listed in Table 6) for automatically loading internal and external memory after a reset. The boot mode is defined by three BMODE input bits dedicated to this purpose. There are two categories of boot modes. In master boot modes the processor actively loads data from parallel or serial memories. In slave boot modes the processor receives data from external host devices.
The boot modes listed in Table 6 provide a number of mechanisms for automatically loading the processor's internal and external memories after a reset. By default, all boot modes use the slowest meaningful configuration settings. Default settings can be altered via the initialization code feature at boot time or by proper OTP programming at pre-boot time. The BMODE bits of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the modes shown in Table 6.

Table 6. Booting Modes

BMODE2�0 Description

000

Idle - No boot

001

Boot from 8- or 16-bit external flash memory

010

Reserved

011

Boot from external SPI memory (EEPROM or flash)

100

Boot from SPI0 host

101

Boot from OTP memory

110

Boot from SDRAM

111

Boot from UART0 Host

� Idle/no boot mode (BMODE = 0x0)--In this mode, the processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the user has mis configured the OTP memory.
� Boot from 8-bit or 16-bit external flash memory (BMODE = 0x1)--In this mode, the boot kernel loads the first block header from address 0x2000 0000 and--depending on instructions containing in the header--the boot kernel performs 8-bit or 16-bit boot or starts program execution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup).
The ARDY is not enabled by default, but it can be enabled by OTP programming. Similarly, all interface behavior and timings can be customized by OTP programming. This includes activation of burst-mode or page-mode operation. In this mode, all signals belonging to the asynchronous interface are enabled at the port muxing level.

� Boot from external SPI EEPROM or flash (BMODE = 0x3)--8-bit, 16-bit, 24-bit or 32-bit addressable devices are supported. The processor uses the PG15 GPIO signal (at SPI0SEL2) to select a single SPI EEPROM/flash device connected to the SPI0 interface; then submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SSEL and MISO signals. By default, a value of 0x85 is written to the SPI0_BAUD register.
� Boot from SPI0 host device (BMODE = 0x4)--The processor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. In the host, the HWAIT signal must be interrogated by the host before every transmitted byte. A pull-up resistor is required on the SPI0SS input. A pull-down on the serial clock may improve signal quality and booting robustness.
� Boot from OTP memory (BMODE = 0x5)--This provides a stand-alone booting method. The boot stream is loaded from on-chip OTP memory. By default the boot stream is expected to start from OTP page 0x40 on and can occupy all public OTP memory up to page 0xDF. This is 2560 bytes. Since the start page is programmable the maximum size of the boot stream can be extended to 3072 bytes.
� Boot from SDRAM (BMODE = 0x6)--This is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP settings.
� Boot from UART0 host (BMODE = 0x7)--Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities.
When performing the autobaud, the UART expects a "@" (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the RX0 signal to determine the bit rate. The UART then replies with an acknowledgment composed of 4 bytes (0xBF--the value of UART0_DLL and 0x00--the value of UART0_DLH). The host can then download the boot stream. To hold off the host the Blackfin processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor HWAIT before every transmitted byte.
For each of the boot modes, a 16-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP memory. Individual boot modes can be customized or even disabled based on OTP programming. External hardware, especially booting hosts may watch the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts

Rev. E | Page 14 of 63 | June 2020

the boot process. By programming OTP memory, the user can instruct the preboot routine to also customize the PLL, the SDRAM Controller, and the Asynchronous Interface.
The boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate event to speed up booting in the later case. Bits 6-4 in the system reset configuration (SYSCR) register can be used to bypass pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by "initialization code." This is a piece of code that is loaded and executed prior to the regular application boot. Typically, this is used to configure the SDRAM controller or to speed up booting by managing PLL, clock frequencies, wait states, or serial bit rates.
The boot ROM also features C-callable function entries that can be called by the user application at run time. This enables second-stage boot or boot management schemes to be implemented with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.
The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages:
� Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations.
� A multi-issue load/store modified-harvard architecture, which supports two 16-bit MACs or four 8-bit ALUs plus two load/store plus two pointer updates per cycle.
� All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model.
� Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers.
� Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.

ADSP-BF512/BF514/BF516/BF518
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore� Embedded Studio and/or VisualDSP++�), evaluation products, emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information, visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite� evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders�, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on "ezkit" or "ezextender".
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user's PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors.

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ADSP-BF512/BF514/BF516/BF518

Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages:
� www.analog.com/ucos3
� www.analog.com/ucfs
� www.analog.com/ucusbd
� www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on "Blackfin software modules" or "SHARC software modules".
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor's internal features via the processor's TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the JTAG port of the DSP to the emulator.

For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)--use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
The following publications that describe ADSP-BF512/ ADSP-BF514/ADSP-BF516/ADSP-BF518 processors (and related processors) can be accessed electronically on our website:
� Getting Started With Blackfin Processors
� ADSP-BF51x Blackfin Processor Hardware Reference
� Blackfin Processor Programming Reference
� ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena.
Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website.
The Application Signal Chains page in the Circuits from the LabTM site (www.analog.com/circuits) provides:
� Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
� Drill down links for components in each chain to selection guides and application information
� Reference designs applying best practice design techniques

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ADSP-BF512/BF514/BF516/BF518

SIGNAL DESCRIPTIONS

The processors' signal definitions are listed in Table 7. In order to maintain maximum function and reduce package size and signal count, some signals have dual, multiplexed functions. In cases where signal function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics.
All pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL output pin (CLKBUF). On the external memory interface, the control and address lines are driven high, with the exception of CLKOUT, which toggles at the system clock rate. During hibernate all outputs are three-stated unless otherwise noted in Table 7.
All I/O signals have their input buffers disabled with the exception of the signals noted in the data sheet that need pull-ups or pull downs if unused.

The SDA (serial data) and SCL (serial clock) pins/balls are open drain and therefore require a pullup resistor. Consult version 2.1 of the I2C specification for the proper resistor value.
It is strongly advised to use the available IBIS models to ensure that a given board design meets overshoot/undershoot and signal integrity requirements. If no IBIS simulation is performed, it is strongly recommended to add series resistor terminations for all Driver Types A, C and D. The termination resistors should be placed near the processor to reduce transients and improve signal integrity. The resistance value, typically 33  or 47 , should be chosen to match the average board trace impedance. Additionally, adding a parallel termination to CLKOUT may prove useful in further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware.

Table 7. Signal Descriptions

Signal Name EBIU ADDR19�1 DATA15�0 ABE1�0/SDQM1�0 AMS1�0 ARE AWE SRAS SCAS SWE SCKE
CLKOUT SA10 SMS Port F: GPIO and Multiplexed Peripherals PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6
PF1/ERxD2/PPI D1/PWM AH/TACLK7 PF2/ETxD3/PPI D2/PWM AL PF3/ERxD3/PPI D3/PWM BH/TACLK0
PF4/ERxCLK/PPI D4/PWM BL/TACLK1 PF5/ERxDV/PPI D5/PWM CH/TACI0
PF6/COL/PPI D6/PWM CL/TACI1 PF7/SPI0SEL1/PPI D7/PWMSYNC

Type Function

Driver Type1

O Address Bus

A

I/O Data Bus

A

O Byte Enable or Data Mask

A

O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used) A

O Asynchronous Memory Read Enable

A

O Asynchronous Memory Write Enable

A

O SDRAM Row Address Strobe

A

O SDRAM Column Address Strobe

A

O SDRAM Write Enable

A

O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-refresh A is used)

O SDRAM Clock Output

B

O SDRAM A10 Signal

A

O SDRAM Bank Select

A

I/O GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate C Clock

I/O GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C

I/O GPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output

C

I/O GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate C Clock

I/O GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLK C

I/O GPIO/Ethernet MII Receive Data Valid/PPI Data 5/PWM CH Out

C

/Timer0 Alternate Capture Input

I/O GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C

I/O GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync

C

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ADSP-BF512/BF514/BF516/BF518

Table 7. Signal Descriptions (Continued)

Signal Name

Type Function

Driver Type1

PF8/MDC/PPI D8/SPI1SEL4

I/O GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4

C

PF9/MDIO/PPI D9/TMR2

I/O GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2

C

PF10/ETxD0/PPI D10/TMR3

I/O GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3

C

PF11/ERxD0/PPI D11/PWM AH/TACI3

I/O GPIO/Ethernet MII Receive D0/PPI Data 11/PWM AH output

C

/Timer3 Alternate Capture Input

PF12/ETxD1/PPI D12/PWM AL

I/O GPIO/Ethernet MII Transmit D1/PPI Data 12/PWM AL Output

C

PF13/ERxD1/PPI D13/PWM BH

I/O GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM BH Output

C

PF14/ETxEN/PPI D14/PWM BL

I/O GPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM BL Out

C

PF152/RMII PHYINT/PPI D15/PWM_SYNCA I/O GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync

C

Port G: GPIO and Multiplexed Peripherals PG0/MIICRS/RMIICRS/HWAIT 3/SPI1SEL3

I/O GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C

PG1/ERxER/DMAR1/PWM CH

I/O GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out

C

PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O GPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out

C

PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3 I/O GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C

PG4/RSCLK0/RSI_DATA1/TMR5/TACI5

I/O GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input

D

PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK

I/O GPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer Reference

C

PG6/TFS0/RSI_DATA3/TMR0/PPIFS1

I/O GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1

C

PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2

I/O GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2

C

PG8/TSCLK0/RSI_CLK/TMR6/TACI6

I/O GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture Input

D

PG9/DT0SEC/UART0TX/TMR4

I/O GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4

C

PG10/DR0SEC/UART0RX/TACI4

I/O GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input C

PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2

I/O GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave C Select 5/Timer2 Alternate CLK

PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS I/O GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out D

PG13/SPI0MISO4/TMR0/PPIFS1/ PTP_CLKOUT

I/O GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock Out

C

PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP /PTP_AUXIN

I/O GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary C Snapshot Trigger Input

PG15/SPI0SEL2/PPIFS3/AMS3

I/O GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3 C

Port H: GPIO and Multiplexed Peripherals

PH0/DR1PRI/SPI1SS/RSI_DATA4

I/O GPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4

C

PH1/RFS1/SPI1MISO/RSI_DATA5

I/O GPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5

C

PH2/RSCLK1/SPI1SCK/RSI DATA6

I/O GPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6

D

PH3/DT1PRI/SPI1MOSI/RSI DATA7

I/O GPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7

C

PH4/TFS1/AOE/SPI0SEL3/CUD

I/O GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave C Select 3/Counter Up Direction

PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG I/O GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/

D

External Clock for PTP TSYNC/Counter Down Gate

PH6/DT1SEC/UART1TX/SPI1SEL1/CZM

I/O GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1

C

/Counter Zero Marker

PH7/DR1SEC/UART1RX/TMR7/TACI2

I/O GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock C Input

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ADSP-BF512/BF514/BF516/BF518

Table 7. Signal Descriptions (Continued)

Signal Name

Type Function

Driver Type1

Port J

PJ0:SCL

I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up E resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)

PJ1:SDA

I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up E resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)

Real Time Clock

RTXI

I

RTC Crystal Input (This ball should be pulled low when not used.)

RTXO

O RTC Crystal Output (Does not three-state during hibernate)

JTAG Port

TCK

I

JTAG Clock

TDO

O JTAG Serial Data Out

C

TDI

I

JTAG Serial Data In

TMS

I

JTAG Mode Select

TRST

I JTAG Reset (This signal should be pulled low if the JTAG port is not used.)

EMU

O Emulation Output

C

Clock

CLKIN

I

Clock/Crystal Input

XTAL

O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)

CLKBUF

O Buffered XTAL Output (If enabled, does not three-state during hibernate)

C

Mode Controls

RESET

I

Reset

NMI

I

Non-maskable Interrupt (This signal should be pulled high when not used.)

BMODE2-0

I

Boot Mode Strap 2-0

Voltage Regulation Interface

PG

I

Power Good (This signal should be pulled low when not used.)

EXT_WAKE

O Wake up Indication (Does not three-state during hibernate)

C

Power Supplies

ALL SUPPLIES MUST BE POWERED See Operating Conditions.

VDDEXT VDDINT VDDRTC VDDMEM VPPOTP VDDOTP GND

P I/O Power Supply P Internal Power Supply P Real Time Clock Power Supply P MEM Power Supply P OTP Programming Voltage P OTP Power Supply G Ground for All Supplies

1 See Output Drive Currents for more information about each driver type. 2 When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball
is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor. 3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity. 4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).

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ADSP-BF512/BF514/BF516/BF518

SPECIFICATIONS
Note that component specifications are subject to change without notice.
OPERATING CONDITIONS

Parameter

Conditions

Min

Nominal

Max

Unit

VDDINT Internal Supply Voltage Internal Supply Voltage

Industrial Models Commercial Models

1.14

1.47

V

1.10

1.47

V

Internal Supply Voltage

Automotive Models

1.33

1.47

V

VDDEXT1, 2 External Supply Voltage External Supply Voltage

1.8 V I/O, Nonautomotive Models 2.5 V I/O, Nonautomotive Models

1.7

1.8

2.25

2.5

1.9

V

2.75

V

External Supply Voltage

3.3 V I/O, All Models

3.0

3.3

3.6

V

VDDMEM3 MEM Supply Voltage MEM Supply Voltage

1.8 V I/O, Nonautomotive Models 2.5 V I/O, Nonautomotive Models

1.7

1.8

2.25

2.5

1.9

V

2.75

V

MEM Supply Voltage

3.3 V I/O, All Models

3.0

3.3

3.6

V

VDDRTC4 VDDOTP1 VPPOTP

RTC Power Supply Voltage OTP Supply Voltage OTP Programming Voltage For Reads1

2.25

2.25

2.5

2.25

2.5

3.6

V

2.75

V

2.75

V

For Writes5

6.9

7.0

7.1

V

VIH
VIHTWI VIL
VILTWI

High Level Input Voltage6, 7 High Level Input Voltage6, 8 High Level Input Voltage6, 8 High Level Input Voltage Low Level Input Voltage6, 7 Low Level Input Voltage6, 8 Low Level Input Voltage6, 8 Low Level Input Voltage Junction Temperature

VDDEXT/VDDMEM = 1.90 V VDDEXT/VDDMEM = 2.75 V VDDEXT/VDDMEM = 3.6 V VDDEXT = 1.90 V/2.75 V/3.6 V VDDEXT/VDDMEM = 1.7 V VDDEXT/VDDMEM = 2.25 V VDDEXT/VDDMEM = 3.0 V VDDEXT = Minimum 168-Ball CSP_BGA @ TAMBIENT = 0�C to +70�C

1.2 1.7 2 0.7 � VBUSTWI
0

V

V

V

VBUSTWI9

V

0.6

V

0.7

V

0.8

V

0.3 � VBUSTWI10 V

+95

�C

Junction Temperature Junction Temperature Junction Temperature

168-Ball CSP_BGA @ TAMBIENT = �40�C to +85�C �40 176-Lead LQFP_EP @ TAMBIENT = 0�C to +70�C 0 176-Lead LQFP_EP @ TAMBIENT = �40�C to +85�C �40

+105

�C

+95

�C

+105

�C

1 Must remain powered (even if the associated function is not used).
2 VDDEXT is the supply to the GPIO. 3 Pins/balls that use VDDMEM are DATA15�0, ADDR19�1, ABE1�0, ARE, AWE, AMS1�0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant
to voltages higher than VDDMEM. When using any of the asynchronous memory signals AMS3�2, ARDY, or AOE VDDMEM and VDDEXT must be shorted externally. 4 If not used, power with VDDEXT. 5 The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent
on voltage and junction temperature) over the lifetime of the part.
6 Parameter value applies to all input and bidirectional pins/balls except SDA and SCL.
7 Bidirectional balls (PF15�0, PG15�0, PH15�0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3�0) of the ADSP-BF51x processors are
2.5 V tolerant (always accept up to 2.7 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 8 Bidirectional pins/balls (PF15�0, PG15�0, PH7�0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2�0) of the ADSP-BF51x are
3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 9 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 8. 10SDA and SCL are pulled up to VBUSTWI. See Table 8.

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ADSP-BF512/BF514/BF516/BF518

Table 8 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port.
Table 8. TWI_DT Field Selections and VDDEXT/VBUSTWI

TWI_DT 000 (default) 001 010 011 100 101 110 111 (reserved)

VDDEXT Nominal 3.3 1.8 2.5 1.8 3.3 1.8 2.5 --

VBUSTWI Minimum 2.97 1.7 2.97 2.97 4.5 2.25 2.25 --

VBUSTWI Nominal 3.3 1.8 3.3 3.3 5 2.5 2.5 --

VBUSTWI Maximum 3.63 1.98 3.63 3.63 5.5 2.75 2.75 --

Unit V V V V V V V --

Clock Related Operating Conditions
Table 9 describes the timing requirements for the processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. Table 10 describes phase-locked loop operating conditions.

Table 9. Core Clock (CCLK) Requirements

Parameter fCCLK

Nominal Voltage Setting

Core Clock Frequency (VDDINT =1.33 V Minimum, All Models) Core Clock Frequency (VDDINT =1.23 V Minimum, Industrial/Commercial Models) Core Clock Frequency (VDDINT = 1.14 V Minimum, Industrial Models Only) Core Clock Frequency (VDDINT = 1.10 V Minimum, Commercial Models Only)

1.400 V 1.300 V 1.200 V 1.150 V

Maximum Unit

400

MHz

300

MHz

200

MHz

200

MHz

Table 10. Phase-Locked Loop Operating Conditions

Parameter

fVCO

Voltage Controlled Oscillator (VCO) Frequency

(Commercial/Industrial Models)

Voltage Controlled Oscillator (VCO) Frequency (Automotive Models)

1 For more information, see Ordering Guide.

Min 72
84

Max

Unit

Instruction Rate1 MHz

Instruction Rate1 MHz

Table 11. SCLK Conditions

V /V DDEXT DDMEM 1.8 V Nominal

V /V DDEXT DDMEM 2.5 V or 3.3 V Nominal

Parameter1

Max

Max

fSCLK

CLKOUT/SCLK Frequency (VDDINT  1.230 V

80

100

Minimum)

fSCLK

CLKOUT/SCLK Frequency (VDDINT < 1.230 V)

80

80

1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 24.

Unit MHz
MHz

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ADSP-BF512/BF514/BF516/BF518

ELECTRICAL CHARACTERISTICS

Parameter VOH
VOL IIH1 IIL1 IIHP2 IOZH3 IOZHTWI4 IOZL3 CIN5, 6 CINTWI4, 6 IDDDEEPSLEEP7
IDDSLEEP IDD-IDLE
IDD-TYP
IDD-TYP
IDDHIBERNATE8
IDDRTC IDDSLEEP8, 9

Conditions

Min

High Level Output Voltage

VDDEXT /VDDMEM = 1.7 V,

1.35

IOH = �0.5 mA

High Level Output Voltage

VDDEXT /VDDMEM = 2.25 V,

2

IOH = �0.5 mA

High Level Output Voltage

VDDEXT /VDDMEM = 3.0 V,

2.4

IOH = �0.5 mA

Low Level Output Voltage

VDDEXT /VDDMEM = 1.7/2.25/3.0 V, IOL = 2.0 mA

High Level Input Current

VDDEXT /VDDMEM = 3.6 V, VIN = 3.6 V

Low Level Input Current

VDDEXT /VDDMEM = 3.6 V, VIN = 0 V

High Level Input Current JTAG VDDEXT = 3.6 V, VIN = 3.6 V

Three-State Leakage Current VDDEXT/VDDMEM= 3.6 V, VIN = 3.6 V

Three-State Leakage Current VDDEXT = 3.0 V, VIN = 5.5 V

Three-State Leakage Current VDDEXT/VDDMEM= 3.6 V, VIN = 0 V

Input Capacitance

fIN = 1 MHz, TAMBIENT = 25�C, VIN = 2.5 V

Input Capacitance

fIN = 1 MHz, TAMBIENT = 25�C, VIN = 2.5 V

VDDINT Current in Deep Sleep Mode

VDDINT = 1.3 V, fCCLK = 0 MHz, fSCLK = 0 MHz, TJ = 25�C, ASF = 0.00

VDDINT Current in Sleep Mode VDDINT Current in Idle

VDDINT = 1.3 V, fSCLK = 25 MHz, TJ = 25�C
VDDINT = 1.3 V, fCCLK = 50 MHz, fSCLK = 25 MHz, TJ = 25�C, ASF = 0.41

VDDINT Current

VDDINT = 1.3 V, fCCLK = 300 MHz, fSCLK = 25 MHz, TJ = 25�C, ASF = 1.00

VDDINT Current

VDDINT = 1.4 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25�C, ASF = 1.00

Hibernate State Current

VDDEXT = VDDMEM =VDDRTC = 3.3 V VDDOTP = VPPOTP = 2.5 V, TJ = 25�C, CLKIN = 0 MHz

VDDRTC Current VDDINT Current in Sleep Mode

VDDRTC = 3.3 V, TJ = 25�C fCCLK = 0 MHz, fSCLK > 0 MHz

IDDDEEPSLEEP8, 10 VDDINT Current in Deep Sleep Mode

IDDINT10, 11

VDDINT Current

fCCLK = 0 MHz, fSCLK = 0 MHz fCCLK > 0 MHz, fSCLK  0 MHz

Rev. E | Page 22 of 63 | June 2020

Typical Max

Unit

V

V

V

0.4

V

10

A

10

A

75

A

10

A

10

A

10

A

5

8

pF

15

pF

2.1

mA

5.5

mA

12

mA

77

mA

108

mA

40

A

20

A

Table 13 +

mA10

(0.20 � VDDINT � fSCLK)

Table 13

mA

Table 13 +

mA

(Table 14 � ASF) +

(0.20 � VDDINT � fSCLK)

ADSP-BF512/BF514/BF516/BF518

Parameter

Conditions

Min

Typical Max

IDDOTP

VDDOTP Current

VDDOTP = 2.5 V, TJ = 25�C,

2

OTP Memory Read

IDDOTP

VDDOTP Current

VDDOTP = 2.5 V, TJ = 25�C,

2

OTP Memory Write

IPPOTP

VPPOTP Current

VPPOTP = 2.5 V, TJ = 25�C,

100

OTP Memory Read

IPPOTP

VPPOTP Current

VPPOTP = Table 17 V, TJ = 25�C,

3

OTP Memory Write

1 Applies to input balls. 2 Applies to JTAG input balls (TCK, TDI, TMS, TRST). 3 Applies to three-statable balls. 4 Applies to bidirectional balls SCL and SDA. 5 Applies to all signal balls, except SCL and SDA. 6 Guaranteed, but not tested. 7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 8 Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 9 Guaranteed maximum specifications. 10Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. 11See Table 12 for the list of IDDINT power vectors covered.

Unit mA mA A mA

Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics shows the current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and temperature (see Table 13), and IDDINT specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (VDDINT) and frequency (Table 14).
There are two parts to the dynamic component. The first part is due to transistor switching in the core clock (CCLK) domain. This part is subject to an Activity Scaling Factor (ASF) which represents application code running on the processor core and L1 memories (Table 12).

The ASF is combined with the CCLK Frequency and VDDINT dependent data in Table 14 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation.
Table 12. Activity Scaling Factors (ASF)1

IDDINT Power Vector

Activity Scaling Factor (ASF)

IDD-PEAK

1.29

IDD-HIGH

1.25

IDD-TYP

1.00

IDD-APP

0.85

IDD-NOP

0.70

IDD-IDLE

0.41

1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSP-BF51x processors.

Table 13. Static Current--IDD-DEEPSLEEP (mA)

TJ (�C)1 �40 �20 0 25 40 55 70

1.10 V 0.9 1.0 1.2 1.8 2.4 3.3 4.6

1.15 V 1.0 1.1 1.3 1.9 2.6 3.5 5.0

1.20 V 1.0 1.2 1.4 2.1 2.8 3.8 5.4

1.25 V 1.1 1.3 1.6 2.3 3.0 4.3 6.0

Voltage (VDDINT)1

1.30 V

1.35 V

1.1

1.2

1.4

1.6

1.8

2.0

2.5

2.8

3.3

3.7

4.6

5.0

6.4

7.0

1.40 V 1.3 1.7 2.2 3.1 4.0 5.5 7.7

1.45 V 1.7 1.9 2.3 3.3 4.4 6.1 8.4

1.50 V 1.9 2.0 2.5 3.7 4.9 6.7 9.2

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ADSP-BF512/BF514/BF516/BF518

Table 13. Static Current--IDD-DEEPSLEEP (mA) (Continued)

TJ (�C)1

1.10 V

1.15 V

1.20 V

1.25 V

85

6.5

7.1

7.7

8.3

100

9.2

10.0

10.8

11.7

105

10.3

11.1

12.1

13.1

1 Valid frequency and voltage ranges are model-specific. See Operating Conditions.

Voltage (VDDINT)1

1.30 V

1.35 V

9.1

9.9

12.7

13.7

14.2

15.3

1.40 V 10.8 15.0 16.6

1.45 V 11.8 16.1 18.0

1.50 V 12.8 17.5 19.4

Table 14. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1

fCCLK (MHz)2

1.10 V

1.15 V

1.20 V

1.25 V

Voltage (VDDINT)2

1.30 V

1.35 V

1.40 V

1.45 V

1.50 V

400

N/A

N/A

N/A

N/A

N/A

N/A

102.1

106.5

111.0

350

N/A

N/A

N/A

N/A

N/A

86.2

90.1

94.0

98.0

300

N/A

N/A

N/A

N/A

71.4

74.7

78.1

81.5

85.0

250

N/A

N/A

N/A

57.5

60.4

63.2

66.1

69.0

71.9

200

N/A

42.5

44.7

47.0

49.4

51.7

54.1

56.5

58.9

150

31.1

32.9

34.7

36.5

38.4

40.2

42.1

44.0

45.9

100

22.0

23.4

24.7

26.0

27.4

28.7

30.1

31.5

33.0

1 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics. 2 Valid frequency and voltage ranges are model-specific. See Operating Conditions.

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ADSP-BF512/BF514/BF516/BF518

ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 15 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 15. Absolute Maximum Ratings

Parameter

Rating

Internal Supply Voltage (VDDINT)
External (I/O) Supply Voltage ( VDDEXT/VDDMEM) Input Voltage1, 2 Input Voltage1, 3

�0.3 V to +1.50 V �0.3 V to +3.8 V
�0.5 V to +3.6 V �0.5 V to +5.5 V

Output Voltage Swing
IOH/IOL Current per Pin Group4 Storage Temperature Range

�0.5 V to VDDEXT/VDDMEM + 0.5 V 80 mA (max)
�65�C to +150�C

Junction Temperature While biased +110�C

1 Applies to 100% transient duty cycle. For other duty cycles see Table 16.
2 Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT � 0.2.
3 Applies to signals SCL, SDA. 4 For more information, see the information preceding Table 18 and Table 19.

Table 16. Maximum Duty Cycle for Input Transient Voltage1

VIN Min (V)2 �0.50

VIN Max (V)2 +3.80

Maximum Duty Cycle3 100%

�0.70

+4.00

40%

�0.80

+4.10

25%

�0.90

+4.20

15%

�1.00

+4.30

10%

1 Applies to all signal pins/balls with the exception of CLKIN, XTAL. 2 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. 3 Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. It is equivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence.

When programming OTP memory on the ADSP-BF51x processor, the VPPOTP pin/ball must be set to the write value specified in the Operating Conditions. There is a finite amount of cumulative time that the write voltage may be applied (dependent on voltage and junction temperature) to VPPOTP over the lifetime of the part. Therefore, maximum OTP memory programming time for the processor is shown in Table 17.

Table 17. Maximum OTP Memory Programming Time

VPPOTP Voltage (V) 6.9 7.0 7.1

25�C 6000 sec 2400 sec 1000 sec

Temperature

85�C 100 sec 44 sec 18 sec

110�C 25 sec 12 sec 4.5 sec

Table 18 and Table 19 specify the maximum total source/sink (IOH/IOL) current for a group of pins. Permanent damage can occur if this value is exceeded. To understand this specification, if pins PF9, PF8, PF7, PF6, and PF5 from Group 1 in Table 19 table were sourcing or sinking 2 mA each, the total current for those pins would be 10 mA. This would allow up to 70 mA total that could be sourced or sunk by the remaining pins in the group without damaging the device. Note that the VOH and VOL specifications have separate per-pin maximum current requirements as shown in the Electrical Characteristics table.

Table 18. Total Current Pin Groups�VDDMEM Groups

Group 1 2 3 4 5 6 7 8

Pins in Group DATA15, DATA14, DATA13, DATA12, DATA11, DATA10 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4 DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1 ABE1, ABE0, SA10, SWE, SCAS, SRAS SMS, SCKE, AMS1, ARE, AWE, AMS0, CLKOUT

Table 19. Total Current Pin Groups�VDDEXT Groups

Group 1 2 3
4 5 6 7

Pins in Group PF9, PF8, PF7, PF6, PF5, PF4, PF3, PF2 PF1, PF0, PG15, PG14, PG13, PG12, PG11, PG10 PG9, PG8, PG7, PG6, PG5, PG4, PG3, PG2, BMODE0, BMODE1, BMODE2 PG1, PG0, TDO, EMU, TDI, TCK, TRST, TMS RESET, NMI, CLKBUF PH7, PH6, PH5, PH4, PH3, PH2, PH1, PH0 PF15, PF14, PF13, PF12, PF11, SDA, SCL, PF10

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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ADSP-BF512/BF514/BF516/BF518

TIMING SPECIFICATIONS
Clock and Reset Timing
Table 20 and Figure 7 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 9, Table 10, and Table 11, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor's speed grade.

Table 20. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

CLKIN Frequency (Commercial/Industrial Models1, 2, 3, 4 12

50

fCKIN

CLKIN Frequency (Automotive Models)1, 2, 3, 4

14

50

tCKINL

CLKIN Low Pulse1

10

tCKINH

CLKIN High Pulse1

10

tWRST

RESET Asserted Pulse Width Low5

11 � tCKIN

Switching Characteristic

MHz MHz ns ns ns

tBUFDLAY

CLKIN to CLKBUF Delay

11

ns

1 Applies to PLL bypass mode and PLL nonbypass mode.
2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 through Table 11. 3 The tCKIN period (see Figure 7) equals 1/fCKIN. 4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models. 5 Applies after power-up sequence is complete. See Table 21 and Figure 8 for power-up reset timing.

CLKIN CLKBUF

tCKIN

tCKINL

tCKINH

RESET

tWRST

tBUFDLAY

tBUFDLAY

Figure 7. Clock and Reset Timing

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ADSP-BF512/BF514/BF516/BF518

Table 21. Power-Up Reset Timing
Parameter Timing Requirements tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, and CLKIN Pins are
Stable and Within Specification

Min 3500 � tCKIN

Max

Unit ns

RESET

tRST_IN_PWR

CLKIN VDD_SUPPLIES

Figure 8. Power-Up Reset Timing

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ADSP-BF512/BF514/BF516/BF518

Asynchronous Memory Read Cycle Timing Table 22. Asynchronous Memory Read Cycle Timing

Parameter

Timing Requirements

tSDAT

DATA15�0 Setup Before CLKOUT

tHDAT

DATA15�0 Hold After CLKOUT

tSARDY

ARDY Setup Before CLKOUT

tHARDY

ARDY Hold After CLKOUT

Switching Characteristics

tDO

Output Delay After CLKOUT1

tHO

Output Hold After CLKOUT 1

1 Output pins/balls include AMS3�0, ABE1�0, ADDR19�1, AOE, ARE.

VDDMEM 1.8V Nominal

Min

Max

2.1 1.2 4 0.2

6 0.8

VDDMEM 2.5 V/3.3V Nominal

Min

Max

Unit

2.1

ns

0.8

ns

4

ns

0.2

ns

6

ns

0.8

ns

CLKOUT AMSx
ABE1�0 ADDR19�1
AOE ARE ARDY
DATA 15�0

SETUP 2 CYCLES
tDO

PROGRAMMED READ ACCESS 4 CYCLES

ACCESS EXTENDED

HOLD

3 CYCLES

1 CYCLE

tHO

tDO tSARDY

tHO

tHARDY

tSARDY tHARDY

tSDAT tHDAT

Figure 9. Asynchronous Memory Read Cycle Timing

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ADSP-BF512/BF514/BF516/BF518

Asynchronous Memory Write Cycle Timing

Table 23. Asynchronous Memory Write Cycle Timing

Parameter

Timing Requirements

tSARDY

ARDY Setup Before CLKOUT

tHARDY

ARDY Hold After CLKOUT

Switching Characteristics

tDDAT tENDAT tDO tHO

DATA15�0 Disable After CLKOUT DATA15�0 Enable After CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT 1

1 Output pins/balls include AMS3�0, ABE1�0, ADDR19�1, DATA15�0, AOE, AWE.

Min

Max

Unit

4

ns

0.2

ns

6

ns

0

ns

6

ns

0.8

ns

CLKOUT AMSx

SETUP 2 CYCLES

PROGRAMMED WRITE ACCESS
2 CYCLES

ACCESS EXTEND HOLD 1 CYCLE 1 CYCLE

tDO

tHO

ABE1�0 ADDR19�1
AWE
ARDY
DATA 15�0

tDO

tSARDY

tHARDY

tENDAT

tSARDY

tHO tHARDY

tDDAT

Figure 10. Asynchronous Memory Write Cycle Timing

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ADSP-BF512/BF514/BF516/BF518

SDRAM Interface Timing

Table 24. SDRAM Interface Timing

VDDMEM 1.8V Nominal

VDDMEM 2.5 V/3.3V Nominal

Parameter

Min

Max

Min

Max

Timing Requirements

tSSDAT

Data Setup Before CLKOUT

tHSDAT

Data Hold After CLKOUT

Switching Characteristics

1.5

1.5

1.3

0.8

tSCLK tSCLKH tSCLKL tDCAD tHCAD tDSDAT tENSDAT

CLKOUT Period1 CLKOUT Width High CLKOUT Width Low Command, Address, Data Delay After CLKOUT2 Command, Address, Data Hold After CLKOUT2 Data Disable After CLKOUT Data Enable After CLKOUT

12.5

10

5

4

5

4

5

4

1

1

5.5

5

0

0

1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 11. Package type and reduced supply voltages affect the best-case value listed here. 2 Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Unit
ns ns
ns ns ns ns ns ns ns

CLKOUT
DATA (IN)
DATA (OUT)
COMMAND, ADDRESS
(OUT)

tSSDAT

tSCLK

tHSDAT tENSDAT

tSCLKL

tSCLKH

tDCAD

tHCAD

tDSDAT

tDCAD

tHCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 11. SDRAM Interface Timing

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ADSP-BF512/BF514/BF516/BF518

External DMA Request Timing
Table 25 and Figure 12 describe the External DMA Request operations.

Table 25. External DMA Request Timing1

VDDMEM/VDDEXT 1.8 V Nominal

VDDMEM/VDDEXT 2.5 V/3.3 V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tDS

DMARx Asserted to CLKOUT High Setup

9

7.2

ns

tDH

CLKOUT High to DMARx Deasserted Hold Time

0

0

ns

tDMARACT

DMARx Active Pulse Width

tSCLK + 1

tSCLK + 1

ns

tDMARINACT DMARx Inactive Pulse Width

1.75 � tSCLK

1.75 � tSCLK

ns

1 Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and VDDMEM are NOT equal may require level shifting logic for correct operation.

CLKOUT
DMAR0/1 (ACTIVE LOW)
DMAR0/1 (ACTIVE HIGH)

tDS

tDH

tDMARACT

tDMARINACT

Figure 12. External DMA Request Timing

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ADSP-BF512/BF514/BF516/BF518

Parallel Peripheral Interface Timing
Table 26 and Figure 13 through Figure 17 and describe parallel peripheral interface operations.

Table 26. Parallel Peripheral Interface Timing

VDDEXT 1.8 V Nominal

VDDEXT 2.5 V/3.3 V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tPCLKW

PPI_CLK Width

tSCLK � 1.5

tSCLK � 1.5

ns

tPCLK

PPI_CLK Period

2 � tSCLK � 1.5

2 � tSCLK � 1.5

ns

Timing Requirements - GP Input and Frame Capture Modes

tPSUD

External Frame Sync Startup Delay1

4 � tPCLK

4 � tPCLK

ns

tSFSPE

External Frame Sync Setup Before PPI_CLK

6.7

6.7

ns

(Nonsampling Edge for Rx, Sampling Edge for Tx)

tHFSPE

External Frame Sync Hold After PPI_CLK

1.75

1.75

ns

tSDRPE

Receive Data Setup Before PPI_CLK

4.1

3.5

ns

tHDRPE

Receive Data Hold After PPI_CLK

2

1.6

ns

Switching Characteristics - GP Output and Frame Capture Modes

tDFSPE tHOFSPE tDDTPE tHDTPE

Internal Frame Sync Delay After PPI_CLK Internal Frame Sync Hold After PPI_CLK Transmit Data Delay After PPI_CLK Transmit Data Hold After PPI_CLK

8

8

ns

1.7

1.7

ns

8.2

8

ns

2.3

1.9

ns

1 The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words guaranteed to be received correctly by the PPI peripheral.

PPI_CLK PPI_FS1/2

tPSUD

Figure 13. PPI with External Frame Sync Timing

PPI_CLK PPI_FS1/2 PPI_DATA

DATA SAMPLED / FRAME SYNC SAMPLED

DATA SAMPLED / FRAME SYNC SAMPLED

tSFSPE

tHFSPE

tPCLKW

tPCLK

tSDRPE

tHDRPE

Figure 14. PPI GP Rx Mode with External Frame Sync Timing

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ADSP-BF512/BF514/BF516/BF518

PPI_CLK PPI_FS1/2 PPI_DATA

DATA DRIVEN / FRAME SYNC SAMPLED
tSFSPE tHFSPE
tDDTPE tHDTPE

tPCLKW

tPCLK

Figure 15. PPI GP Tx Mode with External Frame Sync Timing

FRAME SYNC DRIVEN

DATA SAMPLED

PPI_CLK

tHOFSPE

tDFSPE

tPCLKW

PPI_FS1/2

tPCLK

tSDRPE

tHDRPE

PPI_DATA

Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing

FRAME SYNC DRIVEN

PPI_CLK tHOFSPE
PPI_FS1/2

tDFSPE

PPI_DATA

DATA DRIVEN
tPCLK
tPCLKW

DATA DRIVEN

tDDTPE

tHDTPE

Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing

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ADSP-BF512/BF514/BF516/BF518

RSI Controller Timing
Table 27 and Figure 18 describe RSI controller timing. Table 28 and Figure 19 describe RSI controller (high speed) timing.

Table 27. RSI Controller Timing

Parameter

Min

Max

Timing Requirements

tISU Input Setup Time

5.6

tIH

Input Hold Time

2

Switching Characteristics

fPP1 Clock Frequency Data Transfer Mode fOD Clock Frequency Identification Mode tWL Clock Low Time tWH Clock High Time tTLH Clock Rise Time tTHL Clock Fall Time tODLY Output Delay Time During Data Transfer Mode tODLY Output Delay Time During Identification Mode

0

25

1002

400

10

10

10

10

14

50

1 tPP = 1/fPP 2 Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

SD_CLK INPUT

tPP

tTHL tWL

tTLH tWH

tISU

tIH

tODLY

OUTPUT
NOTES: 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 18. RSI Controller Timing

Unit
ns ns
MHz kHz ns ns ns ns ns ns
VOH (MIN)
VOL (MAX)

Rev. E | Page 34 of 63 | June 2020

Table 28. RSI Controller Timing (High Speed Mode)

Parameter

Timing Requirements

tISU Input Setup Time

tIH

Input Hold Time

Switching Characteristics

fPP1 Clock Frequency Data Transfer Mode tWL Clock Low Time tWH Clock High Time

tTLH Clock Rise Time tTHL Clock Fall Time tODLY Output Delay Time During Data Transfer Mode tOH Output Hold Time

1 tPP = 1/fPP

ADSP-BF512/BF514/BF516/BF518

Min

Max

Unit

5.6

ns

2

ns

0

50

MHz

7

ns

7

ns

3

ns

3

ns

4

ns

2.75

ns

SD_CLK INPUT

tPP

tTHL tWL

tTLH tWH

tISU

tIH

tODLY

tOH

OUTPUT
NOTES: 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 19. RSI Controller Timing (High Speed Mode)

VOH (MIN) VOL (MAX)

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ADSP-BF512/BF514/BF516/BF518

Serial Ports
Table 29 through Table 32 and Figure 20 through Figure 23 describe serial port operations.

Table 29. Serial Ports--External Clock

VDDEXT 1.8V Nominal

Parameter

Min

Max

Timing Requirements

tSFSE1

TFSx/RFSx Setup Before TSCLKx/RSCLKx

3

tHFSE1

TFSx/RFSx Hold After TSCLKx/RSCLKx

3

tSDRE1

Receive Data Setup Before RSCLKx

3

tHDRE1

Receive Data Hold After RSCLKx

3.5

tSCLKEW

TSCLKx/RSCLKx Width

7

tSCLKE tSUDTE2 tSUDRE2

TSCLKx/RSCLKx Period Start-Up Delay From SPORT Enable To First External TFSx Start-Up Delay From SPORT Enable To First External RFSx

2 � tSCLK 4 � tSCLKE 4 � tSCLKE

Switching Characteristics

tDFSE3

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated

10

TFSx/RFSx)

tHOFSE3

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated 0 TFSx/RFSx)

tDDTE3 tHDTE3

Transmit Data Delay After TSCLKx Transmit Data Hold After TSCLKx

10 0

1 Referenced to sample edge. 2 Verified in design but untested. 3 Referenced to drive edge.

Table 30. Serial Ports--Internal Clock

Parameter

Min

Timing Requirements

tSFSI1

TFSx/RFSx Setup Before TSCLKx/RSCLKx

11

tHFSI1

TFSx/RFSx Hold After TSCLKx/RSCLKx

�1.5

tSDRI1

Receive Data Setup Before RSCLKx

11

tHDRI1

Receive Data Hold After RSCLKx

�1.5

Switching Characteristics

tDFSI2

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated

TFSx/RFSx)

tHOFSI2

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated 2 TFSx/RFSx)

tDDTI2

Transmit Data Delay After TSCLKx

tHDTI2

Transmit Data Hold After TSCLKx

1.8

tSCLKIW

TSCLKx/RSCLKx Width

10

1 Referenced to sample edge. 2 Referenced to drive edge.

VDDEXT 1.8V Nominal
Max
3 3

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

3

ns

3

ns

3

ns

3

ns

4.5

ns

2 � tSCLK

ns

4 � tSCLKE

ns

4 � tSCLKE

ns

10

ns

0

ns

10

ns

0

ns

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

9.6

ns

�1.5

ns

9.6

ns

�1.5

ns

3

ns

1

ns

3

ns

1.5

ns

8

ns

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ADSP-BF512/BF514/BF516/BF518

DATA RECEIVE--INTERNAL CLOCK

DRIVE EDGE

tSCLKIW

RSCLKx

SAMPLE EDGE

tHOFSI
RFSx (OUTPUT)

tDFSI

RFSx (INPUT)

tSFSI

tHFSI

DRx

tSDRI

tHDRI

DATA TRANSMIT--INTERNAL CLOCK DRIVE EDGE tSCLKIW
TSCLKx

SAMPLE EDGE

tHOFSI
TFSx (OUTPUT)

tD FSI

TFSx (INPUT)

DTx

tHDTI

tDDTI

tSFSI

tHFSI

DATA RECEIVE--EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

tSCLKEW

tSCLKE

RSCLKx

tHOFSE
RFSx (OUTPUT)

tDFSE

RFSx (INPUT)

tSFSE

tHFSE

DRx

tSDRE

tHDRE

DATA TRANSMIT--EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

tSCLKE

t SCLKEW

TSCLKx

tHOFSE
TFSx (OUTPUT)

tDFSE

TFSx (INPUT)
tHDTE DTx

tDDTE

tSFSE

tHFSE

Figure 20. Serial Ports

TSCLKx (INPUT)
TFSx (INPUT)

tSUDTE

RSCLKx (INPUT)
RFSx (INPUT)

tSUDRE
FIRST
Figure 21. Serial Port Start Up with External Clock and Frame Sync

Rev. E | Page 37 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Table 31. Serial Ports--Enable and Three-State1

Parameter

Min

Switching Characteristics

tDTENE

Data Enable Delay from External TSCLKx

0

tDDTTE

Data Disable Delay from External TSCLKx

tDTENI

Data Enable Delay from Internal TSCLKx

�2.0

tDDTTI

Data Disable Delay from Internal TSCLKx

1 Referenced to drive edge.

DRIVE EDGE TSCLKx
tDTENE/I DTx

DRIVE EDGE tDDTTE/I

Figure 22. Enable and Three-State

Max
tSCLK + 1 tSCLK + 1

Unit
ns ns ns ns

Rev. E | Page 38 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Table 32. External Late Frame Sync

VDDEXT 1.8V Nominal

VDDEXT 2.5 V/3.3V Nominal

Parameter

Min

Max

Min

Max

Switching Characteristics

tDDTLFSE1, 2 Data Delay from Late External TFSx or External RFSx with

12

10

MCE = 1, MFD = 0

tDTENLFSE1, 2 Data Enable from Late FS or MCE = 1, MFD = 0

0

0

1 MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFSE. 2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.

Unit ns ns

EXTERNAL RFSx IN MULTI-CHANNEL MODE

DRIVE EDGE

SAMPLE EDGE

RSCLKx

DRIVE EDGE

RFSx

DTx

tDDTLFSE tDTENLFSE

LATE EXTERNAL TFSx DRIVE EDGE
TSCLKx

1ST BIT

SAMPLE EDGE

DRIVE EDGE

TFSx tDDTLFSE
DTx

1ST BIT

Figure 23. External Late Frame Sync

Rev. E | Page 39 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518
Serial Peripheral Interface (SPI) Port--Master Timing Table 33 and Figure 24 describe SPI port master operations. Table 33. Serial Peripheral Interface (SPI) Port--Master Timing

Parameter

Timing Requirements

tSSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

tHSPIDM

SCK Sampling Edge to Data Input Invalid

Switching Characteristics

tSDSCIM tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tDDSPIDM tHDSPIDM

SPISELx low to First SCK Edge Serial Clock High Period Serial Clock Low Period Serial Clock Period Last SCK Edge to SPISELx High Sequential Transfer Delay SCK Edge to Data Out Valid (Data Out Delay) SCK Edge to Data Out Invalid (Data Out Hold)

VDDEXT 1.8V Nominal

Min

Max

11.6 �1.5

2 � tSCLK �1.5 2 � tSCLK �1.5 2 � tSCLK �1.5 4 � tSCLK 2 � tSCLK �1.5 2 � tSCLK� 1.5
6 �1

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

9.6

ns

�1.5

ns

2 � tSCLK � 1.5

ns

2 � tSCLK � 1.5

ns

2 � tSCLK � 1.5

ns

4 � tSCLK

ns

2 � tSCLK � 1.5

ns

2 � tSCLK � 1.5

ns

6

ns

�1

ns

SPIxSELy (OUTPUT)
SPIxSCK (OUTPUT)

tSDSCIM

tSPICLM

tSPICHM

tSPICLK

tHDSM

tSPITDM

SPIxMOSI (OUTPUT)
CPHA = 1
SPIxMISO (INPUT)

tHDSPIDM

tDDSPIDM

tSSPIDM tHSPIDM

SPIxMOSI (OUTPUT)
CPHA = 0

tSSPIDM

SPIxMISO (INPUT)

tHSPIDM

tHDSPIDM

tDDSPIDM

Figure 24. Serial Peripheral Interface (SPI) Port--Master Timing

Rev. E | Page 40 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Serial Peripheral Interface (SPI) Port--Slave Timing Table 34 and Figure 25 describe SPI port slave operations.
Table 34. Serial Peripheral Interface (SPI) Port--Slave Timing

Parameter

Timing Requirements

tSPICHS

Serial Clock High Period

tSPICLS

Serial Clock Low Period

tSPICLK

Serial Clock Period

tHDS

Last SCK Edge to SPISS Not Asserted

tSPITDS

Sequential Transfer Delay

tSDSCI

SPISS Assertion to First SCK Edge

tSSPID

Data Input Valid to SCK Edge (Data Input Setup)

tHSPID

SCK Sampling Edge to Data Input Invalid

Switching Characteristics

tDSOE tDSDHI tDDSPID tHDSPID

SPISS Assertion to Data Out Active SPISS Deassertion to Data High Impedance SCK Edge to Data Out Valid (Data Out Delay) SCK Edge to Data Out Invalid (Data Out Hold)

VDDEXT 1.8V Nominal

Min

Max

2 � tSCLK �1.5 2 � tSCLK �1.5 4 � tSCLK �1.5 2 � tSCLK � 1.5 2 � tSCLK � 1.5 2 � tSCLK �1.5 1.6 2

0

12

0

11

10

0

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

2 � tSCLK �1.5

ns

2 � tSCLK �1.5

ns

4 � tSCLK �1.5

ns

2 � tSCLK � 1.5

ns

2 � tSCLK � 1.5

ns

2 � tSCLK �1.5

ns

1.6

ns

1.6

ns

0

10.3

ns

0

9

ns

10

ns

0

ns

SPIxSS (INPUT)
SPIxSCK (INPUT)
SPIxMISO (OUTPUT) CPHA = 1 SPIxMOSI
(INPUT)

tSDSCI

tSPICLS

tSPICHS

tDSOE

tDDSPID

tHDSPID

tSSPID

tHSPID

tDSOE
SPIxMISO (OUTPUT)
CPHA = 0
SPIxMOSI (INPUT)

tHDSPID

tSPICLK tDDSPID

tHDS

tSPITDS

tDSDHI

tDDSPID tSSPID

tDSDHI tHSPID

Figure 25. Serial Peripheral Interface (SPI) Port--Slave Timing
Universal Asynchronous Receiver-Transmitter (UART) Ports--Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF51x Hardware Reference Manual.

Rev. E | Page 41 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

General-Purpose Port Timing
Table 35 and Figure 26 describe general-purpose port operations.

Table 35. General-Purpose Port Timing

VDDEXT 1.8V Nominal

Parameter

Min

Max

Timing Requirement

tWFI

General-Purpose Port Signal Input Pulse Width

Switching Characteristic

tSCLK + 1

tGPOD

General-Purpose Port Signal Output Delay from CLKOUT Low 0

11

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

tSCLK + 1

ns

0

8.5

ns

CLKOUT GPIO OUTPUT
GPIO INPUT

tGPOD tWFI

Figure 26. General-Purpose Port Timing

Timer Clock Timing Table 36 and Figure 27 describe timer clock timing.

Table 36. Timer Clock Timing

Parameter

Switching Characteristic

tTODP

Timer Output Update Delay After PPICLK High

Min

Max

Unit

12

ns

PPI_CLK TMRx OUTPUT

tTODP Figure 27. Timer Clock Timing

Rev. E | Page 42 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Timer Cycle Timing
Table 37 and Figure 28 describe timer expired operations. The input signal is asynchronous in "width capture mode" and "external clock mode" and has an absolute maximum input frequency of (fSCLK/2) MHz.

Table 37. Timer Cycle Timing

VDDEXT 1.8V Nominal

VDDEXT 2.5 V/3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Characteristics

tWL1

Timer Pulse Width Input Low (Measured In SCLK Cycles) tSCLK

tSCLK

ns

tWH1

Timer Pulse Width Input High (Measured In SCLK Cycles) tSCLK

tSCLK

ns

tTIS2

Timer Input Setup Time Before CLKOUT Low

10

7

ns

tTIH2

Timer Input Hold Time After CLKOUT Low

�2

�2

ns

Switching Characteristics

tHTO

Timer Pulse Width Output (Measured In SCLK Cycles)

tSCLK � 1.5

(232�1)tSCLK tSCLK � 1

(232�1)tSCLK ns

tTOD

Timer Output Update Delay After CLKOUT High

6

6

ns

1 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode. 2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

CLKOUT TMRx OUTPUT
TMRx INPUT

tTOD

tTIS

tTIH

tHTO

tWH,tWL Figure 28. Timer Cycle Timing

Rev. E | Page 43 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Up/Down Counter/Rotary Encoder Timing

Table 38. Up/Down Counter/Rotary Encoder Timing

VDDEXT 1.8V Nominal

Parameter

Min Max

Timing Requirements

tWCOUNT tCIS tCIH

Up/Down Counter/Rotary Encoder Input Pulse Width Counter Input Setup Time Before CLKOUT Low1 Counter Input Hold Time After CLKOUT Low1

tSCLK + 1 9 0

1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

tSCLK + 1

ns

7

ns

0

ns

CLKOUT CUD/CDG/CZM

tCIS tCIH

tWCOUNT

Figure 29. Up/Down Counter/Rotary Encoder Timing

10/100 Ethernet MAC Controller Timing
Table 39 through Table 44 and Figure 30 through Figure 35 describe the 10/100 Ethernet MAC Controller operations.

Table 39. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Parameter1

Timing Requirements

tERXCLKF tERXCLKW tERXCLKIS tERXCLKIH

ERxCLK Frequency (fSCLK = SCLK Frequency) ERxCLK Width (tERxCLK = ERxCLK Period) Rx Input Valid to ERxCLK Rising Edge (Data In Setup) ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)

1 MII inputs synchronous to ERxCLK are ERxD3�0, ERxDV, and ERxER.

VDDEXT 1.8V Nominal

Min

Max

None tERxCLK � 40% 7.5 7.5

25 + 1% tERxCLK � 60%

VDDEXT 2.5 V/3.3V Nominal

Min

Max

Unit

None tERxCLK � 35% 7.5 7.5

25 + 1% tERxCLK � 65%

MHz ns ns ns

ERx_CLK
ERxD3�0 ERxDV ERxER

tERXCLKW

tERXCLK

tERXCLKIS tERXCLKIH Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Rev. E | Page 44 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Table 40. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Parameter1

VDDEXT 1.8V Nominal

Min

Max

Switching Characteristics

tETF tETXCLKW tETXCLKOV tETXCLKOH

ETxCLK Frequency (fSCLK = SCLK Frequency)

None

ETxCLK Width (tETxCLK = ETxCLK Period)

tETxCLK � 40%

ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)

25 + 1% tETxCLK � 60% 20

ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0

1 MII outputs synchronous to ETxCLK are ETxD3�0.

VDDEXT 2.5 V/3.3V Nominal

Min

Max

None

25 + 1%

tETxCLK � 35% tETxCLK � 65% 20

0

Unit
MHz ns ns ns

MIITxCLK
ETxD3�0 ETxEN

tETXCLKW tETXCLKOH

tETXCLK

tETXCLKOV

Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Table 41. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Parameter1

VDDEXT 1.8V Nominal

Min

Max

Timing Requirements

tEREFCLKF tEREFCLKW tEREFCLKIS

REF_CLK Frequency (fSCLK = SCLK Frequency) EREF_CLK Width (tEREFCLK = EREFCLK Period) Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)

None

50 + 1%

tEREFCLK � 40% tEREFCLK � 60% 4

tEREFCLKIH

RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2 Hold)

1 RMII inputs synchronous to RMII REF_CLK are ERxD1�0, RMII CRS_DV, and ERxER.

VDDEXT 2.5 V/3.3V Nominal

Min

Max

None

50 + 1%

tEREFCLK � 35% tEREFCLK � 65% 4

2

Unit
MHz ns ns
ns

RMII_REF_CLK

tREFCLKW

tREFCLK

ERxD1�0 ERxDV ERxER

tREFCLKIS tREFCLKIH

Figure 32. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Rev. E | Page 45 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Table 42. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Parameter1

Switching Characteristics

tEREFCLKOV tEREFCLKOH

RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid) RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)

1 RMII outputs synchronous to RMII REF_CLK are ETxD1�0.

Min

Max

Unit

8.1

ns

2

ns

RMII_REF_CLK
ETxD1�0 ETxEN

tREFCLK tREFCLKOH
tREFCLKOV

Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Rev. E | Page 46 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

Table 43. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal

Parameter

Min

Max

Unit

Timing Requirements

tECOLH
tECOLL
tECRSH tECRSL

COL Pulse Width High1
COL Pulse Width Low1
CRS Pulse Width High2 CRS Pulse Width Low2

tETxCLK � 1.5

ns

tERxCLK � 1.5

ns

tETxCLK � 1.5

ns

tERxCLK � 1.5

ns

tETxCLK � 1.5

ns

tETxCLK � 1.5

ns

1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.

MIICRS, COL

tECRSH tECOLH

tECRSL tECOLL

Figure 34. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal

Table 44. 10/100 Ethernet MAC Controller Timing: MII Station Management

Parameter1

Min

Max

Unit

Timing Requirements

tMDIOS

MDIO Input Valid to MDC Rising Edge (Setup)

tMDCIH

MDC Rising Edge to MDIO Input Invalid (Hold)

Switching Characteristics

11.5

ns

0

ns

tMDCOV tMDCOH

MDC Falling Edge to MDIO Output Valid MDC Falling Edge to MDIO Output Invalid (Hold)

25

ns

�1.25

ns

1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK. MDIO is a bidirectional data line.

MDC (OUTPUT) MDIO (OUTPUT)

tMDCOH

tMDCOV

MDIO (INPUT)

tMDIOS

tMDCIH

Figure 35. 10/100 Ethernet MAC Controller Timing: MII Station Management

Rev. E | Page 47 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

JTAG Test And Emulation Port Timing Table 45 and Figure 36 describe JTAG port operations.

Table 45. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS1 tHSYS1

System Inputs Setup Before TCK High System Inputs Hold After TCK High

tTRSTW

TRST Pulse Width2 (measured in TCK cycles)

Switching Characteristics

20

ns

4

ns

4

ns

4

ns

5

ns

4

TCK

tDTDO tDSYS3

TDO Delay from TCK Low System Outputs Delay After TCK Low

10

ns

0

13

ns

1 System Inputs = DATA15�0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15�0, PG15�0, PH7�0, MDIO, TD1, TMS, RESET, NMI, BMODE2�0. 2 50 MHz Maximum. 3 System Outputs = DATA15�0, ADDR19�1, ABE1�0, ARE, AWE, AMS1�0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
DT0PRI, DT0SEC, PF15�0, PG15�0, PH7�0, MDC, MDIO.

TCK
TMS TDI
TDO
SYSTEM INPUTS
SYSTEM OUTPUTS

tTCK

tSTAP

tDTDO

tDSYS

tSSYS

tHTAP tHSYS

Figure 36. JTAG Port Timing

Rev. E | Page 48 of 63 | June 2020

OUTPUT DRIVE CURRENTS
Figure 37 through Figure 51 show typical current-voltage characteristics for the output drivers of the ADSP-BF51x processors.

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

200 160 120
80 40

VDDEXT = 3.6V @ � 40�C VDDEXT = 3.3V @ 25�C VDDEXT = 3.0V @ 105�C
VOH

0
�40
�80 VOL
�120

�160
�200 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 37. Driver Type A Current (3.3V VDDEXT/VDDMEM)

160 120 80 40
0 �40 �80 �120

VDDEXT = 2.75V @ � 40�C VDDEXT = 2.5V @ 25�C VDDEXT = 2.25V @ 105�C
VOH
VOL

�160 0

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 38. Driver Type A Current (2.5V VDDEXT/VDDMEM)

80 VDDEXT = 1.9V @ � 40�C

60

VDDEXT = 1.8V @ 25�C

VDDEXT = 1.7V @ 105�C

40

20

VOH

0 �20
VOL �40 �60

�80 0

0.5

1.0

1.5

SOURCE VOLTAGE (V)

Figure 39. Driver Type A Current (1.8V VDDEXT/VDDMEM)

SOURCE CURRENT (mA)

ADSP-BF512/BF514/BF516/BF518

The curves represent the current drive capability of the output drivers. See Table 7 for information about which driver type corresponds to a particular ball.

SOURCE CURRENT (mA)

240 200 160 120
80 40
0 �40 �80 �120 �160 �200 �240
0

VDDEXT = 3.6V @ � 40�C VDDEXT = 3.3V @ 25�C VDDEXT = 3.0V @ 105�C
VOH

VOL

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 40. Driver Type B Current (3.3V VDDEXT/VDDMEM)

SOURCE CURRENT (mA)

160

VDDEXT = 2.75V @ � 40�C

120

VDDEXT = 2.5V @ 25�C

80

VDDEXT = 2.25V @ 105�C

40 VOH
0

�40

�80
VOL �120

�160

�200 0

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 41. Driver Type B Current (2.5V VDDEXT/VDDMEM)

80

VDDEXT = 1.9V @ � 40�C

60

VDDEXT = 1.8V @ 25�C

40

VDDEXT = 1.7V @ 105�C

20

VOH

0

�20

�40 VOL
�60

�80

�100 0

0.5

1.0

1.5

SOURCE VOLTAGE (V)

Figure 42. Driver Type B Current (1.8V VDDEXT/VDDMEM)

SOURCE CURRENT (mA)

Rev. E | Page 49 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

100

80

VDDEXT = 3.6V @ � 40�C

VDDEXT = 3.3V @ 25�C

60

VDDEXT = 3.0V @ 105�C

40 VOH
20

0

�20
�40 VOL
�60
�80

�100 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 43. Driver Type C Current (3.3V VDDEXT/VDDMEM)

80 VDDEXT = 2.75V @ � 40�C

60

VDDEXT = 2.5V @ 25�C

VDDEXT = 2.25V @ 105�C 40

20 VOH
0

�20

�40 VOL
�60

�80 0

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 44. Drive Type C Current (2.5V VDDEXT/VDDMEM)

40 VDDEXT = 1.9V @ � 40�C

30

VDDEXT = 1.8V @ 25�C

VDDEXT = 1.7V @ 105�C

20

VOH 10

0
�10 VOL
�20
�30

�40 0

0.5

1.0

1.5

SOURCE VOLTAGE (V)

Figure 45. Driver Type C Current (1.8V VDDEXT/VDDMEM)

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

160 120
80 40

VDDEXT = 3.6V @ � 40�C VDDEXT = 3.3V @ 25�C VDDEXT = 3.0V @ 105�C
VOH

0

�40

�80 VOL
�120

�160 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 46. Driver Type D Current (3.3V VDDEXT/VDDMEM)

120 100
80 60 40 20
0 �20 �40 �60 �80 �100 �120
0

VDDEXT = 2.75V @ � 40�C VDDEXT = 2.5V @ 25�C VDDEXT = 2.25V @ 105�C
VOH

VOL

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 47. Driver Type D Current (2.5V VDDEXT/VDDMEM)

60

VDDEXT = 1.9V @ � 40�C

40

VDDEXT = 1.8V @ 25�C VDDEXT = 1.7V @ 105�C

20 VOH
0

�20 VOL
�40

�60 0

0.5

1.0

1.5

2

SOURCE VOLTAGE (V)

Figure 48. Driver Type D Current (1.8V VDDEXT/VDDMEM)

Rev. E | Page 50 of 63 | June 2020

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

60 50 40 30 20 10
0 �10 �20 �30 �40 �50 �60
0

0.5

1.0

VDDEXT = 3.6V @ � 40�C VDDEXT = 3.3V @ 25�C V = 3.0V @ 105�C
DDEXT

VOL

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 49. Driver Type E Current (3.3V VDDEXT/VDDMEM)

40 VDDEXT = 2.75V @ � 40�C

30

VDDEXT = 2.5V @ 25�C

VDDEXT = 2.25V @ 105�C 20

10

0

�10
VOL �20

�30

�40 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 50. Driver Type E Current (2.5V VDDEXT/VDDMEM)

20 VDDEXT = 1.9V @ � 40�C

15

V = 1.8V @ 25�C

DDEXT

V = 1.7V @ 105�C DDEXT

10

5

0
�5 VOL
�10
�15

�20 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 51. Driver Type E Current (1.8V VDDEXT/VDDMEM)

ADSP-BF512/BF514/BF516/BF518
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 52 shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/2.5 V/3.3 V.

INPUT OR
OUTPUT

VMEAS

VMEAS

Figure 52. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
Output signals are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving.
The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 53.

tDIS VOH
(MEASURED)
VOL (MEASURED)

REFERENCE SIGNAL

tDIS_MEASURED

tENA

VOH (MEASURED) - V VOL (MEASURED) + V
tDECAY

tENA_MEASURED
VOH(MEASURED) VTRIP(HIGH) VTRIP(LOW)
VOL(MEASURED) tTRIP

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Figure 53. Output Enable/Disable

The time tENA_MEASURED is the interval from when the reference signal switches to when the output voltage reaches VTRIP(high) or VTRIP(low). For VDDEXT (nominal) = 1.8 V, VTRIP (high) is 0.95 V, and VTRIP (low) is 0.85 V. For VDDEXT (nominal) = 2.5 V, VTRIP (high) is 1.3 V and VTRIP (low) is 1.2 V. For VDDEXT (nominal) = 3.3 V, VTRIP (high) is 1.7 V, and VTRIP (low) is 1.6 V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or VTRIP(low) trip voltage.
Time tENA is calculated as shown in the equation:
tENA = tENA_MEASURED � tTRIP
If multiple signals (such as the data bus) are enabled, the measurement value is that of the first signal to start driving.

SOURCE CURRENT (mA)

Rev. E | Page 51 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518
Output Disable Time Measurement
Output signals are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 53.
tDIS = tDIS_MEASURED � tDECAY
The time for the voltage on the bus to decay by V is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation:
tDECAY = CLV  IL
The time tDECAY is calculated with test loads CL and IL and with V equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8 V.
The time tDIS_MEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF51x processor's output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time is tDECAY plus the various output disable times as specified in the Timing Specifications (for example tDSDAT for an SDRAM write cycle as shown in SDRAM Interface Timing).
Capacitive Loading
Output delays and holds are based on standard capacitive loads of an average of 6 pF on all balls (see Figure 54). VLOAD is equal to (VDDEXT/VDDMEM)/2. The graphs of Figure 55 through Figure 66 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown.

VLOAD

50:

70:

50:

4pF

2pF

400:

TESTER PIN ELECTRONICS

45: 0.5pF

T1

DUT

OUTPUT

ZO = 50:(impedance) TD = 4.04 � 1.18 ns

NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 54. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
12

10 tRISE
8
tFALL 6

4

2 tRISE = 1.8V @ 25�C

tFALL = 1.8V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 55. Driver Type A Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM)

RISE AND FALL TIME (ns)

Rev. E | Page 52 of 63 | June 2020

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

ADSP-BF512/BF514/BF516/BF518

8

7

6

tRISE

5 tFALL
4

3

2

1

t = 2.5V @ 25�C

RISE

tFALL = 2.5V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 56. Driver Type A Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM)

6

5 tRISE
4 tFALL
3

2

1 tRISE = 3.3V @ 25�C

tFALL = 3.3V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 57. Driver Type A Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM)

9

8 tRISE
7

6 tFALL
5

4

3

2

1

tRISE = 1.8V @ 25�C

tFALL = 1.8V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 58. Driver Type B Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM)

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

7

6

5 t
RISE
4 tFALL
3

2

1

tRISE = 2.5V @ 25�C

tFALL = 2.5V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 59. Driver Type B Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM)

6

5
tRISE 4
tFALL 3

2

1 tRISE = 3.3V @ 25�C

tFALL = 3.3V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 60. Driver Type B Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM)

25

20 tRISE
15 tFALL
10

5

tRISE = 1.8V @ 25�C

tFALL = 1.8V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 61. Driver Type C Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM)

RISE AND FALL TIME (ns)

Rev. E | Page 53 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

RISE AND FALL TIME (ns)

16

14

12 tRISE
10 tFALL
8

6

4

2

tRISE = 2.5V @ 25�C

t = 2.5V @ 25�C FALL
0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 62. Driver Type C Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM)

RISE AND FALL TIME (ns)

14

12
tRISE 10

8 tFALL
6

4

2

tRISE = 3.3V @ 25�C

tFALL = 3.3V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 63. Driver Type C Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM)

14

12 tRISE
10
t FALL
8

6

4

2

tRISE = 1.8V @ 25�C

t = 1.8V @ 25�C FALL
0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 64. Driver Type D Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (1.8V VDDEXT/VDDMEM)

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

10

9

8

7 tRISE
6 tFALL
5

4

3

2

1

tRISE = 2.5V @ 25�C

tFALL = 2.5V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 65. Driver Type D Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (2.5V VDDEXT/VDDMEM)

8

7

6 t
RISE
5 tFALL
4

3

2

1

tRISE = 3.3V @ 25�C

tFALL = 3.3V @ 25�C 0

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 66. Driver Type D Typical Rise and Fall Times (10%�90%) vs. Load Capacitance (3.3V VDDEXT/VDDMEM)

Rev. E | Page 54 of 63 | June 2020

THERMAL CHARACTERISTICS
To determine the junction temperature on the application printed circuit board use:
TJ = TCASE + JT  PD
where: TJ = Junction temperature (�C) TCASE = Case temperature (�C) measured by customer at top center of package. JT = From Table 47 PD = Power dissipation (see Total Power Dissipation for the method to calculate PD) Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation:
TJ = TA + JA  PD
where: TA = Ambient temperature (�C) Values of JC are provided for package comparison and printed circuit board design considerations when an external heat sink is required. Values of JB are provided for package comparison and printed circuit board design considerations. In Table 47, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. The LQFP_EP package requires thermal trace squares and thermal vias to an embedded ground plane in the PCB. The paddle must be connected to ground for proper operation to data sheet specifications. Refer to JEDEC standard JESD51-5 for more information.

ADSP-BF512/BF514/BF516/BF518

Table 46. Thermal Characteristics for SQ-176-2 Package

Parameter JA JMA JMA JC JT JT JT

Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow

Typical 17.4 14.8 14.0 7.8 0.28 0.39 0.48

Unit �C/W �C/W �C/W �C/W �C/W �C/W �C/W

Table 47. Thermal Characteristics for BC-168-1 Package

Parameter JA JMA JMA JC JT JT JT

Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow

Typical 30.5 27.6 26.3 11.1 0.20 0.35 0.45

Unit �C/W �C/W �C/W �C/W �C/W �C/W �C/W

Rev. E | Page 55 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

176-LEAD LQFP_EP LEAD ASSIGNMENT

Table 48 lists the LQFP_EP leads by lead number.

Table 48. 176-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)

Lead No. 1 2

Signal GND GND

Lead No. 45 46

Signal GND GND

Lead No. 89 90

Signal GND GND

Lead No. 133 134

3

PF9

47

PG1

91

A12

135

4

PF8

48

PG0

92

A11

136

5

PF7

49

VDDEXT

93

A10

137

6

PF6

50

TDO

94

A9

138

7

VDDEXT

51

EMU

95

VDDMEM

139

8

VPPOTP

52

TDI

96

A8

140

9

VDDOTP

53

TCK

97

A7

141

10

PF5

54

TRST

98

VDDINT

142

11

PF4

55

TMS

99

GND

143

12

PF3

56

D15

100

VDDINT

144

13

PF2

57

D14

101

A6

145

14

VDDINT

58

D13

102

A5

146

15

GND

59

VDDMEM

103

A4

147

16

VDDEXT

60

D12

104

VDDMEM

148

17

VDDEXT

61

D11

105

A3

149

18

PF1

62

D10

106

A2

150

19

PF0

63

VDDINT

107

A1

151

20

PG15

64

D9

108

ABE1

152

21

PG14

65

D8

109

ABE0

153

22

GND

66

D7

110

SA10

154

23

VDDINT

67

GND

111

GND

155

24

VDDEXT

68

VDDMEM

112

VDDMEM

156

25

PG13

69

D6

113

SWE

157

26

PG12

70

D5

114

SCAS

158

27

PG11

71

D4

115

SRAS

159

28

PG10

72

D3

116

VDDINT

160

29

VDDEXT

73

D2

117

GND

161

30

VDDINT

74

D1

118

SMS

162

31

PG9

75

VDDMEM

119

SCKE

163

32

PG8

76

D0

120

AMS1

164

33

PG7

77

A19

121

ARE

165

34

PG6

78

A18

122

AWE

166

35

VDDEXT

79

VDDINT

123

AMS0

167

36

PG5

80

A17

124

VDDMEM

168

37

PG4

81

A16

125

CLKOUT

169

38

PG3

82

VDDMEM

126

VDDEXT

170

39

PG2

83

GND

127

NC1

171

40

BMODE2

84

A15

128

VDDEXT

172

41

BMODE1

85

A14

129

VDDEXT

173

42

BMODE0

86

A13

130

EXT_WAKE

174

43

GND

87

GND

131

GND

175

44

GND

88

GND

132

GND

176

GND * Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must be robustly connected to GND.

1 Do not make any electrical connection to this pin.

Signal GND GND PG VDDEXT GND VDDINT GND RTXO RTXI VDDRTC CLKIN XTAL VDDEXT RESET NMI VDDEXT GND CLKBUF GND VDDINT PH7 PH6 PH5 PH4 GND VDDEXT PH3 PH2 PH1 PH0 GND VDDINT PF15 PF14 PF13 PF12 GND VDDEXT PF11 SDA SCL PF10 GND GND 177*

Rev. E | Page 56 of 63 | June 2020

Figure 67 shows the top view of the LQFP_EP lead configuration. Figure 68 shows the bottom view of the LQFP_EP lead configuration.
PIN 176 PIN 1

ADSP-BF512/BF514/BF516/BF518
PIN 133 PIN 132

PIN 1 INDICATOR

ADSP-BF51X 176-LEAD LQFP_EP
TOP VIEW

PIN 44 PIN 45

PIN 89 PIN 88

Figure 67. 176-Lead LQFP_EP Lead Configuration (Top View)

PIN 133 PIN 132

PIN 176 PIN 1

ADSP-BF51X 176-LEAD LQFP_EP
BOTTOM VIEW

GND PAD (PIN 177)

PIN 1 INDICATOR

PIN 89 PIN 88

PIN 44 PIN 45

Figure 68. 176-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. E | Page 57 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

168-BALL CSP_BGA BALL ASSIGNMENT

Table 49 lists the CSP_BGA by ball number.

Table 49. 168-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)

Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name

A1 GND A2 SCL A3 SDA A4 PF13 A5 PF15 A6 PH2 A7 PH1 A8 PH5 A9 PH6 A10 PH7 A11 CLKBUF

C1 PF4

C2 PF7

C3 PF8

C4 PF10

C5

VDDEXT

C6

VDDEXT

C7 PF11

C8

VDDEXT

C9

VDDINT

C10

VDDEXT

C11 RTXI

E10

VDDINT

E12

VDDMEM

E13 ARE

E14 AWE

F1

PF0

F2

PF1

F3

VDDINT

F5

VDDEXT

F6

GND

F7

GND

F8

GND

H1 PG12

H2 PG13

H3 PG11

H5

VDDEXT

H6 GND

H7 GND

H8 GND

H9 GND

H10

VDDINT

H12 A3

H13 ABE0

K6

VDDMEM

K7

VDDMEM

K8

VDDMEM

K9

VDDMEM

K10

VDDMEM

K12 A8

K13 A2

K14 A1

L1

PG5

L2

PG3

L3

PG2

N1 BMODE1 N2 PG1 N3 TDO N4 TRST N5 TMS N6 D13 N7 D9 N8 D5 N9 D1 N10 A18 N11 A16

A12 XTAL

C12 RTXO

F9

GND

H14 SCAS

L12 A9

N12 A14

A13 CLKIN

A14 GND

B1

VDDOTP

B2

GND

B3 PF9

C13 PG C14 NC1 D1 PF3 D2 PF5 D3 VPPOTP

F10

VDDINT

F12 SMS

F13 SCKE

F14 AMS1

G1 PG15

J1

PG10

J2

VDDEXT

J3

PG9

J5

VDDMEM

J6

GND

L13 A6

N13 A11

L14 A4

N14 A7

M1 PG4

P1

GND

M2 BMODE2 P2

TDI

M3 BMODE0 P3

TCK

B4

PF12

B5 PF14

B6 PH0

B7

PH3

B8 PH4

D12

VDDEXT

G2 PG14

D13 CLKOUT

G3

VDDINT

D14 AMS0

G5

VDDEXT

E1

VDDEXT

G6 GND

E2

PF2

G7 GND

J7

GND

J8

GND

J9

GND

J10

VDDINT

J12 A15

M4 PG0 M5 EMU M6 D12 M7 D10 M8 D2

P4

D15

P5

D14

P6

D11

P7

D8

P8

D7

B9

VDDEXT

E3

B10 RESET

E5

B11 NMI

E6

B12

VDDRTC

E7

B13

VDDEXT

E8

B14 EXT_WAKE E9

PF6 VDDEXT VDDEXT VDDINT VDDINT VDDINT

G8 GND

G9 GND

G10

VDDINT

G12 SWE

G13 SRAS

G14 GND

J13 ABE1

J14 SA10

K1

PG6

K2

PG8

K3

PG7

K5

VDDMEM

M9 D0 M10 A17 M11 A13 M12 A12 M13 A10 M14 A5

P9

D6

P10 D4

P11 D3

P12 A19

P13 GND

P14 GND

1 Do not make any electrical connection to this pin.

Rev. E | Page 58 of 63 | June 2020

Figure 69 shows the top view of the CSP_BGA ball configuration. Figure 70 shows the bottom view of the CSP_BGA ball configuration.

ADSP-BF512/BF514/BF516/BF518

A1 BALL PAD CORNER

A B
NC C
D E F G H J K L M N P
1 2 3 4 5 6 7 8 9 10 11 12 13 14

KEY V DDINT V DDEXT

TOP VIEW

Figure 69. 168-Ball CSP_BGA Ball Configuration (Top View)

GND I/O

V DDMEM
V DDRTC

A1 BALL PAD CORNER

A B
C NC
D E F G H J K L M N P
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW

KEY V DDINT V DDEXT

GND I/O

Figure 70. 168-Ball CSP_BGA Ball Configuration (Bottom View)

V DDMEM
V DDRTC

Rev. E | Page 59 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518
OUTLINE DIMENSIONS
Dimensions in Figure 71 are shown in millimeters.

0.75 0.60 0.45
1.00 REF

1.60 MAX
176 1

26.20 26.00 SQ 25.80
PIN 1

24.10 24.00 SQ 23.90

NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO GND. IMPLEMENT THIS BY SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS THE SAME SIZE AS THE EXPOSED PAD. THE GND PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.

133

133

176

132

132

1

1.45 1.40 1.35
0.15 0.10 0.05

12� SEATING PLANE

0.20 0.15 0.09 7� 0�
0.08 MAX COPLANARITY

VIEW A
ROTATED 90� CCW

TOP VIEW (PINS DOWN)

44 45
VIEW A

0.50 BSC LEAD PITCH

89 88

89 88

0.27 0.22 0.17

COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD
Figure 71. 176-Lead Low Profile Quad Flat Package [LQFP_EP] (SQ-176-2)
Dimensions shown in millimeters

EXPOSED PAD

5.80 REF SQ

BOTTOM VIEW (PINS UP)

44 45

EXPOSED PAD IS CENTERED ON THE PACKAGE.

Rev. E | Page 60 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

A1 BALL CORNER

12.10 12.00 SQ 11.90

TOP VIEW

1.50

DETAIL A

1.40

1.30

10.40 BSC SQ
0.80 BSC
0.80 REF

14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P
BOTTOM VIEW

A1 BALL CORNER

0.70 REF
0.36 REF
SEATING PLANE

DETAIL A

1.12 1.06 1.00
0.34 NOM 0.29 MIN

0.50

COPLANARITY

0.45

0.20

0.40

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
Figure 72. 168-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-168-1)
Dimensions shown in millimeters

SURFACE-MOUNT DESIGN
Table 50 is provided as an aid to PCB design. For industry standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard.

Table 50. BGA Data for Use with Surface-Mount Design

Package 168-Ball CSP_BGA

Package Ball Attach Type Solder Mask Defined

Package Solder Mask Opening
0.35 mm diameter

Package Ball Pad Size 0.48 mm diameter

Rev. E | Page 61 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

AUTOMOTIVE PRODUCTS
The ADBF512W and ADBF518W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers should review the product Specifications section of this data sheet carefully. Only the

automotive grade products shown in Table 51 are available for use in automotive applications. Contact your local ADI account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Table 51. Automotive Products

Automotive Models1,2

Temperature Range3

Processor Instruction

Rate (Max)

Package Description

Package Option

ADBF512WBBCZ4xx

�40�C to +85�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADBF518WBBCZ4xx

�40�C to +85�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADBF512WBSWZ4xx

�40�C to +85�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADBF518WBSWZ4xx

�40�C to +85�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

1 Z = RoHS Compliant Part. 2 The use of xx designates silicon revision. 3 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for junction temperature (TJ) specification
which is the only temperature specification.

Rev. E | Page 62 of 63 | June 2020

ADSP-BF512/BF514/BF516/BF518

ORDERING GUIDE

Model1

Processor Instruction Temperature Range2 Rate (Max)

Package Description

Package Option

ADSP-BF512BBCZ-3

�40�C to +85�C

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512BBCZ-4

�40�C to +85�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512BSWZ-3

�40�C to +85�C

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF512BSWZ-4

�40�C to +85�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF512KBCZ-3

0�C to +70�C

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512KBCZ-4

0�C to +70�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512KSWZ-3

0�C to +70�C

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF512KSWZ-4

0�C to +70�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514BBCZ-3

�40�C to +85�C

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514BBCZ-4

�40�C to +85�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514BSWZ-3

�40�C to +85�C

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514BSWZ-4

�40�C to +85�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514KBCZ-3

0�C to +70�C

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514KBCZ-4

0�C to +70�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514KSWZ-3

0�C to +70�C

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514KSWZ-4

0�C to +70�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516KSWZ-3

0�C to +70�C

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516KBCZ-3

0�C to +70�C

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516KSWZ-4

0�C to +70�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516KBCZ-4

0�C to +70�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516BBCZ-3

�40�C to +85�C

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516BBCZ-4

�40�C to +85�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516BSWZ-3

�40�C to +85�C

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516BSWZ-4

�40�C to +85�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF518BBCZ-4

�40�C to +85�C

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF518BSWZ-4

�40�C to +85�C

400 MHz

176-Lead LQFP_EP

SQ-176-2

1 Z = RoHS compliant part. 2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for junction temperature (TJ) specification
which is the only temperature specification.

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D08574-6/20(E)
Rev. E | Page 63 of 63 | June 2020