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JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

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Updated for Intel Quartus Prime Design Suite: 21.2, IP Version: 19.2.0. Describes the features, usage guidelines, and detailed description for the JESD204B design example using Intel Stratix 10 devices.

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JESD204B Intel Stratix 10 FPGA IP Design Example User Guide
Updated for Intel� Quartus� Prime Design Suite: 21.2 IP Version: 19.2.0

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Contents
Contents
1. JESD204B Intel� Stratix� 10 FPGA IP Design Example User Guide................................. 3 1.1. JESD204B Intel Stratix 10 FPGA IP Design Example Quick Start Guide.......................... 3 1.1.1. Directory Structure.................................................................................... 3 1.1.2. Generating the Design................................................................................5 1.1.3. Simulating the Design................................................................................ 7 1.1.4. Compiling and Testing the Design................................................................ 8 1.2. Design Example Detailed Description...................................................................... 16 1.2.1. Features................................................................................................. 16 1.2.2. Hardware and Software Requirements........................................................ 16 1.2.3. Supported Configurations..........................................................................17 1.2.4. Presets................................................................................................... 19 1.2.5. Functional Description.............................................................................. 20 1.2.6. Simulation.............................................................................................. 32 1.2.7. Design Example Files................................................................................35 1.2.8. Registers................................................................................................ 36 1.2.9. Signals................................................................................................... 36 1.2.10. Customizing the Design Example..............................................................38 1.3. JESD204B Intel Stratix 10 FPGA IP Design Example User Guide Archives..................... 41 1.4. Document Revision History for the JESD204B Intel Stratix 10 FPGA IP Design Example User Guide.......................................................................................... 42

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1. JESD204B Intel� Stratix� 10 FPGA IP Design Example User Guide
Intel provides a design example of the JESD204B Intel� FPGA IP targeting Intel Stratix� 10 devices. Generate the JESD204B design example through the IP catalog in the Intel Quartus� Prime Pro Edition software.

1.1. JESD204B Intel Stratix 10 FPGA IP Design Example Quick Start Guide
The JESD204B Intel FPGA IP core provides the capability of generating design examples for selected configurations.
Figure 1. Development Stages for the Design Example

Simulation Fileset Design Example Generation
Synthesis Fileset

Simulation
(Simulator)
Compilation
(Quartus Prime)

Functional Simulation Hardware
Testing

1.1.1. Directory Structure
The JESD204B design example directories contain generated files for the design examples.
Figure 2. Directory Structure for the JESD204B Design Example

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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ed_sim

ed_synth

ip_sim

testbench
models setup_script pattern

ip altjesd_ed_qsys_<data path> altjesd_ss_<data path> pattern

gen_sim_verilog.tcl gen_sim_vhdl.tcl README.txt
testbench

transport_layer

mentor

altera_jesd204_ed_<data path>.qpf

aldec

altera_jesd204_ed_<data path>.qsf

cadence

altjesd_ed_qsys_<data path>.qsys

xcelium

altjesd_ss_<data path>.qsys

synopsys
vcs vcsmx *.v

altera_jesd204_ed_<data path>.sv altera_jesd204_ed_<data path>.sdc *.v
system_console1

Note: 1. Directory `system_console' only generated when `Data Path Only' design example is generated.

Table 1.

Directory and File Description

Directory/File

ed_sim

ed_sim/testbench/models

ed_sim/testbench/setup_scripts

ed_sim/testbench/pattern

ed_sim/testbench/transport_layer

ed_sim/testbench/aldec

ed_sim/testbench/xcelium

ed_sim/testbench/mentor

Description
The folder that contains simulation testbench files.
The folder that contains the testbench and source files.
The folder that contains the test flow setup scripts.
The folder that contains the source files for the pattern generator/checker.
The folder that contains the source files for the transport layer.
The folder that contains the test flow run scripts for RivieraPRO* simulator. Also serves as the working directory for the simulator.
The folder that contains the test flow run scripts for Xcelium* Parallel simulator. Also serves as the working directory for the simulator.
The folder that contains the test flow run scripts for ModelSim* simulator. Also serves as the working directory for the simulator.
continued...

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Directory/File ed_sim/testbench/synopsys/vcs

ed_sim/testbench/synopsys/vcsmx

ed_synth ed_synth/ip ed_synth/altjesd_ed_qsys_<data path>

ed_synth/altjesd_ss_<data path>

ed_synth/pattern
ed_synth/transport_layer
ed_synth/altera_jesd204_ed_<data path>.qpf ed_synth/altera_jesd204_ed_<data path>.qsf ed_synth/altjesd_ed_qsys_<data path>.qsys ed_synth/altjesd_ss_<data path>.qsys ed_synth/altera_jesd204_ed_<data path>.sv ed_synth/altera_jesd204_ed_<data path>.sdc ed_synth/system_console

*.v ip_sim

1.1.2. Generating the Design

Start Parameter Editor

Specify IP Variation and Select Device

Description
The folder that contains the test flow run scripts for VCS* simulator. Also serves as the working directory for the simulator.
The folder that contains the test flow run scripts for VCS MX simulator. Also serves as the working directory for the simulator.
The folder that contains design example synthesizable components.
The folder that contains Platform Designer-instantiated IP modules.
The folder that contains Platform Designer-generated modules from the altjesd_ed_qsys_<data path>.qsys system.
The folder that contains Platform Designer-generated modules from the altjesd_ss_<data path>.qsys system.
The folder that contains the source files for the pattern generator/checker.
The folder that contains the source files for the transport layer.
Intel Quartus Prime project and settings files.
Platform Designer top level system.
Platform Designer subsystem.
Top level HDL source file.
Top level design constraints file.
The folder that contains all files necessary to run scripts in System Console (See Design Example Files for more details on folder content).
Miscellaneous source files
The folder that contains the simulation script to generate the JESD204B IP core Verilog/VHDL simulation model.

Select Design Parameters

Specify Example Design

Initiate Design Generation

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Figure 3. Example Design Tab

To generate the design example from the IP parameter editor:
1. Create a project targeting device family and select the desired device.
2. In the IP Catalog, locate and double-click Interface Protocols JESD JESD204B Intel FPGA IP. The IP parameter editor appears.
3. Specify a top-level name and the folder for your custom IP variation.. Click OK.
4. Select a design from the Presets library by double-clicking the desired preset. When you select a design, the system automatically populates the IP parameters for the design.
Note: If you select another design, the settings of the IP parameters change accordingly.
5. You can customize the preset parameter values according to your specifications. Under the IP tab, specify the JESD204B IP core parameters for your design.
Note: The JESD204B IP core supports a limited range of parameter combinations. Refer to the Supported Configurations on page 17 section for more details. If you specify an unsupported combination of parameters, the Available Example Designs automatically selects None as the default.
6. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
Note: To generate the design example for hardware testing on selected Intel development kits, select the appropriate target development kit from the Target Development Kit drop down box.
7. Click Generate Example Design.

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The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.
Related Information � Presets on page 19 � Supported Configurations on page 17

1.1.2.1. Design Example Parameters

The JESD204B IP parameter editor includes a Example Design tab for you to specify certain parameters before generating the design example.

Table 2.

Parameters in the Example Design Tab

Parameter

Options

Description

Available Example Designs

None (Default)

No design examples selected.

System Console Control

Design example with System Console control.

Example Design Files

Simulation

Generate simulation fileset.

Synthesis

Generate synthesis fileset.

Generated HDL Format for Simulation Verilog (Default)

Verilog HDL format for entire simulation fileset.

VHDL

VHDL format for generated top-level wrapper file set.

Generated HDL Format for Synthesis Verilog (Default)

Verilog HDL format for synthesis fileset.

Example Design Customizations

Generate 3-wire SPI module Check to enable 3-wire SPI interface instead of 4wire SPI interface.

1.1.3. Simulating the Design
These general steps describe how to run the design example simulation. For specific commands for each design example variant, refer to its respective section.

Change to Testbench Directory

Run <Simulation Script>

Analyze Results

To simulate the design, perform the following steps:
1. Change the working directory to <example_design_directory>/ed_sim/ testbench/<Simulator>.
2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.

Riviera-PRO ModelSim VCS/VCS MX Xcelium Parallel

Simulator

Command do run_tb_top.tcl do run_tb_top.tcl sh run_tb_top.sh sh run_tb_top.sh

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The simulation ends with messages that indicate whether the run was successful or not. Refer to Simulation Message and Description table in Testbench on page 33 for more information on messages reported by the simulation flow.
1.1.4. Compiling and Testing the Design
The JESD204B parameter editor allows you to run the design example on a target development kit.

Compile Design in Quartus Prime
Software

Set up Hardware

Program Device

Test Design in Hardware

Perform the following steps to compile the design and program the development board:
1. Launch the Intel Quartus Prime software and compile the design (Processing Start Compilation).
The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel FPGA Download Cable II component or using an external Intel FPGA Download Cable II module to connect to the external JTAG connector.
3. If you are performing external loopback test:
� For designs targeting Intel Stratix 10 GX FPGA Development Kit (H-tile), attach the FMC loopback card to the FMC port A connector.
� For designs targeting Intel Stratix 10 TX Signal Integrity Development Kit (Etile), attach the respective loopback module according to the board revision and channel bonding mode.
-- For engineering sample (ES) edition (Revision A) and non-bonded channel configuration, attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector.
-- For production edition (Revision B) and non-bonded channel configuration, attach the FMC+ loopback module at the FMC+ connector.
-- For production edition (Revision B) and bonded channel configuration, attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector.
4. Power-on the board.
5. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
Note: For more information about using the Clock Control application, refer to the Intel Stratix 10 GX FPGA Development Kit User Guide if you select Stratix 10 FPGA Development Kit or the Intel Stratix 10 TX Transceiver Signal Integrity Development Kit User Guide if you select Stratix 10 TX Signal Integrity Development Kit - E-tile.

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Table 3.

Clock Setting

Clock Name

Clock Frequency

refclk_xcvr Select the frequencies in the PLL/CDR Reference Clock Frequency drop down menu of the IP parameter editor.
refclk_core

mgmt_clk

100 MHz

Figure 4.

Intel Stratix 10 GX FPGA Development Kit Clock Control GUI Setting
This example shows the clock control GUI setting for 6.144 Gbps data rate applied to H-tile devices with Intel Stratix 10 GX FPGA Development Kit.

refclk_core

refclk_xcvr

mgmt_clk

Figure 5.

Intel Stratix 10 TX Signal Integrity Development Kit Clock Control GUI Setting for Non-Bonded Mode Design
This example shows the clock control GUI setting for a design example with non-bonded configuration. This design example is running at 6.144 Gbps on E-tile devices with Intel Stratix 10 TX Transceiver Signal Integrity Development Kit (applies to Revision A and Revision B).

refclk_core

mgmt_clk

refclk_xcvr

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Figure 6.

Intel Stratix 10 TX Signal Integrity Development Kit Clock Control GUI Setting for Bonded Mode Design
This example shows the clock control GUI setting for a design example with bonded configuration. This design example is running at 6.144 Gbps on E-tile devices with Intel Stratix 10 TX Transceiver Signal Integrity Development Kit (applies to Revision B).

refclk_core

mgmt_clk

refclk_xcvr

6. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel Quartus Prime Programmer.
Note: The generated design contains VID assignments that work for the Intel Stratix 10 GX FPGA development board and Intel Stratix 10 TX Signal Integrity development board. If your design is targeting to a VID part in other boards, you need to configure the VID parameters correctly by referring to the Intel Stratix 10 Power Management and VID Interface Implementation Guide section in the Intel Stratix 10 Power Management User Guide. You may ignore the VID assignments if your design is targeting non-VID device parts.
Related Information
� Intel Stratix 10 GX FPGA Development Kit User Guide
� Intel Stratix 10 TX Transceiver Signal Integrity Development Kit User Guide
� Intel Stratix 10 Power Management User Guide
� JESD204B Intel FPGA IP User Guide
� Intel FPGA JESD204B RX Address Map and Register Definitions
� Intel FPGA JESD204B TX Address Map and Register Definitions
1.1.4.1. Board Connectivity
If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

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Refer to the instructions in Generating the Design on page 5.

Note:

Running the hardware test with the design generated as-is is only possible when the JESD204B IP core is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.

Table 4.

Intel Stratix 10 GX FPGA Development Kit Board Connectivity for H-Tile Devices
The generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for Intel Stratix 10 GX FPGA development kit.

Port Name

Port Description

Board Component

Component Description

global_rst_n

Global reset

User PB0 push-button

refclk_xcvr

Transceiver reference clock input

Si5341 clock generator (OUT4)

refclk_core

Core PLL reference clock input

Si5341 clock generator (OUT7)

mgmt_clk

Control clock

Si5338 clock generator (CLK1)

tx_serial_data

TX serial data

J13

FMC port A connector

rx_serial_data

RX serial data

J13

FMC port A connector

Table 5.

Intel Stratix 10 TX Transceiver Signal Integrity Development Kit Board Connectivity for E-Tile Devices
The generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for Intel Stratix 10 TX Transceiver Signal Integrity development kit.

Port Name

Port Description

Board Component

Component Description

global_rst_n

Global reset

S8 push-button

refclk_xcvr

Transceiver reference clock input

Engineering sample version board revision A (nonbonded channels) and production version board revision B (non-bonded channels)

Si5341 clock generator (OUT8)

Production version board revision B (bonded channels)

Si5341 clock generator (OUT4)

refclk_core

Core PLL reference clock

input

Si5341 clock generator (OUT2)

mgmt_clk

Control clock

Si5341 clock generator (OUT3)

tx_serial_data

TX serial data

Engineering sample version board revision A (nonbonded, up to 4 channels)

U32-1

Intel Stratix 10 E-tile banks � 8B (QSFP-DD 1x2 connector)

Engineering sample version board revision A (nonbonded, 5�8 channels)

U32-1 and U75-1

Intel Stratix 10 E-tile banks � 8B (QSFP-DD 1x2 connector)

Production version board revision B (non-bonded, up to 8 channels)
continued...

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Port Name rx_serial_data

Port Description RX serial data

Board Component

Component Description

J27D

Intel Stratix 10 E-tile banks � 8B (FMC+ connector)

Production version board revision B (bonded, up to 4 channels)

U75-1

Intel Stratix 10 E-tile banks � 9C (QSFP-DD 1x2 connector)

Production version board revision B (bonded, 5�8 channels)

U32-1 and U75-1

Intel Stratix 10 E-tile banks � 9C (QSFP-DD 1x2 connector

Engineering sample version board revision A (nonbonded, up to 4 channels)

U32-1

Intel Stratix 10 E-tile banks � 8B (QSFP-DD 1x2 connector)

Engineering sample version board revision A (nonbonded, 5�8 channels)

U32-1 and U75-1

Intel Stratix 10 E-tile banks � 8B (QSFP-DD 1x2 connector)

Production version board revision B (non-bonded, up to 8 channels)

J27D

Intel Stratix 10 E-tile banks � 8B (FMC+ connector)

Production version board revision B (bonded, up to 4 channels)

U75-1

Intel Stratix 10 E-tile banks � 9C (QSFP-DD 1x2 connector)

Production version board revision B (bonded, 5�8 channels)

U32-1 and U75-1

Intel Stratix 10 E-tile banks � 9C (QSFP-DD 1x2 connector)

1.1.4.2. Hardware Test for System Console Control Design Example Perform the following instructions to run the hardware test for the design example.

Note:

This hardware test assumes that the System Console Control design is configured in duplex mode. Make your own modifications if using simplex mode design.

1. Launch the System Console tool from Intel Quartus Prime (Tools System Debugging Tools System Console).
2. In the TCL Console command prompt, type get_service_paths master to print a list of devices connected to your JTAG chain.
3. Open the main.tcl Tcl script located in the System Console directory in any text editor of your choice and locate the following line.
set master_index [expr {$master_list_length - <your offset>}]

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Figure 7.

4. Adjust the master_index offset as necessary to reflect your JTAG chain configuration such that the master_index always points to the Intel Stratix 10 device and save the file.
5. In the TCL Console command prompt, navigate to the system_console directory (cd system_console) and execute the main.tcl script (source main.tcl). Your TCL Console window should resemble the following figure.
Source main.tcl

Stratix 10 device

6. Type start_basic_test at the command prompt to execute the link setup and test procedure.
This procedure executes a set of instructions to set up the pattern generator and checker to transmit and check PRBS pattern, configure the JESD204B IP PHY internal serial loopback mode and report link status.
The following figure illustrates the expected result from a successful link setup and test.

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Figure 8. Successful Test in the System Console

7. In the event that the test fails due to a lane deskew error, use the rbd_offset procedure (described in the following table) to offset the default RBD setting. Refer to the JESD204B Intel FPGA IP User Guide for more details on using the RBD offset.

Table 6.

Procedures in the main.tcl System Console Script
The table describes useful procedures in the main.tcl that may be helpful in debugging.

Procedure

Values

Description

get_service_paths

{master}

Reports all devices that are connected to the JTAG chain. Use this information to set the master index to point to the Intel Stratix 10 device

get_master_index

N/A

Set the targeted device master index. Use get_service_paths master to determine the offset of the Intel Stratix 10 device in the JTAG chain, and edit the offset in this procedure accordingly.
continued...

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Procedure start_basic_test
reset force_link_frame_reset

Values N/A
N/A {0,1}

sloopback det_etile (1)
set_testmode
rbd_offset sysref read_status_pio

{0,1} {0,1}
{alt, ramp, prbs}
{integer} N/A N/A

read_err_status

N/A

clear_err_status

N/A

read_rx_status0

N/A

read_tx_status0

N/A

read_rx_syncn_sysref_ctrl N/A

wait_seconds

{integer}

wait_minutes

{integer}

run_load_PMA_configuration N/A
(1)

Description
Main procedure that sets up link serial loopback mode, pattern generator and checker test mode, pulses sysref and reports link status
Global reset
0: Deassert link and frame resets 1: Assert and hold link and frame resets Note: Link and frame clock domains should be held in reset while
writing to JESD204B IP CSR
0: Disable internal serial loopback 1: Enable internal serial loopback
0: Calls load_adaptation_PMA_configuration for external serial loopback 1: Calls load_adaptation_PMA_configuration for internal serial loopback
alt: Set pattern generator and checker to alternate pattern ramp: Set pattern generator and checker to ramp pattern prbs: Set pattern generator and checker to PRBS pattern
Adjust RBD offset value to eliminate RX lane deskew error.
Single pulse sysref
Read status PIO registers. PIO status configuration: Bit 0 -- Core PLL locked Bit 1 -- TX transceiver ready Bit 2 -- RX transceiver ready Bit 3 -- Pattern checker mismatch error Bit 4 -- TX link error (use read_err_status procedure to report error description) Bit 5 -- RX link error (use read_err_status procedure to report error description)
Read JESD204B IP error status registers. Refer to the JESD204B IP register maps for detailed description of status registers.
Clear JESD204B IP error status registers
Read JESD204B IP rx_status0 register. Refer to the JESD204B IP register maps for detailed description of status registers
Read JESD204B IP tx_status0 register. Refer to the JESD204B IP register maps for detailed description of status registers.
Read JESD204B IP syncn_sysref_ctrl register. Refer to the JESD204B IP register maps for detailed description of status registers
Wait for {integer} seconds
Wait for {integer} minutes
Loads transceiver calibration presets

load_adaptation_PMA_config {0,1} uration (1)

0: Disables internal serial loopback

(1) Applicable only for Intel Stratix 10 E-tile devices.

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Procedure

Values

Description
1: Enables internal serial loopback a. Runs set operation mode. Checks if loopback and PRBS settings
match the design requirements. b. Polls registers 0x207, 0x80 = operation passed, and 0x81 =
operation failed. c. Runs load PMA configuration and load PMA configuration status
check (0x40144 and 0x40143) if you turn on Enable adaptation load soft IP in the parameter editor. d. Starts calibration. Checks if loopback mode, load recipe enable, and PRBS settings match the design requirements. If PRBS is disabled, ensure that there is data sent from the core before starting calibration. e. Polls registers 0x207, 0x80 = operation passed, and 0x81 = operation failed. f. Runs check_cal_stat. � Sets registers 0x203, 0x202, 0x201, and 0x200 to 0x97000001 � Polls registers 0x207, 0x80 = operation passed, and 0x81 =
operation failed � Reads register 0x204. 0x80 indicates successful calibration

Related Information � JESD204B Intel FPGA IP User Guide � Intel FPGA JESD204B RX Address Map and Register Definitions � Intel FPGA JESD204B TX Address Map and Register Definitions

1.2. Design Example Detailed Description

1.2.1. Features
This design example has the following key features: � System Console using Tcl script control mechanism � Synthesis and simulation flows � Configurable transport layer and pattern generator and checker modules � Power-on self test with the following configurable test patterns:
-- Alternating -- Ramp -- PRBS � Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes � Supports option for 3-wire SPI
1.2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the example designs: � Intel Quartus Prime Pro Edition software � Intel Stratix 10 GX FPGA Development Kit (for H-tile devices) � Intel Stratix 10 TX Transceiver Signal Integrity Development Kit (for E-tile devices)

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1.2.3. Supported Configurations

The design examples only support a limited set of JESD204B IP parameter configurations. The IP parameter editor allows you to generate a design example only if the parameter configurations matches the following table.

Note:

If you are not able to generate a design example that fully matches your desired parameter settings, choose the closest allowable parameter values for generation. Modify the post-generated design parameters manually in the Intel Quartus Prime software to match your desire parameter settings. Refer to the JESD204B Intel FPGA IP User Guide for more details on the rules and ranges that govern each IP and transport layer parameter. Refer to Customizing the Design Example for more information about customizing the design example.

Table 7.

Supported JESD204B IP Core Parameter Configurations
Table lists the parameters for the JESD204B IP. The JESD204B IP parameters are governed by various rules and ranges that are described in the JESD204B Intel FPGA IP User Guide. Please refer to the JESD204B Intel FPGA IP User Guide for more details on the legal parameter values. The value ranges given below should be considered as a subset of the allowable values described in the JESD204B Intel FPGA IP User Guide.

JESD204B IP Parameters

Values

Wrapper Options

Both Base and PHY

Data Path

� Receiver � Transmitter � Duplex

JESD204B Subclass Data Rate

1 Any valid value(2)

Transceiver Tile

� E-Tile
� H-Tile
Note: This option is available only when you select an Intel Stratix 10 device that has both H-tile and E-tile. Select the transceiver tile you want for your device. If the Intel Stratix 10 device you selected has only H-tile or E-tile, the supported tile will be automatically selected. Refer to Table 8 on page 18 for more information.

PCS Option

� Enabled Hard PCS � Enabled Soft PCS

Bonding Mode

� Bonded � Non-bonded

PLL/CDR Reference Clock Frequency

Any valid value

Enable Bit Reversal and Byte Reversal

Any valid value

Enable Transceiver Dynamic Reconfiguration

Any valid value

�1

�2

�4

� 6(3)

�8

continued...

(2) Refer to JESD204B Intel FPGA IP User Guide for more details on maximum and minimum data rates for your target device.

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JESD204B IP Parameters M
Enable manual F configuration
F
N N'
S K Enable Scramble (SCR) CS CF High Density User Data Format (HD) Enable Error Code Correction (ECC_EN) Enable adaptation load soft IP

Values
�1 �2 � 3(4) �4 �8 � 16 � 32
� No � Yes only for the following configuration:
L=8, M=8, F=8, S=5, N'=12, N=12
� Auto calculated � Manual F configuration only allowed for the following
configuration: L=8, M=8, F=8, S=5, N'=12, N=12
Integer, range 12 � 16
� 16 � 12 only for the following configurations:
-- L=8, M=8, F=8, S=5, N=12 -- F=3, N'=12, N=12
Any valid value
Any valid value
Any valid value
Integer, range 0 � 3
0
�0 � 1 only for F=1
Any valid value
Any valid value Note: Applicable only for Intel Stratix 10 E-tile devices.

Table 8.

Device Part Number for the Generated Design Examples

Device Variant Intel Stratix 10 TX

Device Part Number Selected
Example: 1ST280EY2F55E1VG
Example: 1ST040EH1F35E1VG

Transceiver Tile Option
E-tile
H-tile E-tile

Targeted Development Device Part Number in

KIt

the Generated Design

Example

Intel Stratix 10 TX Signal Integrity development kit

1ST280EY2F55E1VG

Intel Stratix 10 GX FPGA development kit

1SG280HU1F50E2VG

Intel Stratix 10 TX Signal Integrity development kit

1ST280EY2F55E1VG continued...

(3) L=6 is only allowed when F=1 (4) M=3 is only allowed for L=6

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Device Variant Intel Stratix 10 MX
Intel Stratix 10 DX Intel Stratix 10 SX Intel Stratix 10 GX

Device Part Number Selected
Example: 1SM21BEU1F55E1VG
Example: 1SM21BHN1F53E1VG
Example: 1SD280PT1F55E1VG
Example: 1SX280HH1F55I1VG Example: 1SG280HH1F55E1VG

Transceiver Tile Option
E-tile
H-tile H-tile
E-tile
H-tile H-tile

Targeted Development Device Part Number in

KIt

the Generated Design

Example

Intel Stratix 10 TX Signal Integrity development kit

1ST280EY2F55E1VG

Intel Stratix 10 GX FPGA development kit

1SG280HU1F50E2VG

Intel Stratix 10 TX Signal Integrity development kit

1SG280HU1F50E2VG

Intel Stratix 10 TX Signal Integrity development kit

1ST280EY2F55E1VG

Intel Stratix 10 GX FPGA development kit

1SG280HU1F50E2VG

Intel Stratix 10 GX FPGA development kit

1SG280HU1F50E2VG

Related Information � JESD204B Intel FPGA IP User Guide � Customizing the Design Example on page 38

1.2.4. Presets

Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. Select the presets at the lower right window in the parameter editor.
The presets are applicable for JESD204B IP configurations that generate design examples. You can select one of the presets available for your target device to quickly generate a design example without having to set each parameter in the IP tab and verify that the specified parameters match the supported configurations. You can manually change any of the IP and example design parameters in the Platform Designer user interface after selecting a preset. However, you must ensure that your parameter selection falls within the supported configuration ranges detailed in Supported Configurations on page 17 for design example to generate successfully.

Note:

Selecting a preset overwrites any pre-existing parameter selections for the IP core under the IP tab.

Table 9.

Preset Settings
JESD204B IP Parameters

Wrapper Options Data Path JESD204B Subclass Data Rate PCS Option

Preset 1 JESD204B Example Design (LMF = 222, 6.144 Gbps) Both Base and PHY Duplex 1 6144 Mbps Enabled Hard PCS

Preset 2 JESD204B Example Design (LMF = 888, 6.144 Gbps)
Both Base and PHY
Duplex
1
6144 Mbps
Enabled Hard PCS continued...

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JESD204B IP Parameters
Bonding Mode PLL/CDR Reference Clock Frequency Enable Bit Reversal and Byte Reversal Enable Transceiver Dynamic Reconfiguration L M Enable manual F configuration F N N' S K Enable Scramble (SCR) CS CF High Density User Data Format (HD) Enable Error Code Correction (ECC_EN)

Preset 1 JESD204B Example Design (LMF = 222, 6.144 Gbps) Non-bonded 153.6 MHz No No 2 2 No 2 16 16 1 16 No 0 0 0 No

Preset 2 JESD204B Example Design (LMF = 888, 6.144 Gbps) Non-bonded 153.6 MHz No No 8 8 Yes 8 12 12 5 32 No 0 0 0 No

1.2.5. Functional Description
The design example consists of various components.
The following block diagram shows the design components and the top-level signals of the design example.

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Figure 9.

JESD204B Design Example Block Diagram
Top-Level RTL

Avalon streaming user data
Avalon streaming user data

Test Pattern Generator Test Pattern Checker

Avalon streaming

Assembler (Transport Layer)

Avalon streaming

Top-Level Platform Designer System

JESD204B Subsystem

TX serial data
sync_n Transceiver PLL Reference Clock (1)

Avalon streaming

Deassembler (Transport Layer)

Avalon streaming

RX serial data

Global reset Clock control

System console

Frame clock

Link clock Frame clock

Notes: 1: For L-tile and H-tile devices, this clock is RX Transceiver Reference Clock.
For E-tile devices, this clock is TX/RX Transceiver Reference Clock. 2: For L-tile and H-tile devices only.

Legend

ATX PLL (2)
SPI JTAG-Avalon Memory-Mapped
Bridge Core PLL

TX Transceiver PLL Reference Clock SPI signals
Core PLL Reference Clock

System Console control design example Simplex TX data path option Simplex RX data path option Duplex data path option

� Platform Designer system -- JESD204B subsystem -- JTAG to Avalon master bridge--For System Console Control design example only -- Parallel I/O (PIO) -- ATX PLL (Applicable only for Intel Stratix 10 L-tile and H-tile devices) -- Core PLL -- Serial Port Interface (SPI)--master module
� Test pattern generator (For duplex and simplex TX data path only) � Test pattern checker (For duplex and simplex RX data path only) � Assembler--TX transport layer (For duplex and simplex TX data path only) � Deassembler--RX transport layer (For duplex and simplex RX data path only)
1.2.5.1. Platform Designer System Component
The Platform Designer system instantiates the JESD204B IP core data path and supporting peripherals.

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Figure 10.

Platform Designer System for System Console Control Design Example for Intel Stratix 10 L-Tile and H-Tile Devices

Top Level Platform Designer System

Avalon Streaming 32-bit Data per Transceiver Lane
to/from Transport Layer

JESD204B Subsystem

JESD204B IP Core

Base Core

PHY (Transceivers)

IRQ

TX CSR

RX CSR

TX/RX Serial Data
Transceiver Analog/ Digital Resets Transceiver Reset Controller

Avalon Memory-Mapped Bridge

Transceiver Reset
Reset Sequencer

System Resets(1)

System Console

Core PLL Reset Core PLL

Link Clock Frame Clock

Legend: Avalon Memory-Mapped Interconnect
Avalon Streaming Interconnect Duplex or Simplex TX data path option Duplex or Simplex RX data path option

JTAGtoAvalon Memory-Mapped Bridge (2)

ATX PLL PIO(3)
SPI Master

TX Serial Clock/ Bonding Clock PIO Control
PIO Status
SPI Signal(4)

Notes:
1. System resets comprise the following resets: TX/RX JESD204B IP core CSR resets, TX/RX link resets, TX/RX frame resets.
2. This module is replaced by Avalon Memory-Mapped Bus Functional Module (BFM) in the simulation flow. 3. Parallel input/output modules. Parallel 32-bit output for control signals from JTAG to -Avalon master bridge to HDL components. Parallel
32-bit input for status signals from HDL components to JTAG to Avalon master. 4. If Generate 3-Wire SPI Module option is not selected, 4-wire SPI signal to external converter SPI interface. If Generate 3-Wire SPI Module
option is selected, 3-wire SPI signal to external converter SPI interface.

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Figure 11.

Platform Designer System for System Console Control Design Example for Intel Stratix 10 E-Tile Devices

Top Level Platform Designer System

Avalon Streaming 32-bit Data per Transceiver Lane
to/from Transport Layer

JESD204B Subsystem JESD204B IP Core Base Core

PHY (Transceivers)

TX/RX Serial Data

IRQ

TX CSR

RX CSR

Transceiver PLL (1)
E-Tile Transceiver Reset Controller

Avalon Memory-Mapped Bridge

Reset Sequencer

System Resets (2)

Core PLL Reset

Link Clock

System Console

Core PLL

Frame Clock

Legend: Avalon Memory-Mapped Interconnect
Avalon Streaming Interconnect Duplex or Simplex TX data path option Duplex or Simplex RX data path option

JTAGtoAvalon Memory-Mapped Bridge (3)

PIO (4) SPI Master

PIO Control PIO Status SPI Signal (5)

Notes:
1. E-tile devices have embedded transceiver PLL in the E-tile PHY block.
2. System resets comprise the following resets: TX/RX JESD204B IP core CSR resets, TX/RX link resets, TX/RX frame resets.
3. This module is replaced by Avalon Memory-Mapped Bus Functional Module (BFM) in the simulation flow. 4. Parallel input/output modules. Parallel 32-bit output for control signals from JTAG to -Avalon master bridge to HDL components. Parallel
32-bit input for status signals from HDL components to JTAG to Avalon master. 5. If Generate 3-Wire SPI Module option is not selected, 4-wire SPI signal to external converter SPI interface. If Generate 3-Wire SPI Module
option is selected, 3-wire SPI signal to external converter SPI interface.

The top level Platform Designer system instantiates the following modules: � Platform Designer system
-- JESD204B subsystem -- JTAG to Avalon master bridge -- Parallel I/O (PIO) -- ATX PLL (Applicable only for Intel Stratix 10 L-tile and H-tile devices) -- Core PLL -- Serial Port Interface (SPI)--master module

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The following are the key features of the top level Platform Designer system: � Supports System Console control design example � Supports 3 data path types:
-- Duplex--Both TX and RX data paths present -- Simplex TX--Only TX data path present -- Simplex RX--Only RX data path present � The JESD204B subsystem, parallel I/O and SPI master modules are connected to the JTAG to Avalon master bridge module via the Avalon Memory-Mapped (AvalonMM) interface. � JTAG to Avalon master bridge provides a link to the user via System Console. You can control the behavior of the design example via Tcl scripts executed in the System Console interface. � TX data path flow: -- Input: 32-bit per transceiver lane Avalon Streaming (Avalon-ST) input from
assembler (TX transport layer) -- Output: TX serial data � RX data path flow: -- Input: RX serial data from either external converter source or internal serial
loopback -- Output: 32-bit per transceiver lane Avalon Streaming (Avalon-ST) output to
deassembler (RX transport layer) � SPI master module links out to the SPI configuration interface of external
converters via a 3- or 4-wire SPI interconnect (depending on Generate 3-Wire SPI Module setting). � SPI master module handles the serial transfer of configuration data to the SPI interface on the converter end � The ATX PLL generates the serial clock for clocking the TX serial data (ATX PLL is applicable only for Intel Stratix 10 L-tile and H-tile devices) -- ATX PLL module generated for duplex and simplex TX data path only � The core PLL generates the following clocks for the system: -- Link clock -- Frame clock
Figure 12. Top Level Platform Designer Address Map for Intel Stratix 10 L-Tile and HTile Devices

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Figure 13. Top Level Platform Designer Address Map for Intel Stratix 10 E-Tile Devices

1.2.5.1.1. JESD204B Subsystem in Platform Designer
The JESD204B subsystem instantiates the following modules: � JESD204B Intel FPGA IP � Reset sequencer � Transceiver PHY reset controller � Avalon-MM bridge
JESD204B IP
The generated design example is a self-contained system with its own JESD204B IP core instantiation that is separate from the IP core that is generated from the IP tab. The JESD204B IP base core and PHY layer connect to System Console through the Avalon-MM interconnect. The JESD204B IP core uses three separate Avalon-MM ports: � Base core TX data path--For accessing the TX CSR � Base core RX data path--For accessing the RX CSR � PHY layer--For accessing the transceiver PHY CSR
The structure of the design example varies depending on the values of these JESD204B IP core parameters: � Data path:
-- Duplex--Both TX and RX data paths and CSR interfaces present -- TX only--Only TX data path and CSR interface present -- RX only--Only RX data path and CSR interface present
Reset Sequencer
The reset sequencer is a standard Platform Designer component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system: 1. Core PLL reset--resets the core PLL 2. Transceiver reset--resets the JESD204B IP core PHY module 3. TX/RX JESD204B IP core CSR reset--resets the TX/RX JESD204B IP core CSRs 4. TX/RX link reset--resets the TX/RX JESD204B IP core base module and transport
layer 5. TX/RX frame reset--resets the TX/RX transport layer, upstream and downstream
modules

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The reset sequencer has hard and soft reset options. The hard reset port connects to the global reset input pin in the top level design. The soft reset is activated via AvalonMM interface by TCL scripts (System Console control). When you assert a hard or soft reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

Figure 14.

Reset Sequence

Reset Type

Reset Sequencer Output

Global Reset

reset_in0

Core PLL

reset_out0

Core PLL Locked Transceiver PHY

reset1_dsrt_qual reset_out1

Qualifying Condition

TX Transceiver Ready reset2_dsrt_qual

JESD204B TX CSR

reset_out2

Qualifying Condition

TX Link Layer TX Frame Layer

reset_out3 reset_out4

RX Transceiver Ready reset5_dsrt_qual

JESD204B RX CSR

reset_out5

(1) Qualifying Condition

RX Link Layer

reset_out6

RX Frame Layer

reset_out7

Note:
(1) In the event that the RX transceiver ready (reset5_dsrt_qual) asserts before the TX transceiver ready (reset2_drst_qual), the RX CSR, RX link layer, and RX frame layer will remain in reset until TX CSR, TX link layer, and TX frame layer are out of reset.

Note:

For Intel Stratix 10 L-tile and H-tile devices, reset deassertion staggering of TX/RX analog and digital reset happens before the assertion of TX/RX ready. The reset staggering may incur long simulation time. You may observe the staggering of TX and RX reset through tx_analogreset_stat, tx_digitalreset_stat, rx_analogreset_stat, and rx_digitalreset_stat respectively.

Transceiver PHY Reset Controller
The transceiver PHY reset controller is a standard Platform Designer component in the IP Catalog standard library. This module takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module.
The transceiver PHY reset controller is applicable only for Intel Stratix 10 L-tile and Htile devices. On the other hand, the Intel Stratix 10 E-tile devices have a configurable reset controller embedded in the E-tile transceiver PHY module, which makes use of individual reset counters to control reset timing for the various reset outputs.

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Avalon� Memory-Mapped Bridge
All the Avalon memory-mapped submodules in the JESD204B subsystem are connected via Avalon memory-mapped interconnect to a single Avalon memorymapped bridge. This bridge is the single interface for Avalon memory-mapped communications into and out of the subsystem.
JESD204B Subsystem Address Map
Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window.
Figure 15. JESD204B Subsystem Address Map for Intel Stratix 10 L-Tile and H-Tile Devices

Figure 16. JESD204B Subsystem Address Map for Intel Stratix 10 E-Tile Devices

JTAG to Avalon Master Bridge
The JTAG to Avalon master bridge is a standard Platform Designer component in the IP Catalog standard library. This module provides a connection between a host system and the Platform Designer system via the respective physical interfaces; JTAG on the host system end and Avalon memory-mapped on the Platform Designer system end. Host systems can initiate Avalon memory-mapped transactions by sending encoded streams of bytes via JTAG interface. The module supports reads and writes, but not burst transactions.
Related Information Platform Designer System Component on page 21
1.2.5.1.2. Parallel I/O
Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon master (JTAG to Avalon master bridge). There are two sets of 32-bit PIO registers: � Status registers--input from the HDL components to the Avalon master � Control registers--output from the Avalon master to the HDL components
The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.

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Table 10.

Signal Connectivity for Status Registers

Bit

Signal

Core PLL locked

TX transceiver ready (for duplex and simplex TX data path only)

RX transceiver ready (for duplex and simplex RX data path only)

Test pattern checker data error (for duplex and simplex RX data path only)

TX link error (for duplex and simplex TX data path only)

RX link error (for duplex and simplex RX data path only)

All TX PMA ready (for duplex and simplex TX data path only)

All RX PMA ready (for duplex and simplex RX data path only)

0: Indicates H-tile or L-tile

1: Indicates E-tile

Table 11.

Signal Connectivity for Control Registers

Bit

Signal

TX to RX serial loopback path enable (for Intel Stratix 10 L-tile and H-tile duplex

data path only)

Global reset

SYSREF

1.2.5.1.3. ATX PLL

Note:

This module is only available in the Intel Stratix 10 L-tile or H-tile design example when the duplex or simplex TX data path option is selected.

The ATX PLL is a standard Platform Designer component in the IP Catalog standard library. This module supplies a low-jitter serial clock to the transceiver PHY module. The reference clock input to the ATX PLL comes from an external source.

For simplex TX variant, the frequency selection in the PLL/CDR Reference Clock Frequency drop-down list in the JESD204B IP parameter editor is disabled. The design example generates the ATX PLL with the reference clock frequency of either:
� Hard PCS: data_rate/20
� Soft PCS: data_rate/40

Refer to Changing the Data Rate or Reference Clock Frequency on page 39 for more information about modifying the ATX PLL reference clock frequency to suit your application.
For duplex variant, the ATX PLL and CDR share the same reference clock pin. You must select the frequency from the PLL/CDR Reference Clock Frequency dropdown list in the IP parameter editor.
For the ATX PLL reference clock frequencies supported range, refer to the Intel Stratix 10 Device Datasheet.

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1.2.5.1.4. Core PLL
The core PLL module generates the clocks for the FPGA core fabric. An IOPLL module is instantiated as core PLL.

The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:
� Link clock
� Frame clock

Table 12. Core PLL Ouputs

Link Clock

Clock

Formula Serial data rate/40

Frame Clock

Derived based on settings; refer to Table 13 on page 30.

Description
The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer.
The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric.

Note:

For the frame clock, when the F parameter is 1, 2 or 3, the resulting frame clock frequency easily exceeds the capability of the core PLL to generate and close timing. The top level RTL file, (altera_jesd204_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). F = 3 uses a constant division factor of 2. This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.
For JESD204B IP design examples, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2.
These examples show how to derive the frame clock frequency:
Example 1: The actual frame clock for a serial data rate of 10 Gbps and F = 1 is:

(10000/(10 � 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHz

Example 2: The actual frame clock for a serial data rate of 6 Gbps and F = 3 is:

(6000/(10 � 3)) / 2 = 200 / 2 = 100 MHz

Frame Clock and Link Clock Relationship
The frame clock and link clock are synchronous. For the derived F mode, the ratio of link_clk period to frame_clk period is given by this formula:
link_clk period to frame_clk period ratio = 32xL/(MxSxN')

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Table 13.

fTXframe and fRXframe for Different F Parameter Settings
� fTXlink is the TX link clock frequency � fRXlink is the RX link clock frequency

F Parameter 1

fTXframe(txframe_clk frequency) fTXlinkx(4/F1_FRAMECLK_DIV)

fRXframe(rxframe_clk frequency) fRXlinkx(4/F1_FRAMECLK_DIV)

fTXlinkx(2/F2_FRAMECLK_DIV)

fRXlinkx(2/F2_FRAMECLK_DIV)

fTXlinkx(2/3)

fTXlink

fTXlink/2

fRXlinkx(2/3) fRXlink fRXlink/2

Note:

The IOPLL is generated with the Use Nondedicated Feedback Path option being disabled (default setting). You can turn on the Use Nondedicated Feedback Path option in the IP parameter editor to utilize the clock resources efficiently after the design example is successfully generated. Refer to the Clock Feedback Modes section of Intel Stratix 10 Clocking and PLL User Guide for more information about this option.

Related Information Clock Feedback Modes section of the Intel Stratix 10 Clocking and PLL User Guide

1.2.5.1.5. SPI Master
The SPI master module is a standard Platform Designer component in the IP Catalog standard library. This module uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, external clock modules) via a structured register space inside the converter device. The SPI master has an Avalon-MM interface that connects to the Avalon master (JTAG to Avalon master bridge) via the Avalon-MM interconnect and can receive configuration instructions from the Avalon master.
This module is configured to a 4-wire, 24-bit width interface. If the Generate 3-Wire SPI Module option is selected, an additional module is instantiated to convert the 4wire output of the SPI master to 3-wire.
For more details on the SPI master module, refer to the JESD204B Intel FPGA IP User Guide.
Related Information
JESD204B Intel FPGA IP User Guide

1.2.5.2. Transport Layer
The transport layer in the design example consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is instantiated in the top level RTL file, not in the Platform Designer project.

Note:

When the simplex TX data path option is selected, only the assembler is instantiated in the design example. When the simplex RX data path option is selected, only the deassembler is instantiated in the design example. When the duplex data path option is selected, both assembler and deassembler is instantiated in the design example.

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The transport layer provides the following services to the application layer (AL) and the data link layer (DLL):
� Assembler at the TX path:
-- Maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
-- Reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.
� Deassembler at the RX path:
-- Maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
-- Reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.
The transport layer has many customization options and you can modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core.
For more details on the implementation of the transport layer in RTL and customization options, refer to the JESD204B Intel FPGA IP User Guide.
Related Information
JESD204B Intel FPGA IP User Guide

1.2.5.3. Test Pattern Generator

Note:

This module is only available in the design example when the duplex or simplex TX data path option is selected.

The test pattern generator generates either a parallel PRBS, alternate checkerboard, or ramp wave, and sends it to the transport layer during test mode. The test pattern generator is implemented in the top level RTL file, not in the Platform Designer project.
Related Information
JESD204B Intel FPGA IP User Guide

1.2.5.4. Test Pattern Checker

Note:

This module is only available in the design example when the duplex or simplex RX data path option is selected.

The test pattern checker checks either a parallel PRBS, alternate checkerboard, or ramp wave from the transport layer during test mode and outputs an error flag if there are any data mismatches. The test pattern checker is implemented in the top level RTL file, not in the Platform Designer project.
Related Information
JESD204B Intel FPGA IP User Guide

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1.2.5.5. Clocking Scheme

The main reference clocks for the design example are refclk_core and refclk_xcvr. These clocks must be supplied from a single external source (i.e refclk_core and refclk_xcvr must be synchronous to one another). The refclk_core is the reference clock for the core PLL and the refclk_xcvr is the reference clock for the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from refclk_core.

The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon memory-mapped interfaces of Platform Designer components.

Table 14. System Clocking for the Design Example

Clock

Description

Source

refclk_core

Reference clock for the core PLL

External

refclk_xcvr

Reference clock for the ATX PLL (Intel Stratix 10 L-tile and H-tile devices), TX PLL (Intel Stratix 10 E-tile devices), and RX transceiver PHY

External

link_clk

Link layer clock

refclk_core

frame_clk

Frame layer clock

refclk_core

mgmt_clk

Control plane clock

External

Modules Clocked
Core PLL
ATX PLL (Intel Stratix 10 L-tile and H-tile devices), TX PLL (Intel Stratix 10 E-tile devices), and RX transceiver PHY
JESD204B IP core link layer, transport layer link interface
Transport layer, test pattern generator and checker, downstream modules
Avalon memory-mapped interfaces

1.2.6. Simulation

Execute the simulation by running the relevant simulation run scripts in the supported simulator environment. The following table shows the simulators supported along with the relevant run scripts.

Table 15. Supported Simulators

Simulators

Simulation Directory

Riviera-PRO

/testbench/aldec/

ModelSim

/testbench/mentor/

VCS

/testbench/synopsys/vcs/

VCS MX

/testbench/synopsys/vcsmx/

Xcelium Parallel

/testbench/xcelium/

Run Script run_tb_top.tcl run_tb_top.tcl run_tb_top.sh run_tb_top.sh run_tb_top.sh

The design generates the simulation results which include the transcript or log files in the relevant simulation directory.

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1.2.6.1. Testbench
The simulation design-under-test (DUT) is the generated design example which includes a synthesizable pattern generator and checker. The figures below show the testbench block diagram for simplex and duplex options.
Figure 17. Simulation Testbench Block Diagram (Simplex TX or RX)

TX link error

DUT (Simplex TX) Test Pattern Generator

Assembler (Transport Layer)

Platform Designer System JESD204B IP Core
(Simplex TX)

Read/Write instructions

BFM

Testbench

DUT (Simplex RX)

Pattern mismatch error
Avalon-ST data valid RX link error Read/Write instructions

Test Pattern Checker

Deassembler (Transport Layer)

Serial Data
Platform Designer System JESD204B IP Core
(Simplex RX)

BFM

Note:

Both simplex TX and simplex RX design examples generate the same testbench. The testbench instantiates two DUTs: one simplex TX DUT, one simplex RX DUT. The TX serial data output of the simplex TX DUT is connected to the RX serial data input of the simplex RX DUT. The testbench issues separate Avalon Memory-Mapped (AvalonMM) read/write instructions to the simplex TX and simplex RX DUTs respectively.

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Figure 18. Simulation Testbench Block Diagram (Duplex)

DUT (Duplex)

Test Pattern Generator

Assembler (Transport Layer)

Testbench

Pattern mismatch error
Avalon-ST data valid TX link error RX link error

Test Pattern Checker

Deassembler (Transport Layer)

Read/Write instructions

Platform Designer System JESD204B IP Core (Duplex)
BFM

The simulation flow replaces the JTAG to Avalon master bridge module in the Platform Designer system of the System Console Control design example with the Avalon-MM master bus functional model (BFM). This BFM enables a testbench to send Avalon-MM read/write commands to the design example registers to mimic the functionality of System Console.

The testbench provided in the simulation flow (/testbench/models/tb_top.sv) executes the following steps: 1. Reset DUT. 2. Initialize BFM. 3. Execute Avalon-MM commands to initialize the DUT in the following mode:
� Internal serial loopback mode (for duplex option only) � Pattern generator/checker set to PRBS pattern 4. Wait for DUT to initialize to user mode. 5. Report JESD204B link status.

When simulation ends, the following messages are shown at end.

Table 16. Simulation Messages and Description

Message Pattern Checker(s): Data error(s) found!

Description Pattern mismatch errors found on the pattern checker

Pattern Checker(s): OK!

No errors found on the pattern checker

Pattern Checker(s): No valid data found! JESD204B Tx Core(s): Tx link error(s) found!

No valid data received by pattern checker Link errors reported by JESD204B IP TX

JESD204B Tx Core(s): OK!

No link errors reported by JESD204B IP TX

JESD204B Rx Core(s): Rx link error(s) found!

Link errors reported by JESD204B IP RX

continued...

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Message JESD204B Rx Core(s): OK! TESTBENCH_PASSED: SIM PASSED! TESTBENCH_FAILED: SIM FAILED!

Description No link errors reported by JESD204B IP RX Overall simulation passed Overall simulation failed

1.2.7. Design Example Files

There are two flows for the design example: simulation and synthesis.

Table 17. Design Example Flows and Directory

Design Example Flow

Directory

Simulation

<your project>/ed_sim

Synthesis

<your project>/ed_synth

The following tables list the important folders and files for simulation and synthesis.

Table 18. Design Example Files for Simulation

File Type

File/Folder

Run script files

/testbench/aldec/run_tb_top.tcl /testbench/mentor/run_tb_top.tcl

/testbench/synopsys/vcs/run_tb_top.sh

/testbench/synopsys/vcsmx/run_tb_top.sh

/testbench/xcelium/run_tb_top.sh

Source files

/testbench/models/altjesd_ed_qsys_<data path>.qsys

/testbench/models/altjesd_ss_<data path>.qsys

/testbench/models/ip/

/testbench/models/altera_jesd204_ed_<data path>.sv /testbench/models/tb_top.sv /testbench/spi_mosi_oe.v /testbench/switch_debouncer.v /testbench/pattern/

/testbench/transport_layer

Description
TCL run script for Riviera-PRO simulator
TCL run script for ModelSim simulator
Shell run script for VCS simulator
Shell run script for VCS MX simulator
Shell run script for Xcelium simulator
Top level Platform Designer system project
JESD204B subsystem Platform Designer system project
IP folder containing instantiated IP modules
Top level HDL
Top level testbench
Output buffer HDL
Switch debouncer HDL
Folder containing the test pattern generator and checker HDL
Folder containing assembler and deassembler HDL.

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Table 19. Design Example Files for Synthesis

File Type Intel Quartus Prime project files
Source files

File/Folder altera_jesd204_ed_<data path>.qpf altera_jesd204_ed_<data path>.qsf altera_jesd204_ed_<data path>.sv

altera_jesd204_ed_<data path>.sdc

transport_layer/ pattern/ spi_mosi_oe.v switch_debouncer.v altjesd_ed_qsys_<data path>.qsys altjesd_ss_<data path>.qsys

Description
Intel Quartus Prime project file
Intel Quartus Prime settings file
Top level HDL
Synopsys* Design Constraints (SDC) file containing all timing/placement constraints
Folder containing assembler and deassembler HDL
Folder containing the test pattern generator and checker HDL
Output buffer HDL
Switch debouncer HDL
Top level Platform Designer system project
JESD204B subsystem Platform Designer system project

1.2.8. Registers

Refer to the JESD204B RX Address Map and Register Definitions and JESD204B TX Address Map and Register Definitions for the list of registers.

Note:

The following status bits are not applicable to Intel Stratix 10 devices: � csr_pcfifo_full_err � csr_pcfifo_empty_err

Related Information � Intel FPGA JESD204B RX Address Map and Register Definitions � Intel FPGA JESD204B TX Address Map and Register Definitions

1.2.9. Signals

Table 20. System Interface Signals

Signal Clocks and Resets refclk_core

Clock Domain Direction

Description

Input Reference clock for FPGA core modules.

refclk_xcvr

Input Reference clock for transceiver PHY.

mgmt_clk global_rst_n

-- mgmt_clk

Input Input

Reference clock for all peripherals connected via Avalon-MM interconnect.
Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk.

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Signal Serial Data rx_serial_data[LINK*L-1:0]
tx_serial_data[LINK*L-1:0]

Clock Domain Direction

Description

refclk_xcvr refclk_xcvr

Input Output

Differential high speed serial input data. The clock is recovered from the serial data stream.
Differential high speed serial output data. The clock is embedded in the serial data stream.

Signal JESD204B sysref_out sync_n_out
tx_link_error rx_link_error

Clock Domain Direction

Description

mgmt_clk link_clk
link_clk link_clk

Output Output
Output Output

SYSREF signal for JESD204B Subclass 1 implementation.
Indicates a SYNC_N from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting.
Error interrupt from JESD204B IP core indicating TX link error
Error interrupt from JESD204B IP core indicating RX link error

Signal

Clock Domain Direction

Description

Avalon- ST User Data

avst_usr_din[LINK*TL_DATA_BUS frame_clk _WIDTH-1:0]

Input

TX data from the Avalon-ST source interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
� If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME
� If F = 2, TL_DATA_BUS_WIDTH = F2_FRAMECLK_DIV*8*2*L*N/N_PRIME
� If F = 3, TL_DATA_BUS_WIDTH = 2*8*3*L*N/ N_PRIME
� If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/ N_PRIME
� If F = 8, TL_DATA_BUS_WIDTH = 8*8*L*N/ N_PRIME

avst_usr_din_valid[LINK-1:0] frame_clk

Input

Indicates whether the data from the Avalon-ST source interface to the transport layer is valid or invalid.
� 0--data is invalid
� 1--data is valid

avst_usr_din_ready[LINK-1:0] frame_clk

Output

Indicates that the transport layer is ready to accept data from the Avalon-ST source interface. � 0--transport layer is not ready to receive data � 1--transport layer is ready to receive data

avst_usr_dout[LINK*TL_DATA_BU frame_clk S_WIDTH-1:0]

Output

RX data to the Avalon-ST sink interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
continued...

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Signal

Clock Domain Direction

Description

� If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME
� If F = 2, TL_DATA_BUS_WIDTH = F2_FRAMECLK_DIV*8*2*L*N/N_PRIME
� If F = 3, TL_DATA_BUS_WIDTH = 2*8*3*L*N/ N_PRIME
� If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/ N_PRIME
� If F = 8, TL_DATA_BUS_WIDTH = 8*8*L*N/ N_PRIME

avst_usr_dout_valid[LINK-1:0] frame_clk

Output

Indicates whether the data from the transport layer to the Avalon-ST sink interface is valid or invalid.
� 0--data is invalid
� 1--data is valid

avst_usr_dout_ready[LINK-1:0] frame_clk

Input

Indicates that the Avalon-ST sink interface is ready to accept data from the transport layer.
� 0--Avalon-ST sink interface is not ready to receive data
� 1--Avalon-ST sink interface is ready to receive data

avst_patchk_data_error [LINK-1:0]

frame_clk

Output

Output signal from pattern checker indicating a pattern check error.

Signal SPI spi_MISO (5) spi_MOSI(5)
spi_SDIO(6)
spi_SCLK
spi_SS_n[2:0]

Clock Domain Direction

Description

spi_SCLK spi_SCLK spi_SCLK mgmt_clk spi_SCLK

Input Output
Input/ Output Output
Output

Input data from external slave to the master.
Output data from the master to the external slaves.
Output data from the master to external slave. Input data from external slave to master
Clock driven by the master to slaves, to synchronize the data bits.
Active low select signal driven by the master to individual slaves, to select the target slave. Defaults to 3 bits.

1.2.10. Customizing the Design Example
Use the following guidelines to customize the design example post-generation. Related Information AN804: Implementing ADC-Stratix 10 Multi-Link Design with JESD204B RX IP Core

(5) When Generate 3-Wire SPI Module option is not enabled. (6) When Generate 3-Wire SPI Module option enabled.
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1.2.10.1. Modifying the JESD204B IP Core Parameters
The Platform Designer tool allows only a limited set of design examples to be generated based on the JESD204B IP core parameters selected.
Perform the following instructions to modify the JESD204B IP core parameters postgeneration:
1. Open the generated design example project in the Intel Quartus Prime software.
2. Open the altjesd_ss_<data path>.qsys system in Platform Designer.
3. In the System Contents tab, double-click the altjesd_<data path> module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core.
4. Modify the parameters of the JESD204B IP core module as per your system specifications. When you are done, save the Platform Designer system (File Save).
Note: The JESD204B IP core and transport layer imposes certain limits on the values that can be entered as parameters. Refer to the JESD204B Intel FPGA IP User Guide for a complete listing of the legal parameter values.
5. Click the Generate HDL to generate the HDL files needed for Intel Quartus Prime compilation.
6. After the HDL generation is completed, click the Finish to save your settings and exit Platform Designer.
7. You have to manually change the system parameters in the top level RTL file to match the parameters that you set in the Platform Designer project, if applicable. Open the top level RTL file (altera_jesd204_ed_<data path>.sv) in any text editor of your choice.
8. Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Platform Designer project, if applicable.
9. Save the file and compile the design in Intel Quartus Prime software as per the instructions in the Compiling and Testing the Design on page 8.
Related Information
JESD204B Intel FPGA IP User Guide
1.2.10.2. Changing the Data Rate or Reference Clock Frequency
When changing the data rate or reference clock frequency, you must consider the following:
� The relationships between the serial data rate, link clock, and frame clock as described in the JESD204B Intel FPGA IP User Guide.
� Change the PLL output clock settings according to Table 13 on page 30.
� Take note when changing the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters in the top level RTL file altera_jesd204_ed_<data path>.sv for cases when F=1 or F=2. These parameters further divide-down the frame clock frequency requirement so the resulting clock frequency is within bounds of timing closure for the FPGA core fabric.

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The frame clock and the link clock for the following cases share the same frequency:
� F=1--the default parameter value for F1_FRAMECLK_DIV=4
� F=2--the default parameter value for F2_FRAMECLK_DIV=2
� F=4
Perform the following instructions to modify the JESD204B IP core parameters postgeneration:
1. Open the generated design example project in the Intel Quartus Prime software.
2. Open the top level altjesd_ed_qsys_<data path>.qsys in the Platform Designer.
3. In the System Contents tab, right-click the altjesd_ss_<data path> module and select Drill into Subsystem. This opens the altjesd_ss_<data path>.qsys Platform Designer subsystem.
4. Double-click the altjesd_<data path> module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core.
5. Change the Data rate and PLL/CDR Reference Clock Frequency values to meet your system requirements.
6. Modify the clock frequency values of the refclk_xcvr, link_clk, frame_clk and mgmt_clk clock source modules as necessary to meet your system requirements. Double-click the clock source module to bring up the parameters editor and change the Clock frequency value as necessary. Ensure that the values match the clock frequency values that you have entered for the other modules above.
7. Navigate back to the top level altjesd_ed_qsys_<data path>.qsys hierarchy.
8. For Intel Stratix 10 L-tile and H-tile devices, double-click the xcvr_atx_pll_0 module to bring up the parameters editor for the ATX PLL module. For Intel Stratix 10 E-tile devices, skip to 10 on page 40.
This is the module that generates the serial clock for the TX transceiver PHY.
9. Under the PLL subtab, locate the Output Frequency group and change the PLL output frequency and PLL integer reference clock frequency values to meet your system requirements.
The PLL output frequency is half of the PLL output data rate. Ensure that the data rate and PLL reference clock values match the parameters that you entered into the JESD204B IP core module.
10. Double-click the core_pll module to bring up the parameters editor for the core PLL module.
This is the module that generates the link_clk and frame_clk clocks that clock the core components.
11. Under the PLL subtab, change the Reference Clock Frequency value in the General group to meet your system requirements.
Ensure that the reference clock frequency value matches the ones set for the JESD204B IP core and ATX PLL (Intel Stratix 10 L-tile and H-tile devices) modules.
12. Change the outclk0 group settings (which correspond to the link_clk) and outclk1 group settings (which correspond to the frame_clk) where necessary.
Ensure that the link_clk and frame_clk values satisfy the frequency requirements as described in the JESD204B IP Core User Guide.

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13. Modify the clock frequency values of the refclk_xcvr, refclk_core, link_clk, frame_clk and mgmt_clk clock source modules as necessary to meet your system requirements. Double-click the clock source module to bring up the parameters editor and change the Clock frequency value as necessary. Ensure that the values match the clock frequency values that you have entered for the other modules in earlier steps.
14. Click the Generate HDL button to generate the HDL files needed for Intel Quartus Prime compilation.
15. After the HDL generation is completed, click the Finish to save your Platform Designer settings and exit the Platform Designer window.
16. If the frame_clk settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values are changed, change the parameters in the top level design file, altera_jesd204_ed_<data path>.sv.
17. Modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect your new clock frequency values, if applicable. The following constraints should be modified:
create_clock -name refclk_xcvr -period <clock period value in ns> [get_nodes refclk_xcvr] create_clock -name mgmt_clk -period <clock period value in ns> [get_nodes mgmt_clk]
18. Save the file and compile the design in Intel Quartus Prime software as per the instructions in the Compiling and Testing the Design on page 8.
Related Information
JESD204B Intel FPGA IP User Guide

1.3. JESD204B Intel Stratix 10 FPGA IP Design Example User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

Intel Quartus Prime Version

IP Core Version

User Guide

20.4

19.2.0

JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

20.2

19.2.0

JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

18.1

JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

18.0

JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

17.1

Intel FPGA JESD204B Design Example User Guide for Intel Stratix 10 Devices

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1.4. Document Revision History for the JESD204B Intel Stratix 10 FPGA IP Design Example User Guide

Document Version 2021.06.25
2021.01.07 2020.10.05 2020.09.10

Intel Quartus Prime Version
21.2
20.4 20.3 20.2

IP Version

Changes

19.2.0
19.2.0 19.2.0 19.2.0

� Removed support for NCSim in the following tables and topic:
-- Table: Directory and File Description
-- Table: Supported Simulators
-- Table: Design Example Files for Simulation
-- Simulating the Design
� Removed incorrectly included L-tile support for Intel Stratix 10 GX FPGA Development Kit board.
� Renamed table title Intel Stratix 10 GX FPGA Development Kit Board Connectivity for L-Tile and H-Tile Devices to Intel Stratix 10 GX FPGA Development Kit Board Connectivity for H-Tile Devices.
� Updated the table description in Figure: Intel Stratix 10 GX FPGA Development Kit Clock Control GUI Setting.
� Updated Hardware and Software Requirements.
� Updated the Compiling and Testing the Design and Board Connectivity sections with the latest information for design examples with bonded and non-bonded mode configurations.
� Removed the note in the description for Bonding Mode in Table: Supported JESD204B IP Core Parameter Configurations.
Updated the change in board information for Intel Stratix 10 E-tile devices in the Compiling and Testing the Design and Board Connectivity sections.
� Added design example for Intel Stratix 10 E-tile devices. The existing design example supports Intel Stratix 10 L-tile and H-tile devices. The Intel Stratix 10 E-tile design example uses the Intel Stratix 10 TX Transceiver Signal Integrity Development Kit.
� Updated the Compiling and Testing the Design, Board Connectivity, and Hardware and Software Requirements to include information about the Intel Stratix 10 TX Transceiver Signal Integrity Development Kit.
� Added the following new procedures for Intel Stratix 10 E-tile devices in the Hardware Test for System Console Control Design Example section:
-- det_etile
-- run_load_PMA_configuration
-- load_adaptation_PMA_configuration
� Added the following parameters in the Supported Configurations section:
-- Transceiver Tile
-- Enable Transceiver Dynamic Reconfiguration
-- Enable adaptation load soft IP
� Updated the block diagram in the Functional Description section to include information about the Intel Stratix 10 E-tile design example.
continued...

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Document Version

Intel Quartus Prime Version

IP Version

Changes

� Added Platform Designer system block diagram and top level Platform Designer address map in the Platform Designer System Component section for the Intel Stratix 10 E-tile design example.
� Added information about the Intel Stratix 10 E-tile devices in the Transceiver PHY Reset Controller, Parallel I/O, and Changing the Data Rate or Reference Clock Frequency sections.
� Added a note in the ATX PLL and Clocking Scheme sections that ATX PLL is not applicable for Intel Stratix 10 E-tile devices.

Document Version 2018.12.10
2018.08.10

Intel Quartus Prime Version
18.1
18.0

Changes
� Updated the Enable manual F configuration, F, and N' parameter description in the Supported Configurations section to add information for F=3 configuration.
� Added an example for calculating frame clock frequency when F=3 for actual frame clock for a serial data rate of 6 Gbps in the Core PLL section.
� Updated the fTXframe and fRXframe for Different F Parameter Settings table in the Core PLL section to include a row for F=3.
� Updated the descriptions for avst_usr_din[LINK*TL_DATA_BUS_WIDTH-1:0] and avst_usr_dout[LINK*TL_DATA_BUS_WIDTH-1:0] signals in the System Interface Signals table to include information for F=3.
� Added a reminder note in the Compiling and Testing the Design section to configure the VID assignments if you are using development boards other than the Intel Stratix 10 GX FPGA development board and the Intel Stratix 10 GX Transceiver Signal Integrity development board.
� Edited the duplex variant description in the ATX PLL section. For duplex variant, the ATX PLL and CDR share the same reference clock pin.
� Edited the description for the Generate HDL Parameter for Synthesis parameter in the Design Example Parameters section.
� Added a note in the Reset Sequencer section that for Intel Stratix 10 devices, reset deassertion staggering of TX/RX analog and digital reset happens before the assertion of TX/RX ready.
� Changed the target development board for the design example from Signal Integrity (SI) development board to FPGA development board.
� Updated the Intel Stratix 10 FPGA Development Kit Board Connectivity table to include the FPGA development board information.
� Updated the Clock Control GUI Setting figure. � Shortened the following Platform Designer file names due to Windows
limitation: -- altera_jesd204_ed_qsys_<data path>.qsys to
altjesd_ed_qsys_<data path>.qsys -- altera_jesd204_subsystem_<data path>.qsys to altjesd_ss_<data
path>.qsys � Edited the Platform Designer System for System Console Control
Design Example figure. -- Removed signal connections that indicated support for dynamic
transceiver reconfiguration. The design example does not support dynamic transceiver reconfiguration. -- Added that the output from ATX PLL could either be TX serial clock or TX bonding clock. -- Removed "Core PLL reset" and "JESD204B IP core SerDes PHY reset" from Note 1. These resets are connected internally.

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Date November 2017
May 2017
December 2016

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Version 2017.11.06
2017.05.08
2016.12.09

Changes
� Added information about simplex and duplex ATX reference clock frequencies.
� Defined (altera_jesd204_ed_<data path>.sv) as the top level RTL file in Core PLL.
� Added Frame Clock and Link Clock Relationship subsection. � Defined top level RTL file in Changing the Data Rate or Reference Clock
Frequency. � Updated SDC constraint to be modified in Changing the Data Rate or
Reference Clock Frequency. � Added get_master_index procedure in Procedures in the main.tcl
System Console Script table. � Updated document title. � Updated instances of Qsys to Platform Designer.
� Added new directories and descriptions in Directory Structure. � Updated steps in Generating the Design. � Updated design example parameters and descriptions Design Example
Parameters. � Added new simulators in Simulating the Design. � Updated steps in Compiling and Testing the Design. � Added Hardware Test for System Console Control Design Example. � Updated the supported configuration in Supported Configurations. � Updated preset settings. � Updated JESD204B Design Example Block Diagram. � Updated descriptions and figures in Platform Designer System
Components. � Updated System Clocking for the Design Example. � Added tx_link_error, rx_link_error, and spi_SDIO signals in
System Interface Signals. � Updated Testbench.
Initial release.

JESD204B Intel Stratix 10 FPGA IP Design Example User Guide 44

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