Intel Stratix 10 SX SoC Development Kit User Guide Stratix 10 SX SoC Development

Intel Stratix 10 SX SoC Development Kit User Guide

The Intel Stratix 10 SX SoC Development Kit offers a quick and simple approach for developing custom Arm processor-based SoC designs. The Intel Stratix 10 SX SoCs offer full software compatibility with previous generation SoCs, a broad ecosystem of Arm software and tools, and the enhanced FPGA and digital signal processing (DSP) hardware design flow.

Stratix 10, Stratix 10 SoC, Stratix 10 SX SoC, Stratix 10 SX SoC Development Kit, Stratix 10 SX SoC Development Kit User Guide, Stratix 10 SoC Development Kit User Guide

Intel Corporation

Intel Stratix 10 SX SoC Development Kit User Guide

Output. GXBR4M TX CH1N. PIN N3. PCIE TX P13. Output. GXBR4M TX CH1P. PIN K6. PCIE RX N13. Input. GXBR4M RX CH1N. PIN K5. PCIE RX P13. Input.

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Stratix 10 SX SoC Development Kit User Guide

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Intel® Stratix® 10 SX SoC Development Kit User Guide

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Contents
Contents
1. Overview........................................................................................................................ 4 1.1. General Development Kit Description........................................................................4 1.2. Recommended Operating Conditions........................................................................ 5 1.3. Handling the Development Kit................................................................................. 5
2. Getting Started............................................................................................................... 6 2.1. Installing Quartus Prime Software............................................................................6 2.2. Installing the Intel FPGA Download Cable..................................................................7 2.3. Installing the Intel SoC Embedded Development Suite (EDS).......................................7 2.4. Installing the Intel Stratix 10 SX SoC Development Kit Package................................... 7
3. Development Kit Setup................................................................................................... 9 3.1. Inspect the Development Kit................................................................................... 9 3.2. Default Setup of the Development Kit.......................................................................9 3.3. Intel MAX 10 System Controller Updates................................................................. 10
4. Development Kit Components....................................................................................... 12 4.1. Development Kit Feature Summary........................................................................ 12 4.2. Board Components...............................................................................................14 4.3. Intel Stratix 10 SoC Device Overview..................................................................... 17 4.4. Intel MAX 10 System Controller Overview............................................................... 22 4.5. FPGA Configuration.............................................................................................. 24 4.6. General User Input/Output....................................................................................24 4.7. Connectors and Interfaces.................................................................................... 25 4.7.1. PCIe Slot................................................................................................ 25 4.7.2. ZQSFP+..................................................................................................28 4.7.3. SFP+......................................................................................................29 4.7.4. HDMI..................................................................................................... 29 4.7.5. SDI Port................................................................................................. 30 4.7.6. MXP....................................................................................................... 30 4.7.7. Intel FPGA Download Cable Direct Port (Debug Port).....................................31 4.7.8. FMC+ A/B Slot.........................................................................................32 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins).........................................................38 4.7.10. LMK05028 Jitter Attenuator..................................................................... 45 4.7.11. FPGA-IOMAX10 Interface........................................................................ 46 4.8. Daughter Cards................................................................................................... 49 4.8.1. HPS IO-48 OOBE Daughter Card................................................................ 49 4.8.2. HPS IO-48 NAND Flash Daughter Card........................................................ 59 4.8.3. HPS Boot Flash Card.................................................................................67 4.9. System Memory...................................................................................................72 4.9.1. FPGA Memory (DDR4 SO-DIMM)................................................................ 72 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4 )............................................. 76 4.9.3. HPS I2C Interface.....................................................................................81 4.10. System Power....................................................................................................82 4.10.1. Power Supply Options............................................................................. 82 4.10.2. Power Sequence.....................................................................................83 4.10.3. Power Distribution Network..................................................................... 84

Intel® Stratix® 10 SX SoC Development Kit User Guide 2

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Contents
5. Board Test System........................................................................................................ 86 5.1. Preparing the Board............................................................................................. 87 5.2. Running the BTS..................................................................................................87 5.3. Using the BTS..................................................................................................... 87 5.3.1. The Configure Menu................................................................................. 87 5.3.2. The GPIO Tab.......................................................................................... 89 5.3.3. The QSFP/SFP Tab....................................................................................90 5.3.4. The PCIE Tab...........................................................................................93 5.3.5. The MXP Tab........................................................................................... 96 5.3.6. The FMCA Tab..........................................................................................99 5.3.7. The FMCB Tab........................................................................................105 5.3.8. The DDR4 Tab........................................................................................110 5.3.9. Power Monitor........................................................................................111 5.3.10. The Clock Control................................................................................. 113
A. Additional Information............................................................................................... 115 A.1. Modify the Intel Stratix 10 SX SoC Development Kit to use a battery for the BBRAM... 115 A.2. Modify the Intel Stratix 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project..................116 A.3. Safety and Regulatory Information....................................................................... 117 A.3.1. Safety Warnings.....................................................................................117 A.3.2. Safety Cautions..................................................................................... 119 A.4. Compliance Information......................................................................................121 A.4.1. Compliance and Conformity Statements.................................................... 121
B. Revision History..........................................................................................................122 B.1. Revision History ................................................................................................122

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1. Overview

This document describes the features of the Intel® Stratix® 10 SoC development kit, including detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

This development board comes in two different versions as shown in the table below.

Table 1.

Development Kit Version Information

Development Kit Version Intel Stratix 10 SX SoC L-Tile
Intel Stratix 10 SX SoC H-Tile

Ordering Code DK-SOC-1SSX-L-A DK-SOC-1SSX-L-D DK-SOC-1SSX-H-A

Device Part Number 1SX280LU2F50E1VG
1SX280HU2F50E1VGAS

Figure 1. Development Kit Picture

1.1. General Development Kit Description
The Intel Stratix 10 SoC development board provides a hardware platform for developing and prototyping low-power, high-performance and logic-intensive designs using Intel Stratix 10 SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Intel Stratix 10 SoC designs.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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Figure 2.

Intel Stratix 10 SoC Development Kit Block Diagram
Intel® Enpirion® Power Solutions

Boot Flash DC

10/100/1000 RGMII PHY KSZ9031RNX

HPS Daughtercard

USB 2.0 PHY
USB3320

UART to USB

Micro SD Port

SDMI Bus RGMII USB2.0 UART1 TX/RX

FPGA Boot Flash DC (optional) HILO x72
SODIMM x72

SDMI Bus 2F SDM + JTAG + 05Cdk1

DDR4 Signal Rank

2M 2M 2L

DPIO DDR3/DDR4 Hardcore

Clock

Block 3I

DDR4 Dual 3J

Rank

PCle® Gen3 x 16

Hardcore CxP 1C 1D 1E 1F

22/AB 33/BC FIP/GOA 33/AL 22/BC

24 Channels LVDS Bus

Avalon®-ST 16/32 Bus

FMCA V57.4 PCle EP Trace 16/32 (optional)

FPGA_I/O Intel MAX 10 FPGA
Avalon-ST Intel MAX 10 FPGA_I/O

HBA, HBB FPP Flash

SDI_I/O 68-Bit Bus 24 Channels 16 Channels

HPS_I/O

HPS

FPGA

SGMII

MAC CORE

PCle® Gen3 x 16 Hardcore

100G / 50G Hardcore

4K 4M

1K 1L 1M 1N 4C 4D 4E 4F 4N

ZQSFP x2
PCle Gen3/Gen2/Gen1
x16 RC
FMCA V57.4 PCle EP

SEEPROM/ RTC/TEMP

LT_1 2C

ClockI2C

Ext I2C 1

Ext I2C 2

I2C 1

PMBUS_VID

InJTteAlGF®PSMGwAAiXtc1h0 and Power Sequencer Controller Intel FPGA Download Cable II x2 x4 x1
4 Channels
x1

2X SGMII PHY 88E1111
MXP SFP+ HDMI SDI/O

1.2. Recommended Operating Conditions
· Recommended ambient operating temperature range: 0 °C to 45 °C · Maximum ICC load current: 190 A · Maximum ICC load transient percentage: 30% · FPGA maximum power supported by the supplied heatsink/fan: 300 W

1.3. Handling the Development Kit

When handling the board, it is important to observe static discharge precautions.

Caution:

Without proper anti-static handling, the board can be damaged. Therefore, use antistatic handling precautions when touching the board.

Caution: You must not operate this development kit in a vibration environment.

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2. Getting Started
2.1. Installing Quartus Prime Software
The Intel Quartus® Prime design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The Intel Quartus Prime software delivers the highest performance and productivity for Intel FPGAs, CPLDs, and SoCs.
Design software must enable dramatically increased design productivity in order to take advantage of devices with multi-million logic elements with increased capabilities that provide designers with an ideal platform to meet next-generation design opportunities.
The new Intel Quartus Prime Design Suite design software includes everything needed to design for Intel FPGAs, SoCs and CPLDs from design entry and synthesis to optimization, verification and simulation. The Intel Quartus Prime Design Suite software includes an additional Spectra-Q® engine that is optimized for Intel Stratix 10 and future devices. The Spectra-Q engine enables new levels of design productivity for next generation programmable devices with a set of faster and more scalable algorithms, a hierarchical database infrastructure and a unified compiler technology.
Intel Quartus Prime
The Intel Quartus Prime Design Suite software is available in three editions based on specific design requirements: Pro, Standard, and Lite Edition.
The Intel Quartus Prime Pro Edition is optimized to support the advanced features in Intel's next generation FPGAs and SoCs and requires a paid license.
Intel Quartus Prime Standard Edition includes the most extensive support for Altera's latest device families and requires paid license.
Intel Quartus Prime Lite Edition provides an ideal entry point to Intel's high-volume device families and is available as a free download with no license file required.
Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software, Nios® II EDS and the MegaCore IP Library.
To install Intel's development tools, download the Intel Quartus Prime Pro Edition software from the Quartus Prime Pro Edition page in the Download Center of Intel's website.

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2.2. Installing the Intel FPGA Download Cable
The Intel Stratix 10 SoC Development Kit includes embedded Intel FPGA Download Cable circuits for FPGA and Intel MAX® 10 programming. However, for the host computer and board to communicate, you must install the Intel FPGA Download Cable driver on the host computer.
Installation instructions for the Intel FPGA Download Cable driver for your operating system are available on the Intel website.
On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.

2.3. Installing the Intel SoC Embedded Development Suite (EDS)
The Intel SoC EDS is a comprehensive software tool suite for embedded software development on Intel SoC devices. It contains development tools, utility programs, run-time software, and application examples to expedite firmware and application software of SoC embedded systems.
As a part of the Intel SoC EDS, the Arm* Development Studio (DS) Intel SoC FPGA Edition Toolkit provides a comprehensive set of embedded development tools for Intel's SoC FPGAs.
For more information and steps to install the SoC EDS Tool Suite refer to the links below.
Related Information · Arm Development Studio (DS) Intel SoC FPGA Edition · Intel SoC FPGA Embedded Development Suite User Guide

2.4. Installing the Intel Stratix 10 SX SoC Development Kit Package

The Intel Stratix 10 SX SoC Development Kit offers a quick and simple approach for developing custom Arm processor-based SoC designs. The Intel Stratix 10 SX SoCs offer full software compatibility with previous generation SoCs, a broad ecosystem of Arm software and tools, and the enhanced FPGA and digital signal processing (DSP) hardware design flow.
Intel Stratix 10 SX SoC Development Kit Package Installer is a single installation file contains that Intel Stratix 10 SX SoC Development Kit board design files, documents, and examples including the Board Test System (BTS) installation files.
Download and unzip Intel Stratix 10 SX SoC Development Kit Package Installer first. Install the Intel Stratix 10 SX SoC Board Test System.

Note:

To view the the layout *.brd files in the board package, you can download the Cadence® Allegro®/OrCAD® Free Viewer from Cadence's website.

For additional information, refer to the Intel Stratix 10 SX SoC Development Kit webpage on Intel's website using the link provided at the end of this section.

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Related Information · Intel Stratix 10 SX SoC Development Kit · Cadence Allegro

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3. Development Kit Setup

The instructions in this chapter explain how to setup the Intel Stratix 10 SoC Development Board.

3.1. Inspect the Development Kit

To inspect the board, perform the following steps:
1. Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment.
2. Verify that all components on the board appear in place and intact.

Caution: Without proper anti-static handling, you could damage the board.

Table 2.

Stratix 10 SoC Development Kit Contents

Item

Intel Stratix 10 SoC Development Board

USB Cable

USB Cable Micro

Ethernet Cable

HPS IO48 OOBE Daughter Card

HPS IO48 NAND Daughter Card

SODIMM Memory Card

QSPI Flash

SD Micro Flash

Quantity 1 2 1 1 1 1 1 1 1

Related Information · Thermal Management for FPGAs · Intel Intel Enpirion® Digital Power Configurator Graphical User Interface (GUI)

3.2. Default Setup of the Development Kit
This development kit ships with its board switches preconfigured to support the design examples in the kit.
1. Power up the development board by using the included power supply. 2. When configuration is complete, the configuration done green LED (D22)
illuminates, signaling that the Intel Stratix 10 device is configured successfully.

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Caution:

Use only the provided power supply. Power regulation circuits on the board can be damaged by power supplies with greater voltage and a lower-rated power supply may not be able to provide enough power for the board.

Table 3.

Default Setup

Checkpoint 1 2

Name Power Switch Power Adapter connector

Intel Intel Enpirion®

Reference SW7 J25, J55
J29

JTAG Dongle connector

JTAG Switch

SW1

USB JTAG Port

J57

12V Fan Connector

J16

Boot Switch

SW4

MSEL Switch

SW2

Description
Power is turn off at left position
Both connectors can be used to connect the power adapter
You can install Intel Enpirion dongle to monitor the board power rails. Switch 8 is at off position.
You can install Intel JTAG dongle to access FPGA
Default Setup from bit 1 to bit 8 is "off, off, on, on, on, on, on, on": Intel Stratix 10 SoC and Intel MAX 10 are on the JTAG chain
You need connect Micro USB cable to access Intel Stratix 10 SoC
You need use it to connect thermal Fan
Default set up from bit 1 to Bit 4 is "on, off, on, off" FPGA/HPS I2C is enabled. Daughter card power is on
Default Setup is "on on on on": JTAG mode

3.3. Intel MAX 10 System Controller Updates
The Intel MAX 10 System Controller manages several features on the Intel Stratix 10 SX SoC Development kit, including clocks, I2C, and some configuration signals. In certain situations, it may be necessary to ensure the Intel MAX 10 System Controller internal flash contains the latest available design. This may include the Intel Stratix 10 device failing to configure from OSC_CLK_1, or when other unexpected issues arise. The latest System Controller design is included in the Intel Stratix 10 SX Soc Development Kit Installer Package, in the "system_max10" folder inside the "examples" folder.
To update the internal flash, follow the steps outlined in the procedure below:
1. Power off the Intel Stratix 10 SX SoC Development Kit.
2. Ensure SW1 and SW2 are set to the default settings so the System Intel MAX 10 is on the JTAG chain and the Intel Stratix 10 device does not automatically configure itself.
3. Connect a micro USB cable to J57 for JTAG access and power on the board.
4. Open the Intel Quartus Prime Programmer and scan the device chain.
5. Right click on the Intel MAX 10 and select "Change File". Navigate to the "system_max10" folder and select the .pof file, for example, "max10_system_rev13.pof".

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6. Check the Program/Verify box in the row with the .pof and the Intel MAX 10 Device. The Program/Verify boxes in the immediately following rows, CFM0 and UFM, will auto-check as well. Refer to the following screenshot:
7. Click Start and wait for the programming cycle to finish. 8. Power off the board and reset SW1 and SW2 to prior settings, if any.

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4. Development Kit Components
This chapter introduces the major components on the Intel Stratix 10 Development Board. The board overview figure illustrates the component locations and the board components table provides a brief description of all component features of the board.

4.1. Development Kit Feature Summary

Table 4.

Intel Stratix 10 SoC Development Kit Feature Summary

Feature Programmable Logic HPS memory HPS Boot Flash (Flash Card) HPS IO48 OOBE Daughter Card
HPS IO48 NAND Flash Daughter Card

Description
· Intel Stratix 10 SoC FPGA · 10M04SCU169C8G Intel MAX 10 CPLD as the Intel FPGA Download Cable
and JTAG switch device · 10M16SAU169C8G Intel MAX 10 CPLD as the Power manager and
sequencer device · 10M50DAF484I7G Intel MAX 10 CPLD as the IO level translator, IO MUX
and Passive AVST-16 FPGA controller device
1066 MHz 4 GB 72-bit HILO memory card
· Boot Codes for QSPI, SD Micro · QSPI Flash: 256 MB (MT25QU02GCBB8E12-0SIT) · SD Micro Flash Card: 16 GB (Kingston)
· One HPS IO48 60-pin Samtec Connector · One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45 · One UART port: Standard USB Mini-B Receptacle · One Micro SD Card Connector: Standard Micro SD Card Socket · One USB 2.0 port: Standard USB Micro-AB Receptacle · One Mictor 38-pin connector (JTAG only without Trace signals)
-- Two JTAG targets selected by the resistors MUX: FPGA JTAG chain (optional) and HPS JTAG Port (default)
· I2C: HPS I2C port · GPIO
-- 2 Push buttons -- 3 LEDs -- 1 Ethernet Interrupt from Ethernet PHY -- 1 USB over-current indicator · HPS Clock: 25 MHz oscillator
· One HPS IO48 60-pin Samtec connector · One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45 · One UART port: Standard USB Mini-B Receptacle · NAND Flash (x16): 8 Gb · eMMC (x8): 8 GB 5.0 compliant eMMC
continued...

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Feature

Description

· I2C: HPS I2C port · GPIO
-- 2 Push Buttons -- 3 LEDs -- 1 Ethernet Interrupt from Ethernet PHY · HPS Clock: 25 MHz oscillator

FPGA memory

1200 MHz 16 GB DDR4 SO-DIMM MTA18ASF2G72HZ 2G6

FPGA File Flash (Flash Card)

· NAND Flash (x8): 1 GB · QSPI Flash: 256 MB · SD Micro Flash Card: 16 GB (Kingston)

Two V57.4 High Pin Count FMC+ Slots

· 28 Gbps signals: Insertion loss less than 5 dB, return loss less than 10 dB · FMC+ PCIe* Gen3 x16 cable (not included) · FMC to PCIe Gen3 x8 cable (not included) · 16/32 bit trace
Note: FMC to PCIe cables are sold separately by Samtec. Please contact them directly regarding P/N HDR-201768-01-PCIEC

FPGA PCIe Gen 1/2/3 x16 RC Slot

· 75 W Power · Meets PCIe specifications

FPGA Communication Ports

· Two 28 Gbps ZQSFP+ Ports: 100/50 Gbps IP, Insertion loss less than 5 dB, return loass less than 10 dB
· One 10 Gbps SFP+ Port: 10 Gbps Ethernet IP
· SMA Test Port: Up to four 28 Gbps channels, inseertion loss less than 5 dB, return loss less than 10 dB, one external reference clock
· One DB-9 RS-232 Port (MAX3221)

FPGA Debug Ports

Intel FPGA Download Cable Direct Port & JTAG

FPGA Reference Clocks

· Clock Cleaner -- 122.88 MHz (Network) -- 644.5312 MHz (Network) -- 297 MHz (SDI) -- 245 MHz (SDI)
· Clock Generators -- LMH1983 (27 MHz, 148.5 MHz) -- Si5388 (133.33 MHz) -- PCIe (100 MHz) -- Si5338 (148 MHz, 100 MHz, 27 MHz, 100 MHz) -- Si5341 (155.52 MHz, 644.53125 MHz, 135 MHz, 156.25 MHz, 625 MHz, 100 MHz, 125 MHz, 125 MHz)

I2C Devices

· 4 KB SEEPROM · Real Time Clock · Silicon LabsTM Clock Generators · FMC+ Slots · PCIe Slots · SFP+ · ZQSFP · Clock Cleaner · Power Supplies

Intel MAX 10 Controller I/O CPLD Features

· System Reset Controller · FPGA PS AVST Configuration Controller · I2C Master Controller

continued...

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Feature Intel MAX 10 Power CPLD Sequencer Intel MAX 10 CPLD Features
User I/O
Power Mechanical System Monitor

Description
· UART Level Shifter · FPGA I/O MUX · SDI/HDMI/QSFP/SFP+ I/O level shift
FPGA, PCIe, FMC+ slots power sequencer, Reset.
· Intel FPGA Download Cable II · JTAG Switch
-- Input JTAG Sources (Intel FPGA Download Cable II, 10-pin Program Header, FMCA+, FMCB+, Mictor JTAG)
-- Output JTAG Sources (Intel MAX 10 A JTAG, MAX10B JTAG, Intel Stratix 10 JTAG, FMCA+, FMCB+, PCIe)
-- JTAG Program -- User I/O
· 4 Push Buttons · 4-bit Dipswitch · 4 User LEDs · 2-pin I/O Header · System Intel MAX 10 LEDs and 4-bit switch
· Volgen KTPS200-12160, 12V, 24A · ATX-Power
· 8.5" x 14.5" Rectangular Form Factor · Liquid cool thermal heat sink (300W @ 35C)
Power, Voltage, Current

4.2. Board Components
Figure 3. Board Picture (Top View)

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Figure 4. Board Picture (Bottom View)

Board Components Table

Table 5.

Intel Stratix 10 SoC Board Components Table

Board Reference U15 U43 U46
J1
SW1 SW2 J57
SW4 SW8

Type

Description

Featured Device

FPGA

Intel Stratix 10 SoC FPGA

CPLD

Intel MAX 10 10M50DAF484I7G System Controller

CPLD

Intel MAX 10 10M16SAU169C8G Power Manager CPLD

Configuration, Status and Setup Elements

JTAG chain header

Provides access to the JTAG chain and disables the on-board Intel FPGA Download Cable II when using an external JTAG debugger such as an Intel FPGA Download Cable II

JTAG chain control DIP switch

Remove or include devices in the active JTAG chain

MSEL DIP Switch

Controls the configuration scheme on the board. MSEL pin 0,1,2 connect to the DIP Switch

Micro-USB Header

USB interface to on-board Intel FPGA Download Cable II JTAG for programming and debugging HPS, FPGA orIntel MAX 10 CPLD through a type-B Micro-USB cable.

Function DIP Switch

Selects I2C master, controls PCIe slot power and selects FPGA image source

Power Switch

ON position: Power GUI

continued...

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Board Reference
S2
S1 D22 D20 D19 D31 D1, D2
D24, D26, D28
D29, D30
U26 U29 U25 J19, J20 U33 U31 U34
D21, D23, D25, D27 SW3 S3 S4, S5, S6, S7 S20
J134 J14

Type

Description

OFF position: Intel Enpirion dongle

Program select push button

Toggles the program select LEDs which selects the program image that loads from flash memory to the FPGA

Configure push button

Load image from flash memory to the FPGA based on the settings of the program select LEDs

Configuration done LED

Illuminates when the FPGA is configured

Load LED

Illuminates when the Intel MAX 10 CPLD System Controller

Error LED

Illuminates when the FPGA configuration from flash memory fails

Power LED

Illuminates when 3.3V power is present

JTAG TX/RX LEDs

Indicates the transmit or receive activity of the JTAG chain. The TX and RX LEDs flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle

Program select LEDs

Illuminates to show which flash memory image loads to the FPGA when you press the program select push button

FMC port present LEDs

Illuminates when a daughtercard is plugged into the FMC port

Clock Circuits

Multi-output oscillator

Si5338A quad-output fixed oscillator with 148.5 MHz, 100 MHz, 27 MHz and 100 MHz outputs

50-MHz oscillator

50 MHz crystal oscillator for general purpose logic

Multi-output oscillator

Two 100 MHz outputs for PCIe application

Clock input SMA connector

External clock inputs for the transceiver test port

Multi-output oscillator

Si5341 ten-output fixed oscillator

Multi-output oscillator

Si5338A quad-output fixed oscillator with four 133.33 MHz outputs

Multi-output clock cleaner

LMK05028 Clock Cleaner

General User Input/Output

User LEDs

Four user LEDs. Illuminate when driven high.

User DIP Switch

User DIP switch. When the switch is ON, a logic 0 is selected

FPGA Reset Push Button

Reset the FPGA logic

General user push buttons

Four user push buttons. Driven low when pressed

HPS Reset Push Buttons

HPS cold/warm reset push buttons

Memory Connectors

HPS HILO Memory Connector

HPS memory card include DDR3 HILO memory card and DDR4 HILO memory card

Boot Flash Connector

Boot flash card options include QSPI flash card, SD micro flash card
continued...

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Board Reference J28 U41
J53 J11, J12
J7 J3 J4 J9-J10 J57, U2 J22 U42
J8 J5, U13 J6, U14 J29
J25, J55 SW7

Type

Description

SO-DIMM

16 GB SO-DIMM DDR4 Memory Card

I2C EEPROM

32 Kb I2C serial EEPROM

Communication Ports

PCIe socket

Gen3 x16 Socket

FMC Port

J29 is a V57.4 compatible FMC connector. J19 is a FMC connector defined by Intel 16 transceivers specification

SFP+ Port

One SFP+ Ports

Gigabit Ethernet Port

SGMII Gigabit Ethernet port through FPGA transceiver

Gigabit Ethernet Port

SGMII Gigabit Ethernet Port through FPGA transciever

QSFP28 Optical Transceiver Interface

17 Gbps/28 Gbps, 8 channels connected to QSFP28 modules

USB-UART Port

Mini-B USB interface to USB-to-UART bridge for serial UART interface

DB9 UART Port

DB9 RS-232 UART Port

Real-time clock

DS1339 device with built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time keeping even when the board is not powered

Video and Display Ports

HDMI Port

Display Port interface

SDI Video Output Port

HDBNC 75-Ohm SDI video TX interface

SDI Video Input Port

HDBNC 75-Ohm SDI video RX interface

Power GUI Connector

Intel Enpirion Power GUI Connector

Power Supply

DC input jack

Accepts 12 V DC power supply

Power Switch

Switch to power on or off the board when power is supplied from the DC input jack

4.3. Intel Stratix 10 SoC Device Overview
Intel's 14-nm Intel Stratix 10 SX SoCs deliver 2x core performance and up to 70% lower power over previous generation high-performance SoCs. Featuring several groundbreaking innovations, including the all new Intel HyperflexTM core architecture, this device family enables you to meet the demand for ever-increasing bandwidth and processing performance in you most advanced applications, while meeting your power budget.
Featuring several groundbreaking innovations, including the all new HyperFlexTM core architecture, this device family enables you to meet the demand for ever-increasing bandwidth and processing performance in your most advanced applications, while meeting your power budget.

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With an embedded hard processor system (HPS) based on a quad-core 64-bit Arm Cortex*-A53, the Stratix 10 SoC devices deliver power efficient, application-class processing and allow designers to extend hardware virtualization into the FPGA fabric. Stratix 10 SoC devices demonstrate Intel's commitment to high-performance SoCs and extend Intel's leadership in programmable devices featuring an Arm-based processor system.
Important innovations in Stratix 10 FPGAs and SoCs include:
· All new HyperFlex core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs
· Industry leading Intel 14-nm Tri-Gate (FinFET) technology
· Heterogeneous 3D System-in-Package (SiP) technology
· Monolithic core fabric with up to 5.5 million logic elements (LEs)
· Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles
· Transceiver data rates up to 28.3 Gbps chip-to-chip/module and backplane performance
· Embedded eSRAM (45 Mbit) and M20K (20 kbit) internal SRAM memory blocks
· Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs)
· Hard PCI Express® Gen3 x16 intellectual property (IP) blocks
· Hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) in every transceiver channel
· Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
· Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks with up to 10 TFLOPS compute performance with a power efficiency of 80 GFLOPS per Watt
· Quad-core 64-bit Arm Cortex-A53 embedded processor running up to 1.5 GHz in SoC family variants
· Programmable clock tree synthesis for flexible, low power, low skew clock trees
· Dedicated secure device manager (SDM) for:
-- Enhanced device configuration and security
-- AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and authentication
-- Multi-factor authentication
-- Physically Unclonable Function (PUF) service and software programmable device configuration capability
· Comprehensive set of advanced power saving features delivering up to 70% lower power compared to previous generation high-performance FPGAs
· Non-destructive register state readback and writeback, to support ASIC prototyping and other applications

Intel® Stratix® 10 SX SoC Development Kit User Guide 18

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With these capabilities, Stratix 10 FPGAs and SoCs are ideally suited for the most demanding applications in diverse markets such as:
· Compute and Storage--for custom servers, cloud computing and data center acceleration
· Networking--for Terabit, 400G and multi-100G bridging, aggregation, packet processing and traffic management
· Optical Transport Networks--for OTU4, 2xOTU4, 4xOTU4
· Broadcast--for high-end studio distribution, headend encoding/decoding, edge quadrature amplitude modulation (QAM)
· Military--for radar, electronic warfare, and secure communications
· Medical--for diagnostic scanners and diagnostic imaging
· Test and Measurement--for protocol and application testers
· Wireless--for next-generation 5G networks
· ASIC Prototyping--for designs that require the largest monolithic FPGA fabric with the highest I/O count

Intel Stratix 10 SX SoC devices have a feature set that is identical to the Intel Stratix 10 FPGA devices, with the addition of an embedded quad-core 64-bit Arm Cortex A53 Hard Processor System.

Common to all Stratix 10 family variants is a high-performance fabric based on the new HyperFlex core architecture that includes additional Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel's adaptive logic module (ALM) and a rich set of high performance building blocks including:

To clock these building blocks, Stratix 10 devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, finegrained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating.

All family variants also contain high speed serial transceivers, containing both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Stratix 10 devices contain multiple instantiations of PCI Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power, and increase your productivity.

Table 6.

Stratix 10 FPGA and SoC Common Device Features

Feature Technology
Low power serial transceivers

Description
· 14-nm Intel Tri-Gate (FinFET) process technology · SmartVoltage ID (VID) controlled standard VCC option · 0.8 V and 0.85 V optional VCC core voltage
· Up to 96 total transceivers available · Continuous operating range of 1 Gbps to 28.3 Gbps for Stratix 10 GX/SX devices · Backplane support up to 28.3 Gbps for Stratix 10 GX/SX devices
continued...

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Feature

Description

· Extended range down to 125 Mbps with oversampling · ATX transmit PLLs with user-configurable fractional synthesis capability · XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4 optical module support · Adaptive linear and decision feedback equalization · Transmit pre-emphasis and de-emphasis · Dynamic partial reconfiguration of individual transceiver channels · On-chip instrumentation (EyeQ non-intrusive data eye monitoring)

General purpose I/Os

· Up to 1640 total GPIO available · 1.6 Gbps LVDS--every pair can be configured as an input or output · 1333 MHz/2666 Mbps DDR4 external memory interface · 1067 MHz/2133 Mbps DDR3 external memory interface · 1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing · On-chip termination (OCT)

Embedded hard IP

· PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root port
· DDR4/DDR3/LPDDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory controller)
· Multiple hard IP instantiations in each device
· Single Root I/O Virtualization (SR-IOV)

Transceiver hard IP

· 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) · 10G Ethernet PCS · PCI Express PIPE interface · Interlaken PCS · Gigabit Ethernet PCS · Deterministic latency support for Common Public Radio Interface (CPRI) PCS · Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS · 8B/10B, 64B/66B, 64B/67B encoders and decoders · Custom mode support for proprietary protocols

Power management

· SmartVoltage ID controlled standard VCC option · Low static power device options · Intel Quartus Prime Pro Edition integrated power analysis

High performance monolithic core fabric

· HyperFlex core architecture with Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks
· Monolithic fabric minimizes compile times and increases logic utilization · Enhanced adaptive logic module (ALM) · Improved multi-track routing architecture reduces congestion and improves compile
times · Hierarchical core clocking architecture with programmable clock tree synthesis · Fine-grained partial reconfiguration

Internal memory blocks

· eSRAM - 45-Mbit with hard ECC support · M20K--20-Kbit with hard ECC support · MLAB--640-bit distributed LUTRAM

Variable precision DSP blocks

· IEEE 754-compliant hard single-precision floating point capability · Supports signal processing with precision ranging from 18x19 up to 54x54 · Native 27x27 and 18x19 multiply modes · 64-bit accumulator and cascade for systolic FIRs · Internal coefficient memory banks · Pre-adder/subtractor improves efficiency · Additional pipeline register increases performance and reduces power
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 20

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Feature Phase locked loops (PLL) Core clock networks Configuration
Packaging Software and tools

Description
· Fractional synthesis PLLs (fPLL) support both fractional and integer modes · Fractional mode with third-order delta-sigma modulation · Precision frequency synthesis · Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS
interfaces, clock delay compensation, zero delay buffering
· 1 GHz fabric clocking · 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface · 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface · Programmable clock tree synthesis, backwards compatible with global, regional and
peripheral clock networks · Clocks only synthesized where needed, to minimize dynamic power
· Dedicated Secure Device Manager · Software programmable device configuration · Serial and parallel flash interface · Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3 · Fine-grained partial reconfiguration of core fabric · Dynamic reconfiguration of transceivers and PLLs · Comprehensive set of security features including AES-256, SHA-256/384, and
ECDSA-256/384 accelerators, and multi-factor authentication · Physically Unclonable Function (PUF) service
· Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology · Multiple devices with identical package footprints allows seamless migration across
different device densities · 1.0 mm ball-pitch FBGA packaging · Lead and lead-free package options
· Intel Quartus Prime Pro Edition design suite with new Spectra-Q engine and HyperAware design flow
· Fast Forward compiler to allow HyperFlex architecture performance exploration · Transceiver toolkit · Qsys system integration tool · DSP Builder advanced blockset · OpenCLTM support · SoC Embedded Design Suite (EDS)

Table 7.

Stratix 10 SoC Specific Device Features

SoC Subsystem
Hard Processor System

Feature

Description

Multi-processor unit (MPU) core

· Quad-core Arm Cortex-A53 MPCore processor with Arm CoreSight debug and trace technology
· Scalar floating-point unit supporting single and double precision
· Arm NEON media processing engine for each processor

System Controllers

· System Memory Management Unit (SMMU) · Cache Coherency Unit (CCU)

Layer 1 Cache

· 32 KB L1 instruction cache with parity · 32 KB L1 data cache with ECC

Layer 2 Cache

· 1 MB Shared L2 Cache with ECC

On-Chip Memory

· 256 KB On-Chip RAM

Direct memory access (DMA) controller · 8-Channel DMA

continued...

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SoC Subsystem

Feature
Ethernet media access controller (EMAC)
USB On-The-Go controller (OTG)
UART controller
Serial Peripheral Interface (SPI) controller I2C controller
SD/SDIO/MMC controller

NAND flash controller General-purpose I/O (GPIO) Timers

Secure Device Manager

Security

External Memory Interface

Description · Three 10/100/1000 EMAC with integrated DMA
· 2 USB OTG with integrated DMA · 2 UART 16550 compatible · 4 SPI
· 5 I2C controllers · 1 eMMC version 4.5 with DMA and CE-ATA support · SD, including eSD, version 3.0 · SDIO, including eSDIO, verion 3.0 · CE-ATA - version 1.1 · 1 ONFI 1.0, 8- and 16-bit support · Maximum of 48 software programmable GPIO · 4 general-purpose timers · 4 watchdog timers · Secure boot · Advanced Encryption Standard (AES) and authentication
(SHA/ECDSA) · Hard Memory Controller with DDR4 and DDR3, and
LPDDR3

For further information , please refer to the Intel Stratix 10 GX/SX Device Overview available on the Intel website.
Related Information Stratix 10 GX/SX Device Overview

4.4. Intel MAX 10 System Controller Overview
Intel MAX 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate the optimal set of system components.
Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
The highlights of the Intel MAX 10 devices include:
· Internally stored dual configuration flash · User flash memory · Instant on support · Integrated analog-to-digital converters (ADCs) · Single-chip Nios II soft core processor support

Intel® Stratix® 10 SX SoC Development Kit User Guide 22

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Table 8.

Summary of Features for Intel MAX 10 Devices

Technology Packaging

Feature

Core architecture

Internal memory blocks User flash memory (UFM)
Embedded multiplier blocks ADC
Clock networks Internal oscillator PLLs

General-purpose I/Os (GPIOs) External memory interface (EMIF) (1)

Description
55 nm TSMC Embedded Flash (Flash + SRAM) process technology
· Low cost, small form factor packages--support multiple packaging technologies and pin pitches
· Multiple device densities with compatible package footprints for seamless migration between different device densities
· RoHS6-compliant
· 4-input look-up table (LUT) and single register logic element (LE) · LEs arranged in logic array block (LAB) · Embedded RAM and user flash memory · Clocks and PLLs · Embedded multiplier blocks · General purpose I/Os
· M9K--9 kilobits (Kb) memory blocks · Cascadable blocks to create RAM, dual port, and FIFO functions
· User accessible non-volatile storage · High speed operating frequency · Large memory size · High data retention · Multiple interface option
· One 18 × 18 or two 9 × 9 multiplier modes · Cascadable blocks enabling creation of filters, arithmetic functions, and image
processing pipelines
· 12-bit successive approximation register (SAR) type · Up to 17 analog inputs · Cumulative speed up to 1 million samples per second ( MSPS) · Integrated temperature sensing capability
· Global clocks support · High speed frequency in clock network
Built-in internal ring oscillator
· Analog-based · Low jitter · High precision clock synthesis · Clock delay compensation · Zero delay buffering · Multiple output taps
· Multiple I/O standards support · On-chip termination (OCT) · Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS
transmitter
Supports up to 600 Mbps external memory interfaces: · DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40 and 10M50) · SRAM (Hardware support only)
continued...

(1) EMIF is only supported in selected MAX 10 device density and package combinations. Refer to the External Memory Interface User Guide for more information.

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Feature Configuration Flexible power supply schemes

Description
Note: For 600 Mbps performance, 6 device speed grade is required. Performance varies according to device grade (commercial, industrial, or automotive) and device speed grade (6 or 7). Refer to the MAX 10 Device Data Sheet or External Memory Interface Spec Estimator for more details.
· Internal configuration · JTAG · Advanced Encryption Standard (AES) 128-bit encryption and compression
options · Flash memory data retention of 20 years at 85 °C
· Single- and dual-supply device options · Dynamically controlled input buffer power down · Sleep mode for dynamic power reduction

4.5. FPGA Configuration

This development kit supports the following FPGA configurations: · QSPI Configuration · SDMMC x4 Configuration · JTAG Only

A 4-bit DIP Switch (SW2) is used to select the FPGA configuration mode.

Table 9.
1 2 3 4

DIP Switch Bits
Switch Bit

MSEL0 MSEL1 MSEL2 Not Used

Name

Table 10. DIP Switch Bit Description

MSEL2 OFF ON ON

MSEL1 OFF OFF ON

MSEL0 ON OFF ON

Mode QSPI SDMMC x4, SDMMC x8 JTAG

Note:

The default setting is JTAG mode. The default bit position is "ON, ON, ON, ON"

4.6. General User Input/Output

Table 11.
PIN_A24 PIN_B24

User I/O Pin Map
Pin Name

Schematic Signal Name USER_LED_FPGA0 USER_LED_FPGA2

Description

USER_LED0

USER_LED1

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 24

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PIN_F22 PIN_E22 PIN_A26 PIN_A25 PIN_D23 PIN_D24 PIN_B23 PIN_C23 PIN_E23 PIN_E24

Pin Name

Schematic Signal Name USER_LED_FPGA1 USER_LED_FPGA3 USER_PB_FPGA0 USER_PB_FPGA1 USER_PB_FPGA2 USER_PB_FPGA3 USER_DIPSW_FPGA0 USER_DIPSW_FPGA1 USER_DIPSW_FPGA2 USER_DIPSW_FPGA3

Description USER_LED2 USER_LED3 USER_PB0 USER_PB1 USER_PB2 USER_PB3 USER_DPSW0 USER_DPSW1 USER_DPSW2 USER_DPSW3

4.7. Connectors and Interfaces

The FPGA portion of this development kit includes 96 transceivers.

Table 12. Channel Assignment for Transceiver Applications

Applications FMC+ A SFP+ Port PCIE RC x16 SGMII Port 1 and Port 2 FMC+ B MXP Test Ports SDI Port HDMI ZQSFP+ B ZQSFP+ A

Channel (Bank, Number) 1C (1C, 0-5), 1D (1D, 0-5), 1E (1E, 0-3), 1F (PCIE EP x16) (4C, 0) (4K, 0-5), (4L, 0-5), (4M, 0-3) (4M, 4), (4M, 5) 1K (1K, 0-5), 1L (1L, 0-5), 1M (1M, 0-3), 1N (PCIE EPx16) (4D, 0, 1, 3, 4) TX (4E,1), RX (4F, 0) (4C, 2-5) (4F, (0,1,3,4)) (4N, (0,1,3,4))

4.7.1. PCIe Slot
The PCIe root port is a PCIe Gen3 x16 port. This port is assigned to 4K, 4L and 4M Banks. The transceiver I/O bank power is connected to 1.8 V.
PCIE_PRSNT2n, PCIE_PERSTn and PCIE_WAKE_N 3V3 signals are mapped to the dedicated trasnceiver I/O bank (IO4) in the Intel MAX 10. The system performance of the PCIe root port should meet the PCIe 3.0 specifications.

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Table 13. PCIE Root Port FPGA Pin Map

Pin Name PIN_V12

Schematic Signal Name PCIE_REFCLK_QR0_P

PIN_V13 PIN_L4

PCIE_REFCLK_QR0_N PCIE_TX_N15

PIN_L3

PCIE_TX_P15

PIN_H6 PIN_H5

PCIE_RX_N15 PCIE_RX_P15

PIN_K2

PCIE_TX_N14

PIN_K1 PIN_L8

PCIE_TX_P14 PCIE_RX_N14

PIN_L7

PCIE_RX_P14

PIN_N4 PIN_N3

PCIE_TX_N13 PCIE_TX_P13

PIN_K6

PCIE_RX_N13

PIN_K5

PCIE_RX_P13

PIN_M2

PCIE_TX_N12

PIN_M1

PCIE_TX_P12

PIN_N8

PCIE_RX_N12

PIN_N7

PCIE_RX_P12

PIN_R4

PCIE_TX_N11

PIN_R3

PCIE_TX_P11

PIN_M6

PCIE_RX_N11

PIN_M5 PIN_P2

PCIE_RX_P11 PCIE_TX_N10

PIN_P1

PCIE_TX_P10

PIN_R8 PIN_R7

PCIE_RX_N10 PCIE_RX_P10

PIN_T2

PCIE_TX_N9

PIN_T1 PIN_P6

PCIE_TX_P9 PCIE_RX_N9

PIN_P5

PCIE_RX_P9

PIN_U4 PIN_U3

PCIE_TX_N8 PCIE_TX_P8

PIN_T6

PCIE_RX_N8

Direction Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input

Description REFCLK_GXBR4K_CHTP REFCLK_GXBR4K_CHTN GXBR4M_TX_CH3N GXBR4M_TX_CH3P GXBR4M_RX_CH3N GXBR4M_RX_CH3P GXBR4M_TX_CH2N GXBR4M_TX_CH2P GXBR4M_RX_CH2N GXBR4M_RX_CH2P GXBR4M_TX_CH1N GXBR4M_TX_CH1P GXBR4M_RX_CH1N GXBR4M_RX_CH1P GXBR4M_TX_CH0N GXBR4M_TX_CH0P GXBR4M_RX_CH0N GXBR4M_RX_CH0P GXBR4L_TX_CH5N GXBR4L_TX_CH5P GXBR4L_RX_CH5N GXBR4L_RX_CH5P GXBR4L_TX_CH4N GXBR4L_TX_CH4P GXBR4L_RX_CH4N GXBR4L_RX_CH4P GXBR4L_TX_CH3N GXBR4L_TX_CH3P GXBR4L_RX_CH3N GXBR4L_RX_CH3P GXBR4L_TX_CH2N GXBR4L_TX_CH2P GXBR4L_RX_CH2N
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 26

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Pin Name PIN_T5 PIN_V2 PIN_V1 PIN_U8 PIN_U7 PIN_Y2 PIN_Y1 PIN_V6 PIN_V5 PIN_W4 PIN_W3 PIN_Y6 PIN_Y5 PIN_AB2 PIN_AB1 PIN_W8 PIN_W7 PIN_AA4 PIN_AA3 PIN_AB6 PIN_AB5 PIN_AD2 PIN_AD1 PIN_AA8 PIN_AA7 PIN_AC4 PIN_AC3 PIN_AD6 PIN_AD5 PIN_AE4 PIN_AE3 PIN_AC8 PIN_AC7

Schematic Signal Name PCIE_RX_P8 PCIE_TX_N7 PCIE_TX_P7 PCIE_RX_N7 PCIE_RX_P7 PCIE_TX_N6 PCIE_TX_P6 PCIE_RX_N6 PCIE_RX_P6 PCIE_TX_N5 PCIE_TX_P5 PCIE_RX_N5 PCIE_RX_P5 PCIE_TX_N4 PCIE_TX_P4 PCIE_RX_N4 PCIE_RX_P4 PCIE_TX_N3 PCIE_TX_P3 PCIE_RX_N3 PCIE_RX_P3 PCIE_TX_N2 PCIE_TX_P2 PCIE_RX_N2 PCIE_RX_P2 PCIE_TX_N1 PCIE_TX_P1 PCIE_RX_N1 PCIE_RX_P1 PCIE_TX_N0 PCIE_TX_P0 PCIE_RX_N0 PCIE_RX_P0

Direction Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input

Description GXBR4L_RX_CH2P GXBR4L_TX_CH1N GXBR4L_TX_CH1P GXBR4L_RX_CH1N GXBR4L_RX_CH1P GXBR4L_TX_CH0N GXBR4L_TX_CH0P GXBR4L_RX_CH0N GXBR4L_RX_CH0P GXBR4K_TX_CH5N GXBR4K_TX_CH5P GXBR4K_RX_CH5N GXBR4K_RX_CH5P GXBR4K_TX_CH4N GXBR4K_TX_CH4P GXBR4K_RX_CH4N GXBR4K_RX_CH4P GXBR4K_TX_CH3N GXBR4K_TX_CH3P GXBR4K_RX_CH3N GXBR4K_RX_CH3P GXBR4K_TX_CH2N GXBR4K_TX_CH2P GXBR4K_RX_CH2N GXBR4K_RX_CH2P GXBR4K_TX_CH1N GXBR4K_TX_CH1P GXBR4K_RX_CH1N GXBR4K_RX_CH1P GXBR4K_TX_CH0N GXBR4K_TX_CH0P GXBR4K_RX_CH0N GXBR4K_RX_CH0P

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4.7.2. ZQSFP+

The ZQSFP+ 0/1 ports meet SFF8665 and QSFP28 industrial standards. The connector part number is Molex 170432-001. The cage part number is TE 2227103-2. The PCB trace insertion loss is less than -5 dB and return loss is less than -10 dB. The ZQSFP+
signals (Modesl, RESETL, MOdPrsl, LPmode, int) are mapped to the dedicated I/O in System Intel MAX 10. The BC25, BC26 pins in 2F bank are I2C interface. The user needs this interface to access ZQSFP.

Table 14. ZQSFP+ 0/1 Ports FPGA Pin Map

Pin Name PIN_P9

Schematic Signal Name
CLEARNER_XVR_644.53125 Input MHZ_P

Direction

PIN_P10

CLEARNER_XVR_644.53125 Input MHZ_N

PIN_C4

ZQSFP0_TXN3

Output

PIN_C3

ZQSFP0_TXP3

Output

PIN_A8

ZQSFP0_RXN3

Input

PIN_A7

ZQSFP0_RXP3

Input

PIN_E4

ZQSFP0_TXN2

Output

PIN_E3

ZQSFP0_TXP2

Output

PIN_C8 PIN_C7

ZQSFP0_RXN2 ZQSFP0_RXP2

Input Input

PIN_G4

ZQSFP0_TXN1

Output

PIN_G3 PIN_D6

ZQSFP0_TXP1 ZQSFP0_RXN1

Output Input

PIN_D5

ZQSFP0_RXP1

Input

PIN_F2 PIN_F1

ZQSFP0_TXN0 ZQSFP0_TXP0

Output Output

PIN_G8

ZQSFP0_RXN0

Input

PIN_G7 PIN_T9

ZQSFP0_RXP0 REFCLK0_P

Input Input

PIN_T10

REFCLK0_N

Input

PIN_AF2

ZQSFP1_TXN3

Output

PIN_AF1

ZQSFP1_TXP3

Output

PIN_AG8

ZQSFP1_RXN3

Input

PIN_AG7

ZQSFP1_RXP3

Input

PIN_AJ4

ZQSFP1_TXN2

Output

PIN_AJ3

ZQSFP1_TXP2

Output

Description REFCLK_GXBR4N_CHTP
REFCLK_GXBR4N_CHTN
GXBR4N_TX_CH3N GXBR4N_TX_CH3P GXBR4N_RX_CH3N GXBR4N_RX_CH3P GXBR4N_TX_CH2N GXBR4N_TX_CH2P GXBR4N_RX_CH2N GXBR4N_RX_CH2P GXBR4N_TX_CH1N GXBR4N_TX_CH1P GXBR4N_RX_CH1N GXBR4N_RX_CH1P GXBR4N_TX_CH0N GXBR4N_TX_CH0P GXBR4N_RX_CH0N GXBR4N_RX_CH0P REFCLK_GXBR4N_CHBP REFCLK_GXBR4N_CHBN GXBR4F_TX_CH3N GXBR4F_TX_CH3P GXBR4F_RX_CH3N GXBR4F_RX_CH3P GXBR4F_TX_CH2N GXBR4F_TX_CH2P
continued...

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Pin Name PIN_AF6 PIN_AF5 PIN_AL4 PIN_AL3 PIN_AH6 PIN_AH5 PIN_AK2 PIN_AK1 PIN_AL8 PIN_AL7 PIN_AM12 PIN_AM13

Schematic Signal Name ZQSFP1_RXN2 ZQSFP1_RXP2 ZQSFP1_TXN1 ZQSFP1_TXP1 ZQSFP1_RXN1 ZQSFP1_RXP1 ZQSFP1_TXN0 ZQSFP1_TXP0 ZQSFP1_RXN0 ZQSFP1_RXP0 REFCLK_QSFP1_P REFCLK_QSFP1_N

Direction Input Input Output Output Input Input Output Output Input Input Input Input

Description GXBR4F_RX_CH2N GXBR4F_RX_CH2P GXBR4F_TX_CH1N GXBR4F_TX_CH1P GXBR4F_RX_CH1N GXBR4F_RX_CH1P GXBR4F_TX_CH0N GXBR4F_TX_CH0P GXBR4F_RX_CH0N GXBR4F_RX_CH0P REFCLK_GXBR4F_CHBP REFCLK_GXBR4F_CHBN

4.7.3. SFP+

The SFP+ Port meets SFF-8431 Industrial Standard. The connector part number is Samtec MECT-110-01-M-D-RA1. The cage part number is Molex 74754-0101. The PCB trace insertion loss is less than -5 dB and return loss less than -10 dB.

SFP+ signals (TX_disable, RS0/1, MOD_ABS, LOS, Fault) are mapped to the dedicated transceiver I/O in Intel MAX 10.

Table 15. SFP+ Port FPGA Pin Map

Pin Name

Schematic Signal Name

PIN_BJ5

SFPA_TX_N

PIN_BJ4

SFPA_TX_P

PIN_BH10

SFPA_RX_N

PIN_BH9

SFPA_RX_P

PIN_AT9

REFCLK_SFPA_P

PIN_AT10

REFCLK_SFPA_N

Direction Output Output Input Input Input Input

Description GXBR4C_TX_CH0N GXBR4C_TX_CH0P GXBR4C_RX_CH0N GXBR4C_RX_CH0P REFCLK_GXBR4C_CHBP REFCLK_GXBR4C_CHBN

4.7.4. HDMI

Table 16. HDMI Port FPGA Pin Map

Pin Name

Schematic Signal Name

PIN_AP9

HDMIREFCLK_P

PIN_AP10

HDMIREFCLK_N

PIN_BC4

HDMI_LANE_CLKN

PIN_BC3

HDMI_LANE_CLKP

Direction Input Input Output Output

Description REFCLK_GXBR4C_CHTP REFCLK_GXBR4C_CHTN GXBR4C_TX_CH5N GXBR4C_TX_CH5P
continued...

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4. Development Kit Components UG-20081 | 2020.09.08

Pin Name PIN_BF2 PIN_BF1 PIN_BE4 PIN_BE3 PIN_BG4 PIN_BG3

Schematic Signal Name HDMI_LANE_N2 HDMI_LANE_P2 HDMI_LANE_N1 HDMI_LANE_P1 HDMI_LANE_N0 HDMI_LANE_P0

Direction Output Output Output Output Output Output

Description GXBR4C_TX_CH4N GXBR4C_TX_CH4P GXBR4C_TX_CH3N GXBR4C_TX_CH3P GXBR4C_TX_CH2N GXBR4C_TX_CH2P

4.7.5. SDI Port

Table 17. SDI Port FPGA Pin Map

Pin Name

Schematic Signal Name

PIN_AF9

CLEARNER_SDI_245MHZ_P

PIN_AF10

CLEARNER_SDI_245MHZ_N

PIN_AR4

SDI_TX_N

PIN_AR3

SDI_TX_P

PIN_AR8

SDI_RX_N

PIN_AR7

SDI_RX_P

PIN_AK12

CLEARNER_SDI_297MHZ_P

PIN_AK13

CLEARNER_SDI_297MHZ_N

Direction Input Input Output Output Input Input Input Input

Description REFCLK_GXBL4E_CHTP REFCLK_GXBL4E_CHTN GXBR4E_TX_CH1N GXBR4E_TX_CH1P GXBR4E_RX_CH0N GXBR4E_RX_CH0P REFCLK_GXBL4F_CHTP REFCLK_GXBL4F_CHTN

4.7.6. MXP

The MXP Test Port is a MXP Coaxial Print Connectors. The PCB trace insertion loss is less than -5 dB and return loss is less than -10 dB. You can use it for 100 Gbps applications.

Table 18. MXP Port FPGA Pin Map

Pin Name

Schematic Signal Name

PIN_AK9

REFCLK_SMA_P

PIN_AK10

REFCLK_SMA_N

PIN_AY2

MXP_TXN3

PIN_AY1

MXP_TXP3

PIN_AU8

MXP_RXN3

PIN_AU7

MXP_RXP3

PIN_AW4

MXP_TXN2

PIN_AW3

MXP_TXP2

PIN_AY6

MXP_RXN2

PIN_AY5

MXP_RXP2

Direction Input Input Output Output Input Input Output Output Input Input

Description REFCLK_GXBR4D_CHTP REFCLK_GXBR4D_CHTN GXBR4D_TX_CH3N GXBR4D_TX_CH3P GXBR4D_RX_CH3N GXBR4D_RX_CH3P GXBR4D_TX_CH2N GXBR4D_TX_CH2P GXBR4D_RX_CH2N GXBR4D_RX_CH2P
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 30

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Pin Name PIN_BA4 PIN_BA3 PIN_BB6 PIN_BB5 PIN_BD2 PIN_BD1 PIN_BA8 PIN_BA7

Schematic Signal Name MXP_TXN1 MXP_TXP1 MXP_RXN1 MXP_RXP1 MXP_TXN0 MXP_TXP0 MXP_RXN0 MXP_RXP0

Direction Output Output Input Input Output Output Input Input

Description GXBR4D_TX_CH1N GXBR4D_TX_CH1P GXBR4D_RX_CH1N GXBR4D_RX_CH1P GXBR4D_TX_CH0N GXBR4D_TX_CH0P GXBR4D_RX_CH0N GXBR4D_RX_CH0P

4.7.7. Intel FPGA Download Cable Direct Port (Debug Port)

The Direct Port is connected to the 3B bank.

Table 19. Debug Port FPGA Pin Map

Pin Name

Schematic Signal Name

PIN_AP16

USB0

PIN_AP15

USB1

PIN_AU13

USB2

PIN_AV13

USB3

PIN_AU12

USB4

PIN_AT12

USB5

PIN_AR13

USB6

PIN_AP12

USB7

PIN_AP14

USB_RDN

PIN_AP13

USB_WRN

PIN_AT14

USB_OEN

PIN_AR14

USB_RESETN

PIN_AR18

USB_EMPTY

PIN_AP18

USB_FULL

PIN_AU14

USB_SDA

PIN_AU15

USB_SCL

Description USB Debug Data USB Debug Data USB Debug Data USB Debug Data USB Debug Data USB Debug Data USB Debug Data USB Debug Data USB Debug Control Signal USB Debug Control Signal USB Debug Control Signal USB Debug Control Signal USB Debug Control Signal USB Debug Control Signal USB Debug I2C USB Debug I2C

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Intel® Stratix® 10 SX SoC Development Kit User Guide 31

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4.7.8. FMC+ A/B Slot

Table 20. FMC+ A Slot FPGA Pin Map

Pin Name PIN_AP41

Schematic Signal Name FAGBTCLK0M2CP

Input

Direction

PIN_AP40

FAGBTCLK0M2CN

Input

PIN_BC46 PIN_BC47

FAD5C2MN FAD5C2MP

Output Output

PIN_BD44

FAD5M2CN

Input

PIN_BD45 PIN_BF48

FAD5M2CP FAD4C2MN

Input Output

PIN_BF49

FAD4C2MP

Output

PIN_BC42 PIN_BC43

FAD4M2CN FAD4M2CP

Input Input

PIN_BE46

FAD3C2MN

Output

PIN_BE47

FAD3C2MP

Output

PIN_BE42

FAD3M2CN

Input

PIN_BE43

FAD3M2CP

Input

PIN_BG46

FAD2C2MN

Output

PIN_BG47

FAD2C2MP

Output

PIN_BG42

FAD2M2CN

Input

PIN_BG43

FAD2M2CP

Input

PIN_BF44

FAD1C2MN

Output

PIN_BF45 PIN_BJ42

FAD1C2MP FAD1M2CN

Output Input

PIN_BJ43

FAD1M2CP

Input

PIN_BJ45 PIN_BJ46

FAD0C2MN FAD0C2MP

Output Output

PIN_BH40

FAD0M2CN

Input

PIN_BH41 PIN_AT41

FAD0M2CP

Input

CLEARNER_XVRR_122.88MH Input Z_P

PIN_AT40

CLEARNER_XVRR_122.88MH Input Z_N

PIN_AK41

FAGBTCLK1M2CP

Input

PIN_AK40 PIN_AU46

FAGBTCLK1M2CN FAD11C2MN

Input Output

Description REFCLK_GXBL1C_CHTP REFCLK_GXBL1C_CHTN GXBR1C_TX_CH5N GXBR1C_TX_CH5P GXBR1C_RX_CH5N GXBR1C_RX_CH5P GXBR1C_TX_CH4N GXBR1C_TX_CH4P GXBR1C_RX_CH4N GXBR1C_RX_CH4P GXBR1C_TX_CH3N GXBR1C_TX_CH3P GXBR1C_RX_CH3N GXBR1C_RX_CH3P GXBR1C_TX_CH2N GXBR1C_TX_CH2P GXBR1C_RX_CH2N GXBR1C_RX_CH2P GXBR1C_TX_CH1N GXBR1C_TX_CH1P GXBR1C_RX_CH1N GXBR1C_RX_CH1P GXBR1C_TX_CH0N GXBR1C_TX_CH0P GXBR1C_RX_CH0N GXBR1C_RX_CH0P REFCLK_GXBL1C_CHBP
REFCLK_GXBL1C_CHBN
REFCLK_GXB1D_CHTP REFCLK_GXB1D_CHTN GXBR1D_TX_CH5N
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 32

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Pin Name PIN_AU47 PIN_AV44 PIN_AV45 PIN_AY48 PIN_AY49 PIN_AU42 PIN_AU43 PIN_AW46 PIN_AW47 PIN_AY44 PIN_AY45 PIN_BB48 PIN_BB49 PIN_AW42 PIN_AW43 PIN_BA46 PIN_BA47 PIN_BB44 PIN_BB45 PIN_BD48 PIN_BD49 PIN_BA42 PIN_BA43 PIN_AM41 PIN_AM40 PIN_AF41 PIN_AF40 PIN_AM48 PIN_AM49 PIN_AK44 PIN_AK45 PIN_AN46 PIN_AN47 PIN_AM44

Schematic Signal Name FAD11C2MP FAD11M2CN FAD11M2CP FAD10C2MN FAD10C2MP FAD10M2CN FAD10M2CP FAD9C2MN FAD9C2MP FAD9M2CN FAD9M2CP FAD8C2MN FAD8C2MP FAD8M2CN FAD8M2CP FAD7C2MN FAD7C2MP FAD7M2CN FAD7M2CP FAD6C2MN FAD6C2MP FAD6M2CN FAD6M2CP FAGBTCLK3M2CP FAGBTCLK3M2CN FAGBTCLK2M2CP FAGBTCLK2M2CN FAD17C2MN FAD17C2MP FAD17M2CN FAD17M2CP FAD16C2MN FAD16C2MP FAD16M2CN

Direction Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Input Input Input Input Output Output Input Input Output Output Input

Description GXBR1D_TX_CH5P GXBR1D_RX_CH5N GXBR1D_RX_CH5P GXBR1D_TX_CH4N GXBR1D_TX_CH4P GXBR1D_RX_CH4N GXBR1D_RX_CH4P GXBR1D_TX_CH3N GXBR1D_TX_CH3P GXBR1D_RX_CH3N GXBR1D_RX_CH3P GXBR1D_TX_CH2N GXBR1D_TX_CH2P GXBR1D_RX_CH2N GXBR1D_RX_CH2P GXBR1D_TX_CH1N GXBR1D_TX_CH1P GXBR1D_RX_CH1N GXBR1D_RX_CH1P GXBR1D_TX_CH0N GXBR1D_TX_CH0P GXBR1D_RX_CH0N GXBR1D_RX_CH0P REFCLK_GXBL1D_CHBP REFCLK_GXBL1D_CHBN REFCLK_GXBL1E_CHBP REFCLK_GXBL1E_CHBN GXBR1E_TX_CH5N GXBR1E_TX_CH5P GXBR1E_RX_CH5N GXBR1E_RX_CH5P GXBR1E_TX_CH4N GXBR1E_TX_CH4P GXBR1E_RX_CH4N
continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 33

Pin Name PIN_AM45 PIN_AP48 PIN_AP49 PIN_AN42 PIN_AN43 PIN_AT48 PIN_AT49 PIN_AP44 PIN_AP45 PIN_AR46 PIN_AR47 PIN_AT44 PIN_AT45 PIN_AV48 PIN_AV49 PIN_AR42 PIN_AR43 PIN_AH41 PIN_AH40 PIN_AK38 PIN_AK37 PIN_AG46 PIN_AG47 PIN_AE42 PIN_AE43 PIN_AF48 PIN_AF49 PIN_AG42 PIN_AG43 PIN_AJ46 PIN_AJ47 PIN_AF44 PIN_AF45 PIN_AH48

4. Development Kit Components UG-20081 | 2020.09.08

Schematic Signal Name FAD16M2CP FAD15C2MN FAD15C2MP FAD15M2CN FAD15M2CP FAD14C2MN FAD14C2MP FAD14M2CN FAD14M2CP FAD13C2MN FAD13C2MP FAD13M2CN FAD13M2CP FAD12C2MN FAD12C2MP FAD12M2CN FAD12M2CP FAGBTCLK4M2CP FAGBTCLK4M2CN FAGBTCLK5M2CP FAGBTCLK5M2CN FAD23C2MN FAD23C2MP FAD23M2CN FAD23M2CP FAD22C2MN FAD22C2MP FAD22M2CN FAD22M2CP FAD21C2MN FAD21C2MP FAD21M2CN FAD21M2CP FAD20C2MN

Direction Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Input Input Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output

Description GXBR1E_RX_CH4P GXBR1E_TX_CH3N GXBR1E_TX_CH3P GXBR1E_RX_CH3N GXBR1E_RX_CH3P GXBR1E_TX_CH2N GXBR1E_TX_CH2P GXBR1E_RX_CH2N GXBR1E_RX_CH2P GXBR1E_TX_CH1N GXBR1E_TX_CH1P GXBR1E_RX_CH1N GXBR1E_RX_CH1P GXBR1E_TX_CH0N GXBR1E_TX_CH0P GXBR1E_RX_CH0N GXBR1E_RX_CH0P REFCLK_GXBL1E_CHBP REFCLK_GXBL1E_CHBN REFCLK_GXBL1F_CHTP REFCLK_GXBL1F_CHTN GXBR1F_TX_CH5N GXBR1F_TX_CH5P GXBR1F_RX_CH5N GXBR1F_RX_CH5P GXBR1F_TX_CH4N GXBR1F_TX_CH4P GXBR1F_RX_CH4N GXBR1F_RX_CH4P GXBR1F_TX_CH3N GXBR1F_TX_CH3P GXBR1F_RX_CH3N GXBR1F_RX_CH3P GXBR1F_TX_CH2N
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 34

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Pin Name PIN_AH49 PIN_AJ42 PIN_AJ43 PIN_AL46 PIN_AL47 PIN_AH44 PIN_AH45 PIN_AK48 PIN_AK49 PIN_AL42 PIN_AL43 PIN_AM38 PIN_AM37

Schematic Signal Name FAD20C2MP FAD20M2CN FAD20M2CP FAD19C2MN FAD19C2MP FAD19M2CN FAD19M2CP FAD18C2MN FAD18C2MP FAD18M2CN FAD18M2CP REFCLK0_FMC_P REFCLK0_FMC_N

Direction Output Input Input Output Output Input Input Output Output Input Input Input Input

Table 21. FMC+ B Slot FPGA Pin Map

Pin Name

Schematic Signal Name

PIN_V38

FBGBTCLK0M2CP

PIN_V37

FBGBTCLK0M2CN

PIN_W46

FBD5C2MN

PIN_W47

FBD5C2MP

PIN_Y44

FBD5M2CN

PIN_Y45

FBD5M2CP

PIN_AB48

FBD4C2MN

PIN_AB49

FBD4C2MP

PIN_W42

FBD4M2CN

PIN_W43

FBD4M2CP

PIN_AA46

FBD3C2MN

PIN_AA47

FBD3C2MP

PIN_AB44

FBD3M2CN

PIN_AB45

FBD3M2CP

PIN_AD48

FBD2C2MN

PIN_AD49

FBD2C2MP

PIN_AA42

FBD2M2CN

PIN_AA43

FBD2M2CP

PIN_AC46

FBD1C2MN

Direction Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output

Description GXBR1F_TX_CH2P GXBR1F_RX_CH2N GXBR1F_RX_CH2P GXBR1F_TX_CH1N GXBR1F_TX_CH1P GXBR1F_RX_CH1N GXBR1F_RX_CH1P GXBR1F_TX_CH0N GXBR1F_TX_CH0P GXBR1F_RX_CH0N GXBR1F_RX_CH0P REFCLKI_GXBL1F_CHBP REFCLKI_GXBL1F_CHBN
Description REFCLK_GXBL1K_CHTP REFCLK_GXBL1K_CHTN GXBR1K_TX_CH5N GXBR1K_TX_CH5P GXBR1K_RX_CH5N GXBR1K_RX_CH5P GXBR1K_TX_CH4N GXBR1K_TX_CH4P GXBR1K_RX_CH4N GXBR1K_RX_CH4P GXBR1K_TX_CH3N GXBR1K_TX_CH3P GXBR1K_RX_CH3N GXBR1K_RX_CH3P GXBR1K_TX_CH2N GXBR1K_TX_CH2P GXBR1K_RX_CH2N GXBR1K_RX_CH2P GXBR1K_TX_CH1N
continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 35

Pin Name PIN_AC47 PIN_AD44 PIN_AD45 PIN_AE46 PIN_AE47 PIN_AC42 PIN_AC43 PIN_Y38
PIN_Y37
PIN_AB41 PIN_AB40 PIN_R46 PIN_R47 PIN_M44 PIN_M45 PIN_P48 PIN_P49 PIN_R42 PIN_R43 PIN_T48 PIN_T49 PIN_P44 PIN_P45 PIN_U46 PIN_U47 PIN_T44 PIN_T45 PIN_V48 PIN_V49 PIN_U42 PIN_U43 PIN_Y48 PIN_Y49

4. Development Kit Components UG-20081 | 2020.09.08

Schematic Signal Name

Direction

FBD1C2MP

Output

FBD1M2CN

Input

FBD1M2CP

Input

FBD0C2MN

Output

FBD0C2MP

Output

FBD0M2CN

Input

FBD0M2CP

Input

CLEARNER_XVRL_122.88MH Input Z_P

CLEARNER_XVRL_122.88MH Input Z_N

FBGBTCLK1M2CP

Input

FBGBTCLK1M2CN

Input

FBD11C2MN

Output

FBD11C2MP

Output

FBD11M2CN

Input

FBD11M2CP

Input

FBD10C2MN

Output

FBD10C2MP

Output

FBD10M2CN

Input

FBD10M2CP

Input

FBD9C2MN

Output

FBD9C2MP

Output

FBD9M2CN

Input

FBD9M2CP

Input

FBD8C2MN

Output

FBD8C2MP

Output

FBD8M2CN

Input

FBD8M2CP

Input

FBD7C2MN

Output

FBD7C2MP

Output

FBD7M2CN

Input

FBD7M2CP

Input

FBD6C2MN

Output

FBD6C2MP

Output

Description GXBR1K_TX_CH1P GXBR1K_RX_CH1N GXBR1K_RX_CH1P GXBR1K_TX_CH0N GXBR1K_TX_CH0P GXBR1K_RX_CH0N GXBR1K_RX_CH0P REFCLK_GXBL1K_CHBP
REFCLK_GXBL1K_CHBN
REFCLK_GXB1L_CHTP REFCLK_GXB1L_CHTN GXBR1L_TX_CH5N GXBR1L_TX_CH5P GXBR1L_RX_CH5N GXBR1L_RX_CH5P GXBR1L_TX_CH4N GXBR1L_TX_CH4P GXBR1L_RX_CH4N GXBR1L_RX_CH4P GXBR1L_TX_CH3N GXBR1L_TX_CH3P GXBR1L_RX_CH3N GXBR1L_RX_CH3P GXBR1L_TX_CH2N GXBR1L_TX_CH2P GXBR1L_RX_CH2N GXBR1L_RX_CH2P GXBR1L_TX_CH1N GXBR1L_TX_CH1P GXBR1L_RX_CH1N GXBR1L_RX_CH1P GXBR1L_TX_CH0N GXBR1L_TX_CH0P
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 36

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Pin Name PIN_V44 PIN_V45 PIN_AD41 PIN_AD40 PIN_V41 PIN_V40 PIN_J46 PIN_J47 PIN_F44 PIN_F45 PIN_H48 PIN_H49 PIN_J42 PIN_J43 PIN_L46 PIN_L47 PIN_H44 PIN_H45 PIN_K48 PIN_K49 PIN_L42 PIN_L43 PIN_N46 PIN_N47 PIN_K44 PIN_K45 PIN_M48 PIN_M49 PIN_N42 PIN_N43 PIN_Y41 PIN_Y40 PIN_P41 PIN_P40

Schematic Signal Name FBD6M2CN FBD6M2CP FBGBTCLK5M2CP FBGBTCLK5M2CN FBGBTCLK2M2CP FBGBTCLK2M2CN FBD17C2MN FBD17C2MP FBD17M2CN FBD17M2CP FBD16C2MN FBD16C2MP FBD16M2CN FBD16M2CP FBD15C2MN FBD15C2MP FBD15M2CN FBD15M2CP FBD14C2MN FBD14C2MP FBD14M2CN FBD14M2CP FBD13C2MN FBD13C2MP FBD13M2CN FBD13M2CP FBD12C2MN FBD12C2MP FBD12M2CN FBD12M2CP FBGBTCLK4M2CP FBGBTCLK4M2CN FBGBTCLK3M2CP FBGBTCLK3M2CN

Direction Input Input Input Input Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Input Input Input Input

Description GXBR1L_RX_CH0N GXBR1L_RX_CH0P REFCLK_GXBL1L_CHBP REFCLK_GXBL1L_CHBN REFCLK_GXBL1M_CHBP REFCLK_GXBL1M_CHBN GXBR1M_TX_CH5N GXBR1M_TX_CH5P GXBR1M_RX_CH5N GXBR1M_RX_CH5P GXBR1M_TX_CH4N GXBR1M_TX_CH4P GXBR1M_RX_CH4N GXBR1M_RX_CH4P GXBR1M_TX_CH3N GXBR1M_TX_CH3P GXBR1M_RX_CH3N GXBR1M_RX_CH3P GXBR1M_TX_CH2N GXBR1M_TX_CH2P GXBR1M_RX_CH2N GXBR1M_RX_CH2P GXBR1M_TX_CH1N GXBR1M_TX_CH1P GXBR1M_RX_CH1N GXBR1M_RX_CH1P GXBR1M_TX_CH0N GXBR1M_TX_CH0P GXBR1M_RX_CH0N GXBR1M_RX_CH0P REFCLK_GXBL1N_CHBP REFCLK_GXBL1N_CHBN REFCLK_GXBL1N_CHTP REFCLK_GXBL1N_CHTN
continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 37

4. Development Kit Components UG-20081 | 2020.09.08

Pin Name PIN_B44 PIN_B45 PIN_B40 PIN_B41 PIN_C46 PIN_C47 PIN_A42 PIN_A43 PIN_E46 PIN_E47 PIN_C42 PIN_C43 PIN_D48 PIN_D49 PIN_E42 PIN_E43 PIN_G46 PIN_G47 PIN_D44 PIN_D45 PIN_F48 PIN_F49 PIN_G42 PIN_G43 PIN_T41 PIN_T40

Schematic Signal Name FBD23C2MN FBD23C2MP FBD23M2CN FBD23M2CP FBD22C2MN FBD22C2MP FBD22M2CN FBD22M2CP FBD21C2MN FBD21C2MP FBD21M2CN FBD21M2CP FBD20C2MN FBD20C2MP FBD20M2CN FBD20M2CP FBD19C2MN FBD19C2MP FBD19M2CN FBD19M2CP FBD18C2MN FBD18C2MP FBD18M2CN FBD18M2CP REFCLK1_FMC_P REFCLK1_FMC_N

Direction Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input Input Input

Description GXBR1N_TX_CH5N GXBR1N_TX_CH5P GXBR1N_RX_CH5N GXBR1N_RX_CH5P GXBR1N_TX_CH4N GXBR1N_TX_CH4P GXBR1N_RX_CH4N GXBR1N_RX_CH4P GXBR1N_TX_CH3N GXBR1N_TX_CH3P GXBR1N_RX_CH3N GXBR1N_RX_CH3P GXBR1N_TX_CH2N GXBR1N_TX_CH2P GXBR1N_RX_CH2N GXBR1N_RX_CH2P GXBR1N_TX_CH1N GXBR1N_TX_CH1P GXBR1N_RX_CH1N GXBR1N_RX_CH1P GXBR1N_TX_CH0N GXBR1N_TX_CH0P GXBR1N_RX_CH0N GXBR1N_RX_CH0P REFCLK_GXBL1N_CHBP REFCLK_GXBL1N_CHBN

4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins)
All LVDS interface signals except the LAP/N33, LAP/N32 signals from FMC+ A are directly connected to FPGA I/O ports. For the PCIE ED port application, PCIEA_EP_PERSTn and PCIEA_WAKEN are connected to System MAX10 IO through LAP/N33 signals.
LAP/N32 signals are shorted together into PCIE_present. All LA P/N except LAP/ N33, LAP/N32 signals from FMC+B are directly connected to FPGA I/O ports. For a PCIE ED port application, PCIEA_EP_PERSTn and PCIEA_WAKEN are connected to System MAX10 I/O through FALP/N33 signals. LP/N32 signals are short together into PCIE_present.

Intel® Stratix® 10 SX SoC Development Kit User Guide 38

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Most HB and HA signals from FMC+B are connected to System MAX10 I/O. You must write the code to map these signals to the I/O ports of FPGA.

Table 22. FMC+ A/B Port FPGA Map

PIN_AP21

Pin Name

Schematic Signal Name FALAN20

PIN_AN21

FALAP20

PIN_BG20 PIN_BF20

FALAN25 FALAP25

PIN_BD18

FALAN19

PIN_BE18 PIN_BG19

FALAP19 FALAN21

PIN_BG18

FALAP21

PIN_BH21 PIN_BH20

FALAN24 FALAP24

PIN_BH17

FALAN18

PIN_BG17

FALAP18

PIN_BJ20

FALAN27

PIN_BJ19

FALAP27

PIN_BJ18

FALAN26

PIN_BH18

FALAP26

PIN_AT16

FALAN11

PIN_AT15

FALAP11

PIN_AN18

FALAN15

PIN_AN17 PIN_AU17

FALAP15 FALAN17

PIN_AT17

FALAP17

PIN_AU28 PIN_AU29

FALAN12 FALAP12

PIN_BA30

FALAN9

PIN_BA31 PIN_BC32

FALAP9 FALAN3

PIN_BC31

FALAP3

PIN_AW31 PIN_AW30

FALAN0 FALAP0

PIN_BD31

FA_LA_DEVCLK_N

Description

FMCA LA LVDS

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 39

Pin Name PIN_BE31 PIN_BF30 PIN_BF31 PIN_BD30 PIN_BC30 PIN_BH30 PIN_BG30 PIN_BF32 PIN_BE32 PIN_BG32 PIN_BH32 PIN_BD36 PIN_BE36 PIN_BC35 PIN_BC36 PIN_BB34 PIN_BB33 PIN_BF35 PIN_BF36 PIN_BG35 PIN_BH35 PIN_BE34 PIN_BE33 PIN_BJ36 PIN_BJ35 PIN_AT32 PIN_AU32 PIN_AU35 PIN_AV35 PIN_AY13 PIN_AW13 PIN_AV12 PIN_AV11 PIN_AY12

4. Development Kit Components UG-20081 | 2020.09.08

Schematic Signal Name FA_LA_DEVCLK_P FALAN6 FALAP6 FALAN4 FALAP4 FALAN5 FALAP5 FALAN7 FALAP7 FALAN8 FALAP8 FALAN31 FALAP31 FALAN23 FALAP23 FALAN10 FALAP10 FALAN29 FALAP29 FALAN32_FPGA FALAP32_FPGA FALAN33_FPGA FALAP33_FPGA FALAN22 FALAP22 FALAN14 FALAP14 FALAN30 FALAP30 FAHAN14 FAHAP14 FAHAN18 FAHAP18 FAHAN20

Description

FMCA LA LVDS

FMCA HA LVDS

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 40

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Pin Name PIN_BA12 PIN_BA11 PIN_BA10 PIN_AW11 PIN_AY11 PIN_BB12 PIN_BC12 PIN_BB10 PIN_BC10 PIN_BB20 PIN_BC20 PIN_AY21 PIN_AW21 PIN_AW20 PIN_AW19 PIN_BA19 PIN_BB19 PIN_AU20 PIN_AT20 PIN_BD20 PIN_BD19 PIN_BB18 PIN_BC18 PIN_AV20 PIN_AV21 PIN_BF17 PIN_BE17 PIN_AV28 PIN_AW28 PIN_AV30 PIN_AU30 PIN_AY32 PIN_AY31 PIN_BE29

Schematic Signal Name FAHAP20 FAHAN21 FAHAP21 FAHAN17 FAHAP17 FAHAN0 FAHAP0 FAHAN1 FAHAP1 FAHAN2 FAHAP2 FAHAN11 FAHAP11 FAHAN10 FAHAP10 FAHAN15 FAHAP15 FAHAN19 FAHAP19 FAHAN6 FAHAP6 FAHAN23 FAHAP23 FAHAN16 FAHAP16 FAHAN22 FAHAP22 FAHAN12 FAHAP12 FAHAN5 FAHAP5 FAHAN9 FAHAP9 FAHAN7

Description

FMCA HA LVDS

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 41

Pin Name PIN_BD29 PIN_BJ31 PIN_BH31 PIN_BB29 PIN_BB30 PIN_AV32 PIN_AV33 PIN_BF19 PIN_BE19 PIN_AR16 PIN_AR17 PIN_BB25 PIN_BA25 PIN_BB27 PIN_BC27 PIN_AW29 PIN_AY29 PIN_BB28 PIN_BA29 PIN_AT30 PIN_AT29 PIN_BB32 PIN_BA32 PIN_BG28 PIN_BG29 PIN_BE28 PIN_BF29 PIN_BJ29 PIN_BJ30 PIN_BH28 PIN_BJ28 PIN_BD35 PIN_BD34 PIN_BC33

4. Development Kit Components UG-20081 | 2020.09.08

Schematic Signal Name FAHAP7 FAHAN13 FAHAP13 FAHAN3 FAHAP3 FAHAN4 FAHAP4 FAHBN1 FAHBP1 FAHBN16 FAHBP16 FAHBN6 FAHBP6 FAHBN19 FAHBP19 FAHBN2 FAHBP2 FAHBN3 FAHBP3 FAHBN0 FAHBP0 FAHBN5 FAHBP5 FAHBN15 FAHBP15 FAHBN10 FAHBP10 FAHBN14 FAHBP14 FAHBN18 FAHBP18 FAHBN4 FAHBP4 FAHAN8

Description

FMCA HA LVDS

FMCA HB LVDS

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 42

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4. Development Kit Components UG-20081 | 2020.09.08
Pin Name PIN_BD33 PIN_AY33 PIN_AW33 PIN_BA35 PIN_BB35 PIN_AY36 PIN_BA36 PIN_BF34 PIN_BG34 PIN_BJ34 PIN_BJ33 PIN_AT34 PIN_AT35 PIN_AR31 PIN_AR32 PIN_AU33 PIN_AU34 PIN_AT19 PIN_AR19 PIN_BE21 PIN_BF21 PIN_AY17 PIN_AY40 PIN_BA40 PIN_BA39 PIN_BB39 PIN_BB40 PIN_BC40 PIN_BD38 PIN_BD39 PIN_BC38 PIN_BB38 PIN_BC37 PIN_BB37

Schematic Signal Name FAHAP8 FAHBN8 FAHBP8 FAHBN21 FAHBP21 FAHBN20 FAHBP20 FAHBN12 FAHBP12 FAHBN9 FAHBP9 FAHBN11 FAHBP11 FAHBN7 FAHBP7 FAHBN17 FAHBP17 FACLK1M2CN FACLK1M2CP FACLK0M2CN FACLK0M2CP FACLKDIR FBLAN3 FBLAP3 FBLAN20 FBLAP20 FBLAN11 FBLAP11 FBLAN12 FBLAP12 FBLAN15 FBLAP15 FBLAN27 FBLAP27

Description

FMCA HB LVDS

FMCA M2C Clk1N

FMCA M2C Clk1P

FMCA M2C Clk0N

FMCA M2C Clk0P

FMCA CLK DIR

FMCB LA LVDS

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 43

Pin Name PIN_BD40 PIN_BE40 PIN_BG38 PIN_BG37 PIN_BE38 PIN_BE39 PIN_BE37 PIN_BF37 PIN_BF39 PIN_BF40 PIN_BH37 PIN_BH36 PIN_AW39 PIN_AW38 PIN_BA37 PIN_AY37 PIN_AV40 PIN_AW40 PIN_AY39 PIN_AY38 PIN_AU37 PIN_AU38 PIN_AV38 PIN_AV37 PIN_AR34 PIN_AP35 PIN_AR36 PIN_AP36 PIN_AP33 PIN_AN33 PIN_AT36 PIN_AT37 PIN_AR37 PIN_AT38

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Schematic Signal Name FBLAN8 FBLAP8 FBLAN2 FBLAP2 FBLAN4 FBLAP4 FBLAN16 FBLAP16 FBLAN7 FBLAP7 FBLAN0 FBLAP0 FB_LA_DEVCLK_N FB_LA_DEVCLK_P FBLAN22 FBLAP22 FBLAN9 FBLAP9 FBLAN19 FBLAP19 FAHBN13 FAHBP13 FBLAN26 FBLAP26 FBLAN23 FBLAP23 FBLAN18 FBLAP18 FBLAN10 FBLAP10 FBLAN13 FBLAP13 FBLAN6 FBLAP6

Description

FMCB LA LVDS

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 44

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Pin Name PIN_AR33 PIN_AP34 PIN_AT25 PIN_AU25 PIN_AW25 PIN_AV25 PIN_AT26 PIN_AR26 PIN_AU27 PIN_AT27 PIN_AY26 PIN_AW26 PIN_AN26 PIN_AP26 PIN_AN25 PIN_AP25 PIN_AP29 PIN_AP28 PIN_AR27 PIN_AR28 PIN_AP31 PIN_AP30 PIN_BA26 PIN_BA27

Schematic Signal Name FBLAN5 FBLAP5 FBLAN30 FBLAP30 FBLAN29 FBLAP29 FBLAN24 FBLAP24 FBLAN25 FBLAP25 FBLAN21 FBLAP21 FBLAN28 FBLAP28 FBLAN31 FBLAP31 FBLAN32_FPGA FBLAP32_FPGA FBLAN33_FPGA FBLAP33_FPGA FBLAN14 FBLAP14 FBLAN17 FBLAP17

Description FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS FMCB LA LVDS

4.7.10. LMK05028 Jitter Attenuator
The LMK05028 device is a high-performance clock generator, jitter cleaner, and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications.
The ultra-low jitter reduces bit error rates (BER) in high-speed serial links and improves signal to noise ratio (SNR) when clocking high-speed data converters.
The device has two independent PLL cores that can each synchronize or lock to one of four reference clock inputs, and the LMK05028 can generate up to eight output clocks with up to six different frequencies.

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You can use the FPGA I2C port at FPGA pins BC25, BC26 to control LMK05028. LMK05028 3.3V I/O signals are connected to System MAX10 (U43) IO ports. You need to write code to connect these I/Os to FPGA 1.8V I/O ports. The J21 10-pin Header is used to connect the TI 05028 GUI port. You can use it to configure LMK05028.

Clock outputs from I/O ports (AW35, AW34, BA34, and AY34 pins) in 2B bank are connected to TI LMK05028.

The following table lists the cleaner output signal pin assignments:

Table 23. LMK05028 Clock Cleaner Output Pin Frequencies and Pin Assignments

Output 0 1 2 3 4 5 6 7

Frequency 245 MHz or 297/1.001 MHz 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz 297 MHz 644.53125 MHz

Pin Assignments AF9, AF10 in 4E Bank Y38, Y37 in 1K Bank AT41, AT40 in 1C Bank D8, D9 (FALAP1, FALAN1) in FMCA D8, D9 (FBLAP1, FBLAN1) in FMCB AK12, AK 13 in 4E Bank AK12, AK 13 in 4E Bank P9, P10 in bank 4M

TI LMH1983 is used to generate SDI reference clocks. Four 3.3V IO signals (U43 pins: E17, F17, B21, B22) in the MAX10 system controller are connected to the LMH1983 FIN, VIN, HIN and INIT input pins. SDI users need to write code to map the four 3.3V IOs to the FGPA 1.8V IOs. The 27 MHz output clock is directly connected to clock cleaner input 2. The 148.5 MHz clock is connected to U15AN28 and An27 in IO bank 2F. The clock cleaner application can be found at this link.
Related Information
LMK05028 Network Clock Generator and Synchronizer Evaluation Module

4.7.11. FPGA-IOMAX10 Interface
The I/O signals of the transceiver I/O banks and the 14 I/O ports in 3A banks are connected to System Intel MAX 10.
The figure below illustrates the signal connections between Intel MAX 10 and Intel Stratix 10 SX SoC. You can write your own code to map User I/O to these pins.

Intel® Stratix® 10 SX SoC Development Kit User Guide 46

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pcie_wake_n pcie_prsnt2n pceib_waken pceia_waken
sfpa_txfault sfpa_los
sfpa_mod0_prsntn sfpa_ratese0 sfpa_ratesel1 sfpa_en
sfpa_txdisable
zqsfp1_modprsl zqsfp1_intl
zqsfp1_lpmode zqsfp1_resetl
zqsfp1_modsell
zqsfp0_modprsl zqsfp0_intl
zqsfp0_lpmode zqsfp0_resetl
zqsfp0_modsell

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Figure 5.

Signal Connections
MAX1619

ZQSFP0

ZQSFP1

SFP

PCIE

fan_control overtempn tsense_alertn

poweron_flag
pcie_powerup_perstn bf_presentn

matombio[0] matombio[1]
matombio[2] matombio[3] matombio[4]
matombio[5]

Power MAX10

System MAX10

fpga_pcie_perstn

1v8_io_mux16 1v8_io_mux17 1v8_io_mux18 1v8_io_mux19 1v8_io_mux20
1v8_io_mux21 1v8_io_mux22 1v8_io_mux23 1v8_io_mux24 1v8_io_mux25 1v8_io_mux26 1v8_io_mux27
fpga_max10_io5 fpga_max10_io6 fpga_max10_io7
fpga_max10_io8 fpga_max10_io9
fpga_max10_io10 fpga_max10_io11 fpga_max10_io12 fpga_max10_io13 fpga_max10_io14

Table 24. FPGA-IOMAX10 Pin Map

Pin Name

Schematic Signal Name

PIN_AJ34

NPERSTL0

PIN_AG35

1V8_IO_MUX0

PIN_AH33

1V8_IO_MUX1

PIN_AF34

1V8_IO_MUX2

PIN_AE36

1V8_IO_MUX3

PIN_AG34

1V8_IO_MUX4

PIN_AH32

1V8_IO_MUX5

PIN_AJ33

1V8_IO_MUX6

PIN_AD34

NPERSTL2

PIN_AD35

1V8_IO_MUX7

PIN_AC35

1V8_IO_MUX8

PIN_AB34

1V8_IO_MUX9

PIN_AC33

1V8_IO_MUX10

PIN_AC36

1V8_IO_MUX11

PIN_AB35

1V8_IO_MUX12

PIN_AB36

1V8_IO_MUX13

FPGA

Description

System MAX10_IO

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 47

Pin Name PIN_AH16 PIN_AF15 PIN_AB12 PIN_AF17 PIN_AD16 PIN_AF16 PIN_AE16 PIN_AH17 PIN_AE14 PIN_AD15 PIN_AC15 PIN_AC14 PIN_AB13 PIN_AD14 PIN_AB15 PIN_AB14 PIN_BD13 PIN_BE13 PIN_BF15 PIN_BG15 PIN_BE14 PIN_BF14 PIN_BE16 PIN_BF16 PIN_BD16 PIN_BC16 PIN_BD14 PIN_BD15 PIN_BF12 PIN_BG12 PIN_BJ13 PIN_BJ14 PIN_BG13 PIN_BG14

Schematic Signal Name NPERSTR0 1V8_IO_MUX14 1V8_IO_MUX15 1V8_IO_MUX16 1V8_IO_MUX17 1V8_IO_MUX18 1V8_IO_MUX19 1V8_IO_MUX20 NPERSTR2 1V8_IO_MUX21 1V8_IO_MUX22 1V8_IO_MUX23 1V8_IO_MUX24 1V8_IO_MUX25 1V8_IO_MUX26 1V8_IO_MUX27 AVST_D0 AVST_D1 AVST_D2 AVST_D3 AVST_D4 AVST_D5 AVST_D6 AVST_D7 AVST_D8 AVST_D9 AVST_D10 AVST_D11 AVST_D12 AVST_D13 AVST_D14 AVST_D15 FPGA_MAX10_IO0 FPGA_MAX10_IO1

Intel® Stratix® 10 SX SoC Development Kit User Guide 48

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Description

System MAX10_IO

continued...

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Pin Name PIN_BH15 PIN_BJ15 PIN_BH12 PIN_BH13 PIN_BH16 PIN_BJ16 PIN_AV15 PIN_AW15 PIN_BA15 PIN_BA16 PIN_AW14 PIN_AY14 PIN_BB14 PIN_BA14 PIN_BB15 PIN_BC15 PIN_BC13 PIN_BA17 PIN_AY16 PIN_AY19

Schematic Signal Name FPGA_MAX10_IO2 FPGA_MAX10_IO3 ENETA_INTN_B AVST_VALID CLK_50M_FPGA FPGA_MAX10_IO5 FPGA_MAX10_IO6 FPGA_MAX10_IO7 FPGA_MAX10_IO8 FPGA_MAX10_IO9 FPGA_MAX10_IO10 FPGA_MAX10_IO11 FPGA_MAX10_IO12 FPGA_MAX10_IO13 FPGA_MAX10_IO14 GLOBAL_RESETN FPGA_PR_REQUEST FPGA_PR_DONE FPGA_PR_ERROR AVST_CLK

Description System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO System MAX10_IO

4.8. Daughter Cards
4.8.1. HPS IO-48 OOBE Daughter Card
This is a daughter card for the Intel Stratix 10 SoC IO48 interface. The two types of Intel Stratix 10 SoC Development Kit IO48 daughter cards are OOBE and NAND Flash. These IO48 daughter cards are plugged into the Samtec IO48 connector.

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Intel® Stratix® 10 SX SoC Development Kit User Guide 49

Figure 6. HPS IO-48 OOBE Daughter Card Picture

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Feature Summary

Table 25. IO48 OOBE Daughter Card Feature Summary

Feature IO48 Connector 10/100/1000 Mbps Ethernet PHY with RGMII interface
UART Micro-SD Card Connector USB 2.0
JTAG
I2C

Description

· Samtec QTH-030 Series 60-pin connector on IO48 daughter card side · Samtec QSH-030 Series 60-pin connector on motherboard

· Microchip KSZ9031RNX Ethernet PHY · RGMII MAC Interface · MDC/MDIO Management Interface · Standard RJ-45 with Integrated Ethernet Transformer

· FTDI FT232R UART USB Convertor · Standard USB Mini-B Receptacle

· 4-bit SD card Data Bus · Standard Micro SD Card Socket

· Microchip USB3320 USB 2.0 PHY · ULPI interface connects the USB PHY to Intel Stratix 10 HPS IO48 interface · Standard USB Micro-AB Receptacle · VBUS current limitation when VBUS is sourced to peripheral device

· Mictor 38-pin connector pinouts (JTAG only without Trace signals) · Two JTAG target with resisters MUX
-- FPGA chained JTAG pins in SDM -- HPS dedicated JTAG pins in IO48 (by default)

· HPS I2C and FPGA I2C are connected on the motherboard

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 50

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GPIO

Feature

HPS Clock Mechanical

Description
· 2 Push Buttons · 3 LEDs · 1 Ethernet Interrupt from Ethernet PHY · 1 USB over-current indicator
On-board 25 MHz oscillator provides HPS clock
3" x 1.8" board size

Figure 7. OOBE Daughter Card Block Diagram

FPGA_JTAG (SDM) HPS_JTAG (IO48)

Resistor Multiplexer

MICTOR_JTAG

Mictor 38P

USB ULPI (IO48)

To Motherboard

Samtec QTH-030

Connector

UART_TX, UART_RX (IO48) RGMII + MDC/MDIO (IO48)

SDMMC 4 bit (IO48) HPS_OSC_CLK (IO48) GPIO (IO48)

Microchip USB3320 USB PHY
FTDI FT232R UART-USB
Microchip KSZ9031RNX 10/100/100 Mbps Ethernet PHY
Level Shifter
25 MHz Oscillator
Pushbuttons LEDs

USB v2.0 USB UART
Ethernet RJ-45 with Transformer
MicroSD

IO48 Interface

Stratix 10 SoC IO48 bank can be multiplexed to different peripheral interfaces. The OOBE daughter card is mulitplexed with USB 2.0, Ethernet RGMII, UART, I2C, JTAG,
MicroSD card and GPIO interfaces.

Table 26. IO48 Pinout MUX

HPS Pin Name Q1_1

USB0

Peripheral Name

CLK

Q1_2

USB0

STP

Q1_3

USB0

DIR

Signal continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 51

HPS Pin Name Q1_4 Q1_5 Q1_6 Q1_7 Q1_8 Q1_9 Q1_10 Q1_11 Q1_12 Q2_1 Q2_2 Q2_3 Q2_4 Q2_5 Q2_6 Q2_7 Q2_8 Q2_9 Q2_10 Q2_11 Q2_12 Q3_1 Q3_2 Q3_3 Q3_4 Q3_5 Q3_6 Q3_7 Q3_8 Q3_9 Q3_10 Q3_11 Q3_12 Q4_1

Peripheral Name USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 EMAC0 GPIO1 GPIO1 UART0 UART0 GPIO1 GPIO1 I2C1 I2C1 JTAG JTAG JTAG JTAG SDMMC

DATA0 DATA1 NXT DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 TX_CLK TX_CTL RX_CLK RX_CTL TXD0 TXD1 RXD0 RXD1 TXD2 TXD3 RXD2 RXD3 IO0 IO1 TX RX IO4 IO5 SDA SCL TCK TMS TDO TDI DATA0

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Signal
continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 52

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HPS Pin Name Q4_2 Q4_3 Q4_4 Q4_5 Q4_6 Q4_7 Q4_8 Q4_9 Q4_10 Q4_11 Q4_12

Peripheral Name SDMMC SDMMC SDMMC SDMMC SDMMC CM GPIO1 GPIO1 GPIO1 MDIO0 MDIO0

CMD CCLK DATA1 DATA2 DATA3 HPS_OSC_CLK IO19 IO20 IO21 MDIO MDC

Signal

Figure 8.

Connector to Motherboard
To connect between the motherboard and IO48 OOBE daughter card, Samtec QSH/QTH series connectors are applied. Samtec QTH-030 60-pin connector is used on IO48 OOBE daughter card while Samtec QSH-030 60-pin connector is at the motherboard side.
10/100/1000 Mbps Ethernet PHY
This board supports copper RJ-45 10/100/1000 Mbps Ethernet using an external Ethernet PHY Microchip KSZ9031RNX. The PHY-to-MAC interface employs RGMII using Intel Stratix 10 SoC IO48 EMAC0 to transmit and receive data. For management interface, it uses MDC/MDIO interface between EMAC0 and Ethernet PHY.
Ethernet Block Diagram

To Motherboard

Samtec QTH-030 Connector

RGMII + MDC/MDIO (IO48)

Micrel KSZ9031RNX Ethernet PHY

Ethernet RJ-45 with Transformer

Table 27. Ethernet Signals List

Net Name

IO48 Location

Type

ENET_TXD0

Q2_5

ENET_TXD1

Q2_6

ENET_TXD2

Q2_9

ENET_TXD3

Q2_10

ENET_GTX_CLK

Q2_1

Description RGMII Data Transmit Bit 0 RGMII Data Transmit Bit 1 RGMII Data Transmit Bit 2 RGMII Data Transmit Bit 3 RGMII Transmit Reference Clock
continued...

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Net Name ENET_TX_EN
ENET_RXD0 ENET_RXD1 ENET_RXD2 ENET_RXD3 ENET_RX_CLK
ENET_RX_DV
ENET_MDC ENET_MDIO ENET_INTn
ENET_RESETn

IO48 Location Q2_2
Q2_7 Q2_8 Q2_11 Q2_12 Q2_3
Q2_4
Q4_12 Q4_11 Q3_1

Type IN
OUT OUT OUT OUT OUT
OUT
IN INOUT OUT
IN

Description
RGMII Transmit Control (TX_CTL)
RGMII Data Receive Bit 0
RGMII Data Receive Bit 1
RGMII Data Receive Bit 2
RGMII Data Receive Bit 3
RGMII Receive Reference Clock
RGMII Receive Control (RX_CTL)
Management Clock
Management Data
Ethernet PHY Interrupt Output
Ethernet PHY reset input connected to HPS_RESETn

UART

The IO48 OOBE daughter card uses a USB based UART bridge chip (FTDI FT232R) to bridge communication to a host for general UART usage. This chip uses TXD and RXD for transmission and reception of data.

Table 28. UART Signals List

Net Name

IO48 Location

UART_TX

Q3_3

UART_RX

Q3_4

UART_RESETn

IN OUT IN

Type

Description
UART TX from Intel Stratix 10 HPS to FT232R
UART RX from FT232R to Intel Stratix 10 HPS
FT232R Reset Input connected to HPS_RESETn

Figure 9.

Based on signal direction, HPS IO48's UART_TX is connected to FT232R's RXD pin and HPS IO48's UART_RX is connected to FT232R's TXD.

UART Connection

UART_RX UART_TX

TXD
FT232R RXD

Micro SD Connector
Intel Stratix 10 provides a Secure Digital/ Multimedia Card (SD/MMC) controller for interfacing to external SD/MMC flash cards, secure digital I/O devices and Consumer Electronics Adavnced Transport Architecture (CE-ATA) hard drives.

Intel® Stratix® 10 SX SoC Development Kit User Guide 54

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On IO48 OOBE daughter card, there is a standard MicroSD Memory Card connector that supports 4-bit SD memory interface.

Table 29. MicroSD Card Signal list

Net Name SD_DATA0

IO48 Location Q4_1

SD_DATA1

Q4_4

SD_DATA2

Q4_5

SD_DATA3

Q4_6

SD_CMD

Q4_2

SD_CLK SD_POWER_ON

Q4_3

INOUT

Type

INOUT

IN IN

Description
Bi-directional data signal bit 0
Bi-directional data signal bit 1
Bi-directional data signal bit 2
Bi-directional data signal bit 3
Bi-directional command/ response signal
Host to card clock signal
SD card power ON/OFF control wired to HPS_RESETn

USB 2.0

Intel Stratix 10 HPS provides a USB On-the-Go (OTG) controller that supports both device and host functions. The controller supports all high-speed, full-speed and lowspeed transfers in both device and host modes. Microchip USB 2.0 PHY USB3320 is used on IO48 OOBE daughter card with ULPI interface. A USB 2.0 Micro-AB receptacle to interface external USB host or device.

Table 30. USB 2.0 PHY Signal List

Net Name

IO48 Location

USB_DATA0

Q1_4

USB_DATA1

Q1_5

USB_DATA2

Q1_7

USB_DATA3

Q1_8

USB_DATA4

Q1_9

USB_DATA5

Q1_10

USB_DATA6

Q1_11

USB_DATA7

Q1_12

USB_CLK USB_NXT

Q1_1 Q1_6

INOUT

Type

INOUT

OUT OUT

Description
ULPI bidirectional data bus bit 0
ULPI bidirectional data bus bit 1
ULPI bidirectional data bus bit 2
ULPI bidirectional data bus bit 3
ULPI bidirectional data bus bit 4
ULPI bidirectional data bus bit 5
ULPI bidirectional data bus bit 6
ULPI bidirectional data bus bit 7
ULPI clock output
ULPI next data continued...

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Net Name USB_STP USB_DIR USB_VFLAGn
USB_RESETn

IO48 Location Q1_2 Q1_3 Q3_2

IN OUT OUT

Type

Description
ULPI stop data
ULPI data bus direction
USB over-current limit indicator to HPS IO48 GPIO pin
USB3320 reset input connected to HPS_RESETn

JTAG

The JTAG interface is routed to Mictor 38-pin connector. Other trace signals are not routed to Mictor 38-pin due to the pinout limitation.

There are two JTAG sources for the HPS-JTAG: Mictor 38-pin connector, or SDM chained JTAG pins from the mother board. They are selected with on board resistor MUX by soldering suitable resistors. By default, all resistors are soldered, thus both sources can drive the HPS_JTAG pins.

If Mictor is selected to be the source, the MAX on motherboard can tri-state the FPGA_JTAG pins thus give control to the Probe on Mictor. If MAX is to be the source, no Probe can be connected to the Mictor thus MAX is the only source.

Figure 10. JTAG

IO48 OOBE Daughter Cards

To Motherboard Samtec QTH-030 Connector

FPGA_JTAG Ra = 0 HPS_JTAG Rb = 0

Mictor_JTAG

To Downstream Mictor 38P

Table 31. JTAG Signal List

Net Name HPS_JTAG_TCK

IO48 Location Q3_9

HPS_JTAG_TMS

Q3_10

HPS_JTAG_TDO

Q3_11

HPS_JTAG_TDI

Q3_12

FPGA_JTAG_TCK

FPGA_JTAG_TMS

OUT OUT IN OUT IN IN

Type

Intel® Stratix® 10 SX SoC Development Kit User Guide 56

Description HPS dedicated JTAG TCK on IO48 HPS dedicated JTAG TMS on IO48 HPS dedicated JTAG TDO on IO48 HPS dedicated JTAG TDI on IO48 SDM chained JTAG TCK on SDM bank SDM chained JTAG TMS on SDM bank
continued...
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Net Name FPGA_JTAG_TDO FPGA_JTAG_TDI MICTOR_JTAG_TCK MICTOR_JTAG_TMS MICTOR_JTAG_TDO MICTOR_JTAG_TDI MICTOR_JTAG_TRSTn

IO48 Location

OUT IN IN IN OUT IN IN

Type

Description
SDM chained JTAG TDO on SDM bank
SDM chained JTAG TDI on SDM bank
Mictor JTAG TCK on Mictor Connector
Mictor JTAG TMS on Mictor Connector
Mictor JTAG TDO on Mictor Connector
Mictor JTAG TDI on Mictor Connector
Mictor JTAG TRSTn on Mictor Connector

I2C
The FPGA I2C and HPS I2C are connected on motherboard. HPS I2C left floating on this IO48 OOBE daughter card although it is connected to IO48 connector. A 3-pin 2.54 mm header is reserved on the OOBE daughter card with HPS I2C

GPIO

Remainder GPIO pins on IO48 are used as push buttons and LEDs.

Table 32. IO48 GPIO Signal List

Net Name HPS_PB0

IO48 Location Q3_5

HPS_PB1

Q3_6

HPS_LED0

Q4_9

HPS_LED1

Q4_8

HPS_LED2

Q4_10

ENET_INTn

Q3_1

USB_VFLAGn

Q3_2

OUT OUT IN IN IN OUT OUT

Type

Description
Push Button 0 on daughter card
Push Button 1 on daughter card
LED 0 on daughter card active high
LED 1 on daughter card active high
LED 2 on daughter card active high
Ethernet PHY interrupt output
USB over-current limit indicator to HPS IO48 GPIO pin

HPS Clock
One on board oscillator provides a fixed 25 MHz single-ended clock for HPS PLL input (HPS_OSC_CLK). The OOBE card do not support clock frequency adjustment and external clock injection.

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Figure 11. HPS Clock

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To Motherboard HPS_OSC_CLK

Samtec QTH-030 Connector

HPS_OSC_CLK 25 MHz Oscillator

Power
There are two power rails drawn from motherboard through Samtec connector VCC_12V and VCCIO_HPS.
VCC_12V is major power source for IO48 OOBE daughter card and it will be converted to other power rails with on board regulators. It is recommended to have at least 1 A capability on VCC_12V power rail.
VCCIO_HPS is HPS I/O buffers power supply also from the motherboard. It is 1.8V nominal.
Figure 12. Power Tree

Samtec QTH-030 Connector

VCCIO_HPS 1.8 V/0.5 A
VCC_12 V 1.2 V/0.5 A

LTM4622E 5 A

VCC_5 V 5 V/1.1 A
VCC_3.3 V 3.3 V/1 A

EY1501DI-ADJ 1 A

ENET_VDD1.2 V 1.2 V/0.25 A

Reset

Reset is from Intel MAX 10 CPLD on the Intel Stratix 10 SoC mother board. The Intel MAX 10 controls all device's resets on the devlopment kit.

Figure 13.

Reset Diagram

HPS-1048 Daughter Card

To/From CPLD on Stratix 10 SoC
Motherboard

Samtec QTH-030

HPS_RESETn

Connector

Mictor_SRSTn ENET_RESETn UART_RESETn SD_POWER_ON USB_RESETn

Mictor 38P Ethernet UART USB Convertor SD Card Power Switch
USB

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4.8.2. HPS IO-48 NAND Flash Daughter Card
Figure 14. HPS IO-48 NAND Flash Daughter Card Picture

IO48 NAND Flash Feature Summary

Table 33. Feature Summary

Feature Name IO48 Connector 10/100/1000 Mbps Ethernet PHY with RGMII interface
UART NAND Flash
eMMC
I2C

Description

· Samtec QTH-030 Series 60-pin connector on IO48 daughter card side · Samtec QSH-030 Series 60-pin connector on motherboard

· Microchip KSZ9031RNX Ethernet PHY · RGMII MAC Interface · MDC/MDIO Management Interface · Standard RJ-45 with integrated Ethernet Transformer

· FTDI FT232R UART USB Convertor · Standard USB Mini-B Receptacle

· Micron MT29F8G16ADBDAH4-AIT:D · 1.8V 8 Gb SLC ASYNC NAND Flash · x16 bit data width · VFBGA-63 Package · Multiplexed with eMMC Flash with resistor MUX (Cannot use simultaneously)

· Micron MTFC8GAKAJCN-4M IT · 8 GB 5.0 compliant eMMC · Not support eMMC data strobe due to Intel Stratix 10 HPS limitation · VPFBGA-153 Package

· HPS I2C and FPGA I2C is connected together on the motherboard

continued...

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Feature Name GPIO
HPS Clock Mechanical

Description
· 2 GPIOs as Push Buttons · 3 GPIOs as LEDs · 1 GPIO as Ethernet Interrupt from Ethernet PHY
· 1 On-board 25 MHz oscillator provides HPS clock
· Supposed 3" x 1.8" board size

Block Diagram Figure 15. NAND Daughter Card Block Diagram

NAND/eMMC (IO48)

Resistor Multiplexer

NAND X16 NAND 8 GB X16 SLC MT29F8G16AB BCAH4-IT (1)

eMMC X8

eMMC 8 GB X8 8 MTFC8GAKAJC N-4M IT (2)

To Motherboard Samtec QTH-030 Connector

UART_TX, UART_RX (IO48) RGMII + MDC/MDIO (IO48)

FTDI FT232R UART-USB
Microchip KSZ9031RNX 10/100/100 Mbps Ethernet PHY

USB UART
Ethernet RJ-45 with Transformer

HPS_OSC_CLK (IO48)

25 MHz Oscillator

GPIO (IO48)

Pushbuttons LEDs

Notes: 1. You cannot use the NAND and eMMC connectors at the same time. 2. The eMMC connector is optional.
IO48 Interface
Stratix 10 SoC IO48 bank can be multiplexed to different peripheral interfaces. On NAND daughter card, IO48 bank is interfaced with Ethernet RGMII, UART, I2C, NAND Flash, eMMC and GPIO interfaces.

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Table 34. IO48 Pinout MUX

HPS Pin Name Q1_1

Peripheral Name NAND

Q1_2

NAND

Q1_3

NAND

Q1_4

NAND

Q1_5

NAND

Q1_6

NAND

Q1_7

NAND

Q1_8

NAND

Q1_9

NAND

Q1_10

NAND

Q1_11

NAND

Q1_12

NAND

Q2_1

NAND

Q2_2

NAND

Q2_3

NAND

Q2_4

Q2_5

NAND

Q2_6

NAND

Q2_7

NAND

Q2_8

NAND

Q2_9

NAND

Q2_10

NAND

Q2_11

NAND

Q2_12

NAND

Q3_1

GPIO1

Q3_2

GPIO1

Q3_3

UART0

Q3_4

UART0

Q3_5

GPIO1

Q3_6

GPIO1

Q3_7

I2C1

Q3_8

I2C1

Q3_9

MDIO2

ADQ0 ADQ1 WE_N RE_N WP_N ADQ2 ADQ3 CLE ADQ4 ADQ5 ADQ6 ADQ7 ALE RB CE_N HPS_OSC_CLK ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 IO0 IO1 TX RX IO4 IO5 SDA SCL MDIO

Signal

continued...

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HPS Pin Name Q3_10 Q3_11 Q3_12 Q4_1 Q4_2 Q4_3 Q4_4 Q4_5 Q4_6 Q4_7 Q4_8 Q4_9 Q4_10 Q4_11 Q4_12

Peripheral Name MDIO2 GPIO1 GPIO1 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2 EMAC2

MDC IO10 IO11 TX_CLK TX_CTL RX_CLK RX_CTL TXD0 TXD1 RXD0 RXD1 TXD2 TXD3 RXD2 RXD3

Signal

Connector to Motherboard
To connect between motherboard and IO48 NAND Flash daughter card, Samtec QSH/QTH series connectors are applied. Samtec QTH-030 60-pin connector is used on IO48 NAND Flash daughter card side while Samtec QSH 60-pin is at the mptherboard side.
10/100/1000 Mbps Ethernet PHY
This daughter card supports copper RJ-45 10/100/1000 Mbps Ethernet using an external Ethernet PHY Microchip KSZ9031RNX. The PHY-to-MAC interface employs RGMII using Intel Stratix 10 SoC IO48 EMAC2 to transmit and receive data. For management interface, it uses MDC/MDIO interface between EMAC2 and Ethernet PHY.
Figure 16. Ethernet PHY Block Diagram

To Motherboard

Samtec QTH-030

Connector

RGMII + MDC/MDIO (IO48)

Micrel KSZ9031RNX Ethernet PHY

Ethernet RJ-45 with Transformer

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Table 35. Ethernet Signals List

Net Name ENET_TXD0

IO48 Location Q4_5

ENET_TXD1 ENET_TXD2

Q4_6 Q4_9

ENET_TXD3

Q4_10

ENET_GTX_CLK

Q4_1

ENET_TX_EN

Q4_2

ENET_RXD0 ENET_RXD1 ENET_RXD2 ENET_RXD3 ENET_RX_CLK

Q4_7 Q4_8 Q4_11 Q4_12 Q4_3

ENET_RX_DV

Q4_4

ENET_MDC ENET_MDIO ENET_INTn

Q3_10 Q3_9 Q3_1

UART

Type IN IN IN IN IN
IN
OUT OUT OUT OUT OUT
OUT
IN INOUT OUT

Description RGMII Data Transmit Bit 0
RGMII Data Transmit Bit 1
RGMII Data Transmit Bit 2
RGMII Data Transmit Bit 3
RGMII Transmit Reference Clock RGMII Transmit Control (TX_CTL) RGMII Data Receive Bit 0
RGMII Data Receive Bit 1
RGMII Data Receive Bit 2
RGMII Data Receive Bit 3
RGMII Receive Reference Clock RGMII Receive Control (RX_CTL) Management Clock
Management Data
Ethernet PHY Interrupt Output

Table 36. UART Signals List

Net Name UART_TX

IO48 Location Q3_3

UART_RX

Q3_4

UART_RESETn

IN OUT IN

Type

Description
UART TX from Intel Stratix 10 HPS to FT232R
UART RX from FT232R to Intel Stratix 10 HPS
FT232R reset input connected to HPS_RESETn

Based on the signal direction, HPS IO48's UART_TX is connected to FT232R's RXD pin and HPS IO48's UART_RX is connected to FT232R's TXD.

Figure 17. UART Connection

UART_RX UART_TX

TXD
FT232R RXD

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NAND Flash

The IO48 NAND flash daughter card supports a 16-bit NAND flash. Since some NAND flash pins are mutiplexed with eMMC pins, NAND flash and eMMC flash cannot be used simultaneously. There are MUX resistors to select related IO48 signals are connected to NAND flash or eMMC flash. The default setup is NAND flash.

The proposed NAND flash memory is MT29F8G16ADBDAH4-AIT:D manufactured by Micron. Major parameters are as listed below:

Table 37. NAND Flash Memory Parameters

Paramater Type Density Data Width Voltage Package Operational Temperature

SLC NAND 8 Gb 16-bit 1.8 V VFBGA-63 -40 C to +85 C

Description

An optional NAND socket can be used for easy NAND Flash replacement when NAND flash is not soldered down. The socket vendor is Ironwood with part number SGBGA-6367.

Table 38. NAND Flash Memory Signal List

Net Name NAND_ADQ0

IO48 Location Q1_1

NAND_ADQ1

Q1_2

NAND_ADQ2 NAND_ADQ3

Q1_6 Q1_7

NAND_ADQ4

Q1_9

NAND_ADQ5 NAND_ADQ6

Q1_10 Q1_11

NAND_ADQ7

Q1_12

NAND_ADQ8 NAND_ADQ9

Q2_5 Q2_6

NAND_ADQ10

Q2_7

NAND_ADQ11

Q2_8

NAND_ADQ12

Q2_9

NAND_ADQ13

Q2_10

NAND_ADQ14

Q2_11

NAND_ADQ15

Q2_12

INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT

Type

Direction Bidirectional data bit 0 Bidirectional data bit 1 Bidirectional data bit 2 Bidirectional data bit 3 Bidirectional data bit 4 Bidirectional data bit 5 Bidirectional data bit 6 Bidirectional data bit 7 Bidirectional data bit 8 Bidirectional data bit 9 Bidirectional data bit 10 Bidirectional data bit 11 Bidirectional data bit 12 Bidirectional data bit 13 Bidirectional data bit 14 Bidirectional data bit 15
continued...

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Net Name NAND_WEn NAND_REn NAND_WPn NAND_CLE NAND_ALE NAND_RBn NAND_CEn

IO48 Location Q1_3 Q1_4 Q1_5 Q1_8 Q2_1 Q2_2 Q2_3

IN IN IN IN IN OUT IN

Type

Direction Write Enable Read Enable Write Protect Command Latch Enable Address Latch Enable Ready/Busy Chip Enable

eMMC

The IO48 NAND flash daughter card also supports a 8-bit eMMC flash. Since the eMMC flash pins are multiplexed with NAND pins, NAND Flash and eMMC Flash cannot be used simultaneously. There are MUX resistors to select related IO48 signals are connected to NAND flash or eMMC flash. The default setup is NAND flash, not eMMC.

The proposed eMMC flash memory is MTFC8GAKAJCN-4M IT manufactured by Micron.

Table 39. eMMC Flash Parameters
Parameter Type Density Data Width Voltage Package Operational Temperature

Description eMMC with 5.0-compliant (JESD84-B50) 8 GB 8-bit 3.3 V VCC and 1.8 V/3.3 V VCCQ operation (VCCQ=1.8 V on this card) VFBGA-153 -40 C to +85 C

Table 40. eMMC Signal List

Net Name

IO48 Location

EMMC_D0

Q1_3

EMMC_D1

Q1_4

EMMC_D2

Q1_5

EMMC_D3

Q1_6

EMMC_D4

Q1_7

EMMC_D5

Q1_8

EMMC_D6

Q1_9

INOUT

Type

INOUT

Description
eMMC bidirectional data bus bit
eMMC bidirectional data bus bit
eMMC bidirectional data bus bit
eMMC bidirectional data bus bit
eMMC bidirectional data bus bit
eMMC bidirectional data bus bit
eMMC bidirectional data bus bit
continued...

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Net Name EMMC_D7 EMMC_CLK EMMC_CMD EMMC_DS
EMMC_RSTn

IO48 Location Q1_10
Q1_1 Q1_2

INOUT

Type

IN INOUT

OUT

Description
eMMC bidirectional data bus bit
eMMC clock input
eMMC bi-directional command
eMMC Data Strobe. No Connection. Intel Stratix 10 does not support it.
eMMC reset input. Connected to HPS_RESETn.

Note:

Since Intel Stratix 10 HPS does not support HS400, Data Strobe pin on eMMC flash is not used. HS400 is not supported on this board.

I2C
The FPGA I2C and HPS I2C are connected together on motherboard. HPS I2C left floating on this IO48 debug daughter card although is connected to IO48 connector. A 3-pin 2.54 mm header is reserved with HPS I2C.

GPIO

Table 41. IO48 GPIO Signals List

Net Name HPS_PB0

IO48 Location Q3_5

HPS_PB1

Q3_6

HPS_LED0

Q3_2

HPS_LED1

Q3_11

HPS_LED2

Q3_12

ENET_INTn

Q3_1

OUT OUT IN IN IN OUT

Type

HPS Clock One on-board oscillator provides a fixed 25 MHz single-ended clock for HPS PLL input. Figure 18. Clock Diagram

To Motherboard HPS_OSC_CLK

Samtec QTH-030 Connector

HPS_OSC_CLK 25 MHz Oscillator

Intel® Stratix® 10 SX SoC Development Kit User Guide 66

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Power
There are two power rails drawn from motherboard through Samtec connector VCC_12V and VCCIO_HPS. VCC_12V is major power source and it is converted to other power rails with on-board regulators. It is recommended to have at least 1 A capabiity on VCC_12V power rail.
VCCIO_HPS is HPS I/O buffers power supply from motherboard.
Figure 19. Power Diagram

Samtec QTH-030 Connector

VCCIO_HPS 1.8 V/0.5 A
VCC_12 V 1.2 V/0.5 A

LTM4622E 5 A

VCC_5 V 5 V/1.1 A
VCC_3.3 V 3.3 V/1 A

EY1501DI-ADJ 1 A

ENET_VDD1.2 V 1.2 V/0.25 A

Reset

Reset is from MAX 10 CPLD on Stratix 10 SoC motherboard. The MAX 10 controls all devices' resets on the develpment kit.

Figure 20.

Reset Diagram

HPS-IO48 Daughter Card

To/From CPLD

on Stratix 10 SoC

Motherboard

Samtec HPS_RESETn

QTH-030

Connector

Mictor_SRSTn ENET_RESETn UART_RESETn SD_POWER_ON

Mictor 38P Ethernet UART USB Convertor SD Card Power Switch

4.8.3. HPS Boot Flash Card
The Intel Stratix 10 SoC Boot Flash daughter cards have four independent types as listed below · Boot QSPI Flash · Boot MicroSD · Boot eMMC
Attention: Boot eMMC Flash Card is sold separately and is not included in the development kit package.

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These boot flash daughter cards are connected to the SDM bank of the Intel Stratix 10 FPGA. They are plugged into the Samtec SDM Flash connector.

Table 42. Feature Summary

Feature Card Connector Boot QSPI Flash Card
Boot MicroSD Card Boot eMMC Card Mechanical

Description
· Samtec QSH-030 Series 60-pin connector on Boot Flash daughter cards side · Samtec QTH-030 Series 60-pin connector on the motherboard
· Micron 2 Gb 1.8V QSPI Flash · TPBGA-24 package · Compatible with Intel EPCQ-L devices
· 4-bit SD Card Data Bus · Standard MicroSD Card Socket
· Micron 8 GB eMMC · VFBGA-153 package
· 1.5" x 1"

Connector to Motherboard
To connect between the motherboard and Boot flash daughter card, Samtec QSH/QTH series connectors are used. Samtec QSH-030 60-pin connector is used on boot flash daughter cards while Samtec QTH-030 60-pin connector is at the motherboard side.
Figure 21. Samtec QSH-030

Figure 22. Samtec QTH-030

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Table 43.
1 0

Card Identification

There is one CARD_PRSTn signal on the Boot Flash daughter cards to identify whether card is plugged in. This signal is connected to CPLD on the Intel Stratix 10 SoC development kit.

CARD_PRSTn is pulled high on the motherboard and directly tie to GND on Boot Flash daughter cards.

Card Identification
CARD_PRSTn

Status No daughter card is plugged in One daughter card is plugged in

Power

There are two power rails drawn from motherboard through Samtec connector 3.3 V and 1.8 V.

Table 44. Card Identification

MicroSD QSPI Flash eMMC

Current @ 1.8 V (A) 0.1 0.1

Current @ 3.3 V (A) 0.22 0.05

Total Power (W) 1.32 0.18 0.35

Note:

The power of MicroSD card is estimated at SDR25 (50 MHz).

4.8.3.1. Boot QSPI Flash Daughter Card
This card supports a 2 Gb density QSPI NOR Flash manufactured by Micron. The QSPI NOR Flash uses TPBGA-24 package which is compatible with Intel EPCQ-L devices. To support EPCQ-L devices, you need to change BOM of the board.
The key features of the QSPI Flash used on this board are: · Micron P/N: MT25QU02GCBB8E12-0SIT · 2 Gb NOR Flash · 1.8V QSPI I/O · Operation Temperature: -40 C to +85 C · TPBGA-24 package which is compatible with Intel EPCQ-L devices

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Figure 23. Boot QSPI Flash Daughter Card Picture

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Figure 24.

Boot QSPI Flash Daughter Card Block Diagram
1.8 V I/O SDM QSPI Boot Flash Daughter Card
1.8 V

SDM QSH Connector

Stratix 10 SoC

QSPI Flash MT25QU02GCBB8E12-0SIT

QSPI_RSTn

4.8.3.2. Boot MicroSD Daughter Card
This card suppports a 4-bit Micro SD Card with a Micro SD card socket. There is a voltage level shifter between Intel Stratix 10 SoC SDM bank and MicroSD card which can translate between 1.8 V I/O and 3.3 V I/O.
There is an extra signal called SD_PWR_EN is from CPLD on the Intel Stratix 10 SoC development kit. This signal is used to power cycle/reset MicroSD Card on this board.

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Figure 25. Boot MicroSD Daughter Card Picture

Figure 26.

Boot MicroSD Daughter Card Block Diagram

1.8 V I/O

3.3 V I/O

SDM MicroSD Boot Flash Daughter Card 3.3 V

1.8 V

SDM QSH Connector

Stratix 10 SoC

Level Shifter

3.3 V

Power

SD_PWR_EN Switch

MicroSD Socket
3.3V_SD

4.8.3.3. Boot eMMC Daughter Card
This card supports an 8-bit eMMC Flash manufactured by Micron. The NAND Flash uses VFBGA-153 package.
The key features of the eMMC Flash are: · Micron MTFC8GAKAJCN-4M IT · Type: eMMC with 5.0-compliant (JESD84-B50) · Density: 8 GB · Data Width: 8-bit

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· Voltage: 3.3V VCC and 1.8V/3.3V VCCQ operation · Package: VFBGA-153 · Operation Temperature: -40 C to +85 C

Figure 27.

Boot eMMC Daughter Card Block Diagram
1.8 V I/O SDM eMMC Boot Flash Daughter Card 3.3 V 1.8 V

SDM QSH Connector

Stratix 10 SoC

eMMC Flash MTFC8GAKAJCN-4M IT
EMMC_RSTn

4.9. System Memory

4.9.1. FPGA Memory (DDR4 SO-DIMM)

The 72-bit memory interface connected to the SO-DIMM card is assigned to four I/O banks (3I, 3J, 3K and 3L). The reference clock of the DDR4 port is the 133.33 MHz clock generated by Silicon Lab Si5338. The SODIMM memory part number is MTA18ASF2G72Hz. Its I2C EEPROM Address is 0b1010101. Its Temp Sensor Address is 0b0011101.

Table 45.
PIN_V21 PIN_V22 PIN_T21 PIN_R21 PIN_V23 PIN_V24 PIN_U20 PIN_T20 PIN_R22 PIN_T22 PIN_U23 PIN_E11

SO-DIMM FPGA Pin Map

Pin Name

Schematic Signal Name

SL_DQB3

SL_DQB1

SL_DQB7

SL_DQB6

SL_DQB4

SL_DQB5

SL_DQSN0

SL_DQSP0

SL_DQB0

SL_DQB2

SL_DM0

SL_DQB37

Description

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

continued...

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PIN_F11 PIN_G10 PIN_H10 PIN_D10 PIN_D11 PIN_G12 PIN_H12 PIN_F10 PIN_E10 PIN_F12 PIN_J11 PIN_H11 PIN_K11 PIN_K12 PIN_K10 PIN_J10 PIN_M12 PIN_L12 PIN_L10 PIN_L11 PIN_K13 PIN_N13 PIN_P14 PIN_M13 PIN_M14 PIN_P15 PIN_P16 PIN_P13 PIN_P12 PIN_R16 PIN_R17 PIN_R14 PIN_T19 PIN_U19

Pin Name

Schematic Signal Name SL_DQB33 SL_DQB39 SL_DQB35 SL_DQB36 SL_DQB32 SL_DQSN4 SL_DQSP4 SL_DQB34 SL_DQB38 SL_DM4 SL_DQB56 SL_DQB61 SL_DQB58 SL_DQB59 SL_DQB63 SL_DQB62 SL_DQSN7 SL_DQSP7 SL_DQB60 SL_DQB57 SL_DM7 SL_DQB46 SL_DQB47 SL_DQB41 SL_DQB44 SL_DQB42 SL_DQB40 SL_DQSN5 SL_DQSP5 SL_DQB45 SL_DQB43 SL_DM5 SL_DQB14 SL_DQB9

Description

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 73

PIN_R18 PIN_R19 PIN_W18 PIN_V17 PIN_T17 PIN_U17 PIN_U18 PIN_V18 PIN_T16 PIN_M15 PIN_N15 PIN_K16 PIN_L16 PIN_M18 PIN_M17 PIN_J14 PIN_K14 PIN_H17 PIN_F15 PIN_G15 PIN_J15 PIN_H15 PIN_L14 PIN_H16 PIN_J16 PIN_F16 PIN_E16 PIN_D15 PIN_C15 PIN_B15 PIN_A16 PIN_B13 PIN_B14 PIN_A15

Pin Name

4. Development Kit Components UG-20081 | 2020.09.08

Schematic Signal Name SL_DQB10 SL_DQB11 SL_DQB12 SL_DQB13 SL_DQSN1 SL_DQSP1 SL_DQB15 SL_DQB8 SL_DM1 SL_CK1N SL_CK1P SL_ALERTN SL_EVENTN SL_C1N SL_C0N SL_BG0 SL_BA1 SL_BA0 SL_RASN SL_CASN SL_WEN SL_A13 SL_A12 CLK_EMI_1N CLK_EMI_1P SL_A11 SL_A10 SL_A9 SL_A8 SL_A7 SL_A6 SL_A5 SL_A4 SL_A3

Description

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 Bank 1 ClockN

DDR4 Bank 1 ClockP

DDR4 ALERTn

DDR4 SO-DIMM Eventn

DDR4 Bank 1 C1

DDR4 Bank 0 C0

DDR4 BG0

DDR4 BA1

DDR4 BA0

DDR4 RASN

DDR4 CASN

DDR4 WEN

DDR4 A13

DDR4 A12

DDR4 EMIF Reference Clock N

DDR4 EMIF Reference Clock P

DDR4 A11

DDR4 A10

DDR4 A9

DDR4 A8

DDR4 A7

DDR4 A6

DDR4 A5

DDR4 A4

DDR4 A3

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 74

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PIN_A14 PIN_D16 PIN_C16 PIN_A12 PIN_B12 PIN_D14 PIN_E14 PIN_C12 PIN_C13 PIN_F14 PIN_G14 PIN_D13 PIN_E13 PIN_H13 PIN_G13 PIN_B20 PIN_A19 PIN_B17 PIN_A17 PIN_A21 PIN_A20 PIN_C18 PIN_C17 PIN_B22 PIN_A22 PIN_B19 PIN_E17 PIN_F17 PIN_D18 PIN_E18 PIN_D19 PIN_E19 PIN_C20 PIN_D20

Pin Name

Schematic Signal Name SL_A2 SL_A1 SL_A0 SL_PARITY SL_CS1N SL_CK0N SL_CK0P SL_CKE1 SL_CKE0 SL_ODT1N SL_ODT0N SL_ACTN SL_CS0N SL_RESETN SL_BG1 SL_DQB28 SL_DQB26 SL_DQB27 SL_DQB31 SL_DQB30 SL_DQB24 SL_DQSN3 SL_DQSP3 SL_DQB29 SL_DQB25 SL_DM3 SL_DQB23 SL_DQB19 SL_DQB20 SL_DQB18 SL_DQB16 SL_DQB22 SL_DQSN2 SL_DQSP2

Description

DDR4 A2

DDR4 A1

DDR4 A0

DDR4 Parity

DDR4 BANK 1 CSN

DDR4 BANK 0 Clock N

DDR4 BANK 0 Clock P

DDR4 BANK 1 CKE

DDR4 BANK 0 CKE

DDR4 BANK 1 ODTN

DDR4 BANK 0 ODTN

DDR4 ACTn

DDR4 CS0n

DDR4 SO-DIMM RESETN

DDR4 BG1

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 75

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PIN_D21 PIN_E21 PIN_C21 PIN_J19 PIN_J20 PIN_F19 PIN_G19 PIN_K18 PIN_J18 PIN_F21 PIN_F20 PIN_H18 PIN_G18 PIN_H20 PIN_H21 PIN_J21 PIN_L19 PIN_K19 PIN_L21 PIN_K21 PIN_L20 PIN_M20 PIN_N21 PIN_P21 PIN_N20

Pin Name

Schematic Signal Name SL_DQB17 SL_DQB21 SL_DM2 SL_DQB54 SL_DQB50 SL_DQB52 SL_DQB49 SL_DQB48 SL_DQB53 SL_DQSN6 SL_DQSP6 SL_DQB55 SL_DQB51 SL_DM6 SL_DQB69 SL_DQB68 SL_DQB70 SL_DQB64 SL_DQB71 SL_DQB65 SL_DQSN8 SL_DQSP8 SL_DQB66 SL_DQB67 SL_DM8

Description DDR4 DQ DDR4 DQ DDR4 DM DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQSN DDR4 DQSP DDR4 DQ DDR4 DQ DDR4 DM DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQSN DDR4 DQSP DDR4 DQ DDR4 DQ DDR4 DM

4.9.2. HPS Memory (External 4 GB HILO x72 DDR4 )

The 72-bit HPS DDR4 memory interface (64-bit data and 8-bit ECC data), assigned in FPGA 2L, 2M and 2N I/O banks, is connected to a 4 GB HILO x72 memory daughter card. The target design speed is 1333 MHz DDR4 bus.

Note:

DDR4 HiLo daughter card is not included with H-Tile version of this development kit (DK-SOC-1SSX-H-A) and will be sold separately when available. Please contact Intel you have an urgent need for a card.

Intel® Stratix® 10 SX SoC Development Kit User Guide 76

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Table 46. HPS HILO DDR4 Memory Map

Pin Name PIN_E27

Schematic Signal Name MEM_DMA0

PIN_D26 PIN_G27

MEM_DQA6 MEM_DQA0

PIN_F27

MEM_DQA3

PIN_C27 PIN_B27

MEM_DQA1 MEM_DQA2

PIN_F26

MEM_DQSA_N0

PIN_E26 PIN_B25

MEM_DQSA_P0 MEM_DQA5

PIN_C26

MEM_DQA4

PIN_D25 PIN_L26

MEM_DQA7 MEM_DMA3

PIN_K27

MEM_DQA29

PIN_M27

MEM_DQA24

PIN_L27

MEM_DQA25

PIN_H27

MEM_DQA28

PIN_H26

MEM_DQA30

PIN_K26

MEM_DQSA_N3

PIN_J26

MEM_DQSA_P3

PIN_G25

MEM_DQA26

PIN_F25

MEM_DQA31

PIN_H25 PIN_V30

MEM_DQA27 MEM_DMA1

PIN_U30

MEM_DQA8

PIN_T30 PIN_T29

MEM_DQA9 MEM_DQA10

PIN_U28

MEM_DQA11

PIN_U29 PIN_V27

MEM_DQA15 MEM_DQSA_N1

PIN_V28

MEM_DQSA_P1

PIN_V26 PIN_V25

MEM_DQA14 MEM_DQA12

PIN_U27

MEM_DQA13

Description

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 77

Pin Name PIN_N25 PIN_P25 PIN_P26 PIN_R26 PIN_T25 PIN_U25 PIN_R27 PIN_T26 PIN_M25 PIN_L25 PIN_N27 PIN_U34 PIN_U33 PIN_T31 PIN_R31 PIN_T34 PIN_R34 PIN_T32 PIN_R32 PIN_U32 PIN_V32 PIN_P33 PIN_R36 PIN_T35 PIN_L36 PIN_L35 PIN_P36 PIN_N36 PIN_K37 PIN_K36 PIN_P35 PIN_N35 PIN_M35 PIN_P38

Schematic Signal Name MEM_DMA2 MEM_DQA18 MEM_DQA22 MEM_DQA21 MEM_DQA17 MEM_DQA16 MEM_DQSA_N2 MEM_DQSA_P2 MEM_DQA23 MEM_DQA20 MEM_DQA19 MEM_DQ_ADDR_CMD0 MEM_DQ_ADDR_CMD3 MEM_DQ_ADDR_CMD4 MEM_DQ_ADDR_CMD2 MEM_DQ_ADDR_CMD1 MEM_DQ_ADDR_CMD5 MEM_DQS_ADDR_CMD_N MEM_DQS_ADDR_CMD_P MEM_DQ_ADDR_CMD6 MEM_DQ_ADDR_CMD7 MEM_DQ_ADDR_CMD8 MEM_ADDR_CMD18 MEM_ADDR_CMD17 MEM_ADDR_CMD16 MEM_ADDR_CMD19 MEM_ADDR_CMD26 MEM_ADDR_CMD15 MEM_ADDR_CMD14 MEM_ADDR_CMD13 MEM_ADDR_CMD12 CLK_EMI_N CLK_EMI_P MEM_ADDR_CMD11

4. Development Kit Components UG-20081 | 2020.09.08

Description

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

DDR4 BG0

DDR4 BA1

DDR4 BA0

DDR4 A17

DDR4 A16

DDR4 A15

DDR4 A14

DDR4 A13

DDR4 A12

EMIF Ref clockN

EMIF Ref clockP

DDR4 A11

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide 78

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Pin Name PIN_N37 PIN_R37 PIN_P37 PIN_L39 PIN_K39 PIN_J38 PIN_J39 PIN_M38 PIN_M37 PIN_L37 PIN_K38 PIN_H40 PIN_J40 PIN_G39 PIN_F39 PIN_K40 PIN_L40 PIN_F40 PIN_G40 PIN_H38 PIN_G38 PIN_E40 PIN_D40 PIN_J34 PIN_K34 PIN_N32 PIN_N31 PIN_K33 PIN_K32 PIN_L31 PIN_L32 PIN_N33 PIN_M33 PIN_M34

Schematic Signal Name MEM_ADDR_CMD10 MEM_ADDR_CMD9 MEM_ADDR_CMD8 MEM_ADDR_CMD7 MEM_ADDR_CMD6 MEM_ADDR_CMD5 MEM_ADDR_CMD4 MEM_ADDR_CMD3 MEM_ADDR_CMD2 MEM_ADDR_CMD1 MEM_ADDR_CMD0 MEM_ADDR_CMD31 MEM_ADDR_CMD30 MEM_CLK_N MEM_CLK_P MEM_ADDR_CMD21 MEM_ADDR_CMD20 MEM_ADDR_CMD25 MEM_ADDR_CMD24 MEM_ADDR_CMD23 MEM_ADDR_CMD22 MEM_ADDR_CMD27 MEM_ADDR_CMD28 MEM_DMB0 MEM_DQB1 MEM_DQB3 MEM_DQB6 MEM_DQB0 MEM_DQB4 MEM_DQSB_N0 MEM_DQSB_P0 MEM_DQB5 MEM_DQB2 MEM_DQB7

Description

DDR4 A10

DDR4 A9

DDR4 A8

DDR4 A7

DDR4 A6

DDR4 A5

DDR4 A4

DDR4 A3

DDR4 A2

DDR4 A1

DDR4 A0

DDR4 PAR

DDR4 CSN1 (not use)

DDR4 BANK CLKN

DDR4 BANK CLKP

DDR4 CKe1 ( no use)

DDR4 CKe0

DDR4 ODT1 (no use)

DDR4 ODT0

DDR4 ACTn

DDR4 CSn0

DDR4 Resetn

DDR4 BG1

DDR4 DM

DDR4 DQ

DDR4 DQSN

DDR4 DQSP

DDR4 DQ

continued...

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Intel® Stratix® 10 SX SoC Development Kit User Guide 79

Pin Name PIN_F34 PIN_E34 PIN_J35 PIN_H35 PIN_F35 PIN_G35 PIN_G34 PIN_G33 PIN_H36 PIN_J36 PIN_H33 PIN_D39 PIN_E39 PIN_E38 PIN_D38 PIN_D35 PIN_D34 PIN_F36 PIN_E36 PIN_F37 PIN_E37 PIN_H37 PIN_C36 PIN_D36 PIN_C35 PIN_B35 PIN_B37 PIN_C37 PIN_A35 PIN_A36 PIN_B38 PIN_C38 PIN_A37 PIN_A38

Schematic Signal Name MEM_DMB2 MEM_DQB17 MEM_DQB21 MEM_DQB22 MEM_DQB18 MEM_DQB20 MEM_DQSB_N2 MEM_DQSB_P2 MEM_DQB23 MEM_DQB19 MEM_DQB16 MEM_DMB1 MEM_DQB9 MEM_DQB11 MEM_DQB12 MEM_DQB14 MEM_DQB13 MEM_DQSB_N1 MEM_DQSB_P1 MEM_DQB10 MEM_DQB15 MEM_DQB8 MEM_DMB3 MEM_DQB26 MEM_DQB29 MEM_DQB25 MEM_DQB27 MEM_DQB31 MEM_DQSB_N3 MEM_DQSB_P3 MEM_DQB28 MEM_DQB30 MEM_DQB24 HPS_ALERT_N2

4. Development Kit Components UG-20081 | 2020.09.08
Description DDR4 DM DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQSN DDR4 DQSP DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DM DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQSN DDR4 DQSP DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DM DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQ DDR4 DQSN DDR4 DQSP DDR4 DQ DDR4 DQ DDR4 DQ DDR4 Altertn

Intel® Stratix® 10 SX SoC Development Kit User Guide 80

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4.9.3. HPS I2C Interface

HPS I2C interface is assigned to HPS GPIO IO1, IO6 and IO7. HPS I2C controller can
scan the board and collect MAC address, board temperature and power data of FPGA. A control signal generated by MAX10 system controller is used to enable HPS I2C
system port .

Table 47. I2C Device Address

Type HPS I2C Address FPGA I2C Address

Address 0x14 0x74 0x51 0x5C 0x4C 0x55 0x1D 0x70 0x73 0x47 0x43 0x42 0x46 0x4E 0x70 0x70 0x00 0x65 0x73

Device LTC2497 ADC SI5341 Clock Generator 24LC32A EEPROM DS1339C RTC MAX1619 TEMP SODIMM EEPROM SODIMM TEMP SI5338 Clock Generator SI5338 EMIF Clock Generator LTC3884 Core power Controller LTM4677 VCCR Power Controller LTM4677 VCCERAM_HPS Power controller LTM4677 VCCPT_VCCT Power controller LTM4676A 3.3V power controller SFP+ ZQSFP+ port 0/1 LMK05028 Clock Cleaner LMH1983 SDI clock generator HDMI port

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Figure 28. HPS I2C Interface

S10 SoC I2C Bus Connection

0x55, 0x4D J28 SODIMM

I2C Master U43 MAX10

0x70 U26 Si5338A PCle-FPGA REF CLK

0x73 U31 Si5338B FPGA MEM REF CLK

SODIMM R351/R352

Config
U15 S10 FPGA

U39

3.3V

I2C Level Shifter 3.3V to 2.5V

2.5V

R345/R346

Clock

0x5A, 0x5B, 0x47

0x4B

0x42

0x46

0x43

VID

1.8V

U23 I2C Level Shifter

U53 LTC3884EUK

3.3V to 1.8V

VCC

U110

U111

U115

U113

EM2139H

EM2130L

EM2130H

EM2130L

12V to 3.3V

VCCERAM

VCCPT

VCCR

J29

U40 I2C Level Shifter

PMbus

3.3V 3.3V to 3.3V 3.3V

SW8 J23

PMbus Conn PMbus Conn

R335/R336 HDMI
EXTA EXTA EXTA

HPS

FPGA

FPGA_I2C 1.8V
U24 I2C Level Shifter
3.3V to 1.8V 3.3V

FPGA_I2C 1.8V
U101 I2C Level Shifter
3.3V to 1.8V 3.3V

3.3V R343/R344 J8

U38 I2C Level Shifter

HDMI_LINE

3.3V 3.3V to 5V 5.0V

3.3V

U18

P13HDX1204B

HDMI TX

HDMI_TX

0x4C U37 MAX1619 TEMP SENSE

U33 Si5341A XCVR REF CLK
0x74 SDI
0x51 U41 24LC32A SEEROM

U47 LTC2497
0x14 3.3V

0x35 U102 LMH1983 SDI REF CLK

For LT I2C Dongle

Addr = TBD J53 PCle

Addr = TBD J11 FMC+ A

0x50 J9 QSFP28

U114 EM2130L
VCCT 0x4A

For Enpirion I2C Dongle

Addr = TBD J7 SFP+ A

S10_2L

3.3V

S10_2L R816/R817

Cleaner 3.3V

0x58 U34 LMK05028 CLK Cleaner

S10_2L
0x4E U116 MAX1619 Temp Sense

3.3V

R347/R348

S10_2L

R347/R348

EXTA 0x50
J10 QSFP28
EXTB

U105 I2C Level Shifter

SFP+

3.3V 3.3V to 3.3V 3.3V

Addr = TBD

J12 FMC+ B

4.10. System Power

4.10.1. Power Supply Options

Table 48. Power Supply List

Power Source Name

Power Name

LTC3884 240A
EM2130L, EN63A0QI
EM2130L
EM2130L/EM2130H
EM2130H LTM4625 EN63A0Q1 EN6337QI EP5348UI EN63A0QI EN6360QI TPS51200 (DDR VTT)

Core Power (0.85V) Output 0 (0.95V) Output 1 (0.9V) Output 0 & 1 (1.12V) Output 0 (1.12V) Output 1 (1.8V) Output 0 & 1 (3.3V) Output (5V) Output (1.8V) Output (2.5V) Output (2.4V) Output (1.2V) Output (1.2V) Output (0.6V)

Maximum Output Current (A)

Actual Current (A)

240

190

0.4

0.1

Intel® Stratix® 10 SX SoC Development Kit User Guide 82

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4.10.2. Power Sequence

The power-up/down sequence design follows power-up and power-down sequence requirements for Intel Stratix 10 devices, PCIe Plug-in Card power up/down requirement, and FMC plug-in card power up/down requirement.

The following figures show the development kit power up/down sequence.

Figure 29. Power Up Sequence
S10_12V

AC_Adapter 12V_Switch

MAX10I

Pgood_5V0 3V3_2V5_USB2_1V8

S10_Main_3V3

Pgood_VCCL VCCERAM VCCL_HPS

PgoodVCC T_VCCR

Pgood_VC CPT

MAX10

MAX CPLDs Power Up

10V_threshold S10_VCCL_VCCP

Group 1

S10_GXB_VCCT_VCCR

S10_VCCERAM/VCCL_HPS VCCPLLDIG_HPS VCCPLLDIG_SDM

Group 2
S10_VCCPT VCCH_GXB VCCA_PLL VCCPLL_HPS VCCPLL_SDM VCCADC

5.0 V

3.3 V

2.5 V 2.4 V
1.8 V

1.2V
GP1, 0.85 V, 0.9 V, 0.95 V, 1.12 V

Group 3

0 V POR

PCIE, FMC Peripheral Devices S10_VCCIO_SDM VCCIO, VCCIO_HPS
VCCIO_3V VCCFUSEWR_DSM

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Intel® Stratix® 10 SX SoC Development Kit User Guide 83

Figure 30. Power Down Sequence
AC_Adapter 12V_Switch

4. Development Kit Components UG-20081 | 2020.09.08

3.3 V
2.5 V 2.4 V
1.8 V
1.2V_adj 1.0 V 0.95 V 0.9 V
0 V

0.2V_threshold

10V_threshold POR

Group 3
PCIE, FMC, 3.3V Peripheral Devices
S10_IO VCCFUSEWR_SD

0.2V_threshold

Group 2
S10_VCCPT VCCH_GXB VCCA_PLL
VCCPLL L_HPS VCCPLL_SDM

Group 1
S10_VCC_VCCP/ VCCL_HPS.VCCERAM.VCCT
VCCR VCCERAM

MAX CPLDs

4.10.3. Power Distribution Network
The Intel Stratix 10 Development Kit uses the Intel MAX 10 CPLD (U46) as a power sequencer. J26 needs to be shorted to program Intel MAX 10 Power CPLD (U46). During normal operation, J26 needs to be open. The Intel MAX 10 CPLD monitors all power good signals, the 12V input voltage threshold signal (>10.2V), and turns on each FPGA power supply based on the power sequence requirements.

Intel® Stratix® 10 SX SoC Development Kit User Guide 84

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If 12V input voltage is below 12V input threshold voltage, the power down sequence is triggered. The Intel MAX 10 Power CPLD turns on the quick discharge circuit and turns off each power supply based on power down sequence requirements.

Figure 31.

Power Distribution Network

Slew Rate <3V/ms

12V_Power_Adapter Input

Slew Rate <3V/ms

PCIE_3V3

Slew Rate <1V/ms

Main_12V

PO5V0 5A
LTM4625

EM2130 30A

5V 3V3

10V Threshold 5V

PCIE_12V
FMCA_12V
FMCB_12V A10_12V

MAX 10 Power Sequencer

P3F01AV EM2130
5V

PF1V 30A EM2130

EM2130 30A

LTC3884 240A

FMB_3V3 FMB_3V3

3.3V_IO_ Dicharge

IO_3V3

SODIMM VDD 8A
EN6360QI HILO_VDD 1.55V BAT

PMCBVADJ

Slew Rate <1V/ms
FMCA_3V3 FMA_3V3

EMC_IO

HILO VDDQ 8A
EN6360QI 1.2V

PD2.5V 3A
EN6337QI

PC1.8V 12A EN63AOQI

LT_3V3

IO_2V5

AIO_Main_ 1V8 1V8

1.12V 1.12V

AIO_Main_3V3

1V8

PGHILO-HPS

VDD

Slew Rate <1V/ms

EN6360QI

PLL1V8

1.2V

IO_1V8 Discharge

0V9 0V85 PE0.95V
8A EN6360QI
0.85

VCCP VCC VCCPLLDIG_HPS
VCCL_HPS VCCPLLDIG_SDM VCCERAM
VCCR_GXBL VCCT_GXBR VCCT_GXBL VCCR_GXBL VCCH_GXBL VCCH_GXBR VCCPT VCCA_PLL VCCPLL_HPS VCCPLL_SDM
VCCADC VCCIOHPS VCCSDM
VCCIO2M VCCIO2N VCCIO2L VCCIO2C VCCIO2B VCCIO2A VCCIO2F VCCIO3K VCCIO3B VCCIO3A
VCCIO3A VCCFUSEWR_SDM VCCBAT
A10SOC

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5. Board Test System
This development kit includes an application called the Board Test System (BTS). The BTS is an easy-to-use interface to alter functional settings of the FPGA portion of the SoC. Figure 32. BTS Graphical User Interface (GUI)

You can use the BTS to test board components, modify functional parameters, observe performance and measure power usage. While using the BTS, you reconfigure the FPGA several times with test designs specific to the functionality you are testing.
Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA.
After successful FPGA configuration, the appropriate tab appears that allows you to exercise control over the related board features. Highlights appear in the board picture around the corresponding components.

ISO 9001:2015 Registered

5. Board Test System UG-20081 | 2020.09.08

The BTS communicates over the JTAG bus to a test design running in the FPGA. The BTS and Power Monitor share the JTAG bus with other applications like Nios II debugger and the Signal Tap Embedded Logic Analyzer.

5.1. Preparing the Board

After successful FPGA configuration, with the power to the board off, follow these steps: · Connect the USB cable to your PC and the Intel FPGA Download Cable II port. · Change SW1 and SW4 to the following configuration. · Turn on power to the board and run the Board Test System.

Note:

To ensure operating stability, keep the USB cable connected and the board powered on when running the demostration application.

Table 49.
Bit 1 OFF

SW1 GUI Mode

Bit 2 OFF

Bit 3 ON

Bit 4 ON

Bit 5 ON

Bit 6 ON

Bit 7 ON

Bit 8 ON

Table 50.

SW4 GUI Mode
Bit 1 ON

Bit 2 OFF

Bit 3 ON

Bit 4 ON

5.2. Running the BTS
To run the BTS, navigate to the <Package Root Dir>\examples \board_test_system directory and run the BoardTestSystem.exe application.
The BTS relies on the Intel Quartus Prime software's specific library. Before running the BTS, set the environment variable $QUARTUS_ROOTDIR to the correct directory on your manually or open the Intel Quartus Prime software to automatically set the environment variable. The BTS uses this environment variable to locate the Intel Quartus Prime library.
5.3. Using the BTS
This section describes each control in the BTS.
5.3.1. The Configure Menu
Use Configure Menu to select the design you want to use. Each design example tests different board features. Select a design from this menu and the corresponding tabs become active for testing.

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Figure 33. The Configure Menu

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To configure the FPGA with a test system design, perform the following steps: · On the Configure menu, click the configure command that corresponds to the
functionality you wish to test. · In the dialog box that appears, click Configure to download the corresponding
design to the FPGA.
Figure 34. Programmer Dialog Window

Intel® Stratix® 10 SX SoC Development Kit User Guide 88

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5.3.2. The GPIO Tab
The GPIO tab allows you to interact with all the general purpose user I/O components on the board. You can read DIP switch settings, turn LEDs on/off and detect presses of push buttons. Figure 35. The GPIO Tab

The following sections describe the controls on the GPIO tab.
User DIP Switches
The read-only User DIP Switches control displays the current positions of the switches in the user DIP switch bank (SW1). Change the switches on the board to see the graphical display change.
User LEDs
The User LEDs control displays the current state of the User LEDs. Toggle the LED buttons to turn the board LEDs on or off.
Push Buttons
Read-only control displays the current state of the board user push buttons. Press a push button on the board to view the graphical display change accordingly.

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Qsys Memory Map The Qsys memory map control shows the memory map of the bts_config.sof design running on your board. The memory map is visible only when bts_config.sof design is running on the board.
5.3.3. The QSFP/SFP Tab
This tab allows you to perform loopback tests on the QSFP and SFP ports. Figure 36. The QSFP/SFP Tab

The controls on this tab are described below. Status Displays the following status information during a loopback test:

Intel® Stratix® 10 SX SoC Development Kit User Guide 90

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· PLL Lock: Shows the PLL locked or unlocked state. · Pattern Sync: Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected. · Details: Shows the PLL lock and pattern status. Figure 37. PLL and Pattern Status
Port Allows you to specify which interface to test. The following port tests are available: · QSFP0 x4 · QSFP1 x4 · SFP x1 PMA Setting

Allows you to make chnages to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis.
Serial Loopback: Routes signals between the transmitter and the receiver.
VOD: Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap

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· 1st pre: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.
· 1st post: Specifies the amount of pre-emphasis on the first post-tap of the transmitter buffer.
Equalizer: Specifies the CLTE EQ Gain for the receiver.
AC Gain: Specifies the CLTE AC Gain for the receiver.
VGA: Specifies the VGA Gain for the receiver.
Data Type
Specifies the type of data contained in the transactions. The following data types are available for analysis. · PRBS 7: Selects pseudo-random 7-bit sequences · PRBS 15: Selects pseudo-random 15-bit sequences · PRBS 23: Selects pseudo-random 23-bit sequences · PRBS 31: Selects pseudo-random 31-bit sequences · HF: Selects highest frequency divide-by-2 data pattern 10101010 · LF: Selects lowest frequency divide-by-33 data pattern
Error Control
Displays data errors detected during analysis and allows you to insert errors · Detected Errors: Displays the number of data errors detected in the hardware. · Inserted Errors: Displays the number of errors inserted into the transmit data
stream. · Insert: Inserts a one-word error into the transmit data stream each time you click
the button. Insert is only enabled during transaction performance analysis. · Clear: Resets the Detected Error counter and Inserted Errors counter to zero.
Run Control
· TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
· Start: Initiates the loopback tests. · Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second. · Data Rate: Shows the data rate for each link.

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5.3.4. The PCIE Tab
The PCIE Tab allows you to perform loopback tests on the PCIE port. Figure 38. The PCIE Tab

The following sections describe the controls on the PCIE tab. Status Displays the following status information during a loopback test:

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Port Allows you to specify which interface to test. The following port tests are available: · PCIE x16

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PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis: · Serial Loopback: Routes signals between the transmitter and the receiver. · VOD: Specifies the voltage output differential of the transmitter buffer. · Pre-emphasis tap:
-- 1st pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
-- 1st post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
· Equalizer: Specifies the CLTE EQ Gain for the receiver. · AC Gain: Specifies the CLTE AC Gain for the receiver. · VGA: Specifies the VGA gain of the receiver.

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Data Type
Specifies the type of data contained in the transactions. The following data types are available for analysis. · PRBS 7: Selects pseudo-random 7-bit sequences. · PRBS 15: Selects pseudo-random 15-bit sequences. · PRBS 23: Selects pseudo-random 23-bit sequences. · PRBS 31: Selects pseudo-random 31-bit sequences. · HF: Selects highest frequency divide-by-2 data pattern 10101010. · LF: Selects lowest frequency divide-by-33 data pattern.
Error Control
Displays data errors detected during analysis and allows you to insert errors: · Detected Errors: Displays the number of data errors detected in the hardware. · Inserted Errors: Displays the number of errors inserted into the transmit data
stream. · Insert: Inserts a one-word error into the transmit data stream each time you click
the button. Insert is enabled only during transaction performance analysis. · Clear: Resets the Detected Errors counter and Inserted Errors counter to zero.
Run Control
· TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
· start: this control initates the loopback tests. · Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second. · Data Rate: Shows the data rate for each link.
5.3.5. The MXP Tab
The MXP tab allows you to perform loopback tests on the MXP port.

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Figure 39. The MXP Tab

The following sections describe the controls on the MXP tab.
Status
Displays the following status information during a loopback test: · PLL Lock: Shows the PLL locked or unlocked state. · Pattern Sync: Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected. · Details: Shows the PLL lock and pattern status:

Port Allows you to specify which interface to test. The following port tests are available: · MXP x4

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PMA Setting

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Allows you to make changes to the PMA paratmeters that affect the active transceiver interface. The following settings are available for analysis: · Serial Loopback: Routes signals between the transmitter and the receiver. · VOD: Specifies the voltage output differential of the transmitter buffer. · Pre-emphasis tap:
-- 1st Pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
-- 1st Post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
· Equalizer: Specifies the CLTE EQ Gain for the receiver. · AC Gain: Specifies the CLTE AC Gain for the receiver. · VGA: Specifies the VGA gain for the receiver.
Data Type
Specifies the type of data contained in the transactions. The following data types are available for analysis. · PRBS 7: Selects pseudo-random 7-bit sequences. · PRBS 15: Selects pseudo-random 15-bit sequences. · PRBS 23: Selects pseudo-random 23-bit sequences. · PRBS 31: Selects pseudo-random 31-bit sequences. · HF: Selects highest frequency divide-by-2 data pattern 10101010. · LF: Selects lowest frequency divide-by-33 data pattern.
Error Control
Displays data errors detected during analysis and allows you to insert errors:

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· Detected Errors: Displays the number of data errors detected in the hardware. · Inserted Errors: Displays the number of errors inserted into the transmit data
stream. · Insert: Inserts a one-word error into the transmit data stream each time you click
the button. Insert is enabled only during transaction performance analysis. · Clear: Resets the Detected Errors counter and Inserted Errors counter to zero. Run Control · TX and RX performance bars: Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve. · Start: this control initates the loopback tests. · Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second. · Data Rate: Shows the data rate for each link.
5.3.6. The FMCA Tab
The FMCA tab allows you to perform loopback tests on the FMCA port.

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Figure 40. The FMCA Tab

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The following sections describe the controls on the FMCA tab. Status Displays the following status information during a loopback test:

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Port
Allows you to specify which interface to test. The following port tests are available: · XCVR · CMOS

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PMA Setting

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Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:

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· Serial Loopback: Routes signals between the transmitter and the receiver. · VOD: Specifies the voltage output differential of the transmitter buffer. · Pre-emphasis tap:
-- 1st Pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
-- 1st Post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
· Equalizer: Specifies the CLTE EQ Gain for the receiver. · AC Gain: Specifies the CLTE AC Gain for the receiver. · VGA: Specifies the VGA gain for the receiver.
Data Type
Specifies the type of data contained in the transactions. The following data types are available for analysis. · PRBS 7: Selects pseudo-random 7-bit sequences. · PRBS 15: Selects pseudo-random 15-bit sequences. · PRBS 23: Selects pseudo-random 23-bit sequences. · PRBS 31: Selects pseudo-random 31-bit sequences. · HF: Selects highest frequency divide-by-2 data pattern 10101010. · LF: Selects lowest frequency divide-by-33 data pattern.
Error Control
Displays data errors detected during analysis and allows you to insert errors: · Detected Errors: Displays the number of data errors detected in the hardware. · Inserted Errors: Displays the number of errors inserted into the transmit data
stream. · Insert: Inserts a one-word error into the transmit data stream each time you click
the button. Insert is enabled only during transaction performance analysis. · Clear: Resets the Detected Errors counter and Inserted Errors counter to zero.

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Run Control · TX and RX performance bars: Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve. · Start: this control initates the loopback tests. · Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second. · Data Rate: Shows the data rate for each link.

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5.3.7. The FMCB Tab
The FMCB tab allows you to perform loopback tests on the FMCB port. Figure 41. The FMCB Tab

The following sections describe the controls on the FMCB tab. Status Displays the following status information during a loopback test:

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Port
Allows you to specify which interface to test. The following port tests are available: · XCVR · CMOS

Intel® Stratix® 10 SX SoC Development Kit User Guide 106

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PMA Setting

Allows you to make changes to the PMA paratmeters that affect the active transceiver interface. The following settings are available for analysis:

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Intel® Stratix® 10 SX SoC Development Kit User Guide 108

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5.3.8. The DDR4 Tab
This tab allows you to read and write DDR4 memory on the board. Figure 42. The DDR4 Tab

The controls on this tab are described below.
Start
Initiates DDR4 memory transaction performance analysis
Stop
Terminates transaction performance analysis
Performance Indicators
These controls display current transaction performance analysis information collected since you last clicked Start: · Write, Read and Total performance bars: Show the percentage of maximum
theoretical data rate that requested transactions are able to achieve. · Write, Read and Total (MBps): Show the number of bytes analyzed per second. · Data Bus: 72 bits (8 bits ECC) wide and frequency is 1066 MHz double data rate.
2133 Mbps per pin.

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Error Control
Displays data errors detected during analysis and allows you to insert errors · Detected errors: Displays the number of data errors detected in the hardware. · Inserted errors: Displays the number of errors inserted into the transmit data
stream. · Insert Error: Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance analysis. · Clear: Resets the Detected Errors counter and Inserted Errors counter to zero.
Address Range
Determines the number of addresses to use in each iteration of reads and writes

5.3.9. Power Monitor
The Power Monitor measures and reports current power information and communicates with the Intel MAX 10 device on the board through the JTAG bus. A power monitor circuit attached to the Intel MAX 10 device allows you to measure the power that the FPGA is consuming.
To start the application, click the Power Monitor icon in the BTS. You can also run the Power Monitor as a stand-alone application. The PowerMonitor.exe resides in the <packagedir>\examples\board_test_system directory.

Note:

You cannot run the stand-alone power application and the BTS simultaneously. Also, you cannot run power and clock interface at the same time.

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Figure 43. Power Monitor

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The controls on the Power Monitor are described below.
Test Settings
Displays the following controls: · Power Rails: Indicates the currently selected power rail. After selecting the desired
rail, click Reset to refresh the screen with updated board readings. · Scale: Specifies the amount to scale the power graph. Select a smaller number to
zoom-in to see finer detail. Select a larger number to zoom-out to view the entire range of recorded values. · Speed: Specifies how often to refresh the power graph.
Power Information
Displays the root mean square (RMS) current, maximum and minimum numerical power readings in mA.
Graph
Displays the mA power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset. The yellow line indicates the minimum value read since the last reset.

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General Information Displays the MAX V version and current temperature of the FPGA and the board.
Reset Clears the graph, resets the minimum and maximum values and restarts the Power Monitor.
5.3.10. The Clock Control
The Clock Control application sets the three programmable oscillators to any frequency between 10 MHz and 810 MHz. The frequencies support eight digits of precision to the right of the decimal point. The Clock Control communicates with the Intel MAX 10 device on the board through the JTAG bus. The programmable oscillators are connected to the Intel MAX 10 device through a 2-wire serial bus.
Figure 44. Clock Control

The Si5338 tab and Si5341 tab displays the same GUI controls for each clock generators. Each tab allows for separate control. The Si5338 is capable of synthesizing four independent user-programmble clock frequencies up t0 350 MHz and select frequencies up to 710 MHz.

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F_vco Displays the generating signal value of the voltage-controlled oscillator. Registers Display the current frequency of the clock. Frequency (MHz) Allows you to specify the frequency of the clock. Default Sets the frequency for the oscillator associated with the active tab back to its default value. The default is restored by power cycling the board. Read Reads the current frequency setting for the oscillator associated with the active tab. Set Sets the programmable oscillator frequency for the selected clock to the value in the CLK0 to CLK3 controls for each Si5338. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Intel recommends resetting the FPGA logic after changing frequencies.

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A. Additional Information

A.1. Modify the Intel Stratix 10 SX SoC Development Kit to use a battery for the BBRAM

The Intel Stratix 10 device contains a Battery Backed-up RAM (BBRAM) that is used by the Secure Device Manager. The BBRAM is powered by a special pin on the FPGA named VCCBAT. On the Intel Stratix 10 SX SoC Development Kit, this pin is connected to the main power, and the contents of the BBRAM are lost when the board is powered down. This section describes how to modify the board to accommodate a battery so the BBRAM contents can be preserved when the board loses power.

The modification to the board involves moving a zero-ohm surface mount resistor from one location to another, and then adding a suitable battery power source to a header.

The following schematic diagram shows the default board layout.

VCCPT AG22 VCCPT AG20 VCCPT AG18 VCCPT AG17 VCCPT AE33 VCCPT AE32 VCCPT AE29 VCCPT AE28 VCCPT AE26 VCCPT AE24 VCCPT AE22 VCCPT AE21 VCCPT AE18 VCCPT AE17

J27 1 2
CON2

R720

DNI

R721

VCCBAT EWR_SDM

AV22 AV23

S10_2V4

C762

0.47uF

By default, the VCCBAT pin is powered by the VCCPT power rail through the zero ohm resistor R720. Removing R720 and inserting it in the unpopulated R721 position will cause the power for VCCBAT to come from J27, which is a simple 2 pin 0.1" spaced header. Power can be provided to J27 using a battery with a voltage of 1.2 1.8 volts.

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A.2. Modify the Intel Stratix 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
The supported HPS DDR4 configurations are:
· 72 bits : 64 bit data + 8 bit ECC
· 64 bits : 64 bit data
· 40 bits : 32 bit data + 8 bit ECC
· 32 bits : 32 bit data
· 24 bits : 16 bit data + 8 bit ECC
· 16 bits : 16 bit data
The Golden Hardware Reference Design (GHRD) project has an HPS DDR4 interface configuration with a width of 72 bits.
Flow to modify the HPS DDR4 memory width and ECC Configuration
1. Open the qsys_top.qsys file. Select the emif_hps component and open the Parameter Editor. Change the Memory tab > DQ width as required. If ECC isn't required, unselect the Controller tab parameters Enable Error Detection and Correction Logic with ECC and Enable Auto Error Correction to External Memory. Generate the qsys component.
2. Open the top level RTL file ghrd_s10_top.v. At the top, change the inout wire bus width declarations for emif_hps_mem_mem_dbi_n, emif_hps_mem_mem_dq, emif_hps_mem_mem_dqs and emif_hps_mem_mem_dqs_n for your required DDR4 configuration.
3. In the Quartus Assignment Editor or in the project .qsf file, make these changes:
· For the required DDR4 interface width, disable all the location assignments of the unused mem_dbi_n, mem_dqs, mem_dqs_n and mem_dq signals.
· For narrower width interfaces with ECC, in order to meet the pinout rules in the Intel Stratix 10 SoC Design Guidelines and the Intel Stratix 10 EMIF IP User Guide's HPS DQS group placements, the DQS group used for the ECC bits needs to move so it is placed in lane 3 of I/O bank 2M.
· For a DDR4 interface width of 16 bit + ECC, copy the pin locations for emif_hps_mem_mem_dbi_n [8], emif_hps_mem_mem_dqs[8], emif_hps_mem_mem_dqs_n[8], emif_hps_mem_mem_dq[71:64], to emif_hps_mem_mem_dbi_n[2], emif_hps_mem_mem_dqs[2], emif_hps_mem_mem_dqs_n[2], emif_hps_mem_mem_dq[23:16] respectively.
· For a DDR4 interface width of 32 bit + ECC, copy the pin locations for emif_hps_mem_mem_dbi_n [8], emif_hps_mem_mem_dqs[8], emif_hps_mem_mem_dqs_n[8], emif_hps_mem_mem_dq[71:64], to emif_hps_mem_mem_dbi_n[4], emif_hps_mem_mem_dqs[4], emif_hps_mem_mem_dqs_n[4], emif_hps_mem_mem_dq[39:32] respectively.

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Note: Note:

Note the alert# pin is placed in DQS group 0 which is always in the GHRD project regardless of the HPS DDR4 interface width, so no changes are needed.
Further details for some configurations are shown in Enabling ECC for HPS SDRAM Article on RocketBoards website.

A.3. Safety and Regulatory Information

ENGINEERING DEVELOPMENT PRODUCT - NOT FOR RESALE OR LEASE
This development kit is intended for laboratory development and engineering use only.
This development kit is designed to allow: · Product developers and system engineers to evaluate electronic components,
circuits, or software associated with the development kit to determine whether to incorporate such items in a finished product. · Software developers to write software applications for use with the end product.
This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required Federal Communications Commission (FCC) equipment authorizations are first obtained.
Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under Part 15, Part 18 or Part 95 of the United States Code of Federal Regulations (CFR) Title 47, the operator of the kit must operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47.
Safety Assessment and CE mark requirements have been completed, however, other certifications that may be required for installation and operation in your region have not been obtained.
A.3.1. Safety Warnings

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Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system. The socket outlet must be installed near the equipment and must be readily accessible.
System Grounding (Earthing) To avoid shock, you must ensure that the power cord is connected to a properly wired and grounded receptacle. Ensure that any equipment to which this product will be attached is also connected to properly wired and grounded receptacles.

Power Cord Requirements
The connector that plugs into the wall outlet must be a grounding-type male plug designed for use in your region. It must have marks showing certification by an agency in your region. The connector that plugs into the AC receptacle on the power

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supply must be an IEC 320, sheet C13, female connector. If the power cord supplied with the system does not meet requirements for use in your region, discard the cord and do not use it with adapters.
Lightning/Electrical Storm Do not connect/disconnect any cables or perform installation/maintenance of this product during an electrical storm. Risk of Fire To reduce the risk of fire, keep all flammable materials a safe distance away from the boards and power supply. You must configure the development kit on a flame retardant surface.
A.3.2. Safety Cautions

Caution:

Hot Surfaces and Sharp Edges. Integrated Circuits and heat sinks may be hot if the system has been running. Also, there might be sharp edges on some boards. Contact should be avoided.
Thermal and Mechanical Injury
Certain components such as heat sinks, power regulators, and processors may be hot. Heatsink fans are not guarded. Power supply fan may be accessible through guard. Care should be taken to avoid contact with these components.

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Cooling Requirements
Maintain a minimum clearance area of 5 centimeters (2 inches) around the isde, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan.
Electro-Magnetic Interference (EMI)
This equipment has not been tested for compliance with emission limits of FCC and similar international regulations. Use of this equipment in a residential location is prohibited. This equipment generates, uses and can radiate radio frequency energy which may result in harmful interference to radio communications. If this equipment does cause harmful interfence to radio or television reception, which can be determined by turning the equipment on and off, the user is required to take measures to eliminate this interference.
Telecommunications Port Restrictions
The wireline telecommunications ports (modem, xDSL, T1/E1) on this product must not be connected to the Public Switched Telecommunication Network (PSTN) as it might result in disruption of the network. No formal telecommunication certification to FCC, R&TTE Directive, or other national requirements have been obatined.

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Electrostatic Discharge (ESD) Warning

A properly grounded ESD wrist strap must be worn during operation/installation of the boards, connection of cables, or during installation or removal of daughter cards. Failure to use wrist straps can damage components within the system.

Attention:

Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

A.4. Compliance Information

A.4.1. Compliance and Conformity Statements
CE EMI Conformity Caution
This development board is delivered conforming to relevant standards mandated by Directive 2014/30/EU. Because of the nature of programmable logic devices, it is possible for the user to modify the development kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as a result of modifications to the delivered material is the responsibility of the user of this development kit.

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B. Revision History

B.1. Revision History

Table 51. Revision History for Intel Stratix 10 SX SoC Development Kit User Guide

Document Version

Changes

2020.09.08

Sections Updated: · Overview on page 4 · Installing the Intel SoC Embedded Development Suite (EDS) on page 7 · Development Kit Feature Summary on page 12 · Intel Stratix 10 SoC Device Overview on page 17 · HPS Memory (External 4 GB HILO x72 DDR4 ) on page 76

2020.04.10

Sections Updated: · Overview on page 4 · Installing Quartus Prime Software on page 6 · Installing the Intel FPGA Download Cable on page 7 · Installing the Intel SoC Embedded Development Suite (EDS) on page 7 · Inspect the Development Kit on page 9 · Development Kit Feature Summary on page 12 · Board Components on page 14 · HPS IO-48 OOBE Daughter Card on page 49 · HPS IO-48 NAND Flash Daughter Card on page 59 · Boot QSPI Flash Daughter Card on page 69 · Boot MicroSD Daughter Card on page 70 · HPS Memory (External 4 GB HILO x72 DDR4 ) on page 76

2019.09.20

Added sections: · Modify the Intel Stratix 10 SX SoC Development Kit to use a battery for the BBRAM on page 115 · Modify the Intel Stratix 10 SX SoC Development Kit HPS DDR4 memory width and ECC
configuration using the Golden Hardware Reference Design project on page 116 · Installing the Intel Stratix 10 SX SoC Development Kit Package on page 7 · Intel MAX 10 System Controller Updates on page 10

Document Version 2019.03.20 2018.09.20 2018.08.06

Changes
Removed reference to an internal daughter card.
Removed references to NAND x8 Configuration in FPGA Configuration on page 24
SDM Support of NAND dropped. Removed references to SDM Boot NAND Flash Daughter Card. Updated these sections:
continued...

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Document Version
2018.07.20 2018.04.04

Changes
· Inspect the Development Kit on page 9 · Development Kit Feature Summary on page 12 · HPS Boot Flash Card on page 67
Added device variant SX in the document title
Initial Release.

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