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Charles E. Sporck President, Chief Executive Officer National Semiconductor Corporation
ii
Programmable. Logic Design Guide
Bipolar Memory National Semiconductor Corporation Santa Clara, California ·
iii
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iv
Preface
The CLASS TM Revolution The nature of logic design· is changing and National Semiconductor is leading this change into software-based logic and systems design through the use of structured programmable logic arrays. We welcome you to join us in .the CLASS revolution. CLASS stands for Complete Logic And Software Solutions, and it exemplifies National's commitment to the design, development and support of programmable logic devices, and to the software-based design tools that can make the logic and system designer's task easier.
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Table of Contents
1.0 Introduction 1.1 Purpose of this Design Guide ................................ 1 1.2 Overview of Programmable Logic ............................ 1 1.3 National Semiconductor, The Leader .......................... 2
2.0 Programmable Logic Basics 2.1 What is Programmable Logic ................................ 3 2.2 User Benefits of Programmable Logic ......................... 4 Reduced Board Space .................................... 4 Fast Systems Design ..........................· ........... 5 Design Flexibility ....................................... 5 Multi-level Logic Reduction ... _. ...... , .................... 5 Cost Reduction ......................................... 5 Example to Illustrate Lower Component Costs ................ 7 Example of Cost Reduction Through Reliability Improvements ... 8 Small Inventory ......................................... 9 2.3 Elements of Programmable Logic ........................... 10 The PROM ............................................ 10 The FPLA ............................................. 12 The PAL (Programmable Array Logic) Device ................ 14 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Programmable Logic Versus Other LSI, Semicustom and Custom Alternatives ............................................. 17 Standardized LSI ....................................... 17 Full Custom ICs ........................................ 17 Gate Arrays ........................................... 18
3.0 Boolean Logic Review 3.1 Basic Operators and Theorems .............................. 19 3.2 Derivation of a Boolean Expression .......................... 21 3.3 Minimization ............................................ 24 3.4 K-mapMethod ................. ~ ........................ 25 3. 5 Sequential Circuit Elements ................................ 31 3.6 State Machine Fundamentals ............................... 34
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4.0 The Programmable Logic Family 4.1 Basic Groups ............................................ 39 4.2 The PAL Family ........................................... 39 PAL Devices for Every Task . . . ..... :·. . ........ : . . . . . . . ... . 41 Gates ................................................ 41 Register Options With Feedback .................... ·...... 41 Programmable 1/0 ...................................... 42 PAL Device - Speed/Power Groups ....................... 42 PAL Device Logic Symbols .. ; ............................ 43 4.3 The Prom Family .......·................................... ~ ..... 47 4.4 Logic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.0 How to Design With Programmable Logic 5.1 Problem Definition ....................................... 83 5.2 Device Selection ................. : ....................... 84 5.3 Writing Logic Equations ................................... 87 5.4 Programming the Device .................................. 88 5.5 Testing the Device ..... : ................................. 89 5.6 Programmer Vendor List .................................. 90 5.7 Examples Example 1: Replace Existing Logic ......................... 92 Example 2: Design a Multiplexer ......... ·... ·.............. 95 Example 3: Design a 3-bit Counter ....................... 100 Example 4: Design a Video-Telephone Sync Pulse Detector .... 102
6.0 Software Support 6.1 Advantages of Software-Based Programmable Logic Design ...... 107 6.2 Programmable Logic Analysis by National (PLAN) ............. 108 Boolean Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 File Editing and Documentation ...... ; ..... : ............. 110 Programming and Testing ............................... 110 6.3 Other Software ......................................... 112 CUPL ....................................................... 112 P.AIASM .................................................... 116 ABEL ....................................................... 116 6.4 Software for Testing Programmable Logic .................... 120 6.5 Software Vendor List ..................................... 120
7 .0 Testing and Reliability 7.1 National Factory Testing .................................. 121 7.2 Logic Verifications ....................................... 123 7.3 Customer's Responsibilities ............................... 126 7.4 · · Reliability Data .................. ; ........... ·. ·............ 126 7.5 PAL Device Functional Testing ............................. 127
Table ofContents ix
Combinational and Sequential Circuits .................... 127 Description of PAL (Programmable Array Logic) Device ....... 128 PAL Device Design Procedures ........................... 128 Description of Functional Table ................... ; . . . . . . 129 How to Generate Test Vectors and the Function Table
From Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 133 7.6 Example of Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Example 1: Combinational PAL12H6 . . . . . . . . . . . . . . . . . . . . . . 136 Description , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Example 2: Sequential PAL 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Description ......................................... 143
8.0 Applications 8.1 Basic Gates ............................................ 157 8.2 Basic Clocked Flip-Flops ........ : ........................ 162 8.3 Memory-Mapped I/O (Address Decoder) ..................... 168 Functional Description ................................. 168 8.4 Hexadecimal Decoder/Lamp Driver ......................... 172 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 General Description ....................... : ........... 172 PAL Device Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8.5 Between Limits Comparator/Logic .......................... 178 8.6 Quadruple 3-Line/1-Line Data Selector Multiplexer ............. 181 8.7 4-bit Counter with 2-Iriput Multiplexer ...................... 183 8.8 8-bit Synchronous Counter ............................... 187 8.9 6-bit Shift Register with Three-state Outputs ................. 190 8.10 Portion of Random Control Logic for 8086 CPU Board ......... 194 8.11 DP84312 Dynamic RAM Controller Interface Circuit for the NS32032, CPU . . . . . . . . . . . . . . . . . . . . . . . . . . 197 General Description .................................... 197 Features .............................................. 197 Mnemonic Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 8.12 DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 General Description ....................... : ........... 207 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Mnemonic Description ...................... ~ .......... 211 Functional Description ................. : ............... 211 8.13 DP84332 Dynamic RAM Controller Interface Circuit for the 8086 and 8088 CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Mnemonic Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
x Programmable Logic Design Guide
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 System Description .................................... 231 Refresh Request Logic ......·.. : . . . . . . . . . . . . . . . . . . . . . . . . . 233 8.14 A PAL Device Interface Between the National Semiconductor NS32032 Microprocessor, DP8409 Dynamic RAM Controller, and the DP8400 Expandable Error Checker and Corrector ...... 242
9.0 National Masked Logic (NML) 9.1 NML Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 9.2 NML Guidelines ........................................ 270
10.0
Advantages of National's Programmable Logic Family 10. 1 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 10.2 Broad Product Line ...................................... 271 10.3 Customer Service and Support .............................. 272
11.0 Data Sheets 11.1 PAL Device Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Description . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Features ..................................................... 274 20-Pin, Standard, Small PAL Devices .......................... 276 20-Pin, Standard, Medium PAL Devices ......................... 277 20-Pin, Fast, Small PAL Devices ............................... 279 20-Pin, Fast, Medium PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 20-Pin, Ultra High-Speed, Medium PAL Devices ................ 282 20-Pin, Fast, Half-Power, Small PAL Devices .......... ; ................... 284 20-Pin, Fast, Half-Power, Medium PAL Devices .......................... 286 20-PIN, Ultra High-Speed, Half-Power, Medium PAL Devices ............. 288 24-Pin, Standard PAL Devices ..... _. .................................... 290 24-Pin, Fast PAL Devices ............................................... 292 11.2 ProgrammingNerifying Procedure-20 Pin PAL Devices ......... 294 Pre-verification ........................................ 294 Progr~mming Algorithm ................................... 295 Programming the Security Fuses .... : ..................... 297 11.3 ProgrammingNerifying Procedure-24 Pin PAL Devices ......... 298 Pre-Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... 298 Programming Algorithm ............................... .". 298 Programming the Security Fuses .......................... 301 11.4 Logic PROM Data Sheets .................................. 304 Descriptions ........................................... 304 Testability ................. ·..._......................... 304 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 304
11.5 DM54/74S188, DM54/74S288 (32 x 8) 256-bit TTL PROMs ....... 307
11.6 PL77/87X288 (32 + 8) 256-bit TIL PROM ...................... 309
Table of Contents xi
11.7 DM54/74LS471 (256 + 8) 2K-bit TIT. PROM . . . . . . . . . . . . . . . . . . . . 311
11.8 DM54/74S473, DM54/74S472, DM54/74S473A, DM54/74S472A
DM54/74S472B (512 x 8) 4K-bit TTL PROMS .................. 313
General Description ............................. : ...... 313
Features .............................................. 313
11.9 DM54/74S475, DM54/74S474, DM54/74S475A, DM54/74S474A
DM54/74S474B (512 x 8) 4K-bit TTL PROMS .................. 316
General Description .................................... 316
Features . . . . . . . ....... .- . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 316
11.10 DM77/87SR474, DM77/87SR474B (512 x 8) 4K~bit
Registered TTL PROMs .................................... 319
Resistered TTL PROMs
General Description ................................... 319
Features ............................................. 320
11.11 DM77/87SR476, DM77/87SR25, DM77/87SR476B, DM77/87SR25B
(512 x 8) 4K-bit Registered TTL PROMs ........................ 323
General Description ..................................... 323
Features .............................................. 323
11.12 Registered PROM Programming Procedure ..................... 327
11.13 Non-Registered PROM Programming Procedure ................ 329
11.14 Quality Enhancement Programs ............................... 332
· 12.0 Package Outlines ............................................. 333
13.0 Terminology ................................................. 341
Appendix-An Overview of LSI Testing Techniques
347
Al
Testing Methods .............................................. 348
Concurrent Testing ......................................... 348
Explicit Testing ............................................. 349
A.2
Test Generation Techniques.................................... 351
NP-Complete Problems ..................................... 352
Manual Test Generation .................................... 355
Path Sensitization and the D-Algorithm ...................... 357
Algorithmic Test Generation ................................. 359
The Thatte-Abraham Technique ............................. 360
The Abadir-Reghbati Technique ............................. 362
Simulation-Aided Test Generation ........................... 363
Binary Decision Diagrams .................................. 365
Random Test Generation ................................... 367
A.3
Response Evaluation Techniques .............................. 368
Good Response Generation ................................. 368
Stored Response Testing .................................... 368
Comparison Testing ........................................ 370
Compact Testing .................................... ·....... 370
Transition Counting ....................................... :371
Signature Analysis .......................................... 373
List of Illustrations
Figure No.
Page No.
2.1.1 2.1.2 2.2.1 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6
Conventional Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Programmable Logic Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Multilevel Logic Reduction .................. _. . . . . . . . . . . . . . . . . . . . . . 6 Diode OR Matrix ........................ : ........................ 10 4 x 4 Bit PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PROM Having 16 Words x 4 Bits .................................. 12 FPLA Having 4 Inputs, 4 Outputs, and 16 Products . . . . . . . . . . . . . . . . . . 13 PAL Device Having 4 Inputs, 4 Outputs, and 16 Products . . . . . . . . . . . . 15 (a) Logic Equation, (b) PROM Solution, (c) FPLA Solution, (d) PAL Device Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 3.2.1 3.2.2 3.2.3 3.3.1 3.3.2 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 3.4.10 3.4.11 3.5.1 3.5.2 3.6.1 3.6.2 3.6.3
Basic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Logic Circuits of Eq. 3.2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Logic Circuits of Eq. 3.2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Simplified Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 A Random Logic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Minimied Logic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Truth Tables for AND and OR .............................. ~ ...... 26 K-maps for AND and OR .................. ~ . . . . . . . . . . . . . . . . . . . . . . . 26 K-maps for 3-Variables AND and OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Sample 3-Variable K-maps ..............·. . . . . . . . . . . . . . . . . . . . . . . . . . 28 K-maps for Two and Three Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 K-map of m (O, 2, 3, 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 K-map of M (O, 1, 5, 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Adjacent Minterms on a K-map ............................_........ 29 Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Minimization ................................. -. . . . . . . . . . . . . . . . . . . . 30 Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . 31 Basic Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Implement D Flip-Flop by UsingJ-K ...........-.................. ;.. 33 A Typical Sequential Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 State Diagram .................................................... 35 Example of Hazard Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Figure No.
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3.6.4 3.6.5
Example of Unstable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Example fo Circuit With Unpredictable Output States . . . . . . . . . . . . . . . 37
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3.1 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.4.11 4.4.12 4.4.13 4.4.14 4.4.15 4.4.16 4.4.17 4.4.18 4.4.19 4.4.20 4.4.21 4.4.22 4.4.23 4.4.24 4.4.25 4.4.26 4.4.27 4.4.28 4.4.29 ' 4.4.30
4.4.31 4.4.32
PAL Device Output Register Circuit, Simplified Logic Diagram ....... 41 PAL Device Bidirectional Circuit, Logic Diagram .................... 42 Logic Symbol. DMPAL10H8 ....................... ; ................ 43 PAL Device Logic Symbols - Series 20 ............................ 44 PAL Device Logic Symbols - Series 24 ............................ 46 PROM Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Logic Diagram PAL10H8 .......................................... SO Logic Diagram PAL12H6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sl Logic Diagram PALl4H4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S2 Logic Diagram PAL16H2 .......................................... S3 Logic Diagram PAL16Cl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S4 Logic Diagram PAL10L8 ........................................... SS Logic Diagram PAL12L6 ........................................... S6 Logic Diagram PALl4L4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S7 Logic Diagram PAL16L2 ........................................... S8 Logic Diagram PAL16L8 ........................................... S9 Logic Diagram PAL16R8 ........................................... 60 Logic Diagram PAL1,6R6 ........................................... 61 Logic Diagram PAL16L4 ........................................... 62 Logic Diagram PAL12L10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Logic Diagram PAL14L8 ........................................... 64 Logic Diagram PAL16L6 ........................................... 6S Logic Diagram PAL18L4 ........................................... 66 Logic Diagram PAL20L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Logic Diagram PAL20Cl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Logic Diagram PAL20L10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Logic Diagram PAL20X10 .......................................... 70 Logic Diagram PAL20X8 ........................................... 71 Logic Diagram PAL20X4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Logic Diagram.PAL20L8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Logic Diagram PAL20R8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Logic Diagram PAL20R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7S Logic Diagram PAL20R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 32 x 8 PROM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2S6 x 8 PROM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 · S12 x 8 PROM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 512 X 8 PROM Logic Diagram, SR476/SR25 ..... : .................. 80 512 x 8 Register PROM Logic Diagram ............................ 81
List of Illustrations xv
Figure No.
.Page No.
5.1.1 5.3.1 5.3.2 5.4.1 5.5.1 5.7.1 5.7.2 5.7.3'
5.7.4 5.7.5 5.7.6 5.7.7 5.7.8 5.7.9 5.7.10 5.7.11 5.7.12
Design Sequence of the Programmable Logic Device . . . . . . . . . . . . . 83 Combinational PAL Device Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . 87 Sequential PAL Device Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PAL Device Programming Procedures_............................ 89 Test Vectors Creating Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Design Example, Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Example of PALASM Program Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PALASM Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Logic Diagram of the National Type 12L6 PAL Device . . . . . . . . . . . . . 96 PAL Device Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Block Diagram of a Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Logic Diagram of the National Type 14H4 PAL Device . . . . . . . . . . . . . 99 3-Bit Counter ........... ·.......................................· 100 K-map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Sweep Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 (a) State Diagram, (b) State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 K-map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . 105
6.1.1 6.1.2 6.2.2 6.2.2 6.3.1 6.3.2
6.3.3 6.3.4
Early Role of Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Expanded Role of Software ................ , . . . . . . . . . . . . . . . . . . . . 108 Plan File Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Fuse Map Display from Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 CUPL-GTS Screen Display Example . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 115 Block Diagram: 6809 Memory Address Decoder . . . . . . . . . . . . . . . . . . 117 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 118 Source File: 6809 Memory Address Decoder . . . . . . . . . . . . . . . . . . . . . 119
7.1.1 7.2.1 7.2.2 7.2.3 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8
PAL Device Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 PAL Devices Architecture ............................ ; . . . . . . . . . . . 123 Function of Test Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3-Input and Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Combinational Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Sequential Circuit ....·.......................................... 128 Combinational PAL Device Design Steps ..... , . . . . . . . . . . . . . . . . . . . 130 Sequential PAL Device Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 PAL Device Programming Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Test Vector and Function Table Creating Steps ....... ~ .......... ; 133 Logic Circuit of Example #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
xvi Programmable Logic Design Guide
Figure No.
Page No.
8.1.1 8.1.2 8.2.1 8.3.1 8.3.2 8.4.1 8.4.2 8.5.1 8.5.2 8.6.1 8.7.1 8.7.2 8.9.1 8.10.1 8.11.1 8.11.2 8.11.3
8.11.4 8.11.5 8.11.6 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.12.7 8.12.8 8.12.9 8.12.10 8.12.11 8.12.12 8.13.1 8.13.2 8.13.3 8.13.4 8.13.5 8.13.6 8.13.7 8.13.8
Basic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Logic Diagram PAL12H6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Logic Diagram PAL16R8 ......................... : . . . . . . . . . . . . . . . . 167 Memory Mapped 110 Logic Diagram . . . . . . ... . . . . . . . . . . . . . . . . . . . . . 168 Logic Diagram PAL16L2 .................. : . . . . . . . . . . . . . . . . . . . . . . 171 Hex Display Decoder-Driver, Combinational Logic Diagram . . . . . . 173 Logic Diagram PAL16L8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 PAL Device 16Cl Limit Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Logic Diagram PAL16Cl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Logic Diagram PALl 4H4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Four-Bit Counter With Two-Input Multiplexer . . . . . . . . . . . . . . . . . . . . 183 Logic Diagram PAL16R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Logic Diagram PAL16R6 .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Control Logic for 8086 CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Timing Diagram; Read, Write or Hidden Refresh Memory Cycle for the NS16032-DP8409 Interface . . . . . . . . . . . . . . . . . . . . . . . . . 202 Timing Diagram; Read, or Write Memory Cycle With One Wait . . . . 202 Timing Diagram; Forced Refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 DP84312 Logic Diagram PAL16R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Timing Diagram; 68000 Memory Read Cycle .............. -. . . . . . . 216 Timing Diagram; 68000 Memory Read Cycle and Forced Refresh . . 217 Timing Diagram; TAS Instruction Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Timing Diagram; Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Timing Diagram; Memory Read Cycle and Forced Refresh . . . . . . . . 220 Modified System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Timing Diagram 68000 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . 222 .Timing Diagram 68000 Memory Read Cycle and Memory Refresh . 223 DP84322 Logic Diagram PAL Device 16R4 . . . . . . . . . . . . . . . . . . . . . . . . 226 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Block Diagram ..............................-. . . . . . . . . . . . . . . . . . . 228 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Using a Flip-Flop and a Counter for Refresh Request Logic . . . . . . . . 233 Using the DP84300 Refresh Counter for Refresh Logic . . . . . . . . . . . . 233 Timing Diagram; Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Timing Diagram; Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Timing Diagram; Memory Cycle With 1 Wait State· . . . . . . . . . . . . . . . . 236
List of Illustrations xvii
Figure No.
Page No.
8.13.9 8.13.10 8.13.11 8.14.1 8.14.2 8.14.3 8.14.4 8.14.5 8.14.6 8.14.7 8.14.8 8.14.9 8.14.10 8.14.11 8.14.12
8.14.13
8.14.14 8.14.15 8.14.16 8.14.17
Timing Diagram; Forced Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Timing Diagram, Transparent Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 84332 Logic Diagram PAL16R8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 DP8400, DP8409, NS16032 6 MHz Computer System . . . . . . . . . . . . . . 242 DP8400/8409 System Interface Block Diagram . . . . . . . . . . . . . . . . . . . . 245 Timing Diagram; Read Cycle and Write Cycle . . . . . . . . . . . . . . . . . . . . 250 Timing Diagram; Read Cycle With Simple Bit Error . . . . . . . . . . . . . . . 251 Timing Diagram; Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Timing Diagram; Forced Refresh Then Access . . . . . . . . . . . . . . . . . . . . 253 Simulation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Simulation Timing Diagram; Read!Wrtie Without Errors . . . . . . . . . . 255 Simulation Timing Diagram; Read With Error and Write Cycle . . . . . 256 Simulation Timing Diagram; Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Simulation Timing Diagram; Forced Refresh Then Access . . . . . . . . . 258 Simulation Timing Diagram; Write, Forced Refresh and Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Simulation Timing Diagram; Forced Refresh Followed by Read Access (With Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Logic Diagram of PAL Device #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Logic Diagram of PAL Device #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Logic Diagram of PAL Device #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Logic Diagram of PAL Device #4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.1.1
NML Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
11.1.1 11.2.1 11.3.1 11.3.2 11.4.1 11.4.2 11.4.3 11.4.4 11.5.1 11.6.1 11.7.1 11.8.1 11.9.1 11.10.1 11.11.1 11.12.1 11.13.1
Test Waveforms and Schematics of Inputs and Outputs . . . . . . . . . . . 275 Pin Assignment for Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Pin Assignment for Programming .......... ; . . . . . . . . . . . . . . . . . . . . . 298 Programming Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Standard Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Switching Time Waveforms Non-Registered PROMs . . . . . . . . . . . . . . 305 Switching Waveforms, Registered PROM . . . . . . . . . . . . . . . . . . . . . . . . . 306 Key to Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Block and Connection Diagram . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . 309 Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Block and Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Programming Waveforms, Registered PROM . . . . . . . . . . . . . . . . . . . . . 329 Programming Waveforms, Non-Registered PROM . . . . . . . . . . . . . . . . 331
xviii Programmable Logic Design Guide
Figure No.
Page No.
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10
NS PackageJ16A, 16-Lead Cavity DIP 0) ............................. 3?3 NS Package N16E, 16-Lead Molded DIP (N) (Substitute for N16A) ; ': 334 NS PackageJ20A, 20-Lead Cavity DIP 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 334 NS Package N20A, 20-Lead Molded DIP (N) . . . . . . . . . . . . . . . . . . . . . . 335 NS Packagej24F, 24-Lead Cavity DIP 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 335 NS Package N24C, 24-Lead Molded DIP (N) . . . . . . . . . . . . . . . . . . . . . . 336 NS Package J24A, 24-Lead Cavity DIP 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 NS Package N24A, 24-Lead Molded DIP (N) ....................... 337 NS Package PCC-20, 20-Lead Plastic Leaded Chip Carrier (V) . . . . . . . 338 NS Package PCC-28, 28-Lead Plastic Leaded Chip Carrier (V) . . . . . . . 339
A.1.1 A.2.l{a) A.2.l{b) A.2.2 A.2.3{a) A.2.3(b) A.2.3(c) A.2.3{d) A.2.4(a) A.2.4{b) A.2.4{c) A.2.5 A.2.6 A.3.1 A.3.2 A.3.3 A.3.4 A.3.5
LSI Test Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 A One-Out-of-Four Multiplexer-Gate-Level Description ........ ·... 353 Functional-Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ., 353 Gate-Level Description of a Three-Bit Incrementer . . . . . . . . . . . . . . . . 354 Transfer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Add Instruction ................................................ \ 361 OR Instruction .................................. ; . . . . . . . . . . . . . . 361 Rotate Left Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . 361 A Half-Adder ................................................... :. 365
Binary Decision Diagram for C = x·y ............................ 365
Binary Decision Diagram for S = X +. Y(c) ...................... i· 365
Simplified Binary Decision Diagrams for the Half-Adder .......... ·: 366 Binary Decision Diagrams for a Full-Adder . . . . . . . . . . . . . . . . . . . . . . . 366 Stored Response Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Comparison Testing .....................·....................... , 369 Compact Testing ....................... ; ........................ 371 One-Out-of-Four Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 The 16-Bit Linear Feedback SR Used in Signature Analysis . . . . . . . . . 373
List of Tables
Table No.
Page No.
2.2.1 2.2.2
Typical Component Cost Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 System Cost Comparison Between SSI/MSI Based System and PAL Device Based System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 3.6.1
Truth Table of Eq. 3.2.1 and 3.2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3.1 4.3.2,
Members of the 20-Pin PAL Device Family . . . . . . . . . . . . . . . . . . . . . . . . 39 Members of the 24-Pin PAL Device Family . . . . . . . . . . . . . . . . . . . . . . . . 40 PAL Device Part Number Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20-Pin PAL Device Speed/Power Groups . . . . . . . . . . . . . . . . . . . . . . . . . 42 24-Pin Speed/Power Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PROM Configurati.ons .................................... ; . . . . . . 47 PROM Products for Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1.1 5.2.1 5.2.2 5.6.1 5.6.2 5.7.1 5. 7 .2 5.7.3 5. 7 .4 5.7.5 5. 7 .6 5.7.7
Typical PAL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 20-Pin PAL Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 24-Pin PAL Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PAL Device Programmers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PAL Device Development Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Fuse Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Transition Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Transition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 State Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Transition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2.1 6.2.2 6.2.3 6.3.1 6.3.2
Boolean Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Macro Entry With PIAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Fuse Map File Formats in PIAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Address Ranges for 6809 Controller . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 118 PALASM Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
xix
xx Programmable Logic Design Guide
Table No.
Page No.
7.1.1 7.2.1 7.2.2 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11
Test Fuses .........................................·............. . 121 Test Vectors Generated by the Exhaustive Method ............... . 125 Test Vectors Generated by Fault Modeling ...................... . 125 National's PAL Device Family ................................... . 129 Test Vectors ................................................... . 138 Test Vectors ............ : ....................................... . 139 Final Test Vectors ............................................. . 139 Final Function Table ........................................... . 140 Test Vectors ................................................... . 145 Test Vectors ...................... , ............................ . 148 Test Vectors -.·.................................................. . 149 State Assignment .............................................. . 150 Transition Table ............................................... . 150 Final Function Table .......................................... : . 151
8.4.1 8.11.1 8.11.2 8.11.3 8.11.4 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.13.1 8.13.2 8.13.3 8.13.4 8.13.5
Function Description .......................................... . 172 Recommended Operating Conditions .......... ; ................ . . 198 Electrical Characteristics .............................·.......... . 198 Switching Characteristics ....... ·..............·.................. . 198 Function Table ................................................ . 205 Recommended Operating Conditions . : ......................... . 209 Electrical Characteristics ....................................... . 209 Switching Characteristics ....................................... . 209 Memory Speed ................................................ . 213 Memory Speed of 68000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Function Table. . ................. ·... ·........................... . 225 Recommended Operating Conditions ........................... . 229 Electrical Characteristics ....................................... . 229 Switching Characteristics ....................................... . .229 Memory Speed Requirements .................................. . 231 Function Table ................................................ . . 240
11.1.1 11.1.2 11.1.3 11.1.4
11.1~5
11.1.6
11.1.7 11.1.8
20-Pin PAL Devices ............................................. . 274 24-Pin PAL Devices ............................................ . 274 Absolute Maximum Ratings ........ ~ ............................ . 275 Standard Test Load ............................................ . 275 AC and DC Specifications for 20-Pin, Standard, Small PAL Devices . 276 AC and DC Specifications for 20-Pin, Standard, Medium
PAL Devices ................................................... . 277 AC and DC Specifications for 20-Pin, Fast, Small PAL Devices ..... . 279 AC and DC Specifications for 20-Pin, Fast, Medium PAL Devices .. . 280
List of Tables :xxi
Table No.
Page No.
11.1.9
11.1.10
11.1.11
11.1.12
11.1.13 11.1.14 11.2.1 11.2.2 11.3.1 11.3.2 11.3.3 11.4.1 11.5.1 11.5.2 11.6.1 11.6.2
11.7.1 11.7.2 11.8.1 11.8.2 11.9.1 11.9.2
11.10.1
11.11.1
11.12.1
11.13.1
11.13.2 11.14.1
AC and DC Specifications for 20-Pin, Ultra High-Speed, Medium PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 AC and DC Specifications for 20-Pin, Fast, Half-Power, Small PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 AC and DC Specifications for 20-Pin, Fast, Half-Power, Medium PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 AC and DC Specifications for 20-Pin, Ultra High-Speed, Half-Power, Medium PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 AC and DC Specifications for 24-Pin, Standard PAL Devices . . . . . . . . 290 AC and DC Specifications for 24-Pin, Fast PAL Devices . . . . . . . . . . . . 292 Input Line Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Input Line Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Input Line Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Product Line Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Programming Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 (32 X 8) 256-Bit Tn PROM Options . .. . .. . .. . . .. . .. . .. . . .. . . . . . . 307 AC and DC Specifications for (32 X 8) 256-Bit Tn PROMs . . . . . . . . 308 (32 X 8) 256-Bit Tn PROM Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 AC and DC Specifications for (32 x 8) 256-Bit Tn Logic PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 (256 X 8) 2048-Bit Tn PROM Options . . . . . . . .. . . .. .. . . . . . . .. . . . 311 AC and DC Specifications for (256 X 8) 2048-Bit Tn PROMs . . . . . . 312 (512 x 8) 4096-Bit Tn PROM Options . . . . . . . . . . . . .. .. . . . . . . . . . . 313 AC and DC Specifications for (512) 4096-Bit Tn PROM . . . . . . . . . . . 314 (512 X 8) 4096-Bit Tn PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
AC and DC Specification's for (512 x 8) 4096-Bit Tn
High-Speed PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
AC and DC Specifications for (512 x 8) 4K-Bit Registered
Tn PROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 AC and DC Specifications for (512 x 8) 4K_-Bit Registered Tn PROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Programming Parameters Do Not Test or You May Program the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Programming Parameters Do Not Test or You May Program the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Approved Programmers for NSC PROMs . . . . . . . . . . . . . . . . . . . . . . . . . 332 Quality Enhancement Program for Bipolar Memory . . . . . . . . . . . . . . 332
A.3.1 A.3.2
The eight test patterns used for testing the multiplexer of Figure A.4.4 ............... :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 A different sequence of the eight multiplexer test patterns . . . . . . . . 373
Programmable Logic
Design Guide
1
Introduction
1.1 PURPOSE OF THIS DESIGN GUIDE
This book was conceived to fill the need for a comprehensive Design Guide about Field-Programmable Logic Devices. The Guide is organized to serve both the experienced programmable logic user and the uninitiated. The primary objective of this guide is to introduce the uninitiated logic designer to programmable logic and to take the designer through a step-by-step approach to logic design by using programmable logic devices. The Guide is compreheµsive in that it covers all aspects of design, including: Boolean logic basics, sequential and combinational circuit basics, testing, and applications. Every effort has been made to clearly illustrate points with examples. National Semiconductor invites comments and suggestions from our users on improving this Design Guide.
1.2 OVERVIEW OF PROGRAMMABLE LOGIC
Programmable Logic has been used for many years as the means of customizing logic design. The early devices were primarily mask-programmed and were developed by computer manufacturers for in-house use while the vast majority of other logic users were relegated to the world of standard SSI/MSI devices. Then, in the mid to late seventies, along came fuse-programmable logic. The logic devices could actually be customized by the designer who used external pulses generated by simple programmer equipment. Now logic designers had devices that could be customized instantly and that offered higher integration than standard logic. Field-programmable logic devices became the first, true semicustom logic that was widely available for both the small and the larger user.
Today, the user can choose from a variety of speeds, power, packages, logic features and vendors.
The logic designer's task is being simplified even further by the rapid development of software tools that actually perform some of the design tasks such as logic minimization, higher level Boolean representation, device selection, and test vector generation. The final goal is to simply specify input-output or state descriptions in a high-level language to obtain a completely programmed and functionally tested device.
Technology developments are also taking place to achieve field-programmable logic devices in low-power CMOS technology and high-speed ECL technology.
1
2 Programmable Logic Design Guide 1.3 NATIONAL SEMICONDUCTOR, THE LEADER National Semiconductor, entered the field programmable logic marketplace in .1980 with the introduction ofthe PAL® device family. By 1984 National had taken the leadership of this market through technological advances and customer support. In particular, National is the first company to come out with the 15 ns high-performance family of PAL devices. National also has the broadest product line of programmable-logic products that will include CMOS and ECL products. National Semiconductor is committed to maintaining its leadership in this area through technological innovation, customer support and product quality.
PAL is a registered trademark of and used under. license to Monolithic Memories, Inc.
2
Programmable Logic Basics
2.1 WHAT IS PROGRAMMABLE LOGIC?
Programmable logic devices are essentially uncommitted logic gates where the user determines the final logic configuration of the device. Hence, programmable logic devices are true semicustom products. A major feature of these devices is fieldprogrammability, which offers almost instant customization. A mask-programmable option is also available for volume applications. The internal structure of these devices is a·fuse-programmable interconnection of AND gates, OR gates, and Registers. These devices allow the user to design combinational as well as sequential circuits. The basic programmable array is AND-OR logic in the familiar Sum-of-Products (SOP) representation. The conventional schematic representation is shown in Figure 2.1.1.
u:: A
B A
e
) )
02
_____ ....., A---.....f-""\AB
e----t-J
c-----1-,co
o - - - - t _ J---------r----------'""-1-1-...-""~""""'~---01
---------- A----r-""\AD
0-----1__~
Figure 2 .1.1 Conventional Representation
3
4 Programmable Logic Design Guide
Its programmable logic equivalent is shown in figure 2.1.2.
D
c
8
A
Figure 2.1.2 Programmable Logic Representation
Various programmable logic products are built around this structure by adding features and other logic elements such as programmable Active-Low or Active-High outputs, output registers, internal feedback, and state registers.
A definition of programmable logic is not complete without including software. An important part of these products is the software and design automation tools that aid systems design with programmable logic devices.
2.2 USER-BENEFITS OF PROGRAMMABLE LOGIC
The use of.programmable logic devices in systems design presents the user with many benefits, some of which are obvious and some of which are nqt. The versatility and power of programmable logic devices can be demonstrated through the most common benefits described below.
Reduced Board Space
Today, programmable logic typically implements from 4 to 20 SSI and MSI logic devices on a single chip. PC board real estate is one of the most valuable and limited items in a system and programmable-logic devices are ideal for reducing board space. This can allow the system manufacturer to reduce the size of a system or to increase the logic power for a system of a given size.
Programmable Logic Basics 5
Fast Systems Design
Fast turnaround in systems design can be achieved. Systems can be prototyped quickly by using available design automation development tools. Standard design tools reduce the need for manual design and documentation. After the first prototype has been built, modifications and correction to the logic can also be made quickly, without having to rewire or rework the PC board. The net result is that the programmable-logic user can enjoy a competitive advantage in the marketplace by bringing new products to market early.
Design Flexibility
Systems design is generally an iterative process. It starts with ideas and concepts and then progresses through an iterative series of evaluation, modification, and refinement of the original design. Numerous logic configurations have to be evaluated in this process and the painless way to perform these evaluatiOns is through the use of programmable logic. All of the changes can be made at the CAD terminal, which will also ensure that the documentation is updated to include the changes.
With the use of programmable logic, the designer is not limited to standard off the shelf parts and, therefore, can use non,-standard logic structures. The engineer now simply chooses what is needed instead of taking only what is available.
Design flexibility derived from using programmable logic means logic changes are easy in all phases of the system life cycle. For example, logic changes can be made during prototyping, during system testing, during system production, and in the field.
Many manufacturers need to be able to perform some final customization to the system. The use of programmable logic allows this customization to be implemented quickly.
Multilevel Logic Reduction
The designer can compress multiple levels of logic into a two-level AND-OR structure through the use of programmable logic, thus simplifying the design and in many cases obtaining a speed and/or power advantage. An example is shown on the following page in Figure 2.2.1.
Cost Reduction
The systems manufacturer can realize cost reduction by the use of programmable logic through a variety of factors, including:
· Lower component cost through - PC board area reduction. - Reduction in connectors used. - Simpler back panel. - Smaller power supplies. - Reduced cooling.
6 Programmable Logic Design Guide
LOGIC EQUATION
= F1 i [b + c(d +e) + i g) + hij + k
LEVEL 5 I LEVEL 4 1 LEVEL 3
I
I
I
d
I
LEVEL 1
k-----
AND/OR NETWORK
Figure 2.2.1 Multilevel Logic Reduction
· Lower design and development cost through - Quick-turnaround software-supported design. - Easy-to-make changes. - Computerized documentation. - Simplified layout.
· Lower manufacturing cost through - Fewer component insertions. - Fewer boards to manufacture. - Less component, board and system testing.
· Lower service costs through - Improved reliability. - Fewer spare parts. - Faster logic fixes.
Programmable Logic Basics 7
Example to Illustrate Lower Component Costs
Table 2.2 .1 is an example of the elements of component cost. The costs used are typical of those found in the ·industry and will have to be modified to reflect a specific situation.
Cost Varlable Purchasing, Receiving, Inventory ~ncoming Inspection PC Board Assembly Labor Connectors, Wire, etc. Power Supplies, Cooling System Assembly Rack, Cabinet, Panels Total Overhead IC Cost Total IC Cost in System
Cost Range $
0.01-0.03 0-0.15 10-100
0.10-0.40 30-100 45-120 40-80 20-50
0.12-2.00
Ave Cost $
0.02 0.08 30.00 0.20 60.00 60.00 60.00 30.00
Table 2.2.1 Typical Component Cost Structure
Cost/IC $
0.02 0.08 0.30 0.20 0.10 0.10 0.10 o.o5· 0.95 0.50 1.45
Assume a system with 600 SSI/MSI ICs. The total cost of the system is therefore as follows:
SSI/MSI System Cost = 600 x $1.45 = $870
PAL devices are used to replace the SSI/MSI discrete logic devices. The replacement can be accomplished at various efficiencies, where efficiency is defined as:
Efficiency = Average number of SSI/MSI devices replaced by one PAL.
If we assume that the cost of programming a PAL device is $0.40 then the total cost of a PAL based system is as follows:
PAL based system cost = - -60-0 - x (PAL Device Price + Overhead + Programming Cost) Efficiency
- -60-0 - x (PAL Device Price + $0.95 + $0.40) Efficiency
8 Programmable Logic Design Guide
Various efficiencies and PAL device prices are substituted in the above equation to obtain the PAL based system costs in Table 2.2.2 below.
Efficiency Factor (EF)
SSl/MSI System Cost (1)
PAL Device System Cost (2) at a PAL Device Purchase Price of
$8.00 $6.00 $4.00 $3.00
Your SSl/MSI System Cost
3:1
870
1870 1470 1070 870
4:1
870
1403 1103 803 653
6:1
870
935 735 535 435
8:1
870
701 551 401 325
(1) Cost = 600 ICs x 1.45/IC = $870 (2) · Cost = [600 + EF] x [PAL Device price + Overhead + Programming Cost]
= [600 + EF] x [PAL Device price + 0.95 + 0.40] = [600 + EF] x PAL Device price + 1.35
Your PAL Device System Cost @ /PAL Device
Table 2.2.2 System Cost Comparison Between SSI/MSI Based System and PAL Device Based System.
Most users realize at least a 4: 1 ratio and at today's PAL device prices, it is clearly more economical to use PAL devices. Furthermore, as prices decline, even low efficiencies become economical.
Example of Cost Reduction J"hrough Reliability Improvements
A simple example is used here to illustrate the power of PAL devices to improve system reliability. Assume that systems fail for only two reasons:
· External connection failures (70 %) - Solder. - Connectors. - Back plane wiring.
· IC failures (30%)
A hypothetical system is defined as having 5 boards each with 100 SSI/MSI devices. With the following assumptions:
- System is in use for 3 years. - Single device failure probability is 0.01 % within the 3 years. - Single device failure will cause board failure, which will result in system
failure. - 100 systems are sold. - $1000 cost for each system failure.
Programmable Logic Basics 9
The system failure probabilities and expected costs are computed below. SSI/MSI device-related board failure probability = 1 - (0.9999)100 = 0.009989 SSI/MSI device-related system failure. probability = 1 - (0.990011)5 = 0.0489583
External connection failure probability =
0.0489583 x 70 30
= 0.114236
Total system failure probability within the three years= 0.1631943 · Total Expected Cost from system failures during the three years= $1000 x 100 x
0.1631943;;::; $16,000
The logic designer now uses PAL devices and other LSI devices to realize a 5: 1 SSI/MSI chip replacement. The system will now have one board. The system failure probability and expected cost of the PAL device-based system is computed below:
Device-related board failure probability
= 1 - (0.9999) 100 = 0.009989
0. 009989 x 70 External connection failure probability =
30
= 0.023307666
Total PAL device-based system failure probability = 0.033296666
Total Expected Cost of PAL device based system= $1000 x 100 x 0.033296666
~$3300
On comparing the expected costs from system failures of the SSI/MSI based system to that of the programmable-logic based system, there is approximately a 5: 1 ratio of cost in favor of the programmable-logic based system.
This example is somewhat simplistic and some gross assumptions were made to illustrate the advantages of using programmable logic. In reality, the actual reliability improvement will depend on numerous factors that have not been addressed here.
Small Inventory
The programmable logic family can be used to replace up to 90% of TTL components.
This allows the user to lower inventory costs considerably, in addition to simplifying
the inventory system.
·
10 Programmable Logic Design Guide 2.3 ELEMENTS OF PROGRAMMABLE LOGIC The first programmable integrated circuit logic device was the diode matrix. It was introduced in the early 1960s. This approach featured rows and columns of metallization, connected at the crosspoints with diodes and aluminum fuses (Figure 2.3.1). These fuses could be selectively melted, leaving some of the crosspoints open and others connected. The result was a diode-logic OR matrix.
Figure 2.3.1 Diode OR Matrix
The PROM Integrated circuit designers added input decoders and output buffers to the basic diode matrix, creating the field-programmable read-only memory (PROM) (Figure 2.3.2). This extended the programmable-logic concept considerably, since the input variables could now be encoded. It also reduced the number of pins required per input variable. At the same time, the input circuitry, along with the output buffers, provided TTL compatibility, the lack of which was one of the drawbacks of the diode matrix. For the sake of simplicity and clarity, the programmable diode matrix is shown at a simple crosspoint in Figure 2.3.3
A decoder is nothing more .than a collection of AND gates that combine all the inputs to produce product terms. The basic logic implemented by the PROM is AND-OR with the AND gates all preconnected on the chip, making this portion fixed.
Programmable Logic Basics 11
The OR matrix is implemented with diode-fuse interconnections, making it programmable. Thus, the PROM is an AND-OR logic element with fixed AND matrix and programmable OR.
There are many advantages to using PROMs as logic devices. Because they are used in many applications, they are produced in high volume. Also, the PROM is a universal logic solution. In other words, all of the product terms of the input variables are generated. This makes it possible to implement any AND-OR function of these variables.
On the less positive side, it is difficult to accomodate a large number of variables with PROMs. For each variable added to the PROM, not only does the package increase by one pin, but the size of the fuse matrix doubles. For example, an eight-function, five-variable PROM (32 x 8) requires a 256-fuse element matrix. An eight-function, six-variable device (64 x 8) requires a 512-element matrix. As a practical matter, PROMs are limited in the maximum number of input variables they can be designed to handle. Manufacturers are currently producing no larger than 13-input PROMs.
r-----------, DECODER AND
I
1112
FUSE MATRIX (OR)
12~-----<1~~-------~~~---t
L----------.J
F3
Figure 2.3.2 4 x 4 Bit Prom
12 Programmable Logic Design Guide
"OR" ARRAY (PROGRAMMABLE)
"AND" ARRAY · (FIXED)
Figure 2.3.3 PROM with 16 Words x 4 Bits
The FPLA The Field-Programmable Logic Array (FPLA) overcomes some of the size restrictions of PROMs because its designers recognized that not all product terms are required to
Programmable Logic Basics 13 implement most logic functions. By having a second fuse matrix (an AND matrix), the FPLA allows the designer to select and program only those product terms used in each specific function (Figure 2.3.4). These product terms are then combined in the OR fuse array to form an AND-OR logic equation.
"OR" ARRAY (PROGRAMMABLE)
"AND" ARRAY (PROGRAMMABLE)
Figure 2.3.4 FPLA with 4 Inputs, 4 Outputs, and 16 Products
14 Programmable Logic Design Guide
In addition to specifying the number of inputs and functions, the FPLA manufacturer must also specify the number of product terms available, since there are less than
zn terms (with n as the number of input variables). The fact that the number of product terms is less than zn is what allows the FPLA to accommodate larger values of n, i.e.,
more inputs. This is in contrast to the PROM where the number of product terms is
always equal to zn.
Although the FPLA usually requires less fuses to implement a given logic function, the additional fuse matrix does pose some difficulties of its own. The biggest problem is the circuitry required to select and program these fuses - circuitry that is not used in the final logic solution, but which is paid for in die area. This "chip overhead" cost is not significant if the FPLA's capabilities are fully utilized, but it does become significant for less complex problems that leave unused logic.
As has been shown, PROMs provide all of the product terms for a limited number of input variables in generating AND-OR logic functions. FPLAs, on the other hand, provide a limited number of product terms for a larger numb~r of input variables. However, the FPLA is unrestricted in combining the product terms in the OR matrix, which adds considerable flexibility to this device.
Because of the dual fuse matrix and the overhead cost of the circuitry required for programming, the FPLA cannot be used economically in some low complexity logic problems. The cost saving associated with the removal of the AND matrix (by hardwiring it) is evident when one compares price. PROMs cost less than FPLAs. As mentioned, however, the PROM approach significantly restricts the number of input variables.
The PAL (Programmable Array Logic) Device
Savings similar to th9se of PROMs could be made without the penalty of restricting the input variables, by removing the OR matrix from the FPLA, or hardwiring it. In the PAL device concept (Figure 2.3.5), the AND fuse array allows the designer to specify the product terms required. The terms are then hardwired to a predefined OR matrix to form AND-OR logic functions.
An immediate observation is that because the OR gates in PAL devices are prewired, the degree to which the product terms can be combined at these OR gates is restricted. PAL devices partially compensate for this by offering different part types that vary the OR-gate configuration. Specifying the OR-gate connection therefore becomes a task of device selection rather than of programming, as with the FPLA. With this approach, PAL devices eliminate the need for a second fuse matrix with little loss in overall flexibility.
Programmable Logic Basics 15
"OR" ARRAY (FIXED)
"AND" ARRAY (PROGRAMMABLE)
Figure 2.3.5 PAL Device Having 4 Inputs, 4 Ouputs, and 16 Products
16 Programmable Logic Design Guide
Comparison
To illustrate the difference among the three most popular field-programmable logic concepts, the same four logic expressions will be solved with each, as shown in Figure 2 .3 .6(a). For comparison, each of the approaches is shown as an AND matrix, followed by an OR matrix. The PROM solution shown in Figure 2.3.6(b) requires a 16-fuse
A B
FUSIBLE OR
LOGIC EQUATIONS F1 =A F2=AB Fa=A+B F4=AB+AB
(a)
PROM HARD AND
A B
HARD OR
A B
FUSIBLE OR
---------A
PAL
FPLA
--------8 -----t----n,.-AB
---+---t----AB
---+---+----+--A ---+---+----+--"0" --------AB ------+----+--"0"
----------------A8
t--1---+---+---.-'Ae
--------AB
FUSIBLE AND
FUSIBLE AND
F1 F2 Fa F4
(c)
(d)
Figure 2.3.6 (a) Logic Equation, (b) PROM Solution, (c) FPLA Solution and (d) PAL Device Solution
Programmable Logic Basics 17
matrix, whereas the FPLA and PAL device require 32 fuses each. If we were to add another input varia.ble, the number of fuses in a PROM increases to 32, while the FPLA needs only 8 more and the PAL device needs 16 more. A fourth input again doubles the number of PROM fuses to 64, but adds only 8 to the FPLA and 16 to the PAL device. This example illustrates the previous statement that as the number of inputs increases, PROMs consume more .fuses than either FPLAs or PAL devices.
2.4 PROGRAMMABLE LOGIC VERSUS OTHER LSI, SEMICUSTOM AND CUSTOM ALTERNATIVES
Logic designers are noticing an apparent "complexity gap" between TTL and LSI. Products designed with discrete TTL devices would consume unacceptable amounts of ·physical space and electrical power. Software-programmable LSI devices (microprocessors) offer high density and need relatively little power to operate. But the designer pays a high price in software development and still has to use discretes to interface them to the outside world. Until recently, there has been no device that provides a really effective way of bridging this gap. National has seen this need, and now offers the designer a family of PAL (Programmable Array Logic) devices to fill it. PAL devices offer powerful capabilities for creating cost-effective new products· or for improving the effectiveness of existing logic designs. PAL devices save time and money by solving many of the system partitioning and interface problems not otherwise effectively solved by today's semiconductor device technology.
Standardized LSI
LSI (Large Scale Integration) offers many advantages, but advances have been made at the expense of either device flexibility or software complexity. LSI technology has been and still is leading to larger and larger standard logic functions. LSI offers high functional density and low power consumption; single ICs now perform functions that formerly required complete circuit cards. However, most LSI devices don't interface with user systems without large numbers of support devices. Designers are still forced to turn to random logic for many applications. LSI is slow, and it is rigidly partitioned. For all its capability to perform varied and complex tasks, the microprocessor is a slow and expensive way of doing simple, repetitive tasks when the necessary interface and other support devices are added. And, when the time, money, and memory required for software development are considered it is even more expensive.
Full Custom IC's
Custom IC's can be effective design solutions if the product is of low-to-medium complexity, its logic function is well-defined, and its market is high-volume. Its design cycle is typically long, and its cost can be prohibitive. This tends to discourage its use.
18 Programmable Logic Design Guide
Gate Arrays
A close relative of the custom circuit is the gate array. With gate arrays, the total logic capability of the chip, its pinouts, and its performance are predefined by the semiconductor manufacturer. The user specifies only the logic interconnection pattern, a process much the same as interconnecting standard small-scale integration (SSI) logic circuits. since only a metallization pattern is required, the setup costs and turnaround time for gate arrays are lower than for custom circuits, but because the designer can seldom utilize· the entire logic capability of the chip, the unit cost· per active element is often higher. The setup costs and turnaround time for gate arrays are considerably higher than that for programmable logic, which has practically no turnaround delay.
3
Boolean Logic Review
3.1 BASIC OPERATORS AND THEOREMS
A gate is an electronic circuit which operates on one or more input signals to produce an output signal. There are three basic gates from which all other logic can be realized: AND, OR, and INVERTER gates. Figure 3.1.1 shows these three basic gates and their truth table.
A
)
F
B
(A) AND GATE
A B
D
F
(B) OR GATE
A I>
F
(C) INVERTER
INPUT
A
B
0
0
o·
1
1
0
1
1
INPUT
A
B
0
0
0
1
1
0
1
1
INPUT
A
0 1
OUTPUT
F 0 0 0 1
OUTPUT
F 0 1 1 1
OUTPUT
F
1 0
Figure 3.1.1 Basic Gates
To express the function of these gates by Boolean"' algebra, we ne.ed to define Boolean operators as follows:
= Logical Equality Negate (not, invert, complement)
+ OR (sum) · AND (product) : +: Exclusive OR :·: Exclusive NOR
19
20 Programmable Logic Design Guide
The function of an AND gate in Figure 3.1.1 can be expressed as:
F =Ao B
The function of an OR gate and INVERTER can .be expressed as:
F =A+ B
and
F =A
Boolean operators are logical operators, which are different from arithmetic oper-
ators. For example, + is logical addition, o is logical multiplication. We call such equa-
tions Boolean equations or logic equations. A number of logic theorems and laws will be used to manipulate and reduce logical
equations. These theorems and laws are as follows:
Theorem 1 Theorem 2 Theorem 3 Theorem 4 Theorem 5 Theorem 6 Theorem 7 Theorem 8 Theorem 9 Theorem 10 Theorem 11 Theorem 12 Theorem 13
A+ 0 AoO
= A.
= o·
A+ 1
= 1
Ao 1
= A
A+ A
= A
Ao A
-A
A+A
= 1
Ao A
= 0
A..
= A
A+ Ao B = A
A(A + B)
= A
(A+ B)·(A + C) = A + B·C
A+ Ao B = A + B
Commutative Law
A+B =B+A AoB =Bo A
Associative Law
A + B + C = (A + B) + C = A + (B + C) A o B o C = (A o B) o C = A · (B · C)
Distributive Law
A + (B o C o D) = (A+ B) o (A + C) · (A + D) A o (B + C + D) = A · B + A · C + A · D
DeMorgan's Theorem
(A+ B + C) =A·B·C (A o B o C) =A+B+c
·George Boole was the son ofa shoemaker. His formal education ended in the third grade. Despite this, be was a brilliant scholar, teaching Greek and Latin in his own school, and an accepted mathematician who made lasting contributions in tbe areas of differential and difference equations as well as in algebra.
Boolean Logic Review 21
The complement of any Boolean expression, or a part of any expression, may be found by means of DeMorgan's theorem. Two steps are used to form a complement in this theorem:
1. OR symbols are replaced with AND symbols or AND symbols with OR symbols.
2. Each of the terms in the expression is complemented.
DeMorgan's theorem is one of the most powerful tools for engineering applications. It is very useful for designing with programmable logic devices because it provides a quick and simple conversion method between PRODUCT-OF-SUMS and SUM-OF-PRODUCTS expressions, which will be defined later.
3.2 DERIVATION OF A BOOLEAN EXPRESSION
Any logic expression can be reduced to a two-level form and expressed as either a SUM-OF-PRODUCTS (SOP) or PRODUCT-OF-SUMS (POS). Before we define SOP or POS, we need to define "terms."
1. Product Term - A product term is a single variable or the logical product of several
variables. The variable may or may not be complemented.
·
2. Sum Term - A sum term is a single variable or the sum of several variables. The variables may or may not be complemented.
3. Normal Term - A normal term is a product or sum term in which no variable appears more than once.
4. Minterm - A minterm is a product term containing every variable once and only once (either true or complemented).
5. Maxterm - A maxterm is a sum term containing every variable once and only once (either true or complemented).
For example, the term A · B · C is a product term; A + B is a sum term; A is both a
product term and a sum term; A + B · C is neither a product term nor a sum term; A +
B is a sum term; A · B · C is a product term; Bis both a sum term and a product term.
We now define two most important forms:
1. SUM-OF-PRODUCTS Expression -A sum-of-products expression is a product term or several product terms logically added together.
2. PRODUCT-OF-SUMS Expression - A product-of-sums expression is a sum term or several sum terms logically multiplied together.
For example, the expression A ·. B + A · B is a sum-of-products expression;
(A + B) · (A + B) is a product-of-sums expression.
22 Programmable Logic Design Guide·
One prime reason for using sum-of-products or product-of-sums expressions is their straightforward conversion to very simple gating networks. In their purest, simplest form they go into two-level networks, which are networks for which the longest path through which a signal must pass from input to output is two gates long.
When designing a logic circuit, the logic designer works from two sets of known values; .the various states which the inputs to the logical network can take, and the· desired outputs for each input condition. The logic expression is derived from these sets of values and the procedure is as follows:
1. Construct a table of the input and output values (Table 3.2.1 left halt).
2a. To derive a SUM-OF-PRODUCTS (SOP) expression: A product term column is added listing the inputs A, B, and C according to their value in the input columns (Table 3.2.1). Then the product teqns from each row in which the output is a "1" are collected.
Therefore:
F=A·B·C +A·B·C + A·B·C
(Eq. 3.2.1)
2b. To derive a PRODUCT-OF-SUMS (POS) expression: A sum term column is added listing the inputs A, B and C according to their complement value in the input columns (Table 3.2.1). Then the sum terms from each row in which the output is "O" are collected.
Therefore:
= F (A + B + .C) (A + B + C) (A + B + C) (A + B + C) (A + B + C)
(Eq. 3.2.2)
Inputs
A
B
c
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Outputs
F
0 0 1 1 0 0 1 0
Product Terms
ABC ABC ABC ABC ABC ABC ABC ABC
Sum Terms
A+B+C A+B+C A+'B+C A+B+C A+B+C A+B+C A+B+C A+B+C
Table 3.2.1 Truth Table of Eq. 3.2.1 and Eq. 3.2.2
Figure 3.2.1 is the logic circuit which direct derived from Eq. 3.2.1. Figure 3.2.2 is derived from Eq. 3.2.2.
Boolean Logic Review 23
Eq. 3.2.1 can be simplified as shown below:
F =A·B·C+.A·B·C+A·B·C =A · B (C + C) + A · B · C =A·B+A·B·C =B (A + A· C) =B (A + C) =A·B + B·C
Eq 3.2.2 can be simplified as shown:
F=~+B+q~+B+~~+B+q~+B+~~+~+~ = (A + B) (A + B) (A + C) = B (A + C) =A·B+B·C
The two final expressions obtained are identical and can be implemented by: the circuit shown in Figure 3.2.3. This is much simpler than the circuits in Figures 3.2.1 and 3.2.2. This simplified procedure is called minimization.
A.------r~
CB----- ---------- -t.-...~___J~----------
t---------------1 B----------1 A-----__.~,
c--------1~J
A _ _ _ _ _ ___,.---
~ -------t_J
Figure 3.2.1 Logic Circuits of Eq. 3.2.1
A
C B
--------------t-...-._-r_.,..,.,.
>
-
-
-
-
-
-
-
-
-
gA------.....----...... >---------
~ ---------r-----.....>-------i=i~~~~=)------ F
AcB -----------i-Lr-_._..,.,.,.,.,>-------
e > - - - - - A. _______.----...._
Figure 3.2.2 Logic Circuits of Eq. 3.2.2
24 Programmable Logic Design Guide
Figure 3.2.3 Simplified Logic Circuits 3.3 MINIMIZATION Logic circuits can be represented by logic expressions or so called logic equations. As discussed, we can minimize the logic circuit through logic equations minimization. For example, Figure 3.3.1 can be expressed by Eq. 3.3.1.
B A--~--+----.-.1.-~..,_ __
c --......................____.,,,
F
Figure 3.3 .1 A Random Logic Circuit
F = (A · B · C + D) · (B + D) + A o C · (B + b) (Eq. 3.3.1) By using the theorems and laws mentioned in 3.1, we minimize Eq. 3.3.1 as follows:
F = AoB·C + BoD + AeBoCoD + D + A·C·B + AoCoD
= A · B · C (1 + D) + D (B + 1) + A· C · B + A o Co D Distributive Law
= A· B· C + D + A·C· B + A·Co D
Theory 3
= A · B (C + C) + D (1 + A· C)
Distributive Law
= A· B + D.
Boolean Logic Review 25
The minimum SOP expression can now be implemented as the simple AND-OR logic circuits as shown in Figure 3.3.2.
:_____o-------.
D
D>----- F = AB+ D
Figure 3.3.2 Minimized Logic Circuit
We can use Boolean Algebra to reduce the number of product terms. However, Karnaugh Mapping and the Quine-McCluskey method are two other powerful tools to minimize the logic equations. We'll discuss Karnaugh Mapping method in the next section.
3.4 K-MAP METHOD
A Karnaugh map, hereafter called a K-map, is a graphical method for representing a Boolean function. It is similar to a truth table in that the K-map supplies the TRUE or FALSE value of a Boolean function for all possible combinations of its logical argument. There are many ways in which a K-map can be arranged. The most important considerations of the arrangement are:
1. There must be a unique location on the K-map for entering the TRUE/FALSE value of the function that corresponds to each combination of input variables.
2. The locations should be arranged so, with minimization mentioned in Section 3.3, that they are readily apparent to the trained observer.
The second consideration implies that a successful K-mapping arrangement should point to groups of minterms or maxterms that can be combined into reduced forms. K-maps are also useful in expanding partially reduced expressions into standard forms prior to the minimization process.
The K-map is one of the most powerful tools at the hands of the logic designer. The power of the K-map does not lie in its application of any marvelous new theorems, but rather in its utilization of the remarkable ability of the human mind to perceive patterns in pictorial representations of data. This is not a new idea. Anytime we use a graph instead of a table of numerical data, we are utilizing the human ability to r_ecognize
26 Programmable Logic Design Guide
complex patterns and relationships in a graphical representation far more rapidly and surely than in a tabular representation. A few examples of how to create· a K-map follow.
First, consider a truth table for two variables. We list all four possible input combinations and the corresponding function values, i.e., the truth tables for AND and OR. (Figure 3.4.1)
A B A·B
0 0
0
0 1
0
1 1
1
1 0
0
A B
0 0 0 1 1 1 1 0
A+B
0 1 1 1
Figure 3.4~ 1 Truth Tables for AND and OR
As an alternative approach, set up a diagram consisting of four small boxes, one for each combination of variables. Place a "1" in any box representing a combination of variables for which the function has the value 1. There is no logical objection to putting "O's" in the other boxes, -but they are usually omitted for clarity.
The diagrams in Figure 3.4.2(a) are perfectly valid K-maps, but it is more common to arrange the four boxes in a square, as shown in Figure 3.4.2(b).
~B 00
01
11
10
~B 00
01
11
10
I
I
A+B
(A)
A
B
0
1
0
A
B
0
1
0
1
1
1
'
1
1 '
1
A+B (B)
Figure 3.4.2 K-maps for AND and OR
Boolean Logic Review 27
Since there must be one square for each input combination, there must be 2n squares in a K-map for n-variables. Whatever the number of variables, we may interpret the map in terms of a graphical form of the truth table (Figure 3.4.3(a)) or in terms of union and intersection of areas (Figure 3.4.3(b)).
The K-maps for some other three-variable functions are shown in Figure 3.4.4. Particularly note the functions mapped in Figure 3.4.3(a) and 3.4.4(b). These are both minterms. Each is represented by one square, obviously, and each one of the eight squares corresponds to one of the eight minterms of three variables. This is the origin of the name minterm. A minterm is the form of Boolean function corresponding to the minimum possible area, other than 0, on a K-map. A maxterm, on the other hand, is the form of Boolean function corresponding to the maximum possible area, other than 1, on a K-map. Figure 3.4.3 (b) and 3.4.4 (c) are two examples.
A B c
0 o. 0
00 1 01 0 01 1 10 0 10 1 11 0 11 1
A·B·C
0 0 0 0
O'
0 0 1
A
AB
c 00
01
0
11
10
1 (a)
1
A·B·C
A
B A
B A
1
1
1
c 1
1
1
1
c 1
1
1
1
J
B
B
A + B + C = A+B+C
(b)
Figure 3.4.3 K-Maps for 3-variable AND and OR
28 Programmable Logic Desigri Guide
A
AB
c 00
01
11
10
0
1
1
B AC+AC
(a) A
ABC
(b)
AB
c 00
01
11
10
0
1
1
1
1
1
1
B
A+B+C
(c)
C+AB (d)
Figure 3.4.4 Sample 3-variable K-maps
Since each square on a K-map corresponds to a row in a truth table, it is appropri-
ate to number the squares just as we numbered the row. These standard K-maps are
shown in Figure 3.4.5 for two and three variables. Now, if a function is stated in the
form of the minterm list, all we need to do is enter l's in the corresponding squares to
produce the K-map.
·
A
B
0
1
0 0
2
AB
C
00
01
11
10
0 0
2
6
4
1 1
3
1 1
3
7
5
Figure 3.4.5 K-maps for Two and Three Variables
If a function is stated as a maxterm list, we can enter O's in the squares listed or l's in those not listed.
A map showing the O's of a function is a ·perfectly valid K-map, although it is more common to show the l's.
Boolean Logic Review 29
For example, the K-map of f(A, B, C) = m(O, 2, 3, 7) is shown in Figure 3.4.6 and the K-map of f(A, B, C) = M(O, 1, 5, 6) is shown in Figure 3.4.7. where m means minterm, M means maxterm.
AB
c 00
01
11
10
0 1
1
1
1
1
Figure 3.4.6 K-map of m(O, 2, 3, 7)
AB
c 00
01
11
10
0 0
0
1 0
0
AB
c 00
01
11
10
0 OR
1
1
1
1
1
Figure 3.4.7 K-map of M(O, 1, 5, 6)
As shown, the K-map can be generated from the truth table on minterm expression or maxterm expression. For the remainder of this section, we will learn how to minimize the minterm expression by using the K-map.
The general principle of this minimization technique is "Any pair of n-variable minterms which are adjacent on a K-map may be combined into a single product term of n - 1 literals." The definition of "adjacent" should include opposite edges of the K-map, for instance, Figure 3.4.8(a) and 3.4.8(b) both have a pair of adjacent minterms.
(a)
(b)
Figure 3.4.8 Adjacent Minterms on a K-map
30 Programmable Logic Design Guide
Consider this function f(A, B, C) = m(O, 1, 4, 6)
= ABC + ABC + ABC + ABC
Which results on the K-map, on the pattern shown in Figure 3.4.9
AB
c
00
0
r----1
0 1
1 1 1
01
11
l 2
6
1
3
7
10 4
1 J
5
Figure 3.4.9 Minimization
Therefore, combine minterms 0 and 1, 4 and 6 to get a minimal expression:
f(A, B, C) =AB + AC
Figure 3.4.10 shows some examples. Notice that it is permissible to include a minterm in several terms if it helps make the term shorter.
AB
CD
00
01
11
10
00 1 ]
1 '[ 1
.-- '---
01
1
11
1
....______.
~
10
1
AB
CD
00
01
11
10
00 1
1
01
1
1
11
1
1
10 1
1
Figure 3.4.10 Minimization
Boolean Logic Review 31
Quite often, some of the possible combinations of input values never occur. In .this case, we "don't care" what the function does if these input combinations appear. The K-map makes it easy to take advantage of these "don't care" conditions by letting the "don't care" minterms be I or 0, depending on which value results in a simpler expression. Figure 3.4.11 shows an example of the use of "don't cares" (redundancies) to simplify the terms.
c0 AB 00
01
00 x
·x
01
11
10
j 1
11
l10 1
x
1
1 J
Figure 3.4.11 Minimization
When working with larger functions, the tabular reduction developed by Quine and modified by McCluskey is an alternative to the K-map method. The Quine-McCluskey minimization method involves simple, repetitive operations that compare each minterm that is present in a sun-of-minterms expression for a Boolean functions to all other minterms with which it may form a combinable grouping.
The reader can refer to "Introduction to Switching Theory and Logic Design" by Hill and Peterson to understand the Quine-McCluskey method.
3.5 SEQUENTIAL CIRCUIT ELEMENTS
Us~ally the subject of logic design is.subdivided into two types: sequential and combinational. A purely combinational logic subsystem has no memory. Its outputs are completely defined by its present inputs. The analysis and design of combinational logic is much easier. A sequential logic subsystem has memory and its outputs are functions of not only present inputs but the previous outputs. Circuits of multiplexer/selector, decoder/encoder, adder, and comparator are examples of combinational circuits. Shift register, counter, state machine, and memory controller are examples of sequential circuits.
32 Programmable Logic Design Guide
DATA-.;....,.n _.,. Q"+ 1 : D" CLOCK--u
on an+1
0
0
1
1
- - u --~- .... Q"·1 =ff·Q+T·Gi)"
--ns.a --i>an+1=(S+R·S·a)" . R0 S:it: 1
-- c
-- R
- - v a -~an+1=(J·Q+K·a)"
-- c
.
--
K
T"
an+1
0
an
1
(Q)"
R s . an+1
0 0
an
0 1
1
1 0 1 1
0
x
J K
0 0 0 1 1 0 1 1
an+1
an
0 1 (O)"
Figure 3.5.1 Basic Flip-Flops
Just as we have a logic gate as the basic combinational circuit element, we have a flip-flop as a basic sequential circuit element. A flip-flop is a memory device which can remember, or store, a binary bit of information. There are four basic flip-flop types: (1) D flip-flop, (2) T flip-flop, (3) RS flip-flop, and (4) JK flip-flop. Figure 3.5. l sbows these elements and their truth table.
With the memory elements, the output does not change as a function of the inputs until the clock transition. Therefore, a superscript notation is used to indicate that the output during clock period n + 1 is a function of the inputs during the previous clock period n.
The D (delay) flip-flop means the input (D) is "stored" in the flip flop when the clock occurs and will appear on the output (Q) during the next (n + 1) clock time. The D flip-flop is thus very much like a single-bit RAM. It is very useful for data storage and· other special applications.
The other three types of flip-flops defined in Figure 3.5.1 are also one-bit storage elements, but instead of simply storing the input, they change state in response to the inputs by various logical rules. Since they hold their previous state in spite of the clock, unless an input goes true, they often simplify the combinational logic functions required to control them in control applications.
Boolean Logic Review 33
The T (toggle) flip-flop, for example, stays in its previous state if the T input is false
before the clock. If the T input is true, the output changes to the opposite state (toggle)
on the clock. The T flip-flop is thus useful, for example, in binary counters where we
want each bit to invert every time there is a carry from the lower order bits.
The R-S flip-flop sets after the S input is true and resets after the R input is true. Its
output is undefined if both Rand Sare true. It is possible to define a Set Overrides Reset
(SOR) or a Reset Overrides Set (ROS) flip-flop. It will set or reset respectively if both the
Rand the S inputs are true.
The J-K flip-flop sets after] is true and resets after K is true. It is similar to an R-S
flip-flop except that if] and Kare both true, the output changes to the opposite state
(toggle). It can be used as a T flip-flop by tying the] and K inputs together.
Since theJ-K flip-flop can essentially do the job of both the R-S and the T flip-flop,
the R-S and the T flip-flops are seldom seen. The choice is between J-K flip-flops for
small counters and control or D flip-flops for data storage applications. Actually the J-K
flip-flop can even do the job of the D flip-flop with the addition of a single inverter, as
shown in Figure 3.5.2.
·
J
Q
o- ---
CLOCK
Figure 3.5.2 Implement D Flip-Flop by Using J-K
Another memory element type, called a latch, is often described on data sheets with a truth table like the one for the D flip-flop in Figure 3.5.1. It is definitely not like a D flipflop, however because the output changes as soon as the clock goes high and does not "latch" until the clock falls (if the input changes while the clock is high, the output follow it). Because of this characteristic, a latch is not usable in the synchronous logic.
34 Programmable Logic Design Guide
3.6 STATE MACHINE FUNDAMENTALS
The relationships among present-state variables, primary input variables, next-state (or excitation) variables, and primary output variables that describe the behavior of a sequential system can be specified in several ways. As an example, consider the simple sequential system that is shown in Figure 3.6.1.
- - - - - - - F 11------1-··\..- -....
y
y
12----+----------.....,_~
y
y
DELAY
Figure 3.6.1 A Typical Sequential Circuit
This system has two primary input variables, having four different combinations of
values. There is one primary output variable and one state variable. It uses delay for
memory. There are only two possible present states: y = 0 and y = 1. When combined
with the four input combinations, these give eight different total present states. The values of the next-state variable, Y, and the primary output variable, F, must be specified
for each total present state. The tabular arrangement shown in Table 3.6.1 is a common method for presenting this information. This descriptive tool is called a state table.
PRESENT- STATE
y 0 1
NEXT-STATE y
= 1112 00 01 10 11
0 1 01 0 1 11
OUTPUT F
= 11 12 00 01 10 11
0 0 0 0
00 11
Table 3.6.1 State Table
Boolean Logic Review 35
Q 0, 0/0
1, 0/0
(::0
0, 1/0 1, 1/0
0, 1/0
Figure 3.6.2 State Diagram
A second method for describing the behavior of a sequential system is the use of a state diagram. This method presents a pictorial representation of the present-state/next-state sequences that apply to the sequential device. State changes are marked with directed arrows, with the primary input and output conditions that apply to each state transfer given beside the arrows. The state diagram for the system of Figure 3.6.1 is shown in Figure 3.6.2. A slash separates the input information from the output information.
State tables and state diagrams are essential tools in the analysis and design of sequential digital systems. The reader should be familiar with these two tools by reading the references listed in the end of this section.
36 Programmable Logic. Design Guide
Because a sequential system has feedback from its outputs to its input, certain types of instabilities and uncertainties can occur. When present, these conditions make the operation of circuit difficult or impossible to describe. They may even render the circuit useless, since its behavior may not be predictable or consistent. Several of these types of problems are listed below.
1) The input or output conditions of the system may be indeterminant. For example, the circuit in Figure 3.6.3.
Figure 3.6.3 Example of Hazard Circuit
2) The output condition of the system may be unstable, changing even though the external inputs do not change. Figure 3.6.4. illustrates an example.
..,________. . .,. >c:i--~------
F
DELAY
Figure 3.6.4 Example of Unstable Circuit
Boolean Logic Review 37
3) The output condition of the system, even though stable, may not be predictable depending upon the primary input conditions. Figure 3.6.5 is an example.
11------------. . .-""\ .... .-------t.-~-------------------- -----------F1
12 ______....,______,-,
. - -......_ ,.....-------------------+--....- - - - - - - - F 2
DELAY
DELAY
Figure 3.6.5 Example of Circuit with Unpredictable Output States
However, these problems mentioned above can be avoided by making certain restrictions in the way sequential systems are designed and used. For instance, the following are some restrictions: 1. Avoiding continuing instabilities (oscillations). 2. Allowing only fundamental-mode operation. 3. Allowing only pulse-mode operation.
References Hill & Peterson "Introduction to Switching Theory and Logical Design" Kohavi "Switching and Finite Automata Theory" Rhyne "Fundamentals of Digital Systems Designs" Krieger "Basic Switching Circuit Theory."
4
The Programmable Logic Family
National's programmable logic family consists of PAL devices and PROMs that come in a variety of gate densities, pin-counts, architectures, speed and power specifications. The following sections describe and tabulate these various options in addition to displaying the logic schematics.
4.1 BASIC GROUPS
The programmable logic devices are divided into two sections: one to address PAL devices and the other to address PROMs.
4.2 THE PAL DEVICE FAMILY
The PAL device family is separated by pin-count and by architecture. There is a 20-pin family and a 24-pin family. Each family contains simple combinational logic devices and more complex devices which have on-chip feedback options and output registers. The 20-pin small PAL devices and the 20-pin medium PAL devices are listed in Table 4.2 .1.
Part No.
10H8 12H6 14H4 16H2 10L8 12L6 14L4 16L2 16C1 16L8 16R8 16R6 16R4
No. of Inputs
10 12 14 16 10 12 14 16 16 10
8 8 8
No. of Outputs
8 6 4 2 8 6 4 2 1 8 8 8 8
No. of I/Os
6 2 4
No. of Registers
8 6 4
Output Polarity
AND-OR AND-OR AND-OR AND-OR AND-NOR AND-NOR AND-NOR AND-NOR AND-OR/NOR AND-NOR AND-OR AND-OR AND-OR
Functions
AND-OR Array AND-OR Array AND-OR Array AND-OR Array AND-OR-Invert Array AND-OR-Invert Array AND-OR-Invert Array AND-OR-Invert Array AND-OR/AND-OR-Invert Array AND-OR-Invert Array AND-OR-Invert Register AND-OR-Invert Register AND-OR-Invert Register
Table 4.2.1 Members of the 20-Pin PAL Device Family 39
40 Programmable Logic Design Guide
The 24-pin PAL devices are listed in Table 4.2.2 and Table 4.2.3 shows how to read the part numbers.
Part No.
12L10 14LB 16L6 18L4 20L2 20LB 20L10 20RB 20R6 20R4 20X10 20XB 20X4
No. of Inputs
12 14 16 18 20 14 12 12 12 12 10 10 10
No. of Outputs
10 8 6 4 2 2 2 8 ,6 4 10 8 4
No. of I/Os
6 8 2 4 2 6
No. of Registers
8 6 4 10 8 4
Output Polarity
AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR
Functions
AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert w/Registers AND-OR Invert w/Registers AND-OR Invert w/Registers AND-OR-XOR Invert w/Registers AND-OR-XOR Invert w/Registers AND-OR-XOR Invert w/Registers
Table 4.2.2 Members of the 24-Pin PAL Device Family
-- ---------
PROGRAMMABLE LOGIC - FAMILY PAL FOR PAL DEVICES NL FOR NATIONAL MASKED.LOG PL FOR FACTORY PROGRAMMED PAL DEVICE
- - - - - - - - - - NUMBER OF ARRAY INPUTS
- -· - - - - - -OUTPUT TYPE: H =ACTIVE HIGH .L =ACTIVE LOW
. C =COMPLEMENTARY
R=REGISTER X =EXCLUSIVE-OR WITH
REGISTER P =PROGRAMMABLE
OUTPUT POLARITY
- - - - - - NUMBER OF OUTPUTS
- - - -SPEED RANGE
---NO SYMBOL= STANDARD SPEED A= HIGH-SPEED A2 =HIGH-SPEED, HALF-POWER B =ULTRA HIGH SPEED, ETC.
PACKAGE TYPE: N =PLASTIC DIP
rI J =CERAMIC DIP V =PLASTIC LEADED CHIP CARRIER
-TEMPERATURE RANGE:· C=O TO +75 DEG. C
. M = - 55 TO + 125 DEG. C
Table 4.2.3 PAL Device Part Number Interpretation
The Programmable Logic Family 41
PAL Devices For Every Task
The members of the PAL device family are listed in Tables 4.2.1 and 4.2.2. They are designed to cover the spectrum of logic functions at lower cost and lower package count than SSI/MSI logic. This allows you to select the PAL device that best fits. your application. PAL devices come in three basic configurations: Gates, Register Outputs With Feedback, and Programmable I/O.
Gates
PALs are available in sizes from 12 x 10 (12 inputs, 10 outputs) to 20 x 2, with either active-high or active-low output configurations. One part has complimentary outputs. This wide variety of input/output formats allows the PAL to replace many different-sized blocks of combinational logic with single packages.
Register Options With Feedback
High-end members of the PAL device family feature latched data outputs with r~gister feedback. Each Sum-Of-Product term is stored in a D flip-flop on the rising edge of the system clock. (See Figure 4.2.1) The Q-output of the flip-flop can then be gated to the output pin by enabling the active low TRI-STATE© buffer.
In addition to being available to transmission, the Q-output is also fed back into the PAL array as an input term. This feedback allows the PAL device to "remember" its prior state. And, it can alter its function based upo~ that state. This allows one to configure the PAL device as a state machine that can be programmed to execute elementary functions such as count up, count down, skip, shift, and branch.
INPUTS, FEEDBACK AND 1/0
...
CLOCK
E
"r"""' J,__
r"
-....1""'11
1""'11
_}~
1""'11 -I
~ r---
D Q 1--1
H~ Q~
h.
~
~L
.....
Figure 4~2.1 PAL Device Output Register Circuit, Simplified Logic Diagram
42 Programmable Logic Design Guide
Programmable 1/0
Another feature of the high-end members of the PAL family is programmable input/output. This allows the product terms to directly control the outputs of the PAL device. (Figure 4.2.2) One product term is used to enable the TRI-STATE buffer, which in turn gates the summation term to the output pin. The output is also fed back into the PAL device array as an input. Thus, the PAL drives the I/O pin when the TRI-STATE gate is enabled. The I/0 pin is an input to the PAL device array when the TRI-STATE gate is disabled. This feature can be used to allocate available pins for 1/0 functions or to provide bidirectional output pins for operations such as shifting and rotating serial data.
INPUTS, FEEDBACK AND 1/0
....
- :>--tl I::.._...._.
:~~:: -.
-·"'
110
i...
h.
...~ . .....-
~ _......,...
Figure 4.2.2 PAL Device Bidirectional Circuit, Logic Diagram
PAL Device - Speed/Power Groups
PAL devices are available with various speed/power specifications. For easy reference, these are summarized in Tables 4.2.4 and 4.2.5.
20-Pln Small PAL Devices
20-Pln Medium PAL Devices
10H8, 12H6, 14H4, 16H2, 10L8, 12L6, 14L4,
16L2, 16C1
16L8, 16R8, 16R6, 16R4
TAA Max (ns)
Ice Max (mA)
TAA Max (ns)
Tsu Min (ns)
TCLK Max (ns)
Standard
35
90
35
35
25
A Series
25
90
25
25
15
B Series
-
-
15
15
12
A-2 Series
35
45
35
35
25
B-2 Series
-
-
*25
*25
*15
*Preliminary information.
Table 4.2.4 20-Pin PAL Device Speed/Power Groups
Ice Max (mA) 180 180 180 90 *90
The Programmable Logic Family 43
20L10
20X10, 20X8, 20X4
20C1, 20L2, 18L4, 16L6, 14L8,
12L10
20LBA,20RBA,20R6A,20R4A
TAA Max Ice Max Tsu Min TcLK Max Ice Max TAA Max Ice Max TAA Max Tsu Min TcLK Max Ice Max
(ns) (mA) (ns)
(ns)
(mA) (ns) (mA) (ns)
(ns)
(ns)
(mA)
[standard 50
165
50
30
180
40
100
-
-
-
-
- [A Series
-
-
-
-
-
-
25
25
15
210
Table 4.2.5 24-Pin Speed/Power Groups
PAL Device Logic Symbols
The logic symbols for each of the individual PAL devices gives a concise functional description of that device. Figure 4.2.3 shows a typical logic symbol, that of the 10H8 gate array.
PAL10H8
Fi~ure 4.2.3 Logic Symbol, PAL10H8
44 Programmable Logic .Design Guide
PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL 16C1
PAL10L8
PAL12L6
PAL14L4
PAL16L2
Figure 4.2.4 PAL Device Logic Symbols - Series 20
PAL16L8
The Programmable Logic Family 45
PAL16RB
PAL16R6
PAL16R4
Figure 4.2.4 PAL Device Logic Symbols - Series 20 (Contd.)
46 Programmable Logic Design Guide
PAL12L10
PAL14L8
PAL16L6
PAL18L4
PAL20L2
PAL20C1
PAL20L10
PAL20x 10
PAL20x8
PAL20x4
PAL20R4
PAL20R6
PAL20L8
PAL20R8
Figure 4.2.5 PAL Device Logic Symbols - Series 24
The Programmable Logic Family 47
4.3 THE PROM FAMILY
National's broad PROM family extends from a 32 x 8 bit (256 bit) PROM to a 4096 x 8 bit (32K) PROM. Only the low density byte-wide PROMs are considered here for programmable logic applications. The products in this category are shown in Table 4. 3.1.
Part No. 74$288 87X288B 74LS471 74LS472 74S472A 74S472B 74$474 74S474A 74S474B 87SR474 87SR476 87SR25
Density 256 Bit (32 x 8) 256 Bit (32 x 8) 2K (256 x 8) 4K (512 x 8) 4K (512 x 8) 4K (512 x 8) 4K (512 x 8) 4K (512x 8) 4K (512 x 8) 4K (12x 8) 4K (512 x 8) 4K (512 x 8)
No. of Inputs
5 5 8 9 9 9 9 9 9 9 9 9
No. of Outputs
8 8 8 8 8 8 8 8 8 8 8 8
No. of Product Terms/
Output 32 32 256 512 512 512 512 512 512 512 512 512
.Military versions are also available. Above data is commercial. ·24 Pin Narrow Dual-In-Line Package
No. of Pins
16 16 20 20 20 20 24 24 24 . 24* 24* ·24·
TAA Max (ns) 35 15 60 60 50 35 65 45 35 35 35 35
Ice Max (mA) 110 140 100 155 155 155 170 125 170 185 185 185
Table 4.3.1 PROM Configurations
48 Programmable Logic Design Guide
Size (Bits) Organization
DIP (Pins)
Part Number
TAA
TEA
ICC
Temperature
(Max.)lnnS (Max.)lnnS (Max.)lnmA Celsius
32 ic 8 Standard PROMS
256
32x8 QC 16
DM54S188
45
32x8 QC 16
DM74S188
35
32x8 TS 16
DM54S288
45
32x8 TS 16
DM74S288
35
30
110
-55to +125
20
110
Oto +70
30
110
-55to +125
20
110
Oto +70
32 x 8 Ultra High-Speed PROMs
256
32x8 TS 16
PL77X288
20
32x8 TS 16
PL87X288
15
15
140
-55to +125
12
140
Oto +70
256 x 8 Standard PROMs
2048
256x8 TS 20
DM54LS471
70
256x8 TS 20
DM74LS471
60
35
100
-55to +125
30
100
Oto +70
512 x 8 Standard PROMs
4096 512x8 QC 20
DM54S473
75
512x8 QC 20
DM74S473
60
512x8 TS 20
DM54S472
75
512x8 TS 20
DM74S472
60
512x8 QC 20
DM54S473A
60
512x8 QC 20
DM74S473A
45
512x8 TS 20
DM54S472A
60
512x8 TS 20
DM74S472A
45
512x8 TS 20
DM54S472B
50
512x8 TS 20
DM74S472B
35
512x8 QC 24
DM54S475
75
512x8 QC 24
DM74S475
65
512x8 TS 24
. DM54S474
75
512x8 TS 24
DM74S474
65
512x8 QC 24
DM54S475A
60
512x8 QC 24
DM74S475A
45
512x8 TS 24
DM54S474A
60
512x8 TS 24
DM74S474A
45
512x8 TS 24
DM54S474B
50
512x8 TS 24
DM74S474B
35
35
155
-55to +125
30
155
Oto +70
35
155
-55to +125
30
155
Oto +70
35
155
-55to +125
25
155
Oto+70
35
155
-55to +125
25
155
Oto +70
35
155
-55to +125
25
155
Oto+70
40
170
-55to +125
35
170
Oto +70
40
170
-55to +125
35
170
Oto +70
35
170
-55to +125
25
170
Oto +70
35
170
-55to +125
25
170
Oto+70
35
170
-55to +125
25
170
Oto +70
512 x 8 Registered PROMS
4076
512x8 REG 24* DM77SR474
40**
30
512x8 REG 24* DM87SR474
35**
25
512x8 REG 24* DM77SR476
40**
30
512x8 REG 24*
DM77SR25
40**
30
512x8 REG 24* DM87SR476
35**
25
512x8 REG 24*
DM87SR25
35**
25
185
-55to +125
185
Oto +70.
185
-55to +125
185
-55to +125
185
Oto +70
185
Oto +70
* 300 mil wide package. ** Set-up time.
Table 4.3.2 PROM Products for Logic
The Programmable Logic Family 49
01 02 2
16 Vee 1S E1
03 3
14 A4
a4 4
13 A3
32x8
as s
12 A2
a6 6
11 A1
a7 7
10 AO
GND 8
9 08
AO A1 2
20 Vee
19 A7
A2 3
18 A6
A3 4
17 AS
A4 S
16 E2
2S6x8
01 6
1S E1
02 7 03 8
14 06
13 a1
04 9
12 a6
GND 10
11 as
AO l Al 2 A2 3 A3 4 A4 5
QI 6
02 7
03 8 04 9 GND IO
S12x 8
A1
As As A4 A3 A2 A1 Ao Oo 01 02 GND
1
24
2 S12 x 8 23 3 REG. 22
4
21
S j:t 20
6
ffi'l:t' 19
7 ~ 18
8
:cE 17
9
16
10
1S
11
14
12
13
Vee
Ag NC
G
INIT(CLR)
Gs
CK
07 Os Os 04 03
Oo 01 02 GND
24
2
23
S12x8
3 REG. 22
4
21
le It) 20
~ ~
~~
19 18
5E :E
cc 17
9
16
10
1S
11
14
12
13
Vee
Ag PS
G
INIT (CLR)*
GS
CK
07 Os Os 04 03
A7 I A6 2 A5 3
A4 4 A3 5 A2 6 Al 7 AO B QI g 0210
03 11 GNO 12
S12x 8
Figure 4.3.1 PROM Logic Symbols
Note: All of the virgin devices come with their fuses intact. But for the sake of simplicity, the fuse-linked crosspoints in the array are shown unconnected.
4.4 LOGIC DIAGRAMS
The following pages show the logic diagrams of the PAL device and PROM family of programmable logic devices. The logic diagrams are ordered in the following sequence:
PAL Devices: Figures 4.4.1-4.4.13 (20-pin PAL devices) Figures 4.4.14-4.4.27 (24-pin PAL devices)
PRO Ms: Figures 4.4.28-4.4.32
50 Programmable Logic Design Guide
... ~
..-~
2 ... ~
Inputs (0-31)
11
~ ~
19
.·.I
"
3 ...
..>. ~ ..
.
"
. 4 ... ~ ~
14 Ii
I
5 ...
I
~
JI JJ
6 ...
~.>. ..-~ . " 7 ... ~ .. . . 11
1_
-- ' _Jo< 3
. / _Jo< .J
_Jo< L
1
18
---1:5 .J
17
--:R]
16
15
..>..<.- .J
14 ~
.J-_r..r-.e-e.<.:.:
lx _
.J
L \
13
8 ... ....>.......
....
12
""'
9 ....
~ ... ~
I I J J ·I I 1 It
A
11
~
UUHU JIHJIJI
'"'"'""
Figure 4.4.1 Logic Diagram PAL lOHB
The Programmable Logic Family 51
1 ..
DI ll 41
Inputs (0-31)
I!
llll
1111
lDll
1411
lll!JDJI
D I
2 ..
..,.
I !
3 ...
12..,.-
"II 4 ...
...,
14 II
5 .......,
ll ll
6 .....
L.2.,._
40 41
7 ... L..Z., . 41
8 .... ~
II 17
9 ..
-..K. _J
19
-----_1'<
18
---:K ]
17
---:J.( =i
16
---...K _J
15
---.t-< _J
14
-..K. _J
13
---Jo< I
12
.....
11
~
1121 Ii
II
1111
1117
2011
141$
lllllDJI
Figure 4.4.2 Logic Diagram PAL 12H6
52 Programmable Logic Design Guide
1 ...
2 ...
·~
Inputs (0-31)
0 12] 4 !ii 1 191011
3 a..
....
19
<.
-v
4 ...
~
II 11 11 11
5
b.
L?
" " n
11
"IJ
14 15
6
lb.
~
" " " "
7 ....
....
18
~
J_
-- :> :Jo< _I
~
-- ':Jo<
1_
17
.1
::Jo<
-:H ::J
--- '_I.
16
1_
-- :> .M. ~
.M. _]
Jo< -Ly
15
.1
_}oil
--_}oil
-=-'i
_}oil L
- ....
' -~
14 13
8
!lo..
.A
12
_5J
9
h.
~
.
11
~ -v
0 I 1 l 4 SI 1 I 11011 Ull
2011UU H2S1121 21llllll
Figure 4.4.3 Logic Diagram PAL14H4
1 ... ~ ..., 2 ....
~
The Programmable Logic Family 53
Inputs (0-31)
0II J
4 I i 1 . I 910 II
11131411
11111119
I
10111113
14111&11
I
lllllOJI
....
19
<_...._..
3 .....
....
18
~
4 ... ~
14
II
II
M'
<O
eI .
5 Cl)
.....
11 11 19 JO JI
E
-~
u
~
JI JJ 34
::J
JI
"C
JI
n0 .
JI JI 39
6 b;-
7 ~
8 ..~ ... ...,
.A
17
~ -
~~
' ..~ ~ ....
~
16
~
..... _J
_.rP.:. - ~
15
t: I
.....
14
~
_...
13
N
~
12
.....
:.Q
9 ....
0 I 1 J 4 111 191011 111J1411 11111111 10111113 14111111 1129JOJI
.....
.s.t
11-
Figure 4.4.4 Logic Diagram PAL 16H2
54 Programmable Logic Design Guide
1 ... ...~
2 ... >
INPUTS (0·31)
· 1 1J
4~ I 1
I I \Cl 11 If ll 1' 15
1· 111111
1t fl l1 tJ
1' l~ l· 21
18 lt JO Jt
19
.... _:!IC
3 ... ~
4 ..
...::lit_
5 .
...~
6 .... ...~
....
18
31:....
17 ~....
..1 _J
- ~~
_..,
.l
15
::J
- _J
.A
14
.,JI;....
7- - - r . ........ _
__,,... A
13
:"'
-8 ... .....2._
_:e;...A..
12
9 -
> ....
II II
ei I 1
I I '9 II
11 ll 1' I~
!ti 11 11 II
Z'O 11 11 U 111~ 1' l1 1f 11 :Ml ll
....
11
....:<; ....
Figure 4.4. 5 Logic Diagram PAL 16C 1
The Programmable Logic Family 55
Inputs (0-31) )
0111 .,
11
llll
1111
1011
IHS
11113011
1 ....
\ o 1
2 ...
- - L ? '..,.-
I I
3 ...
--~ .J .,....
19
---J-< ]
""""'-
18
11 11
4 ....
2' IS
5 ......_
ll ll
6 .... ~ ..,.-
.·o
7 ....
....
8 .... ..~ .
-u
51
9 ....
------ .,,_
_t< __)
'""
17
---Jo< _J K:'
16
-----R" 1 "....'..-.
15
14
----~
"'-
-~ .J
...,.........
13
---Jo< :J ...,....,_,.
12
11
_st
~
II
1111
1111
1011
l'IS
lill l0l1
Figure 4.4.6 Logic Diagram PAL 10L8
56 Programmable Logic Design Guide
.~ ,._
2
v~v-
I I 10 11
3 ...
~
"11
- 4 .~ ..
"IS
5 ... ~
II 13
6 ...
~
..40
7 .~ ....,
..
"so
SI
Inputs (0-31)
I
l
I
l
I
8 ~ ... V"
.A
19
··~
-~
L
-...K. J
- '~ f
"""'
18
--:R-i .,.,_
17
-...-.
...K. _J
"""''
16
---- .,.,_
:J-<: :J
~
15
---...K. _J "~ "'
14
:R:h,.
13
Jo<.
.,.,_
- '-1-<_ L .,,/"
....
12
_,<
-...,~
9 ....
----t.J.,t...,_.
I 1 Z J Ci I 1 I I
~..A,...
11
HHJIZT HZIJIU
Figure 4.4.7 Logic Diagram PAL12L6
...
--Q
2 ...
- ---1.2
The Programmable Logic Fanlily 57
11 JJ t SI 1
Inputs (0-31)
3 ...
-
_..<......
19
4 ....
1-2:: .
"II
II
-5 -Q... -
IC
2'
21
-:ua
II
"C
a2.
,.J2
II
Ii
. 6 .... ~
...
u u
- 7
-
-
-
u.... _
....
18
_sJ-
l_
- i t-<
1-<
...K. L
-\
'~
17
1
::Jo< _)
--- '-~ ..... ../°
16
1
-- -L..r ~
~ _I '
- ':K
15
J_
:r<: _)
--:r<:
"""" :-J..o..<.
::J
L
/~
' ....
14 13
~ -
8 ...
-
.A
12
5J
9 ....
~
....
11
~
~
I 1 I J t l I 1 I 11111 lllJ
21Z12lU lt25llZ1 2121JDJI
Figure 4.4.8 Logic Diagram PAL14L4
58 Programmable Logic Design Guide
1 ...
12
- 2 ... .2-
Inputs (0-31)
D 1 2 I 4 I I 7 I 11011 12111411 16111119 !0!1221! 24212627 2129!DJ1
I
....
19
~....
3 ....
....
18
<.I-
""'~
4 ..
R-
24
21
21
M'
27 ll
U)
ll
eI. 5 ...
10 JI
Cll
e{!!.
-CJ
~
Jl ll 11 II
:I
ll
e'C
ll ll
D.
ll
6 .
~ -
7 ..
....
17
~
..... ,
.".",",, 1-11
1-11
.11""".--"""11."""11. .....................
, '
"'-
16 15
1-11
....1-11
1-11
~
....
14
.SI
....
13
~
8 .
-
....
12
~
9 ..
I 1 l l I I I 1 I 11111 11111111 11111111 20211221 21212127 21211011
....
11
-~
~
Figure 4.4.9 Logic Diagram PAL 16L2
The Programmable Logic Family 59
Inputs (0-31)
2
.....
... - - - l z ..,-
3 .....
- - - - - -....t i
4 ...
.,i.._
5 ..... ..~ .
6 ....
.,.~ ..,-
- 7 ~ .h,...._
8 ......
-- - - - l...z
9 ...... - - I.,..i...,-
1121
I I 2
· l
I I 1
C 117
I 11111 llllltll 11111111 ID211111 ICISllll lllllDll
I I
II 11 ll II IC
u
II II II II 21 21 22 2J
2C 15 21 11 21 21 10 JI
12 JI IC IS JI 17 II II
u··
..u
Cl
.C.l .
CJ
..Cl
H 51
u
SJ IC H
51 SI 51 51 ID II 12 ll
0 I 2 l CI 17 I 11011 llllltll 11111111 10111111 14251111 11111011
>-tl .......................
19
...tool
1--1
~ _...,
.................................
w.
~ 18
,,.,..,.
......................................
·~:J 17
.....
"'"
i............:........:......
~ 16
,,.,.,
...~.........
..~......
~
15
_.,
- .....
..~ ...... ;J
14
~~
_...,
....rr........--..... .~ ~...
~.:~J
13
.,..,.
_;J_ ....................
12
.~~...
~ ...,...,
11
Figure 4.4.10 Logic Diagram PAL 16L8
60 Programmable Logic Design Guide
Inputs (0-31)
CHCHIH2HJf--14Hl~6~ll--8~9~1~C·~·-;~,,rJlrOl~l-lr61~11rol~l-2~01~il~ll+J--+-,.+,,+2,+1.--+-1.+1,+JQ~Jlf--l,...I>--t'
;:I-:Hl;-H~l;l-:-l;-;+l:-;>:-l:-f:-;-<;i-:-;l+:-:~1:~:4:--:-+=+:--:t~;-;l+;--=l;-;-~;-.t~:--:+-+-=l;--.~-:l:---+.-:-+:-+-1.+-:-+:1-+-=-.1:--:--++.+-:+:++-+-.l:+-:--+~++=-+~l~--~+t~-=-~~++~-~f~+=--:--;lL1~~.fIL."..>>.Jr-_--_-t.4-~---....,/
6~~1--~~-+-+++-++++--+-+++-++++-+~+--t-+-t--t~1~>-1 ..... )~~l--~~-+-+++-++++-+-+++-++++-+~+--t-+-t--t~1 ~,
~ .... V'
M'
ID
eI .
II)
e ~
-u
::I
e"C
Cl.
7
h.--~~+-+-+-+--+-+++-++++--+-++-+-++++--. ~
48~~1--++++-+-+++-++++--+-+++-++-t-+-+~+-~-+Hf--l~I>---4,
...-. :::~~~~=tttt=tttt=tttt=tttt=tt~~=~~~~=~~~~=~i::l~=-' .... ;;:~ttt=tttt=tttt=tttt=tttt=tt~~=~~~~=~~~~=~~~~
;:-+-+-+-l--H-++-l-++-l-++++-l-++-l-++++-++++-+++-+--l~rJ.-+--
11-+-+-+-+--H-++-l-+++-++++-++++-++++-++++-+++-+--lt:~-1
8 ~ h---~~+-+-+-+---+-+++-++++-+-t-++--t-+-t-+-++-t-+-~
0 I 2 3 4 ~ & 1 8 9 1011 \/1)141!> 16171819 2021n2; /q!J{b/1 liji9JOJI
Figure 4.4.11 Logic Diagram PAL 16R8
The Programmable Logic Family. 61
Inputs (0-31)
1
CK
~.. ...-...... ~ SR
.t...-...:... ~ 3 ...
111 J ·SI 1 111011 11 nu n 1111 1111 1111 u u u n 1111 n n H ,,
I I I I
1-o 1-o
....
I
'
.1.-.o.
I
1
I
II II
........
II
" " "
~
J
...
19 LIAO
...>..,
II 11 II II II II II II
4
D1 ~
1'.
....
I............:........
'
'
J
~
1'.
~
~ ~
I""I
Mco '
e I
II II II II II
U)
5 ...
E
;!
D2
.. ~ ~
II
tS
:I
e"O
a.
03
..6 .. ~..,
II
"II
JI
" " "
..
...""u...
7 ... "
~
....
.."""I..I
..8 .... ~ ..
II
"II
ID
..II
II
SL 9 .p..
' ....,...._............
"' loOI
J
· ...
7.
"V~
[~~·Q rv
a1-6
"' I................:......... 1
'....
...
~
' ....
l-o
'}..
l-o
l...-....o...
""' ' ...
~
-v
~ ~ ~ ~
.c.. ~ l....:...>- ".""/'
b-1 ...
~ ~
..............................
""'
~
~1
<·....t----'
12 RILO
~ E
Figure 4.4.12 Logic Diagram PAL I6R6
62 Programmable Logic Design Guide
Inputs (0-31)
D 12 J
.'I
I I
I I 1
~ .. ...,
· s6 1
I 91011 1Z1lU 15 1811111' 2021222) 24252117 112'l0l1
..........
"""r"""""""""-"'''''
~ ~
19
I
'10
11
11
""IS 3 .....
~ ........~
~ .....
l.".:"."...
18
...~..,
11
"11 "10
II II II
4 ...
, .....
"~
~
..."""..."""....'''... ~
../
...
~
....">..,
~l
-...,~
74
lS
Mco"
II 11
eI .
II II 30
en
]1
E 5 ..
-~
u
~
""" V'
JI
::I
ll
e'?J
"JS
a..
"J7
"l!
6 ...
~
... V'
."4"1
".,.,
7 ... "
..~ ..., .... 'S'I ".". IS
8 ..
.i:.:. ~
""'
.""""."""".".''' ~ ...
~ ~
~
...... """"'"""
t:>- .... _-.1~
...............
./
""" 1
~ ~
.A
JC:
'.....
""""
~ '--
."""."""."".' t: J ...
~ ~
-.I.C.,.....,.
E.... -,:)_J
13
tn : __) c~ .A
~
..""SI
SI
:>-J .....
""""'""""
!....?. -7,
"II
II
....".".". "3 _) To.<
9 ..
.A
~
0 I 1 J · s I 1 '11011 121JU1§ 11171111 202\UU uuun llUJOJT
1C..t--
"""""
12
~
Figure 4.4.13 Logic Diagram PAL 16R4
The Programmable Logic Family 63
Inputs (0-39)
1
2
~
0123 45
I 9
1213
1&17
2021
2·25
2129
3233
31373139
23
0 1
2 ~
22
I 9
3
- --12
21
16 17
4
- -t~
2· 2S
5 -~
32 33
6
::t.
~
40 '1
7
~.
20
~
18
17
",g
- 8 ::t.
16
S6 S7
9
-~-
64 6S
10
--1::l!
~-
72 73
1
-f-2. ~
0 1 2 3 '5
I g
1213
1617
2021
2425
2129
3233
31373139
15
14 13 c-
""
Figure 4.4.14 Logic Diagram PAL12Ll0
64 Programmable Logic Design Guide
1
--t2
0 1 Z3 4 5 I 7
I t
--
Inputs (0-39)
1213
1117
Z11Z1
ZH5
Zlzt
32333'35 31373131
:2.c:c._
· I
10 11
3 ..~
11 17
4
-l.2_ "V
24 25
5
--f~
3Z 33
6
~
40
u
.7....·.~
..
'9
8
~
51 57
9.
-t_> v
"15 "17
10.
--l::::lt
23
...< I - - -
22
21
,~ _,
19
18
._,
17
,~ _,
15 14
..<.....I---
.11
~
z 0 1 3 4 5 6 7
11
1213
1617
fOZ1
ZH5
ZIZ9
32333435 36373139
Figure 4.4.15 Logic Diagram PAL14L8
13
..< .. ...I---
~e Programmable Logic Family 65
1
-I.>...
0 1 2 3 4 5 I 7 I 91011 1213
Inputs (0-39)
1117
2021
2'25
21213031 32333435 31373131
~
23
~...
3
--1~
"
15 17 11 19
4 .. ~ "
24 25 26 27
5 .. ~
32 33
6
~ v
40 41
7 -Ci:
.
49 50 51
8 ->
56 57 51 59
9 -~v
22 ~
21 ._,
20 ._,
19
L..I
18
L..I
17
LJ
16
._,
15 ~
..0 ..
-Clt
14 ~
. 1
--[~
D 1 2 3 4 5 6 7 8 91011 1213
1617
2021
2425
21293031 32333435 36373139
Figure 4.4.16 Logic Diagram PAL 16L6
13
~
66 Programmable Logic Design ~uide
INPUTS (0-39)
G 1 Z 3 4 5 I 7 I I 10 11 12 1314 15 1117
ZGZ1
1 ·
-l> v
~
3 ->
-< 23
-4
-·t>
5 -
..·>.
24 25 21 27 21
6 21
..__,~
32 33 34 35
40 41 42
-7 43
-D
41 41 50 51 52
8 53 ->
v
9
~
10
..~
22
. <t."J---;.
"'
21
.... ?~
~
~
'-'
.(}.....I
18
~ ~
~ ~
t)-., 16
4!""1--
15 ct-""
14 ~ ....
- 11 :lt..
0 1 Z 3 4 5 6 7 891011 12131415 1617
2021
Figure 4.4.17 Logic Diagram PAL 18L4
13
~
1 ..
- 2-
~
. 3
-t.2.
. 4 ~
5
- >... 3l 33 J4 3$ 31 31 31
.6 31 ~ 40 41 41 43 44 4S 41
7 47
-~
. 8
-.:>
. 9 ·~
0 ....2...
. 1
-..lt.
The Programmable Logic Family 67
Inputs (0-39)
23
--z
22
--z "'
21
~
"'
20
CC.t--
~
~ 1P-Jr'
rp....)-l -.
I~ -)-,
....,_,
~~ ~
)...)-'
tµ-r-.
d= 17
i:
16
i:
15
~
Figure 4.4.18 Logic Diagram PAL20L2
14
JCI--
~
13 .1.1...:.t--
68 Programmable Logic Design Guide
Inputs (0-39)
1
--1r 2
D 1 Z 3 · 5 6 7 111011 1Z131·15 16171119 ZD21Z2Z3 2·252127 21213031 32333'35 36173611
2 ~
.23
,.;:....
3
--1>
22
,.;:
4
-t::t.
5
-t.2
32 33 3· 35 36 37 38
6 39 -u.
·D ·1
..·2
'3
cs
'6
7 '7
--t-2..
8
--12
21
,.;:
20
<
~
1R~ ~ ~ ~ -DJ
JJ-?-"1'
19
RJ ~ .~ ....r~
18
H~ ~""'-
17
<
~
.,,.~
16
9
--1>
10
- - rt 2
15
" ~
14
~~
11
-~
13
1C.
D 1 2 3 · 5 6 7 8 9 1D 11 12 1J 1' 15 16 17 11 19 2D 21 22 23 2'25 26 27 21 29 3D 31 32 33 3435 3117 36 39
Figure 4.4.19 Logic Diagram PAL20C 1
The Programmable Logic Family 69
Inputs (0-39)
0 123
0 1 2 3
2 ~
4 567
I 91011 12131.'15 16171119 20212223 24 252627 21293031 32333435 3637 3139
@
_,j_ 23
.....
.JC~ ~
8 9 10 11
3
I~
~ .... ~
16 17 18 19
4 ... -~..,.
24 25 26 27
5 ..
-t~
@ -d 21
....
~i----'
~,
@~20
....
~
~
-:u:s
32 33 34 35
"C 6
a:0
~
40 41 42 43
7
I~
@_~-r
_S..t-----o
~
_, S:P~ K:t.: ~ 18
48 49 50 51
8 .. ~
~~ J-\_i.
J 17
56 57 58 59
9 2
v
64 65 65 67
10 - - f Y . ..,.
~
~-J 15
:o=v~
72 73 74 75
11
~
{Jj:-{--f:-t/'
J
v
14
13
_.;(;
~,
0 1 2 3 4 5 6 7 891011 12131415 16171819 20212223 24252627 28293031 32333435 36373839
Figure 4.4.20 Logic Diagram PAL20Ll0
70 Programmable Logic Design Guide
INPUTS (0-39)
- I....'..
0 1 Z 3 4 5 6 7 I 9 1011 12131415 11171119 ZOZ1ZZ23 Z4 ZSHZ7 21293031 32333435 31373139
0 1
z
3
I~ Di>~8 23
~
...
<
I 9
10 11
3
-t.r>-
~] ~ - D
._,
Q. 22 ......
-<
16 17
18 19
4
{§99~ I.I. 21
t-<'"'1
......
- tr2 .
~
Z4 ZS
Z6
.e...n. eI .
27
~u r
en
:aw:E:
32 33
34
I-
3S
Iu- 6
:c:::>
- t,.,,..2
0a:
40
Q.
41
4Z 43
7. "1.A.
48 49
so
S1
s-µ_
S6 57
58 S9
9' ;t_
64 6S 66 67
..Qli.
~.2
7Z 73 74 7S
1-t~
~~~ b--L
1.1. 20 .......
£
~
IDI>~ Cl 19 ...... _J
<C.
~
}§9~~ ......,_
Gt 18 ......
<
~
~- ~~ Q 17 ......
-._,-
< ~
ID~~ - -._,--
1...1... 16
<
~~~ IJ. 15 .....
........
~
ID~~· 4
£
~ 3
0 1 Z 3 4 S 6 7 8 91011 1Z13141S 16171819 ZOZ1ZZ23 Z4 ZSZ6Z7 28293031 3233 34 3S 36373839
Figure 4.4.21 Logic Diagram PAL20X10
The Programmable Logic Family 71
INPUTS (0-39)
_to...
y
D 1 2 3 4 5 I 1 I 11011 U13141S 11171111 2D2122Z3 24252127 21ZUUI 32333435 31373131
0 1 2 3
~
~ """LJ'""' ---z...
2 3
a
9
10 II
~~M~ -
2 2
"""LJ'"-
~. ~
"'
I& 11
18 19
~·
~ ~D- h.... 21 < ~
r-
24 25
26
27
- a,..;.- -~n
eI .
e:awen:
t-
32 33
34 35
t; 6 :::i.
::::>
Q
aa0 : .
40 41
42
43
-7;rt·.-
~~~ """LJ'"-
G...l. 20
-"-....
~D-~ C...l. 19
"""LJ'" ~
~~~ t;.L... 18 ~ ....
48 49
50 51
8.
r-
~ ~D- h.... 17 -~....
56 57
58 59
..9
-t.2
~~~ h.... 16
..._,
-"-
64 65
66
®D- ~-
~ l.l... 15
67
,J-1..
Q
..0-i:::i.
12 73 74 75
1-i>-.
0 123
4 5I 1
1
I 11011 12131415 16171119
~
<it'
m ,"" -i
I II
I
=1....
20212223 24252627 21293031 32333435 36373139
14
~
Figure 4.4.22 Logic Diagram PAL20X8
72 Programmable Logic Design Guide
INPUTS (0-39)
........v
0 1 2 3 4 5 8 7 I 91011 12131415 11171119 202122%3 24252127 21293031 3233 34 35 3137 31 39
0 1 2 3
~
B:> }-( J
-;J
y
23
-._., \
J
~-
8 9 10 11
L.~.
J ~J
~/ y
22
... ~,.....__.
16 17 18 19
4 ~ ~
24 25
26
,(..j.) 27
aI 5 ~
t.n
:.aw.E.:.
32 33
34 35
t; 6
c:::> ~ .-~
a0a.:
40 41
42
43
7 ...
~
48 49
50 51
~-u
J ~J
~/ y
21
...~..--
~9~8 20
-c.
~~~~ ~
~9~ t;t .....
18
...
~
~
~~~ .....
56 57 58 59
l~ li' _.J. J
1 6
9 ... ~
-"1----'
64 65 66 67
10
---1.:&.
J :~ tR~ J ... ,.;;...
72 73 74 75
11 ... .;Jt
0 123
4 567
~_,.!
J ~ ..... ..c:: ~
8 91011 12131415 16171819 20212223 24252627 21293031 32333435 36373139
15
1 4
~ 3
Figure 4.4.2 3 Logic Diagram PAL20X4
The Programmable Logic Family 73
Inputs (0-39) 20L8
0 123
~ ~ I I 10 11 12 13 14 15
3 ...
,.~ ._
'15
17 11 11 20 21 22
4 .... 23 ,..2_..
24 25 26 27 21 29 30 31
5 ....
,.~ ._
32 33 34 35 36 37 31
.. - '6 ..39 ~
40 41 42 43 44 45 46
-7 .. 47
..~ . 41 41 50 51 52 53 54 55
.. - 8 .... ~
51 57 51 51 ID 11 12 13
9·... ~e14s 66 17 II 61 70
o ... 71 ~
11 ~-
...~
o 1 2 3
4517 4 5 11
11mtt 111ott
uuw~ 12131415
u11uu ~nnn
16111119 2on2223
ttnHn nn~~
24252627 2129~31
n~~~ 31373131
....
-CL
,..., -"'
H
~ q::;~ _,/
f-).....
b-i ....
~
r
--~
P-~ t-j.... ~ ./
t-j....
b-i
~ ~ .....
r
.Pt~.-..j...-..-..... -·./
t-j....
b-i ....
~ ,
rp...,
~ l={-i ../
~ b-i
- ,...,
=G.....
1~ ~ ~ -i--~ ../
t~ j....,
....
,...,
1C "'
""" J~ ~ p-i..-..i
t-j....
b-i
.A
_jC
·pr - -"'
p-t-j.... ./
t-j....
b-i ...
,...,
'JC: ""'
~ P;j~
~ ../
b~-i --c....
-~
~ ,
3233~35 36373139
Figure 4.4.24 Logic Diagram PAL20L8
J
23
r--
J.
22
......
J.
21
~
20
......
1
19
L -.......
18
_,.L-~
17
1~- 16
1
15
......
14 13
TUU5598-10
74 Programmable Logic Design Guide
- v...... 1123
~ I I ID 11 12 13 14 15
- 3 ...
.. ~ 16 17 18 19 20 71 22 23
4 ...,.~ .._
24 25 26 27 21 29 30 31
,-..5 .... ~
32 33 34 35 36 37 31
. ,-6 ..39 40 41 42 43 44 45 41 47
7 ..
,--... 41 41 50 51 52 53 54 55
- 9 ... ...~ 51 17 51 51 ID 11 12 13
9 ...
...~ ...
.65
118 17
89 70 71
10 ..~ .
11:. -
...~ -11 Z3
4567 4517
llWH 11wn
uuw~ uuw~
Inputs (0-39)
ronun ~U16~
H~HU HH~~ ~"~" 36373139
....
~
-"'"
R-'
"~ ~ ./
1b-'-r-i
....
~
r....'..),..-...'
P~- "./
8::
~
~
-~
p -r l -
.Pt..-...,r.-.-... ./
b-i .... ~
8~µ-:-- "./ "'
8::
~
......
p-0- _-_"L'".-
i~ ~ b)-- ~ ' ...... ~
r')-' -"'"
1.rt~ .-.-.{.-..>,".i.."--.. ~
b-i
......
~
r~ ')-'
"'
' H~
1b--i.-i
......
~
rp"H-
"'"
2 J-')....
~
~ ......
....
~
-~
16U16W ronun Hnnu nn~~ ~"M» 31V31S
~
-"'"
Figure 4.4.2 5 Logic Diagram PAL20R8
23
~
~~1 ~ ~ ~ ~ ~ ~8
n ~
~~6 ~~5
1 4
~ 3
TUU5598-13
The Programmable Logic Family 75
Inputs (0·39)
1
· 1 z 3 4517 11~11 uuuu """~~nun Nnnn nn»n nnMn :IUUUI
~ I
·
I
ID
11
,.IZ
13
15
- 3 ... ..~ .
.A
23
,......
~ ,
::>l--ir pp--
t-r"r--"
:J er .~ .._)-i
22
.A
~ ,
16 11 II 11 lO n IZ
4 ...23
rp}-p-J-,_ ".""/"
8=.....
~
-t> rv
24 ZS 21 21 21 21 JD 31
5 ....
.A
~ _ ,
rp-
1t~~ J-.f.r-.-., .-/
._
.A
n ~
·
,,~ ,_
_jC ,
32
c;;
33 34
eco.
35 36 37
en
E
{!!.
u
::::s
JI 31
6 ..
~
""""'
'4°1
42
e"C
43 44
a.
45
46
47
...7 .. ~
41
5G 51 52 53 54 55
8 ,..;. t:
{' ):-r-:
1;:--rr- ./ t~ -:>- ...
~_ ,
rpr--
v1-r-
".".""/ Id-= ...
..'J_C.....,
~ pt~ -)-; "."."/"
t~ -)-;
..ii
~ ,
.~~ ~ ~ ~ ~
51
p - 57
51 51 go
P-L./ ~ 11
n
. -... ~ 9 ..u ~ 64 u ... B:;N 11
r")--l
t-)-; """"
1~ ...)..-..,
,......
JC:....
15
H 70
8= ~ n
10 ..~
11: -
- ~
1~ -i-
.....,
.A
~ -.....
<:
14
.....
~ · 1 z s 4117 ··~11 UUHU 11111111 10nnn ttn2121 2121JDn UUMU JIVJIH
Figure 4.4.26 Logic Diagram PAL20R6
TUU5598-12
76 Programmable Logic Design Guide
20R4
0123
~ · I 9 10 11 12 13 14 15
3 .....>...
16 17 18 19 20 21 22 23
4 ....
·~ 24
25 26 27 28
'29 30 31
5 .i.t...>.....
4567
89ron
uuu~
~11m~
~~nn
~~~v
~M~~
n"34"
36373839
.....
23
,.....
.....· ~.....
~ ~
µI--)--
bl-r--
22
,.....,
....
§: 1=r ~ ~ ~
.._)-1
....
21
..-~ .."""
~ ~ ~ ~ " - '""'"-. . /
~
b-i
.....
~ ~
3~ ::.....
32 33 34 35 36 37 38
6 ... 39
,.~ .._
40 41 42 43 44 45 46 47
7 ...
~ ~ ~ p- ~../
1t-rrt,...i..,::
-....
~ . T....
~ p- ~.../
1-)-
b-i ....
~R>~
~
~ R>~
...:..:..t.
48 49 50 51 52 .53 54 55
8 ......~ .....
i'H :r --"
t~ :bl--'
1t.."..-.i.i----1'
....
- ,..., 3::.L...
~ ~
56 57 58 59 60 ·61 62 63
.9 .... ~
64 65 61 67 61 69 70
n
10 ...~
t-1--
~~ .......
....
-- r-
.jC.....
16
~ }~ ;.....
P~ -
t1-rr-
15
11~y
.. ~
0123
4567. 19ron
uuu~
n11n~ ~~nn ~~Hv HH38~
I 32333435 36373839
....
iC ...
14
~
Figure 4.4.27 Logic Diagram PAL20R4
TUU5598·11
The Programmable ·Logic Family 77
A4
A3
A2
A1
AO
~~~~~~v~~
'A4A3A2A1 Aii
A4A3 A2 A1 AO
AA A3 A2 A1 Aii
AAAlAZA1 AO
A4A3 A2 A1 AO AAAl A2i\f AO -MAlA2A1 Aii
A4A3A2A1 AO
AAA3A2i\1All
MA3 AZAl AO
MA3 A2 A1 Aii
MA3 A2 A1 AO
MA3A2A1A!i
MA3A2Al AO
MA3 A2 A1 AD
25 ANO GATES
MA3A2A1 AO
A4 A3 A2A1 Aii A4Al AZ Al AO A4Al AZ A1 Aii
A4Al AZ A1 AO
A4 AJ A2 Ai Aii A4AlA2 Ai AO A4 Al A2 A1 Ali
A4AJ A2A1 AO
A4 A3 A2 Ai AD
A4 A3 A2Al AD
A4 A3 A2 A1 Ali
A4A3AZA1 AO
A4A3A2i\1 Aii
A4A3A2 A1 AO
A4 A3 A2 A1 Aii
A4A3A2A1 AO
FIXED "AND" ARRAY GENERATING ALL 25
PRODUCT TERMS
*OR array Is shown with all fuses blown
PROGRAMMf\BLE "OR" ARRAY" _I'\
1=(
r<.
P<.
L..I
Ir<\.
~
L,..I
J\
}::< ~
F<. P<.
L..I
'OOC:r
ii _.1...'.
2 ~~rL:~~k';~7
07 06 05 04 03 02 01 00
TL/L/6747·3
Figure 4.4.28 32 X 8 PROM Logic Diagram
78 Programmable Logic Design Guide
11 la Is 14 13 12 '1 lo
,fl ~~t ,~; ~~ ~~~ ,~l )J; ~~
~
K
L..,;J
.'K"'
II IIIIII II IIIIII
I I I I I I I I
28
IIIIIIII II IIiIII
I
AND
IIIIIIII II IIIIII
I
GATES
II IIII II II II IIII
I
II IIII II II II IIII
I
FIXED AND ARRAY GENERATING ALL 28
PRODUCT TERMS
Figure 4.4.29 256 x 8 PROM Logic Diagram
The Programmable Logic Family 79
la 11 I& Is 14 13 12 11 lo
29 AND GATES
II II II II ·I I I I I I I I
II II IIII II II II II II IIIIII
II IIII II IIII II IIII II IIII II II II
FIXED AND ARRAY GENERATING ALL 29
PRODUCT TERMS
Figure 4.4.30 512 x 8 PROM Logic Diagram
80 Programmable Logic Design Guide
SR476/SR25
le 11 Is Is 14 13 12 '1 lo
,~; ,~ ,~ _,~; N~ ~~ ~~ fl> ,Fl .
II IIIII I II IIIII
I
I
29 11 I I I I I I I I I I I I I I I
I
I
AND I I I I I I I I I I I I I I I I I
I
I
GATES I I ·1 I I I I I 11 I I I I I I I
I
I
II II III II II II IIII
I
I
FIXED AND ARRAY GENERATING ALL 29
PRODUCT TERMS ·
INITIALIZE WORD
"D" FLIP-FLOP
Figure 4.4.31 512 x 8 Registered PROM Logic Diagram
The Programmable Logic Family 81
SR474
la 11 Is Is 14 13 12 11 lo
· ~~>n~ > ~~>n~ ) ~ ) )/'fl)~~1 ~
29 AND GATES
II II IIII II II IIIIII II II IIIIII II IIIIII II II IIIIII II IIIIII II II IIII II II IIIIII IIIIIIIIII IIIIIIII
I I I I I I I I
FIXED AND ARRAY GENERATING ALL 29
PRODUCT TERMS
CLK
"D" FLIP-FLOP
INITIALIZE WORD
8-BIT EDGE-TRIGGERED REGISTER
Figure 4.4.32 512 x 8 Registered PROM Logic Diagram
5
How to Design with Programmable Logic
There .are two design objectives to keep in mind when using programmable logic devices. The first objective is to use the programmable logic device to replace discrete chips in the existing product. Each device will be able to replace 3 to 8 TTL chips. The second objective is to design the programmable logic device into the new/next generation product.
Each design is different. But the procedures are similiar. Figure 5.0 shows a typical design sequence.
DEFINE
SELECT
THE 1--~ THE . - -
PROBLEM
DEVICE
WRITE THE
LOGIC EQUATION
PROGRAM THE
DEVICE
TEST THE DEVICE
Figure 5. 1.1 Design Sequence of the Programmable Logic Device
The design sequence can also be viewed as a set of five questions: (1) How do I define the problem? (2) How do I select the logic device? (3) How do I write the logic equations? (4) How do I program the device? (5) How do I test the device?
5.1 PROBLEM DEFINITION
First, we need to know the function of the logic circuit. Is it used for generating combinational control signals, decoding addresses/operation codes, or multiplexing/demultiplexing signals? Is it used for counting or shifting bits, generating different control sequences, or implementing a state machine for any usage?
83
84 Programmable Logic Design Guide
Then we can decide on the type of logic circuit. Is it combinational, sequential or mixed? Table 5.1.1 shows the typical combinational and sequential circuits and the PAL devices that can be adapted.
Typical Circuits
COMBINATIONAL
Decoder/encoder, multiplexer, adder, memory mapped 1/0, strictly signal combination (no latch).
SEQUENTIAL
Counter, shift registers, accumulator, Control sequence. generator
PAL Devices Used For
10H8, 12H6, 14H4, 16H2, 10L8, 12L6, 14L4, 16L2, 16C1, 12L10, 14L8, 16L6, 18L4, 20L2, 16LS
16L8, 16R8, 16R6, 16R4, 20L10, 20X10, 20X8, 20X4, 20L8, 20R8, 20R6, 20R4
Table 5.1.1 Typical PAL Circuits
5.2 DEVICE SELECTION
The next questio~ is, which PAL device should we choose to optimize space -and cost? To answer this, we first need to calculate the number of inputs and outputs of the logic circuits.being designed and decide on the outp.uts' polarity: active-low or active-high. For example, if there are 10 input and 7 output signals and the majority of outputs are active-low, then the best choice is the 10L8. If the number of outputs are six; then we can use either the 10L8 or 12L6. Since each PAL device has limited product terms, we need to know how many product terms each output uses. The number of product terms each output will use ·can be viewed· from logic equations. For instance, the logic
equation of 01 = Pl + P2 + P3 + P4 + PS will use five product terms for the output 01.
Fortunately, National's software, PIAN, will help the user to select the right PAL device. See chapter 6 for a discussion of PLAN.
Table 5.2.1 shows National's ~O pin PAL device configurations and Table 5.2.2 shows the 24 pin PAL devices.
How to Design With Programmable Logic 85
PAL 10HB
Complexity (1)
Max Propagation Delay (ns) 1/0 (and CLK to Output)
Serles Serles
Standard
A
B
Ice Max
(mA)
No. of Data Inputs
No. of Outputs and Configurations
20S
35
25
90
10 8x=&:D-
10L8
20S
12H6
20S
35
25
35
25
90
10 0x::g:o..-
90
12 4x=&:D-2x~
12L6
20S
14H4
20S
14L4
20S
16C1
20S
35
25
35
25
35
25
35
25
16H2
20S
16L2
20S
35
25
35
25
90
12 4x::g:o..-2x~
90
14 4x~
90
14 4x~
1x:r 90
16
2x. 90
16
2x. 90
16
16L8
20M
35
25
6x!Er2x~ 15 180
16-10
16R4
20M
16R6
20M
··ltN-··!Er 35/25
25/15 15/12 180
12-8
6xltN-2x!JEr 35/25
25/15 15/12 180
10-8
16RB
20M
35/25
25/15 15/12 180
a Bx~
Table 5.2.1 20 Pin PAL Device Configuration
86 Programmable Logic Design Guide
Max Propagation Delay (ns)
110 (and CLK to Output)
Ice No. of
Complexity
Serles Serles Max Data
PAL
(1)
Standard
A
B
(mA) Inputs
No. of Outputs and Configurations
12L10
24S
40
100
12
10x=8D---
14L8
24S
40
100
14 6x=8D---2x·~
16L6
24S
40
18L4
24S
40
20C1
24$
40
20L2
24S
40
100
16 2x=8D---4x~
100
18 2x~2x~
1xlF 100
20
2x. 100
20
20L10
24M
50
165 20-12 8x~2x~
20X4
24M
50/30
4x~6x~ 180
16-10
20X8
24M
50/30
8x~2x~ 180
12-10
20X10
24M
50/30
10x~ 180
10
(1) Complexity: 20 = 20-Pin PAL 24 = 24 Pin PAL
S =Small PAL M = Medium PAL
Table 5.2.2 24 Pin PAL Device Configuration
How to Design With Programmable Logic 87
5.3 WRITING LOGIC EQUATIONS
Writing logic equations from an existing combinational circuit is straightforward. Examples are given in Chapter 3. Also, the generation of logic equations for a new design combinational circuit is quite simple. The procedures are as follows: 1. Define the inputs and outputs. 2. Generate the Truth Table.
3. Use the techniques mentioned in Section 3.2 to get the SOP expression for each output.
4. Use the minimization techniques mentioned in Section 3.3, i.e., Boolean Algebra, KMap or the Quine-McCluskey method to minimize every SOP expression.
5. These four steps result in the logic equations. Figure 5.3.1 shows these steps:
DEFINE INPUTS AND OUTPUTS
KARNAUGH MAPS OR BOOLEAN ALGEBRA (PROGRAMMING THE PAL DEVICE)
FUNCTIONAL DESCRIPTION ._ -. - -
TRUTH TABLE
TRANSFER FUNCTION
(LOGIC EQUATIONS)
CIRCUITS (PAL)
DEVICE
FUNCTION TABLE
Figure 5.3.1 Combinational PAL Device Design Steps
It is much more complicated to generate logic equations for a sequential circuit. Generally, the procedures are as follows: 1. Define the inputs and outputs, different states and variables. 2. Generate the state diagram. 3. Generate the state table. 4. Minimize the state table.
88 Programmable Logic Design Guide
5. Assign the new state. 6. Generate the transition table. 7. Use the minimization technique to minimize transition table. 8. These seven steps result in the logic equations. Figure 5.3.2 shows these seven steps.
MINIMIZING THE . STATE TABLE
FUNCTIONAL DESCRIPTION to- - -
STATE DIAGRAM
STATE TABLE
_.,.. MINIMAL
STATE TABLE
STATE ASSIGNMENT
KARNAUGH MAPS OR BOOLEAN ALGEBRA (PROGRAMMING THE PAL DEVICE)
TRANSITION - - - - - - - - . . TABLE ~---
TRANSFER FUNCTION
(LOGIC EQUATIONS)
CIRCUITS
- - - . - j (PAL) DEVICE
-------..J FUNCTION TABLE
Figure 5.3.2 Sequential PAL Device Design Steps
5.4 PROGRAMMING THE DEVICE
Given the logic equations, the PAL device programmer will manage the programming· job for us. All we need to do is to enter those logic equations into the terminal. The programming procedures are shown in Figure 5.4 .1.
After programming, the fuse status should be verified. Most programmers will provide this fuse verification capability.
Manually coding the programming format sheet, which has appeared in National's· 1983 PAL Device Data Book will not be discussed in this Design Guide.
ENTER LOGIC EQUATIONS
LOAD PATTERN INTO
PROGRAMMER
How to Design With Programmable Logic 89
ENTER FUNCTION
TABLE
EXERCISE FUNCTION TABLE
INTO LOGIC EQUATION (SIMULATION)
IF NO FUNCTION TABLE AVAILABLE
CREATE
_.,..
BIT PATTERN
PROGRAM FUSE
MATRIX
VERIFY FUSE
MATRIX
TEST PAL:s FUNCTION WITH TEST VECTORS
ANOTHER* LOGIC TEST
BLOW -~ SECURITY FUSE
IF WANT
* FOR EXAMPLE: DATA I/O's FINGERPRINT TEST.
Figure 5.4.1 PAL Device Programming Procedures
5.5 TESTING THE DEVICE*
Fuse verification tells us if the fuse was blown correctly or not; but it doesn't tell us if the PAL device functions properly. Therefore, we also need to do functional testing. There are two ways to do functional testing. One method uses function tables. Another method uses test vectors. Each of these methods may give a different result. ,
Function tables are generated without reference to the logic equations. The function table tells what the PAL device should do. Function tables are used to determine if the device functions as intended. If it does not, we have to go back to the equations, since there may be a problem there.
Test vectors are generated directly from the logic equations. They are used to verify the internal operation of the PAL device. If a problem is detected, it implies that something is internally wrong with the device. However, a device may pass the test vector screening and still not function properly if the logic equations were derrived incorrectly.
It is the logic designer's responsibility to generate the function table. This is the person who best knows the design. After the design is released, the test engineer will
·Also see Chapter 7 for details about testing.
90 Programmable Logic Design Guide
take the responsibility for testing incoming devices. As mentioned before, the function table.can't catch all the interior bugs. Therefore, the test engine:er needs to write the test vectors. It is a large and sophisticated job to create test vectors. Figure 5.5.1 shows these steps and will be explained in chapter 7. There are a few software packages available for generating test vectors, for example; HIL0 1, and TEGAS2 , LOGCAP~, 'LAZAR4.
LOGIC EQUATIONS I- _..
S·A·O TEST FOR EACH PRODUCT TERM S-A-1 TEST FOR EACH PRODUCT TERM S-A-1 TEST FOR EACH LOGIC EQUATION
Figure 5.5.1 Test Vectors Creating Steps
TEST VECTORS
5.6 PROGRAMMER VENDOR LIST
Mfgr. Data 1/0 Digelec Kontron
Stag
Cite I
Basic Equipment
Model 19, 19A or 100A
µP 803
PAL· Device Module
1427
FAM 51
EPP 80 or MPP SOS
PPX
MOD 21
PM 202+ BAAL
System 47
PAL
Device DesignSoftware
Adapters Included
Performs Logic
Simulation
1428-1
No
No
-2
-3
20+24
Yes
No
Pin
Socket
SA27+
No
No
SA 27·1
.AM10H8 ·
Yes
No
·
AM16C1
PL1
No
No
Storage Media for
Bit Pattern
Master PAL
Test Vectors
-
Master
+
PAL
Master
-
PAL
Master
-
PAL
Master 7 PAL,
PROM, EPROM
PROM
Programs 20- 24· Pin Pin Yes No
Yes Yes
Yes Yes Yes No
Yes Yes
Blows Security
Fuses No
Yes
Yes Yes
Yes
All these systems program and verify the PAL in the PROM mode. They do not perform a logic simulation in the PAL device mode. Additional (external) circuitry for logic simulation should be used if PAL devices go into volume production - otherwise, a small percentage of the PAL devices will show failures when testing the complete PC board. OK for prototype-making.
Table 5.6.1 PAL Device Programmers
1. HILO is a registered trademark of Gen Rad. 2. TEGAS is a registered trademark of CDC. J. LOGCAP is a registered trademark of Phoenix Data Systems. 4. LAZAR is a registered trademark of Teled)!1Je.
How to Design With Programmable Logic 91
Mfgr. Data 10
Digelec
Stag
Structured Design Structured Design
PAL· Basic Device Equipment Module
Adapters
PAL Device DesignSoftware Included
Performs Logic
Simulation
Storage Media for Programs
Bit
Test
20· 24·
Pattern Vectors Pin Pin
Model 19, 29A or 100 and Any Terminal
Logic· Pack
Design NJ.and
Progr.
M
Yes
Yes,
Master External Yes Yes
Automatic PAL
or
or Manual
or
Generation
of Test EPAOM
Vectors
µP 803 FAM 52 20- and
Yes
24-Pin
hJapter
-
ZL30
-
Yes
Any
8D20/
-
Yes
Terminal
24
Any
8D1000
-
Terminal
_L
Yes
Yes,
Master External Yes Yes
Automatic PAL
or Manual
Generation
of Test
Vectors
Yes, Automatic or Manual Generation
of Test Vectors
Master PAL
External
Yes Yes
Yes,
Master External Yes Yes
Manual
PAL
or
Generation or
of Test
Vectors
On Wafertape
Yes,
Master External Yes Yes
Manual
PAL
or.
Generation or
of Test
Vectors
EPROM
Blows Security
Fuses Yes
Yes
Yes
No
Yes
All these systems allow software supported PAL device design. They perform a fuse-verify in the PROM mode and can do a logic simulation in the PAL device mode. All 5 programmers and 5 development systems can be connected with a host computer to run more sophisticated design software and/or for storage use.
Table 5.6.2 PAL Device Development Systems
92 Programmable Logic Design Guide 5. 7 EXAMPLES Example 1: Replace the existing logic circuit in Figure 5. 7_. 1 by a PAL device.
15 o-------+---r----,.
le o - - - - - - - t - - L _ J
l 7 v - -.......---+-----~
la e>---+----+---r------.
lg
.___._.--....". JC>----~ 09
Figure 5.7.1 Design Example, Logic Diagram
We will follow the procedure discussed in this chapter. We know the first step is to understand the function of this circuit. There is no register and latch involved. By experience, we understand that this circuit is used to manipulate different input signals and generate different outputs. We should select the combinational PAL device (i.e., PAL10H8, PAL10L8, PAL12H6, etc.).
The second step is to choose the specific device. Because the number of inputs is 10 and the number of. outputs is 6, _we limit our choice to be 10H8, 10L8, 12H6 and 12L6. Three outputs have AND-OR functions and 3 outputs have AND-OR-INVERT functions. We could still select from either active-high or active-low (H or L) parts. Since the more complex functions are AND-OR-INVERT, the active LOW (L) series is most likely. Therefore, we now limit our choice to the 10L8 and 12L6 devices. A review of the 10L8's logic diagram shows that all of its NOR gates are two-input gates, and the design example requires a three-input gate. On the other hand, the 12L6 has two 4input gates which will accommodate the 3-input requirement. It, therefore, is selected.
The third step is to write the logic equation. It is very straightforward for this example.
How to Design With Programmable Logic 93
We get:
01 /11 02 = /I 1 · 12 03 = 11 + 13
04 = /(/13 * 14) 05 = /(/13 * 15 * 16 + 17 + Is * 19) 06 =/(Is* 19 + /13 * /17 * 19 * 110)
Since we have selected a PAL12L6 (which has inverting outputs) we rieed to apply DeMorgan's theorem to convert tliese equations from active-high to active-low outputs. DeMorgan's theorem can be used to convert any logic form to the AND-OR or AND-NOR structure used in PALs. Applying DeMorgan's theorem gives the active LOW form of the equation:
/01 = 11
102 11 + /12
/03 /11 * /13 /04 /13 * 14
/05 /13 * 15 * 16 + 17 + Is * 19 106 =Is *·19 + /13*/17*19*110
Assuming that there are no board layout constraints, input I1 through I10 may be assigned to pins 1 through 11 (pin 10 is ground). The only constraint on output pin
assignment is that o5 must be assigned to pin 13 or 18 to take advantage of one of the 4-
input NOR gates.
The fourth step is to program the PAL device. To do this we must enter the logic equations into the computer or the PAL device programmer. National's PLAN software allows users to enter logic equations in any format. But PALASM requires the program shown in Figure 5.7.2 in its host computer to be used as follows:
Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 17 Line 18
PAL12L6 PAT201 PAL DESIGN EXAMPLE
11 12 13 14 Is Is 17 la lg GND 110 NC Os Os 04 03 02 01 NC Vee
/01=11 102= 11 +/12 /03 = /11 · /13 /04 = /13 · 14
* /Os= la · lg+ /13 · 111 · lg · 110
/Os = /13 Is · Is + 11 + la · lg
DESCRIPTION
THIS PROGRAM IS A DESIGN SAMPLE DESCRIBING THE USE OF PALASM AS A PAL DESIGN AID.
Figure 5.7.2 Example of PALASM Program Input
94 Programmable Logic Design Guide
Line 1:
At the left margin, the PAL device is specified. For this example, the 12L6 remains the best solution, therefore entering PAL12L6 at the left margin.
Line 2:
A unique pattern number for this PAL device design is entered at the left margin on Line 2, followed by designer's name and date.
Line 3:
The name or description of the device or function is entered. If this runs over one line, Line 4 may be used to complete it.
Line 4: If not used to complete Line 3, this line is skipped.
Lines 5, 6, These lines are used for pin assignments. All 20 of the pins on the PAL are
and 7:
assigned symbolic names, usually corresponding to the symbols used on
the logic diagram. (Note that GND and Vcc must be included.) Assignment
starts at pin 1 and proceeds sequentially, through pin 20.
Line 8:
Beginning on Line 8 or Line 6, if only Line 5 is needed for the pin assign-
ments, the logic equations that describe the required functions are written using the symbols defined in Lines 5, 6 and 7, in the format applicable to the PAL device selected. For example, the output of the 12L6 is low for the selected product term; therefore, the logic equations must be of the form /Ox = f(I 1, 12 ,...). The symbology used must be that shown in Figure 5.7.3.
EQUAL . - REPLACED BY, FOLLOWING CLOCK
I COMPLEMENT · AND, PRODUCT + OR, SUM :+:XOR .·. XNOR ( ) CONDITION TRI-STATE IF STATEMENT, ARITHMETIC
Figure 5.7.3 PALASM Operators
Then the PAL device software will generate the fuse map and bit pattern shown in Table 5. 7.1, load pattern into programmer, program the device and verify the fuse matrix. Since there is no function table in this example, we need to do another logic test to guarantee it works properly. For example, we can do the fingerprint test if we already have a known good device, or we can generate a few (or whole) test vectors to do the structure test in a DATA 1/0 programmer.
How to Design With Programmable Logic 95
8 9 10 11
x-x-Xxxxx xx xx xx
xxxxxx xxxxxx
xxxx xx
xxxx xx
xxxxxx
xxxx xx
xxxx xxxx xx xx
xx xx xx xx xx xx
16 --X17 -X--
24 25
x-x--xXx
x-xXx-x-
xx
xx
xx
xx
xx xx
xx xx
32 33
xx xx
x-xXx-x-
xXx-
xx
xx
xx
xxx,x
xx xx
40
41
-X--
X--- X---
-X
X-X-
48
-X--
X- X-
49
X-
50 51
xx xx
xx xx
xx
xx
xx
xx
xXx- x-.x-
xXx-x-x-
Table 5.7 .1 Fuse Map
Figure 5.7.4 is the logic diagram of this PAL device and Figure 5.7.5 shows the PAL device legend.
Example 2: Design a multiplexer to select one of three input data buses which contain 4 data lines, as shown in Figure 5.7.6. The output should be high if we don't select any data bus.
From Figure 5.7.6 we know there are 14 input lines and 4 outputs. Since we select one out of three, we need 3 product terms in each output. In addition, we need another product term to implement diselection which will cause all output-high. From the PAL device select chart (Table 5.2.1) we find 14H4 is the best fit.
The logic equation is very easily derived from intuition or we can get from the truth table shown in Table 5.7.2.
PLAN software will help us to select the device, assign pinouts, and generate a fusemap. All we need to do is enter the logic equations.
Yl /SELA * /SELB .* A1 + SELA * /SELB * B1 + /SELA * SELB * C1 + SELA *
SELB
Y2 /SELA * /SELB * A2 + SELA * /SELB * B2 + /SELA * SELB * C2 + SELA *
SELB
Y3 /SELA * /SELB * A3 + SELA * /SELB * B3 + /SELA * SELB * C3 + SELA *
SELB
Y4 /SELA * /SELB * A4 + SELA * /SELB * B4 + /SELA * SELB * C4 + SELA *
SELB
96 Programmable Logic Design .Guide
...
--i....~ ~
-2- - f......."~
I I
"
3 ... ~·
" " 4 .....
---t .... ~ ~
" "
5
.~ ... ~
"ll
6 ~
".. 7 ...
....~~
....
",,
8
...
.;>..
I
I
I
~
19
NC
"'""
I
-:=.:i.c -l-[ 1f \
18
-:R. J 2 ~ 17
-~ :::J3 ""-
16
--=-<: ::J 4
.,..,.
~
15
---tS- _J 5 ""- 14
_;.... l_
~6J>
13
-ms:'
...
~
12 NC
.. 9 ....
lg
~
~
11 I
10
Figure 5.7.4 Logic Diagram of the National Type 12L6 PAL®
How to Design With Programmable Logic 97
PAL Legend
Constants
LOW (L) HIGH (H)
NEGATIVE (N) ZERO (0) POSITIVE (P) ONE (1)
GND Vee
FALSE TRUE
- f - x
FUSE NOT BLOWN
- - t - FUSE BLOWN
Operators Equations
EQUAL .- REPLACED BY FOLLOWING CLOCK / COMPLEMENT
AND, PRODUCT + OR, SUM
:+: XOR :*: XNOR ( ) CONDITIONAL THREE S~ATE, IF STATEMENT, ARITHMETIC
Standard PALASM
'1i;+I;12
Il*/I2 + /Il*I2
Conventional Symbology
PAL Device Symbology
Vee
INPUT HIGH
-- LOGIC STATE HL LH
H
PRODUCT WITH ALL \_ FUSES INTACT REMAINS
LOW ALWAYS SHORTHAND NOTATION
~A~FUS~
PAL Logic Diagram
INPUT LINE NUMBER
r O!Jl
PRODUCT ; LINE ;
NUMBERl :
~
~ 'I Ii I
~ q 1U 11
11It1 'I!\ lb 11 U l'I 10 1111 JI 1· I\ Jt.11 Ill l'I JO JI
p IN
NUM BERS''.
I
' b:: ~
,...
..... -j
_1
s.....
lllo '
ACTIVE HIGH THREE-STATE ENABLE
~CKt
J /
~
/AVJ 19
'-
STANDARD SUM OF PRODUCTS
~FORET IS EQUATED AT THESE NODES
~
HE BUBBLE)
/ '
r;:i 18
~v
'
~
""'
Figure 5.7.5 PAL Legend
98 Programmable Logic Design Guide
EN UP/DOWN
~
_..
BCD
~
~
COUNTER
4L 7
BUSA
EN UP/DOWN
CLK
---._..
BCD
COUNTER
4L
/
BUS8
SELECT
4z
BUSC
/
, --......
2;--
MULTIPLEXER
w- ~ DECODER DRIVER
7-SEGMENT DISPLAY
Figure 5.7.6 Block Diagram of a Multiplexer
A1 A2 A3 A4
A1 A2 A3 A4
x x x x x x x x x x x x
B1 82 83 84
x x x x
81 82 83 84
x x x x x x x x
C1 C2 C3 C4
x x x x x x x x
C1 C2 C3 C4
x x x x
SELA SEL8 Y1 Y2 Y3 Y4 L L A1 A2 A3 A4 H L 81 82 83 B4 L H C1 C2 C3 C4 H H HHHH
Table 5.7. 2 Truth Table
We can replace 2 of 745153 in this application. The Function Table and logic diagram are shown in Table 5.7.3 and Figure 5.7.7.
A1 A2 A3 A4 B1 82 83 84
L L .L L. x x x x xxxx xxxx HHHH xxxx xxxx HHHH xxxx xxxx
xxxx xxxx
C1 C2 C3 C4
x x x x x x x x x x x x x x x x
L L L H
L L HL
SELA SELB Y1 Y2 Y3 Y4
L L LLLL
H H HHHH
L L HHHH
H L HHHH
L H LLLH
L
H L LHL
Table 5.7 .3 Function Table
A4 ...
-
Aa ..
~
How to Design With Programmable Logtc 99
Inputs (0-31)
11 J) 4 II I 111111
uunu 11111111
A2 ..
-
.A1
-12:
84 ..
~
Cf)'
co
e I E"'
~ 1S
e:I
a. 83 ..
~ -
-82---u...-·
"""" lj
H II JI JJ
,.IJ
II
'
II
...,,.
Cl
....
C4
_st
~
....
C3
~
~
~
--- _l
:Jo< J
-y :Jo<
Jo<
-:.:_J
../
~
V4
_l
~
- ' _Jo< ~
_Jo< _Jo<
-::i:J_
.../
l
Ya
1
:Joe:
------""""
::J
L
\
../
Y2
l_
Jo< ~
Y1
Jo< :Jo<
:-:.:_J
../
~
i - ·~
....
C2
~ ~
81 ....
....
C1
~
s ELA ...
,, JJ 4111 111111 IJIJ
1111
JIJIJJll HHllJJ 11111111
....
SEL8
~
~
Figure 5.7.7 Logic Diagram of the National Type 14H4 PAL Device
100 Programmable Logic Design Guide
Example 3: Design a 3-bit counter which causes only one bit change for each change of state shown in Figure 5.7.8. A RESET input will initialize the counter to OOOi
The PAL device under design is used for a 3-bit counter with only one input line, RESET. When active, it will reset all three flip-flops. Obviously we can use a 16R4 to implement this application.
A
B
c
0
0
0 f--
0
0
0
0
0
0
REPEAT
0
0
0 .-
0
0
0
0
0
Figure 5.7.8 3-Bit Counter
Q" _ _ _ --an+1·
0 ----- 0
0 ----- 1
1 ----- 0 1 ----- 1
0
J
K
s
R
T
0
0
x 0
x 0
1
1
x 1
0
1
0
x 1
0
1
1
1
x 0
x 0
0
*Q", an+ 1 STAND FOR PRESENT ANO NEXT STATE; XIS DON'T CARE.
Table 5.7.4 Transition Lists
How to Design With Programmable Logic 101
We can easily write the transition table for this simple example as shown in Table 5.7.5.
CLK
R (RESET)
A"
t
0
0
t
0
0
t
0
0
t
0
0
t
0
1
t
0
1
t
0
1
+
0
1
+
1
x
B"
en
An+1
0
0
0
0
1
0
1
1
0
1
0
1
1
.0
1
1
1
1
0
1
1
0
0
0
x
x
0
Table 5. 7 .5 Transition Table
Bn+1
0 1 1 1 1 0 0 0 0
cn+1
1 1 0 0 1 1 0 0 0
We can get the logic equation from Table 5.7.5 by K-map minimization technology as shown in Figure 5.7.9.
AB
. cR 00 01
l 00 0 1
11 10
l1 0
01 0 0 0 0
11 0 0 0 0
' 10 0 0 [ 1 1 J
A
AB
cR 00 01
l 00 0
1
11 10
J1 0
01 0 0 0 0
11 0 0 0 0
J 10 [ 1
1
0
0
B
Figure 5.7.9 K-map
AB
CR 00 01 11 10
00 ~ 0 L!_J 0
01 0 0 0 0
11 0 0 0 0
10 111 0 111 0
c
A:= BCR+ACR B: = BCR+ACR C: = ABR+ABR
We can also get the Function Table from Table 5.7.5. In this case, we replace 2 of 74500 and 1 of 745175.
102 Programmable Logic Design Guide
Example 4: Design a video-telephone sync pulse detector.
The video-telephone set contains a CRT for displaying the received picture from another video-telephone, and a vidicon camera for generating the picture to be transmitted.
The vidicon sweeps across the head and shoulders view of the person talking, starting at the upper left of the picture and moving right as shown in Figure 5.7.10.
Figure 5.7.10 Sweep Generation
The dots shown in the figure represent samples taken by the vidicon. The vidicon produces a voltage that is proportional to the light intensity for each sample taken. The voltage is then quantized into seven levels. These seven levels correspond to light levels from white to black with intermediate levels of gray. Because there are seven quantized levels, a 3-bit quantizer is employed. These seven levels are then channel-encoded such that where the code 1 1 1 is reserved for the line sync pulse. The data are transmitted in a bit-serial manner. When the sync pulse is detected, the receiver camera flies back to start a new line, as shown in Figure 5. 7.10. The use of the line sync pulse ensures that
0 0 0 - --- 0 0 1 0 10 0 1 1 0 0 1 0 1
1 0 - --- -
WHITE LEVELS OF GRAY BLACK
How to Design With Programmable Logic 103
all the lines start at a well-defined left edge. This prevents the occurrence of skewed lines which will distort the picture.
The PAL device under design is used as a sync pulse detector which will trigger the flyback circuit. There is another. feature we need to design into this PAL device which automatically resets to the initial state after three input pulses. This reset procedure will . ensure that no false output occurs due to consecutive sequences which produce an overlapping 1 1 1 sequence.
From the function description above, we can generate the State Diagram and State Table as shown in Figure 5.7.11 (a) and (b).
010, 1/1
x
0
A
D/O
BIO
B
E/O
C/O
c
A/O
A/1
D
E/O
E/O
E
A/O
A/O
(A) STATE DIAGRAM
(B) STATE TABLE
Figure 5.7.11 (A) State Diagram (B) State Table ·
Where A is the initial state, the sequence A~ B ~ C __!.fl_. A will detect the sync pulse (1 1 l) and generate a "1" output. Note that the state diagram is arranged so that every sequence of length 3 returns the machine to the initial state A.
Since we have 5 different states (3 registers are enough), 1 input for serial data, 1 non-register output for sync pulse detecting, we may use the 16R4 to implement this application.
104 Programmable Logic Design Guide Let's assign these 5 different states as in Table 5.7.6.
STATE
A B
c
D E
STATE ASSIGNMENT
Y1, Y2, V3
000 001 0 1 0 1 0 1 1 1 0
Table 5.7.6 State Assignment
Then from the State table Figure 5.7.11 (B) we get the Transition ta~le shown in Table 5.7.7.
y1 y2 y3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
x
0
1
x
0 1
101 001 0 0 110 010 0 0 000 000 0 1
xxx xxx x x xxx xxx x x
1 .1 0 1 1 0 0 0 000 000 0 0
xxx xxx x x
Y1 V2 VJ
Z
Table 5.7.7 Transition Table
From Table 5.7.7 Transition Table we can draw the K-map of each register output Yl, Y2, Y3 and the non-register output Z as shown in Figure 5.7.12.
How to Design With Programmable Logic 105
y3 x
y1 y2 0 0 0 1 1 1 1 0
[ ] 0 0
0
0 []
y3 x
y1 y2 0 0 0 1 1 1 1 0
0 0
o. 0
1 1
01 0
0
x
x
01 0
0
x x
1 0
0
x
x
10 0 x x
0 0
x
1 [~ .___
0x x 1 1
Y1
Y1 = Y1*Y3 + v2·x
Y2 Y2 = Y3
Y3 X Y1 Y2 0 0 0 0 [1
0 1 11 10
J 1
0
0
0 1
0
0
x
x
1 0
0
x
x
l x] 0 x
0
0
Y3
Y3 = Y2*Y3
Y3 X
Y1 Y2 0 0
0 0
0
0 1 0
1 1· 1 0
0
0
J 0 1
0 ~1
x x
1 0
0
x x
0 x
x
0
0
z z = v1 ·v2·x
Figure 5.7.12 K-map
Therefore, we get the logic equations as:
Yl := Yl *Y3 + Y2*X
Y2 := Y3 Y3 := Y2*Y3 Z = Yl *Y2*X
106 Programmable Logic Design Guide
Summary
The four design examples are quite simple for purposes of illustration. The author has attempted to give the reader a very clear idea and to encourage the reader to use PAL devices. The reader can find other examples in the applications section of Chapter 8.
Here the author would like to point out one thing; "There are many different approaches to designing a PAL device circuit.'' Some users like to directly code the PAL device logic diagram (coding "x"). In this case, users may not need logic equations. But if circuits become more complicated, then the user will find that the logic equations are much easier to get than directly coding "x" in the PAL device logic diagram. There are many ways to develop logic equations. One approach is to use truth tables or transition tables. Another way, which is widely used, is from timing waveforms.
The user can draw the timing diagram for each output, then derive his logic equations from these timing waveforms. But no matter what method is used, the user still needs to know the K-map or other techniques (the Quine-McCluskey method is frequently used) to minimize his logic gates.
The author strongly recommends deriving the logic equations for PAL devices rather than coding "X" in the PAL device logic diagram. Then the user can take advantage of PAL device software (PLAN, PAIASM, etc.) instead of manually coding the PAL device programming format sheet.
6
Software Support
Today a variety of software products makes the logic design engineer's task much easier. The designer can now focus on the intricacies of logic design at the Boolean level instead of filling in tedious fuse map charts, or worrying whether a standard logic part exists to implement the logic. Some of the traditional programmer vendors are now marketing full-fledged development systems or CAD systems that include the terminal, software and the hardware for fuse blowing, and logic verification. Other vendors market software only or programmer/verifier only. The key part of any development system is the software and this section describes the attributes of these products.
6.1 ADVANTAGES OF SOFTWARE-BASED PROGRAMMABLE LOGIC DESIGN When programmable logic devices were first introduced, the only method for specifying the logic to be implemented was to manually code the status of each fuse on a form and then enter this information into a programmer. With a device like the PAL16L8 which has 2048 fuses, this manual method is clearly time-consuming and error-prone. Furthermore, these early programmers could not verify if the programmed device was functional. They could only check if the correct fuses were blown. Information about testing is found in Chapter 7.
The first phase in software development was the development of tools to eliminate the manual fuse-map entry. Users could enter Boolean equations in Sum-Of-Products format on a computer and the program would generate the fuse-map information which could be downloaded to a programmer unit (Figure 6. l.1).
Figure 6.1.1 Early Role of Software
107
108 Programmable Logic Design Guide
Subsequent developments in software goes further in providing two additional capabilities. The first area of improvement is logic design. Recent developments are emphasizing design tools for logic circuit desig1_1 with features like high level logic design options and plans for logic minimization, and state-machine synthesis. The second area being addressed is that of functional testing of programmed devices. Most of the current software has features to perform simulation for design verification, i.e., verify if the user supplied test vectors match the logic conditions described by the equations for the logic being implemented. These test vectors can also be downloaded to a programmer which will perform a functional test on the programmed device (Figure 6.1.2).
LOGIC EQUATIONS
PAL DEVICE
PROGRAMMED DEVICE
LOGIC DESIGN AIDS
Figure 6.1.2 Expanded Role of Software
The next section describes National's contribution to advanced programmable logic design software called Programmable Logic Analysis by National (PLAN).
6.2 PROGRAMMABLE. LOGIC ANALYSIS BY NATIONAL (PLAN)
PLAN is a set of interactive· software tools for logic designers who will be using programmable logic devices i~ their circuits. Th~ advantages of PLAN are that: (1) it is easy to use; and (2) it comes with clear and simple documentation that explains the numerous features of PLAN and the methods of accessing and using these features. PLAN also has a liberal sprinkling of error messages to help the user. PLAN does not have PALASM type input format constraints and is available on more than one operating system. The package actually contains three programs: PLUS, SERV, and PROG.
PLUS allows the user to define logic via Boolean equations and also selects an appropriate device and assigns pin-outs. The resulting equations, device, and pin-outs are stored in a file.
Software Support 109
The next program, called SERV, can then be used to access the logic defined by PLUS for possible reassignment of the device and pin-out. When the device and pin-outs are finalized, SERV also displays the pin-out diagrams, fuse-maps and equations. For documentation purposes, the above data can also be printed out.
The third program, called PROG, takes the logic and pin assignment data and provides it to a programmer in a format that the user selects. This program can also acquire a previously defined file containing test vectors and download it to a programmer for functional verification.
The ·software package is available on 8-inch SSSD (Single Side Single Density) floppy disks to run under CP/M-80 and 5 1/4-inch SSSD floppy disks for operation under MS-DOS and APPLE-DOS. Future revisions will include other operating systems.
Boolean Entry . The Boolean entry operators that PLAN supports are shown in Table 6.2 .1
EQUALITY · AND,PRODUCT
+ OR, SUM I COMPLEMENT. ·
. - REPLACED BY (AFTER CLOCK)
0 CONDITIONAL TRI-STATE
: + : EXCLUSIVE OR
Table 6.2.1 Boolean Operators
An example of a logic equation using these qperators is: (/INPl · INP2) OUT2 = /INP3 * INP4
A useful feature. that PLAN offers during Boolean logic entry is the definition and inclusion of logic macros. Table 6.2 .2 is an example of the use of the macro feature in PLAN.
MACRO IS EN1 ·/CK2
INPUT
= OUT1 INP1 */INP2
+ /INP1 * INP2
= OUT2 INP3 + INP4
*INPS*INP6
RESULTING EQUATION
= OUT1 INP1 */INP*1EN1 */CK2
+ /INP1*1NP2*EN1*/CK2
= OUT2 INP3 + INP4EN1 */CK2
*INPS*INP6
Tuble 6.2.2 Macro Entry with PLAN
110 Programmable Logic Design Guide
PLAN allows the user to edit the Boolean equations after entry. When the equations are finalized, the program will automatically select a device that can implement the defined logic and assign pin-outs to that device. This process is shown in Figure 6.2.3~
The information can also be stored in a file and the data in the file is essentially the information in Figure 6.2 .3.
EQUATIONSNARIABLE_S
LADSHG = D*KJR*/RDIUH
+ OJH*IH
OEU = EUY*KJR + DU ERIJH = DJ*JD*JJJ·JPP
+ IODF*DFJ*JJJ*JPP
I
DEVICE
LOGIC DEVICE NAME IS PAT0099 THE SOURCE DEVICE IS A PAL 14H4 A SERIES 20 SMALL PAL WITH ACTIVE HIGH OUTPUTS
PIN OUTS
D--1 1 """lC7 20 1--Vcc ·
KJR--1 2
19 I -
RDIUH--1 3
18 t-DFJ
OJH--1 4
17 I -
IH- 5
16 t-OEU
EUY- 6
15 t-LADSHG
DU- 7
14 t-ERIJH
DJ-I 8
13 t--IODF
__..
JD-I 9
12 t-JPP
GND_, 10
11 t-JJJ
Figure 6.2.1 PLAN File Information
File Editing and Documentation
The program SERV can be used to change the selected device and also to change the pin-out assignment. When the device and pin-outs have been finalized, the device diagram with pin-out, the equations or the fuse-map of the programmed device can be printed out or viewed on the screen. Figure 6.2.4 is an example of the fuse-map display.
Programming and Testing
In order for a programmer to function, it has to receive the fuse-map information in a specified format. The third program in PLAN, called PROG, will provide the fuse-map information, at the users option, in any of the five formats listed in Table 6.2.3.
The programmer fuse-map data can be saved in a file for later use. PROG can also access a file containing test vectors and download them to a programmer for functional verification of a programmed device.
Because of its ability to support the various data formats, niany programmers are supported by PLAN and most are physically interfaced through a standard RS-232 cable.
Software Support 111
FUSE MAP FOR LOGIC PAT0099 - SOURCE DEVICE IS DMPAL 14H4
INPUTS (0·31)
1
1 22 22 23
02 46 80 2 6 02 46 80
16 xxxx xxxx xxxx xx xx xxxx xxxx xxxx 17 xxxx xxxx xxxx xx xx xxxx xxxx xxxx 19 xxxx xxxx . xxxx xx xx xxxx xxxx xxxx
24 X--
X-
EUrKJR
25
X---
DU
26 xxxx xxxx xxxx xx xx xxxx xxxx xxxx
27 xxxx xxxx xxxx xx xx xxxx xxxx xxxx
32 X-X- -X--
D*KJR*/RDIUH
33
X--- X-
OJH*IH
34 xxxx xxxx xxxx xx xx xxxx xxxx xxxx
35 xxxx xxxx xxxx xx xx xxxx xxxx xxxx
40
X-X- X-X- DJ*JD*JJJ*JPP
41
--X-
--X- --X- --X- IODF*DFJ*JJJ*JPP
42 xxxx xxxx xxxx xx xx xxxx xxxx xxxx
43 xxxx xxxx xxxx xx xx xxxx xxxx
PRODUCT TERMS (0-63)
X'S REPRESENT INTACT FUSES, 152 HAVE BEEN REMOVED.
Figure 6.2.2 Fuse-Map Display from PLAN
MMI Hex JED EC Intel Hex Standard Hex PALASM Format
Table 6.2.3 Fuse-Map File Formats in PLAN
Order from: National Semiconductor Corporation PLAN 2900 Semiconductor Drive MIS D3698 Santa Clara, CA. 95057 (408) 721-4107
112 Programmable Logic Design Guide
6.3 OTHER SOFTWARE
CUPLTM by Assisted Technology
CUPL is the first software CAD tool designed especially for the support of all programmable logic devices (PLDs), including PALs and FROMs. It was developed specifically for YOU, the Hardware Design Engineer. Each feature of the· CUPL language has been chosen to make using programmable logic easier and faster than conventional 1TL logic design.
Major Features of CUPL
Universal · PRODUCT SUPPORT: CUPL supports products from every manufacturer of of programmable logic. With CUPL you are free to use not only programmable logic. With CUPL you are free to use not only PALS, but also other programmable logic devices. · PALASM CONVERSIONS: CUPL has a PALASM to CUPL language translator which allows for an easy conversion from your previous PAIASM designs to CUPL.
· LOGIC PROGRAMMER COMPATIBILl1Y: CUPL produces astandardJEDEC down-
load file and is compatible with any logic programmer that JEDEC files.
High Level Language High Level Language means that the software has features that allow you to work in terms that are more like the way you think than like the final PLD programming pattern. Examples of these are:
· FLEXIBLE INPUT: CUPL gives the engineer complete freedom in entering logic descriptions for their design. - Equations - Truth Tables - State Machine Syntax
· EXPRESSION SUBSTITUTION: This allows you to pick a name for an equation and then, rather than write the equation each time it is used, you need only use the name. CUPL will properly substitute the equation during the compile process.
Software Support 113
· SHORTHAND FEATURES: Instead of writing out fully expanded equations CUPL
provides varous shorthand capabilities such as:
- List Notation: Rather than [A6,AS,A4,A3,A2,Al,AO]
CUPL only requires [A7..0]
- Bit Fields: A group of bits may be assigned to a name,
as in FIELD ADDR = [A7..0]
Then ADDR may be used in other expressions
- ·Range Function: Rather than
Al 5 & !Al4 #
Al5 & Al4 & !A13 #
Al5 & Al4 & Al3 & !Al2
CUPL only requires ADDR: [8000..EFFF] ·
- The Distributive Property:
From Boolean Algebra, where
A & (B # C)
is replaced by
A&B#A&C
- DeMorgan's Theorem:
From Boolean Algebra, where
!(A & B)
is replaced by
!A# !B
Self Documentirig CUPL provides a template file which provides a standard "fill-in-the-blanks" documentation system that is uniform among all CUPL users. Also, CUPL allows for free form comments throughoutyour work so there can be detailed explanations included in each part of the project.
Error Checking CUPL includes a comprehensive error check capability with detailed error messages designed to lead you to the source of the problem.
Logic Reduction CUPL contains the fastest and most powerful minimizer offered-for Programmable Logic equation reduction. The minimizer allows the choice of various levels of minimization ranging from just fitting into the target device to the absolute minimum.
Simulation With CSIM, the CUPL Simulator, you can simulate your logic prior to programming an actual device. Not only can this save devices but it can help in debugging a system level problem.
Test Vector Generation Once the stimulus/response function table information has been entered into the simulator, CSIM will verify the associated test vectors and append them to theJEDEC file for downloading to the logic programmer. The programmer will verify not only the fuse map, but also the functionality of the PLD, giving you added confidence in the operation of your custom part.
114 Programmable Logic Design Guide
Expandability CUPL is designed for growth so as new PALs and other devices are introduced you will be kept current with updated device libraries and product enhancements.
CUPL-GTSTM
In recent years, programs like CUPL and ABEL have become available to provide high level language support for PAL designs. These languages allow the designer to represent a PAL function in terms of high-level equations, truth tables or state machines~
Many hardware designers, however, are most comfortable with the traditional logic schematic as a logic description format.
CUPL-GTS is a powerful combination of hardware and software which turns an IBMPC type computer into a programmable logic workstation allowing the user to draw logic schematics for the function of a PAL. A basic premise in creating GTS was to provide a friendly environment where the user is isolated from the traditional keyboard as much as possible. Virtually all functions can be actuated with one button by way of the mouse and a series of pop-up menus which ease the user's task An area is provided at the top of the CUPL-GTS screen for prompting the user regarding the next operation in a command sequence. Highlighting of various elements on the screen is coordinated with these prompts. For the most part, the user need only utilize the conventional keyboard for defining symbolic names for wires, pins, objects, and files.
An on-screen HELP facility is provided to aid the user with CUPL-GTS commands.. In addition to the basic set of object types which can be easily picked from a pop-up menu, the ability to call up macro-objects is also provided. These macro-objects have been preyiously drawn using GTS and stored away on the disk under their own symbolic name.
After a logic schematic has been entered, the user may quickly check to see if the design fits into a specific PAL. This is done by selecting the "Translate to PLD" command from the main menu which automatically invokes the GTS translation programs. These programs run in an on-screen window which overlays the graphical information, providing feedback in the form of error messages displayed in this window. In this way many errors can be quickly .determined and remedied without ever having to let go of the mouse.
When the user wishes a hard copy version of a design, the print command from the main menu may be selected. This causes the GTS print program to execute in an onscreen wndow according to the printer configuration file (PRINTCAP). The PRINTCAP .file allows the user to configure the GTS print function for any dot matrix printer they might have.
Often a logic description does not fit in a particular PAL due to a logic capacity (product-term) limitation. When this occurs, the universal capability_ ofGTS will easily allow the user to try placing this same logic in a different PAL of a· similar architecture.
Software Support 115
Since CUPL-GTS incorporates CUPL the high level language in its internal operation, it also benefits from CUPL's powerful "Quine Procedure" logic minimizer. This is especially advantageous for CUPL-GTS as logic descriptions showing many levels of gates can be very deceptive in their ability to consume the logic capacity.of a PAL. The presence of the logic minimizer can eliminate unnecessary and redundant logical functions, and maximizes the probability that a design will fit in a target PAL.
Also included with CUPL-GTS is the CUPL simulator; CSIM, which allows the user to simulate a logic design prior to physically creating a programmed PAL. Not only can this save devices, but it can help significantly in debugging a system level problem.
CUPL-GTS is designed for growth and expandability. As new programmable logic devices are introduced users will be kept current with updated device libraries and product enhancements.
Most of us first use PAL devices to replace 1TL in order to shrink a design and/or add functionality. The following example shows how a simple 1/0 decoder design would appear on the CUPL-GTS screen prior to translation to a PAL16L8 or PAL16P8.
ISelect Command From Main Menu
Help
Change Scale
AEN 9
LS32
LS04
Set Center Redraw Screen Add Object
LSOO
IOREQ
LSOO
LS04
Add Wire Add Pin
Change Object
LS04
Name/Rename Move
Delete
Query
Find
7 AS
Translate to PLO Load From Disk
A9 8
Save On Disk Quit
More .··
Figure 6.3.1 CUPL-GTS Screen Display Example
116 Programmable Logic Design Guide
PALA SM
The oldest design aid for PAL devices is PALASM, which is a FORTRAN IV-based software package. PALASM accepts logic equations in a rigid format and assembles· them into fuse-map data for programmers. In addition, PALASM also accepts user input test vectors, performs simulation and formats them to be programmer compatible. Table 6.3.2 lists the PALASM operators.
Comment follows
Complement, prefix to a pin name.
* +
AND (product) OR (sum)
:+:
XOR (exclusive OR)
=*:
XNOR (exclusive NOR)
( )
Conditional three-state
Equality
Replaced by after the low to high
transition of the clock.
Table 6.3.2 PALASM Operators
ABEL TM by Data 1/0
As the use of PALs and PLEs (PROMs) increases, high level design tools become neces-
sary. Designers need easier, faster, and more efficient ways to design with such pro-
grammable devices. With the more complex devices currently being introduced to the
market, this need is even greater. Additionally, a designer should be able to specify logic
designs in a way that makes sense in engineering terms; he or she should not have to
learn a new way of thinking about designs.
ABELTM, a complete logic design tool for PALs, PLEs, and FPLAs meets these require-
ments. ABELTM incorporates a high-level design language and a set of software programs
that process logic designs to give correct and efficient designs. ABELTM was developed by
Data I/O Corporation, Redmond, WA
The ABELTM design language offers structures familiar to designers: state diagrams,
truth tables, and Boolean equations. The designer can choose any of these structures or
combine them to describe a design. Macros and directives are also available to simplify
complex designs.
.
The ABELTM software programs process designs described with the high-level lan-
guage. Processing includes syntax checking, automatic logic reduction, automatic design
simulation, verification that a given design can be implemented in a chosen device, and
automatic generation of design documentation.
Software Support 117
To use ABEL TM, the designer uses an editor to created a source file containing an ABELTM design description. He then processes the source file with the ABELTM software programs to produce a programmer load file. The programmer load file is used by logic and PLE programmers to program devices. Several programmer load file formats are supported by ABELTM so that different programmers may be used.
The source file created by the designer must contain test vectors if simulation is to be performed. Test vectors describe the desired (expected) input-to-output function of the design in a truth table format. The ABELTM simulator applies the inputs contained in the test vectors to the design and checks the obtained outputs against the expected outputs in the vectors. If the outputs obtained during simulation do not match those specified in the test vectors, an error is reported.
Following is a design described in the ABELTM design language. This design would be processed to verify its correctness and to reduce the number of terms required to implement it. The design is implemented in a PAL.
6809 Memory Address Decoder
Address decoding is a typical application of programmable logic devices, and the following describes the ABEL TM implementation of such a desing.
Design Specification
Figure 6.3.2 shows a block diagram for the design and a continuous block of memory divided into sections containing dynamic RAM (DRAM), 110 (IO), and two sections of ROM (ROMl and ROM2). The purpose of this decoder is to monitor the six high-order bits (Al5-A10) of a sixteen-bit address bus and select the correct section of memory based on the value of these address bits. To perform this function, a simple decoder with six inputs and four outputs is designed with a 14L4 PAL.
A15 ROM1
A14
ROM2 A13
10 A12
DRAM A11
A10
IROM11ROM2- 1/0
~ DRAM
FFFF F800 F000 E800 E000
0000
Figure 6.3.2 Block Diagram: 6809 Memory Address Decoder
118 Programmable Logic Design Guide
Table 6.3.1 shows the address ranges associated with each section of memory. These address ranges can also be seen in figure 6.3.2.
Memory Section
DRAM 1/0
ROM2 ROM1
Address Range {hex)
0000-DFFF EOOO-E7FF FOOO-F7FF F800-FFFF
Table 6.3.1 Address Ranges for 6809 Controller
Design Method
Figure 6.3.3 shows a simplified block diagram for the address decoder. The address decoder is implemented with simple Boolean equations employing both relational and logical operators as shown in figure 6.3.4. A significant amount of simplification is achieved by grouping the address bits into a set named Address. The lower-order ten address bits that are not used for the address decode are given "don't care" values in the address set. In this way, the designer indicates that the address in the overall design (that beyond the decoder) contains sixteen bits, but that bits 0-9 do not affect the decode ·of that address. This is opposed to simply defining the set as, Address = [A15,A14,A13,A12,All,Al0}, which ignores the existence of the lower-order bits. Specify,ing all 16 address lines as members of the address set also allows full 16-bit comparisons of the address value against the ranges shown in table 6.3.1.
Address
Figure 6.3.3 Simplified Block Diagram: _6809 Memory Address Decoder
SoftwareSupport 119
mod u 1e rn6809a title 1 6809 memory decode Jean Designer Data I/O Corp Redmond WA
24 Feb 19841
U09
device 1 P14L4';
A15,A14,A13,A12,A11,A10 pin 1,2,31 4 1 5,6;
ROM1 1 101 ROM2,DRAM
pin 14,15,16,17;
H,L,X ,. 1,0,.X.; Address .. CA15, A14, A13, A12, Al 1, AlO, X, X, X, X, X, X, X, X, X, XJ;
equations !DRAM !IO !ROM2
!ROMl
= <Address <= AhDFFF>;
<Address>= AhEOOO> & (Address
= (Address>· AhFOOO> & <Address
= <Address>= AhFBOO>;
<= AhE7FF>; <= AhF7FF>;
test vectors er1d m6809a
<Address->
"hOOOO -> ··'·h4000 -> "h8000 -> "hCOOO -> ''hEOOO -> ····hE800 -> AhFOOO -> "hF800 ->
CROM1,ROM2,IO,DRAMJ>
C H, H, H, L J;
C H, H, H, L J ;
C H, H, H, L J;
C H, H, H, L J;
C H, H, L, H J;
C H, H, H,
( H, L, H,
H J; H J;
C L, H, H, H J; ·
Figure 6.3.4 Source File: 6809 Memory Address Decoder
Test Vectors
In this design, the test vectors are a straightfoiward listing of the values that must appear on the output lines for specific address values. The address values are specified in hexadecimal notation on the left sife of the"->'~ symbol. Inputs to a design always appear on the left side of the test vectors. The expected outputs are specified to the right of the "->"symbol. The designer chose in this case to use the symbols Hand L instead of the binary values 1 and 0 to describe the outputs. The correspondence between the symbols and the binary values was defined in the constant declaration section of the source file, just above the section labeled equations.
Summary
A design described with the ABELTM design language has been shown. This design shows how Boolean equations with logical and relational operators are used to describe an address decoder. Test vectors were written to test the function of the design using ABELTM 's simulator. In addition to the Boolean equations shown in this example, ABELTM features truth tables and state diagrams. State diagrams allow the designer to fully describe state machines in terms of their states and state transitions. Truth tables specify designs in terms of their inputs and outputs, much like test vectors.
Regardless of the method used to describe logic, ABELTM's automatic logic reduction and simulation ensure that the design uses as few terms as possible and that it operates as the designer intended. The end results are savings in time, devices, board space, and money.
120 Programmable Logic Design Guide
6.4 SOFTWARE FOR TESTING PROGRAMMABLE LOGIC
Some of the test equipment vendors also have software that can be used for testing programmed devices in a production environment. These software packages do not have any design .aids but have automatic test vector generation and simulation tools and are generally written to run on powerful mini-computers.
6.5 SOFTWARE VENDOR LIST
Listed below are the major software vendors for Programmable Logic.
NATIONAL SEMICONDUCTOR CORPORATION PLAN 2900 Semiconductor Drive MIS 16-198 P.O. Box 58090 Santa Clara, CA 95052-8090 (408) 721-4107
ASSISTED TECHNOLOGIES, INC. 2381 Zanker Road, Suite 150 San Jose, CA 95131
DATA 1/0 CORPORATION 10525 Willows Road N.E. C-46 Redmond,. WA 98052
A vendor who supplies software for production testing of Programmable Logic is provided below.
GENRAD 170 Tracer Lane Waltham, MA 02254
7
Testing and Reliability
7.1 NATIONAL FACTORY TESTING
National's PAL devices include special test circuitry designed to permit thorough AC and DC testing to be accomplished on an unprogrammed unit. This test circuitry is used to ensure good programming yield and to verify that devices will meet all parametric and switching specifications after programming.
Each PAL device has special test fuses. These test fuses are blown during factory testing and demonstrate beyond reasonable doubt that the device is capable of opening all fuses when programmed by the user. They also increase the confidence level in unique addressing.
Table 7.1.1. shows the total number of fuses and test fuses for each device. Figure 7. 1.1 shows the PAL test flow in National's factory.
Since PAL devices are logic devices, in addition to testing_ the fuses blown their logic function should be tested after programming. This can be performed on a National tester, or on some PAL device programmers, using user defined test vectors or by comparison against a known good unit (fingerprint test).
Test vectors are relatively easy to generate for combinational designs using PAL devices. Sequential function testing is more difficult.
National's application Note# 351 by Tom Wang tells the user how to generate these test vectors. National also supports customer test vectors and fully tests its custom order NML or programmed PAL devices.
Device Number
PAL10H8 PAL12H6 PAL14H4 PAL16H2 PAL16C1 PAL16L8 PAL16R8 PAL16R6 PAL16R4
AND Array Organization
Input Lines
x
T/C
x
Product Lines
=
Number of Fuses
10
2
16
320
12
2
16
384
14
2
16
448
16
2
16
512
16
2
16
512
16
2
64
2048
16
2
64
2048
16
2
64
2048
16
2
64
2048
Table 7 .1.1 Test Fuses
Number of Test Fuses
42 44 46 48 48 98 98 98 98
121
122 Programmable Logic Design Guide
START
F
~-·~
OPENS AND SHORTS
·~
ICC
·-F -
GROSS FUNCTIONAL
"HIGH"
·-F
~-
GROSS FUNCTIONAL
"LOW"
'-F
~-
MIX CHECK
1
WORD PATTERN CHECK
I
F ~
BIT PATTERN CHECK
l
ARRAY CHECK
I
PROG WORD
l
PROG BIT
F
~--1
l
ARRAY CHECK
l
t FOR SAMPLE ONLY
* FOR NMUPROGRAMMED PAL
l
VERIFY WORD ~·
I
VERIFY BIT
-·F
~·
1
DC PARAMETRIC
TESTS
l
AC TESTt
-·F
~·
_F ,.
~·
I
*FUNCTIONAL TEST
-·F
~
Figure 7.1.1 PAL Device Test Flow
Testing and Reliability 123
7.2 LOGIC VERIFICATION
PAL devices are not only memory devices, but also logic devices. Therefore, in addition to verifying the fuses blown after programming, we also need.to verify the logic operation before it is put in a system. Logic verification provides assurance that a device will function in a board. Figure 7.2 .1 shows the PAL device's architecture which will clarify the difference between fuse programming/verification and logic verification. The programming/verification circuit is required to allow custom configuration by the user. This circuit is operational only when a super voltage is applied to Vcc· Under normal 5.0 volt operation, this circuit is invisible and the logic circuit will take over. Therefore the skills we use to check the PAL device under normal 5.0 volt operation are called logic verification. The most important skill we use now is called functional test.
PROGRAMMING/
~
VERIFICATION
CIRCUIT
--t--I-N-P-UT---1-----,
--"
.............
... PROGRAMMABLE ARRrA-Y ------
1------------
OUTPUT
-------·
I
!
L----.-
LOGIC CIRCUIT
-PROGRAMMINGNERIFICATION FLOW ---FUNCTIONAL FLOW
Figure 7.2.1 PAL Device's Architecture
124 . Programmable Logic Design Guide
Functional testing must accomplish two purposes:
1) It must verify that the PAL device, after programming, performs the function intended.
2) It must verify the circuit removed through programming does not affect the PAL. device's operation.
The functional testing technique relies on the test vectors. A test vector means a combination of desired input variable values and expected outputvariable values. The PAL device will be exercised by the desired input values. Then, the received outputs will be compared w~th the expected output values. The device is considered a "malfunction" if the comparison does not match. Figure 7.2 .2 shows an example.
EXERCISEDINPUTS 1 1 0 1 1 0 1 1 0 1
J
l
EXPECTED OUTPUTS
10110110
\..
,...
.I
~
PAL } OUTPUTS
DEVICE
INPUTS ...... ~ "
[ ...... ~ ...... COMPARISON ~
ERROR IF ...... ~
MISMATCH
Figure 7.2.2 Function of Test Vector
There are many methods ofgenerating test vectors:
1. Exhaustive - generate the whole different input combination and the expected output values. For instance, for 3-input AND gate in Figure 7.2.3, we get eight test vectors as in Table 7.2 .1. For an n-inputs device, we get 2n test vectors.
A B
c
Figure 7 .2.3 3-lnput AND Gate
Testing and Reliability 125
A
B
c
F
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
Table 7.2 .1 Test Vectors Generated by Exhaustive Methods
2. Fault modeling - Use the stuck at Oand stuck at 1 technique to sensitize the different logic path. For instance, in Figure 7.2.3, there are three different paths, i.e. AF, BF and CF. Therefore we get six test vectors shown in Table 7.2.2 (a). Due to vector 1,3 and 5 being the same, we can reduce to four test vectors as in Table 7.2.2 (b).
A
B
c
F
1
1
1
1
0
1
1
0
1
1
1
1
1.
0
1
0
1
1
1
1
1
1
0
0
(A)
A
B
c
F
0
1
0
1
0
0
0
0
(B)
Table 7 .2 .2 Test Vectors Generated by Fault Modeling
3. Structure Test - Only pick up the possible existing input states and their corresponding output states.
There is another skill to do the logic verification. It uses the signature analysis technique. This technique uses random input values exercising on a good device to generate different outputs. The outputs are manipulated in certain ways to get a "test sum" called a "signature." Then, using the same sequence of input values to another device we get its signature which is compared with the known good one. Some PAL device programmer vendors offer user fingerprint tests which are based on signature analysis techniques such as DATA 110, Digital Media.
126 Programmable Logic Design Guide
7.3 CUSTOMER'S RESPONSIBILITfES
The number of parts that are non-functional after programming is generally less than 2 % and may be picked up. during board-level check. However, the author strongly recommends that the user do the logic verification before putting PAL device components into the system.
Since the user defines the function of the PAL device, it is impossible for the supplier to perform full functional testing prior to shipment unless the user orders an NML or programmed PAL device from National.
It is the user's responsibility to generate test vectors or do the fingerprint test. The methods for generating test vectors was discussed in Section 7.2.
7.4 RELIABILITY DATA
Following is sample reliability data on National's PAL devices. For additional information
please contact your National representative or distributor.
.
Product: Package:
Bipolar PALs (DM3300) Molded (N) and Hermetic 0)
Test Method: Dynamic (DHlL)/Static (SHlL) High Temperature Operating Life Conditions: Continuous Operation at Rated Supply Voltage, and 125°C Duration: 1000 Hours
Filel.D.
Device Package Test Sample 168 500 1000
Type
Type
Size Hours
Failure Mode
RMB75131 RMB75133 RMB75101 RMB75137 RMB75096 RMB75132 RMB75097 RMB75142 RMB75143 RMB75144 RMB75190 RMB75144 RMB75154
16R4 16L8 16R6 16R6 16R4 16R4 16L8 16R8 16L8 16R8 16R4 16R8 16L8
J
DHTL
77
77
77
. 77
SHTL
77
77
77
77
N
DHTL
77
77
77
SHTL
77
77
0
0
0
0
0
0
0
0
0
0
1
0 Fuse verify and functional
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Total Devices: 1001 Total Device Hours at 125°C: 1001·103
Testing and Reliability 127
Failure Rate at Stress = 0.2%/1000 Hours
Total Device Hours at 55°C, and 0.4EV = 12.012*106
Failure Rate at 55°C, 0.4EV and 60% Confidence Level: %/1000 Hours: 0.0168; PPM Hours: 0.168; Fits: 168; MTBF: 5.9*106
Test Method: Temperature Humidity Bias Test Conditions: Continuous Operation at Rated Supply Voltage, 85°C, and 85%RH Duration: 1000 Hours
Fllel.D.
Device
Package
Sample
168
500
1000
FallureMode
iype
"fYpe
Size
Hours
RMB75143
16L8
N
RMB75144
16R8
RMB75199
16R4
77
0
0
0
77
0
0
0
77
0
0
0
Total Devices: 231 Failure Rate at Stress: 0.4%/1000 Hours
7.5 PAL DEVICE FUNCTIONAL TESTING
Combinational and Sequential Circuits
Digital circuits can be classified as either combinational or sequential. Combinational circuits (e.g., decoder, multiplexer, adder, etc.) whose present value of the outputs at any time are functions of only the present circuit inputs at that time can be described as:
Y = F(X)
where Fis Boolean sum of products transfer function (Figure 7.5.1).
---+@-+ INPUTS X
OUTPUTS Y
Figure 7.5.1 Combinational Circuit
Sequential circuits (e.g., counter, shift register, accumulator, etc.) whose present value of the outputs at any given time will be the functions not only of the present circuit inputs at that time, but also the previous value of the outputs can be described as:
Y= F(X, Y) where Fis the Boolean Sum-of-Product transfer function. See (Figure 7.5.2).
128 ~Programmable Logic Design Guide
CLOCK INPUTS X
OUTPUTS V
Figure 7.5.2 Sequential Circuit
Description of PAL (Programmable Array Logic) Device
Due to rapidly increasing integrated circuit technology, logic circuit designers face a difficult decision: should they use conventional TTL gates or custom LSI to implement desired combinational/sequential circuits.
Use of conventional TTL gates does not take advantage of the increased ·integration available. However, expensive and complicated software often makes custom LSI unsatisfactory. There is a big void between these two solutions. This void is now being addressed by semicustom approaches (e.g., PAL devices or gate array, etc). Since PAL devices have advantages over other semicustom chips in many areas (for instance, cost effectiveness, quick turnaround, complete software support, multi-source, etc.), it may be the best approach for the logic designer designing combinational/sequential circuits.
National offers the designer a family of PAL devices. See Table 7.5.1 for a broad· overview of National's products.
PAL Device Design Procedure
Designing combinational circuits is straightforward. The first step is to define the circuit's function. The second step is to build a truth table. The third step is to minimize the truth table by using Karnaugh maps or Boolean algebra, in order to get the transfer function (i.e., logic equations). Step four is programming the circuits. Figure 7.5.3 is a flow diagram which applies to designing combinational PAL devices.
It is much more complicated to design a sequential circuit, as discussed in many textbooks and articles. Figure 7.5.4 is a flow diagram which applies to designing sequential PAL devices.
The last step in both Figures 7.5.3 and 7.5.4 is programming the PAL device. The entire procedure for programming a PAL device is shown in Figure 7.5.5. The first step is to generate the logic equations and function table. The second step is, using PAL device software tools (e.g.,. PALASM®, PLANTM, .etc.), to create a bit pattern and exercise the function table, if any, in the logic equations. The third step is.to load the bit pattern into a PAL device programmer to program and verify the fuse matrix. The fourth step is to functionally test the PAL device. The last step is to blow the security fuse. This last step is optional.
Testing and Reliability 129
Standard
(35 ns) 10H8 12H6 14H4 16H2 10L8 12L6 14L4 16L2 16C1 16L8 16R8 16R6 16R4
(40 ns) 12L10 14L8 16L6 18L4 20L2 20C1
(50 ns) 20L10 20X10 20X8 20X4
High Speed (25 ns)
10H8A 12H6A 14H4A 16H2A 10L8A 12L6A 14L4A 16L2A 16C1A 16L8A 16R8A 16R6A 16R4A
20L8A 20R8A 20R6A 20R4A
Ultra-High Speed (15 ns)
16L88 16R88 16R6B 16R48
Low Power (35 ns)
10H8A2 12H6A2 14H4A2 16H2A2 10L8A2 12L6A2 14L4A2 16L2A2 16L1A2 16L8A2 16R8A2 16R6A2 16R4A2
Package (Pins)
20 20 20 20 20 20 20 20 20 20 20 20 20
24 24 24 24 24 24 24 24 24 24
24 24 24 24
Description
/
10 Input, 8 Output AND-OR Array 12 Input, 6 Output AND-OR Array 14 Input, 4 output AND-OR Array 16 Input, 4 Output AND-OR Array 10 Input, 8 Ouptut AND-OR Array 12 Input, 6 Output AND-OR Array 14 Input, 4 Output AND-OR Array 16 Input, 2 Output AND-OR Array 16 Input, 1 Output AND-OR/NOR Array 16 Input, 8 Output AND-OR-Inv Array 16 Input, 8 Output AND-OR-Reg Array 16 Input, 6 Output AND-OR Reg Array 16 Input, 4 Output AND-OR-Reg Array
12 Input, 10 Output AND-OR Array 14 Input, 8 Output AND-OR Array 16 Input, 6 Output AND-OR Array 18 Input, 4 Output AND-OR Array 20 Input, 2 Output AND-OR Array 20 Input, 1 Output AND-OR/NOR Array 20 Input, 8 Output AND-OR-Inv Array 20 Input, 8 Output AND-OR-Reg Array 20 Input, 6 Output AND-OR-Reg Array 20 Input, 4 Output AND-OR-Reg Array
20 Input, 10 Output AND-OR-Inv Array 20 Input, 10 Output AND-OR-XOR-Reg Array 20 Input, 8 Output AND-OR-XOR-Reg Array 20 Input, 4 Output AND-OR-XOR-Reg Array
Table 7.5.1 National's PAL Device Family
Description of Functional Table
In Figures 7.5.3, 7.5.4 and 7.5.5 we encounter a step called "generating function table." However, what is the meaning of a function table and why do we need it? A function table is a sequence of test conditions which are representative of the device in actual circuit operation. When we derive the logic equations by using Karnaugh maps or Boolean algebra, it is possible to introduce errors that may not be obvious. The function table is a means of expressing what we expect the PAL device to do in the system. PALASM or other software simulators will exercise the function table in the logic equations and report simulation errors. Then, we can correct the function table and/or the logic equations until no simulation error occurs.
130 Programmable Logic Design Guide
FUNCTION TABLE
FUNCTIONAL DESCRIPTION
.--------. DEFINE INPUTS - - - - - - AND OUTPUTS
TRUTH TABLE
KARNAUGH MAPS OR - - - - - - BOOLEAN ALGEBRA
TRANSFER FUNCTION
.(LOGIC
EQUATIONS)
CIRCUITS (PAL)
DEVICE
(PROGRAMMING THE PAL DEVICE)
Figure 7.5.3 Combinational PAL Device Design Steps
Even if both the logic equations and blown fuses are correct, there is no guarantee that the PAL device will function properly. PALASM or other software tools can generate test vectors from the function table entries and exercise these test vectors in the PAL device after it has been programmed. Even though the functional verification fallout is very small (typically less than 2% ), it is necessary to perform this test at the device level. Ten devices on a board with a 2% device fallout translates into 18% fallout at the board level if these devices are not individually tested.
Thus, we can see that a good function table will provide a high degree of confidence that the design is correct. It will also help ensure that the PAL device will work properly the first time it is plugged into the system.
Testing and Reliability 131
FUNCTIONAL DESCRIPTION
l
STATE DIAGRAM
I
STATE TABLE
1
MINIMIZING THE - - STATE TABLE
FUNCTION TABLE
MINIMAL STATE TABLE
I
_ _ STATE ASSIGNMENT ·
I+-
TRANSITION TABLE
J
TRANSFER FUNCTION
(LOGIC· EQUATIONS)
l
CIRCUITS (PAL)
DEVICE
_ _ KARNAUGH MAPS OR BOOLEAN ALGEBRA
- - (PROGRAMMING THE PAL DEVICE)
Figure 7 .5.4 Sequential PAL Device Design Steps
132 Programmable Logic Design Guide
ENTER LOGIC EQUATIONS
~-
ENTER FUNCTION TABLE
j_
CREATE BIT PATTERN
l
EXERCISE FUNCTION TABLE IN LOGIC EQUATIONS (~IMULATION)
I
LOAD PATTERN INTO PROGRAMMER
!
PROGRAM FUSE MATRIX
!
VERIFY FUSE MATRIX
I
TEST PAL DEVICE FUNCTION WITH TEST VECTORS OR DO
OTHER LOGIC TEST
!
BLOW SECURITY FUSE (DO FUNCTIONAL TESTING AGAIN)
Figure 7. 5.5 PAL Device Programming Procedures
Testing and Reliability 133
How to Generate Test Vectors and the Function Table from Logic Equations
It is the PAL device designer's responsibility to generate the function table since he/she knows the operation of the design best. However, if this is not possible, we can generate the function table manually from the existing logic equations. To do this, the correct logic equations are needed. Figure 7.5.6 outlines the procedure which will be detailed by examples in the next section. The "optimization" procedure is sometimes difficult and may need intuition. (Notice the diffe~ent procedure between combinational and sequential PAL in the last step.)
LOGIC EQUATIONS (KNOWN GOOD)
l
SAO TEST FOR EACH PRODUCT TERM SA1 TEST FOR EACH PRODUCT TERM SA1 FOR EACH PRODUCT EQUATION
l
- - - MINIMIZATION
TEST VECTORS
COMBINATIONAL PAL
~~
GENERATE STATE DIAGRAM AND · TRANSITION TABLE FOR STATE
SEQUENTIAL PAL
l
- - - OPTIMIZATION
L...+
FUNCTION TABLE
Figure 7.5.6 Test Vector and Function Table Creating Steps
134 Programmable Logic Design Guide
Before going to the next section, a few conventions are defined. First, only the following symbols can be accepted in the test vectors or function table:
H-Logic High L-Logic Low X-Irrelevant "Don't Care" Z-High Impedance C-Clock ?-Undetermined 0 and 1 can be treated as Low and High.
Second, let's consider a general logic equation (or product equation)
01 =Pl + P2 + P3
where 0 1 is the output; Pl, P2 and P3 are the product terms.
If Pl= Il * Iz * /I3 P2 = /I2 * I3 * Is P3 = I6 * /Is * /I9
where I1, Iz, I3, Is, I6, Is and I9 are inputs. Then the output 0 1 will be
01=11 * Iz * /I3 + /I2 * I3 * Is+ I6 * /Is * /19
where, Ii, I2, /I3, Is, I6, /Is, /I9 are called factors. Consider a particular test vector, VI, which will cause the product term Pl to be
high and the product terms P2 and P3 to be low. In this case the output, Oi, will be high. Now, if a fault is created by the PAL device which causes Pl to be low, then the output, 0 1, will be low which is different from the fault-free condition. This fault condition is called "stuck at O" (SAO) fault. Thus, the vector, VI, is able to detect the product term, Pl, for the SAO fault and we can say that VI covers Pl for the SAO fault.
In order to get Pl to be high, all factors of Pl should be high (i.e., Ii, I2 and /I3 are high). Both 12 =high and /I3 =high will cause P2 to be low no matter what Is is. Therefore, the vector of:
Il Iz I3 I4 Is 16 I7 Is I9 I10 In I12 01 02 03 04 Os 06 H H L XXL X XX X X X H X X X X X
will cover P1 for the SAO fault. Similarly, if there is another vector, V2, which causes Pl to be lowt (only one fac-
tor of P1 is low, the other factors of P1 are high) provided that P2 and P3 are low, then the output, Oi, is low. Now if a fault is created by the PAL device which causes Pl to be high then the output, Oi, will be high which is different from the fault-free condition.
t To talk about letting a product term which is under test be low means that we onlyforce onefactor ofthis term to be low and the other factors should remain high.
Testing and Reliability 135
This fault condition is called "stuck at l" (SAl) fault. Thus, the vector, V2, is able to detect the product term, Pl, for SAi fault and we can say that V2 covers Pl for SAi fault.
For example, if I1 is low, I2 and /I3 are high, the Pl is low. Therefore the vector of
Il I2 I3 I4 I5 I6 I7 Is I9 I10 In I12 01 02 03 04 05 06 LHLXXLXXXXXXLXXXXX
will cover Pl for the SAl fault. Similarly, the following vectors will cover Pl for the SAi fault, too.
Il I2 I3 I4 I5 I6 17 Is I9. Ilo Ill I12 01 02 03 04 05 06 HLLXXLXXXXXX L XX XX X HHHXXLXXXXXX L XX XX X
To get an SAl fault test for a product equation, generate a vector which sets all the factors in each product term to be low. The output of this product equation will then be low. If a fault is created by an AND or OR gate of the PAL d~vice which causes the product term to be high, then the output will be high, which is different from the faultfree condition. For example, if Il, I2, /I3, I5, I6, /Is, /I9 are low, then the following vector will cover equation 0 1 for an SAl fault.
Il I2 I3 I4 Is 16 I7 Is I9 Ilo Ill I12 01 02 03 04 05 06 LLHXLLXHHXXX L XX XX X
A good function table should cover all of the product terms for the SAO and SA 1 faults. The Product Term Coverage (PTC) is calculated as:
·PTC = Total # of SAO Faults Tested + Total # of SA 1 Faults Tested x 100 (%)
2 x Total Number of Product Terms
To achieve 100% PTC is the goal of generating a function table. PALASM version 1. 5 and up will inform the user of:
· Total number of SAI faults tested
· Total number of SAO faults tested
· Product term coverage (PTC)
In case all the product terms are not covered,· the user receives a message which tells him the product term and the type of fault for which it was not tested (e.g., "Product P2 of EQN 1 Untested (SAO) Fault"). This implies that the user must update the function table by including vectors which will cover product terms for the faults.
136 Programmable Logic Design Guide
7.6 EXAMPLES OF TESTING
Example 1: Combinational PAL12H6
PAL12H6 PTAN301 Tom Wang Portion of random control logic for 8086 CPU board
PD EN ED EA S1 SA E1 DO DE GND SO NC3 NO C3 HA SS LA MW PW VCC
MW = ISO + PW * DE
(1)
LA= /SA * /DO
(2).
SS = S1 * PD * /SA
(3)
HA = S1 * PD * /SA * EA * E1
(4)
C3 = PD * ED * EA
(5)
NO= PD* /EN
Description
This is a portion of random control logic for 8086 CPU board. See (Figure 7.5.7).
:: ---cill""""""""""'),_--...---->-CD------ MW
so------
PD - - - 1 ~-o-------+-......;.--....-., ~------NO
HA
SI -----------+----1.-~IO-....,._.,. ~-<>--- SS
LA
Figure 7. 5.7 Logic Circuit of Example 1
Testing and Reliability 137
The generation of function table is described in the following steps:
Step 1: Get Test Vector Coding Form; Fill in the input and output names.
Step 2:
Exercise the product term 1 (/SO) of equation 1. SAO Fault Testing: Let PTl be high and PT2 be low, then the output of equa-
tion 1, MW, should be high; so, we get vector 1. SAl Fault Testing: Let PTl and PT2 be low, then the output of equation 1, MW
should be low; so we get vector 2.
Step 3: Exercise product term 2 (PW * DE) of equation 1.
SAO Fault Testing: Let PTl be low and PT2 be high, then the output of equation 1, MW, should be high (i.e., vector 3).
SAl Fault Testing: Let PTl and PT2 be low, then the output of equation 1, MW, should be low.
Since PT2 consists of two factors, PW and DE, we create two SAl test vectors (i.e., vectors 4 and 5).
Step 4:
SAl Fault Testing for product equation 1. Let PTl and PT2 be low, then the output of equation 1, MW, should be low (i.e., vector 6). This step is similar to the SAl test in step 3 but is different, since all the factors in this equation were set to be low.
Step 5:
Exercise product term 1 (/SA * /DO) of equation 2.
SAO Fault Testing: Let PTl be high, then the output LA should be high. SAl Fault Testing: Let PTl be low, then the output LA should be _low. So, we get vectors 7, 8, and 9 in Table 7.5.2
Step 6: SAl fault test for product equation 2, we get vector 10.
Step 7: Continue to exercise the rest of the product terms, completing all 31 test vectors (Table 7.5.2).
Step 8: Optimize the test vectors to get the function table. 1) Because of vector 2, we don't need vectors 4 and 6.
2) Combine vectors 7-10 with vectors 1-6.
3) Rearrange vectors 11-15, then combine with the preceding vectors.
4) Merge vectors 28-31 with vectors 23-27.
5) This results in only 17 vectors (Table 7.5.3).
6) These 17 vectors can still be minimized by comparison and intuition to get only 7 vectors (Table 7.5 .4).
7) By inserting "X" into unused spaces, the result is Table 7.5.S, which is the function table.
138 Programmable Logic Design Guide
Inputs
so PD EN ED EA SI SA El DO DE
NC3 PW
1
x L
L
2
x H
L
3
H H
H
4
H H
L
5
L H
H
6
L H
L
7
L
L
8
H
L
9
L
H
10
H
H
11 H
H L
12 H
L L:
13 L
H L
14 H
H H
15 L
L H
16 H
HH L H
17 H
HL L H
18 L
HH L H
19 H
HH H H
20 H
LH L H
21 H
HH L L
22 L
LL H L
23 H
H H
24 L
H H
25 H
L H
26 H
H L
27 L
L L
28 H L
29 L L
30 H H
31 L H
Outputs NO C3 HA SS LA MW
H L H L L L H L L L
H L L L H L L L L L L H L L L L H L L L
Table 7.5.2 Test Vectors
Testing and Reliability 139
Inputs
PD EN ED EA SI SA El DO DE so NC3 PW
1 H
H L
L xL
L
2 H
H H
L xH
L
3 H
L L
H H H
H
4 L
L H
H L H
H
5 L
H L
6 H
HH L H
7 H
HL L H
8 L
HH L H
9 H
HH H H
10 H
LHL H
11 H
HH L L
12 L
LL HL
13 H L H H
14 L L H H
15 H H L H
16 H
H L
17 L H L L
Outputs
NO C3 HA SS LA MW
HH H LL L L L H LL L L H L L L L L L H H L L L L L L L
Table 7.5.3 Test Vectors
Inputs
PD EN ED EA SI SA El DO DE so NC3 PW
1H L H HH L H L x L
L
2 H H L HH H H L x H
L
3 H
HL L HH HH
H
4LHL LLHL HL H
H
5 L L H HH L H
6 H
HLHL H
7 H
HH L L
Outputs
NO C3 HA SS LA MW
H H H HH H L L L LL L
L LLH L L L LL L L L L L
L L L
Table 7.5.4 Final Test Vectors
140 Programmable Logic Design Guide
Inputs
PD EN ED EA SI SA El DO DE so NC3 PW
1H L H H H L H L x L x L
2H H L H H HH L x H x L
3HxxH L LHHH H x H
x 4 L H L L L H L H L H
H
5L L H H H LHx xx x x
6HxH L H L Hx xx x x
7HxxHH L L xxx x x
Outputs
NO C3 HA SS LA MW
HHHHH H
LLLLL L
xxL L L H
LLLLL L
L L L Lxx x L L xx x xxL xx x
Table 7. 5. 5 Final Function Table
The following are printouts of PAL device design specifications, function table, pinout list, fuse map, simulation result,, and fault testing result. We get 100 % PTC!
PALASM VERSION 1. 5
PAL12H6 PTANJOl TOM WANG PORTION OF RANDOM CONTROL LOGIC FOR 8086 CPU BOARD PD EN ED EA Sl SA El DO DE GND SO NCJ NO CJ HA SS LA MW PW VCC MW = /SO + PW*DE
LA = /SA*/DO
SS = Sl*PD*/SA
HA = Sl*PD*/SA*EA*El CJ = FD*ED*EA NO = PD*/EN
FUNCTION TABLE PD EN ED EA Sl SA El DO DE SO NCJ PW NO CJ HA SS LA MW
H L H H H L H L X LX L H H H H H H HHLHHHHLXHXLLLLLLL HXXHLLHHHHXHXXLLLH LHLLLHLHLHXHLLLLLL LLHHHLHXXXXXLLLLXX H X H L H L H X X X X X X L L. X X X HXXHHLLXXXXXXXLXXX
DESCRIPTION PORTION OF RANDOM CONTROL LOGIC FOR 8086 CPU BOARD
Testing and Reliability 141
TOM WANG
************** **************
*
* *
*
**** PO * l*
P A L
****
*20* vcc
****
****
·* **** EN * 2* ****
1 2 H6
*
....****
*19* PW
*
*
****
****
ED * 3*
*18* MW
****
****
*
....****
EA * 4*
* **** *17* LA ****
*
*
****
****
Sl * 5*
*16* SS
****
****
*
*
****
****
SA ·*··6·*
*15* HA ****
*
*
**** El * 7*
****
*14* CJ
**** *
·* ·~·
****
****
DO * 8*
*13* NO
****
****
*
****
****
DE * 9*
*12* NC3
****
****
*
*
**** GND *10*
****
*11* so
****
****
*
*
*******************************
TOM WANG
1 101llOlOXXOXHHHHHHO1 2 llOllllOXXlXLLLLLLOl 3 lXXlOOlllXlXXXLLLHll
4 Ol0001010XlXLLLLLLl 1 5 OOlllOlXXXXXLLLLXXXl 6 1Xl0101XXXXXXLLXXXX1
7 lXXllOOXXXXXXXLXXXXl
PASS SIMULATION
49
8
TOM WANG
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*f PLT PAL12H6 8 0 0000 0000 0000 0000 0000 0000 0000 0000 1 0000 0000 0000 0000 0000 0000 0000 0000 2 0000 0000 0000 0000 0000 0000 0000 0000 3 0000 0000 0000 0000 0000 0000 0000 0000 4 0000 0000 0000 0000 0000 0000 0000 0000 5 0000 0000 0000 0000 0000 0000 0000 0000 6 0000 0000 0000 0000 0000 0000 0000 0000 7 0000 0000 0000 0000 0000 0000 0000 0000
8 ---- ---- --00 --00 --00 --00 ---- ---X /SO 9 ---- --X- -:-00 --00 --00 --00 ---- X--- PW*OE
10 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx 11 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx
12 0000 0000 0000 0000 0000 0000 0000 0000 13 0000 0000 0000 0000 0000 0000 0000 0000 14 0000 0000 0000 0000 0000 0000 0000 0000 15 00~0 0000 0000 0000 0000 0000 0000 0000
16 ---- --:-- --00 --00 -XOO --00 -X-- ---- /SA*/00
17 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx
18 0000 0000 0000 0000 0000 0000 0000 0000 19 0000 0000 0000 0000 0000 0000 0000 0000 20 0000 0000 0000 0000 0000 0000 0000 0000 21 0000 0000 0000 0000 0000 0000 0000 0000 22 0000 0000 0000 0000 0000 0000 0000 0000 23 0000 0000 0000 0000 0000 0000 0000 0000
24 --X- ---- --00 X-00 -XOO --00 ---- ---- Sl*PD*/SA
25 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx
26 0000 0000 0000 0000 0000 0000 0000 0000 27 0000 0000 0000 0000 0000 0000 0000 0000 28 0000 0000 0000 0000 0000 0000 0000 0000 29 0000 0000 0000 0000 0000 0000 0000 0000 30 0000 0000 0000 0000 0000 0000 0000 0000 31 0000 0000 0000 0000 0000 0000 0000 0000
142 Programmable Logic Design Guide
32 --X- ---- X-00 X-00 -XOO X-00 ---- ---- Sl*PO*/SA*EA*El
33 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx
34 0000 0000 0000 0000 0000 0000 0000 0000 35 0000 0000 0000 0000 0000 0000 0000 0000 36 0000 0000 0000 0000 0000 0000 0000 0000 37 0000 0000 0000 0000 0000 0000 0000 0000 38 0000 0000 0000 0000 0000 0000 0000 0000 39 0000 0000 0000 0000 0000 0000 0000 0000
40 --X- X--- X-00 --00 --00 --00 ---- ---- PO*EO*EA
41 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx
42 0000 0000 0000 0000 0000 0000 0000 0000 43 0000 0000 0000 0000 0000 0000 0000 0000 44 0000 0000 0000 0000 0000 0000 0000 0000 45 0000 0000 0000 0000 0000 0000 0000 0000 46 0000 0000 0000 0000 0000 0000 0000 0000 47 0000 0000 0000 0000 0000 0000 0000 0000
48 -XX- ---- --00 --00 --00 --00 ---- ---- PO*/EN
49 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx ' 50 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx 51 xxxx xxxx xxoo xxoo xxoo xxoo xxxx xxxx
52 0000 0000 0000 0000 0000 0000 0000 0000 53 0000 0000 0000 0000 0000 0000 0000 0000 54 0000 0000 0000 0000 0000 0000 0000 0000 55 0000 0000 0000 0000 0000 0000 0000 0000
56 0000 0000 0000 0000 0000 0000 0000 0000 57 0000 0000 0000 0000 0000 0000 0000 0000 58 0000 0000 0000 0000 0000 0000 0000 0000 59 0000 0000 0000 0000 0000 0000 0000 0000 60 0000 0000 0000 0000 0000 0000 0000 0000 61 0000 0000 0000 0000 0000 0000 0000 0000 62 0000 0000 0000 0000 0000 0000 0000 0000 63 0000 0000 0000 0000 0000 0000 0000 0000
ENO*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O) 0 : PHANTOM FUSE (L,N,0)
NUMBER OF FUSES BLOWN = 206
FUSE BLOWN (H,P,l) 0 : PHANTOM FUSE (H,P,l)
TOM WANG
1 101 llOlOXXOXHHHHHHOl 2 llOllllOXXlXLLLLLLOl 3 lXXlOOlllXlXXXLLLHll 4 OlOOOlOlOXlXLLLLLLll 5 0011 lOlXXXXXLLLLXXXl 6 1Xl0101XXXXXXLLXXXX1 7 lXXllOOXXXXXXXLXXXXl
PASS SIMULATION
49
8
NUMBER OF STUCK AT ONE (SAl) FAULTS ARE =
NUMBER OF STUCK AT ZERO (SAO) FAUL TS ARE = 7
PRODUCT TERM COVERAGE
=lOOi
Testing and Reliability 143
The differences between sequential and combinational circuits have been discussed. The output of sequential circuits is a function not only of the present inputs, but the previous outputs.
There are two kinds of outputs in the sequential PAL device: registered output, and non-registered output. For example, pin 14 of the PAL16R4 is a registered output; pin I3 is a non-registered output. Different combinations of registered outputs are defined as different states. Each present-state is related to the present inputs and previous state, so the function table vectors need to be arranged in proper sequential order.
Furthermore, since the previous state is obtained from the previous vector, it is necessary to "initialize" the registers to a "known state". (Output is a function of the inputs but is independent of the previous state, similar to a clear or preset function) .
. The following is an example of the sequential PAL16R4. Referring to Figure 7.5.6, generate the state diagram and state transition table to derive the proper function table.
Example 2: Sequential PAL16R4
PAL16R4 PTAN302 Tom Wang Op code analyzer
CLK /2BI2 /2B23 /B2Bl /B2B3 /3B /B3B /BIB GND /EN FIST /ILLOP
IC IB IA 117 /RD F23 VCC
If (VCC) /FIST= F23
If (VCC) ILLOP =IA * /B * IC
; (I) ; (2)
C: = A * /B * IC * /B3 B + IA * /B * C * /B2 B2 + RD + A * B * C * /BIB + A * /B * C *
/B2B3 * /3B + IA * B * /B2BI
; (3)
B: =A * /B * IC * /B3B +IA * /B *. C * /B2B2 +RD+ A * B * C * /BIB * /2B23 +
A * /B * C * /B2B3 +IA * B * /B2BI
; (4)
A:= A * /B * IC * /B3B +IA * /B * C * /B2B2 +RD+ A * B * C * /BIB * /2B12 +
A * /B * C * /B2B3 +IA * B * /B2BI + B * IC
(5)
17: =A * B * C
(6)
If (VCC) /F23 =IA * /B * IC+ A * B * C
(7)
Description
The function of this PAL device is to analyze the incoming op code. The generation of the function table is described in the following steps:
Step 1:
Get test vector coding form. Fill in the input and output names. Since the outputs C, B and A act as inputs as well, they appear on both sides and are considered first because they feed back to themselves. Therefore, equations 3, 4, and 5 are exercised first.
144 Programmable Logic Design Guide
Step 2:
Step 3:
Step 4: Step 5: Step 6: Step 7:
Step 8:
Exercise product term I of equation 3.
SAO Fault Testing: Let PTI (A * /B * IC* /B3B) be high and PT2, 3, 4, 5, and
6 be low; the output of equation 3 should be high; so, we get vector I in Table 7.5.6. SAI Fault Testing: Let PTI, 2, 3, 4, 5, and 6 be low; the output of equation 3 should be low; so, we get vectors 2, 3, 4, and 5 in Table 7.5.6.
Exercise product term 2 of equation 3. SAO Fault Testing: Let PT2 be high and PTI, 3, 4, 5, and 6 be low; the output
of equation 3 should be high; so, we get vector 6 in Table 7.5.6. SAI Fault Testing: Let PTI 2, 3, 4, 5, and 6 be low; the output of equation 3 should be low; so, we get vectors 7, 8, 9, and 10 in Table 7.5.6.
Exercise product term 3 of equation 3 (only SAO fault ,testing is needed). SAO Fault Testing: Let PT3 be high and PTI, 2, 4, 5, and 6 be low; the output
of equation 3 should be high; so, we get vector 11 in Table 7.5.6.
Continue to exercise the rest of the product terms, completing all of equation 3.
SAI fault test for product equation 3; so, we get vector 25.
Repeat step 2 through step 6 for equation 4; i.e., SAO Fault Testing: Let PTI be high and PT2, 3, 4, 5, and 6 be low; the output of equation 4 should be high. SAI Fault Testing: Let PTI, 2, 3, 4, 5, and 6 of equation 4 be low, the output of equation 4 should be low. SAO Fault Testing for PT2, SAI Fault Testing for PT2. SAO Fault Testing for PT3, SA I Fault Testing for PT3. SAO Fault Testing for PT4, SAI Fault Testing for PT4. SAO Fault Testing for PT5, SAI Fault Testing for PTS. SAO Fault Testing for PT6, SAI Fault Testing for PT6. SAO Fault Testing for equation 4. So, we get vectors 26 to 50.
Repeat step 2 through step 6 for equation 5: i.e., SAO Fault Testing: Let PTI be high and PT2, 3, 4, 5, 6, and 7 be low; the output of equation 5 should be high. SAI Fault Testing: Let PTI, 2, 3, 4, 5, 6, and 7 of equation 5 be low; the output of equation 5 should be low. SAO Fault Testing for PT2, SAI Fault Testing for PT2. SAO Fault Testing for PT3, SAI Fault Testing for PT3. SAO Fault Testing for PT4, SAI Fault Testing for PT4.
Testing and Reliability 145
Inputs
CLK 2812 2823 8281 8282 8283 38 838 818 EN c 8 A RD
1
L
L LH L
2
L
LLL L
3
L
LHH L
4
L
HLH L
5
H
L LH L
6
L
HL L L
7
L
HLH L
8
L
HHL L
9
L
LLL L
10
H
HL L L
11
H
12
L
HHH L
13
L
HHL L
14
L
HLH L
15
L
L HH L
16
H
HHH L
17
L L
HLH L
18
L L
HL L L
19 20
L L L L
-
HHH L L LH L
21
L H
HLH L
22
H L
HLH L
23
L
HL L
24
H
HL L
25
H H H HH H
HHL L
26
L
LLH L
27
L
LLL L
28
L
L HH L
29
L
HLH L
30
H
L LH L
31
L
HL L L
32
L
HLH L
33
L
HHL L
34
L
LLL L
35
H
HL L L
37
H
37
L
L
HHH L
38
L
L
HHL L
39
L
L
HLH L
Outputs RIST ILLOP C 8 A 17 F23
H L L L L H L L L L H H L L L L H L L L L L H L L
H L L L L H L L L L H H L L
Table 7.5.6 Test Vectors
146 Programmable Logic Design Guide
Inputs
c CLK 2812 2823 8281 8282 8283 38 838 818 EN 8 A RD
40
L
L
L HH L
41
L
H
HHH L
42
H
L
HHH L
43
L
HLH L
44
L
HLL L
45
L
HHH L
46
L
LLH L
47
H
HLH L
48
L
HL L
49
H
HL L
50
HHH H
H H
HH L L
51
L
LLH L
52
L
LLL L
53
L
HLH L
54
H
LLH L
55
L
HLL L
56
L
HLH L
57
L
HHL L
58
L
LLL L
59
H
HLL L
60
H
61
L
L
HHH L
62
L
L
HHL L
63
L
L
HLH L
64
L
H
HHH L
65
H
L
HHH L
66
L
HLH L
67
L
HLL L
68
L
HHH L
69
L
LLH L
70
H
HLH L
71
L
HL L
72
H
HL L
73
LH L
74
H
HH H
H H
HHL L
Outputs RIST ILLOP C 8 A 17 F23
L L L H L L L L H L L
H L L L H L L L L H H L L L L H L L L L H L H L
Table 7 .5.6 Test Vectors Continued
Testing and Reliability 147
SAO Fault Testing for PTS, SA I Fault Testing for PTS. SAO Fault Testing for PT6, SA I Fault Testing for PT6. SAO Fault Testing for equation 5. So, we get vectors 51 to 74.
Step 9: Minimize the vectors following these rules: 1) Vectors which have same inputs can be combined to be one vector.
2) If the inputs of a vector are subsets of another vector's inputs, then they can be combined to form one vector.
So, vectors 1, 26, and 51 can be combined to one vector 1 in Table 7.5.7; vectors 12 and 37 can be combined to one vector 21 in Table 7.5.7, etc.
3) Decide the"?" (undetermined) state in the output by using the inputs and logic equations (inserting the known values into logic equations).
Therefore, we get Table 7.5.8.
Step 10: Assign the state numbers. See Table ·7.5.9, then we get Table 7.5.10.
Step 11: Build the state diagram and transition path (Figure 7.5.8) from the vector Table 7.5.10.
Step 12:
Generate the function table from the state diagram. I) Be aware of two rules:
a) Generate the initial state first. b) Generate the function table in sequential order and cover all possible paths.
2) The value of outputs Fl ST, ILLOP, 17 and F23 in each test vector can be derived easily by inserting the previous values of outputs C, B, and A and the present values of inputs (none in this example) into their corresponding logic equations.
3) We can quickly identify that the RD signal in this example is the initialize or reset signal, so RD is set high as the first vector in the function table.
4) Finally, insert an "X" into the unused space. We get the function table as shown in Table 7.5.11.
148 Programmable Logic Design Guide
Inputs
CLK 2812 2823 8281 8282 8283 38 838 818 EN C 8 A RD
1
L
LLH L
2
L
LLL L
3
L
L HH L
4
L
HLH L
5
H
LLH L
6
L
HLL L
7
L
HLH L
8
L
HHL L
9
L
LLL L
10
H
11
HLL L
xxx H
12
L L
HLH L
13
L L
HLL L
14
L L
HHH L
15
L L
L L H .L
16
L H
HLH L
17
H L
HLH L
18
L
x H L .L
19
H
xH L L
20
H H H H H HH H
HH L L
21
L
L
HHH L
22
L
L
HHL L
23
L
L
HLH L
24·
L
L
LHH L
25
L
H
HHH L
26
H
L
HHH L
27
L
L
HHH L
28
L
L
HHL L
29
L
30
L
L
HLH L
H
H HH L
31
H
L
HHH L
32
LHX L
Outputs RIST ILLOP C 8 A 17 F23
H H H L L L L LH L L L L L L H H H L L L L L L L L L L L L H H H H H H L L L L L L L L L L L L L L L H H H L L L L L L HH ? L L ? L L ? L L ? L L ? HL ? H? H L? L L? L L? L .H ? L ? ?H
Table 7. 5.7 Test Vectors
Testing and Reliability 149
Inputs
c CLK 2812 2823 8281 8282 8283 38 838 818 EN 8 A RD
1
L
L LH L
2
L
LLL L
3
L
I. H H L
4
L
HLH L
5
H
LLH L
6
L
HL L L
7
L
HLH L
8
L
HHL L
9
L
LLL L
10
H
HLL L
11
H
12
L L
HLH L
13
L L
HLL L
14
L L
HHH L
15
L L
L LH L
16
L H
HLH L
17
H L
HLH L
18
L
xH L L
19
H
xH L L
20
H H H H H HH H
HH L L
21
L L
L
HHH L
22
H L
L
HHH L
23
L
L
HH L L
24
L
L
L
HLH L
25
L
H
L
HLH L
26
L L
L
L HH L
27
L H
L
LHH L
28
L
H
HHH L
29
L H
30
'H .H
L
HHH L
L
HHH L
31
L L
L
HHH L
32
L H
L
HHH L
33
L
L
L
HHL L
34
L
L
HLH L
35
L
H
L
HLH L
36
L
H
H H H
37
H L
L
H H· H
38
H H
L
H H H
39
40
H
L H H
L Hx
41
L
L H L
Outputs RIST ILLOP C 8 A 17 F23
HH H L L L L L H L L L L L L HH H L L L L L L L L L L L L HH H HH H L L L L L L L L L L L L L L L HH H L L L L L L HH H HH L L L L L L H L L L L L H L L L L L L H L H HL L H H H H L H L L L LH L L L L L L L HH L HL L L LH L LH H H H
Table 7.5.8 Test Vectors
150 Programmable Logic Design Guide
c
B
A
State#
H
H
H
1
H
H
L
2
L
L
L
3
H
L
L
4
H
L
H
5
L
H
H
6
L
L
H
7
L
H
L
8
Table 7. 5.9 State Assignment
Inputs
c CLK 2812 2823 8281 8282 8283 38 838 B1B EN
B
A RD
1 c
L
H 7
7
7 L
2 c
L
H 3
3
3 L
3 c
L
H 6
6
6 L
4 c
L
H 5
5
5 L
5 c
H
H 7
7
7 L
6 c
L
H 4
4
4 L
7 c
L
H 5
5
5 L
8 c
L
H 2
2
2 L
9 c
L
H 3
3
3 L
10 c
H
H 4
4
4 L
11 c
H
H
12 c
L L
H 5
5
5 L
13 c
L L
H 4
4
4 L
14 c
L L
H 1
1
1 L
15 c
L L
H 7
7
7 L
16 c
L H
H 5
5
5 L
17 c
H L
H 5
5
5 L
18 c
L
H 2 or 8 2 or 8 2 or 8 L
19 c
H
H 2 or 8 2 or 8 2 or 8 L
c 20
H H H H H HH HH 2
2
2 L
21 c L L
LH 1
1
1 L
22 c H L
LH 1
1
1 L
23 c
L
LH 2
2
2 L
24 c
L
L
L H ,5
5
5 L
25 c
L
H
LH 5
5
5 L
26 c
L L
LH 6
6
6 L
27 c
L H
LH 6
6
6 L
28 c
L
HH 1
1
1 L
Outputs RIST ILLOP C B A 17 F23
1 1 1 3 3 3 7 7 7 3 3 3 3 3 3 1 1 1 3 3 3 3 3 3 3 3 3 33 3 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 1 1 3 3 3 3 3 3 1 1 1 2 2 2 3 3 3 7 7 7 3 3 3 7 7 7 3 3 3 3 3 3
Table 7 .5.10 Transition Table
Testing and Reliability 151
Inputs
c CLK 2812 2823 8281 8282 8283 38 838 818 EN
8
A RD
29 c L H
LH 1
1
1 L
30 c H H
LH 1
1
1 L
31 c L L
LH 1
1
1 L
32 c L H
LH 1
1
1 L
33 c L
LH 2
2
2 L
34 c L
L
LH 5
5
5 L
35 c L
H
LH 5
5
5 L
36 c L
HH 1
1
1 L
37 c H L
LH 1
1
1 L
38 c H H
LH 1
1
1 L
39 c
H 6
6
6 L
40 c
H
H 8 or 6 8 or 6 8 or 6 L
41 c
L
H 8
8
8 L
42 c
L
L
Outputs RIST ILLOP C 8 A 17 F23
5 55 4 44 1 11 5 55 3 33 8 8 8 3 33 3 33 2 2 2 4 44 7 77 7 77 1 1 1
zzz
Table 7.5.iO Transition Table Continued
FUNCTION TABLE CLK /2812 /2823 /8281 /8282 /8283 /38 /838 /818 /EH FlST /ILLOP /C /B /A /17 /RD F23 CXXXXXXXXL HHL L L L L L CLHXXXXXHL LHL LHl HH CXXHXXXXXL HHL L L HHL C LHXXXXXHL L H L L HL HH CXXLXXXXXLHL HHHHHL CXXXXXXXXL HHL L L HL L C L L XXXXXHL L HL HHL HH CXXXHXXXXL HHL L L HHL Cl L XXXXXHL L HL HHL HH CXXXLXXXXL HLHHHHHL CXXXXXXXXL HHL L l HL L CHLXXXXXHL LHLHL LHH CXXXXHHXXL HHL L L HHL CHLXXXXXHL LHLHL LHH C XXXXL XXXL HL HHHHHL CXXXXXXXXL HH L L L HL L CHLXXXXXHL LHLHL LHH CXXXXHL XXL L HHL L HHH CXXXXXXXXL L HHHL HHH CXXXXXXL XL HL HHHHHL CXXXXXXXXL HHL L L HL L CHl XXXXXHL LHL HL LHH CXXXXHL XX L L HH L L HHH C XXXXXXXXL L HHHL HHH C XXXXXXHXL HHL L L HHL CXXXXXXXL L HLHHHLHL C XXXXXXXXL HHL L L HL L CHHXXXXXH L HHL L L L L L DESCRIPTION OP CODE ANALYZER
Table 7.5.11 Final Function Table
152 Programmable Logic Design Guide
Now we can get any test sequence we like just by following the state transition. The first vector should be the initialize vector and, by intuition,
we know state <D is the initialize state. Figure 7.5.8 State Diagram
The following are printouts of PAL device design specifications, function table, pinout list, fuse map, simulation result, and fault testing result. We get 100% PTC!
PALASM VERSION 1.5 PAL16R4 PTAN302 TOM WANG OP CODE ANALYZER CLK /2812 /2823 /8281 /8282 /8283 /38 /838 /818 GND /EN FlST /ILLOP /C /8 /A /17 /RD F23 VCC IF (VCC)/FlST · F23 IF (VCC)ILLOP · /A*/8*/C C:·A*/8*/C*/838 + /A*/8*C*/8282 + RD + A*8*C*/818 + A*/8*C*/8283*/38 + /A*8*/8281 8:·A*/8*/C*/838 + /A*/8*C*/8282 + RD + A*8*C*/818*/2823 + A*/8*C*/8283 + /A*8*/8281 A:·A*/B*/C*/838 + /A*/8*C*/8282 + RD + A*8*C*/818*/2812 + A*/8*C*/8283 + /A*8*/8281 + 8*/C 17:· A*8*C IF{VCC)/F23 =/A*/B*/C + A*8*C
Testing and Reliability 153
TOM WANG
CLK /2612 /2623 /6261 /B2B2 /B2B3
/3B /63B /616 GND
************** **************
*
* *
*
****
****
* l*
P A L
*20*
****
****
*
1 6 R4
*
****
****
* 2*
*19*
****
****
*
*·
****
****
* 3*
*18*
****
****
*
*
****
****
* 4*
*17*
****
****
*
*
****
****
* 5*
*16*
****
****
*
*
****
****
* 6*
'*15*
****
****
*
*
****
****
* 7*
*14*
****
****
*
*
****
****
* 8*
*13*
****
****
*
*
****
****
* 9*
*12*
****
****
*
*
****
****
*10*
*11*
****
****
*
*
*******************************
vcc
F2J /RD /17 /A /B /C /ILLOP Fl ST /EN
TOM WANG
1 CXXXXXXXXXOHHLLLLOLl 2 COlXXXXXlXOLHLLHLlHl 3 CXXlXXXXXXOHHLLLHlll 4 COlXXXXXlXOLHLLHLlHl 5 CXXOXXXXXXOHLHHHHlll 6 CXXXXXXXXXOHHLLLHOLl
7 COOXXXXXlXOLHLHHLlHl 8 CXXXlXXXXXOHHLLLHlll 9 COOXXXXXlXOLHLHHLlHl 10 CXXXOXXXXXOHLHHHHlll 11 CXXXXXXXXXOHHLLLHOLl 12 ClOXXXXXlXOLHLHLLlHl 13 CXXXXllXXXOHHLLLHlll 14 ClOXXXXXlXOLHLHLLlHl 15 CXXXXOXXXXOHLHHHHlll 16 CXXXXXXXXXOHHLLLHOLl
154 Programmable Logic Design Guide
17 ClOXXXXXlXOLHLHLLlHl 18 CXXXXlOXXXOLHHLLHlHl 19 CXXXXXXXXXOLHHHLHlHl 20 CXXXXXXOXXOHLHHHHlll 21 CXXXXXXXXXOHHLLLHOLl 22 ClOXXXXXlXOLHLHLLlHl 23 CXXXXlOXXXOLHHLLHlHl 24 CXXXXXXXXXOLHHHLHlHl 25 CXXXXXXlXXOHHLLLHlll 26 CXXXXXXXOXOHLHHHLlll 27 CXXXXXXXXXOHHLLLHOLl 28 CllXXXXXlXOHHLLLLOLl
PASS SIMULATION
672
TOM WANG
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
8EG*FPLT PAL16R4 8
0 ---- ---- ---- ---- --~- ---- ---- ----
1 ----
2 3
x-x-x-x-
---x-x-x-x-
---x-x-x-x-
--X-
x--x-xXx
--X-
x--x-xXx
--X-
x--x-xXx
----
x-x-x-x-
----
x-x-x-x-
A/A*8**/C8*/C
4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
67 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
1980 xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx 11 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 12 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1134 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 15 xxxx xxxx xxxx xxxx·xxxx xxxx xxxx xxxx
1176 x--x-x-x x-x--x-x x-x--x-x x--x-xXx x--x-xXx x--x-xXx x-x-x-x- x-x-x-x- A*8*C 18 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 19 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 2210 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 22·xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 23 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
24 ---- ---- ---- ---X --X- --X- X--- ---- A*/8*/C*/838
25 ---- ---- ---- X-X- ~-x- ---X ---- ---- /A*/8*C*/8282
2276
----
X---
---X ----
-------
~---
---X
------X
------X
-------
---X---
ARD*8*C*/818*/2812
28 ---- ---- ---- ---X X-X- ---X ---- ---- A*/8*C*/8283
29 ---- ---- X--- --X- ---X ---- ---- ---- /A*8*/8281
3310 x-x--x-x -x-x-x-x x-x--x-x x-x-x--x x--x-xXx x--xXxx- x-x-x-x- x-x-x-x- 8*/C
32 ---- ---- ---- ---X --~- --X- X--- ---- A*/8*/C*/838
33 ---- ---- ---- X-X- --X- ---X ---, ·--- /A*/8*C*/8282
34 ---- ---X ---- ---- ---- ---- --·- ---- RD
35 36
-------
X-------
--------
---X ---X
---X
X-X-
---X ---X
-------
X---
--~-
A*8*C*/818*/2823 A*/8*C*/8283
3378 -xx-x-x- -xx-x-x- xXx-x-x- x--xXxx- x--x-xXx x-x-x--x x~x-x-x- x-x-x--x /A*8*/8281
39 xxxx xxxx xxxx xxxx xxxx xxx~ xxxx xxxx
Testing and Reliability 155
40 41 42
----------
----
------x-
----
--------
x----xx-
------xx----
-------x-x--
x--·
----------
A*/8*/C*/838 /A*/B*C*/8282 RO
43 44
-------
-------
-------
------xx
x----xx-
x-----xx
--------
X------
A*B*C*/B.18 A*/B*C*/8283*/38
45 46 47
-xx-x-xxxxx
x-x-x-xxxxx
xxx-x-xxxxx
x--xxxxxxxx
x--x-xxx xxxx
x-x-x--x xxxx
x-x-x--x xxxx
xxxx xxxx
/A*B*/8281
48 ---- ---- ---- ---- ---- ---- ----
49 50
x-x-x-x-
x-x-x-x-
x-x-x-x-
x--xXxx-
x--xXxx-
x--xXxx-
x-x-x-x-
xxxx
/A*/8*/C
51 52
xxxxxxxx
xxxxxxxx
xxxxxxxx ·
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
53 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
54 55
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
56 ---- ---- ---- ---- ---- ---- ---- ----
57 58
x--xXxx-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
-xx-x-x-
F23
59 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
60 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
61 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
62 63
xXxXxXxX
xXxXxXxX
xXxXxXxX
JxXxXxXx
xXxXxXxX
xXxXxXxX
xXxXxXxX
xXxXxXxX
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,0)
FUSE BLOWN (H,P,l)
NUMBER OF FUSES BLOWN = 786
TOM WANG
FILE: PTAN302 FUSEPLOT A <« NATIONAL SEMICONDUCTOR TIMESHARING SERVICES SYST
1 CXXXXXXXXXOHHLLLLOLl 2 COlXXXXXlXOLHLLHLlHl 3 CXXlXXXXXXOHHLLLHlll 4 COlXXXXXlXOLHLLHLlHl 5 CXXOXXXXXXOHLHHHHlLl 6 CXXXXXXXXXOHHLLLHOLl 7 COOXXXXX lXOLHLHHLlH 1 8 CXXXlXXXXXOHHLLLHlll 9 COOXXXXXlXOLHLHHLlHl 10 CXXXOXXXXXOHLHHHHlll 11 CXXXXXXXXXOHHLLLHOL 1 12 ClOXXXXXlXOLHLHLLlHl 13 CXXXXllXXXOHHLLLHlll 14 ClOXXXXXlXOLHLHLLlHl 15 CXXXXOXXXXOHLHHHHlLl 16 CXXXXXXXXXOHHLLLHOLl 17 ClOXXXXXlXOLHLHLLlHl lB CXXXXlOXXXOLHHLLHlHl
19 CXXXXXXXXXOLHHHLHlHl 20 CXXXXXXOXXOHLHHHHlll 21 CXXXXXXXXXOHHLLLHOLl 22 ClOXXXXXlXOLHLHLLlHl 23 CXXXXlOXXXOLHHLLHlHl 24 CXXXXXXXXXOLHHHLHlHl 25 CXXXXXXlXXOHHLLLHlll 26 CXXXXXXXOXOHLHHHLlll 27 CXXXXXXXXXOHHLLLHOLl 28 CllXXXXXlXOHHLLLLOLl
PASS SIMULATION
672
29
NUMBER OF STUCK AT ONE ( SAl) FAULTS ARE = 24
NUMBER OF STUCK AT ZERO (SAO) FAULTS ARE = 24
PRODUCT TERM COVERAGE
=lOOl
156 Programmable Logic Design Guide
8
Applications*
8.1 BASIC GATES
This example demonstrates how fusable logic can implement the basic inverter, AND
OR, NANO, NOR and exclusive -OR functions. The PAL 12H6 is selected because it has 12
inputs and 6 outputs.
.
A---(»--e
~:::[)---e
PAL12H6
Vee
A B E H 0 R
Figure 8.1.1 Basic Gates
· Applications contained in this chapterare for mustration purposes onlyand National makes no representation or warranty that such applications wl11 be suitable for the use speciJled without further testing or mod111cation.
157
158 Programmable Logic Design Guide
PALASM VERSION 1.5
PAL12H6
TOM WANG
BASIC GATE
NSC SANTA CLARA
C D F GMN P Q I GND J K L R 0 H E B A VCC
B = /A
E = C*D
H=F+ G
L = /I + /J + /K
0 = /M*/N
R = P* /Q + /P*Q
FUNCTION TABLE
A B C 0 E F G H I J K L MN0 P Q R
xxxxHxxxxx-L-xxxxxxxxxHL---xxxxxxHHxLL--xxxxxxxHHLL--xxHxxxxxLLL---HHxxxxxxLLx--HHxxxxxxxLL--xHHxxxHxxxL---xxxxxxxxLxx--xxxxxxxLxxx--xxxxxxxxLxx--Hxxxxxxxxxx---xx-xxxxxxxxx-xx-xxxxxxxxx-x-xxxxxxxxxx---xxXXXxxxxxx--XXxxxXxxxxx--xXXXxxxxxxx-
;TEST ;TEST ;TEST ;TEST ;TEST ;TEST ;TEST ;TEST ;TEST ;TEST ;TEST
INVERTER INVERTER AND GATE AND GATE AND GATE ANO GATE OR GATE OR GATE OR GATE OR GATE NANO GATE
xxx·xxx
xx xx xx x x x
xx xx xx x xx
L LHH L H L H HL LH
xx xx xx x x x
X X X ;TEST X X X ;TEST X X X ;TEST
NANO NANO NANO
GATE GATE GATE
x x x x x x x x H H H L x x x X X X ;TEST NANO GATE
x x x x x x x x x x x x L L H X X X ;TEST NOR GATE
xx xx xX:Xx
xxxx xxxx xxxx
xxxx xxxx xxxx
xx xx·xx xx xx xx xx xx
L HL HL L H H L
x x x
X X X ;TEST X X X ;TEST X X X ;TEST L L L ;TEST
NOR GATE NOR GATE NOR GATE EXCLUSIVE
OR
GATE
x x x x x x x x x x x x x x x L H H ;TEST EXCLUSIVE OR GATE
xx xx
xx xx xx
xx xx xx
xx xx xx xx
x x x x x x
H L H ;TEST H H L ;TEST
EXCLUSIVE EXCLUSIVE
OR OR
GATE GATE
DESCRIPTION
BASIC GATE
************** **************
*
****
c * l*
* *
P A L
***** *20* vcc
****
****
*
1 2 H6
*
****
****
0 * 2*
*19* A
****
****
*
*
****
****
F * 3*
*18* B
****
****
*
*
****
****
G * 4*
*17* E
****
****
Applications 159
*
*
****
****
M * 5*
*16* H
****
****
*
*
****
****
N * 6*
*15* 0
****
****
*
*
****
****
p * 7*
*14* R
****
****
*
*
****
****
Q * 8*
*13* L
****
****
*
*
****
****
* 9*
*12* K
****
****
*
*
****
****
GND *10*
*11* J
****
****
*
*
*******************************
BASIC GATE
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL12H6 8
8
9
10 11
x-x-x-xxxxx xxxx
x--x-xXx xxxx xxxx
x--x0o0o xxoo xxoo
-x-x0o0o xxoo xxoo
x--x0o0o xxoo xxoo
x--x0o0o xxoo xxoo
x-x-x-xxxxx xxxx
-xx-x-xxxxx xxxx
/A
16 17
xXx-xXx-
x-x-x-x-
x--x0o0o
-x-x0o0o
x--x0o0o
x--x0o0o
x-x-x-x-
x-x-x-x-
C*D
24 ---- X--- --00 --00 --00 --00 ---- ---- F 25 ---- ---- X-00 --00 --00 --00 ---- ---- G
32 33
x-x-x-x-
-xx-x-x-
x--x0o0o
x-XxOoOo
x-XxOoOo
x--x0o0o
-xx-x-x-
x-x-x-x-
/M*/N
40 ---- ---- --00 --00 --00 X-00 -X-- ---- P*/Q 41 ---- ---- --00 --00 --00 -XOO X--- ---- /P*Q
48 ---- ---- --00 --00 --00 --00 ---- -X-- /I
49 ---- ---- --00 --00 --00 --00 ---- ---X /J
50 51
x-x-x-x-
x-x-x-x-
x--x0o0o
-x-x0o0o
x--x0o0o
-x-x0o0o
x--x-xXx
x-x-x-x-
/K
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O)
FUSE BLOWN (H,P,1)
0 : PHANTOM FUSE (L,N,O) 0 PHANTOM FUSE (H,P,l)
NUMBER OF FUSES BLOWN = 306
160 Programmable Logic Design Guide
BASIC GATE
1 XXXXXXXXXXXXXXXXXHOl 2 XXXXXXXXXXXXXXXXXLll 3 OOXXXXXXXXXXXXXXLXXl 4 OlXXXXXXXXXXXXXXLXXl 5 lOXXXXXXXXXXXXXXLXXl 6 llXXXXXXXXXXXXXXHXXl 7 XXOOXXXXXXXXXXXLXXXl 8 XXOlXXXXXXXXXXXHXXXl 9 XXlOXXXXXXXXXXXHXXXl 10 XXllXXXXXXXXXXXHXXXl 11 XXXXXXXXOXOOHXXXXXXl 12 XXXXXXXXOXOlHXXXXXXl 13 XXXXXXXXOXlOHXXXXXXl 14 XXXXXXXXlXOOHXXXXXXl 15 XXXXXXXXlXllLXXXXXXl" 16 XXXXOOXXXXXXXXHXXXXl 17 XXXXOlXXXXXXXXLXXXXl 18 XXXXlOXXXXXXXXLXXXXl 19 XXXXllXXXXXXXXLXXXXl 20 XXXXXXOOXXXXXLXXXXXl 21 XXXXXXOlXXXXXHXXXXXl 22 XXXXXXlOXXXXXHXXXXXl 23 XXXXXXllXXXXXLXXXXXl
PASS SIMULATION
230
BASIC GATE
1 XXXXXXXXXXXXXXXXXHOl 2 XXXXXXXXXXXXXXXXXLll 3 OOXXXXXXXXXXXXXXLXXl 4 OlXXXXXXXXXXXXXXLXXl 5 lOXXXXXXXXXXXXXXLXXl 6 llXXXXXXXXXXXXXXHXXl 7 XXOOXXXXXXXXXXXLXXXl 8 XXOlXXXXXXXXXXXHXXXl 9 XXlOXXXXXXXXXXXHXXXl 10 XXllXXXXXXXXXXXHXXXl 11 XXXXXXXXOXOOHXXXXXXl 12 XXXXXXXXOXOlHXXXXXXl 13 XXXXXXXXOXlOHXXXXXXl 14 XXXXXXXXlXOOHXXXXXXl 15 XXXXXXXXlXllLXXXXXXl 16 XXXXOOXXXXXXXXHXXXXl 17 XXXXOlXXXXXXXXLXXXXl 18 XXXXlOXXXXXXXXLXXXXl 19 XXXXllXXXXXXXXLXXXXl 20 XXXXXXOOXXXXXLXXXXXl 21 XXXXXXOlXXXXXHXXXXXl 22 XXXXXXlOXXXXXHXXXXXl 23 XXXXXXllXXXXXLXXXXXl
24
PASS SIMULATION
230
PRODUCT: 1 OF EQUATION. 4
PRODUCT: 2 OF EQUATION. 4
PRODUCT: 3 OF EQUATION. 4
24
UNTESTED(SAO)FAULT UNTESTED(SAO)FAULT UNTESTED(SAO)FAULT
NUMBER OF STUCK AT ONE (SAl) FAULTS ARE = 10
NUMBER OF STUCK AT ZERO (SAO) FAULTS ARE = 7
PRODUCT TERM COVERAGE
= 85%
c 1
..
~
2 ....
D
~
I I
" "
3 ..
F
~
.. U'
"11
4 ...
G
:>:
"" U'
Mco '
eI .
" "
(/)
E
. ~
5 M
u
~...,
::I
e"C
"ll
ll.
6 .
N
~
" "
.. p ,7
""~ U
....
" "
. a,8 ~
Inputs (0-31)
Applications 161
.....
-;c:
~~
- , o..c
J
'{"
'"--l._8cC,: ---,
-=kS -i
- , "-.1..-.<..'
19 A 18 B
17 E
16 H
:ms: ::J
15
0
-=t:S ::J
14 R
-+ :=M ,
13 L
=llS'
-r
1 2 K
"""'
9 ....
p~
.....
11
-..,..c.....'
J
Figure 8.1.2 Logic Diagram PAL12H6
162 Programmable Logic Design Guide
8.2 BASIC CLOCKED FLIP FLOPS
This example demonstrates how fusable logic, PAL16R8, can implement the basic flipflops;]-K flip-flop; T flip-flop, D flip-flop, and S-R flip-flop. A PAL16L8 can be substituted for this application. Then, the·clock input (CLK) would be gated with the data inputs to implement the basic flip-flop.
PALASM VERSION 1.5
PAL16R8 BF LIP BASIC NSC CLK J K T PR CLR D S R GND /OC /SRC /SRT /DC /OT /TC /TT /JKC /JKT VCC JKT:=J*/JKT*/CLR
+/K*JKT*/CLR +PR JKC:=/J*K*/PR +/J*/JKT*/PR +K*JKT*/PR +CLR TT:=T*/TT*/CLR +/T*TT*/CLR +PR TC:=/T*/TT*/PR +T*TT*/PR +CLR DT:=D*/CLR +PR DC:=/D*/PR +CLR SRT.:=S*/CLR +/R*SRT*/CLR +PR SRC:=/S*R*/PR +/S*/SRT*/PR +CLR FUNCTION TABLE CLK /QC PR CLR J K JKT JKC T TT TC D OT DC S R SRT SRC
X H X X x x z z x z z x z z x x z Z;HI-Z
C L L H C L L L C L L L C L L L C L L L C L L L C L L L C L H L C L L L C L L L
X X L L L L L H L H H H H L H L L H L H L X X H H H L H L H
H H H L L L H L H L
xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx
xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx
xxxxx xxxxx xxxxx . xxxxx xxxxx xxxxx
X;CLEAR X; X; X;TOGGLE X; X; X; X;PRESET X;TOGGLE X;
C L L H C L L L C L L L C L L L C L H L
xxxxx xxxxx xxxxx
x x x x x
X L H L L H H H L H L H X H L
xxx xxx xxx xx xx xx
xxxxx xxxxx xxxxx
X;CLEAR X; X;TOGGLE X;TOGGLE X;PRESET
Applications 163
C L L H C L L L C L L L C L L L C L H L
x x x xxxx xxxx xxxx
x x x x x
x x x xxxx xxxx xxxx
X L H L L H H H L L L H XH L
xxxxxx xxx xx xx xx
X;CLEAR X; X; X; X;PRESET
C L L H C LL L C L L L C L L L C L L L C L H L C L L L C L L L
xxxxxxxxxxxxxxxx xxxxxxxx
x x x x x x x x
xxxxxx xxxxxx xxxxxx xx xx xx
xxxxxxxxxxxxxxxx xxxxxxxx
X X L L L L H L H L H L L H L X X H L L H HL H
H;CLEAR H; L;SET H;RESET H;HOLD L;PRESET L; L;
------------------------------------------------------
DESCRIPTION
BASIC
************** **************
*
.* *
*
**** CLK * l*
P AL
****
*20* vcc
****
****
*
1 6 R8
*
****
****
J * 2*
*19* /JKT
****
****
*
*
****
****
K * 3*
*18* /JKC
****
****
*
*
****
****
T * 4*
*17* /TT
****
****
*
*
****
****
PR * 5*
*16* /TC
****
****
*
*
****
****
CLR * 6*
*15* /OT
****
****
*
*
****
****
D * 7*
*14* /DC
****
****
*
*
****
s * 8*
**** *13* /SRT
****
****
*
*
****
****
R * 9*
*12* /SRC
****
****
*
*
****
****
GND *10*
*11* /QC
****
****
*
*
*******************************
164 Programmable Logic Design Guide
BASIC
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16R8 8
0 X-X- ---- ---- ---- -X-- ---- ---- ---- J*/JKT*/CLR
1 ---X -X-- ---- ---- -X-- ---- ---- ---- /K*JKT*/CLR
2 3 4 5
6
7
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxXxxxxx-xxxx-xxxxxxxx
xx-xxxxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
PR
8 -X-- X--- ---- -X-- ---- ---- ---- ---- /J*K*/PR
9 -XX- ---- ---- -X-- ---- ---- ---- ---- /J*/JKT*/PR
10 ---X X--- ---- -X-- ---- ---- ---- ---- K*JKT*/PR
11 12 13 14 15
xx-xx-xx-xxxxxxxxxx
xx-xx-xx-xxxxxxxxxx
xx-xx-xx-xxxxxxxxxx
xx-xx-xx-xxxxxxxxxx
xXx-x-xxxxxxxxxxxxx
x-x-x-xxxxxxxxxxxxx
x-x-x-xxxxxxxxxxxxx
x-x-x-xxxxxxxxxxxxx
CLR
16 ---- ---- X-X- ---- -X-- ---- ---- ---- T*/TT*/CLR
17 ---- --~- -X-X ---- -X-- ---- ---- ---- /T*TT*/CLR
18 19 20 21 22 23
xx-xx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xxxxXxxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
xxxx-xxxx-xxxx-xxxxxxxx
PR
24 ---- ---- -XX- -X-- ---- ---- ---- ---- /T*/TT*/PR
25 ---- ---- X--X -X-- ---- ---- ---- ---- T*TT*/PR
26 27 28 29 30 31
-xxxx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xxXxx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
xx-xx-xx-xxxxxxxxxxxxxx
'CLR
32 ---- ---- ---- ---- -X-- X--- ---- ---- 0*/CLR
33 34 35 36 37
x-x-x-xxxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxx
xXx-x-xxxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxx
-xx-x-xxxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxx
PR
38 39
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
40 ---- ---- --~- -X-- ---- -X-- ---- ---- /0*/PR
41 42 43 44 45 46 47
x-x-x-xxxxxxxxx xxxxxxxx xxxx
-xx-x-xxxxxxxxx xxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxxxxxx xxxx
-xx-x-xxxxxxxxx xxxxxxxx xxxx
xXx-x-xxxxxxxxx xxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxxxxxx xxxx
x-x-x-xxxxxxxxx xxxxxxxx xxxx
CLR
Applications 165
48 ---- ---- ---- ---- -X-- ---- X--- ---- S*/CLR
49 ---- ---- ---- ---- -X-- ---- ---X -X-- /R*SRT*/CLR
50 51
x-x-x-x-
x-x-x-x-
x-x-x-x-
xXx-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
PR
52 53
54 55
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
xxxx xxxx xxxxxxxx
56 ---- ---- ---- -X-- ---- ---- -X-- X--- /S*R*/PR
57 ---- ---- ---- -X-- ---- ---- -XX- ---- /S*/SRT*/PR
58 59
60
61 62
63
x-x-x-xxxxx xxxxxxxx xxxx
x-x-x-xxxxx xxxxxxxx xxxx
-xx-x-xxxxx xxxxxxxx xxxx
-xx-x-xxxxx xxxxxxxx xxxx
Xxx-x-xxxxx xxxxxxxx xxxx
-xx-x-xxxxx xxxxxxxx xxxx
-xx-x-xxxxx xxxxxxxx xxxx
x-x-x-xxxxx xxxxxxxx xxxx
CLR
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O}
NUMBER OF FUSES BLOWN = 686
FUSE BLOWN (H;P,l}
BASIC
1 XXXXXXXXXXlZZZZZZZZl 2 CXXXOlXXXXOXXXXXXLHl 3 CXXXOlXXXXOXXXXXXLHl 4 COOXOOXXXXOXXXXXXLHl 5 COlXOOXXXXOXXXXXXLHl 6 CllXOOXXXXOXXXXXXHLl 7 ClOXOOXXXXOXXXXXXHLl 8 COOXOOXXXXOXXXXXXHLl 9 COlXOOXXXXOXXXXXXLHl 10 CXXXlOXXXXOXXXXXXHLl 11 CllXOOXXXXOXXXXXXLHl 12 ClOXOOXXXXOXXXXXXHLl 13 CXXXOlXXXXOXXXXLHXXl 14 CXXXOlXXXXOXXXXL~XXl 15 CXXOOOXXXXOXXXXLHXXl 16 CXXlOOXXXXOXXXXHLXXl 17 CXXlOOXXXXOXXXXLHXXl 18 CXXXlOXXXXOXXXXHLXXl 19 CXXXOlXXXXOXXLHXXXXl 20 CXXXOlXXXXOXXLHXXXXl 21 CXXXOOOXXXOXXLHXXXXl 22 CXXXOOlXXXOXXHLXXXXl 23 CXXXOOOXXXOXXLHXXXXl 24 CXXXlOXXXXOXXHLXXXXl 25 CXXXOlXXXXOLHXXXXXXl 26 CXXXOlXXXXOLHXXXXXXl 27 CXXXOOXOOXOLHXXXXXXl 28 CXXXOOXlOXOHLXXXXXXl 29 CXXXOOXOlXOLHXXXXXXl 30 CXXXOOXOlXOLHXXXXXXl 31 CXXXlOXXXXOHLXXXXXXl 32 CXXXOOXOOXOHLXXXXXXl 33 CXXXOOXlOXOHLXXXXXXl
PASS SIMULATION
759
34
166 Programmable Logic Design Guide
BASIC 1 XXXXXXXXXXlZZZZZZZZl 2 CXXXOlXXXXOXXXXXXLHl 3 CXXXOlXXXXOXXXXXXLHl .4 COOXOOXXXXOXXXXXXLHl 5 COlXOOXXXXOXXXXXXLHl 6 tllXOOXXXXOXXXXXXHLl 7 ClOXOOXXXXOXXXXXXHLl 8 COOXOOXXXXOXXXXXXHLl 9 COlXOOXXXXOXXXXXXLHl 10 CXXXlOXXXXOXXXXXXHLl 11 CllXOOXXXXOXXXXXXLHl 12 ClOXOOXXXXOXXXXXXHLl 13 CXXXOlXXXXOXXXXLHXXl 14 CXXXOlXXXXOXXXXLHXXl 1~ CXXOOOXXXXOXXXXLHXXl 16 CXXlOOXXXXOXXXXHLXXl 17 CXXlOOXXXXOXXXXLHXXl 18 CXXXlOXXXXOXXXXHLXXl 19 CXXXOlXXXXOXXLHXXXXl
20 CXXXOlXXXXOXXLHXXXXl 21 CXXXOOOXXXOXXLHXXXXl 22 CXXXOOlXXXOXXHLXXXXl 23 CXXXOOOXXXOXXLHXXXXl 24 CXXXlOXXXXOXXHLXXXXl 25 CXXXOlXXXXOLHXXXXXXl 26 CXXXOlXXXXOLHXXXXXXl 27 CXXXOOXOOXOLHXXXXXXl 28 CXXXOOXlOXOHLXXXXXXl 29 CXXXOOXOlXOLHXXXXXXl 30 CXXXOOXOlXOLHXXXXXXl 31 CXXXlOXXXXOHLXXXXXXl 32 CXXXOOXOOXOHLXXXXXXl 33 CXXXOOXlOXOHLXXXXXXl
PASS SIMULATION
759
PRODUCT: 1 OF EQUATION. 2
PRODUCT: 4 OF EQUATION. 2
PRODUCT: 2 OF EQUATION. 3
PRODUCT: 3 OF EQUATION. 4
PRODUCT: 2 OF EQUATION. 6
PRODUCT: 3 OF EQUATION. 8
34
UNTESTED(SAO)FAULT UNTESTED(SAO)FAULT UNTESTED(SAO)FAULT UNTESTED(SAO)FAULT UNTESTED{SAO)FAULT UNTESTED{SAO)FAULT
NUMBER OF STUCK AT ONE (SAl) FAULTS ARE = 23
NUMBER OF STUCK AT ZERO (SAO) FAULTS ARE = 17
PRODUCT TERM COVERAGE
= 86%
Applications 167
1 CLK
D-;...~~n---+4-l-l'-l-+4-l-4-+-1-1--+-1-++--+-l-++-+-4tt::t!tt::t!tt:=:=:=~~~~~~t-~_J
lCl-i!-~'t~-H~~t~-H=t-~t-~-t~-l~t-=t-!~t!-H!t-!t--=t-tltt-Htr-tIH~--~1t~-t~-;~~H~-1~~-~H-~Ht-=-L~I"~"'~.>~-~=, !~t!=.~~3::!--..~SRT
s 8
~ro.::--+-++-+-+-+-++-+-++-+-+-+-++-+-+t-+--+-1-++----.
~~~~->--+-++-+-+-+-++-+-++-+-+-+-++-+-+-+-+--+-t-++-+....
~
~ A
liH-H-lf--1H-IH--+-1H-l-1~H--+-1H-l--lf-HH--Hl-H'-ljl-HH--r~:>--~,
~i :+f+t::+f+t::+f+t:~++:::U++:::t++t::Ufl:::t++:t:=1§~~~-~ ~~ SRC
9
R
.~..~.,~._ ~~>_ --1+-+Hf--+++----H+-+++-+--++--+++--++-++----+++++++--+--++-++--++-+1--+1-f+-H+f+--++-+-+-+-++-.+..-.+. ~
.... '
DI 2 J 4 Si 1 8 91011 llD'41~ 16111119 20111nJ IO~lbl1 21U930l1
---"""..~.
~ ~OC
Figure 8.2.1 Logic Diagram PAL16R8
168 Programmable Logic Design Guide
8.3 MEMORY-MAPPED 1/0 (ADDRESS DECODER)
Memory-mapped VO is an interface technique that treats I/O devices' physical addresses the same as memory address space. That is, no Memory-I/O decoding is required. Furthermore, most computers have more instructions to manipulate the contents of memory than they have I/O instructions. Therefore, the use of memory map~ ping can make I/O control much more flexible. PAL devices can be used to make memory-mapped I/O implementation easy, even if changes in memory addresses are required.
Functional Description
Figure 8.3.1 shows a circuit that is typical of those found in memory-mapped I/O applications. The inputs to the decode logic are the system memory address lines, Ao-AF. The logic shown compares the address on the memory bus with the programmed comparison address. When an address on the bus matches, the corresponding I/O port enable signal is set. In conjunction with other system control signals, this enable can be used to transfer data to and from the system dat~ bus.
ABF D ABE ABO D ABC ABB ABA AB9 ABS AB7 D AB6 ABS AB4 AB3 AB2D AB1 D ABOD
PORT 0= 1F7S
[> [>
[>
[>[> [>
MEMORY MAPPED 10
PORTO
ABE
ABO ABC ABB ABA AB9 ABS AB7 AB6 ABS AB4 AB3 AB2 AB1 ABO
PORT 1=1F79 MEMORY MAPPED 10
Figure 8.3.1 Memory Mapped I/O Logic Diagram
PORT 1
Applications 169
PAL Device Design
One PAL 16L2 can be used to monitor a 16-bit address bus, fully decode addresses, and furnish enables to two ports, each of which can be anywhere within 64K of address space. Partial decoding for a larger number of ports can be done using other members of the PAL device family.
Typical logic equations for the memory-mapped 1/0 logic are as follows:
Port 0 = /ABO·/ABl ·/AB2· AB3·AB4·AB5·AB6·/AB7· ABB·AB9·ABA·ABB·ABC· IABD· IABE· IABF
Port 1 = ABO·/ABl ·/AB2·AB3·AB4·AB5·AB6·/AB7· ABB·AB9· ABA·ABB·ABC· IABD· IABE· IABF
The above example shows address decoding for memory locations 1F7Btt and 1F79tt. The equation terms could be changed to accommodate any 16-bit address.
PALASM VERSION 1.5 PAL16L2 PAT MEMORY MAP ABO ABl AB2 AB3 AB4 ABS AB6 AB? ABS GND AB9 ABA ABB ABC /PORTl /PORTO ABO ABE ABF VCC PORTO=/ABO*/AB1*/AB2*AB3 *AB4*AB5*AB6*/AB7*AB8*AB9*
ABA*ABA*ABC*/ABD*/ABE*/ABF . PORTl=ABO*/ABl*/AB2*AB3*AB4*AB5*AB6*/A87*A88*AB9*
ABA*ABB*ABC*/ABD*/ABE*/ABF DESCRIPTION MEMORY
************** **************
*
* *
*
****
****
ABO * l*
P A L.
*20* vcc
****
****
*
16 L2
*
****
****
ABl * 2*
*19* ABF
****
****
*
*
****
****
AB2 * 3*
*18* ABE
****
****
*
*
****
****
AB3 * 4*
*17* ABO
****
****
*
*·
****
****
AB4 * 5*
*16* /PORTO
****
****
170 Programmable Logic Design Guide
*
*
****
****
ABS * 6*
*15* /PORTl
****
****
*
*
AB6 **.*'*7**
**** *14* ABC
****
****
*
*
****
****
AB7 * 8*
*13* ABB
****
****
*
*
****
****
ABS * 9*
*12* ABA
****
****
*
*
****
****
GND *10*
*11* AB9
****
"****
*
*
*******************************
MEMORY 11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901 BEG*FPLT PAL16L2 8
24 25 26 27 28 29 30 31
x-Xxx-Xx xxxx xxxxxxxxxxxx xxxxxxxx
x-Xxx-Xx xxxx xxxxxxxxxxxx xxxxxxxx
xXx-x-Xx xxxx xxxxxxxxxxxx xxxxxxxx
xXx-x-Xx xxxx xxxxxxxxxxxx xxxxxxxx
xXx-xXxxxxx xxxxxxxxxxxx xxxxxxxx
xXx-x-x~ xxxxxxxx xxxx xxxx xxxx xxxx
x-XxxXxxxxx xxxxxxxxxxxx xxxxxxxx
xXx-Xxxxxxx xxxxxxxxxxxx xxxxxxxx
/ABO*/AB1*/AB2*AB3*AB4*AB5*AB6*
32 33 34 35 36 37 38 39
xxxx-XxxxxxxxxXxxxxxxxx xxxxxxxx
xxxx-Xxxxxxxxx-Xxxxx xxxx xxxxxxxx
xxxxXxxxx-xxxx-Xxxxx xxxx xxxxxxxx
xxxxXxxxx-xxxx-Xxxxx xxxx xxxxxxxx
xxXxx-xxXxxxxxxxxxx xxxx xxxxxxxx
xxxxXxxxx-xxxxXxxxxxxxx xxxxxxxx
xxx-xXxxxxxxxXxxxxxxxxx xxxxxxxx
xxxxXxxxx-xxxxXxxxxxxxx xxxxxxxx
ABO*/AB1*/AB2*AB3*AB4*AB5*AB6*/
END*FPLT
LEGEND: X : FUSE NOT BLOWN {L,N,O)
FUSE BLOWN {H,P,l)
0 : PHANTOM FUSE {L,N,O) 0 PHANTOM FUSE {H,P,1)
NUMBER OF FUSES BLOWN = 32
AB0 1
...
12..
2 . ~ r
I I I I I ~I I I 11111 llllUll 11111111 101.11111 11111111 11111111
Appllcatlons 171
.
19
<
ABF
~"'
3 ...
-12_
4 ...
...
II
II
II
II
11
II
II
5 ...
11
---1.2'
II II II Ii II 11 II II
6 ...
R
7 .
AB6
~ -
8 ...
AB7
r
...
18
~ _ ,
ABE
..
~ ,
17 ABO
,.. ,
16
"""""
Id
- ,'
' ,....
15
~
....
~
14 ABC
....
~
13 ABB
..
12
< ,
ABA
9 ..
AB6
R-
I I I I I I I I I 11111 1111141' 11111111 lllllllJ 14111111 11111111
....
11
~
Figure 8.3.2 Logic Diagam PAL 16L2
172 Programmable Logic Design Guide
8.4 HEXADECIMAL DECODER/LAMP DRIVER
The increasing use of microcomputers has led to an increased need to display numbers in hexadecimal· format (0-9, A-F). Standard drivers for this function are not available, so most applications are forced to use several packages to decode each digit, of the display. Since 6 to 12 digits are often being displayed, this approach can become very expensive. This example demonstrates how the hexadecimal display format can be both decoded and the LED indicators. driven using a single PAL for each digit of the display.
Functional Description
A hex decoder/lamp driver accepts a four-bit hex digit, converts it to its corresponding seven-segment display code, and activates the appropriate segments on the display. These drivers can be used in both direct-drive and multiplexed display applications. A single PAL can provide both the basic decode/drive functions, and additional useful features as well.
General Description
Figure 8.4.1 shows three digits of a display system that uses three PALs to implement
the complete decoding and display-driving functions. The inputs to each section are a
hex code on pins D0-D3; a ripple blanking signal, an intensity control signal, and a lamp
test signal.
·
The hex codes are decoded to form the seven-segment patterns shown in Figure
8.4.1. The input codes, digit, represented, and segments driven are as follows:
03
D2
D1
Do
Digit
Segments
0
0
0
0
0
ABC DEF
0
0
0
1 .
1
BC
0
0
1
0
2
AB DEG
0
0
1
1
3
ABCDG
0
1
0
0
4
BCFG
0
1
0
1
5
ACDFG
0
1
1
0
6
ACDEFG
0
1
1
1
7
ABC
1
0
0
0
8
ABCDEFG
1
0
0
1
9
ABCDFG
1
0
1
0
A
ABCEFG
1
0
1
1
8
1
1
0
0
c
CD EFG ADEF
1
1
0
1
D
BC DEG
1
1
1
0
E
AD EFG
1
1
1
1
F
AEFG
Table 8.4.1 Function Description
Applications 173
I I I I
DISPLAY j
LEADING 6 Vee
ZEROS
BLANK 5_
LEADING ":" ZEROS
THREE STAGE HEXADECIMAL DECODER /DRIVER
PAL 16L8 BCD TO HEXADECIMAL DECODER/7SEGMENT DRIVER WITH RIPPLE BLANKING
HEXADECIMAL INPUTS
LED/LAMP DRIVER OUTPUTS
OFF tvcc
INTENSITY
-------t--t----1
ON_£_
ONt LAMP TEST
OFF
TO NEXT STAGE
Figure 8.4.1 Hex Display Decoder-Driver, Combinational Logic Diagram
174 Programmable Logic Design Guide
Ripple-blanking input RBI is used to suppress leading zeroes in the display. The signal is propagated from the most significant digit to the least significant digit. If the digit input is zero and RBI is low (indicating that the previous digit is also zero), all segments are left blank and this digit position's ripple-blanking output RBO is set low.
Intensity control signal IC controls the duty cycle of the display driver. When IC is high, all segment drivers are turned off. Pulsing this pin with a duty-cycled signal allows the adjustment of the display's apparent brightness.
Lamp test signal LT lets you check to see if all LED segments are energized.
PAL Device Implementation
The PAL16L8 has both the required 1/0 pins and the drive current capability to perform as the complete display decoder-driver circuit with seven inputs and eight outputs. The logic equations for this circuit are shown in the listing. One PAL device drives each digit; they may be cascaded without limit. With minor changes, the same logical structure could be useq with multiplexer logic to allow a single PAL device to decode and drive multiple digits.
PALASM VERSION 1.5
PAL16L8 PAT07 HEX BLANK /RBI DO Dl 02 D3 IC LT NC NC GNO NC G /RBO F E D C B A VCC IF{/IC)/A=/RBO*/DO*/D2+/RB0*/00*03+/RBO*Ol*D2+
/RBO*Dl*D2*/03+/RBO*DO*D2*/D3+/RBO*/Dl*/D2*03+LT IF(IC)/B=/RB0*/02*/D3+/RB0*/00*/02+/RBO*/D0*/01*/03+
/RBO*OO*Dl*/03+/RB0*00*/01*/03+LT IF(IC)/C=/RBO*OD*/Ol+/RB0*00*/02+/RBO*/Ol*/02+
/RB0*02*/03+/RB0*/02*03+LT IF(IC)/D=/RB0*/01*03+/RB0*/00*/02*/03+
/RBO*DO*Ol*/02+/RB0*/00*01*02+/RB0*00*/01*02+LT IF(IC)/E=/RB0*/00*/02+/RB0*02*03+/RB0*/00*01+
/RBO*Dl*03+LT IF(IC)/F=/RB0*/00*/0l+/RB0*/02*03+/RBO*Dl*D3+
/RB0*/00*02+/RBO*/Ol*D2*/D3+LT IF(VCC)RB0=/00*/0l*/D2*/03*/RBI IF(/IC)/G=/RBO*Dl*/02+/RBO*OO*D3+/RB0*/02*D3+
/RBO*/DO*Dl+/RBO*/Ol*D2*/03+LT DESCRIPTION
HEX
************** **************
*****
/RBI * l*
* *
P AL
***** *20* vcc
****
****
*
1 6 L8
*
****
****
DO * 2*
*19* A
****
****
Applications 175
*
*
****
****
01 *3*
*18* B
****
****
*
*
**** 02 * 4*
****
*17* c
****
****
*
*
****
****
03 * 5*
*16* 0
****
****
*
*
****
****
IC * 6*
*15* E
****
****
*
*
****
****
LT * 7*
*14* F
****
****
*
*
****
****
NC * 8*
*13* /RBO
****
****
*
*
****
****
NC * 9*
*12* G
****
****
*
*
****
****
GNO *10*
*11* NC
****
****
*
*
*******************************
HEX
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16L8 8
0 ---- ----
-x--
i -{-- ---- -x--
--X-
2 -x-- ---- ---- x---
--X-
3 ---- x--- x---
--x-
4
5 6
x-------
----
x---x--
x-xx--------
-x~-
-x-x---
--x----xx--
7 ----
x---
/IC /RB0*/00*/02 /RB0*/00*03 /RBO*Ol*02 /RBO*Ol*02*/03 /RB0*00*02*/03 /RB0*/01*/02*03
LT
8 ----
x---
IC
9
10 11 12 13
---xx------x--x---
--xxx-------
--xx----
-x----xxx------
--x-
/RB0*/02*/03
--x-
/RB0*/00*/02
--x-
/RBO*/DO*/Dl*/03
--x-
/RBO*OO*Ol*/03
--x-
/RBO*OO*/Ol*/03
14 ----
x---
LT
15 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
176 Programmable Logic Design Guide
16 ---- ---- ---- ---- X--- ---- ---- ---- IC
17 X--- -X-- ---- ---- ---- ---- .--X- ---- /RB0*00*/01
18 19
X------
----X--
-X--X--
-------
-------
-------
--X-
--x~
--------
/RB0*00*/02 /RB0*/01*/02
20 ---- ---- X--- -X-- ---- ---- --X- ---- /RB0*02*/D3
21 ---- ---- -X-- X--- ---- ---- --X- ---- /RB0*/02*03
22 ---- ---~ ---- ---- ---- X--- ---- ---- LT
.
23 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
24 ---- ---- ---- ---- X--- ---- ---- ---- IC
25 ---- -X-- ---- X--- ---- --~- --X- ---- /RB0*/01*03
26 -X-- ---- -X-- -X-- ---- ---- --X- ---- /RB0*/00*/02*/03
27 X--- X--- -X-- ---- ---- ---- --X- ---- /RBO*OO*Ol*/02
28 -X-- X--- X--- ---- ---- ---- --X- ---- /RB0*/00*01*02
29 X--- -X-- X--- ---- ---- ---- --X- ---- /RB0*00*/01*02
30 31
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
xXx-x-x-
x-x-x-x-
x-x-x-x-
LT
32 ---- ---- ---- ---- X--- ---- ---- ---- IC
33 -X-- ---- -X-- ---- ---- ---- --X- ---- /RB0*/00*/02
34 ---- ---- X--- X--- ---- ---- --X- ---- /RB0*02*03
35 -X-- X--- ---- ---- ---- ---- --X- ---- /RB0*/00*01
36 ----.X--- ---- X--- ---- ---- --X- ---- /RBO*Ol*03
37 38 39
-xxxx-xx-xx-
xx-xx-xx-xx-
xx-xx-xx-xx-
x-xxx-xx-xx-
xx-xx-xx-xx-
xxXxx-xx-xx-
xx-xx-xx-xx-
xx-xx-xx-xx-
LT
40 ---- ---- ---- ---- X--- ---- ---- ---- IC
<l~ -·-- -X-- ---- ---- ---- ---- --X- ---- /RB0*/00*/0l
42 ---- ---- -X-- X--- ---- ---- --X- ---- /RB0*/02*03
43 ---- X--- ---- X--- ---- ---- --X- ---- /RBO*Ol*03
44 -X-- ---- X--- ---- ---- ---- --X- ---- /RB0*/00*02
45 ---- -X-- X--- -X-- ---- ---- --X- ---- /RB0*/01*02*/03
46
47
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
xXx-x-x-
x-x-x-x-
x-x-x-x-
LT
48 ---- ---- ---- ---- ---- ---- ---- ----
49 50
51 52 53 54 55
xxxxx-XxxxxxxxxxxXxxxxxxxxx
xxxxx-Xxxxxxxxxxx-xxxxxxxxx
xxxxx-Xxxxxxxxxxx-xxxxxxxxx
xxxxx-Xxxxxxxxxxx-xxxxxxxxx
xxxxx-xxxxx-xxxxx-xxxxxxxxx
xxxxx-xxxxx-xxxxx-xxxxxxxxx
xxxxx-xxxxx-xxxxx-xxxxxxxxx
xxxxx-xxxxx-xxxxx-xxxxxxxxx
/00*/01*/02*/03*/RBI
56 ---- ---- ---- ---- -X-- ---- ---- ---- /IC
57 ---~ X--- -X-- ---- ---- ---- --X- ---- /RBO*Dl*/02
58 X--- ---- ---- X--- ---- ---- --X- ---- /RB0*00*03
59 ---- ---- -X-- X--- ---- ---- --X- ---- /RB0*/02*03
60 -X-- X--- ---- ---- ---- ---- --X- ---- /RBO*/DO*Ol
61 ---- -X-- X--- -X-- ---- ---- --X- ---- /RB0*/01*02*/03
62 63
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
x-x-x-x-
xXx-x-x-
x-x-x-x-
x-x-x-x-
LT
ENO*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O)
FUSE BLOWN (H,P,l)
NUMBER OF FUSES BLOWN = 1496
Applications 177
2
~
.. v
3
.....
~
4 .~ .
5 ..... ~ .. U'
. 6
IC
">""-
7 LT
~
.. v
8 NC
.~ .. ..,
~ NC
... v
0 I! J
0 I l I 1 I 6 1
4161
I 91011 lltJUIS 11111119 2021222l 2'1~2621 212UOJ1
I
9
10
II
I! II
Ii:
"II
II 11 II II 10 !I 22 21
l4
,,21
16
21 29 JO II
Jl 31 J4 JI J6 11 JI 39
40 41
"41
44
.,41
46
..
49 ilfi
so
II SI SJ
S,4,
'6 11 I! 19 60 61 61 61
0 12 l 4 S61 891011 121l141S 161111119 2021121l 242S21i21 1829JDll
N .-..
>-
.J..:.
19A
..".."...'
~ -v-....t . -
t....:....
t:
\""."",'',
~ ~
18 B
...
.....
:J L ~~ ~
17 c
..................................
-<...........
:>_-J:]
16 D
...
-v .....
~
l>-
~ ~
-
15 E
~
....
_~""r '....- . --'
J::
I:
1"" l-o lo.
J.
IQ
~ ~
14 F
-
"'"'"""'
"h"' '"""-
13
" _;J
....
""'""'
~ l-o
t:'-
l-o l-o
G
...l-o
J.i
-<4
""'~
11 NC
Figure 8.4.2 Logic Diagram PAL16L8
178 Programmable Logic Design Guide 8.5 BETWEEN LIMITS COMPARATOR/LOGIC
PAL16C1
LOGIC SYMBOL
Figure 8. 5.1 PAL Device 16C 1 Limit Checker
PALASM VERSION 1.5
PAL16Cl PAT 0021 BETWEEN LIMITS COMPARITOP LOGIC NSC /EQlU /LTl /EQlL /GT2 /EQ2U /LT2 /EQ2L /GT3 /EQ3U GNO /LT3 /EQ3L NC NC NC /BTWL /GTO /LTO /GTl VCC
/BTWL = GT3 + GT2*EQ3U + GTl*EQ3U*EQ2U + GTO*EQ3U*EQ2U*EQ1U +
LT3 + LT2*EQ3L + LTl*EQ3L*EQ2L + LTO*EQ3L*EQ2L*EQ1L DESCRIPTION
BETWEEN LIMITS COMPARITOP LOGIC
************** **************
*
* *
*
****
****
/EQlU * l*
P A L
*20* vcc
****
****
*
1 6 c 1
*
****
****
/LTl * 2*
*19* /GTl
***-**
**** *
****
****
/EQlL * 3*.
*18* /LTO
****
****
*
*
Applications 179
/GT2 /EQ2U /LT2 /EQ2L /GT3 /EQ3U
GNO
****
****
* 4*
*17*
****
****
*
*
****
****
* 5*
*16*
****
****
*
*
****
****
* 6*
*15*
****
****
*
*
****
****
* 7*
*14*
****
****
*
*
****
****
* 8*
*13*
****
****
*
*
****
****
* 9*
*12*
****
****
*
*
****
****
*10*
*P*
****
****
*
*
*******************************
BETWEEN LIMITS COMPARITOP LOGIC
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16Cl 8
/GTO /BTWL NC NC NC /EQ3L /LT3
24 ---- ---- ---- ---- ---- ---- -X-- ---- GT3 25 ---- ---- -X-- ---- ---- ---- ---- -X-- GT2*EQ3U 26 ---- ---X ---- -X-- ---- ---- ---- -X-- GTl*EQ3U*EQ2U 27 ---X ---- ---- -X-X ---- ---- ---- -X-- GTO*EQ3U*EQ2U*EQ1U 28 ---- ---- ---- ---- ---- --~- ---- ---X LT3 29 ---- ---- ---- ---- -X-- ---- ---X ---- LT2*EQ3L 30 -X-- ---- ---- ---- ---- -X-- ---X ---- LTl*EQ3L*EQ2L 31 ---- -X-- ---X ---- ---- -X-- ---X ---- LTO*EQ3L*EQ2L*EQ1L
32
33
34 35 36
37
38 39
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ENO*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O)
FUSE BLOWN (H,P,l)
0 : PHANTOM FUSE (L,N,O) 0 PHANTOM FUSE (H,P,l)
NUMBER OF FUSES BLOWN = 236
180 Programmable Logic Design Guide
1 ... ~ -.....
2 ...
a.2
D 1 Z I · 5 I 1 I 11D11 11131·15 11171111 ZDZ11Zll ZU5ZU7 ZIZl!Ol1
...
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- 16
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j
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14
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13
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8
..
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12
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9 ...
I I Z I · 5 I 1 I l1Dl1 lllll·h 11171111 ZDZIZZI! ZCZ5ZU7 ZIZllO!I
....
11
.s.t
Figure 8.5.2 Logic Diagram PALI6Cl
Applications 181 8.6 QUADRUPLE 3-LINE/1-LINE DATA SELECTOR MULTIPLEXER
PALASM VERSION 1.5 PAL14H4 PAT0016 DATA SECLECTOR MULTIPLEXER PAL DESIGN lA 2A 3A 4A lB 2B 3B 4B lC GND 2C 3C 4C 4Y 3Y 2Y lY Sl SO VCC
lY = lA*/SO*/Sl + lB*SO*/Sl + lC*/SO*Sl 2Y = 2A*/SO*/Sl + 2B*SO*/Sl + 2C*/SO*Sl
3Y = 3A*/SO*/Sl + 3B*SO*/Sl + 3C*/SO*Si
4Y = 4A*/SO*/Sl + 4B*SO*/Sl + 4C*/SO*Sl
DESCRIPTION DATA SECLECTOR MULTIPLEXER
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901 BEG*FPLT PAL14H4 8
S(1·2) Y(1·4)
16 --X- ---X ---X --00 --00 ---- ---- ---- ~~*/SO*/Sl
17 ---- --X- ---X X-00 --00 ---- ---- ---- _3*50*/Sl
18 19
x-x-x-x-
x--x-xXx
x--xXxx-
x--x0o0o
~-00
xxoo
x-x-x-x-
x-x-x-x-
xXx-x-x-
:C*/SO*Sl
24 X--- ---X ---X --00 --00 ---- ---- ---- 2A*/SO*/Sl
25 ---- --X- ---X --00 X-00 ---- ---- ---- 2B*SO*/Sl
26 27
x-x-x-x-
x--x-xXx
x--xXxx-
x--x0o0o
x--x0o0o
x-x-x-x-
x-x-x-x-
x--xXxx-
2C*/SO*Sl
32 ---- X--X ---X --00 --00.---- ---- ---- 3A*/S0*/Sl
33 ---- --X- ---X --00 --00 X--- ---- ---- 36*50*/Sl
34 35
x-x-x-x-
x--x-xXx
x--xXxx-
x--x0o0o
x--x0o0o
x-x-x-x-
x--xXxx-
x-x~x-x-
3C*/SO*Sl
40 ---- ---X X--X --00 --00 ---- ---- ---- 4A*/S0*/Sl
41 ---- --X- ---X -~00 --00 ---- X--- ----·4B*SO*/Sl
42 43
x-x-x-x-
x--x-xXx
x--xXxx-
x--x0o0o
x--x0o0o
x--xXxx-
x-x-x-x-
x-x-x-x-
4C*/SO*Sl
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O)
FUSE BLOWN (H,P,1)
0 : PHANTOM FUSE (L,N,O) 0 PHANTOM FUSE (H,P,1)
NUMBER OF FUSES BLOWN = 348
182 Programmable Logic Design Guide
1 ...
1A
-
- 2 ...
2A ~
.. 3A 3
· I I J. '11 J I ' 1111 nu
4 .
4A
-
. 18 5 ..
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IO II II II
,.II
II
II
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7 38
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-.....
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-------
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\
---- _l
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1
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48 --2:
...... _st
. 9
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..
I 1 I J ·I Ir I 11111 lllJ
1111
11111111 JIHHIJ HHHU
<.......
~~
Figure 8.6.1 Logic Diagram PAL14H4
19
18 17 1Y 16
2Y
15 3Y
14 4Y 13 4C 12 3C 11 2C
8.7 4-BIT COUNTER WITH 2-INPUT MULTIPLEXER
Applications 183
INPUT A
INPUT B
CARRY
IN
OP SELECT
4-BIT COUNTER WITH
2-INPUT MUX AND
3-STATE OUTPUTS
CARRY
OUT
CLOCK ENABLE OUTPUT
OUTPUTS
Figure 8.7.1 Four-Bit Counter With Two-Input Multiplexer
PALASM VERSION 1.5
PAL16R4 PAT0034 4 BIT COUNTER WITH2 INPUT MUX NSC CLOCK AO Al A2 A3 BO Bl B2 B3 GNO /E COUT Il Q3 Q2 Ql QO IO CIN VCC /QO:=/Il*/IO*/QO + /Il*IO*/AO + Il*/IO*/BO + Il*IO*/CIN*/QO + Il*IO*CIN*QO /Ql:=/Il*/IO*/Ql + /Il*IO*/Al + Il*/IO*/Bl + Il*IO*/CIN*/Ql + Il*IO*CIN*Ql*QO + Il*IO*/Ql*/QO ./Q2:=/Il*/IO*/Q2 + /Il*IO*/A2 + Il*/IO*B2 + Il*IO*/CIN*/Q2 + Il*IO*CIN*Q2*Ql*QO + Il*IO*/Q2*/Ql + Il*IO*/Q2*/QO /Q3:=/ll*/IO*/Q3 + /Il*IO*/A3 + Il*/I0*/83 + Il*IO*/CIN*/Q3 + Il*IO*CIN*Q3*Q2*Ql*QO + Il*IO*/Q3*/Q2 + Il*IO*/Q3*/Ql + Il*IO*/Q3*/QO IF(VCC)/COUT = /CIN + /Q3 + /Q2 + /Ql + /QO DESCRIPTION
4 BIT COUNTER WITH2 INPUT.MUX
************** **************
*
* *
*
****
****
CLOCK * l*
P AL
*20* vcc
****
****
*
1 6 R4
*
****
****
AO * 2*
*19* CIN
****
****
*
*
****
****
Al * 3*
*18* IO
****
****
184 Programmable Logic Design Guide
*
*
****
****
~2 * 4*
*17* QO
****
****
*
*
****
****
A3 * 5*
*16* Ql
****
****
*
*
****
****
BO * 6*
*15* Q2
****
****
*
*
****
****
Bl * 7*
*14* Q3
****
****
*
*
****
****
'B2 * 8*
*13* 11
****
****
*
*
**** B3 * 9*
**** *12* COUT
****
****
*
*
****
****
GND *10*
*11* /E
****
****
*
*
*******************************
4 BIT COUNTER WITH2 INPUT MUX
11 1111 1111 2222 2222 1233 0123 4567 8901 2345 6789 0123 4567 8901
BE01G*xxFxxPxxLxxT xxPxxAxxLxx16Rxxxx4xxxx 8xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
2 XXXX XXXX XXXX XXXX XXXX XXXX XXXX. XXXX
3 4
5 6 7
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8
9
10
11
12 13 14 15
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Applications 185
16 ---- ---X ---X ---- ---- ---- ---X ---- /Il*/IO*/QO
17 -X-- --X- ---- ---- ---- ---- ---X ---- /Il*IO*/AO
18 ---- ---X ---- ---- -X-- ---- --X- ---- Il*/IO*/BO
19 ---X --X- ---X ---- ---- ---- --X- ---- Il*IO*/CIN*/QO
20 21 22 23
xxx--xxxXxxxxxx-
xx-x-xxxXxxxxxx-
xx-x-xxxXxxxxxx-
xxx-xxx-xxx-xxx-
xx-xxxx-xxx-xxx-
xxx-xxx-xxx-xxx-
xxx--xxxXxxxxxx-
xxx-xxx-xxx-xxx-
Il*IO*CIN*QO
24 ---- ---X ---- ---X ---- ---- ---X ---- /Il*/IO*/Ql
25 ---- -XX- ---- ---- ---- ---- ---X ---- /Il*IO*/Al
26 ---- ---X ---- ---- ---- -X-- --X- ---- Il*/10*/Bl
27 ---X --X- ---- ---X ---- ---- --X- ---- Il*IO*/CIN*/Ql
28 --X- --X- --X- --X- ---- ---- --X- ---- Il*IO*CIN*Ql*QO
29 30 31
-xxxx-xx-xx-
xx--xxXxxxx-
x-x-xx-xxXxx
-xx-xx-xxXxx
x-xxx-xx-xx-
xx-xx-xx-xx-
x-x-xxXxxxx-
x-xxx-xx-xx-
Il*IO*/Ql*/QO
32 ---- ---X ---- ---- ---X ---- ---X ---- /Il*/IO*/Q2
33 ---- --X- -X-- ---- ---- ---- ---X ---- /Il*IO*/A2
34 -~-- ---X ---- ---- ---- ---- X-X- ---- Il*/IO*B2
35 ---X --X- ---- ---- ---X --~- --X- ---- Il*IO*/CIN*/Q2
36 --X- --X- --X- --X- --X- ---- --X- ---- Il*IO*CIN*Q2*Ql*QO
37 ---- --X- ---- ---X ---X ---- --X- ---- Il*IO*/Q2*/Ql
38 39
x-x-x-x-
-x-xXxx-
x--x-xXx
x-x-x-x-
-x-x-xXx
-xx-x-x-
x--xXxx-
x-x-x-x-
Il*IO*/Q2*/QO
40 ---- ---X ---- ---- ---- ---X ---X ~--- /ll*/IO*/Q3 41 ---- --X- ---- -X-- ---- ---- ---X ---- /Il*IO*/A3 42 ---- ---X ---- ---- ---- ---- --X- -X-- Il*/IO*/B3 43 ---X --X- ---- ---- ---- ---X --X- ---- Il*IO*/CIN*/Q3 44 --X- --X- --X- --X- --X- --X- --X- ---- Il*IO*CIN*Q3*Q2*Ql*QO 45 ---- --X- ---- ---- ---X ---X --X- ---- Il*IO*/Q3*/Q2 46 ---- --X- ---- ---X ---- ---X --X- ---- Il*IO*/Q3*/Ql 47 ---- --X- ---X ---- ---- ---X --X- ---- Il*IO*/Q3*/QO
48 49 50 51 52 53 54 55
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.
56 ---- ---- ---- ---- ---- ---- ---- ----
57 ---X ---- ---- ---- ---- ---- ---- ---- /CIN
58 --~- ---- ---- ---- ---- --~X ---- ---- /Q3
59 ---- ---- ---- ---- ---X ---- ---- ---~ /Q2
60 ---- ---- ---- ---X ---- ---- ---- ---- /Ql
61 62 63
x-x-x-xxxxx
x-x-x-xxxxx
x--x-xXx xxxx
x-x-x-xxxxx
-xx-x-xxxxx
x-x-x-xxxxx
x-x-x-xxxxx
x-x-x-xxxxx
/QO
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O)
FUSE BLOWN (H,P,l)
NUMBER OF FUSES BLOWN = 921
186 Programmable Logic Design Guide
a 12 J · S 17 I tlOll UU1415 11111111 uz1un HHUZJ UZ1ll11
I
. . 1
' J
I 1
~ ..
r~ el
19
.....
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* ~
18
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11 11 11 11
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to.
w '
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8 ...
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11
"IJ
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' ...."""...."""......''' ../
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j
.....
.~ .JC..:..L.
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~
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Figure 8.7.2 Logic Diagram PAL16R4
Applications 187
8.8 8-BIT SYNCHRONOUS COUNTER
The 8-bit synchronous counter is used in many systems. The input AO serves a mode control with LOW for LOAD operation and HIGH for count operation. Input Al enables the LOAD operation when AO is set in the LOAD mode and doesn't care when the count mode is chosen. This enables the counter to be cascaded as a multibyte counter with the capability of leading individual byte from a simple byte wide data bus and a common clock. /CIN is the carry input and /COUT is the carry output.
PAL20X8 SBIT SYNCHRONOUS COUNTER LOGIC DESIGN NSC CLK AO XO Xl X2 X3 X4 X5 X6 X7 Al GND /EN /COUT /Y7 /Y6 /Y5 /Y4 /Y3 /Y2 /Yl /YO /CIN VCC YO:=/Al*/AO*YO +AO*YO :+:Al*/AO*XO +AO*CIN Yl:=/Al*/AO*Yl+ AO*Yl:+: Al*/AO*Xl + AO*CIN*YO Y2:=/Al*/AO*Y2+ AO*Y2:+: Al*/AO*X2 + AO*CIN*YO*Yl Y3:=/Al*/AO*Y3+ AO*Y3:+:Al*/AO*X3 + AO*CIN*YO*Yl*Y2 Y4:=/Al*/AO*Y4 + AO*Y4 :+: Al*/AO*X4+ AO*CIN*YO*Yl*Y2*Y3 Y5:=/Al*/AO*Y5 + AO*YS:+: Al*/AO*X5+ AO*CIN*YO*Yl*Y2*Y3*Y4 Y6:=/Al*/AO*Y6 + AO*Y6:+: Al*/AO*X6+ AO*CIN*YO*Yl*Y2*Y3*Y4*Y5 Y7:=/Al*/AO*Y7 + AO*Y7:+: Al*/AO*X7+ AO*CIN*YO*Yl*Y2*Y3*Y4*Y5*Y6 IF(VCC)COUT = CIN*YO*Yl*Y2*Y3*Y4*Y5*Y6*Y7 DESCRIPTION
188 Programmable Logic Design Guide
LOGIC DESIGN
CLK AO XO Xl X2 X3 X4 XS X6 X7 Al GND
************** **************
*
* *
*
**** * l*
P AL
****
*24* vcc
****
****
*
2 0 x 8
*
****
****
* 2*
*23* /CIN
****
****
*
*
****
****
* 3*
*22* /YO
****
****
*
*
****
****
* 4*
*21* /Yl
****
****
*
*
****
****
* 5*
*20* /Y2
****
****
*
*
****
****
* 6*
*19* /Y3
****
****
*
*
****
****
* 7*
*18* /Y4
****
****
*
*
****
****
* 8*
*17* /YS
****
****
*
*
****
****
* 9*
*16* /Y6
****
'**** -
*
*
****
****
*10*
*15* /Y7
****
****
*
*
****
****
*11*
*14* /COUT
****
****"
*
*
****
****
*12*
*13* /EN
****
****
*
*
*******************************
Applications 189
LOGIC DESIGN
11 1111 1111 2222 2222 2233 3333 3333 0123 4567 8901 2345 6789 0123 4567 8901 2345 6789
BE023G1*xxxxFPxxxxLxxxxxxxxT
xPxAxLx20Xxx8xx 10xxxx xxxx xxxx xxxx xxxxxxxx xxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
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8 -X-- ---X ---- ---- ---- ---- ---- ---- ---- -X-- /Al*/AO*YO 9 X--- ---X ---- ---- ---- ---- ---- ---- ---- ---- AO*YO 10 -X-- X--- ---- ---- ---- ---- ---- ---- ---- X--- Al*/AO*XO 11 X--X ---- ---- ---- ---- ---- ---- ---- ---- ---~ AO*CIN
16 -X-- ---- ---X ---- ---- ---- ---- ---- ---- -X-- /Al*/AO*Yl 17 X--- ---- ---X ---- ---- ---- ---- ---- ---- ---- AO*Yl 18 -X-- ---- X--- ---- ---- ---- ---- ---- ---- X--- Al*/AO*Xl 19 x-~x ---X ---- ---- ---- ---- ---- ---- ---- ---- AO*CIN*YO'
24 -X-- ---- ---- ---X ---- ---- ---- ---- ---- -X-- /Al*/AO*Y2 25 X--- ---- ---- ---X ---- ---- ---- ---- ---- ---- AO*Y2 26 -X-- ---- ---- X--- ---- ---- ---- ---- ---- X--- Al*/AO*X2 27 X--X ---X ---X ---- ---- ---- ---- ---- ---- ---- AO*CIN*YO*Yl
32 -X-- ---- ---~ ---- ---X ---- ---- ---- ---- -X-- /Al*/AO*Y3 33 X--- ---- ---- ---- ---X ---- ---- ---- ---- ---- AO*Y3 34 -X-- ---- ---- ---- X--- ---- ---- ---- ---- X--- Al*/AO*X3 35 X--X ---X --~X ---X ---- ---- ---- ---- ---~ ---- AO*CIN*YO*Yl*Y2
40 -X-- ---- ---- -~-- ---- ---X ---- ---- ---- -X-- /Al*/AO*Y4 41 X--- ---- ---- ---- ---- ---X ---- ---- ---- ---- AO*Y4 42 -X-- ---- ---- ---- -~-- X--- ---- ---- ---- X--- Al*/AO*X4 43 X--X ---X ---X ---X ---X ---- ---- ---- ---- ---- AO*CIN*YO*Yl*Y2*Y3
48 -X-- ---- ---- ---- ---- ---- ---X ---- ---- -X-- /Al*/AO*Y5 49 X--- ---- ---- ---- ---- ---- ---X ---- ---- ---- AO*Y5 50 -X-- ---- ---- ---- ---- ---- X--- ---- ---- X--- Al*/AO*X5 51 X--X ---X ---X ---X ---X ---X ---- ---- ---- ---- AO*CIN*YO*Yl*Y2*Y3*Y4
56 -X-- ---- ---- ---- ---- ---- ---- ---X ---- -X-- /Al*/AO*Y6 57 X--- ---- ---- ---- ---- ---- ---~ ---X ---- ---- AO*Y6 58 -X-- ---- ---- ---~ ---- ---- ---- X--- ---- X--- Al*/AO*X6 59 X--X ---X ---X ---X ---X ---X ---X ---- ---- ---- AO*CIN*YO*Yl*Y2*Y3*Y4*Y5
64 -X-- ---- ---- ---- ---- ---- ---- ---- ---X -X-- /Al*/AO*Y7 65 X--- ---- ---- ---- ---- ---- ---- ---- ---X ---- AO*Y7 66 -X-- ---- ---- ---- ---- ---- ---- ---- X--- X--- Al*/AO*X7 67 X--X ---X ---X ---X ---X ---X ---X ---X ---- ---- AO*CIN*YO*Yl*Y2*Y3*Y4*Y-
72 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
73 74 75
xx--xx-xxXxx
xx--xx-xxXxx
xx--xx-xxXxx
x-x-xx-xxXxx
xx--xx-xxXxx
xx--xx-xxXxx
x-x-xx-xxXxx
xx--xx-xxXxx
xx--xx-xxXxx
xx-xx-xx-xx-
CIN*YO*Yl*Y2*Y3*Y4*Y5*Y-
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O) : FUSE BLOWN (H,P,l) 0 : PHANTOM FUSE (L,N,O) 0 : PHANTOM FUSE (H,P,1)
NUMBER OF FUSES BLOW = 1243
190 Programmable Logic Design Guide 8.9 6·BIT SHIFT REGISTER WITH THREE-STATE OUTPUTS
PALASM VERSION 1.5
PAL16R6 PAT05 6BIT SVALE CK SR DO Dl D2 D3 D4 D5 SL GND /E RILO Q5 Q4 Q3 Q2 Ql QO LIRO VCC IF(SR*/SL)/LIRO=/QO /QO:=/SR*/SL*/QO+SR*/SL*/Ql+/SR*SL*/LIRO+SR*SL*/DO /Ql:=/SR*/SL*/Ql+SR*/SL*/Q2+/SR*SL*/QO+SR*SL*/Dl /Q2:=/SR*/SL*/Q2+SR*/SL*/Q3+/SR*SL*/Ql+SR*SL*/D2 /Q3:=/SR*/SL*/Q3+SR*/SL*/Q4+/SR*SL*/Q2+SR*SL*/D3 /Q4:=/SR*/SL*/Q4+SR*/SL*/Q5+/SR*SL*/Q3+SR*SL*/D4 /Q5:=/SR*/SL*/Q5+SR*/SL*/RILO+/SR*SL*/Q4+SR*SL*/D5 IF{/SR*SL)/RILO=/Q5 DESCRIPTION
6BIT
************** **************
*
* *
*
****
****
CK * l*
PAL
*20* vcc
****
****
*
1 6 R6
'*
****
****
SR * 2*
*19* LIRO
****
****
*
*
****
****
DO * 3*
*18* QO
****
****
*
*
****
****
Dl * 4*
*17* Ql
****
****
*
*
****
****
D2 * 5*
*16* Q2
****
****
*
*
****
****
D3 * 6*
*15* Q3
****
****
*
*
****
****
D4 * 7*
*14* Q4
****
****
*
*
****
****
D5 * 8*
*13* Q5
****
****
*
*
****
****
SL * 9*
*12* RILO
****
****
Applications 191
*****
*****
GND *10*
*11* /E
****
****
*********************************
6BIT
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16R6 8
0 X--- ---- ---- ---- ---- ---- ---- -X-- SR*/Sl
1 2 3
xx-xx-xx-xx-
xx--xx-xxXxx
xx-xx-xx-xx-
xx-xx-xx-xx-
x-x-x~xxxxx
xx-xx-xx-xx-
xx-xx-xx-xx-
xx-xx-xx-xx-
/QO
4 5 6 7
xxxxxxxxxxxxxxxx
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xxxxxxxxxxxxxxxx
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8 -X-- ---X ---- ---- ---- ---- ---- -X-- /SR*/SL*/QO
9 X--- ---- ---X ---- ---- ---- ---- -X-- SR*/Sl*/Ql
10 -X-X ---- ---- ~--- ---- ---- ---- X--- /SR*SL*/LIRO
11 12 13
xxXxx-xx-xx-
xx-Xxxxx-xx-
xx-xx-xx-xx-
xx-xx-xx-xx-
x-xxx-xx-xx-
xx-xx-xx-xx-
xx-xx-xx-xx-
xxXxx-xx-xx-
SR*SL*/00
14 15
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
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16 -X-- ---- ---X ---- ---- ---- ---- -X-- /SR*/SL*/Ql
17 X--- ---- ---- ---X ---- ---- ---- -X-- SR*/SL*/Q2
18 -X-- ---X ---- ---- ---- ---- ---- X--- /SR*SL*/QO
19 20 21 22 23
xxxxXxxxx-xxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
xxxx-Xxxxxxxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
xxxxXxxxx-xxxx-xxxx-
SR*SL*/01
24 -X-- ---- ---- ---X ---- ---- ---- -X-- /SR*/Sl*/Q2
25 X--- ---- ---- ---- ---X ---- ---- -X-- SR*/Sl*/Q3
26 -X-- ---- ---X ---- ---- ---- ---- X--- /SR*SL*/Ql
27 28 29 30 31
xxXxx-xx-xxxxxxxxxx
-xxxx-xx-xxxxxxxxxx
xx-xx-xx-xxxxxxxxxx
-xxXxxxx-xxxxxxxxxx
-xxx-xxx-xxxxxxxxxx
-xxxx-xx-xxxxxxxxxx
-xx-xxxx-xxxxxxxxxx
xXxxx-xx-xxxxxxxxxx
SR*SL*/02
32 -X-- ---- ---- ---- ---X ---- ---- -X-- /SR*/SL*/Q3
33 X--- ---- ---- ---- ---- ---X ---- -X-- SR*/Sl*/Q4 34 -X-- ---- ---- ---X ---- ---- ---- X--- /SR*SL*/Q2
35 36 37 38 39
xxxXxxx-xxx-xxxxxxx
x-xxxxx-xxx-xxxxxxx
xxx-xxx-xxx-xxxxxxx
xxx-xxx-xxx-xxxxxxx
xxx-Xxxxxxx-xxxxxxx
xxx-xxx-xxx-xxxxxxx
xx-xxxx-xxx-xxxxxxx
xxxXxxx-xxx-xxxxxxx
SR*SL*/03
192 Programmable Logic Design Guide
40 -X-- ---- ---- ---- ---- ---X ---- -X-- /SR*/SL*/Q4
41 X--- ---- ---- ---- ---- ---- ---X -X-- SR*/SL*/Q5
42 -X-- ---- ~--- ---- ---X ---- ---- X--- /SR*SL*/Q3
43 44
45 46 47
xXx-x-xxxxx xxxxxxxx
x-x-x-xxxxx xxxxxxxx
x-x-x-xxxxx xxxxxxxx
x-x-x-xxxxx xxxxxxxx
x-x-x-xxxxx xxxxxxxx
-xXxx-xxxxx xxxxxxxx
x-x-x-xxxxx xxxxxxxx
xXx-x-xxxxx xxxxxxxx
SR*SL*/04
48 -X-- ---- ---- ---- ---- ---- ---X -X-- /SR*/SL*/Q5
49 X--- ---- ---- ---- ---- ---- ---- -X-X SR*/SL~/RILO
50 -X-- ---- ---- ---- ---- ---X ---- X--- /SR*SL*/Q4
51 52 53
54
55
xxxXxxxxx-xxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
x-xxxxxxx-xxxx-xxxx-
xxxx-xxxx-xxxx-xxxx-
x-x~x-xxxxx xxxx xxxx
xxxx-xxxx-xxxx-xxxx-
xxxx-Xxxxxxxxx-xxxx-
xxxxXxxxx-xxxx-xxxx-
SR*SL*/05.
56 -X-- ---- ---- ---- ---- ---- ---- X--- /SR*SL
57
58
59 60 61
62
63
xxxx-xxxx-xxxx-xxxxxxxx xxxx
xxxx-xxxx-xxxx-xxxxxxxx xxxx
xxxx-xxxx-xxxx-xxxxxxxx xxxx
xxxx-xxxx-xxxx-xxxxxxxx xxxx
xxxx-xxxx-xxxx-xxxxxxxx xxxx
xxxx-xxxx-xxxx-xxxxxxxx xxxx
xxxx--xxxx-xxxxXxxxx xxxx xxxx
x~x-x-xxxxxxxxx xxxx xxxx xxxx
/Q5
END*FPLT
LEGEND: X : FUSE NOT BLOWN (L,N,O). - · FUSE BLOWN (H,P,1)
NUMBER OF FUSES BLOWN = 818
Applications 193
Inputs (0-31)
CK ~--~~~~~~~~~~~~-~~~~~~
Q 1 1 ] · !t ' ' I 110 II 111)" ·~ , . . , ,, 11 20 21111) 141n1' 11 11n10 ]I
'IQ 0 ' l J 4 !i I 1 I
11 11 IJ IC l!I 111111 u 10 21221l 24 n 21 n 21H1D JI
Figure 8.9.1 Logic Diagram PAL16R6
194 Programmable Logic Design Guide 8.10 PORTION OF RANDOM CONTROL LOGIC FOR 8086 CPU BOARD
PD~~~~~~ ~0--------~1----~~--~ EN~----------------~---+--~--~--~-
EQ~~---------------------+--~-;:._-:._-_-_~_""1..___,,t----------~------'--~C3
EA~~~~~~~~~~~-+-~_.
Sl~--------------~----1---~------t
SA-----------.-----t :>c>----------------L-.J
10-----HA
---~~- >o-----ss
JO-----LA
oo~---------------~-----------------------1~~
Figure 8.10.1 Control Logic for 8086 CPU Board
PALASM VERSION 1.5
PAL12H6 PAT03 8086 CPU PD EN EO EA Sl SA El DO DE GND SO NC3 NO C3 HA SS LA MW PW VCC MW=/SO+PW*DE LA=/SA*/DO SS=Sl*PD*/SA HA=Sl*PD*/SA*EA*El C3=PD*EO*EA NO=PD*/EN DESCRIPTION
·0006
************** **************
* ****
* *
*****
PD * i*
P A L
*20* vcc
****
****
*
1 2 H6
*
****
****
EN * 2*
*19* PW
****
****
Applications 195
*
*
****
****
EO * 3*
*18* MW
****
****
*
*
****
****
EA * 4*
*17* LA
****
****
*
*
****
****
Sl * 5*
*16* SS
****
****
*
*
****
****
SA * 6*
*15* HA
****
****
*
*
****
****
El * 7*
*14* C3
****
****
*
*
****
****
DO * 8*
*13* NO
****
****
*
*
****
****
DE * 9*
*12* NC3
****
****
*
*
****
****
GND *10*
*11* so
****
****
*
*
*******************************
8086
11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL12H6 8
8 ---- ---- --00 --00 --00 --00 ---- ---X /SO
9 10 11
-xxx-xxx-xx-
x-x-xxXxxxx-
-xx-xx0oo0oo
-xx-xx0oo0oo
-xx-xx0oo0oo
-xx-xx0oo0oo
x-xxx-xx-xx-
xxXxx-xx-xx-
PW*DE
16 17
x-x-x-x-
x-x-x-x-
x--x0o0o
x--x0o0o
x-XxOoOo
x--x0o0o
x-Xxx-x-
x-x-x-x-
/SA*/00
24 25
x--xXxx-
x-x-x-x-
-x-x0o0o
xXx-o0o0
x-XxOoOo
x--x0o0o
x-x-x-x-
x-x-x-x-
Sl*PD*/SA
32 33
x--xXxx-
x-x-x-x-
xXx-o0o0
xXx-o0o0
x-XxOoOo
xXx-o0o0
x-x-x-x-
x-x-x-x-
Sl*PD*/SA*EA*El
40 41
x--xXxx-
xXx-x-x-
xXx-o0o0
x--x0o0o
x--x0o0o
x--x0o0o
x-x-x-x-
x-x-x-x-
PD*EO*EA
196 Programmable logic Design Guide
48 -XX- ---- --00 --00 --00 --00 ---- ---- PD*/EN
49
50 51
xXxXxXxX xxxx
xxXxxXXxxXxx
xXxXoOoO xxoo
xXXxOoOo xxoo
XxXxOooO xxoo
xXxXoOoO xxoo
xXxXxXxX xxxx
XxXxXxxX xxxx
END*FPLT LEGEND: X : FUSE NOT BLOWN (L,N,0)
0 : PHANTOM FUSE (L,N,O)
NUMBER OF FUSES BLOWN = 206
: FUSE BLOWN (H,P,l) 0 : PHANTOM FUSE (H,P,1)
PAL DEVICES FOR EASY INTERFACE BETWEEN DP8408/09* DRAM CONTROLLER AND POPULAR MICROPROCESSORS
High storage density and low cost have made dynamic RAMs the designers choice in most memory applications. However, the major drawbacks of dynamic RAMs are the complex timing involved and periodic refresh needed to keep all memory cells charged. With the introduction of the DP8408/09 Dynamic 'RAM controller/driver, the above complexities are simplified.
Use of PAL devices adds flexibility in the design as PAL device logic equations can be modified by the user for his/her application and programmed into any of the PAL devices. In addition, PAL devices lower the parts count in memory system design. For most memory operations, the PAL devices (DP8432/322/332) can be directly connected between the control signals from the CPU chip set and the DP8408/09 dynamic RAM controller. The PAL device allows hidden refresh using the DP8408/09. In a standard memory cycle, the access can be slowed by one clock cycle to accommodate slower memories. This extra wait state will not appear during the hidden refresh cycle, so faster devices on the CPU bus will not be affected. Similarly, PAL devices allow for the insertion of wait states for processors operating at high CPU clock frequencies to use slower dynamic RAMs.
The following three applications describe the use of National's PAL16R6, PAL16R4 and PAL16R8 for the ease and flexibility of interfacing DP8408/09 with popular microprocessors such as the 32032, 68000, 8086, and 8088. Today the PAL device family offers the designer flexibility to design desired speed/power PAL device in his memory systems, and achieve the memory operations at very high frequencies with or without wait state conditions.
· DP8408109 is part of tbe interface product line at National Semiconductor Corp.
Applications 197
8.11 DP84312 DYNAMIC RAM CONTROLLER INTERFACE CIRCUIT FOR THE NS32032 CPU
.General Description
The DP84312 dynamic RAM Controller interface is a PAL device for interface between the DP8409 dynamic RAM Controller and the NS32032 microprocessor.
Using timing signals from the NS32032;timing and control unit and the NS32032 the DP84312 supplies all control signals needed to perform memory read, write, byte write, and refresh.
Features
· Low parts count memory system. · Allows the DP8409 to perform hidden refresh. · Allows for the insertion of wait states for slow dynamic RAMs. 0 Supplies independent CASs for byte writing. · Possibility of operation at 8MHz with no wait states. 0 20-pin 0.3 inch wide package. 0 Standard NationalSemiconductor PAL device part (PAL16R6). 0 PAL device logic equations can be modified by the user for his/her specific applica-
tion and programmed into any of the National Semiconductor PAL device family, including the new high speed PAL devices.
Dual-In-Line Package
CLK 1
20 Vee
RASIN 2
19 RFSH
RFRQ 3
18 CASH
HBE 4
17 CASL
AO 5
16 NC
WAITIN 6
15 NC
CTTL 7
14 NC
cs 8
13 NC
WAIT1 9
12 WAIT
GND 10
11 GND
TOP VIEW
Figure 8.11.1 Connection Diagram
198 Programmable Logic Design Guide
Symbol Vee loH loL TAA
Parameter Supply Voltage High Level Output Current
Min
Typ
Max
4.75
5.00
5.25
-3.2
, · Low Level Output Current
Operating Free Air Temperature
0
24 (Note2)
75
Table 8.11.1 Recommended Operating Conditions
Units
v
mA
mA
oc
Symbol
Parameter
V1H High Level Input Voltage V1L Low Level Input Voltage Vic Input Clamp Voltage VoH High Level Output Voltage VoL Low Level Output Voltage lozH Off-State Output Current
High Level Voltage Applied
lozL Off-State Output Current Low Level Voltage Applied
11
Input Current at
Maximum Input Voltage
l1H High Level Input Current l1L Low Level Input Current los Short Circuit Output Current Ice Supply Current
Conditions
Vee= Min, 11= -18 mA Vee= Min, V1H=2V, V1L=0.8V, loH= Max Vee= Min, V1H=2V, V1L=0.8V,,loL=Max Vee= Max, V1H=2V, Vo=2.4V, V1L=0.8V
Vee= Max, V1H=2V, Vo=0.4V, V1L=0.8V
Vee= Max, V1=5.5V
Vee= Max, V1=2.4V Vcc=,Max, V1=0.4V Vee= Max Vee= Max
Min Typ 2
2.4
Max
0.8 -1.5
0.5 100
Units
v v v v v
µ.A
-100
µ.A
1.0
mA
25
µ.A
-250
µ.A
-30
-130 mA
150 225
mA
(Note 1)
Table 8.11.2 Electrical Characteristics
Symbol
Parameter
Conditions RL=6670
Commercial
TA= 0°C to +75°C
Vcc=5.0V:t5%
Min
Typ
Max
two
WAITIN to WAIT Delay
CL=45 pF
tpo
Clock to Output
CL=45 pF
25
40
15
25
tpzx
Pin 11 to Output Enable
CL=45 pF
15
25
tpxz
Pin 11 to Output Disable
CL=5 pF
15
25
tw
1 Width of Clock High
25
J Low
25
tsu
Set-Up Time
th
Hold Time
Note 1: Ice= max at minimum temperature. Note 2: One output at a time; otherwise 16 mA.
Table 8.11.3
40
0
-15
Switching Chracteristics
Units
ns ns ns ns ns · ns ns ns
...- AOO-AD15 .t
ADO-AD15
ODIN
..
ADS n,,.~ (
NS32032
... ~
DM74LSr G
~"'
AM1·AM20
~~
DM74S139
lo? PERIP ~ A, B,G 1r..1
~ ~ ROM
--"'
l
1 r
cs
.... WIN
@
WR ~I WR
D0-015
I'--+ 81
t'--+ BO
H Q0-6, 7
A0-6, 7
r-+
~
....
C0-6, 7 DP8409
R0-6, 7
ADS
@
RASO ~I RASO"
@
RAS1 ~I RAS1
MM5295·12 MM4164-12
1'?
A16-A22 AO-A15
DP84300
~ M1 RFCK
@
RAS2 ~I RAS2
@
RAS3 ~I RAS3
HBE ~
A16-A23 ROY PHl2 PHl1
I I 1
I + - ROY PHl1 PHl2 ADS CTTL
..... ~ i.
A16-A23"
" AO
NS32201 FCLK NTSO
NCWAIT
NPER
t
PERIP
add butters. @These outputs may need resistors.
to
AO-A23
.----+ RGCK
M2
CS RFSH
.... CTTL AO
.... HBE FCLK NTSO WAIT
' WAITIN
RFl/O t--. RASIN
1
J ...
RFRQ
DP84312
CASL CASH
...,..,..
@ · @!
~··r~. ·i1...
CASL CASH
Figure 8.11.2 System Block Diagram
~
= ~
r!i
~
ct.
= 0
r.J'J ~
\0 \0
200 Programmable Logic Design Guide
Mnemonic Description
Input Signals
CLK
Clock input. This clock comes f~om the FCLK output of the NS32201
timing and control unit, and supplies timing for the internal logic.
RAS input. This input is connected to the NTSO pin of the NS32201 This signal marks the start of a memory cycle.
RFRQ
Refresh request. The DP8409 requests a forced refresh with this input.
HBE, AO
Address select inputs. These inputs select the type of write during a write cycle, and select their respective CAS outputs. These inputs must remain stable throughout the memory cycle.
WAI TIN
This wait input allows other devices to use the NCWAIT line of the NS16201 clock chip.
CTTL
System clock input. This clock is used to synchronize the memory system to the microprocessor clock.
Chip select. This input is used to determine if a memory cycle or a hidden refresh cycle is to be performed.
WAITl
Insert one wait state. This input allows the use of slow memories with a microprocessor using a fast clock by inserting a wait s-tate in selected memory cycles.
Output Signals
RFSH
Refresh. This output switches the DP8409 to a refresh mode.
CASH, CASL
CAS outputs. CASH is for controlling the high bank of dynamic RAMs, while CASL controls the CAS line of the lower bank of RAMs. If only eight RAMs are used in each bank, the CAS outputs will directly drive the memories. For large arrays, these outputs should be buffered with a high current driver, such as the DP84244 MOS driver.
WAIT
This output controls the insertion of wait states. This output is ORed. with WAITIN to allow other devices to insert wait states.
Functional Description
The DP84312 detects the start of a memory cycle when NTSO from the NS32032 timing and control unit (TCU) goes low. The NTSO signal is also used to supply RASIN to the DP8409 dynamic RAM controller. After the DP8409 has latched the row address and supplied the column address to the DRAMs, the DP84312 latches the column
Applications 201
address. The DP84312 supplies two CAS outputs: one for the high byte of memory, and the other for the low byte. The ability to control the upper and lower bytes of memory separately is important during a memory write cycle where one byte of memory is to be written (byte write).
By connecting WAITl of the DP84312 to ground, all selected memory cycles will have one wait state inserted. This allows an NS32032 operating at high CPU clock frequency to use slower dynamic RAMs.
Memory refresh can be achieved in one of two ways: hidden or forced. Hidden refresh is accomplished whenever a refresh is requested (internal to the DP8409) and an unselected memory cycle occurs. With a hidden refresh, the DP84312 does nothing while the DP8409 performs the refresh. If no refresh occurs before the trailing edge of refresh clock, the DP8409 will request a forced refresh. The DP84312 detects this request, and allows the current memory cycle to finish. It then outputs wait states to the CPU, which will hold the CPU if it requests a memory cycle. During this time the DP84312 has switched the dynamic RAM controller to the auto refresh mode, allowing it to perform a refresh. At the end of the refresh cycle, the DP8409 is switched back to the auto access mode, and the wait is removed after a sufficient RAS precharge time. The total forced refresh takes four CPU clock cycles, of which some, none or all may be actual wait states. If the CPU does not request a memory cycle during this refresh cycle, the refresh will not impact the CPU's performance.
The DP84312 can possibly be operated at 8 MHz with no wait states (WAITl = "1 ") given the following conditions:
T2 + T3 = 250 ns NTSO generation= 15 ns max. RASIN to CAS delay DP8409~2 = 130 ns max. External CASH,L generation using 74502 and 745240
7.5 ns (74502) + 10 ns (745240) - 7.5 ns (less load on 8409 CAS line)= 10 ns max. Transceiver delay= 12 ns max. NS 16032 data setup= 20 ns max. .·. Minimum tCAc = 63 ns
= 250 - 15 - 130 - 10 - 12 - 20 Minimum tRAs = 250 ns Minimum tRP = 250 ns Minimum tRAH = 20 ns
The DP84312 is a standard National PAL device part (PAL 16R6). The user can modify the PAL device equations to support his/her particular application. The DP84312 logic equations, function table (functional test), and logic diagram can be seen at the end of this section.
202 Programmable Logic Design Guide
FCLK
1-t1OR t4-\-- t1 -1--t2--j-t3--f-----t4--l-t1OR t1-I
CTTL
NTSO
Li --·
i
L.
CASH,L
DATA
_ > - - - - - - - - - FRO(MR RAMEAD)---------------""""'f(. READ DATA )
DATA
FROM CPU--------c(ADDRESs}-(.
DATA TO BE WRITTEN
)>------
(WRITE)
.
- ""·- - - - - - - - - - - -
Figure 8.11.3 Timing Diagram; Read, Write or Hidden Refresh Memory Cycle for the NS32032-DP8409 Interface
CPU STATE l-t4 OR ii-1---n---1---t2--1-tw---1---t3---j---t4-I 't1 OR t1
NTSO
NC WAIT RAS
CASH,L DATA
) > - - - - - - - FROM R A M - - - - - - - - - - - - - - - - - - - - - c ( VALID
DATA
FROMCPU-------""""(ADDREss){~_ _ _D_At_A_T_o_eE_w_R_IT_T_E_N_T_o_M_E_M_o_R_v_ _ _ _)~----
Figure 8.11.4 Timing Diagram; Read, or Write Memory Cycle With One Wait
Applications 203
t,, t1
t1, t1
t1, T1
T1, t1
t1, t1
CPU STATE I- t1 OR t4 -l-t1 OR t1 -I-OR tH -1-·0R tH - 1 - OR tH - 1 - OR tH - I OR t2
FCLK
__ NTSO ..1.
__ .. ,
RFRQ 1
NC WAIT
RFSH
RAS___ _..I.
Figure 8.11.5 Timing Diagram; Forced Refresh Cycle
PAL16R6 DP84312 Interface Circuit for the NS32032/DP8409 Memory System CK NTSO /RFRQ /HBE AO /WAITIN CTTL /CS /SLOW GND /OE /WAIT ID IC /B IA ICASL /CASH /RFSH VCC
CASH: = A*IB*C*D* HBE*CS + /A*IB*D*HBE*CS
CASL: = A*IB*/C*D*/AO *CS+ /A*IB*D*/AO*CS
A : = /A*IB*/C*ID*INTSO*CS*SLOW +
B*/C*ID + A*/C*ID +
A*B B : = /A*IB*/C*ID*NTSO*RFRQ*CTI1. +
/A*B + A*B*/C + B*C*D
LI ---·
I
I
L--
204 Programmable Logic Design Guide
C : = /A*IB*/C*ID*NTSO*RFRQ*C1TL + /A*IB*D + A*B*D + B*C*ID +
IA*IB*C*ID*INTSO
D : = /A*IB*/C*ID*INTSO*CS*/SLOW + /A*IB*/C*ID*INTSO*/CS + A*/C + IB*/C*D .+
/A*B*C
IF (VCC) WAIT = IB*/C*ID*/NTSO*CS*SLOW + /A*B*D + B*/C*ID + A*B + A*C*ID +
/CS*WAITIN
IF (VCC) RFSH = /A*B + B*/C*ID + A*B*/C +
A*B*C
Applications 205
CK NTSO RFRQ HBE AO WAITIN CTTL cs SLOW OE CASH CASL A B c D WAIT RFSH
c H c H c L c L c x
c H c L
c x
c x
c x
c. x c H c L
c x c H
c H c H c H c H c H c H
c H c H
c H c H c H c L
c L
c L
c L
c H c H
H LL H
H
L L
H
x LL H
x LL x LL x LL x· L H
H H H H
x LH H
x LH H x LH H
x LH H
x LL H
x x
L L L L
H L
x LL H
x LL H
L xx H
x xx H
H xx H
H xx H
H xx H
H xx H
H xx H
H xx H
H xx H
H xx H
H xx L
H xx L
H xx L
x x
x x x x
H H
H HH H
HH H L x
HH H L L
xL H L L
xL H L H
xL H L H
xL H L L
xL L L L
xL L L L
xL L L H
xL L L H
xL L L H
xH H L L
xH x L L
xH x L L
xH x L L
x· H x L L
Hxx L L
Lxx L L
Hxx L L
LxxL L
Hx x L L
LxxL L
Hxx L L
LxxL L
Hxx L L
xH H L L
x x
H H
x x
L L
L L
xH x L L
xH x L L
xH x L L
HH H Hz
x xxxx x x
L LLLL L
L
L LLLH L
L
H L LHH L
L
H LLHL L
L
L L L L. L L
L
L HLLL H
L
L HLLH L
L
L LLLH L
L
L L L H H L ,L
L LLHL L
L
L LLLL L
L
L LLLH L
L
L L LHH H
L
L LLHL L
L
L LLLL L
L
L LHHL L
H
L LHHH H
H
L LHLH H
H
L LHLL H
H
L HHL L H
H
L HHLH H
H
L HHHH H
H
L HHHL H
L
L HLHL H
L
L LLLL L
L
L LLLH H
L
L L LHH H
L
L LLHL H
L
L LLHL L
L
L LLLL L
L
z zzzz z z
Table 8.11.4 Function Table
206 Programmable Logic Design Guide
T--1> CK 0 1 2 3
NTSO 2
RFRQ 3
0 1 2
· 3
s
I 7
~ ...--
· I
10 11 12 13 14 15
....;.;t
HBE
-4
u :i 'C
2
CL
AO 5
16 17 11 19 20 21 22 23
......L.
24 25 26 27 21 29 30
...... 31 ;JJt
32 33 34 35
36 37 38 39
WAITIN...,
6 ...~
40 41 42 43 44 45 46 47
. CTTL·...._ .Jk·
7
41
49
50
51
52
53
54
55
cs
8
......L..-
56 57
58
59 60 61 62 63
- SLOW""'
~ 9 ~ ....
0 123
4U7 4 5 6 7
Inputs (0-31)
111011 12131415 11171111 20212223 24212127 0213031
191011 12131415 16171819 20212223 24252627 28293031
,.....
~l ~
~ ~
~
...@ eoI
RFSH 19
1['.....t. -----'
......
~
.../ ......
~--H
~ ~
,_
~
....
~~17
3C,:...,.
,......
II-
0 ~
~
......
"IC"". "'
........
H
...~ ~
~
../
~
;~:,,,
....
~ ~ ~ ~
Ji[......
............... 1"""'-\-~ ../
~ .A
~ .....,...,.
~ ~
......
).-C
III-
~
IE:l
~..........
~ ~
........
1-( lo-(
1-c 1-c 1-( 1-( 1....-...(..
*.:J
~
WAIT 12
~11
Figure 8.11.6 DP84312 Logic Diagram PAL16R6
Applications 207
8.12 DP84322 DYNAMIC RAM CONTROLLER INTERFACE CIRCUIT FOR THE 68000 CPU
General Description
The DP84322 dynamic RAM controller interface is a PAL device for interface between the DP8409 dynamic RAM Controller and the 68000 microprocessor.
The DP84322 supplies all the control signals needed to perform memory read, write and refresh. Logic is included for inserting a wait state when using fast CPUs.
Features
· Provides 3-chip solution for the 68000 CPU and dynamic RAM interface. · Works with all 68000 speed versions. · Possibility of operation at 8 MHz with no wait states. · Performs hidden refresh.
DUAL-IN-LINE PACKAGE
CLOCK
20 Vee
AS 2
19 RASIN.
UDS 3
18 DTACK
LOS 4
17 RFSH
R/W 5
16 NC
RFRQ 6
15 NC
CAS 7
14 NC
cs 8
13 CASU
WAIT 9
12 CASL
G_ND 10
11 OE
TOP VIEW
Figure 8.12.1 Connection Diagram
208 Programmable Logic Design Guide
· DTACK is automatically inserted for both memory access and memory refresh.
· Performs forced refresh using typically 4 CPU clocks.
· Standard National Semiconductor PAL device part (PAL16R4).
· PAL device logic equations can be modified by the user for his specific application and programmed into any of National's PAL device family, including the new high speed PAL devices.
AS
_..
--....
--
RASIN
_-..... GENERATOR
-_..... RASIN
LOS UDS
_....... __.....
-
CAS
.......... CASL
CAS
_..... GENERATOR
_._.... CASU
R/W WAIT
~I
...........
- - ~ _.....
._-..............
DTACK GENERATOR
..-.,.......
r+I
_..
--.... DTACK
---...........
REFRESH/ ACCESS
ARBITRATION
_..
--....
LOGIC
__..... M2 (RFSH)
Figure 8.12.2 Block Diagram
Applications 209
Symbol Vee loH loL TA
Parameter Supply Voltage High Level Output Current
Low Level Output Current
Operating Free Air Temperature
Min
Typ
Max
4.75
5.00
5.25
-3.2
24 (Note2)
0
75
Table 8.12.1 Recommended Operating Conditions
Units
v
mA
mA
oc
Symbol
Parameter
V1H High Level Input Voltage V1L Low Level Input Voltage Vic Input Clamp Voltage VoH High Level Output Voltage Vol Low Level Output Voltage lozH Off-State Output Current
High Level Voltage Applied
Conditions
Vee= Min, 11= -18 mA Vee= Min, V1H=2V, V1L=0.8V, loH=Max Vee= Min, V1H = 2V, V1L = 0.8V,·loL =Max Vee= Max, V1H= 2V, Vo=2.4V, V1L=0.8V
Min Typ 2
2.4
Max
0.8 -1.5
0.5 100
Units
v v v v v
µA
lozL Off-State Output Current Low Level Voltage Applied
11
Input Current at
Maximum Input Voltage
Vee,,;, Max, V1H=2V, Vo=0.4V, V1L=0.8V Vee= Max, V1=5.5V
-100
µA
1.0
mA
l1H High Level Input Current
Vee= Max, V1=2.4V
l1L Low Level Input Current
Vee= Max, V1=0.4V
las Short Circuit Output Current Vee= Max
Ice Supply Current
Vee= Max
25
µA
-250
µA
-30
-130
mA
150 225 mA (Note 1)
Table 8.12.2 Electrical Characteristics
Symbol
Parameter
tpo
Input to Output
tpo
Clock to Output
tpzx
Pin 11 to Output Enable
tpxz
Pin 11 to Output Disable
tpzx
Input to Output Enable
tpxz
Input to Output Disable
tw
Width of Clock
} High Low
tsu
Set-Up Time
th
Hold Time
Note 1: Ice= max at minimum temperature. Note 2: One output at a time; otherwise 16 mA.
Table 8.12.3
Test Conditions RL=667fl
CL =45 pF
CL= 5 pF CL =45 pF CL =5 pF
Commercial
TA= 0°C to + 75°C
Vee= 5.0V ±5%
Min
Typ
Max
25
40
15
25
15
25
15
25
25
40
25
40
25 25
40
0
-15
Switching Characteristics
Units
ns ns ns ns ns ns ns ns ns ns
A1-A23
68000
r-+ DrAcK
00-015
..ii ~
ii" "'11111
ADDRESS_ BUS
"'"'I
ADDRESS ] DECODER
AS ~~
DP84322 and DP8409 for 68000 CPU
.,..... R0-6, 7, 8
..,....... C0-6, 7, 8
- · · 00-6. 7. 8 *......... RASO *..,, .·...·..·
,.... BO
...; B1
WE *...A....A...A.
Vee
L... ADS
...; cs
RAS1 .*.,.,.,.,.,.,..
OM74LS393 1'.._
OP8409 ..;. RFCK
CLK
.... 10 MHz MAX ... RGCK
RAS2 *...............
R/W
...; WIN
_.....
...,..
A0-6, 7, 8 D1N
"""'.....
-! RAS
_.. CASU
-! CASL .
=: WE
Dour
.....,.....
~· ..it A0-6. 7. 8 D1N ......
_.. RAS
=:, CASU
.... CASL
~WE
Dour
..,......
~*~~
~·
A0-6, 7, 8
DIN
.....
~
_.,, RAS
-!' CASU
_. CASL ... WE
Dour
.....,.....
L+I cs VRASIN l.......+I A5 RFSH
_... RtW
..;. RASIN
~ M2 (RFSH)
o- Ml
3 >
RAS3 *..A. 'AI',A, .
~ ,,4_ A0-6. 7. 8 D1N ................. RAS
UDS
.. uos
1~ MO
_...... CASU
LOS
~ LOS OP84322
...; CAS
__. r-+I AFRO DTACK ~ WAIT CASU
AFRO
CAS ~
_... CASL _... WE
Dour
._.,.....
:1....... DP84244
DRAMS
CASL
~L
POE
DATA BUS
BUFFER NECESSARY IF MORE THAN ONE BANK
·These outputs may need resistors.
"Ill ~
Figure 8.12.3 System Block Diagram
N
~
<:>
f
;~-
t""4
. 0
~
(')
t='
~ rlJ
~·
@ ·.
~
Applications 211
Mnemonic Description
Input Signals
CLOCK
The clock signal determines the timing of the outputs and should be connected directly to the 68000 clock input.
Address Strobe from the 68000 CPU. This input is used to generate RASIN to the DP8409.
Upper and lower data strobe from the 68000 CPU. These inputs, together with AS, R/W, provide DTACK to the 68000.
R/W
Read/write from the 68000 CPU, when WAIT = 0. Selects processor
speed when WAIT= 1 (" l" = 4, to 6 MHz, "O" = 8 MHz).
Column Address Strobe from the DP8409. This input, together with LDS and UDS, provides two separate CAS outputs for accessing upper and lower memory data bytes.
Chip Select. This input enables DTACK output. CS = 0, DTACK output is enabled; CS= 1, DTACK output is TRI-STATE®.
RFRQ
Refresh Request. This input requests the DP84322 for a forced refresh.
WAIT
This input allows the necessary wait state to be inserted for memory access cycles.
Output Signals
RASIN
CASU, CASL
This output provides a memory cycle start signal to the DP8409 and provides RAS timing during hidden refresh.
These signals are the separate CAS outputs needed for byte writing.
DTACK
This output is used to insert wait states into the 68000 memory cycles when selected and during a forced refresh cycle where the CPU attempts to access the memory. This output is enabled when CS input is low and TRI-STATE when CS is high.
RFSH
This output controls the mode of the DP8409. It always goes low for 4 CPU clock periods when AS is inactive and' a forced refresh is requested through RFRQ input. This allows the DP8409 to perform an automatic forced refresh.
Functional Description
As a 68000 bus cycle begins, a valid address is output on the address bus Al-A23. This address is decoded to provide Chip Select (CS) to the DP8409. After the address becomes valid, AS goes low and it is used to set RASIN low from the DP84322 interface
212 Programmable Logic Design Guide
circuit. Note that CS must go low for a minimum of 10 ns before the assertion of RASIN for a proper memory access. As an example, with an 8 MHz 68000, the address is valid for at least 30 ns before AS goes active. AS then has to ripple through the DP84322 to produce RASIN. This means the address is valid for a minimum of 40 ns before RASIN goes low, and the decoding of CS should ·rake less than 30 ns. At this speed the DM74LS138 or DM74LS139 decoders can be selected to guarantee the 10 ns minimum required by CS set-up time going low before the access RASIN goes low(tcsRL of the DP8409). This is important because a false hidden refresh may take place when the minimum tcsRL is not met.
Typically RASIN occurs atthe end of S2. Subsequently, selected RAS output, row to column select and then CAS will automatically follow RASIN as determined by mode 5 of the DP8409. Mode 5 guarantees a 30 ns minimum for.row address hold time (tRAH) and a minimum of 8 ns column address set-up time (tAsc). If the system requires instructions that use byte writing, then CASU and CASL are needed for accessing upper and lower memory data bytes, and they are provided by the DP84322. In the DP84322, LDS and UDS are gated with CAS from the DP8409 to provide CASL and CASU. Therefore, designers need not be concerned about delaying CAS during write cycles to a~sure valid data being written into memory. The 8 MHz 68000 specifies during a write cycle that data output is valid for a minimum of 30 ns before DS goes active. Thus, CASL and CASU will not go low for at least 40 ns after the output data becomes stable, guaranteeing the 68000 valid data. is written tQ memory.
-errs Furthermore, the gating of UDS, and CAS allows the DP84322 interface con-
troller to support the test and set instruction (TAS). The 68000 utilizes the read-modify-write cycle to execute this instruction. The TAS instruction provides a method of communication between processors in a multiple processor system. Because of the nature of this instruction, in the 68000 this cycle is indivisible and the Address Strobe AS is asserted through the entire cycle. However, DS is asserted twice for two accesses: a read then a write. The dynamic RAM controller and the DP84322 respond to this read-modify-write instruction as follows (refer to the TAS instruction timing diagram for clarification). First, the selected RAS goes low as a result of AS going low, and this RAS output will remain low throughout the entire cycle. Then the DP84322's selected CAS output (CASL or CASU) goes low to read the specified data byte. After this read, DS goes high causing the selected CAS to go high. A few clocks later R/W goes low and then DS is reasserted. As DS goes low, the selected CAS goes low strobing the CPU's modified data into memory, after which the cycle is ended when AS goes high.
The two CAS outputs from the DP84322 however, can only drive one memory bank. For additional driving capability, a memory driver such as the DP84244 should be added to drive loads of up to 500 pF.
Since this DP84322 interface circuit is designed to operate with all of the 68000 speed versions, a status input called WAIT is used to distinguish the 8 MHz from the others. The WAIT input should be set low for a 6 MHz or· less allowing full speed of operation with no wait states. Data Transfer Acknowledge input (DTACK) of the 68000 at these speeds is automatically inserted during S2 for every memory transaction cycle
Applications 213
and is then negated at the end of that cycle when UDS and/or LDS go high. For the 8 MHz 68000 however, a wait state is required for every memory transaction cycle. At these speeds, the WAIT input is set high, selecting the DP8409's CAS output to generate DTACK and again DTACK is negated at the end of the cycle when UDS or LDS goes high. Note that DTACK output is enabled only when the DP8409's CS is low. Therefore when the 68000 is accessing 1/0 or ROM (in other words, when the DP8409 is not selected), the DP84322 's DTACK output goes high impedance logic 'I' through the external pull-up resistor and it is now up to the designer to supply DTACK for a proper bus cycle.
Table 8.12 .4 indicates the maximum memory speed in terms of the DRAM timing parameters: tcAc (access-time from CAS) and tRP (RAS precharge time) required by different 68000 speed versions.
Microprocessor Clock
8 MHz 6 MHz 4 MHz
Maximum tcAC
125 ns 90 ns 270 ns
Minimum tRP
140 ns 170 ns 280 ns
Table 8.12.4 Memory Speed
Minimum tRAS
220 ns 290 ns 450 ns
Pin 5 (R/W input to the DP84322) is not used as R/W when the WAIT input is high. Therefore, when WAIT is high and pin 5 is low, this is configured for the 8 MHz 68000. The dynamic RAM controller in this configuratfon operates in mode 5 and mode 1.
When both WAIT and pin 5 are high, this is configured for 4 MHz and 6 MHz 68000, allowing only two microprocessor clocks for memory refresh. Furthermore, the designer can use the DP8408 because the dynamic RAM controller now operates in mode 0 and mode 5 or mode 6. In addition, the.programmable refresh timer, DP84300, should be used to determine the refresh rate (RFCK) and to provide the refresh request (RFRQ) input to the DP84322. The refresh timer can provide over two hundred different divisors. RFRQ is given at the beginning of every RFCK cycle arid remains active until M2 goes low for memory refresh. The DP84322 samples RFRQ when AS is high, then sets M2 low for two microprocessor clocks, taking the DP8408 or DP8409 to the external control refresh mode. RASiN for this refresh is also issued by the DP84322. If a memory access is pending, RASIN for this access will not be given until it is delayed for approximately one microprocessor clock, allowing RAS precharge time for · the dynamic RAMs.
214 Programmable Logic Design Guide
The following table indicates different memory speeds in terms of the DRAM parameters required by 4 MHz and 6 MHz 68000:
Microprocessor Clock
4 MHz' 6 MHz
Maximum
tcAc·
290 ns 110 ns
Minimum
tRAS
200 ns 125 ns
Minimum
tRP
225 ns 140 ns
Minimum
tRAH
20 ns 20 ns
Table 8.12.5 Memory Speed of 68000
When WAIT= 1, pin 5 = 0 (8 MHz), the PAL device controller supports read and write cycles with one inserted wait state, forced refresh with five wait states inserted if CS is valid, and hidden refresh. This PAL device mode does not support the TAS instruction.
When WAIT ~ pin 5 = 1 (4-6 MHz), the PAL device controller supports read and write cycles with no wait states inserted, and forced refresh with two wait states inserted if CS is valid. This PAL device mode does not support the TAS instruction and only supports hidden refresh when used in mode 5 with the DP8409 controller.
The DP84322 can possibly be operated at 8 MHz with no wait states (WAIT= "O") given the following conditions:
FAST PAL DEVICE (PAL 16R4A) S2 + S3 + S4 +SS = 250 ns RASIN delay = 60 ns (AS low max.)
+ 25 ns (Fast PAL delay)= .85 ns max. RASIN to CAS delay DP8409-2 = 130 ns max. External CASH,L generation using 74S02
and 74S240 7.5 ns (74S02) + 10 ns.(74S240) - 7.5 ns (less load on 8409 CAS line)= 10 ns max. Transceiver delay (74LS245) = 12 ns max. 68000 data setup into S6 = 40 ns min. : . Minimum tCAc = 53 ns
= 250 - 85 - 130 - 10 - 12 + 40 Minimum tRAs = 240 ns Minimum tRP = 150 ns Minimum tRAH = 20 ns
Refresh Cycle
Since the access sequence timing is automatically derived from RAS IN in mode 5, R/C and CASIN are not used and now become Refresh Clock (RFCK) and RAS-generator
Applications 215
clock (RGCK) respectively. The Refresh Clock RFCK may be divided down from RGCK, which is the micropocessor clock, using the DM74LS393 or DM74LS390. RFCK provides the refresh time interval and RGCK the fast clock for all-RAS refresh if forced refreshing is necessary. The DP8409 offers both hidden refresh in mode 5 and forced refresh in mode 1 with priority placed on hidden refreshing. Assume 128 rows are being refreshed, then a. 16µs maximum clock period is needed for RFCK to distribute refreshing of all the rows over the 2 ms period.
The DP8409 provides hidden refreshing in mode 5 when the refresh clock (RFCK) is high and the microprocessor is accessing RAM. In other words, when the DP8409's chip select is inactive because the microprocessor is not accessing elsewhere, all four .RAS outputs follow RAS IN, strobing the contents. of the on-chip refresh counter to every memory bank. RASIN going high terminates the hidden refresh and also increments the refresh counter, preparing it for the next refresh cycle. Once a hidden refresh has taken place, a forced refresh will not be requested by the DP8409 for the current RFCK cycle.
However, if the microprocessor continuously accessed the DP8409 and memory while RFCK was high, a hidden refresh could not have taken place and now the system must force a refresh. Immediately _after RFCK goes low, the Refresh Request signal (RFRQ) from the DP8409 goes low, indicating a forced refresh is necessary. First, when RFRQ goes low any time during S2 to 57, the controller interface circuit waits until the end of the current memory access cycle and then sets M2 (RFSH) low. This refresh takes four microprocessors clocks to complete. If the current cycle is another memory cycle, the 68000 will automatically be put in four wait states.
Alternately, when RFRQ goes low while AS is high during SO to S1, M2 is now set low at 52. Therefore, it requires an additional microprocessor clock for this refresh. Once the DP8409 is in mode 1 forced refresh, all the RAS outputs remain high until two RGCK trailing edges after M2 goes low, when all RAS outputs go low. This allows a minimum of one and a half clock periods of RGCK for RAS precharge time. As specified in the DP8409 data sheet, the RAS outputs remain low for two clock periods of RGCK. The refresh counter is incremented as the RAS outputs go high. Once the forced refresh has ended, M2 is brought high, the DP8409 back to mode 5 auto access. Note that RASIN for the pending access is not given until it has been delayed for a full microprocessor clock, allowing RAS precharge time for the coming access.·
If the 68000 bus is inactive (i.e., the 68000's instruction queue is full, or the 68000 is executing internal operations such as a multiply instruction, or the 68000 is in half state ... ) and a refresh has been requested, a refresh will also take place because RFRQ is continuously sampled while AS is high. Therefore, refreshing under these conditions will be transparent to the microprocessor. Consequently, the system throughput is increased because the DP84322 allows refreshing while the 68000 bus is inactive.
The 84322 is a standard National P~ device part (PAL16R4). The user can modify the PAL equations to support his particular application. The 84322 logic equations, function table, and logic diagram can be seen at the end of this section.
216 Programmable Logic Design Guide
CLOCK
68000 MEMORY READ CYCLE (WAIT= 0, PIN 5 = R/W)
A1·A23
OUTPUTS FROM 68000
AS
UDS, LOS
RiW
H "-----------v.-~_L_io_A_o_o_R_E_s_s__________--')~-----
RASIN
OUTPUTS FROM
DP843~2
RFSH DTACK
CASU, CASL
RASO~
RAS3
QO-Q8
OUTPUTS FROM
DP8409
CAS WE
SELECTED RAS. OUTPUT
COLUMN ADDRESS
RFRQ
tcAC -I
toFF:1
DRAM OUTPUT
-----------------------....:.----.....c(
MEMORY DATA
'j---
Figure 8.12 .4 Timing Diagram; 68000 Memory Read Cycle
CLOCK
Applications 217
MEMORY READ CYCLE ANO FORCED REFRESH (WAIT= 1, PIN 5 = 0)
f - OP84322 DETECTS START OF CYCLE, SO INSERTS REFRESH CYCLE -
I- I OP84322 CONTINUES
MEMORY ACCESS CYCLE-
AO-A15
OUTPUTS FROM 68000
AS UOS,LOS
RJW
RASIN
OUTPUTS FROM
OP84322
RFSH DTACK
4 µP CLOCK PERIODS
CASU, CASL
_ _ _ _ _ _ _ _ _ _ _ _. . . . , . , . . . . _ A L L
RASORAS3
RAS OUTPUTS
ao-as
REFRESH ADDRESS
OUTPUTS FROM
OP8409
CAS WE
RFRQ
ORAM OUTPUT
MEMORY DATA
Figure 8.12.5 Timing Diagram; 68000 Memory Read Cycle and Forced Refresh
218 Programmable Logic Design Guide
TAS INSTRUCTION CYCLE (WAIT= O, PIN 5 = RIW)
so
S1
S4
S6
SS S10 . S12 514 S16 S18 SO
CLOCK
J--<_________ A1-A23
S2 sa ·ss S7 S9 S11 S13 S15 S17 S19
A_o_o_R_Es_s_ _ _ _ _ _ _ _ _} -
OUTPUTS FROM 68000
UDS, LOS
RiW
RASIN
OUTPUTS FROM
DP84322
RFSH' DTACK
CASU, CASL
RASO· RAS3
QO-QS
OUTPUTS FROM
DP8409
CAS WE
RFRQ
DRAM OUTPUT
to FF
SELECTED RAS 'OUTPUT COLUMN ADDRESS
CPU DATA
Figure 8.12.6 Timing Diagram; TAS Instruction Cycle
Applications 219
MEMORY READ CYCLE (WAIT= 1, PIN 5 = 0)
CLOCK
==>---< A1·A23
......______________A_o_o_R_E_s_s _____________~)>------
g (J)
!;
=~=
0
f: II. co
:::>
0
AS
uos, LOS
RiW
RASIN
!(J);=~= a~
g.a.... "- aa.o. Q
RFSH DTACK
CASU, CASL
RASORAS3
(J)
!;
=~ =
0)
:
!;0..11.
a..
Q
0
QO-QB CAS WE
---tcAc-
SELECTED RAS OUTPUT
COLUMN ADDRESS
DRAM
MEM
OUTPUT---------------------------------------c.___o_A_T_A _~
Figure 8.12.7 Timing Diagram; Memory Read Cycle
220 Programmable Logic Design Guide
(WAIT= 1, PIN 5 = 0)
DP84322 DETECTS
I START OF CYCLE, so
-INSERTS REFRESH CYCLE -
I DP84322 MEMORYCONTINU~
-- ACCESS CYCLE I
INPUTS FROM 68000
ALL RAS OUTPUTS REFRESH ADDRESS
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - c : M E M ODARTAY
Timing Diagram; Memory Read Cycle and For'ced Refresh
A1-A23 AS
68000 CLK
r-+ DTACK
RiW
UDS
~
LOS
DO-D15
~
DP8408, DP8409 AND 68000 INTERFACE
ADDRESS BUS
,.."Ill
J ADDRESS
DECODER
IT I
RFRQ
.-..,..... R0-6, 7, 8
r-+ C0-6, 7, 8
I--+ BO
L...........+ B1
00-6, 7, 8 ,.*.A,,A,,.A, .
RASO
*AAA
"YYT
WE .*.A.,,.,A,,A, .
,.. ADS
.. cs
RAS1 .*..A,,A,,,A, .
DP8408/9
DP84300 }·M2
-6.
"1"t CASIN
RAS2 *-yAy.AVA
RIC
*WIN
......
-,.
A0-6, 7,8
D1N
....t
....-
---: RAS
__... CASU
....,. CASL __... WE Dour
~ A0-6, 7,8
D1N
....t
....-
*RAS --.. CASU ~ CASL
-: WE
Dour
> r-+ .~
.A
A0-6, 7,8 0 1N ....-
__... RAS
....,. CASU
· CASL ~ WE Dour
L+ cs VRASIN
.. RASIN
~ AS
. "1"-+ RiW __... UDS
MODE.{_; RFSH
,
M2 (RFSH)
M1
SOR 6 - + MO
__..... LOS DP8.!'~22
r
*~ CAS RFRQ DTACK ~
"1"_. WAIT CASU
~ OE
CASL
DATA BUS
:~
... .~
-. RAS3 *AAA.
CAS I -
~ .... A0-6, 7,8 0 1N ~
,... RAS ~ CASU ~ CASL *WE
Dour
__.....
_:1
,..L
DP84244
DRAMs
BUFFER NECESSARY IF MORE THAN ONE BANK
.-..,.... ...Ii.i,...
..I,ii....
....
-,..
"'II~
*These outputs may need resistors.
Figure 8.12.9 Modified System Block Diagram
~
= ~
Q
Q'.
a 0
N N lo-I
222 Programmable Logic Design Guide
CLOCK
68000 MEMORY READ CYCLE (WAIT AND PIN 5=1).
- - - - ADDRESS ->--C
COLUMN ADDRESS
--------------------------------....c;(MEMORYDATA)>-------
Figure 8.12.10 Timing Diagram; 68000 Memory Read Cycle
Applications 223
68000 MEMORY READ CYCLE AND MEMORY REFRESH (WAIT AND PIN 5 = O)
DP84322 DETECTS
I START OF CYCLE SO
I~ DP84322 CONTINUES __.J
INSERTS REFRESH CYCLEr--MEMORY ACCESS CYCLE------i
END WAIT STATE
~OF~
(1-tcAC-
SELECTED RAS OUTPUT
COLUMN ADDRESS
-ic::>-------------------------------------1.MEMORYDATA
Figure 8.12.11 Timing Diagram; 68000 Memory Read Cycle and Memory Refresh
224 Programmable Logic Design Guide
PAL 16R4 DP84322 Dynamk RAM Controller Interface for the MC68000-DP8409 Memory System CK/AS IUDS /IDS R/RFRQ /CAS /CS WAIT GND /OE /CL /CU IC IB IA /RFSH /DTACK /RASIN VCC
IF (VCC) RASIN = AS*RFSH*/A +
RFSH*R*A*WAIT
IF (CS) DTACK = IR*CAS*WAIT + UDS*/A*IB*/WAIT + LDS*/A*IB*/WAIT + AS*IR*/A*IB*WAIT +
AS*IRFSH*R*/A*IB*WAIT
RFSH: = /AS*RFRQ + RFSH*IR*/C*WAIT + RFSH*R*/A*WAIT +
RFSH */C*IWAIT
A:= RFSH B:= A C: = B IF (VCC) CU = UDS*CDS IF (VCC) CL = LDS*CAS
Applications 225
jcK AS UDS LOS R RFRQ CAS cs WAIT OE CL cu c Ii A. RFSH DTACK RASIN
cH L L H H cH L L H H
H L
H H
L L
L H H xxx L L L xxx
x x
x x
H H
C' H L H H H
cH H L H H
L H L L H L xxx x L H L L L H xxx x
x x
H H
cH H H H H
H H L L H H HHH H
z
H
cL L H H H
H L L L H H HHH H
L
L
cL L H H H
L L L. L H L H H H H
L
L
cL H H H H
L L L L H H HHH H
H
L
cL H H L H
L L L L H H HHH H
L
L
c L ·L H L H
L L L L H L ·H H H H
L
L
cH H H L H
H L L L H H HHH H
H
H
cH H H L L
H L L L H H HHH L
H
H
cH H H L
L
H L L L H H HHL L
H
H
cL H L L H
H L L L H H HLL L
H
H
cL H L L H
H L L L H H LLL L
H
H
cL H L L H
H L L L H H LLL H
H
H
cL H L L H
H L L L H' H L L H H
H
L
cL H L L H
L L L L L H L HH H
L
L
cL H L L H
L L L L L H HHH H
L
L
cH H H L H
L L L L H H HHH H
H
H
cH H H L
L
H L H L H H HHH L
H
H
cH H
H L
L
H L H L H H HHL L
H
H
cL L
L L
H
H L H L H H HLL L
H
H
cL L
LL H
H L H L H H LLL L
H
H
cL L
LL H
H L H L H H LLL H
H
H
cL L
LL H
H L H L H H LLH H
H
L
cL L L L H
L L H L L L L HH H
L
L
cH H H L H
L L H L H H HHH H
L
H
cH H H L H
H H H L H H HHH H
z
H
cH H H H L
H L H L H H HHH ~
H
H
cH H H H L
H L H L H H HHL L
H
L
cL L H H H
H L H L H H HL L H
H
H
cL L H H H
H L H L H H ·L L H H
H
L
cL L H H H
L L H L H L L HH H
L
L
cH H H H H
L L H L H H HHH H
H
H
cH H H H H
H L H H H H zzz z
H
H
Table 8.12.6 Function Table
226 ·Programmable Logic Design Guide
CLOCK
1
D1 2 3
D I 2
3 4
5 I 7
~
2 p
· 9
ID 11 12
13 14 15
uos .... 3 ..~
4 5. 7
- Inputs (0 31)
111011 12131415 11171111 2D21l2l3 24252127 · 21213031
-1-
- ~- "'IA
IA IA IA
LQ.
~ - ...
- ~ ............
~
w~:..
~ ... .
RASIN 19
DTACK 18
16 17 18 19 20 21 22 23
Los .... 4 ..~
~
. ,
1-o
i-. i--.
..._....
~
~--H Q 17 Q
24
M'
co
e I
25
26 27
28 29
Cl)
30
§
~
RIW .... 5 ...;'If_
31
u 32
="O
33
e 34
a.
35 36
37
38
39
RI~
6 ..
~
)
...
~
~
"j"'
...
"'Z~
flil-
~ 16
~~15
40 41 42 43 44 45 46 47
AS"" 7 r~ ·v
41 49
50 51
52 53 54
cs .... 55
8 ~~
.. w.~IT .... ~ 9
56 57 51 59 6lJ 11 12 13
0I 23
4 5 6 7
~
~
~ ~
-)...
*7G:
14'
~
.1"-."4."
14 ~
tt.
~
I 91011 12131415 16171119 20212223 24252627 21293031
_;/
~......
~~14
s
CASU 13
... ~
s ~
CASL 12
~11
Figure 8.12.12 DP84322 Logic Diagram PAL Device 16R4
Applications 227
8.13 DP84332 DYNAMIC RAM CONTROLLER INTERFACE CIRCUIT FOR THE 8086 AND 8088 CPUS
General Description
The DP84332 dynamic RAM controller interface is a PAL device for interface between the DP8408 dynamic RAM controller and the 8086 and 8088 microprocessors. No wait states are required for memory access. Memory refreshing may be hidden (no wait states) or forced (up to three wait states).
The DP84332 supplies all the control signals needed to perform memory read, write and refresh. Logic is also included to insert a wait state when using slow memory.
CLOCK
Dual-In-Line Package 20 Vee
AO 2
19 NC
BHE 3
18 NC
cs 4
17 NC
ALE 5
16 RFSH
RFCK 6
15 ROY
AWAIT 7
14 CASH
RFRQ 8
13 CASL
NC 9
12 RASIN
GND 10
11 OE
TOP VIEW
TL/F/5000-1
Figure 8.13.1 Connection Diagram
228 Programmable Logic Design Guide
Features
· Low parts count controller for the DP8408/DP8409. · Works with 8086 systems configured in min or max mode. · Performs hidden refresh using the DP8408 dynamic RAM controller. · Compatible with both the 8086 and 8088 microprocessors. · Capable of working at all CPU clock frequencies up to 8 MHz. · Standard National Semiconductor PAL device part (PAL16R8). · PAL device logic equations can be modified by the user for his specific application
and programmed into any of the PAL devices in the National Semiconductor family, including the new high speed PAL devices.
BHE---------------.1 A O - - - - - - - - - - - - - -. . .· GENCERAASTOR
CASH CASL
AWAIT--+ COUNTER
RASIN GENERATOR
------+----· RDY1
C S - - - - - - - - - - - - - -. . . 1 A L E - - - - - - - - - - - - - -. . . 1
RFRQ -----------_,.·
REFRESH REQUEST
RFCK --------------,..· ENCODER
TLIF/5000-2
Figure 8.13.2 Block Diagram
Applications 229
Symbol Vee loH loL TA
Parameter Supply Voltage High Level Output Current
Low Level Output Current
Operating Free Air Temperature
Min
Typ
Max
4.75
5.00
5.25
-3.2
24 (Note2)
0
75
Table 8.13.1 Recommended Operating Conditions
Units
v
mA
mA
oc
Symbol V1H V1L Vic VoH Vol lozH
lozL
11.
l1H l1L las Ice
Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Off-State Output Current High Level Voltage Applied Off-State Output Current Low Level Voltage Applied Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current
Conditions
Vee= Min, 11= -18 mA Vcc=Min, V1H=2V, V1L=0.8V, loH=Max Vee= Min, V1H=2V, V1L=0.8V, IOL= Max Vcc=Max, V1H=2V, Va=2.4V, V1L=0.8V
Vcc=Max, V1H=2V, Va=0.4V, V1L=0.8V
Vee= Max, V1=5.5V
Vee= Max, V1=2.4V Vee= Max, V1=0.4V Vee= Max Vee= Max
Min 2 2.4
-30
Table 8.13.2 Electrical Characteristics
Typ Max
0.8 -1.5
0.5 100
Units
v v v
v v
µA
-100 µA
1.0 mA
25 µA -250 µA
-130 mA
150 225 mA (Note 1)
Symbol
Parameter
tpo
Clock to Output
tpzx
Pin 11 to Output Enable
tpxz
Pin 11 to Output Disable
tw
l Width of Clock
High
l Low
tsu
Set-Up Time
tH
Hold Time
Note 1: Ice= max at minimum temperature.
Note 2: One output at a time; otherwise 16 mA.
Conditions RL=6670
CL:45pF CL=45 pF CL= 5 pF
Commercial
TA= 0°C to + 75°C
Vee= 5.0V ~ 5%
Min
Typ
Max
15
25
15
25
15
25
25 25
40
0
-15
Table 8.13.3 Switching Characteristics
Units
ns ns ns ns ns ns ns
230 Programmable Logic Design Guide
Mnemonic Description
Input Signals
CLOCK
The CLOCK signal determines the timing of the outputs and should be connected directly to the 8086 clock.
AO, BHE
These inputs come from the 8086 CPU. They must remain stable during the memory cycle for proper operation of the CAS outputs.
Chip enable. This input is used to select the memory and enable the hidden refresh logic.
ALE
Address latch enable. This input is used to i~dicate the beginning of a
memory cycle.
RFCK
Refresh clock. The period of this input determines the refresh interval. The duty cycle of this clock will determine the length of time that the circuit will attempt a hidden refresh.
AWAIT
When connected to VCC, the DP84332 will insert an extra wait state in selected memory cycles.
Refresh request. This input requests the DP84332 to perform a refresh. The state of the RFCK input will determine what type of refresh will be performed.
Output Signals
RASIN CASH, CASL RDY
RFSH
This output provides a memory cycle start signal to the DP8408, and provides RAS timing during refresh.
These signals are. the separate CASs needed for byte writing. Their presence is controlled by BHE and AO respectively.
This output is used to insert a wait state into the 8086 memory cycles when selected and during a forced refresh cycle where the 8086 attempts to access the memory. The 8284A clock circuit should be configured so that ASYNC is enabled.
This output controls the mode of the DP8408 dynamic RAM controller. When low, it switches the DP8408 into an all RAS refresh mode. This signal is also used to reset the refresh request logic.
Functional Description
A memory cycle starts when chip select (CS) and the address latch enable (ALE) are true. RASIN is supplied from the DP84332 to the DP8408 dynamic RAM controller which then supplies a RAS signal. to the selected dynamic RAM bank. After the neces-
Applications 231
sary row address hold time, the DP8408 switches the address outputs to the column address. The DP84332 then supplies the required CAS signals (CASH, CASL) to the RAM. For byte operations, only one CAS will be activated. To differentiate between a read and a write, the DT/R signal from the CPU is inverted and supplied by the DP8408 to the memory array.
A refresh cycle is started by one of two conditions. One is when a refresh is requested (RFRQ is true), refresh clock (RFCK) is high, and a non-selected memory cycle is started (CE is not true, ALE is high). This is called hidden refresh because it is transparent to the CPU. In this case, the address supplied to the memories comes from the refresh counter in the DP8408, and no CAS signals are generated from the DP84332 . The second form of refresh occurs when a refresh is requested, refresh clock is low, and there is no memory cycle in progress. This is called forced refresh, because the CPU will be forced to wait during the next memory cycle to allow for the refresh to be performed. In this case, a refresh is performed as before, but any attempt to access memory is delayed by wait states until after the refresh is finished. In either case, the refresh request is cleared by the refresh line (RFSH), which also goes to the DP8408.
In a standard memory cycle, the access can be slowed down by one clock cycle to accommodate slower memories. This extra wait state will not appear during the hidden refresh cycle, so faster devices on the CPU bus will not be affected.
With higher speed systems, memory speed requirements will affect the performance of the system. Table 1 shows memory speed requirements at three different CPU clock speeds.
CPU Clock Frequency
8 MHz 5 MHz
No Walt States
tcAC 1 Wait State
:s 105 ns :s170 ns
:s223 ns :s370 ns
tRAH
:s30 ns :s30 ns
Table 8.13.4 Memory Speed Requirements
System Description
For memory operation, the DP84332 can be directly connected between the control signals from the CPU chip set and the DP8408 dynamic RAM controller. Each CAS output of the DP84332 is capable of driving eight memory devices. If additional drive is required, a DP84244 buffer can be used to increase the fanout to the full capabilities of the DP8408 (eight memories per output of the DP84244).
The 84332 is a standard National Semiconductor PAL part (PAL 16R8). The user can modify the PAL equations to support his particular application. The 84332 logic equations, function table, and logic diagram can be seen at the end of this section.
INTERFACING THE DP8408 TO AN 8086 SYSTEM
.....
I
ADDRESS PORT
ADDRESS BUS [ DM74LS139
.,A.
_.....
--,,. R0-6, 7
,._..... C0-6, 7
...* Q0-6, 7 ...
RAS 3 *... ,,.
-v~ YC(<(
.. B1
............... BO
ALE
* ADS
~ cs
* RAS 2 ,.
.--.
DP84300 I+
DP8408
,._... A0-6, 7
* RAS 16K, ~ CAS 64K ~ WE
~
.......
16K,
,........
64K
,......
_.....
--,,.
......._ .-.-.,,..
...._
....-
8086 8284A
~ ASVNC
CLK OT/A
r-+ RDY1 r+ AEN1
LATCHED { BAHOE
DATA PORT
~ .1111
10 MHz MAX · MM 74LS04
><~ "'
*WIN
* RAS 1 ...
~
_....
--,,.
.......
16K,
..-.....
__.
64K
..it_
....-
-
.. RFCK......, .. RFRQ .-...........
.......
'7 r-I+ RAS1R
.-.-.....
..,........
_..
DP84332
AWAIT
CONTROL
M2
J t (RFSH)IM1
* RAS 0 ... ,A. ~ ..
tMoWE CASH~
"-+
_._....
16K,
. =__.
* .. ....
64K
cAsL
ORAMs
'O' =NO WAIT+ '1' =ONE WAIT
SEE TABLE I
CASH ~L
.t OE
__.:.J~
* ~
DP84244
,..L
,._.....
...._
'1111
FOR CK~8MHz M1 = 'O', MO= '1'
"'lli"'
FOR CK>8MHz M1 = '1', MO= 'O' ..,. ~
DATA BUS
*THESE OUTPUTS MAY NEED RESISTORS
Figure 8.13.3 System Block Diagram
N
~
N
a ~
1
-~
~
·.t"'"'I
0
aQ
n
·.0
~ rlJ
~·~.
Q.
~
Applications 233
Refresh Request Logic
To generate the refresh request for the DP84332, external circuitry is required. Figure 1 shows how this can be implemented, using standard SSI and MSI logic. A DM74LS393 counter is used to time the period between refresh cycles, while the DM74LS74 flip-flop is used to record the need of a new refresh. A better solution is to use the 24-pin DP84300 programmable refresh timer, as shown in Figure 2. This part allows a maximum amount of time for a hidden refresh to occur before lowering the refresh clock output, and implements the refresh request logic.
SYSTEM CLOCK
DIVIDER
"O" D
Q
DM74LS74
----<RFSH
Figure 8.13.4 Using a Flip-Flop and a Counter for Refresh Request Logic
SYSTEM
CLOCK----1
RFCK
---ltl DIVIDE
CONSTANT
DP84300
RFSH ~---1
Figure 8.13.5 Using the DP84300 Refresh Counter for Refresh Logic
234 Programmable Logic Design Guide
PCLK
t1,..---j-t2
j-ta--j-t4
--~~
-~__,;
AD0-15---......c ADDRESS
DATA READ
ALE
RAMADD~~~~--<( ROWADD ><-~~~~~c_o_Lu_M_N~AD_D_R_E_s_s~~~~-->--
Figure 8.13.6 Timing Diagram; Read Timing
Applications 235
PCLK
t1--1--t2 --- t3--J--t4--1
AD0-15-----< ADDRESS
WRITE DATA
ALE OT/A
x______ RAM ADD-----( ROW ADD
c_o_L_U_M_N_A_D_DR_E_s_s_ _ _ _ _) -
Figure 8.13.7 Timing Diagram; Write Timing
236 Programmable Logic Design Guide
1-t1-1-t2-1-t3-1-tw-1-tH--1
PCLK
ALE tsu
READ DATA VALID~ DATA~~~~~~~~~~~~~~~~~-<(--~~--}---
Figure 8.13.8 Timing Diagram; Memory Cycle With 1 Wait State
1-t4-1
PCLK
RFCK
Applications 237
ALE
_____ ___.
RASIN
RAM ADD ROY
'-----
--
WAIT STATES DUE TO ALE
Figure 8.13.9 Timing Diagram; Forced Refresh
238 Programmable Logic Design Guide
t1
t2
t3
PCLK
AD0·15
cs
ADDRESS
ALE
cs
RFCK
RFSH
tpo
tpo
RASIN
tpo
tpo
RAs
CAS
RAM ADD
(
REFRESH ADDRESS
>
Figure 8.13.10 Timing Diagram, Transparent Refresh
PAL16R8 Dynamic RAM Controller Interface for the 8086-8408 System CK AO /BHE /CS ALE RFCK WAIT /RFRQ NC GND /OE /RASIN /CA /CB RDY /RFSH IA /B /MRQ VCC
MRQ: = /RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*RFRQ*CS*ALE*/RFCK + MRQ*RASIN +
RAISIN*/CA*/CB*RDY*RFSH*/A*MRQ*CS*ALE
B: = RASIN*/CA*/CB*RFSH*/A*/B + RASIN*/CA*/CB*IRDY*/RFSH*/A*IB*WAIT +
RASIN*RDY*/RFSH*A*/B
Appllcatlons 239
A:= RASIN*ICA*ICB*RDY*/RFSH*/A*IB*/WAIT + RASIN*RDY*/RFSH*/A*B +
RASIN*RDY*/RFSH*A*/B
RFSH: = /RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*RFRQ*/CS*ALE*RFCK* + /RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*RFRQ*IRFCK +
RASIN*/CA*/CB*RFSH*/A*/B
/RDY: = /RASIN*/CA*/CB*RDY*/RFSH*/A*IB*MRQ*RFRQ*CS*ALE*/RCFK + RASIN*/CA*/CB*RDY*RFSH*/A*/MRQ*CS*ALE + /RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*IRFRQ*CS*ALE*WAIT + /RASIN*/CA*/CB*/RDY*/RFSH*/A*IB*MRQ*/RFRQ*WAIT + RASIN*/CA*/CB*/RDY*RFSH*/A +
/RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*RFRQ*CS*ALE*RFCK*WAIT
CB:= RASIN*/CA*/CB*/RFSH*/A*IB*BHE + RASIN*CB*RDY*/RFSH*/A*B*WAIT +
RASIN*CB*RDT*/RFSH*N*B
CA:= RASIN*/CA*/CB*/RFSH*/A*IB*BHE + RASIN*CA*RDY*/RFSH*/A*B*WAIT +
RASIN*CA*RDY*RFSH*A*/B
RASIN: =
/RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*/RFRQ*CS*ALE + /RASIN*/CA*/CB*/RDY*/RFSH*/A*IB*MRQ*/RFRQ + RASIN*/CA*/CB*/RFSH*/A*/B + RASIN*RDY*/RFSH*/A*B*WAIT + /RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ.*RFRQ*ALE*RFCK +
/RASIN*/CA*/CB*RDY*/RFSH*/A*IB*/MRQ*RFRQ*IRFCK +
RASIN*/CA*/CB*RFSH*/A*IB +
RASIN*RDY*/RFSH*A*IB
240 Programmable Logic Design Guide
CK AO BHE cs ALE RFCK WAIT RFRQ OE RASIN CA CB ROY RFSH A B MRQ
cL L H L
H
L
H
L
x x x x x xx x
cL L H L
H
L
H
L
H
H
H
H
H
HH H
cx x L H x
L
H
L
L
H
H
H
H
HH H
cL H L L
x
L
H
L
L
L
H
H
H
LH H
cL H L L
x
L
H
L
L
L
H
H
H
LL H
cx x H L H
L
H
L
H
H
H
H
H
HH H
cx x L H
x
H
H
L
L
H
H
L
H
H H
H
cH H L L
x
H
H
L
L
H
H
H
H
H L
H
cH H L L
x
H
H
L
L
H
H
H
H
LH H
cH H L L
x
H
H
L
L
H
H
H
H
LL H
c x x H 'L
H
H
H
L
H
H
H
H
H
HH H
cx x H H H
x
L
L
L
H
H
H
L
HH H
cx x H L
x
x
x L
L
H
H
H
L
H L
H
cx x x L
x
x
H
L
H
H
H
H
H
HH H
cx x x L
L
x
L
L
L
H
H
H
L
HH H
cx x x L
x
x
x L
L
H
H
H
L
HL H
cx x x L
x
x
H
L
H
H
H
H
H
H H
H
cx x L H L
x
:.. L
L
H
H
L
L
H H
L
cH L L L
x
x
x L
L
H
H
L
L
H L
L
cH L L L
x
x
H
L
H
H
H
L
H
H H
L
cH L L L
x
L
H
L
L
H
H
H
H
HH H
cH L L L
x
L
H
L
L
H
L
H
H L H I;
cH L L L
x
L
H
L
L
H
L
H
H
L L
H
cx x L L x
L
H
L
H
H
H
H
H
H H
H
cx x x L
L
x
L
L
L
H
H
H
L
HH H
cx x L H x
H
x L
L
H
H
L
L
H L
L
cL L L L
x
H
x L
H
H
H
L
H
H H
L
cL L L L
x
H
H
L
L
H
H
L
H
HH H
cL L L L
x
H
H
L
L
L
L
H
H
H L
H
cL L L L
x
H
H
L
L
L
L
H
H
LH H
cL L L L
x
H
H
L
L
L
L
H
H
LL H
cx x L L x
H
H
L
H
H
H
H
H
H H H'
cx x L H H
L
L
L
L
H
H
H
H
H H
H
cH L L L
x
L
x
L
L
H
L
H
H
LH H
cH L L L
x
L
x
L
L
H
L
H
H
L L
H
cx x L L x
L
x
L
H
H H
H
H HH H
cx x L H H
H
L
L
L
H H
L
H HH H
c x x L L x x x H z z z z z zz z
Table 8.13.5 Function Table
Applications 241
1
Inputs (0-31)
CLOCK~~~~~~~~~~~~~~~~~~~--,
.-+-l-~4-1-l-+--+-~~14-3-+-+-~3~~-l-+-~4-1-1-+--+-H-1-+·H-l--~=~,--~Q DI 1 l
D
I
I l
~
·Ii 1
8 9 10 I I
; · 1) 14 I~
1b 11 1o })
lal
, ..... L/;J~ )1 -*-
I
i 1
AO ~
-+-+-+--++-+-+~+++--H-H--+-+-+-+-+++-+-~~~-_,<----11--1~~~--'
....i---1-1-+-<.........
, ,....
~~
I
I
9
ID
II
11
IJ
14
11
3
BHE
.~ .. ...,.
cs 4
16
"lj
'9 10 11 22 ll
...
~
l· II
l6
11 lb
19 1D
JI
ALE
5
... ~
l1 Jl JO JI l6 JI JI l9
RFCK
6
....
~
... V"
15
ROY
4D 41
.41
4J
41 46 41
7 ... AWAIT ~
48 '9 ID II 11 ll 14 II
8 ...
,;>.
NC
16 II 18 19 6D ii 61 6l
9 .. ~
D 1 IJ
]
::i::
4 ~fl 1 K 91011 1/11'41~ 16111819 2U11ll/, l~l'ilbJJ llU~)Oll
..... ,
R""""""'' -
~
."t."-.".-.'
'
Figure 8.13.11 84332 Logic Diagram PAL16R8
242 Programmable Logic Design Guide
8.14 A PAL DEVICE INTERFACE BETWEEN THE NATIONAL SEMICONDUCTOR NS32032 MICROPROCESSOR, DP8409 DYNAMIC RAM CONTROLLER, AND THE DP8400 EXPANDABLE ERROR CHECKER AND CORRECTOR
TERMINAL
RS-232
CPU &
STATIC RAM
ROM NMC2764(2)
CLOCK CHIP
SERIAL 1/0
NMC2116(2)
. MONITOR
,..,.~ t~ ·"~"""!~
NS32202 NS32201
INS8251
[~
[
.... ::::: ~~
"Ill: i;--
1111..._)?
'-.> ADDRESS BUS,..- ~4 BITs
,;
DATA BUS
a----.;;a.c;...16-B-IT_S_.._ _.
PARALLEL PORT
INS8255
[
~ ~
~ ~~--~,;;:ii,,c;;~----------' CONTROL BUS vA...__ _ _ _ __ _
~~
~_.,. ............. ~
.. 4-PAL
,, CONTROLLER
IA
CONTROL
~
DP8400
11'"
~" ~
CONTROL 8409
>i- "11111~ ADDRESS
~
DP8409
-ij
....
.,__._ ,,
CONTROL
MEMORY (DRAM)
(256K DRAMS)
4 BANKS OF 22
2M BYTES PLUS
.. .. CK BITS
~
;iii.
DATA
CHECK BITS
Figure 8.14.1 DP8400, DP8409, NS16032 6 MHz Computer System
· Application 8.14 is contributed by lfebster (Rusty) Meier, Design Engineer of National Semiconductor
Applications 243
Four PAL devices were used in this application in order to interface between the NS32032, DP8409 and the DP8400. These PAL devices have the following features:
1. The PAL devices control the following types of cycles: a) READ cycles with no errors detected, ALWAYS CORRECT MODE b) READ cycles with single error detected, the correct data will be written back to memory c) WRITE cycles d) BYTE WRITE cycles e) DRAM REFRESH cycles The PAL devices take care of everything, no extra control logic is needed.
2. The outputs of the PAL device control the DP8409, the DP8400 and insert WAIT states at the appropriate times into the NS32032 cycles.
3. The PAL device contains outputs to interrupt the NS32032, or cause a cycle abort if an error greater than a single error is detected (DOUBLERR), or if there is a bus parity error in data transfer from the CPU to memory (PARITYERROR).
4. This PAL device design should work up to 8Mhz with the NS32032. If it is desired to go faster, another WAIT state will have to be inserted into all cycles, and the PAL device equations will have to be adjusted accordingly. Another possibility would be to use the new oxide isolated DP8400 and the new DRAM controller DP8419 (pin compatible with DP8409 in modes 0, 1,4,5). These parts would allow considerably more time margin.
5. As can be seen by looking at the PAL device logic diagrams some external logic
is needed and some external logic may be added. For example, a system reset
input could be added to allow the internal flip-flops to be set to a known state
- in this case a refresh state (In PAL device number 1, for example, I used exter-
nal logic to "NOR" the RFI/O input with a system RESET input). An output
enable input was also included to allow all the PAL device outputs to be
tri-stated.
·
6. This PAL device interface performs HIDDEN REFRESHES (CPU not accessing the Dynamic RAM controlled by the DP8409, indicated by /CS being high) assuming a four-T state processor access cycle.
7. Logic diagrams, the PAL device equations, and the timing diagrams follow this introduction section. Basically everything is self-explanatory.
8. I feel that if one is using this interface above 4-6MHz, he should use the fast PAL devices (example "PAL16R8A'.' instead of "PAL16R8"). The fast PAL devices have an input to output maximum time of 25ns and 15ns if it is a registered output.
244 Programmable Logic Design Guide
The slow PAL devices have an input-to-output maximum time of 35ns and 25ns if it is a registered output. Depending on the specific type of PAL's and logic used, the user can calculate the speed requirements for the DRAM at the specified processor frequency with the timing that I have chosen.
9. The four PAL devices that I have-used allow full use of the DP8400 and all its modes of operation. For example, one can perform a complete diagnostic test of the DP8400 without needing to use the external memory. This is possible using an 1/0 port to control M2 and Ml of the DP8400, along with diagnostic control signals DIAGCS and DIAGD. These signals from the 1/0 port allow the user complete control over the operating modes of the DP8400 and its data syndrome, and check bit latches.
PAL Device Number 1 Inputs
1. FCLK 2. CTTL 3. /CS 4. /DDIN 5. RFI/O 6. INCY 7. /AOHBE
8. NTSO 9. /ERRLATCH 10. /OE
Fast Clock (twice CTTL frequency) from NS32201
Output clock from NS32201
Chip Select for the Dynamic RAM controll~d by the DP8409 and DP8400.
Data Direction in, from NS32032, indicates the direction of the data transfer during a bus cycle.
Refresh request output from the DP8409, is also used as a reset input to set PAL to a known state.
Output from PAL device number 2 indicating that the NS32032 is in an access cycle.
If address bit OAND high byte enable (fromNS32032) are both low this input is high. Used to determine when byte operations are in progress.
FromNS32201, indicating that timing state T2 is starting, it stays low until the beginning of T4.
Output from PAL device number 3 indicating that any error, AE, was valid during a READ access cycle.
Controlled externally, TRI-STATE PAL outputs.
Applications 245
ADDRESS/DATA BUS
B1
00-7 ---,..,..,.-1ADORESS AFRO (RFl/O)
DP8409
-----~-o-~J.\.l,.\..,r.-,,-,-.-__R-MACASs o-3
I--"""~""",.___.. WE
DECODER -__,8--M74LS245M-...8...............- - - - - - - - - . . . - - - - - - H D I 0 - 7 ADDRESS/
DATA 0-7
ADDRESS/ DATA 8-15
DATA TRANSMIT/
RECEIVE
DIR
G
PBUF1 n----~
i + - - - -8-+--.,...----t 74LS244
MEMORY 008-15
OBO OB1 CSLE OLE OLE
M2
":'
OB1 CSLE OLE DP8400
OLE
M2
C0-5
OeS
cs
8
6 R·
-::"
@ RESISTOR REQUIRED DEPENDS ON DRAM LOAD. · R=2.7Kf!
74LS244
000-7
0016-21 (CHECK BITS)
74LS244
0116-21 (CHECK BITS)
Figure 8.14.2 DP8400/8409 System Interface Block Diagram
246 Programmable Logic Design Guide
PAL Device Number 1 Outputs
1. /RAS IN 2. /RFSH 3. /lDLY 4. /2DLY 5. /3DLY
6. /4DLY
7. /ODCLEN 8. /CYCLED
Input to DP8409.
Input to DP8409, causes the DP8409 to enter mode 1 to do a refresh.
Delay used by the PAL devices to determine the state of the processor system.
Delay used by the PAL devices to determine the state of the processor system.
Delay used by the PAL devices to determine the state of the processor system.
Delay used by the PAL devices to determine the state of the processor system.
/OLE, DLE, CSLE enable latch signal.
Indicates that a processor access cycle is complete.
PAL Device Number 2 Inputs
1. /RFSH
2. /RAS IN 3. AO 4. /HBE 5. /DDIN
6. /ADS
7. NTSO 8. /2DLY 9. /4DLY 10. /ERRLATCH
11. CSOE
Output from PAL device number 1 that indicates whether the DRAMs are being refreshed. Output from PAL device number 1.
Output from NS32032, address bit 0.
Output from NS32032, high byte enable. Data Direction in, from NS32032.
Address strobe from NS32032. Output fromNS32201. Output from PAL device number 1.
Output from PAL device number 1. Output from PAL device number 3 indicating that an error has occured during a READ cycle. Chip select Output Enable, TRI-STATE the outputs of the PAL device when low, and also used· for other control purposes.
Applications 247
PAL Device Number 2 Outputs
1. /OBO 2. OBl 3. /PB UFO
4. /PBUFl 5. /DOUTB
6. /INCY 7. /CWAIT
Controls DP8400 output buffer for byte "O".
Controls DP8400 output buffer for byte "1". Controls the processor buffer transceiver for byte "O".
Controls the processor buffer transceiver for byte "1 ". Controls memory buffers that interface between the DRAM and the DP8400/memory data bus.
Output indicating that the NS32032· is in an access cycle.
Output toNS32201 that causes WAIT states to be inserted into the NS32032 bus cycles.
PAL Device Number 3 Inputs
1. /DDIN 2. /RFSH 3. /AOHBE
4. /ERRLATCH
5. /lDLY 6. /2DLY 7. /3DLY
8. /4DLY 9. /RESET
10. AE 11. EO 12. El
Output fromNS32032.
Output from PAL device number I indicating a forced refresh of the memory. Output of AO and /HBE logically NORed together. Therefore, if either input is high this signal will be low. This signal is useful to determine whether words or bytes are being written.
Output from PAL device number 4 indicating that an error has occurred during a CS READ cycle, it may be a single or multiple bit error.
Input from PAL device number 1.
Input from PAL device number 1.
Input from PAL device number 1.
Input from PAL device number 1.
Input from external logic that resets the double bit error. latch /DOUBLERR or the parity error latch PARITYERR.
Output from DP8400 indicating an error.
Output from DP8400 indicating the type of error.
Output from DP8400 indicating the type of error.
248 Programmable Logic Design Guide
13. /PARITYERROR This is an output of this PAL device also. This input indicates that a PARITY error has occurred during a WRITE cycle.
14. CSOE
Chip Select Output enable, tristates the registered outputs of the PAL device when low.
PAL Device Number 3 Outputs
1.
/WIN
2. /MODECC
3. /PARITYERR
Input to the DP8409.
Input to the. DP8400, changes between READ and WRITE modes.
Can be used to interrupt the system when a parity error has been detected during a WRITE cycle.
PAL Device Number 4 Inputs
1.
FCLK
2. ODCLEN
3. · DIAGCS
. 4. DIAGD
5. /RESET 6. /CYCLED
7. AE 8. /EOI
9. /3DLY 10. /OE 11. /DDIN
12. /RFSH
Fast clock fromNS32201.
/OLE, DLE, CSLE latch enable input.
Enable input from I/O port for diagnostics to enable CSLE, check bit syndrome latch enable .
Enable input from 1/0 port for dagnostics to enable DLE, data latch enable.
Reset input from I/O port to reset PAL error latches.
Output from PAL device number 1 indieating that a pro. cessor access cycle is complete.
Output from DP8400 indicating an error.
When this input is low it indicates that either error flag EO or El was high.
This is an input from PAL device number 1.
Output from 1/0 port that enables the PAL outputs.
NS32032 input that indicates the direction of the bus transfer during a bus cycle.
Output from PAL device number 1 indicating a DRAM refresh cycle.
Applications 249
PAL Device Number 4 Outputs
1.
DLE
2. CSLE
3. /OLE 4. /DOUBLE RR
5. /ERRLATCH
Output that controls the DP8400 Data latch.
Output that controls the DP8400 Check bit Syndrome latch.
Output that controls the DP8400 Output latch.
Can be used to interrupt the system when a double bit error has been detected during a READ cycle.
Used in the PAL device controller to indicate that an error has occurred during a /CS READ cycle, as indicated by AE being valid.
250 Programmable Logic Design Guide
32032 8 MHz "READ" CYCLE (NO ERRORS)
WRITE CYCLE
FCLK
T1
T2
TW
T3
T4
T1
T2
T3
T4
CTTL
I I
I ADS I I
I
I
lf/ I I I I
I I
I
I I
I
RASIN ,'
I
RAS I I
I
I .
I
I
~1 . . . . . . . . . . . . ._ . . . . . _ . . . . . . . , . _ . . , . . .
I I Ii I I
I
,, I \I I
I I ..., -.I...........-...,._...,.._,..
~I I
I I
\1I
I I
I II
CAS I
I
I
1·
~
~
DP8400 MEM DATA BUS
1
I·
. . . . . . , _ , . ' " " '"""I. . . , . . . . . . . . . ,
DATA TO BE WRITTEN
I I
r:I I
~
I I
I r
OLE,DLE
I = CSLE ODCLE I II
CHECK BITS
I I I I
iii:iiJFO' iiBiJF1 ON LY I I
I
I MODECC
I
I
II..... II II I WIN
WRITE ECC ..--.-...----.~--..-..-...,.......--..,-...--,_..._..,D~:J?n
I
I
I
I
I I I I
h___I ___I____________Ii :
ODIN
I I
I I I
I I
I CWAIT
I
~
I'/
I I
I
AE
Figure 8.14.3 Timing Diagram; Read Cycle and Write Cycle
FCLK CTTL
32032 8 MHz "READ" CYCLE W/SINGLE BIT ERROR
RASIN I RAS I CAS I
I DP8400 MEM
DATA BUS _..,_.....,_....,_,....__.....
OBtJ. PBUF1 I
081, PBUFO
I
I
I
OLE, OLE I I I
= CSLE
I ODfLE
MODECC I
I WIN
Applications 251
"WRITE" CYCLE - EXTENDED FROM ERROR IN "READ" CYCLE
DATA TO BE WRITTEN
.1_____L
PBUFO, PBUF1 ONLY
ERRLATCH
I
Figure 8.14.4 Timing Diagram; Read Cycle With Simple Bit Error
252 Programmable Logic Design Guide
32032 8 MHz BYTE WRITE FCLK
CTTL
nl JI
I
\f': : ACIBi
I
n I I RASINj I \ I 1'-·..,...-+--+--+--+.......................... I :,: :n ~1
--,-- ..... I I
I
CASI
I ......................__._ii--..,_.,.__
DP8400 DATA
MEM BUS
I-1__......I.,1--'"--.....i
-
-
DOUTB
I
--+_.. OLE, OLE_....._......_..._.......
= CSLE ODCLE
CHECK BITS .,.._...,_....,__,._......-+C
I MODECC
WINI
WEI
. I
I
I
I ODIN
Figure 8.14.5 Timing Diagram; Byte Write
FCLK CTTL
NTSO
Applications 253
NEW 32032 FORCED REFRESH THEN ACCESS
CYCLED ~
I I RFl/O
I RFSH I
I ODIN I
CWAIT I
I
Figure 8.14.6 Timing Diagram; Forced Refresh Then Access
FClJ( CTTL
-CS -DOI RFI-
AB -HBE NTS
-ADS
-OE DIAGCS
DIAGP RESET
AE ED E1
Figure 8.14.7 Simulation Circuit
-RASIN -RFSH - IDLY -2DLY -JOLY -4DLY -ODCLEN -CYCLED
-080 -081 -PBUFO
PBUF1 DOU TB
INCY CWAIT
ODCLE
LE SLE OLE WIN MODECC DOUBLE RR ERRLATCH
PARITYERR
N
't·
I
ti'
~
0
(lQ
~ ""'
0
~ rlJ
~-
~
"Q"'.
~
Applications 255
SCALE 2:1
CTTL -CS -ODIN NTSO -ADS
-~ASIN
-1DLY -2DLY -3DLY -4DLY
SIMULATION RESULTS
READ (NO ERRORS)
READ (W/SINGLE ERROR)
TIME 591 STARTING TIME 591 ENDING TIME 1521
TRIGGER TIME 591
591
691
791 891
991
1091 1191 1291
1391 1491
-I
r
I
L
I
ri.J
n
:I
_ rI t
J
I
r
t
I I
J rt.J r
l
JI rrI
_
1
-n
l
-ru
J
l
J
1
l
J
1
-ODCLE -INCY
-n
-CYCLED
-081
-PBUFO
-CWAIT
-DOUTB
Li J
1
1
l l
I
r n
J J
Ll
-WIN
-MODECC
J
-ERRLAT
Figure 8.14.8 Simulation Timing Diagram; Read/Write Without Errors
256 Programmable Logic Design Guide
READ (W/ERROR) CONTINUED
WRITE STANDARD FROM PREVIOUS READ W/ERROR CYCLE
SCALE 2:1 CTTL
TIME 1491 STARTING TIME 1491 ENDING TIME 2421 TRIGGER TIME 1491
1491 1591 1691 1791 1891 1991 2091 2191 2291 2391
r
I
t
I
. r
L
I
r
I
L r
I
L
r
I
L
r
I
L
nI
_
I
r
I
Lt-
-CS -ODIN NTSO -ADS
-RASIN -1DLY -2DLY
i l -3DLY
.,..4QLY -ODCLE
-INCY -CYCLED
-081 -PBUFO -CWAIT
-DOUTB -WIN
-MODECC -ERRLAT
J
J
1
I l
I .
I
J
l
l
l
J
l
J
.l
l~ J
I
l
I
l
1
I
I
r I-
r
·.
l _r1I-
~
r
t-
...
r ...
l
r t-
Figure 8.14.9 Simulation Timing Diagram; Read With Error and Write Cycle
Applications 257
SCALE 2:1 CTTL
BYTE WRITE
WRITE
TIME 2391 STARTING TIME 2391 ENDING TIME 3321 TRIGGER TIME 2391
2391 2491 2591 2691 2791 2891 2991 3091 3191 3291
-
r
L
r
I
U
r
u I
I I
rUri.J
I
rLl r1....
r
~
U
-CS
-ODIN
NTSO
l
I
ru ~
-ADS
-RASIN
J
-1DLY -2DLY
-30LY
-4DLY ....
-ODCLE -INCY
n ~
-CYCLED .....
-091
-PBUFO -CWAIT -DOUTB
l
J
1
~
I l
l
L
J
1
I
l j_ l J
1 I
-WIN
-MODECC
I
l
J
l
~
u
1-
-ERRLAT
Figure 8.14.10 Simulation Timing Diagram; Byte Write
258 Programmable Logic Design Guide
SCALE 2:1 · CTTL
TIME 3591
3591 3691 3791 3891 3991 4091 4191 4291 4391 4491
.l_
.l_
.l_
_l_
_l_
_l_
_l_
.l_
.l_
_l_
_run-rL-rLrun_rLru I
11 1
12 ·
rw1
1rw2 1 TW3 1 TW4 1
TW5
rws
-I I -CS
-ODIN RFl-0
AO
-HBE
-t1-I NTSO
L
-ADS
-RASIN -RFSH -1DLY
.....
-n
-2DLY
-3DLY
l
-4DLY
-ODCLE
-INCY
- -CYCLED
-080
-081
-PBUFO -PBUF1
...ti
L
JD I
1
L
L
Il l
7 1
u
J
\
~
:s:: ~ ~
1
. "-'"
Figure 8.14.11 Simulation Timing Diagram; Forced Refresh Then Access
Applications 259
SCALE 2:1 CTTL
WRITE
FORCED REFRESH & READ ACCESS
.
(W/ERROR)
TIME 3101
STARTING TIME 3101 ENDING TIME 4031 TRIGGER TIME 3101
3101 3201 3301 3401 3501 3601 3701
3801 3901 4001
n... I I I I I I I
I II
-rLr-Lrl- r-LrL.rLrL
-CS
-ODIN
l
NTSO -ADDS -RASIN
-M-1 II
IJ
II
I
-1DLY
1
I
l
-2DLY
i
n
-3DLY
- -4DLY
-ODCLE
- -INCY
l r
l
l
- -CYCLED
-081
-PBUFO
l
-CWAIT
I
l~ ~ l
-DOUTB -WIN
-MODECC
--~n
-ERRLAT
l
I
I
Figure 8.14.12 Simulation Timing Diagram; Write, Forced Refresh and Read Access
260 Programmable Logic Design Guide
SCALE 2:1 CTTL
FORCED REFRESH FOLLOWED BY READ ACCESS (W/ERROR)
TIME 4001 STARTING TIME 4001 ENDING TIME 4931 TRIGGER TIME 4001 4001 4101 4201 4301 4401 4501 4601 4701 4801 4901
I I II III I II
-1:.rLrUn:.n:.rt..rLri:..I-
-CS
-ODIN
NTSO
-ADDS
-RASIN
/__
r I-
-1DLY
I l
-2DLY -3DLY -4DLY -ODCLE -INCY
~ J_P
' z ~ L l
r
I
L
_J_
-......-
1 ... ~ J7 z_L
l
T
-CYCLED
1
l
-081
~
-PBUFO -CWAIT
j_
1
j_
.~
L L
l
I I~
n ~
-DOUTB
l l J
-WIN -MODECC
~
-ERRLAT
l l
Figure 8.14.13 Simulation Timing Diagram; Forced Refresh Followed by Read Access (With Error)
Applications 261
PAL Device Number 1 This PAL Device is Part of a Four PAL Device Set Needed to Control the 32201, 8409, 84001nterlace
PALI6R8A
RFSH: = /RFIO* /IDLY* /2DLY* /INCY* /CTTL + RFSH */RFIO + RFSH* IDLY+ RFSH*4DLY
IDLY:= RFSH */RFIO + RFSH*IDLY*/4DLY + RFSH* IDLY*CTTL + /RFSH*RASIN* /2DLY* /3DLY* /4DLY + /RFSH*CS*RASIN*/4DLY*DDIN + /RFSH*CS*RASIN* /4DLY* /DDIN* AOHBE + /RFSH*CS* IDLY*CTTL *DDIN + /RFSH*CS* lDLY*CTTL */ODIN* AOHBE
2DLY: = IDLY*/4DLY + IDLY*RFSH + /RFSH*CS* IDLY*DDIN + /RFSH*CS* IDLY* /ODIN* AOHBE
3DLY: = 2DLY*/4DLY 2DLY*RFSH + /RFSH*CS*2DLY*DDIN + /RFSH*CS*3DLY*ERRLATCH*RASIN + /RFSH* CS* 2DLY* /ODIN* AOHBE
4DLY: = 3DLY*RASIN + 3DLY*RFSH + /RFSH*CS*30LY*20LY*DDIN + /RFSH*CS*3DLY*ERRLATCH + /RFSH* CS* RAS IN* 4DLY* /ODIN* AOHBE ,
RASIN: = /RFSH*INCY*/CYCLED*/4DLY*/CTTL + /RFSH*CS*RASIN*ODIN* IDLY+ /RFSH *CS* RAS IN* ODIN* ERRLATCH *CYCLED+ /RFSH*CS*RASIN*DDIN*/CYCLED + /RFSH *CS* RAS IN* /ODIN* 3DLY *AOHBE + /RFSH *INCY* /NTSO */ERRLATCH */4DLY* RAS IN
; RFSH in idle states or in long ; accesses of, other devices or ; at the beginning of an access
; Start RFSH IDLY ; Hold RFSH IDLY ; Extend RFSH IDLY ; For READS and WRITES ; For READs ; For BYTE WRITES ; Extend IDLY during READ ; Extend IDLY during BYTE WRITEs
; For READs or WRITEs ; Extend for RFSH ; Extend for READ ; Extend for BYTE WRITE
; For READS or WRITES ; Extend for RFSH ; Extend for READ ; Extend for READ with error ; Extend for BYTE WRITE
; For READs or WRITEs ; Exten,d for RFSH ; Extend for READ ; Extend for READ with error ; Extend for BYTE WRITE
; Start /RASIN ; READ cycle without error ; READ cycle with error ; WRITE cycle ; BYTE WRITE cycle ; Hidden RFSH, assume on ; four 'T' States.
262 Programmable Logic Design Guide
CYCLED:= /RFSH*1DLY*2DLY*3DLY*4DLY + /RFSH*/DDIN*2DLY*3DLY*/AOHBE + CYCLED*CTTL + CYCLED* /NTSO + CYCLED* RAS IN* /DDIN *AOHBE
ODCLEN: = CS* /RFSH*DDIN*RASIN*2DLY* /4DLY* /ERRLATCH + CS* /RFSH* /DDIN*RASIN* /2DLY* /3DLY* /4DLY* /AOHBE + CS* /RFSH* /DDIN*RASIN*2DLY* /4DLY* AOHBE + CS* /RFSH* /DDIN*RASIN* lDLY*CYCLED* AOHBE
PAL Device Number 2
PAL16L8A
IF (CSOE) OBO = /DOUTB*DDIN*4DLY*RASIN*/RFSH +
/DOUTB*AO*HBE* /DDIN*4DLY*RASIN* /RFSH
IF (CSOE) OBl = /DOUTB*DDIN*4DLY*RASIN*/RFSH +
/DOUTB* /AO* /HBE* /DDIN*4DLY*RASIN* /RFSH
IF (CSOE) PBUFO = /DOUTB*/AO*DDIN*4DLY*RASIN*/RFSH +
/DOUTB */AO* /HBE */DDIN *4DLY *RAS IN* /RFSH+ /DOUTB* /Av" HBE* /DDIN*RASIN* /RFSH
IF (CSOE) PBUFl = /DOUTB*IIBE*DDIN*4DLY*RASIN*/RFSH +
/DOUTB *AO* HBE */DDIN *4DLY* RAS IN* /RFSH + /DOUTB* /AO*HBE* /DDIN*RASIN* /RFSH
IF (CSOE) DOUTB = ODIN* /RFSH*2DLY* /4DLY + /AO* /HBE* /ODIN* /RFSH*2DLY* /4DLY + AO*HBE* /ODIN* /RFSH*2DLY* /4DLY
; BYTE WRITE or READ cycles ; WRITE cycle ; End CYCLED
; End BYTE WRITE cycle
; READ and READ with error
; WRITE cycle
; BYTE WRITE cycle ; BYTE WRITE cycle
; READ or READ ; w/error ; BYTE WRITE ; high byte
; READ or READ ; w/error ; BYTE WRITE ; low byte
; READ, ; READ/error
; BYTE WRITE ; Word WRITE
; READ" ; READ/error
; BYTE WRITE ; Word WRITE
; READ cycle ; BYTE WRITE ; BYTE WRITE
IF (VCC) INCY = /RFSH *ADS* /4DLY +
/RFSH*CSOE*/NTSO*/RASIN +
INCY* /4DLY + INCY*CSOE*/DDIN*RASIN +
INCY* /CSOE *RASIN
IF (CSOE) CWAIT = RFSH*CSOE*/NTSO + /RFSH*CSOE*/NTSO*/RASIN +
/RFSH*DDIN*RASIN*2DLY*INCY*/4DLY + /RFSH*/DDIN*/AO*/HBE*RASIN*/4DLY + /RFSH*/ODIN*AO*HBE*RASIN*/ROLY +
/RFSH*INCY*ERRIATCH*/2DLY*/NTSO
PAL Device Number 3
PAL14L4A
WIN=
/RFSH*ERRIATCH*/2DLY*3DLY*4DLY*CSOE + /RFSH*DDIN*3DLY*IAOHBE*CSOE +
/RFSH*/DDIN*AOHBE*/2DLY*4DLY*CSOE
MODECC = /RFSH*ERRIATCH*/1DLY*4DLY*CSOE + /RFSH*/DDIN*/AOHBE*CSOE +
/RFSH*/DDIN*AOHBE*/1DLY*4DLY*CSOE
PARITYERR =
/RFSH*/ODIN*/RESET*4DLY*
/AE*EO*/El *AOHBE*CSOE +
/RFSH*/DDIN*/RESET*4DLY*
/AE*/EO*El *AOHBE*CSOE +
/RFSH*DDIN*/RESET*4DLY*
/AE*/EO*/El */AOHBE*CSOE +
PARITYERR*/RESET*CSOE
Applications 263
; Start INCY ; Start INCY for access ; after forced refresh ; or READ w/error ; Continue INCY ; WRITE cycles ; Non-/CS cycles
; Access in RFSH ; Access after ; forced refresh ; READ cycle ; BYTE WRITE ; BYTE WRITE ; Insert WAITS ; into the next ; cycle
; READ w/error ; Word WRITE ; BYTE WRITE
; READ w/error ; Word WRITE ; BYTE WRITE
; Parity error byte ; " 1" during WRITE ; Parity error byte ; "O" during WRITE
; Parity error ; both bytes
264 Programmable Logic Design Guide
PAL pevice Number 4
PAL16R6A
IDLE:= ODCLEN + DLE*DIAGD
/CSLE: =
ODCLEN + CSLE *DIAGCS
OLp: = ODCLEN DOUBLERR: =
/RFSH* /DIAGCS */DIAGD* /RESET* OLE*CYCLED*AE*/EOl + DOUBLE RR* /RESET
ERRLATCH: =
DDIN*OLE*CYCLED*/DIAGCS*/DIAGD* AE + ERRLATCH *3DLY
; Hold IDLE for diagnostics
; Hold /CLSE for diagnostics
; Double bit error ; during READs ; or BYTE WRITES
; Error during READ
Applications 265
(16201) FCLK
:1__p
Inputs (0-31)
~ r;:vJ. o-++++--+-t-++-+-t-++-+++-1-+++-+-+-+++-t-++-+-++-IH-4~~4
;-++++--+-t-++---+-t-++-+++-t-+++-t-t-+++-+++-+-++-H-4§~>-'>-1---../>---~~~o;
RASIN 19
(16201) CTIL
· -++++--+-t-++-+-+++-+++-1-+++-+-+-+++-1-+-+-+-++-1H-4t:~-1
2 ..... _
...
~
~
··-++++--+-t-++-+-1-+-+-+++-1-+++-+-+-+++-1-+-++-++-IH-~~,_4
ODIN 11-++++--+-t-++---+-+++-+++-1-+++-t-t-+++-+++-+-++-1H-~~~-+-"""-./,____4~ 4o; ~
(16032)
RFPO
4 ~ h""'="""--++++-++-++-.
~
(8409)
!l RF 110 ;::-+t+t+:+t-t-+:-ttj-:+t+-t-:-:+:-:t-t+t+t-:+t+=+-t1t-t+:+~+-ttt-tt=-t++:+t-tH:-tt+:-=tt+t-:1-t+:-t~=~m-~>-~1§'~r.).. ~---+-l~
M' RF 1/0
.,8CD_ SYSTEM RESET E ~ (ACTIVE
HIGH)
5 .">'r-..:-----t-t-H-+tt-r--t"TT~
..... J ~
~~-+-+-++---+-IH-+-+-++-l-+++-t-+-+++-+-++-+-t-++-+-++-H-4~">--41
. ~; :t~-t.t.=i~i:t-t=.tt1i:t=-t.tt1t:"-t-t.tt":t~-t-t=t1i:t-t=.tt1;:;::~§j~t--/
INCY
~;-+-+-++---+-11-+-+-+-tt-1-+++-1-+-+++-+-++-+-++-1-+-++-+-+--48-r-4
.. (PAL #2 OUTPUT) -61__J""'f"""~.,---1-+-+-+-++-1r-t---;--rtt--++Tt--.
·a-++-++---+-11-+-+-+-++-1-+++-1-+-+++-+-++-+-t-++-+-++-H-~~,_4,
o; ~;-++-++---+-11-+-+-+++-1-+++-1-+-+++-+-++-+-++-1-+-++-+-+--~~J--+---..:...>. ->---~~~
AOHBE
AO HBE
..7 r""'~~-++-1-t-++-tt--++++--t-t-++-+-t-++-.. ~
~
--~
IF EITHER
::-++-++---+-11-+-+-++-H-+++-1-+-+++-+-++-+-++-1-+-++-+-+--~E~4
IJ 13
INPUT HIGH !!-++++-+-11-++-t-H-i-++t-t-t++t--i-+++-++1+-+t-H-~~J---+--./>---4~40;~
THIS IS LOW
. .J---f-___J (FROM 16032)
8
-.:__-Jµ"'r-..:----++++-++H-+Mi-+-+-H-+-t+t+-H-t+--+
~=nn====~
I·
::C:""'
QJ-IJ NTSO
;:-++-++---+-11-+-+-+-1-+-+-+++-1-+-+++-+-++-+-t-++-+-++-H---r-)---t
;: -++++-+-11-++-t-H-i-++t-t-t++t--i-+++-++1+-+t-H--C>---i~
CYCLED 12
:;
f..c
./>-----i-i
jVo- OE
ERRLATCH
·1 -++-++---+-11-+-+-+1-+-+-+++-1-+-+++-+-++-+-++-1-+-++-+-+----r=>--1,
9 (PAL #3 OUTPUT)
">.
z
11
.... _.
0111 4'iol '191Qll 1111~1~ 1111/lij\~ JUlllll ,,/.J~il l·t~JU)l
....,~
Figure 8.14.14 Logic Diagram of PAL Device #1
266 Programmable Logic Design Guide
(PAL#1)
RFSH 1
(PAL#1)
RASIN
2
.......
~ ..,
AO
3 .....
l.Z
.. v
4 H8E..._,
~
rv
M' (16032)
U)
eI..
(I)
E
ODIN
5 ..... ...2. ...",.
-~
u
::I (16032)
e"C
a.
ADS
6 ....
..~ . v
(16201) NTSO 7 ....
--1~ r·v
PAL#1)
2 CLY 8
-.1.. ...7.,
PAL#1)
4 DLY -9 - - 1...,..-
r-v
Inputs (0-31)
0 Ill
. 0
I l I
5 I l
· 517
I !11011 UllUIS 11111119 10212221 2·252121 212'l0J1
I
'11
~
"II
111·
IS
11 II II
"lO
ll 11 11
l· IS ll 11 ll ll 10 ll
--<!
ll II IC IS II II II II
·c1a
Cl
u
...0
Cl
..,.
so
SI Sl 51 5· 5S
51 SI SI
SI IO II ll II
-,
0 11 l
· 5I 1
I I Tl
111011 12131415 11111119 202121ll 242S2127 212UOJI
; : i , .........
t;: ::J
OBO 19
-i
19' l
A ~t--
"V ...
~] J..:...
OB1
lg:
18
- ;:J"""'"'
1--
~ '---
PeUF1o7
16
~
"""'"
~ h l , ~::::::]
PBUF1 16
-yo-
A
~ -v ...
...............
~
~
~ DOUTB 15
.A
~
-....
>-tl .~....... """'-
INC1Y4
~ It
"""'"
~ CSOE 13
cs
OE
"' --v<-...
TRIS TAT E INPUT, MUST
BE HIGH TO
i::
~ ~
t:
; : i CWAIT ENABLE 12 PAL OUTPUT
~
~ IA,
ERR LATCH
-<'-v ....
11
Figure 8.14.15 Logic Diagram of PAL Device #2
Applications 267
(16201) 1
.
ODIN
. ...,
0 Ill
~- (PAL#1) RFSH
----+-<
4 II 1
i-
AOHBE
3
IF EITHER IS HIGH THE OUTPUT IS LOW
4 ...
ERRLATCH
11
"11
ti
(PAL#1}
1DiY ~
Mc.o '
eI .
2· n
Cl)
21
E
11
~
u
:J
e'tJ
CL
l2 12·
2'
II
. (PAL#1) 6
2DLY I.?
(PAL#1} 7
3DLY
.·o
"·2
..
~...,
Inputs (0-31}
J111 nu unnn unJ.011
~
19
-~
-v
CSOE
PARITYERR
...
18
<..,..-
1
r~..,<_.,,.. :yz'I
"'
.JV
17 PARITY ERR
J
-- 'r< 'I"
i:f=J .JO
I
~
P< WiC'
-{
-i
./"
\ "'1Ao'
16 WIN
15 MODECC
,-. ·- .....:. J
"lit( 'I"
~
""1.9tt
jl..F
14
\ ~
~
13
<:-
-v
E1
... (PAL#1} 8 4DLY
~
12
·~
....,
EO
9 ...
~
11
...
_.<..Q,,
AE
1111 ' s 11 111011 1111
1111
lOllllU 24252527 11211111
Figure 8.14.16 Logic Diagram of PAL Device #3
268 Programmable Logic Design Guide
EO
8 ...
El
~
E01
9 ... 3DLY ~
~
...,... 1
·~"'
'. /
j
~.,
1
'. /
j
_,<
,,......
-~"'
'. /
' ~
' ,~ ....
~
'
' ... ~
'
./
j
~.,
tr;I~ ERRLATCH
~ ~
~~ "'
12 ODIN
~ OE
Figure 8.14.17 Logic Diagram of PAL Device #4
9
National Masked Logic (NML)
National Masked Logic (NML) was introduced to provide cost benefits of volume production to programmable logic users who have large volume applications for a given logic pattern. NML devices are mask-programmed and functionally tested in-house by Natfonal, thus relieving the customer of programming and testing the devices. Therefore, for these volume applications, the customer can simplify his production line and gain cost savings through the use of NML.
The NML option is available for all of National's programmable logic products. The NML products have the same data sheet specifications as the field-programmable products. The following are the procedures and guidelines involved in using NML.
9.1 NML PROCEDURE
The procedure for using NML is shown in Figure 9.1.1. When a customer has decided on the NML approach, the equations should be supplied to National for generation of programmed parts. These programmed devices are then sent to the customer for verification of the logic pattern in the application. After the logic has been verified by the customer in his circuit, National is notified. At that point orders for the masks are placed in-house at National. At the same time, the Test Engineering and Product Engineering departments prepare to test and qualify the product upon generation of first silicon. After successful testing and qualification, the product is released for routine production.
When the order is placed the customer will also be required to provide test vectors to functionally test the logic. When considering the use of NML, the customer should keep in mind the need for functional testing of the part. He should generate a sequence of test vectors that will test the logic functionality to meet his needs.
269
270 · Programmable Logic Design Guide
CUSTOMER INPUT (EQUATIONS)
OK
VERIFICATION
8-12 WEEKS
MARKETING APPLICATIONS ENERATES BIT MAP
MASKS MADE
ENGINEERING PREPARES
TO QUAL/TEST
Figure 9.1.1 NML-Procedure
9.2 NML GUIDELINES
In evaluating whether NML is an economic option for a certain application, ·it is important to keep in mind the following guidelines. The most important and somewhat obvious point is that the logic pattern must be verified and frozen. A minimum quantity for economic justification of NML is at least 10,000 units. At these volumes there is usually a nominal charge for mask generation. The lead time from the point at which the equations are verified to the point at which finished goods are shipped is 8-12 weeks.
NML users typically realize cost savings of between 10-40% over the cost of unprogrammed devices, depending on the volume and the device being used. Keep in mind that NML users do not have to incur programming and testing costs associated with unprogrammed devices.
10
Advantages of National's Programmable Logic Family
National Semiconductor has taken leadership of the programmable logic .market through commitments in technology, quality, customer service and support, and by offering a broad product line. In addition, National is also committed to continuing developments in software leading to automated design with programmable logic products.
10.1 TECHNOLOGY
Through innovations in circuit design and process technology, National was the first to introduce the fastest PAL devices, thus clearly establishing itself as the leading technology house for programmable logic devices. The technology used is the proprietary oxide isolated OXISS process that offers higher integration than other bipolar processes and also offers improved performance. The advantages of this superior technology are being harnessed to produce ECL programmable logic devices that will offer speeds at 6 ns. Furthermore, National is also pursuing a major development program to introduce CMOS programmable logic devices.
10.2 BROAD PRODUCT LINE
National's leading technology position has resulted in the broad TTL product line that is currently available. This product line offers a variety of speed, power, and density options as evidenced by the product line description in Chapter 4. For the future, National will offer a broader spectrum of speed and power options through CMOS and ECL devices. More options in the TTL family of programmable products are also forthcoming. Some of the forthcoming features are FPLA-type structures, higher densities, improved testability through register preloads, and scan registers. ,
To complete the product line, National is also committed to software development and support. PLAN is the first step toward meeting that commitment.
271
272 Programmable Logic Design Guide
10.3 CUSTOMER SERVICE AND SUPPORT
Within the field offices, National has fully equipped and trained Field Application Engineers (FAEs) who can support customers in designing with programmable logic. The FAEs also have the software and the development systems at their disposal to fully support the customer. In addition, the factory applications and engineering staff are also available to support the customer in programmable logic-based designs.·
Customer training seminars are also given, as part of National's service, to inform and train customers on programmable logic products and their applications.
11
Data Sheets
11.1 PAL DEVICE DATA SHEETS
The PAL device data sheets are broken down into two main sections: 20-pin PALs and 24-pin PALs, and within each section the various speed/power groups are shown separately.
Description
The PAL device family utilizes National's Schottky TTL process and bipolar PROM fusible-link technology to provide user-programmable logic to replace conventional SSI/MSI gates and flip-flops. Typical chip count reduction gained by using PAL devices is greater than 4: 1.
The family lets the systems engineer customize his chip by opening fusible liI?-ks to configure AND and OR gates to. perform desired logic functions. Complex interconnections that previously required. time-consuming layouts are thus transferred from PC board to silicon where they can be easily modified during prototype checkout or production.
The PAL device transfer function is the familiar Sum-of-Products with a single array of fusible links. Unlike the PROM, the PAL device is a programmable AND array, driving a fixed OR array. (The PROM is a fixed AND array driving a programmable OR array.) In addition, the PAL device family offers these options:
· Variable input/output ratio.
· Programmable TRI-STATE® outputs.
· Registers and feedback. Unused inputs are tied directly to Vcc or GND. Product terms with all fuses blown
assume the logical high state, and product terms connected to both true and complement of ~my single input assume the logical low state. Registers consist of D-type flip-flops that are loaded on the low-to-high transition of the clock. PAL device logic diagrams are shown with all fuses blown, enabling the designer to use the diagrams as coding sheets.
The entire PAL device family is programmed using conventional· PROM programmers with appropriate personality and socket adapter cards. Once the PAL device is programmed and verified, two additional fuses may be blown to make verification dif.:. ficult. This feature gives the user a proprietary circuit that is very difficult to copy.
273
274 Programmable Logic Design Guide
Features
· Programmable replacement for SSI and MSI TTL Logic. · Simplifies prototyping and board layout. · Skinny DIP packages. · Reliable titanium-tungsten fuses. · Available in standard, low power and high speed versions.
Part No.
10H8 12H6 14H4 16H2 10L8 12L6 14L4 16L2 16C1 16L8 16R8 16R6 16R4
No. of Inputs
10 12 14 16 10 12 14 16 16 10 8 8
8
No. of Outputs
8 6 4 2 8 6 4 2 1 8 8 8 8
No. of I/Os
6 2 4
No. of Registers
8 6 4
Output Polarity
AND-OR AND-OR AND-OR AND-OR AND-NOR AND-NOR AND-NOR AND-NOR AND-OR/NOR AND-NOR AND-OR AND-OR AND-OR
Functions
AND-OR Array AND-OR Array AND-OR Array AND-OR Array AND-OR-Invert Array AND-OR-Invert Array AND-OR-Invert Array AND-OR-Invert Array AND-OR/AND-OR-Invert Array AND-OR-Invert Array AND-OR-Invert Register AND-OR-Invert Register AND-OR-Invert Register
Table 11.1.1 20-Pin PAL Devices
Part No.
12L10 14L8 16L6 18L4 20L2 20L8 20L10 20R8 20R6 20R4 20X10 20X8 20X4
No. of Inputs
12 14 16 18 20 14 12 12 12 12 10 10 10
No. of Outputs
10 8 .6 4 2 2 2 8 6 4 10 8 4
No. of I/Os
6 8 2 4 2 6
No. of Registers
8 6 4 10 8 4
Output Polarity
AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR AND-NOR
Functions
AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert Gate Array AND-OR Invert w/Registers AND-OR Invert w/Registers AND-OR Invert w/Registers AND-OR-XOR Invert w/Registers AND-OR-XOR Invert w/Registers AND-OR-XOR Invert w/Registers
Table 11.1.2 24-Pin PAL Devices
Data Sheets 275
Supply Voltage, Vee Input Voltage Off-State Output Voltage Storage Temperature Range
Operating Programming
7V
12V
5.5V
12V
5.5V
12V
-65°C to +150°C
Table 11.1.3 Absolute Maximum Ratings
IV~~I
Al
OUTPUT
Tc,. A2
COU'L
A1·310 R1·200 R2·7SO R2·390
A1·HO R2·1.1k
':"
':"'
Table 11.1.4 Standard Test Load
EQUIVALENT INPUT ~
8kQ NOM
TYPICAL OUTPUT ~
40Q NOM.
Set-Up and Hold
TIMING
~VJ (SEE NOTE Al
n
INPUT
·
-----~"-t----------ov
-i--f-----.. Im.up
IHOLO
JV
DATA
____ INPUT
, Vr
------ov
Propagation Delay
INPUT
Pulse Width
- - - - - - HIGH-LEVEL PULSE
LOW-LEVEL PULSE
Enable and Disable
IN-PHASE
OUTPUT ----+-"
OUT OF PHASE OUTPUT
Note A: Vr= 1.5V Note B: Ci_ includes probe and jig capacitance. Note C: In the examples above, the phase rela· tionships between inputs and outputs have been chosen arbitrarily.
NORMALLY HIGH VoH
O.SV
OUTPUT
(SI OPENI
NORMALLY LOW OUTPUT
(SI CLOSED!
Note 0: All input pulses are supplied by genera· lions having the following characteristics: PFl'l= 1MHz, Zour=SOQ.
Figure 11.1.1 Test Waveforms and Schematics of Inputs and Outputs
276 Programmable Logic Design Guide
10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2
Recommended Operating Conditions
Symbol
Parameter
Vee
Supply voltage
Military
Commercial
Unit
Min Nom Max Min Nom Max
4.5
5.0 . 5.5 4.75 5.00 5.25
v
loH
High-level output current
-2.0
-3.2
mA
loL
Low-level output current
8
8
mA
TA
Operating free air temperature -55
125 0
75
oc
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
Min
V1H
High-level input voltage
2
V1L
Low-level input voltage
Vic
Input clamp voltage
Vee= MIN 11 = -18 mA
Typ Max Unit
v 0.8 v -1.5 v
VoH
High-level output voltage
Vol 11
Low-level output voltage
Input current at maximum input voltage
Vee= MIN V1H = 2V 2.4
V1L = 0.8V · loH = MAX Vee= MIN V1H = 2V
v1L = a.av loL = MAX
v Vee= MAX V1 = 5.5
v 0.5 v
1.0 mA
l1H
High-level input current
l1L
Low-level input current
Vee= MAX V1 = 2.4V
= Vee= MAX V1 0.4V
25 µ.A - 250 µ.A
ios
Short'circuit output current
Vee= MAX Vo=OV
-30
- 130 mA
ice
Supply current
Vee= MAX
55
90 mA
Switching Characteristics
Over Recommended Ranges of Temperature and Vcc
Symbol
Parameter
tpo From any input to any output
Test Condltionstt R1=5600 R2=1.1 kO
CL.= 15pF
Military
Commercial
TA = - 55°to+125·c TA = o· to 75°c Vee = s.ov z 10% Vee = s.ov ± 5% Unit
Min
Typ
Max Min Typ Max
25
45
25
35 ns
Table 11.1.5 AC and DC Specifications for 20-Pin Standard Small PAL Devices
Data Sheets 277
16L8, 16R8, 16R6, 16R4 Recommended Operating Conditions
Symbol
Parameter
Vee
Supply voltage
Military
Commercial
Min Norn Max Min Nom Max
4.5
5.0
5.5 4.75 5.00 5.25
Unit
v
loH
High-level output current
-2.0
-3.2
mA
loL
Low-level output current
TA
Operating free air temperature -55
12 125· 0
24
mA
75
oc
= ·operating Case Temperature only, Tc 125°C
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol V1H
Parameter High-level input voltage
Test Conditions
Min Typ Max Unit '
2
v
V1L
Low-level input voltage
0.8
v
Vic
Input clamp voltage
Vee= MIN 11 = ·18 mA
-1.5
v
VoH Vol loZH iozL
11 l1H l1L ios
Ice
High-level output voltage
Low-level output voltage
Off-state output current high-level voltage applied
Off-state output current low-level voltage applied
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
Supply Current
16L8 16R4, 16R6, 16R8
Vee= MIN V1H = 2V 2.4
v 1L = o.8v IOH = MAX Vee= MIN V1H = 2V v 1L = o.8v loL = MAX
Vee = MAX. V1H = 2V, Vo = 2.4V. VIL = o.8v
Vee = MAX. V1H = 2V Vo = 0.4V. v1L = o.8v
v
0.5
v
100 µA
- 100 1iA
Vee = MAX V1 = 5.5 V Vee MAX V1 = 2.4V Vee MAX V1 = 0.4V Vcc=MAX Vo=OV
Vee= MAX
1.0 mA
25 µA
- 250 1·A
- 30
- 130 mA
140 180
150 180 mA
Table 11.1.6 AC and DC Specifications for 20-Pin Standard, Medium PAL Devices
278 Programmable Logic Design Guide
Switching Characteristics
Over Recommended Ranges of Temperature and Vcc
Miiitary
Commercial
Symbol
Parameter
Test Condltlonstt R1, R2
TA= -55° to+ 125°C Vcc= 5.0V ± 10%
TA=oo
to 75°C
Unit
Vee 5.0V±5%
Min Typ Max 1 Min Typ Max
tpo Input to output
25 45
25 35 ns
tpo Clock to output
CL= 50pF
15 25
15 25 ns
tpzx Pin 11 to output enable tpxz Pin 11 to output disable
CL =5pF
15 25 15 25
15 25 ns 15 25 ns
tpzx Input to output enable
CL= 50pF
25 45
25 35 ns
tpxz Input to output disable
CL =5pF
25 45
25 35 ns
tw Width of clock
High Low
25
25
ns
25
25
tsu Setup time
16R8, 16R6, 16R4 16X4, 16A4
45
35
ns
th Hold time
0 -15
0 -15
ns
ttSee Standard Test Load and Definition of Waveforms
Table 11.1.6 AC and DC Specifications for 20-Pin Standard, Medium PAL Devices (Cont.)
Data Sheets 279
10H8A, 12H6A, 14H4A, 16H2A, 16C1A, 10L8A, 12L6A, 14L4A, 16L2A Recommended Operating Conditions
Symbol
Vee loH loL TA Tc
Parameter
Supply Voltage High Level Output Current Low Level Output Current Operating Free-Air Temperature Operating Case Temperature
Military
Min Type Max
4.5
5
5.5
-2
12
125
Commercial
Min Typ Max
4.75
5
5.25
-3.2
24
0
75
oc
Units
v
mA mA
oc
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol V1H V1L Vic
Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage
VoH
High Level Output Voltage
VoL
Low Level Output Voltage
11
Input Current at Maximum Input Voltage
l1H
High Level Input Current
l1L
Low Level Input Current
los
Short Circuit Output Current
Ice
Supply Current
Test Conditions
Vee= Min., 11= -18mA Vee= Min., V1H = 2V
V1L = o.sv, loH =Max.
Vee= Min., V1H = 2V
V1L = o.sv, loL =Max.
Vee= Max., V1=5.5V Vee= Max., V1= 2.4 V Vee= Max., V1= 0.4 V Vee=5V Vee= Max.
Min. Typ. Max. Unit
2
v
0.8 v
-1.5
v
2.4
v
0.5 v
1 mA
25 µA
-0.25 µA
-30
-130 mA
55
90 mA
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Military: TA= -55°C to + 125°C*, Vee= SV ± 10%
Commercial: TA=O to 75°C, Vee=5V±5%
Symbol
Parameter
tpo
From any Input to any Output
16C1A
Military
Commercial
Test Conditions
Unit
Min. Typ. Max. Min. Typ. Max.
CL=15pF
15 30
15 25 ns
CL= 15pF
35
30 ns
Table 11.1.7 AC and DC Specifications for 20-Pin Fast, Small PAL Devices
280 Programmable Logic Design Guide
16L8A, 16R8A, 16R6A, 16R4A
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
Parameter
Mllltary
Commerclal
Unit
Min. Typ. Max. Min. Typ. Max.
4.5
5
5.5 4.75 5 5.25 v
tw
Width of Clock
Low High
20 10
15 10
ns
20 10
15 10
tsu
Setup Time from Input or Feedback to Clock
16R8A, 16R6A,16R4A
30
16
25 16
ns
th
Hold Time
TA
Operating Free-Air Temperature
Tc
Operating Case Temperature
0 -10
0 -10
ns
-55
0 25 75 oc
125
oc
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol V1H V1L Vic
VoH
VoL
lozH lozL 1, l1H l1L los Ice
Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage
High Level Outp1,1t Voltage
Low Level Output Voltage
Off-state Output Current
Maximum Input Current High Level Input Current Low Level Input Current Output Short-Circuit Current**
Supply Current t
Test Conditions
Vee= Min., 11=-18mA
Vee= Min. V1L=0.8V V1H=2V
loH=~2mA
loH =-3.2mA
Vcc=Min. V1L=0.8V V1H=2V
loL= 12mA loL=24mA***
Vee= Max. Vo=2.4V V1L=0.8V V1H =2V Vo=0.4V
Vee= Max., V1= 5.5 V Vee = Max., V1= 2.4 V
Vee= Max., V1=0.4 V
Vcc=5V Vo=OV
Vee= Max.
MIL COM
MIL COM
Min. Typ. Max. Unit
2
v
0.8
v
-0.8 -1.5
v
2.4 2.8
v
0.3 0.5
v
100 µA -100 µA
1
mA
25
µA
-0.02 -0.25 mA
-30 -70 -130 mA
120 180 mA
t Ice= Max. at minimum temperature.
Table 11.1.8 AC and DC Specifications for 20-Pin Fast Medium PAL Devices
Data Sheets 281
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Military: TA= -55°C to + 125°C*, Vee= 5V ± 10% Commercial: TA= 0 to 75°C, Vee= 5V ± 5%
Symbol
'Parameter
Test Conditions tt
Military
Commerclal
R1,R2
Min. Typ. Max. Min. Typ. Max.
Unit
tpo
Input or Feedback to Output
CL=50pF
15 30
15 25
ns
teLK Clock to Output or Feedback
10 20
10 15
ns
tpzx Pin 11 to Output Enable
10 25
10 20
ns
tpxz Pin 11 to Output Disable
CL=5pF
11
25
11
20
ns
tpzx Input to Output Enable
CL=50pF
10 30
10 25
ns
tpxz Input to Output Disable
CL=5pF
13 30
13 25
ns
fMAX Maximum Frequency
20 30
25 30
ns
ttSee Waveforms, Test Load on pg, 24-21.
Table 11.1.8 AC and DC Specifications for 20-Pin Fast Medium PAL Devices (Cont.)
282 Programmable Logic Design Guide
16L8B, 16R8B, 16R6B, 16R4B Recommended Operating Conditions
Symbol
Parameter
Vee
Supply Voltage
tw
Width of Clock
1 Low
j High
tsu
Setup Time from Input or Feedback to Clock
th
Hold Time
TA
Operating Free-Air Temperature
Tc
Operating Case Temperature
Military
Min Typ Max
4.5
5
5.5
25
10
25
10
50
25
0
-5
-55
125
125
Commercial
Min Typ Max
4.75 5 5.25
25 10
25 10
35 25
0
-5
0
25 75
Units
v
ns
ns ns
oc oc
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
V1H* High Level Input Voltage
V1L* Low Level Input Voltage
Vic Input Clamp Voltage
Test Conditions Vcc=Min., 11= -18mA
Min Typ Max Units
2
v
0.8 v
v -0.8 -1.5
VoH High Level Output Voltage
Vcc=Min. VIL =0.8V V1H=2V
loH= -2mA MIL loH= -3.2mA COM
2.4 3.4
v
Vol Low Level Output Voltage
Vcc=Min. VIL =0.8V V1H=2V
loL = 12mA 10 L=24mA
MIL COM
3.0 0.5
v
lozH Off-State Output Current t
lozL
11
Maximum Input Current
llH
High Level Input Current t
Ill
Low Level Input Current t
Vcc=Max. V1L=0.8V V1H=2V
V0 =2.4V V0 =0.4V
Vcc=Max., V1=5.5V
Vcc= Max., V1= 2.4V
Vee= Max., V1=0.4V
lExcept pins 1 & 11 Fins 1 & 11
100 µA
-100 µA 1 mA 25 µA
-0.04 -0.25 mA
-0.4
las Output Short-Circuit Current** Vcc=5V
V0 =0V
Ice Supply Current
Vcc=Max.
-30 -70 -130 mA 120 180 mA
t 110 pin leakage is the worst case of lozx or l1x e.g. l1L and lozH·
· These are absolute voltages with respect to pin 10 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
· · Only one output shorted at a time.
· · · Pins 1 and 11 may be raised to 20V max.
Table 11.1.9 AC and DC Specifications for 20-Pin Ultra High-Speed, Medium PAL Devices
Data Sheets 283
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Military: TA= - 55°C to+ 125°C*, Vee= SV ± 10% Commercial: TA= Oto 75°C, Vee= SV ± 5%
Sym tpo teLK tpzx tpxz tpzx
tpxz
fMAX
Parameter
Input or Feed- 16R6B 16R4B 16LBB back to Output
Clock to Output or Feedback
Pin 11 to Output Enable Pin 11 to Output Disable
Input to Output Enable
16R6B 16R4B 16LBB
Input to Output Disable
16R6B 16R4B 16LBB
Maximum Frequency
16RBB 16R6B 16R4B
Test Conditions Min
R1 =200Q R2=390Q
30
Military Typ Max
11
20
8
15
10 20
10 20
11
25
11
20
50
Commercial Min Typ Max
11
15
8
12
10 15
10 15
11
20
11
15
40 50
Units
ns ns ns ns ns
ns
MHz
Table 11.1.9 AC and DC Specifications for 20-Pin Ultra High-Speed, Medium PAL Devices (Cont.)
284 Programmable Logic Design Guide
10H8A2, 12H6A2, 14H4A2, 16H2A2, 16C1A2, 10L8A2, 12L6A2, 14L4A2, 16L2A2 Recommended Operating Conditions
Symbol
Vee loH loL TA
Parameter
Supply Voltage
High-Level Output Current
Low-Level Output Current
1 Small PAL ttt l Medium PAL
Operating Free-Air Temperature
Military
Min Typ Max
4.5
5
5.5
-2.0
8
12
-55
125
Commercial
Min Typ Max
4.75
5
5.25
-3.2
8
24
0
25
75
Units
v
mA mA
·c
Electrical Characterist.ics Over Recommended Operating Temperature Range
Symbol V1H· V1L" Vic
Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage
Test Conditions Vee= Min., 11 = -18 mA
Min
Typ
Max Units
2
v
0.8
v
-0.8
-1.5
v
Vee= Min. loH = -2mA
MIL
VoH
High Level Output Voltage
V1L = o.8V
2.4
2.8
v
V1H c= 2V
loH = -3.2mA COM
Vee= Min.
Vol
Low Level Output Voltage
V1L = o.8V loL =Max.
V1H = 2V
0.3
0.5
v
lozH lozL
Off-State Output Currentt
Vee= Max. V1L = o.8V V1H = 2V
Vo= 2.4V Vo= 0.4V
100
µA
-100
µA
11
Maximum Input Current
Vee = Max., V1 = 5.5V
1
mA
l1H
High Level Input Currentt
Vee = Max., V1 = 2.4V
l1L
Low Level Input Currentt
Vee = Max., V1 = 0.4V
25
µA
-0.02 -::..0.25 mA
los
Output Short-Circuit Current·· Vee= Max., Vo= OV
-30
-70
-130
mA
Ice
Supply Current
Vee-= Max.
Small PALttt Medium PAL
28
45
mA
70
90tt
t 1/0 pin leakage is the worst case of lozx or l1x. e.g. l1L and lozH· tt Maximum Ice specification applies to unprogrammed devices only. Ice could increase up to 10% for programmed units. ttt Small PAL consists of 10H8A2, 12H6A2, 14H4A2, 16H2A2, 16C1A2, 10L8A2, 12L6A2, 14L4A2 and 16L2A2. Medium PAL consists of 16L8A2, 16R8A2,
16R6A2 and 16R4A2. ~ These are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system and/or tester noise. Do not attempt to test
these values without suitable equipment.
· · Only one output shorted at a time.
· · · Pins 1 and 11 may be raised to 20V max.
Table 11.1.10 AC and DC Specifications for 20-Pin Fast, Half-Power, Small PAL Devices
Data Sheets 285
Switching Characteristics Over Recommended Ranges of Temperature and Vee
Military: TA = -55·c to + 125·c·, Vee = 5V± 10%
Commercial: TA = o to 75·c, Vee = 5V ± 5%
Symbol
Parameter
Teat Condition·
tpo
Input or Feedback to Output
tcLK
Clock to Output or Feedback
tpzx
Pin 11 to Output Enable
CL= 50pF
tpxz
Pin 11 to Output Disable
CL= 5pF
tpzx
Input to Output Enable
CL= 50pF
tpxz
Input to Output Disable
CL= 5pF
fMAX
Maximum Frequency
tw
Width of Clock
1Low High
Setup Time from Input
tsu
or Feedback to Clock
th
Hold Time
Note: The max lpo ol 16C1A2 in commercial range is 40 ns.
Military
Min Typ Max
25
45
15
25
15
25
15
25
25
45
25
45
14
25
25
10
25
10
50
25
0
-15
Commercial
Min Typ Max
25
35
15
25
15
25
15
25
25
35
25
35
16
25
25
10
25
10
35
25
0
-15
Units
ns ns ns ns ns ns MHz ns ns
ns
ns
Table 11.1.10 AC and DC Specifications for 20-Pin Fast, Half-Power, Small PAL Devices (Cont.)
286 Programmable Logic Design Guide
16'-:8A2, 16R8A2, 16R6A2, 16R4A2 Recommended Operating Conditions
Symbol
Parameter
Vee
Supply Voltage
tw
Width of Clock
1 Low l High
tsu
Setup Time from Input or Feedback to Clock
th
Hold Time
TA
Operating Free-Air Temperature
Tc
Operating Case Temperature
Military
Commercial
Min Typ Max Min Typ Max
4.5
5
5.5 4.75 5 5.25
25
10
25 10
25
10
25 10
50
25
35 25
0
-15
0 -15
-55
125 0
25 75
125
Units
v
ns
ns ns
oc oc
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
VIH * High Level Input Voltage
VIL* Low Level Input Voltage
Vic
Input Clamp Voltage
VoH High Level Output Voltage
Vcc=Min., 11= -18mA
Vcc=Min. V1L=0.8V V1H=2V
loH= -2mA loH= -3.2mA
MIL COM
Vol Low Level Output Voltage
Vee= Min.
V1L = 0 . 8 V V1H=2V
10 L= 12mA MIL 10 L=24mA COM
lozH Off-State Output Current t
lozL
Vcc=Max. V0 =2.4V
V1L=0.8V V1H=2V
V0 =0.4V
11
Maximum Input Current
Vee= Max., V1=5.5V
llH
High Level Input Current t
Vcc= Max., V1= 2.4V
Ill
Low Level Input Current t
Vee= Max., V1=0.4V
los
Output Short-Circuit Current** Vcc=5V, V0 =0V
Ice
Supply Currenttt
Vee= Max.
Min Typ 2
-0.8
Max
0.8 -1.5
Units
v v v
2.4 3.4
v
v 0.3 0.5
100 µA -100 µA
1 mA 25 µA -0.02 -0.25 mA -30 -70 -130 mA 70 90tt mA
t 1/0 pin leakage is the worst case of lozx or l1x e.g. l1L and lozH· tt Maximum Ice specification applies to unprogrammed devices only. Ice could increase up to 10% for programmed units.
· These are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
Only one output shorted at a time. · · Pins 1 and 11 may be raised to 20V max.
Table 11.1.11 AC and DC Specifications for 20-Pin Fast, Half Power Medium PAL Devices
Data Sheets 287
Programmable Array Logic PAL Low Power PAL Series 20A2
Symbol
Parameter
tpo
Input or Feedback to Output
Clock to Output or Feedback
tpzx
Pin 11 to Output Enable
tpxz
Pin 11 to Output Disable
tpzx
Input to Output Enable
tpxz
Input to Output Disable
fMAX
Maximum Frequency
Mlllt~
Test Condltlonstt Min Typ Max
25 50
CL =50pF
15 25
15 25
CL =5pF
15 25
CL =50pF
25 45
CL =5pF
25 45
14 25
Commercial Min Typ Max
25 35 15 25 15 25 15 25 25 35 25 35 16 25
Unit
ns ns ns ns ns ns MHz
Table 11.1.11 AC and DC Specifications for 20-Pin Fast, Half Power Medium PAL Devices (Cont.)
288 Programmable Logic Design Guide
16L8B2, 16R8B2, 16R6B2, 16R4B2 Recommended Operating Conditions
Symbol
Parameter
Vee
Supply Voltage
tw
Width of Clock
Low High
tsu
Setup Time from Input or Feedback to Clock
16R8B, 16R6B, 16R4B
th
Hold Time
TA
Operating Free-Air Temperature
Tc
Operating Case Temperature
Mllltai'y
Min Typ Max
4.5
5
5.5
20 10
20 10
25 10
Commercial
Min Typ Max 4.75 5 5.25 15 8 15 8 20 10
Units v ns ns
0
-5
A
0
-55
[/'···JS 0
-5 25 75
ns
oc
;;;::;. ...·.((/'. ~~O\I}:_
oc
:>·······-.·)···
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
V1H* High Level Input Voltage
~
~
~dltlons
VIL* Low Leve.I Input Voltage
v,c
Input Clamp Voltage
~~> ./;:! - ,j:( ""b~.l- 18mA
Von~ VoH High level output
[~i:{.!~· 10H= -2mA
MIL
iy.lli.
loH = - 3.2mA COM
Voltag;l\~!> Vol Low Level Output
= Vee= Min. loL 12mA
V1L=0.8V
MIL
V1H=2V loL =24mA
COM
lozH Off-State Output Current t
lozL
1,
Maximum Input Current
Vee= Max. V1L=0.8V V1H=2V
V0 =2.4V V0 =0.4V
Vcc= Max., V1=5.5V
llH
High Level Input Current t
Vcc=Max., V1=2.4V
Ill
Low Level Input Current t
Vcc= Max., V1= 0.4V
los
Output Short-Circuit Current** Vcc=5V, V0 =0V
Ice
Supply Currenttt
Vee= Max.
Min Typ Max Units
2
v
-0.8
0.8 v
1.5 v
2.4 3.4
v
0.3 0.5 v
100 µ.A -100 µ.A
1 mA
25 µ.A
-0.01 -0.25 mA
-30 -70 -130 mA
70
90 mA
t 1/0 pin leakage is the worst case of lozx or 11x e.g. 111. and lozH· tt Maximum Ice specification applies to unprogrammed devices only. Ice could increase up to 10% for programmed units.
· These are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system and/or tester noise. Do
not attempt to test these values without suitable equipment.
Only one output shorted at a time.
· · Pins 1 and 11 may be raised to 20V max.
Table 11.1.12 AC and DC Specifications for 20-Pin Ultra High-Speed, Half Power, Medium PAL Devices
Data Sheets 289
Switching Characteristics
Military: TA= -55°C to+ 125°C*, Vee= SV ± 10% Commercial: TA= 0 to 75°C, Vcc= SV ± 5%
Symbol
Parameter
Test Conditions
tpo
Input or Feed- 16R6B 16R4B 16LBB
back to Output
tcLK
Clock to Output or Feedback
tpzx
Pin 11 to Output Enable
tpxz
Pin 11 to Output Disable
tpzx
Input to
16R6B 16R4B 16LBB
Output Enable
R1 =2000 R2 =3900
tpxz
Input to
16R6B 16R4B 16LBB
Output Disable
Maximum
fMAX
Frequency
16RBB 16R6B 16L4B
Military
Commercial
Unit
Min Typ Max Min Typ Max
15
30
15 25
ns
11
8 20
8 15 ns
10 25
10 20 ns
10 25
10 20 ns
11 30
11 25 ns
11 30
11 25 ns
20 30 50
25 30 40
MHz
· These are absolute voltage with respect to pin 10 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
· · Only one output shorted a time.
t 1/0 pin leakage is the worst case of 10 zx or 11x e.g. l1L and 10 zw
Table 11.1.12 AC and DC Specifications for 20-Pin Ultra High-Speed, Half Power, Medium PAL Devic.es (Cont.)
290 Programmable Logic Design Guide
12L10,14L8,16L6,18L4,20L2,20C1 20L10,20X10,20X8,20X4
Operating Conditions
Symbol
Parameter
Vee Supply Voltage TA Operating Free-air Temperature Tc Operating Case_ Temperature
Military
Commercial Unit
Min lYP Max Min Typ Max
v 4.5 5 5.5 4.75 5 5.25
0
75 oc
-55
125
oc
Electrical Characteristics Over Operating Conditions
Symbol Parameter
Test Conditions
VIL
Low Level Input Voltage
.VIH
High Level Input Voltage
Vic
Input Clamp Voltage
l1L
t Low Level Input Current
l1H
t High Level Input Current
Vee= Min. Vee= Max. Vee= Max.
11=-18mA V1=0.4V V1=2.4V
11
Maximum Input Current
Vee= Max. V1=5._5V
VoL Low Level Output Voltage
Vee= Min.
v1L = o.0v
11H=2V
loL = 12mA loL =24mA
MIL COM
VoH High Level Output Voltage
Vee= Min.
V1L =0.8V V1H =2V
loH=-2mA
MIL
loH =-3.2mA COM
t lozL Off-state Output Current
lozH
Vee= Max.
V1L =0.8V V1H =2V
V0 =0.4V V0 2.4V
los
Output Short-Circuit Current** Vee= Max. V0 =0V
Ice
Supply Current
Vee= Max.
20X4, 20X8, 20X10 20L10
t 1/0 pin leakage is the worst case of 10zx or 11x, e.g., 11L and lozH·
· Pins 1 and 13 may be raised to 22V max.
·· Only one output shorted at a time.
12L10, 14L8, 16L6 18L4, 20L2, 20C1
Min lYP Max Unit
0.8 2
-1.5 --0.25
25 1
0.5 v
2.4
v
-100 µA
100 µA
-30
-130 mA
120 180 mA
90 165
60 100
Table 11.1.13 AC and DC Specifications for 24-Pin, Standard PAL Devices
Data Sheets 291
Switching Characteristics Over Operating Conditions
Symbol
Parameter
tpo Input or Feedback to Output
tpo Input or Feedback to Output
tcLK Clock to Output or Feedback tpzx Pin 13 to Output Enable tpxz Pin 13 to Output Disable tpzx Input to Output Enable tpxz Input to Output Disable
Low tw Width of Clock
High tsu Set-Up Time from Input or Feedback th Hold Time fMAX Maximum Frequency
Test Conditions R1,R2
20L10, 20X10 20X8,20X4 CL= 50pF 12L10, 14L8, 16L6 18L4, 20L2, 20C1 CL= 50pF CL= 50pF CL= 50pF . CL= 5pF
CL =50pF
CL= 5pF
Military
Commercial Unit
Min Typ Max Min Typ Max
35 60
35 50 ns
25 45
25 40 ns
20 40
20 30 ns
20 45
20 35 ns
20 45
20 35 ns
35 55
35 45 ns
35 55
35 45 ns
40 20
35 20
ns ·
30 10 60 38 0 -15 10.0
25 10 50 38 0 -15 12.5
ns ns ns MHz
Table 11.1.13 AC and DC Specifications for 24-Pin, Standard PAL Devices(Cont.)
292 Programmable Logic Design Guide
20L8A,20R8A,20R6A,20R4A Operating Conditions
Symbol
Parameter
Vee Supply Voltage TA Operating Free-Air Temperature Tc Operating Case Temperature·
Military
Min Typ Max
4.5
5
5.5
-55
125
Commercial
Min Typ Max
4.75 5 5.25
0
75
Units
v oc oc
Electrical Characteristics over Operating Conditions
Symbol
Parameter
V1L Low Level input Voltage
V1H High Level Input Voltage
Vic Input Clamp Voltage
l1L Low Level Input Current t
l1H High Level Input Current t
11
Maximum Input Current
VoL Low Level Output Voltage
VoH High Level Output Voltage
lozL 1-----1 Off-State Output Currentt
lozH los Output Short-Circuit Current** Ice Supply Current
Test Conditions
Vee= Min., 11= -18mA Vee= Max., V1= 0.4 V Vee= Max., V1 = 2.4 V
Vee= Max., V1= 5.5 V
Vcc=Min. V1L=0.8V V1H=2V
loL=12mA loL.;,24mA***
Vee= Min. V1L=0.8V.
V1H=2V
loH=-2mA loH=-3.2mA
Vcc=Max. V1L=0.8V V1H=2V
Vo=0.4V Vo=2.4V
Vcc=5V, Vo=OV
Vcc=Max.
MIL COM MIL COM
Min Typ Max Units
0.8 v
2
v
v · - t - -
-1.5
-0.25 mA
25 µA
1
mA
0.5 v
2.4
v
-100 µA
100 µA
-30
-130 mA
160 210 mA
110 pin leakage is the worst cast of lozx or 11x, e.g. l1L and lozH· Pins 1 and 13 may be raised to 20V max. · · Only one output shorted at a time. These are absolute voltages with 'espect to the ground pin on the device and Includes all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
Table 11.1.14 AC and DC Specifications for 24-Pin, Fast PAL Devices
Data Sheets 293
Switching Characteristics over Operating Conditions
Symbol
Parameter
tpo
Input or Feedback to Output
lcLK
Clock to Output or Feedback
tpzx
Pin 13 to Output Enable
tpxz
Pin 13 to Output Disable
tpzx
Input to Output Enable
tpxz
Input to Output Disable
l Low
tw
l Width of Clock
High
tsu
Setup Time from Input or Feedback
th
Hold Time
IMAX
Maximum Frequency
Test Conditions
20L8A, 20R6A 20R4A CL=50pF CL= 50pF CL=50pF CL=5pF CL=50pF CL=5pF
20R8A, 20R6A, 20R4A
Military Min Typ Max
18
30
12
20
10
25
11
25
10
30
13
30
20
7
20
7
30
18
0 -10
20
40
Commercial Min Typ Max
Units
18
25
ns
12
15
ns
10
20
ns
11
20
ns
10
25
ns
13
25
ns
15
7
ns
15
7
ns
25
18
ns
0 -10 28.5 40
ns MHz
Table 11.1.14 AC and DC Specifications for 24-Pin, Fast PAL Devices (Cont.)
294 Programmable Logic Design Guide
11.2 PROGRAMMING/VERIFYING PROCEDURE - 20 PIN PAL DEVICES*
As long as Pin 1 is at HH, Pin 11 is at ground, and Pin 12 is either at HH or Z (as defined in Table 11.2 .1) - Pins 16, 17, 18, and 19 are outputs. The other pin functions are: IO (Pin 2) through 17 (Pin 9) plus Pin 12 address the proper row; AO (Pin 15), Al (Pin 14), and A2 (Pin 13) address the proper product lines.
When Pin 11 is at HH, Pin 1 is at ground, and Pin 19 is either at HH or Z - Pins 12, 13, 14, and 15 are outputs. The other pin functions are: IO (Pin 2) through 17 (Pin 9) plus Pin 19 address the proper row; AO (no~ Pin 18), Al (now Pin 17), and A2 (now Pin 16) address the proper product lines.
PRODUCTS 0 THRU 31
PRODUCTS 32 THRU 63
Figure 11.2.1 Pin Assignment for Programming
Pre-Verification
Step 1.1 Raise Vcc to 5V. Step 1.2 Raise Output Disable pin, OD, to VrnH· Step 1.3 Select an input line by specifying Inputs and L/R as shown in Table 11.2.2. Step 1.4 Select a product line by specifying AO, Al and A2 one-of-eight select as shown
in Table 11.2.2 Step 1.5 Pulse the CLOCK pin and verify (with CLOCK at V1L) that the output pin, 0, is
in the state corresponding to an unblown fuse. - For verified unblown condition, continue procedure from Step 1.3 through Step 1.5. - For verified blown condition, stop procedure and reject part.
Note: For programming purposes many PAL pins have double functions.
Data Sheets 295
Input Line
Pin Identification
Number 17 15 Is 14 13 12 11 lo L/R
0 HH HH HH HH HH HH HH L z 1 HH HH HH HH HH HH HH H z
2 HH HH HH HH HH HH HH L HH
3 HH HH HH HH HH HH HH H HH 4 HH HH HH HH HH HH L HH z 5 HH HH HH HH HH HH H HH z
6 HH HH HH HH HH HH L HH HH
7 HH HH HH HH HH HH H HH HH 8 HH HH HH HH HH L HH HH z 9 HH HH HH HH HH H HH HH z 10 HH HH HH HH HH L HH HH HH
11 HH HH HH HH HH H HH HH HH 12 HH HH HH HH L HH HH HH z 13 HH HH HH HH H HH HH HH z
14 HH HH HH HH L HH HH HH HH
15 HH HH HH HH H HH HH HH HH 16 HH HH HH L HH HH HH HH z 17 HH HH HH H HH HH HH HH z
18 HH HH HH L HH HH HH HH HH
19 HH HH HH H HH HH HH HH HH 20 HH HH L HH HH HH HH HH z 21 HH HH H HH HH HH HH HH z
22 HH HH L HH HH HH HH HH HH
23 HH HH H HH HH HH HH HH HH 24 HH L HH HH HH HH HH HH z 25 HH H HH HH HH HH HH HH z
26 HH L HH HH HH HH HH HH HH
27 HH H HH HH HH HH HH HH HH 28 L HH HH HH HH HH HH HH z 29 H HH HH HH HH HH HH HH z
30 L HH HH HH HH HH HH HH HH
31 H HH HH HH HH HH HH HH HH
Table 11.2.1 _Input Line Select
Product Line
Pin Identification
Number 03 02 01 Oo A2 A1 Ao
0,32 z z z HH z z z 1,33 z z z HH z z HH 2,34 z z z HH z HH z 3,35 z z z HH z HH HH
4,36 z z z HH HH z z 5,37 z z z HH HH z HH 6,38 z z z HH HH HH .z 7,39 z z z HH HH HH HH
8,40 z z HH z z z z 9,41 z z HH z z z HH 10,42 z z HH z z HH z 11,43 z z HH z z HH HH
12,44 z z HH z HH z z
13,45 z z HH z HH z HH 14,46 z z HH z HH HH z 15,47 ·z z HH z HH HH HH
16,48 z HH z z z z z 17,49 z HH z z z z HH 18,50 z HH z z z HH z 19,51 z HH z z z HH HH
20,52 z HH z z HH z z
21,53 z HH z z HH z HH 22,54 z HH z z HH HH z 23,55 z HH z z HH HH HH 24,56 HH z z z z z z 25,57 HH z z z z z HH 26,58 HH z z z z HH z 27,59 HH z z z z HH HH 28,60 HH z z z HH z z 29,61 HH z z z HH z HH 30,62 HH, z z z HH HH z
31,63 HH z z z HH HH HH
Table 11.2.2 Input Line Select
Programming Algorithm
Step 2.1 Raise Output Disable pin, OD to Vmtt·
Step 2.2 Programming pass. For all fuses to be blown: Step 2.2.1 Lower CLOCK pin to ground. Step 2 .2 .2 Select an input line by specifying Inputs and L/R as shown in Table 11.2.2. Step 2.2.3 Select a product line by specifying AO, Al and A2 one-of-eight select as shown in Table 11.2.2.
Step 2 .2 .4 Raise Vcc to IHH.
296 Programmable Logic Design Guide
Step 2.2.5 Program the fuse by pulsing the output pins of the selected product group one at a time to VrnH (as shown in the Programming Waveforms).
Step 2.2 .6 Lower Vcc to 5V. Step 2.2.7 Repeat this procedure from Step 2.2.2 until pattern is complete.
Step 2.3 First verification pass. For all fuse locations: Step 2.3. l Select an input line by specifying Inputs and L/R as shown in Tables 11.2.1 and 11.2.2. Step 2.3.2 Select a product line by specifying AO, 'Al, and A2 one-of-eight select as shown in Table 11.2 .2. Step 2.3.3 Pulse the CLOCK pin and verify (with CLOCK at V1t) that the output pin, 0, is in the correct state. - For verified output state, continue procedure. - For overblow condition, stop procedure and reject part. - For underblow condition, reexecute Steps 2.2.4 through 2.2.6 and 2.2.3. If successful, continue procedure. After three attempts to blow fuse without success, reject part but continue procedure. Step 2.3.4 Repeat this procedure from Step 2.3.i until the entire array is exercised.
Step 2.4 High Voltage Verify. For all fuse locations: Step 2.4.1 Raise Vcc to 5. 5V. Step 2.4.2 Select an input line by specifying Inputs and L/R as shown in Tables 11.2.1 or 11.2.2. Step 2.4.3 Select a product line by specifying AO, Al, and A2 one-of-eight select as shown in Table 11.2.2. Step 2.4.4 Pulse the CLO-CK pin and verify (with CLOCK at V1t) that the output pin, 0, is in the correct state. - For verified output state, continue procedure. - For invalid output state, stop procedure and reject part. Step 2.4.S Repeat this procedure from Step 2.4.1 ·until the entire array is exercised.
Step 2.5 Low Voltage Verify. For all fuse locations: Step 2.5.1 Lower Vee to 4.SV. Step 2.5.2 Select an input line by specifyiµg inputs and L/R as shown in Tables 11.2.1 or 11.2.2. Step 2.5.3 Select a product line by specifying AO, Al, and A2 one-of-eight select as shown in Table 11.2.2.
*NSC programming spec. Rev. 1. The old programming spec. is still valid.
Data Sheets 297
Step 2.5.4 Pulse the CLOCK pin and verify (with CLOCK at V1L) that the out, put pin, 0, is in the correct state. - For verified output state, continue procedure. - For invalid output state, continue procedure and reject part.
Programming the Security Fuses
Step 3-. 1 Verify per Step 2.4 and Step 2.5.
Step 3.2 Raise Vcc to 6V.
Step 3.3 Program the first fuse by pulsing Pin 1 to Vp. (From 1 to 5 pulses is acceptable.)
Step 3.4 Program the second fuse by pulsing Pin 11 to Vp. (1 to 5 pulses is acceptable.)
Step 3.5 Verify per Step 2.4 and Step 2.5: - A device is "secure" if either half fails to verify.
Voltage Legend
L =Low level input voltage, V1L
HH =High level program voltage, VrnH
H =High level input voltage, Vrn
z = 10 kn to 5V
Note: For programming purposes many PAL device pins have double functions.
298 Programmable Logic Design Guide
11.3 PROGRAMMING/VERIFYING PROCEDURE - 24 PIN PAL DEVICES*
As long as Pin 1 is at HH, Pin 13 is at ground, and Pin 14 is either at HH or Z (as defined in Table 11.3 .1) - Pins 19, 20, 21, and 22 are outputs. The other pin functions are: 10 (Pin 2) through 19 (Pin 11) plus Pin 14 address the proper row; AO (Pin 15), Al (Pin 16), and A2 (Pin 17) address the proper product lines.
As long as Pin 13 is at HH, Pin 1 is at ground, and Pin 23 is either at HH or Z (as defined in Table 11.3.1) - Pins 15, 16, 17 and 18 are outputs. The other pin functions are: 10 (Pin 2) through 19 (Pin 11) plus Pin 23 address the proper row; AD (Pin 22), Al (Pin 21), and A2 (Pin 20) address the proper product lines.
PRODUCTS 0 THRU 39
PRODUCTS 40 THRU 79
OD
Yee
CLOCK
Yee
lo
Oo
lo
UR
11
01
11
Ao
12
02
12
A1
13
03
13
A2
1,
o,
1,
NC
15
NC
15
Oo
Is
A2
Is
01
17
A1
l7
02
1,
Ao
la
03
lg
UR
lg
o.
GND
CLOCK
GND
OD
Top View
Top View
Figure 11.3.1 Pin Assignment for Programming
Pre-Verification
Step 1.1 Raise Vcc to 5V.
Step 1.2 Raise Output Disable pin, OD, to VrnH·
Step 1.3 Select an input line by specifying Inputs and L/R as shown in Table 11.3 .1.
Step 1.4 Select a product line by specifying AO, Al and A2 one-of-eight select as shown
in Table 11.3.2.
·
Step 1.5 Pulse the CLOCK pin and verify (with CLOCK at V1L) that the output pin, OH, is in the state corresponding to an unblown fuse. - For verified unblown condition, continue procedure from Step 1.3
through Step 1.5. - For verified blown condition, stop procedure and reject part.
Programming Algorithm
Step 2.1 Raise Output Disable pin, OD, to VrnH·
Step 2.2 Programming pass. For all fuses to be blown: Step 2.2 .1 Lower CLOCK pin to ground. Step 2.2 .2 Select an input line by specifying inputs and L/R as shown in Table 11.3.1.
Data Sheets 299
Input Line Number
Pin Identification
0 HH HH HH HH HH HH HH HH HH L Z 1 HH HH HH HH HH HH HH HH HH H Z 2 HH HH HH HH HH HH HH HH HH L HH
3 HH HH HH HH HH HH HH HH HH H HH 4 HH HH HH HH HH HH HH HH L HH Z
5 HH HH HH HH HH HH HH HH H HH Z 6 HH HH HH HH HH HH HH HH L HH HH 7 HH HH HH HH HH HH HH HH H HH HH
8 HH HH HH HH HH HH HH L HH HH Z 9 HH HH HH HH HH HH HH H HH HH Z 10 HH HH HH HH HH HH HH L HH HH HH 11 HH HH HH HH HH HH HH H HH HH HH 12 HH HH HH HH HH HH L HH HH HH Z 13 HH HH HH HH HH HH H HH HH HH Z 14 HH HH HH HH HH HH L HH HH HH HH 15 HH HH HH HH HH HH H HH HH HH HH 16 HH HH HH HH HH L HH HH HH HH Z 17 HH HH HH HH HH H HH HH HH HH Z 18 HH HH HH HH HH L HH HH HH HH HH 19 HH HH HH HH HH H HH HH HH HH HH 20 HH HH HH HH L HH HH HH HH HH Z 21 HH HH HH HH H HH HH HH HH HH Z 22 HH HH HH HH L HH HH HH HH HH HH 23 HH HH HH HH H HH HH HH HH HH HH 24 HH HH HH L HH HH HH HH HH HH Z 25 HH HH HH H HH HH HH HH HH HH Z 26 HH HH HH L HH HH HH HH HH HH HH 27 HH HH HH H HH HH HH HH HH HH HH 28 HH HH L HH HH HH HH HH HH HH Z 29 HH HH H HH HH HH HH HH HH HH Z 30 HH HH L HH HH HH HH HH HH HH HH 31 HH HH H HH HH HH HH HH HH HH HH 32 HH L HH HH HH HH HH HH HH HH Z 33 HH H HH HH HH HH HH HH HH HH Z 34 HH L HH HH HH HH HH HH HH HH HH 35 HH H HH HH HH HH HH HH HH HH HH 36 L HH HH HH HH HH HH HH HH HH Z 37 H HH HH HH HH HH HH HH HH HH Z 38 L HH HH HH HH HH HH HH HH HH HH 39 H HH HH HH HH HH HH HH HH HH HH
Table 11.3.1 Input Line Select
Input Line
Pin Identification
Number 04 03 02 01 Oo ~ A1 Ao
0,40 1, 41 2, 42 3,43 4,44 5, 45 6, 46 7, 47 8, 48 9, 49 10, 50 11, 51 12, 52 13, 53 14, 54 15, 55 16, 56 17, 57 18,58 19,59 20, 60 21, 61 22, 62 23, 63 24, 64 25,65 26, 66 27, 67 28, 68 29, 69 30, 70 31, 71 32, 72 33, 73 34, 74 35, 75 36, 76 37, 77 38, 78 39, 79
z z z z HH z z z z z z z HH z z HH z z z z HH z HH z z z z z HH z HH HH z z z z HH HH z z z z z z HH HH z HH z z z z HH HH HH z z z z z HH HH HH HH z z z HH z z z z z z z HH z z z HH z z z HH z z HH z z z z HH z z HH HH z z z HH z HH z z z z z HH z HH z HH z z z HH z HH HH z z z z HH z HH HH HH z z HH z z z z z z z HH z z z z HH z z HH z z z HH z z z HH z z z HH HH z z HH z z HH z z z z HH z z HH z HH z z HH z z HH HH z z z HH z z HH HH HH z HH z z z z z z z HH z z z z z HH z HH z z z .z HH z z HH z z z z HH HH z HH z z z HH z z z HH z z z HH z HH z HH z z z HH HH z z HH z z z HH HH HH HH z z z z z z z HH z z z z z z HHZ HH z z z z z HH z HH z z z z z HH HH HH z z z z HH HH z HH z z z z HH z HH HH z z z z HH HH z HH z z z z HH HH HH
Table 11.3.2 Product Line Select
300 Programmable Logic Design Guide
Step 2.2.3 Select an input line by specifying inputs and L/R as shown 'in Table 11.2.2.
Step 2.2.4 Select a product line by specifying AO, Al, and A2 one-of-eight select as shown in Table 11.2.2
Step 2.2.5 Raise Vee to VrnH· Step 2.2.6 Program the fuse by pulsing the output pins of the selected
product group one at a time to VrnH (as shown in the Programming Waveforms). Step 2.2.7 Lower Vee to 5V. . . Step 2.2.8 Repeat this procedure from Step 2.2.2 uritil pattern is complete.
Step 2.3 First verification pass. For all fuse locations: Step 2.3 .1 Select an input line by specifying Inputs and L/R as shown in Tables 11.2.1 and 11.2.2. Step 2.3:2 Select a product line by specifying AO, Al, and A2 one-of-eight select as shown in Table 11.2.2. Step 2.3.3 Pulse the CLOCK pin and verify (with CLOCK at V1L) that the output pin, 0, is in the correct state. - For verified output state, continue procedure.· - For overblow condition, stop procedure and reject part. - For underblow condition, reexecute Steps 2.2 .4 through 2.2.6 and 2.2.3. If successful, continue procedure, after three attempts to blow fuse without success, reject part but continue procedure. Step 2.3.4 Repeat this procedure from Step 2.3.1 until the entire array is exercised.
Step 2.4 High Voltage Verify. For all fuse locations: Step 2.4.1 Raise Vee to 5.5V. Step 2.4.2 Select an input line by specifying Inputs and L/R as shown in Table 11.3 .1. Step 2.4.3 Select a product line by specifying AO, Al, and A2 one-of-eight select as showri in Table 11.3 .2. Step 2.4.4 Pulse the CLOCK pin and verify-(with CLOCK at V1L) that the output pin, 0, is in the correct state. - For verified output state, continue the procedure. - For invalid output state, stop procedure and reject part. Step 2.4.5 Repeat this. procedure from step 2.4.1 .until the entire array is exercised.
Step 2.5 Low Voltage Verify. For all fuse locations: Step 2.5.1 Lower Vee to 4.5V. Step 2.5.2 Select an input line by specifying inputs and L/R as shown in Table 11.3 .1. Step 2.5.3 Select a product line by specifying AO, Al, and A2 one-of-eight as shown in Table 11.3.2.
Data Sheets 301
Step 2.5.4 Pulse the CLOCK pin and verify (with CLOCK at V1L) that the output pin, 0, is in the correct state. - For verified output state, continue procedure. - For invalid output state, continue procedure and reject part.
Programming the Security Fuses
Step 3 .1 Verify per Step 2.4 and Step 2 .5 Step 3.2 Raise Vee to 6V. Step 3.3 For PAL 24 and PAL 24A:
- Program the first fuse by pulsing Pin 1 to Vp (From 1 to 5 pulses is acceptable.)
- Program the second fuse by pulsing Pin 13 to Vp (1 to 5 pulses is acceptable.)
Step 3.4 Verify per Step 2.4 and Step 2.5: - A device is "secure" if either half fails to verify.
Symbol V1HH
l1HH
leeH tveeP tp to to2
Vp Ip tpp
tRP
VeePP
Parameter
Program Level Input Voltage
Output Program Pulse
Program Level Input Current
OD, LIA
All Other Inputs
Program Supply Gurrent
Pulse Width of Vee@V1HH
Program Pulse Width
Delay Time
Delay Time after UR Pin
Veep Duty Cycle
Security Fuse Programming Voltage
Security Fuse Programming Supply Current
Security Fuse Programming Pulse.Width
Security Fuse Programming Duty Cycle
Rise Time of Output Programming and Address Pulses
Rise Time of Security Fuse Programming Pulses
Vee Value During Security Fuse Programming
Vee Value for First Verify
Vee Value for High Vee Verify
Vee Value for Low Vee Verify
Min Typ Max Units
11.5 11.75 12
v
50
50
mA
10
900 mA
60
µS
10
20
50
µS
100'
ns
10
µS
20
%
18 18.5 19
v
400 mA
10
40
70
µS
50
%
1
1.5 10
V/µs
1
1.5 10
5.75 6 6.25
4.75
5
5.25
v
5.4 5.5 5.6
4.4 4.5 4.6
Table 11.3.3 Programming Parameters
*NSC programming spec. Rev. 1. The old programming spec. is still valid.
302 Programmable Logic Design Guide
Array Programming Waveforms
OD V1HH·~
VIL
rto
CLOCK V I L !
o1 - - - -
VIHH --1--+--ltolm--------
V1H---++
VIL _ _ _°"'"
VIHH ----+--6--------
A, L/R
Vee 5y _ _ _ ___,
REPEAT UNTIL PATTERN IS PROGRAMMED
-to
-to
1-TP-I
VIHH - - - - - - + - + ; . . - - - - i i
0 VoH-----~
VoL-----.1
TL/L/5598·7
Note:
Vee (Low Voltage Verlfy)=4.5V
Vee (High Voltage Verify)=5.5V
Vee (First Verify) = 5v
A Delay (t02) must always precede the Positive Clock Transition. (e.g. see step 1.2.3.3 for underblow condition)
Figure 11.3.2 Programming Waveforms
VIHH OD
VIL Vee
VIHH VIH VIL
VIHH A, L/R
z
VoH 0
VoL
V1H CLOCK
VIL
Verification Waveforms
~ -to
-~lo - I-to
Data Sheets 303
REPEAT UNTIL ARRAY IS VERIFIED
Security Fuse Programming Waveforms
Veep-~~~-~-------------------t
Vee o------
PIN 1
-Tpp-1
to-
Vp~~~~"-t-1...-----.
PIN 11
Figure 11.3.2 Programming Waveforms (Cont.) Refer to Chapter 5 for a List of PAL Programmer Vendors
304 Programmable Logic Design Guide
11.4 LOGIC PROM DATA SHEETS
Description
This generic Schottky PROM family by National provides the industry with one of the widest selections in sizes and organizations. Four-b~t wide PROMs are provided with 256 to 4096 words in pin compatible 16 and 18-pin dual-in-line packages. The 8-bit wide devices range from 32 to 4096 words in a variety of packages. Being 'generic', all PROMs share a common programming algorithm.
National's new Programmable Read-Only Memories (PROMs) feature titaniumtungsten (Ti:W) fuse links designed to program efficiently with only 10.5 Volts applied. The high peformance and reliability of these PROMs are the result of fabrication by a Schottky bipolar process, of which the titanium-tungsten metallization is an integral part, and an on-chip programming circuit is used.
A major advantage -of the titanium-tungsten fuse technology is the low programming voltage of the fuse links. At 10.5 Volts, this voltage level virtually eliminates the need for guard-ring devices and wide spacings required for other fuse technologies. Care is taken, however, to minimize voltage drops across the die and to reduce parasitics. The device is designed to insure that worst~case fuse operating current is low enough for reliable long-term oper.ation. The Darlington programmiilg circuit is liberally designed to insure adequate power density for blowing fuse links. The complete circuit design is optimized to provide high performance over the entire operating ranges of Vcc and temperature.
Testability
The Schottky PROM die includes extra rows and columns of fusible links for testing the programmability of each chip. These test fuses are placed at the worst-case chip locations to provide the highest possible confidence in the programming tests in the final product. A ROM pattern is also permanently fixed in the additional circuitry and coded to provide a parity check of input address levels. These and other test circuits are used to test for correct operation of the row and column-select circuits and functionality of input and enable gates. All test circuits are available at both wafer and assembled device levels to allow 100 % functional and parametric testing at every stage of the test flow.
Reliability
As with all National products, the Ti:W PROMs are subjected to an ongoing reliability evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating life, temperaturehumidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million Schottky Ti:W PROM device hours have been logged. DIP (N-package) and cerdip 0-package). Device performance in all package configurations is excellent.
Data Sheets 305
Supply Voltage (Note 2) Input Voltage (Note 2) Output Voltage (Note 2) Storage Temperature Lead Temperature (10 seconds)
- 0.5 to + 7.0V
-1.2 to + 5.5V
- 0.5 to + 5.5V - 65 to + 150C
300C
Table 11.4.1 Absolute Maximum Ratings
Vcc
R1
GND
*Device input waveform characteristics are; Repetition rate = 1MHz Source impedance= 5011 Rise and Fall times= 2.Sns max. (1.0 to 2.0 volt levels)
*TAA is measured with stable enable inputs. *TEA and TER are measured from the 1.5
volt level on inputs and outputs with all address and enable inputs stable at applicable levels.
*For loL = 16mA, R1=3000 and R2 = 6000
for loL = 12mA, R1 = 4000 and R2 = 8000.
*"C" includes scope and jig capacitance.
Figure 11.4.1 Standard Test Load
TM __ 3.ov "l/lll)A/
ADDRESS OV
v._~_L_ID-----------
~ ~A~~~~~-
OUTPUT
VALID
I~~ I
~TXZ~
TEA__...j
TER--..j
ENABLE
3 ·
:
:
_--_-_-_--J'(--------yL---_-_..
._. -_-_
Figure 11.4.2 Switching Time Waveforms Non-Registered PROMs
306 Programmable Logic Design Guide
I- t,,(A)-1 . 1-ls(A) -1---1 IH(A)
Ao-~-------------1--'fm. I ~.- .............- .............-------~~v
as--/---IJ_I__..\ts.(.\G..\S>l--1-tH(GS)·/IXPsl·ts(Gs)·i---1f-t-H1(Gs1)./.1...1..J..././../ ... ---~~v
1 - 1 ls(GS)l:-=·t,,(GS)1
l'M.(CP)
lwL(CP)
CP
1-1
IWL(CP) ,...-_,...'r'""'T"'T""'l'""'T""T""T"""-------- 3V
~.............,..........._ _ _ -_ -_ -_ -_ -_-_u _v OV
1--~ir=~~
I- t,i_z(0>-1 VOL
----3V
----uv
I isciiiiii--11--
~--_..;--ov
»ITT\\\ fO ~:v -t,,(INIT)· , . . . . , . . . _ - - - - - - - - - - - - - - - - - - - - - - - - - - 3y
Figure 11.4.3 Switching Waveforms, Registered PROM
WAVEFORM INPUTS
OUTPUTS
~
1lU
MUST BE STEADY
MAY CHANGE FROM H TO L
MAY CHANGE FROM L TOH
WILL BE STEADY
WILL BE CHANGING FROM H TO L WILL BE CHANGING FROM L TOH
WAVEFORM
WI»_
)})(ff
INPUTS
DON'T CARE: ANY CHANGE PERMITTED
OUTPUTS
CHANGING: STATE UNKNOWN
DOES NOT APPLY
CENTER LINE ISHIGH IMPEDANCE "OFF" STATE
Figure 11.4.4 Key to Timing Diagram
Data Sheets 307
11.5 DM54/74S188, DM54/74S288 (32 x 8) 256-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 32 words by 8 bits configuration. A memory enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the OFF or high impedance state. The memories are available in both open-collector and TRI-STATE® versions.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
· Advanced titanium-tungsten (Ti:W) fuses. · Schottky-clamped for high speed.
Address access-22 ns typ. Enable access-15 ns typ. Enable recovery-15 ns typ. · PNP inputs for reduced input loading. · All DC and AC parameters guaranteed over temperature. · Low voltage TRI-SAFETM programming.
OpenMilitary Commercial Collector TRI-STATE Package
DM74S188
x
x
N,J
DM74S288
x
x
N,J
DM54S188
x
x
J
DM54S288
x
x
J
Table 11.5.1 (32 x 8) 256-Bit TTL PROM Options
INPUT BUFFER . - - - - - - - - - - - - - - - .
as a1 as as 04 a3 a2 a1
ORDER NUMBER: DM74S188 J, DM74S288 J, DM54S188 J, DM54S288 J SEE NS PACKAGE J16A
ORDER NUMBER: DM74S188 N OR DM74S288 N SEE NS PACKAGE N16A
Figure 11.5.1 Block and Connection Diagram
308 Programmable Logic Design Guide
DM54/74S188, DM54/74S288 (32 x 8) 256-BIT TTL PROMs
DC Electrical Characteristics
(Note 3)
Sym
Parameter
Conditions
DM54S188/288 Min Typ Max
l1L Input Load Current
Vee= Max, V1N = 0.45V
-80 -250
l1H Input Leakage Current Vee= Max, V1N = 2.7V
25
Vee= Max, V1N = 5.5V
1.0
Vol Low Level Output Voltage Vee= Min, loL = 16mA
0.35 0.50
V1L Low Level Input Voltage
0.80
V1H High Level Input Voltage
2.0
loz Output Leakage Current .Vee= Max, VcEx = 2.4V
50
1Open-Collector Only 1
vcc = Max, vCEX = 5.5V
100
Ve ·Input Clamp Voltage
Vee= Min, l1N =-18mA
-0.8 -1.2
C1 Input Capacitance
Vee= 5.0, V1N = 2.0V
4.0
TA= 25C, 1MHz
Co Output Capacitance
Vee= 5.0V, Vo= 2.0V
6.0
TA = 25C, 1MHz, Outputs Off
Ice Power Supply Current
Vee= Max, Inputs Grounded All Outputs Open
70 110
DM74S188/288
Min Typ Max -80 -250 25 1.0 0.35 0.45 0.80
2.0 50 100
-0.8 -1.2 4.0
6.0
70 110
Units
µA . µA
mA
v v v
µA µA
v
pF
pF
mA
TRI-STATE® Parameters
los Short Circuit Output Current
loz Output Leakage 1TRl-STATE1
VoH Output Voltage High
Vo= OV, Vee= Max 1Note 41
-20
-70 -20
-70 mA
Vee= Max, Vo =·0.45 to 2.4V
+50
+50 µA
Chip Disabled loH=-2.0mA loH= -6.5mA
-50
-50 µA
2.4 3.2
v
2.4 3.2
v
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
Sym
Parameter
JEDEC Symbol
DM54S188/288 Min Typ Max
DM74S188/288 Min Typ Max
Units
TAA Address Access Time TEA Enable Access Time TEA Enable Recovery Time TZX Output Enable Time TXZ -Uutput Disable Time
TAVQV TEVQV TEXQX TEVQX TEXQZ
22 45 15 30 15 35 . 15 30 15 35
; 22 35
ns
15 20 ns
15 25 ns
15 20 ns
15 25 ns
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee= 5.0V and TA= 25C. Note 4: During los measurement. only one output at a time should be grounded. Permanent damage may otherwise result
Table 11.5.2 . AC and DC Specifications for (32 x 8) 256-Bit TTL PROMs
Data Sheets 309
11.6 PL77X288/PL87X288 (32 x 8) 256-BIT TTL LOGIC PROMs
General Description
These Schottky programmable logic devices are organized in the popular 32 words by 8-bit configuration. An enable input is provided to control the output states. When the device is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the OFF or high impedance state. The memories are available in the TRI-STATE® version only.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
o Advanced titanium-tungsten (Ti-W) fuses o Schottky-clamped for high speed
- Addressed access-10 ns typ - Enable access-8 ns typ - Enable recovery-8 ns typ o PNP inputs for reduced input loading o All DC and AC parameters guaranteed over temperature o Low voltage TRI-SAFE TM programming
PL87X288 PL77X288
Military
x
Commercial
x
Open· Collector
TRI-STATE
x x
Package
N, J J
Table 11.6.1 (32 x 8) 256-Bit TIL PROM Options
Dual·ln-Llne Package
A4
A3 A2
256 BIT OR ARRAY PROVIDING
oo
16 Vee
Al
ALL 32 PRODUCT TERMS
01
15
AO
02
14 A4
03
13 A3
ii
04
12 A2
07
06
05
04
03
02
01
00
05
11 Al
06
10 AO
GND
07
TOP VIEW
Figure 11.6.1 Block and Connection Diagram
310 Programmable Logic Design Guide
PL77X288/PL87X288 (32 x 8) 256-BIT TTL LOGIC PROMs
DC Electrical Characteristics (Note 3)
Symbol
Parameter
Conditions
l1L Input Load Current Vee= Max, V1N = 0.4V l1H Input Leakage Current Vee:; Max, V1N = 2.7V
Vee= Max, V1N = 5.5V
VoL Low Level Output Voltage
Vee= Min, loL = 24 mA (Com) loL = 12 mA (Mil)
V1L Low Level Input Voltage
(Note?)
V1H High Level Input Voltage
(Note?)
Ve Input Clamp Voltage Vcc=Min,1 1N= -18mA
c, Input Capacitance Vee= 5.0V, V1N = 2.0V
TA=25°C, 1 MHz
Co Output Capacitance Vee= 5.0V, Vo= 2.0V
TA= 25·c, 1 MHz, Outputs Off
Ice Power Supply Current Vee= Max, Inputs Grounded All Outputs Open
TRl·STATE
los Short C?ircuit Output Vo= OV, Vee= Max
Current
(Note4)
loz Output Leakage (TRI-STATE)
Vee= Max, V0 =0.4V to 2.4V Chip Disabled
VoH Output Voltage High loH = -2.0 mA loH= -3.2mA
PL77X288 Min Typ Max
-80 0.35
-250 25 1.0 0.50
0.80
2.0
-0.8 4.0
-1.5
6.0
110 140
-30 2.4
-130
100 -100 3.2
PL87X288 Min Typ Max
-80 0.35
-250 25 1.0 0.50
0.80
2.0
-0.8 4.0
-1.5
6.0
110 140
-30
-130
100 -100
2.4
3.2
Units
µA µA mA
v v v v
pF
pF
mA
mA
µA µA
v v
AC Electrical Characteristics with standard load and operating conditions
Symbol
Parameter
JEDEC Symbol
tAA Address Access Time (Note 5) tEA Enable Access Time (Note 5) tER Enable Recovery Time (Note 6) tzx Output Enable Time (Note 5) txz Output Disable Time (Note 6)
TAVQV TEVQV TEXQX TEVQX TEXQZ
PL77X288
Min
Typ
Max
10
20
8
15
8
15
8
15
8
15
PL87X288
Min
Typ
Max
10
15
8
12
8
12
8
12
8
12
Units
ns ns ns ns ns
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at these values. Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming parameters. Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee= 5.0V.and TA= 25'C. Nole 4: During las measurement, only one output at a time should be grounded. Permanent damage may otherwise result. Note 5: CL= 50 pF. Note 6: CL= 5 pF. Note 7: These are absolute voltages with respect to the ground pin on the device and Includes all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
Table 11.6.2 AC and DC Specifications for (32 X 8) 256-Bit TTL Logic PROMs
Data Sheets 311
11.7 DM54/74LS471 (256 x 8) 2048-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 256 words by 8 bits configuration. Memory enable inputs are provided to control the output states. When the device is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the "OFF" of high impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
· Advanced titanium-tungsten (Ti-W) fuses · Schottky-clamped for high speed
- Addressed access-40 ns typ - Enable access-15 ns typ - Enable recovery-15 ns typ · PNP inputs for reduced input loading · All DC and AC parameters guaranteed over temperature · Low voltage TRI-SAFE TM programming
OpenMilitary Commercial Collector TRI-STATE Package
DM74LS471
x
x
N,J
DM54LS471
x
x
J
Table 11.7.1 (256 x 8) 2048-Bit TTL PROM Options
A7 A6
AO I 2
Al
AS
AO
2048-BIT ARRAY
A2
Al
GENERATING 256
A3
UNIQUE PRODUCT TERMS A4
A2 A3 A4
08
07
06
OS
04 03
02
01
20 Vee 19 A7
18 A6
17 AS 16 -
E2
IS Ei
14 08
13 V7 12 I I 06
OS
Order Number; DM74LS471 J, DM54LS471 J, See NS Package J20B
Order Number; DM74LS471 N See NS Package N20A
Figure 11.7.1 Block and Connection Diagram
312 Programmable Logic Design Guide
DM54/74LS471 (256 x 8) 2048-BIT TTL PROMs
DC Electrical Characteristics 1Note 31
Sym
Parameter
Conditions
l1L Input Load Current
Vee= Max, V1N = 0.45V
l1H Input Leakage Current
Vee= Max, V1N = 2.7V
Vee= Max, V1N = 5.5V
Vol Low Level Output Voltage Vee= Min, loL = 16mA
V1L Low Level Input Voltage V1H High Level Input Voltage Ve Input Clamp Voltage
Vee= Min, l1N = -18mA
C1 Input Capacitance
Vee= 5.0, V1N = 2.0V
TA= 25C, 1MHz
Co Output Capacitance
Vee= 5.0V, Vo= 2.0V TA = 25C, 1MHz, Outputs Off
Ice Power Supply Current
Vee= Max, Inputs Grounded All Outputs Open
DM54LS471
Min Typ Max -80 -250 25 1.0 0.35 0.50 0.80
2.0 -0.8 -1.2 4.0
DM74LS471
Min Typ Max -80 -250 25 1.0 0.35 0.45 0.80
2.0 -0.8 -1.2 4.0
Units
µA µA mA
v v v v
pF
6.0 75 100
6.0
pF
75 100 mA
TRI-STATE~' Parameters
los Short Circuit Output Current
loz Output Leakage 1TRl-STATE1
VoH Output Voltage High
Vo= OV, Vee= Max rNote41 Vee= Max, Vo= 0.45 to 2.4V Chip Disabled loH = -2.0mA loH = 6.5mA
-20
-70 -20
-70 mA
+50
+50 µA
-50
-50 µA
2.4 3.2
v
2.4 3.2
v
AC Electrical Characteristics rWith Standard Load and Operating Conditions I
Sym
Parameter
JEDEC Symbol
DM54LS471
DM74LS471
Units
Min Typ Max Min Typ Max
TAA Address Access Time TEA Enable Access Time TER Enable Recovery Time TZX Ou!Q_ut Enable Time TXZ Ou!Q_ut Disable Time
TAVQV TEVQV TEXQX TEVQX TEXQZ
45 70 15 35 15 35 15 35 15 35
Note 3: These limrts apply over the entire operatrng range unless stated otherwise. All typical values are for Vee= 5.0V and TA= 25C Note 4: Durrng las measurement. only one output at a time should be grounded. Permanent damage may otherwise result
40 60 15 30 15 30 15 30 15 30
ns ns ·
ns ns ns
Table 11.7.2 AC and DC Specifications for (256 X 8) 2948-Bit TTL PROMs
Data Sheets 313
11.8 DM54/74S473, DM54/74S472; DM54/74S473A, DM54/74S472A; DM54/74S4728 (512 x 8) 4K-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 512 words by 8 bits configuration. A memory enable input is provided to control the output states. Whenthe device is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the OFF or high impedance state. The memories are available in both open-collector and TRI-STATE® versions.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
o Advanced titanium-tungsten (Ti:W) fuses. o Schottky-clamped for high speed.
Address access-25 ns typ. Enable access-15 ns typ. Enable recovery-15 ns typ. o PNP inputs for reduced input loading. o All DC and AC parameters guaranteed over temperature. o Low voltage TRI-SAFETM programming.
DM74S473 DM74S472 DM54S473 DM54S472
Mlltary
x x
Commercial
x x
OpenCollector
x
x
TRI-STATE
x x
Package
N,J N,J 'J J
Table 11.8.1 512 x 8 4096-Bit TTL PROM Optics
INPUT
BUFFER AS
.--~~~~~~~~~~~---.
A7
A6
AS
4096-BIT ARRAY
AO
GENERATING S12 UNIQUE
A1
PRODUCT TERMS
A2 ,A3 A4
E1
Order Number: OM74S473 J, DM74S472 J, OMS4S473 J, or OMS4S472 J See NS Package J208
Order Number: DM74S473 N or DM74S472 N See NS Package N20A
a1 a6 as C4 a3 a2 a1
Figure 11.8.1 Block and Connection Diagram
314 Programmable Logic Design Guide
DM54/74S473, DM54/74S472, DM54/74S473A, DM54/74S472A, DM54/74S472B DC Electrical Characteristics
(Note 3)
Sym
Parameter
Conditions
l1L Input Load Current
Vee= Max. V1N = 0.45V
l1H Input Leakage Current
Vee= Max, V1N = 2.7V
Vee= Max, V1N = 5.5V
Vol Low Level Output Voltage Vee= Min, loL = 16mA
V1L Low Level Input Voltage
V1H High Level Input Voltage
loz Output Leakage Current 1Open-Collector Only 1
Vee= Max, VcEX = 2.4V
v v cc = Max, CEX = 5.5V
Ve Input Clamp Voltage
c, Input Capacitance
Vee= Min, l1N = -18mA Vee= 5.0, V1N = 2.0V
TA= 25C, 1MHz
Co Output Capacitance
Vee= 5.0V, Vo= 2.0V TA = 25C; 1MHz, Outputs Off
Ice Power Supply Current
Vee= Max. Inputs Grounded All Outputs Open
DM545473/472
Min Typ Max -80 -250 25 1.0 0.35 0.50 0.80
2.0 50 100
--0.8 -1.2 4.0
6.0
110 155
DM745473/472
Min Typ Max -80 -250 25 1.0 0.35 0.45 0.80
2.0 50 100
-0.8 -1.2 4.0
6.0
110 155
Units
µA µA mA
v v v
µA µA
v
pF
pF
mA
TRI-STATE® Parameters
los Short Circuit Output Current
loz Output Leakage 1TRl-STATE1
VoH Output Voltage High
Vo= OV, Vee= Max 1Note41
-20
-70 -20
-70 mA
Vee= Max, Vo= 0.45 to 2.4V
+50
+50 µA
Chip Disabled loH =-2.0mA loH=6.5mA
-50 -
2.4 3.2
-50 µA
v
2.4 3.2
v
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
Sym
Parameter
TAA Address Access Time TEA Enable Access Time TER Enable Recove_!Y Time TZX Output Enable Time TXZ Output Disable Time
JEDEC Symbol
TAVQV TEVQV TEXQX TEVQX TEXQZ
DM545473/472 Min Typ Max
DM745473/472 Min Typ Max
Units
40 75 15 35. 15 35 15 35 15 35
40 60 ns 15 30 ns 15 30 ns 15 30 ns 15 30 ns
.Table 11.8.2 AC and DC Specifications for (512 x 8) 4096-Bit 1TL PROM
Data Sheets 315
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
Sym Parameter
JEDEC Symbol
DM54S473A/472A, B
Min Typ
Max
DM74S473A/472A, B
Min
Typ
Max
TAA Address Access Time TAVQV 473A/472A
25
60
25
45
4728
25
50
25
35
TEA Enable Access Time TEVQV 473A/472A
15
35
15
30
4728
15
35
15
25
TEA Enable Recovery Time TEXQX 473A/472A
15
35
15
30
4728
15
35
15
25
TZX Output Enable Time TEVQX 473A/472A
15
35
15
30
4728
15
35
15
25
TXZ !output Disable Time TEXQZ 473A/472A
15
35
15
30
4728
15
35
15
25
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee= 5.0V and TA= 25C. Note 4: During los measurement only one output at a time should be grounded. Permanent damage may otherwise result.
Units
ns ns ns ns ns ns ns ns ns ns
Table 11.8.2 AC and DC Specifications for (512 x 8) 4096-Bit TfL PROM (Cont.)
316 Programmable Logic Design Guide
11.9 DM54/74S475, DM54/74S474; DM54/74S475A, DM54/74S474A; DM54/74S4748, (512 x 8) K-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 512 words by 8 bits configuration. Memory enable inputs are provided to control the output states. When the device is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the OFF or high impedance state. The memories are available in both open-collector and TRI-STATE® versions.
PROMs are shipped from the factory with lows iri all locations. A high may be programmed into any selected location by following the programming instructions.
Features
· Advanced titanium-tungsten (Ti:W) fuses.
· Schottky-clamped for high speed. Address access-25 ns typ. Enable access-15 ns typ. Enable recovery-15 ns typ.
· PNP inputs for reduced input loading.
· All DC and AC parameters guaranteed over temperature.
· Low voltage TRI-SAFPM programming.
OpenMilitary Commercial Collector TRI-STATE Package
DM74S475
x
x
N,J
DM74S474
x
x
N,J
DM54S475
x
x
J
DM54S474
x
x
J
Table 11.9.1 (512 X 8) 4096-Bit TIT. PROM
4096-BIT ARRAY GENERATING 512 UNIQUE PRODUCT TERMS Az A,
Ao .....................-.---.---.---.--.----.---
07 06 05 04 03 02 01
ORDER NUMBER: DM74S475 J, DM74S475 J, DM45S475 J, DM54S474 J SEE NS PACKAGE J24A
ORDER NUMBER: DM74S475 N OR DM74S474 N SEE NS PACKAGE N24A
Figure 11.9.1 Block and Connection Diagram
Data Sheets 317
DM54/74S745, DM54/74S474, DM54/74S475A, DM54/74S474A, DM54/74S474B DC Electrical Characteristics
(Note 3)
Sym
Parameter
l1L Input Load Current l1H Input Leakage Current
Vol Low Level Output Voltage V1L Low Level Input Voltage V1H High Level Input Voltage loz Output Leakage Current
(Open-COiiector Only) Ve Input Clamp Voltage C1 Input Capacitance
Co Output Capacitance Ice Power Supply Current
Conditions
DM54S475/474 Min Typ Max
Vee= Max, V1N = 0.45V
-80 -250
Vee= Max, V1N = 2.7V
25
Vee= Max, V1N = 5.5V
1.0
Vee= Min, loL = 16mA
0.35 0.50
0.80
2.0
Vee= Max, VcEX. = 2.4V
50
Vee = Max, vCEX = 5.5V
100
Vee= Min, l1N =-18mA
I
-0.8 -1.2
Vee= 5.0, V1N = 2.0V
4.0
TA= 25C, 1MHz
Vee= 5.0V, Vo= 2.0V
6.0
TA= 25C, 1MHz, Outputs Off
Vee= Max, Inputs Grounded All Outputs Open
115 170
TRI-STATE® Parameters
los Short Circuit Output Current
loz Output Leakage (TRI-STATE)
VoH Output Voltage High
Vo= OV, Vee= Max
-20
-70
(Note 4)
Vee= Max, Vo= 0.45 to 2.4V
+50
Chip Disabled
-50
loH =-2.0mA
2.4 3.2
loH=6.5mA
DM74S475/474
Min Typ Max -80 -250 25 1.0 0.35 0.45 0.80
2.0 50 100
-0.8 -1.2 4.0
6.0
115 170
-20
-70
+so
-50
2.4 3.2
Units
µA µA mA
v v v
µA
µA
v
pF
pF
mA
mA
µA µA
v v
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
Sym
Parameter
TAA Address Access Time TEA Enable Access Time TER Enable Recove_!Y Time
IZX Qu!Q_ut EnableTime
TXZ Output Disable Time
JEDEC Symbol
TAVQV TEVQV TEXQX TEVQX TEXQZ
DM54S475/474 DM74S475/474 Units
Min Typ Max Min Typ Max
40 75 20 40 20 40 20 40 20 40
40 65 ns 20 35 ns 20 35 ns 20 35 ns 20 35 ns
Table 11.9.2 AC and DC Specifications for (512 x 8) 4096-Bit TfL High Speed PROM
318 Programmable Logic Design Guide
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
Sym Parameter TAA Address Access Time
: DM54S475A/474A, B
JEDEC Symbol
Min Typ
Max
1 TAVQV 475A/474A
25
60
l 4748
25
50
DM74S475A/474A, B
Min
Typ
Max
25
45
25
35
TEA Enable Access Time TEVQV
15
35
15
25
TEA Enable Recovery Time TEXQX
15
35
15
25
TZX Output Enable Time TEVQX
15
35
15
25
TXZ Output Disable Time TEXOZ
15
35
15
25
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee= 5.0V and TA= 25C. Note 4: During 105 measurement: only one output at a time should be grounded. Permanent damage may otherwise result.
Units
ns ns ns ns ns ns
Table 11.9.2 AC and DC Specifications for (512 x 8) 4096-Bit TIT. High Speed RPOM (Cont.)
Data Sheets 319
11.10 DM77/87SR474, DM77/87SR474B (512 x 8) 4K-BIT REGISTERED TTL PROM
General Description
The DM77/87SR474 is an electrically programmable Schottky TTL read-only memory with D-type, master-slave registers on-chip. This device is organized as 512 words by 8-bits and is available in the TRI-STATE output version. Designed to optimize system performance, this device also substantially reduces the cost and size of pipelined microprogrammed systems and other designs wherein accessed PROM data is temporarily stored in a register. The DM77/87SR474 also offers maximal flexibility for memory expansion and data bus control by providing both synchronous and asynchronous output enables. All outputs will go into the OFF state if the synchronous chip enable (GS) is high before the rising edge of the clock, or if the asynchronous chip enable (G) is held high. The outputs are enabled when GS is brought low before the rising edge of
the clock and G is held low. The GS flip-flop is designed to power-up to the OFF state
with the application of Vee· Data is read from the PROM by first applying an address to inputs A0-A8. During the
setup time the output of the array is loaded into the mas~er flip-flop of the data register. During the rising edge (low-to-high transition) of the clock, the data is then transferred to the slave of the flip-flop and will appear on the output if the· output is enabled. Following the rising edge clock transition, the addresses and synchronous chip enable can be removed and the output data will remain stable.
The DM77/87SR474 also features an initialize function, INIT. The initialize function provides the user with an extra word of programmable memory which is accessed with single pin control by applying a low on INIT. The initialize function is synchronous and is loaded into the output register on the next rising edge of the clock. The unprogrammed state of the INIT is all lows, _providing a CLEAR function when not programmed.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instruction.s. Once programmed,. it is impossible to go back. to a low.
320 Programmable Logic Design Guide
Features
· On-chip, edge-triggered registers. · Synchronous and asynchronous enables for word expansion. · Programmable synchronous register INITIALIZE. · 24-pin, 300 mil thin-DIP package. · 35 ns address setup and 20 ns clock to output for maximum system speed. · Highly reliable, titanium tungsten fuses. · TRI-STATE® outputs. · Low voltage TRI-SAFETM programming. · All parameters guaranteed over temperature. · Pinout compatible with DM77SR181 (lK x 8) Registered PROM for future
expansion.
INPUT BUFFER
4096 BIT ARRAY GENERATING 512 UNIQUE
PRODUCT TERMS
INITIALIZE WORD
B·BIT EDGE·TRIGGERED REGISTER
A1 As As A4 Al A2 A, Ao
Oo
o,
C2 GND
1·
24
23
22
21 20
19 DM77SR474
7
18
17
16
10
15
11
14
12
13
Vee As NC
a
iNiT (CLR) Gs
CK
07
Oe
Cs
C4 03
TUL5189
Order Number DM77SR474J, DM87SR474J, DM87SR474N, DM77SR474BJ, DM87SR474BJ
or DM87SR474BN See NS Package J24F or N24C
Co 01 Q2 C3 Q4 0 5 Q 6 Q 7 TL/L5189
Figure 11.10.1 Block and Connection Diagrams
DM77/87SR474 DC Electrical Characteristics (Note 3)
Data Sheets 321
Symbol
Parameter
Conditions
LIL
Input Load Current
Vcc= Max., V1N= 0.45V
Vee= Max., V1N= 2.7V
llH
Input Leakage Current
Vee= Max., V1N=5.5V
Vol Low Level Output Voltage Vee= Min., 10 L= 16mA
VIL
Low Level Input Voltage
VIH High Level Input Voltage
loz
Output Leakage Current Vee= Max., VeEx = 2.4V
Ve
Input Clamp Voltage
C1
Input Capacitance
Vee= Min., 11N= -18mA
vcc= 5.0, VIN= 2.0V
TA= 25°C, 1MHz
DM77SR474
DM87SR474 Units
Min. Typ. Max. Min. fyp. Max.
-80 -250
-80 -250 µ.A
25
25 µ.A
1.0
1.0 mA
0.35 0.50
v 0.35 0.45
0.80
0.80 v
2.0
2.0
v
50 -0.8 -1.2
50 µ.A
v -0.8 -1.2
4.0
4.0
pF
Co
Output Capacitance
Vcc=5.0V, V0 =2.0V TA= 25°C, 1MHz, Outputs Off
6.0
6.0
pF
Ice
Power Supply Current
Vee= Max., Inputs Grounded All Outputs Open
135 185
135 185 mA
TRI-STATE Parameters
los
Short Circuit Output Current
V0 = OV, Vee= Max. (Note 4)
-20
-70 -20
-70 mA
loz
Output Leakage
_{TRI-STATE}_
VoH Output Voltage· High
Vee= Max., V0 = 0.45 to 2.V ChifJ_ Disabled
10 H= -2.0mA
loH= -6.5mA
-50
+50 -50
+50 µ.A
2.4 3.2
v
2.4 3.2
v
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee= 5.0V and TA= 25°C. Note 4: During las measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Table 11.10.1 AC and DC Specifications for (512 x 8) 4K-Bit Registered 1TL PROMs
322 Programmable Logic Design Guide
DM77/87SR474B Switching Characteristics
Symbol
tS{A)
tH(A) tS{INIT)
tH(INln tPHL(CLK) tPLH(CLK) ~WH(CLK) WL(CLK) tS{GS)
tH(GS) tPZL(CLK) tPZH(CLK) tPZL(G) tPZH(G) tPLZ(CLK) tPHZ(CLK) iPLZ(G) PHZ(G)
Parameter
J Address to CLK (High) Setup Time ~=:~:B
Address to CLK (High) Hold Time
DMnSR474
Min. Typ. Max. 55 20 40 20 0 -5
DM87SR474
Min. Typ. Max. 50 20 35 20 0 -5
Units ns
INIT to CLK (High) Setup Time
30 20
25 20
ns
INIT to CLK (High) Hold Time
0 -5
0 -5
ns
Jl SR474
Delay from CLK (High) to Output (High or Low) SR4748
15 30 15 25
15 27 15 20 ns
CLK Width (High or Low)
25 13
20 13
ns
GS to CLK (High) Setup Time GS to CLK (High) Hold Time
10 0
10 0
ns
5 0
5 0
ns
Delay from CLK (High) to Output Active (High or Low)
20 35
20 30 ns
Delay from G (Low) to Output Active (High or Low)
15 30
15 25 ns
Delay from CLK (High) to Output Inactive (TRI-STATE)
Delay from G(Low) to Output Inactive (TRI-STATE)
20 35 15 30
20 30 ns
-
15 25 ns
Table 11.10.1 AC and DC Specifications for (512 x 8) 4K-Bit Registered TIL PROMs ·(Cont.)
Data Sheets 323
11.11 DM77/87SR476, DM77/87SR25, DM77/87SR476B, DM77/87SR25B (512 x 8) 4K-BIT REGISTERED TTL PROMs
General Description
The DM77/87SR476 is an electrically programmable schottky TTL read-only memory with D-type, masterslave registers on-chip. This device is organized as 512 words by 8-bits and is available in the TRI-STATE® output version. Designed to optimize system performance, this device also substantially reduces the cost and size of pipelined microprogrammed systems and other designs wherein accessed PROM data is temporarily stored in a register. The DM77/87SR476 also offers maximal flexibility for memory expansion and data bus control by providing both synchronous and asynchronous output enables. All outputs will go into the OFF state if the synchrounous chip enable (GS) is high before the rising edge of the clock, or if the asynchrounous chip enable (G) is held high. The outpus are enabled when GS is brought low before the rising edge of
the clock and G is held low. The GS flip-flop is designed to power up to the OFF state
with the application of Vee· Data is read from the PROM by first applying an address to inputs AO-A8. During the
rising edge (low-to-high transition) of the clock, the data is then transferred to the slave of the flip-flop and will appear on the output if the output is enabled. Following the rising edge clock transition, the addresses and synchronous chip enable can be removed and the output data will remain stable.
The DM77SR476 also features an initialize function, INIT. The initialize function provides the user with an extra word of programmable memory which is accessed with single pin control by applying a low on INIT. The initialize function is asynchronous and is loaded into the output register when INIT is brought low. The unprogrammed state of the INIT is all lows, which makes it compatible with the CLEAR function on the AM27S25. PS loads lows into the output registers when brought low.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions. Once programmed, it is impossible to go back to a low.
Features
· Functionally compatible with AM2 7S2 5.
o On-chip, edge-triggered registers.
· Synchronous and asynchronous enables for word expansion.
· Programmable asynchronous INITIALIZE (SR476 only).
· 24-pin, 300 mil thin-DIP package.
· 35 ns address setup and 20 ns clock to output for maximum system speed.
324 Programmable Logic Design Guide
· Highly reliable, titanium tungsten fuses. · TR~-STATE outputs. · Low voltage TRI-SAFETM programming. · All parameters guaranteed over temperature. · Preset input.
1 OF64 WORD DECODER
1 OF8 BIT
DECODER
INIT (CLR)-~~M>-------'
Ps"--GM>-----~s
CLK --i ::-------1
4096-BIT ARRAY GENERATING 512 UNIQUE PRODUCT TERMS
INITIALIZE WORD
I
8-BIT EDGE-TRIGGERED REGISTER
G
A1
Ae
As A4 A3 A2 A1
Ao
Oo 01 02 GND
1·
24
23
22
21
20
DM77SR476 DM77SR25
19
18
17
16
10
15
11
14
12
13
Vee Aa
Ps
G
INIT (CLR)·
G;
CK
07 Oa
05 04 03
·cLR only on DM77/87SR25
TUL5190
Order Number DM77SR476J, DM77SR25J, DM77/87SR476N, DM77/87SR25N, DM77SR476BJ, DM77SR25BJ, DM77/87SR476BN
or DM77/87SR25BN See NS Package J24F or N24C
Figure 11.11.1 Blo~k and Connection Diagrams
Data Sheets 325 DM77/87SR476, DM77/87RS25, DM77/87SR476B, DM77/87SR25B DC Electrical Characteristics (Note 3)
Symbol
Parameter
Conditions
LIL
Input Load Current
vcc= Max., v,N = 0.45V
Vee= Max., V1N= 2.7V
llH
Input Leakage Current
Vcc= Max., V1N= 5.5V
VOL Low Level Output Voltage Vee= Min., 10 L= 16mA
VIL
Low Level Input Voltage
VIH High Level Input Voltage
loz Output Leakage Current Vcc=Max., VcEx=2.4V
Ve
Input Clamp Voltage
Vcc= Min., 11N= - 18mA
c,
Input Capacitance
Vee= 5.0, V1N= 2.0V
TA= 25°C, 1MHz
Co
Output Capacitance
Vcc=5.0V, V0 =2.0V TA= 25°C, 1MHz, Outputs Off
Ice
Power Supply Current
Vee= Max., Inputs Grounded All Outputs Open
TRI-STATE Parameters
los
Short Circuit Output Current
V0 = OV, Vee= Max. (Note 4)
loz
Output Leakage
(TRI-STATE)
Vcc=Max., V0 =0.45to2.V Chip Disabled
VoH Output Voltage High
10 H= -2.0mA loH= -6.5mA
DM77SR474
DM87SR474 Units
Min. Typ. Max. Min. Typ. Max.
-80 -250
-80 -250 µA
25
25 µA
1.0
1.0 mA
0.35 0.50
0.35 0.45 v
0.80
0.80 v
2.0
2.0
v
50 -0.8 -1.2
50 µA
-0.8 -1.2 v
4.0
4.0
pF
6.0
6.0
pF
135 185
135 185 mA
-20
-70 -20
-70 mA
-50
+50 -50
+50 µA
2.4 3.2
v
2.4 3.2
v
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee= 5.0V and TA= 25°C. Note 4: Ouring los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Table 11.11.1 AC and DC Specifications for (512 x 8) 4K-Bit Registered TfL PROMs
326 Programmable Logic Design Guide
Switching Characteristics
Symbol
Parameter
1SR476, SR25
ts( A)
l Address to CLK (High) Setup Time
SR4768, SR25B
tH(A)
Address to CLK (High) Hold Time
tPHL(CLK) Delay from CLK (High) to Output
tPLH(CLK) (High or Low)
lSR476, SR25
l SR4768, SR25B
twH(CLK) twL(CLK) ts(GS) tH(GS) tpLH(PS)
CLK Width (High or Low)
GS to CLK (High) Setup Time GS to CLK (High) Hold Time Delay from PS (Low) to Output (High)
tPLH(INIT) tPHL(INIT) twL(PS) twL(INIT) ts( PS) ts( INIT)
Delay from INIT (Low) to Output (Low or High)
PS Pulse Width (Low) INIT Pulse Width (Low) PS Recovery (High) to CLK (High) INIT Recovery (High) to CLK (High)
tpzL(CLK) Delay from CLK (Low) to Active Output (High or Low) tpzH(CLK)
tpzL(G) tpzH(G)
Delay from G(Low) to .dctive Output (Low or High)
tPLZ(CLK) Delay from CLK (High) to Inactive Output (TRI-STATE) tPHZ(CLK)
tPLZ(G) tPHZ(G)
Delay from G(High) to Inactive Output (TRI-STATE)
DM77SR476, 4768 DM87SR476, 4768 DM77SR25, 258 DM87SR25, 258
Min. Typ. Max. Min. Typ. Max.
55 20
50 20
40 20
35 20
0 -5
0 -5
15 30
15 27
15 25
15 20
25 13
-25 13
10 0
10 0
5
0
5
0
20 30
20 25
20 30
20 25
15 10 15 10 25 10 25 10
15 10 15 10 20 10 20 10
20 35
20 30
15 30
15 25
20 35
20 30
15 30
15 25
Units
ns ns ns
ns ns ns ns ns ns
ns ns ns ns ns ns
Table 11.11.1 AC and DC Specifications for 20-Pin Ultra High-Speed, Medium PAL Devices (Cont.)
Data Sheets 327
11.12 REGISTERED PROM PROGRAMMING PROCEDURE
National Schottky PROMs are shipped from the factory with all fuses intact. As a result, the outputs will be low (logical "O") for all addresses. To generate high (logical" l ") levels at the outputs, the device must be programmed. Information regarding commercially available programming equipment can be obtained from National. If it is desired to build your own programmer, the following conditions must be observed:
1. Programming should be attempted only at ambient temperatures between 15 ° and 30°C.
2. Address and enable inputs must be driven with TTL logic levels during program-ming and verification.
3. Programming will occur at the selected address when Vee is at 10.SV, and at the selected bit location when the output pin representing that bit is at 10. SV, and the device is subsequently enabled. To achieve these conditions in the appropriate sequence, the following procedure must be followed:
a) Select the desired word by applying high or low levels to the appropriate address inputs. Disable the device by applying a high level to the asynchronous
Chip Enable input G. GS is held low during the enable programming time.
b) Increase Vee from nominal to 10.5 volts ( ± O.SV) with a slew rate between l.O and 10.0V/µs. Since Vee is the source of the current required to program the fuse as well as the Ice for the device at the programming voltage, it must be capable of supplying 750mA at 11.0V.
c) Select the output where a logical high is desired by raising that output voltage to 10.SV ( ± O.SV). Limit the slew rate from 1.0 to 10.0V/µs. This voltage change may occur simultaneously with the increase in Vcc, but must not precede it. It is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20k0 minimum. (Remember that the outputs of the device are disabled at this time.)
d) Enable the device by taking the chip enable (G) to a low level. This is done with a pulse of lOµs. The lOµs duration refers to the time that the circuit (device) is enabled. Normal input levels are used, and rise and fall times are not critical.
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing Vee to 4.0V ( ± 0.2V) for one verification and to 6.0V ( ± 0.2V) for a second verification. Verification at a Vee level of 4.0V and 6.0V will guarantee proper output states over the Vee and temperature range of the programmed part. Each data verification must be preceded by a positive going (low-to-high) clock edge to load the data from the array into the output register. The device must be enabled to sense the state of the outputs. During verification, the loading of the output must be within specified Im and IoH limits. Steps b, c, and d must be repeated up to 10 times or until verification that the bit has been programmed.
328 Programmable Logic Design Guide
f) The initialize word is programmed by setting INIT input to a logic low and programming the initialize word output by output in the same manner as any other address. This can be accomplished by inverting the A9 address input from the PROM programmer and applying it to the INIT input. Using this method, the initialize word will program at address 512.
g) Following verification, apply five additional programming pulses to the bit being programmed. The programming procedure is now complete for the selected bit.
h) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of Vcc at the programming voltage must be limited to a maximum of 25% . This is necessary to minimize device junction temperatures. After all selected bits are programmed, the entire contents of the memory should be verified.
Programming Parameters
Do not test or you may program the device
Symbol
VccP lccP Vop lop IRR PwE VccvL VccvH Moc
Parameter
Required Vee for Programming Ice During Programming Required Output Voltage for Programming Output Current While Programming Rate of Voltage Change of Vcc or Output Programming Pulse Width (Enabled) Required Low Vee for Verification Required High Vee for Verification Maximum Duty Cycle for Vee at Veep
Test Conditions
Min.
10
Vcc=11V
10
Vour= 11V 1
9
3.8
5.8
Recommended Value 10.5
10.5
10 4 6 25
Max.
11 750 11 20 10 11 4.2 6.2 25
Units
v
mA
v
mA V/µs µS
v v
%
Table 11.12.1 Programming Parameters. Do Not Test or You May Program the Device.
Data Sheets 329
Programming Waveforms
=t=
ADINDPRUESTSS
SELECTED ADDRESS STABLE
><=
---------------------~
-
T,
VceP-
Vcc Vccvtt
5.0V
-I T51-
v-:-T2 ------.
t l PROGRAMMED Vott
/
m m w f??02?'.J -- - - OUTPUT
VcCVL
Vccvtt
~
f??m
VoL
TJ r---1T4j-
~~~~~;
~~~~~:
ii
ENABLE
LJl______I
I
CLK
--J PWE 1-
nr-Ts-1
nf--Ts-j
CLOCK - - - - - - - - - - - - _ _ .
..___ _ _ _ __.
---
T, = 100 ns MIN.
T2=5 µS MIN. (T2 MAY BE> 0 IF Veep RISES AT THE SAME RATE OR FASTER THAN Vop.)
TJ=lOO ns MIN.
T4=100 ns MIN.
T5=100 ns MIN.
Ts=50 ns MIN.
Figure 11.12.1 Programming Waveforms Registered PROM
11.13 NON-REGISTERED PROM PROGRAMMING PROCEDURE
National Schottky PROMs are shipped from the factory with all fuses intact. As a result, the outputs will be low (logical "O") for all addresses. To generate high (logical "l ") levels at the outputs, the device must be programmed. Information regarding commercially available programming equipment can be obtained from National. If it is desired to build your own programmer, the following conditions must be observed:
1. Programming should be attempted only at ambient temperatures between 15 and 30 degrees Celsius.
2. Address and enable inputs must be driven with TTL logic levels during programming and verification.
3. Programming will 9ccur at the selected address when Vee is at 10.5 volts, and at the selected bit location when the output pin representing that bit is at 10.5 volts, and the device is subsequently enabled. To ad1ieve these conditions in the appropriate sequence, the following procedure must be followed:
330 Programmable Logic Design Guide
a) Select the desired word by applying high or low levels to the appropriate address inputs. Disable the device by applying a high level to asynchronous Chip Enable input G. GS is held low during the enable programming time.
b) Increase Vcc from nominal to 10. 5 volts ( ± 0.5V) with a slew rate between 1.0 and 10.0V/µs. Since Vcc is the source of the current required to program the fuse as well as the Ice for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0 V.
c) Select the output where a logical high is desired by raising that output voltage to 10.5 volts ( ± 0.5V). Limit the slew rate from 1.0 to 10.0V/µs. This voltage change may occur simultaneously with the increase in Vcc, but must not precede it. It is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20k0 minimum. (Remember that the outputs of the device are disabled at this time.)
a d) Enable the device by taking the chip enable (G) to low level. This is done with a
pulse of lOµs. The lOµs duration refers to the time that the circuit (device) is enabled. Normal input levels are used and rise and fall times are not critical. e) Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing Vee to 4.0V ( ± 0.2V) for one verification and to 6.0V ( ± 0.2V) for a second verification. Verification at a Vee level of 4.0V and 6.0V will guarantee proper output states over the Vee and temperature range of the programmed part. Each data verification must be preceded by a positive going (low-to-high) clock edge to load the data from the array into the output register. The device must be enabled to sense the state of the outputs. During verification, the loading of the output must be within specified Im and Iott limits. Steps b, c, and d mus~ be repeated up to 10 times or until verification that the bit has been programmed. f) Following verification, apply five additional programming pulses to the bit being programmed. The programming procedure is now complete for the selected bit. g) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of Vcc at the programming voltage must be limited to a maximum of 25% . This is necessary to minimize device junction temperatures. After all selected bits are programmed, the entire contents of the memory should be verified.
Note: Since only an enabled device is programmed, it is possible to program these parts at the board level if all of the programming parameter are complied with.
TRI-STATE® is a registered trademark of National Semiconductor Corp. TRI-SAFETM is a trademark of National Semiconductor Corp.
Data Sheets 331
Programming Parameters Do not test or you may program the device
Symbol
VccP lccP Vop lop IRR Pwe VccvL VccvH Moc
Parameter
Required Vee for Programming Ice During Programming Required Output Voltage for Programming Output Current While Programming Rate of Voltage Change of Vee or Output Programming Pulse Width (Enabled) Required Low Vee for Verification Required High Vee for Verification Maximum Duty Cycle for Vee at Veep
Test Conditions Min.
10 Vee= 11V
10 Vour= 11v
1 9 3.8 5.8
Recommended Value 10.5
10.5
10 4 6 25
Max.
11 750 11 20 10 11 4.2 6.2 25
Units
v mA v mA V/µs µS v v %
Table 11.13.1 Programming Parameters Do Not Test or You May Program the Device
Programming Waveforms Non-Registered PROM
ADDRESS INPUTS
- - - - - ->C SELECTED ADDRESS STABLE T1
VccP-
_,t Vcc VccvH 5.0V
-jTsl-
VccvL
VccvH
Vop- -
PROGRAMMED VoH
/
OUTPUT W//////////////
·VoL
G
ENABLE
CLK CLOCK
~ --~~-- ~
OUTPUT
OUTPUT
T3 r---1T41-
VERIFY
VERIFY
Lr-il n -1 PWE
I
r-T&-1
I
nr--Ta~
T1=100 ns MIN.
T2=5 J'S MIN. (T2 MAY BE > 0 IF Veep RISES AT THE SAME RATE OR FASTER THAN Vop.)
T3=100 ns MIN.
T4=100 ns MIN. Ts=100 ns MIN.
T5=50 ns MIN.
Figure 11.13.1 Programming Waveforms Non-Registered PROM
332 Programmable Logic Design Guide
MANUFACTURER
DATA 110
PRO-LOG KONTRON STAG AIM DIGELEC STARPLEXTM
SYSTEM#
5/17/19/29A M910, M980 MPPBOS PPX RP400 UP803
Table 11.13.2 Approved Programmers for NSC PROMs
11.14 QUALITY ENHANCEMENT PROGRAMS
A+PROGRAM*
B+PROGRAM
Test
D.C. Parametric And Functionality AC. Parametric
Mechanical
Seal Tests Hermetic
Condition 25°C
Each Temperature
Extreme 25°C
Critical
Major Fine Leak (5 x 10 -81
Gross
'Includes 160 hours of burn-in at 125°C.
Guaranteed LOTAQLS
0.05
0.05
0.4 O.D1 0.28 0.4
0.4
Test
D.C. Parametric And Functionality AC. Parametric
Mechanical
Seal Tests Hermetic
Condition 25°C
Each Temperature
Extreme 25°C
Critical
Major Fine Leak !5 x 10 -8)
Gross
Guarnnteed LOTAQLS
0.05
0.05
0.4 0.01 0.28 0.4
0.4
Table 11.14.1 Quality Enhancement Program for Bipolar Memory
12
_Package Outlines
0.025 (0.635)
RAD
0.290 - 0.320
0.785
I gI--. [-----(19.939)---------j Ii.I m15l r1m4 1M3 AX12 IT1T11 li1001 191 0.220- 0.310 (5.588- 7.874) """""...,..,.,....,..,.,....,..,.,....,..,.,....,..,.,......,.,.~____i_
0.005 - 0.020 (0.127 - 0.508) RADTYP
0.200
+0.635) ( 10.16 -1.524
~-,r--.t:---t-~=-
86° 94 TYP
°
j --l' 0.020 - 0.060 0.018±0.003 i- 0.125-0.200 (0.508-1.524) (0.457 ± 0.076) (3.175 - 5.080) ~ 0.100±0.010
(2.540 ± 0.254)
Figure 12.1 NS Package J16A 16-Leact·cavity DIP CT)
333
334 Programmable Logic Design Guide
0.090
0.780
0.092 (2.286) fJ,;:(19.81) ~
PINN0.11DENT~f0} J (2.3137) NOM
MAX
DIANOM~ 14 1J 12 11 10 9
(j)
0.280
0.250 ± 0.005
(7.112) MIN
}n (~:~:~) 0.300-0.320 ~f==1L1M1AX
}C:hFr- _-_...------,.-....,,...----+ (7.62-8.128)
0.065 --
<1·l65_1 )_........
'J r95°±5:t- 0.009-0.015
I· .I 1---j 1--lh (0.229-0.~~~~o±o.015
0.040 (1.016)
TYP
(6.35 ± 0.127)
0.130 ± 0.005
(3.302 ±0.127)
0.020
(0M5I0N8)
sso 940
0.125
0.325 ~~:~~:
I
+o.&35)
\B.255 - 0.381
(0.762±0.381)
~ 0.018±0.003 (3.175)
MIN
0.100±0.010 (0.457±0.076)
(2.540 ±0.254)
Figure 12.2 NS Package N16E 16-Lead Molded DIP (N) (Substitute for N16A)
0.985 - - - - (25.019) - - - -
MAX
0.290 - 0.320
1 (7:366- 8.128) GLASS
0.005
(0~1~7)
0.060 ±0.005 (1.52~;:·127)
0.020 - 0.060 (0.508 - 1.524)
SEALANT"".+-~~~~~~~~-+-+---.---+---, 0.200
,,._--+-1---1 0.008 - 0.012
(5.080)
(0.203 - 0.305) 86~
MAX
----+0.025
0.385 - 0.060
94° TYP
0.060 (1.524)
MAX
0.125 ± 0.200
tl
(3.175-5.080)
--IL o.01s ±0.003
(0.457 ±0.076)
I
0.150 (3.810)
0.100±0.010
TYP
MIN
+0.635) ( 9.779 - 1.524
BOTH ENDS
(2.540 ± 0.254) TYP
Figure 12.3 NS Package J20A 20-Lead Cavity DIP 0)
Package Outlines 335
0.092 (2.3137) DIANOM
PIN NO. 1 INDENT
1.040
----(26.42) -----i
MAX
0.090
(2.286) NOM
Figure 12.4 NS Package N20A 20-Lead Molded DIP. (N)
0.025
(0.635) RAD
0.180
(4.572)
MAX
~ae·g~·
0.095TYP (2.413)
o(.21.0504±±00..0215o4)~
MAX
TYP
BOTH ENDS
0.295 --MAX (7.493)
0.030 - 0.055 0.672 - 1.397
RADTYP
Figure 12.5 NS Package J24F 24-Lead Cavity DIP 0)
336 Programmable Logic Design Guide
0.092 (2.3137)
DIA
0.300 - 0.320 (7.62- 8.128)
0.009 - 0.015
(0.229-0.381) .
+ 0.025 !
I 0.280
0·325 -0.015 ~ , - - - (7.112)
i-.~ ~
{
+ 0.635)
,8.255 - 0.381
MIN 0.075 ± 0.015
(1.905 ±0.381)
~ ~ 0.100 ±0.010
(2.54 ±0.254)
TYP
0.018 ±0.003
(0.457 ±0.076)
TYP
0.020 (0.508)
MIN
0.125 (3.175)
MIN
Figure 12.6 NS Package N24C 24-Lead Molded DIP (N)
0.025 (0.635)
RAD
0.030 - 0.055 (0.762 - 1.397)
RAD TYP 0.005
1.290
<a,;;;>------1
0.600 (15.240)
f MAX
tGLASS
I
0.514 - 0.526
(13.06 -13.36)
"~~~..,........,..-_t
GLASS
0.055 ±0.005 (1.397 ±0.127)
0.180 (4.572) MAX 0.020 - 0.070
(0.508 - 1.778)
(2.540 ±0.254)
--JI-. If--
as 0 0.125-0.200 0.150
I \
0.018 ±0.003
940 TYP
(3·
1
7
~~~·0
9
0)
<3:i~O)
(0.457 ±0.076)
Figure 12.7 NS Package J24A 24-Lead Cavity DIP (J)
Package Outlines 337
1.270 1------(32.258)------
MAX
I 0.540 ±0.005
DOTTED OUTLINES REFLECT ALTERNATE MOLDED BODY CONFIGURATION
0.075
0.040
Ir_--
0.625
+0.025 - 0.015-
I
+ 0.635 15.875 - 0.381
~
0.075 ± 0.015
(1.905 ±0.381)
r
0.009- 0.015
0.100 ±0.010
(0.229- 0.381)
(2.540 ±0.254)
0.015
(0.381) MIN
0.125
(3.175) MIN
Figure 12.8 NS Package N24A 24-Lead Molded DIP (N)
338 Programmable Logic Design Guide
4 SPACES AT 0.050:1:j (1.270) 19 20 1 2 3
w
0.226 (5.740) .NOM-
SQUARE
I (01.1.403)45J
x45°
ii VIEW A-A
0.310 - 0.330 (7.874 - 8.382) (CONTACT DIMENSION)
0.026 - 0.032 (o.&60 - 0.813)
TYP
0.013 - 0.018
(0.330 - 0.457) TYP
PIN NO 1 IDENT
0.018 - 0.040 1"--""'1r....--'1-1--J----(0.457 -·1.016)
0.165 - 0.180 (4.191 - 4.572)
0.385 - 0.395 (9.779-10.03)
SQUARE
Figure 12.9 NS Package PCC-20 20-Lead Plastic Leaded Chip Carrier (V)
Package Outlines 339
-.-----~~~~--i-
0.326
22 (8.280) NOM SQUARE
VIEWA·A
~·
0.045
(1.143) --l l+-
x450
SQUARE (CONTACT DIMENSION)
0.445 - 0.455
(11.30 - 11.54) SQUARE
PIN N0.1 IDENT
0.485 - 0.495 (12.32 -12.57)
SQUARE
f
f 0.026 - 0.032 0.095 - 0.125
(0.660 - 0.813) (2.413 - 4.572) TYP
0.165 - 0.180 (4.191 - 4.572)
Figure 12.10 NS Package PCC-28 28-Lead Plastic Leaded Chip Carrier (V)
13
Terminology
Term PAL Device
PROM
FPLA
Product Term (Pn)
Summing Term (Sn)
Output Polarity Don't Care Active High
Active Low
+ +
Explanation Programmable Array Logic. AND-OR Array with a· programmable AND array and a fixed OR array.
Programmable Read-Only Memory. AND-OR Array with a fixed AND array and a programmable OR array.
Field-Programmable Logic Array. AND-OR Array with a programmable AND array and a programmable OR array.
Logical AND operation on input variables. Example: Po= AoA1A15, P10 = AzA5
Logical OR operation on product terms. Example: S1 =Po+ Pio
= AoA1A15 + AzA5
Inversion or Non-inversion of summing term outputs.
Variable can take any logic state without affecting logic operation.
Output is a logic high when Sum-of-Products expression is true. Within programmable logic context, refers to a non-inverted output.
Output is a logic low when Sum-of-Products expression is true. Within programmable logic context, refers to an inverted output.
Fixed connectioq.
Programmable connection in virgin array.
341
342 Programmable Logic Design Guide
Term
+ +
Maximum Clock Frequency, fMAX:
High Level Input Current, Im: High Level Output Current, IoH:
Low Level Input Current, I1L: Low Level Output Current, IoL:
Off-State (High-Impedance State) Output Current of a 3-State Output), Ioz: Short-Circuit Output Current, Ios:
Supply Current, Ice:
Explanation
Unconnected in programmed part.
Programmed, connected.
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence while maintaining stable transitions of logic level at the output with input conditions established that should cause changes of output logic level in accordance with the specification.
The current into an input when a high level voltage is applied to that input.*
The current into an output with input conditions applied that, according to the product specification, will establish a high level at the output.*
The current into an input when a low level voltage is applied to that input.*
The current into an output with input conditions applied that, according to the product specification, will establish a low level at the output.*
The current into an output having 3-state capability with input conditions applied that, according to the product specification, will establish the high-impedance state at the output.*
The current into an output when that output is short-circuited to ground (or other specified potential) with input conditions applied to establish the output logic level farthest from ground potential (or other specified potential).*
The current into the Vcc Supply terminal of an integrated circuit.*
Terminology , 343
Term
Output Enable Time (of a 3-State Output) to High Level, tpZH(or Low Level, tPZL): Output Enable Time (of a 3-State Output) to High or Low Level, tpzx:
Output Disable Time (of a 3-State Output) from High Level, tpttz(or Low Level, tpLz): Output Disable Time (of a 3-State Output) from High or Low Level, tpxz:
Explanation
The interval during which a signal is retained at a specified input terminal after an active transition occurs at another specified input terminal.
Notes: 1. The hold time is the actual time between
two events ahd may be insufficient to accomplish the intended result. A minimum value is specified that is the shortest interval for which correct operation of the logic element is guaranteed.
2. The hold time may have a negative value, in which case the minimum limit defines the longest interval (between the release of data and the active transition) for which correct operation of the logic element is guaranteed.
The propagation delay time between the specified reference points on the input and output voltage waveforms with the 3-state output changing from a high-impedance (oft) state to the defined high (or low) level.
The propagation delay time between the specified reference points on the input and output voltage waveforms with the 3-state output changing from a high-impedance (oft) state to either of the defined active levels (high or low).
The propagation delay time between the specified reference points on the input and output voltage waveforms with the 3-state output changing from the defined high (or low) level to a high-impedance (oft) state.
The propagation delay time between the specified reference points on the input and output voltage waveforms with the 3-state output changing from either of the defined active levels (high or low) to a high-impedance (oft) state.
344 Programmable Logic Design Guide
Term Propagation Delay Time, tp0 : Propagation Delay Time, Low-to-High Level Output, tpu-f Propagation Delay Time, High-to-Low Level Output, tPHL: Pulse Width, tw: Setup Time, tsu
High Level Input Voltage, Vrn:
Explanation
The time between the specified· reference points on the input and output voltage waveforms with the output changing from one defined level (high or low) t~ the other defined level.
The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level.
The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined high level to the defined low level.
The time interval between specified reference . points on the leading and trailing edges of the pulse waveform.
The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal.
Notes: 1. The setup time is the actual time between
two events and may be insufficient to· accomplish the setup. A minimum value is specified that is the shortest interval for which correct operation of the logic element is guaranteed. 2. The setup time may have a negative value in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation of the logic element is guaranteed.
An input voltage within the more positive (less negatiVe) of the two ranges of values used to represent the binary variables.
Note: A minimum is specified that is the least positive value of high level voltage for which
Terminology 345 ·
Term High Level Output Voltage, VoH: Input Clamp Voltage, V1c: Low Level Input Voltage, V1L:
Low Level Output Voltage, VoL: Negative-Going Threshold Voltage, VTPositive-Going Threshold Voltage, VT+:
Explanation
operation of the logic elements within specification limits is guaranteed.
The voltage at an output terminal with input conditions applied that, according to the product specification, will establish a high level at the output.
An input voltage in a region of relatively low differential resistance that serves to limit the input voltage swing.
An input voltage level within the less positive (more negative) of the two ranges of values used to represent the binary variables.
Note: A maximum is specified that is the most positive value of the low level input voltage for which operation of the logic element within specification limits is guaranteed.
The voltage at an output terminal with input conditions applied that according to the product specification will establish a low level at the output.
The voltage level at a transition-operated input that causes operation of the logic element according to specificadon as the input voltage falls from a level above the positive-going threshold voltage, VT+.
The voltage level at a transition-operated input that causes operation of the logic element according to specification as the input voltage rises from a level below the negative-going threshold voltage, VT _ .
*Current out of a terminal is given as a negative value.
Appendix - an Overyiew of LSI Testing Techniques
The growth in the complexity and performance of digital circuits can only be described as explosive. Large-scale integrated circuits are being used today in a variety of applications, many of which require highly reliable operation. This is causing concern among designers of tests for LSI circuits. The testing of these circuits is difficult for several reasons:
· The number of faults that has to be considered is large, since an LSI circuit contains thousands of gates, memory elements, and interconnecti_ng lines, all individually subject to different kinds of faults.
· The observability and controllability of the internal elements of any LSI circuit are limited by the available number of I/O pins. As more and more elements are packed into one chip, the task of creating an adequate tes! becomes more difficult. A typical LSI chip may contain 5000 gates but only 40 I/O pins.
· The implementation details of the circuits usually are not disclosed by the manufacturer. For example, the only source on information about commercially available microprocessors is the user's manual, which details the instruction set and describes the architecture of the microprocessor at the register-transfer level, with some information of the system timing. The lack of implementation information eliminates the use of many powerful test generation techniques that depend on the actual implementation of the unit under test.
· As more and more gates and flip-flops are packed into one chip, new failure modes - such as pattern-sensitivity faults - arise. 1 These new types of faults are difficult to detect and require lengthy test patterns.
· The dynamic nature of LSI devices requires high-speed test systems that can test the circuits when they are operating at their maximum speeds.
· The bus structure of most LSI systems makes fault isolation more difficult because many devices - any of which can cause a fault - share the same bus.
© 1983 IEEE, Reprinted, witb pennission, from lEEE MICRO, l-01. 3, No. 1, pp. 34, February· 1983. M.S. Abadir, H.K. Regbbati, Autbors.
347
348 Programmable Logic Design Guide
e Solving the problems above increases the number of test patterns required for a successful test. This in turn increases both the time required for applying that test and the memory needed to store the test patterns and their results.
LSI testing is a challenging task. Techniques that worked well for SSI and.MS! circuits, such as the D-algorithm, do not cope with today's complicated LSI and VLSI circuits. New testing techniques must be developed. In what follows, we describe some basic techniques developed to solve the problems associated with LSI testing.
A.1 TESTING METHODS
There are many test methods for LSI circuits, each with its own way of generating and processing test data. These approaches can be divided into two broad categories concurrent and explicit. 2
In co·ncurrent approaches, normal user-application input patterns serve as diagnostic patterns. Thus testing and normal computation proceed concurrently. In explicit approaches, on the other hand, special input patterns are applied as tests. Hence, normal computation and testing occur at different times.
Concurrent Testing
Systems that are tested concurrently are designed such that all the information transferred among various parts of the system is coded with different types of error detecting codes. In addition, special circuits monitor this coded data continuously and signal detection of any fault.
Different coding techniques arc required to suit the different types of information used inside LSI systems. For example, m-out-of-n codes (n-bit patterns with exactly m l's and n - m O's) are suitable for coding control signals, while arithmetic codes are best suited for coding ALU operands.3
The monitoring circuits - checkers - are placed in various locations inside the systems so that they can detect most of the faults. A checker is sometimes designed in a way that enables it to detect a fault in its own circuitry as well as in the monitored data. Such a checker is called a self-checking checker. 3
Hayes and McCluskey surveyed various concurrent testing methods that can be used with microprocessor-based LSI systems. 2 Concurrent testing approaches provide the following advantages:
o Explicit testing expenses (e.g., for test equipment, down time, and test pattern generation) are eliminated during the life of the system, since the data patterns used in normal operation serve as test patterns.
o The faults are detected instantaneously during the use of the LSI chip, hence the first faulty data pattern caused by a certain fault is detected. Thus, the user can rely on the correctness of his output results within the degree of fault coverage provided by the
Appendix 349
· error detection code used. In explicit approaches, on the other hand, nothing can be said about the correctness of the results until the chip is explicitly tested.
o Transient faults, which may occur during normal operation, are detected if they cause any faulty data pattern. These faults cannot be detected by any explicit testing method.
Unfortunately, the concurrent testing approach suffers from several problems that limit its usage in LSI testing:
o The application patterns may not exercise all the storage element or all the internal · connection lines. Defects may exist in places that are not exercised, and hence the faults these defects would produce will not be detected. Thus, the assumption that faults are detected as they occur, or at least before any other fault occurs, is no longer valid. Undetected faults will cause fault accumulation. As a result, the fault detection mechanism may fail because most error detection codes have a limited capability for detecting multiple faults.
o Using error detecting codes to code the information signals used in- an LSI chip requires additional I/O pins. At least two extra pins are needed as error signal indicators. (A single pin cannot be used, since such a pin stuck at the good value could go undetected.) Because of constraints on pin count, however, such requirements cannot be fulfilled.
o Additional hardware circuitry is required to implement the checkers and to increase the width of the data carriers used for storing and transferring the coded information.
o Designing an LSI circuit for concurrent testing is a much more complicated task than designing· a similiar LSI circuit that will be tested explicitly.
o Concurrent approaches provide no control over critical voltage or timing parameters. Hence, devices cannot be tested under marginal timing and electrical conditions.
o The degree of fault coverage usually provided by concurrent methods is less than that provided by explicit methods.
The above-mentioned problems have limited the use of concurrent testing for most commercially available LSI circuits. However, as digital systems grow more complex and difficult to test, it becomes increasingly attractive to build test procedures into the UUT (unit under test) itself. We will not consider the concurrent approach further in this article . For a survey of work in concurrent testing, see Hayes and McCluskey. 2
Eltplicit Testing
All explicit testing methods separate the testing process from normal operation. In general, an explicit testing process involves three steps:
o Generating the test patterns. The goal of this step is to produce those input patterns which will exercise the UUT under different modes of operation while trying to detect any existing fault.
350 Programmable Logic Design Guide
· Applying the test patterns to the UUT. There are two ways to accomplish this step. The first is external testing - the use of special test equipment to apply the test patterns externally. The second is internal testing - the application of test patterns internally by forcing the UUT to execute a self-testing procedure. 2 Obviously, the second method can only be used with systems that can execute programs (for example, with microprocessor-based systems.) External testing gives better control over the test process and enables testing under different timing and electrical conditions. On the other hand, internal testing is easier to use because it does not need special test equipment or engineering skills.
· Evaluating the responses obtained from the UUT. This step is designed with one of two goals in mind. The first is the detection of an erroneous response, which indicates the existence of one or more faults (go/no-go testing). The other is the isolation of the fault, if one exists, in an easily replaceable module (jault location testing). Our interest in this article will be go/no-go testing, since fault location testing of LSI circuits sees only limited use.
Many explicit test methods have evolved in the last decade. They can be distinguished by the techniques used to generate the test patterns and to detect and evaluate the faulty responses (Figure A.1.1 ). In what follows, we concentrate on explicit testing
TEST GENERATION
LSI TESTING
CONCURRENT TESTING
MANUAL ALGORITHMIC
INTERNAL
EXTERNAL
SIMULATION· AIDED
GOOD RESPONSE GENERATION
COMPACT TESTING
STORED RESPONSE
COMPARISON
TRANSITION COUNTING
SIGNATURE ANALYSIS
Figure A.1.1 LSI Test Technology
Appendix 351
and present in-depth discussions of the methods of test generation and response evaluation employed with explicit testing.
A.2 TEST GENERATION TECHNIQUES
The test generation process represents the most important part of any explicit testing method. Its main goal is to generate those test patterns that, when applied to the UUT, sensitize existing faults and propagate a faulty response to an observable output of the UUT. A test sequence is considered good if it can detect a high percentage of the possible UUT faults; it is considered good, in other words, if its degree offault coverage is high.
Rigorous test generation should consist of three main activities:
· Selecting a good descriptive model, at a suitable level, for the system under consideration. Such a model should reflect the exact behavior of the system in all its possible modes of operation.
· Developing a fault model to define the types of faults that will be considered during test generation. In selecting a fault model, the percentage of possible faults covered by the model should be maximized, and the test costs associated with the use of the model should be minimized. The latter can be accomplished by keeping'the complexity of the test generation low and the length of the tests short. Clearly these objectives contradict one another - a good fault model is usually found as a result of a trade-off between them. The nature of the fault model is usually influenced by the model used to describe the system.
· Generating tests to detect all the faults in the fault model. This part of test generation is the soul of the whole test process. Designing a test sequence to detect acertain fault in a digital circuit usually involves two problems. First, the fault must be excited; i.e., a certain test sequence must be applied that will force a faulty value to appear at the fault site if the fault exists. Second, the test must be rnade sensitive to the fault; i.e., the effect of the fault must propagate through the network to an observable output.
Rigorous test generation rests heavily on both accurate descriptive (system) models and accurate fault models.
Test generation for digital circuits is usually approached either at the gate-level or at the functional level. The classical approach of modeling digital circuits as a group of connected gates and flip-flops has been used extensively. Using this level of description, test designers introduced many types of fault models, such as the classical stuck-at model. They also assumed that such models could describe physical circuit failures in terms of logic. This assumption has sometimes restricted the number of physical failures that can be modeled, but it has also reduced the complexity of test generation since failures at th~ elementary level do not have to be considered.
Many algorithms have been developed for generating tests for a given fault in combinational networks. I,4,5,6,7 However, the complexity of these algorithms depends on the topology of the network; it can become very high for some circuits. Ibarra and
352 Programmable Logic Design Guide
Sahni have shown that the problem of generating tests to detect single stuck-at faults in a combinational circuit modeled at the gate level is an NP-complete problem. 8 Moreover, if the circuit is sequential, the problem can become even more difficult depending on the deepness of the circuit's sequential logic.
Thus, for LSI cicuits having many thousands of gates, the gate level approach to the test generation problem is not very feasible. A new appoach, the functional level, is needed.
Another important reason for considering faults at the functional level is the constraint imposed on LSI testing by a user environment - the test patterns have to be generated without a knowledge of the implementation details of the chip at the gate level.
Appendix 353
The only source of information usually available is the typical IC catalog, which details
the different modes of operation and describes the general architecture of the circuit.
With such information, the test designer finds it easier to define the functional behavior
of the circuit and to associate faults with the functions. He can partition the UUT into var-
ious modules such as registers, multiplexers, ALUs, ROMs, and RAMs. Each module can
be treated as a "black box" performing a specified input/output mapping. These modules
can then be tested for functional failures; explicit consideration of faults affecting the
internal lines is not necessary. The example given below clarifies the idea.
Consider a simple one-out-of-four multiplexers such as the one shown in Figure
A.2.1. This multiplexer can be modeled at the gate level as shown in Figure A.2.l(a), or at
the functional level as shown in Figure A.2.l(b).
x
y
z
w
u
(a)
xy zw
C1 Co u 0 0x
1-0UT-OF-4 MUX
0 1y
1 0z
(b)
u
1 1w
Figure A.2.1 (a) A One-out-of-four Multiplexer-gate-level Description; (b) Functional-level Description.
A possible fault model for the gate-level description is the single stuck-at fault model. With this model, the fault list may contain faults such as the line labeled with
'1" is stuck at 0, or the control line "Co" is stuck at 1.
At the functional level, the multiplexer is considered a black box with a well-defined function. Thus, a fault model for it may specify the following as possible faults: selection of wrong source, selection of no source, or presence of stuck-at faults in the input lines or in the multiplexer output. With this model, the fault list may contain faults such as source "X" 'is selected instead of source "Y," or line "Z" is stuck at 1.
354 Programmable Logic Design Guide
Ad hoc methods - which determine what faults are the most probable - are sometimes used to generate fault lists. But if no fault model is assumed, then the tests derived must be either exhaustive or a rather ad hoc check of the functionality of the system. Exhaustive tests are impossible for even small systems because of the enormous number of possible states, and superficial tests provide neither good coverage nor even an indication of what faults are covered.
Once the fault list has been defined, the next step is to find the test patterns required to detect the faults in the list. As previously mentioned, each fault first has to be excited so that an error signal will be generated somewhere in the UUT. Then this signal has to be sensitized at one of the observable outputs of the UUT. The three examples below describe how to excite and sensitize different types of faults in the types of modules usually encountered in LSI circuits.
Consider the gate-level description of the three-bit incrementer shown in Figure A2.2.
Figure A.2.2 Gate-level Description of a Three-Bit Incrementer
The incrementer output, Y2 Y1 Y0, is the binary sum of Ci and the three-bit binary number X2X1X0 , while C0 is the carry-out bit of the sum. Note that X0(Y0) is the least significant bit of the incrementer input (output).
Assume we want to detect the fault "line/ is stuck at O." To excite that fault we will
force a 1 to appear on line f so that, if it is stuck at 0, a faulty value will be generated at
the fault site. To accomplish this both Xo and Ci must be set to 1. To sensitize the faulty Oat/, we have to set X1 to 1; this will propagate the fault to Y2 independent of the value of X2. Note that if we set X1 to 0, the fault will be masked since the AND gate output will be 0, independent of the value at/. Note also that X2 was not specified in the above test. However, by setting X2 to 1, the fault will propagate to both Y2 and C0 , which makes the response evaluation task easier.
Consider a microprocessor RAM and assume we want to generate a test sequence to detect the fault "accessing word i in the RAM results in accessing the word} instead."
Appendix 355
To excite such a fault, we will use the following sequence of instructions (assume a microprocessor with single-operand instructions):
Load the word 00 ... 0 into the accumulator.
Store the accumulator contents into memory address j.
Load the word 11 ... 1 into the accumulator.
Store the accumulator contents into memory address i.
If the fault exists, these instructions will force a 11 ... 1 word to be stored in memory address j instead of 00 ... 0. To sensitize the fault, we need only read what is in memory address j, using the appropriate instructions. Note that the RAM and its fault have been considered at the functional level, since we did not specify how the RAM is implemented.
Consider the program counter (PC) of a microprocessor and assume we want to generate a test sequence that will detect any fault in the incrementing mode of this PC, i.e., any fault that makes the PC unable to be incremented from x to x + 1 for any address x. One way to excite this fault is to force the PC to step through all the possible addresses. This can be easily done by initializing the PC to zero and then executing the no-operation instruction x + 1 times. As a result, the PC will contain an address different than x + 1. By executing another no-operation instruction, the wrong address can be observed at the address bus and the fault detected. In practice, such an exhaustive test sequence is very expensive, and more economical tests have to be used. Note that, as in the example immediately above, the problem and its solution have been considered at the functional level.
Four methods are currently used to generate test patterns for LSI circuits: manual test generation, algorithmic test generation, simulation-aided test generation, and random test generation.
Manual Test Generation
In manual test generation, the test designer carefully analyzes the UUT. This analysis can be done at the gate level, at the functional level or at a combination of the two. The analysis of the different parts of the UUT is intended to determine the specific patterns that will excite and sensitize each fault in the fault list. At one time, the manual approach was widely used for medium-and small-scale digital circuits. Then, the formulation of the D-algorithm and similar algorithms eliminated the need for analyzing each circuit manually and provided an efficient means to generate the required test patterns.1,5 However, the arrival of LSI circuits and microprocessors required a shift back toward manual test generation techniques, because most of the algorithmic techniques used with SSI and MSI circuits were not suitable for LSI circuits.
Manual test ·generation tends to optimize the length of the test patterns and provides a relatively high degree of fault coverage. However, generating tests manually takes a considerable amount of effort and requires persons with special skills. Realizing
356 Programmable Logic Design Guide
that test generation has to be done economically, test designers are now moving in the direction of automatic test generation..
One good example of manual test generation is the work done by Sridhar and Hayes,9 who generated test patterns for a simple bit-sliced microprocessor at the functional level.
A bit-sliced microprocessor is an array of n identical ICs called slices, each of which is a simple processor for operands of kbit length, where k is typically 2 or 4. The interconnections among the n slices are such that the entire array forms a processor for nkbit operands. The simplicity of the individual slices and the regularity of the interconnections make it feasible to use systematic methods for fault analysis and test generation.
Sridhar and Hayes considered a one-bit processor slice as a simplified model for the commercially available bit-sliced processors such as the Am2901. 10 A slice can be modeled as a collection of modules interconnected in a known way. These modules are regarded as black boxes with well-defined input-output relationships. Examples of these functional modules are ALUs, multiplexers, and registers. Combinational modules are described by their truth tables, while sequential modules are defined. by their state tables (or state diagrams).
The following fault categories were considered:
o For combinational modules, all possible faults that induce arbitrary changes in the truth table of the module, but that cannot convert it into a sequential circuit.
o For sequential modules, all possible faults that can cause arbitrary changes in the state table of the module without increasing the number of states.
Only one module was assumed to be faulty at any time. To test for the faults allowed by the above-mentioned fault model, all possible input patterns must be applied to each combinational module (exhaustive testing), and a checking sequence 11 to each sequential module. In addition, the responses of each module must be propagated to observable output lines. The tests required by the indivi.dual modules were easily generated manually - a direct consequence of the small operand size (k = 1). And because the slices were identical, the tests for one slice were easily extended to the whole array of slices. In fact, Sridhar and Hayes showed that an arbitrary number of simple fnterconnected slices could be tested with the same number of tests as that required for a single slice, as long as only one slice was faulty at one time. This property is called C-testability. Note that the use of carry-lookahead when connecting slices eliminates C-testability. Also note that slices with operand sizes equal to 2 or more usually are not C-testable. The idea of modeling a digital system as a collection of interconnected functional modules can be used in modeling any LSI circuit. However, using exhaustive tests and checking sequences to test individual modules is feasible only for toy systems. Hence, the fault model proposed by Sridhar and Hayes, though very powerful, is not directly applicable to LSI testing.
Appendix 357
PATH SENSITIZATION AND THE D-ALGORITHIVI
One of the classical fault detection methods at the gate and flip-flop level is the Dalgorithm 1·5 employing the path sensitization testing tcchnique.'1 The basic principle involved inpath sensitization is relatively simple. For an input X; to detect a
fault "line a is stuck atj,j =0, l," the input X; must cause the signal ain f11~. ~or~
mal (fault-free) circuitto take· the value}. This condition is necessary but11otg1f~ ficient to detect the fault. The error signal must be propagated along so11w pat}:i from its site· to an observable output.
To generate a test to detect a stuck-at fault in a combinational circuit, the fol~ lqwing path sensitization procedure must be followed:
C!J Excitation-:-Tfie ·inputs must be specified so as .to generate the appropriate value (O for stuck~at 1 and I for stuck-at O) at the site of the fault.
?e f:rror propagation-Apath from the fault site tqan observabl.~ output must
selected, ·. and.a~ditional signal . values to·.prop;igat~the fault signal aloqgthJs path must .be sp~cifie<:f.
o Linejustificatio~~Input values must be specifi~dsqas··to produce.·tbe signal~ values specified ir1 the step above.
m Jhere maybe several possible· choices for err6rptopagation and line justifica-
ti.pn. Also, $0111S c~s~s there may be a choic~ ?f w~ys in which to excite the
!~~lL Sp111e 9{ m~se c.}1c;>i.ce? may lead to· an il1~p~sis~c:;ncy~ and so the procedure
must backtrackand consider the next alternative;Jf all the alternatives lead to an it1fonsi~~e~9y, fR.is.itppli?s .· th.at the .fa~If.canrip(becietected.
Ifo facili~~tetht;!~a~h ~ensitizatio.11 process, .weif1troduce the symbol Dtorep~~
s~W a ~i~l1~lyv~ic}1 }1as tI.1e valuel i~ ano.rtpal drfttit and O in a faulty dfcuit, ~~d
J5 ~() i·epresenta ~i~ma! which. ha~.thS ya~ue 0 in a normal circuit .and . 1. in a faulty
circuit.The path?~11sitiz~tionproq:durecan be formulated.in terms qf a. cubical al~eb~a.1.'f t? e~aple '1utomaticgeneration of test. This also facilitates test genera~ tip~J?r ll1()re. comple-:~ fault. mqdels and for· fault propagation through ~~···---·-·· lqgtf. el~ments.
~e shall·. ctefine three.··typesofcubes(i.e.,. line values specified.in JJ'-''"""'''"'..··"'"·>·· nofatiqn):
· fp(acir~~It ele1nentE.whichireav~es the combinational function/,
VY? sp~es''··. offer ·. a typic~lprs.~entation of the prirne . implicams off
Th.~sc i;:ubes concisely represent tl)e logical. behavior· of E.
· ~ [~pr~1~iti~eD-5ube.of it~~~t?j11~1logi~ element Especifies· the 111inimalinl)~t
c;:pn#itf.()?f t}1at.1nust peappliedto f: in· order to produce.an c~rror signal (Dor
QI~S!h<! qµtput of E.
358 Programmable Logic Design Guide
Appendix 359
Lir1e1:us1titic:at:ionl...;_Jt:-;xc~cution of Steps 1 to 5 may result in specifying the out-
.....~...........,.. an element E but leaving some of the inputs to the element unspeci-
J.J.~ ...... J..;>µ'·........
... -..
inputs of such
an
element
are
assigned
values
so
as
to
........,.............,. output value. This is done by intersecting the test cube with ~..·im·i·+·:"'" cube of the element which has no specified signal values that differ
test'cube.
Algorithmic test generation
In algorithmic test generation, the test designer devises a set of algorithms to generate the 1's and O's needed to test the UUT. Algorithmic test techniques are much more economiGal than manual techniques. They also provide the test designer with a high level of flexibility. Thus, he can improve the fault coverage of the tests by replacing or modifying parts of the algorithms. Of course, this task is much simpler than modifying the 1's and O's in a manually generated test sequence.
Techniques that use the gate-level description of the UUT, such as path sensitization4 and the D-algorithm,5 can no longer be used in testing complicated LSI circuits. Thus, the problem of generating meaningful sets of tests directly from the functional description of the UUT has become increasingly important. Relatively little work has been done on functional-level testing of LSI chips that are not memory elements.9, l2, l3, l4, l5, l6, l7 Functional testing of memory chips is relatively simple because of the regularity of their design and also because their components can be easily controlled and observed from the outside. Various test generation algorithms have been
360 Programmable Logic Design Guide
developed to detect different types of faults in memories. 1·IS In the rest of this section we will concentrate on the general problem of generating tests for irregular LSI chips, i.e., for LSI chips which are not strictly memory chips.
It is highly desirable to find an algorithm that can generate tests for any LSI circuit, or at least most LSI circuits. One good example of work in this area is the technique proposed by Thatte and Abraham for generating tests for microprocessors. 12 ·13 Another approach, pursued by the authors of this article, is a test generation procedure capable of handling general LSI circuits. 15,I6,I7
The Thatte-Abraham Technique
Microprocessors constitute a high percentage of today's LSI circuits. Thatte and Abraham12 ·I3 approached the microprocessor test generation problem at the functional level.
The test generation procedure they developed was based, on:
o A functional description of the microprocessor at the register-transfer level. The model is defined in terms of data flow among storage units during the execution of an instruction. The functional behavior of a microprocessor is thus described by information about its instruction set and the functions performed by each instruction.
o A fault model describing faults in the various functional parts of the UUT (e.g., the data transfer function, the data storage function, the instruction decoding and control function). This fault model describes the faulty behavior of the UUT without knowing its implementation details.
The microprocessor is modeled by a graph. Each register in the microprocessor (including general-purpose registers and accumulator, stack, program counter, address buffer, and processor status word registers) is represented by a node of the graph. Instructions of the microprocessors are classified as being of transfer, data manipulation, or branch type. There exists a directed edge (labeled with an instruction) from one node to another if during an execution of the instruction data flow occurs from the register represented by the first node to that represented by the second. Examples of instruction representation are given in Figure A.2.3.
Having described the function or the structure of the UUT, one needs an appropriate fault model in order to derive useful tests. The approach used by Thatte and Abraham is to partition the various fun~tions of a microprocessor into five classes: the register decoding function, the instruction decoding and control function, the data storage function, the data transfer function, and the data manipulation function. Fault models are derived for each of these functions at a higher level and independently of the details of implementation for the microprocessor. The fault model is quite general. Tests are derived allowing any number of faults, but only in one function at a time; this restriction· exists solely to cut down the complexity of test generation.
Appendix 361
(a)
(b)
(c)
(d)
Figure A.2.3
Representations of Microprocessor Instruction - 11' (a) Transfer
Instruction, ~2 -R1; (b) Add Instruction, R3-R1 + R2; (c) 13, OR Instruction, R2-R1 OR R2; (d) 14 Rotate Left Instruction.
The fault model for the register decoding function allows any'possible set of registers to be accessed instead of a particular register. (If the set is null then no register is accessed.) This fault model is thus very general and independent of the actual realization of the decoding mechanism.
For the instruction decoding and control function, the faulty behavior of the microprocessor is specified as follows. When instruction 11, is.executed any one of the following can happen:
y, o Instead of instruction some other instruction Ik is executed. This fault is denoted
by F(I/Ik).
· In addition to instruction Ip some other instruction Ik is activated. This fault is denoted by F(I/11 + lk).
· No instruction is executed. This fault is denoted by F(I/¢).
Under this specification, any number of instructions can be faulty. In the fault model for the data storage function, any cell in any data storage module
is allowed to be stuck at 0 or 1. This can occur in any number of cells. The fault model for the data transfer function includes the following types of faults:
o A line in a path used in the ex.ecution of an instruction is stuck at 0 or 1.
· Two lines of a path used in the instruction are coupled; i.e., they fail to carry different logic values.
Note that the second fault type cannot be modeled by single .stuck-at faults. The transfer paths in this fault model are logical paths and thus will account for any failure in the actual physical paths.
Since there is a variety of designs for the ALU and other functional units such as increment or shift logic, no specific fault model is used for the data manipulation function. It is assumed that complete test sets can be derived for the functional units for a given fault model.
By carefully analyzing the logical behavior of the microprocessor according to the fault models presented above, Thatte and Abraham formulated a set of algorithms to
362 Programmable Logic Design Guide
generate the necessary test patterns. These algorithms step the microprocessor through a precisely defined set of instructions and addresses. Each algorithm was designed for detecting a particular class of faults, and theorems were proved which showed exactly the kind of faults detected by each algorithm. These algorithms employ the excitation and sensitization concepts previously described.
To gain insight into the problems involved in using the algorithms, Thatte investigated the testing of an eight-bit microprocessor from Hewlett-Packard. 12 He generated the test patterns for the microprocessor by hand, using the algorithms. He found that 96 percent of the single stuck-at faults that could affect the microprocessor were detected by the test sequence he generated. This figure indicates the validity of the technique.
The Abadir-Reghbati technique
Here we will briefly describe a test generation technique we developed for LSI circuits. IS, t6 We assumed that the tests would be generated in a user environment in which the gate-and flip-flop-level details of the chip were not known.
We developed a module-level model for LSI circuits. This model bypasses the gate and flip-flop levels and directly describes blocks of logic (modules) according to their functions. Any LSI circuit can be modeled as a network of interconnected modules such as counters, registers, ALUs, ROMs, RAMs, multiplexers, and decoders.
Each module in an LSI circuit was modeled as a black box having a number of functions defined by a set of binary decision diagrams (see box, next page). 19 This type of diagram, a functional descr~ption tool introduced by Akers in 1978, is a concise means for completely defining the logical operation of one or more digital functions in an implementation-free form. The information usually found in ari IC catalog is sufficient to derive the set of binary decision diagrams describing the functions performed by the different modules in a device. These diagrams - like truth tables and state tables - are amenable to extensive logical analysis. However, unlike truth tables and state tables, they do not have the unpleasant property of growing exponentially with the number of variables involved. Moreover, the diagrams can be stored and processed easily in a digital computer. An important feature of these diagrams is that they state exactly how the module will behave in every one of its operation modes. Such information can be extracted from the module's diagrams in the form of a set of experiments. is,2o Each of these experiments describes the behavior of the module in one of its modes of operation. The structure of these experiments makes them suitable for use in automatic test generation.
We also developed a functional-level fault model describing faulty behavior in the different modules of an LSI chip. This model is quite independent of the details of implementation and covers functional faults that alter the behavior of a module during one of its modes of operation. It also covers stuck-at faults affecting any input or output pin or any interconnection line in the chip.
Using the above-mentioned models, we proposed a functional test generation procedure based on path sensitization and the D-algorithm. 15 The procedure takes the
Appendix 363
module-level model of the LSI chip and the functional description of its modules as parameters arid generates tests to detect faults in the fault model. The fa ult collapsing technique1 was used to reduce the length of the test sequence. As in the D-algorithm, the procedure employs three basic operations, namely implication, D-propagation, and line justification. However, these operations are performed on functional modules.
We also presented algorithmic solutions to the problems of performing these operations on functional modules. 16 For each of the three operations, we gave an algorithm which takes the module's set of experiments and current state (i.e., the values assigned to the module inputs, outputs, and internal memory elements) as parameters and generates all the possible states of the module after performing the required operation.
We have also reported our efforts to develop test sequences based on our test gen-
eration procedure for typical LSI circuits. 17 More specifically, we considered aone-bit
microprocessor slice C that has all the basic features of the four-bit Am2901 microprocessor slice. 10 The circuit C was modeled as a network of eight functional modules: an ALU, a latch register, an addressable register, and five multiplexers. The functions of the individual modules were described in terms of binary decision diagrams or equivalent sets of experiments. Tests capable of detecting various faults covered by the fault model were then generated for the circuit C. We showed that if the fault collapsing technique is used, a significant reduction in the length of the final test sequence results.
The test generation effort was quite straightforward, indicating that the technique can be automated without much difficulty. Our study also shows that for a simplified version of the circuit C the length of the test sequence generated by our technique is very close to the length of the test sequence manually generated by Sridhar and Hayes9 for the same circuit. We also described techniques for modeling some of the features of the Am2909 four-bit microprogram sequencer10 that are not covered by the circuit C.
The results of our case study were quite promising and showed that our technique is a viable and effective one for generating tests for LSI circuits.
Simulation-aided Test Generation
Logic simulation techniques have been used widely in the evaluation and verification of new digital circuits. However, an important application of logic simulation is to interpret the behavior of a circuit under a certain fault or faults. This is known as fault simu·lation. To clarify how this technique can be used to generate tests for LSI systems, we will first describe its use with SSI/MSI-type circuits.
To generate a fault simulator for an SSI/MSI circuit, the following information is needed: 1
· the gate-level description of the circuit, written in a special language;
· the initial conditions of the memory elements; and
· a list of the faults to be simulated, including classical types of faults such as stuck-at faults and adjacent pin shorts.
364 Programmable logic Design Guide
The above is fed to a simulation package which generates the fault simulator of the circuit under test. The resulting simulator can simulate the behavior of the circuit under normal conditions as well as when any faults exist.
Now, by applying various input patterns (either generated by hand, by an algorithm, or at random), the simulator checks to see if the output response of the correct circuit differs from one of the responses of the faulty Circuits. If it does, then this input pattern detects· the fault which created the wrong output response; otherwise the input pattern is useless. If an input pattern is found to detect a certain fault, this fault is deleted from the fault list and the process continues until either the input patterns or the faults are finished. At the end, the faults remaining in the fault list are those which cannot be detected by the input patterns. This directly measures the degree of fault coverage of the input patterns used.
Two examples of this type of logic simulator are LAMP - the Logic Analyzer for Maintenance Planning developed at Bell Laboratories,21 and the Testaid III fault simulator developed at the Hewlett-Packard Company. 12 Both work primarily at the gate level and simulate stuck-at faults only. One of the main applications of such fault simulators is to determine the degree of fault coverage provided by a test sequence generated by any other test generation technique.
There are two key requirements that affect the success of any fault simulator:
· the existence of a software model for each primitive element of the circuit, and
· the existence of a good fault model for the UUT which can be used to generate a fault list covering most of the actual physical faults.
These two requirements have been met for SSI/MSI circuits, but they pose serious problems for LSI circuits. If it can be done at all, modeling LSI circuits at the gate level requires great effort. One part of the problem is the lack of detailed information about the internal structure of most LSI chips. The other is the time and memory required to simulate an LSI circuit containing thousands of gates. Another severe problem facing almost all LSI test generation techniques is the lack of good fault models at a level higher than the gate level.
The Abadir-Reghbati description model proposed in the previous section permits the test designer to bypass the gate-level description and,· using binary decision diagrams, to define blocks of logic according to their functions. Thus, the simulation of complex LSI circuits can take place at a higher level, and this eliminates the large time and memory requirements. Furthermore, the Abadir-Reghbati fault model is quite efficient and is suitable for simulation purposes. In fact, the implication operation16 employed by the test generation procedure represents the main building block of any fault simulator. It must be noted that fault simulation techniques are very useful in optimizing the length of the test sequence generated by any test generation technique.
BINARY DECISION DIAGRAMS
Appendix 365
366 Programmable Logic Design Guide
Appendix 367 EJ" by traversing the Ej diagram, he obtains a value of 0. ~eturn~
c1+ 1 diagram with E1 =Owill result in taking the O branch. and
CJ+l =AJ = 1.
node variables . can refer. to . other auxiliary functions, \ . 'les.crioe· cmnpJlCX modules by breaking their functions
diagram· will consist of small diagra.ms connect:ed. m a 111era1·cni.;;·······.··1 of these diagrams describes either
Random Test Generation This method can be considered the simplest method for testing a device. A random number generator is used to simultaneously apply random input patterns both to the UUT and to a copy of it known to be fault-free. (This copy is called the golden unit.) The results obtained from the two units are compared, and if they do not match, a fault in the UUT is detected. This response evaluation technique is known as comparison testing; we will discuss it later. It is important to note that every time the UUT is tested, a new random test sequence is used.
The important question is how effective the random test is, or, in other. words, what fault coverage a random test of given length provides. This question can be answered by employing a fault simulator to simulate the effect of random test patterns of various lengths. The results of such experiments on SSI and MSI circuits show that
368 Programmable Logic Design Guide
random test generation is most suitable for circuits without deep sequential logic.1,22,23 However, by combining random patterns with manually generated ones, test designers can obtain very good results.
The increased sequentiality of LSI circuits reduces the applicability of random testing. Again, combining manually generated test patterns with random ones improves the degree of fault coverage. However, two factors restrict the use of the random test generation technique:
· The dependency on the golden unit, which is assumed to be fault-free, weakens the level of confidence in the results.
· There is no accurate measure of how effective the test is, since all the data gathered about random tests are statistical data. Thus, the amount of fault coverage provided by a particular random test process is unpredictable.
A.3 RESPONSE EVALUATION TECHNIQUES
Different methods have been used to evaluate UUT responses to test patterns. We restrict our discussion to the case where the final goal is only to detect faults or, equivalently, to detect any wrong output response. There are two ways of achieving this goal - using a good response generator or using a compact testing technique.
Good Response Generation
This technique implements an ideal strategy: comparing UUT responses with good response patterns to detect any faulty response. Clearly, the key problems are how to obtain a good response and at what stage in the testing process that response will be generated. In current test systems, two approaches to solving these problems are taken - stored response testing and comparison testing.
Stored Response Testing
In stored response testing, a one-shot operation generates the good response patterns at the end of the test generation stage. These patterns are stored in an auxiliary memory (usually a ROM). A flow diagram of the stored response testing technique is shown in Figure A.3.1.
Different methods can be used to obtain good responses of a circuit to a particular test sequence. One way is to do it manually by analyzing the UUT and the test patterns. This method is the most suitable if the test patterns were generated manually in the first place.
The method most widely used to obtain good responses from the UUT is to apply the test patterns either to a known good copy of the UUT - the golden unit - or to a software-simulated version of the UUT. Of course, if fault simulation techniques were used to generate the test patterns, the UUT's good responses can be obtained very easily as a partial product from the simulator.
TEST PATTERNS
UUT
UUT RESPONSE
Appendix 369
STORED GOOD
RESPONSE
COMPARATOR
Figure A.3.1 Stored Response Testing
TEST PATTERNS
· UUT
GOLDEN UNIT
UUT RESPONSE
GOOD RESPONSE
ERROR SIGNAL
COMPARATOR
Figure A.3.2 Comparison Testing
The use of a known good device depends on the availability of such a device. Hence, different techniques must be used for the user who wants to test his LSI system and for the designer who wants to test his prototype design. However, golden units are usually available once the device goes into production. Moreover, confidence in the correctness of the responses can be increased by using three or five good devices together to generate the good responses.
The major advantage of the stored response technique is that the good responses are generated only once for each test sequence, thus reducing the cost of the response evaluation step. However, the stored response technique suffers from various disadvantages:
· Any change in the test sequence requires the whole process to be repeated.
370 Programmable Logic Design Guide
· A very large memory is usually needed to store all the good responses to a reasonable test sequence, because both the length and the width of the responses are relatively large. As a result, the cost of testing equipment increases.
· The speed with which the test patterns can be applied to the UUT is limited by the access time of the memory used to store the good responses.
Comparison Testing
Another way to evaluate the responses of the UUT during the testing process is to apply the test patterns simultaneously to both the UUT and a golden unit and to compare their responses to detect any faulty response. The flow diagram of the comparison testing technique is shown in Figure A.3.2. The use of comparison testing makes possible the testing of the UUT at different speeds under different electrical parameters, given that these parameters are within the operating limits of the golden unit, which is assumed to be ideal.
Note that in comparison testing the golden unit is used to generate the good responses every time the UUT is tested. In stored response testing, on the other hand, the golden unit is used to generate the good responses only once.
The disadvantages of depending on a golden unit are more serious here, however, since every explicit testing process requires one golden unit. This means that every tester must contain a golden copy of each LSI circuit tested by that tester.
One of the major advantages of comparison testing is that nothing has to be changed in the response evaluation stage if the test sequence is altered. This makes comparison testing highly desirable if test patterns are generated randomly.'
Compact Testing
The major drawback of good response generation techniques in general, and stored response t~sting in particular, is the huge amount of response data that must be analyzed and stored. Compact testing methods attempt to solve this by compressing the response data R into a more compact form f(R) from which most of the fault information in R can be derived. Thus, because only the compact form of the good responses has to be stored, the need for large memory or expensive golden units is eliminated. An
important property of the compression function f is that it can be implemented with
simple circuitry. Thus, compact testing does not require much test equipment and is . especially suited for field maintenance work. A general diagram of the compact testing technique is shown in Figure A.3.3.
Several choices for the function f exist, such as "the number of 1's in the
sequence," "the number of 0 to 1 and 1·to 0 transitions in the sequence" (transition counting), 24 or "the signature of the sequence" (signature analysis).25 For each compression functionf, there is a slight probability that a response Rl different from the fault-free response RO will be compressed to a form equal tof(RO), i.e.,J(Rl) = f(RO).
Appendix 371
Thus, the fault causing the UUT to produce RI instead of RO will not be detected, even though it is covered by the test patterns.
The two compression functions that are the most widely accepted commercially are transition counting and signature analysis.
TEST PATTERNS
UUT
RESPONSES R
J(r)
GOOD COMPRESSED RESPONSES
ERROR SIGNAL
COMPARATOR
Figure A.3.3 Compact Testing
Transition Counting
In transition counting, the number of logical transitions (0 to 1 and vice versa) is computed at each output pin by simply running each output of the UUT into a special counter. Thus, the number of counters needed is equal to the number of output pins observed. For every m-bit output data stream (at one pin), an n-bit counter is required, where n = (log2m]. As in stored response testing, the transition counts of the good responses are obtained by applying the test sequence to a golden copy of the UUT and counting the number of transitions at each output pin. This latter information is used as a reference in any explicit testing process.
In the testing of an LSI circuit by means of transition counting, the input patterns can be applied to the UUT at a very high rate, since the response evaluation circuitry is very fast. Also, the size of the memory needed to store the transition counts of the good responses can be very small. For example, a transition counting test using 16 million patterns at a rate of one MHz will take 16 seconds, and the compressed stored response will occupy only K 24-bit words, where K is the number of output pins. This can be contrasted with the 16 million K-bit words of storage space needed if regular stored response testing is used.
The test patterns used in a transition counting test system must be designed such that their output responses maximize the fault coverage of the test. 24 The example below shows how this can be done.
372 Programmable Logic Design Guide
Consider the one-out-of-four multiplexer shown in Figure A.3.4. To check for multiple stuck-at faults in the multiplexer input lines, eight test patterns are required, as shown in Table A.3.1. The sequence of applying these eight patterns to the multiplexer is not important if we want to evaluate the output responses one by one. However, this sequence will greatly affect the degree of fault coverage if transition counting is used. To illustrate this fact, consider the eight single stuck-at faults in the four input lines Xl,X2,X3, and X4 (i.e., Xl stuck-at 0, Xl stuck-at 1, X2 stuck-at 0, and so on). Each of these faults will be detected by only one. pattern among the eight test patterns·. For
X1 X2 X3 X4
So 1/4 MUX
So S1 y
0 0 X1 0 1 X2 1 0 X3 1 1 X4
y
Figure A.3.4 One-Out-of-Four Multiplexer
example, the fault "Xl stuck-at O" will be detected by applying the first test pattern in Table A.3.1, but the other seven test patterns will not detect this fault. Now, suppose we want to use transition counting to evaluate the output responses of the multiplexer. Applying the eight test patterns in the sequence shown in Table A.3.1 (from top to bottom) will produce the output response 10101010 (from left to right), with a transition count of seven. Any possible combination of the eight faults described above will change the transition count to a number different from seven, and the fault will be detected. (Note that no more than four of the eight faults can occur at any one time.) Thus, the test sequence shown in Table A.3.1 will detect all single and multiple stuck-at faults in the four input lines of the multiplexer.
Now, if we change the sequence of the test patterns to the one shown in Table A.3.2, the fault coverage of the test will decrease considerably. The output responses of the sequence of Table A.3.2 will be 11001100, with a transition count of three. As a result, six of the eight single stuck-at faults will not be detected, because the transition count of the six faulty responses will remain three. For. example, the fault "Xl stuck-at l" will change the output response to 11101100, whic~.has a transition count of three. Hence, this fault will not be detected. Moreover, most of the multiple combinations of the eight faults will not change the transition count of the output, and hence they will not be detected either.
It is clear from the above example that the order of applying the test patterns to the UUT greatly affects the fault coverage of the test. When testing combinational circuits, the test designer is completely free to choose the order of test patterns. However, he
Appendix 373
So S1 X1 X2 X3 X4 v
0
0
1 0
0
0
1
0
0
0
1
1
1
0
0
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
0
0
1
0
1
1
0
1
1 0
1
0
1
1
0
0
0
1
1
1
1
1
1
1
0
0
So S1 X1 X2 X3 X4 v
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
Table A.3.1
The eight test patterns used for testing the multiplexer of Figure A.3.4
Table A.3.2 A different sequence of the eight multiplexer test patterns
cannot do the same with test patterns for sequential circuits. More seriously, because he is dealing with LSI circuits that probably have multiple output lines, he will find that a particular test sequence may give good results at some outputs and bad results at others. One way to solve these contradictions is to use simulation techniques to find the optimal test sequence. However, because of the limitations discussed here, transition counting cannot be recognized as a powerful compact LSI testing method.
Signature Analysis
In 1977 Hewlett-Packard Corporation introduced a new compact testing technique called signature analysis, intended for testing LSI systems. 25-28 In this method, each
output response is passed through a 16-bit linear feedback shift register whose contents /(R), after all the test patterns have been applied, are called the test signature. Figure A.3.5 shows an example of a linear feedback shift register used in signature analysis.
SERIAL DATA INPUT
16-BIT SHIFT REGISTER
Figure A.3.5 The 16-bit Linear Feedback Shift Register Used in Signature Analysis
374 Programmable Logic Design Guide
The signature provided by linear feedback shift registers can be regarded as a unique fingerprint - hence, test designers have extremely high confidence in these shift registers as tools for catching errors. To better understand this confidence, let us examine the 16-bit linear feedback shift register shown ·in Figure A.3.5. Let us assume a data stream of length n is fed to the serial data input line (representing the output response to be evaluated). There are 2n possible combinations of data streams, and each one will be compressed to one of the 216 possible signatures. Linear feedback shift registers have the property of equally distributing the different combinations of data streams over the different signatures. 27 This property is illustrated by the following numerical examples.
· Assume n = 16. Then each data stream will be mapped to a distinctive signature
(one-to-one mapping).
·
· Assume n = 17. Then exactly two data streams will be mapped to the same signature. Thus, for a particular data stream (the UUT good output response), there is ·only one other data stream (a faulty output response) that will have the same signature; i.e., only one faulty response out of 217 - 1 possible faults will not be detected.
· Assume n = 18. Then four different data streams will be mapped to the same signature. Hence, only three faults out of 218 - 1 possible faults will not be detected.
We can generalize the results obtained above. For any response data stream of
length n > 16, the probability of missing a faulty response when using a 16-bit signa-
ture analyzer is27
2n-16_1 -2 -16, for n> > 16.
2n- 1
Hence, the possibility of missing an error in the bit stream is very small (on the order of 0.002 percent). Note also that a great percentage of the faults will affect more than one output pin - hence the probability of not detecting these kind of faults is even lower.
Signature analysis provides a much higher level of confidence for detecting faulty output responses than that provided by transition counting. But, like transition counting, it requires only very simple hardware circuitry and a small amount of memory for storing the good signatures. As a result, the signatures of the output responses can be calculated even when the UUT is tested at its maximum speed. Unlike transition counting, the degree of fault coverage provided by signature analysis is not sensitive to the order of the test patterns. Thus, it is clear that signature analysis is the. most attractive solution to the response evaluation problem.
The rapid growth of the complexity and performance of digital circuits presents a testing problem of increasing severity. Although rriany testing methods have worked well for SSI and MSI circuits, most of them are rapidly becoming obsolete. New techniques are required to cope with the vastly more complicated LSI circuits.
Appendix 375
In general, testing techniques fall into the concurrent and explicit categories. In this article, we gave special attention to explicit testing techniques, especially those approaching the problem at the functional level. The explicit testing process can be partitioned into three steps: generating the test, applying the test to the UUT, and evaluating the UUT's responses. The various testing techniques are distinguished by the methods they use to perform these three steps. Each of these techniques has certain strengths and weaknesses.
We have tried to emphasize the range of testing techniques available, and to highlight some of the milestones in the evolution of LSI testing. The details of an individual test method can be found in the sources we have cited.
References
1. M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design ofDigital Systems, Computer Science Press, Washington, DC, 1976.
2. J.P. Hayes and E.J. McCluskey, "Testing Considerations in Microprocessor-Based Design," Computer, Vol. 13, No. 3, Mar. 1980, pp. 17-26.
3. ]. Wakerly, Error Detecting Codes, Self-Checking Circuits and Applications, American Elsevier, New York, 1978.
4. D.B. Armstrong, "On Finding a Nearly Minimal Set of Fault Detection Tests for Combinatorial Nets," IEEE Trans. Electronic Computers, Vol. EC-15, No. 2, Feb. 1966, pp. 63-73.
5. J.P. Roth, W.G. Bouricius, and P.R. Schneider, "Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits," IEEE Trans. Electronica Computers, Vol. EC-16, No. 5, Oct. 1967, pp. 567-580.
6. S.B. Akers, "Test Generation Techniques," Computer, Vol. 13, No. 3, Mar. 1980, pp. 9-15.
7. E.I. Muehldorf and A.D. Savkar, "LSI Logic Testing - An Overview," IEEE Trans. Computers, Vol. C-30, No. 1, Jan. 1981, pp. 1-17.
8. O.H. Ibarra and S.K. Sahni, "Polynomially Complete Fault Detection Problems," IEEE Trans. Computers, Vol. C-24, No. 3, Mar. 1975, pp 242-249.
9. T. Sridhar and J.P. Hayes, "Testing Bit-Sliced Microprocessors," Proc. 9th Int'/ Symp. Fault-Tolerant Computing, 1979, pp. 211-218.
376 Programmable Logic Design Guide
10. Tbe Am2900 Family Data Book, Advanced Micro Devices, Inc., 1979.
11. Z. Kohavi, Switching and Finite Automata Tbeory, McGraw-Hill, New York, 1970.
12. S.M. Thatte, "Test Generation for Microprocessors," PhD thesis, University of Illinois, Urbana, 1979.
13. S.M. Thatte andJ.A. Abraham, "Test Generation for Microprocessors," IEEE Trans. Computers, Vol. C-29, No. 6, June 1980, pp. 429-441. -
14. M.A. Breuer and A.D. Friedman, "Functional Level Primitives in Test Generation," IEEE Trans. Computers, Vol. C-29, No. 3, Mar. 1980, pp. 223-235.
15. M.S. Abadir and H.K. Reghbati, "Test Generation for LSI: A New Approach," Tech. Report 81-7, Dept. of Computational Science, University of Saskatchewan, Saskatoon, 1981.
16. M.S. Abadir and H.K. Reghbati, "Test Generation for LSI: Basic Operations," Tech. Report 81-8, Dept. of Computational Science, University of Saskatchewan, Saskatoon, 1981.
17. M.S. Abadir and H.K. Reghbati, "Test Generation for LSI: A Case Study," Tech. Report 81-9, Dept. of Computational Science, University of Saskatchewan, Saskatoon, 1981.
18. M.S. Abadir and H.K. Reghbati, "Functional Testing of Semiconductor Random Access Memories," Tech. Report 81-6, Dept. of Computational Science, Univeristy of Saskatchewan, Saskatoon, 1981.
19. S.B. Akers, "Binary Decision Diagram," IEEE Trans Computers, Vol. C-27, No. 6, June 1978, pp. 509-516.
Appendix 377
20. S.B. Akers, "Functional Testing with Binary Decision Diagram," Proc. 8t/J Int'! Symp. Fault-Tolerant Computing, June 1978, pp. 82-92.
21. B.A. Zimmer, "Test Techniques for Circuit Boards Containing Large Memories and Microprocessors," Proc. 1976 Semiconductor Test Symp., pp. 16-21.
22. P. Agrawal and V.D. Agrawal, "On Improving the Efficiency of Monte Carlo Test Generation," Proc. 5th Int'! Symp. Fault-Tolerant Computing, June 1975, pp. 205209.
23. D. Bastin, E. Girard, J.C. Rault, and R. Tulloue, "Probabilistic Test Generation Methods," Proc. 3rd Int'! Symp. Fault-Tolerant Computing, June 1973, p. 171.
24. J.P. Hayes, "Transition Count Testing of Combinational Logic Circuits," IEEE Trans. Computers, Vol. C-25, No. 6, June 1976, pp. 613-620.
25. "Signature Analysis," Hewlett Packard]., Vol.28, No. 9, May 1977.
26. R. David, "Feedback Shift Register Testing," Proc. 8th Int 'l Symp. Fault-Tolerant Computing, June 1978.
27. H.J. Nadig, "Testing a Microprocessor Product Using Signature Analysis," Proc. ,1978 Semiconductor Test Symp., pp. 159-169.
28. J.B. Peatman, Digital Hardware Design, McGraw-Hill, New York, 1980.
29. M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W.H. Freeman, San Francisco, 1978.
30. E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, Washington, DC, 1978. ·
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National Semiconductor (Far East) Ltd. Taiwan Branch P.O. Box 68-332 Taipei 7th Floor, Nan Shan Life Bldg., 302 Min Chuan East Road, Taipei, Taiwan R.O.C. Tel: (02) 501-7227 Telex: 22837 NSTW Cable: NSTW TAIPEI
National Semiconductor (Far East) Ltd. Korea Office Third Floor, Hankyung Bldg. 4-25 Hannam-Dong Yongsam-Ku, Seoul 140, Korea Tel: 797-8001 /3 Telex: K24942 NSRK
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