1987 U70-B Hitachi 8 16-Bit Microprocessor Data Book

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8/16-BIT MICROPROCESSOR DATA BOOK #U70-B @HITACHI® MEDICAL APPLICATIONS Hitachi's products are not authorized for use in MEDICAL APPLICATIONS, including, but not limited to, use in life support devices without the written consent of the appropriate officer of Hitachi's sales company. Buyers of Hitachi's products are requested to notify Hitachi's sales offices when planning to use the products in MEDICAL APPLICATIONS. When using this manual, the reader should keep the following in mind: l. This manual may, wholly or partially, be subject to change without notice. 2. All rights reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this manual without Hitachi's permission. 3. Hitachi will not be responsible for any damage to the user that may result from accidents or any other reasons during operation of his unit according to this manual. 4. This manual neither ensures the enforcement of any industrial properties or other rights, nor sanctions the enforcement right thereof. 5. Circuitry and other examples described herein are meant merely to indicate characteristics and performance of Hitachi semiconductorapplied products. Hitachi assumes no responsibility for any patent infringements or other problems resulting from applications based on the examples described herein. 6. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. August 1987 ©Copyright 1987, Hitachi America Ltd. Printed in U.S.A. II CONTENTS ·GENERAL INFORMATION · Quick Reference Guide .............................. . VIII · Introduction of Packages........................ . 1 · Reliability and Quality Assurance ............... . 11 · Reliability Test Data of Microcomputer ......... . 17 · Program Development and Support System ........... . 23 ·DATA SHEETS · NMOS 8-Bit Microprocessor HD6802 Microprocessor with Clock and RAM. 30 HD6802W Microprocessor with Clock and RAM ................. . 43 HD6803 Micro Processing Unit .......................... . 56 HD6809 Micro Processing Unit .................... . 83 HD6809E Micro Processing Unit .............................. . 115 · CMOS 8-Bit Microprocessor HD6303R Micro Processing Unit 151 HD6303X Micro Processing Unit 185 HD6303Y Micro Processing Unit 224 HD6305X2 Micro Processing Unit 268 HD63B09 Micro Processing Unit ........................... . 302 HD63B09E Micro Processing Unit 348 HD64180R Micro Processing Unit .................... . 385 · 16-Bit Microprocessor HD68000 Micro Processing Unit (NMOS) .... 519 HD68HCOOO Micro Processing Unit (CMOS). .519 · Hitachi Sales Offices ........................... . 606 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Ill @HITACHI IV Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 GENERAL , INFORMATION · Quick Reference Guide · Introduction of Packages · Reliability and Quality Assurance · Reliability Test Data of Microcomputer · Program Development and Support System v @HITACHI VI Hitachi America lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 QUICK REFERENCE GUIDE · NMOS 8-BIT MICROPROCESSOR Type No. H06802 Clock Frequency (MHz) 1.0 Supply Voltage (V) Operating Temperature· 1°c1 RAM (byte) Oscillator 5.0 -20--+75 128 Yes H06802W 1.0 5.0 H06803 H06803-1 H06809 H06BA09 H06BB09 H06809E H06BA09E H06BB09E 1.0 (H06803) 1.0 (H06809) 1.0 (H06809E) 1.25 (H06803-1) 1.5 (H068A09) 1.5 (H068A09E) 2.0 (H06BB09) 2.0 (H068B09E) 5.0 5.0 5.0 -20-+75 0-+10 -20--+75 -20--+75 256 128 - - Yes Yes Yes - Package Features OP-40 OP-40 ·Internal oscillator and RAM added to the H06800 · 32 byte RAM Battery backed up possible OP-40 OP-40 OP-40 ·Upward instruc- ·The highest ·Full software tion compatibil- version of the compatibility ity with the HMCS6800 with the H06800 family H06809 ·On-chip SCI ·Powerful ad- ·Bus employ- and timer dressing modes ment on time ·Easy relocat- sharing basis able/reentrant ·External clock programming Compatibility Reference Page MC6802 30 MC6809 MC6809E - MC6803 MC68A09 MC6BA09E MC6803-1 MC6BB09 MC6BB09E 43 56 83 115 ·Wide Temperature Range (-40-+85°C) version is available. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 VII QUICK REFERENCE GUIDE------~~------------------ · CMOS 8-BIT MICROPROCESSOR Type No. HD6303R HD63A03R HD63803R HD6303X HD63A03X HD63803X Clock Frequency (MHz) 1.0 (HD6303R) 1.5 (HD63A03R) 2.0 (HD63803R) 1.0 (HD6303X) 1.5 (HD63A03X) 2.0 (HD63803X) Supply Voltage (V) 5.0 5.0 Operating Temperature* (°C) 0-+10 0-+10 RAM (byte) 128 192 External Memory Expansion (byte) 65k 65k Package DP-40, FP-54, CG-40, CP-52 DP-64S, FP-80, CP-68 Features · On-chip timer and synchronous/asynchronous SCI · Upward instruction compatibility with the HD6800 · Low power consumption modes (sleep and standby) HD6303Y HD63A03Y HD63B03Y HD63C03Y 1.0 (HD6303Y) 1.5 (HD63A03Y) 2.0 (HD63803Y) 3.0 (HD63C03Y) 5.0 0-+10 256 65k DP-64S, FP-64, CP-68 Reference Page 151 *Wide Temperature Range (-40-+85°C) version is available. CPtM® is the registered trade mark of Digital Research Inc. 185 224 @HITACHI VIII Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE HD6305X2 HD63A05X2 HD63B05X2 1.0 (HD6305X2) 1.5 (HD63A05X2) 2.0 (HD63B05X2) 5.0 0- +70 128 16k HD6305Y2 HD63A05Y2 HD63B05Y2 1.0 (HD6305Y2) 1.5 (HD63A05Y2) 2.0 (HD63B05Y2) 5.0 0- +70 256 16k HD63B09/E HD63C09/E 2.0 (HD63B09/E) 3.0 (HD63C09/E) 5.0 -20- + 75 65k HD64180R HD64180R 6.0 (HD64180RP-6) 6.0 (HD64180RCP-6X) 8.0 (HD64180RP-8) 8.0 (HD64180RCP-8X) 5.0 0- +70 512k 5.0 0- +70 1M DP-64S, FP-64 DP-64S, FP-64 DP-40 DP-64S CP-68 · On-chip timer and synchronous SCI · Powerful bit manipulation instruction · Low power consumption modes (wait, stop and standby) 268 268 · Software compatibility with the HD6809/E · Easy relocatable/ reentrant programming · Flexible system expansion capabilities 302/348 · On-chip MMU, DMAC, synchronous/ asynchronous SCI and timer · Software compatibility with Z80/8080 385 385 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 IX QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - · NMOS 16-BIT MICROPROCESSOR Type No. Clock Frequency (MHz) HD68000·8 HD68000·10 HD68000·12 HD68000Y8 HD68000Y10 HD68000Y12 8.0(HD68000-8) 8.0(HD68000Y..S) 10.0(HD68000·10) 10.0(HD68000Y-10 12.5(HD68000·12) 12.5(HD68000Y-12 HD68000P8 HD68000PS8 HD68000CP8 8.0(HD680001!8) 8.0(HD68000PS8) 8.0(HD68000CP-8) Supply Voltage (V) 5.0 Operating Temperature (QC) 0-+10 Power Dissipation (W) 1.5 (f = 6MHz, 8MHz, 10MHz), 1.75 (f = 12.5 MHz) 0.9 (f = 8MHz) Package DC-64 PGA-68 DP-64 DP-64S CP-68 Feature Compatibility High performance MPU featuring 32-bit data processing function MC68000L6 MC68000L8 MC68000L10 MC68000L12 MC68000R6 MC68000R8 MC68000R10 MC68000R12 MC68000P6 MC68000P8 MC68000FN6 MC68000FN8 Reference Page 519 519 519 I 519 519 · CMOS 16-BIT MICROPROCESSOR Type No. H D68HC000-8 HD68HC000·10 HD68HC000-12 HD68HCOOOY..S HD68HC000""10 HD68HCOOOY-12 HD68HCOOOP-8 HD68HCOOOP10 HD68HC000~12 HD68HCOOOPS8 HD68HCOOOP5-10 HD68HCOOOPS'l 2 HD68HCOOOCP-8 HD68HCOOOCP..10 H D68HCOOOCP..12 Clock 8.0(HD68HC000-8 ) 8.0(HD68HC000¥8 ) 8.0(HD68HCOOOP8 ) 8.0(HD68HCOOOP98 ) 8.0(HD68HCOOOC~ ) Frequency 1O.O(HD68HC000-10) 10.0(HD68HCOOOY10) 10.0(HD68HCOOOP-10) 10.0(HD68HCOOOPS10) 10.0(HD68HCOOOC~O) (MHz) 12.5(HD68HC000-12) 12.5(HD68HCOOOY12) 12.5(HD68HCOOOl!.12) 12.5(HD68HCOOOP912) 12.5(HD68HCOOOCP-l2) Supply Voltage 5.0 (V) Operating Temperature (QC) 0-+10 Current Dissipa· tion (mA) Package DC-64 PGA-68 25 (f = 8 MHz) 30 (f= 10 MHz) 35 (f = 12.5 MHz) DP-64 DP-64S CP-68 Feature High performance MPU featuring 32-bit data processing function Compati· bility MC68HCOOOL8 MC68HCOOOL 10 MG68HCOOOL 12 MC68HCOOOR8 MC68HCOOOR10 MC68HCOOOR12 MC68HCOOOG8 MC68HCOOOG10 MC68HCOOOG12 MC68HCOOOFN8 MC68HCOOOFN 10 MC68HCOOOFN12 Reference Page 519 519 519 519 519 @HITACHI x Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 INTRODUCTION OF PACKAGES Hitachi microcomputer devices include various types of package which meet a lot of requirements such as ever smaller, thinner and more versatile electric appliances. When selecting a package suitable for the customers' use, please refer to the following for Hitachi microcomputer packages. 1. Package Classification There are pin insertion types, surface mounting types and multi-function types, applicable to each kind of mounting method. Also, plastic and ceramic materials are offered according to use. Fig. 1 shows the package classification according to the mounting types on the Printed Circuit Board (PCB) and the materials. Pin Insertion Type Standard Outline Shrink Outline DIP S-DIP PGA Plastic DIP Ceramic DIP Shrink Type Plasti~ DIP Shrink Type Ceramic DIP Package Classification Surface Mounting Type Flat Package Chip Carrier Multi-function Type EPROM on the Package Type DIP; DUAL IN LINE PACKAGE S-DIP; SHRINK DUAL IN LINE PACKAGE PGA: PIN GRID ARRAY FLAT-DIP; FLAT DUAL IN LINE PACKAGE FLAT-QUIP; FLAT QUAD IN LINE PACKAGE CC: CHIP CARRIER SOP;SMALL OUTLINE PACKAGE FPP; FLAT PLASTIC PACKAGE PLCC; PLASTIC LEADED CHIP CARRIER LCC; LEADLESS CHIP CARRIER SOP (Plastic) FPP (Plastic) PLCC (Plastic) LCC (Glass Sealed Ceramic) Fig. 1 Package Classification according to the Mounting Type on the Printed Circuit Board and the Materials. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 INTRODUCTION OF P A C K A G E S - - - - - - - - - - - - - - - - - - - - - - - - 2. Type No. and Package Code Indication Type No. of Hitachi microprocessor is followed by package material and outline specifications, as shown below. The package type used for each device is identified by code as follows, illus· trated in the data sheet of each device. When ordering, please write the package code beside the type number. Type No. Indication HDxxxxP !Note) The HD68000 with shrink type plastic DIP loP-645) has a different type No. from other devices. Type No.; H D68QQQPS8 Package designation Packase Classification No indication : Ceramic DIP P Plastic DIP F FPP CP PLCC CG LCC Y PGA (16-bit microcomputer device) Package Code Indication DP-645 L,. .Qiu!io.e. ~M-a te-r-ia-ls.... -~ N-u_m_be- 'r'-o-f-P-in~·I I °'.t!in· D ;DIP P ; Plastic S; S·DIP C;CC F ; FLAT G ; Glass Sealed ceramic C ;Ceramic; (Note) PGA packages of 16~bit microcomputer devices have a different indication. P G A - 6 8 Package Code Indication; Package Classification Number of Pins ~HITACHI 2 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 3. Package Dimensional Outli,ne Hitachi microprocessor employs the packages shown in Table 1 Package List Table I according to the mounting method on the PCB. Method of Mounting Package Classification Pin Insertion Type Standard Outline (DIP) Shrink Outline S-DIP PGA Flat Package FLAT-QUIP (FPP) Surface Mounting Type Chip Carrier PLCC LCC Package Material Plastic Ceramic Plastic Glass Sealed Ceramic Plastic Plastic Glass Sealed Ceramic Package Code DP-40 DP-64 DC-64 DP-64S PGA-68 FP-54 FP-64 FP-80 CP-52 CP-68 CG-40 Plastic DIP · DP-40 52.8(2.079) 54.0max. (2. I 26max.) Unit: mm(inch) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 3 · DP-64 82.04 (3.230) 83.22max.(3.276max.J 64 33 Unit: mm(inch) 22.86 (0.900) @HITACHI 4 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I Ceramic DIP eDC-64 64 81.28 (3.200) Unit: mm( inch) 33 22 86 (0900) I ,_______.~ 0.25!~ (O.OI0!8:8Sl) Shrink Type Plastic DIP eDP-645 Unit: mm(inch) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 5 I Pin Grid Arrey ePGA-68 2642 (1.040) 8 ·~ .::; D @ 5.08max. 2.54min. (0.200max.) (O. IOOm;n.) 22.86±0.45 (0.900±0.0187) Z.54max. (0. IOOmax.) Unit: mm( inch) Flat Packlge eFP-54 25.6±0.4 ( 1.008±0.016) 20 Z.9max. (0.J 14max.) ·FP-64 25.6±0.4(1.008 ± 0.0 16) JI_ 0.15±0.05 (0.006±0.002) I b 2.9max. (O. I I 4max.) Unit: mm(inch) · ~05 (0.039±0.006) (o.014±Q.004) 0.15± 0· oozl (o.oos±O. ~j_o·-1-=5=r· ~(0061t~-no0.00~l;Z))_____________ 1.1 ±0.3 . @HITACHI 6 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 e FP-80 25.6 ± 0.4( 1.008 ± 0.016) 20 (0.787) 2.9max. (O.l 14max.) 80 lmmmrmmm~ _JL -L 0.8±0.15 0.35±0.1 (0.031 ±0.006) (0.014±0.004) _L o \S±O.OS (0.~06±0.002) ~ooei±o.0121 o·-15· 1.1±0.'3\. I Plastic Leaded Chip Carrier · CP-52 1 8~ ~ N~ -:o 0 ci -H-H ~o ~~ c 20 07±0 12 (0.790±0.005) I 52 0 47 46 20 I J34 21 33 19.12 (0.753) d!..-1~-------~1 -H -H :~ e 18.04±0.5 (0. 710±0.020) Unit: mm( inch) Unit: mm(inch) @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 7 · CP-68 9 10 ~~ I~ . g; ~ 8~ ~ 26~ 27 25.15±0.12 (0 990-; 0.005) 16~ 0 61 60 ~ B E ~ d ~ ~ ~~ 44 'UUL.,,IUUU. 43 ~ 'i'I 0 ~ ~ ci d -+< -+< 0 N ~ i""' 8 Unit: mm(inch) Leedless Chip Carrier · CG-40 12.19±0.3 (0.480±0.012) (CG-40) 0.75max. (0.030maJ1:.) Unit : mm(inch) @HITACHI 8 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 4. Mounting Method on Board Lead pins of the package have surface treatment, such as solder coating or solder plating, to make them easy to mount on the PCB. The lead pins are connected to the package by eutectic solder. The following explains the common connecting method of leads and precautions. 4.1 Mounting Method of Pin Insertion Type Package Insert lead. pins of the package into through-holes (usually about <f>0.8mm) on the PCB. Soak the lead part of the package in a wave solder tub. Lead pins of the package are held by the through-holes. Therefore, it is easy to handle the package through the process up to soldering, and easy to automate the soldering process. When soldering the lead part of the package in the wave solder tub , be careful not to get the solder on the package, because the wave solder will damage it. 4.2 Mounting Method of Surface Mounting Type Package Apply the specified quantity of solder paste to the pattern on any printed board by the screen printing method, and put a package on it. The package is now temporarily fixed to the printed board by the surface tension of the paste. The solder paste melts when heated in a reflowing furnace, and the leads of the package and the pattern of the printed board are fixed together by the surface tension of the melted solder and the self alignment. The size of the pattern where the leads are attached, partly depending on paste material or furnace adjustment, should be I.I to 1.3 times the leads' width. The temperature of the reflowing furnace depends on package material and also package types. Fig. 2 lists the adjustment of the reflowing furnace for FPP. Pre-heat the furnace to 150°C. The surface temperature of the resin should be kept at 235°C max. for 10 minutes or less. Ensure good heater or temperature controls because the material of a plastic package is black epoxy-resin which damages easily. When an infrared heater is used, if the temperature is higher than the glass transition point of epoxy-resin (about 150°C), for a long time, the package may be damaged and the reliability lowered. Equalize the temperature inside and outside the packages by l~ssening the heat of the upper surface of the packages. Leads of FPP may be easily bent under shipment or during handling and cannot be soldered onto the printed board. If they are, heat the bent leads again with a soldering iron to reshape them. Use a rosin flux when soldering. Don't use a chloric flux because the chlorine in the flux tends to remain on the leads and lower the reliability of the product. Even if you use a rosin flux, remaining flux can cause the leads to deteriorate. Wash away flux from packages with alcohol, chlorothene or freon. But don't leave these solvents on the packages for a long time because the marking may disappear. 5. Marking Hitachi trademark, product type No., etc. are printed on packages. Case I and Case II give examples of marks and Nos. Case I applies to products which have only a standard type No. Case II applies to products which have an old type No. and a standard type No. (1) The temperature of the leads should be kept at 260°C for 10 minutes or less. (2) The temperature of the resin should be kept at 235°C for 10 minutes or less. (3) Below is shown the temperature profile when soldering a package by the reflowing method. Time_____. Figure 2 Reflowing Furnace Adjustment for FPP @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 9 INTRODUCTION OF P A C K A G E S - - - - - - - - - - - - - - - - - - - - - - - Case I; Includes a standard type No. (a) (b) @ l1JDB (c)BDB809B (d) D~B~r5J Case II; Includes an old type No. and a standard type No. (a) (b) '® l1JDB B (e) D~BBDDDB (d)D~B~rsl (c) B DBBDDB Meaning of Each Mark (a) Hitachi Trademark (b) Lot Code (c) Standard Type No. (d) Japan Mark (e) Old Type No. @HITACHI 10 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 RELIABILITY AND QUALITY ASSURANCE 1. VIEWS ON QUALITY AND RELIABILITY Basic views on quality in Hitachi are to meet individual user's purchase purpose and quality required, and to be at the satisfied quality level considering general marketability. Quality required by users is specifically clear if the contract specification is provided. If not, quality required is not always definite. In both cases, efforts are made to assure the reliability so that semiconductor devices delivered can perform their ability in actual operating circumstances. To realize such quality in manufacturing process, the key points should be to establish quality control system in the process and to enhance morale for quality. In addition, quality required by users on semiconductor devices is going toward higher level as performance of electronic system in the market is going toward higher one and is expanding size and application fields. To cover the situation, actual bases Hitachi is performing is as follows; (l) Build the reliability in design at the stage of new product development. (2) Build the quality at the sources of manufacturing process. (3) Execute the harder inspection and reliability confirmation of final products. (4) Make quality level higher with field data feed back. (5) Cooperate with research laboratories for higher quality and reliability. With the views and methods mentioned above, utmost efforts are made for users' requirements. 2. RELIABILITY DESIGN OF SEMICONDUCTOR DEVICES 2.1 Reliability Targets Reliability target is the important factor in manufacture and sales as well as performance and price. It is not practical to rate reliability target with failure rate at the certain common test condition. The reliability target is determined corresponding to character of equipments taking design, manufacture, inner process quality control, screening and test method, etc. into consideration, and considering operating circumstances of equipments the semiconductor device used in, reliability target of system, derating applied in design, operating condition, maintenance, etc. 2.2 Reliability Design To achieve the reliability required based on reliability targets, timely sude and execution of design standardization, device design (including process design, structure design), design review, reliability test are essential. ( 1) Design Standardization Establishment of design rule, and standardization of parts, material and process are necessary. As for design rule, critical items on quality and reliability are always studied at circuit design, device design, layout design, etc. Therefore, as long as standardized process, material, etc. are used, reliability risk is extremely small even in new development devices, only except for in the case special requirements in function needed. (2) Device Design It is important for device design to consider total balance of process design, structure design, circuit and layout design. Especially in the case new process, and new material are employed, technical study is deeply executed prior to device development. (3) Reliability Evaluation by Test Site Test site is sometimes called Test Pattern. It is useful method for design and process reliability evaluation of IC and LSI which have complicated functions. 1. Purposes of Test Site are as follows; · Making clear about fundamental failure mode · Analysis of relation between failure mode and manufac- turing process condition · Search for failure mechanism analysis · Establishment of QC point in manufacturing 2. Effectiveness of evaluation by Test Site are as follows; · Common fundamental failure mode and failure mecha- nism in devices can be evaluated. · Factors dominating failure mode can be picked up, and comparison can be made with process having been experienced in field. · Able to analyze relation between failure causes and manufacturing factors. · Easy to nin tests. etc. 2.3 Design Review Design review is organized method to confirm that design satisfies the performance required including users' and design work follows the specified ways, and whether or not technical improved items accumulated in test data of individual major fields and field data are effectively built in. In addition, from the standpoint of enhancement of competitive power of products, the major purpose of design review is to ensure quality and reliability of the products. In Hitachi, design review is performed from the planning stage for new products and even for design changed products. Items discussed and determined at design review are as follows; (1) Description of the products based on specified design documents. (2) From the standpoint of specialty of individual participants, design documents are studied, and if unclear matter is found, sub-program of calculation, experiments, investigation, etc. will be carried out. (3) Determine ·contents of reliability and methods, etc. based on design document and drawing. (4) Check process ability of manufacturing line to achieve design goal. (5) Discussion about preparation for production. (6) Planning and execution of sub-programs for design change proposed by individual specialist, and for tests, experiments and calculation to confirm the design change. (7) Reference of past failure experiences with similar devices, confumation of method to prevent them, and planning and execution of test program for confumation of them. These studies and decisions are made using check lists made individually depending on the objects. 3. QUALITY ASSURANCE SYSTEM OF SEMICONDUCTOR DEVICES 3.1 Activity of Quality Assurance General views of overall quality assurance in Hitachi are as follows; (I) Problems in individual process should be solved in the @HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 11 RELIABILITY AND QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - - process. Therefore, at final product stage, the. potential failure factors have been already removed. (2) Feedback of information should be made to ensure satisfied level of process ability. . (3) To assure reliability required as an result of the things mentioned above is the purpose of quality assurance. The followings are regarding device design, quality approval at mass production, inner process quality control, product inspection and reliability tests. 3.2 Quality Approval To ensure quality and reliability required, quality approval is carried out at trial production stage of device design and mass production stage based on reliability design described at section 2. The views on quality approval are as follows; (1) The third party performs approval objectively from the standpoint of customers. (2) Fully consider past failure experiences and information from field. (3) Approval is needed for design change and work change. (4) Intensive approval is executed on parts material and pro- cess. (5) Study process ability and fluctuation factor, and set up control points at mass production stage. Considering the views mentioned above, quality approval shown in Fig. 1 is performed. 3.3 Quality and Reliability Control at Mass Production For quality assurance of products in mass production, quality control is executed with organic division of functions in manufacturing department, quality assurance department, which are major, and other departments related. The total function flow is shown in Fig. 2. The main points are described below. 3.3.1 Quality Control of Parts and Material As the performance and the reliability of semiconductor devices are getting higher, importance is increasing in quality control of material and parts, which are crystal, lead frame, fine wire for wire bonding, package, to build products, and materials needed in manufacturing process, which are mask pattern and chemicals. Besides quality approval on parts and materials stated in section 3.2, the incoming inspection is, also, key in quality control of parts and materials. The incoming inspection is performed based on incoming inspection specification following purchase specification and drawing, and sampling inspection is executed based on MIL-STD-1050 mainly. The other activities of quality assurance are as follows: (1) Outside Vendor Technical Information Meeting (2) Approval on outside vendors, and guidance of outside vendors (3) Physical chemical analysis and test The typical check points of parts and materials are shown in Table 1. 3.3.2 Inner Process Quality Control Inner process quality control is performing very important function in quality assurance of semiconductor devices. The following is description about control of semi-final products, fmal products, manufacturing facilities, measuring equipments, Step Target Specification Contents Design Review Purpose Design Trial Production Characteristics of Material and i . - - - - - - 1 Confirmation of Parts Characteristics and Appearance Reliability of Materials Dimension and Parts Heat Resistance '----------' Mechanical Electrical Others Characteristics Approval 1 i - - - - - - - - - 1 Electrical Characteristics Function Voltage Current Temperature Others Appearance, Dimension ~-----1 Confirmation of Target Spec. Mainly about Electrical Characteristics ~aliu:;<aililitltvrAAIJlppP,r:;;o~va>f1('111J1:-'1]..,__ _ _ _ _ _ _.fRR;je1i;;;a;bbJii1itity;TT';esttt-----°14-------fconfirmation of aUality Life Test Thermal Stress Moisture Resistance Mechanical Stress Others and Reliability in Design fiCOhu;;;aiTlit~y~Al>.ippjp;';r;;:ov~a;f1f:12!\'1="il-oi---------fiRR.e;ji1;f;;abibiiil1;t";ty';'Tf.e'5stt----lt-0------1 Confirmation of Quality Process Check same as and Reliability in Mass Mass Quality Approval U) Production Production Figure 1 Flow Chart of Quality Approval @HITACHI 12 Hitachi America Ltd. · 2210 O'lbole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y AND QUALITY ASSURANCE circumstances and sub-materials. The quality control in the manufacturing process is shown in Fig. 3 corresponding to the manufacturing process. (1) Quality Control of Semi-final Products and Final Products Potential failure factors of semiconductor devices should be removed preventively in manufacturing process. To achieve it, check points are set-up in each process, and products which have potential failure factor are not transfer to the next process. Especially, for high reliability semiconductor devices, manufacturing line is rigidly selected, and the quality control in the manufacturing process is tightly executed - rigid check in each process and each lot, 100% inspection in appropriate ways to remove failure factor caused by manufacturing fluctuation, and execution of screening needed, such as high temperature aging and temperature cycling. Contents of inner process quality control are as follows; · Condition control on individual equipments and workers, and sampling check of semifinal products. · Proposal and carrying-out improvement of work · Education of workers · Maintenance and improvement of yield · Picking-up of quality problems, and execution of counter- measures · Transmission of information about quality (2) Quality Control of Manufacturing Facilities and Measuring Equipment Equipments for manufacturing semiconductor devices have been developing extraordinarily with necessary high performance devices and improvement of production, and are important factors to determine quality and reliability. In Hitachi, automatization of manufacturing equipments are promoted to improve manufacturing fluctuation, and controls are made to maintain proper operation of high performance equipments and perform the proper function. As for maintenance inspection for quality control, there are daily inspection which is performed daily based on specification related, and periodical inspection which is performed periodically. At the inspection, inspection points listed in the specification are checked one by one not to make any omission. As for adjustment and maintenance of measuring equipments, maintenance number, specification are checked one by one to maintain and improve quality. (3) Quality Control of Manufacturing Circumstances and Sub- materials Quality and reliability of semiconductor device is highly Process Quality Control Method Material. Parts Material, Parts Inspection on Material and Parts for Semiconductor Devices ;---- I I I I I I I I I I I I ----, I 1--I I I I rI --- I I I I 1---____ JI Manufacturing Equipment, Environment, Sub~material, Worker Control Inner Process Quality Control 100% Inspection on Appearance and Electrical Characteristi~ Products I I I I I I ~---- Sampling Inspection on Appearance and Electrical Characteristics Reliability Test Lot Sampling, Confirmation of QuaIity Level Confirmation of Quality Level Lot Sampling, Confirmation of Quality Levei Testing, Inspection Lot Sampling Confirmation of Quality Level, Lot Sampling Customer r ---------------, : Quality Information 1 1 Claim : II Field Experience General Quality Information I L-----------------~ Feedback of Information Figure 2 Flow Chart of Quality Control in Manufacturing Process @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 13 RELIABILITY AND QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - - affected by manufacturing process. Therefore, the controls of manufacturing circumstances - temperature, humidity, dust and the control of submaterials - gas, pure water - used in manufacturing process are intensively executed. Dust control is descnbed in more detail below. Dust control is essential to realize hlgher integration and higher reliability of devices. In Hitachi, maintenance and improvement of cleanness in manufacturing site· are executed with paying intensive attention on buildings, facilities, airconditioning systems, materials delivered-in, clothes, work, etc., and periodical inspection on floating dust in room, falling dusts and dirtiness of floor. 3.3.3 Final Product Inspection and Reliability Assurance (I) Final Product Inspection Lot inspection is done by quality assurance department for products which were judged as good products in 100% test, which is fmal process in manufacturing department. Though 100% of good products is expected, sampling inspection is executed to prevent mixture of failed products by mistake of work, etc. The inspection is executed not only to confirm that the products meet users' requirement, but to consider potential factors. Lot inspection is executed based on MIL-STD-1050. (2) Reliability Assurance Tests To assure reliability of semiconductor devices, periodical reliability tests and reliability tests on individual manufacturing lot required by user are performed. Table 1 Quality Control Cheek Points of Material and Parts (Example) Material, Parts Wafer Mask Fine Wire for Wire Bonding Frame Ceramic Package Plastic Important Control Items Appearance Dimension Sheet Resistance Defect Density Crystal Axis Appearance Dimension Resistoration Gradation Appearance Dimension Purity Elongation Ratio Appearance Dimension Processing Accuracy Plating Mounting Characteristics Appearance Dimension Leak Resistance Plating Mounting Characteristics Electrical Characteristics Mechanical Strength Composition Electrical Characteristics Thermal Characteristics Molding Performance Mounting Characteristics Point for Check Damage and Contamina- tion on Surface Flatness Resistance Defect Numbers Defect Numbers, Scratch Dimension Level Uniformity of Gradation Contamination, Scratch, Bend, Twist Purity Level Mechanical Strength Contamination, Scratch Dimension Level Bondability, Solderability Heat Resistance Contamination, Scratch Dimension Level Airtightness Bondability, Solderability Heat Resistance Mechanical Strength Characteristics of Plastic Material Molding Performance Mounting Characteristics @HITACHI 14 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y AND QUALITY ASSURANCE Process Purchase of Material I Wafer ~Surface Oxidation Inspection on Surface Oxidation Photo Resist Inspection on Photo Resist O PQC Level Check Diffusion Inspection on Diffusion o PQC Level Check Frame Evaporation Inspection on Evaporation o PQC Level Check Wafer Inspection Inspection on Chip Electrical Characteristics Chip Scribe Inspection on Chip Appearance o PQC Lot Judgement Assembling o PQC Level Check Package Inspection after Assembling O PQC Lot Judgement Sealing o PQC Level Check Final Electrical Inspection o Failure Analysis Appearance Inspection Sampling Inspection on Products Receiving Shipment Control Point Wafer Oxidation Photo Resist Diffusion Evapora· tion Characteristics, Appearance Appearance, Thickness of Oxide Film Dimension, Appearance Diffusion Depth, Sheet Resistance Gate Width Characteristics of Oxide Film Breakdown Voltage Thickness of Vapor Film, Scratch, Contamination Wafer Chip Thickness, VTH Characteristics Electrical Characteristics Appearance of Chip Assembling Appearance after Chip Bonding Appearance after Wire Bonding Pull Strength, Compression Width, Shear Strength Appearance after Assembling Sealing Marking Appearance after Sealing Outline, Dimension Marking Strength Analysis of Failures, Failure Mode, Mechanism Purpose of Control Scratch, Removal of Crystal Defect Wafer Assurance of Resistance Pinhole, Scratch Dimension Level Check of Photo Resist Diffusion Status Control of Basic Parameters IVTH, etc.) Cleanness of surface, Prior Check of V1H Breakdown Voltage Check Assurance of Standard Thickness Prevention of Crack, Quality Assurance of Scribe Quality Check of Chip Bonding Quality Check of Wire Bonding Prevention of Open and Short Guarantee of Appearance and Dimension Feedback of Analysis Information Figure 3 Example of Inner Process Quality Control @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 15 RELIABILITY AND QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - - Customer Claim (Failures, Information) Sales Dept. Sales Engineering Dept. r------------ ---------------------1 ---------. Qualitv Assurance Dept. Failure Analvsis I I I I I Manufacturing Dept. Report Design Dept. Countermeasure I Execution of I Countermeasure I I I I I I Qualitv Assurance Dept. Follow-up and Confirmation II of Countermeasure Execution I I Report I L------------ --------------------~ Sales Engineering Dept. Replv Customer Figure 4 Process Flow Chart of Field Failure @HITACHI 16 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 RELIABILITY TEST DATA OF MICROCOMPUTER 1. INTRODUCTION Microcomputer is r~quired to provide higher reliability and quality with increasing function, enlarging scale and widening application. To meet this demand, Hitachi is improving the quality by evaluating reliability, building up quality in process, strengthening inspection and analyzing field data etc.. This chapter describes reliability and quality assurance data for Hitachi 8·bit and 16-bit multi-chip microcomputer based on test and failure analysis results. More detail data and new information will be reported in another reliability data sheet. 2. PACKAGE AND CHIP STRUCTURE 2.1 Package The reliability of plastic molded type has been greatly improved, recently their applications have been expanded to automobiles measuring and control systems, and computer terminal equipment operated under relatively severe conditions and production output and application of plastic molded type will continue to increase. To meet such requirements, Hitachi has considerably im· proved moisture resistance, operation stability, and chip and plastic manufacturing process. Plastic and ceramic package type structure are shown in Figure 1 and Table 1. (1) Ceramic DIP 0 Lid Chip (2) Plastic DIP Bonding wire l3l Plastic Flat Package Bonding wire Chip Item Package Lead Seal Die bond Wire bond Wire Figure 1 Package Structure Table 1 Package Material and Properties Ceramic DIP Alumina Tin plating Brazed Alloy 42 Au-Sn Alloy Au-Si Ultrasonic Al Plastic DIP Epoxy Solder dipping Alloy 42 or Cu N.A Au-Si or Ag paste Thermo compression Au Plastic Flat Packa11.9 Epoxy Solder plating Alloy 42 N.A Au-Si or Ag paste Thermo compression Au @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 17 RELIABILITY TEST DATA OF M I C R O C O M P U T E R - - - - - - - - - - - - - - - - - - - 2.2 Chip Structure Hitachi microcomputers are produced in NMOS E/D tech· nology or low power CMOS technology. Si-gate process is used in both types because of high reliability and high density. Chip structure and basic circuit are shown in Figure 2. Si-Gate N-channel E/D Si·Gate CMOS Drain Source Drain Source FET1 FET2 FET2 N-channel DMOS N-channel EMOS Si02 Source Drain FET2 P-channel EMOS N-channel EMOS Figure 2 Chip Structure and Basic Circuit 3. QUALITY QUALIFICATION AND EVALUATION 3.1 Reliability Test Methods Reliability test methods shown in Table 2 are used to qualify and evaluate the new products and new process. Table 2 Reliability Test Methods Test Items Operating Life Test High Temp, Storage Low Temp, Storage Steady State Humidity Steady State Humidity Biased Temperature Cycling Temperature Cycling Thermal Shock Soldering Heat Mechanical Shock Vibration Fatigue Variable Frequency Constant AC'celeration Lead Integrity Test Condition 12s0 c, 1000hr Tstg max, 1000hr Tstg min, 1000hr 65°C 95%RH, 1000hr 85°C 85%RH, 1000hr -55°C-150°C, 10cycles -20°C - 125°c; 200 cycles 0°c- 100°c, 100 cycles 2so0 c, 10 sec 1500G 0.5 msec, 3 times/X, Y, Z 60Hz 20G, 32hrs/X, Y, Z 20-2000Hz 20G,4 min/X, Y, Z 200000, 1 min/X, Y, Z 225gr, 90° 3 times MIL·STD·883B Method No. 1005,2 1008,1 1010.4 1011,3 2002,2 2005,1 2007, 1 2001,2 2004,3 @HITACHI 18 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y TEST DATA OF MICROCOMPUTER 3.2 Reliability Test Result Reliability test result of 8-bit microprocessors is shown in Table 3 to Table 7, that of 16-bit microprocessors in Table 8, Table 9. There is little difference according to device series, as the design and production process, etc. are standardized. Table 3 Dynamic Life Test (8-bit microprocessor) Device Type HD6800 HD6802 HD6809 Sample Size 248 pcs 452 85 Component Hours 248000 153712 85000 Failures 0 1* 0 Total 785 486712 1 *leakage current Estimated Field Failure Rate = 0.01% / 1000 hrs at Ta= 75°C (Activation Energy :: 0. 7eV, Confidence Level 60%) Table 4 High Temperature, High Humidity Test (8-bit microprocessor) (Moisture Resistance Test) (1) 85°C 85%RH Sias Test Device Type HD6800P HD6802P HD6809P Total Vee Bias 5.5V 5.5V 5.5V 168 hrs 0/45 0/38 0/22 0/105 500 hrs 0/45 0/38 0/22 0/105 1000 hrs 0/45 0/38 0/22 0/105 (2) High Temperature-High Humidity Storage Life Test Device Type Condition HD6800P HD6802P HD6802P HD6809P 65°C 95%RH 80°C 90%RH 65°C 95%RH 65°C 95%RH 168 hrs 0/22 0/22 0/38 0/45 500 hrs 0/22 0/22 0/38 0/45 (3) Pressure Cooker Test (Condition ; 2atm 121°C) Device Type HD6800P HD6802P 40 hrs 0/42 0/22 60 hrs 0/42 0/22 (4) MIL-STD-8838 Moisture Resistance Test (Condition; 65°C- -10°C, over 90"A>RH, Vee= 5.5V) Device Type 10 cycles HD6800P HD6802P 0/25 0/25 100 hrs 0/42 0/22 20 cycles 0125 0/25 1000 hrs 0/22 0/22 0/38 0/45 40 cycles 0/25 0/25 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 19 RELIABILITY TEST DATA OF M I C R O C O M P U T E R - - - - - - - - - - - - - - - - - Table 5 Temperature Cycling Test (8-bit microprocessor} (-55°C - 25°C - 150°C) Device Type HD6800P HD6802P HD6809P 10 cycles 0/453 0/502 0/202 100cycles 0/44 0/77 0/45 200cycles 0/44 0/77 0/45 Device MPU total Table 6 High Temperature, Low Temperature Storage Life Test CB-bit microprocessor) Temperature 150°C -55°c 168 hrs 0/88 0/76 500 hrs 0/88 0/76 Table 7 Mechanical and Environmental Test (8-bit microprocessor) Test Item Condition Thermal Shock Soldering Heat Salt Water Spray Solderability Drop Test Mechanical Shock Vibration Fatigue Vibration Variable Freq. Lead Integrity 0°c-100°c 10 cycles 260°C, 10 sec. 35°C, NaCl 5% 24 hrs 230°C, 5 sec. Rosin flux 75cm, maple board 3times 1500G, 0.5 ms 3 times/X, Y, Z 60 Hz, 20G 32 hrs/X, Y, Z 100-2000Hz 20G, 4 times/X, Y, Z 225 g, so· Bonding 3 times Plastic DIP Flat Plastic Package Sample Size Failure Sample Size Failure 110 0 100 0 180 0 20 0 110 0 20 0 159 0 34 0 110 0 20 0 110 0 20 0 110 o.' 20 0 110 0 20 0 110 0 20 0 1000 hrs 0/88 0/76 @HITACHI 20 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y TEST DATA OF MICROCOMPUTER Device Type HD68000 Table 8 Dynamic Life Test (16-bit microprocessor) Condition Ta 125°C 150°C Vee 5.5V 5.5V 168 hrs 0/62 0/52 500 hrs 0/62 0/52 1000 hrs 0/62 0/52 Estimated Field Failure Rate = 0.013%/1000 hrs at Ta= 75°C (Activation Energy 0. 7eV, Confidence Level 60%) Test Item High Temperature Storage Low Temperature Storage Temperature Cycling (1) Temperature Cycling (2) Thermal Shock Soldering heat Solderability Mechanical Shock Vibration Variable Freq. Constant Acceleration Table 9 Mechanical and Environmental Test (16-bit microprocessor) Condition Device Type Sample Size Failure Ta= 295°C, 1000 hrs 42 0 Ta= -55°C, 1000 hrs 42 0 -55°C - 25°C - 150°C 10 cycles 189 0 -20°C - 25°C - 125°C 500 cycles 44 0 -55°C - 125°C 15 cycles 44 0 260°C, 10 sec 44 0 230°C, 5 sec 44 0 1500G, 0.5 msec 3 times/X, Y, Z 44 0 20 - 2000 Hz, 20G 3 times/X, Y, Z 44 0 20000G 1 min/X, Y, Z 44 0 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 21 RELIABILITY TEST DATA OF M I C R O C O M P U T E R - - - - - - - - - - - - - - - - - - - 4. PRECAUTION 4. 1· Storage It is preferable to store semiconductor devices in the following ways to prevent detrioration in their electrical characteristics, solderability, and appearance, or breakage. (1) Store in an ambient temperature of 5 to 30°C, and in a relative humidity of 40 to 60%. (2) Store in a clean air environment, free from dust and active gas. (3) Store in a container which does not induce static electric- ity. (4) Store without any physical load. (5) If semiconductor devices are stored for a long time, store them in the unfabricated form. If their lead wires are formed beforehand, bent parts may corrode during storage. (6) If the chips are unsealed, store them in a cool, dry, dark, and dustless place. Assemble them within 5 days after unpacking. Storage in nitrogen gas is desirable. they can be stored for 20 days or less in dry nitrogen gas with a dew point at -30°C or lower. Unpacked devices must not be stored for over 3 months. (7) Take care not to allow condensation during storage due to rapid temperature changes. 4.2 Transportation As with storage methods, general precautions for other electronic component parts are applicable to the trahsportation of semiconductors, semiconductor-incorporating units and other similar systems. In addition, the following considerations must be given, too: (1) Use containers or jigs which will not induce static electricity as the result of vibration during transportation. It is desirable to use an electrically conductive container or aluminium foil. (2) In order to prevent device breakage from clothes-induced siaiic eieciriciiy, workers shouitl be properiy grountletl wiih a resistor while handling devices. The resistor of about I M ohm must be provided near the worker to protect from electric shock. (3) When transporting the printed circuit boards on which semiconductor devices are mounted, ·suitable preventive measures against static electricity induction must be taken; for example, voltage built-up is prevented by shorting terminal circuit. When a belt conveyor is used, prevent the conveyor belt from being electrically charged by applying some surface treatment. (4) When transporting semiconductor devices or printed circuit boards, minimize mechanical vibration and shock. to apply surge voltage from the tester, to attach a clamping circuit to the tester, or not to apply any abnormal voltage through a bad contact from a current source. During measurement, avoid miswiring and short-circuiting. When inspecting a printed circuit board, make sure that no soldering bridge or foreign matter exists before turning on the power switch. Since these precautions depend upon the types of semiconductor devices, contact Hitachi for further details. 4.4 Soldering Semiconductor devices should not be left at high temperatures for a long time. Regardless of the soldering method, soldering must be done in a short time and at the lowest possible temperature. Soldering work must meet soldering heat test conditions, namely, 260°C for 10 seconds and 350°C for 3 seconds at a point 1 to 1.5 mm away from the end of the device package. Use of a strong alkali or acid flux may corrode the leads, deteriorating device characteristics. The recommended soldering iron is the type that is operated with a secondary voltage supplied by a ttansformer and grounded to protect from lead current. Solder the leads at the farthest point from the device package. 4.5 Removing Residual Flux To ensure the reliability of electronic systems, residual flux must be removed from circuit boards. Detergent or ultrasonic cleaning is usually applied. If chloric detergent is used for the plastic molded devices, package corrosion may occur. Since cleaning over extended periods or at high temperatures will cause swollen chip coating due to solvent permeation, select the type of detergent and cleaning condition carefully. Lotus Solvent and Oyfron Solvent are recommended as a detergent. Do not use any trichloroethylene solvent. For ultrasonic cleaning, the following conditions are advisable: · Frequency: 28 to 29 kHz (to avoid device resonation} · Ultrasonic output: l 5W/£ · Keep the devices out of direct contact with the power generator. · Cleaning time: Less than 30 seconds 4.3 Handling for Measurement Avoid static electricity, noise and surge-voltage when semiconductor devices are measured. It is possible to prevent breakage by shorting their terminal circuits to equalize electrical potential during transportation. However, when the devices are to be measured or mounted, their terminals are left open to provide the possibility that they may be accidentally touched by a worker, measuring instrument, work bench, soldering iron, belt conveyor, etc. The device will fail if it touches something which leaks current or has a static charge. Take care not to. allow curve tracers, synchroscopes, pulse generators, D.C. stabilizing power supply units etc. to leak current through their terminals or housings. Especially, while the devices are being tested, take care not @HITACHI 22 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 PROGRAM DEVELOPMENT AND SUPPORT SYSTEM · PROGRAM DEVELOPMENT AND SUPPORT SYSTEM OF 8-BIT/16-BIT MICROPROCESSOR H680SD200 is prepared as system development device to develop software and hardware of various types of microcomputer system. Fig. I shows the program development procedure using this system development device. H680SD200 loads a universal OS, CP/M-68K® developed jointly wjth Digital Research Inc. and operates with the existing CP/M". *CP/M®and CP/M-68K®are registered trademarks of Digital Rese8rch Inc. Error Assembler ~~~;~C~} (~S~~or) C Compiler for 6301(6303) and68000 Software Debug No In Case of H680SD200 Fig. 1 Program Development Procedure @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 23 PROGRAM DEVELOPMENT AND SUPPORT S Y S T E M - - - - - - - - - - - - - - - - - - Table 1 System Development Equipment SD200 MPU - - Product Name CP/M-68K VAX-11 Interface Program DATA 1/0 EPROM Programmer Interface Program PKW-1000/7000 EPROM Programmer Interface Program FORTRAN Product Code Function Note S680CPM3F · Single user Operating System. · 68000 Assembler, C compiler, Screen editor and Linker are included. S680CLC3F ·Interface Program between the SD200 and theVAX-11. · File transfer function. Option · VT52 Terminal Emulation. S680CDl1F · Interface Program between the SD200 and the DATA 1/0 EPROM Programmer model 22/29. S680CPK2F · Interface Program between the SD200 and the PKW-1000/7000 EPROM Programmer (Aval Corp. Japan) .. S680CFR1F · FORTRAN Compiler. (Subset of FORTRAN77) Option 16-bit MPU HD68000 Super PL/H Symbolic Debugger 64180ASE 8 bit 6305/63L05/6805 MPU/MCU Macro Assembler 6301/6801/6800 Macro Assembler 6301 C Compiler S680CPL1 F · Super PL/H Compiler. ·Symbolic Debugger for programs written in 68000 S680CSD2F Assembler or Super PL/H. S180CAS1F · Realtime In-circuit Emulator for 64180. · 6305Z(63L05/6805 Macro Assembler. S35XAS6-F · Linkage editor is included. S31XAS6-F · 6301/6801/6800 Macro Assembler. · Linkage editor is included. S31CCLN-F · C Compiler for 6301 (6303). Option Option Supplied with H180AS01 E Option Option Option @HITACHI 24 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - P R O G R A M DEVELOPMENT AND SUPPORT SYSTEM MPU Machine OS Table 2 Cross System Product Name Product Code ISIS-II 6305/63L05/6805 Assembler S35MDS1-F Intel MOS 8-bit MCU CP/M ISIS-II CP/M 6305/63L05/6805 Assembler S35MDS2-F 6301 Assembler S31MDS1-F 6301 Assembler S31MDS2-F IBM-PC PC-DOS 6301 Macro Assembler 6305 Macro Assembler S31 IAS1-F* S351AS1-F* Function 6305/63L05/6805 Assembler. Object code is absolute address format. Conditional assemble function. 6305/63 L05/6805 Assembler. Object code is absolute address format. Conditional assemble function. 6301 /6801 Assembler. Object code is absolute address format. Conditional Assemble function. 6301 /6801 Assembler. Object code is absolute address format. Conditional Assemble function. 6301 Macro Assembler. Linkage Editor is included. 6305 Macro Assembler. Linkage Editor is included. ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 25 PROGRAM DEVELOPMENT AND SUPPORT S Y S T E M - - - - - - - - - - - - - - - - - Table 3 Third Parties' Products Assemblers for HITAClil's microcomputen are provided by the other companies. Hitachi introduce some venders and their products listed below. Please contact those venden directly if you have questions or requests to purchase these products. Vender Name MICROTEC 505W Olive, Suite 325 Sunnyvale, CA94086 (408)733-2919 U.S.A. Product Name 6301 Assembler 6305 Assembler 6809 Assembler 68000 Assembler 64180 Assembler 64180 Simulator 64180 c 64180 Pascal 6301 Assembler 6305 Assembler 64180 Assembler 64180 c 64180 Pascal CAMELOT 79 London Road Knebworth Herts, SG3 6HG, England Stevenage (0438) 812215 AVOCET SYSTEMS, INC. 804 South State St. Dover, DE19901 (302) 734-0151 U.S.A. MICROWARE SYSTEMS CORPORA· TION 5835 Grand Avenue Dos Moines, IA50312 (512) 279-8844 U.S.A. 6301 Assembler 6305 Assembler 6800/6801 /6301 Assembler 6805 Assembler 6309/6809 Assembler 64180 Assembler 6309/6809 Assembler 68000/68HCOOO Assembler OS/System VAX11 IBM-PC IBM-PC CP/M MS-DOS, CP/M-86 CP/M MS-DOS, CP/M-86 CP/M MS-DOS, CP/M-86 CP/M MS-DOS, CP/M-86 OS-9 OS-9 Product Code ASM68 ASM05 ASM69 ASM68K ASM180 INT180 MCC180 PAS180 ASM68 ASM05 ASM180 MCC180 PAS180 . XASM-68 XASM-05 XASM-09 XASM-180 - KCRS *Under development $HITACHI 26 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - - - - - - - - - - - - - - - - - - P R O G R A M DEVELOPMENT AND SUPPORT SYSTEM · Development System for 4-Bit, 8-Bit, and 16-Bit Microcomputers <H680SD200> The H680SD200 is a development system for Hitachi 4-bit, 8-bit and 16-bit microcomputers. It is a desktop system in which a 16-bit microprocessor HD68000 is loaded as the CPU. Its standard system configuration includes a CRT, a keyboard, and two floppy disk drives. An assembler, compiler, and incircuit emulator (ASE) associated with the user's MCU are available as options. APPLICABLE DEVICES · HMCS400 series · HD6305U, HD6305V · HD6301V, HD6301X, HD6301Y · HD64180 · HD68000, HD68HCOOO (Other 4-bit and 8-bit microcomputers will be supported in the future.) · FEATURES · Adopts general CP/M-68K® operating system · Two internal 8 inch floppy disk drives (double-sided, double- density) and a 40M byte hard disk (available as an option) make it possible to provide substantial external memory. · Since CRT editor (screen editor) is included in the standard system, efficient programming, editing, and debugging of source programs are possible. · C compiler for HD68000 is included. FORTRAN and Super PL/H for H068000 and C Compiler for HD6301 (H06303) are available as options. · User prototype system can easily be debugged using incircuit emulator (ASE) associated with the user's MCU. · With connection of VAX-11® to RS-232C interface, H680SD200 operates as VAX-11® (OS, VMS) work station. · When 2M byte memory board is connected, high-speed operation can be realized. · Following interface are included (1) EPROM programmer (2) Printer (Centronics specification) (3) Serial interface emulator for 4-bit and 8-bit single chip microcomputers *CP/M® is a registered trade mark of Digital Research Inc. **VAX·11®is a registered trade mark of Digital Equipment Corp. H680SD200 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 27 HD64180 THIRD-PARTY DEVELOPMENT TOOLS Product: Cross-Assemblers and Cross-Compilers Company ASM SIW SIM C COMP PASCAL American Automation VII VII VII (714-731-1661) Microtec Research VII VII VII VII (408-733-2919) Avocet Systems Cll Cll (800-448-8500) 2500AD Software Cll (303-369-5001) BSO v v v v (617-894-7800) Sumitronics v (408-737-7683) SLR Systems c (800-833-3061) UniwarelSDS v (312-971-8170) Softaid (800-433-8812) Allen Ashley (818-793-5748) [l=IBM-PC, V=VAX, C=CPIM] BASIC c Product: Support Tools Company Product Description Electronic Molding (401-769-3800) Robinson Nugent (812-945-0211) Yamaiche/Nepenlhe ( 415-856-9332) Methode Electronics (312-392-3500) TSI, Inc (800-874-2288) Micromint (800-635-3355) Shrink-DIP Adapter for Breadboarding PIN 28764-72-341 Shrink-DIP Socket PIN TSS-6475-TNO Shrink-DIP Socket PIN IC 38-64075-04 S-D Test Socket PIN IC 76-64075-04 PLCC Adapter for Hitachi's ASE 64180 IBM-PC Card with DSD80 Remote Software Debugger 64180 Evaluation Board PIN SB180 Product: Operating Systems Company Type of Operating System Echelon (415-948-3820) JMI Software (215-628-0840) Oecmation (408-960-1678) Hunter & Ready (415-326-2950) IPI (516-938-6600) ZCPR3 (CPIM) C Executive/BO Multi-Tasking Kernel Quick-Task Realtime Executive VRTXIBO Multi-Tasking Kernel (Z80) MTOSIBO Multi-Tasking Kernel (ZBO) HITACHI ORDERING INFORMATION Part Number Description H180ASE02 H680SM01S H180ABX H180CP01 Adaptive System Evaluator, ASE-II 256K Byte Emulation Memory Board (Option) 8 MHz Buffer Box for ASE-I User, Includes V2.0 System Software PLCC-68 MPU Adapter for 1 Mbyte Addressing (Option) @HITACHI 28 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 DATA SHEETS NMOS 8-BIT MICROPROCESSOR ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 29 HD6802~~~~~~~~ MPU (Microprocessor with Clock and RAM) The HD6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present HD6800 plus an internal clock oscillator and driver on the same chip. In addition, the HD6802 has 128 bytes of RAM on the cWp located at hex addresses 0000 to 007F. The first 32 bytes of RAM, at hex addresses 0000 to 001 F, may be retained in alow power mode by utilizing Vcc standby, thus facilitating memory retention during a power-down situation. The HD6802 is completely software compatible with the HD6800 as well as the entire HMCS6800 family of parts. Hence, the HD6802 is expandable to 65k words. · FEATURES · On-Chip Clock Circuit · 128 x 8 Bit On-Chip RAM · 32 Bytes of RAM are Retainable · Software-Compatible with the H06800 · Expandable to 65k words · Standard TTL-Compatible Inputs and Outputs · 8 Bit Word Size · 16 Bit Memory Addressing · Interrupt Capability · Compatible with MC6802 · BLOCK DIAGRAM · PIN ARRANGEMENT 0 HD6802 Vee Vee Vee Standby Vee Vee Counter/ { Timer 1/0 "FIB -~{1/0 iRCi cs, E ~g~~o. RM TIMER 0 0 -0, VMA Clock R/W D0 -D, T1'fQ RE"§ HALT ;+; E Rfii HD6802 MPU 0 0 -0, RE iiiMi BA (Top View) AES EXT AL XTAL RE Vee Standby RiW o, o, o, o, D, o, o, o, A,. A,. A,, A,, Vss Control { A 0 -A10 cs, Ao-Au Vss @HITACHI 30 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee* Vee Standby* -0.3- +7.0 v Input Voltage Operating Temperature Storage Temperature Vin* Topr Tstu -0.3 - +7.0 v -20 - +75 oc -55 - +150 oc *With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · RECOMMENDED OPERATING CONDITIONS Item Supply Voltage Input Voltage Operation Temperature . Symbol min typ max Unit .Vee Vcc Standby* 4.75 . V1H V1L 1 Except RES RES -0.3 2.0 4.25 5.0 - 5.25 0.8 Vee Vee v v v v Topr -20 25 75 oc *With respect to Vss (SYSTEM GND) · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vcc=5.0V±5%, Vee Standby=5.0V±5%, Vss=OV, Ta=-20-+75°C, unless otherwise noted.) Input "High" Voltage Item Input "Low" Voltage Output "High" Voltage Output "Low" Voltage Three State (Off State) Input Current Input Leakage Current Power Dissipation Input Capacitance Output Capacitance Except RES RES Except RES RES Do-07, E Ao-Ais. R/W. VMA BA o.-o.,. Except 0 0 -D, **** Do-07 Except Do-07 Ao-A1s. R/W, BA, VMA, E Symbol ...V1H VIL VoH Vol ITSI .lin Po Gn C,,ut Test Condition loH = -205µA loH = -145µA loH = -100µA loL = 1.6mA V;n = 0.4-2.4V V;n = 0-5.25V V;n=OV, T0 =25°C, f=l.OMHz V1n=OV, T0 =25°C, 1=1.0MHz min typ** max Unit 2.0 4.25 - - Vee Vee v -0.3 -0.3 - 0.8 0.8 v 2.4 - - 2.4 - -v 2.4 - - - - 0.4 v -10 - 10 µA -2.5 - 2.5 µA - 0.6 1.2 w - 10 12.5 - pF 6.5 10 - - 12 pF · In power~down mode, maximum power dissipation is less than 42mW. · ·*·*ATs8 ·l2!!5il°!Cin,pVu«tf.a· s5 V histeresis character, applied voltage up to 2.4V is regarded as "Low" level when it goes up from OV. ****Does not include EXTAL and XTAL, which are crystal inputs. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 31 · AC CHARACTERISTICS (Vcc=5.0V±5%, Vee Standby=5.0V±5%, \fss=OV, Ta=-20-+75°C, unless otherwise noted.I 1. CLOCK TIMING CHARACTERISTICS. Item Frequency of Operation Cycle Time Clock Pulse Width Clock Fall Time 1Input Clock+ 4 JCrystal Frequency l "High" level l "Low" Level Symbol f fXTAL fcvc PW.pH PW.pL ~ Test Condition min 0.1 1.0 Fig. 2, Fig. 3 1.0 at 2.4V (Fig. 2, Fig. 3) 450 at O.BV (Fig. 2, Fig. 31 o.av - 2.4V(Fig.2,Fig.31 - typ max Unit - 1.0 - MHz 4.0 - 10 µs - 4500 ns - 25 ns 2. READ/WRITE TIMING Item Address Delay Peripheral Read Access Time Data Setup Time (Read) Input Data Hold Time Output Data Hold Time Address Hold Time (Address, R/W, VMA) Data Delay Time (Write) Bus Available Delay Processor Controls Processor Control Setup Time Processor Control Rise and Fall Time (Measured at O.BV and 2.0VI Symbol tAo tacc tosR tH tH tAH to ow taA tpcs tper tpef Test Condition min typ* max Fig. 2, Fig. 3, Fig. 6 - - 270 Fig. 2 530 - - Fig. 2 100 - - Fig. 2 10 - - Fig. 3 20 - - Fig. 2, Fig. 3 10 - - Fig.3 - - 225 Fig. 4, F'ig. 5, Fig. 7, Fig. 8 - - 250 Fig. 4-Fig. 7, Fig. 12 200 - - Fig. 4-Fig. 7, Fig. 12, Fig. 13, Fig. 16 - - 100 *Ta= 25°C, Vee = 5V 3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING Item RAM Enable Reset Time (11 RAM Enable Reset Time (2) Reset Release Time RAM Enable Reset Time (31 Memory Ready Setup Time Memory Ready Hold Time Symbol tRE1 tRE2 tLRES tRE3 tsMR tHMR Test Condition Fig. 13 Fig. 13 Fig. 12 Fig. 12 Fig. 16 Fig. 16 min typ max 150 - - E-3 cycles - - 20* - - 0 - - 300 - - 0 - 200 Unit ns ns ns ns ns ns ns ns ns ns Unit ns ms ns ns ns ·tAes · 20 msec min. for S type. 50 msec min. for R type. @HITACHI 32 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6802 5.0V c~ 130pF for D,-D,. E = 90pF for A0 -A 15 , R/W. and VMA ~ 30pF for BA R== 11knfor D 0 ,..,D 1 , E = 16kn for A0 ~A 15 .R/W. and VMA ~ 24kn for BA C includes stray Capacitance. All diodes are 152074 03" or equivalent. Figure 1 Bus Timing Test Load E RtW Address From MPU VMA Data From Memory or Peripherals ~ Data Not Valid Figure 2 Read Data from Memory or Peripherals E Address From MPU VMA Data From MPU M%?:a Data Not Valid Figure 3 Write Data in Memory or Peripherals @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 33 I· The Last Instruction Cycle + 0.4V HALT Cycle · 2.4V BA E HALT IPC, 2.4V Figure 4 Timing of HALTand BA HALT Cycle + Instruction Cycle 2.0V o.ev IPCS t .. BA UV Figure 5 Timing of HALT and BA MPU Reset MPU Restart Sequence ,------"°' 2.4V E 0.4V VMA 2.4V Figure 6 RES and MPU Restart Sequence @HITACHI 34 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 WAIT Cycle or The Last Instruction Cycle E IRQ, NMI 2.4V Interrupt Sequence M -- - - ~.,~·C!_'.'~"- -- -- -- - -- -- - - - -- - - -{,.., Figure 7 IRO and NMI Interrupt Timing The last execution cycle of WAI instruction (#9) WAIT Cycle 2.4V 2.4V BA Figure 8 WAI Instruction and BA Timing u MPU REGISTERS A general block diagram of the HD6802 is shown in Fig. 9. As shown; the number and configuration of the registers are the same as for the HD6800. The 128 x 8 bit RAM has been added to the basic MPU. The first 32 bytes may be operated in a low power mode via a Vcc standby. These 32 bytes can be retained during power-up and power-down conditions via the RE signal. The MPU has three 16-bit registers and three 8-bit registers available for use by the programmer (Fig. I0). · Program Counter (PC) The program counter is a two byte (16-bit) register that points to the current program address. · Stack Pointer (SP) The stack pointer is a two byte (16-bit) register that contains the address of the next available location in an external push-down/pop-up stack. This stack is normally a random access Read/Write memory that may have any location (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be non-volatile. · Index Register (IX) The index register is a two byte register that is used to store data or a sixteen bit memory address for the Indexed mode of memory addressing. · Accumulators IACCA, ACCB) The MPU contains two 8-bit accumulators that are used to hold operands and results from an arithmetic logic unit(ALU). · Condition Code Register (CCR) The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative(N), Zero(Z), Overflow(V), Carry from bit7(C), and half carry from bit3(H). These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit(!). The used bits of the Condition Code Register (B6 and B7) are ones. Fig. 11 shows the order of saving the microprocessor status within the stack. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 35 MR 3 E 37 lln40 NMi 6 HALT 2 mt!. EXTAL 39 XTAL 38 BA 7 VMA 5 R/\'V 34 .. .. Vee .. Pins 8,35 D, 2o7, o, 29 D, 3o0, 31 D, 3o2, 33 D., Vq · Pins 1,21 Figure9 Expanded Block Diagram 1 I ACCA I 0 Accumulator A 7 I ACCB 0 J Accumulator B 15 0 IX Index Register 15 I PC 1~ I I 0 Program Counter I 0 Stack Pointer Cerrv !From Bit 71 ,.,.Overflow Ne91nive Interrupt mask H·lf C.rry IFrom Bil 3) Figure 10 Programming Model of The Microprocessing Unit Sf'· lt9Ck Pointer CC· CondltiOn Cod9s IAtso ctlled,the Proceuor Status Bvte> ACCI · Accumulator 8 ACCA · Accumul9tor A IXH · lndmc Attit·r, Hither Order 8 lits ~~= =i:.--~;.~·~~its PCL · Praer-n Count9r, LOWlf Ordlf 8 lits m-2 m-1 m+1 m+2 m-9 m-8 m-7 SP m-6 m-5 ~~T m-4 m-3 m-2 m-1 II m+1 m+2 A l. . . Figure 11 Saving The Status of The Microprocessor in The Stack ~HITACHI 36 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · HD6802 MPU SIGNAL DESCRIPTION Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine the state of the processor. These control and timing signals for the HD6802 are similar to those of the HD6800 except that TSC, DBE, t/l 1 , t/l2 input, and two unused pins have been eliminated, and the following signal and timing lines have been added. RAM Enable (RE) Crystal Connections EXTAL and XTAL Memory Ready(MR) Vee Standby Enable t/l2 Output(E) The following is a summary of the HD6802 MPU signals: · Address Bus (A0 - A15 ) Sixteen pins are used for the address bus. The outputs are capable of driving one standard TTL load and 90pF. · Data Bus (D0 - 07) Eight pins are used for the data bus. It is bidirectional, transferring data to and from the memory and peripheral devices. It also has three-state output buffers capable of driving one standard TTL load and l 30pF. Data Bus will be in the output mode when the internal RAM is accessed. This prohibits external data entering the MPU. It should be noted that the internal RAM is fully decoded from $0000 to $007F. External RAM at $0000 to $007F must be disabled when internal RAM is accessed. e HALT When this input is in the "Low" state, all activity in the machine will be halted: This input is level sensitive. In the halt mode, the machine will stop at the end of an instruction. Bus Available will be at a "High" state. Valid Memory Address will be at a "Low" state. The address bus will display the address of the next instruction. To insure single instruction operation, transition of the HALT line must not occur during the last 250ns of E and the HALT line must go "High" for one Clock cycle. HALT should be tied "High" if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. · Read/Write (RJW) This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or Write ("Low") state. The normal standby state of this signal is Read ("High"). When the processor is halted, it will be in the logical one state ("High"). This output is capable of driving one standard TTL load and 90pF. · Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. This signal is not three-state. One standard TTL load and 90pF may be directly driven by this active high signal. · Bus Available {BA) The Bus Available signal will normally be in the "Low" state. When activated, it will go to the "High" state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the "Low" state or the processor is in the wait state as a result of the execution of a WAI instruction. At such time, all three-state output drivers will go to their off state and other outputs to their normally inactive level. The processor is removed from the wait state by the occurrence of a maskable (mask bit I=O) or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30pF. · Interrupt Request (IRQ) This level sensitive input requests that an interrupt sequence be generated within the machine. The processor will wait, until it completes the current instruction that is being executed before it recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the machine will begin an interrupt sequence. The index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that poin ts to a vectoring address which is located in memory locations FFF8 and FFF9. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. The HALT line must be in the "High" state for interrupts to be serviced. Interrupts will be latched internally while HALT is "Low". A 3k!l external register to Vee should be used for wire-OR and optimum control of interrupts. · Reset (RES) This input is used to reset and start the MPU from a power-down condition, resulting from a power failure or an initial start-up of the processor. When this line is "Low", the MPU is inactive and the information in the registers will be lost. If a "High" level is detected on the input, this will signal the MPU to begin the restart sequence. This will start execution of a routine to initialize the processor from its reset condition. All the higher order address lines will be forced "High". For the restart, the last two(FFFE, FFFF) locations in memory will be used to load the program that is addressed by the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the MPU can be interrupted by IRQ. Power-up and reset timing and power-down sequences are shown in Fig. 12 and Fig. 13 respectively. · Non-Maskable Interrupt (NMI) A low-going edge on this input requests that a non-mask- inter~sequence be generated within the processor. As with the IRQ signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask bit in the Condition Code Register has no effect on NM!. The Index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt routine in memory. A 3k!l external resistor to Vee should be used for wire-OR and optimum control of interrupts. Inputs IRQ and Nm are hardware interrupt lines that are sampled when E is "High" and will start the interrupt routine on a "Low" E following the completion of an instruction. IRQ and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. Fig. 14 is a flowchart describing the major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 37 Vee E 1--tpcs >4.25V ,,.--------s1-----:-:::::::-:;"'.:!l..-t------------l-__ - O.BV Option 1 (See Note below) Option 2 See Figure B for Power Down condition RE O.BV VMA (NOTE) If option 1 is chosen, RES and RE pins can be ti<!d together. Figure 12 Power-up and Reset Timing Vee E RE Figure 13 Power-down Sequence Figure 14 MPU Flow Chart @HITACHI 38 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 1 Memory Map for Interrupt Vectors Vector MS LS FFFE FFFF FFFC FFFD FFFA FFFB FFF8 FFF9 Description Restart (RES) Non-Maskable Interrupt (NMI) Software Interrupt (SWI) Interrupt Request ITROI · RAM Enable (REI A TIL-compatible RAM enable input controls the on-chip RAM of the HD6802. When placed in the "High" state, the on-chip memory is enabled to respond to the MPU controls. In the "Low" state, RAM is disabled. This pin may also be utilized to disable reading and writing the on-chip RAM during a power-down situation. RAM enable must be "Low" three cycles before Vee goes below 4.75V during power-down. RE should be tied to the correct "High" or "Low" state if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. · EXTAL and XTAL The HD6802 has an internal oscillator that may be crystal controlled. These connections are for a parallel resonant fundamental crystal (AT cut). A divide-by-four circuit has been added to the HD6802 so that a 4MHz crystal may be used in lieu of a lMHz crystal for a more cost-effective system. Pin39 of the HD6802 may be driven externally by a TTL input signal if a separate clock is required. Pin38 is to be left open in this mode. An RC network is not directly usable as a frequency source on pins 38 and 39. An RC network type TTL or CMOS oscillator will work well as long as the TIL or CMOS output drives the HD6802. If an external clock is used, it may not be halted for more than 4.Sµs. The HD6802 is a dynamic part except for the internal RAM, and requires the external clock to retain information. Conditions for Crystal (4 MHz) · AT Cut Parallel resonant · C0 = 7 pF max. · R 1 =SOU max. c. Crystal Equivalent Circuit C, = C, = 22pF ± 20% Figure 15 Crystal Oscillator When using the crystal, see the note for Board Design of the Oscillation Circuit in HD6802. · Memory Ready (MRI MR is a TIL compatible input control signal which allows stretching of E. When MR is "High", E will be in normal operation. When MR is "Low", E may be stretched integral multiples of half periods, thus allowing interface to slow memories. Memory Ready timing is shown in Fig. 16. MR should be ti!!d "High" if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. A maximum stretch is 4.Sµs. E MA Figure 16 Memory Ready Control Function @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 39 · Enable (E) This pin supplies the clock for the MPU and the rest of the system. This is a single phase, TTL compatible clock. This clock may be conditioned by a Memory Ready Signal. This is equivalent to ~2 on the HD6800. · Vee Standby This pin supplies the de voltage to the first 32 bytes of RAM as well as the RAM Enable (RE) control logic. Thus retention of data in this portion of the RAM on a power up, power-down; or standby condition is guaranteed at the range of 4.0 V to 5.25 V. Maximum current drain at 5.25V is 8mA. · MPU INSTRUCTION SET The HD6802 has a set of 72 different instructions. Included are binary and decimal arithmetic, logical, shift, rotate, load, store, conditional or unconditional branch, interrupt and stack manipulation instructions. This instruction set is the same as that for the 6800MPU(HD6800 etc.) and is not explained again in this data sheet. · NOTE FOR BOARD DESIGN OF THE OSCILLATION CIRCUIT IN HD6802 In designing the board, the following notes should be taken when the crystal oscillator is used. 0 HD6802 ------- Crystal oscillator and load capacity CL must be placed near ~ the LSI as much as possible. ~ 39 t---..---1, '*7 [Normal oscillation may be disturbed when external noise isJ induced to pin 38 and 39. 38 Pin 38 signal line should be wired apart from pin 37 signal line as much as possible. Don't wire them in parallel, or normal oscillation may be disturbed when E signal is feedbacked to XTAL. The following design must be avoided. Must be avoided ii/\ f.. \ 0 -t---;:--;------ I Signal C A signal line or a power source line must not cross or go near the oscillation circuit line as shown in the left figure to prevent 39 the induction from these lines and perform the correct oscillation. The resistance among XTAL, EXTAL and other pins 38 should be over !OMO. HD6802 Figure 17 Note for Board Design of the Oscillation Circuit @HITACHI 40 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6802 _..---Other signals are not wired in this area. ~ E E _l / / E E signal is wired apart from 38 pin and39pin. (Top View) Figure 18 Example of Board Design Using the Crystal Oscillator ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 41 ·NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6802 When HALT input signal is asserted to "Low" level, the MPU will be halted after the execution of the current instruction except WAI instruction. The "Halt" signal is not accepted after the fetch cycle of the WAI instruction (See © in Fig. 19). In the case of the "WAI" instruction, the MPU enters the "WAIT" cycle after stacking the internal registers and outputs the "High" level on the BA line. When an interrupt request signal is input to the MPU, the MPU accepts the interrupt regardless the "Halt" signal and releases the "WAIT" state and outputs the interrupt's vector address. If the "Halt" signal is "Low" level, the MPU halts after the fetch of new PC contents. The sequense is shown below. WAI E Address ""' RtW VMA 4 - - - +--------<~ BA CD When the interrupt occurs during the WAIT CYCLE, the MPU accepts the interrupt even if HALT is at "Low" level. Figure 19 HD6802 WAIT CYCLE & HALT Request @HITACHI 42 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6802W~~~~~~~ MPU (Microprocessor with Clock and RAM) HD6802W is the enhanced version of HD6802 which con- tains MPU, clock and 256 bytes RAM. Internal RAM has been extended from 128 to 256 bytes to increase the capacity of system read/write memory for handling temporary data and manipulating the stack. The internal RAM is located at hex addresses 0000 to OOFF. The first 32 bytes of RAM, at hex addresses 0000 to 001 F, may be retained in a low power mode by utilizing Vcc standby, thus facilitating memory retention during a power-down situation. The HD6802W is completely software compatible with the HD6800 as well as the entire HMCS6800 family of parts. Hence, the HD6802W is expandable to 65k words. HD6802WP (DP-40) · FEATURES · On-Chip Clock Circuit · 256 x 8 Bit On-Chip RAM · 32 Bytes. of RAM are Retainable · Software-Compatible with the HD6800, HD6802 · Expandable to 65k words · Standard TTL-Compatible Inputs and Outputs · 8 Bit Word Size · 16 Bit Memory Addressing · Interrupt Capability · BLOCK DIAGRAM Vee Vee Vee Standby Vee Counter/ { Timerl/O ms ~., { 1/0 iRo cs, E =~o,R/W TIMER o.-o, VMA Clock R/W o.-o, nm MR RES VMA "HAIT E RE R~D8802W jijMj (MPUI o.-o, BA · PIN ARRANGEMENT 0 RES EXT AL )(TAL E VMA NMI RE Vee s~b'V Rfii o, D, o, HD6802W o, o, o, o, o, A., Vee A,. A., A., A., --,_ _ _ _ _ ___.,....- Vss (Top View) I Control { A0 -A 15 Vss @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 43 A expanded block diagram of the HD6802W is shown in Fig. I. As shown, the number and configuration of the registers are the same as the HD6802 except that the internal RAM has been extended to 256 bytes. Output Buffer1 MR 3 E 37 1'lS 40 NMI 6 HALT 2 Tim 4 EXTAL 39 XTAL 38 BA 7 VMA 5 R/W 34 Progrom Counter H Stack Pointer H Index Register H 35 Vcc Standby 36 RAM Enable Data Buffer ALU 26 27 28 29 30 31 32 33 Vee. Pins 8,35 o, D, o, D, o, o, o, o, Vss · Pins 1,21 Figure 1 Expanded Block Diagram Address Map of RAM is shown is Fig. 2. The HD6802W has 256 bytes of RAM on the chip located at hex addresses 0000 to OOFF. The first 32 bytes of RAM, at hex addresses 0000 to 001 F, may be retained in a low power mode by utilizing Vcc standby and setting RAM Enable Signal "Low" level, thus facilitating memory retention during a power-down situation. 0000 } retention by V cc Standby 001F 0020 ------------- Figure 2 Address Map of H06802W @HITACHI 44 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ·ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee· Vcc Stand by· -0.3-+7.0 v Input Voltage Operating Temperature Storage Temperature Vin* Topr T·tv -0.3-+7.0 v -20-+75 oc -55-+150 oc ·With respect to Vss (SYSTEM GND) tNOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · RECOMMENDED OPERATING CONDITIONS Item Supply Voltage Input Voltage Operation Temperature Symbol Vee-.. . V~Standby* V1L 1 Except RES l VIH · RES Topr · With respect to Vss (SYSTEM GND) min 4.75 4.0 -0.3 2.0 Vee -0.75 -20 typ max Unit 5.0 5.25 v - 0.8 v - Vee Vee v 25 75 oc · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS 1Vcc=5.0V±5%, Vee Standby=5.0V±5%, Vss=OV, Ta=-20-+75°C, unless otherwise noted.) Input "High" Voltage Item Input "Low" Voltage Output "High" Voltage Output "Low" Voltage Three State (Off State) Input Current Input Leakage Current Power Dissipation Input Capacitance Output Capacitance Except RES RES Except RES RES Do-D7, E Ao-A1s. R/W, VMA BA D.-D.,. Except D0 -D7 Do-D7 Except D0 -D7 Ao-A1s. R/W, BA, VMA Symbol ..V1H V1L VoH VoL ...ITSI lin Po **** C.n C,,ut Test Condition loH = -205µA loH = -145µA loH = -lOOµA loL = 1.6mA V;0 = 0.4-2.4 V V;n = 0-5.25V V;0 =0V, T8 =25°C, f=l.OMHz V;0 =0V, T8 =25°C, f=l.OMHz min typ* max Unit 2.0 - - Vcc-0.75 Vee Vee v -0.3 -0.3 - 0.8 0.8 v 2.4 - - 2.4 - - v 2.4 - - - - 0.4 v -10 - 10 µA -2.5 - 2.5 µA - 0.7 1.2 w - 10 12.5 - pF 6.5 10 - - 12 pF · ·· TA0s=R25H° ei,nVpu~a=s5hVisteresis character, applied voltage up to 2.4V is regarded as ''Low" level when it goes up from OV. ···Does not include EXTAL and XTAL, which are crystal inputs. ···· In power-down mode, maximum power dissipation is less than 42mW. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 45 9 AC CHARACTERISTICS (Vee=5.0V±5%, Vee Standby=5.0V±5%, Vss=OV, Ta=-20-+75°C, unless otherwise noted.) 1. CLOCK TIMING CHARACTERISTICS Item Frequency of Operation Cycle Time Clock Pulse Width Clock Fall Time ~lock74 Frequency l "High" Level l "Low" Level Symbol f fxTAL \:ye PW</>H PW</>L tit> Test Condition min 0.1 1.0 Fig. 4, Fig. 5 1.0 at 2.4V(Fig. 4, Fig. 5) 450 at O.SV (Fig. 4, Fig. 5) O.SV - 2.4V(Fig.4,Fig.5) - typ max - 1.0 - 4.0 - 10 - 4500 - 25 Unit MHz µs ns ns 2. READ/WRITE TIMING Item Address Delay Peripheral Read Access Time Data Setup Time (Read) Input Data Hold Time Output Data Hold Time Address Hold Time (Address, R/W, VMA) Data Delay Time (Write) Bus Available Delay Processor Controls Processor Control Setup Time Processor Control Rise and Fall Time (Measured at O.SV and 2.0V) *Ta= 25°C, Vee= 5V Symbol Test Condition min typ* max Unit tAD Fig. 4, Fig. 5. Fig. 8 lace Fig. 4 - - 270 ns 530 - - ns tosR Fig. 4 100 - - ns tH Fig. 4 10 - - ns tH Fig. 5 20 - - ns tAH Fig. 4, Fig. 5 10 - - ns toow Fig. 5 - - 225 ns taA Fig. 6, Fig. 7, Fig. 9, Fig. 10 - - 250 ns tpcs Fig. 6 - Fig. 9, Fig. 11 200 - - ns lpcr, 1Pct Fig. 6 - Fig. 9, Fig. 11, Fig. 12, Fig. 14 - - 100 ns 3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING Item AAM Enable Reset Time (1) RAM Enable Reset Time (2) Reset Release Time RAM Enable Reset Time (3) Memory Ready Setup Time Memory Ready Hold Time Symbol tRE1 lRE2 lLRES tRE3 tsMR tHMR Test Condition Fig. 12 Fig. 12 Fig. 11 Fig. 11 Fig. 14 Fig. 14 min typ max 150 - - E-3 cycles - - 20 - - 0 - - 300 - - 0 - 200 Unit ns ms ns ns ns @HITACHI 46 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 5.0V C = 130pF for D,-D,. E = 90pF for A, -A,., R/W, and VMA = 30pF for BA R= 11kl1forD,-D,,E = 16k!l for A0 -A,~, R/W, and VMA = 24kl1 for BA C includes stray Capacitance. All diodes are 1S2074®or equivalent. Figure 3 Bus Timing Test Load E R/W Address From MPU VMA Data From Memory or Peripherals 2.0V ~ Data Not Valid O.BV Figure 4 Read Data from Memory or Peripherals E R/W Address From MPU VMA Data From MPU ~ Data Not Valid 2.4V 0.4V Data Valid Figure 5 Write Data in Memory or Peripherals @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 47 The Last Instruction Cycle 0.4V + HALT Cycle 2.4V BA 2.4V Figure 6 Timing of HALT and BA .,.+ HALT C,.yc_I_·_____ Instruction Cycle E HALT 2.0V o.av tpcs tPcr ---.......-----... BA 0.4V Figure 7 Timing of HALT and BA MPU Reset ,.------.......i 2.4V MPU Restart Sequence E 0.4V VMA 2.4V Figure 8 RES and MPU Restart Sequence @>HITACHI 48 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 WAIT Cycle or The Last Instruction Cycle 2.4V Interrupt Sequence IRQ, NMI -- - - - - - - ------ (When WAIT Cycle) -- -- -- - -- - - - - - - - - - -"\ \ BA 0.4V Figure 9 IRQ and NMI Interrupt Timing + The last execution cycle of WAI instruction(,#9_)_ _ _ _ _..., WAIT Cycle 2.4V 2.4V BA Figure 10 WAI Instruction and BA Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose. CA 95131 · (408) 435-8300 49 · H06802W MPU SIGNAL DESCRIPTION · Address Bus (A0 - A1s I Sixteen pins are used for the address bus. The outputs are capable of driving one standard TTL load and 90pF. · Data Bus (D0 - D1 I Eight pins are used (or the data bus. It is bidirectional, transferring data to and from the memory and peripheral devices. It also has three-state output buffers capable of driving one standard TTL load and 130pF. Data Bus will be in the output mode when the internal RAM is accessed. This prohibits external data entering the MPU. It should be noted that the internal RAM is fully decoded from $0000 to $00FF. External RAM at $0000 to $00FF must be disabled when internal RAM is accessed. · HALT When this input is in the "Low" state, all activity in the machine will be halted: This input is level sensitive. In the halt mode, the machine will stop at the end of an instruction. Bus Available will be at a "High" state. Valid Memory Address will be at a "Low" state. The address bus will display the address of the next instruction. To insure single instruction operation, transition of the HALT line must not occur during the last tPCs of E and the HALT line must go "High" for one Clock cycle. HALT should be tied "High" if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. · Read/Write (R/WI This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read ("High") or Write ("Low'') state. The normal standby state of this signal is Read ("High"). When the processor is halted, it will be in the logical one state ("High"). This output is capable of driving one standard TTL load and 90pF. · Valid Memory Address (VMAI This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. This signal is not three-state. One standard TTL load and 90pF may be directly driven by this active high signal. · Bus Available (BAI The Bus Available signal will normally be in the "Low" state. When activated, it will go to the "High" state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the "Low" state or the processor is in the wait state as a result of the execution of a WAI instruction. At such time, all three-state output drivers will go to their off state and other outputs to their normally inactive level. The processor is removed from the wait state by the occurrence of a maskable (mask bit I=O) or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30pF. · Interrupt Request (I R0) This level sensitive input requests that an interrupt sequence be generated within the machine. The processor will wait, until it completes the current instruction that is being executed before it recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the machine will begin an interrupt sequence. The index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit address will be Joade<I that points to a vectoring address which is located in memory locations FFF8 and FFF9. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. The HALT line must be in the "High" state for interrupts to be serviced. Interrupts will be latched internally while HALT is "Low". A 3k!2 external register to Vee should be used for wire-OR and optimum control of interrupts. · Reset (RES) This input is used to reset and start the MPU from a power-down condition, resulting from a power failure or an initial start-up of the processor. When this line is "Low", the MPU is inactive and the information in the registers will be lost. If a "High" level is detected on the input, this will signal the MPU to begin the restart sequence. This will start execution of a routine to ipitialize the processor from its reset condition. All the higher order address lines will be forced "High". For the restart, the last two(FFFE, FFFF) locations in memory will be used to Joa<! the program that is addressed by the program counter. During the restart routine, the interrupt mask bit is set and mµst be reset before the MPU can be interrupted by IRQ. Power-up and reset timing and power-down sequences are shown in Fig. 11 and Fig. 12 respectively. · Non-Mask11ble Interrupt (NMI) A Jow-gouig edge on this input requests that a non-mask- inter~sequence be generated within the processor. As with the IRQ signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask bit in the Condition Code Register has no effect on NMI. The Index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt routine in memory. A 3kQ external resistor to Vcc should be used for wire-OR and optimum control of interrupts. Inputs IRQ and 1ilMI are hardware interrupt lines that are sampled when E is "High" and will start the interrupt routine on a "Low" E following the completion of an instruction. lRQ and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. Fig. 13 is a flowchart describing the major decision paths and interrupt vectors of the microprocessor. Table I gives the memory map for interrupt vectors. ~HITACHI 50 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Vee E 1--tpes >Vcc-0.75V .r----------iJ----.,,....,,.--:!1..-T------------l--- - O.BV Option 1 (See Note below) RE 0.8':_ ~~~~~~~~~ VMA 2.ov tpcr O.BV (NOTE} If option 1 is chosen, RES and RE pins can be tied together. Figure 11 Power-up and Reset Timing Option 2 See Figure 12 for Power Down condition Vee E RE Figure 12 Power-down Sequence Figure 13 MPU Flow Chart @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 51 Table 1 Memory Map for Interrupt Vectors Vector MS LS FFFE FFFF FFFC FFFD FFFA FFFB FFFS FFF9 Description Restart (RES) Non-Maskable Interrupt (NMI) Software Interrupt (SWI) Interrupt Request (IRO) · RAM Enable (RE) A TTL-compatible RAM enable input controls the on-chip RAM of the HD6802W. When placed in the "High" state, the on-chip memory is enabled to respond to the MPU controls. In the "Low" state, RAM is disabled. This pin may also be utilized to disable reading and writing the on-chip RAM during a power-down situation. RAM enable must be "Low" three cycles before Yee goes below 4.75V during power-down. RE should be tied to the correct "High" or "Low" state if not used. This is good engineering design practice in general and necessary to insure proper operation of the part. · EXTAL and XTAL The HD6802W has an internal oscillator that may be crystal controlled. These connections are for a parallel resonant fundamental crystal (AT cut). A divide-by-four circuit has been added to the HD6802W so that a 4MHz crystal may be used in lieu of a !MHz crystal for a more cost-effective system. Pin39 of the HD6802W may be driven externally by a TTL input signal if a separate clock is required. Pin38 is to be· left open in this mode. An RC network is not directly usable as a frequency source on pins 38 and 39. An RC network type TTL or CMOS oscillator will work well as long as the TTL or CMOS output drives the HD6802W. If an external clock is used, it may not be halted for more than 4.Sµs. The HD6802W is a dynamic part except for the internal RAM, and requires the external clock to retain information. Conditions for Crystal (4 MHz) · AT Cut Parallel resonant · C0 = 7 pF max. · R1 = 80Sl max. c. Crystal Equivalent Circuit :I. c, C, = C, = 22pF ±.20% When using the crystal, see the note for Board Design of the Oscillation Circuit in HD6802W. · Memory Ready (MR) MR is a TTL compatible input control signal which allows stretching of E. When MR is "High", E will be in normal operation. When MR is "Low", E may be stretched mtegral multiples of half periods, thus allowing interface to slow memories. Memory Ready timing is shown in Fig. 14. MR should be tied "High" if not used. This is. good engineering design practice in general and necessary to insure proper operation of the part. A maximum stretch is 4.5.µs. E MR Figure 14 Memory Ready Control Function @HITACHI 52 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · Enable (E) This pin supplies the clock for the MPU and the rest of the system. This is a single phase, TTL compatible clock. This clock may be conditioned by a Memory Ready Signal. This is equivalent to <f>2 on the HD6800. · Vee Standby This pin snpplies the de voltage to the first 32 bytes of RAM as well as the RAM Enable (RE) control logic. Thus retention of data in this portion of the RAM on a power-up, power-down, or standby condition is guaranteed at the range of 4.0 V to 5.25 V. Maximum current drain at 5.25V is 8mA. · MPU INSTRUCTION SET The HD6802W has a set of 72 different instructions. Included are binary and decimal arithmetic, logical, shift, rotate, load, store, conditional or unconditional branch, interrupt and stack manipulation instructions. This instruction set is the same as that for the 6800MPU (HD6800 etc.) and is not explained again in this data sheet. · NOTE FOR BOARD DESIGN OF THE OSCILLATION CIRCUIT IN HD6802W In designing the board, the following notes should be taken when the crystal oscillator is used. 0 HD6802W --------- Crystal oscillator and load capacity CL must be placed near --------- the LSI as much as possible. ~ m, 39 1----...---i, ---- 38 ....... ~ [Normal oscillation may be disturbed when external noise is] induced to pin 38 and 39. -------------- Pin 38 signal line should be wired apart from pin 37 signal line as much as possible. Don't wire them in parallel, or normal oscillation may be disturbed when E signal is feedbacked to XTAL. The following design must be avoided. Must be avoided ii,/\ 00 00 \ 0 -+-----:---;------- Signal C A signal line or a power source line must not cross or go near the oscillation circuit line as shown in the left figure to prevent 39 the induction from these lines and perform the correct oscillation. The resistance among XTAL, EXTAL and other pins 38 should be over lOMn. HD6802W Figure 15 Note for Board Design of the Oscillation Circuit @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 53 HD6802W-------------------------------- HD6802W .,.----other signals are not wired in this area. i E _J / / E E si9nal is wired apart from 38 pin and39pin. (Top View) Figure 16 Example of Board Design Using the Crystal Oscillator @HITACHI 54 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6802W When HALT input signal is asserted to "Low" level, the MPU will be halted after the execution of the current instruction except WAI instruction. The "Halt" signal is not accepted after the fetch cycle of the WAI instruction (See CD in Fig. 17). In the case of the "WAf' instruction, the MPU enters the "WAIT" cycle after stacking the internal registers and outputs the "High" level on the BA line. When an interrupt request signal is input to the MPU, the MPU accepts the interrupt regardless the "Halt" signal and releases the "WAIT" state and outputs the interrupt's vector address. If the "Halt" signal is "Low" level, the MPU halts after the fetch of new PC contents. The sequense is shown below. WAI Address Bu· Rfii VMA - r - - - - - - - - - 1 IROor tpcs liiMI ~--- BA © Hill When the interrupt occurs during the WAIT CYCLE, the MPU accepu the interrupt even if HALT is at "Low" level. Figure 17 HD6802W WAIT CYCLE & HAIT Request @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 55 HD6803, HD6803-1---- MPU (Micro Processing Unit) The HD6803 MPU is an 8-bit micro processing unit which is compatible with the HMCS6800 family of parts. The HD6803 MPU is object code compatible with the HD6800 with improved execution times of key instructions plus several new 16-bit and 8-bit instruction including an 8 x 8 unsigned multiply with 16-bit result. The HD6803 MPU can be expanded to 65k bytes. The HD6803 MPU is TTL compatible and requires one +0.5 volt power supply. The HD6803 MPU has 128 bytes of RAM, Serial Communications Interface (S.C.I.), and parallel 1/0 as well as a three function 16-bit timer. Features and Block Diagram of the HD6803 include the following: · FEATURES · Expanded HMCS6800 Instruction Set · 8 x 8 Multiply · On-Chip Serial Communications Interface (S.C.I.) · Object Code Compatible with The HD6800 MPU · 16-Bit Timer · Expandable to 65k Bytes · Multiplexed Address and Data · 128 Bytes of RAM (64 Bytes Retainable On Power Down) · 13 Parallel 1/0 Lines · Internal Clock/Divided-By-Four · TTL Compatible Inputs and Outputs · Interrupt Capability · Compatible with MC6803 and MC6803-1 HD6803P HD6803P-1 (DP-40) · PIN ARRANGEMENT 0 IRO, 5 RES Vee PJO P,, P,, P,. P,, HD6803 · BLOCK DIAGRAM P,, P,, P,. P,, P., AS RMi D_olAo D1/A1 0 2 /A 2 03/A3 0 4 tA 4 Os/A:. 06/Ab 01/A7 A, A, A,, A,, A,, Au A,. Au Vee Standby BDo/A, ,;A, 1/A2 BQ,/A, ·/A· 1/A1 Do/Ao D·/A· R;W AS -.-.--p. ,....o-++-·P,. Mto-t+--r+r-_-...P. pu,, ,.._.................. p,. (Top View) Ao A, A,. A,, A., A,, A,. A,. Vee Standby · TYPE OF PRODUCTS Type No. Bus Timing HD6803 1.0MHz HD6803·1 1.25MHz @HITACHI 56 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol ..Vee Vin Topr T..., Value Unit -0.3-+7.0 v -0.3-+7.0 v 0 -+70 ·c -55-+150 ·c · With respect to Vss !SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee ·5.0V±5%, Vss · OV, Ta· 0-+70°C, unless otherwise noted.I Item Input "High" Voltage m Other Inputs· Symbol V1H Test Condition min typ 4.0 - 2.0 - Input "Low" Voltage All Inputs· VIL -0.3 - Input Load Current EXTAL ll;nl v,n = O-Vee - - Input Leakage Current NMI, IR01, RES l!m.J '{m_ = 0 - 5.25V - - Three State (Offset) Pio- P11. Do/A0- D1IA1 -- Leakage Current P20 - P2· llTsil V,n = 0.5 - 2.4V - - Do/Ao - D1IA1 l LOAD = -205 µA 2.4 - Output "High" Voltage As - ~IS, E, R/W, AS VoH ILOAD = -145µA 2.4 - Other Outputs ILOAD = -10QµA 2.4 - Output "Low" Voltage All Outputs VoL ILOAD = 1.6 mA - - Darlington Drive Current Pio - P11 -loH Vout = 1.5V 1.0 - Power Dissipation Po -- Input Capacitance Do/Ao - D1IA1 Other Inputs - V;n = OV, Ta= 25°C, - Cin f=1.0MHz -- Vee Standby Power down Operating Vsee Vse 4.0 - - 4.75 Standby Current Power down lsee V599 = 4.0V - - ·Except Mode Programming Levels. max Vee Vee 0.8 0.8 2.5 10 100 - - 0.5 10.0 1200 12.5 10.0 5.25 5.25 8.0 Unit v v mA _E_A µA v v mA mW pF v mA @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 57 · AC CHARACTERISTICS BUS TIMING IVcc · 5.0V ± 5%, Vss · OV, T1 · O- +70°C, unless otherwise noted.I Item Symbol Cycle Time Address Strobe Pulse Width "High" · Address Strobe Rise Time Address Strobe Fall Time Address Strobe Delay Time · Enable Rise Time Enable Fall Time Enable Pulse Width "High" Time · Enable Pulse Width "low" Time · Address Strobe to Enable Delay Time · Address Delay Time Address Delay Time for latch · Data Set-up Write Time Data Set-up Read Time lf Data Hold Time Read Write Address Set-up Time for latch · Address Hold Time for latch Address Hold Time Peripheral Read Access Time (Multiplexed Busl* Oscillator stabilization Time Processor Control Set-up Time tcvc PW ASH tAsr tASf tASo ter te1 PWeH PWeL tASED lAD tADL tosw tosR tHR tHW tASL tAHL tAH (tAccMI tRC tpcs Test Condi· ti on HD6803 min typ max HD6803-1 Unit min typ max 1 - 10 0.8 - 10 µs 200 - - 150 - - ns 5 - 50 5 - 50 ns 5 - 50 5 - 50 ns 60 - - 30 - - ns 5 - 50 5 - 50 ns 5 - 50 5 - 50 ns 450 - - 340 - - ns 450 - - 350 - - ns Fig. 1 60 - - 30 - - ns - - 260 - - 260 ns - - 270 - - 260 ns 225 - - 115 - - ns 80 - - 70 - - ns 10 - - 10 - - 20 - - 20 - - ns 60 - - 50 - - ns 20 - - 20 - - ns 20 - -- - 20 - - (600} - - ns (420) ns Fig. 8 100 - - 100 - - ms Fig. 7,8 200 - - 200 - - ns *These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum (=in the highest speed operation). PE~IPHERAl PORT TIMING (Vee· 5.0V ± 5%, Vss · OV, Ta· 0 - +70°C, unless otherwise noted.I Item Peripheral Data Setup Time Peripheral Data Hold Time Delay Time, Enable Negative Transition to Peripheral Data Valid *Except P21 Port 1, 2 Port 1, 2 Port 1, 2* Symbol Test Condition min typ max Unit tposu Fig. 2 200 - - ns tPDH Fig. 2 200 - - ns tpwo Fig. 3 - - 400 ns ®HITACHI 58 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 TIMER, SCI TIMING (Vee= 5.0V ±5%, Vss = OV, Te· 0 - +70°C, unless otherwise noted.I Item Timer Input Pulse Width Delay Time, Enable Positive Transition to Timer Out SC I Input Clock Cycle SCI Input Clock Pulse Width Symbol tpwT tToo tScyc tPW...§£.K Test Condition min typ 2tcyc+200 - Fig.4 - - 1 - 0.4 - max Unit - ns 600 ns - love 0.6 tScvc MODE PROGRAMMING (Vee= 5.0V ±5%, Vss = OV, Ta· 0 - +70°C, unless otherwise noted.I Item Symbol Test Condition min typ Mode Programming Input "Low" Voltage VMPL - - Mode Programming Input "High" Voltage VMPH 4.0 - RES "Low" Pulse Width Mode Programming Set-up Time Mode Programming 1ffi Rise Time~ 1µs Hold Time j ffi Rise Time < 1µs PWRSTL tMPS tMPH Fig. 5 3.0 - 2.0 - 0 - 100 - max Unit 1.7 v -v - tcvc - tcyc - - ns Address Strobe IASI i--~~~~~~~~~~t.,..~~~~~~~~~~~-ot 2.2V PW ASH 0.6V Enable IEI 2.4V 0.5V tAo- ter Address Vahd MPUWrite Do/A,, -0;/A; !Pou 3) 2 2V Address Vahd 06V ·et ,..., MPU Read Du/Ao -07/A; (Port 3) Figure 1 Expanded Multiplexed Bus Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 59 Enable (El r-MPURead o.sv2.4V Figure 2 Data Set-up and Hold Times (MPU Read) r MPUWrote Enable (E) o.sv1='·wox/ All Oat: ""2"".2="'v"."""---. Port O u t p u t s Q . 6 V Data Vahd *Not applicable to P21 Figure 3 Port Data Delay Timing (MPU Write) Enable (E) Timer Counter P,. Output Figure 4 1TOD~ 2.2V !"o.'e-v-----Timer Output Timing Figure 5 Mode Programming Timing viTHI Point AL ·2.2k0 ~- 1S2074 iii' or EQu·v R C = 90pF for D0/A0 - 07/A7, As -A15 , E, AS, R/W R 12 kn for Do/Ao - D 7/A 7, As - A 15 , E, AS, R/W 24 kn for P10 ...... P17, P20 - P14 TTL Load Figure 6 Bus Timing Test Load @HITACHI 60 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 -1 L·t IM..uctN>n Enable IEI lntet"nal AddreuB~-"--;""'"--1''~~-,:!'~.,,...,'°"-::::,,...,."'-,,,,,.-::''~,,,-~""',,....,~"""",.....,,J'""""""'""'"""-='""',...,""..,.,_.,....,,,.,,,...,__,"°"......,,,,J~~ IRO, lntern·'""'\r--y--y--......,.,--,,---v--v----..,---.r---v---v--'V"---v--v--""""\r---v-- D·t· Bui..l't---"---"0o""""c'"-_,'"o-.-c.-.-".""PC"'o-""PC~7'\,PC8"""'-"'PC,.,.15~X-O-_X_7,,,.,X'°'B'"-"'x1"·"-A"'c"c""A~-.-. cc-.-''"""=J\-..-..J~-"""'v'"oct"'0<_,,....,..;.-11.'"."..'."·-- LSB Interrupt Rou1in9 lnternel Rfii * i'RCfi ; Internal mterrupt Figure 7 Interrupt Sequence ~No1Valid Figure 8 Reset Timing Instruction · SIGNAL DESCRIPTIONS · Vee and Vss These two pins are used to supply power and ground to the chip. The voltage supplied will be +5 volts ±5%. · XTAL and EXTAL These connections are for a parallel resonant fundamental crystal, AT cut. Devide-by-4 circuitry is included with the internal clock, so a 4 MHz crystal may be used to run the system at 1 MHz. The devide-by-4 circuitry allows for use of the inexpensive 3.58 MHz Color 1V crystal for non-time critical applications. Two 22pF capacitors are needed from the two crystal pins to ground to insure reliable operation. An example of the crystal interface is shown in Fig. 9. EXTAL may be driven by an external TTL compatible source with a 45% to 55% duty cycle. It will devided by 4 any frequency less than or equal to 5 MHz. XTAL must be grounded if an external clock is used. Nominal Cry~tal Parameter ~I m Co Rs 4 MHz 5 MHz 7pF max. 4.7pF max. 6011 max. 3011 typ, XTAL1---<11~--..., CJ EXTAL 1---<ll.._, Cu = CL2 = 22pF ± 20% (3.2 - 5 MHz) (NOTE] AT cut parallel resonance parameters tL21-CL1 Figure 9 Crystal Interface @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 61 · Vee Standby This pin will supply +S volts ±5% to the standby RAM on the chip. The first 64 bytes of RAM will be maintained in the power down mode with 8 mA current max. The circuit of figure 13 can be utilized to assure that Vcc Standby does not go below Vsee during power down. To retain information in the RAM during power down the following procedure is necessary: I) Write "O" into the RAM enable bit, RAME. RAME is bit 6 of the RAM Control Register at location $0014. This disables the standby RAM, thereby protecting it at power down. 2) Keep Vee Standby greater than Vsse. Vee Standby i P o w e r l i n e Figure 10 Battery Backup for Vee Standby · ReMt(RESI This input is used to reset and start the MPU from a power down condition, resulting from a power failure or an initial startup of the processor. On power up, the reset must be held "Low" for at least I 00 ms. When reset during operation, RES must be held "Low" at least 3 clock cycles. When a "High" level is detected, the CPU does the following; 1) All the higher order address lines will be forced "High". 2) I/O Port 2 bits, 2, I, and 0 are latched into programmed control bits PC2, PC l and PCO. 3) The last two ($FFFE, $FFFF) locations in memory will be used to load the program addressed by the program counter. 4) The interrupt mask bit is set. Clear before the CPU can recognize maskable interrupts. · Enable CEI This supplies the external clock for the rest of the system when the internal oscillator is used. It is a single phase, TTL compatible clock, and will be the divide-by-4 result of the crystal oscillator frequency. It will drive one TTL load and 90 pF capacitance. · Non-Maskable Interrupt (NMI) When the falling edge of the input signal is detected at this pin, the CPU begins non-maskable interrupt sequence internally. As with interrupt Request signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask bit in the Condition Code Register has no effect on lilMI. In response to an NMI interrupt, the Index Register, Program Counter, Accumulators, and Condition Code Register are stored on the stack. At the end of the sequence, a 16-bit address will be loaded that points to a vectoring address located in memory locations SFFFC and SFFFD. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt service routine in memory. A 3.3 kQ external resistor to Vee should be used for wire-OR and optimum control of interrupts. Inputs JIU), and NM! are hardware interrupt lines that are sampled during E and will start the interrupt routine on the E following the completion of an instruction. · Interrupt Request (IRQ1 ) This level sensitive input requests that an interrupt sequence be generated within the machine. The processor will complete the current instruction before it recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators, and Condition Code Register are stored on the stack. Next the CPU will respond to the interrupt request by setting the interrupt mask bit "High" so that no further maskable interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations $FFF8 and $FFF9. An address loaded at these locations causes the CPU to branch to an interrupt routine in memory. The IRQ 1 requires a 3.3 kQ external resistor to Vee which should be used for wire-OR and optimum control of inte~ts. Internal Interrupts will use an internal interrupt line (IRQ2 ). This interrupt will operate the same as IRQ 1 except that it will use the vector address of $FFFO through $FFF7. IRQ 1 will have priority to IRQ2 if both occur at the same time. The Interrupt Mask Bit in the condition code register masks both interrupts (See Table I). Highest Priority Lowest Priority Table 1 Interrupt Vector Location Vector MSB LSB FFFE FFFF FFFC FFFD FFFA FFFB FFF8 FFF9 FFF6 FFF7 FFF4 FFF5 FFF2 FFF3 FFFO FFF1 Interrupt ~ NMI Software Interrupt (SWO fRO"", ICF (Input Capture) OCF (Output Compare) TOF (Timer Overflow) SCI (ROAF+ ORFE +TORE) · Read/Write (RiWI This TTL compatible output signals the peripherals and memory devices whether the CPU is in a Read ("High") or a Write ("Low") state. The normal standby state of this signal is Read ("High"). This output can drive one TTL load and 90pF capacitance. · Address Strobe (AS) In the expanded multiplexed mode of operation, address strobe is output on this pin. This signal is used to latch the 8 LSB's of address which are multiplexed with data on D0 / A0 to D, IA7 · An 8-bit latch is utilized in conjunction with Address Strobe, as shown in figure 11. So D0 /Ao to D7 / A7 can become data bus during the E pulse. The timing for this signal is shown in Figure I of Bus Timing. This signal is also used to disable the address from the multiplexed bus allowing a deselect time, tASD before the data is enabled to the bus. · PORTS There are two 1/0 ports on the HD6803 MPU; one 8-bit port and one 5-bit port. Each port has an associated write @HITACHI 62 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 only Data Direction Register which allows each I/O line to be progranuned to act as an input or an output·. A "I" in the corresponding Data Direction Register bit will cause that 1/0 line to be an output. A "O" in the corresponding Data Direction Register bit will cause that I/O line to be an input. There are two ports: Port I, Port 2. Their addresses and the addresses of their Data Direction registers are given in Table 2. * The only exception is bit 1 of Port 2, which can either be data input or Timer output. Table 2 Port and Data Direction Register Addresses Ports 1/0 Port 1 1/0 Port 2 Port Address $0002 $0003 Data Direction Register Address $0000 $0001 · 1/0 Port 1 This is an 8-bit port whose individual bits may be defined as inputs or outputs by the corresponding bit in its data direction register. The 8 output buffers have three-state capability, allowing them to enter a high impedance state when the peripheral data lines are used as inputs. In order to be read properly, the voltage on the input lines must be greater than 2.0 V for a logic" I" and less than 0.8 V for a logic "O". As outputs, these lines are TTL compatible and may also be used as a source of up to 1 mA at l .S V to directly drive a Darlington base. After reset, the I/O lines are configured as inputs. · 1/0 Port 2 This port has five lines that may be defined as inputs or outputs by its data direction register. The 5 output buffers have three-state capability, allowing them to enter a high impedance state when used as an input. In order to be read properly, the voltage on the input lines must be greater than 2.0 V for a logic "I" and less than 0.8 V for a logic "0". As outputs, this port has no internal pullup resistors but will drive TTL inputs directly. For driving CMOS inputs, external pullup resistors are required. After reset, the 1/0 lines are configured as inputs. Three pins on Port 2 (pin 8, 9 and I 0 of the chip) are requested to set following values (Table 3) during reset. The values of above three pins during reset are latched into the three MSBs (Bit 5, 6 and 7) of Port 2 which are read only. Port 2 can be configured as 1/0 and provides access to the Serial Communications Interface and the Timer. Bit I is the only pin restricted to data input or Timer output. Table 3 The Values of three pins Pin Number 8 9 10 Value L H L [NOTES) L; Logical ''O" H; Logical "1" · BUS · Data/Address Lines (Do/Ao -D1/A1) Since the data bus is multiplexed with the lower order address bus in Data/Address, latches are required to latch those address bits. The 74LS373 Transparent Octal D-type latch can be used with the HD6803 to latch the least significant address byte. Figure 11 shows how to connect the latch to the HD6803. The output control to the 74LS373 may be connected to ground. · Address Lines (As - A1s) Each line is TTL compatible and can drive one TTL load and 90 pF. After reset, these pins become output for upper order address lines (As to Ats). GND · INTERRUPT FLOWCHART The Interrupt flowchart is depicted in Figure 16 and is com- AS l D, G OCa, 74LS373 lA~'"'mon to every interrupt excluding reset. ·,-A, Function Table l'· o, a, o,-o .... - Output Control L L L H Enable G D H H H L L x x x Output a H L a. z Figure 11 Latch Connection @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 63 HD6803 · MEMORY MAP The MPU can provide up to 6Sk byte address space. A memory map is shown in Figure 12. The first 32 locations are reserved for the MPU's internal register area, as shown in Table 4 with exceptions as indicated. Table 4 Internal Register Area Register Port 1 Data Direction Register·* Port 2 Data Direction Register** Port 1 Data Register Port 2 Data Register Not Used Not Used Not Used Not Used Timer Control and Status Register Counter (High Byte) Counter (Low Byte) Output Compare Register (High Byte) Output Compare Register (Law Byte) Input Capture Register (High Byte) Input Capture Register I Low Bytel Not Used Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register RAM Control Register Reserved · External Address ·· 1; Output, O; Input Address 00 01 02 03 04* 05* 06* 07* 08 09 OA OB oc OD OE OF* 10 11 12 13 14 15-lF Internal Registers External Memory Space Internal RAM External Memory Space · PROGRAMMABLE TIMER The HD6803 contains an on-chip 16-bit programmable timer which may be used to measure an input waveform while independently generating an output waveform. Pulse widths for both input and output signals may vary from a few microseconds to many seconds. The timer hardware consists of an 8-bit control and status register, a 16-bit free running counter, a 16-bit output compare register, a 16-bit input capture register A block diagram of the timer registers is shown in Figure 13. · Free Running Counter ($0009:$000A) The key element in the programmable timer is a 16-bit free running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at any time. The counter is cleared to zero by reset and may be considered a read-only register with one exception. Any CPU write to the counter's address ($09) will always result in preset value of $FFF8 being loaded into the counter regardless of the value involved in the write. This preset figure is intended for testing operation of the part, but may be of value in some applications. · Output Compare Register ($0008:$000CI The Output Compare Register is a 16-bit read/write register which is used to control an output waveform. The contents of this register are constantly compared with the current value of the free running counter. When a match is found, a flag is set (OCF) in the Timer Control and Status Register (TCSR) and the current value of the Output Level bit (OLVL) in the TCSR is clocked to the Output Level Register. Providing the Data Direction Register for Port 2, Bit 1 contains a "I" (Output), the output level register valiie will appear on the pin for Port 2 Bit I. The values in the Output Compare Register and Output Level bit may then be changed to control the output level on the next compare value. The Output Compare Register is set to $FFFF during reset. The Compare function is inhibited for one cycle following a write to the high byte of the Output Compare Register to insure a valid 16-bit value is in the register before a compare is made. · Input Capture Register ($0000:$000EI The Input Capture Register is a 16-bit read-only register used to store the current value of the free running counter when the proper transition of an external input signal occurs. The input transition change required to trigger the counter transfer is controlled by the input Edge bit (IEDG) in the TCSR. The Data Direction Register bit for Port 2 Bit 0, should· be clear (zero) in order to gate in the external input signal to the' edge detect unit in the timer. The input pulse width must be at least two E-cycles to ensure an input capture under all conditions. · With Port 2 Bit 0 configured as an output and set to ·· 1'', the external input will still be seen by the edge detect unit. l S F F F O l - - - - - 4 \ $FFFF.__ _ __. External Interrupt Vectors (NOTE) Excludes the following addresses which may be used externally: $04, $05, $06, $07,and $OF. Figure 12 HD6803 Memory Map @HITACHI 64 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Bot 1 Pori 2 DOR Output Input Levrl Edgr 81t 1 811 0 Pott 2 Pon 2 Figure 13 Block Diagram of Programmable Timer Timer Control and Status Register I I I I I I I 6 5 4 3 2 1 0 ICF OCF TOF EICI EOCI ET01 1EOG OLVLI $0008 · Timer Control ·nd Status Register (TCSRI ($00081 The Timer Control and Status Register consists of an 8-bit register of which all 8 bits are readable but only the low order 5 bits may be written. The upper three bits contain read-only timer status information and indicate the followings: · a proper transition has taken place on the input pin with a 'subsequent transfer of the current counter value to the input capture register. · a match has been found between the value in the free rUMing counter and the output compare register, and when $0000 is in the free running counter. Each of the flags may be enabled onto the HD6803 internal bus (IRQ2 ) with an individual Enable bit in the TCSR. If the I-bit in the HD6803 Condition Code register has been cleared, a prior vectored interrupt will occur corresponding to the flag bit(s) set. A description for each bit follows: Bit 0 OLVL Output Level - This value is clocked to the output level register on a successful output comp.are. If the DOR for Port 2 bit 1 is set. the value will appear on the output pin. Bit I IEDG Input Edge - This bit controls which transition of an input will trigger a transfer of the counter to the input capture register. The DOR for Port 2 Bit 0 must be clear for this function to operate. IEDG = 0 Transfer takes place on a negative edge ('"High"-10-··Low" transition). IEDG = I Transfer takes place on a positive edge ("Low"-to-"High" transition). Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this bit enables IRQ2 to occur on the internal bus for a TOF interrupt; when clear the interrupt is in· hibited. Bit 3 EOCI Enable Output Compare Interrupt - When set, this bit enables 1RQ2 to appear on the internal bus for an output compare interrupt; when clear the interrupt is inhibited. Bit 4 EICI Enable input Capture Interrupt - When set, this bit enables 1RQ2 to occur on the internal bus for an input capture interrupt: when clear the interrupt is inhibited. Bit 5 TOF Timer Overflow Flag - This read-only bit is set when the counter contains $FFFF. It is cleared by a read of the TCSR (with TOF set) followed by an CPU read of the Counter ($09). Bit 6 OCF Output Compare Flag - This read-only bit is set when a match is found between the output compare register and the free running counter. It is cleared by a read of the TCSR (with OCF set) followed by an CPU write to the output compare register (SOB or SOC). Bit 7 !CF Input Capture Flag - This read-only status bit is set by a proper transition on the input; it is cleared by a read of the TCSR (with ICF set) followed by an CPU read of the Input Capture Register ($00). @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 65 · SERIAL COMMUNICATIONS INTERFACE The HD6803 contains a full-duplex asynchronous serial communications interface (SCI) on chip. The controller comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same data rate. Both transmitter and receiver communicate with the CPU via the data bus ani! with the outside world via pins 2, 3, and 4 of Port 2. The hardware, software, and registers are ex· plained in the following paragraphs. · Wak·Up Future In a typical multi-processor application, the software protocol will usually contain a destination address in the initial byte(s) of the message. In order to permit non-selected MPU's to ignore the remainder of the message, a wake-up feature is included whereby all further interrupt processing may be optionally inhibited until the beginning of the next message. When the next message appears, the hardware re-enables (or "wakes-up") for the next mes5age. The "wake-up" is automatically triggered by a string of ten consecutive I's which indicates an idle transmit line. The software protocol must provide for the short idle period between any two consecutive messages. · Programmable Options The following features of the HD6803 serial 1/0 section are programmable: · format - standard mark/space (NRZ) · Clock - external or internal · baud rate - one of 4 per given CPU l/>2 clock frequency or external clock x8 input · wake-up feature - enabled or disabled · Interrupt requests - enabled or masked individually for transmitter and receiver data registers · clock output - internal clock enabled or disabled to Port 2 (Bit 2) ·Port 2 (bits 3 and 4) - dedicated or not dedicated to serial 1/0 individually for transmitter and receiver. · Serial Communications Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 14. The registers include: · an 8-bit control and status register ·a 4-bit rate and mode control register (write only) · an 8-bit read only receive data register and · an 8-bit write only transmit data register. In addition to the four registers, the serial 1/0 section utilizes bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of Port 2 is utilized if the internal-clock-out or external-clock-in options are selected. Transmit/Receive Control and Status (TRCSI Register TI1e TRCS register consists of an 8-bit register of which all 8 bits may be read while only bits 0-4 may be written. The register 1s initialized to $20 by reset. The bits in the TRCS register are defined as follows: IBit 7 R..e and MOde Control Repitter Bit 0 l=l~l~l~lm Tr·nsmit/Receive Control and Status Register $12 """ 2 :i~ ...-'-'--.. !Not Addressable) Receive Shift Register 3 '-------....--------' ----E Tx ·Bit 12 Transmit Shift Register S13 Transmit Data Register Figure 14 Serial 1/0 Registers Bit 0 WU Bit I TE Bit 2 TIE Bit 3 RE Bit 4 RIE "Wake-up" on Next Message - set by HD6803 software and cleared by hardware on receipt of ten consecutive I's or reset of RE flag. II should be noted that RE flag should be set in advance of CPU set of WU flag. Transmit Enable - set by HD6803 to produce preamble of nine consecutive J's and to enable gating of transmitter output to Port 2, bit 4 regardless of the DOR value corresponding to this bit; when clear, serial 1/0 has no effect on Port 2 bit 4. TE set should be after at least one bit time of data transmit rate from the set-up of transmit data rate and mode. Transmit Interrupt Enable - when set, will pennit an IRQ2 interrupt to occur when bit 5 (TORE) is set; when clear, the TORE value is masked from the bus. Receiver Enable - when set, gates Port 2 bit 3 to input of receiver regardless of DOR value for this bit: when clear, serial 1/0 has no effect on Port 2 bit 3. Receiver Interrupt Enable - when set, wiU permit an IRQ2 interrupt to occur when bit 7 (RDRF) or bit 6 (ORFE) is set: when clear, the interrupt is masked. Transmit/Receive Control and Status Register 7 .6 . 5 . 4 3 2 1 0 @HITACHI 66 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Bit 5 TORE Transmit Data Register Empty - set by hardware when a transfer is made from the transmit data register to the output shift register. The TDRE bit is cleared by reading the status register. then writing a new byte into the transmit data register, TDRE is initialized to I by reset. Bit 6 ORFE Over-Run-Framing Error - set by hardware when an overrun or framing error occurs (receive only). Rate and Mode Control Register x 6 x I I I I 5 4 3 2 0 x x CCI cco 551 550 ADDA : $0010 An overrun is defined as a new byte received with last byte still in Data Register/Buffer. A framing error has occured when the byte boundaries in bit stream are not synchronized to bit counter. If WU-flag is set, the ORFE bit will not be set. The ORFE bit is cleard by reading the status register, then reading the Receive Data Register. or by reset. Bit 7 RDRF Receiver Data Register Full-set by hardware when a transfer from the input shift register to the receiver data register is made. lfWU-flag is set, the RDRF bit will not be set. The RDRF bit is cleared by reading the status register, then reading the Receive Data Register, or by reset. Rate and Mode Control Register (RMCR) The Rate and Mode Control register controls the following serial 1/0 variables: ·Baud rate ·format ·clocking source, ·Port '.! bit '.! configuration The register consists of 4 bits all of which are write-only and cleared by reset. The 4 bits in the register may be considered as a pair of 2-bit fields. The two low order bits control the bit rate for Internal clocking and the remaining twq bits control the format and clock select logic. The register definition is as follows: Bit 0 SSO} Speed Select - These bits select the Baud rate for Bit 1 SS1 the internal clock. The four rates which may be selected are a function of the CPU lfi2 clock frequency. Table 5 lists the available Baud rates. Bit 2 CCO} Clock Control and Format Select - this 2-bit field Bit 3 CC1 controls the format and clock select logic. Table 6 defines the bit field. Table 5 SCI Bit Times and Rates SSl : SSO 0 0 0 1 1 0 1 1 · HD6803·1 Only XTAL E E o- 16 E o- 128 E 7 1024 E o- 4096 2.4576 MHz 614.4 kHz 26 µs/3B.400 Baud 208 µs/4 ,800 Saud 1.67 ms/600 Baud 6.67 ms/150 Baud 4.0 MHz 1.0MHz 16 µs/62,500 Baud 128 µs/7812.5 Baud 1.024 ms/976.6 Baud 4.096 ms/244.1 Baud Table 6 SCI Format and Clock Source Control 4.9152 MHz" 1.2288 MHz 13.0 µs/76,800 Baud 104.2 µs/9,600 Baud 833.3 µs/1,200 Baud 3.33 ms/300 Baud CCl: CCO 0 0 0 1 1 0 1 1 Format NRZ NRZ NRZ Clock Source Internal Internal External Port 2 Bit 2 - Not Used Output· Input Port 2 Bit 3 ...-... Clock output is available regardless of values for bits RE and TE. Bit 3 is used for serial input if RE= "1" in TRCS; bit 4 is used for serial output if TE= "1" in TRCS. Port 2 Bit 4 ...-... Internally Generated Clock If the user wishes for the serial 1/0 to furnish a clock. the following requirements are applicable: ·the values of RE and TE are immaterial. ·CC l. CCO must be set to I0 ·the maximum clock rate will be E .;- 16. · the clock will be at Ix the hit rate and will have a rising edge at mid-bit. Externally Generated Clock If the user wishes to provide an external clock for the serial 1/0, the following requirements are applicable: ·the CC I, CCO, field in the Rate and Mode Control Register must be set to 11 , ·the external clock must be set to 8 times (X8) the desired baud rate and ·the maximum external clock frequency is 1.0 MHz. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 67 · Serial Operations The serial 1/0 hardware should be initialized by the HD6803 software prior to operation. This sequence will normally consist of; · writing the desired operation control bits to the Rate and Mode Control Register and ·writing the desired operational control .bits in the Transmit/ Receive Control and Status Register. The Transmitter Enable (TE) and Receiver Enable (RE) bits may be left set for dedicated operations. Transmit Operations The transmit operation is enabled by the TE bit in the Transmit/Receive Control and Status Register. This bit when set, gates the output of the serial transmit shift register to Port 2 Bit 4 and takes unconditional control over the Data Direction Register value for Port 2, Bit 4. Following a RES the user should configure both the Rate and Mode Control Register and the Transmit/Receive Control and Status Register for desired operation. Setting the TE bit during this procedure initiates the serial output by first transmitting a nine-bit preamble of I's. Following the preamble, internal synchronization is established and the transmitter section is ready for operation. At this point one of two situation exist: I) if the Transmit Data Register is empty (TORE = I), a continuous string of ones will be sent indicating an idle line, or, 2) if data has been loaded into the Transmit Data Register (TORE = 0), the word is transferred to the output shift register and transmission of the data word will begin. During the data transmit, the 0 start bit is first transmitted. Then the 8 data bits (beginning with bit 0) followed by the stop bit, are transmitted. When the Transmitter Data Register has been emptied, the hardware sets the TORE flag bit. If the H06803 fails to respond to the flag within the proper time, (TORE is still set when the next nornrnl transfer from the parallel data register to the serial output register should occur) then a I will be sent (insteaq of a 0) at "Start" bit time. followed by more I's until more data is supplied to the data re~ister. No O's will be sent while TORE remains a I. Receive Operation The .receive operation is enabled by the RE bit which gates in the serial input through Port 2. Bit 3. The receiver section operation is conditioned by the contents of the Transmit/ Receive Control and Status Register and the Rate and Mode Control Register. The receiver bit interval is divided into 8 sub-intervals for internal synchronization. In the NRZ Mode. the received bit stream is synchronized by the first 0 (space) encountered. The approximate center of each bit time is strobed during the next I0 bits. If the tenth bit is not a I (stop bit) a framing error is assumed, and bit ORFE is set. If the tenth bit as a I. the data is transferred to the Receive Data Register. and interrupt flag RDRF is set. If RORF is still set at the next tenth bit time. ORFE will be set. indicating an overrun has occurred. When the H06803 responds to either flag (RDRF or ORFE) by reading the status register followed by reading the Data Register. RORF (or ORFE) will be cleared. it at power d?wn if Vee Standby is held greater than v 588 volts, as explained prevmusly tn the signal description for Vcc Standby. 1. I _sp_~_e $00141.. R_v_..l_R_A_M_.:.. M_x_eo-1.r_·o_~_R_·ILgi._._:_·....._x_IL_x_.1..._x_. Bit 0 Not used. Bit I Not used. Bit 2 Not used. Bit 3 Not used. Bit 4 Not used. Bit 5 Not used. Bit 6 RAME The RAM Enable control bit allows the user the ability to disable the standby RAM. This bit is set to a logic ·· 1·· by RES which enables the standby RAM and can be written to one or zero under program control. When the RAM is disabled. data is read from external memory. Bit 7 STBY The Standby Power bit is cleared when the standPWR by voltage is removed. This bit is a read/write status flag that the user can read which indicates that the standby RAM voltage has been applied. and the data in the standby RAM is valid. · GENERAL DESCRIPTION OF INSTRUCTION SET The HD6803 is upward object code compatible with the HD6800 as it implements the full HMC'S6800 instruction set. The execution times of key instructions have been reduced to increase throughout. In addition. new instructions have been added; these include 16-bit operations and a hardware multiply. Included in the instruction set section are the following: · CPU Programming Model-Figure 15. · Addressing modes ·Accumulator and memory instructions - Table 7 · New instructions ·Index register and stack manipulations instructions - Table 8 · Jump and branch instructions - Table 9 ·Condition code register manipulation instructions -Table IO · Instructions Execution times in machine cycles - Table II · Summary of cycle by cycle operation - Table 12 · Summary of undefined instructions - Table 13 · CPU Programming Model The programming model for the H06803 is shown in Figure 15. The double (D) accumulator is physically the same as the Accumulator A concatenated with the Accumulator B so that any operation using accumulator D will destroy information in A and B. · RAM CONTROL REGISTER . _This register. which is addressed at $0014. gives status mlormation about the standby RAM. A 0 in the RAM enable bit (RAME) will disable the standby RAM, thereby protecting @HITACHI 68 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · CPU Addressing Modes 8·811 Accumulators A and 8 The HD6803 8-bit micro processing unit has seven address Or 16-811 Double Accumulator 0 modes that can be used by a programmer, with the addressing ,,. x oj lnduReg1ster()() mode a function of both the type of instruction and the coding within the instruction. A summary of the addressing modes for ,,. SP oj Stack Pointer ISP! a particular instruction can be found in Table 11 along with the associated instruction execution time that is given in machine cycles. With a clock frequency of 4 MHz, these times would be 11· PC oj Program Counter !PC) microseconds. Accumulator (ACCXI Addressing In accumulator only addressing, either accumulator A or Cond1t1on Code Register CCCRI accumulator B is specified. These are one-byte instructions. Immediate Addressing Carry/Borrow from MSB Overflow Zero Negittve In immediate addressing, the operand is contained in the second byte of the instruction except LOS and LOX which have the operand in the second and third bytes of the instruction. Interrupt Half Carry \From Bit 31 The CPU addresses this location when it fetches the immediate instruction for execution. These are two or three-byte instruc- Figure 15 CPU Programming Model tions. @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 69 Table 7 Accumulator & Memory Instructions Addressing Modes Operations Add Mnemonic ADDA IMMED. - DP # SB 2 2 DIRECT - DP # 9B 3 2 INDEX EXTEND " - - OP OP # AB 4 2 BB 4 3 IMPLIED - OP # Boolean/ Arithmetic Operation A+M-A ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-B Add Double ADDO CJ 4 3 03 5 2 E3 6 2 F3 6 3 A:B+M:M+l ··A: B Add Accumulators ABA lB 2 1 A+ B-A Add With Carry ADCA S9 2 2 99 3 2 A9 4 2 89 4 3 A+M+C-A AND ADCB ANDA - C9 2 2 09 3 2 E9 4 2 F9 4 3 84 2 2 94 3 2 A4 4 2 84 4 3 B+M+C-B A·M-A ANDB C4 2 2 04 3 2 E4 4 2 F4 4 3 B·M-B Bit Test BIT A 85 2 2 9S 3 2 AS 4 2 BS 4 3 A·M BIT B cs 2 2 DS 3 2 ES 4 2 FS 4 3 B·M Clear CLR 6F 6 2 7F 6 3 00- M CLRA 4F 2 1 oo-A CLRB SF 2 1 00-B Compare CMPA 81 2 2 91 J 2 At 4 2 Bl 4 3 A-M CMPB Cl 2 2 01 3 2 El 4 2 Fl 4 3 B-M Compare Accumulators CBA 11 2 1 A-B Complement, l's COM 63 6 2 73 6 J M-M COMA 43 2 1 A -A COMB 53 2 1 B -B Complement, 2's NEG 60 6 2 70 6 3 00-M-M (Negate) NEGA 40 2 1 00-A-A NEGB so 2 1 00-B-B Decimal Ad1ust. A DAA Converts binary add of BCD 19 2 1 characters into BCD format Decrement DEC 6A 6 2 7A 6 3 M-1 -M DECA 4A 2 1 A-1 -A DECB SA 2 1 B - 1 -· B Exclusive OR EORA EORB 88 2 2 98 3 2 AS 4 2 BS 4 3 ca 2 2 08 3 2 ea 4 2 F8 4 3 A(i) M - A B M-· B Increment INC INCA , 6C 6 2 7C 6 3 4C 2 M + 1 -M A+ 1 -A INCB SC 2 1 B + 1 · B Load Accumulator LDAA LDAB 86 2 2 96 3 2 A6 4 2 B6 4 3 C6 2 2 06 3 2 E6 4 2 F6 4 3 M -·A M -B Load Double Accumulator LOO cc J 3 DC 4 2 EC s 2 FC s 3 M + 1 - 8. M ·A Multiply Unsigned OR, Inclusive MUL ORAA 30 10 1 Ax B ··A :B SA 2 2 9A 3 2 AA 4 2 BA 4 3 A+M-A ORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B + M- B Push Data PSHA 36 3 1 A - Msp, SP - 1 ·SP PSHB 37 3 1 B - Msp, SP - 1 ·SP Pull Data PULA 32 4 1 SP + 1 - SP, Msp ·· A PULB 33 4 1 SP + 1 - SP, Msp - B Rotate Left ROL ROLA ROLB 69 6 2 79 6 3 49 2 1 ~)~!111!! I f:l S9 2 1 B C b7 bO Rotate Right ROA RORA RORB c:o:uiiiiiiJJ ~I 66 6 2 76 6 3 46 2 1 B j C b7 bO S6 2 1 Th~ Cond1t1on Code Register notes are listed after Table 10. Condition Code Regisu~r 54 3 2 10 H INzvc . ! I I I I . I I I II ..I I I I · I I I I I . I I I I I . I I I I I .· · I I R . . . I I R . . . I I R . . . I I R ..R s R R ..R s R R .· R s R R ..I I I I .. I I I I ..I I I I ..I I R s .· I I R s ··I I Rs .· I I <DlI@ . . I I <D@ .· I I <D@ . . I I I~ · · I .· I . . I . . · I . . . I .· I .· I . . I . . · I . . · I I @· I @. I @· I R I R I @· I ®. I ®· I R I A . . · I I R . . . . . 0 . . · I ; R . . . ; I A ....... · · · · · . . · · · · . . . . . · ..I I @ I . . I .· I .· I . . ; I (i) I I @I 1@ I ; @I ..: I @ ; @HITACHI 70 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 7 Accumulator & Memory Instructions (Continued) Addressing Modes Operations Shift Left ArithmP.tic Mnemonic ASL ASLA ASL8 IMMED. DIRECr INDEX EXTEND - - - - " " OP OP " OP OP " 68 6 2 78 6 3 Oouhle Shift Left, Arithrn~tic ASLD Shih Riqht ArithmP.tic Shift Right Loqir.al ASA ASRA ASRIJ LSR LSRA LSRB 67 6 2 77 6 3 64 6 2 74 6 3 Double Shift Right Logical LSRD Store Accumulator STAA ST"'8 97 3 2 A7 4 2 B7 4 3 D7 3 2 E7 4 2 F7 4 3 Store Double Accumulator 5T{) DD 4 2 ED 5 2 FD 5 3 Subtract SUBA SUB6 80 2 2 90 3 2 AO 4 2 BO 4 3 co 2 2 DO 3 2 EO 4 2 FO 4 3 Double Subtract SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 Subtract Arcumulators SBA Subtract With Carry SBC.A SBCB 82 2 2 92 3 2 A2 4 2 B2 4 3 C2 2 2 D2 3 2 E2 4 2 F2 4 3 Transfer Accu·mulators TAB TBA Test Zero or Minus TST TSTA 6D 6 2 70 6 3 TSTB The Cond1t1on Corle R~1ster notes are listed after Table 10. IMPLIED - OP " Boolean/ Arithmetic Operation 48 2 1 M: l ~ ~ o - 58 2 1 05 3 1 ~ Aee AJ x~e a 1-0 A7 AO 87 Bf} =~ 47 2 1 Ml 57 2 1 -- 44 2 1 MAl O-+j-llllllll--9 8 b7 bO 54 2 1 04 3 1 o-ol -----+ ACC A/ ACCB ~ A7 AO 87 BO A- M 8-M A-M B _... M + 1 A-M-A 8 -M-B A: B-M: M+1-A: B 10 2 1 A-B-A A-M-C-A B -M-C-B 16 2 1 A-B 17 2 1 B- A M-00 4D 2 1 A -00 5D 2 1 B - 00 Condition Code Register 54 32 10 H INzvc · · I I @I . · I I ~,1 . · I I ~I .· I I KIDI I .· I I @1 · · I 1@1 · · I l~I . . R l~I . · R 1@1 ..R I @ I .· R I ® I .· · I I R · · · I I R .· · I I R · ·I I I I ··I I I I .· · I I I I ·I I I I ··I I I I ··I I I I .· I I R · . . · I I R ·· I I RR .· I I R R ..I I R R Direct Addressing In direct addrrssing. the address of the operand is contained in the second bvte of the instruction. Direct addressing allows the user to dire~tly address the lowest 256 bytes in the machine i.e., locations zero through :?55. Enhanced execution times are achieved by storing data in these locations. In most configura· tions, it should be a random access memory. These are two-byte instructions. E><tdnded Addressing In extended addressing. the address contained in the second. hvte of ·he instruction i; used as the higher 8-bits of the address of the operand. The third byte of the lnstruction is used as the lower 8-hits of the address for the operand. This is an absolute >ddress in memory. These are three-byte instructions. Indexed Addressing In indexed addressing. the address contained in the second hyte of the instruction °is added to the index register's lowest 8-bits in the CPU. The carry is then added to the higher order 8-bits of the index register. This result is then used to address memory. The modified address is held in a temporary address register so there is no change to the index register. These are two-byte instructions. Implied Addressing In the implied addressing mode the instruction gives the address (i.e., stack pointer, index register, etc.). These are one-byte instructions. Relative Addressing In relative addressing, the address contained in the second byte of the instruction is added to the program counter's lowest 8-bits plus two. The carry or borrow is then added to the high 8-bits. This allows the user to address data within a range of -1~6 to +129 bytes of the present instruction. These are twobyte instructions. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 71 · New Instructions In addition to the existing 6800 Instruction Set, the following new instructions are incorporated in the H06803 Microcomputer. ABX ADDO ASLD LOO LSRD MUL PSHX PULX STD SUBD BRN CPX Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account the possible carry out of the low order byte of the X-Register. Adds the double precision ACCO* to the double precision value M:M+l and places the results in ACCO. Shifts all bits of ACCO one place to the left. Bit 0 is loaded with zero. The C bit is loaded from the most significant bit of ACCO. Loads the contents of double precision memory locauon into the double accumulator A:B. The condition codes are set according to the data. Shifts all bits of ACCO one place to the right. Bit 15 is loaded with zero. The C bit is loaded from the least significant bit to ACCO. Multiplies the 8 bits in accumulator A with the 8 bits in accumulator l:l to obtain a 16-bit unsigned number in A:B, ACCA contains MSB of result. The contents of the index register is pushed onto the stack at the address contained in the stack pointer. The stack pointer is decremented by 2. The index register is pulled from the stack beginning at the current address contained in the stack pointer +1.. The stack pointer is incremented by 2 in total. Stores the contents pf double accumulator A:B in memory. The contents of ACCO remain unchanged. Subtracts the contents of M:M + 1 from the contents of double accumulator AB and places the result in ACCO. Never branches. If effect, this instruction can be considered a two byte NOP (No operation) requiring three cycles for execution. Internal processing modified to permit its use with any conditional branch instruction. *ACCD"is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A·accumum lator is the most significant byte. Table 8 Index Register and Stack Manipulation Instructions Pointer Operations Mnemonic Compare Index Reg Decrement Index Reg Decrement Stack Pnt r Increment Index Reg Increment Stack Pntr Load Index Reg load Stack Pntr Store Index Reg Store Stack Pntr Index Reg - Stack Pntr Stack Pntr-+ Index Reg Add Push Data CPX DEX DES INX INS LDX LDS STX STS TXS TSX ABX PSHX Pull Data PULX -IMMED. OP # BC 4 3 Addressing Modes - " - - DIRECT INDEX EXTND OP OP # OP # 9C 5 2 AC 6 2 BC 6 3 IMPLIED - OP # Boolean/ Arithmetic Operation X-M M + 1 09 3 1 X-1-X 34 3 1 SP-1-SP 08 3 1 x + 1- x 31 3 1 SP+1-SP CE 3 3 DE 4 2 EE 5 2 FE 5 3 M- XH 0 IM+11- XL BE 3 3 9E 4 2 AE 5 2 BE 5 3 M-SPH. (M+11-SPL DF 4 2 EF 5 2 FF 5 3 xH-M.xL-(M+1) 9F 4 2 AF 5 2 BF 5 3 SPH - 'Ill. SPL - IM+ 11 35 3 1 X - 1- SP 30 3 1 SP+ 1- X 3A 3 1 B + x- X JC 4 1 xL-MsP.SP-1-sP XH - M,p. SP - 1 - SP 38 5 1 SP+ 1-sP,M,p-xH SP+1-SP.M..,-XL Cond1t1on Code Register 5 4 3 2 10 H INzvc .· I I l I . . · · t · . . .· · · . . . . · t .. . · · · . ·a:. · · ;Q_ I R·e · t R . · 0) I R · . . . 7 I R .. .. · · . .· · · · . .. .. · .. ... · . .·r · · The Condition Code Register notes are listed after Table 10. @HITACHI 72 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 9 Jump and Branch Instructions Operations Mnemonic Branch Always Branch Never Branch If Carry Clear Branch If Carry Set Branch If "' Zero Branch If > Zero Branch If > Zero Branch If Higher Branch If c;;_ Zero Branch If Lower Or Same Branch If < Zero Branch If Minus Branch If Not Equal Zero Branch If Overflow Clear Branch If Overflow Set Branch If Plus Branch To Subroutine Jump Jump To Subroutine BRA BAN BCC BCS BEO BGE BGT BHI BLE BLS BLT BMI BNE eve BVS BPL BSA JMP JSR Addressing Modes - RELATIVE OP # 20 3 2 21 3 2 24 3 2 25 3 2 27 3 2 2C 3 2 2E 3 2 22 3 2 2F 3 2 - " - DIRECT INDEX OP OP # - EXTND OP # - IMPLIED OP # 23 3 2 20 3 2 28 3 2 26 3 2 28 3 2 29 3 2 2A 3 2 SD 6 2 6E 3 2 7E 3 3 90 5 2 AD 6 2 BO 6 3 No Operation NOP 01 2 1 Return From Interrupt Return From Subroutine Software Interrupt Wait for Interrupt RTI ATS SWI WAI 38 10 1 39 5 1 3F 12 1 3E 9 1 Branch Test None None C=O C·1 Z·1 N(±)V·O Z + (N (±)VI· 0 C+Z=O Z + (N (±)VI· 1 c +z - 1 N(±)V·1 N·1 z-o v-o v- 1 N·O Advances Prag. Cntr. Onlv Condition Code Register 54 32 10 H INz v c . · · · · · . · · · · · . . · · · · · · · · · · .. .. · · . . . · · · . . .· · · .... · · . . .· · · .... · · ... ... . . · · · · . . . · · · . . · · · · . . · · · · . . · · · · .. ... · . · · · · · .· · · · · . . . · · · -@- . . · · · · . ... s · . . ~. · · Table10 Condition Code Register Manipulation Instructions Operations Clear Carry Clear Interrupt Mask Clear Overflow Set Garry Set Interrupt Mask Set Overflow Accumulator A-+ CCR CCR -+ Accumulator A Mnemontc CLC CLI CLV SEC SEI SEV TAP TPA 'l'\ddressingModes IMPLIED - OP # oc 2 1 OE 2 1 OA 2 1 OD 2 1 OF 2 1 OB 2 1 06 2 1 07 2 1 Boolean Operation o-c 0-1 o-v 1-c 1-1 1-V A- CCR CCR-A Condition Code Register 54 32 10 H I Nz v c . . . · · A . . . . R · . · · · · A . . · · · s . . . s · · ....s · --] ---- .· · · · · Condition Code Register Notes: (Bit set it test is true and cleared otherwise) 1 (Bit VI !Bit Cl (Bit C) (Bit V) (Bit V) (Bit V) (Bit N) (All) (Bit I) (All) (Bit Cl Test: Result= 10000000? Test: Result · 00000000? Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set) Test: Operand"" 10000000 prior to execution? Test: Operand"" 01111111 prior to execution? Test: Set equal to result of N (±) C after shift has occurred. Test: Result less than zero? (Bit 15 = 1) Load Condition Code Register from Stack. (See Special Operations) Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state. Set according to the contents of Accumulator A. Set equal to result of Bit 7 (ACCB) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 73 Table 11 Instruction Execution Times in Machine Cyde ABA ABX ADC ADD ADDO AND ASL ASLD ASA BCC BCS BEO BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BAA BAN BSA eve BVS CBA CLC CLI CLR CLV CMP COM CPX DAA DEC DES DEX EOR INC INS · . · ACCX I~::- Direct Extended Indexed Implied · · 2 Re· lative · · ·· 3 · ·2 3 4 4·· · 2 3 4 4 · · 4 5 6 6 · · · 2 3 4 4 · 2 ··6 6 ·· · · 3 · 2 ·66 ·· · · · · · · · · · · · · · · · · · · 3 2 3 4 4 · · · · · · · · · 3 · · · · · 3 · · · · · · · · 3 · · · · · 3 · · · · · · · · 3 · · · · · 6 · · · · 3 · · · 3 · · · · 2 · · · · 2 · · · · · · 2 · 6 6 · 2 · 2 3 4 4 · ·6 6 ·· · 4 5 6 6 · · · · · 2 ··6 6 · · · · · · · · · 2 3 4 4 2 6 6 · · · · · · ACCX ~~.~:- Direct te~~~ d~~~ Im· plied Ae· lative INX JMP JSR LOA LOO LOS LOX LSA LSAD MUL NEG NOP ORA PSH PSHX PUL PULX AOL ROA ATI ATS SBA SBC SEC SEI SEV STA STD STS STX SUB · · · · · · · 5 · 2 3 · 3 4 · 3 4 · 3 4 2 ·· · · · · · 2 · · · · 2 3 3 ·· · · · 4 ·· · · · · 2 ·· · · · · · · · · 2 · · · · · · · · · 4 · · 4 · 4 3 ·· 3 · 3 3·· 6 6 · · 4 4 ·· 5 5 · 5 s · · s s · · 6 6 · · ··3 · · 10 · 6 6 · · · · 2 4 4 ·· · · · · · 4 · · · · · 5 · 6 6 · 6 6 ·· · · 10 · 5 · · · 4 4 · 2 ··2 · · · 2 4 4 ·· 5 s · 5 5 · 5 5 ·· 4 4·· SUBD 4 6 6 SWI TAB · · · · · 12 2 · · TAP · · 2 · TBA · · 2 · TPA · · · · · TST 2 ·· 6 6 TSX · · · · TXS WAI · · · 3 ·9 · @HITACHI 74 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · Summary of Cycle by Cycle Operation Table 12 provides a detailed description of the information present on the Address Bus, Data Bus, and the Read/Write line (R/W) during each cycle for each instruction. This information is useful in comparing actual with expected results during debug of both software and hardware as the control program is executed. The information is categorized in groups according to addressing mode and number of cycles per instruction. (In general. instructions with the same addressing mode and number of cycles execute in the same manner: exceptions are indicated in the table). Address Mode & Instructions IMMEDIATE ADC EOR ADD LOA AND ORA BIT SBC CMP SUB LOS LOX LOO CPX SUBD ADDO DIRECT ADC EOR ADD LOA AND ORA BIT SBC CMP SUB STA LOS LOX LOO STS STX STD CPX SUBD ADDO JSR Cycles Cycle # Table 12 Cycle by Cycle Operation Address Bus R/W Line Data Bus 2 1 Op Code Address 2 Op Code Address+ 1 1 Op Code 1 Operand Data 3 1 Op Code Address 2 Op Code Address + 1 3 Op Code Address + 2 4 1 Op Code Address 2 Op Code Address + 1 3 Op Code Address + 2 4 Address Bus FF FF 3 1 Op Code Address 2 Op Code Address + 1 3 Address of Operand 3 1 Op Code Address 2 Op Code Address + 1 3 Destination Address 4 1 Op Code Address 2 Op Code Address+ 1 3 Address of Operand 4 Operand Address + 1 4 1 Op Code Address 2 Op Code Address + 1 3 Address of Operand 4 Address of Operand + 1 5 1 Op Code Address 2 Op Code Address + 1 3 Operand Address 4 Operand Address + 1 5 Address Bus F FF F 5 1 Op Code Address 2 Op Code Address + 1 3 Subroutine Address 4 Stack Pointer 5 Stack Pointer + 1 1 Op Code 1 Operand Data (High Order Byte) 1 Operand Data (Low Order Byte I 1 Op Code 1 Operand Data (High Order Byte I 1 Operand Data (low Order Byte) 1 Low Byte of Restart Vector 1 Op Code 1 Address of Operand 1 Operand Data 1 Op Code 1 Destination Address 0 Data from Accumulator 1 Op Code 1 Address of Operand 1 Operand Data (High Order Byte I 1 Operand Data (low Order Byte) 1 Op Code 1 Address of Operand 0 Register Data (High Order Byte) 0 Register Data (Low Order Byte I 1 Op Code 1 Address of Operand 1 Operand Data (High Order Byte) 1 Operand Data (low Order Byte) 1 Low Byte of Restart Vector 1 Op Code 1 Irrelevant Data 1 First Subroutine Op Code 0 Return Address (Low Order Byte) 0 Return Address (High Order Byte) (Continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 75 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Cycles Cycle # Address Bus R/W Line Data Bus INDEXED JMP 3 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector ADC EOR ADD LOA AND ORA BIT SBC CMP SUB 4 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FF FF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 1 Operand Data STA 4 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 0 Operand Data LOS LOX LOO LOO 5 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 1 Operand Data (High Order Byte) 5 Index Register Plus Offset + 1 1 Operand Data (Low Order Byte) STS 5 1 Op Code Address 1 Op Code STX 2 Op Code Address + 1 1 Offset STD 3 Address Bus FF FF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 0 Operand Data (High Order Byte) 5 Index Register Plus Offset + 1 0 Operand Data (Low Order Byte) ASL LSR ASR NEG CLR ROL COM ROR DEC TST* INC 6 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 1 Current Operand Data 5 Address Bus FFFF 1 Low Byte of Restart Vector 6 Index Register Plus Offset 0 New Operand Data CPX SUBD ADDO 6 1 Op Code Address 1 Op Code 2 Op Code Address+ 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register +Offset 1 Operand Data (High Order Byte) 5 Index Register +Offset + 1 1 Operand Data {Low Order Byte) 6 Address Bus FFFF 1 Low Byte of Restart Vector JSR 6 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FF FF 1 Low Byte of Restart Vector 4 Index Register +Offset 1 First Subroutine Op Code 5 Stack Pointer 6 Stack Pointer - 1 0 Return Address (Low Order Byte) 0 Return Address (High Order Byte) · In the TST instruction, R/W line of the sixth cycle is "1" level, and AB= FFFF, 08 =Low Byte of Reset Vector. (Continued) @HITACHI 76 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions Cycles Cycle # Address Bus R/W Line Data Bus EXTENDED JMP 3 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Jump Address (High Order Byte) 3 Op Code Address + 2 1 Jump Address (Low Order Byte) ADC EOR ADD LDA AND ORA BIT SBC CMP SUB 4 1 Op Code Address 2 Op Code Address + 1 3 Op Code Address + 2 4 Address of Operand 1 Op Code 1 Address of Operand (High Order Byte) 1 Address of Operand (Low Order Byte) 1 Operand Data STA 4 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Destination Address (High Order Byte) 3 Op Code Address + 2 1 Destination Address (Low Order Byte) 4 Operand Destination Address 0 Data from Accumulator LOS 5 1 Op Code Address 1 Op Code LDX 2 Op Code Address + 1 1 Address of Operand (High Order Byte) LDD 3 Op Code Address + 2 1 Address of Operand (Low Order Byte) 4 Address of Operand 1 Operand Data (High Order Byte) 5 Address of Operand + 1 1 Operand Data (Low Order Byte) STS 5 1 Op Code Address 1 Op Code STX 2 Op Code Address + 1 1 Address of Operand (High Order Byte) STD 3 Op Code Address + 2 1 Address of Operand (Low Order Byte) 4 Address of Operand 0 Operand Data (High Order Byte) 5 Address of Operand + 1 0 Operand Data (Low Order Byte) ASL LSR ASR NEG CLR ROL COM ROR DEC TST* INC 6 1 Op Code Address 2 Op Code Address + 1 3 Op Code Address + 2 4 Address of Operand 5 Address Bus FFFF 6 Address of Operand 1 Op Code 1 Address of Operand (High Order Byte) 1 Address of Operand (Low Order Byte) 1 Current Operand Data 1 Low Byte of Restart Vector 0 New Operand Data CPX SUBD ADDO 6 1 Op Code Address 2 Op Code Address + 1 3 Op Code Address + 2 4 Operand Address 5 Operand Address + 1 6 Address Bus FFFF 1 Op Code 1 Operand Address (High Order Byte) 1 Operand Address (Low Order Byte) 1 Operand Data (High Order Byte) 1 Operand Data (Low Order Byte) 1 Low Byte of Restart Vector JSR 6 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Address of Subroutine (High Order Byte) 3 Op Code Address + 2 1 Address of Subroutine (Low Order Byte) 4 Subroutine Starting Address 1 Op Code of Next Instruction 5 Stack Pointer 0 Return Address (Low Order Byte) 6 Stack Pointer - 1 0 Return Address (High Order Byte) - ·In the TST instruction, R/W line of the sixth cycle is "1" level, and AB= FFFF, 08 =Low Byte of Reset Vector. (Continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 77 Address Mode & Instructions IMPLIED ABA DAA SEC ASL DEC SEI ASR INC SEV CBA LSR TAB CLC NEG TAP CLI NOP TBA CLR ROL TPA CLV ROR TST COM SBA ABX ASLD LSRD DES INS INX DEX PSHA PSHB TSX TXS PULA PULB PSHX PULX RTS WAI .. Table 12 Cycle by Cycle Operation (Continued) Cycles Cycle # Address Bus R/W Line Data Bus 2 1 Op Code Address 2 Op Code Address + 1 1 Op Code 1 Op Code of Next Instruction 3 1 Op Code Address 2 Op Code Address + 1 3 Address Bus FFFF 1 Op Code 1 Irrelevant Data 1 Low Byte of Restart Vector 3 1 Op Code Address 2 Op Code Address + 1 3 Address Bus FFFF 1 Op Code 1 Irrelevant Data 1 low Byte of Restart Vector 3 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Op Code of Next Instruction 3 Previous Register Contents 1 Irrelevant Data 3 1 Op Code Address 2 Op Code Address + 1 3 Address Bus FF FF 1 Op Code 1 Op Code of Next Instruction 1 low Byte of Restart Vector 3 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 1 Op Code 1 Op Code of Next Instruction 0 Accumulator Data 3 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 1 Op Code 1 Op Code of Next Instruction 1 Irrelevant Data 3 1 Op Code Address 2 Op Code Address + 1 3 Address Bus FF FF 1 Op Code 1 Op Code of Next Instruction 1 Low Byte of Restart Vector 4 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 4 Stack Pointer + 1 1 Op Code 1 Op Code of Next Instruction 1 Irrelevant Data 1 Operand Data from Stack 4 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 4 Stack Pointer - 1 5 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 4 Stack Pointer + 1 5 Stack Pointer +2 5 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 4 Stack Pointer + 1 5 Stack Pointer + 2 9 1 Op Code Address 2 Op Code Address + 1 3 Stack Pointer 4 Stack Pointer - 1 1 Op Code 1 Irrelevant Data 0 Index Register (Low Order Byte} 0 Index Register (High Order Byte l 1 Op Code 1 Irrelevant Data 1 Irrelevant Daia 1 Index Register (High Order Byte) 1 Index Register (low Order Byte) 1 Op Code 1 Irrelevant Data 1 Irrelevant Data 1 Address of Next Instruction (High Order Byte) 1 Address of Next Instruction (low Order Byte) 1 Op Code 1 Op Code of Next Instruction 0 Return Address (Low Order Byte) 0 Return Address (High Order Byte) (Continued) @HITACHI 78 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6803 Table 12 Cycle by Cycle Operation (Continued) Address Mode & Instructions WAI"" MUL RTI SWI Cycles 10 10 12 Cycle ;: 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 Address Bus Stack Pointer - 2 Stack Pointer - 3 Stack Pointer - 4 Stack Pointer - 5 Stack Pointer - 6 Op Code Address Op Code Address + 1 Address Bus FF FF Address Bus FFFF Address Bus FFFF Address Bus FFFF Address Bus FFFF Address Bus FFFF Address Bus FFFF Address Bus FFFF Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 Stack Pointer + 2 Stack Pointer + 3 Stack Pointer + 4 Stack Pointer + 5 Stack Pointer + 6 Stack Pointer + 7 R/W Line 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Op Code Address 1 Op Code Address + 1 1 Stack Pointer 0 Stack Pointer - 1 0 Stack Pointer - 2 0 Stack Pointer - 3 0 Stack Pointer - 4 0 Stack Pointer - 5 0 Stack Pointer - 6 0 Stack Pointer - 7 1 Vector Address FFFA (Hex) 1 Vector Address FFFB (Hex) 1 Data Bus Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Cond. Code Register Op Code Irrelevant Data Low Byte of Restart Vector Low Byte of Restart Vector Low Byte of Restart Vector Low Byte of Restart Vector Low Byte of Restart Vector Low Byte of Restart Vector Low Byte of Restart Vector Low Byte of Restart Vector Op Code Irrelevant Data Irrelevant Data Contents of Cond. Code Reg. from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (Low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (low Order Byte) Op Code Irrelevant Data Return Address (low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte} Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Cond. Code Register Irrelevant Data Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) (Continued) ·· While the MPU ss 1n the "Wait" state, its bus state wdl appear as a series of MPU reads of an address which is seven locations less than the original contents of the Stack Pointer. Contrary to the H06800, none of the ports are driven to the high impedance state by a WAI instruction. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 79 RELATIVE_·, Address Mode & Instructions BCC BHT BNE BCS BLE BPL BEQ BLS BRA BGE BLT BVC BGT BMT BVS BRN BSR Cycles 3 6 Table 12 Cycle by Cycle Operation (Continued) Cycle # 1 2 3 Address Bus Op Code Address Op Code Address + 1 Address Bus FFFF R/W Line 1 1 1 Data Bus Op Code Branch Offset Low Byte of Restart Vector 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Branch Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Subroutine Starting Address 1 Op Code of Next Instruction 5 Stack Pointer 0 Return Address (Low Order Bytel 6 Stack Pointer - 1 0 Return Address (High Order Bytel · Summary of Undefined Instruction Operations The HD6803 has 36 underlined instructions. When these are carried out, the contents of Register and Memory in MPU change at random. When the op codes (4E, SE) are used to execute. the MPU continues to increase the program counter and it wjll not stop until the Reset signal enters. These op codes are used to test the LSI. Table 13 Op codes Map HD6803 MICROPROCESSOR INSTRUCTIONS OP CODE ~ 0 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 ------- =-====-=== . . 0000 0 0001 0010 1 2 0011 3 ACC A 0100 4 ACC B IND EXT 0101 0110 0111 56 7 ACCA or SP IMM] OIRJ INDjEXT 1000J 100!_]_ 1010J1011 e Jg] A] B ACCB or X IMMj OIRj INDJ EXT 1100J1101j 111~ 1111 cjoJejF SBA BRA TSX NEG SUB 0 NOP CBA BRN INS CMP 1 ::::::.::::: BHI PULA 1+11 ~ BLS PULB (+11 COM LSRO (+1) ~ BCC DES LSR SBC 2 SUBO 1·21 ADDO (+21 3 ANO 4 ASLO (+11 ~ BCS TAP TAB BNE TXS PSHA ===R=O=R == BIT 5 LOA 6 TPA TBA BEO PSHB INX (+1) ~ eve PULX (+21 ASR 0 ASL STA J:2J STA 7 EOR B 1001 9 DEX (+11 OAA BVS RTS 1+21 ROL AOC 9 1010 A 1011 B 1100 c 1101 0 1110 E 1111 F CLV ~ BPL ABX DEC ORA A SEV ABA BMI RTI 1+71 CLC ~ BGE PSHX 1+11 INC . CPX (+21 . ADO LOO (+11 B c ~ sec BLT MUL (+7) TST 1+5~. JSR 1+21 LC -- .. . CLI BGT WAI (+6) _.... JMP (-3) LOS 1+11 SEI ~ BLE SWI 1+9) CLR ~(+ill STS 1+11 .k."i!i STD 1+11 LOX (+11 ·(·ill STX 1+11 0 e F BYTE/CYCLE 1/2 1/2 2/3 1/3 1/2 1/2 216 316 212 J 213J 214 J 314 212J 213J 214j 3/4 (NOTES) 11 Undefined Op codes are marked with c:;;::::::::::i. 2) ( ) indicate that the number in parenthesis must be added to the cycle count for that instruction. J) The instructions shown below are all 3 bytes and are marked with ...... Immediate addressing mode of SUBO, CPX, LOS, ADDO, LOO and LOX instructions, and undefined op codes IBF, CO, CFI. 4) The Op codes (4E, 5E) are 1 byte/- cycles instructions, and are marked with ...... @HITACHI 80 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I ~ ~ )> 3 '!1 ff !"c:'". I\) "a ' 0 0aro l@· -~ ~ l5 :I ~ (f) C') ~ :I '0 ~ () )> <O ~ ~ ~ ~,,. (,.) (;< Co "g ' CXl Stack Machine State PC,X,A,B,CC Condition Code Register I I I IN lz I vi c ITMP 1~ ITMP 1~1 ·sc;1 = TIE·TDRE + RIE·(RDRF + ORFE) Vector- PC NMI FFFC FFFD SWI IAQI ICF OCF TOF SCI FFFA FFFB FFF8 FFF9 FFF6 FFF7 FFF4 FFF5 FFF2 FFF3 FFFO FFF1 Non-Maskable Interrupt Software Interrupt Maskable Interrupt Request 1 Input Capture Interrupt Output Compere Interrupt Timer Overflow Interrupt SCI Interrupt (TORE + ROAF + ORFE) :I: Figure 16 Interrupt Flowchart 0 m CXl 0 w 8 16 ROM RAM PIA GPIA PTM Address Bus Data Bus Figure 17 H06803 MPU Expanded Multiplexed Bus · Caution for the HD6803 Family SCI, TIMER Status Flag The flags shown in Table 14 are cleared by reading/writing (flag reset condition 2) the data register corresponding to each flag after reading the status register (flag reset condition I). To clear the flag correctly, take the following procedure: I. Read the status register. 2. Test the flag. 3. Read the data register. Table 14 Status Flag Reset Conditions TIMER SCI Status Flag ICF OCF TOF RDRF ORFE TORE Flag Reset Condition 1 (Status Register) When each flag is "1 ", TRCSR/Read When each flag is "1 ", TRCSR/Read Flag Reset Condition 2 (Data Register) ICR/Read OCR/Write TC/Read RDR/Read TOR/Write @HITACHI 82 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809, HD68A09, HD68B09- MPU (Micro Processing Unit) The HD6809 is a revolutionary high perfonnance 8-bit microprocessor which supports modern programming techniques such as position independence, reentrancy, and modular programming. This third-generation addition to the HMCS6800 family has major architectural improvements which include additional registers, instructions and addressing modes. The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The HD6809 has the most complete set of addressing modes available on any 8-bit microprocessor today. The HD6809 has hardware and software features which make it an ideal processor for higher level language execution or standard controller applications. HD6800 COMPATIBLE · Hardware - Interfaces with All HMCS6800 Peripherals · Software - Upward Source Code Compatible Instruc- tion Set and Addressing Modes · ARCHITECTURAL FEATURES · Two 16-bit Index Registers · Two 16-bit lndexabJe Stack Pointers · Two 8-bit Accumulators can be Concatenated to Form One 16-Sit Accumulator · Direct Page Register Allows Direct Addressing Through- out Memory · HARDWARE FEATURES · On Chip Oscillator · DMA/BREO Allows OMA Operation or Memory Refresh · Fast Interrupt Request Input Stacks Only Condition Code Register and Program Counter · MADY Input Extends Data Access Times for Use With Slow Memory · Interrupt Acknowledge Output Allows Vectoring By Devices · SYNC Acknowledge Output Allows for Synchronization to External Event · Single Bus-Cycle RESET · Single &-Volt Supply Operation · NMI Blocked After RESET Until After First Load of Stack Pointer · Early Address Valid Allows Use With Slower Memories · Early Write-Data for Dynamic Memories · Compatible with MC6809, MC68A09 and MC68809 · SOFTWARE FEATURES · 10 Addressing Modes HMCS6800 Upward Compatible Addressing Modes Direct Addressing Anywhere in Memory Map Long Relative Branches Program <;ounter Relative True Indirect Addressing Expanded Indexed Addressing: HD6809P, HD68A09P, HD68B09P (DP-40) · PIN ARRANGEMENT HD6809 A,, (Top View) HALT XTAI,. EXT AL RS MADY Q DMAtBAEo Rfii o, o, o, o, o, o, o, D, A., A., A., @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 83 0, 5, 8, or 16-bit Constant Offsets 8, or 16-bit Accumulator Offsets Auto-Increment/Decrement by 1 or 2 · Improved Stack Manipulation · 1464 Instructions with Unique Addressing Modes · 8 x 8 Unsigned Multiply · 16-bit Arithmetic · TransfertExchange All Registers · Push/Pull Any Registers or Any Set of Registers · Load Effective Address · BLOCK DIAGRAM PC u s y x A D{ B DP cc ALU +--Vee +--Vss IR RES NMI FIRQ TRCi DMA/BREQ R/W HALT BA BS XTAL EXT AL MADY E Q @HITACHI 84 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Symbol ..Vee Vin Operating Temperature Topr Storage Temperature T.,· Value -0.3-+7.0 -0.3 - +7.0 -20-+75 -55 - +150 Unit v v QC QC * With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · RECOMMENDED OPERATING CONDITIONS Item Supply Voltage Input Voltage Symbol ..Vee VIL min typ 4.75 5.0 -0.3 - . VrH Logic (Ta= O- +75QC) 2.0 Logic (Ta= -20 - OQC) 2.2 - RES 4.0 - Operating Temperature Topr -20 25 *With respect to Vss (SYSTEM GND) max 5.25 0.8 Vee Vee Vee 75 Unit v v v QC · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee =5V±5%, Vss = OV, Ta= -20-+75QC, unless otherwise noted.) Item Input "High" Voltage Input "Low" Voltage Input Leakage Current Three State (Off State) Input Current Output "High" Voltage Output "Low" Voltage Power Dissipation Input Capacitance Output Capacitance *Ta=25QC. Vee=5V Symbol Test Condition Ta= 0 - +75QC HD6809 min !.l'2.'.' max 2.0 - Vee HD68A09 min !YI>_* max 2.0 - Vee HD68B09 min t~· max - 2.0 Vee Unit Except RES VrH - Ta= -20-0QC 2.2 - Vee 2.2 Vee 2.2 - Vee v RES 4.0 - Vee 4.0 - Vee 4.0 - Vee VIL --0.3 - 0.8 --0.3 - 0.8 -0.3 - 0.8 v Except EXTAL, XTAL lin Vin-0-5.25V, Vcc=max ' -2.5 - 2.5 -2.5 - 2.5 -2.5 - 2.5 µA D0 -D7 A 0 -A15 , R/W ITSI Vin=0.4-2.4V, Vcc=max -10 - -100 - 10 -10 100 -100 - 10 -10 - 100 -100 - 10 100 µA D0 -D 1 ILoAo--205µA, 2.4 Vcc=min - - 2.4 - - 2.4 - - AO-A!S· R/W, Q,E VoH ILoAo=-145µA, Vcc=min 2.4 - - 2.4 - - 2.4 - - v BA.BS I LOAo=-100µA, Vcc=min 2.4 - - 2.4 - - 2.4 - - VoL ILoAo=2mA Po - - 0.5 - - 0.5 - - 0.5 v - - - 1.0 - 1.0 - - 1.0 w D0 -D 1 Except 0 0 -0 7 Cin Vin=OV, Ta=25°C, - 10 15 7 10 - 10 15 7 10 - 10 15 7 10 pF A0 -A 15 ,R/W, BA, BS Cout f=1MHz - - 12 - - 12 - - 12 pF @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 85 · AC CHARACTERISTICS (Vcc=5V±5%, Vss = OV, Ta= -20-+75°C, unless otherwise noted.) 1. CLOCK TIMING Item Frequency of Operation (Crystal or External Input) Cycle Time Total Up Time Processor Clock "High" Processor Clock "Low'' E Rise and Fall Time ELow to QHigh Time 0 Clock "High" Q Clock "Low" Q Rise and Fall Time Olow to E Falling Symbol fxTAL tcyc tuT tpweH tpweL tEr· tef tAVS tpwaH tPWQL tar.tat tae Test Condition Fig. 2, Fig. 3 HD6809 HD68A09 HD68B09 min typ max min typ max min tYP max Unit 0.4 - 4 0.4 - 6 0.4 - 8 MHz - - 1000 10000 667 - 10000 500 10000 ns 975 - - 640 - - 480 - - ns - 450 - 15500 280 15700 220 - 15700 ns - 430 5000 280 - 5000 210 - 5000 ns - - - 25 - 25 - - 20 ns - 200 250 130 - 165 80 - 125 ns - 450 - 5000 280 - 5000 220 5000 ns 450 - 15500 280 - 15700 220 - 15700 ns - - - 25 - 25 - - 20 ns 200 - - 133 - - 100 - - ns 2. BUS· TIMING Item Address Delay Address Valid to OHigh Peripheral Read Access Time ltuT-tAo-tosR=tAccl Data Set Up Time (Read) l Input Data Hold Time Address Hold Time A 0 -A,,. RJW Data Delay Time (Write) Output Hold Time Symbol Test Condition HD6809 HD68A09 HD68B09 min typ max min typ max min typ max Unit tAo - - 200 - - 140 - - 110 ns tAa - - 50 - 25 - - 15 - ns tAcc Fig. 2, Fig. 3 - - 695 - - 440 - - 330 ns tosR toHA - 80 - - 60 - 40 - - ns 10 - - 10 - - 10 - - ns Fig. 2, Fig. 3 Ta=0-+75°C tAH Fig. 2, Fig. 3 Ta=-20-0°C 20 - - 20 - - 20 - - ns - - - 10 10 - - 10 - ns tDDW 1DHW Fig. 3 Fig.3 Ta=0-+75°C Fig. 3 Ta=-20-0°c - - 200 - - 140 - - 110 "' 30 - - 30 - - 30 - - ns - 20 - - 20 - - 20 - ns 3. PROCESSOR CONTROL TIMING Item MADY Set Up Time Interrupts Set Up Time HALT Set Up Time AES Set Up Time DMA/BAEQ Set Up Time Processor Control Rise and Fall Time Crystal Oscillator Start Time Symbol Test Condition HD6809 HD68A09 HD68B09 min typ max min typ max min t"l'l'_ max Unit tpcsM 125 - - 125 - - 110 - - ns tp,.-,<: tpc"" tpcsR tpcso Fig. 6-Fig. 10 Fig. 14, Fig. 15 200 - - 200 200 125 - - - 140 - 140 - - 140 - - 125 - - 110 - - - 110 - 110 - - 110 - - - - - ns ns ns ns tpcr, t~ tRC - - - 100 - - 100 - 100 ns - - 50 - - 30 - - 30 ms @HITACHI 86 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 5.0V · C = 30pF (BA, BS) 130pF (D, - 0 7 , E, Q) 90pF (A0 - A11 , R/W) ·A= 11k!l(D0 -D7 ) 16kll (A, - A.,, E, Q, R/W) 24kll (BA, BS) All diodes are 1520749or equivalent. C includes Stray Capacitance. Figure 1 Bus Timing Test Load *Hold time for BA, BS not specified. Figure 2 Read Data from Memory or Peripherals *Hold time for BA, BS not specified. Figure 3 Write Data to Memory or Peripherals · PROGRAMMING MODEL As shown in Figure 4, the HD6809 adds three registers to the set available in the HD6800. The added registers include a Direct Page Register, the User Stack pointer and a second Index Register. · Accumulators (A, B, DI The A and B registers are general purpose accumulators which are used for arithmetic calculations and manipulation of data. Certain instructions concatenate the A and B registers to form a single 16-bit accumulator. This is referred to as the D register, and is formed with the A register as the most significant byte. · Direct Page Regillter (OP) The Direct Page Register of the HD6809 serves to enhance the Direct Addressing Mode. The content of this register appears at the higher address outputs (A8 -A15 ) during Direct Addressing Instruction execution. This allows the direct mode to be used at any place in memory, under program control. To ensure HD6800 compatibility, all bits of this register are cleared during Processor Reset. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 87 · Index Registers IX, Y) The Index Registers are used in indexed mode of addressing. The 16-bit address in this register takes part in the calculation of effective addresses. This address may be used to point to data directly or may be modified by an optional constant or register offset. During some indexed modes, the contents of the index register are incremented or decremented to point to the next item of tabular type. data. All four pointer registers (X, Y, U, S) may be used as index registers. 15 X - Index Register Y - Index Register U - User Stack Pointer S - Hardware Stack Pointer PC A l B D 0 }"""'",.,,_ Program Counter Accumulators 7 0 _,j Lj_ _ _ _ _ o_P_ _ _ _ Direct Page Register j I I j I I I I I 7 0 E F H 1 N Z V C CC - Condition Code Register Figure 4 Programming Model of The Microprocessing Unit · Stack Pointer (U, SI The Hardware Stack Pointer (S) is used automatically by the processor during subroutine calls and interrupts. The stack pointers of the HD6809 point to the top of the stack, in contrast to the HD6800 stack pointer, which pointed to the next free location on the stack. The User Stack Pointer (U) is controlled exclusively by the programmer thus allowing argu· ments to be passed to and from subroutines with ease. Both Stack Pointers have the same indexed mode addressing capabil· ities as the X and Y registers, but also support Push and Pull instructions. This allows the HD6809 to be used efficiently as a stack processor, greatly enhancing its ability to support higher level languages and modular programming. · Program Counter The Program Counter is used by the processor to point to the address of the next instruction to be executed by the processor. Relative Addressing is provided allowing the Program Counter to be used like an index register in some situations. · Condition Code Register The Condition Code Register defines the State of the Processor at any given time. See Fig. 5. F H Carry Overflow ----Zero -----Negative - - - - - - IRQ Mask - - - - - - - - H a l f Carry - - - - - - - - - FIRQ Mask - - - - - - - - - - - - E n t i r e Flag Figure 5 Condition Code Register Format · CONDITION CODE REGISTER DESCRIPTION · BitO (Cl Bit 0 is the carry flag, and is usually the carry from the binary ALU. C is also used to represent a 'borrow' from subtract like instructions (CMP, NEG, SUB, SBC) and is the complement of the carry from the binary ALU. · Bit 1 (V) Bit 1 is the overflow flag, and is set to a one by an operation which causes a signed two's complement arithmetic overflow. This overflow is detected in an operation in which the carry from the MSB in the ALU does not match the carry from the MSB-1. · Bit2 (Z) Bit 2 is the zero flag, and is set to a one if the result of the previous operation was identically zero. · Bit3 !NI Bit 3 is the negative flag, which contains exactly the value of the MSB of the result of the preceding operation. Thus, a negative two's-complement result will leave N set to a one. · Bit4 (I) Bit 4 is the lRQ mask bit. The processor will not recognize interrupts from the IR:Q line if this bit is set to a one. NMI FIRQ, Il«:i, RES, and SWI all are set I to a one; SWl2 and swJ3 do not affect I. · Bit5 (H) Bit 5 is the half-carry bit, and is used to indicate a carry· from bit 3 in the ALU as a result of an 8-bit addition only (ADC or ADD). This bit is used by the DAA instruction to perform a BCD decimal add adjust operation. The state of this flag is @HITACHI 88 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 undefined in all subtract-like instructions. · Bit& (Fl Bit 6 is the FIRQ mask bit. The processor will not recognize interrupts from the FIRQ line if this bit is a one. NMI, FIRQ, SWI, and RES all set F to a one. mQ, SWI2 and SWl3 do not affect F. · Bit 7 IEI Bit 7 is the entire flag, and when set to a one indicates that the complete machine state (all the registers) was stacked, as opposed to the subset state (PC and CC). The E bit of the stacked CC is used on a return from interrupt (RT!) to determine the extent of the unstacking. Therefore, the current E left in the Condition Code Register represents past action. · SIGNAL DESCRIPTION · Power IVss. Vccl Two pins are used tO supply power to the part: Vss is ground or 0 volts, while Vee is +5.0V ±5%. · Address Bus (Ao-A1s I Sixteen pins are used to output address information from the MPU onto the Address Bus. When the processor does not require the bus for a data transfer, it will output address FFFF16 , R/W = "High", and BS = "Low"; this is a "dummy access" or VMA cycle. Addresses are valid on the rising edge of Q (see Figs. 2 and 3). All address bus drivers are made high impedance when output Bus Availalbe (BA) is "High". Each pin will drive one Schottky TTL load or four LS TTL loads, and typically 90 pF. · Data Bus (00 -D,) These eight pins provide communication with the system bi-directional data bus. Each pin will drive one Schottky TTL load or four LS TTL loads, and typically 130 pF. · Raad/Write (R/W) This signal indicates the direction of data transfer on the data bus. A "Low" indicates that the MPU is writing data onto the data bus. R/W is made high impedance when BA is "High". R/W is valid on the rising edge of Q. Refer to Figs. 2 and 3. · Reset !RISI A "Low" level on this Schmitt-trigger input for greater than one bus cycle will reset the MPU, as shown in Fig. 6. The Reset vectors are fetched from locations FFFE16 and FFFF16 (Table I) when Interrupt Acknowledge is true, (BA · BS= I). During initial power-on, the Reset line should be held "Low" until the clock oscillator is fully operational. See Fig. 7. Because the HD6809 Reset pin has a Schmitt-trigger input with a threshold voltage higher than that of standard peripherals, a simple R/C network may be used to reset the entire system. This higher threshold voltage ensures that all peripherals are out of the reset state before the Processor. Table 1 Memory Map for Interrupt Vectors Memory Map For Vector Locations MS LS FFFE FFFC FFFA FFFB FFF6 FFF4 FFF2 FFFO FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF3 FFF1 Interrupt Vector Description RES NMI SWI IRO FIRO SWl2 SWl3 Reserved · HALT A "Low" level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. When halted, the BA output is driven "High" indicating the buses are high impedance. BS is also "High" which indicates the processor is in the Halt or Bus Grant state. While halted, the MPU will not respond to external real-time requests (FIRQ, IRQ) although DMA/BREQ will always be accepted, and NMI or RES will be latched for later response. During the Halt state Q anc!__!_ continue to run normally. If the MPU is not running (RES, DMA/BREQ). a halted state (BA· BS=!) can be achieved by pulling HALT "Low" while lrnS" is still "Low". If DAM/BREQ and HALT are both pulled "Low", the processor will reach the last cycle of the instruction (by reverse cycle stealing) where the machine will then become halted. See Figs. 8 and 16. · Bus Available, Bus Status (BA, BS) The BA output is an indication of an internal control signal which makes the MOS buses of the MPU high impedance. This signal does not imply that the bus will be available for more than one cycle. When BA goes "Low", an additional dead cycle will elapse before the MPU acquires the bus. The BS output signal, when decoded with BA, represents the MPU state (valid with leading edge of Q). Table 2 MPU State Definition BA BS MPU State 0 0 Normal (Running) 0 1 Interrupt or RESET Acknowledge 1 0 SYNC Acknowledge 1 HALT or Bus Grant Interrupt Acknowledge is indicated during both cycles of a hardware-vector-fetch (RES, NM!, FIRQ, IRQ, SW!, SWI2, SWl3). This signal, plus decoding of the lower four address lines, can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device. See Table 1. Sync Acknowledge is indicated while the MPU is waiting for external synchronization on an interrupt line. Halt/Bus Grant is true when the HD6809 is in a Halt or Bus Grant condition. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 89 co 0 I ~ ;",: )> 3 c~;· "r ' 0. "0"'' 0 o0ro i@· ~ :I ~ :::i - ffi (f) C') ~ :I '-- £ CD () )> CD (J"1 ~ ~ 0 ~,,. "'"'(J"1 "00 ' = -+--..., '::.~ S\\\\SSW~ .. "5.$\ ~ \\~~ \\\\\SSSW~ :c 0 CJ) OD 0co New PC H·Bvte I VJ;!;{ ,.,._________________________ New PC H1Bvte New PC Lo8y'te VIDi: flfSI_ lns1ruc11on '~------4"s.------------- Figure 6 RES Timing ....l.!4_1sv SF------------ Vee E RES :'__~ tRe v, 8MHz 6 MHz 4 MHz Cin Cout 18pF±2~ 18 pF ± 20% 22pF±20% 22 pF ± 20% 22pF±20% 22pF ± 20% HD6809 38 Y, 39 Gn J; Tcout TTT Figure 7 Crystal Connections and Oscillator Start Up · Non Maskable Interrupt (NMll* A negative edge on this input requests that a non-maskable interrupt sequence be generated. A non-maskable interrupt cannot be inhibited~ the program, and also has a higher priority than FIRQ, IRQ or software interrupts. During recognition of an NMI, the entire machine state is saved on the hardware stack. After reset, an NMI will not be recognized until the first program load of the Hardware Stack Pointer (S). The pulse width of !ITMI "Low" must be at least one E cycle. If the NMI input does not meet the minimum set up with respect to Q, the interrupt will not be recognized until the next cycle. See Fig. 9. 2nd To Last Last Cycle I. ·I · I· I· Cycle Of Current Inst. Of Current Inst, Dead Cycle· Halted Dead lnstructio Instruction Dead Cycle Fetch Execute Cycle Halted a Address--,,----,,---~ Bus >--'-~1.1-~~~~~~~~~C==x::::J~~~~ Fetch Execute RJW r--v~"\.......~---.1;~~~~~~~~~~1--~~- BS ·..Data ,............_~, (==x::::J..-~~- lnstruction Opcode Figure 8 HALT and Single Instruction Execution for System Debug LaatCycto of Current lnttruc:t:k»n Instruction Fetch 1 - - + - - - - - - - - - - - - - l n t l i r r u p t St.eking and Vector Fetch Se<au·nee - - - - - - - - - - - - - . . . - _ _ _ , Im+1 Im+2 j m+3 Im+4 Im+s 1m+8 Im+7Im+e1 m+9 1,zt+10 1 m+11 1 m+12(+13 1 m+14 1 m+1s 1 m+18r+17 1 m+t~I· n I n+t I Q "Ir ,,...,..""'-'~~~~~~~~~~~~~~~~~~~~~~~~~~~--''-'=-"'=-~~~~~- o... _ _,,__ _,.___ _,.___....t\._ __,,._.,,._ _,,~..J''--~'--~'---J'-----""-~"--"---"--"--~~-""===""',,-.J'--""""""="--"--" ~ PCL PCH UL UH YL YH )(L XH OP A CC Figure 9 iRO and NM! Interrupt Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 91 Lllllt Cycle of Current lratruc:tion lnstruc::tion Fetdl o+1 a ...,_ ""' ··~·Iripes PC PC FFFF SP-1 SP-2 SP-3 FFFF FFF6 FFF7 FFFF NcrwPC NcrwPC+1 FfFm V1H ~0-~BV~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~- ''-----~' Figure 10 FIRQ Interrupt Timing · Fast-Interrupt Request (FIRO)" A "Low" level on this input pin will initiate a fast interrupt sequence provided its mask bit (F) in the CC is clear. This se~nce has priority over the standard Interrupt Request (IRQ), and is fast in the sense that it stacks only the contents of the condition code register and the program counter. The interrupt service routine should clear the source of the interrupt before doing an RTL See Fig. 10. · Interrupt Request (IRQ)* A "Low" level input on this pin will initiate an interrupt Request sequence provided the mask bit (I) in the CC is clear. Since IRQ stacks the entire machine state it provides a slower response to interrupts than FIRQ. IRQ also has a lower priority than FIRQ. Again, the interrupt service routine should clear the source of the interrupt before doing an RTL See Fig. 9. * NMI, FIRQ, and IRQ requests are sampled on the falling edge of Q. One cycle is required for synchronization before these interrupts are recognized. The pending interrupt(s) will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If IRQ and FIRQ do not remain "Low" until completion of the current instruction they may not be recognized. However, NMI is latched and need only remain "Low" for one cycle. · XTAL, EXTAL These inputs are used to connect the on-chip oscillator to an external parallel-resonant crystal. Alternately, the pin EXTAL may be used as a TTL level input for external timing by grounding XTAL. The crystal or external frequency is four times the bus frequency. See Fig. 7. Proper RF layout techniques should be observed in the layout of printed circuit boards. <NOTE FOR BOARD DESIGN OF THE OSCILLATION CIRCUIT> In designing the board, the following notes should be taken when the crystal oscillator is used. 1) Crystal oscillator and load capacity Cin, Cout must be placed J near the LSI as much as possible. [ Normal oscillation may be disturbed when external noise is induced to pin 38 and 39. 2) Pin 38 and 39 signal line should be wired apart from other signal line as much as possible. Don't wire them in parallel. [ Normal oscillation may be disturbed feedbacked to pin 38 and 39. when E or Q signal is I J 0 l"r"-'-'-'-=<,_~,ICo:J,. L_J.,.,.,...,..._~,c~ HD6809 Figure 11 Board Design of the Oscillation Circuit. <THE FOLLOWING DESIGN MUST BE AVOIDED> A signal line or a power source line must not cross or go near the oscillation circuit line as shown in Fig. 12 to prevent the induction from these lines and perform the correct oscillation. The resistance among XTAL, EXTAL and other pins should be over IOMQ. @HITACHI 92 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Must be avoided. I\ 0 HD6809 · E,O E is similar to the HD6800 bus timing signal 1/12 ; Q is a quadrature clock signal which leads E. Q has no parallel on the HD6800. Addresses from the MPU will be valid with the leading edge of Q. Data is latched on the falling edge of E. Timing for E and Q is shown in Fig. 13. · MRDY This input control signal allows stretching of E and Q to extend data-access time. E and Q operate normally while MRDY is "High". When MRDY is "Low'', E and Q may be stretched in integral multiples of quarter (1/4) bus cycles, thus allowing interface to slow memories, as shown in Fig. 14. A maximum Figure 12 Example of Normal Oscillation may be Disturbed. 01 Start Cycle I End of Cycle Latch Data) I E X-....;;o....;;.s""v_ _ _ _ _~/ t I o.sv ~tAvs~ : : Q ~.lf""~2~.4-V-------."'~----I:_ _ __ I Address Valid I Figure 13 E/0 Relationship· Figure 14 MADY Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA g5131 · (408) 435-8300 93 stretch is 10 microseconds. During nonvalid memory access (WA cycles) MRDY has no effect on stretching E and Q; this_ inhibits slowing the processor during "don't care" bus accesses. MRDY may also be used to stretch clocks (for slow memory) when bus control has been transferred to an external device (through the use of HALT and DMA/BREQ). Also MRDY has effect on stretching E and Q during Dead Cycle. · DMA/BREQ The DMA/BREQ input provides a method of suspending execution and acquiring the MPU bus for another use, as shown in Fig. 15. Typical uses include DMA and dynamic memory refresh. Transition of DMA/BREQ should occur during Q. A "Low" level on this pin will step instruction execution at the end of the current cycle. The MPU will acknowledge DMA/BREQ by setting BA and BS to "High" level. The requesting device will now have up to 15 bus cycles before the MPU retrieves the bus for self-refresh. Self-refresh requires one bus cycle with a lead- ing and trailing dead cycle. See Fig. 16. Typically, the DMA controller will request to use the bus by asserting DMA/BRE_Q pin "Low" on the leading edge of E. When the MPU replies by setting BA and BS to a one, that cycle will be a dead cycle used to transfer bus mastership to the DMA controller. False memory accesses may be prevented during and dead cycles by developing a system DMAVMA signal which is "Low" in any cycle when BA has changed. --~~-- When BA goes "Low" (either as a result of DMA/BREQ = "High" or MPU self-refresh), the DMA device should be taken off the bus. Another dead cycle will elapse before the MPU accesses memory, to allow transfer of bus mastership without contention. · MPU OPERATION During normal operation, the MPU fetches an instruction from memory and then executes the requested function. This MPU E DEAD 0.5V OMA DEAD MPU Q DMA/BAEQ BA,BS ADDA (MPU) *DMAVMA is a signal which is developed externally, but is a system requirement for DMA. Figure 15 Typical OMA Timing {<14 Cycles) @HITACHI 94 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 E a DMA/BREQ IOEAo1..- - - - - - - - - - 1 4 OMA Cycles----------__,OEAOI MPU loeA+..--OMA- 1 1 I I I II I I II I *DMAVMA is a signal which is developed externally, but is a system requirement for OMA. Figure 16 Auto - Refresh OMA Timing (Reverse Cycle Stea ling) sequence begins at RES and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An interrupt, HALT or DMA/BREQ can also alter the normal execution of instructions. Fig. 17 illustrates the flow chart for the HD6809. · ADDRESSING MODES The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The HD6809 has the most complete set of addressing modes available on any microcomputer today. For example, the HD6809 has 59 basic instructions; however, it recognizes 1464 different variations of instructions and addressing modes. The addressing modes support modern programming techniques. The following addressing modes are available on the F!D6809: (I) Implied (Includes Accumulator) (2) Immediate (3) Extended (4) Extended Indirect (5) Direct (6) Register (7) Indexed Zero-Offset Constant Offset Accumulator Offset Auto Increment/Decrement (8) Indexed Indirect (9) Relative (10) Program Counter Relative · Implied (Includes Accumulator) In this addressing mode, the opcode of the instruction contains all the address information necessary. Examples of Implied Addressing are: ABX, DAA, SWI, ASRA, and CLRB. · Immediate Addressing In Immediate Addressing, the effective address of the data is the location immediately following the opcode (i.e., the data to be used in the instruction immediately follows the opcode of the instruction). The HD6809 uses both 8 and 16-bit immedir!e values depending on the size of argument specified oy the opcode. Examples of instructions with Immediate Addressing are: LOA #$20 LOX #$FOOO WY :OCAT (NOTE) # signifies Immediate addressing, $signifies hexa- decimal value. · Extended Addressing In Extended Addressing, the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of Extended Addressing include: WA CAT STX MOUSE LDD $2000 · Extended Indirect As a special case of indexed addressing (discussed below), "l" level of indirection may be added to Exten.ded Addressing. In Extended Indirect, the two bytes following the postbyte of an Indexed instruction contain th<e address of the data. LDA [CAT] LDX [$FFFE] STU [DOG) · Direct Addressing Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. This byte specifies the lower 8-bit of the address to be used. The upper 8-bit of the address are supplied by the direct page register. Since only one byte of address is required in direct addressing, this mode requires less memory and executes faster than extended addressing. Of course, only 256 locations (one page) can be @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 95 co Ol ::r: ~ ":?: )> 3 c~;· "'!a:". I\) I\) 0 0 oQ. i@· CD ~ J: ~ ~ ::J - <n C') ~ J: '0 56 () )> "'(JI ~ 1 t; '{' <XI "00 ' RES SeQ. l>-+OPR 1-+F, I 1~RJW ClrN'MT logic ~ :c 0 Ol c~o y CWAI HD6809 Interrupt Structure Bus State I BA BS Running I 0 0 Interrupt or Reset Acknowledge 0 Sync 0 Halt/Bus Grant (NOTE) Asserting RES will result in entering the reset sequence from any point in the flow chart. Figure 17 Flowchart for HD6809 Instruction accessed without redefining the contents of the DP register. Since the DP register is set to $00 on Reset, direct addressing on the HD6809 is compatible with direct addressing on the HD6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are: LOA $30 SETDP LOB $10 (Assembler directive) $1030 LDD <CAT (NOTE l < is an assembler directive which forces direct addressing. · Register Addressing Some opcodes are followed by a byte that defines a register or set of registers to be used by the instruction. This is called a postbyte. Some examples of register addressing are: TFR X, Y Transfers X into Y EXG PSHS PULU A, B A, B, X, Y X, Y, D Exchanges A with B Push Y, X, Band A onto S Pull D, X, and Y from U · Indexed Addressing In all indexed addressing, one of the pointer registers (X, Y, U, S, and sometimes PC) is used in a calculation of the effective address of the operand to be used by the instruction. Five basic types of indexing are available and are discussed below. The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode as well as the pointer register to be used. Fig. 18 lists the legal formats for the postbyte. Table 3 gives the assembler form and the number of cycles and bytes Post-Byte Register Bit 7 65 43 21 0 0 RR x x xx x 1 RR 0 0 0 0 0 1 R R 0/1 0 0 0 1 1 RR 0 0 0 1 0 1 R R 0/1 0 0 1 1 1 R R 0/1 0 1 0 0 1 R R 0/1 0 1 0 1 1 R R 0/1 0 1 1 0 1 R R 0/1 1 0 0 0 1 R R 0/1 1 0 0 1 1 R R 0/1 1 0 1 1 1 x x 0/1 1 1 0 0 1 x x 0/1 1 1 0 1 1 RR 11 1 1 1 Indexed Addressing Mode EA = ,R + 5 Bit Offset ,R + ,A++ ,-R ' - -R EA = ,R + 0 Offset EA = ,R + ACCB Offset EA = ,R + ACCA Offset EA = , R + B Bit Offset EA= ,R + 16 Bit Offset EA = ,R + D Offset EA= ,PC+ 8 Bit Offset EA= ,PC+ 16 Bit Offset EA= [,Address) Addressing Mode Field Indirect Field (Sigh bit when b7 = O) { O 1 ........ ........ Non Indirect Indirect ~--------- Register Field: RR 00 = x 01 = y 10 = u x = Don't Care 11 =S Figure 18 Index Addressing Postbyte Register Sit Assignments Type Constant Offset From R (2's Complement Offsets) Accumulator Offset From R (2's Complement Offsets) Auto Increment/Decrement R Constant Offset From PC (2's Complement Offsets) Extended Indirect Table 3 Indexed Addressing Mode Forms No Offset 5 Bit Offset 8 Bit Offset 16 Bit Offset A Register Offset B Register Offset D Register Offset Increment By 1 Increment By 2 Decrement By 1 Decrement By 2 8 Bit Offset 16 Bit Offset 16 Bit Address Non Indirect Assembler Form Postbyte OP Code ,R 1RR00100 n, R ORRnnnnn n, R 1 RR01000 n, R A,R ' 1 RR01001 1RR00110 8, R 1 RR00101 D,R 1 RR01011 ,R + 1RROOOOO ,R + + 1 RR00001 , -R 1 RR00010 '-- R n, PCR 1 RR00011 1 xx01100 n, PCR - 1xx01101 - -+ + # 0 0 1 0 1 1 4 2 1 0 1 0 4 0 2 0 3 0 2 0 3 0 1 1 5 2 -- R ~ X, Y, U or S x = Don't Care RR: 00= x 01 = y 10 11 = = u s ~and #indicate the number of additional cycles and bytes for the particular variation. Indirect Assembler Form Postbyte OP Code [.R] 1 RR10100 defaults to 8-bit [n, R] 1RR11000 [n, R] 1RR11001 [A, R] 1RR10110 [B, R] 1 RR10101 [D, R] 1RR11011 not allowed LR ++J 1 RR10001 not allowed [. - - Fl] 1RR10011 [n;PCR] 1xx11100 [n, PCR] 1xx11101 (n] 10011111 -+ + # 3 0 4 1 7 2 4 0 4 0 7 0 6 0 6 0 4 1 8 2 5 2 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 97 added to the basic values for indexed addressing for each variation. Zero-Offset Indexed In this mode, the selected pointer register contains the effective address of the data to be used by the instruction. This is the fastest indexing mode. Examples are: LDD O,X LDA S Constant Offset Indexed In this mode, a two's-complement offset and the contents of one of the pointer registers are added to form the effective address of the operand. The pointer register's initial content is unchanged by the addition. Three sizes of offsets are available: 5-bit (-16 to +15) 8-bit (-128 to +127) 16-bit (-32768 to +32767) The two's complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and cycles. The two's complement 8-bit offset is contained in a single byte following the postbyte. The two's complement 16-bit offset is in the two bytes following the postbyte. In most cases the programmer need not be concerned with the size of this offset since the assembler will select the optimal size automatically. Examples of constant-offset indexing are: LDA 23,X LDX -2,S LDY 300,X LDU CAT,Y Accumulator-Offset Indexed This mode is similar to constant offset indexed except that the two's-complement value in one of the accumulators (A, B or D) and the contents of one of the pointer registers are added to form the effective address of the operand. The contents of both the accumulator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time. Some examples are: LDA B,Y LDX D,Y LEAX B,X Auto Increment/Decrement Indexed In the auto increment addressing mode, the pointer register contains the address of the operand. Then, after the pointer register is used it is incremented by one or two. This addressing mode is useful in stepping through tables, moving data, or for the creation of software stacks. In auto decrement, the pointer register is decremented prior to use as the address of the data. The use of auto decrement is similar to that of auto increment; but the tables, etc., are scanned from the "High" to "Low" addresses.· The size of the increment/decrement can be either one or two to allow for tables of either 8 or 16-bit data to be accessed and is selectable by the programmer. The predecrement, post-increment nature of these modes allow them to be used to create additional software stacks that behave identically to the U and S stacks. Some examples of the auto increment/decrement addressing modes are: LDA ,X+ STD ,Y++ LDB ,-Y LDX ,--S Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the effective address. Consider the following instruction: STX 0, X + + (X initialized to 0) The desired result is to store a 0 in locations $0000 and $0001 then increment X to point to $0002. In reality, the following occurs: 0-+ temp calculate the EA; temp is a holding register X+2-+X perform autoincrement X-+(temp) do store operation · Indexed Indirect All of the indexing modes with the exception of auto increment/decrement by one, or a ±4-bit offset may have an additional level of indirection specified. In indirect addressing, the effective address is contained at the location specified by the contents of the Index register plus any offset. In the example below, the A accumulator is loaded indirectly using an effective address calculated from the Index register and an offset. Before Execution A= XX (don't care) X= $FOOO $0100 LDA [$10,X] EA is now $FOIO $FOIO $Fl $FOl I $50 $F 150 is now the new EA $F150 $AA After Execution A = $AA Actual Data Loaded X= $FOOO All modes of indexed indirect are included except those which are meanijlgless (e.g., auto increment/decrement by indirect). Some examples of indexed indirect are: LDA [,X] LDD [10,S] LDA [B,Y] LDD [,X++J · Relative Addressing The byte(s) following the branch opcode is (are) treated as a signed offset which may be added to the program counter. If the !>ranch condition is true then the call!ulated address (PC + signed offset) js loaded into the program counter. Program execution continues at the new location as indicated by the PC; short (1 byte offset) and long (2 bytes offset) relative addressing modes are available. All of memory can be reached in long relative addressing as an effective address is interpreted modulo 216 · Some examples of relative addressing are: CAT DOG BEQ BGT LBEQ LBGT CAT DOG RAT RABBIT (short) (short) (long) (long) @HITACHI 98 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · · · RAT NOP RABBIT NOP · Program Counter Relative The PC can be used as the pointer register with 8 or 16-bit signed offsets. As in relative addressing, the offset is added to the current PC to create the effective address. The effective address is then used as the address of the operand or data. Program Counter Relative Addressing is used for writing position independent programs. Tables related to a particular routine will maintain the same relationsWp after the routine is moved, if referenced relative to the Program Counter. Examples are: LDA CAT, PCR LEAX TABLE, PCR Since program counter relative is a type of indexing, an additional level of indirection is available. I.DA [CAT, PCR] LDU [DOG, PCR] · HD6809 INSTRUCTION SET The instruction set of the HD6809 is similar to that of the HD6800 and is upward compatible at the source code level. The number of opcodes has been reduced from 72 to 59, but because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) has risen from 197 to 1464. Some of the new instructions and addressing modes are described in detail below: · PSHU/PSHS The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register, or set of registers with a single instruction. · PULU/PULS The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following the push or pull opcode determines wWch register or registers are to be pushed or pulled. The actual PUSH/PULL sequence is fixed; each bit defines a unique register to push or pull, as shown in below. PUSH/PULL POST BYTE +-Pull Order Push Order-+ PC U Y X DP B A cc FFFF ... <- increasing memory address .....0000 PCS YXDPBACC ·TFR/EXG Within the HD6809, any register may be transferred to or exchanged with another of like-size; i.e., 8-bit to 8-bit or 16-bit to 16-bit. Bits 4-7 of postbyte define the source register, while bits 0-3 represent the destination register. Three are denoted as follows: 0000- D 0001 - x 0010 - y 0011 - u 0100- s 0101 - PC 1000 - A 1001 - B 1010 - cc 1011 - DP (NOTE) All other combinations are undefined and INVALID. TRANSFER/EXCHANGE POST BYTE l ~ou~c~ joe~11~AT[oNI · LEAX/LEAY/LEAU/LEAS The LEA (Load Effective Address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction are illustrated in Table 4. The LEA instruction also allows the user to access data in a position independent manner. For example: LEAX MSGl,PCR LBSR · · MSG I FCC PDATA (Print message routine) 'MESSAGE' TWs sample program prints: 'MESSAGE'. By writing MSG I, PCR, the assembler computes the distance between the present address and MSG I. TWs result is placed as a constant into the LEAX instruction wWch will be indexed from the PC value at the time of execution. No matter where the code is located, when it is executed, the computed offset from the PC will put the absolute address of MSG 1 into the X pointer register. TWs code is totally position independent. The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the autoincrement and autodecrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows: LEAa, b+ (any of the 16-bit pointer registers X, Y, U or Smay be substituted for a and b.) 1. b-+ temp (calculate the EA) 2. b + I -+ b (modify b, postincrement) 3. temp-+ a (load a) LEAa,-b l. b - 1 -+ temp (calculate EA with predecrement) 2. b - 1 -+ b (modify b, predecrement) 3. temp-+ a (load a) Autoincrement-by·two and autodecrement·by·two instruc- tions work similarly. Note that LEAX, X+ does not change X, however LEAX, -X does decrement X. LEAX 1, X should be used to increment X by one. ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 99 Table 4 LEA Examples Instruction LEAX 10, X LEAX 500, X LEAY A, Y LEAY D, Y LEAU -10, U LEAS -10, S LEAS 10, S LEAX 5, S~ Operation Comment X + 10 --> X Adds 5-bit constant 10 to X X + 500--> X Adds 16-bit constant 500 to X Y +A --> Y Adds 8-bitaccumulator to Y Y + D --> Y Adds 16-bit D accumulator to Y U - 10 --> U Subtracts 10 from U S - 10 --> S Used to reserve area on stack S + 10 --> S Used to 'clean up' stack S + 5 --> X Transfers as well as adds FFFF16 on the address bus, R/W="High" and BS="Low". The following examples illustrate the use of the chart; see Fig. 20. Example 1: LBSR (Branch Taken) Before Execution SP = FOOO $8000 LBSR CAT · MUL Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D accumulator. This unsigned multiply also allows multipleprecision multiplications. Long And Short Relative Branches The HD6809 has the capability of program counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8 or 16-bit signed offset is added to the value of the program counter to be used as the effective address. This allows the program to branch anywhere in the 64k memory map. Position independent code can be easily generated through the use of relative branching. Both short (8-bit) and long ( 16-bit) branches are available. ·SYNC After encountering a Sync instruction, the MPU enters a Sync state, stops processing instructions and waits~ an interrupt. If the pending interrupt is non-maskable (NM!) or maskable ~. IRQ) with its mask bit (F or I) clear, the processor will clear the Syne state and perform the ~rmal interrupt stacking and se)"Vice routine. Since FIRQ and IRQ are not edge-triggered, a "Low" level with a minimum 4uration of three bus cycles is required to assure that the inte~t will be taken. If the pending interrupt is maskable (FIRQ, IRQ) with its mask bit (F or I) set, the processor will clear the Sync state and continue processing by executing the next inline instruction. Fig. 19 depicts Sync timing. Software lnterNpts A Software Interrupt is an instruction which will cause an interrupt, and its associated vector fetch. These Software Interrupts are useful in operating system calls, software debugging trace operations, memory mapping, and software developm'ent systems. Three levels of SW! are available on this HD6809, and are prioritized in the following order: SW!, SWl2, SWl3. 16-Bit Operation The HD6809 has the capability of processing 16-bit data. These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes and pulls. · CYCLE-BY-CYCLE OPERATION The address bus cycle-by-cycle performance chart illustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the HD6809. Each instruction begins with an opcode fetch. While that opcode is being internally decoded, the next program byte is always fetched. (Most instructions will use the next byte, so this technique considerably speeds throughput.) Next, the operation of each opcode will follow the flow chart. VMA is an indication of $AOOO CAT Cycle# 1 2 3 4 5 6 7 8 9 Address 8000 8001 8002 FFFF FFFF AOOO FFFF EFFF EFFE CYCLE-BY-CYCLE FLOW Data R/W Description 17 1 Opcode Fetch IF 1 Offset High Byte FD 1 Offset Low Byte · 1 \/MA Cycle · 1 VMACycle · 1 Computed Branch Address · 1 VMACycle 03 0 Stack Low Order Byte of Return Address 80 0 Stack High Order Byte of Return Address Example 2: DEC (Extended) $8000 DEC $AOOO FCB $AOOO $80 CYCLE-BY-CYCLE FLOW Cycle# Address Data R/W Description 1 8000 7A 1 Opcode Fetch 2 8001 AO 1 Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 FFFF · 1 VMACycle 5 AOOO 80 1 Read the Data 6 FFFF · 1 VMACycle 7 AOOO 7F 0 Store the Decre- mented Data · The data bus has the data at that particular address. · HD6809 INSTRUCTION SET TABLES The instructions of the HD6809 have been broken down into five different categories. They are as follows: 8-Bit operation (Table 5) 16-Bit operation (Table 6) Index register/stack pointer instructions (Table 7) Relative branches (long or short) (Table 8) Miscellaneous instructions (Table 9) HD6809 instruction set tables and Hexadecimal Values of instructions are shown in Table 10 and Table 11. @HITACHI 100 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 lelt Cycle of Previous Instruction ........ Sync Acknowledge Last Cycle of Sync Instruction a Address Doto BA es_~J\..~~~~~~~~~~~~~~~~-"r~~~~-'-~~~~~~~~~~~-'-~~~~~~~ ~ ----------------------'l'.r---ivr[i<-iJ_i4·j ·ct · · ~ O.B.::rr-IPCS (NOTES) · If the associated mask bit is set when the interrupt is reques~his ~will be an instruction fetch from address location PC+ 1. However, if the interrupt is accepted (NMI or an unmasked FIRQ or IRQ) interrupt processing continues with this cycle as Im) on Figure 9 and 10 (Interrupt Tim!!!sl., "'·- If mask bits are clear, rR1l and FIRQ must be held "Low" for three cycles to guarantee that interrupt will be taken, although only one cycle is necessary to bring the processor out of SYNC. Figure 19 Sync Timing ~ Opcode !Fetch) Long Short Br·nch Branch Immediate a Inherent Opcode+ vi;;; ADDA I i Stack !Write) Stack (Write) Opera11ori Indexed Opcode+ ACCA Offset ACCB Offset R.;. 5 Bit R + 8 Bit PC+ 8 Bit Auto Auto R+ 16·Bit lncfDec Inc/Dec Bv1 Bv2 R·D PC + E1ttend11d No OffHt 16-Bit Indirect Opcoda + Opcode + Opcode + Opcode + V A Opcode +Opcode+ Opcode +Opcode+ VA vk wk vk vk vk vk v.h w¥ k VMA Fetch {NOTE) Write operation during store instruction. Figure 20 Address Bus Cycle-by-Cycle Performance @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 101 Implied Page H-----------i---+---0----..---------i.----H-- AsLA ASLB ASRA ASRB CLRA CLAS COMA COMB OAA DECA OECB INCA INCB LSLA LSLB LSRA LSRB NEGA NEGS NOP ROLA ROLB RORA RORB SEX TSTA TSTB ABX ATS TFR EXG MUL PSHU PULU SW! CWA! PSHS PULS SW!2 SW!3 STACK STACK VIVI v 'TMA STACK' ID11mniv Readl {SITWAnCtelK)'0.' T (Wr! {STACK )'~2 RT! STACK ST1K(D"eRmffmdy! (NOTE) STACK": Address stored in stack pointer ~fore execution. STACK": AddresS set to stack pointer a~ the result of the execution. Figure 20 Address Bus Cycle-by-Cycle Performance (Continued) Non-Implied AOCA AOCB ADDA ADDS ANDA ANDS SITA BITS CMPA CMPB EORA EORB LOA LOB ORA ORB SBCA secs STA STB SUSA sues LOO LOS LOU LOX LOY ANDCC ORCC ASL ASR CLR COM DEC !NC LSL LSR NEG ROL AOR TST ADDO CMPC CMPS CMPU CMPX CMPY sueo JSR STD STS STU STX STY VMA \iMA ADDA + VMA STACK J~~~e~ ADDA + Tllllr Figure 20 Address Bus Cycle-by-Cycle Performance (Continued) 102 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 5 8-Bit Accumulator and Memory Instructions Mnemonic(s) ADCA,ADCB ADDA,ADDB ANDA,ANDB ASL,ASLA,ASLB ASR,ASRA,ASRB BITA, BITB CLR, CLRA, CLRB CMPA,CMPB COM, COMA, COMB DAA DEC,DECA,DECB EORA, EORB EXG Rl, R2 INC, INCA, INCB LOA, LOB LSL, LSLA, LSLB LSR, LSRA, LSRB MUL NEG, NEGA, NEGB ORA, ORB ROL, ROLA, ROLB ROR, RORA, RORB SBCA, SBCB STA,STB SUBA, SUBB TST, TSTA, TSTB TFR Rl, R2 Operation Add memory to accumulator with carry Add memory to accumulator And memory with accumulator Arithmetic shift of accumulator or memory left Arithmetic shift of accumulator or memory right Bit test memory with accumulator Clear accumulator or memory location Compare memory from accumulator Complement accumultor or memory location Decimal adjust A accumulator Decrement accumulator or memory location Exclusive or memory with accumulator Exchange Rl with R2 (Rl, R2 =A, B, CC, DP) Increment accumulator or memory location Load accumulator from memory Logical shift left accumulator or memory location Logical shift right accumulator or memory location Unsigned multiply (Ax B-+ D) Negate accumulator or lflemory Or memory with accumulator Rotate accumulator or memory left Rotate accumulator or memory right Subtract memory from accumulator with borrow Store accumulator to memory Subtract memory from accumulator Test accumulator or memory location Transfer Rl to R2 (Rl, R2 =A, B, CC, DP) (NOTE) A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS, PULU) instructions. Mnemonic(s) ADDO CMPD EXG D, R LOO SEX STD SUBD TFR D, R TFR R,D Table 6 16-Bit Accumulator and Memory Instructions Operation Add memory to D accumulator Compare memory from D accumulator Exchange D with X, Y, S, U or PC Load D accumulator from memory Sign Extend B accumulator into A accumulator Store D accumulator to memory Subtract memory from D accumulator Transfer D to X, Y, S, U or PC Transfer X, Y, S, U or PC to D (NOTE) D may be pushed (1>11lled) to either stack with PSHS, PSHU (PULS, PULU) instructions. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA g5131 · (408) 435-8300 103 HD6809 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Mnemonic(s) CMPS, CMPU CMPX,CMPY EXG R1, R2 LEAS, LEAU LEAX, LEAY LDS,LDU LOX, LOY PSHS PSHU PULS PULU STS,STU STX, STY TFR Rl, R2 ABX Table 7 Index Register/Stack Pointer Instructions Operation Compare memory from stack pointer Compare memory from index register Exchange D, X, Y, S, U or PC with D, X, Y, S, U or PC Load effective address into stack pointer Load effective address into index register Load stack pointer from memory Load index register from memory Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack Push A, B, CC, DP, D, X, Y, S, or PC onto user stack Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack Pull A, B, CC, DP, D, X, Y, Sor PC from user stack Store stack pointer to memory Store index register to memory Transfer D, X, Y, S, U or PC to D, X, Y, S, U or PC Add B accumulator to X (unsigned) Mnemonic(s) BEQ, LBEQ BNE, LBNE BMI, LBMI BPL,LBPL BCS,LBCS BCC,LBCC BVS, LBVS BVC, LBVC BGT, LBGT BGE, LBGE BEQ, LBEO BLE,LBLE BLT,LBLT BHI, LBHI BHS, LBHS BEQ, LBEO BLS, LBLS BLO,LBLO BSR,LBSR BRA,LBRA BRN, LBRN Table 8 Branch Instructions Operation SIMPLE BRANCHES Branch if equal Branch if not equal Branch if minus Branch if plus Branch if carry set Branch if carry clear Branch if overflow set Branch if overflow clear SIGNED BRANCHES Branch if greater (signed) Branch if greater than or equal (signed) Branch Branch if if - - equal less than -or -equ-al-(si-gne-d)- - - - - - - - - - - - - - - - - - - - Branch if less than ( s i g n e d ) - - - · - - - - - - - - - - - - - - - - - - - - UNSIGNED BRANCHES Branch if higher (unsigned) Branch if higher or same (unsigned) Branch if equal Branch if lower or same (unsigned) Branch if lower (unsigned) OTHER BRANCHES Branch to subroutine Branch always Branch never 104 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Mnemonic(sl A N DCC CWAI NOP ORCC JMP JSR RTI ATS SWI, SWl2, SWl3 SYNC Table 9 Miscellaneous Instructions Operation AND condition code register AND condition code register, then wait for interrupt No operation OR condition code register Jump Jump to subroutine Return from interrupt Return from subroutine Software interrupt (absolute indirect) Synchronize with interrupt line @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 105 Table 10 HD6809 Instruction Set Table INSTRUCTION/ FORMS ABX IMPLIED - OP # JA 3 1 ADC ADCA ADCB ADD ADDA ADDB ADDO AND ANDA ANDB AN DCC ASL ASLA 48 2 1 ASLB 5B 2 1 ASL ASR ASRA 47 2 1 ASRB 57 2 1 ASR BCC BCC LBCC BCS BCS LBCS BEQ BGE BEQ LBEQ BGE LBGE BGT BGT LBGT BHI BHI LBHI BHS BHS HD6809 ADDRESSING MOOES DIRECT - OP # - - - EXTENDED IMMEDIATE INDEXED® RELATIVE OP # OP # OP # OP -® # 99 4 09 4 9B 4 DB 4 03 6 94 4 04 4 2 B9 5 2 F9 5 2 BB 5 2 FB 5 2 F3 7 2 B4 5 2 F4 5 3 89 2 3 C9 2 3 8B 2 3 CB 2 3 C3 4 3 84 2 3 C4 2 1C 3 2 A9 4+ 2+ 2 E9 4+ 2+ 2 AB 4+ 2+ 2 EB 4+ 2+ 3 E3 6+ 2+ 2 A4 4+ 2+ 2 E4 4+ 2+ 2 08 6 2 78 7 3 68 6+ 2+ 07 6 2 77 7 3 67 6+ 2+ 24 3 2 10 5(6) 4 24 25 3 2 10 5(6) 4 25 27 3 2 10 5(6) 4 27 2C 3 2 10 5(6) 4 2C 2E 3 2 10 5(6) 4 2E 22 3 2 10 5(6) 4 22 24 3 2 LBHS BIT BLE BLO BITA BITB BLE LBLE BLO LBLO BLS BLS 10 ~(6) 4 24 95 4 2 85 5 3 85 2 2 A5 4+ 2+ 05 4 2 F5 5 3 C5 2 2 E5 4+ 2+ 2F 3 2 10 5(6) 4 2F 25 3 2 10 5(6) 4 25 23 3 2 LBLS BLT BLT LBLT BMI BMI LBMI BNE BNE LBNE BPL BPL LBPL BRA BRA LBRA 10 5(6) 4 23 20 3 2 10 5(6) 4 20 2B 3 2 10 5(61 4 28 26 3 2 10 5(6) 4 26 2A 3 2 10 5(6) 4 2A 20 3 2 16 5 3 BRN BRN LBRN 21 3 2 10 5 4 21 DESCRIPTION ArUi++N~xG-+~xED- A l B+M+c~B 5 3 2 1 0 HNz v c · · · · · l l IIl I I I I I A+M-A II I Il · B+M-B I I I t I D+M:M+ 1-D I I l I AAM-A B AM-B · · l I I I 0 0 · · CCI\ IMM-CC <-t- (fJ t-t-l ~} (J{IIIITU}" @ @ I I ® I I t t I I I I I l ~l-.-0 Branch C=O . . . . . Long Branch @I I I ·· (fl) l I I · @ I I l · · · · · C=O Branch C=1 Long Branch C=l ·· ·· ·· ·· ·· z Branch =1 lozng= Branch 1 Branch N$V=O Long Branch N8JV=O ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· Branch ZV!N<!lVl-0 · · ·· ·· ·· ·· Long Branch ZV(N$V)=O · · · · Branch CVZ=O · · · · · · Long Branch CVZ=O Branch C=O Long Branch C=O · · · · · · · · · · Bit Test A (MA Al ·· ·· Bit Test B (M AB) I I 0 I I 0 Braru:h ZV!N<ilV)·1 · · · · · Long Branch · · · · · ZV(N EeV)=l Branch C·l Long Branch C·1 ·· ·· ·· ·· ·· Branch CVZ=1 Long Branch CVZ=1 · · · · · · · · · · Branch N <JJV·1 ·· · · Long Branch ·· · ·· · N<ilV·l Branch N·l Long Branch N·1 ·· ·· ·· ·· ·· Branch Z ·O Long Branch Z·O ·· ·· ·· ·· ·· Branch N · 0 Long Branch N ·0 ·· ·· ·· ·· ·· Branch Always Long Branch/ Always ·· ·· ·· ·· ·· Branch Never · ·· ·· ·· ·· Long Branch Never · (to be continued) 106 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809 INSTRUCTION/ FORMS BSA BSA IMPLIED OP - # LSSR BVC BVC LBVC BVS BVS LBVS CLR CLRA 4F 2 1 CLRB 5F 2 1 CLR CMP CMPA CMPB CMPD CMPS CMPU CMPX CMPY COM COMA 43 2 1 COMB 53 2 1 COM CWAI DAA 19 2 1 DEC DECA 4A 2 1 DECB 5A 2 1 DEC EOR EORA EORB EXG Rl, R2 1E 7 2 INC INCA 4C 2 1 INCB 5C 2 1 INC JMP JSR LO LOA LOB LOO LOS LOU LOX LOY LEA LEAS LEAU LEAX LEAY LSL LSLA 4S 2 1 LSLB 5S 2 1 LSL LSR LSRA 44 2 1 LSRB 54 2 1 LSR MUL 30 11 1 NEG NEGA 40 2 1 NEGB 50 2 1 NEG NOP 12 2 1 HD6809 ADDRESSING MODES DIRECT - OP # EXTENDED IMMEDIATE - OP - # OP # INDEXE[)(D OP - # RELATIVE OP ...... :$) # SD 7 2 17 9 3 2S 3 2 10 5(S) 4 2S 29 3 2 10 5(S) 4 29 OF s 91 4 01 4 10 7 93 11 7 9C 11 7 93 9C s 10 7 9C 2 7F 7 2 Bl 5 2 F1 5 3 10 s 3 B3 11 s SC 3 11 8 B3 2 BC 7 3 10 s BC 3 SF S+ 2+ 3 Sl 2 2 Al 4+ 2+ 3 C1 2 2 E1 4+ 2+ 4 10 5 4 10 7+ 3+ S3 A3 4 11 5 4 11 7+ 3+ SC AC 4 11 5 4 11 7+ 3+ S3 A3 3 SC 4 3 AC S+ 2+ 4 10 5 4 10 7+ 3+ SC AC 03 s 2 73 7 3 S3 S+ 2+ 3C ~20 2 OA s 9S 4 OS 4 2 7A 7 2 BS 5 2 FS 5 3 3 SS 2 3 cs 2 SA S+ 2+ 2 AB 4+ 2+ 2 ES 4+ 2+ QC s 2 7C 7 3 SC S+ 2+ OE 3 2 7E 4 3 SE 3+ 2+ 90 7 2 BO 8 3 AD 7+ 2+ 96 4 2 BS 5 3 BS 2 2 AS 4+ 2+ OS 4 DC 5 10 s 2 FS 5 2 FC s 3 10 7 3 C6 2 3 cc 3 4 10 4 2 ES 4+ 2+ 3 EC 5+ 2+ 4 10 S+ 3+ DE FE CE EE s DE 5 2 FE 3 CE 3 3 EE 5+ 2+ 9E 5 2 BE 6 3 BE 3 3 AE 5+ 2+ s 10 3 10 7 4 10 4 4 10 S+ 3+ 9E BE SE AE 32 4+ 2+ 33 4+ 2+ 30 4+ 2+ 31 4+ 2+ 08 s 2 7S 7 3 SS 6+ 2+ 04 s 2 74 7 3 64 6+ 2+ 00 6 2 70 7 3 60 S+ 2+ DESCRIPTION 5 32 10 HNzv c Branch to Subroutine Long Branch to Subroutine Branch V=O Long Branch V=O · · · · · · · · · · .·· ·· · ·· ·· Branch V= 1 Long Branch v =1 ·· ·· ·· ·· ·· O-A O- B o-M 0 10 0 ·· 0 1 a a ·0 100 Compare M from A ® I I I I · Compare M from B @ I I I I Compare M: M + 1 I I I I fromD · Compare M: M + 1 I I I I from S · Compare M: M + 1 I I I I from U · Compare M: M + 1 I I I I · from X Compare M: M + 1 from Y I I I I A-A l!-B llil-M CC/\IMM-CC (except 1-+E) Wait for Interrupt Decimal Adjust A A-1-A B-1-B M-1-M AE1JM-A BEllM-B R1-R2® I I01 ·· I I 0 1 ·I I 01 (-t- <'M-- J · I I ®I · · · I I I I I I I I I · · · · · I I I I 0 0 · · <-r- ®n-- l A+ 1-A B+ 1-B M+1-M ·· ··· I I I I I I I I I · EA®-Pc · · · · · Jump to Subroutine · · · · · M-A .· .· M-B M: M+ 1- D ·· ·· M: M+ 1-s I I I I 0 a I I0 I Ia M: M+ 1- U M: M+ 1- X M: M+ 1-Y EA®-s EA®-u EA®- X EA®-Y · · · I I I I I I 0 a a · · · . ···· · · · · · · I I · · · · · · · A~} OiJI- IIll]J-· ··· I I I I I I I I I I I I ~A·\iITI-IIJJJiJ ··· 0 a 0 I I I · · · I I I AxB-D (Unsigned) A+ 1-A 1!+1-e llil+ 1-M No Operation 1· . I · (jj) @I I I I l~ I I I I I I I I · · · · (to be continued) ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 107 INSTRUCTION/ FORMS OR ORA ORB ORCC PSH PSHS IMPLIED OP - # 34 s+cv 2 PSHU 36 s+© 2 HD6809 ADDRESSING MODES - - DIRECT EXTENDED IMMEDIATE INDEXED® RELATIVE OP # OP - # OP # OP - # OP -® # 9A 4 2 BA 5 DA 4 2 FA 5 3 BA 2 2 AA 4+ 2+ 3 CA 2 2 EA 4+ 2+ 1A 3 2 PUL PULS 35 5+© 2 PULU 37 5+© 2 AOL ROLA 49 2 1 ROLB 59 2 1 AOL 09 6 2 79 7 3 ROA RORA 46 2 1 RORB 56 2 1 ROA 06 6 2 76 7 3 RTI 38 6/15 1 69 6+ 2+ 66 6+ 2+ ATS 39 5 1 SBC SEX SBCA SBCB 1D 2 92 4 02 4 1 2 82 5 2 F2 5 3 82 2 3 C2 2 2 A2 4+ 2+ 2 E2 4+ 2+ ST STA STB STD STS STU STX STY 97 4 2 B7 5 3 07 4 2 F7 5 3 DD 5 2 FD 6 3 10 6 3 10 7 4 OF FF OF 5 2 FF 6 3 9F 5 2 BF 6 3 10 6 3 10 7 4 9F BF A7 4+ 2+ E7 4+ 2+ ED 5+ 2+ I 10 6+ 3+ EF EF 5+ 2+ AF 5+ 2+ 10 6+ 3+ AF SUB SU8A SUBB SUBD 90 4 DO 4 93 6 2 BO 5 2 FO 5 2 83 7 3 80 2 3 co 2 3 83 4 2 AO 4+ 2+ 2 EO 4+ 2+ 3 A3 6+ 2+ SWI SWI® 3F 19 1 sw12® 10 20 2 I 3F SWl3® 11 20 2 3F I SYNC 13 ~4 1 TFR R1, R2 1F 6 2 TST TSTA 40 2 1 TSTB TST 50 2 1 OD 6 2 70 7 3 I 60 6+ 2+ . DESCRIPTION 53 2 10 HNz vc AVM-A BvM-B CCV IMM- CC · ·· I I I I 0 0 · C-t- (1) 1-1) Push Registers on S Stack Push Registers on U Stack ··· ·· · · · · · ( +- Pull Registers from @H) S Stack ( +- Pull Registers from @) 1-1 ) U Stack .I I I I ~}~ · I I I I ·I I I I ~) COiJJIDliY · · · I I I I I I · · · I l I Return From Interrupt Return From Subroutine . . . . . C+- CVH) A-M-C-A B-M-C-B Sign Extend B into A A-M B~ M D-M: M+1 s- M: M + 1 · . @ I I I I @I I I I II · I ···· I I ! I I l I 0 0 0 0 · · · · u- M: M + 1 x- M: M + 1 Y- M: M + 1 · · · I I I I l I 0 0 0 · · · A-M-A @I I I I · B - M - B @I I I I 0-M: M +1-D l l Il Software I nterrupt1 ·· ·· ·· ·· ·· Software lnterrupt2 · · · · · Software I nterrupt3 Synchronize to Interrupt R1 -R2~ Test A Test B Test M · · · · · ( · tl ~lr-: ~ · I l 0· · I I0· (NOTES) (j) This column gives a base cycle and byte count. To obtain total count, and the values obtained from the INDEXED ADDRESSING MODES tabl·. @ R1 and R2 may be any pair of B bit or any pair of 16 bit registers. The 8 bit registers are: A, B, CC, DP The 16 bit registers are: X, Y, U, S, D, PC @ EA is the effective address. @ The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled. @ 5(6) means: 5 cycles if branch not taken, 6 cycles if taken. @ SWI sets 1 and F bits. SWl2 and SWl3 do not affect I and F. <1J Conditions·Codes set as a direct result of the instruction. @ Value of half-carry flag is undefined. ® Special Case - Carry set if b7 is SET. ®> Condition Codes set as a direct result of the instruction if CC is specified, and not affected otherwise. LEGEND: OP Operation Code (Hexadecimal) Number of MPU Cycles # Number of Program Bytes + Arithmetic Plus Arithmetic Minus x Multiply M Complement of M Transfer Into H Half-carry (from bit 3) N Negative (sign bid Z Zero (byte) V Overflow, 2's complement C Carry from bit 7 t Test and set if true, cleared otherwise · Not Affected CC Condition Code Register Concatenation V Logical or A Logical and c±> Logical Exclusive or 108 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 11 Hexadecimal Values of Machine Codes OP Mnem Mode 00 NEG Direct 01 02 03 COM 04 LSR 05 06 ROA 07 ASA 08 ASL, LSL 09 AOL OA DEC OB OC INC OD TST OE JMP OF CLR Direct # 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 3 2 6 2 10 } See 11 Next Page 12 NOP Implied 2 13 SYNC Implied ~4 14 15 16 LBRA Relative 5 3 17 LBSR Relative 9 3 18 19 DAA Implied 2 1 1A ORCC lmmed 3 2 18 1C AN DCC lmmed 3 2 1D SEX lE EXG 1F TFR Implied i Implied 2 1 8 2 6 2 20 BRA Relative 21 BAN 22 BHI 23 BLS 24 BHS,BCC 25 BLO, BCS 26 BNE 27 BEQ 28 eve 29 BVS 2A BPL 28 BMI 2C BGE 2D BLT 2E BGT 2F BLE Relative 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 OP Mnem 30 LEAX 31 LEAY 32 LEAS 33 LEAU 34 PSHS 35 PULS 36 PSHU 37 PL!LU 38 39 ATS 3A ABX 38 RTI JC CWAI JD MUL 3E 3F SWI Mode # Indexed t 4+ 2+ 4+ 2+ 4+ 2+ Indexed 4+ 2+ Implied 5+ 2 I 5+ 5+ S+ 5 2 2 2 3 Implied 6, lS lmmed ~20 Implied 11 Implied 19 40 NEGA Implied 2 41 42 43 COMA 2 44 LSRA 2 45 46 RORA 2 47 ASRA 2 48 ASLA, LSLA 2 49 ROLA 2 4A DECA 2 4B 4C INCA 2 4D TSTA 2 4E 4F CLRA Implied 2 so NEGB Implied 2 51 S2 53 COMB 2 54 LSRB 2 SS 56 RORB 2 57 ASAB 2 SB ASLB,LSLB 2 59 ROLB 2 SA DECB 2 SB 5C INCB 2 50 TSTB 2 SE SF CLRB Implied 2 OP Mnem Mode 60 NEG Indexed 61 62 63 COM 64 LSR 65 66 ROA 67 ASA 68 ASL, LSL 69 ROL 6A DEC 68 6C INC 6D TST 6E JMP 6F CLR Indexed # 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 3+ 2+ 6+ 2+ 70 NEG Extended 7 3 71 72 73 COM 7 3 74 LSA 3 7S 76 ROA 3 77 ASA 7 3 78 ASL,LSL 3 79 AOL 7 3 7A DEC 7 3 78 7C INC 7 3 7D TST 7 3 7E JMP 4 3 7F CLR Extended 7 3 80 SUSA lmmed 81 CMPA 82 SBCA 83 SUBD i 2 2 2 2 2 2 4 3 84 ANDA 2 2 BS SITA 2 2 86 LOA 2 2 87 88 EDRA 2 2 89 ADCA 2 2 BA ORA 2 2 88 ADDA 2 2 BC CMPX lmmed 4 3 SD BSA Relative 7 2 BE LOX lmmed 3 3 BF LEGEND: ..... Number of MPU cycles (less possible push pull or indexed-mode cycles) # Number of program bytes * Denotes unused opcode (to be continued) @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 109 OP Mnem 90 SUBA 91 CMPA 92 SBCA 93 SUBD 94 ANDA 95 BITA 96 LOA 97 STA 98 EORA 99 ADCA 9A ORA 9B ADDA 9C CMPX 90 JSR 9E LOX 9F STX AO SUBA Al CMPA A2 SBCA A3 SUBD A4 ANDA A5 BITA A6 LOA A7 STA AB EORA A9 ADCA AA ORA AB ADDA AC CMPX AD JSR AE LOX AF STX BO SUBA Bl CMPA 82 SBCA 83 SUBD B4 ANDA 85 BITA B6 LOA B7 STA BB EORA B9 ADCA BA ORA BB ADDA BC CMPX BO JSR BE LOX BF STX CO SUBB Cl CMPB C2 SBCB C3 AOOD C4 ANOB CS BITB Mode Direct i Direct # 4 2 4 2 4 2 6 2 4 2 4 4 2 4 2 4 2 4 2 4 2 4 2 6 2 2 5 2 5 2 Indexed j Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 7+ 2+ 5+ 2+ 5+ 2+ 5 3 5 3 5 3 7 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 7 3 8 3 6 3 rExtended s 2 2 2 4 3 2 2 2 3 2 2 lmmed 2 2 OP Mnem C6 LOB C7 ca EORB C9 ADCB CA ORB CB ADDB CC LDD CD CE LOU CF DO SUBB 01 CMPB 02 SBCB 03 ADDO 04 ANDB 05 BITB 06 LOB 07 STB 08 EORB 09 ADCB DA ORB DB AODB DC LDD DD STD DE LOU OF STU EO SUBB E1 CMPB E2 SBCB E3 ADDO E4 ANDB E5 BITB ES LOB E7 STB EB EORB E9 AOCB EA ORB EB ADDB EC LOO ED STD EE LOU EF STU FO SUBB Fl CMPB F2 SBCB F3 ADDO F4 ANOB F5 BITB F6 LOB F7 STB FS EORB F9 AOCB FA ORB FB AOOB (NOTE): All unused opcodes are both undefined and illegal Mode # lmmed 2 2 I 2 2 2 3 2 2 2 2 3 lmmed 3 3 Direct Direct 4 2 4 2 4 2 6 2 4 2 4 2 4 2 4 2 4 2 4 2 4 4 2 5 2 5 2 5 2 5 2 Indexed Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ Extended 5 3 5 3 5 3 7 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 Extended 5 3 OP Mnem Mode # FC LOO Extended 6 3 FD STD FE LOU t 6 3 6 3 FF STU Extended 6 3 2 Bytes Opcode 1021 LBRN Relative 1022 LBHI 1023 LBLS 1024 LBHS, LBCC 1025 LBCS, LB LO 1026 LBNE 1027 LBEQ 1028 LBVC 1029 LBVS 102A LBPL 102B LBMI 102C LBGE 1020 LBLT 102E LBGT 102F LBLE Relative 103F SWl2 Implied 1083 CMPO 108C CMPY ;lmmed 108E LOY lmmed 1093 CMPD 109C CMPY 109E LOY Direct t 109F STY Direct 10A3 CMPD 10AC CMPY 10AE LOY Indexed i 10AF STY Indexed 1083 CMPO Extided 10BC CMPY 10BE LOY lOBF STY Extended 10CE LOS lmmed 10DE LOS Direct 100F STS Direct 10EE LOS lnde·ed 10EF STS Indexed 10FE LOS Extended lOFF STS Extended 113F SWl3 Implied 1183 CMPU lmmed 118C CMPS lmmed 1193 CMPU Direct 119C CMPS Direct 11A3 CMPU Indexed 11AC CMPS Indexed 1183 CMPU Extended 11 BC CMPS Extended 5 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 20 2 5 4 5 4 4 4 7 3 7 3 6 3 6 3 7+ 3+ 7+ 3+ 6+ 3+ 6+ 3+ 8 4 8 4 7 4 7 4 4 4 6 3 6 3 6+ 3+ 6+ 3+ 7 4 7 4 20 2 5 4 5 4 7 3 3 7+ 3+ 7+ 3+ 8 4 8 4 110 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · NOTE FOR USE [I] Exceptional Operation of HD68=09=~=~ (a) Exceptional Operations of DMA/BREO, BA signals (#1) HD6809 acknowledges the input signal level of DMA/BREQ at the end of each cycle, then determines whether the next sequence is MPU or OMA. When "Low" level is detected, HD6809 executes DMA I I MPU cycle cDyecalde E OMA cycle sequence by setting BA, BS to "High" level. However, in the conditions shown below the assertion of BA, BS delays one clock cycle. < Conditions for the exception > (I) DMA/BREQ : "Low" for 6-13 cycles (2) DMA/BREQ : "High" for 3 cycles Dead cycle MPU cycle .JI I Dead cycle OMA cycle DMA/BREO :~.!_-----'-~ BA, BS 6-13 cycles 3 cycles Figure 21 Exception of BA, BS Output Assertion of BA delays one clock cycle (b) Exceptional Operations of DMA/BREO, BA signals (#2) HD6809 includes a self refresh counter for the re- E __fl_Jl__I' I 11 cycle "High" I ' I I I I DMA/BREO verce cycle steal. And it is only cleared if DMA/BREQ is inactive ("High"} for 3 or more MPU cycles. So l or 2 inactive cycle(s) doesn't affect the self refresh counter. BA, BS MPU I I OM ti I I I I I I ' I j Dead MPU Dead OMA Self Refresh counter l2 cycles ..High'i DMA/BREQ BA,BS I I I l \; I: t : effectiw (l5 cycles) 1 ' t '2 cycle~ I : _. : t-1; : : Raver~ cycl~ steal : I I : ; : : ---TT~~ i i MPU Dead I I I I l I I D~A Dead MPU Dead I I I I I : t : Dead MPU Dead OMA Self Refresh counter lt-·--------."'tt""ec_t..,.iw-,("1"'5-cy-,cl,..e"'sl------~·ootj Reverse cycle steal Figure 22 Exception of DMA/BREO @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose. CA 95131 · (408) 435-8300 111 (c) How to avoid these exceptional operations It is necessary to provide 4 or more cycles for in· active DMA/BREQ level as shown in Fig. 23. _____ OMA/BRicf"""""\~~~~~~~~~~~~~--'J~.~~4_o_r_m_or_e_c_v_cle_s~-i!~~~~~~~~~~~.~ BA,BS__j \ _,I Figure 23 How to Avoid Exceptional Operations [2] Restriction for OMA Transfer There is a restriction for the DMA transfer in the HD6809 (MPU), HD6844 (DMAC) system. Please take care of foJ. lowing. (a) An Example of the System Configuration This restriction is applied to the following system. (I) DMNBREQ is used for DMA request. (2) "Halt Burst Mode" is used for DMA transfer OMA/BREQ HD6B09 (MPU) OMA transfer request ra 0 CI - - - Eclock "7474 DRllH HD6B44 (OMAC) BA OGRNT OMA acknowledge Figure 24 An Example of HD6809, HD6844 System The restriction is also applied to the system which doesn't ) ( use 7474 Flip-Flop. Fig. 24, Fig. 25 shows an example which uses 7474 for synchronizing OMA request with E. (b) Restriction "The number of transfer Byte per one DMA Burst transfer must be less than or equal to 14." Halt burst OMA transfer should be less than or equal to 14 cycles. In another word, the number stored into DMA Byte count register should be 0-14. * Please than care of the section [1](b) if 2 or more DMA channels are used for the DMA transfer. (c) Incorrect operation of HD6809, HD6844 system "Incorrect Operation" will occur if the number of DMA transfer Byte is more than 14 bytes. If DMN BREQ is kept in "Low" level HD6809 performs reverse cycle steals once in 14 DMA cycles by taking back the bus control. In this case, however, the action taken by MPU is a little bit different from the DMAC. As shown in Fig. 25, DMA controller can't stop DMA transfer (@) by BA falling edge and excutes an extra DMA cycle during HD6809 dead cycle. So MPU cycle is excuted right after DMA cycle, the Bus confliction occurs at the beginning of MPU cycle. (d) How to impliment Halt Bust OMA transfer I> 14 cyclesl Please use HALT input of HD6809 for the DMA request instead of DMA/BREQ. @HITACHI 112 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 E I I HD6809 side DMA/BREQ o-------14 cycles------. H06809 reverse cycle steal BA HD6B09,---M-P-U~c-yc~le-r...~o:i1-------D-M-A-cy_c_le-,------P:>7.:".7.it""l".:"'.'.'."."1:>'77~--~D~M7A::-cy-c71e-s-cycle eMxPcUutceydcrleighist ) after OMA, Bus confliction occurs. DGRNT (BA)---+--- HD6844 cycles OMA cycles ®l MPU sets BA to inactive "Low" ) ) for reverse cycle steal, But ( DMAC couldn't acknowledge the request and performs extra OMA during Dead cycle. Figure 25 Comparison of HD6809, HD6844 OMA cycles OMA cycles [3] Note for CLR Instruction Cycle-by-cycle flow of CLR instruction (Direct, Ex- tended, Indexed Addressing Mode) is shown below. In this sequence the content of the memory location specified by the operand is read before writing "00" into it. Note that status Flags, such as IRQ Flag, will be cleared by this extra data read operation when accessing the control/status register (sharing the same address between read and write) of peripheral devices. Example: CLR (Extended) $8000 $AOOO CLR PCB $AOOO $80 Cycle# Address Data RfW Description I 8000 7F I Opcode Fetch 2 8001 AO 1 Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 5 FFFF * AOOO 80 1 VMACycle 1 Read the Data 6 FFFF * 1 VMACycle 7 AOOO 00 0 Store Fixed "00" into Specified Location * The data bus has the data at that particular address. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 113 (4] Note for MRDY 806809 require synchronization of the MRDY input with the 4f clock. The synchronization necessitates an external oscillator as shown in Figure 26. The negative transition of the MRDY signal, normally derived from the chip select decoding, must me~t the tPCs timing. MRDY's positive transition must occur with the rising edge of 4f. 4xf Oscilllltor Part of HD6809 MRDV 36 .NI.ROY Stretch Active Low Chip Select ForSiow Memory or Peripheral +5v .1k 14 A2 74121 3 Al. 5 B CLR Q % 7474 MRDV Synchronization PR D R }' CVhaolsueens 11 Raq'd c 7 MRCiV Stretch ._~St_re.~.h~·"'"'"0.~7-R_C~---'~~~~~- To Memory Figure 26 MRDY Synchronization 114 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809E,HD68A09E,---HD68B09E MPU(Micro Processing Unit} The HD6809E is a revolutionary high performance 8-bit microprocessor which supports modern programming techniques such as position independence, reentrancy, and modular programming. This third-generation addition to the HMCS6800 family has major architectural improvements which include additional registers, instructions and addressing modes. The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The HD6809E has the most complete set of addressing modes available on any 8-bit microprocessor today. The HD6809E has hardware and software features which make it an ideal processor for higher level language execution or standard controller applications. External clock inputs are provided to allow synchronization with peripherals, systems or other MPUs. HD6800 COMPATIBLE · Hardware - Interfaces with All HMCS6800 Peripherals · Software - Upward Source Code Compatible Instruction Set and Addressing Modes · ARCHITECTURAL FEATURES · Two 16-bit Index Registers · Two 16-bit Indexable Stack Pointers · Two 8-bit Accumulators can be Concatenated to Form One 16-Bit Accumulator · Direct Page Register Allows Direct Addressing Throughout Memory · HARDWARE FEATURES · External Clock Inputs, E and 0, Allow Synchronization · TSC Input Controls Internal Bus Buffers · LIC Indicates Opcode Fetch · AVMA Allows Efficient Use of Common Resources in A Multiprocessor System · BUSY is a Status Line for Multiprocessing · Fast Interrupt Request Input Stacks Only Condition Code Register and Program Counter · Interrupt Acknowledge Output Allows Vectoring By Devices · SYNC Acknowledge Output Allows for Synchronization to External Event · Single Bus-Cycle RESET · Single 5-Volt Supply Operation · NMI Blocked After RESET Until After First Load of Stack Pointer · Early Address Valid Allows Use With Slower Memories · Early Write-Data for Dynamic Memories · SOFTWARE FEATURES · 10 Addressing Modes HMCS6800 Upward Compatible Addressing Modes Direct Addressing Anywhere in Memory Map Loog Relative Branches Program Counter Relative True Indirect Addressing Expanded Indexed Addressing: 0, 5, 8, or 16-bit Constant Offsets 8, or 16-bit Accumulator Offsets Auto-Increment/Decrement by 1 or 2 · Improved Stack Manipulation · 1464 Instruction with Unique Addressing Modes · 8 x 8 Unsigned Multiply · 16-bit Arithmetic · Transfer/Exchange All Registers · Push/Pull Any Registers or Any Set of Registers · Load Effective Address · PIN ARRANGEMENT HALT TSC LIC ~ AVMA a BUSY R/W HD6809E o, o, o, o, o. o, o, o, Au A,. A,, Au (Top View) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 115 HD6809E------------------------------ · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Symbol Value Unit Vee* -0.3-+7.0 v Vin* -0.3-+7.0 v Topr -20 -+75 oc Tstg ....,55 -+150 oc * With respect to Vss (SYSTEM GND) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · RECOMMENDED OPERATING CONDITIONS Item Supply Voltage Logic, 0, RES E Input Voltage Logic RES E Operating Temperature * With respect to Vss (SYSTEM GND) Symbol Vee* VIL· V1Lc* V1H* V1Hc* Topr min typ 4.75 5.0 -0.2 - -0.3 - 2.2 - 4.0 - Vcc* -0.75 - -20 25 max unit 5.25 v 0.8 v 0.4 v Vcc* v Vee* v Vee* +o.3 v 75 oc · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee"' 5.0V ±5%, Vss = OV, Ta~ -20 - +75°C, unlen otherwise noted.) Item Symbol Test Condition Input ..High'" Voltage Input "Low" Voltage lnpot Leakage Current Loglc,O m E Loaic.a.m E Logic. 0, RES E Do-o., Output "High" Vol- Ao-Au,R/W BA,BS, LIC, AVMA. BUSY Output "'Low"' Voltage Power Diaipation Input Capacitance Do-07, Logic lnput,O.AH E Output Clpecitance Frequency of Operation Th....smo IOff Statel Input Current ABAo,-ABS1,1L.RIC/,W. AVMA,BUSY E,0 Do-o, Ao-A11,R/W ·Ta· 25°C, Vee· 5V VIH VIHR VIHC VIL VILC lin VOH VOL Po Cin Cout f ITSI Vln=0-5.25V, Vcc·max ILoad · -20!ijlA, Vcc=min ILold · -14!ij1A, Vcc·min ILoad· -100jlA, Vct;·min ILoad·2mA, Vcc·min VincOV. Ta·25°C, f·1MHz Vin ·OV, Ta· 25°C, f·1MHz Vin·0.4-2.4V, Vcc·max HO&m9E HD68A09E H068B08E min typ· max min typ· max min typ· max Unit - - 2.2 Vee 2.2 Vee 2.2 - Vee v - - - 4.0 Vee 4.0 Vee 4.0 Vee v ~75- - -0.2 -0.3 - -2.5 - - -100 Vee +o.3 ~75- - 0.8 -0.2 0.4 -0.3 - 2.5 -2.6 - 100 -100 - Vee +o.3 ~7~- - 0.8 -0.2 0.4 -0.3 - - 2.5 -2.5 - 100 -100 Vee +0.3 v 0.8 v 0.4 v 2.5 /IA 100 /IA 2.4 - - 2.4 - - 2.4 - - v 2.4 - - 2.4 - - 2.4 - - v 2.4 - - 2.4 - - 2.4 - - v - - 0.5 - - 0.5 - - 0.5 v - - 1.0 - - 1.0 - - 1.0 w - - 10 16 10 15 - 10 15 pt' - - - 30 50 30 50 30 50 pf - - 10 15 - 10 15 10 15 pf 0.1 - -10 - -100 - 1.0 0.1 - - 10 -10 - 100 -100 - 1.5 0.1 10 -10 - 100 -100 - 2.0 MHz 10 /IA 100 /IA .HITACHI 116 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809E · AC CHARACTERISTICS (Vee= 5.0V ±5%, Vss · OV, Ta= -20-+75°C, unless otherwise noted.) READ/WRITE TIMING Item Cycle Time Peripheral Read Access Times !eye - tEf - tAo - tosR =tAcc Data SetUlll Time (Read) Input Data Hold Time Output Data Hold Time Ta =O- +75°C Ta= -20-o·c Address Hold Time !Address. R/W) Ta=0-+75°C Ta=-20-o·c Address Delay Data Delay Time (Write) E Clock "Low"' E Clock "High'" (Measured at V1 HI E Rise and Fall Time a Clock "High" Q Rise and Fall Time E "Low" to a Rising Q "High" to E Rising E "High" to a Falling Q "Low" to E Falling Interrupts HALT, RES and TSC Setup Time TSC Drive to Valid Logic Levels TSC Release MOS Buffers to High Impedance TSC Three-State Delay Control Delay (BUSY, LIC) Control Delay (AVMA*) Processor Control Rise/Fall TSC Input Delay Symbol !eve Test Condition HD6809E HD68A09E HD68B09E Unit min typ max min typ max min typ max - - 1000 10000 667 - 10000 500 10000 ns tACC 695 - - 440 - - 330 - - ns 'DSR t o HR - - 80 - - 60 - 40 - ns 10 - - 10 - - 10 - - ns toHw 30 - - 30 - - 30 - - ns 20 - - 20 - - 20 - - ns 20 - - 20 - - 20 - - ns 'AH 10 - - 10 - - 10 - - ns 'AD to ow 'PWEL 'PWEH 'Er. 'Ef -- Fig. 1, 2, - - 7-10, 14 and 17 450 - 450 - -- - 200 - 200 - 9500 295 9500 280 25 - - - 140 - 140 - - 9500 210 9500 220 25 - - 120 ns 110 ns 9500 ns 9500 ns 20 ns tpwaH tar.tat tEa1 'Ea2 'E03 450 -200 - 200 200 - 9500 280 - 9500 220 - 25 - - 25 - - - 130 - - 100 - - 130 - - 100 - - 130 - - 100 - 9500 ns 20 ns - ns - ns - ns 'Ea4 'PCS 200 - - 130 - - 100 - - ns 200 - - 140 - - 110 - - ns 'TSA - - 210 - - 150 - - 120 ns tTSR - - 200 - - 140 - - 110 ns 'TSO tco - - 120 - - 85 - - BO ns - - 300 - - 250 - - 200 ns tco tpc,. tpc1 tpcT - - 300 - - 270 - - 240 ns - - 100 - - 100 - - 100 ns 10 - - 10 - - 10 - - ns · AVMA drives a not-valid data before providing correct output, so spec tco max= 270 nsec (HD68A09E} and 240 nsec (HD68809E) are applied to this signal. When this delay time causes a problem in user's application, please use D-type latch to get stable output. ·~ Q~ I AVMA iaNot Valid%' @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 117 E i.----- tpweL-----.i ' - - - - t p w e H - - - - f\.v...:.:ILC:..._ _ _ __ tea1 Q R/W Acklr. BA, BS* Data BUSY, LIC, AVMA -NotValld · Hold time for BA, BS not specified (NOTE I Waveform measurements for all inputs and outPuts ara specified at logic "High"· VIHrnin and logic "Low" · V1Lmax unless otherwise specified. Figure 1 Read Data from Memory or Petipherals ,._----------~tcyc----------~~ E Q R/W A<klr. 2.4V BA, es· 0.5V Data Data Valid BUSY, LIC, 2.4V AVMA 0.5V ~NotValid · Hold time for BA, BS not specified (NOTEI Waveform measurements for ell inputs and outputs are specified at logic "High"~V1Hmln and logic "Low"· V1Lmox unless otherwise specified. Figure 2 Write Data to Memory or Peripherals 118 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 o.-o., +--Vee +--Vss IA PC u s y x A D{ B DP cc m lilMi FIRQ mo: LIC AVMA R/W TSC HALT BA BS BUSY ALU '----E '----a Figure 3 HD6809E Expanded Block Diagram 6.0V RL =2.2 kll C =30 pF for BA, BS, LIC, AVMA, BUSY 130 pF for De -D, 90 pF for Ao -A11 , R/W R = 11.7 kilfor Do -D, 16.6 icilfor Ao -A11, R/W 24 kilfor BA, BS, LIC, AVMA, BUSY All diodes are 1S2074@ or equivalent. C includes stray capacitance. Figure 4 Bus Timing Test Load · PROGRAMMING .MODEL As shown in Figure 5, the HD6809E adds three registers to the set available in the HD6800. The added registers include a Direct Page Register, the User Stack pointer and a second Index Register. · Accumulators (A, B, DI The A and B registers are general purpose accumulators which are used for arithmetic calculations and manipulation of data. Certain instructions concatenate the A and B registers to form a single 16-bit accumulator. This is referred to as the D Register, and is formed with the A Register as the most significant byte. · Direct Page Register (DP) The Direct Page Register of the HD6809E serves to enhance the Direct Addressing Mode. The content of this register appears at the higher address outputs (A8 - A15) during direct addressing instruction execution. This allows the direct mode to be used at any place in memory, under program control. To ensure HD6800 compatibility, all bits of this register are cleared during Processor Reset. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 119 15 X - Index Register Y - Index Register U - User Stack Pointer S - Hardware Stack Pointer PC A I B -y- D 0 Pointer Registers Program Counter Accumulators 0 ,___ _ _ _o_P_ _ _ _~) Direct Page Register I I I j I I I I I 7 0 E F H 1NZ VC CC - Condition Code Register Figure 5 Programming Model of The Microprocessing Unit · Index Registers (X, VI The Index Registers are used in indexed mode of addressing. The 16-bit address in this register takes part in the calculation of effective addresses. This address may be used to point to data directly or may be modified by an optional constant or register offset. During some indexed modes, the contents of the index register are incremented or decremented to point to the next item of tabular type data. All four pointer registers (X, Y, U, S) may be used as index registers. · Stack Pointer (U, SI The Hardware Stack Pointer (S) is used automatically by the processor during subroutine calls and interrupts. The User Stack Pointer (U) is controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. The U-register is frequently used as a stack marker. Both Stack Pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push and Pull instructions. This allows the HD6809E to be used efficiently as a stack processor, greatly enhancing its ability to support higher level languages and modular programming. (NOTE) The stack pointers of the HD6809E point to the top of the stack, in contrast to the HD6800 stack pointer, which pointed to the next free location on stack. · Program Counter (PC) The Program Counter is used by the processor to point to the address of the next instruction to be executed by the processor. Relative Addressing is provided allowing the Program Counter to be used like an index register in some situations. · Condition Code Register (CC) The Condition Code Register defines the state of the processor at any given time. See Figure 6. E F H Carry Overflow '----Zero - - - - - Negative ' - - - - - - - IRQ Mask ~-------Half Carry - - - - - - - - - FIRQ Mask ' - - - - - - - - - - - E n t i r e Flag Figure 6 Condition Code Register Format " CONDITION CODE REGISTER DESCRIPTION · Bit 0 (C) Bit 0 is the carry flag, and is usually the carry from the binary ALU. C is also used to represent a 'borrow' from subtract like instructions (CMP, NEG, SUB, SBC) and is the complement of the carry from the binary ALU. · Bit 1 (VI Bit I is the overflow flag, and is set to a one by an operation which causes a signed two's complement arithmetic overflow. This overflow is detected in an operation in which the carry from the MSB in the ALU does not match the carry from the MSB-1. · Bit 2 (Z) Bit 2 is the zero flag, and is set to a one if the result of the previous operation was identically zero. · Bit3 (N) Bit 3 is the negative flag, which contains exactly the value of the MSB of the result of the preceding operation. Thus, a negative two's-complement result will leave N set to a one. 120 @HITACHI Hitachi America Ltd, · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · Bit 4 (I) Bit 4 is the IRQ mask bit. The processor will not recognize interrupts from the TR<) line if this bit is set to a one. NM!, FIRQ, IRQ, RES and SWI all set I to a one; SWl2 and SWl3 do not affect I. · Bit5 IHI Bit 5 is the half-carry bit, and is used to indicate a carry from bit 3 in the ALU as a result of an 8-bit addition only (ADC or ADD). This bit is used by the DAA instruction to perform a BCD decimal add adjust operation. The state of this flag is undefined in all subtract-like instructions. · Bit& (Fl Bit 6 is the FIRQ mask bit. The processor will not recognize interrupts from the FIRQ line if this bit is a one. NM!, FIRQ, SWI, and RES all set F to a one. IRQ, SWl2 and SWl3 do not affect F. · Bit 7 (E) Bit 7 is the entire flag, and when set to a one indicates that the complete machine state (all the registers) was stacked, as opposed to the subset state (PC and CC). The E bit of the stacked CC is used on a return from interrupt {RTI) to determine the extent of the unstacking. Therefore, the current E left in the Condition Code Register represents past action. · HD6809E MPU SIGNAL DESCRIPTION · Power (Vss. Vee) Two pins are used to supply power to the part: Vss is ground or 0 volts, while Vee is +5.0 V ±5%. · Address Bus (A0 - A15 I Sixteen pins are used to output address information from the MPU onto the Address Bus. When the processor does not require the bus for a data transfer, it will output address FFFF 16 , R/W = "High", and BS = "Low"; this is a "dummy access" or VMA cycle. All address bus drivers are made highimpedance when output Bus Available (BA) is "High" or when TSC is asserted. Each pin will drive one Schottky TTL load or four LS TTL loads, and 90 pF. Refer to Figures l and 2. · Data Bus (D0 - D, I These eight pins provide communication with the system bi-directional data bus. Each pin will drive one Schottky TTL load or four LS TTL loads, and 130 pF. · Read/Write (R/W) This signal indicates the direction of data transfer on the data bus. A "Low" indicates that the MPU is writing data onto the data bus. R/W is made high impedance when BA is "High" or when TSC is asserted. Refer to Figures 1 and 2. · RES A "Low" level on this Schmitt-trigger input for greater than one bus cycle will reset the MPU, as shown in Figure 7. The Reset vectors are fetched from locations FFFE16 and FFFF16 (Table l) when Interrupt Acknowledge is true, {BA · BS = 1). During initial power-on, the Reset line should be held "Low" until the clock input signals are fully operational. Because the HD6809E Reset pin has a Schmitt-trigger input with a threshold voltage higher than that of standard peripherals, a simple R/C network may be used to reset the entire system. This higher threshold voltage ensures that all peripherals are out of the reset state before the Processor. Table 1 Memory Map for Interrupt Vectors Memory Map for Vector Locations MS LS FFFE FFFC FFFA FFFB FFF6 FFF4 FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF2 FFF3 FFFO FF Fl Interrupt Vector Description RES NMI SWI iRQ FIRQ SWl2 SWl3 Reserved · HALT A "Low" level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. When halted, the BA output is driven "High" indicating the buses are high impedance. BS is also "High" which indicates the processor is in the Halt state. While halted, the MPU will not ~nd to external real-time requests (FIRQ, IRQ) although NMI or RES will be latched for later response. During the Halt state Q and E should continue to run normally. A halted state (BA · BS = l) can be achieved by pulling HALT "Low" while RES is still "Low". See Figure 8. · Bus Available, Bus Status (BA, BS) The Bus Available output is an indication of an internal control signal which makes the MOS buses of the MPU high impedance. When BA goes "Low", a dead cycle will elapse before the MPU acquires the bus. BA will not be asserted when TSC is active, thus allowing dead cycle consistency. The Bus Status output signal, when decoded with BA, represents the MPU state {valid with leading edge of Q). MPU State BA BS 0 0 0 0 1 MPU State Definition Normal (Running) Interrupt or RESET Acknowledge SYNC Acknowledge HALT Acknowledge Interrupt Acknowled~ indicated during both cycles of a hardware-vector-fetch (RES, NMI, FIRQ, IRQ, SWI, SWl2, SW13). This signal, plus decoding of the lower four address lines, can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device. See Table I. Sync Acknowledge is indicated while the MPU is waiting for external synchronization on an interrupt line. Halt Acknowledge is indicated when the HD6809E is in a Halt condition. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 121 ::c I\) 0 m I\) OD 0cmo sI · 0 ~ )> 3 CD r;· a"c':. 0""'' 0 cQ. l@· CD ~ :I ~ :::J c: CD en C') -"' :I :::J '-0 5""' (") )> ."901' ~ ..0s... ""a,'' 0"0 ' E Q RES Address Data r n R/W New PCH New PCL li'MA 1st Opcode ~ 'uy-A--1\-J BA ~~~~~~~~~~~~~~~~~~ T BS AVMA BUSY LIC New PCH New PCL 'i7MA (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High"= V IHmin and logic "Low"= V 1Lmax unless otherwise specified . Figure 7 RES Timing I ::I' ~ :!: )> 3 ~ Ci" ."~' N N 0 0 c2. l@· ~ "~' "'c::::> ::c "' en 0 "':::> ::c '0 (}) ~ () )> CD ."~' ~ 0 El w-I> ~ w 0 0 N w 2nd to Last Last Cycle Cycle of of Current Current Dead Inst. I Inst. I Cycle Halted Dead Instruction Instruction Dead Cycle I Fetch I Execute I Cycle Halted a E HA[T Addren Bus R/W BA BS Data Bus AVMA ~~-----~ \ LIC Fetch Execute Instruction Opcode I '-----~- (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High''= V IHmln and logic "Low''= ViLmax unless otherwise specified. Figure 8 HALT and Single Instruction Execution for System Debug :cI: O> 00 0co m · Non Maskable Interrupt (NMI)* A negative transition on this input requests that a non- maskable interrupt sequence be generated. A non-maskable interrupt cannot be inhibited by the program, and also has a higher priority than FIRQ, IRQ or software interrupts. During recognition of an NMI, the entire machine state is saved on the hardware stack. After reset, an NMr will not be recognized until the first program load of the Hardware Stack Pointer (S). The pulse width of NMr low must be at least one E cycle. If the NMI input does not meet the minimum set up with respect to Q, the interrupt will not be recognized until the next cycle. See Figure 9. · Fast-lnterruPt Request (FIRQ)* A "Low" level on this input pin will initiate a fast interrupt sequence, provided its mask bit (F) in the CC is clear. This sequence has priority over the standard Interrupt Request (iRQ), and is fast in the sense that it stacks only the contents of the condition code register and the program counter. The interrupt service routine should clear the source of the interrupt before doing an RTI. See Figure 10. · Interrupt Request (IRQ)* A "Low" level input on this pin will initiate an Interrupt Request sequence provided the mask bit (I) in the CC is clear. Since IRQ stacks the entire machine state it provides a slower response to interrupts than FIRQ. IRQ also has a lower priority than FIRQ. Again, the interrupt service routine should clear the source of the interrupt before doing an RTL See Figure 9. · NMI, F'TRQ, and fRQ requests are sampled on the falling edge of Q. One cycle is required for synchronization before these interrupts are recognized The pending interrupt(s) will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If IRQ and FIRQ do not remain "Low" until completion of the current instruction they may not be recognized. However, NMI is latched and need only remain "Low" for one cycle. · Clock Inputs E, Q E and Q are the clock signals required by the HD6809E. Q must lead E; that is, a transition on Q must be followed by a similar transition on E after a minimum delay. Addresses will be valid from the MPU, tAo after the falling edge of E, and data will be latched from the bus by the falling edge of E. While the Q input is fully TTL compatible, the E input directly drives internal MOS circuitry and, thus, requires ·levels above normal TTL levels. This approach minimizes clock skew inherent with an internal buffer. Timing and waveforms for E and Q are shown in Figures I and 2 while Figure 11 shows a simple clock generator for the HD6809E. · BUSY Busy will be "High" for the read and modify cycles of a read- modify-write instruction and during the access of the first byte of a double-byte operation (e.g., LDX, STD, ADDD). Busy is also "High" during the first byte of any indirect or other vector fetch (e.g., jump extended, SWI indirect etc.). In a multi-processor system, busy indicates the need to defer the rearbitration of the next bus cycle to insure the integrity of the above operations. This difference provides the indivisible memory access required for a "test-and-set" primitive, using any one of several read-modify-write instructions. Busy does not become active during PSH or PUL operations. A typical read-modify-write instruction (ASL) is shown in Figure 12. Timing information is given in Figure 13. Busy is valid tco after the rising edge of Q. · AVMA AVMA is the Advanced VMA signal and indicates that the MPU will use the bus in the following bus cycle. The predictive nature of the AVMA signal allows efficient shared-bus multiprocessor systems. AVMA is "Low" when the MPU is in either a HALT or SYNC state. AVMA is valid tco after the rising edge ofQ. · LIC LIC (Last Instruction Cycle) is "High" during the last cycle of every instruction, and its transition from "High" to "Low" will indicate that the first byte of an opcode will be latched at the end of the present bus cycle. LIC will be "High" when the MPU is Halted at the end of an instruction, (i.e., not in CWAI or RESET) in SYNC state or while stacking during interrupts. LIC is valid tco after the rising edge of Q. · TSC TSC (Three-State Control) will cause MOS address, data, and R/W buffers to assume a high-impedance state. The control signals (BA, BS, BUSY, AVMA and LIC) will not go to the high-impedance state. TSC is intended to allow a single bus to be shared with other bus masters (processors or DMA controllers). While E is "Low", TSC controls the address buffers and R/W directly. The data bus buffers during a write operation are in a high-impedance state until Q rises at which time, if TSC is true, they will remain in a high-impedance state. If TSC is held beyond the rising edge of E, then it will be internally latched, keeping the bus drivers in a high-impedance state for the remainder of the bus cycle. See Figure 14. · MPU Operation During normal operation, th.e MPU fetches an instruction from memory and then executes the requested function. This sequence begins after RES and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An interrupt or HALT input can also alter the normal execution of instructions. Figure 15 illustrates the flow chart for the HD6809E. 124 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 :i:: ~ =. )> 3 "~'· Ill ~ I\) c;I\) 0 o2. i@· -~"' :I g" ~ en 0 gi :I c... 0 ~ ~ ~ ~ ~ !.E.. ~ O:> "g ' N (11 Last Cycle of Current Instruction Instruction Fetch i - - - - 1 - - - - - - - - - - - - - - - - - - l n t e r r u p t Stacking and Vector Fetch Sequence ------------------i--~o-! l··m-2 · 1 m-1j ·· m ·1·m+1 ·1 m+2 ·1·m+3··1·m+4 ·1 m+5 ·1m+6 ·1·m+ 7·1m+8··1·m+ 9··1m· +10jm+11jm+ · ·· 12··1m +13m+ I· 14jm+ · 15m+ ·I· 16 m+ 1· 17jm+18 ·· ·!· n j n+1 j ·· · E a Data \7MA PCL PCH UL UH YL YH XL XH DP 8 A CC VMA New New l71ilA PCH PCL R/W~ \ I BBS :Ax::::::x:x:::::>:. ::::x::::>.~~-~~~-~--~~~~~~~~~-I~---\-,__ --_-_-_ -~_ ABUVLSIYCM-:A:::~:-),~,_-~~~~~;;;~===================='.'.'.~~~~~~~~~~~~~~~I~~\~~~~~~ t::=. E {NOTE) Waveform measurements for all inputs and outputs are specified at logic "High"= ViHmin and logic "Low"= V1Lmax unless otherwise specified. E clock shown for reference only. Figure 9 TAO and NMI Interrupt Timing J: 0 O> CX) 0 CmD N Ol I ~ :!: )> 3 ~c;· r"a': l'IJ "0 ' 0 oQ. f@· <t> -~ ~ ffi :I ~ en C') ~ :I <0 ~ () )> ""~ ' ' ~ $ t; 01 00 8"' Last Cycle of Current Instruction I· ·I Interrupt Stacking and Vector Fetch Sequence :i::: 0 a> ~ Instruction cmo + Fetch ·I E a t~cfr~~~~ Address Bus FIRQ V~IL tpcs PC PC FFFF SP-1 SP-2 SP-3 $FFFF $FFF6 $FFF7 $FFFF Now PC New PC + 1 Data 'lMA PCL PCH cc VMA New PCH New PCL BA BS AVMA ~~ LIC E / -- ~ ~ (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High"= V IHmin and logic "Low"= V ILmax unless otherwise specified. E clock shown for reference only. Figure 10 Fl RQ Interrupt Timing ~-------------------1 I +5V I I I I I I IMRD I I I IL ___ _ HD6809E 74LS04 +5V NOTE: If optional circuit is not included the CLR and PRE inputs of U2 and UJ must be tied high. Figure 11 HD6809E Clock Generator Memory Location PC-+ $0200 $0201 $0202 $0203 $0204 Memory Contents $68 $9F $63 $00 Contents Description ASL Indexed Opcode Extended Indirect Postbyte Indirect Address Hi·Byte Indirect Address Lo·Byte Next Main Instruction $6300~ Effective Address Hi·Byte $6301~ Effective Address Lo·Byte '""~ .....~. Figure 12 Read Modify Write Instruction Example (ASL Extended Indirect) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 127 I\.) 00 Is: () :!: )> 3 o~ · ."r': !"- 0""'' 0 oQ_ i@· "~' :c ~ :c:> "' :c (/) C') ~ '0-- 5"0' 0 )> ."~' ~ -:;;: 0 .$ -I> "z:' "00 ' :I: Last Cycle of c 0) Current Instr. co I· m-1 I m I m+1 I m+2 ·I· m+3 · I· m+4 ·I· m+5 ·I· m+6 · I· m+7 I· m+ 8 ·I m+9 ·I m+10 I n · I 0 CmD E a Address Data BUSY LIC _ __,! AVMA E (NOTE) Waveform measurements for all inputs and outputs are specified at logic ''High"= V IHmin and logic ''Low''= V ILmax unless otherwise specified. Figure 13 BUSY Timing (ASL Extended Indirect Instruction) (NOTES) Data will be asserted by the MPU only during the interval while R/W is "Low" and E or Q is "High". Waveform measurements for all inputs and outputs are specified at logic "High.. · V IHmln and logic .. Low"· V 1Lmax unless otherwise specified. Figure 14 TSC Timing I ~ ~ l> 3 ::!. "'" "'!p:.: ~ 0 0 c0 l@· -1D ~ :I "~' ~ en (') ~ :I '0 ~ ~ ~ ~ ~ .!E i 0 "co' m Sea. 0--DPR 1-F,I 1~R,W C~film Logic -Di-ss-m-l'riD-lf (NOTES) 1. Asserting RES will result in entering the reset sequence from any point in the flow chart. 2. BUSY is "High" during first vector fetch cycle. CWAI HD6809E Interrupt Structure Bus State BA BS Running 0 0 Interrupt or Reset Acknowledge 0 1 Sync Acknowledge 1 0 Halt Acknowledge 1 1 :I: 0 O> ~ Figure 15 Flowchart for HD6809E Instruction cmo · ADDRESSING MODES The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The HD6809E has the most complete set of addressing modes available on any microcomputer today. For example, the HD6809E has 59 basic instructions; however, it recognizes 1464 different variations of instructions and addressing modes. The addressing modes support modern programming techniques. The following addressing modes are available on the HD6809E: ( 1) Implied (Includes Accumulator) (2) Immediate (3) Extended (4) Extended Indirect (5) Direct (6) Register (7) Indexed Zero-Offset Constant Offset Accumulator Offset Auto Increment/Decrement (8) Indexed Indirect (9) Relative (10) Program Counter Relative · Implied (Includes Accumulator) In this addressing mode, the opcode of the instruction contains all the address information necessary. Examples of Implied Addressing are: ABX, DAA, SWI, ASRA, and CLRB. · Immediate Addressing In Immediate Addressing, the effective address of the data is the location immediately following the opcode (i.e., the data to be used in the instruction immediately follows the opcode of the instruction). The HD6809E uses both 8 and 16-bit immediate values depending on the size of argument specified by the opcode. Examples of instructions with immediate Addressing are: LDA #$20 LDX #$FOOO LDY #CAT (NOTE) # signifies immediate addressing, $ signifies hexadecimal value. · Extended Addressing In Extended Addressing, the contents of the two bytes im- mediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of Extended Addressing include: LDA CAT STX MOUSE LDD $2000 · Ex111nded Indirect As a special case of indexed addressing (discussed below), one level of indirection may be added to Extended Addressing. In Extended Indirect, the two bytes following the postbyte of an Indexed instruction contain the address of the data. LDA [CAT] LDX [$FFFE] STU [DOG] · Direct Addressing Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. This byte specifies the lower 8 bits of the address to be used. The upper 8 bits of the addres.; are supplied by the direct page register. Since only one byte of address is required in direct addressing, this mode requires less memory and executes faster than extended addressing. Of course, only 256 locations (one page) can be accessed without redefining the contents of the DP register. Since the DP register is set to $00 on Reset, direct addressing on the HD6809E is compatible with direct addressing on the HD6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are: LDA $30 SETDP $10 (Assembler directive) LDB $1030 LDD <CAT (NOTE) < is an assembler directive which forces direct addressing. · Register Addressing Some opcodes are followed by a byte that defines a register or set of registers to be used by the instruction. This is called a postbyte. Some examples of register addressing are: TFR X, Y Transfer X into Y EXG A, B Exchanges A with B PSHS A, B, X, Y Push Y, X, Band A onto S PULU X, Y, D Pull D, X, and Y from U · Indexed Addressing In all indexed addressing, one of the pointer registers (X, Y, U, S, and sometimes PC) is used in a calculation of the effective address of the operand to be used by the instruction. Five basic types of indexing are available and are discussed below. The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode as well as the pointer register to be used. Figure 16 lists the legal formats for the postbyte. Table 2 gives the assembler form and the number of cycles and bytes added to the basic values for indexed addressing for each variation. Post-Byte Register Bit · · 7 6 3 21 0 0 RR d d d d d -Indexed Addressing EA · ,R + 5 Bit Offset 1 RR 0 0 0 0 0 ,R+ 1 RR I 0 0 0 1 ,R ++ 1 RR 0 0 0 1 0 ,-R 1 RR I 0 0 1 1 .--R 1 RR I 0 1 0 0 EA·,R+OOffset 1 RR I 0 1 0 1 EA · ,R + ACCB Offset 1 RR I 0 1 1 0 EA · ,A + ACCA Offset 1 RR I 1 0 0 0 EA·,R+SBitOffset 1 1 1 1 .. ..R R I RR I I I 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 EA· ,R + 18 Bit Offset EA· ,R + 0 Offset EA·!'C +BBit Offset EA · ,PC + 16 Bit Offset -1 R R I 1 1 1 1 EA · (,Address) L _ Addressing Mode Field ~----- Indirect Field (Sigh bit when b7 '"'0) x ~-------Register Field, RR 00· 1t ·Don't Care 01 ·Y .. Id "'0fftet:Bit ' 0 · Non Indirect 1 ·Indirect 10-u 11 -s Figure 16 Index Addressing Postbyte Register Bit Assignments @HITACHI 130 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809E Table 2 Indexed Addressing Mode Type Constant Offset From R (2's Complement Offsets) Accumulator Offset From R (2's Complement Offsets) Auto Increment/Decrement R Constant Offset From PC (2's Complement Offsets) Extended Indirect Forms No Offset 5 Bit Offset 8 Bit Offset 16 Bit Offset A Register Offset B Register Offset D Register Offset Increment By 1 Increment By 2 Decrement By 1 Decrement By 2 8 Bit Offset 16 Bit Offset 16 Bit Address Non Indirect Assembler Form Post byte OP Code ,R 1 RR00100 n, R ORRnnnnn n,R 1 RR01000 n, R 1 RR01001 A, R 1 RR00110 B,R 1 RR00101 D,R 1 RR01011 ,R + 1RROOOOO ,R ++ 1 RR00001 , -R 1 RR00010 ,- - R 1RROOOl1 n, PCR 1xx01100 n,PCR - 1xx01101 - + + -# 0 0 1 0 1 1 4 2 1 0 1 0 4 0 2 0 3 0 2 0 3 0 1 1 5 2 -- R=X,Y,UorS RR: x = Don't Care OO=X 01 =y 10 =u 11 =s ~and# indicate the number of additional cycles and bytes for the particular variation. Indirect Assembler Form Postbyte OP Code [,Rl 1 RR10100 defaults to 8-bit [n, R] 1RR11000 [n, R] 1RR11001 [A,R] 1RR10110 [B, R] 1 RR10101 [D, RI 1RR11011 not allowed [,R ++] 1RR10001 not allowed [, - - R] 1 RR10011 [n,PCR] 1xx11100 [n, PCRJ 1xx11101 [n] 10011111 -+ + # 3 0 4 1 7 2 4 0 4 0 7 0 6 0 6 0 4 1 8 2 5 2 Zero-Offset Indexed In this mode, the selected pointer register contains the effective address of the data to be used by the instruction. This is the fastest indexing mode. Examples are: LDD O,X LDA S Constant Offset Indexed In this mode, a two's-complement offset and the contents of one of the pointer registers are added to form the effective address of the operand. The pointer register's initial content is unchanged by the addition. Three sizes of offsets are available: 5-bit (-16 to +15) 8-bit (-128 to +127) 16-bit (-32768 to +32767) The two's complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and cycles. The two's complement 8-bit offset is contained in a single byte following the postbyte. The two's complement 16-bit offset is in the two bytes following the postbyte. In most cases the programmer need not be concerned with the size of this offset since the assembler will select the optimal size automatically. Examples of constant-offset indexing are: LDA 23,X LDX -2,S LDY 300,X LDU CAT,Y Accumulator-Offset Indexed This mode is similar to constant .offset indexed except that the two's-complement value in one of the accumulators (A, B or D) and the contents of one of the pointer registers are added to form the effective address of the operand. The contents of both the accumuiator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time. Some examples are: LDA B,Y LDX D,Y LEAX B,X Auto Increment/Decrement Indexed In the auto increment addressing mode, the pointer register contains the address of the operand. Then, after the pointer register is used it is incremented by one or two. This addressing mode is useful in stepping through tables, moving data, or for the creation of software stacks. In auto decrement, the pointer register is decremented prior to use as the address of the data. The use of auto decrement is similar to that of auto increment; but the tables, etc., are scanned from the high to low addresses. The size of the increment/decrement can be either one or two to allow for tables of either 8- or 16-bit data to be accessed and is selectable by the programmer. The pre- @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 131 decrement, post-increment nature of these modes allow them to be used to create additional software stacks that behave identically to the U and S stacks. Some examples of the auto increment/decrement addressing modes are: LDA ,X+ STD ,Y++ LDB ,-Y LDX ,--S Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the effective address. Consider the following instruction: STX 0, X + + (X initialized to 0) The desired result is to store a 0 in locations $0000 and $0001 then increment X to point to $0002. In reality, the following occurs: 0-+temp calculate the EA; temp is a holding register x+2 .... x perform autoincrement X-+ (temp) do store operation · Indexed Indirect All of the indexing modes with the exception of auto increment/decrement by one, or a ±4-bit offset may have an additional level of indirection specified. In indirect addressing, the effective address is contained at the location specified by the contents of the Index Register plus any offset. In the example below, the A accumulator is loaded indirectly using an effective address calculated from the Index Register and an offset. Before Execution A= XX (don't care) X= $FOOO $0100 LDA ($10,X] EA is now $F010 $F010 $Fl $FOil $50 $F 150 is now the new EA $Fl50 $AA After Execution A= $AA (Actual Data Loaded) X= $FOOO All modes of indexed indirect are included except those which are meaningless (e.g., auto increment/decrement by 1 indirect). Some examples of indexed indirect are: LDA [,X] LDD (10,S] LDA [B, Y] LDD [,X++] · Relative Addressing The byte(s) following the branch opcode is (are) treated as a signed offset which may be added to the program counter. If the branch condition is true then the calculated address (PC + signed offset) is loaded into the program counter. Program execution continues at the new location as indicated by the PC; short (1 byte offset) and long (2 bytes offset) relative addressing modes are available. All of memory can be reached in long relative addressing as an effective address is interpreted modulo 216 · Some examples of relative addressing are: BEQ CAT (short) BGT DOG (short) CAT DOG LBEQ LBGT RAT (long) RABBIT (long) RAT NOP RABBIT NOP · Program Counter Relative The PC can be used as the pointer register with 8 or 16-bit signed offsets. As in relative addressing, the offset is added to the current PC to create the effective address. The effective address is then used as the address of the operand or data. Program Counter Relative Addressing is used for writing position independent programs. Tables related to a particular routine will maintain the same relationship after the routine is moved, if referenced relative to the Program Counter. Examples are: LDA CAT,PCR LEAX TABLE, PCR Since program counter relative is a type of indexing, an additional level of indirection is available. LDA (CAT, PCR] LDU [DOG, PCR] · HD6809E INSTRUCTION SET The instruction set of the HD6809E is similar to that of the HD6800 and is upward compatible at the source code level. The number of opcodes has been reduced from 72 to 59, but because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) has risen from 197 to 1464. Some of the new instructions are described in detail below: · PSHU/PSHS The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register, or set of registers with a single instruction. · PULU/PULS The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following the push or pull opcode determines which register or registers are to be pushed or pulled. The actual PUSH/PULL sequence is fixed; each bit defines a unique register to push or pull, as shown in below. PUSH/PULL POST BYTE cc A ----8 -----DP ------x ~------ y · - - - - - - - - SIU - - - - - - - - - PC <- Pull Order Push Order -+ PC UYXDPBACC FFFF ....... <-- increasing memory address ....... 0000 PC SYXDPBACC 132 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809E · TFR/EXG Within the HD6809E, any register may be transferred to or exchanged with another of like-size; i.e., 8-bit to 8-bit or 16-bit to 16-bit. Bits 4-7 ofpostbyte define the source register, while bits 0-3 represent the destination register. These are denoted as follows: 0000-D 0001 -X 0010-Y 0011- u 0100 -S 0101 -PC 1000-A 1001 - B 1010 - cc 1011 -DP (NOTE) All other combinations are undefined and INVALID. TRANSFER/EXCHANGE POST BYTE Fo~Rc~ Io+++NI · LEAX/LEAY/LEAU/LEAS The LEA (Load Effective Address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction are illustrated in Table 3. The LEA instruction also allows the user to access data in a position independent manner. For example: LEAX MSG 1, PCR LBSR PDATA (Print message routine) MSG! FCC 'MESSAGE' This sample program prints: 'MESSAGE'. By writing MSG!, PCR, the assembler computes the distance between the present address and MSGI. This result is placed as a constant into the LEAX instruction which will be indexed from the PC value at the time of execution. No matter where the code is located, when it is executed, the computed offset from the PC will put the absolute address of MSG 1 into the X pointer register. This code is totally position independent. The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the autoincrement and autodecrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows: LEAa, b+ (any of the 16-bit pointer registers X, Y, U or Smay be substituted for a and b.} l. b-+ temp (calculate the EA) 2. b + I -+ b (modify b, postincrement) 3. temp-+ a (load a) LEAa,-b I. b - 1 -+temp (calculate EA with predecrement) 2. b - I _,. b (modify b, predecrement) 3. temp -+a (load a) Autoincrement-by-two and autodecrement-by-two instructions work similarly. Note that LEAX, X+ does not change X, however LEAX, -X does decrement X. LEAX I, X should be used to increment X by one. Instruction LEAX 10, X LEAX 500, X LEAY A. Y LEAY D, Y LEAU -10, U LEAS -10, S LEAS 10, S LEAX 5, S Table 3 LEA Examples Operation X + 10 --> X X + 500--> X Y + A _,. Y Y + D ->Y u -10 _,. u S-10-->S s + 10 _,. s S+ 5 _,. X Comment Adds 5-bit constant 10 to X Adds 16-bit constant 500 to X Adds 8-bit A accumulator to Y Adds 16-bit D accumulator to Y Subtracts 10 from U Used to reserve area on stack Used to 'clean up' stack Transfers as well as adds · MUL Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D accumulator. This unsigned multiply also allows multipleprecision multiplications. long and Short Relative Branches The HD6809E has the capability of program counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8 or 16-bit signed offset is added to the value of the program counter to be used as the effective address. This allows the program to branch anywhere in the 64 k memory map. Position independent code can be easily generated through the use of relative branching. Both short (8-bit) and long (16-bit) branches are available. ·SYNC After encountering a Sync instruction, the MPU enters a Sync state, stops processing instructions and waits for an interrupt. If the pending interrupt is non-maskable (NMI) or maskable (FIRQ, IRQ) with its mask bit (F or I) clear, the processor will clear the Sync state and perform the normal interrupt stacking and service routine. Since FIRQ and IRQ are not edge-triggered, a low level with a minimum duration of three bus cycles is required to assure that the interrupt will be taken. If the pending interrupt is maskable (FIRQ, IRQ) with its mask bit (F or I) set, the processor will clear the Sync state and continue processing by executing the next inline instruction. Figure 17 depicts Sync timing. Software Interrupts A Software Interrupt is an instruction which will cause an interrupt, and its associated vector fetch. These Software Interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SW! are available on this HD6809E, and are prioritized in the following order: SWI, SWI2, SWI3. 16-Bit Operation The HD6809E has the capability of processing 16-bit data. These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes and pulls. · CYCLE-BY-CYCLE OPERATION The address bus cycle-by-cycle performance chart illustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the HD6809E. Each instruction begins with an opcode fetch. While that opcode is being internally decoded, the next program byte is always fetched. (Most instructions will use the next byte, so this @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 133 technique considerably speeds throughput.) Next, the operation of each opcode will follow the flow chart. VMA is an indication of FFFF16 on the address bus, R/W ="High" and BS ="Low". The following examples illustrate the use of the chart; see Figure 18. Example I: LBSR (Branch Taken) Before Execution SP= FOOO $8000 LBSR CAT $AOOO Cycle# 1 2 3 4 5 6 7 8 9 CAT Address 8000 80()1 8002 FFFF FFFF FFFF FFFF EFFF EFFE CYCLE-BY-CYCLE FLOW Data RJW Description 17 1 Opcode Fetch IF I Offset High Byte FD I Offset Low Byte · I WA.Cycle · I WA Cycle · · 1 -WA Cycle I WA Cycle 03 () Stacie Low Order Byte of Return Address 80 () Stacie High Order Byte of Return Address Example 2: DEC (Extended) $8000 DEC $AOOO FCB $AOOO $80 CYCLE-BY.CYCLE FLOW Cycle# Address Data R/W Description 1 8000 7 A I Opcode Fetclt 2 8001 AO I Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 FFFF · I WA Cycle 5 AOOO 80 I Read the Data 6 FFFF · I WA.Cycle 7 AOOO 7F () Store the Deere, mented Data * The data bus has the data at that particular address. · HDll809E ll\ISTRUCTION SET TABLES The instructions of the HD6809E have been broken down into five differertt categories. They are as follows: 8-Bit operation (Table 4) 16-Bit operation (Table 5) Index regiSter/stack pointer instructions (Table 6) Relative branches (long or short) (Table 7) Miscellaneous instructions (Table 8) HD6809E instruction set tables and Hexadecimal Values of instructions are shown in Table 9 and Table I0. 134 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 :i:: ~ '1: )> 3 CD 5· I» ~ ~ 0 Q c0 t@· '~° :c ~ ~ CD - :c (/) C') ~ <- ~ ~ ~ ~ j ffi § (.,) U'I Last Cycle Sync of Previous Opcode 11nstructio'n1 Fetch · I ·Execute I Sync Ac\knowledge Last Cycle of Sync Instruction E a Address Oata R/W~- - - - - - , \ ~ I I I 0 BA I ~ I AVMA~_ _ _ _ _ _ _ _ _\.l.__ _ _ _ _~ I I L i e rI- - ' \\...____]I --------------__J ~fltpcf rim t ' i l FNiRMGI '1" ' - - - - -j; - I - - - - - - - - - - - . ~-------- ~ '( See Note 1 rIt1-: See:N:otet2 p=~:--~:;_~~~~~~~~~~~~ (NOTES) 1. If th8 associated mask bit is set when the interrupt is r~ested. UC will go "Low" and this Cycle will be an instruction fetch from address locatlon PC + 1. However, if the interrupt is accepted (NMI or an unmasked FlRO or TRCi) LIC will remain ''High'' and interrupt processing will start with this cycle as (m) o~re 9 and 10 (Interrupt Timing). 2. If mask bits are clear, TRn and "FT"RO must be held "Low'' for three cycles to guarantee that interrupt will be taken, although only one cycle is necessary to bring the processor out of SYNC. 3. Waveform measurements for all inputs and outputs are specified at logic "High"= V1Hmin and logic "Low"= V1Lmax unless otherwise specified. Figure 17 SYNC Timing c::c O> gCIO m (A) en ::c =~ . )> 3 g"'· ~ ~ 0 0 -0c}@· CD" -~ ::c "~' ~ (/) ~ :0:c ~'- ~ c~".n' 1... a :c 0 ( Fetch ) I O> gCl) Opcode (Fetch) m Long Bra,n...c..h.. Short Branch Immediate and Implied Opcode+ VMA _I VMA Opcode+ _I VMA N VMA Offset ACCA ACCB R + 5 Bit R +B Bit PC+BBit iiMA Auto Auto Inc/Dec Inc/Dec bv1 bv2 VMA V¥A VMA · I VMA PC + Extended No 16 Bits Indirect Offset Opcode+ Opcode+ r+ + I I ~ ·VMA VMA VMA ~ ·= WA Opcode! VMA N VMA I VMA I Steck Write I Steck Write Operation (Following Pages) Fetch (NOTE) 1. Busy = "High" during access of first byte of double byte immediate load. 2. Write operation during store instruction. Busy = "High" during first two cycles of a double-byte access and the fim cycle of read-modify-write eccess. 3. AVMA is asserted on the cycle befora a VMA cycle. Figure 18 Address Bus Cycle-by.Cycle Performance s:r· ":=: .,)> 3 5· O> .i:;: fl- "0"'' 0 .oQ,. l@· ~ :I ~ :c::i "' (fl C') -:I O> ::i '0-- (J) !" () )> "'~°' -;:;: 0 !E -wI> ""0 w ' ' 0 w -.J Implied Page I ASLA ASLB ASRA ASRB CLRA CLRB COMA COMB DAA DECA DECB INCA INCB LSLA LSLB LSRA LSRB NEGA NEGB NOP ROLA ROLB RORA RORB SEX TSTA TSTB ABX I VMA ATS TFR EXG VJilA ~ V1D: \lMA STACK (R) STACK (R) VMA I VMA VMA i7MA VMA VMA VMA 111 1 1 PSHU PULU SWI PSHS PULS sw12'1 CWAI I RTI SWl3 I VMA WA -VMA VMA I I VMA VMA I I i7MA VMA I IADDA +-SP I ADDA I STACK (R) i7MA WM I I STACK (W) STACK (W) STACK (W) STACK (W) _ ~AC"" ~AC"" 7 STACK (W) STACK (W) ? b VMA ( } 12 VMA Stack (W) STACK (W) STACK (W) STACK (W) STACK (W) 0 VMA VMA I (Note 3) {stack (Rl} 1~ STACK (W) STACK (W) STACK (W) STACK (W) (Note 3) 0 STACK (W) STACK (W) STACK (W) STACK (W) STACK (W) STACK (W) STACK (W) STACK (W) I I oo ISTACK (R) STACK (R) I ADDA+- SP VMA IVMA ; (Note 4) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) STACK (R) 1 1 VECTOR (H), VECTOR (H), BUSY +-1 BUSY+-1 VECTOR (L), VECTOR (L), BUSY+-0 I BUSY +-0 I l l l VMA VMA ADDA +-SP (NOTES) 1. Stack (W) refers to the following sequence: SP +- SP - 1, then ADDA +-SP with R/W - "Low" Stack (R) refers to the following sequence: ADDA+- SP with R/W- "High", then SP +-SP+ 1. PSHU, PULU instructions use the user stack pointer (i.e., SP= U) and PSHS, PULS use the hardware stack pointer (i.e., SP == S). 2. Vector refers to the address of an interrupt or reset vector (see Table 1). :t 3. The number of stack accesses will vary according to the number of bytes saved, c 4. VMA cycles will occur until an interrupt occurs. ceon Figure 18 Address Bus Cycle-by-Cycle Performance (Continued) 0cmo c.u 00 :c ~ ;!: )> 3 CD 5· ~"' oi.~ 0 0 ;0;; · ~ :I ~ ~ CD - en 0 ~ :I <... ~ () )> <D gU1 i ~"" :c 0 Non Implied , mC» 0cmo ADCA ADCB AODA ADDB ANDA ANDB BITA BITB CMPA CMPB EORA EORB LOA LOB ORA ORB SBCA SBCB STA STB SUBA SUBB LOO LOS LOU LOX LOY AN DCC ORCC ASL ASR CLR COM DEC INC LSL LSR NEG ROL ROR TST ADDO JSR STD CMPD STS CMPS STU CMPU STX CMPX STY CMPV SUBD VMA STACKIWI STACKIWI VMA,BUSV+-1 ADDR+ BUSV+-0 ADDR+ WA VM'A ADDR+ I WA ADDF +IWl _'j , , l 1 t (NOTES) 1. Stack (W) refers to the following sequence: SP+- SP - 1, then ADDR +-SP with R/W ="Low" Stack (RI refers to the following sequence: ADDR +-SP with R/W·"High", then SP+-SP + 1. PSHU, PULU instructions use the user stack pointer (i.e., SP· UI and PSHS, PULS use the hardwate stack pointer !i.e., SP s SI. 2. Vector refers to the add.ress of an interrupt or reset vector 1-· Table 1). 3. The number of stack accesses will vary according to the number of bytes saved. 4. VMA cycles will occur until an interrupt occurs. Figure 18 Address Bus Cycle-by.Cycle Performance (Continued) Mnemonic(s) ADCA, ADCB ADDA,.ADDB ANDA,ANDB ASL,ASLA,ASLB ASR,ASRA,ASRB BITA,BITB CLR,CLRA,CLRB CMPA,CMPB COM, COMA, COMB DAA DEC,DECA,DECB EORA, EORB EXG Rl, R2 INC, INCA, INCB LOA, LOB LSL, LSLA, LSLB LSR, LSRA, LSRB MUL NEG, NEGA, NEGB ORA, ORB ROL, ROLA, ROLB ROR, RORA, RORB SBCA, SBCB STA,STB SUBA, SUBB TST, TSTA, TSTB TFR Rl, R2 Table 4 8-Bit Accumulator and Memory Instructions Operation Add memory to accumulator with carry Add memory to accumulator And memory with accumulator Arithmetic shift of accumulator or memory left Arithmetic shift of accumulator or memory right Bit test memory with accumulator Clear accumulator or memory location Compare memory from accumulator Complement accumultor or memory location Decimal adjust A accumulator Decrement accumulator or memory location Exclusive or memory with accumulator Exchange Rl with R2 (Rl, R2 =A, B, CC, DP) Increment accumulator or memory location Load accumulator from memory Logical shift left accumulator or memory location Logical shift right accumulator or memory location Unsigned multiply (A x B-+ D) Negate accumulator or memory Or memory with accumulator Rotate accumulator or memory left Rotate accumulator or memory right Subtract memory from accumulator with borrow Store accumulator to memory Subtract memory from accumulator Test accumulator or memory location Transfer Rl to R2 (Rl, R2 =A, B, CC, DP) (NOTE) A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS, PULU) instructions. Mnemonic($) ADDO CMPD EXG D, R LOO SEX STD SUBD TFR D, R TFR R,D Table 5 16-Bit Accumulator and Memory Instructions Operation Add memory to D accumulator Compare memory from D accumulator Exchange D with X, Y, S, U or PC Load D accumulator from memory Sign Extend B accumulator into A accumulator Store D accumulator to memory Subtract memory from D accumulator Transfer D to X, Y, S, U or PC Transfer X, Y, S, U or PC to D (NOTE) D may be pushed (1>11lled) to either stack with PSHS, PSHU (PULS, PULUl instNctions. HD6809E ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 139 Mnemonic(s) CMPS,CMPU CMPX,CMPY EXG Rl, R2 LEAS, LEAU LEAX,LEAY LDS,LDU LDX, LDY PSHS PSHU PULS PULU STS,STU STX, STY TFR R1, R2 ABX Mnemonic(s) BEO, LBEO BNE,LBNE BMI, LBMI BPL,LBPL BCS,LBCS BCC,LBCC BVS, LBVS BVC,LBVC BGT,LBGT BGE, LBGE BEO, LBEO BLE,LBLE BLT,LBLT BHI, LBHI BHS, LBHS BEO, LBEO BLS, LBLS BLO,LBLO BSR,LBSR BRA, LBRA BAN, LBRN Table 6 Index Register Stack Pointer Instructions Operation Compare memory from stack pointer Compare memory from index register Exchange D, X, Y, S, U or PC with D, X, Y, S, U or PC Load effective address into stack pointer Load effective address into index register Load stack pointer from memory Load index register from memory Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack Push A, B, CC, DP, D, X, Y, S, or PC onto user stack Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack Pull A, B, CC, DP, D, X, Y, Sor PC from user stack Store stack pointer to memory Store index register to memory Transfer D, X, Y, S, U or PC to D, X, Y, S, U or PC Add B accumulator to X (unsigned) Table 7 Branch Instructions Operation SIMPLE BRANCHES Branch if equal Branch if not equal Branch if minus Branch if plus Branch if carry set Branch if carry clear Branch if overflow set Branch if overflow clear SIGNED BRANCHES Branch if greater (signed) Branch if greater than or equal (signed) Branch if equal Branch if less than or equal (signed) Branch if less than (signed) UNSIGNED BRANCHES Branch if higher (unsigned) Branch if higher or same (unsigned) Branch if equal Branch if lower or same (unsigned) Branch if lower (unsigned) OTHER BRANCHES Branch to subroutine Branch always Branch never 140 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Mnemonic(s) AN DCC CWAI NOP ORCC JMP JSR RTI RTS SWI, SWl2, SWl3 SYNC Table 8 Miscellaneous Instructions Operation AND condition code register AND condition code register, then wait for interrupt No operation OR condition code register Jump Jump to subroutine Return from interrupt Return from subroutine Software interrupt (absolute indirect} Synchronize with interrupt line @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 141 Table 9 HD6809E Instruction Set Table INSTRUCTION/ FORMS IMPLIED - OP # ABX 3A 3 1 ADC' -ADCA ADCB ADD ADDA ADDB ADDO AND ANDA ANDB AN DCC ASL ASLA 48 2 1 ASLS 58 2 1 ASL ASR ASRA 47 2 1 ASRS 57 2 1 ASA ace BCC LBCC BCS BCS LBCS BEQ BGE BEQ LBEQ BGE LBGE BGT BGT LBGT BHI BHI LBHI BHS BHS HD6809E ADDRE$SING MODES DIRECT - OP # - - - EXTENDED IMMEDIATE INDEXED<]) RELATIVE OP # OP # OP # OP ...@ # 99 4 2 89 5 3 S9 2 2 A9 4+ 2+ 09 4 2 F9 5 3 C9 2 2 E9 4+ 2+ 98 4 2 SB 5 3 SB 2 2 AB 4+ 2+ DB 4 2 FS 5 3 CB 2 2 EB 4+ 2+ 03 6 2 F3 7 3 C3 4 3 E3 6+ 2+ 94 4 04 4 2 S4 5 2 F4 5 3 84 2 3 C4 2 1C 3 2 A4 4+ 2+ 2 E4 4+ 2+ 2 08 6 2 7S 7 3 68 6+ 2+ 07 6 2 77 7 3 67 6+ 2+ 24 3 2 10 5(6) 4 24 25 3 2 10 5(6) 4 25 27 3 2 10 5(6) 4 27 2C 3 2 10 5(61 4 2C 2E 3 2 10 5(61 4 2E 22 3 2 10 5(61 4 22 24 3 2 LBHS BIT BLE BLO BITA BITB BLE LBLE BLO LBLO BLS BLS 10 5(61 4 24 95 4 2 85 5 3 B5 2 2 A5 4+ 2+ 05 4 2 F5 5 3 C5 2 2 E5 4+ 2+ 2F 3 2 10 5(6) 4 2F 25 3 2 10 5(61 4 25 23 3 2 LBLS BLT BLT LBLT BMI BMI LBMI BNE BNE LBNE BPL BPL LBPL BRA BRA LSRA 10 5(61 4 23 20 3 2 10 5(6) 4 20 2B 3 2 10 5(61 4 2B 26 3 2 10 5(6) 4 26 2A 3 2 10 5(6) 4 2A 20 3 2 16 5 3 BRN BAN LSRN 21 3 2 10 5 4 21 DESCRIPTION ArU.+N+~Gx1+-1x:E-DA I a+_M+c-s 53 2 10 HNz v c · · · · · I I I I I I I I I I A+M-A I I I I I B+M-B D+M:M+1-D AllM-A B llM-B CCII IMM-CC ·I I I I I I I I I I I 0 · · I t 0 · ·<-t- lt!t-rl ~}QiJIIIID}· (~ <HJ I I I I I I I I (~ I I I I !CffiiTIID.o ") BA M b7 I c~l I .. c 1...lt) I I I I · · · I I I Branch C = 0 Long Branch ·· ·· ·· ·· ·· C=O Branch C = 1 Long Branch c =1 ·· ·· ·· ·· ·· Branch Z=1 Long Branch Z=1 Branch N tD V=O Long Branch NtDV=O ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· · · Branch ZVINtDVl-0 · · · · ·· ·· Long Branch ZVIN tDVl=O · · · · · Branch CVZ=O · · · · · Long Branch CVZ=O Branch C=O Long Branch C=O · · · · · · · · · · Bit Test A (MllAI ·· Bit Test B (M 118) I I 0· I I 0· BranchZVINtDVl·1 · · · · · Long Branch · · · · · ZVIN tDV)·l Branch C·1 Long Branch C=1 ·· ·· ·· ·· ·· Branch CVZ=l Long Branch CVZ=1 · · · · · · · · · · Branch N Q) V= 1 ·· · ·· · ·· Long Branch · · NtDV=l Branch N=l Long Branch N·l ·· ·· ·· ·· ·· Branch Z ·O ~ng Branch Z·O ·· ·· ·· ·· ·· Branch N · 0 Long Branch N·O ·· ·· ·· ·· ·· Branch Always Long Branch/ Always ·· ·· ·· ·· ·· · · · · Branch Never · · · · · Long Branch Never · (to be continued) 142 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6809E ADDRESSING MODES INSi'6':i'U"~ON/ IMPLIED DIRECT EXTENDED IMMEDIATE INDEXEl)Cl' RELATIVE ~O~P~,_~.-#-t~O~P,--~.--#--t-O~P,--~.--#-t-~O~P,--~.--#--t~O~P,--~,-#-t~O~Pc-r--@"'"'"~#, DESCRIPTION esR BSR LeSR eve eve Leve evs evs LBVS 80 7 2 17 9 3 28 3 2 10 5(6) 4 28 29 3 2 10 5(6) 4 29 Branch to Subroutine Long Branch to Subroutine Branch V = 0 Long Branch V=O Branch V = 1 Long Branch V=1 5 3 2 1 0 HNZ VC ..· ..· ..· ..· ..· · · · · · ·· ·· ·· ·· ·· CLR CLRA CLRB CLR 4F 2 5F 2 OF 6 2 7F 7 3 6F 6+ 2+ O-A o- B O-M · 0 10 0 · 0 10 0 · 0100 CMP CMPA CMPB CMPD CMPS CMPU CMPX CMPY 91 4 2 Bl 5 3 Bl 2 2 Al 4+ 2+ 01 4 2 Fl 5 3 Cl 2 2 El 4+ 2+ 10 7 3 10 8 4 10 5 4 10 7+ 3+ 93 B3 B3 A3 11 7 3 11 8 4 11 5 4 11 7+ 3+ 9C BC BC AC 11 7 3 11 B 4 11 5 4 11 7+ 3+ 93 83 B3 A3 9C 6 2 BC 7 3 BC 4 3 AC 6+ 2+ 10 7 3 10 8 9C BC 4 10 5 BC 4 10 7+ 3+ AC Compare M from A @ I I I I Compare M from B @ I I I I Compare M: M + 1 · I I I I fromD Compare M: M + 1 · I I I l from S Compare M: M + 1 · I I I I fromU Compare M: M + 1 · I I I I from X Compare M: M + 1 · I I I I from Y COM COMA COMB COM 43 2 53 2 03 6 2 73 7 3 63 6+ 2+ A-A B-B fil-M · II01 · I I01 · I I01 CWAI DAA 19 2 3C f;20 2 CC/\IMM-CC (except 1-+E) Wait for Interrupt Decimal Adjust A (-+-al r-1) · I I @I DEC DECA DECB DEC 4A 2 5A 2 OA 6 2 7A 7 3 6A 6+ 2+ A-1-A B-1-B M-1-M · Il I· ·I I I· · l I I· EOR EORA EORB 9B 4 2 BB 5 3 BB 2 2 AB 4+ 2+ DB 4 2 FB 5 3 C8 2 2 EB 4+ 2+ AeM-A BeM-B · I I O· · I I O· EXG R1,R2 lE 7 2 Rl -R2® (-+-@)r-) INC JMP JSR INCA INCB INC 4C 2 5C 2 1 1 oc 6 2 7C 7 3 OE 3 2 7E 4 3 90 7 2 BO B 3 6C 6+ 2+ SE 3+ 2+ AD 7+ 2+ A+ 1-A B+ 1- B M+1-M EA®- PC · I I I · · I I I · ·I I I· · · · · · Jump to Subroutine · · · · · LO LEA LOA LOB LOO LOS LOU LOX LOY LEAS LEAU LEAX LEAY 96 4 2 B6 5 06 4 2 F6 5 DC 5 2 FC 6 10 6 3 10 7 DE FE DE 5 2 FE 6 9E 5 2 BE 6 10 6 3 10 7 9E BE 3 86 2 2 A6 4+ 2+ 3 cs 2 2 E6 4+ 2+ 3 cc 3 3 EC 5+ 2+ 4 10 4 4 10 6+ 3+ CE EE 3 CE 3 3 EE 5+ 2+ 3 BE 3 3 AE 5+ 2+ 4 10 4 4 10 6+ 3+ BE AE 32 4+ 2+ 33 4+ 2+ 30 4+ 2+ 31 4+ 2+ M-A M-B M: M+ 1- D M: M+1-S M: M+ 1- U M: M+ 1- X M: M+ 1-Y · I I O· · I I0· · I I0· · l I0· · I I 0· ... . . · I I 0 · · I I0· · · · · · ·· t ·· ·· t·· LSL LSR LSLA LSLB LSL LSRA LSRB LSR 48 2 58 2 44 2 54 2 OB627B73 04 6 2 74 7 3 68 6+ 2+ 64 6+ 2+ MUL 30 11 1 NEG NEGA 40 2 1 NEGB 50 2 1 NEG 00 6 2 70 7 3 NOP 12 2 60 S+ 2+ Axe-o (Unsigned) A+1-A B+1-B fi1+1-M No Operation ®I I I I @I I I I @I I I I · · · · · (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 143 HD6809E ADDRESSING MODES INSi't~CJ~DN/ 1---IM_P_L_l_E_D~~D~IR_E_C_T~~E-X_T_E_N_D_E_D~~IM~M-E-D-IA-T~E~-IN_D_E_X~E-D-©~R-E_L_A_T_l_V_E--< DP - # OP - # OP - # DP - # OP - # OP -® # DESCRIPTION 532 10 HNZ VC OR ORA ORB ORCC 9A4 2 BAS 38A2 2 AA4+2+ DA 4 2 FA 5 3 CA 2 2 EA 4+ 2+ IA 3 2 AVM-A · I I0· BvM-B · I I 0· CCV IMM-CC ( HC:t>I-) PSH PSHS 34 s+© 2 PSHU 36 s+© 2 Push Registers on · · · · · S Stack Push Registers on · · · · · U Stack PUL PULS PULU ROL ROLA 49 2 1 ROLB 59 2 1 ROL 09 6 2 79 7 3 69 6+ 2+ Pull Registers from ( H@>I- ) S Stack Pull Registers from ( H@I-) U Stack ~}~: ! ! ! ! ROR RORA 46 2 1 RORB 56 2 1 ROR 06 6 2 76 7 3 RTI 38 6/15 1 RTS 39 5 1 66 6+ 2+ ~) Lttiiit!fifj! : ! ! : t Return From Interrupt Return From Subroutine ( H CV r- ) · · · · · SBC SBCA SBCB 92 4 2 82 5 3 82 2 2 A2 4+ 2+ 02 4 2 F2 5 3 C2 2 2 E2 4+ 2+ A-M-C-A @ I I I I 8-M-C-B @ I I I I SEX 10 2 1 Sign Extend B into A · I I ·· ST STA STB STD STS STU STX STY 97 4 2 87 5 3 07 4 2 F7 5 3 DD 5 2 FD 6 3 10 6 3 10 7 4 OF FF OF 5 2 FF 6 3 9F 5 2 BF 6 3 10 6 3 10 7 4 9F BF A7 4+ 2+ E7 4+ 2+ ED 5+ 2+ 10 6+ 3+ EF EF 5+ 2+ AF 5+ 2+ 10 6+ 3+ AF A-M e-M D-M: M+1 S-M: M+1 U-M: M+1 X-M: M+ 1 Y-M: M+1 · I I0· · I I0· · I I0· · I I0· · I I0· · I I 0· · I I0· SUB SUSA SUBB SUBD 90 4 DO 4 93 6 SWI SWI® 3F 19 1 sw12® 10 20 2 3F SWIJ® 11 20 2 3F SYNC 13 ;;;4 1 2 BO 5 2 FO 5 2 83 7 3 BO 2 3 co 2 3 83 4 2 AO 4+ 2+ 2 EO 4+ 2+ 3 A3 6+ 2+ A - M- A ff!) I I I I B - M- B ff!) I I I I O-M:M+1-D ·I I I I Software lnterrupt1 · · · · · Software lnterrupt2 · · · · · Software Interrupt3 · · · · · Synchronize to Interrupt · · · · · TFR R1,R2 1F 6 2 R1 - R2® ( H®ll-) TST TSTA 4D 2 TSTB SD 2 TST OD627D73 6D 6+ 2+ Test A Test B Test M · I I0· · I I0· · I I0· (NOTES) (j) This column gives a base cycle and byte count. To obtain total count, and the values obtained from the INDEXED ADDRESSING MODES table. @ R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers. The B bit registers are: A, 8, CC, DP The 16 bit registers are: X, Y, U, S, D, PC @ EA is the effective add<ess. @ The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled. @ 5(6) means: 5 cycles if branch not taken, 6 cycles if taken. ® SWI sets 1 and F bits. SWl2 and SWl3 do not affect I and F. (]) Conditions·Codes set as a direct result of the instruction. @ Value of half-carry flag is undefined. @ Special Cese - Carry set if b7 is SET. @:I Condition Codes set as a direct result of the instruction if CC is .,.citied, and not affected otherwise. LEGEND: OP Operation Code (Hexadecimal) Number of MPU Cycles # Number of Program Bytes + Arithmetic Plus Arithmetic Minus Multiply Complement of M Transfer Into H Half-carry lfrom bit 31 N Negative (sign bitl z Zaro (byte) v Overflow, 2's complement c Carry from bit 7 ·*cc Test and set if true, cleared otherwise Not Affected Condition Code Register Concatenation v Logical or A Logical and @ Logical Exclusive or 144 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 10 Hexadecimal Values of Machine Codes HD6809E OP Mnem Mode 00 NEG Direct 01 02 03 COM 04 LSR 05 06 ROR 07 ASR 08 ASL, LSL 09 ROL OA DEC OB oc INC OD TST OE JMP OF CLR Direct # 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 3 2 6 2 10 } See 11 Next Page 12 NOP Implied 2 13 SYNC 14 Implied ~4 15 16 LBRA Relative 5 3 17 LBSR Relative 9 3 18 19 DAA Implied 2 1 1A ORCC lmmed 3 2 18 1C AN DCC lmmed 3 2 10 SEX 1E EXG 1F TFR Implied i Implied 2 B 2 6 2 20 BRA Rel~tive 21 BRN 22 BHI 23 BLS 24 BHS,BCC 25 BLO,BCS 26 BNE 27 BEQ 28 eve 29 BVS 2A BPL 28 BMI 2C BGE 20 BLT 2E BGT 2F BLE Relative 3 2 3 ·2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 OP Mnem 30 LEAX 31 LEAV 32 LEAS 33 LEAU 34 PSHS 35 PULS 36 PSHU 37 PULU 3B 39 RTS 3A ABX 3B RTI 3C CWAI 30 MUL 3E 3F SWI Mode Indexed t Indexed Implied l Implied lmmed Implied # 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 5+ 2 5+ 2 5+ ~ 5+ 2 5 3 6, 15 1 ~20 2 11 1 Implied 19 40 NEGA Implied 2 41 42 43 COMA 2 44 LSRA 2 45 46 RORA 2 47 ASRA 2 4B ASLA, LSLA 2 49 ROLA 2 4A DECA 2 48 4C INCA 2 40 TSTA 2 4E 4F CLRA Implied 2 50 NEGB Implied 2 51 52 53 COMB 2 54 LSRB 2 55 56 RORB 2 57 ASRB 2 SB ASLB, LSLB 2 59 ROLB 2 SA DECB 2 58 5C INCB 2 50 TSTB 2 5E 5F CLRB Implied 2 OP Mnem Mode 60 NEG Indexed 61 62 63 COM 64 LSR 65 66 ROR 67 ASR 6B ASL, LSL 69 ROL 6A DEC 6B 6C INC 60 TST 6E JMP 6F CLR Indexed # 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 5.;. 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 3+ 2+ 6+ 2+ 70 NEG Extended 7 3 71 72 73 COM 7 3 74 LSR 7 3 75 76 ROR 7 3 77 ASR 7 3 78 ASL, LSL 7 3 79 ROL 7 3 7A DEC 7 3 78 7C INC 7 3 70 TST 7 3 7E JMP 4 3 7F CLR Extended 7 3 80 SUBA lmmed 2 2 B1 CMPA 2 2 82 SBCA 2 2 83 SUBD 4 3 84 ANDA 2 2 BS BITA 2 2 86 LOA 2 2 B7 88 EORA 2 2 89 ADCA 2 2 BA ORA 2 2 88 ADDA 2 2 BC CMPX lmmed 4 3 BO BSR Relative 7 2 BE LOX lmmed 3 3 BF LEGEND: .- Number of MPU cycles (less possible push pull or indexed-mode cycles) # Number of program bytes Denotes unused opcode (to be continued) ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 145 HD6809E OP Mnem 90 SUBA 91 CMPA 92 SBCA 93 SUBD 94 ANDA 95 BITA 96 LOA 97 STA 9B EORA 99 ADCA 9A ORA 9B ADDA 9C CMPX 90 JSR 9E LOX 9F STX AO SUBA Al CMPA A2 SBCA A3 SUBD A4 ANDA A5 BITA A6 LOA A7 STA AB EORA A9 ADCA AA ORA AB ADDA AC CMPX AD JSR AE LOX AF STX BO SUBA Bl CMPA B2 SBCA B3 SUBD B4 ANDA B6 BITA B6 LOA B7 STA BB EORA B9 ADCA BA ORA BB ADDA BC CMPX BO JSR BE LOX BF STX co SUBB Cl CMPB C2 SBCB C3 ADDO C4 ANDB cs BITB Mode Direct Direct # 4 2 4 2 4 2 6 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 6 2 7 2 5 2 6 2 Indexed Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 7+ 2+ 5+ 2+ 5+ 2+ Extended 6 3 5 3 5 3 7 3 6 3 6 3 6 3 5 3 6 3 5 3 5 3 !i 3 7 3 8 3 6 3 rExtended 6 2 2 2 4 3 2 2 2 3 2 2 lmmed 2 2 OP Mnem C6 LOB C7 cs EORB C9 ADCB CA ORB CB ADDI! cc LOO CD CE LOU CF DO SUBB DI CMPB 02 SilCB 03 ADDO 04 ANDB 05 BITB 06 LOB 07 STB 08 EORB 09 ADCB DA ORB DB ADDB DC LOO DD STD DE LOU OF STU EO SUBB El CMPB E2 SBCB E3 ADDO E4 ANDB E5 BITB E6 LOB E7 STB EB EORB E9 ADCB EA ORB EB ADDB EC LOO ED STD EE LOU EF STU FO SUBB Fl CMPB F2 SBCB F3 ADDO F4 ANDB F5 BITB F6 LOB F7 STB FS EORB F9 ADCB FA ORB FB ADDB (NOTE): All unused opcodes are both undefined and illegal Mode # lmmed 2 2 I 2 2 2 2 3 2 2 2 2 3 lmmed 3 3 Direct Direct 4 2 4 2 4 2 6 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 5 2 6 2 5 2 5 2 Indexed Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ Extended 5 3 5 3 5 3 7 3 6 3 5 3 6 3 5 3 5 3 5 3 5 3 Extended 5 3 OP Mnem Mode # FC LOO Extended 6 3 FD STD FE LOU l 6 3 6 3 FF STU Extended 6 3 2 Bytes Opcode 1021 LBRN Relative 1022 LBHI 1023 LBLS 1024 LBHS,LBCC 1025 LBCS, LBLO 1026 LBNE 1027 LBEQ 1028 LBVC 1029 LBVS 102A LBPL 102B LBMI 102C LBGE 1020 LBLT 102E LBGT 102F LBLE Relative 103F SWl2 Implied ; 1083 CMPD lmmed IOBC CMPY 108E LOY 1093 CMPD 109C CMPY 109E LOY lmmed :Direct 109F STY Direct IOA3 CMPD IOAC CMPY 10AE LOY tIndexed 10AF STY Indexed 1083 CMPD IOBC CMPY IOBE LOY 10BF STY Extended t Extended 10CE LOS lmmed 10DE LOS Direct IODF STS Direct 10EE LOS Indexed 10EF STS Indexed 10FE LOS Extended 10FF STS Extended 113F SWl3 Implied 1183 CMPU · lmmed 118C CMPS lmmed 1193 CMPU Direct 119C CMPS Direct 11A3 CMPU Indexed 11AC CMPS Indexed 1183 CMPU Extended llBC CMPS Extended 5 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 5161 4 6(6) 4 5(6) 4 5(6) 4 5(6) 4 5(6) 4 6(6) 4 5(6) 4 5(6) 4 5(6) 4 20 2 5 4 6 4 4 4 7 3 7 3 6 3 6 3 7+ 3+ 7+ 3+ 6+ 3+ 6+ 3+ B 4 8 4 7 4 7 4 4 4 6 3 6 3 6+ 3+ 6+ 3+ 7 4 7 4 20 2 6 4 6 4 7 3 7 3 7+ 3+ 7+ 3+ 8 4 8 4 146 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · NOTE FOR USE Execution Sequence of CLR Instruction Cycle-by-cycle flow of CLR instruction (Direct, Extended, Indexed. Addressing Mode) is shown below. In this sequence the content of the memory location specified by the operand is read before writing ''00" into it. Note that status Flags, such as IRQ Flag, will be cleared by this extra data read operation when accessing the control/status register (sharing the same address between read and write) of peripheral devices. Example: CbR (Extended) $8000 CLR $AOOO FCB $AOOO $80 Cycle# Address Data R/W Description 1 8000 7F 1 Opcode Fetch 2 8001 AO 1 Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 s · FFFF AOOO 80 1 VMACycle l Read the Data 6 · FFFF l VMACycle 7 AOOO 00 0 Store Fixed ''00" into Specified Location · The data bus has the data at that particular address. HD6809E @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 147 148 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 CMOS 8-BIT MICROPROCESSOR @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 149 150 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6303R,HD63A03R, HD63B03R CMOS MPU (Micro Processing Unit) The HD6303R is an 8-bit CMOS micro processing unit which has the completely compatible instruction set with the HD6301Vl. 128 bytes RAM, Serial Communication Interface (SCI), parallel 1/0 ports and multi function timer are incorpora· ted in the HD6303R. It is bus compatible with HMCS6800 and can be expanded up to 65k bytes. Like the HMCS6800 family, 1/0 level is TTL compatible with +5.0V single power supply. As the HD6303R is CMOS MPU, power dissipation is extremely low. And also HD6303R has Sleep Mode and Stand-by Mode as lower power dissipation mode. Therefore, flexible low power consumption application is possible. · FEATURES · Object Code Upward Compatible with the HD6800, HD6801, HD6802 · Multiplexed Bus (00 /A0 -D7/A7 A1 -A15 ), Non Multiplexed Bus (00 -D,, Ao-A15 I · Abundant On-Chip Functions Compatible with the HD6301V1; 12B Bytes RAM, 13 Parallel 110 Lines, 16-bit Timer, Serial Communication Interface (SCI) · Low Power Consumption Mode; Sleep Mode, Stand-By Mode · Minimum Instruction Execution Time lµs (f=lMHz), 0.67µs (f=1.5MHz), 0.5jls (f=2.0MHz) · Bit Manipulation, Bit Test Instruction · Error Detecting Function; Address Trap, Op Code Trap · Up to 65k Bytes Address Space · Wide Operation Range Vcc=3to6V (f=0.1-0.5MHzl f·0.1to2.0MHz1Vcc=5V± 10%) · TYPE Of: PRODUCTS Type No. lkllTlming HD6303R 1.0MHz HD83A03R 1.&MHz HD83803R 2.0MHz HD6303RP, HD63A03RP, HD63B03RP (DP-40) HD6303RF, HD63A03RF, HD83803RF (FP-54) HD6303RCG,HD63A03RCG, HD63803RCG · ICG-40) HD6303RCP, HD63A03RCP, HD63B03RCP ICP-521 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435:5300 151 · PIN ARRANGEMENT (Top View) · HD6303RP, HD63A03RP, HD63B03RP · HD6303RF, HD63A03RF, HD83B03RF · HD6303RCG, HD83A03RCG, HD63B03RCG AS filii Do/Ao 0 1 1A1 D2/A2 <NC> <NC> 7 m 03/.lis S'TIY D,IA,. D1!A1 01/A.1 0......1....IA1 .................... Vee t~J t~J l~J :..f;J ~c:.;J t~J t~J t~J tf:tJ L~J D1/A1 ~ [~s Au Do/"4 ~l <NC> · <NC> D1/A1 Os/As RiW 3]t] AS 3)] 0°.'I'A"o' 1 Do/Ao · 01/A.1 <NC> E ~] Vss 1] XTAL !] EXTAL ~] ~~A,, [2~ A1· [2:2 A11 [~1 Vee [~ A7/P11 [1! At/P11 ~:a Al/Pts NMI ~] ~! A4/P1· J <NC> cNC> IRQ1 ~ [1~ AJ/Pu r.01 r,:;.1 rc»1 ro..1 r21 r=1 r~1 r~1 f:!1 r~1 · HD6303RCP, HD63A03RCP, HD63B03RCP · BLOCK DIAGRAM <NC> RES STBY P20 P21 P22 P23 P24 <NC> Ao/P10 I A1/P11 A2/P12 <NC> <NC> D2/A2 A Da/A3 04/A4 <NC> Os/As Da/Aa D1/A1 <NC> As Ao A10 <NC> p,. p., Pai P., P,. Pio/Ao ....P11/A1 Pu/A.2 Pt1/Aa .-..,..,-,,',,,",.,,',,"..", 152 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol Vee Vin Topr T,,. Value Unit -0.3-+7.0 v -0.3- Vcc+o.3 v o- +70 oc -55 -+150 oc (NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field. But be careful not to apply over.voltage more than maximum ratings to these high input impedance protection circuits. To auure the normal operation. we reccrnmend Vin· Vout: V55 :;I;, (Vin or Vout) :;; Vee- · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee = 5.0V±10%, Vss · OV, Ta· 0-+70°C, unless otherwise noted.) Item Symbol Test Condition min typ max Unit Rt'S, ffiiY Input "High" Voltage EXTAL V1H Other Inputs Input "Low" Voltage All Inputs VIL Input Leakage Current NMI, iR01 , RES, STBY ll;n I Vcc-0.5 - Vccx0.7 - Vee +o.3 v 2.0 - -0.3 - 0.8 v V;n =0.5-Vcc-0.5V - - 1.0 µA Three State (off-state) Leakage Current P10-P17 , P20-P24 , Do-D1, As-Ats llTS11 V;n =0.5-Vcc-0.5V - - 1.0 µA Output "High" Voltage All Outputs Output "Low" Voltage All Outputs VoH VoL loH = -200µA loH = -10µA loL = 1.6mA 2.4 -- v Vcc-0.7 - - v - - 0.55 v Input Capacitance All Inputs Cin V;n=OV, f= 1.0MHz, Ta= 25°C - - 12.5 pF Standby Current Non Operation l~c - 2.0 15.0 µA Current Dissipation* RAM Stand-By Voltage jclperating (f=1 MHz**) Ice Sleeping (f=1MHz**) - VRAM 2.0 6.0 10.0 mA 1.0 2.0 -- v * V1H min= Vcc-1.0V, VIL max= 0.SV ·· Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. values about Current Dissipations at f = x MHz operation are decided according to the following formula; typ. value If· xMHzl · typ. value If= 1MHz) xx max.value (f=xMHz) =max.value(f= 1MHz) xx (both the sleeping and opehlting) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 153 · AC CHARACTERISTICS (Vee= 5.0V±10%, Vss = OV, Ta= 0-+70°C, unless otfierwise noted.) BUS TIMING Test HD6303R HD63A03R HD63B.03R Item Symbol Con· Unit dition min typ max min typ max min typ max Cycle Time tcyc 1 - 10 0.666 - 10 0.5 - 10 µs Address Strobe Pulse Width · "High" PW ASH 220 - - 150 - - 110 - - ns Address Strobe Rise Time tAsr Address Strobe Fall Time tASf Address Strobe Delay Time · tASD Enable Rise Time ter Enable Fall Time te· Enable Pulse Width "High" Level" PWeH Enable Pulse Width "Low" Level* PWeL -- -- 60 -- -- 450 - 450 - 20 - 20 - - 40 20 - - 20 - - - 300 - - 300 - 20 - 20 - - 20 - 20 - - 20 - - - 220 - - 220 - 20 ns 20 ns - ns 20 ns 20 ns - ns - ns Address Strobe to Enable Delay· Time tASED 60 - Address Delay Time ~ tAD2 Fig. 1 - - Address Delay Time for Latch* tADL Fig. 2 - - Data Set-up Time Write tosw Read tosR 230 80 - Data Hold Time Read tHR Write tHW 0 20 - Address Set-up Time for Latch· tASL 60 - Address Hold Time for Latch tAHL 30 - Address Hold Time tAH 20 - A0 - A 7 Set-up Time Before E* tASM 1 Peripheral Read Non-Multiplexed Bus · (tACCN) J · Access Time Multiplexed Bus (tAccMl 200 - --- Oscillator stabilization Time tRc Fig. 8 20 - Processor Control Set-up Time tpcs Fig. 9 200 .,.. - 40 - 250 - - 250 - - 250 - - - 150 - - 60 - - 0- - 20 - - 40 - - 20 - - 20 - - 110 - 650 - - 650 - - - 20 - - 200 - - 20 - 190 - - 190 - - 190 - - - 100 - - 50 - - 0 - - 20 - - 20 - - 20 - - 20 - - 60 - 395 - - 395 - - - 20 - - 200 - - ns 160 ns 160 ns 160 ns - ns - ns - ns - ns - ns - ns - ns - ns 270 ns 270 ns - ms - ns *These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum (= in the highest speed operation). PERIPl:IERAL PORT TIMING Item Symbol Peripheral Data Set-up Time Port 1, 2 tposu Peripheral Data Hold Time Port1,2 tpoH Delay Time, Enable NegaJ Port 1 tive Transition to Peri- 2· ' tPWD pheral Data Valid * Except P21 Test Condit i on Fig. 3 Fig. 3 Fig. 4 HD6303R H063A03R HD63B03R Unit min typ max min typ max min typ max 200 - - 200 - - 200 - - ns 200 - - 200 - - 200 - - ns - - 300 - - 300 - - 300 ns 154 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 TIMER, SCI TIMING Item Timer Input Pulse Width Delay Time, Enable Positive Transition to Timer Out SCI Input Clock Cycle SCI Input Clock Pulse Width Test Symbol Con- dition tpwT tToo Fig. 5 tScyc tpwscK HD6303R HD63A03R HD63B03R Unit min typ max min typ max min typ max - 2.0 - 2.0 - - 2.0 - - tcyc - - 400 - - 400 - - 400 ns 2.0 0.4 - - 2.0 - 0.6 0.4 - - 2.0 0.6 0.4 - - tcyc 0.6 tScyc MODE PROGRAMMING Item RES "Low" Pulse Width Mode Programming Set-up Time Mode Programming Hold Time Test Symbol Con· di t i on PWRSTL tMPS Fig.6 tMPH HD6303R HD63A03R HD63B03R Unit min typ max min typ max min typ max - 3 - 3 - - 3 - - 1cvc 2 - - 2 - - 2 - - 1cvc 150 - - 150 - - 150 - - ns Address Strobe IASI ENble I El 2.4V O.BV IEf MPUWrite 0 0 -D,.A0 -A, MPU Raod o.-o.,. A0 -A., Figure 1 Multiplexed Bus Timing - Not Valid @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 155 tcyc 2.4V R/ii Address V·lid O.BV wo.u-o.w, .;'"---4-----4--------C A.-A, (Port 1) 2.4V O.IV Figure 2 Non-Multiplexed Bus Timing tMPURHd !Im Not Valid '· ,,. P.. -Pu ... Inputs Figure 3 Port Data Set-up and Hold Times (MPU Read) All O.ta 2AV Dau V·id Port Outputs _ _ _ _ _ _ __, 11..:;0:;:.B::,v_ __ Note) Port 2: Except P11 Figure 4 Port Data Delay Times (MPUWrite) Figure 5 Timer Output Timing Figure 6 Mode Programming Timing 156 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Test Point e Vee RL s 2.2kll (4.0kll for E) ® 152074 or Equiv. e=90pF for AS, R/W, 0 0 /Ao - o./A,, and AS -=30pF for P2 o - P,4 and Ao /P10 - A., /P 17 =40pF for E R=12kQ Figure 7 Bus Timing Test Loads (TTL Load) Interrupt Tfft lntern·I Addreu Bus --"""+~~,....,~,_,,~-....,=,J\.-,,::--'"'-;:::-:-"'..,,,,,.,..-""'=.-"-.....-,-.,.,,..,"C""....,..,,.':'::=:-'1:=:='":::=rf'--'' NMI, iRcfi Internal --"",--...,....-""'--...,....-""'--..,--......--v--"'"\.r--v--"'"\.r--v--"'"\.r--v--"'"\.r--v- D·t· Bus--J\.---'~o-p_C_odeJ\-i:'!!-·n""'1,-,.-~-ve~n~tp_c_o_-_,..~PC~B---"~,-.O---"~,-.-e--"'"~_,...,.,....,,."'-.,..._,...,,,::r.:!~-=:':'!'""''""'!_'-,,....-.I'._ =~n·I ---~""D-··_·__·_c_,_ _·_c_·_·_ _,._,_ _,._·_·_ _ _ _ _ _ _~""'"'--'=-==== lntemel Wnte Figure 8 Interrupt Sequence ..::' ,....-)\\\\\\\\\\\\\\\\\\\\\\\ ~ternM -~\\\\\\\\\\\\\\\\\\\\\\\\ l~i------;11-------_ _ __ 1~____.,,__ Figure 9 Reset Timing · FUNCTIONAL PIN DESCRIPTION · Yee· Yss These two pins are used for power supply and GND. Recommended power supply voltage is 5V ± 10%. 3 to 6V can be used for low speed operation (I 00 - 500 kHz). · XTAL, EXTAL These two pins are connected with parallel resonant funoia- mental crystal, AT cut. For instance, in order to obtain the system clock I MHz, a 4MHz resonant fundamental crystal is used because the devide-by-4 circuitry is included. An example of the crystal interface is shown in Fig. 10. EXTAL accepts an external clock input of duty 45% to 55% to drive. For external clock, XTAL pin should be open. The crystal and capacitors should be mounted as close as possible to the pins. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 157 AT Cut Parallel Resonence Crystel Co· 7pFmax R1 · 60 !l max CJ EXTALt------. CL1 · CL2·10-22pF ±. 20% (3.2-SMHz) Figure 10 Crystal Interface · Standby (STBYI This pin is used to place the MPU in the standby mode. If this goes to "Low" level, the oscillation stops, the internal clock is tied to Vss or Vcc and the MPU is reset. Jn order to retain information in RAM during standby, write "O" into RAM enable bit (RAME). RAME is bit 6 of the RAM Control Register at address $0014. This disables the RAM, so the contents of RAM is guaranteed. For details of the standby mode, see the Standby section. · Reset (RES) This input is used to reset the MPU. 'RES must be held "Low" for at least 20ms when the power starts up. It should be noted that, before clock generator stabilize, the internal state and 1/0 ports are uncertain, because MPU can not be reset without clock. To reset the MPU duting system operation, it must be held "Low" for at least 3 system clock cycles. From the third cycle, all address buses become "high-impedance" and it continues while 'RES is "Low". If RS goes to "High", CPU does the following. (I) I/O Port 2 bits 2,1,0 are latched into bits PC2, PC!, PCO of program control register. (2) The contents of the two Start Addresses, SFFFE, SFFFF are brought to the program counter, from which program starts (see Table I). (3) The interrupt mask bit is set. In order to have the CPU recognize the maskable interrupts IRQ, and IRQ., clear it before those are used. · Enlble (El This output pin supplies system clock. Output is a single- phase, TTL compatible and 1/4 the crystal oscillation frequency. It will drive two LS TTL load and 40pF capacitance. · Non Maskable Interrupt (NMll When the falling edge of the input signal of this pin is re- cognized, NMI sequence starts. The current instruction is con- tinued to complete, even if mJI signal is detected. Interrupt mask bit in Condition Code Register has no effect on NM! detection. In response to NMI interrupt, the information· of Program Counter, Index Register, Accumulators, and Condition Code Register are stored on the stack. On completion of this sequence, vectoring address $FFFC and $FFFD are generated to load the contents to the program counter. Then the CPU branch to a non maskable interrupt service routine. · Interrupt Request (IRQ1) This level sensitive input requests a maskable interrupt sequence. When IRQ1 goes to "Low", the CPU waits until it completes the current instruction that is being executed. Then, if the interrupt mask bit in Condition Code Register is not set, CPU begins interrupt sequence; otherwise, interrupt request is neglected. Once the sequence has started, the information of Program Counter, Index Register, Accumulator, Condition Code Register are stored on the stack. Then the CPU sets the interrupt mask bit so that no further maskable interrupts may be responded. -Table 1 Interrupt Vectoring memory map Highest Priority Voctor LSI! FFFE FFFF lnwrupt Ill! FFEE FFEF TRAP FFFC FFFA FFF8 FFFO FFF9 FFF9 liill Software tnwrup· rswo i1lm'1 Cor ii3> FFFI FFF7 ICF (Timer Input (epture) FFF4 FFF5 OCF (filNf' Output ~J LPriority FFF2 FFFO FFF3 TOF fTimw Owfflow) FFF1 SCI CRDAF + ORFE + TORE) At the end of the cycle, the CPU generates 16 bit vectoring addresses indicating memory addresses SFFF8 and $FFF9, and loads the contents to the Program Counter, then branch to an interrupt service routine. The Internal Interrupt will generate signal (IRQ2) which is quite the same as IRQ, except that it will use the vector address $FFFO to $FFF7. When IRQ 1 and IRQ2 are generated at the same time, the former precedes the latter. Interrupt Mask Bit in the condition code register, if being set, will keep the both interrupts off. On occurrence of Address error or Op-code error, TRAP interrupt is invoked. This interrupt has priority next to RES: Regardless of the interrupt Mask Bit condition, the CPU will start an interrupt sequence. The vector for this interrupt will be $FFEE, $FFEF. · Rllld/Write IRJWI This TTL compatible output signals peripheral and memory devices whether CPU is in Read ("High"), or in Write ("Low"). The normal stand-by state is Read ("High"). Its output will drive one TTL load and 90pF capacitance. · Addr· Strobe (ASI In the multiplexed mode, address strobe signal appears at this pin. It is used to latch the lower 8 bits addresses multiplexed with data at Do/Ao - D1/A1. The 8-bit latch is controlled by address strobe as shown in Figure 15. Thereby, Do/Ao - D1/A1 can become data bus during E pulse. The timing chart of this signal is shown in Figure I. Address Strobe (AS) is sent out even if the internal address is accessed. · PORTS There are two 1/0 ports on HD6303R MPU (one 8-bit ports and one 5-bit port). Each port has an independent write-only data direction register to program individual 1/0 pins for input or output.· When the bit of associated Data Direction Register is "I", 1/0 pin is programmed for output, if "0", then programmed for 158 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 an input. There are two ports : Port 1, Port 2. Addresses of each port and associated Data Direction Register are shown in Table 2. · Only one exception is bit 1 of Port 2 which becomes either a data input or a timer output. It cannot be used as an output port. Table 2 Port and Data Direction Register Addresses Ports Port Address Data Direction Register Address 1/0 Port 1 1/0 Port 2 $0002 $0003 $0000 $0001 · 1/0 Port 1 This is an 8-bit port, each bit being defined individually as input or outputs by associated Data Direction Register. The 8-bit output buffers have three-state capability, maintaining in high impedance state when they are used for input. In order to be read accurately, the voltage on the input lines must be more than 2.0V for logic "I" and less than 0.8V for logic "O". These are TTL compatible. After the MPU has been reset, all I/O lines are configured as inputs in Multiplexed mode. In Non Multiplexed mode, Port I will be output line for lower order address lines (Ao - A1 ), which can drive one TTL load and 30 pF capacitance. · 1/0 Port2 This port has five lines, whose 1/0 direction depends on its data direction register. The 5-bit output buffers have three-state capability, going high impedance state when used as inputs. In order to be read accurately, the voltage on the input lines must be more than 2.0V for logic "I" and less than 0.8V for logic "O". After the MPU has been reset, 1/0 lines are configured as inputs. These pins on Port 2 (P20 - P22 of the chip) are used to program the mode of operation during reset. The values of these three pins during reset are latched into the upper 3 bits (bit 7, 6 and 5) of Port 2 Data Register which is explained in the MODE SELECTION section. In all modes, Port 2 can be configured as 1/0 lines. This port also provides access to the Serial 1/0 and the Timer. However, note that bit I (P21 ) is the only pin restricted to data input or Timer output. · BUS · Do/Ao - D,/A7 This TTL compatible three-state buffer can drive one TTL load and 90 pF capacitance. Non Multiplexed Mode In this mode, these pins become only data bus (Do - D1 ). Multiplexed Mode These pins becomes both the data bus (Do - D7) and lower bits of the address bus (Ao - A7 ). An address strobe output is "High" when the address is on the pins. ·A8 -A,. Each line is TTL compatible and can drive one TTL load and 90 pF capacitance. After reset, these pins become output for upper order address lines (A8 - Au). · MODE SELECTION The operation mode after the reset must be determined by the user wiring the P20, P21, and P22 externally. These three pins are lower order bits; 1/0 0, 1/0 I, 1/0 2 of Port 2. They are latched into the control bits PCO, PC I, PC2of1/0 Port 2 register when ~goes "High". 1/0 Port 2 Register is shown below. Port 2 DATA REGISTER · 5 4 , 0 An example of external hardware used for Mode Selection is shown in Figure 11. The HDl4053B is used to separate the peripheral device from the MPU during reset. It is necessary if the data may conflict between peripheral device and Mode generation circuit. No mode can be changed through software because the bits 5, 6, and 7 of Port 2 Data Register are read-only. The mode selection of the HD6303R is shown in Table 3. The HD6303R operates in two basic modes: (I) Multiplexed Mode, (2) Non Multiplexed Mode. · Multiplexed Mode The data bus and the lower order address bus are multiplexed in the Do/Ao - D1/A1 and can be separated by the Address Strobe. Port 2 is configured for 5 parallel 1/0 or Serial 1/0, or Timer, or any combination thereof. Port I is configured for 8 parallel 1/0. · Non Multiplexed Mode In this mode, the HD6303R can directly address HMCS6800 peripherals with no address latch. D0 IAo - D7 / A7 become a data bus and Port I becomes Ao - A7 address bus. In this mode, the HD6303R is expandable up to 65k bytes with no address latch. · ~Order AddrBn Bus Latch Because the data bus is multiplexed with the lower order address bus in Do/Ao-D1/A1 in the multiplexed mode, address bits must be latched. It requires the 74LS373 Transparent octal D-type to latch the I.SB. Latch connection of the HD6303R is shown in Figure 15. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 159 Vee A P,. -M----+--+---+---4 P,. -+---+-t---i--1 P,, -.+---+--+---+---4 06303 1 - - - - - 1 P,. IPCOI 1 - - - - - t P11 IPCU 1-----tP,, IPC21 HD14053B Noto 1I Figure of Multiplexed Mode 21 RC.,Resot Constant 3) R1 ·10kn Figure 11 Recommended Circuit for Mode Selection lnh A B c Vss x. x, v. Y, z. z, Binary to 1-of-2 Decoder with Inhibit x y z Truth Table Control Input Select Inhibit C B A On Switch HD1<I053B 0 0 0 0 z. v. x. 0 0 0 1 z. v. x. 0 0 1 0 z. v1 x. 0 0 1 1 z. v, x, 0 1 0 0 z. v. x. 0 1 0 1 z, v. x. 0 1 1 0 z, YI x, 0 1 1 1 z, YI X, 1 xxx Figure 12 HD14053B Multiplexers/De-Multiplexers Vee Port 1 81/0 Linn Port 2 51/0 Linn SCI Ttmer Vss A, -Au 8 Addrass Lines Figure 13 HD6303R MPU Multiplexed Mode Port 2 5 Par·llel 1/0 SCI Timer Vee HD6303R MPU Vss Enoble Niii IRQ1 00 -o, 8Det1 Lines ·-A, -Au Lints Figure 14 HD6303R MPU Non Multiplexed Mode 160 ~HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 GND AS O,/A,-0,/A, [ Address/O·t· ~ ]---· D, a, 74LS373 ~ ),.,. ,__, ..... Figure 15 Latch Connection Output Control (QC) l l l H Function Table En1bte G D H H H l l x x x Output a H l a, z Table 3 Mode Selection Operating Mode Multiplexed Mode Non Multiplexed Mode L: logic "O" H: logic "1" P20 P21 P22 L H L L L H H L L · MEMORY MAP The MPU can provide up to 65k byte address space. Figure 16 shows a memory map for each operating mode. The first 32 locations of each map are for the CPU's internal register only, as shown in Table 4. Table 4 Internal Register Area Register Port 1 Data Direction Register** Port 2 Data Direction Register .. Port 1 Data Register Port 2 Data Register Timer Control and Status Register Counter (High Byte) Counter (Low Byte) Output Compare Register (High Byte) Output Compare Register (Low Byte) Input Capture Register (High Byte) Input Capture Register ILow Byte) Rate and Mode Control Register Transmit/Receive Control and Status Register Receive Data Register Transmit Data Register RAM Control Register Reserved · External address in Non Multiplexed Mode 1 =Output, 0 = Input Address oo· 01 02· 03 OB 09 OA OB oc OD OE 10 11 12 13 14 15-IF E111ern11I Memory SP<JCI! SFFFF ' - - - - ' · (NOTE] Excludes the following addresses which may be used externally; $00, $02. Figure 16 HD6303R Memory Maps @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 161 · PROGRAMMABLE TIMER The HD6303R contains 16-bit programmable timer which may measure input waveform.In addition to that it can generate an output waveform by itself. For both input and output waveform, the pulse width may vary from a few microseconds to several seconds. The timer hardware consi~ts of · an 8-bit control and status register · a 16-bit free running counter ·a 16-bit output compare register ·a 16-bit input capture register A block diagram of the timer is shown in Figure 17. lit1 .... 2 """ Figure 17 ------"' Outp,,,1 Input '-8ftl Edfl li!i t litO '-12 ~2 Programmable Timer Block Diagram · Free Running Counter ($0009: $000A) The key element in the programmable timer is a 16-bit free running counter, that is driven by an E (Enable) clock to increment its values. The counter value will be read out by the CPU software at any time with no effects on the counter. Reset will clear the counter. When the MSB of this counter is read, the LSB is stored in temporary latch. The data is fetched from this latch by the subsequent read of I.SB. Thus consistent double byte data can be read from the counter. When the CPU writes arbitrary data to the MSB ($09), the value of $FFF8 is being pre-set to the counter ($09, $0A) regardless of the write data value. Then the CPU writes arbitrary data to the L'iB ($0A), the data is set to the "Low" byte of the counter, at the same time, the data preceedingly written in the MSB ($09) is set to "High" byte of the counter. When the data is written to this counter, a double byte store instruction (ex. STD) must be used. If only the MSB of counter is written, the counter is set to $FFF8. The counter value written to the counter using the double byte store instruction is shown in Figure 18. To write to the counter can disturb serial operations, so it should be inhibited during using the SCI. If external clock mode is used for SCI, this will not disturb serial operations. (5AF3 written to the counter) Figure 1B Counter Write Timing · Output Compire Register ($000B:$000C) This is a 16-bit read/write register which is used to control an output waveform. The contents of this register are constantly being compared with current value of the free running counter. When the contents match with the value of the free running counter, a flag (OCF) in the timer control/status register (TCSR) is set and the current value of an output level Bit (OLVL) in the TCSR is transferred to Port 2 bit I. When bit 1 of the Port 2 data direction register is "I" (output), the OLVL value will appear on the bit I of Port 2. Then, the value of Output Compare Register and Output level bit may be ch8J!ged for the next compare. The output compare register is set to $FFFF during reset. The compare function is inhibited at the cycle of writing to the high byte of the output compare register and at the cycle just after that to ensure valid compare. It is also inhibited in same manner at writing to the free running counter. In order to write a data to Output Compare Register, a double byte store instruction (ex.STD) must be used. · Input Captlire Register ($0000: $000El The input capture register is a 16-bit read-only register used to hold the current value of free running counter captured when the proper transition of an external input signal occurs. The input transition change required to trigger the counter transfer is controlled by the input edge bit (IEDG). To allow the external input signal to go in the edge detect unit, the bit of the Data Direction Register corresponding to bit 0 of Port 2 rnust ha<e been cleared (to zero). To insure input capture in all cases, the width of an input pulse requires at least 2 Enable cycles. · Timer Control/Status Register (TCSR l ($0008) This is an 8-bit register. All 8-bits are readable and the lower S bits may be written. The upper 3 bits are read-only, indicating the timer status information as is shown below. (I) A proper transition has been detected on the input pin (!CF). (2) A match has been found between the value in the free running counter and the output compare register (OCF). (3) When counting up to $0000 (TOP). Each flag has an individual enable bit in TCSR which determines whether or not an interrupt request may occur (ll{Q2). If the I-bit in Condition Code Register has been cleared, a prior vectored address occurs corresponding to each flag. A description of each bit is as follows. Timer Control I Status Register j I I I I I 76 s· J21 o j j ocF oc· ro· Eoco EOco noo ·EDG OLvLI soooa Bit 0 OLVL (Output Level); When a match is found in the value between the counter and the output com- 162 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 pare register, this bit is transferred to the Port 2 bit 1. If the DOR corresponding to Port 2 bit 1 is set "l ",the value will appear on the output pin of Port 2 bit I. Bit 1 IEDG (Input Edge): This bit control which transition of an input of Port 2 bit 0 will trigger the data transfer from the counter to the input capture register. The DDR corresponding to Port 2 bit 0 must be clear in advance of using this function. When IEDG =0, trigger takes place on a n.egative edge ("High'!..to-"Low" transition). When IEDG = 1, trigger takes place on a positive edge ("Low"-to"High" transition). Bit 2 ETOI (Enable Timer Overflow Interrupt); When set, this bit enables TOF interrupt to generate the interrupt request (IRQ2 ). When cleared, the interrupt is inhibited. Bit 3 EOCI (Enable Output Compare Interrupt); When set, this bit enables OCF interrupt to generate the interrupt request (IRQl). When cleared, the interrupt is inhibited. Bit 4 EICI (Enable Input Capture Interrupt); When set, this bit enables !CF interrupt to generate the interrupt request (IRQi). When cleared, the interrupt is inhibited. Bit 5 TOF (Timer Over Flow Flag); This read-only bit is set at the transition of $FFFF to $0000 of the counter. It is cleared by CPU read of TCSR (with TOF set) followed by a CPU read of the counter ($0009). Bit 6 OCF (Output Compare Flag); This read-only bit is set when a match is found in the value between the output compare register and the counter. It is cleared by a read of TCSR (with OCF set) followed by a CPU write to the output compare register ($000B or $000C). Bit 7 ICF (Input Capture Flag); The read-only bit is set by a proper transition on the input, and is cleared by a read of TCSR (with ICF set) followed by a CPU read of Input Capture Register ($0000). Reset will clear each bit of Timer Control and Status Register. · SERIAL COMMUNICATION INTERFACE The HD6303lt contains a full-duplex asynchronous Serial Communication Interface (SCI). SCI may select the several kinds of the data rate. It consists of a transmitter and a receiver which operate independently but with the same data format and the same data rate. Both of transmitter and receiver communicate with the CPU via the data bus and with the outside world through Port 2 bit 2, 3 and 4. Description of hardware, software and register is as follows. · Wake-Up Feature In typical multiprocessor applications the software protocol will usually have the designated address at the initial byte of the message. The purpose of Wake-Up feature is to have the nonselected MPU neglect the remainder of the message. Thus the non-selected MPU can inhibit the all further interrupt process until the next message begins. Wake-Up feature is re-enabled by a ten consecutive "l "s which indicates an idle transmit line. Therefore software protocol must put an idle period between the messages and must prevent it within the message. With this hardware feature, the non-selected MPU is reenabled (or "waked-up") by the next message. · Programmable Options The HD6303R has the following programmable features. ·data format; standard mark/space (NRZ) ·clock source; external or internal ·baud rate; one of 4 rates per given E clock frequency or 1/8 of external clock ·wake-up feature; enabled or disabled ·interrupt requests; enabled or masked individually for transmitter and receiver .clock output; internal clock enabled or disabled to Port 2 bit 2 ·Port 2 (bits 3, 4); dedicated or not dedicated to serial I/O individually · Serial Communication Hardware The serial communications hardware is controlled by 4 registers as shown in Figure 19. The registers include: - an 8-bit control/status register · a 4-bit rate/mode control register (write-only) ·an 8-bit read-only receive data register ·an 8-bit write-only transmit data register Besides these 4 registers, Serial 1/0 utilizes Port 2 bit 3 (input) and bit 4 (output). Port 2 bit 2 can be used when an option is selected for the internal-clock-out or the externalclock-in. · Transmit/Receive Control Status Register (TRCSR) TRCS Register consists of 8 bits which all may be read while only bits 0 to 4 may be written. The register is initialized to $20 on RES. The bits of the TRCS Register are explained below. Transmit I Receive Control Status Register 715432'0 Bit 0 WU (Wake Up); Set by software and cleared by hardware on receipt of ten consecutive "I "s. While this bit is "I", RDRF and ORFE flags are not set even if data are received or errors are detected. Therefore received data are ignored. It should be noted that RE flag must have already been set in advance of WU flag's set. Bit 1 TE (Transmit Enable); This bit enables transmitter. When this bit is set, bit 4 of Port 2 DDR is also forced to be set. It remains set even if TE is cleared. Preamble of ten consecutive "1 "s is transmitted just after this bit is set, and then transmitter becomes ready to send data. If this bit is cleared, the transmitter is disabled and serial I/O affects nothing on Port 2 bit 4. Bit 2 TIE (Transmit Interrupt Enable); When this bit is set, TORE (bit S) causes an mol interrupt. When cleared, TORE interrupt is masked. Bit 3 RE (Receive Enable); When set, Port 2 bit 3 can be used as an input of receive regardless of DOR value for this bit. When cleared, the receiver is disabled. Bit 4 RIE (Receive Interrupt Enable); When this bit is set, RDRF (bit 7) or ORFE (bit 6) cause an mQ. interrupt. When cleared, this interrupt is masked. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 163 Bit 5 TORE (Transmit Data Register Empty); When the data is transferred from the Transmit Data Register to Output Shift Register, thi~ bit ~ set by hard- ware. The bit is cleared by reading the status register followed by writing the next new data into the Transmit Data Register. TORE is initialized tolbylttX Bit 6 ORFE (Over Run Framing Error); When overrun or framing error occurs (receive only), this bit is set by hardware. Over Run Error occurs if the attempt is made to transfer the new byte to the receive data register while the RDRF is "l ". Framing Error occurs when the bit counter is not synchronized with the boundary of the byte in the re- ce1vmg bit stream. When Framing Error is detected, RDRF is not set. Therefore Framing Error can be distinguished from Overrun Error. That is, if ORFE is "l" and RDRF is "l", Overrun Error is detected. Otherwise Framing Error occurs. The bit is cleared by reading the status register followed by reading the receive data register, or by RES: Bit 7 RDRF (Receive Data Ragistar Full); This bit is set by hardware when the data is transferred from the receive shift register to the receive data register. m: It is cleared by reading the status register followed by reading the receive data register, or by lit J A·· and Modt ContrOI Aep111tr Bit O I Icc· Icco I551 Isso ls·o R9caive Shift . . . . . . 551 sso 0 0 0 1 1 0 1 1 ··Ctoc· 2 10 E TrM1sm11 Shih Rqister "·lit 11 Sil Transmit O·t· Register Figure 19 Serial 1/0 Register I I I I I I I 6 5 4 3 2 I 0 x x x x cc1 cco ss1 sso ADDR S0010 Transfer Rate I Mode Control Register Table& SCI Bit Times and Transfer Rates XTAL E E+ 16 E+ 126 E + 1024 E + 4096 2.4576MHz 614.4 kHz 26 111/38,400 S.Ud 2Cllllls/4,800 81Ud 1.67ms/600 Baud 6.67ms/150 81ud 4.0MHz 1.0MHz 16 11s/62,500 81Ud 126 11s/7812.5 BIUd 1.024ms/976.6 81ud 4.096ms/244.1 81Ud 4.9152MHz 1.2288MHz 13 ,,s/76.IOOlllud 104.2,.s/ 9,800111ud 833.3,.s/ 1.2008eud 3.333ms/ 300lllud 164 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 6 SCI Format and Clock Source Control CCI: CCO 0 0 0 1 1 0 1 1 ForrTI1t - NAZ NAZ NAZ Clock Source - Internal Internal External Port 2 Bit 2 - Not Used*** Output· Input Port 2 Bit 3 ...-... Port 2 Bit 4 ...-... · Clock output is aveilable regardless of values for bits RE and TE. ·· Bit 3 is used for serial input if RE· ''1" in TRCS. Bit 4 is used for serial output if TE · "1" in TRCS. ***This pin can be used as 1/0 port. · Transfer Rate/Mode Control Register IRMCR) The register controls the following serial 1/0 functions: · Bauds rate ·data format · clock source ·Port 2 bit 2 feature It is 4-bit write-only register, cleared by ~. The 4 bits are considered as a pair of 2-bit fields. The lower 2 bits control the bit rate of internal clock while the upper 2 bits control the format and the clock select logic. Bit OSSO} Bit I SS I Speed Select These bits select the Baud rate for the internal clock. The rates selectable are function of E clock frequency of the CPU. Table 5 lists the available Baud Rates. BBiitt23 CCCCO1} Clock Control/Format Select They control the data format and the clock select logic. Table 6 defines the bit field. · Internally Generated Clock If the user wish to use externally an internal clock of the serial 1/0, the following requirements should be noted. ·CCI, CCO must be set to "10". ·The maximum clock rate must be E/16. ·The clock rate is equal to the bit rate. ·The values of RE and TE have no effect. · Externally Generated Clock If the user wish to supply an external clock to the Serial 1/0, the following requirements should be noted. ·The CC I, CCO must be set to "11" (See Table 6). ·The external clock must be set to 8 times of the desired baud rate. ·The maximum external clock frequency is E/2 clock. · Serial Operations The serial I/O hardware must be initialized by the software before operation. The sequence will be normally as follows. ·Writing the desired operation control bits of the Rate and Mode Control Register. ·Writing the desired· operation control bits of the TRCS register. If Port 2 bit 3, 4 are used for serial 1/0, TE, RE bits may be kept set. When TE, RE bit are cleared during SCI operation, and subsequently set again, it should be noted that TE, RE must be kept "O" for at least one bit time of the current baud rate. If TE, RE are set again within one bit time, there may be the case where the initializing of internal function for transmitter and receiver does not take place correctly. · Transmit Operation Data transmission is e.nabled by the TE bit in the TRCS register. When set, the output of the transmit shift register is connected with Port 2 bit 4 which is unconditionally configured as an output. After ~. the user should initialize both the RMC register and the TRCS register for desired operation. Setting the TE bit causes a transmission of ten-bit preamble of "I "s. Following the preamble, internal synchronization is established and the transmitter is ready to operate. Then either of the following states exists. (!) If the transmit data register is empty (TORE= !), the consecutive "I "s are transmitted indicating an idle states. (2) If the data has been loaded into the Transmit Data Register (TORE = 0), it is transferred to the output shift register and data transmission begins. During the data transfer, the start bit ("O") is first transferred. Next the 8-bit data (beginning at bit 0) and finally the stop bit ("I"). When the contents of the Transmit Data Register is transferred to the output shift register, the hardware sets the TORE flag bit: If the CPU fails to respond to the flag within the proper time, TORE is kept set and then a continuous string of l's is sent until the data is supplied to the data register. · Receive Operation The receive operation is enabled by the RE bit. The serial input is connected with Port 2 bit 3. The receiver operation is determined by the contents of the TRCS and RMC register. The received bit stream is synchronized by the first "O" (start bit). During 10-bit time, the data is strobed approximately at the center of each bit. If the tenth bit is not "I" (stop bit), the system assumes a framing error and the ORFE is set. If the tenth bit is "l ", the data is transferred to the receive data register, and the RDRF flag is set. If the tenth bit of the next data is received and still RDRF is preserved set, then ORFE is set indicating that an overrun error has occurred. After the CPU read of the status register as a response to RDRF flag or ORFE flag, followed by the CPU read of the receive data register, RDRF or ORFE will be cleared. · RAM CONTROL REGISTER The register assigned to the address $0014 gives a status information about standby RAM. RAM Control Register Bit 0 Not used. Bit 1 Not used. Bit 2 Not used. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 165 Bit 3 Not ulld. Bit 4 Not ulld. Bit 5 Not ulld. Bit 6 RAM Enable (RAME). Using this control bit, the user can disable the RAM. RAM Enable bit is set on the positive edge of 1rnS and RAM is enabled. The program can write "I" or "O". If RAME is cleared, the RAM address becomes external address and the CPU may read the data from the outside memory. Bit 7 Standby Power Bit (STBY PWRI This bit can be read or written by the user program. It is cleared when the Vcc voltage is removed. Normally this bit is set by the program before going into stand-by mode. When the CPU recovers from stand-by mode, this bit should be checked. If it is "I", the data of the RAM is retained during stand-by and it is valid. · GENERAL DESCRIPTION OF INSTRUCTION SET The .HD6303R has an upward object code compatible with the HD6801 to utilize all instruction sets of the HMCS6800. The execution time of the key instruction is reduced to increase the system through-put. In addition, the bit operation instruction, the exchange instruction between the index and the accumulator, the sleep instruction are added. This section describes: ·CPU programming model (See Fig. 20) · Addressing modes ·Accumulator and memory manipulation instructions (See Table 7) ·New instructions · Index register and stack manipulation instructions (See Table 8) ·Jump and branch instructions (See Table 9) ·Condition code register manipulation instructions (See Table 10) ·Op-code map (See Table 11) ·Cycle-by-cycle operation (See Table 12) · CPU Programming Model The programming model for the HD6303R is shown in Fig- ure 20. The double accumulator is physically the same as the accumulator A concatenated with the accumulator B, so that the contents of A and B is changed with executing operation of an accumulator D. t. · ·LJ' · 3 ,,_ - - - - - - - o - - - - - - - - ; 8O-·8;116A-8;«1uOmou·b'l"o"A" «Au'm""ulaoto' 0 , . ,.. x . ·I lnci,I( Register tXI ·I Stack Poifller ISP) I" PC o( Prograr'n Counter IPCI ' 0 Condit-ion Code Register (CCR) Carry/Borrow from MSB Overflow Zero Negative Interrupt Half Carry !From Bit 31 Figure 20 CPU Programming Model · CPU Addressing Modes The HD6303R has seven address modes which depend on both of the instruction type and the code. The address mode for every instruction is shown along with execution time given in terms of machine cycles (Table 7 to 11 ). When the clock frequency is 4 MHz, the machine cycle will be microseconds. Accumulator (ACCXI Addressing Only the accumulator (A or B) is addressed. Either accumulator A or B is specified by one-byte instructions. Immediate Addressing In this mode, the operand is stored in the second byte of the instruction except that the operand in LDS and LDX, etc are stored in the second and the third byte. These are two or three-byte instructions. Direct Addressing In this mode, the second byte of instruction indicates the address where the operand is stored. Direct addressing allows the user to directly address the lowest 256 bytes in the machine; locations zero through 255. Improved execution times are achieved by storing data in these locations. For system configuration, it is recommended that these locations should be RAM and be utilized preferably for user's data realm. These are two-byte instructions except the AIM, OIM, EIM and TIM which have three-byte. Extended Addressing In this mode, the second byte indicates the upper 8 bit addresses where the operand is stored, while the third byte indicates the lower 8 bits. This is an absolute address in memory. These are three-byte instructions. Indexed Addressing In this mode, the contents of the second byte is added to the lower 8 bits in the Index Register. For each of AIM, OIM, EIM and TIM instructions, the contents of the third byte are added to the lower 8 bits in the Index Register. In addition, the result· ing "carry" is added to the upper 8 bits in the Index Register. The result is used for addressing memory. Because the modified address is held in the Temporary Address Register, there is no change to the Index Register. These are two-byte instructions but AIM, OIM, EIM, TIM have three-byte. Implied Addressing In this mode, the instruction itself gives the address; stack pointer, index register, etc. These are I-byte instructions. Relative Addressing In. this mode, the contents of the second byte is added to the lower 8 bits in the program counter. The resulting carry or borrow is added to the upper 8 bits. This helps the user to address the data within a range of -126 to +129 bytes of the current execution instruction. These are two-byte instructions. 166 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 7 Accumulator, Memory Manipulation Instructions ()pemioftl Add AddOaablo Add Aeeumutnors Add With C..ry ANO Bit Test Clur eon-e Compere Accumul1tors Complement, , ., Complement, 2'1 (N. . . . .I Decimal Adjust. A Cloe........ EJCclusiw OR 1........... LAccumuletor Un- ~Double Accumulator Multiply OR, Inclusive Pt.tlh Oete Pull OM.II R.,....Left Rotete Right Mnemonk: ADDA AODB ADDO ABA AOCA AOCB ANDA ANOB BITA BIT B CLR CLRA CLRB CMPA CMP8 C!A COM COMA COMB NEG NEGA NEGB OAA DEC OECA OECB EORA EORB INC INCA INCB LOAA LDAB LOO MUL ORAA ORAB PSHA PSHB PULA PULB AOL ROLA ROLB ROA RORA RORB Condition Codi Addressing Modes Register 1-EO DIRECT INDEX EXTEND IMPllEO B-/ Arithmetic Operation · 5 3 2 10 OP - # OP - # OP - # OP - # OP - # H INZ v c · . BB 2 2 9B 3 2 AB 4 2 BB 3 A+M-A · · . CB 2 2 DB 3 2 EB 2 FB 3 B+M-8 · . . CJ 3 3 03 2 E3 5 2 F3 5 3 A:8+M:M+1-A: B . 1B 1 1 A+B-+A · · . BB 2 2 99 3 2 A9 2 89 3 · · . C9 2 2 09 3 2 ES 2 F9 3 A+M+C-A a+M+c ..... a · · . . . 84 2 2 94 3 2 A4 2 84 3 A·M-+A · · .. . C4 2 2 04 3 2 E4 2 F4 3 B·M-B · · .. . 85 2 2 95 3 2 A5 2 B5 3 A·M · · .. . C5 2 2 05 3 2 E5 2 F5 3 B·M . 6F 5 2 7F 5 3 00-M . 4F 1 1 00-A . 5F 1 1 oo-e · · . . 81 2 2 91 3 2 A1 2 B1 3 A-M · · .. C1 2 2 01 3 2 E1 2 F1 3 B-M I IIII I IIII I I I I I IIII I I I I I I I I I I I IR I IR I IR I IR · RsRR · RsRR · RsRR I I I I I I I I .. 11 1 1 A-8 . · 63 6 2 73 6 3 M-M .. 43 1 1 A-A .. 53 1 1 I" -8 .. 60 6 2 70 6 3 00-M-M . . 40 1 1 00-A-A . . 50 1 1 oo-B-B Converts bin1ry ICld of BCO . . 19 2 1 eheracters into BCD formM . · 6A 6 2 7A 8 3 M-1-+M . . 4A 1 1 A-1 -A . . 5A 1 1 B - 1-B · · . . . 88 2 2 9B 3 2 A8 2 BB 3 A@M-A · · . · C8 2 2 08 3 2 E8 2 FB 3 8@M- B . . 6C 6 2 7C 6 3 M+t-+M . 4C 1 1 A·+ 1 -A · .· 5C 1 1 8+1- B · · .. . 88 2 2 96 3 2 A6 2 86 3 M-A · · .. . C6 2 2 06 3 2 E6 2 F6 3 M-B I I I I I I Rs I I Rs I I Rs I I © 1> I I (i) 00 I I ©(). I I I (j) I I @. I I @· I I @· I IR ~I IR I I . I I . I I . I IR I IR . . . cc 3 3 DC 4 2 EC 5 2 FC 5 3 M + t- 8, M-+ A I IR . . 30 1 1 AxB-+A:B · . . · · . BA 2 2 9A 3 2 AA 2 BA 4 3 A+M-+A · . . CA 2 2 DA 3 2 EA 2 FA 4 3 8 + M- B · ....· . 36 1 A - Mtl'. sP - 1 - sP .. · .. 37 1 B -Mtp.SP-1-sP ....· .· .· 32 3 1 SP+ 1-+sP,Mtp-A . . . . .. 33 3 1 sP+1-sP.Mtp-B ...· ~ n:I 88 6 2 79 6 3 48 1 1 :} , . 59 1 I lt1 I 11 11 lO . ·· 88 6 2 76 6 3 =14if . · 46 1 1 · . · 56 1 1 ,,1 I II ii!liO~ · @ I IR I I [if"· I I ~I I I ~I I I t>fT IT t>fT I I (I) I I I ii I Note) Condition Code Register will be explained in Note of Tabl· 10. Cto be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 167 Table 7 Accumulator, Memory Manipulation lnstructioru ()peratton1 Shift Left Arithmetic Double Shift Left, Arithmetic Shilt Right Arithmetic Shih Atght Laglcol Double Shift Right Logicail Stora Accumulator Store Double Accumulator SubtrK1 Double SubtrKt SubtrflCt Accumuletors Subtrect WithC.rry -T,.n1f1r Accumulators T· Zero or Minus And lmmodiote ORlmmedlote EDR lmrnediote Tnt Immediate Mnemonic ASL ASLA ASLB ASLO ASR ASRA ASRB LSR LSRA LSRB LSRD STAA STAB STD SUBA SUBB SUBD SBA SBCA SBCB TAB TBA TST TSTA TSTB AIM DIM EIM TIM Addr111ing Modes Condition~ Roglstor IMMEO DIRECT INDEX EXTEND IMPllED lool·n/ Arithmetic Operatton 54 32 10 OP - # OP - # OP - # OP - # OP - # H INzv c .. 68 6 2 78 6 3 "\ - .. 48 1 1 =~ . 58 1 1 I I () I I I ®I · I I (I) I .. 06 1 1 ~ I 11@ I .. 67 6 2 77 6 3 II I :1~ .. 47 1 1 .. 57 1 1 I I I I ~ rt- . T- 64 6 2 74 6 3 · RI "\ -- ... :~ · 44 1 1 RI 6 I 54 1 1 RI I ~ . ';Cf 04 1 1 o...j A1 ACCNJA/1 I 90~ o R I ~11 .. 97 3 2 A7 4 2 87 4 3 .. 07 3 2 E7 4 2 F7 4 3 A-M B-M I I Ro I I Ro .. . DD 4 2 ED 5 2 FD 5 3 A-M B-M+1 I IR . . BO 2 2 90 3 2 AO 4 2 BO 4 3 . . co 2 2 00 3 2 EO 4 2 FO 4 3 .. 83 3 3 93 4 2 A3 5 2 83 5 3 A-M-A B -M-B A:8-M:M+1-A:8 I I I I I I I I I I I I . . 10 1 1 A-B-A I I I I .. 82 2 2 92 3 2 A2 4 2 82 4 3 A-M-C-A . C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C-B . . 16 1 1 A-B .. 17 1 1 B-A . 60 4 2 70 4 3 M-00 .. 40 1 1 A -00 .. 50 1 1 B - 00 I I I I · IIII · IIR I I R· · I I RR I I RR I I RR 71 6 3 61 7 3 72 6 3 62 7 3 75 6 3 65 7 3 78 4 3 88 5 3 M·IMM-M M+IMM-M MEtllMM-M M·IMM ··I I R· ·· I I R · ·· I I R o ·· I I R e Note) Condition Code Register will be explained in Note of Table 10. 168 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · New lllltnlctlons In addition to the HD6801 Instruction Set, the HD6303R baa the following new instructions: AIM----(M) · (IMM)-+(M) Evaluates the AND of the immediate data and the memory, places the result in the memory. OIM----(M) +(IMM)-+ (M) Evaluates the OR of the immediate data and the memory, places the result in the memory. EIM----(M)(!) (IMM)-+ (M) Evaluates the EOR of the immediate data and the memory, places the result in the memory. TIM----(M) · (IMM) Evaluates the AND of the immediate data and the memory, changes the flag of associated condition code register Each instruction baa three bytes; the first is op-code, the second ii immediate data, the third is address modifier. XGDX--(ACCD) .. (IX) Exchanges the contents of accumulator and the index register. SLP- - - -The MPU is brought to the sleep mode. For sleep mode, see the "sleep mode" section. Table 8 Index Register, Stack Manipulation Instructions """'· Oporolionl CDoecmrpemoreen·t -ln·d"lx"A'll Dlcrement S1Kk Pntr Increment lndl· Reg tnc,..,..nt Sieck Pn1r LoedlndlxRlt LOltd S1Hlc Pntr Store Index A11 -Store Steck Pntr ·Index A19 - StKk Pntr Steck Pntr - lndH R.. Pulhllet· Mnemonic cPX DEX DES INX INS LOX LOS STX STS TXS TSX ABX PSHX Addreuing Modts I-ED DIRECT INDEX EXTEND OP - # OP - # OP - # OP - # 8C 3 3 9C 4 2 AC 5 2 BC 5 3 CE 3 3 DE 4 2 EE 5 2 FE 5 3 BE 3 3 IE 4 2 AE 5 2 BE 5 3 DF 4 2 EF 5 2 FF 5 3 9F 4 2 AF 5 2 BF 5 3 Pull Dete PULX Each- XGDX Notel Condition Code Register will be explained in Note of Table 10. IMPLIED - OP # 09 1 1 34 1 1 09 1 1 31 1 1 laolun/ Arithmetic ()pention X-M:M+1 x-1-x SP-1-SP x+1-x sP+1-SP M- XH. CM+ 1)- XL M- sPH, IM+11-sPL XH-+ M. XL ... (M + 1) SPH-M,SPL -IM+11 35 1 1 X-1-sP 30 1 1 SP+1-x 3A 1 1 l+X-4: X 3C 5 1 XL -M,p.SP-1-SP XH- M,p, sP-1-SP 3B 4 1 sP+ 1-SP.M,p-XH sP+ 1- sP, M,p- XL 18 2 1 ACCD-IX Condition Code R.._ 5 4 32 10 H I Nzv c ..I I I I ... .I · .· · · · · . · · · I · . · · · · · · · Q) I R · . ·. (/) I R · · · (/) I R · · · · (/) I R . · · · · · . · · · · · . . · · · · ....· · ....· · ... · · · · ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 169 Table 9 Jump, Branch Instruction Addressing MOdes Operations Mnemonic RELATIVE DIRECT INDEX EXTEND IMPLIED Branch Test Branch Always Branch Never Branch If Carry Cl·r Branch If Carry Set Branch If · Zaro Branch If ;;;i. Zero 8t9nch If > Zero 8r11nch If Higher Branch If < Zero BRA BRN BCC BCS BEO BGE BGT BHI BLE OP - # OP - # OP - # OP - # OP - # 20 3 2 21 3 2 24 3 2 25 3 2 27 3 2 2C 3 2 2E 3 2 22 3 2 2F 3 2 None None C·O C·1 Z·1 N@V·O Z+ IN@VI · 0 C+Z·O Z+fN@Vl·1 Branch If Lower Or Some Branch If < Zero 8,.nch It Minus Branch If Not EqUll Zoro BLS BLT BMI BNE 23 3 2 20 3 2 2B 3 2 26 3 2 C+Z·1 N@V· 1 N· 1 Z·O Branch If Overflow Cloer Branch If Overflow Set 8,.nch If Plus Branch To Subroutine Jump Jump To Subroutine No ()porotion BVC BVS BPL BSR JMP JSR NOP 2B 3 2 2B 3 2 2A 3 2 8D 5 2 &E 3 2 7E 3 3 90 5 2 AO 5 2 BO 6 3 01 1 1 V·O v-1 N·O Advances Prog. Cntr. Only Return From lnterruPt Return From Subroutine Software Interrupt Wait for Interrupt· Sleep RTI RTS SWI WAI SLP 38 10 1 39 5 1 3F 12 1 3E 9 1 1A 4 1 Note) *WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state. Condition Code Register will be explained in Note of Table 10. Co~i::i!";"' ....................H5 ....................4I .................N3 . . · .................z2 . . · ..................··v1 ....................0c -@- .. .. · · . .s · · · ... · (j) · · ···· · 170 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 10 Condition Code Register Manipulation Instructions OplrMiDM C'-C-y CIWI·-- . . . . . .Pl- C'-C>wrflaw SolCltry SotOWrflaw Accumuletor A~ CCR CCA---A MnemoniC CLC CLI CLY SEC SEI SEY TAP TPA - · IMPLIEO OP oc I I OE I I OA I I 00 I I Of I I OI I I OI I I 07 I I loolun ()poroti"" o-c 0-1 o-Y 1-c 1-1 1-Y A- CCA CCA-A Concht:ton Code R..tst:er ......H.s- . · I . . A s . . - 32 I 0 Nz y c . .· A . . . · . . .A . . . s .. .. . . 1r-s -· . . ·T· (NOTE 1] Condition Code Register Notes: (Bit ·t if test is true and cleared otherwi1e) (!) CBil VI Tnl: Result · 10000000? ® CBit Cl Tnt: Result 'I 00000000? @ CBil Cl Test: BCD Character of high-order byte FHltr IMn 9? CN01 clured if preyiously setl @ CBil VI Test: Operand· 10000000 prior to oxacution? @ CBit VI Test: Operand · 01111111 prior 10 execution? @ (Bit V) Test: Set equal to N·C·1 after the execution of instructions CV CBit NI To11: Result Ins 1han zero? CBil 15·1) @ !All Bitl Load Condition Code ROllister from Slack. @ (lit t) Set when interrupt occurs. If previously set. a Non-Mllskeble Interrupt is required to exit the wait st1te. @I CAii Bil) Sol according to the contents of Accumulator A. @ CBit Cl Result of Multiplication Bil 7· 1 of ACCB? (NOTE 21 CLI instruction and interrupt. If interrupt mask-bit Is sol (1-'.1"1 end interrupt is requested mRr. · "0" or TRQ, · "O"l and then CLI instruction is executed, tho CPU ._ndi · follows. ' (j) The next instNction of CLI is one-machine cycle instruction. Subsequent two Instructions are exacutld before tho Interrupt is responded. ® That 11, the next and the next of the next Instruction are exacutld. The next instruction of CLI is two-machine cycle Cor morel instruction. Only tho next Instruction is exacutld and then tho CPU jump to the interrupt routine. Even if TAP instruction is used, insteed of CLI, tha same thing occurs. Table 11 OP-Code Map ~ .., -..., OP CODE 0011 0 ' 0 2 ~ SllA BRA - 0I NOP CIA BRN 0011 2 ~ .../ IHI 0011 a ~ ~ 81.S OIOO 4 LSRD ~ ace 5 ASLD ~ BCS '"'0110 TAP TAB BNE · 0111 1 TPA TBA BEQ ,.. INX XGDX ave ·· 1001 .oEX OM IVS 0011 a TSX INS PULA PULi DES TXS PSHA PSHB PULX RTS ACC A ACC 8 ~ l I ACCA ar SP IND IMM DIR IND] EXT ACCB ar X J IMM DIA] IND1 EXT ------ · '"' OIOO OIOI 0110 4 5 1 NEG AIM OIM COM LSR EIM ROA J I I IOGO] 1001 ] IOIO j IOll 1100 1111 mo 1111 ·1·1A]a c]o]E]F SUB CMP SBC SUBO ADDO AND BIT LOA ASR .../l STA .............. ] STA ASL EOR ROL ADC 0 2 ' a 4 5 · 1 · · 1011 A CLY SLP IPL ABX DEC ORA A 1011 B SEV ABA BMI RTI - - - 1 TIM ADD B "'? 1100 c CLC BGE PSHX INC CPX LOO c 1101 D SEC ............ ILT MUL TST -1 JSR ~J. STD D "'' E Cll 1111 F SEI 0 ............ BGT WAI ..........-1.........-:J. JMP --;? 81.E SWI CLR ' · 2 a 4 5 1 LOS "::;7[ STS ·J I l Aj B LOX .....c......J-i STX o] E] F E F UNDEFINED OP CODE c:;;:::::i · Only for instructions of AIM, OIM, EIM, TIM @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 171 · Instruction Execution Cycles In the HMCS6800 series, the execution cycle of each instruc- tion ii the number. of cycles between the start of the current instruction fetch and just before the start of the subsequent instruction fetch. The HD6303R uses a mechanism of the pipeline control for the instruction fetch and the subsequent instruction fetch ii perfonned during the current instruction being executed. Therefore, the method to count instruction cycles used in the HMCS6800 series cannot be applied to the instruction cycles such as MULT, PULL, DAA and XGDX in the HD6303R. Table 12 provides the information about the relationship among each data on the Address Bus, Data Bus, and R/W status in cycle-by-cycle basil during the execution of each instruction. Address Mode S. Instructions Table 12 Cycle-by.Cycle Operation Cycles Cycle # Address Bus R/W Data llus IMMEDIATE ADC ADD AND BIT CMP EOR LOA SBC ORA SUB ADDO CPX LOO LOS LOX SUBD 1 Op Code Address+ 1 2 Op Code Address+ 2 2 1 Op Code Address+ 1 3 2 Op Code Address+2 3 Op Code Address+3 1 Operand Data 1 Next Op Code 1 Operand Data (MSB) 1 Operand Data (LSB) 1 Next Op Code DIRECT ADC AND CMP LOA SBC STA ADD BIT EOR ORA SUB ADDO CPX LOO LOS LOX SUBD STD STS STX JSR TIM AIM EIM OIM 1 Op Code Address+ 1 2 Address of Operand 3 3 Op Code Address+2 1 Op Code Address+ 1 3 2 Destination Address 3 Op Code Address+2 1 Op Code Address+ 1 4 2 Address of Operand 3 Address of Operand+ 1 4 Op Code Address+2 1 Op Code Address+ 1 4 2 Destination Address 3 Destination Address+ 1 4 Op Code Address+2 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer - 1 5 Jump Address 1 Op Code Address+ 1 4 2 Op Code Address+ 2 3 Address of Operand 4 Op Code Address+3 1 Op Code Address+ 1 2 Op Code Address+2 6 3 Address of Operand 4 FFFF 5 Address of Operand 6 Op Code Address+3 1 Address of Operand (LSB) 1 Operand Data 1 Next Op Code 1 Destination Address 0 Accumulator Data 1 Next Op Code 1 Address of Operand (LSB) 1 Operand Data (MSB) 1 Operand Data (LSB) 1 Next Op Code 1 Destination Address (LSB) 0 Register Data (MSB) 0 Register Data (LSB) 1 Next Op Code 1 Jump Address (LSB) 1 Restart Address (LSB) 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Immediate Data 1 Address of Operand (LSB) 1 Operand Data 1 Next Op Code 1 Immediate Data 1 Address of Operand (LSB) 1 Operand Data 1 Restart Address (LSB) 0 New Operand Data 1 Next Op Code - Continued - ~HITACHI 172 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Address Mode & Instructions INDEXED JMP ADC AND CMP LOA SBC TST STA ADD BIT EOR ORA SUB ADDO CPX LOS SUBD LDD LOX STD STS STX JSR ASL COM INC NEG ROR ASR DEC LSR ROL TIM CLR 'AIM EIM OIM Table 12 Cycle-by.Cycle Operation (Continued) Cycles Cycle # Address Bus R/W Data Bus 1 Op Code Address+ 1 3 2 FFFF 3 Jump Address 1 Op Code Address+ 1 2 FFFF 4 3 IX+Offset 4 Op Code Address+2 1 Offset 1 Restart Address (LSB) 1 First Op Code of Jump Routine 1 Offset 1 Restart Address (LSB) 1 Operand Data 1 Next Op Code 1 Op Code Address+ 1 4 2 FFFF 3 IX+Offset 4 Op Code Address+2 1 Op Code Address+ 1 2 FFFF 5 3 IX+Offset 4 IX+Offset+ 1 5 Op Code Address+2 1 Op Code Address+ 1 2 FFFF 5 3 IX+Offset 4 IX+Offset+ 1 5 Op Code Address+2 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer- 1 5 IX+Offset 1 Op Code Address+ 1 2 FFFF 6 3 IX+Offset 4 FFFF 5 IX+Offset 6 Op Code Address+ 2 1 Op Code Address+ 1 2 Op Code Address+ 2 5 3 FFFF 4 IX+Offset 5 Op Code Address+3 1 Op Code Address+ 1 2 FFFF 5 3 IX+Offset 4 IX+Offsat 5 Op Code Address+2 1 Op Code Address+ 1 2 Op Code Address+2 3 FFFF 7 4 IX+Offset 5 FFFF 6 IX+Offset 7 Op Code Address+3 1 Offset 1 Restart Address (LSB) 0 Accumulator Data 1 Next Op Code 1 Offset 1 Restart Address (LSB) 1 Operand Data (MSB) 1 Operand Data (LSB) 1 Next Op Code 1 Offset 1 Restart Address (LSB) 0 Register Data (MSB) 0 Register Data (LSB) 1 Next Op Code 1 Offset 1 Restart Address (LSB) 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Offset 1 Restart Address (LSB) 1 Operand Data 1 Restart Address (LSB) 0 New Operand Data 1 Next Op Code 1 Immediate Data 1 Offset 1 Restart Address (LSB) 1 Operand Data 1 Next Op Code 1 Offset 1 Restart Address (LSB) 1 Operand Data 0 00 1 Next Op Code 1 lmmadiate Data 1 Offset 1 Restart Address (LSB) 1 Operand Data 1 Restart Address (LSB) 0 New Operand Data 1 Next Op Code - Continued - .HITACHI Hitachi America Ltd, · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 173 Table 12 Cycle-by-Cycle Operation (Continued) Address Mode & Cycles Cycle Instructions # Address Bus EXTEND JMP 3 ADC ADD TST AND BIT CMP EOR 4 LOA ORA SBC SUB STA 4 ADDO CPX LOO LOS LOX 5 SUBD STD STS STX 5 JSR 6 ASL ASR COM DEC INC LSR NEG ROL 6 ROR CLR 5 1 Op Code Address+1 2 Op Code Address+2 3 Jump Address 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 Op Code Address+3 1 Op Code Address+ 1 2 Op Code Address+2 3 Destination Address 4 Op Code Address+3 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 Address of Operand+ 1 5 Op Code Address+3 1 Op Code Address+l 2 Op Code Address+2 3 Destination Address 4 Destination Address+ 1 5 Op Code Address+3 1 Op Code Address+1 2 Op Code Address+2 3 FFFF 4 Stack Pointer 5 Stack Pointer- 1 6 Jump Address 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 FFFF 5 Address of Operand 6 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 Address of Operand 5 Oi:i Code Address+3 Data Bus 1 Jump Address (MSB) 1 Jump Address (LSB) 1 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data 1 Next Op Code 1 Destination Address (MSB) 1 Destination Address (LSB) 0 Accumulator Data 1 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data (MSB) 1 Operand Data (LSB) 1 Next Op Code 1 Destination Address (MSB) 1 Destination Address (LSB) 0 Register Data (MSB) 0 Register Data (LSB) 1 Next Op Code 1 Jump Address (MSB) 1 Jump Address (LSB) 1 Restart Address (LSB) 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB} 1 Operand Data 1 Restart Address (LSB) 0 New Operand Data 1 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data 0 00 1 Next Op Code - Continued - 174 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Address Mode & Instructions Table 12 Cycle-by-Cycle Operation (Continued) Cycles Cycle ii Address Bus R/W Data Bus IMPLIED ABA ABX ASL ASLD ASA CBA CLC cu CLR CLV COM DEC DES DEX INC INS INX LSR LSRD AOL ROA NOP SBA SEC SEI SEV TAB TAP TBA TPA TST TSX TXS DAA XGDX PULA PULB PSHA PSHB PULX PSHX ATS MUL 1 Op Code Address+ 1 1 2 1 Op Code Address+ 1 2 FFFF 1 Op Code Address+ 1 3 2 FFFF 3 Stack Pointer+ 1 1 Op Code Address+ 1 4 2 FFFF 3 Stack Pointer 4 Op Code Address+ 1 1 Op Code Address+ 1 4 2 FFFF 3 Stack Pointer+ 1 4 Stack Pointer+ 2 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer - 1 5 Op Code Address+ 1 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer+ 1 4 Stack Pointer+ 2 5 Return Address 1 Op Code Address+ 1 2 FFFF 3 FFFF 7 4 FFFF 5 FFFF 6 FFFF 7 FFFF 1 Next Op Code 1 Next Op Code 1 Restart Address (LSB) 1 Next Op Code 1 Restart Address (LSB) 1 Data from Stack 1 Next Op Code 1 Restart Address (LSB) 0 Accumulator Data 1 Next Op Code 1 Next Op Code 1 Restart Address (LSB) 1 Data from Stack (MSB) 1 Data from Stack (LSB) 1 Next Op Code 1 Restart Address (LSB) 0 Index Register (LSB) 0 Index Register (MSB) 1 Next Op Code 1 Next Op Code 1 Restart Address (LSB) 1 Return Address (MSB) 1 Return Address (LSB) 1 First Op Code of Return Routine 1 Next Op Code 1 Restart Address (LSB) 1 Restart Address (LSB) 1 Restart Address (LSB) 1 Restart Address (LSB) 1 Restart Address (LSB) 1 Restart Address (LSB) - Continued - ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 175 HD6303R.------------------------------- Address Mode & Instructions Table 12 Cycle-by-Cycle Operation (Continued) Cycles Cycle # Address Bus R/W Data Bus IMPLIED WAI RTI SWI SLP 1 Op Code Address+ 1 2 FFFF 3 Stack Pointer 4 Stack Pointer- 1 9 5 Stack Pointer-2 6 Stack Pointer-3 7 Stack Pointer-4 8 Stack Pointer-5 9 Stack Pointer-6 1 Op Code Address+ 1 2 FFFF 3 Stack Pointer +1 4 Stack Pointer+ 2 10 5 Stack Pointer+ 3 6 Stack Pointer +4 7 Stack Pointer+5 8 Stack Pointer+6 9 Stack Pointer+ 7 10 Return Address 1 Op Code Address+1 2 FFFF 3 Stack Pointer 4 Stack Pointer - 1 5 Stack Pointer - 2 12 6 Stack Pointer - 3 7 Stack Pointer - 4 8 Stack Pointer - 5 9 Stack Pointer - 6 10 Vector Address FFFA 11 Vector Address FFFB 12 Address of SWI Routine 1 Op Code Address+ 1 2 FFFF FFFF I r 4 Sleep j 3 FFFF 4 Op Code Address+1 1 Next Op Code 1 Restart Address (LSB) 0 Return Address (LSB) 0 Return Address (MSB) 0 Index Register (LSB) 0 Index Register (MSB) 0 Accumulator. A 0 Accumulator B 0 Conditional Code Register 1 Next Op Code 1 Restart Address (LSB) 1 Conditional Code Register 1 Accumulator B 1 Accumulator A 1 Index Register (MSB) 1 Index Register (LSB) 1 Return Address (MSB) 1 Return Address (LSB) 1 First Op Code of Return Routine 1 Next Op Code 1 Restart Address (LSB) 0 Return Address (LSB) 0 Return Address (MSB) 0 Index Register (LSB) 0 Index Register (MSB) 0 Accumulator A 0 "Accumulator B 0 Conditional Code Register 1 Address of SWI Routine (MSB) 1 Address of SWI Routine (LSB) 1 First Op Code of SWI Routine 1 Next Op Code 1 Restart Address (LSB) High Impedance-Non MPX Mode Address Bus -MPX Mode l Restart Address (LSB) Next Op Code - Continued - 176 @HITACHI Hitachi America Ltd" · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 12 Cycle-by-Cycle Operation (Continued) Address Mode & Cycles Cycle Instructions ii RELATIVE BCC BCS BEQ BGE BGT BHI BLE BLS BLT BMT BNE BPL BRA BRN eve BVS BSR 1 3 2 3 1 2 5 3 4 5 Address Bus R/W Op Code Address+ 1 1 FFFF 1 \Branch Address......Test="1" Op Code Address+ 1.. ·Test="O" 1 Op Code Address+ 1 1 FFFF 1 Stack Pointer 0 Stack Pointer-1 0 Branch Address 1 Data Bus Branch Offset Restart Address (LSB). First Op Code of Branch Routine Next Op Code Offset Restart Address (LSB) Return Address (LSB) Return Address (MSB) First Op Code of Subroutine · LOW POWER CONSUMPTION MODE The HD6303R has two low power consumption modes; sleep and standby mode. This sleep mode is available to reduce an average power consumption in the applications of the HD6303R which may not be always running. · SleepMode On ex1'cution of SLP instruction, the MPU is brought to the sleep mode. In the sleep mode, the CPU stops its op1'ration, but the contents of the registers in the CPU are retained. In this mode, the peripherals of CPU will remain active. So the operations such as transmit and receive of the SCI data and counter may keep in op1'ration. In this mode, the power consumption is reduced to about 1/6 the value of a normal operation. The escape from this mode can be done by interrupt, RES, ~- The RES resets the MPU and the STBY brings it into the standby mode (This will be mentioned later). When interrupt is requested to the CPU and accepted, the sleep mode is released, then the CPU is brought in the operation mode and jumps to the interrupt routine. When the CPU has masked the interrupt, after recovering from the sleep mode, the next instruction of SLP starts to execute. However, in such a case that the timer , interrupt is inhibited on the timer side, the sleep mode cannot be released due to the absence of the interrupt request to the CPU. · Sblndby Mode Bringing "STDY "Low", the CPU becomes reset and all clocks of the HD6303R become inactive. It goes into the standby mode. This mode remarkably reduces the power con- sumptions of the HD6303R. In the standby mode, if the HD6303R is continuously sup- plied with power, the contents of RAM is retained. The standby mode should escape by the reset start. The following ii the typical application of this mode. . First, RMI routine stacks the CPU's internal informatioo and the contents of SP in RAM, disables RAME bit of RAM control register, sets the standby bit, and then goes into the standby mode. If the standby bit keeps set on reset start, it means that the power has been kept during stand-by mode and the contents of RAM is normally guaranteed. The system recovery may be possible by returning SP and bringing into the condition before the standby mode has started. The timing relation for each line in this application is shown in Figure 21. ..___~1-------11 r+- ·~·~ l 1 ~: I I 1 I i<-ot ~ OS.kregit11r1 ORAM control regitt9r·t ::::,'=~! time 1---+- rest1rt Figure 21 Standby Mode Timing ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 177 · ERROR PROCESSING When the HD6303R fetches an undefined instruction or fetches an instruction from unusable memory area, it generates the highest priority internal interrupt, that may protect from system upset due to noise or a program error, · Op.code Enor Fetching an undefined op-code, the HD6303R will stack the CPU register as in the case of a normal interrupt and vector to the TRAP (SFFEE, SFFEF), that has a second highest priority CDS is the highest). · Add,_Enar When an instruction is fetched from other than a resident RAM, or an external memory area, the CPU starts the same interrupt as OJH:Ode error. In the case which the instruction is fetched from external memory area and that area is not usable, the address error can not be detected. The address which cause address error are shown in Table 13. 1bla feature is applic:able only to the instruction fetch, not to normal read/write of clata ac:ceuing. Transitions among the active mode, sleep mode, standby mode and reset are shown in Figure 22. Figures 23, 24 show a system configuration. The system flow chart of HD6303R is shown in Figure 25. Table 13 Address Error Address Error Figure 22 Transitions among Active Mode, Standby Mode, Sleep Mode, and Reset HD6303R MPU Enoble 8 16 8 ROM RAM PIA GPIA PTM Address Bus D·t· Bus Figure 23 HD6303R MPU Multiplexed Mode HD6303R MPU 18 8 ROM RAM PIA GPIA PTM -Bu· Det18u1 Figure 24 HD6303R MPU Non-Multiplexed Mode 178 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 PC-PC-1 STACK PCL-MSP PCH-MSP-1 IXL-MSP-2 IXH-MSP-3 ACCA--MSP-4 ACCB-MSP-6 CCR-MSP-6 INTERRUPT REQUEST FLAG EXCEPT NMI CLEAR Figure 25 H06303R System Flow Chart @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 179 · PRECAUTION TO THE BOARD DESIGN OF OSCILLA· TION CIRCUIT As shown in Fig. 26, there is a case that the cross talk dis- turbs the normal oscillation if signal lines are put near the oscillation circuit. When designing a board, pay attention to this. Crystal and CL must be put as near the HD6303R as possible. HD6303R E 30----~ HD6303R Do not use this kind of print board design. Figure 26 Precaution to the boad design of oscillation circuit (TopViewl Fig. 27 Example of Oscillation Circuits in Board Design · PIN CONDITIONS AT SLEEP AND STANDBY STATE · SleepState The conditions of power supply pins, clock pins, input pins_ and E clock pin are the same as those of operation. Refer to Table 14 for the other pin conditions. · Standby State Only power supply pins and "STDY are active. As for the clock pin EXTAL, its input is fixed internally so the MPU is not influenced by the pin conditions. XTAL is in "I" output. All the other pins are in high impedance. p~de P20 - p,. Function Condition Ao/Pio A1/P11 Function Condition Aa -A1s Do/AoD1/A.1 Function Condition Function Condition R/W Function Condition AS Table 14 Pin Condition in Sleep State Non Multiplexed Mode 1/0 Port Keep the condition just before sleep Address Bus (A0 -A1I Output "1" Address Bus (A1 -Aul Output "1" Data Bus (D0 -D1I High Impedance R/WSignal Output "1" - Multiplexed Mode -1/0 Port 1/0 Port Keep the condition just before sleep - Address Bus (A1 -Aul E: Address Bus (A0 -A7), E: Data Bus E: Output "1", E: High Impedance -R/WSignal Output AS 180 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ~ n Table 15 Pin Condition during RESET Non-Multiplexed Mode Multiplexed Mode P20 - P24 High Impedance Ao/Pio - A7/P!7 High Impedance As -A1s Do/Ao - D7/A, R/W High Impedance High Impedance "1" Output E : "1" Output E : "1" Output !NoMI (High Impedance) I:: "1"0utput AS E : High Impedance (Note) In the multiplexed mode, the data bus is set to "1" output state during E = "1" and it causes the conflict with the output of external memory. Following 1 and 2 should be done to avoid the conflict; (1) Construct the system that disables the external memory during reset. 12) Add 4.7 kn pull-down resistance to the AS pin to make AS pin "O" level during E = "1 ''. This operation makes the data bus high impedance state. · DIFFERENCE BETWEEN HD6303 AND HD6303R The HD6303R is an upgraded version of the HD6303. The difference between HD6303 and HD6303R is shown in Table 16. Table 16 Difference between HD6303 and HD6303R Item HD6303 HD6303R Operating Mode Mode 2: Not defined Mode 2: Multiplexed Mode (Equivalent to Mode 4) Electrical Characteristics The electrical characteristics of 2MHz version (B version) are not spec- ified. Some characteristics are improved. The 2MHz version is guaranteed. Timer Has problem in output compare function. (Can be avoided by soft- ware.) The problem is solved. · RECEIVE MARGIN OF THE SCI Receive margin of the SCI contained in the HD6303R is shown in Table 17. Note: SCI = Serial Communication Interface HD6303R Table 17 Bit distortion tolerance (t-to) /to ±37.5% Character distortion tolerance (T-To) /To Ideal Waveform START 2 3 4 5 6 8 STOP I r--to--1 Bit length ""·1------------Character length T0 - - - - - - - - - - Rul Waveform · APPLICATION NOTE FOR HIGH SPEED SYSTEM DESIGN USING THE HD6303R This note describes the solutions of the potential problem caused by noise generation in the system using the HD6303R. The CMOS ICs and LSls featured by low power consumption and high noise immunity are generally considered to be enough with simply designed p9wer source and the GND line. But this does not apply to the applications configured of high speed system or of high speed parts. Such high speed system may have a chance to work incorrectly because of the noise @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 181 by the transient current generated during switching. One of example is a system in which the HD6303R directly accesses high speed memory such as the HM6264. The noise generation owing to the over current (Sometimes it may be several hundreds mA for peak level.) during switching may cause data write error. This noise problem may be observed only at the Expanded Mode (Mode l, 2, 4, 5 and 6) of the Hti6303R. Assuming the HD6303R is used as CPU in a system. I. Noise Occurrence If the HD6303R is connected to high speed RAM, a write error may occur. As shown in Fig. 28, the noise is generated in address bus during write cycle and data is written into an unexpected address from the HD6303R. This phenomenon causes random failures in systems whose data bus load capacitance exceeds the specification value (90 pF max.) and/or the impedance of the GND line is high. E AS R/W X ~_-Noise X - - - . J --~--- Fig. 28 Noise Occurrence in address bus during write cycle If the data bus D0 - D7 changes from "FF" to "00", extremely large transient current flows through the GND line. Then the noise is generated on the LSI's Vs pins proportioning to the transient current and to the impedance [Zg) of the GND line. -1 Fig. 30 shows the dependency of the noise voltage on the each parameter. I I o.----c: II I '-I: id I _,.o\_ IHD63~ Fig. 29 Noise Source This noise level. Vn. appears on all output pins on the LSI including the address bus. Zg N Vn: Noise Voltage Zg: GND Impedance Cd: Data bus load capacitance N: Number of data bus lines switching from H to L Fig. 30 Dependency of the noise voltage on each parameter II. Noise Protection To avoid the noise on the address bus during the system operation mentioned before. there are two solutions as follows: The one method is to isolate the HD6303R from peripheral devices so that peripherals are not affected by the noise. The other is to reduce noise level to the extent of not affecting peripherals using analog method. 182 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 1. Noise Isolation Addresses should be latched at the negative edge of the AS signal or at the positive edge of the E signal. The 74LS373 is often used in this case. - ~---------Do O., LS373 0 /A,- D,IA,..,_--e_--1 G HD6303R Ao -A., A1 - A1st---+---- AS ~-------~ "Additional Latch (74LS373 for noise isolation) 2. Noise Reduction As the noise level depends on each parameter such Cd, Vee Zg, the noise level can be reduced to the allowable level by con.' trolling those analog parameters. (a) Transient Current Reduction (I) Reduce the data bus load capacitance. If large load capacitance is expected, a bus buffer should be in· serted. (2) Lower the power supply voltage Vee within specifi· cation. (3) Increase a time constant at transient state by insert· ing a resistor (100 - 2000) to Data Buses in series to keep noise level down. Table 18 shows the relationship between a series resistor and noise level or a resistor and DC/AC characteristics. R Item Noise Voltage Level DC Characteristics f = 1 MHz AC Charac· teristics f=1.5MHz f = 2 MHz Table 18. Resistor 1oL tADL tACCM tADL tASL tACCM No 1.6mA 190ns 395 ns 160 ns 20 ns 270 ns 1000 See Fig. 31 1.6mA No change 190 ns 395 ns 180 ns 20 ns 250 ns 2000 1.0mA -· 210 ns - 375 ns ·----···-·· ·-· 200 --· n..s..... 0 ns 230 ns Fig. 31 shows an example of the dependency of the noise voltage on the load capacitance of the data bus.· conditions i Maximum allowed ) load capacitance of 1.5 Vee= 5.0V Cd = 90 the HD6303R specification Ta= 2s·c Zg = 0 l N·S >rc·o >0: ~ 0.5 *Note: The value of series resistor should be carefully selected because it heavily depends on each parameter of actual application system. Fig. 32 shows the typical wave form of the noise. E pin so 100 Data bus load capacitance Cd [pF] Fig. 31 A1 pin ns Fig. 32 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 183 (b) Reduction of GND line impedance (I) Widen the GND line width on the PC board. (2) Place the HD6303R close by power source. (3) Insert a bypass capacitor between the Vee line and the GND of the HD6303R. A tantalum capacitor (about 0.lµF) is effective on the reduction. PoW.r Source (Recommended) Power Source Fig. 33 Layout of the HD11303R on the PC board · POWER.ON RESET At power-on It Is necessary to hold i(g "low" to reset the Internal state of the device and to provide sufficient time for the oscillator to stabilize. Pay attention to the following. *Just after power-on, the MPU doesn't enter reset state until the oscWation starts. This Is because the reset signal is Input Internally, with the clocked synchronization as shown below. RES pin a----10 Q t - - - - - - - - lntamel reset signal Inside the LSI Fig. 34 Reset Circuit Thus, just after power-on the LSI state (I/O port, mode condition etc.) is unstable until the oscillation starts. If it is necessary to inform the LSI state to the external devices during this period, it needs to be done by the external circuits. 184 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6303X,HD63A03X, HD63B03X CMOS MPU(Micro Processing Unit) The HD6303X is a CMOS 8-bit micro processing unit (MPU) which includes a CPU compatible with the HD6301VI, 192 bytes of RAM, 24 parallel I/O pins, a Serial Communication Interface (SCI) and two timers on chip. HD6303XP, HD63A03XP, HD63B03XP · FEATURES · Instruction Set Compatible with the HD6301V1 · 192 Bytes of RAM · 24 Parallel 1/0 Pins 16 1/0 Pins-Port 2, 6 B Input Pins-Port 5 · Darlington Transistor Qrive (Port 2, 61 · 16-Bit Programmable Timer Input Capture Register x 1 Free Running Counter x 1 Output Compare Register x 2 · 8-Bit Reloadable Timer External Event Counter Square Wave Generation · Serial Communication Interface · Memory Ready · Halt · Error-Detection (Address Trap, Op-Code Trapl · Interrupts ... 3 External, 7 Internal · Up to 65k Bytes Address Space · Low Power Dissipation Mode Sleep Mode Standby Mode · Minimum Instruction Execution Time -0.5µs (f· 2.0 MHz) · Wide Range of Operation Vee= 3-6V (f =0.1 -o.5 MHz). f=0.1-1.0MHz;HD6303X Vee· 5V±10% [ f = 0.1 - 1.5 MHz; HD63A03X f = 0.1 - 2.0 MHz; HD63B03X (DP-648) HD6303XF, HD63A03XF, HD63B03XF (FP-80) HD6303XCP, HD63A03XCP, HD63B03XCP (CP-681 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435·8300 185 · PIN ARRANGEMENT (Top View) · HD6303XP, HD63A03XP, HD63803XP v. 0 E XTAL RD EXTAL 3 WR" MPo 'R/W MP1 [!If mllRv Nm BA Do 01 Pao D1 Pu Da Pu 1 o. .P.a..i D1 D1 ,.,Pao Pao D1 Ao .................... A1 Az A1 A. Al Al .P...a..o.. A1 Vu Al "............·.... Al Ato A11 A11 A11 '',.··, A1· At1 Vee · HD6303XCP, HD63A03XCP, HD83803XCP · HD6303XF, HD63A03XF, HD63803XF P20 P21 0 oD2. P22 P23 1 oo.. P24 Os P2s 01 P2a NC P21 Ai> NC A1 Pso A, Ps1 A· Ps2 2 Aa Ps3 2 As P54 Aa "·· Psa A1 Yss Ps1 As 186 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · BLOCK DIAGRAM Vee---- Vss Vss P2o(Tin) P21(Tout1) P22(SCLK) P23(Rx) P24(Tx) P2s(Tout2) P2e(Tout3) P21(TcLK) a:0NQ 0.. 0 IN? t'. 0 OQ N ~ if v l\i ...___ I'~lllllll _L ...J ...J ~ x ~ w x !a!:1!0!:1!a!:a:;: I~ :i:: CPU ~la3::: Ba'_:: I!!:< ,Cl) ;>- - ...._ ~ '--- Q; I/I. E t= " L---1 '-----! u CJ) /\. I\, Pso(IRQ1,) Ps1(1lm22i) Ps2(M R) Ps3(RA[f) Ps· Pss Ps· Ps1 N r--- Q; E v1 t= ...-- "' 0 0.. .____ ""' Cl) !.!,! 0 ""'Cl) -"""0'' "<( Peo- P.,- Pu- "' P u - P.. - ~ Pes- Pee- Pe,- /l a: " 0 0 i"f' J RAM 192 Bytes .____ ,___ RD WR ' - - R;W LIR BA ..---- 1--- Do _]\ ..:J!;! t - - D, t - - D, ID 1--- D, ..I :J ID 1--- D. !!! t - - Ds 0 t - - De .____1--- D, ...-- f--- Ao £ t-- A, I\ ::> ID t - - A2 .::> f--- A, ID .., -0 t-- A, f--- A, v 'O !---- Ao . <( _ _t - - A, ...-- .~, t - - ::: t---- .::> ID !---- ::J f - - - -v~ ID ::: ~ f--t---- 'O 'O t-- <( .____t---- @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 187 · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol Vee Vin Topr T11g Value Unit -0.3-+7.0 v -0.3 - Vcc+o.3 v 0-+10 ·c -55- +150 ·c (NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field. But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the normal operation, we recommend Vin· Vout= Vss ~(Vin or Vout) ~Vee· · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee = 5.0V±10%, Vss - ov. T· = o-+70°C, unless otherwise noted.) Item Symbol RES, STBY Input "High" Voltage EXTAL V1H Other Inputs Input "Low" Voltage All Inputs V1L Input Leakage Current Three State (off-state) Leakage Current NMI, RES,STBY, MP0 , MP1, Port 5 Ao-A1s. Do-D1. RD, WR, R/W,Port 2,Port 6 ll;nl llTsil Output "High" Voltage Output "Low" Voltage Darlington Drive Current Input Capacitance Standby Current All Outputs All Outputs Ports 2, 6 All Inputs Non Operation VoH VoL -loH Cin lsTB Current Dissipation* RAM Standby Voltage lsLP Ice VRAM Test Condition V;n = 0.5-Vcc-0.5V min typ Vcc-0.5 - Vccx0.7 - 2.0 - -0.3 - -- V;n = 0.5-Vcc-0.5V - - loH = -200µ.A loH = -10µ.A loL = 1.6mA Vout = 1.5V 2.4 - Vcc-0.7 - -- 1.0 - Vin= OV, f = 1MHz, Ta= 25°C - - - 3.0 Sleeping (f = 1MHz**) - 1.5 Sleeping (f = 1.5MHz**) - 2.3 Sleeping (f = 2MHz**) - 3.0 Operating (f = 1MHz**) - 7.0 Operating (f = 1.5MHz**) - 10.5 Operating (f = 2MHz**) - 14.0 2.0 - · V 1H min= Vcc-1.0V, v 1L max= O.BV , All output terminals are at no load . .. Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. values about Current Dissipations at x MHz ope,ration are decided according to the following formula; typ. value (I = x MHz} = typ. value (f = 1MHz) · x max. value (f = x MHz)· ma·. value If= 1MHz) · x (both the sleeping and operating) max Vee +0.3 O.B 1.0 1.0 - 0.4 10.0 12.5 15.0 3.0 4.5 6.0 10.0 15.0 20.0 - Unit v v µ.A µ.A v v v mA pF µ.A mA mA mA mA mA mA v 188 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · AC CHARACTERISTICS (Vee= 5.0V±10%, Vss = OV, Ta· 0-+70°C, unleuoth-ise noted.I BUS TIMING Item Symbol Test Condition HD6303X min typ max HD63A03X min typ max HD63B03X Unit min typ max Cycle Time teyc 1 - Enable Rise Time te, -- Enable Fall Time te1 -- Enable Pulse Width "High" Level" PWeH 450 - Enable Pulse Width "Low" Level" PWeL 450 - Address, R/WDelay Time· tAo -- Data Delay Time }write to ow -- Data Set-up Time }Read Address, R/W Hold Time· tosR tAH 80 - Fig. 1 80 - Data Hold Time [Write" tHw 1Read tHR 80 0 - RD, WR Pulse Width" PWRw 450 - RD, WR Delay Time tRwo -- RO, WR Hold Time tHRW -- CTR Delay Time to LR -- LIA Hold Time tHLR 10 - MR Set-up Time" tSMR 400 - MR Hold Time· tHMR Fig. 2 - - E Clock Pulse Width at MR PWeMR -- 10 0.666 - 25 - - 25 - - - 300 - - 300 - 250 - - 200 - - - 70 - - 50 - - 50 - - 0- - 300 - 40 - - 30 - - 200 - - - 10 - - 280 - 90 - - 9- - 10 0.5 - 25 - - 25 - - - 220 - - 220 - 190 - - 160 - - - 70 - - 35 - - 40 - -0- - 220 - 40 - - 30 - - 160 - - - 10 - - 230 - 40 - - 9- - 10 µs 25 ns 25 ns - ns - ns 160 ns 120 ns - ns - ns - ns - ns - ns 40 ns 25 ns 120 ns - ns - ns 0 ns 9 µs Processor Control Set-up Time tpcs Fig. 3, 10, 11 200 - - 200 - - 200 - - ns Processor Control Rise Time Processor Control Fall Time BA Delay Time Oscillator Stabilization Time Reset Pulse Width tpcr tpcf Fig. 2,3 - - 100 - 100 - - 100 - - 100 - - 100 ns - 100 ns teA Fig. 3 - - 250 - - 190 - - 160 ns tRc Fig. 11 20 - - 20 - - 20 - - ms PWRsT 3 - - 3 - - 3 - - tevc · These timings change in approximate proportion to tcyc· The figures in this characteristics represent those when tcyc is minimum (= in the highest speed operation). PERIPHERAL PORT TIMING Item Symbol Peripheral Data Set-up Time Ports 2, 5, 6 l Peripheral Data Hold Time Ports 2, 5, 6 Delay Time (Enable Negative Transition to Ports 2, 6 Peripheral Data Valid) tposu tpoH tPWO Test Condition Fig. 5 Fig. 5 Fig. 6 HD6303X min typ max 200 - - 200 - - - - 300 HD63A03X min typ max 200 - - 200 - - - - 300 HD63B03X Unit min typ max 200 - - ns 200 - - ns - - 300 ns @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 189 TIMER, SCI TIMING Item Timer 1 Input Pulse Width Delay Time (Enable Positive Transition to Timer Output) 1 SCI Input Async. Mode j Clock Cycle Clock Sync. SCI Transmit Data Delay Time (Clock Sync. Mode) SCI Receive Data Set-up Time (Clock Sync. Mode) SCI Receive Data Hold Time (Clock Sync. Mode) SCI Input Clock Pulse Width Timer 2 Input Clock Cycle Timer 2 Input Clock Pulse Width Timer 1·2. SCI Input Clock Rise Time Timer 1·2, SCI Input Clock Fall Time Symbol tPWT tToo tScyc tTXO Test Condition Fig. 8 Fig. 7 Fig.8 Fig. 4,8 HD6303X min !}12_ max 2.0 - - - - 400 1.0 - 2.0 - - - - 200 HD63A03X min ~ max 2.0 - - - - 400 1.0 - - 2.0 - - - - 200 HD63803X min ~ max 2.0 - - - - 400 1.0 - - 2.0 - - - - 200 tsRX Fig. 4 290 - - 290 - - 290 - - tHRX 100 - - 100 - - 100 - - tPWSCK 0.4 - 0.6 0.4 - 0.6 0.4 - 0.6 ttcyc 2.0 - - 2.0 - - 2.0- - - tPWTCK Fig. 8 200 - - 200 - - 200 - - tcxr - - 100 - - 100 - - 100 text - - 100 - - 100 - - 100 Unit tcvc ns tcvc tcyc ns ns ns tscyc tcyc ns ns ns 190 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 E Ao-A1s, R/W RD.WR MPUWrite Do-D1 MPU Read Do-D1 tcyc PWeL o.av t,o 2.4V o.av PWeH 1.. (Ef tRWO PWRW o.av to ow 2.4V oav IAH IHRW 2.4V to LR Figure 1 Bus Timing ------PW<M·------.,..i E 2.4V \ \ \ o.av ~---- tHMR MR Figure 2 Memory Ready and E Clock Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 191 Last Instruction Execution Cycle I E HALT Cycle Instruction Execution Cycle BA Figure 3 HALT and BA Timing Synchronous Clock Transmit Data Receive Data · 2.0V is high level when clock input. 2.4V is high level when clock output. Figure 4 SCI Clocked Synchronous Timing fMPU Read l MPUWrite E tPWD PP2e0o--PP2.1, ________., ""o2""...e4...vV.._Da_ta Valid (Outputs) Figure 5 Port Data Set-up and Hold Times tMPU Read) Figure 6 Port Data Delay Times tMPU WriteI @HITACHI 192 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 E Timer 1 - - - - - ,....,,..__..._-'-"" ·. - - - FRC P21. P25 - - - - - - - . ; . . . - Outputs _________, "I'=...__ __ E T2CNT N 00 'TOD~ P 26 Output _ _ _ _~ 1'-"2o.,4.aV..,y.__ _ TCONA =N (a) Timer 1 Output Timing (bl Timer 2 Output Timing Figure 7 Timer Output Timing h--f .. · · * Timer 2; ttcvc SCI ; tscvc **Timer 1; tPWT Timer 2; tPWTCK SCI ; IPWSCK Figure 8 Timer 1·2, SCI Input Clock Timing C=90pF for D0-D1,Ao-A1s. E =30pF for Port 2, Port 6, RD, WR, R/W, BA, LI R R=12kQ Figure 9 Bus Timing Test Loads (TTL Load) Interrupt Test ln!ernal AddreuBus--J\.-+--'"---"---'"--...J'<.__J\..._...J'l.....-J\.-....J'---J\.---'"--.J'l-_,l'\..._J\_ _,l'\..._...J'<._ NMI, ifiOi. IRQ2, IRQ3 DIntearntaal Bus--J'---'"---"--"--...1'.__r..,_ _ _,.,__-"~--'"---"--"--..J'.__,.._ _,.._ _,"---"'- Op Operand Irrelevant PCO- PCB- IXO- IX8- ACCA ACCB CCR Vector Vector First Inst. of Code Op Code Data PC7 PC15 IX7 IX 15 MSB LSB Interrupt Routine Internal Read Internal Write Figure 10 Interrupt Sequence @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 193 ,:=x::::l.,____,,_______ i.xerroal ····ilf'Bl*&._...,.,___________;'::::x::1,-,_______ ·i'W _ __ , . _ _ , , __ _ _ _-;,,~,___r--f. 111! m')\\\\\\111\i* ·-----vvv~~ w. -~\\\\\11\\\\\jjW 1:TD;~ ~·-·)--·----:::PoCa--PCoO- -First-O~m+--i~-PC15 PC7 Instruction Figure 11 Reset Timing · FUNCTIONAL PIN DESCRIPTION · Vee. Vss Vee and Vss provide power to the MPU with SV±10%supply. In the case of low speed operation (fmax = SOOkHz), the MPU can operate with three through six volts. Two Yss pins should be tied to ground. o XTAL, EXTAL These two pins interface with an AT-cut parallel resonant crystal. Divide-by-four circuit is on chip, so if 4MHz crystal oscillator is used, the system clock is !MHz for example. AT Cut Parallel Resonant Crystal Oscillator Co=7pF max Rs=60Q max CJ EXTALt------. Cu =CL2 = lOpF -22pF · 20% (3.2-SMHz) J.c,,J-c,, Figure 12 Crystal Interface EXTAL pin can be drived by the external clock of 45 to 55% duty, and one fourth frequency of the external clock is produced in the LSI. The external clock frequency should be less than four times of the maximum operable frequency. When using the external clock, XTAL pin should be open. Fig. 12 shows an example of the crystal interface. The crystal and CL!, CL2 should be mounted as close as possible to XTAL and EXTAL pins. Any line must not cross the line between the crystal oscillator and XTAL, EXTAL. o STBY This pin makes the MPU standby mode. In "Low" level, the oscillation stops and the internal clock is stabilized to make reset condition. To retain the contents of RAM at standby mode, "O" should be written into RAM enable bit (RAME). RAME is the bit 6 of the RAM/port 5 control register at $0014. RAM is disabled by this operation and its contents is sustained. Refer to "LOW POWER DISSIPATION MODE" for the standby mode. o Reset (RES) This pin resets the MPU from power OFF state and pro- vides a startup procedure. During power-on, RES pin must be held "Low" level for at least 20ms. The CPU registers (accumulator, index register, stack pointer, condition code register except for interrupt mask bit), RAM and the data register of a port are not initialized during reset, so their contents ate unknown in this procedure. To reset the MPU during operation, RES should be held "Low" for at least 3 system-clock cycles. At the 3rd cycle during "Low" level, all the address buses become "High". When RES remains "Low", the address buses keep "High". If RES becomes "High", the MPU starts the next operation. (I) Latch the value of the mode program pins;MP0 and MP 1 · (2) Initialize each internal register (Refer to Table 3). (3) Set the interrupt mask bit. For the CPU to recognize the maskable interrupts IRQ 1 , IRQ2 and IRQ3 , this bit should be cleared in advance. (4) Put the contents(= start address) of the last two addresses ($FFFE, $FFFF) into the program counter and start the program from this address. (Refer to Table I). *The MPU is usable to accept a reset input until the clock 194 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 becomes normal oscillation after power on (max. 20ms). During this transient time, the MPU and 1/0 pins are undefined. Please be aware of this for system designing. · Enable (El This pin provides a TTL-compatible system clock to external circuits. Its frequency is one fourth that of the crystal oscillator or external clock. This pin can drive one TTL load and 90pF capacitance. · Non·Maskllble Interrupt (NMI) When the falling edge of the input signal is detected at this pin, the CPU begins non-maskable interrupt sequence internally. As well as the IRQ mentioned below, the instruction being executed at NMI signal detection will proceed to its completion. The interrupt mask bit of the condition code register doesn't affect non-maskable interrupt at all. When starting the acknowledge to the NMI, the contents of the program counter, index register, accumulators and condition code register will be saved onto the stack. Upon completion of this sequence, a vector is fetched from $FFFC and $FFFD to transfer their contents into the program counter and branch to the non-maskable interrupt service routine. (Note) After reset start, the stack pointer should be initialized on an appropreate memory area and then the falling edge should be input to NMI pin. · Interrupt Request (IRQ1, IRQ2) These are level-sensitive pins which request an internal interrupt sequence to the CPU. At interrupt request, the CPU will complete the current instruction before its request acknowl· edgement. Unless the interrupt mask in the condition code register is set, the CPU starts an interrupt sequence; if set, the interrupt request will be ignored. When the sequence starts, the contents of the program counter, index register, accumulators and condition code register will be saved onto the stack, then the CPU sets the interrupt mask bit and will not acknowledge the maskable request. During the last cycle, the CPU fetches vectors depicted in Table I and transfers their contents to the program counter and branches to the service routine. The CPU uses the external interrupt pins, IRQ1 and ~, also as port pins P50 and Psi. so it provides an enable bit to Bit 0 and I of the RAM port 5 control register at $0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for the details. When one of the internal interrupts, ICI, OCI, TOI, CMI or SIO is generated, the CPU produces internal interrupt signal (IRQ3 ). IRQ3 functions just the same as IRQ 1 or IRQ2 except for its vector address. Fig. 13 shows the block diagram of the interrupt circuit. Priority Highest Lowest Table 1 Interrupt Vector Memory Map Vector MSB LSB FFFE FFFF FFEE FFEF FFFC FFFD FFFA FFFB FFFB FFF9 FFF6 FFF7 FFF4 FFF5 FFF2 FFF3 FFEC FFED FFEA FFEB FFFO FFF1 Interrupt RES TRAP NMI SWI (Software lnterruptl IR01 ICI (Timer 1 Input Capture) OCI (Timer 1 Output Compare 1, 2) TOI (Timer 1 Overflow) CMI (Timer 2 Counter Match) IRQ2 SIO (RDRF+ORFE+TDRE) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 195 Each Register's Interrupt Enable Flog "1 "; Enable, "O"; Disable fR01 Condition i1mi ---~~0-+..--~ Rc;:;:.r ICI I-MASK ICF - - -........C>-"-o-+......::~-""ll";Enabte . , ..; D i l l b l OCF1 OCF2 TOF IR<h CMF RDRF ORFE TORE TRAP Slotp Cllnc:el Sign1I SWI Figure 13 Interrupt Circuit Block Diagram · Mode Program (MP0 , MP 1l To operate MPU, MP0 pin should be connected to "High" level and MP, should be connected to "Low" level (refer to Fig. 15). · Read/Write (R/W) This signal, usually be in read state ("High"), shows whether the CPU is in read ("High") or write ("Low") state to the peripheral or memory devices. This can drive one TTL load and 30pF capacitance. · RD,WR These signals show active low outputs when the CPU is reading/writing to the peripherals or memories. This enables the CPU easy to access the peripheral LSI with RD and WR input pins. These pins can drive one TTL load and 30pF capacitance. · Load Instruction Register (LIRI This signal shows the instruction opecode being on data bus (active low). This pin can drive one TTL load and 30pF capacitance. · Memory Ready IMR; P52 ) This is the input control signal which stretches the system clock's "High" period to access low-speed memories. During thls signal is in "High", the system clock operates in normal sequence. But this signal in "Low'', the "High" period of the system clock will be stretched depending on its "Low" level duration in integral multiples of the cycle tinle. This allows the CPU to interface with low-speed memories (see Fig. 2). Up to 9 µscan be stretched. During internal address space· access or nonvalid memory access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High" period of system clock to allow peripheral devices to access low-speed memories. As this signal is used also as P52 , an enable bit is provided at bit 2 of the RAPtf/port 5 control register at $0014. Refer to "RAM/PORT S CONTROL REGISTER" for more details. · Halt (HALT; P53) This is an input control signal to stop instruction execution and to release buses. When this signal switches to "Low", the CPU stops to enter into the halt state after having executed the present instruction. When entering into· the halt state, it makes BA (P.,.) "High" and also an address bus, data bus, RD, WR, R/W high impedance. When an interrupt is generated in the halt state, the CPU uses the interrupt handler after'the halt is cancelled. (Note) Please don't switch the HALT signal to "Low" when the CPU executes the WAI instruction and is in the interrupt wait state to avoid the trouble of the CPU's operation after the halt is cancelled. · Bus Available (BAI This is an output control signal which is normally "Low" but "High" when the CPU accepts HALT and releases the buses. The HD6800 and HD6802 make BA "High" and release the buses at WAI execution, while the HD6303X doesn't make BA "High" under the same condition. But if the HALT becomes "Low" when the CPU is in the interrupt wait state after having executed the WAl, the CPU makes BA "High" and releases the buses. And when the HALT becomes "High", the CPU returns to the interrupt wait state. 196 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · PORT The HD6303X provides three 1/0 ports. Table 2 gives the address of ports and the data direction register and Fig. 14 the block diagrams of each port. Table 2 Port and Data Direction Register Address Port Port 2 Port 5 Port6 Port Address $0003 $0015 $0017 Data Direction Register $0001 - $0016 Port 2 is also used as an 1/0 pin for the timers and the SCI. When used as an I/0 pin for the timers and the SCI, port 2 except P20 automatically becomes an input or an output depending on their functions regardless of the data direction register's value. Port 2 Data Direction Register 6 5 4 3 · Port2 An 8-bit input/output port. The data direction register (DDR) of port 2 controls the 1/0 state. It provides two bits; bit 0 decides the 1/0 direction of P20 and bit I the 1/0 direction of P21 to P27 ("O" for input, "l" for output). Data Bus A reset clears the DDR of port 2 and configures port 2 as an input port. This port can drive one TTL and 30pF capaci- = tance. In addition, it can produce 1mA current when Vout I .SV to drive directly the base of Darlington transistors. Port Write Signal Port Read Signal ....L. Tri-state Control Port 2 Figure 14 Port Block Diagram · Port 5 An 8-bit port for input only. The lower four bits are also usable as input pins for interrupt, MR and HALT. RAM and port 5. RAM/Port 5 Control Register · Port 6 An 8-bit 1/0 port. This port provides an 8-bit DDR corre- sponding to each bit and can specify input or output by the bit ("O" for input, "I" for output). This port can drive one TTL load and 30pF capacitance. A reset clears the DDR of port 6. In addition, it can produce lmA current when V001 = 1.SV to drive directly the base of Darlington transistors. · BUS · o.-o, These pins are data bus and can drive one TTL load and 90pF capacitance respectively. · Ao-A15 These pins are address bus and can drive one TTL load and 90pF capacitance respectively. 7 6 4 3 2 10 BitO, Bit 1 IR0 1 , IRQ2 Enable Bit (IRQ 1 E, IRQ2 E) When using P50 and P51 as interrupt pins, write "I" in these bits. When "O", the CPU doesn't accept an external interrupt or a sleep cancellation by the external interrupt. These bits become ''O" during reset. Bit 2 Memory Ready Enable Bit (MRE) When using P52 as an input for Memory Ready signal, write "I" in this bit. When "O". the memory ready function is prohibited and P52 can be used as 1/0 port. This bit becomes "I" during reset. · RAM/PORT 5 CONTROL REGISTER The control register located at $0014 controls on-chip Bit 3 Halt Enable bit (HLTE) When using P53 as an input for Halt signal, write "I" in this @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 197 bit. When "O", the halt function is prohibited and P53 can be used as 1/0 port. This bit becomes "l" during reset. (Note) When using P52 and P53 as the input ports in mode 1 and 2, MRE and HLTE bit should be cleared just after the reset. Notice that memory ready and halt function is enable till MRE and HLTE bit is cleared. Bit 4, Bit 5 Not Used. Bit 6 RAM Enable (RAME) On-<:hip RAM can be disabled by this control bit. By re- setting the MPU, "l" is set to this bit, and on-<:hip RAM is enabled. This bit can be written "I" or "O" by software. When RAM is in disable condition (= logic "0"), on-<:hip RAM is invalid and the CPU can read data from external memory. This bit should be "O" before getting into the standby mode to protect on-<:hip RAM data. Vee HD6303X MPU Vss Vss E RD Wll R/W CTR BA 8 Data Bus 16 Address Bus Bit 7 Standby Power Bit (STBY PWR) When Vcc is not provided in standby mode, this bit is cleared. This is a flag for both read/write by software. If this bit is set before standby mode, and remains set even after returning from standby mode, Vcc voltage is provided during standby mode and the on-chip RAM data is valid. Figure 15 Operation Mode · MEMORY MAP The MPU can address up to 6Sk bytes. Fig. 16 gives memory map of HD6303X. 32 internal registers use addresses from "00" as shown in Table 3. Address 00 01 02· 03 04° 05 os· 07* 08 09 OA OB oc OD OE OF 10 11 12 13 14 15 16 Table 3 Internal Register Registers - Port 2 Data Direction Register Rtw*·· w Port 2 R/W - - .· - - - - - - Timer Control/Status Register 1 R/W Free Running Counter ("High") R/W Free Running Counter ("Low") R/W Output Compare Register 1 ("High") R/W Output Compare Register 1 ("Low") R/W Input Capture Register {"High") R Input Capture Register ("Low") R Timer Control/Status Register 2 R/W Rate, Mode Control Register R/W Tx/Rx Control Status Register R/W Receive Data Register R Transmit Data Register w RAM/Port 5 Control Register R/W Port 5 R Port 6 Data Direction Register w Initialize at RESET - $FC - Undefined - - - $00 $00 $00 $FF $FF $00 $00 $10 $00 $20 $00 $00 $7C or $FC - $00 (continued) ®HITACHI 198 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 3 Internal Register Address 17 18* 19 lA 18 lC 10 lE lF*" Registers Port 6 - Output Compare Register 2 ("High") Output Compare Register 2 ("Low") Timer Control/Status Register 3 Time Constant Register Timer 2 Up Counter - Test Register R/W*** R/W - R/W R/W R/W w R/W - Initialize at RESET Undefined - $FF $FF $20 $FF $00 - - · External Address. ·· Tnt Register. Do not accen to thi· register. · · · R : Read Only Register W : Write Only Register R/W: Reed/Write Register H06303X Expanded Mode :=~~ ~~~1 :r.:~~::: External $00401111 Memory SInptaecrenal ~ RAM $00FF ~ and incremented by system clock. The counter value is readable by software without affecting the counter. The counter is cleared by reset. When writing to the upper byte ($09), the CPU writes the preset value ($FFF8) into the counter (address $09, $0A) regardless of the write data value. But when writing to the lower byte ($0A) after the upper byte writing, the CPU writes not only the lower byte data into lower 8 bit, but also the upper byte data into higher 8 bit of the FRC. The counter will be as follows when the CPU writes to it by double store instructions (STD, STX etc.). $09Write SOA Write External Memory Space $FFFF..__ _ _,, · Excludes the following addresses which mey be used externally: $02, $04, $06, $01, $18. Figure 16 H06303X Memory Map · TIMER 1 The HD6303X provides a 16-bit programmable timer which can simultaneously measure an input waveform and generate two independent output waveforms. The pulse widths of both input/output waveforms vary from microseconds to seconds. Timer I is configurated as follows (refer to Fig. 18). Control/Status Register I (8 bit) Control/Status Register 2 (7 bit) Free Running Counter (16 bit) Output Compare Register I (16 bit) Output Compare Register 2 (16 bit) Input Capture Register (16 bit) · Free-Running Counter (FRCI ($0009 : OOOAI The key timer element is a t 6-bit free-running counter driven SFFFB $5AF3 In the case of the CPU write l$5AF31 to the FRC Figure 17 Counter Write Timing · Output Compare Register (OCR) ($0008,$000C; OCR1) ($0019,$001A ;OCR2) The output compare register is a 16-bit read/write register which can control an output waveform. The data of OCR is always compared with the FRC. When the data matches, output compare flag (OCF) in the timer control/status register (TCSR) is set. If an output enable bit (OE) in the TCSR2 is "I", an output level bit (OLVL) in the TCSR will be output to bit I (Tout I) and bit 5 (Tout 2) of port 2. To control the output level again by the next compare, the value of OCR and OLVL should be changed. The OCR is set to $FFFF at reset. The compare function is inhibited for a cycle just after a write to the OCR or to the upper byte of the FRC. This is to begin the comparison after setting the 16-bit value valid in the register and to inhibit the compare function at this cycle, because the CPU writes the upper byte to the FRC, and at the !)ext cycle the counter is set to $FFF8. · For data write to the FRC or the OCR, 2-byte transfer instruction (such as STX etc.) should be used. · Input Capture Register (ICR) ($0000 : OOOE) The input capture register is a 16-bit read only register which stores the FRC's value when external input signal transition @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 199 generates an input capture pulse. Such transition is controlled by input edge bit (IEDG) in the TCSRI. In order to input the external input signal to the edge detecter, a bit of the DDR corresponding to bit 0 of port 2 should be cleared ("O"). When an input capture pulse occurs by the external input signal transition at the next cycle of CPU's high-byte read of the ICR, the input capture pulse will be de· layed by one cycle. In order to ensure the input capture oper· ation, a CPU read of the ICR needs 2-byte transfer instruction. The input pulse width should be at least 2 system cycles. This register is cleared ($0000) during reset. · Timer Control/Status Registar 1 (TCSR1 I ($0008) The timer control/status register 1 is an 8-bit register. All bits are readable and the lower 5 bits are also writable. The upper 3 bits are read only which indicate the following timer status. Bit 5 The counter value reached to $0000 as a result of counting-up (TOF). Bit 6 A match has occured between the FRC and the OCR I (OCFI). Bit 1 Defined transition of the timer input signal causes the counter to transfer its data to the ICR (ICF). The followings are each bit descriptions. Timer Control/Status Register 1 6 54 32 0 ICF OCF1 TOF EICI EOCl1 ETOI IEDG LVL1 $0008 Bit 0 OLVL1 Output Level 1 OLVLI is transferred to port 2, bit I when a match occurs between the counter and the OCR!. If bit 0 of the TCSR2 (OE!) is set to"!", OLVLI will appear at bit I of port 2. Bit 1 IEDG Input Edge This bit determines which edge, rising or falling, of input signal of port 2, bit 0 will trigger data transfer from the counter to the ICR. For this function, the DDR corresponding to port 2, bit 0 should be cleared beforehand. IEDG=O, triggered on a falling edge ("High" to "Low") IEDG= I , triggered on a rising edge ("Low" to "High") Bit 2 ETOI Enable Timer Overflow Interrupt When this bit is set, an internal interrupt (IRQ·) by TOI interrupt is enabled. When cleared, the interrupt is inhibited. Bit 3 EOCl1 Enable Output Compare Interrupt 1 When this bit is set, an internal interrupt (IRQ·) by OCI I interrupt is enabled. When cleared, the interrupt is inhibited. Bit 4 EICI Enable Input Capture Interrupt When this bit is set, an internal interrupt (IRQ3) by !CI interrupt is enabled. When cleared, the interrupt is inhibited. Bit 5 TOF Timer Overflow Flag This read-only bit is set when the counter incre· ments from $FFFF by I. Cleared when the counter's upper byte ($0009) is ready by the CPU after the TCSRI read. Bit 6 OCF1 Output Compare Flag 1 This read-only bit is set when a match occurs be· tween the OCR! and the FRC. Cleared when writing Bit 7 to the OCR! (SOOOB or SOOOC) after the TCSRI or TCSR2 read. ICF Input Capture Flag This read-only bit is set when an input signal of port 2, bit 0 makes a transition as defined by IEDG and the FRC is transferred to the ICR. Cleared when reading the upper byte ($0000) of the ICR following the TCSRI or TCSR2 read. · Timer Control/Status Registar 2 (TCSR2l ($000FI The timer control/status register 2 is a 7-bit register. All bits are readable and the lower 4 bits are also writable. But the upper 3 bits are read-only which indicate the following timer status. ' Bit 5 A match has occured between the FRC and the OCR2 (OCF2). Bit 6 The_ same status flag as the OCF I flag of the TCSR I , bit 6. Bit 1 The same status flag as the ICF flag of the TCSRI, bit 7. The followings are the each bit descriptions. Timer Control/Status Register 2 76543210 ~OCl+LVL~ I 1cF locF1locF2I - oe2 I OE1 lsoooF Bit 0 OE'1 Output Enable 1 This bit enables the OLVLI to appear at port 2, bit I when a match has occurred between the counter and the output compare register 1. When this bit is cleared, bit I of port 2 will be an 1/0 port. When set, it will be an output ofOLVLI automatically. Bit 1 OE2 Output Enable 2 This bit enables the OLVL2 to appear at port 2, bit 5 when a match has occurred between the counter and _the output compare register 2. When this bit is cleared, port 2, bit 5 will be an 1/0 port. When set, it will be an output ofOLVL2 automatically. Bit 2 OLVL2 Output Level 2 OLVL2 is transferred to port 2, bit 5 when a match has occurred between the counter and the OCR2. If bit 5 of the TCSR2 (OE2) is set to "!", OLVL2 will appear at port 2, bit 5. Bit 3 EOCl2 Enable Output Compare Interrupt 2 When this bit is set, an internal interrupt (IRQ·) by OCI2 interrupt is enabled. When cleared, the interrupt is inlubited. Bit 4 Not Used Bit 5 OCF2 Output Compare Flag 2 This read-only bit is set when a match has occurred between the counter and the OCR2. Cleared when writing to the OCR2 ($0019 or SOOIA) after the TCSR2 read. . Bit 6 OCF1 Output Compare Flag 1 Bit 7 ICF Input Capture Flag OCF I and ICF addresses are partially decoded. The CPU read of the TCSRl/TCSR2 makes it possible to read OCFI and ICF into bit 6 and bit 7. Both the TCSRI and TCSR2 will be cleared during reset. (Note) If OBI or OE2 is set to "!" before the first output compare match occurs after reset restart, bit 1 or bit 5 of port 2 will produce "0" respectively. @HITACHI 200 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 $19, S1A Output Compare Register 2 IR(h P21 P2t P20 Figure 18 Timer 1 Block Diagram · TIMER2 In addition to the timer I, the HD6303X provides an 8-bit reloadable timer, which is capable of counting the external event. This timer 2 contains a timer output, so the MPU can generate three independent waveforms (refer to Fig. 19). The timer 2 is configured as follows: Control/Status Register 3 (7 bit) 8-bit Up Counter Time Constant Register (8 bit) · Timer 2 Up Counter (T2CNT) ($0010) This is an 8-bit up counter which operates with the clock decided by CKSO and CKSI of the TCSR3. The CPU can read the value of the counter without affecting the counter. In addition, any value can be written to the counter by software even during counting. The counter is cleared when a match occurs between the counter and the TCONR or during reset. If a write operation is made by software to the counter at the cycle of counter clear, it does not reset the counter but put the write data to the counter. · Time Constant Register ITCONR) ($001Cl The time constant register is an 8-bit write only register. It is always compared with the counter. When a match has occurred, counter match flag (CMF) of the timer control status register 3 (TCSR3) is set and the value selected by TOSO and TOSI of the TCSR3 will appear at port 2, bit 6. When CMF is set, the counter will be cleared simultaneously and then start counting from $00. This enables regular interrupts and waveform outputs without any software support. The TCONR is set to "$FF" during reset. · Timer Control/Sta1Us Register 3 (TCSR31 ($001 Bl The timer control/status register 3 is a 7-bit register. All bits are readable and 6 bits except for CMF can be written. The followings are each pin descriptions. Timer Control/Status Register 3 I I 7 6 54 32 1 0 CMF JEcMtl - T2E lros1lrosolcKs1jcKsol soo1s ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 201 HD6303X Internal Data Bus ~---Timerl FRC Input Clock ..,._ _ _,__Port 2 Select Bit 7 ~ ~ c: :J u 0 Output Level t--+--~>------+-~Port2 Control Bit 6 IRQ3 Figure 19 Timer 2 Block Diagram Bit 0 Bit 1 CKSO Input Clock Select 0 CKS1 Input Clock Select 1 Input clock to the counter is selected as shown in Table 4 depending on these two bits. When an external clock is selected, bit 7 of port 2 will be a clock input automatically. Timer 2 detects the rising edge of the external clock and increments the counter. The external clock is countable up to half the frequency of the system clock. Table 4 Input Clock Select CKS1 0 0 1 1 CKSO 0 1 0 1 Input Clock to the Counter E clock E clock/8* E clock/128* External clock ·These clocks come from the FRC of the timer 1. If one of these clocks is selected as an input clock to the up counter, the CPU should not write to the FRC of the timer 1. Bit 2 Bit 3 TOSO Timer Output Select 0 TOS1 Timer Output Select 1 When a match occurs between the counter and the TCONR timer 2 outputs shown in Table S will appear at port 2, bit 6 depending on these two bits. When both TOSO and TOSI are "O", bit 6 of port 2 will be an 1/0 port. Table 5 Timer 2 Output Select TOS1 0 0 1 1 TOSO 0 1 0 1 Timer Output Timer Output Inhibited Toggle Output* Output "O" Output "1" ·When a match occurs between the counter and the TCONR, timer 2 output level is reversed. This leads to production of a square wave with 50% duty to the external without any software support. Bit 4 T2E Timer 2 Enable Bit When this bit is cleared, a clock input to the up counter is prohibited and the up counter stops. When set to"!", a clock selected by CKSI and CKSO (Table 4) is input to the up counter. (Note) P26 outputs "O" when T2E bit cleared and timer 2 set in output enable condition by TOSI or TOSO. It also outputs "O" when T2E bit set "I" and timer 2 set in output enable condition before the first counter match occurs. Bit 5 Not Used Bit 6 ECMI Enable Counter Match Interrupt When this bit is set. an internal interrupt (IRQJ} by CMI is enabled. When cleared, the interrupt is inhibited. Bit 7 CMF Counter Match Flag This read-only bit is set when a match occurs between the up counter and the TCONR. Cleared by writing "O" by software write (unable to write "I" by software). Each bit of the TCSR3 is cleared during reset. @HITACHI 202 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · SERIAL COMMUNICATION INTERFACE (SCll The HD6303X SCI contains two operation modes; one is an asynchronous mode by the NRZ format and the other is a clocked synchronous mode which transfers data synchronizing with the serial clock. The SCI consists of the following registers as shown in Fig. 20 Block Diagram: Control/Status Register (TRCSR) Rate/Mode Control Register (RMCR) Receive Data Register (RDR) Receive Data Shift Register (RDSR) Transmit Data Register (TDR) · Transmit Data Shift Register (TDSR) The serial 1/0 hardware requires an initialization by software for operation. The procedure is usually as follows: I) Write a desirable operation mode into each correspond- ing control bit of the RMCR. 2) Write a desirable operation mode into each correspond- ing control bit of the TRCSR. When using bit 3 and 4 of port 2 for serial 1/0 only, there is no problem even if TE and RE bit are set. But when setting the baud rate and operation mode, TE and RE should be "O". When clearing TE and RE bit and setting them again, more than I bit cycle of the current baud rate is necessary. If set in less than I bit cycle, there may be a case that the internal transmit/receive initialization fails. · Asynchronous Mode An asynchronous mode contains the following two data formats: 1 Start Bit + 8 Bit Data + I Stop Bit I Start Bit + 9 Bit Data + I Stop Bit In addition, if the 9th bit is set to "I" when making 9 bit data format, the format of I Start bit + 8 Bit Data + 2 Stop Bit is also transferred. Data transmission is enabled by setting TE bit of the TRCSR, then port 2, bit 4 will become a serial output independently of the corresponding DDR. For data transmit, both the RMCR and TRCSR should be set under the desirable operating conditions. When TE bit is set during this process, 10 bit preamble will be sent in 8-bit data format and 11 bit in 9-bit data format. When the preamble is produced, the internal synchronization will become stable and the transmitter is ready to act. The conditions at this stage are as follows. 1) If the TDR is empty (TDRE=l), consecutive l's are produced to indicate the idle state. 2) If the TDR contains data (TDRE=O), data is sent to the transmit data shift register and data transmit starts. During data transmit, a start bit of "O" is transmitted first. Then 8-bit or 9-bit data (starts from bit 0) and a stop bit· "l" are transmitted. When the TDR is "empty", hardware sets TDRE flag bit. If the CPU doesn't respond to the flag in proper timing (the TDRE is in set condition till the next normal data transfer starts from the transmit data register to the transmit sift register), "I" is transferred instead of the start bit "O" and continues to be transferred till data is provided to the data register. While the TORE is "I". "O" is not transferred. Data receive Is possible by setting RE bit. This makes port 2, bit 3 be a serial input. The operation mode of data receive is decided by the contents of the TRCSR and RMCR. The first "O" (space) synchronizes the receive bit flow. Each bit of the following data will be strobed in the middle. If a stop bit is not "I", a framing error assumed and ORFE is set. When a framing error occurs, receive data is transferred to the receive data register and the CPU can read error-generating data. This makes it possible to detect a line break. If the stop bit is "l", data is transferred to the receive data register and an interrupt flag RDRF is set. If RDRF is still set when receiving the stop bit of the next data, ORFE is set to indicate overrun generation. When the CPU read the receive data register as a response to RDRF flag or ORFE flag after having read TRCS, RDRF or ORFE is cleared. (Note) Clock Source in Asynchronous Mode If CC 1 : CCO = I0, the internal bit rate clock is provided at P22 regardless of the values for TE or RE. Maximum clock rate is E+ 16. If both CCI and CCO are set, an external TTL compatible clock must be connected to P22 at sixteen times (16x) the desired bit rate, but not greater than E. · aoclced Synchronous Mode In the clocked synchronous mode, data transmit is sYnchronized with the clock pulse. The HD6303X SCI provides functionally independent transmitter and receiver which makes full duplex operation possible in the asynchronous mode. But in the clocked synchronous mode an SCI clock 1/0 pin is only P22 , so the simultaneous receive and transmit operation is not available. In this mode, TE and RE should not be in set condition ("I") simultaneously. Fig. 21 gives a synchronous clock and a data format in the clocked synchronous mode. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 203 Receive Shift Register BilO Bil7 ROB Rate ·nd Mode Control Register 81tO SS2 CC2 CC1 CCO SS1 SSO HD6303X Internal Data Bus 8117 Transmit Shift Register Bit7 BotO RDRF OAFE TDRE RIE RE TIE TE WU Transm1t/Receive Control and Status Register ~:~=~~ FAC. Up Counter - L __Ba_i.t...R.._a·t·_e··_,__J Figure 20 Serial Communication Interface Block Diagram Data transmit is realized by setting TE bit in the TRCSR. Port 2, bit 4 becomes an output unconditionally independent of the value of the corresponding DOR. Both the RMCR and TRCSR should be set in the desirable operating condition for data transmit. When an external clock input is selected, data transmit is performed under the TORE flag "0" from port 2, bit 4, synchronizing with 8 clock pulses input from external to port 2, bit 2. Data is transmitted from bit 0 and the TORE is set when the transmit data shift register is "empty". More than 9th clock pulse of external are ignored. Synchronous clock Data <:!:======= Transmit Direction ~NotValid · Transmit data is output from a falling edge of a synchronous clock to the next falling edge. · Receive data is latched at the rising edge. Figure 21 Clocked Synchronous Mode Format When data transmit is selected to the clock output, the MPU produces transmit data and synchronous clock at TORE flag clear. Data receive is enabled by setting RE bit. Port 2, bit 3 will be a serial input. The operating mode of data receive is decided by the TRCSR and the RMCR. If the external clock input is selected, RE bit should be set when P22 is "High". Then 8 external clock pulses and the synchronized receive data are input to port 2, bit 2 and bit 3 respectively. The MPU put receive data into the receive data shift register by this clock and set the RDRF flag at the termination of 8 bit data receive. More than 9th clock pulse of external input are ignored. When RDRF is cleared by reading the receive data register, the MPU starts receiving the next data. So RDRF should be cleared with P22 "High" When data receive is selected to the clock output, 8 synchro- nous clocks are output to the external by setting RE bit. So receive data should be input from external, synchronously with this clock. When the first byte data is received, the RDRF flag is set. After the second byte, receive operation is performed and output the synchronous clock to the external by clearing the RDRF bit. · Transmit/Receive Control Status Register ITRCSR) 1$0011) The TRCSR is composed of 8 bits which are all readable. Bits 0 to 4 are also writable. This register is initialized to $20 during reset. Each bit functions as follows. 204 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Transmit/Receive Control Status Register I I I I I 765432 0 IRORFIORFEITOREI RIE RE TIE TE WU $0011 Bit 0 WU Wake-up In a typical multi-processor configuration, the software protocol provides the destination address at the first byte of the message. In order to make un- interested MPU ignore the remaining message, a wake-up function is available. By this, uninterested MPU can inhibit all further receive processing till the next message starts. Then wake-up function is triggered by consecutive l's with I frame length (10 bits for 8-bit data, 11 for 9-bit). The software protocol should provide the idle time between messages. By setting this bit, the MPU stops data receive till the next message. The receive of consecutive "I" with one frame length wakes up and clears this bit and then the MPU restarts receive operation. However, the RE flag should be already set before setting this bit. In the clocked synchronous mode WU is not available, so this bit should not be set. Bit 1 TE Transmit Enable When this bit is set, transmit data will appear at port 2, bit 4 after one frame preamble in asynchronous mode, while in clocked synchronous mode it appears immediately. This is executed regardless of the value of the corresponding OOR. When TE is cleared, the serial 1/0 doesn't affect port 2, bit 4. Bit 2 TIE Transmit Interrupt Enable When this bit is set, an internal interrupt (IRQ3) is enabled when TORE (bit 5) is set. When cleared, the interrupt is inhibited. Bit 3 RE Receive Enable When set, a signal is input to the receiver from port 2, bit 3 regardless of the value of the OOR. When RE is cleared, the serial 1/0 doesn't affect port 2, bit 3. Bit 4 RIE Receive Interrupt Enable When this bit is set, an internal interrupt, IRQ3 is enabled when RDRF (bit 7) or ORFE (bit 6) is set. When cleared, the interrupt is inhibited. Bit 5 TORE Transmit Data Register Empty TORE is set when the TDR is transferred to the transmit data shift register in the asynchronous mode, while in clocked synchronous mode when the TDSR is "empty". This bit is reset by reading the TRCSR and writing new transmit data to the transmit data register. TORE is set to "I" during reset. (Note) TORE should be cleared in the transmittable state after the TE set. Bit 6 ORFE Overrun Framing Error ORFE is set by hardware when an overrun or a fram· ing error is generated (during data receive only). An overrun error occurs when new receive data is ready to be transferred to the ROR during RDRF still being set. A framing error occurs when a stop bit is "O". But in clocked synchronous mode, this bit is not affected. This bit is cleared when reading the TRCSR, then the RDR, or during reset. Bit 7 RDRF Receive Data Register Full RDRF is set by hardware when the RDSR is transferred to the RDR. Cleared when reading the TRCSR, then the RDR, or during reset. (Note) When a few bits are set between bit 5 to bit 7 in the TRCSR, a read of the TRCSR is sufficient for clearing those bits. It is not necessary to read the TRCSR everytime to clear each bit. · Transmit Ra111/Mode Control Regil18r IRMCRI The RMCR controls the following serial 1/0: ·Baud Rate · Clock Source · Data Format · Port 2, Bit 2 Function In addition, if 9-bit data format is set in the asynchronous mode, the 9th bit is put in this register. All bits are readable and writable except bit 7 (read only). This register is set to $00 during reset. Transfer Rate/Mode Control Register I I I I I I I I I 7654321 0 Roe Toe 552 cc2 cc1 cco 551 550 $0010 Bit 0 sso} Bit 1 SS1 Speed Select Bit 5 SS2 These bits control the baud rate used for the SCI. Table 6 lists the available baud rates. The timer I FRC (SS2=0) and the timer 2 up counter (SS2=1) provide the internal clock to the SCI. When selecting the timer 2 as a baud rate source, it functions as a baud rate generator. The timer 2 generates the baud rate listed in Table 7 depending on the value of the TCONR. (Note) When operating the SCI with internal clock, do not perform write operation to the timer/counter which is the clock source of the SCI. Bit2 CCO} Bit 3 CC1 Clock Control/Format Select" Bit4 CC2 These bits control the data fonnat and the clock source (refer to Table 8). · CCO, CC I and CC2 are cleared during reset and the MPU goes to the clocked synchronous mode of the external clock operation. Then the MPU sets port 2, bit 2 into the clock input state. When using port 2, bit 2 as an output port, the OOR of port 2 should be set to"!" and CC I and CCO to ''O" and "I" respectively. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 205 Table 6 SCI Bit Times and Transfer Rates ( 1) Asynchronous Mode SS2 SS1 sso 0 0 0 0 0 1 0 10 0 11 1 - - XTAL E E+16 E+128 E+1024 E+4096 - 2.4576MHz 614.4kHz 26µs/38400Baud 208µs/4800Baud 1.67ms/600Baud 6.67ms/150Baud * 4.0MHz 1.0MHz 16µs/62500Baud 128µs/7812.5Baud 1.024ms/976.6Baud 4.096ms/244.1 Baud * 4.9152MHz 1.2288MHz 13µS/76800Baud 104.2 µS/9600Baud 833.3µs/1200Baud 3.333ms/300Baud * *When SS2 is "I", Timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N. Baud Rate f 32 (N+l) f : input clock frequency to the) ( timer 2 counter N =0-255 (21 Clocked Synchronous Mode · SS2 SS1 sso 0 0 0 00 1 0 10 0 11 - 1 - XTAL E E+2 E+16 E+128 E+512 - 4.0MHz 1.0MHz 2µs/bit 16µS/bit 128µ5/bit 512µs/bit ** 6.0MHz 1.5MHz 1.33µ5/bit 10.7µ5/bit 85.3µS/bit 341 µS/bit ** B.OMHz 2.0MHz 1µS/bit 8µS/bit 64µs/bit 256µs/bit ** *Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is operatable up to DC - I /2 system clock. ·· The bit rate is shown as follows with the TCONR as N. Bit Rate (µs/bit) = 4 (~+ 1 ) f: input clock frequency to the) ( timer 2 counter N =0-255 Table 7 Baud Rate and Time Constant Register Example -...___-.... XTAL Baud Rate~ 2.4576MHz 3.6864MHz 4.0MHz 110 150 300 600 1200 2400 4800 9600 19200 38400 21 · 127 63 31 15 7 3 1 0 - 32· 191 95 47 23 11 5 2 - 35· 207 103 51 25 12 - - - - * E/8 clock is input to the timer 2 up counter and E clock otherwise. 4.9152MHz 43· 255 127 63 31 15 7 3 1 0 B.OMHz 10· 51· 207 103 51 25 12 -- - - 206 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 8 SCI Format and Clock Source Control CC2 CC1 cco Format Mode Clock Source Port 2, Bit 2 0 0 0 B-bit data Clocked Synchronous External Input 0 0 1 B-bitdata Asynchronous Internal Not Used** 0 1 0 8-bit data Asynchronous Internal Output* 0 1 1 B-bit data Asynchronous External Input 1 0 0 B-bit data Clocked Synchronous Internal Output 1 0 1 9-bit data Asynchronous Internal Not Used** 1 1 0 9-bit data Asynchronous Internal Output· 1 1 1 9-bit data Asynchronous External Input ·Clock output regardless of the TRCSR, bit RE and TE. ** Not used for the SCI. I Port 2, Bit 3 Port 2, Bit 4 When the TRCSR, RE bit is "1", bit 3 is used as a serial input. When the TRCSR, TE bit is "1", bit 4 is used as a serial output. Bit 6 Bit 7 TD8 Transmit Data Bit 8 When selecting 9-bit data format in the asynchronous mode, this bit is transmitted as the 9th data. In transmitting 9-bit data, write the 9th data into this bit then write data to the receive data register. ROB Receive Data Bit 8 When selecting 9-bit data format in the asynchronous mode, this bit stores the 9th bit data. In receiving 9-bit data, read this bit then the receive data register. · TIMER, SCI STATUS FLAG Table 9 shows the set and reset conditions of each status flag in the timer I , timer 2 and SCI. As for Timer I ancl Timer 2 status flag, if the set and reset condition occur simultaneously, the set condition is prior to the reset condition. But in case of SCI control status flag, the reset condition has priority. Especially as for OCF I and OCF2 of Timer I, the set signal is generated periodically whenever FRC matches OCR after the set, and which can cause the unclear of the flag. To clear surely, the method is necessary to avoid the occurence of the set signal between TCSR Read and OCR write. For example, match the OCR value to FRC first, and next read TCSR, and then write OCR at once. Table 9 Timer 1, Timer 2 and SCI Status Flag Set Condition ICF FRC-+ ICR by edge input to P20 · Timer 1 OCF1 OCF2 OCRl-FRC OCR2-FRC Timer 2 SCI TOF CMF RDRF ORFE TORE FRC=$FFFF+1 cycle T2CNT=TCONR Receive Shift Register -+ RDR 1. Framing Error (Asynchronous Mode) Stop Bit= 0 2. Overrun Error (Asynchronous Mode) Receive Shift Register -+ RDR when RDRF=l 1. Asynchronous Mode TOR -+ Transmit Shift Register 2. Clocked Synchronous Mode Transmit Shift Register is "empty" 3. IB=o Reset Condition 1. Read the TCSR1 or TCSR2 then ICRH, when ICF=l 2. lml=O 1. Read the TCSR 1 or TCSR2 then write to the OCR1H or OCRl L, when OCF1 =1 2. lml=O 1. Read the TCSR2 then write to the OCR2H or OCR2L, when OCF2=1 2. IB=o 1. Read the TCSR1 then FRCH, when TOF-1 2. IB=O 1. Write "O" to CM F, when CM F = 1 2. RES=O 1. Read the TRCSR then RDR, when RDRF=1 2. IB=O 1. Read the TRCSR then RDR, when ORFE-1 2. RES=O Read the TRCSR then write to the TOR, when TDRE=l (Note) TORE should be reset after the TE set. (Note} 1. -+;transfer 2. For example; "ICRH" means High byte of ICR. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 207 · LOW POWER DISSIPATION MODE The HD6303X provides two low power dissipation modes; sleep and standby. · SleepMode The MPU goes to the sleep mode by SLP instruction execu- tion. In the sleep mode, the CPU stops its operation, while the registers' contents are retained. In this mode, the peripherals except the CPU such as timers, SCI etc. continue their functions. The power dissipation of sleep-condition is one fifth that of operating condition. The MPU returns from this mode by an interrupt, RES or STBY; it goes to the reset state by RES and the standby mode by STBY. When the CPU acknowledges an interrupt request, it cancels the sleep mode, returns to the operation mode and branches to the interrupt routine. When the CPU masks this interrupt, it cancels the sleep mode and executes the next instruction. However, for example if the timer I or 2 prohibits a timer interrupt, the CPU doesn't cancel the sleep mode because of no interrupt request. This sleep mode is effective to reduce the power dissipation for a system with no need of the HD6303X's consecutive operation. · Standby Mode The HD6303X stops all the clocks and goes to the reset state with STBY "Low". In this mode, the power dissipation is reduced conspicuously. All pins except for the power supply, the STBY and XTAL are detached from the MPU internally and go to the high impedance state. In this mode the power is supplied to the HD6303X, so the contents of RAM is retained. The MPU returns from this mode during reset. The followings are typical usage of this mode. Save the CPU information and SP contents on RAM by NMI. Then disable the RAME bit of the RAM control register and set the STBY PWR bit to go to the standby mode. If the STBY PWR bit is still set at reset start, that indicates the power is supplied to the MPU and RAM contents are retained properly. So system can restore itself by returning their pre-standby informations to the SP and the CPU. Fig. 22 depicts the timing ·at each pin with this example. Vee ©NMll © NMI HD6303X STiY ® 1J RES ® STBY RES @ I I I I I 111111 I I I I I 111111 I I I ~ o Save registers o RAM/Port 5 Control Register Set Figure 22 Standby Mode Timing I~ II I I I~ I I I I 1---1 oOscillator Start Time i---;. Restart · TRAP FUNCTION The CPU generates an interrupt with the highest priority (TRAP) when fetching an undefined instruction or an instruction from non-memory space. The TRAP prevents the systemburst caused by noise or a program error. · Op Code Error When fetching an undefined op code, the CPU saves CPU registers as well as a normal interrupt and branches to the TRAP ($FFEE, $FFEF). This has the priority next to reset. · Address Error When an instruction fetch is made from internal register ($0000-SOOI F), the MPU generates an interrupt as well as an op code error. But on the system with no memory in its external memory area, this function is not applicable if an instruction fetch is made from the external non-memory area. This function is available only for an instruction fetch and is not applicable to the access of normal data read/write. (Note) The TRAP interrupt provides a retry function different- ly from other interrupts. This is a program flow return to the address where the TRAP occurs when a sequence returns to a main routine from the TRAP interrupt routine by RTI. The retry can prevent the system burst caused by noise etc. However, if another TRAP occurs, the program repeats the TRAP interrupt forever, so the consideration is necessary in programming. · INSTRUCTION SET The HD6303X provides object code upward compatible with the HD680 I to utilize all instruction· set of the HMCS6800. It also reduces the execution times of key instruc- 208 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 tions for throughput improvement. Bit manipulation instruction, change instruction of the index register and accumulator and sleep instruction are also added. The followings are explained here. CPU Programming Model (refer to Fig. 23) Addressing Mode Accumulator and Memory Manipulation Instruction (refer to Table 10) New Instruction Index Register and Stack Manipulation Instruction (refer to Table 11) Jump and Branch Instruction (refer to Table 12) · Condition Code Register Manipulation (refer to Table 13) Op Code Map (refer to Table 14) · 1'n9ammin9 Model Fig. 23 depicts the HD6303X programming model. The double accumulator D ·consists of accumulator A and B, so when using the accumulator D, the contents of A and B are destroyed. F.----·- ___·u~ ___!_ - -3 ....,_.......... 11 D 0 Or 16·B·t Double Accumul'1or 0 E· ·I .............. oo I·· SP ·I S1.ckfto111HtlsPI I.. PC ' .·I Prop.... COuM· IPCI Oo·d·h~ Oodo . . .,~ ICCRI ·--·-C.·yflklr,_f,OlllMSB .......... '"'.""'" H1llC:.rylFroml1tJI Figure 23 CPU Programming Model · CPU Acldre11ing Mode The HD6303X provides 7 addressing modes. The addressing mode is decided by an instruction type and code. Table 10 through 14 show addressing modes of each instruction with the execution times counted by the machine cycle. When the clock frequency is 4 MHz, the machine cycle time becomes microseconds directly. Accumulator (ACCX) Addressing Only an accumulator is addressed and the accumulator A or Bis selected. This is a one-byte instruction. Immediate Addressing This addressing locates a data in the second byte of an instruction. However, LOS and LDX locate a data in the second and third byte exceptionally. This addressing is a 2 or 3-byte instruction. Direct Addressing In this addressing mode, the second byte of an instruction shows the address where a data is stored. 256 bytes ($0 through $255) can be addressed directly. Execution times can be reduced by storing data in this area so it is recommended to make it RAM for users' data area in configurating a system. This is a 2-byte instruction, while 3-byte with regard to AIM, OIM, EIM and TIM. Extended Addressing In this mode, the second byte shows the upper 8 bit of the data stored address and the third byte the lower 8 bit. This indicates the absolute address of 3-byte instruction in the memory. Indexed Addressing The second byte of an instruction and the lower 8 bit of the index register are added in this mode. As for AIM, OIM, EIM and TIM, the third byte of an instruction and the lower 8 bits of the index register are added. This carry is added to the upper 8 bit of the index register and the result is used for addressing the memory. The modified address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte instruction except AIM, OIM, EIM and TIM (3-byte instruction). Implied Addressing An instruction itself specifies the address. That is, the instruction addresses a stack pointer, index register etc. This is a one-byte instruction. Relative Addressing The second byte of an instruction and the lower 8 bits of the program counter are added. The carry or borrow is added to the upper 8 bit. So addressing from -126 to +129 byte of the current instruction is enabled. This is a 2-byte instruction. (Note) CLI, SEI Instructions and Interrupt Operation When accepting the IRQ at a preset timing with CLI and SEI instructions, more than 2 cycles are neces· sary between the CLI and SEI instructions. For example, the following program (a) (b) don't accept the IRQ but (c) accepts it. CLI CLI CLI NOP SEI NOP NOP SEI SEI (a) (b) (c) The same thing can be said to the TAP instruction instead of the CU and SEI instructions. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose. CA 95131 · (408) 435-8300 209 Table 10 Accumulator, Memory Manipulation Instructions Oper1tions Add Add Double Add Accumuletors Add With Otrry AND Bit Test Clear Compare ComP11re Accumulators Complement, 1's Complement, 2's CNeptel Oecim1I AdJust. A Decrement Exclusive OR Increment Lood Accumulator La.d Double Accumulator Multiply Unsigned OR. lnclu11ve Push Oeta Pull O·t· Rotate Leh Rotate Rtght Mnemonic ADDA ADDB ADDO ABA ADCA ADCB ANDA ANDB BIT A BIT B CLR CLRA CLRB CMPA CMPB CBA COM COMA COMB NEG NEGA NEGB DAA DEC DECA DECB EORA EORB INC INCA INCB LDAA LDAB LDD MUL ORAA ORAB PSHA PSHB PULA PULS ROL ROLA ROLB ROR RORA RORB Condition Code Addressing Modes Register IMMEO DIRECT INOEX EXTEND IMPLIED - - - - - OP # OP # OP # OP # OP # Boolean/ Artthmetic Opention s4 32 10 H I Nzvc · . SB 2 2 98 3 2 AB 4 2 BB 3 A+M-A I . CB 2 2 DB 3 2 EB 4 2 FB 4 3 . . s C3 3 3 03 4 2 E3 5 2 F3 3 B+M-B I A:B+M:M+1-A: B . 1B 1 1 A+B-A I . B9 2 2 99 3 2 A9 4 2 89 4 3 A+M+C-A I . C9 2 2 D9 3 2 E9 4 2 F9 4 3 B+M+C-B I . . 84 2 2 94 3 2 A4 4 2 B.4 4 3 A·M-+A . . . C4 2 2 04 3 2 E4 4 2 F4 4 3 B·M-+B . . . BS 2 2 95 3 2 AS 4 2 BS 4 3 A·M . . . cs 2 2 DS 3 2 ES 4 2 FS 4 3 .. 6F s 2 7F 5 3 B·M 00-M . . 4F 1 1 00-A . . SF 1 1 oo-B . . 81 2 2 91 3 2 J\1 4 2 81 4 3 A-M · . . C1 2 2 01 3 2 E1 2 F1 4 3 8-M I II I I I I I I I I I I I I I I I I I I I I I · I I R I IR I IR I IR R s R R R s RR R sRR I I I I I I I I .. 11 1 1 A-B . . 63 6 2 73 6 3 M-M . . 43 1 1 A-A .. S3 1 1 B -a . . 60 6 2 70 6 3 00-M-M . . 40 1 1 00-A-A . . 50 1 1 00-B-B .. 19 2 1 Converts bin1ry add of BCD chlracters into BCD formet . . ., . 6A 6 2 7A 6 3 M-1-M .. ., . 4A 1 1 A-1-A .. ., . SA 1 1 B - 1-B · · . . . 88 2 2 9B 3 2 AB 2 BB 3 A@M-A · · .. . CB 2 2 DB 3 2 EB 2 FB 3 B@M- B . . 6C 6 2 7C 6 3 M+1-+M , . . 4C 1 A+ 1 -A . . SC 1 1 B + 1- 8 . . . 86 2 2 96 3 2 A6 4 2 86 4 3 M-A . . . C6 2 2 06 3 2 E6 4 2 F6 4 3 M-B . . . cc 3 3 DC 4 2 EC 5 2 FC s 3 M + 1 - 8, M- A I I I I I I Rs I I Rs I I Rs I I <l>O I I (!)0 I I (l) t.D I I I CD I I I I I I I IR I IR I I IS · I I IS · I I IS · I IR I IR I IR . . . . ·JO 30 7 1 A1t8-+A:8 . . . BA 2 2 9A 3 2 AA 4 2 BA 4 3 A+M-A . . . CA 2 2 DA 3 2 EA 4 2 FA 4 3 B+M- 8 ..... . 36 4 1 A - MIP. SP - 1 - SP ...... 37 4 1 B - MIP. SP - 1 - SP ..... . 32 3 1 SP+1-SP,M11>-A ... ... 33 3 1 sP+1-SP,M11>-B . .. .. · =14J.i rMl 69 6 2 79 6 3 49 1 1 .. · 59 1 1 · c I II III bl' .... ·· 66 6 2 76 6 3 46 1 1 =1~1111111i;l .. · B C Dl' DO · 56 1 1 I IR I IR I I I I I I I I I I I I I I I I I I (Note) Condition Code Register will be explained in Note of Table 13. (continued) 210 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 10 Accumulator, Memory Manipulation Instructions ()perettons Shift Left Arithmetic Double Shift Lah, Arithmetic SlllltRitht Arithmetic Shift Right lDllitol Double Shih Aight Logic1I Store Accumul1tor Store D®bl· Accumulltor Subtract DoubltSubt<ll<I SubtrllCt Ac1::umul·tor1 Subtract With C.rry Tran1ftr Accumuletors T"t z.,o°' Minu1 And Immediate OR Immediate EOR lmmedi1te Tut lmmediete Mnemonk: ASL ASLA ASLB ASLD ASR ASRA ASRB LSR LSRA LSRB LSRD STAA STAB STD SU8A SUBS SUBD SBA SICA sacs TAB TBA TST TSTA TSTB AIM OIM EIM TIM Addreuing Modes Condition Code Register IMMED. DIRECT INDEX EXTEND IMPLIED Boolean/ Arithmetic Operatton 5 4 32 10 OP - # OP - - # OP - # OP - # OP # H I NZv c .. 68 6 2 78 6 3 .. 48 1 1 MA l CJ4CI-II1JI]J+- 0 .. 58 1 1 I C b7 bO I I @I I I ®' I I6I Jt-o . 05 1 1 ~., ACC A': ~cc I · I I ~I .. 67 6 2 11 6 3 , :1~ .. 47 1 1 57 1 I I I II I ··I I 6 I 84 6 2 74 8 3 , ·· ·· 44 1 M: l o - ~ .. 54 1 1 , ., · · 04 1 o...i A'C "i1m I I+[] .. 11 IO c · · . 97 3 2 A7 4 2 87 4 3 A-M .. . D7 3 2 E7 4 2 F7 4 3 B-M . · . DO 4 2 ED 5 2 FD 6 3 A-M 8-+Mi-1 . · 80 2 2 90 3 2 AO 4 2 BO 4 3 . . co 2 2 DO 3 2 EO 4 2 FO 4 3 · . 83 3 3 93 4 2 A3 5 2 83 6 3 A-M-A 8 ·M -B A:B-M:M+1.-.tA: 8 · . 10 1 1 A-8-A · . 82 2 2 92 3 2 A2 4 2 82 4 3 A-M·C-A · . C2 2 2 02 3 2 E2 4 2 F2 4 3 s-M-c-a , . · . 16 1 A-B , , · . . 17 8- A · · 60 4 2 7D 4 3 M-00 . 4D 1 1 A ·00 , · .· SD 1 8 - 00 R I I R I I R I I R I ~I I IR I IR I IR I I I I II II I I I I I I II I I I I II II I I R I IR I I RR I I RR I I RR 71 8 3 81 7 3 M-IMM-M ·· I I R · 72 8 3 82 7 3 M+IMM-·M ·· I I R · 75 8 3 65 1 3 M''iliMM-M ·· t t R · 78 4 3 88 5 3 M·IMM ·· t t Re INotel Condition Code Register will be ""plained in Note of Table 13. ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 211 · Additional Instruction In addition to the HD6801 instruction set, the HD6303X prepares the following new instructions. AIM ....... (M)·(IMM) -> (M) Executes "AND" operation to immediate data and the memory contents and stores its result in the memory. OIM ....... (M) +(IMM) -> (M) Executes "OR" operation to immediate data and the memory contents and stores its result in the memory. EIM . . . . . . . (M) <!> (IMM) -> (M) Executes "EOR" operation to immediate data and the memory contents and stores its result in the memory. TIM . . . . . . . (M) · (IMM) Executes "AND" operation to immediate data and changes the relative flag of the condition code register. These area 3-byte instructions; the first byte is op code, the second immediate data and the third address modifier. XGDX ..... (ACCO) +-+(IX) Exchanges the contents of accumulator and the index register. SLP Goes to the sleep mode. Refer to "LOW POWER DIS· SIPATION MODE" for more details of the sleep mode. Table 11 Index Register, Stack Manipulation Instructions Pointer Operations Compere Index Reg Decrement Index Reg Decrement Steck Pntr Increment lnde· Reg Increment Steck Pntr Load Index Reg Load Stack Pntr Store Index Reg Store Steck Pntr lnrtex Reg ..... Stack Pntr St·ek Pntr-+ Index Reg Add Push Data Pull Data Exchange Mnemonie CPX DEX DES INX INS LOX LOS STX STS TXS TSX ABX PSHX PULX XGDX -IMMED. OP # sc 3 3 Addre11ing Modes - - - DIRECT INDEX EXTEND DP # OP # OP # 9C 4 2 AC 5 2 SC 5 3 -IMPLIED DP # 09 1 1 Boote1n/ Arithmetic ()per1tion X-M:M+1 x-1- x 34 1 1 SP-1-SP 08 1 1 x + 1- x 31 1 1 51'+1-SP CE 3 3 DE 4 2 EE 5 2 FE 5 3 · SE 3 3 9E 2 AE 5 2 SE 5 3 OF 4 2 EF 5 2 FF 5 3 M- XH, (M+ 11- XL_ M- sPH. (M+11-sPL XH .... M, XL .... (M + 1) 9F 4 2 AF 5 2 BF 5 3 SPH - M, SPL _. CM+ 1l 35 1 1 X-1-SP 30 1 1 sP+1-x 3A 1 1 a +x- x 3C 5 1 XL -_M.,. SP- 1 - SP xH- M.,,sP-1-sP 38 4 1 sP+ 1-SP,MIP- XH SP+ 1-SP,MIP- XL 18 2 1 ACCD··IX Condition Code A. .i l t l f 54 3 2 10 H ............·· I N · : .....· ·· rm· · a> .....··00..... z . I I I · I I ....II . v : ..·· R R .....RR c . . I · . · . . . . . . . · · ·· ··· (Note) Condition Code Register will be explained in Note of Table 13. 212 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 12 Jump, Branch Instructions Oper·tions Mnemonic Br·nch Alweys Branch Newr Branch If C.ry Cl·r Branch If C.ry $91 Branch If · Zero Br1nch If ;;;.. Zero Branch If > Zero Br1nch If Hightt Branch If < Zero 8r1nch 1f Lower Or Somo Br1nch If < Zero Br1nch If Minus lr1nch If Not Equ1I Zero lronoh If Ovorltow Cltlr Brooch If Overflow Sot Brooch II Pl·· lr1nch To Subroutine Jump J·mP To S.broutlno NoOporotton A.wrn From lnttrruPt F11turn From llubroutlno Software lnttr"IPt Witt fOr Interrupt· ::!!:~ BRA BRN BCC BCS BEQ BGE BGT BHI BLE BLS BLT BMI BNE BVC IVS BPL 8SR JMP JSR NOP llTI RTS SWI WAI -su· Addressing MOdes - RELATIVE OIRECT DP - # OP # 20 3 2 21 3 2 24 3 2 25 3 2 27 3 2 2C 3 2 2E 3 2 22 3 2 2F 3 2 INDEX OP - # - EXTEND OP # IMPLIED OP - # 23 3 2 2D 3 2 28 3 2 21 3 2 21 3 2 29 3 2 2A 3 2 80 5 2 IE 3 2 7E 3 3 , 90 s 2 AO & 2 BD 8 3 01 1 38 10 1 39 5 1 3F 12 1 3E I 1 IA 4 [I Branch Test None None C·O C·1 z. 1 N@V·O Z + IN@VI · 0 C+Z·O Z +IN@ VI· 1 C+Z·1 N@V· 1 N·1 Z·O V·O v · 1 N·O Adv.nce1 Pfog, Cntr. Only CNotel ·WAI puts R/W high; Address Bus I08I to FFFF: Data Bus go· to the thr111tate. Condition Code Register will be explained In Note of Table 13. Condition Codi Register 5 4 3 2 10 .............. ..H I N z v c · · . ... · · .. ... · .. . · · · .... .. · · ·· · · . . · · · · ..· · · · · · · · · · . . · · · · .· · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·· ·· ·· ·· ·· ·· · · · · · · :J · · · · · · · s · · Ill. · · · · · · · · · · · · · HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 213 Table 13 Condition Code Register Manipulation Instructions ()ptretions ctnrc.rrv Clnr Interrupt Me1k CS..rOverflow Set C.ry Set Interrupt Mlsk SetOwrflow Accumuln>r A - CCR CCR -+ Accumulator A Mnemonic CLC CLI CLV SEC SEI SEV TAP TPA JAdd .... ing~ - IMPLIED OP # oc 1 1 OE 1 1 OA 1 1 OD 1 1 OF 1 1 OB 1 1 06 1 1 07 1 1 Boolean Operation o-c 0-1 o-v 1-c 1-1 1-v A- CCR CCR-A Condition Code Register ......H5 . - . · I . . R s . . - @ .......N 3 .......z 2 . . 1 v . . R . s - 0 . . c R . . s . - LEGEND OP Operation Code (Hexadecimal! Number of MCU Cycles Msp Contents of memory location pointed to by Stack Pointer # Number of Program Bytes + Arithmetic Plus Arithmetic Minus · Boolean AND + Boolean Inclusive OR e Boolean EKclusive OR iiii Complement of M Transfer into 0 Bit= Zero 00 Byte = Zero CONDITION CODE SYMBOLS H Half-carry from bit 3 to bit 4 I Interrupt mask N Negative (sign bitl Z Zero (bytel V Overflow, 2's complement C Carry/Borrow from/to bit 7 R Reset Always S Set Always t Set if true after test or clear · Not Affected (Note) Condition Code Register Notes: (Bit set if test is true and cleared otherwise) <1J IBit VI Test: Result= 10000000? '21 (Bit Cl Test: Result~ 000000007 0l (Bit Cl Test: BCD Character of high-order byte greater than 10? (Not cleared if previously setl (4) (Bit V) ~ IBitVI Test: Operand= 10000000 prior to execution? Test: Operand= 01111111 prior to execution? s' !Bit VI Test: Set equal to NS. C == 1 after the execution of instructions Ji (Bit NI Test: Result less than zero? (Bit 15=1) \81 (All Bitl Load Condition Code Register from Stack. (9; (Bit 11 Set when interrupt occurs. If previously set. a Non-Maskable Interrupt is required to exit the wait state. (!OJ (All Bitl Set according to the contents of Accumulator A. @ IBitCI Result of Multiplication Bit 7=1? (ACCBI Table 14 OP-Code Map OP CODE ACC A ACC B ~ ACCA or SP IND R IMMj DIR j IND j EXT ACCB or X J J j IMM DIR IND EXT ~ 0000 0 0 0001 1 0010 2 0000 0 . / SBA BRA 0001 1 NOP CBA BRN 0010 2 ~ . / BHI 0011 5 . / ~ BLS 0011 3 TSX INS PULA PULB 0100 0101 0110 0111 --4 5 6 7 NEG AIM - - _l OIM C]O_ M J J J 1000 1001 10!0 1011 s]9]AjB l J J 1100 1101 1110 1111 c] D j E j F SUB 0 CMP I SBC 2 SUBD ADDO 3 0100 4 LSRD . / BCC DES LSR 0101 5 ASLD . / ecs TXS EIM 0110 6 TAP TAB BNE PSHA - - - R_OlR AND 4 BIT 5 LOA 6 0111 7 TPA TBA BEQ PSHB 1000 8 INX XGDX eve PULX ASR ~ STA ~ STA 7 ASL EOR 8 1001 9 DEX 1010 A CLV 1011 B SEV 1100 c CLC DAA BVS SLP BPL ABA BMI . / BGE ---RTS ROL ABX DEC RTI l PSHX INC TIM ADC 9 ORA A ADD B CPX LOO c 1101 D SEC . / BLT MUL TST BSR] JSR ./l STD D 1110 E CLI . / BGT WAI k:::::::::L:::::::l JMP LOS LOX E 1111 F SEI . / BLE SWI 0 1 2 3 4 I I l 1 I CLR 5 s ./l 7 8l 9 STS A ./j STX B c l D Ej F F 'UNDEFINED OP CODE 1ZJ ·Only each instructions of AIM, OIM, EIM, TIM 214 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · CPU OPERATION · CPU Instruction Flow When operating, the CPU fetches an instruction from a memory and executes the required function. This sequence starts with RES cancel and repeats itself limitlessly if not affected by a special instruction or a control signal. SWI, RTI, WAI and SLP instructions change this operation, while NMI, IRQi. IRQ2 , IRQ3 , HALT and STBY control it. Fig. 24 gives the CPU mode transition and Fig. 25 the CPU system flow chart. Table 15 shows CPU operating states and port states. · Operation at Each Instruction Cyde Table 16 shows the operation at each instruction cycle. By the pipeline control of the HD6303X, MULT, PUL, DAA and XGDX instructions etc. prefetch the next instruction. So attention is necessary to the counting of the instruction cycles because it is different from the usual one ······ op code fetch to the next instruction op code. Table 15 CPU Operation State and Port State Port Ao -A, Port 2 Do -D, A1 -A15 Port 5 Port 6 Control Signal Reset H T T H T . T STBY*** T T T T T T T HALT T Keep T T T ..Keep Sleep H Keep T H T .Keep H; High, L; Low, T; High Impedance * AO, WA, AiW, LIA = H, BA = L ·· AD, WA, A/W = T, LIA, BA= H ** · E pin goes to high impedance state. Figure 24 CPU Operation Mode Transition @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA g5131 · (408) 435-8300 215 ~ "' Ol I ~ :!: ~ 3 r~;· r"c':. 0""'' 0 ac0c l@· ;-~~~ :I (/) 0 ~ :I '0 - "'_CD () ~ ""~ ' ' ,. 0 ~... ""a,'' ~ 0 :I: 0 Ow > PC-1 0wx PC·! STACK PC.IX ACCA ACCB CCR (Note) 1. The program sequence will come to the AES start from any place of the flow during RES. When STBY=O, the sequence will go into the standby mode regardless of the CPU condition. 2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more details of interrupts. Figure 25 HD6303X System Flow Chart Address Mode llo Instructions IMMEDIATE ADC AND ADD BIT CMP EOR 2 LOA ORA SBC SUB ADDO CPX LOO LOS 3 LOX SUBD DIRECT ADC ADD AND BIT CMP EOR 3 LOA ORA SBC SUB STA 3 ADDO CPX LOO LOS LOX SUBO 4 STD STS STX 4 JSR 5 TIM 4 AIM EIM DIM 6 Table 16 Cycle-by-Cycle Operation Address Bus R/W RD 1 Op Coda Address+ 1 2 Op Code Address+ 2 1 0 1 1 0 1 1 Op Code Address+ 1 2 Op Code Address+2 3 Op Code Address+3 1 Op Code Address+ 1 2 Address of Operand 3 Op Code Address+ 2 1 Op Code Address+ 1 2 Destination Address 3 Op Code Address+ 2 1 Op Code Address+ 1 2 Address of Operand 3 Address of Operand+ 1 4 Op Code Address+ 2 1 Op Code Address+ 1 2 Destination Address 3 Destination Address+ 1 4 Op Code Address+ 2 1 Op Code Address+ 1 2 FFFF 3 Stack Pointer 4 Stack Pointer - 1 5 Jump Address 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Address of Operand 4 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Addre'lls + 2 3 Address of Operand 4 FFFF 5 Address of Operand 6 Op Code Address+ 3 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 1 0 1 Data Bui 1 Operand Data 0 Next Op Code 1 Operand Data (MSBI 1 Operand Data lLSBI 0 Next Op Code 1 Address of Operand lLSBI 1 Operand Data 0 Next Op Coda 1 Destination Address 1 Accumulator Data 0 Next Op Code 1 Address of Operand lLSBI 1 Operand Data lMSBI 1 Operand Data lLSBI 0 Next Op Coda 1 Destination Address (LSB) 1 Register Data (MSBI 1 Register Data lLSBI 0 Nut Op Code 1 Jump Address lLSBI 1 Restart Address (LSBI 1 Return Address lLSBI 1 Return Address (MSBI 0 First Subroutine Op Code 1 Immediate Data 1 Address of Operand (LSBI 1 Operand Data 0 Nut Op Code 1 Immediate Data 1 Address of Operand (LSBI 1 Operand Data 1 Restart Address (LSBI 1 New Operand Data 0 Next Op Code (Continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 217 Address Mode 8i Instructions INDEXED JMP ADC AND CMP LOA SBC TST STA ADD BIT EOR ORA SUB ADDO CPX LOS SUBD LDD LOX STD STS STX JSR ASL COM INC NEG ROR ASR DEC LSR ROL TIM CLR AIM EIM OIM Cycles Cy~le 1 3 2 3 1 2 4 3 4 1 4 2 3 4 1 2 5 3 4 5 1 2 5 3 4 5 1 2 5 3 4 5 1 2 6 3 4 5 6 1 2 5 3 4 5 1 2 5 3 4 5 1 2 3 7 4 5 6 7 Address Bus Op Code Address+ 1 FFFF Jump Address Op Code Address+l FFFF IX+Offset Op Code Address+ 2 Op Code Address+ 1 FFFF IX+Offset Op Code Address+ 2 Op Code Address+ 1 FFFF IX+Ollset IX+Offset+1 Op Code Address+ 2 Op Code Address+ 1 FFFF IX+Offset IX+Offset+l Op Code Address+ 2 Op Code Address+ 1 FFFF Stack Pointer Stack Pointer - 1 IX+Offset Op Code Address+ 1 FFFF IX+Offset FFFF IX+Offset Op Code Address+ 2 Op Code Add.ress + 1 Op Code Address+ 2 FFFF IX+Offset Op Code Address+3 Op Code Address+ 1 FFFF IX+Offset IX+Offset Op Code Address+ 2 Op Code Address+ 1 Op Code Address+ 2 FFFF IX+Offset FFFF IX+Offset Op Code Address+3 R/W RD Data Bus 1 0 1 1 Offset 1 1 1 1 Restart Address (LSB) 1 0 1 0 First Op Code of Jump Routine 1 0 1 1 Offset 1 1 1 1 Restart Address (LSBI 1 0 1 1 Operand Data 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restart Address (LSB) 0 1 0 1 Accumulator Data 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restart Address (LSB) 1 0 1 1 Operand Data (MSB) 1 0 1 1 Operand Data (LSB) 1 0 1 0 Next Op Code 1 -~- 1 1 Offset 1 1 1 Restart Address (LSB) 0 1 0 1 Register Data (MSB) 0 1 0 1 Register Data (LSB) 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restart Address (LSB) 0 1 0 1 Return Address (LSBI 0 1 0 1 Return Address (MSB) 1 0 1 0 First Subroutine Op Code 1 0 1 1 Offset 1 1 1 1 Restart Address (LSBI 1 0 1 1 Operand Data 1 1 1 1 Restart Address ILSBI 0 1 0 1 New Operand Data 1 0 1 0 Next Op Code 1 0 1 1 Immediate Data 1 0 1 1 Offset 1 1 1 1 Restart Address (LSBI 1 0 1 1 Operand Data 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restart Address ILSB) 1 0 1 1 Operand Data 0 1 0 1 00 1 0 1 0 Next Op Code 1 0 1 1 Immediate Data 1 0 1 1 Offset 1 1 1 1 Restart Address (LSB) 1 0 1 1 Operand Data 1 1 1 1 Restart Address (LSB) 0 1 0 1 New Operar)d'"Data 1 0 1 0 Next Op Code (Continued) 218 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Cycles C~le Addre11 8"1 EXTEND JMP 3 ADC ADD TST ANO BIT CMP EOR 4 LOA ORA SBC SUB STA 4 ADDO CPX LOO LOS LOX 5 SUBO STD STS STX 5 JSR 6 ASL ASR COM DEC INC LSR NEG ROL 6 ROR CLR 5 1 Op Code Address+ 1 2 Op Code Addre11 + 2 3 Jump Addre11 1 Op1'odeAddress+ 1 2 Op Code Addre11 + 2 3 Address of Operand 4 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Addi ess + 2 3 Destination Address 4 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Address of Operand 4 Address of Operand+ 1 5 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Destination Address 4 Destination Address+ 1 5 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+2 3 FFFF 4 Stack Pointer 5 Stack Pointer - 1 6 Jump Addre11 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Address of Operand 4 FFFF 5 Address of Operand 6 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Address of Operand 4 Address of Operand 5 Op Code Address+ 3 Data Bua ! 1 1 1 1 1 0 1 ! 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 ! 1 1 1 1 1 0 1 1 0 1 1 0 1 t 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 1 0 1 1 0 T 1 0 1 1 0 1 0 1 0 1 0 1 1 Jump Address (M5B) 1 Jump Address ILSBI 0 Next Op Code 1 Address of Operand iMSB) 1 Address of Operand ILSBI 1 Operand Deta 0 Next Op Code 1 Destination Address iMSBI 1 Destination Address (LSB) 1 Accumulator Data 0 Next Op Code 1 Address of Operand iMS!li 1 Address of Operand (LSB) 1 Operand Data iMSBI 1 Operand Data ILSBI 0 Next Op Code 1 Destination Address iMSB) 1 Destination Address (LSB) 1 Register Data IMSB) 1 Register Data (LSBl 0 Next Op Code 1 Jump Address (MSB) 1 Jump Address (LSBI 1 Restart Address (LSB) 1 Return Address ILSB) 1 Return Address (MSB) 0 First Subroutine Op Code 1 Address of Operand (MS-Bl 1 Address of Operand (LSBI 1 Operand Data 1 Restart Address ILSB) 1 New Operand Data 0 Next Op Code 1 Address of Operand IM~Slll 1 Address of Operand (LSB) 1 Operand Data 1 00 0 Next Op Code (Continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 219 Address Mode & Cycles Cv;le Instructions Address Bus IMPLIED ABA ABX ASL ASLD ASA CBA CLC Cll CLR CLV COM DEC DES DEX INC INS INX LSR LSRD R(l)L ROR SBA NOP SEC SEI SEV TAB TAP TBA TPA TST TSX TXS DAA XGDX PULA PULB PSHA PSHB PULX PSHX RTS MUL 1 Op Code Address+ 1 1 2 1 Op Code Address+ 1 2 FFFF 1 Op Code Address+ 1 3 2 FFFF 3 Stack Pointer+ 1 1 Op Code Address+ 1 4 2 FFFF 3 Stack Pointer 4 Op Code Address+ 1 1 OpCode Address+ 1 4 2 FFFF 3 Stack Pointer+ 1 4 Stack Pointer+ 2 1 Op Code Address+ t 2 FFFF 5 3 Stack Pointer 4 Stack Pointer - 1 5 Op Code Address+ 1 t Op Code Address+ 1 2 FFFF 5 3 Stack Pointer+ 1 4 Stack Pointer+ 2 5 Return Address t Op Code Address+ 1 2 FFFF 3 FFFF 7 4 FFFF 5 FFFF 6 FFFF 7 FFFF R/W Data Bus 1 0 1 0 Next Op Code 1 0 1 0 Next Op Code 1 t t 1 Restart Address {LSB) 1 0 1 0 Next Op Code 1 1 1 1 Restart Address (LSB) 1 0 1 1 Data from Stack 1 0 1 1 Next Op Code 1 1 1 1 Restart Address (LSB) 0 1 0 1 Accumulator Data 1 0 1 0 Next Op Code 1 0 1 0 Next Op Code 1 1 1 1 Restart Address (LSB) 1 0 1 1 Data from Stack (MSB) 1 0 1 t Data from Stack (LSB) 1 0 1 1 Next Op Code 1 t 1 1 Restart Address (LSB) 0 t 0 t Index Register (LSB) 0 t 0 t Index Register (MSB) 1 0 t 0 Next Op Code 1 0 1 1 Next Op Code 1 1 1 t Restart Address (lSB) 1 0 1 1 Return Address (MSB) 1 0 1 t Return Address (LSB) 1 0 1 0 First Op Code of Return Routine 1 0 1 0 Next Op Code t t 1 1 Restart Address (LSBI 1 1 1 1 Restart Address (LSB) 1 1 1 t Restart Address (LSB) 1 t 1 t Restart Address (LSB) t 1 t 1 Restart Address (LSBI 1 1 1 1 Restart Address (LSB) (Continued) 220 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 IMPLIED WAI RTI SWI SLP RELATIVE ace BCS BEQ BGE BGT BHI BLE BLS BLT BMT BNE BPL BRA BRN eve avs BSR Cycl11 cv:le Addreu Bus 0111 Bus 1 Dp Coda Addre11+1 2 FFFF 3 Steck Pointer 4 Sllr.k Pointer-1 9 5 S11ck Pointer-2 8 Steck Pointer- 3 1 Steck Poin11r-4 8 Stack Poinllr- 5 9 Steck Pointer-8 1 Op Code Addr... +1 2 FFFF 3 Stack Pointer+ 1 4 Stack Pointer+ 2 10 5 Steck Pointer+3 8 Steck Pointer+4 1 Sllck Pointer+ 5 8 Steck Pointer+ 6 9 Sllck Pointer+ 7 10 Return Address 1 Op Code Address+! 2 FFFF 3 Stack Pointer 4 Stack Pointer-1 5 Steck Pointer -2 12 8 Steck Pointer -3 1 Steck Pointer-4 8 Stack Pointer - 5 9 Sllck Pointer-8 10 Vector Address FFFA 11 Vector Address FFFB 12 Address ol SWI Routine 1 Op Code Address+ 1 2 FFFF 1 4 Sleep I 3 FFFF 4 Op Code Address+ 1 1 0 1 1 NextOpCode 1 1 1 1 Restart Addr... (LSBI 0 1 0 1 Return Addre11 (LSBI 0 1 0 1 Return Addr... (MSBI 0 1 0 1 Index Regisllr (LSBI 0 1 0 1 Index Regiller (MSBI 0 1 0 1 Accumulator A 0 1 0 1 Accumulator B 0 1 0 1 Conditional Code Register 1 0 1 1 Next Op Code 1 1 1 1 Resllrt Addr... (LSBI 1 0 1 1 Conditional Code Register 1 0 1 1 Accumulator B 1 0 1 1 Accumulator A 1 0 1 1 Index Regiller (MSBI 1 0 1 1 Index Register (LSBI 1 0 1 1 Return Addr... (MSBI 1 0 1 1 Return Addr... (LSBI 1 0 1 0 First Op Code of Return Routine 1 0 1 1 Next Op Code 1 1 1 1 Resllrt Address (LSBI 0 1 0 1 Return Address (LSBI 0 1 0 1 Return Address (MSBI 0 1 0 1 Index Register (LSBI 0 1 0 1 Index Register (MSBI 0 1 0 1 Accumulator A 0 1 0 1 Accumulator B 0 1 0 1 Conditional Code Register 1 0 1 1 AddrHS of SWI Routine (MSBI 1 0 1 1 Address of SWI Routine ILSBI 1 0 1 0 First Op Code of SWI Routine 1 0 1 1 Next Op Code 1 1 1 1 Restart Address (LSBI IIII l 1 1 1 1 Restart Address ILSBI 1 0 1 0 Next Op Code 1 Op Code Address+ 1 1 0 1 1 Branch Offset 3 2 FFFF 1 1 1 1 Restart Addross ILSBI 3 J Branch Address· .....Test= "1" I Op Code Address+1···Test="O" 1 0 1 First Op Code of Branch Routine 0 Next Op Code 1 Op Code Address+! 2 FFFF 5 3 Stack Pointer 4 Stack Pointer- 1 5 Branch Address 1 0 1 1 Offset 1 1 1 1 Restart Address (LSB) 0 1 0 1 Return Address ILSBI 0 1 0 1 Return Address IMSBI 1 0 1 0 First Op Code of Subroutine $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 221 · PRECAUTION TO THE BOARD DESIGN. OF OSCILLA- TION CIRCUIT As shown in Fig. 26, there is a case that the cross talk dis- turbs the· normal oscillation if signal lines are put near the oscillation circuit. When designing a board, pay attention to this. Crystal and CL. must be put as near the HD6303X as possible. · j ! 11 en en ,J;iCL ; 1-:'l~--,H XTAL r-20mm max-j _/'Avoid signal lines ~ in this area. ~ E E ~ _J_ E HD6303X Do not use this kind of 1;>rint board design. Figure 26 Precaution to the boad design of oscillation circuit · RECEIVE MARGIN OF THE SCI Receive margin of the SCI contained in the HD6303X is shown in Table 17. Note: SCI= Serial .Communication Interface HD6303X (OP-645) (Top View) Figure 27 Example of Oscillation Circuits in Board Design HD6303X Table 17 Bit distortion tolerance (t-to) /to ±43.7% Character distortion tolerance (T-Tol fro ±4.37% ldNI waveform RHI Waveform START I. 2 3 4 5 6 7 8 STOP 222 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · POWER-ON RESET _ At power-on it is necessary to hold RES "low" to reset the internal state of the device and to provide sufficient time for the oscillator to stabilize. Pay attention to the following. ·Just after power-on, the MPU doesn't enter reset state until the oscillation starts. This is because the reset signal is input internally, with the clocked synchronization as shown below. RES pin 01-----10 Q t - - - - - - - - · Internal reset signal Inside the LSI Fig. 28 Reset Circuit Thus, just after power-on the LSI state (I/O port, mode condition etc.) is unstable until the oscillation starts. If it is necessary to inform the LSI state to the external devices during this period, it neeil~ to be done by the external circuits. · RESET SIGNAL AND MEMORY READY FUNCTION The reset signal is strobed to CPU synchronized with internal clock. Since internal clock is held to "High" level during = memory-ready-state (MR "Low"), reset sygnal is not strobed to CPU. Please MR input (P52 ) should be "High" level during reset- state . · HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 223 HD6303Y ,HD63A03Y, HD63B03Y CMOS MPU (Micro Processing Unit) The HD6303Y is a CMOS 8-bit micro processing unit which contains a CPU compatible with the HD630IVI, 256 bytes of RAM, 24 parallel 1/0 Pins, Serial Communication Interface (SCI) and two timers. · FEATURES · Instruction Set Compatible with the HD6301 V1 · 256 Bytes of RAM · 24 Parallel 1/0 Pins · Parallel Handshake Interface (Port 6) · Darlington Transistor Drive (Port 2, 6) · 16-bit Programmable Timer Input Capture Register x 1 Free Running Counter x 1 Output Compare Registers x 2 · 8-Bit Reloadable Timer External Event Counter Square Wave Generation · Serial Communication Interface (SCI) Asynchronous Mode (8 Transmit Formats, Hardware Parity) Clocked Synchronous Mode · Three Kinds of Memory Ready · Halt · Error Detection (Address Error, Op-code Error) · Interrupt - 3 External, 7 Internal · Maximum 65k Bytes Address Space · Low Power Dissipation Mode Sleep Standby (Hardware Set, Software Set) · Wide Operating Range Vee = 3 to 5.5 (f = 0.1 to 0.5 MHz) Vee= 5V ± 10% (f = 0.1 - 3 MHz) · Minimum Instruction Cycle Time _: HD6303Y ......... 1µs (f = 1 MHz) - HD63A03Y ....... 0.67µs (f = 1.5 MHz) - HD63803Y ....... 0.5µs (f=2.0 MHz) - HD63C03Y . . . . . . . 0.33µs (f = 3.0 MHz) · TYPE OF PRODUCTS Type No. HD6303Y HD63A03Y HD63B03Y HD63C03Y* * Preliminary Bus Timing 1 MHz 1.5 MHz 2MHz 3MHz HD6303YP, HD63A03YP, HD63B03YP, HD63C03YP* (DP-645) HD6303YF, HD63A03YF, HD63803YF, HD63C03YF (FP-64) HD6303YCP, HD63A03YCP, HD63B03YCP, HD63C03YCP (CP-68) 224 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I . PIN ARRANGEMENT · HD6303YP, HD63A03YP, HD63803YP, HD63C03YP · HD6303YF, HD63A03YF, HD63803YF, HD63C03YF Pu 1 P1., 1 ...Pa 1 , PH 1 P.,, 1 p.,J 1 p,, P.,. 21 P.,., 22 p.,, 2 · A, A, 2 Vss PH 4 P.o 2s 4t A 1 A, P11 2s ...Pu 7 Pu B 37 A,, A,, Pu J A 14 PH 31 3 A" P., -"~-----.r'-3 Vee (Top View) · HD6303YCP, HD63A03YCP, HD63803YCP, HD63C03YCP (Top View) @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 225 B BLOCK DIAGRAM VccVssVss- P2o(Tin J----- P21(Tout1)----- a: P22(SCLK) - - - . . + . i N 0 0 P23( Rx P2.(Tx )----.J----1-+-~ la-: 0 P2s(Touh)--~~ CL N la-: 0 P2&( Tout3) ---1-+-1-+-HM CL P21(TCLK) --M-1~1-W!..___..____, ..J ..J ~x.o.,wx~ !!: CPU Pso(i°RIT1 Ps1(fA02 Ps2(MR ) .-----i Ps3( HACTJ .----.t Ps·(IS J -----..i in la-: 0 Pss(i:rn" ) -----..i CL a: 0 0 in la-: 0 CL Ps& Ps1 P&o P&1 a: P&2 <D c0 Ps3 p64 Pss I- ~ CL <D la-: 0 CL P&& Ps1 RAM 256Bytes 226 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee -0.3-+7.0 v Input Voltage Vin -0.3-Vce+0.3 v Operating Temperature Topr 0-+10 ·c Storage Temperature T,1g -55-+150 ·c (NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field. But be careful not to apply overvoltage more than maximum ratings to theae high input impedance protection circuits. To assure the normal operation, we recommend Vin, Vout: V58 ~ (Vin orVout) ~Vee· · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee= 6.0V±10%. Vss = ov. T· = o-+1o·c. unl···otherwlsenoted.) Item Jm:,STBV Input "High" Voltage EXTAL Other Inputs Input "Low" Voltage Input leakage Current Three State Leakage Current All Inputs NM!, m. STBV. MP0,MP1 ~-AAk Do-D7, RD, · R , Ports 2, 5,6 Output "High" Voltage All Outputs Output "Low" Voltage Darlington Driva Current Input Capacitance Standby Current All Outputs Ports 2, 6 AH Inputs Non Operation Current Dissipation· RAM Standby Voltage Symbol VIH Vil 11.. 1 l·rsil VoH Vol -IOH c .. lsra lsLP Ice VRAM Test Condition v.. = 0.5-Vcc-0.5V Vin= 0.5-Vec-0.5V IOH = - 200µ.A IOH= -10µ.A loL = 1.6mA Vout= 1.5V Vin= OV, f = 1MHz, Ta= 25°C Sleeping (f= 1MHz··) Sleeping (f= 1.5MHz..) Sleeping (f= 2MHz..I Operating (f= 1MHz"") Operating (f= 1.5MHz..) Operating (f= 2MHz··) min typ max Unit Vcc_-0.5 - VeeX0.7 2.0 - Vee +0.3 v -0.3 - 0.8 v - - 1.0 µ.A - - 1.0 µ.A 2.4 - Vec-0.7 - -- -v -v 0.4 v 1.0 - 10.0 mA - - 12.5 pf - 3.0 15.0 µ.A - 1.5 3.0 mA - 2.3 4.5 mA - 3.0 6.0 mA - 7.0 10.0 mA - 10.5 15.0 mA - 14.0 20.0 mA 2.0 -- v v., min= Vee - 1.0V, V._ max= O.BV (All outputtorminals are at no load.I Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. values about Current Dissipations at X MHz operation are decided according to the following formula: typ. value (f = )( MHzl = typ. value (f = 1MHzl x X ma·, value (f = )( MHz) = max. value If = 1MHz) x X (both the sleeping and operating) @HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 227 ov. · AC CHARACTERISTICS IVcc = 15.0V±10%. Vas= T. = o-+1o·c. unlHsotherwlsenoted.) BUS TIMING Item Symbol Cycle Time Enable Rise Time Enable Fall Time Enable Pulse Width "High" Level· Enable Pulse Width "Low" Level· Address, R/W Delay Time· Data Delay Time jWrite Data Set-up Time }Read Address, R/W Hold Time· 1Write· J Data Hold Time Read RD, WR Pulse Width· "Im, WR Delay Time 1rn, WR Hold Time DR Delay Time DR Hold Time MR Set-up Time· MR Hold Time· E Clock Pulse Width at MR tcyc 'er te1 PWeH PWEL tAD to ow tosR tAH 'Hw tl!A PWRW '-a tiiRW lo LR tHLR tsMR tiiMR PWEMA Test Condition Fig. 1 Fig. 2 HD6303Y HD63A03Y HD63803Y Unit min typ max min typ max min typ max 1 - - 10 0.666 10 0.5 - 10 µ.s - - 25 - - 25 - - 25 ns - - - 25 - - 25 - 25 ns - 450 - 300 - - 220 - - ns - - - - 450 - 300 - 220 ns - - - - 250 - 190 - 160 ns - - - 200 - - 160 - 120 ns - - - 80 - 70 - - 60 ns - 80 - - 50 - - 40 - ns - 70 - - 50 - 40 - - ns 0 - - 0 - - 0 - - ns - - - 450 - - 300 - 220 ns - - - 40 - - 40 - 40 ns - - 20 - - - 20 - 20 ns - - - - 200 - 160 - 120 ns - 10 - - 10 - - 10 - ns - - 400 - - 280 - 230 - ns - - 100 - - 70 - - 50 ns - - 9 - - 9 - - 9 µ.s Processor Control Set-up Time Processor Control Rise Time Processor Control Fall Time BA Delay Time Oscillator Stabilization Time Reset Pulse Width t,.cs tpc, t,.cr taA tRc PWnsT Fig.3, 13, 14 200 - - 200 - - - 200 - ns - - - 100 - 100 - - 100 ns Fig.2,3 - - - 100 - - 100 - 100 ns Fig. 3 - - - - 250 - 190 - 160 ns - - - Fig.14 20 - - 20 - 20 ms 3 - - 3 - - 3 - - tcyc ·P- These timings change in approximate proportion to t..,.- The figures in this characteristics represent those when l,,.,c is minimum (= in the highest oparation). PERIPHERAL PORT TIMING Item Peripheral Data Set Up Time Peripheral Data Hold Time Delay Time (from Enable Fall Edge to Peripheral Output) Input Strobe Pulse Width Input Data Hold Time Input Data Set-Up Time Output Strobe Delay Time Port 2, 5, 6 Port 2, 5, 8 Port 2, 5, 6 Port6 Port6 Symbol trosu t,gH Test HD6303Y HD63A03Y HD63803Y Condition min typ max min typ max min typ Unit max - 200 - 200 - - 200 - - no Fig. 5 - - - - 200 - 200 - 200 no t,.w., - - - - Fig.8 - 300 - 300 300 no ~ 200 - - 200 - - 200 - - ns "lo"s - - - - - Fig. 10 150 150 - 150 ns - - 100 - 100 - 100 - - ns loso1 - - Fig. 11 - - 200 - 200 - 200 ns loso2 228 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 TIMER, SCI TIMING Item Symbol Timer 1 Input Pulse Width Delay Time (Enable Positive Transition to Timer Output) SCI Input lAsync. Mode J Clock Cycle Clock Sync. SCI Transmit Data Delay Time (Clock Sync. Model SCI Receive Data Set-up Time (Clock Sync. Model SCI Receive Data Hold Time (Clock Sync. Model SCI Input Clock Pulse Width Timer 2 Input Clock Cycle Timer 2 Input Clock Pulse Width Timer 1·2, SCI Input Clock Rise Time Timer 1·2, SCI Input Clock Fall Time tpwT tTOo tscyc tTXD tsRX tHRX t,wscK ~ tPWTCK tcKr tcKI Test Condition Fig.9 Fig. 7, 8 Fig. 9 Fig.4 Fig.4 Fig. 9 HD6303Y HD63A03Y HD63B03Y Unit min typ max min typ max min typ max - - - - - 2.0 - 2.0 2.0 t!!r£_ - - 400 - - 400 - - 400 ns - 1.0 - 2.0 - - 1.0 - 2.0 - - 1.0 - 2.0 - -~ - ~c - - 220 - - 220 - - 220 ns - - 260 - 260 - - - 260 ns - 100 - 0.4 - 2.0 - 200 - 100 - 0.6 0.4 - 2.0 - 200 - - 100 - - 0.6 0.4 - - 2.0 - 200 - - ns 0.6 tsg_c - ~c - ns - - - 100 - - - 100 100 ns - - - 100 - - - 100 100 ns @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 229 2.4V E PWn o.av .... 2.4V o.av PWEH ti;, Figure 1 Sus Tming i-------1PW·11·------1 2.4V \ E \ \ \.---- o.av MR 2.0V o.av t.c1 Figure 2 Mllfl'!orv R'8dy and E Clock Timing 230 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction Execution Cycle E BA Synchronous Clock Figure 3 HALT and BA Timing Transmit Data Receive Data "2.0V is high level when clock input. 2.4V is high level when clock output. Figure 4 SCI Clocked Synchronous Timing fMPU Read E Figure 5 Port Data Set-up and Hold Times (MPU Read) rMPUWrite E a.av I'----' tPWO P20-P21· Pso-P.,,------..... ~---- P.110-Pe1 (outputel------"' ~..2,o.·.,4,.v.V .D.a_ta_Valid Figure 6 Port Data Delay Times (MPU Write) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 231 E r - - - Timer 1 ----.,.-.....,~~"-· FRC P2i, P 2 s - - - - - - - - - - . . i.-,...,~-- Outputs - - - - - - - - - ' "'"""'"""'--- Figure 7 Timer 1 Output Timing ~hr j::U---: ·· tcKf * * ·rimer 2 ; ttcyc SCI ; tScyc ..Timer 1 ; tPWT Timer 2 ; tPWTCK SCI ;tPWSCK Figure 9 Timer 1 ·2. SCI Input Clock Timing E T2CNT N $00 P2s Output (TCONR=N) Figure 8 Timer 2 Output Timing tPWIS PORTS Data (Input) Figure 10 Port S Input Latch Timing MPU access of PORTS E Figure 11 Output Strobe Timing Interrupt Tnt = C = 90pf for D0 -D7, A,,-A15, E 30pf for Port 2, Port 5, Port 8, Mi, WR", R/W, BA.Illf R = 12k0 Figure 12 Bus Timing Test Loads (TTL Load) Internal Addrnslus~. . . ., . . _ . . _ _ , , . . . . _ . . . . . , . , . . __ __ , , . _ . . . . J ' - - J ' -. . . ....J'~. . . ., . _. . . .~. . . .. . . . J ' - - - J ' -. . . ._ , , . . _ . . . , . , . . _. . . .J ' -. . . ....J'~. . . ., . _ Niiri. Mo. im;, IAQ, Internal Aeod lntern1I Write Figure 13 Interrupt Sequence 232 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ·· ~-. . . . . ..___~-~~~ .:::::r:l,_____,,__~~ ....." r·. .:11..IL......~~~~~~~':::x:::l.~,,__~~ - . . . . . .--.~~~~~~.~__,---< ·~~~ ... l\\\\\\\t~~~11l\llmm«1111r"~~~~~~~~~~~~~~-t1:7'\:>-f~ t:-lllllJlllllllllllllll,.__~~~~--:.~c~Jlllllllf+-~~~~~~~-~ PC15 PC7 Instruction Figure 14 Reset Timing · FUNCTIONAL PIN DESCRIPTION · vce>v.. Vee and Vss provide power to the MPU with 5V±l0% supply. In the 1:1SC oflow speed operation (fmax=500kHz), the MPU can operate with 3 to 5.5 volts. Two Vss pins should be tied to ground. · XTAL,EXTAL These two pins interface with an AT-cut parallel resonant crystal. Divide-by-four circuit is on chip, so if 4MHz crystal oscillator is used, the system clock is lMHz for example. EXTAL pin can be drived by the external clock with 45% to 55% duty. The system clock which is one fourth frequency of the external clock is generated in the LSI. The external clock frequency should be less than four times of the maximum operating frequency. When using the external clock, XTAL pin should be open. Fig. 15 shows examples of connection circuit. The crystal and Cu, CL2 should be mounted as close as possible to XTAL and EXTAL pins. Any line must not cross the line between the crystal oscillator and XTAL, EXTAL. AT Cut Parallel Resonant Crystal Oscillator Co=7pF max Rs=60Q max XTALt-------. CJ EXTALt-----. Cu=Cu = 10pF-22pF±20% (3.2-BMHz) Figure 15 Connection Circuit · JflV This pin makes the MPU standby mode. In "Low" level, the os- cillation stops and the internal clock is stabilized to make reset condition. To retain the contents of RAM at standby mode, "O" should be written into RAM enable bit (RAME). RAME is the bit 6 of the RAM/port 5 control register at $0014. RAM is disabled by this operation and its contents is sustained. Refer to "LOW POWER DISSIPATION MODE" for the standby mode. · RHet (iiD) This pin resets the MPU from power OFF state and provides a startup procedure. During power-on, Ja:!S pin must be held "Low" level for at least 20ms. The CPU registers (accumulator, index register, stack pointer, condition code register except for interrupt mask bit), RAM and the data register of ports are not initialized during reset, so their contents are undefined in this procedure. To reset the MPU during operation, RES should be held "Low" for at least 3 system-clock cycles. At the 3rd cycle during "Low" level, all the address buses become "High". When RllS remains "Low", the address buses keep "High". IfllES" becomes "High", the MPU starts the next operation. (1) Latch the value of the mode program pins; MP0 and MP,. (2) Initialize each internal register (Refer to Table 4). (3) Set the interrupt mask bit. For the CPU to recognize the maskable interrupts IRQ., IRQ. and IRQ., this bit should be cleared in advance. (4) Put the contents (=start address) of the last two addresses (SFFFE, SFFFF) into the program counter and start the program from this address. (Refer to Table 1). · Enable IEI This pin provides a TIL-compatible system clock to external cir- cuits. Its frequency is one fourth that of the crystal oscillator or external clock. This pin can drive one TIL load and 90pF capacitance. · Non-Meakebl· Interrupt INMU When the falling edge of the input signal is detected at this pin, the CPU begins non-maskable interrupt sequence internally. As @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 233 well as the mQ mentioned below, the instruction being executed at Nm signal detection will proceed to its compeletion. The interrupt mask bit of the condition code register doesn't affect non-maskable interrupt at all. In response to an Nm interrupt, the contents of the program counter, index register, accumulators and condition code register will be saved onto the stack. Upon completion of this sequence, a vector is fetched from SF.FFC and SFFFD to transfer their contents into the program counter and branch to the non-maskable interrupt service routine. (Note) At reset start, the stack pointer should be initialized on an appropriate memory area and' then the falling edge be input to 1illll pin. · Interrupt Reqll98t ftlm;. l1Rr2l These are level-sensitive pins which request an internal interrupt sequence to the CPU. At interrupt request, the CPU will complete the current instruction before the acceptance of the request. Unless the interrupt mask in the condition code register is set, the CPU starts an interrupt sequence; if set, the interrupt request will be ignored. When the sequence starts, the contents of the program counter, index register, accumulators and condition code register will be saved onto the stack, then the CPU sets the interrupt mask bit and will not acknowledge the maskable request. During the last cycle, the CPU fetches vectors depicted in Table I and transfers their contents to the program counter and branches to the service routine. The CPU uses the external interrupt pins dRQ, and IR.Q.) also as port pins P,. and P51 , so it provides an enable bit to Bit 0 and 1 of the RAM port S control register at $0014. Refer to "RAM/PORTS CONTROL REGISTER." for the details. When one of the internal interrupts, ICI, OCI, TOI, CMI or SIO is generated, the CPU produces internal interrupt signal OR.Q.). IR.Q. functions just the same as iRQ; or 'iRQ; except for its vector address. Fig. 16 shows the block diagram of the interrupt circuit. Each Status Register's Interrupt Enable Flag ··1··; Enable, "O"; Disable ISF Conditton ' Code ---+--o-~o-4----l11egiste< I MASK ICF ---+.-.o-'ll-i-=--1"0"; Enoble ··1··; Disable OCF1 IRCb TOF CMF RDRF PER __,.,__~y-o-+, ORFE TORE ---+-<O""""O--f.-J TRAP SWI Figure 16 Interrupt Circuit Block Diagram Interrupt Request Signal Sleep Cancel Signal 234 @HITACHI Hitachi America Ltd, · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 1 Interrupt Vector Memory Map Priority Highest Vector MSB LSB FFFE FFFF FFEE FFEF FFFC FFFD FFFA FFFB FFFB FFF9 FFF6 FFF7 FFF4 FFF5 FFF2 FFF3 Lowest FFEC FFEA FFFO FFED FFEB FFF1 Interrupt "RES TRAP Nm SWI (Software Interrupt) M 1, ISF (port 6 Input Strobel ICI (Timer 1 Input Capture) OCI (Timer 1 Output Compare 1, 21 TOI (Timer 1 Overflow) CMI (Timer 2 Counter Match) M2 SIO (RDRF+ ORFE +TORE+ PERI · Mode Program IMP.,. MP11 Set MP, "High" and MP, "Low". · Raad/Write (R/W) This signal, usually be in read state ("High"), shows whether the CPU is in read ("High") or write ("Low") state to the peripheral or memory devices. This can drive one TIL load and 30pf capacitance. · 'Im". WI{ These signals show active low outputs when the CPU is reading/ writing to the peripherals or memories. This enables the CPU easy to access the peripheral LSI with RU andWR input pins. These pins can drive one TIL load and 30pF capacitance. · Load ln·tructlon Regl·ter ILIRI This signal shows the instruction opecode being on data bus (active low). This pin can drive one TIL load and 30pF capacitance. · Memory Ready IMR; P121 This is the input control signal which stretches the system clock's "High" period to access low-speed memories. HD6303Y can select three kinds of low-speed memory access method by RAM/Port 5 Control Register's MRE bit and AMRE bit. In the case that CPU accesses low-speed memories by the external MR signal (MRE="l", AMRE="O"), the system clock operates in normal sequence when this signal is in "High". But this signal in "Low", the "High" period of the system clock will be stretched depending on its "Low" level duration in integral multiples of the cycle time. This allows the CPU to interface with tow-speed memories (See Fig. 2). Up to 9,..s can be stretched. During internal address space access or nonvalid memory access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High" period of system clock to allow peripheral devices to access low-speed memo- ries. Refer to "RAM/PORT 5 CONTROL REGISTER" for more details. · Halt IRAL'f; P13l This is an input control signal to stop instruction execution and to release buses. When this signal switches to "Low", the CPU stops to enter into the halt state after having executed the present instruction. When entering into the halt state, it makes BA "High" and also an address bus, data bus, llD, WR:, R/W high impedance. When an interrupt is generated in the halt state, the CPU uses the interrupt handler after the halt is cancelled. When halted during the sleep state, the CPU keeps the sleep state, while BA is "High" and releases the buses. Then the CPU returns to the previous sleep state when the HALT signal becomes "High". (Note) Please don't switch the HALT signal to "Low" when the CPU executes the WAI instruction and is in the interrupt wait state to avoid the trouble of the CPU's operation after the halt is cancelled. · Bu· Available IBAI This is an output control signal which is normally "Low" but "High" when the CPU accepts 1IACT and releases the buses. The' HD6800 and HD6802 make BA "High" and release the buses at WAI execution, while the HD6303Y doesn't make BA "High" under the same condition. · PORT The HD6303Y provides three 8-bit 1/0 ports. Each port provides Data Direction Register (DDR) which controls the 1/0 state by the bit. Table 2 Port and Data Direction Register Address Port Port2 Port5 Port6 Port Address $0003 $0015 $0017 Data Direction Register $0001 $0020 $0016 · Port 2 An 8-bit I/O port. Port 2 DDR (P2DDR) controls the 1/0 state. This port provides DDR corresponding to each bit and can define input or output by the bit ("O" for input, "I" for output). As Port 2 DDR is cleared during reset, it will be an input port. Port 2 is also used as an I/O pin for timer 1, Timer 2 and the SCI. Pins for Timers and the SCI set or reset each DDR depending on their functions and become 1/0 pins. When port 2 functions as an I/ 0 port after used as 1/0 pins of the timers or the SCI, the I/O direction of the pins remain as it is used as the 1/0 pin of timer and SCI. Port 2 can drive one TIL load and 30pF capacitance. This port can produce lmA when Vout= l.SV to drive directly the base of Darlington transistor. Pzo ITinl P.. is also used as an external input pin for the input-capture. This pin is an 1/0 port which is an input or output as defined by the Data Direction Register (P.,DDR) ("0" for an input and "I" for an output). Then either a signal to or from P20 ("to" for an output port, "from" for an input port) is always input to the Timer 1 input capture. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 235 RES 1----tl .------IQ R D P20DDR ~ c Q WP2D ~ 1-------1 Q D ~ P20DATA RP2 WP2 _L_ WP20 : DOR Write Signal WP2 : Port Write Signal RP2 : Port Read Signal '>----- --------· Timer 1 Input Capture Input P21 !Tout 11. P24 ITxl. P211Tout 21. P21 !Tout 3) These four pins can be also used as output pins for Timer l, Timer 2 and a transmit output of the SCI. Timer 1, and the SCI have a register which enables output By setting these registers, they automatically will be output pins of timer or the SCI. RES l ------'--las R o,1----4 P2.DDR c l!l w Q'" ,........,......,, __ r...-..... a o t - - - - ii E ... ,_P_2.DcATA .!= rTi-m-e-r -1-, -T-im-e-r-2- and SCI WP2 L.....S-IL..1----------+----'--- Output Data .__._ _ _ _ _ _ _ _+ - - - - i i - - Output Enable Signal 236 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 PulSCLKI P11 is also used as a clock 110 pin for the SCI. It is selected as a clock input or output pin by the operating mode of the SCI. It is usa- ble as an 110 port when the SCI has no clock input or output (as an output port if P21 DOR= I, as an input port if P21 DDR=O). P22 DOR c ~ WP2D l!! . -..........,_...r"'T"'-,Q D 1---+_.c"' P22DATA c ~ SCI r---- - ------ ! WP2 E '-+----o---- Clock Input Enable signal 1--..r-ri....+--------+----r--- Output Clock ...__._ _ _ _ _ _ _ _ _ _ ___,,___ Clock Output Enable signal RP2 -L ~..;-....;~Input Clock P23 (Rx), P27 ITCLKI P11 and P., are also used as received data input pins for the SCI and external clock input pins for Timer 2. The SCI and Timer 2 have registers which enable input. If the registers are set, the DOR (P23 DOR, P27 DDR) are cleared and P23 and P27 will be input pins for Rx and TCLK. RES Since the SCI will be a clocked synchronous mode by an external clock-input during reset, the DOR of P22 is cleared automatically and P22 is an input port. Set the SCI to a mode where P22 is not used (CCO or CCI of the RMC Register is "O" or "I" respectively) and write "l" to the P22 DOR to make P22 an output port. R1 R2 111 ..---------1,Q D t - - - +..... ~ P2. DOR f! c ~ WP2D ii E 1------~a 0 1 - - - +..... .!= P2.DATA c WP2 rSC-I-, -T-im-e-r-2--- Input Enable signal ..--..-~- SCI Receive Data, Timer 2 External Clock MSB LSB P21 P29 P25 P24 P23 P22 P21 P20 PORT2 DOR ($0001) DOR DOR DOR DOR DOR DOR DOR DOR (Write only, S00 .__...__.._...,.._..__..__....__....__....__ _, during reset.) ._I_p2_7_..l_p2_1_..l_p_25_..l_p_2_4...l._p_2_3_,l_p_2_2_,l_p2_1_,l_p2_0....115.~~!Zll .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 237 · Port 6 An &-bitl/O port. TheDDR of port Scontrols 1/0 state. Each bit of port S has a DDR which defines 1/0 state ("0" for input and "1" for output). During reset, the DDR of port S is cleared and port S becomes an input port. Port S is also usable as mQ,, ~HALT, MR and the strobed signal of port 6 for handshake (iS, OS). It is set to input or output automatically if it is used as these control signal pins (except P... JID. Since the DDR of port S, as is port 2, is set or reset by the con- trol signal, 1/0 directions of the 1/0 ports are retained after the control signal is disabled. Port 5 can drive one TTL load and 90pF capacitance. PIO liiRf1l. P11 liROal P60 and P61 are also usable as interrupt pins. The RAM/port S control registers of ll{Q", and lRQ; have enable bits (IQlE, IQ2E). When these bits are set to "1", P,. and P11 will automatically be in- terrupt input pins. P12 IMRI. P13 IHALTI ~hPaavndePe,n. aabreleablsitos usable as MR and HALT inputs. MR and (MRE, HLTE) in the RAM/Port S Control Register as IIQ, and IRQ,,. Since MRE is cleared during reset, P62 is usable as an 1/0 port, and HLTEis set during reset, the DDR of P53 will be automatically reset to be a HALT input pin. HLTE of the RAM/Port S Control Register has to be cleared to use P.. as an 1/0 port. RES R1 R> ....-----~a 01---t--. Psn DOR c ~ WP5D c ~ WP5D : DOR Write signal 1-------10 01----t--.Oi WP5 : Port Write signal PsnDATA c ~ E RP5 : Port Read signal . RP5 _!._ WP5 '---+-------tRAM/PORT 5 Control Register · Initializing value during reset; IRQ1E= ..O... IRQ2E= ..0..,MRE= ..O",HLTE= ·· , .. P141iil _ P.. is also usable as the input strobe (IS) for port 6 handshake interface. This pin, as is P,0, is always an 1/0 port. If P.. is used as an RES output port (set the DDR of Pu to "1"), an output signal from P64 will be the input to 15. R .-----~a 01----~ Ps· DOR c ~ WP5D ~ 1-------ta Ps· 0 DATA 1 - - - -. . 0 oE; c !!! RP5 WP5 -= ...!... " > - = - - - - - - - - - + - - -... Port 6 Control Status Register iS 238 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 P11 lmil P·· is also usable as the output strobe (OS) for port 6 handshake interface. It will be an 1/0 port during reset, and an OS output pin by setting the OS enable register (OSE) of the port 6 Control Status Register (P6CSR). RES R .. :I D Poo DOR c ..al !9 0 w SD ii E a D ! .!: PosDATA c rPo-rt-6-C-o-n-tr-ol-/S-ta-tus Register WPS 1 I I '--'"T'-+-~~~~~~J--~~1--os OSE ( 1 : OS output ) 0 : OS output disable P11,P17 P,. and P67 are 1/0 ports. RES R a D Pon DOR c .. :I WPSD .al !9 a D 0 Psn DATA c ii E ! WPS .!: MSB LSB Pn DOR Pse DOR Pss DOR P,.. DOR P53 DOR P52 DOR P51 DDR Pso DOR PORT5 DOR ($00201 IWrite only, $00 during reset.I I I I I I I I I I P., P58 P66 P54 Pu P52 P51 Pso P(RO/RWT,5no($t0in0i1- 51 tialized during reset.I .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 239 · Port 8 8-bit 1/0 port. Port 6 DDR controls 1/0 stste. Each bit of port 6 has a DOR and designates input or output ("0" for input, "I" for output). During reset, Port 6 DDR is cleared and port 6 becomes an input port. Port 6 controls parallel handshake interface besides functions as an 110 port. Therefore, it provides DDRs to control and IS LATCH to latch the input dats. Port 6 can drive one TTL load and 30pF capacitsnce. It can drive directly the base of Darlington transistor as port 2. RES ..------IQ R oi------.l Pen DOR c ~ Q - - - - - a WP6D iii E oF-~~-~ Pen DATA c RS R D IS LATCH c WP6 WP6D : DOR Write signal WP6 : Port Write signal RP6 : Port Read signal Port 6 Control Status Register MSB LSB Pe1 DOR Pee DOR Pes DOR Pu DOR Pe3 DOR P92 DOR Pe1 DOR Peo DOR PORTS DOR ($00161 IWrite only, $00 during reset.I I I I I I I I I I PORTS ($00171 (R/W, not iniPe1 Pee Pas P94 P03 P92 Pe1 Pso tialized during reset.I · BUS · Address Bus IA0 - A 111 Address Bus (A0 - A15) is used for addressing the memory and peripheral LSI. This bus can interface with the bus of HMCS 6800 and drive one TTL load and 90pF capacitsnce. · Data Bus ID0 - D71 8-bit parallel data bus for data transmit between the memory or peripheral LSI. This bus can drive one TTL load and 90pF capacitance. · RAM/PORT 5 CONTROL REGISTER The control register located at $0014 controls on-chip RAM and port 5. RAM/Port 5 Control Register (RP5CR) 765432 0 ~~~ RAME ~[!~ A~R HLTE MRE IR~2 IR~, $0014 Bit 0, Bit 1 TIRr1, iRQ2 Enable Bit (IRQ1E, IRQ2E) When using P50 and P51 as interrupt pins, write "I" in these bits. When the bit is set to "I", the DDRs corresponding to P,0 and P,1 are cleared and become MQ1 input pin and MQ2 input pin. When IRQ1E and IRQ2E are set, P60 and P,1 cannot be used as an output ports. When "O", the CPU doesn't accept an external interrupt or a sleep cancellation by the external interrupt. These bits are cleared during reset. l!it 2 Memory Ready Enable Bit IMREI When using P., as an input pin of the "memory ready" signal, write "I" in this bit. When set, P,. DDR is automatically cleared and becomes the MR input pin. The bit is cleared during reset. Bit 3 Halt Enabla Bit IHLTE) When using P53 as an input pin ofthe HALT signal, write "1" in this bit. When this bit is set, P,. DDR is automatically cleared and becomes the Halt input pin. If the bit is "O", the Halt function is inhibited and P,. is used as an 110 port. The bit is set to "l" during reset. Bit 4 Auto Memory Ready Enable Bit IAMREI When the bit is set and the CPU accesses the external address, "memory ready" operates automatically and stretches the E clock's "High" duration for one system clock. When MRE bit of bit 2 is cleared and when the CPU accesses the external address space, the function operates. When MRE bit is set and then the CPU accesses the external address space with P62 (MR) pin in "low", "memory ready" operates automatically. This bit is set to "l" during reset. 240 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MRE 0 0 1 1 AMRE 0 1 0 1 Table 3 "Memory Ready" Function Function "Memory ready" inhibited. When the CPU accesses the external address, "High" duration of E clock automatically becomes one-cycle longer. This state is retained during reset. "Memory ready" operates by P52 (MR) pin. The function is the same as that of tha HD6301 XO. When the CPU accesses the external address space with the P52 (MR) pin in "low", the "auto memory ready" operates. This function is affective if it has both "high-speed memory" and "slow memory" outside. Input CS signal of "slow memory" to MR pin. Bit I Stllndby Flag ISTBY FLAG) By clearing this flag, HD6303Y gets into the standby mode by software. This flag is set to "I" during reset, so the standby mode is canceled with ]{ES" pin in "low". The }{ES" pin should be in "low" until oscillation becomes stable (min. 20ms.). If the mY pin in is in "low", the standby mode can not be canceled with the RES" pin in "low". Bit 8 RAM Enable (RAMEI On-chip RAM can be disabled by this control bit. By resetting the MPU, "I" is set to this bit, and on-chip RAM is enabled. When this bit is cleared (=logic "0") on-chip RAM is invalid and the CPU can read data from external memory. This bit should be "O" before getting into the standby mode to protect on-chip RAM data. Bit 7 Standby Power Bit ISTBY PWR) When Vcc is not provided in standby mode, this bit is cleared. This is a flag for read/write and can be read by software. Ifthis bit is set before standyby mode, and remains set even after returning from standby mode, Vcc voltage is provided during standby mode and the on-chip RAM data is valid. (a) MRE=O, AMRE= 1 E l ____ J . ____ I I ...Io. Addre55-..,....,....,.--..-.... ,....--.-.-le_m_a_l_a_d_d_~-u----~r~,n-1-em--a1--·r---.-x-le_m_a_l_a_dd-~-u-----...-------- Bus ad (bl MRE=1, AMRE=1 E It ____ ..:I I"----"": Address-...,_..,,.,,.,.,.,....... ,_...,,,,.,..,.,,,.,...... ,....e-x-te-rn-a-l--a-dd-r-e-ss-----~·--""""""',,_~,--e-x-te-r-n-al--a-d-d-re-s-s----·· Bus MR (CS pin of "slow memory") (c) MRE=1,AMRE=O (HD6301XO Compatible Mode) E Address Bus MR '1,. ____J' Figure 17 Memory Ready Timing · Port 8 Control/Stlltu· Register This is the ControVStatus Register for parallel handshake inter- face using Port 6. The functions are as follows; 1) Latches input data to Port 6 at the IS (P54) falling edge. 2) Outputs a strobe signal OS (P.,) outward by reading or writ- ing to port 6. 3) When IS FLAG is set at the IS falling edge, an interrupt occurs. The following shows Port 6 Control/Status Register (P6CSR). 7 6 I-I-I I 5 4 3 2 LATCH ENABLE 0 $0021 ·a;1 7 is Reed·Oni¥M ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 241 BltO Bit 1 Bit Z Not used. Bit 3: Latch Eneble This register controls the input latch for Port 6 (ISLATCH). When this bit is set to "1 ", the input dats to port 6 will be latched inward at the1! (P..>falUng edge. An input latch will be canceled by reading Port 6, which enables to latch the next dats. 1f cleared, the input latch remains canceled and this bit t'unctions as a usual input , port. This bit is cleared during reset. Bit 4: OSS Output Strobe Select This register initiates an output strobe ({jS) from P,. by reading or writing to port 6. When cleared, M occurs by reading Port 6. When set, N occurs by writing to Port 6. This bit is cleared during reset. Bit I: 081 Output Strobe Eneble This register decides the enabling or disabling of the output strobe. When cleared, P11 functions as an 1/0 port. When set, P11 t'unctlona as an N output pin. (P11 DOR is set by OSB.) This bit is cleared durina reset. Bit 8: 18 IRO, Eneble Input Strobe Interrupt Eneble When set, an~ interrupt to the CPU occurs by setting IS FLAG of bit 7. When cleared, the interrupt doea not occur. This bit is cleared durin1 reset. Bit 7: 18 Flel Input Strobe Flee This flag is set at the IS (P..>falling edge. This Ila& is for read- only. When set, the Ila& is cleared by reading or writing to Port 6 after reading the Port 6 Control Status Register. This bit is cleared during reset ·MEMORY MAP The MPU can address up to 6Sk bytes. Memory map is shown in F'ig. 20. 40 addresses (SOOOO - $0027 except $00, S02, $04, SOS, S06, $07, SIB) are the internal regiaters as shown in Table 4. Port 6 Control/Status Register Figure 18 Input Strobe Interrupt block Diagram Vee Im Wit R/W t:1lf HD6303Y BA MPU 242 Figure 19 HD6303Y Operating Function ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 4 lntemal Register Address Register oo· 01 02· 03 04" 05· oe· 01· 06 09 OA OB oc OD OE OF 10 11 12 13 14 15 16 17 18 19 1A 18 1C 10 1E 1f···· 20 21 22 23 24 25 26 27 Port 1 DOR (Data Direction Registerl Port2 DOR Port 1 Port2 Port3 DOR Port4DDR Port3 Port4 Timer Control/Status Register 1 Free Running Counter (MSBI Free Running Counter (LSB) Output Compare Register 1 (MSBI Output Compare Register 1 (LSBI Input Capture Register (MSB) Input Capture Register (LSBI Timer Control/Status Register 2 Rate/Mode Control Register Tx/Rx Control Status Register 1 Receive Data Register Transmit Data Register RAM/Port 5 Control Register Port5 Porte DOR Port6 Port7 Output Compare Register 2 (MSBI Output Compare Register 2 (LSBI Timer Control/Status Register 3 Time Constant Register Timer 2 Up Counter Tx/Rx Control Status Register 2 Test Register· PORT5DDR PORT 6 Control/Status Register ----- - Reserved · External addreas. ·· R: Reed-only register, W: Write-only register, R/W: Read/Write register. ··· When empty bit is in the register, it is set to ··1 ··. ···· Register for test. Don't access this register. Abbreviation P1DDR P2DDR PORT1 PORT2 P3DDR P4DDR PORT3 PORT4 TCSR1 FRCH FRCL OCR1H OCR1L ICRH ICRL TCSR2 RMCR TRCSR1 RDR TOR RP5CR PORT5 P&DDR PORTS PORT7 OCR2H OCR2L TCSR3 TCONR T2CNT TRCSR2 TSTREG P5DDR P&CSR ----- Rtw·· w w R/W R/W w w R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R w R/W R/W w R/W R/W R/W R/W R/W w R/W R/W - w R/W ------ Initialized value during reset·.. $FE $00 indefinite indefinite $FE $00 indefinite indefinite $00 $00 $00 $FF $FF $00 $00 $10 $CO $20 $00 indefinite $FB or$78 indefinite $00 indefinite indefinite $FF $FF $20 $FF $00 $28 - $00 $07 ------ .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 243 $0000 $0027 $0040 $013F mtern111 · Register Extemel Memory Space Internal RAM 256 Bytes External Memory Space $FFFF "This mode does not include the addresses: $00, $02. $04, $05, $06, $07 or $18 which can be used externally. Figure 20 H06303Y Memorv Map · TIMER 1 The HD6303Y provides a 16-bit programmable timer which can simultaneously measure an input waveform and generate two independent output waveforms. The pulse widths of both input/output waveforms vary from microseconds to seconds. Timer l is configured as follows (refer to Fig. 22). Control/Status Register 1 (8 bit) Control/Status Register 2 (7 bit) Free Running Counter (16 bit) Output Compare Register 1 (16 bit) Output Compare Register 2 (16 bit) Input Capture Register (16 bit) e Free-Running Counter IFRCll$0009:000AI The key timer element is a 16-bit free-running counter driven and incremented by system clock. The counter value is readable by software without affecting the counter. The counter is cleared during reset. When writing to the upper byte ($09), the CPU writes the preset value ($FFF8) into the counter (address $09, SOA) regardless of the write data value. But when writing to the lower byte (SOA) after the upper byte writing, the CPU writes not only lower byte data into lower 8 bit, but also upper byte data into higher 8 bit of the FRC. The counter will be as follows when the CPU writes to it by double store instructions (STD, STX, etc.) Counter value SFFF8 i In the case of the CPU write ( S 5AF3) to the FRC Figure 21 Counter Write Timing e Output ComP11re Register (OCR) 1$000B, $000C; OCR11 ($0019, $001A: OCR2) The output compare register is a 16-bit read/write register which can control an output waveform. The data of OCR is always compared with the FRC. When the data matches, output compare flag (OCF) in the timer control/status register (TCSR) is set. Ifan output enable bit (OE) in the TCSR2 is "l ",an output level bit(OLVL) in the TCSR will be output to bit 1 (OCR l) and bit S (OCR 2) of port 2. To control the output level again by the next compare, the value of OCR and OLVL should be changed. The OCR is set to SFFFF at reset. The compare function is inhibited for a cycle just after a write to the upper byte of the OCR or FRC. This is to set the 16-bit value valid in the counter register for compare. In addition, it is because counter is to set $FFF8 at the next cycle of the CPU's upper byte write to the FRC. · For data write to the FRC or the OCR, 2-byte transfer instruction (such as STX, etc.) should be used. e Input Capture Register llCRI ($GOOD : OOOEI The input capture register is a 16-bit read-only register which stores the FRC's value when external input signal transition generates an input capture pulse. Such transition is controled by input edge bit (IEDG) in the TCSR1. In order to input the external input signal to the edge detector, a bit of the DOR corresponding to bit 0 of port 2 should be cleared ("O"). When an input capture pulse OCC\lrs by external input signal transition at the next cycle of CPU's high-byte read of the !CR, the input capture pulse will be delayed by one cycle. In order to ensure the input capture operation, a CPU read of the ICR needs 2-byte transfer instruction. The input pulse width should be at least 2 system cycles. This register is cleared ($0000) during reset. e Timer Control/Statue Register 1 (TCSR1) 1$00081 The timer control/status register I is an 8-bit register. All bits are readable and the lower S bits are also writable. The upper 3 bits are read-only which indicate the following timer status. Bit S The counter value reached to $0000 as a result of coun- ting-up (TOF). Bit 6 A match has occurred between the FRC and the OCR 1 (OCFI). Bit 7 Defined transition of the timer input signal causes the counter to transfer its data to the !CR (!CF). The followings are the each bit descriptions. Timer Control/Status Register 1 76 54 32 0 !CF OCF 1 TOF EICI EOCl1 ETOl IEOG OLVL1 $0008 Bit 0 OLVL1 Output Level 1 OLVLI is transferred to port 2, bit 1 when a match occurs be- tween the counter and the OCR!. If bit 0 of the TCSR2 (OEl). is set to "I", OLVLI will appear at bit 1 of port 2. 8it 1 IEDG Input Edge This bit determines which edge, rising or falling, of input signal of bit 0 of port 2 will trigger data transfer from the counter to the !CR. For this function, the DOR corresponding to port 2, bit 0 should be cleared beforehand. IEDG= 0, triggered on a falling edge ("High" to "Low") !EOG= I, triggered on a rising edge ("Low" to "High") Bit 2 ETOI Enable Timer Overflow Interrupt When this bit is set, an internal interrupt (IRQ,) by TOI inter- rupt is enabled. When cleared, the interrupt is inhibited. Bit 3 EOCl1 Enable Output ComP11re Interrupt 1 244 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 When this bit is set, an internal interrupt (IRQ,) by OCH interrupt is enabled. When cleared, the interrupt is inhibited. Bit 4 ElCI Enable Input Capture Interrupt When this bit is set, an internal interrupt (IRQ,) by ICI interrupt is enabled. When cleared, the interrupt is inhibited. Bit 5 TOF Timer Overflow Fltlg This read-only bit"is set when the counter increments from SFFFF by 1. aeared when the counter's MSB byte ($0009) is read by the CPU after the TCSRl read at TOF= 1. Bit 8 OCF1 Output Compere Fleg 1 This read-only bit is set when a match occurs between the OCRl and the FRC. Cleared when writing to the OCRl ($000B or SOOOC) after the TCSRl or TCSR2 read at OCF= 1. Bit 7 ICF Input Capture Fltlg This read-only bit is set when an input signal of port 2, bit 0 makes a transition as defined by IEDG and the FRC is transferred to the ICR. Cleared when reading the upper byte ($0000) of the ICR after the TCSR1 or TCSR2 read at ICF= 1. e Timer Control/Stetu· Regl·ter 2 (TCSR2) l$000F) The timer control/status register 2 is a 7-bit register. All bits are readable and the lower 4 bits are also writable. But the upper 3 bits are read-only which indicate the following timer status. Bit S A match has occurred between the FRC and the OCR2 (OCF2). Bit 6 Timer Control/Status Aegister 2 I 7 8 5 4 3 2 1 0 1cF jocF11ocF21-1eoc12fLvL21oe21 oe1 SOOOF Bit 7 The same status flag as the ICF flag of the TCSRl, bit 7. The followings are the each bit descriptions. Bit 0 OE1 Output Eneble 1 This bit enables the OLVLl to appear at port 2, bit 1 when a match has occurred between the counter and the output compare register 1. When this bit is cleared, bit 1 of POrt 2 will be an 1/0 port. When set, it will be an output ofOLVLl automatically. Bit 1 OE2 Output Eneble 2 This bit enables the OLVL2 to appear at port 2, bit S when a match has occurred between the counter and the output compare register 2. When this bit is cleared, port 2, bit S will be an U 0 port. When set, it will be an output of0LVL2 automatically. Bit 2 OLVL2 Output Level 2 OLVL2 is transferred to port 2, bit Swhen a match has occurred between the counter and the OCR2. If bit S of the TCSR2 (OE2), is set to "1 ", OLVL2 will appear at port 2, bit S. Bit 3 EOCl2 Eneble Output Compere lnterrurrt 2 When this bit is set, an internal interrupt (IRQ,) by OCI2 interrupt is enabled. When cleared, the interrupt is inhibited. Bit 4 Not used Bit 15 OCF2 Output Compere Fleg 2 This read-only bit is set when a match has occurred between the counter and the OCR2. Cleared when writing to the OCR2 ($0019 or SOOlA) after the TCSR2 read at OCF2= 1. Bit 8 OCF1 Output Compere Flag 1 Bl't 7 ICF Input C.pture Fleg OCFl and ICF are dual addressed. If which register, TCSRl or TCSR2, CPU reads, it can read OCFl and ICF to bit 6 and bit 7. Both the TCSR1 and TCSR2 will be cleared during reset. <Note) If OEl or OE2 is set to "I" before the first output com- pare match occurs after reset restart, bit I or bit Sof port 2 will produce "0" respectively. $19. S1A Output Compere Register 2 IR(b Figure 22 Timer 1 Block Diagram @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 245 ·TIMER 2 In addition to the timer 1, the HD6303Y provides an 8-bit re- loadable timer, which is capable of counting the external event. The timer 2 contains a timer output, so the MPU can generate three independent waveforms. (Refer to Fig. 23.) The timer 2 is configured as follows: Control/Status Register 3 (7 bits) · 8-bit Up Counter · Time Constant Register (8 bits) · Timer 2 Up Counter CT2CNTI ltoCl1DI This is an 8-bit up counter which operates with the clock decided by CKSO and CKSl ofthe TCSR3. The CPU can read the value of the counter without affecting the counter. In addition, any value can be written to the counter by software even during counting. The counter is cleared when a match occurs between the counter and the TCONR or during reset. If the write operation is made by software to the counter at the cycle ofcounter clear, it does not reset the counter but put the write data to the counter. · Time Constant Register CTCONRI l$001CI The time constant register is an 8-bit write only register. The data of register is always compared with the counter. When a match has occurred, the counter match flag (CMF) of the timer control status register 3 (TCSR3) is set and the value selected by TOSO and TOSI of the TCSR3 will appear at port 2, bit 6. When CMF is set, the counter will be cleared simultaneously and then start counting from $00. This enables regular interrupts and waveform outputs without any software support. The TCONR is set to "$FF" during reset. · Timer Control/Status Register 3 CTCSR31 1$001 Bl The timer control/status register 3 is a 7-bit register. All bits are readable altd 6 bits except for CMF can be written. The followings are each pin descriptions. Timer Control/Status Register 3 -1 7 6 5 4 3 2 1 0 ICMF,ECMll T2E,TOS1,TOSO,CKS1,CKSOI $0018 Bit 0 CKSO Input Cloek Select 0 Bit 1 CKS1 Input Clock Select 1 Input clock to the counter is selected as shown in Table S depending on these two bits. When an external clock is selected, bit 7 of port 2 will be a clock input automatically. TIDler 2 detects the rising edge of' the external clock and increments the counter. The external clock is countable up to half the frequency of the system clock. HD8303Y Internal Data Bus .----Timerl FRC Input Clock Select Port2 Bit 7 J... !c ! u 5 Output Level Control Port 2 Bit 8 T2E TOSl TOSO CKSl CKSO T$C0S0R1B3 IR<b Figure 23 Timar 2 Block Diagram 246 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 5 Input Clock Select CKS1 0 0 1 1 CKSO 0 1 0 1 Input Clock to the Counter Eclock E clock/e· E clock/128· Extemal clock · These clocko come from the FRC of the timer 1. If one of th... clocki Is selected es an input clock to the up counter. the CPU should not write to the FRC of the timer 1. Bit 2 TOSO Timer Output Select 0 Bit 3 TOS1 Timer Output Select 1 When a match occurs between the counter and the TCONR timer 2 outputs shown in Table 6 will appear at port 2, bit 6 depending on these two bits. When both TOSO and TOSI are "0", bit 6 of port 2 will be an 1/0 port. Table 6 Timer 2 Output Select TOS1 0 0 1 1 TOSO 0 1 0 1 Timer Output Timer Output Inhibited Toggle Output" Output"O" Output "1" · When · match occurs between the counter end the TCONR, timer 2 output level is reversed. This leads to production of a square wave with 60% duty to the external without any software suppdrt. Bit 4 TZE Timer 2 Enable Bit When this bit is cleared, a clock input to the up counter is inlu'bited and the up counter stops. When set to "l", a clock selected by CKSI and CKSO (Table S) is input to the up counter. (Note) P21 outputs "O" when T2E bit cleared and timer 2 set in output enable condition by TOSI or TOSO. It also outputs "0" when T2E bit set "I" and timer 2 set in output enable condition before the first counter match occurs. Bit & Not Used. Bit 8 ECMI Enable Counter Match Interrupt When this bit is set, an internal interrupt (IRQ,) by CMI is enabled. When cleared, the interrupt is inhibited. Bit 7 CMF Counter Match Flag This read-only bit is set when a match occurs between the up counter and the TCONR. Cleared by writing "O" at CMF= I by software (unable to write "I" by software). Each bit of the TCSR3 is cleared during reset. · SERIAL COMMUNICATION INTERFACE (SCI) The Serial Communication Interface (SCI) in the HD6303Y contains the following two operating modes: asynchronous mode by the NRZ format, and clocked synchronous mode which transfers data synchronously with the clock. In the asynchronous mode, data length, parity bits and number of stop bits can be selected, and'eigHt transfer formats are provided. The SCI consists of the following registers as shown in Fig. 24 Block Diagram. Transmit/Receive Control Status Register 1 (TRCSRI) Rate/Mode Control Register (RMCR) Transmit/Receive Control Status Register 2 (TRCSR2) Receive Data Register (RDR) Recevie Shift Register Transmit Data Register (TDR) Transmit Shift Register To operate the SCI, initialize the RMCR and TRCSR2, after selecting the desirable operating mode and transfer format. Next, set the enable bit (TE or RE) of the TRCSRl. Operating mode and transfer format should be changed when the enable bit (TE, RE) is cleared. When setting the TE or RE apin after changing the operating mode or transfer format, interval of more than a 1-bit cycle of the baud rate OJ bit rate is necessary. If a I-bit cycle or more is not allowed, the SCI block may not be initialized. Receive Shift Register MSB RDR MSB TDR HD8303Y INTERNAL DATA BUS LSB RMCR SS1 SSO Transmit Shift Register Timerl FRC Timer2 Figure 24 SCI Block Diagram $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435~8300 247 · Asynchronous Mod· Asynchronous mode contains 8 transfer formats as shown in Fig. 25. Data transmission is enabled by setting TE bit of the TRCSR l, then port 2, bit 4 will unconditionally become a serial output independently of the corresponding DDR. To transmit data, set the desirable transmit format with RMCR and TRCSR2. When the TE bit is set, the data can be transmitted after transmitting the one frame of preamble ("l"). The conditions at this stage are as follows. I) If the TDR is empty (TDRE= !), consecutive l's are pro- duced to indicate the idle state. 2) If the TDR contains data (TDRE=O), data is sent to the Transmit Shift Register and data transmit starts. During data transmit, a start bit of "O" is transmitted first. Then 7-bit or 8-bit data (starts from bit 0) is transmitted. With PEN= 1, the parity bit, even or odd, selected by EOP bit is added, lastly the stop bit (1 bit or 2 bis) is sent. When the TDR is "empty", hardware sets TDRE flag bit. If the CPU doesn't respond to the flag in proper timing (the TDRE is in set condition till the next normal data transfer starts from the transmit data register to the transmit sift register), "I" is transferred instead of the start bit "O" and continues to be transferred till data is provided to the data register. While the TDRE is "1 ", "O" is not transferred. Data receive is possible by setting RE bit. This makes port 2, bit 3 a serial input. The operation mode of data receive is decided by the contents of the TRCSR2 and RMCR at first, and set RE bit of TRCSRl. The first "O" (space) synchronizes the receive bit flow. Each bit of the following data will be strobed in the middle. If a stop bit is not "I", a framing error assumed and ORFE is set. When a framing error occurs, receive data is transferred to the Receive Data Register and the CPU can read the error-generating data. This makes it possible to detect a line break. When PEN bit is set, the parity check is done. If the parity bit does not match the EOP bit, a parity error occurs and the PER bit is set, not the RDRF bit. Also, when the parity error occurs the receive data can be read just like in the case of the framing error. The RDRF flag is set when the data is received without a framing error and a parity error. If RDRF is still set when receiving the stop bit of the next data, ORFE is set to indicate the overrun generation. CPU can get the receive data by reading RDR. When 7 bit data format is selected, the 8th bit of RDR is "O". When the CPU read the receive Data Register as a response to RDRF flag or ORFE flag after having read TRCSR, RDRF or ORFE is cleared. (Note) Clock Source in Asynchronous Mode If CCI :CCO= 10, the internal bit rate clock is provided at P., regardless of the values for TE or RE. Maximum clock rate is E+l6. If both CCI and CCO are set, an external TTL compatible clock must be connected to P22 at sixteen times (16x) the desired bit rate, but not greater than E. ( 1) lsTARTI (2) lsTARTI (3) lsTARTI (4) lsTARTI (5) lsTARTl (6) lsTARTl (7) lsrARTI (8) lsrARTI 7Bit Data 7Bit Data 7Bit Data 7Bit Data 8Bit Data 8Bit Data 2STOP I I I PARITY STOP I I PARITY 2 STOP I STOP' 2STOP 88it Data 88it Data IPARITYj 2 STOP Figure 25 Asynchronous Mode Transfer Format · Clocked Synchronous Mod· In the clocked synchronous mode, data transmit is synchronized with the clock pulse. The HD6303Y SCI provides functionally independent transmitter and receiver which makes full duplex operation possible in the asynchronous mode. But in the clocked synchronous mode an SCI clock 1/0 pin is only P22, so the simultaneous receive and transmit operation is not available. In this mode, TE and RE should not be in set condition ("I") simultaneously. Fig. 26 gives a synchronous clock and a data format in the clocked synchronous mode. I) Data transmit Data transmit is realized by setting TE bit in the TRCSR I. Port 2, bit 4 becomes an output unconditionally independent of the value of the corresponding DDR. Both the RMCR and TRCSR should be set in the desirable oper- ating condition for data transmit. When an external clock input is selected and the TDRE flag is "O", data transmit is performed from port 2, bit 4, synchronizing with 8 clock pulses input from external to port 2, bit 2. Data is transmitted from bit 0 and the TDRE is set when the Transmit Shift Register (TSR) is "empty". More than 9th clock pulse of external are ignored. When data transmit is selected to the clock output, the MPU produces transmit data and synchronous clock at TDRE flag clear. 2) Data receive Data receive is enabled by setting RE bit.. Port 2, bit 3 will be a serial input. The operating mode of data receive is decided by the TRCSRl and the RMCR. If the external clock input is selected, 8 external clock pulses and the synchronized receive data are input to port 2, bit 2 and bit 3 respectively. The MPU put receive data into the receive data shift register by this clock and set the RDRF flag at the termination of 8 bit 248 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 data receive. More than 9th clock pulse of external input are ignored. When RDRF is cleared, the MPU starts receiving the next data instantly. So, RDRF should be cleared with P11 "High". When data receive is selected with the clock output, 8 syn- chronous clocks are output to the external by setting RE bit. So re- c:eive data should be input from external synchronously with this clock. When the first byte data is received, the RDRF flag is set. After the second byte, receive operation is performed by sending the synchronous clock to the external after clearing the RDRF bit. <:c=====:::J· Transmit Direction Synchronous dock ~NotVelid - Tren1mit dllte i1 produced from· falling edge of· synchronous dock to tha next falling edge. · R-ive date is latched at tha rising edgo. Figure 26 Clocked Synchronous Mode Format e Trmn8mlt/R-lve Control Status Register CTRCSR1 I 1$00111 The TRCSRI is composed ofB bits which are all readable. Bits 0 to 4 are also writable. This register is initialized to $20 during reset. Each bit functions are as follows. Transmit/Receive Control Status Register I I 7 8 5 4 3 2 1 0 IRDRF ORFEI TDREI RIE I RE I TIE TE I WU I $0011 Bit 0 WU Wake-up In a typical multi-processor configuration, the software pro- tocol provides the destination address at the first byte of the message. In order to make uninterested MPU ignore the remaining message, a wake-up function is available. By this, unin- terested MPU can inhibit all further receive processing till the next message starts. Then wake-up function is triggered by consecutive l's with l frame length. The software protocol should provide the idle time between messages. By setting this bit, the MPU stops data receive till the next re- message. The receive ofconsecutive "l" with one frame length wakes up and clears this bit by hardware and then the MPU starts receive operation. However, the RE flag should be already set before settin& this bit. In the clocked synchronous mode WU is not available, so this bit should not be set. Bit 1 TE Transmit Enable When this bit is set, transmii data will appear at port 2, bit 4 after one frame preamble in asynchronou5 mode, while in clocked synchronous mode it appears immediately. This is executed regardless of the value of the corresponding DDR. When TE is cleared, the serial 1/0 doesn't affect port 2, bit 4. Bit 2 TIE Transmit Interrupt Enable When this bit is set, an internal interrupt (IRQ.) is enabled when TDRE (bit S) is set. When cleared, the interrupt is inhibited. Bit 3 RE ~Ive Enable When set, a signal is input to the receiver from port 2, bit 3 regardless of the value of the DDR. When RE is cleared, the serial UO doesn't aftTect port 2, bit 3. Bit 4 RIE Receive Interrupt Enable When this bit is set, an internal interrupt (IRQ.) is enabled when RDRF (bit 7) or ORFE (bit 6) is set. When cleared, the interrupt is inhibited. Bit & TDRE Transmit Data Raglater Empty TDRE is set by hardware when the TDR is transferred to the Transmit Shift Register in the asynchronous mode, while in clocked synchronous mode when the TDSR is "empty". This bit is cleared by reading the TRCSR I or TRCSR2 and writing new transmit data to the TDR when TDRE= l TDRE is set to "1" during reset. Bit 8 ORFE Overrun Framing Enor ORFE is set by hardware when an overrun or a framing error is generated (during data-receive only). An overrun error occurs when new receive data is ready to be transferred to the RDR during RDRF still being set. A framing error occurs when a stop bit is "0". But in clocked synchronous mode, this bit is not affected. This bit is cleared by reading the TRCSRl or TRCSR2, and the RDR, when RDRF= I. ORFE is cleared during reset. Bit 7 RDRF Receive Data Register Full RDRF is set by hardware when data is received normally and transferred from the Receive Shift Register (RSR) to the RDR. This bit is cleared by reading TRCSRl or TRCSR2, and the RDR, when RDRF= l. This bit is cleared during reset. e Transmit Reta/Mode Control Reglatar IRMCRI The RMCR controls the following serial 1/0: · Baud Rate · Data Format · Clock source · Port 2, Bit 2 Function · Operation Mode All bits are readable/writable. Bit 0 to Sof the RMCR are cleared during reset. Transfer Rate/Mode Control Register I- I I I 7 8 5 4 3.2 1 0 5521 cc21 cc1 ecol 551 5501 soo10 Bit 0 SSO Bit 1 881 Bit & 882 Speed Select These bits control the baud rate used for the SCI. Table 7 lists the available baud rates. The timer I FRC (SS2=0) and the timer 2 up counter (SS2= l) provide the internal clock to the SCI. When selecting the timer 2 as a baud rate clock source, it functions as a baud rate generator. The timer 2 generates the baud rate listed in Table 8 depending on the value of the TCONR. (Note) When operating the SCI with internal clock, do not per- form write operation to the timer/counter which is the @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 249 Table 7 SCI Bit Times and Transfer Rates (11 Asynchronous Mode 5$2 551 550 0 0 0 00 1 0 10 0 11 1- - XTAL E E+16 E+12B E+1024 E+4096 - 2.4576MHz 614.4kHz 26,-s/38400Baud 20811S/4800Baud 1.67ms/600Baud 6.67ms/150Baud · 4.0MHz 1.0MHz 16µs/62500Baud 12811s/7812.5Baud 1.024ms/976.6Baud 4 096msl244.1 Baud · 4.9152MHz 1,2288MHz 13µs/76800Baud 104.211s/9600Baud 833.3µs/1200Baud 3.333ms/300Baud · ·When SS2 is "I", Timer 2 provides SCI ciocks. rt1e baud rate is shown as follows wi1h 1he TCONR as N. f Baud Rate = 32 (N+ 1) f : input clock frequency to the) ( timer 2 counter N = 0-255 121 Clocked Synchronous Mode · 552 $$1 sso 0 0 0 00 1 0 10 0 11 1-- XfAL E E+2 E+16 E+128 E+512 - 40MHz 1.0MHz 2 1,s/bit 16µ5/bit 128µs/bit 512µ5/blt ·· 6.0MHz 1.5MHz 1 33µSlbit 10.7µS/bit 85.3µ5/blt 341115/bit ·· B.OMHz 2.0MHz lµs/bit Sµs/bit 64µs/bit 256µ5/bit · · ·Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is operatable up to DC - I /2 system clock. ··The bit rate is shown as follows with the TCONR as N. Bit Rate (µs/bit) = 4 (N+ I) f f: input clock frequency to the) ( timer 2 counter N= o-2ss Table 8 Baud Rate and Time Constant Register Example ~L Baud 2.4576MHz 3.6864MHz 4.0MHz 110 150 300 600 1200 2400 4800 9600 19200 38400 21· 32· 35· 127 191 207 63 95 103 31 47 51 15 23 25 7 11 12 3 5 - 1 0 - -2 - - - · E/8 clock is input to the timer 2 up counter and E clock otherwise. 4.9152MHz 43· 255 127 63 31 15 7 3 1 0 8.0MHz 10· 51" 207 103 51 25 12 - - 250 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Bit 2 Bit 3 Bit 4 clock source of the SCI. cco CC1 Clock Control/Format Select· CC2 These bits control the data formal and the clock source (refer to Table 9). · CCO, CCI and CC2 are cleared during reset and the MPU goes to the clocked synchronous mode of the external clock operation. Then the MPU automatically set port 2, bit 2 into the clock input state. When using port 2, bit 2 as an output port, the DOR of port 2 should be set to "l" and CCI and CCO to "0" and "l" respectively. Bit 6 Not Used. Bit 7 Not Used · Transmit/Receive Control Status Register 2 ITRCSR21 The TRCSR2 is a 7-bit register which can select a data format in the asynchronous mode. The upper 3 bits are the same address as the TRCSRI. Therefore, the RDRF, ORFE and TORE can be read by either the TRCSRI or TRCSR2. Bits 0 to 2 of the TRCSR2 are used for read/write. Bits 4 to 7 are used only for read. Transmit/Receive Control Status Register 2 7654321 $001E Bit 0 BBL Stop Bit Length This bit selects the stop bit length in the asynchronous mode. If this bit is "0", the stop bit is I-bit. If" I", the stop bit is 2-bit. This bit is cleared during reset. Bit 1 EOP Even/Odd P·rlty This bit selects the parity generated and checked when the PEN is "I". If this bit is "O", the parity is even. If" I", it is odd. This bit is cleared during reset. Bit 2 PEN P·rlty En·ble This bit decides whether the parity bit should be generated and checked in the asynchronous mode or not. If this bit is "O", the parity bit is neither generated nor checked. If" I", it is generated and checked. This bit is cleared during reset. The 3 bits above do not affect the SCI opertion in the clocked synchronous mode. Bit 3 Not Used Bit 4 PER Parity Error This bit is set when the PEN is "l" and a parity error occurs. It is cleared by reading the RDR after reading the TRCSR2, when PER=I. Bit & TDRE Transmit Data Register Empty Bit 6 ORFE Overrun/Framing Error Bit 7 RDRF Receive Data Register Full · Each flag of the TORE, ORFE, and RDRF can be read from either the TRCSRI or TRCSR2. · TIMER. SCI STATUS FLAG Table to shows the set and reset conditions of each status flag in the timer I, timer 2 and SCI. Table 9 SCI Format and Clock Source Control CC2 CC1 cco Format Mode Clock Source Port 2, Bit 2 0 0 0 8-bit data Clocked Synchronous External Input 0 0 1 8-bit data Asynchronous Internal Not Used** 0 1 0 8·bit data Asynchronous Internal Output* 0 1 1 B-bit data Asynchronous External Input 1 0 0 8·bit data Clocked Synchronous Internal Output 1 0 1 7-bit data Asynchronous Internal Not Used.. 1 1 0 7-bit data Asynchronous Internal Output* 1 1 1 7-bit data Asynchronous External Input l Port 2, Bit 3 Port 2, Bit 4 When the TRCSR1, RE bit is "1", bit 3 is used as a serial input. When the TRCSR 1, TE bit is "1 ", bit 4 is used as a serial output. ·Clock output regardless of the TRCSRI, bit RE and TE. ·· Not used for the SCI. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 251 P6CSR IS FLAG ICF Timer 1 OCF1 OCF2 TOF Timer 2 CMF RDRF ORFE SCI TORE PER !Note) - ; Transfer = ; equal Table 1O Timer 1, Timer 2 and SCI Status Flag Set Condition Falling edge input to P54 (IS) FRC - ICR by Rising or Falling edge input to P20 (Selecting with the IEDG bit) OCR1 = FRC OCR2 = FRC FRC = $FFFF+ 1 cycle T2CNT = TCONR Receive Shift Register - RDR 1. Framing Error (Asynchronous Model Stop Bit= 0 2. Overrun Error (Asynchronous Mode) Receive Shift Register - RDR when RDRF = 1 1. Asynchronous Mode TOR - Transmit Shift Register 2. Clocked Synchronous Mode Transmit Shift Register is "empty" 3. RES"= 0 Parity when PEN= 1 ICRH; Upper byte of ICR OCR 1H; Upper byte of OCR 1 OCR2H; Upper byte of OCR2 Clear Condition 1. Read the P6CSR then read or write the PORTS, when IS FLAG = 1 2. RES=o 1. Read the TCSR 1 or TCSR2 then ICRH, when ICF = 1 2. RES=O 1. Read the TCSR1 or TCSR2 then write to the OCR1H or0CR1L, when OCF1 = 1 2. m = o 1. Read the TCSR2 then write to the OCR2H or OCR2L, when OCF2 = 1 2. m = o 1. Read the TCSR1 then FRCH, when TOF= 1 2. ~=O 1. Write "O" to CMF, when CMF = 1 2. RE"S=o 1. Read the TRCSR1 or TRCSR2 then RDA, whenRDRF = 1 2. RES= 0 1. Read the TRCSR1 or TRCSR2 then RDA, when ORFE = 1 2. RES=O Read the TRCSR 1 or TRCSR2 then write to the TOR, when TORE = 1 1. Read the TRCSR2 then RDA, when PER= 1 2. m=o OCR 1L; Lower byte of OCR 1 OCR2L; Lower byte of OCR2 FRCH; Upper byte of FRC 252 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · LOW POWIR Dl881PATION MODE The HD6303Y provides two low power dissipation modes; sleep and standby. · 81HP Mode The MPU goes to the sleep mode by SLP instruction execution. In the sleep mode, the CPU stops its operation, while the registers' contents are retained. In this mode, the peripherals except the CPU such as timers, SCI, etc. continue their functions. The power dissipation ofsleep-condition is one fourth that of operating condition. The MPU returns from this mode by an interrupt, RES or "STBY; it goes to the reset state by1ll!S" and the standby mode by "STBY. When the CPU acknowledges an interrupt request, it cancels the sleep mode, returns to the operation mode and branches to the interrupt routine. When the CPU masks this interrupt, it cancels the sleep mode and executes the next instruction. However, for example, if the timer I or 2 prohibits a timer interrupt, the CPU doesn't cancel the sleep mode because of no interrupt request. This sleep mode Is effective to reduce the power di11ipatlon for a system with no need of the HD6303Y's consecutive operation. ·. Standby Mode The MPU goes to the standby mode with the1TBY "Low" or by clearing the STBY Oas. In this mode, the HD6303Y stops all the clocks and goes to the reset state. In this mode, the power dissipation is reduced to several µ,A. During standby, all pins, except the power supply (Vee, V~, the1TBY, lll!S"and XTAL (which out- cc> puts "0"), go to the high impedance state. In this mode, power (V is supplied to the HD6303Y, and the contents of RAM is retained. The MPU returns from this mode during reset. When the MPU goes to the standby mode with STBY "Low", it will restart at the timing shown in Fig. 27(a). When the MPU goes to the standby mode by clearing the STBY Oas, it will restart only by keeping the 1{ES "Low" for longer than the oscillating stabilization time. (F1g. 27(b)) Vee (l)NMll (~ CD NMI HD8303Y sm ~ t)AEs (l ST8Y RES 'I> v.. v.. mm II I I I I I I I 111111 I~ I I I I I I I· ·I· Standby Mode O Save llogiatero ·I· ·I 0 Oodllotor Sun I 0 RAM/Port 5 C-Regilter Sat Tilnto f - + Restart (a) Standby Mode by STBY Vee HD8303Y + I I I I I I OSTBY FLAG Clear !-1 I I I : I ! Standby Mode I I ' 0' Olcilllltor: Start~ Tme !Restart (b) Standby Mode by the STBY Flag Figure 2 7 Standby Mode Timing 4!>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 253 · TRAP FUNCTION The CPU generates an interrupt with the highest priority (TRAP) when fetching an undefined instruction or an instruction from non-memory space. The TRAP prevents the system-burst caused by noise or a program error. · Op Code Error When fetching an undefined op code, the CPU saves registers as well as a normal interrupt and branches to the TRAP (SFFEE, SFFEF). This has the priority next to reset. · Address Error When an instruction fetch is made from the address of internal register, the MPU generaters an interrupt as well as an op code error. But on the system with no memory in its external memory area, this function is not applicable if an instruction fetch is made from the external non-memory area. Addresses where an address error occurs are from $0000 to $0027. This function is available only for an instruction fetch and is not applicable to the access of normal data read/write. (Note) The TRAP interrupt provides a retry function differently from other interrupts. This is a program flow return to the address where the TRAP occurs when a sequence returns to a main routine from the TRAP interrupt routine by RTI. The retry can prevent the system burst caused by noise, etc. However, if another TRAP occurs, the program repeats the TRAP interrupt forever, so the consideration is neces- sary in programming. · INSTRUCTION SET The HD6303Y provides object code upward compatible with the HD6801 to utilize all instruction set of the HMCS6800. It also reduces the execution times of key instructions for throughput improvement. Bit manipulation instruction, change instruction of the index register and accumulator and sleep instruction are also added. The followings are explained here. CPU Programming Model (refer to Fig. 28) Addressing Mode Accumulator and Memory Manipulation Instruction (refer to Table 11) New Instruction Index Register and Stack Manipulation Instruction (refer to Table 12) Jump and Branch Instruction (refer to Table 13) Condition Code Register Manipulation (refer to Table 14) Op Code Map (refer to Table 15) · Programming Modal Fig. 28 depicts the HD6303Y programming model. The double accumulator D consists of accumulator A and B, so when using the accumulator D, the contents of A and Bare destroyed. · CPU Addr-ing Mode The HD6303Y provides 7 addressing modes. The addressing mode is determined by an instruction type and code. Tables 11 through 15 show addressing modes of each instruction with the execution limes counted by the machine cycle. When the clock frequency is 4MHz, the machine cycle time becomes microseconds directly. Accumulator IACCXI Addressing Only an accumulator is addressed and the accumulator A or B is selected. This is a one-byte instruction. Immediate Addr-lng This addressing locates a data in the second byte of an instruction. However, LOS and LDX locate a data in the second and third byte exceptionally. This addressing is a 2 or 3-byte instruction. Direct Addressing In this addressing mode, the second byte ofan instruction shows , . ·I lrtdf>1 ........ IXI I.. ... ·I 5'11dilloin·l5"1 I" "" ·I .....,_ Coun1er IPCI 1 · -._..·. -... Coo··"" COdo ,* ... ICCRI Qlrry/lor,_ fr- MSa ............. ~c..rvtFroma11JI Figure 28 CPU Programming Model the address where a data is stored. 256 bytes ($0 through $255) can be addressed directly. Execution times can be reduced by storing data in this area so it is recommended to make it RAM for users' data area in configurating a system. This is a 2-byte instruction, while 3 byte with regard to AIM, OIM, EIM and TIM. Extended AddrHsing In this mode, the second byte shows the upper 8 bit of the data stored address and the third byte the lower 8 bit. This indicates the absolute address of 3 byte instruction in the memory. Indexed Addressing The second byte of an instruction and the lower 8 bit of the index register are added in this mode. As for AIM, OIM, EIM and TIM, the third byte of an instruction and the lower 8 bits of the index register are added. This carry is added to the upper 8 bit of the index register and the result is used for addressing the memory. The modified address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte instruction except AIM, OIM, EIM and TIM (3-byte instruction). Implied Addressing An instruction itself specifies the address. This is, the instruction addresses a stack pointer, index register, etc. This is a one-byte instruction. Relative Addressing The second byte of an instruction and the lower 8 bits of the pro- gram counter are added. The carry or borrow is added to the upper 8 bit. So addressing from - 126 to + 129 byte of the current instruc- tion is enabled. This is a 2-byte instruction. (Note) CLI, SE! Instructions and Interrupt Operation When accepting the IRQ at a preset timing with CL! and SE! instructions, more than 2 cycles are necessary between the CL! and SEI instructions. For example, the following program (a)(b) don't accept the !RQ but (c) accepts it. CLI CLI CLI NOP SEI NOP NOP SEl SEI (a) (b) (c) The same thing can be said to the TAP instruction instead of the CL! and SE! instructions. 254 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 11 Accumulator, Memory Manipulation Instructions Operattons Add Add Double Add Accumul·tors Add With C.ry ANO litT"t Cloor Compare Compere Accumulators Complement, 1's Complenwnt, 2's (N. . .t e l Oecimel Adjust. A Decrement Exclusiw OR Increment LAccumuletor ~Double Accumuietor Multiply UnligMd OR, lnclusiva ..... Dot· Pull Data R....,.Left RouteAilht Mnemonic ADDA ADDB ADDO ABA ADCA ADCB ANDA ANOB BIT A BIT B CLR CLRA CLRB CMPA CMPB CBA COM CDMA COMB NEG NEGA NEG8 OAA DEC DECA DECB EDRA EORB INC INCA INC& LDAA LOAB LOO MUL DRAA ORAB PSHA PSHB PULA PULB AOL ROLA ROLB ROA RORA RORB Addressing Modes ,......... Condition CocA IMMEO DIRECT INDEX EXTEND IMPLIED Boolean/ Arithmetic Operetion 5 4 32 10 - - - - - OP # OP # OP # OP # OP # H I NZ vc . 88 2 2 9B 3 2 AB 4 2 BB 4 3 A+M-A I . CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+M-B I . . CJ 3 3 03 4 2 EJ 5 2 FJ 5 3 A:B+M:M+1-A: B . 18 1 1 A+ 8-A I . B9 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-A I . C9 2 2 09 3 2 E9 4 2 F9 4 3 a+M+c-a I . . . 84 2 2 94 3 2 A4 4 2 84 4 3 A·M-A .. . C4 2 2 04 3 2 E4 4 2 F4 4 3 B·M-B . . . 85 2 2 9S 3 2 AS 4 2 BS 4 3 . . . cs 2 2 OS 3 2 ES 4 2 FS 4 3 .. 6F s 2 7F s 3 A·M B·M 00-M . . 4F 1 1 00-A . . Sf 1 1 00- B . . 81 2 2 91 3 2 A1 4 2 81 4 3 . . C1 '2 2 01 3 2 E1 4 2 F1 4 3 A-M B-M I I I I I I II I I I I I I I I I I I I I I I I I IR I IR I IR I IR R s RR R s RR Rs RR II II II II . 11 1 1 A-B ..· 63 6 2 73 6 3 M-M .. 43 1 1 A-A . . 53 1 1 a-a . . 60 6 2 70 6 3 00-M-M .. 40 1 1 00-A-A . 50 1 1 00-B-B ..· 19 2 1 Converts binttry Mid of BCD chefacters into BCD tormM . BA 6 2 7A 6 3 M-1-M · 4A 1 1 A-1-A · .·· .· 88 2 2 98 3 2 AB 4 2 BB SA 1 1 B - 1 -B 3 A@M-A . .· · CB 2 2 08 3 2 Ea 4 2 F8 4 3 B@M- 8 . · 6C 6 2 JC 6 3 M+1-M ..· "' . 4C 1 1 A+ 1 -A . . SC 1 1 I+ 1- 8 · .. . 86 2 2 96 3 2 A6 4 2 86 3 M-A . . . C6 2 2 06 3 2 E6 4 2 F6 4 3 M-8 · . · cc 3 3 DC 4 2 EC 5 2 FC 5 3 M + 1-1.M- A I I I I I I Rs I I Rs I I Rs I I {j) ~' I I ·1: <% I I @ (J, I I I II I I @. I I Iii) · I I @· I IA I IR I I I I <I'. I I IS· · I IR I IR I IR . . · . 30 7 1 AxB-A:B · . . 8A 2 2 9A 3 2 AA 4 2 BA 3 A+M-A · . . CA 2 2 DA 3 2 EA 4 2 FA 4 3 B+M- B · ...... 36 1 A--.s·-1-T · ...... 37 1 8 - -·SP - 1 - sP · . . · . 32 3 1 SP+ 1-SP.Mms>-A · .. · ..· 33 3 1 sP+ 1-sP.--a :j .... l.iJ4i 69 6 2 79 6 3 49 1 1 · . 59 1 1 · c I IIIII ~ b7 lO · . "'rr 66 6 2 76 6 3 · . ,.. 46 1 1 =11.aO<f I I I I I I I j;J I C b1 1:10 .. 56 1 1 · ® I I R· I IR I I (l; I I I tli I I I I I ~rr I I I I I '.t, I (Nolll) Condition Code R19i111tr will be expl1ined in Note of Table 14. (continued) ®HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 255 T1ble 11 Aoaumul1tor, Memory M1nlpul1tlon ln1tructlon1 Cllllrlllo·· 1111111.111 Arlth-11 Doulilllhllt Liil, Arllhnw111 "'"11111111 Arllh-11 ......, lhlfl llllhl -·Double 111111 """' LotlCll Accurnulltor ...,. Doublt Acoumu..tor Subtrect DoullleSubtrlCI Subtrec:t Acc:umuletort SubtrlCI With C.rry Trensf.; Accumulltors Tiit Zero Of Minus Andlmmodiota OAlmmodim EOAlmmodiota Tntlmmodiota M-11 AIL AILA AILI AILO AIR AlllA Allll Liii LlfllA Llflll LIAO STAA STAI STD SUIA SUH SUBO SBA SICA SBCB TAB TBA TST TSTA TST8 AIM OIM EIM TIM IMMIO Addlllti"I Modll OllllCT INOIX IXTINO IMl'l.110 ...... , Ari1hnw11t1 Clper11ion C..nlfl!l!lilolntlCf odi I 4 3 a10 OP - II OP * II 0' * II 0' - OI' - II I NI Vc · · .... ,, , "I - ··"· ' · 2 71 · 3 · ·· I :~· I I I; I I I !I I I !!!] I '?! I al · · ill t.-o OI I I ·'7 I AO .., · I I .' ,, :1~ · ·~ 17 · 2 '7 41 I 17 I ··· ··· I I I I I I I I 14 · 2 74 · 3 · · !I I I ,44 , "I - 114 · · :~ I ' · II I I A I I I , , - f'9 .. 04 " ~· 17 3 2 A7 2 17 4 3 · " . D7 3 2 E7 4 2 F7 4 3 ··o..t !B!ZIBI AO 17 IO A~M a~M I ··I I Ao ··I I DD 4 2 ED 5 2 FD 5 3 A~M B-M+1 ·· I I A o 80 2 2 90 3 2 AO 4 2 80 4 3 a> 2 2 DO 3 2 EO 4 2 FO 4 3 83 3 3 93 4 2 A3 5 2 83 5 3 A-M ... A 8 -M ~a A:8-M:M+l~A:8 ·· I I I I ··I I I I ··I I I I 10 1 1 A-B~ A 82 2 2 92 3 2 A2 4 2 82 · 3 A-M-C~A C2 2 2 02 3 2 E2 ' 2 F2 · 3 16 ,1 I 8-M-c~8 A~8 17 1 8~ A , , eo 4 2 70 4 3 4D M-00 A -00 71 e 3 61 7 3 72 e 3 62 7 3 5D 1 1 8 -00 M·IMM-M M+IMM-M 75 6 3 65 7 3 M®IMM-M 78 4 3 68 5 3 M·IMM ..· · I I I I ·· I I I I I I I I ··I I Ao ..· · I I A o ·· I I AR I I RR ·· I I R R ·· I I fll · ·· I I A I ·· I I R · ·· I I R I CN01a) Condition Code Register will be explained in Nola of Table 14. 256 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · Addltlon·I Instruction In addition to the HD6801 instruction set, the HD6303Y pre- pues the following new instructions. AIM . . . . . . . . . . . (MHIMM) - (M) Executes "AND" operation to immediate dats and the memory contents and stores its result in the memory. OIM . . . . . . . . . . . (M)+ (IMM) - (M) Executell "OR" operation to immediate dats and the memo- ry contents and stores its result in the memory. EIM . . . . . . . . . . . (M) ffi (IMM) - (M) Executes "EOR" operation to immediate dats and the memory contents and stores its result in the memory. TIM . . . . . . . . . . . (MHIMM) Executes "AND" operation to immediate dats and changes the relative flag of the condition code register. These are the 3-byte instructions; the first byte is op code, the second immediate dats and the third address modifier. XGDX . . . . . . . . . (ACCD)-(IX) Exchanges the contents of accumulator and the index register. SLP Goes to the sleep mode. Refer to "LOW POWER DISSIPATION MODE" for more detsils of the sleep mode. Table 12 Index Register, Stack Manipulation Instructions Pointw Operetion1 Compore I - · R19 --···-Reg O.Crement Steck flntr Increment Inell· Ree Increment Steck Pntr L-1-aReg Loed Stack Pntr Store Inda· A.. -Store SUiek Pntr lnde111 A...... Stack Pntr S1eck Pntr - Ind.. A11 PuthO.U Pull °""' Exch- Mnemonic CPX DEX DES INX INS LOX LDS STX STS TXS TSX ABX PSHX PULX XGDX Addressing MNn -·/ - · · · - · IMMED. DIRECT INDEX EXTEND IMPLIED OP OP - OP - # OP - OP Arithnwtic O..retion ac 3 3 9C 4 2 AC 5 2 BC 5 3 X-MoM+1 09 1 1 X-1- X 34 1 I SP-1-sP OB 1 I x + 1- x 31 I I sP+1-sP CE 3 3 DE 4 2 EE 5 2 FE 5 3 M- XH, (M+ 1),,. X1,. BE 3 3 9E 4 2 AE 5 2 BE 5 3 M- sPH. IM+ 11- sPL DF 4 2 EF 5 2 FF 5 3 9F 4 2 AF 5 2 BF 5 3 XH - M. XL - IM+ 11 S,H .... M,$PL -CM+11 35 I I x-1-sP 30 I 1 sP+1-X 3A 1 1 B + x-x 3C 5 I XL - M,p. sP - I - SP XH- M,p, sP-1- SP 3B 4 1 sP + 1 - sP, M,p- XH sP + 1-sP.M,p-XL IB 2 I ACCD··IX Condition Codi . . . .i. . . . 5 4 3 2 10 H I Nz v c ..l I I I ..· I · · .. . · · · ... .I · .. ..· · . · · <l! I R . · · (f) I R . · · ".t I R . . · 'f I R ... ..· ...........· . . · · · · .... · · · · · · · · INotel Condition Code Register will be expleined in Note of Tabla 14. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 257 T1bl1 13 Jump, Br1noh lnatruct!on - ....,... Modtl CltilrllloOI '"""""''-' IPlnell NIWlf 1r11111h If Clrrv ci.r lrtllllh If C.ry Ill lr11111h II · Zero M-niCI lllA lllN ICC IOI llQ - ,, · · !11111.ATM ClllllCT INCllX IXTINCI IMPL!lll QI' - 0' OP * II 0' - 0, - 20 3 2! 3 14 3 " ~ 27 3 lllAChTlll NoM Nont C·O e ·.! 1·1 lr11111h II Ill Ztrt IOI IC 3 lrenllll II > Zero l·enllll 11 Hllltor lrtneh tic Zero IOT 21 3 IHI ILi ' n 2' 3 ......lreneh II LoMr Or ILi 23 3 N(f)V·O Z +IN® VI ·O C+Z·O Z+ IN~VI · 1 C+Z·I lrellllh II< Zero ILT 20 3 N@V· 1 lrenoh II Mlnua IMI 21 3 N· 1 lreneh II Not lqual Ztr'I INI 211 3 Z·O lrenoh 110..rllow c.... IVC 211 3 2 V·O lrenelllf<>wrl-lot IVS .... Bnnell II Plu1 IPL lnnellTo..-11ne Jump JM' JumpTo-outlne JSR No ()porotlofl NOP 211 3 2 2A 3 2 10 5 2 · , IE 3 2 7E 3 3 IO I 2 AO 5 2 10 3 01 I V· I N·O Ad...... ,,... Cntr. Only Return From lnterNPt RTI Aetum From SofMM't Interrupt --·'""Wah for Interrupt· RTS SWI WAI ~ 38 10 I 39 s 1 3F 12 I 3E 9 I IA 4 I (Notel ·WAI puts R/W high; Addr111 Bus - to FFFF; Dau Bus - to the thrll · - · Condition Codi Rlgister will be explained in Note of Table 14. , c.11:.~c;- I 43I 0 H · · · · · · · · · I · · · · · · · · · N ·· · · ·· · · · I · ··· · · · · · ········v··········e · · · · · · · · · · ·· · · ·· · · · · ·· · · ·· · · · · · · ·· · · · · · · ·· · · · · · · · · ·· ·· ·· · · · · · · ·· · · -(Ii- .. · · · ··· · s···· · @ ·· ··· · · · 258 @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ()ptrMions c._ Clt·v C'9er Interrupt Mask C-0-f- Set car,. SM lnterruPt Mesk SetO-fAccumulllO< A - CCR CCFI ... Accumu..UM' A Table 14 Condition Code Register Manipulation Instructions Mnemonic CLC CLI CLV SEC SEI SEV TAP TPA ~dd......, _ IMPLIED - OP # oc 1 1 OE 1 1 OA 1 1 00 1 1 OF 1 1 , OB 1 1 06 1 I 07 1 1 Boolean ()ptrahon o-c 0-1 o-v i-c 1-1 i-v A- CCR CCR-A Condition Code R90i11er ......H5 . - - .....R4sI @ ......N·3 .......z2-.....Rvs1- 0 . . c R -...s LEGEND OP Operation Code CHexadecimal! Number of MCU Cycles MSP Contents of memory location pointed by Stack Pointer # Number of Program Bytes + Arithmetic Plus Arithmetic Minus · Boolean AND + Boolean Inclusive OR e Boolean Exclusive OR M Complement of M Trensfer into 0 Bit= Zero 00 Byte = Zero CONDITION CODE SYMBOLS H Half-carry from bit 3 to bit 4 I Interrupt mask N Negotive Csign bit) Z Zero Cbvtel V Overflow, 2's complement C Carry/Borrow from/to bit 7 R Reset Always S Set Always f Set if true after test or cle· · Not Affected (Note) Condition Code Register Notes: (Bit set if test is true and cleared otherwise) (i) (Bit VI Test: Result= 10000000? @ IBit Cl Test: Result~ 00000000? @ CBit Cl Test: BCD Character of hi!li-order byte greater than 10? CNot cleared ii previously set) @ CBit VI ® CBit V) ® (Bit V) Test: Operand= 10000000 prior to execution? Test: Operand = 01111111 prior to execution? Test: Set equal to N<t C = 1 after the execution of instructions (f) IBit NI Test: Result less than zero? !Bit 15=1 I ® CAii Bitl Load Condition Code Register from Stack. (9) (Bit I) Set when interrupt occurs. If previously set. a Non-Maskable Interrupt is required to exit the wait state. @) (All Bid Set according to the contents of Accumulator A. @ CBit Cl Result of Multiplication Bit 7=1? IACCBI Table 15 OP-Code Map ~ .-.-- OP CODE 0 0001 0 I SBA 0010 2 BRA -0001 01 NOP CeA BRN ..-- DOIO 2 ~ .....----- BHI DOii s .....----- Bl.S ~ l l l l l ACC ACC IND A B ACCA or SP ACCB or X R IMM DIR INO EXT IMM DIR j INO EXT DOii 3 TSX INS PULA --01DO OIOI 0110 0111 4 s 6 7 NEG AIM OIM I I I I I I 1000 1D01 1010 1011 11DO 1m 1110 1111 I J 9 j A j B cj_oJEJF SUB CMP sec PULB COM SUBD ADDO 0 I 2 3 DIDO 4 LSRO .....----- ecc DES LSR AND 4 OIOI s ASLD .....----- ecs TXS EIM 0110 I TAP TAB BNE PSHA - - RJO_R BIT s LOA 6 0111 7 TPA TeA BEO PSHB ASA /j_ STA ~"! STA 7 1000 I INX 1001 9 DEX 1010 A CLV 1011 B SEV llDO c CLC XGDX ave OM BVS SLP BPL ..--AeA BMI BGE PULX RTS ABX RTI PSHX -- ASL ROL DEC INC TIM EOA · ADC 9 ORA A AOO B CPX LDD c 1101 D SEC .....----- BLT MUL TST BSR J JSR ,.,....--1 STD D 1110 E Cll 1111 F SEI 0 ..,...,....-.-..-.-,.-,. BGT Bl.E WAI SWI ,._...,...-"~ CLR JMP I 2 s 4 s I 7 LOS ..--1 · I 9 I STS A I a LOX ~ c I D I STX E I F E F UNDEFINED OP CODE C2::J 'Only - h instructions of AIM, DIM, EIM, TIM @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 259 · CPU OPERATION · CPU lnatructlon Flow When operating, the CPU fetches an instrutioo from a mel!!Q!l and executes the required function. This sequence starts with RES" cancel and repeats itself limitlessly if not affected by a special instruction or ·a control signal. ~ lQ1_WAI and SLP instructions change this operation, while NMI, IRQ., IRQ,,, IRQ,, IIAtT and m Y control it. Fig. 29 gives the CPU mode transition and Fig. 30 the CPU system flow chart. Table 16 shows CPU o~rating states and port states. · Operation et heh Instruction Cycle Table 17 shows the operation at each instructioo cycle. By the pipeline control of the HD6303Y, MULT, PUL, DAA and XGDX instnictions, etc. prefetch the next instniction. So attentioo is necessary to the counting of the instruction cycles because it is different from the usual ooe-from op code fetch to the next instnictioo op code. Figure 29 CPU Operation Mode Transition Table 16 CPU Operation State and Port, Bus, Control Signal State Port Ao-A7 Port2 Do-D1 Aa-A15 Port5 Port6 Control Signal Reset H T T H T . T , ·t llD,Wl!,RiW;LIR=H,BA=L ·2 lm,Wll. R/W = T,tor. BA= H 0 3 Epm goes to high Impedance aUlte. STBY'3 T T T T T T T HALT T Keep T T Keep ..Keep Sleep H Keep T H ..Keep Keep 260 ~HITACHI Httaelll America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I ~- ::. )> 3 'r!;l · ~"" ~ 0 0 cQ.;i@· (I) ~ :I ~ :::J - l5 rJJ C') ~ :I '- 5l !" 0 )> "~ ' ~ .,. a ..$... ~ "g' I\.) en ~~~~~~G PC·1 PC·1 STACK (Note) 1. The program oequence will coma to the RES start from any piece of the flow during RES. When STBY=O, the sequence will go into the standby mode regardless of the CPU condition. 2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more details of interrupts. N :c Figure 30 HD6303Y System Flow Chart w m c -0w< Address Mode Instructions Cycles Cycle # Address Bus EXTEND JMP 3 ADC ADD TST AND BIT CMP EOR 4 LOA ORA SBC SUB STA 4 ADDO CPX LOO LOS LOX 5 SUBD STD STS STX 5 JSR 6 ASL ASR COM DEC INC LSR 6 NEG ROL ROR CLR 5 1 Op Code Address+ 1 2 Op Code Address+2 3 Jump Address 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Destination Address 4 Op Code Address+3 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 Address of Operand+ 1 5 Op Code Address+3 1 Op Code Address+ 1 2 Op Code Address+ 2 3 Destination Address 4 D!lstination Address+ 1 5 Op Code Address+ 3 1 Op Code Address+ 1 2 Op Code Address+2 3 FFFF 4 Staci< Pointer 5 Stack Pointer - 1 6 Jump Address 1 Op Code Address+ 1 2 Op Code Address+2 3 Address of Operand 4 FFFF 5 Address of Operand 6 Op Coc!e Address+3 1 Op C.ode Address+! 2 Op Code Address+ 2 3 Address of .Operand 4 Address of Operand 5 Op Code Adcjress + 3 R/W RD 1 -u- 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 o- 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 T 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 Data Bus 1 Jump Address (MSB) 1 Jump Address (LSB) 0 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data 0 Next Op Code 1 Destination Address (M-S-Bl 1 Destination Address (LSB) 1 Accumulator Data 0 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data (MSB) 1 Operand Data (LSB) 0 Next Op Code 1 Destination Address (MSB) 1 Destination Address (LSB) 1 Register Data (MSB) 1 Register Data (LSB) 0 Next Op Code 1 Jump Address (MSB) 1 Jump Address (LSB) 1 Restart Address (LSB) 1 Return Address (LSB) 1 Return Address (MSB) 0 First Subroutine Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSBJ 1 Operand Data 1 Restart Address (LSB) 1 New Operand Data 0 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data 1 00 0 Next Op Code (Continued) 262 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Address Mode & Cycles Cycle Instructions ii Address Bus IMPLIED ABA ABX ASL ASLD ASR CBA CLC cu CLR CLV COM DEC DES OEX INC INS INX LSR LSRD ROL ROR NOP SBA SEC SEI SEV TAB TAP TBA TPA TST TSX TXS DAA XGDX PULA PULB PSHA PSHB PULX PSHX RTS MUL 1 Op Code Address+ 1 1 2 1 Op Code Address+ 1 2 FFFF 1 Op Code Address+ 1 3 2 FFFF 3 Stack Pointer + 1 1 Op Code Address+ 1 4 2 FFFF 3 Stack Pointer 4 Op Code Address+ 1 1 Op Code Address+ 1 4 2 FFFF 3 Stack Pointer + 1 4 Stack Pointer + 2 1 -op-Code Address+1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer - 1 5 Op Code Address+ 1 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer+ 1 4 Stack Pointer + 2 5 Return Address 1 Op Code Address+ 1 2 FFFF 3 FFFF 7 4 FFFF 5 FFFF 6 FFFF 7 FFFF R/W Data Bus 1 0 1 0 Next Op Code 1 0 1 0 Next Op Code 1 1 1 1 Restart Address (LSB) 1 0 1 0 Next Op Code 1 1 1 1 Restart Address (LSB) 1 0 1 1 Data from Stack 1 0 1 1 Next Op Code 1 1 1 1 Restart Address (LSB) 0 1 0 1 Accumulator Data 1 0 1 0 Next Op Code 1 0 1 0 Next Op Code 1 1 1 1 Restart Address (LSB) 1 0 1 1 Data from Stack (MSB) 1 0 1 1 Data from Stack (LSB) 1 0 1 1 Next Op Code 1 1 1 1 Restart Address (LSB) 0 1 0 1 Index Register (LSB) 0 1 0 1 Index Register (MSB) 1 0 1 0 Next Op Code 1 0 1 1 Next Op Code 1 1 1 1 Restart Address (LSB) 1 0 1 1 Return Address (MSB) 1 0 1 1 Return Address (LSB) 1 0 1 0 First Op Code of Return Routine 1 0 1 0 Next Op Code 1 1 1 1 Restart Address (LSB) 1 1 1 1 Restart Address (LSB) 1 1 1 1 Restart Address (LSB) 1 1 1 1 Restart Address (LSB) 1 1 1 1 Restart Address (LSB) 1 1 1 1 Restart Address (LSB) (Cont1.nued) @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 263 Table 17 Cycle-by-Cycle Operation Address Mode 8i Cycles Cycle Instructions # Address Bus R/W IMMEDIATE ADC ADD AND BIT CMP EOR LOA ORA SBC SUB ADDO CPX LOO LOS LOX SUBD 1 Op Code Address+1 2 Op Code Address+ 2 2 1 Op Code Address+ 1 3 2 Op Code Address+ 2 3 Op Code Address+3 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 DIRECT ADC AND CMP LOA SBC STA ADD BIT EOR ORA SUB ADDO CPX LOO LOS LOX SUBD STD STS STX JSR TIM AIM EIM OIM 1 Op Code Address+ 1 2 Address of Operand 3 3 Op Code Address+2 1 Op Code Address+ 1 3 2 Destination Address 3 Op Code Address+2 1 Op Code Address+ 1 4 2 Address of Operand 3 ·Address of Operand+ 1 4 Op Code Address+2 1 Op Code Address+ 1 4 2 Destination Address 3 Destination Address+ 1 4 Op Code Address+2 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer- 1 5 Jump Address 1 Op Code Address+ 1 4 2 Op Code Address+2 3 Address of Operand 4 Op Code Address+3 1 Op Code Address+ 1 2 Op Code Address+2 6 3 Address of Operand 4 FFFF 5 Address of Operand 6 Op Code Address+3 1 0 1 1 0. 1 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 t 0 1 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 1 0 1 Data Bus 1 Operand Data 0 Next Op Code 1 Operand Data (MSB) 1 Operand Data (LSBI 0 Next Op Code 1 Address of Operand (LSB) 1 Operand Data 0 Next Op Code 1 Destination Address 1 Accumulator Data 0 Next Op Code 1 Address of Operand (LSB) 1 Operand Data (MSB) 1 Operand Data (LSB) 0 Next Op Code 1 Destination Address {LSB) 1 Register Data (MSBI 1 Register Data (LSB) 0 Next Op Code 1 Jump Address (LSBI 1 Restart Address (LSB) 1 Return Address {LSB) 1 Return Address {MSB) 0 First Subroutine Op Code 1 Immediate Data 1 Address of Operand (LSB) 1 Operand Data 0 Next Op Code 1 Immediate Data 1 Address of Operand {LSBI 1 Operand Data 1 Restart Address (LSB) 1 New Operand Data 0 Next Op Code (Continued) 264 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Adclrm Mode i Instruction· INDEXED JMP ADC AND CMP LOA SBC TST STA ADD BIT EOR ORA SUB ADDO CPX LOO LOS LOX SUBD STD STS STX JSR ASL ASR COM DlC INC LSR NEG ROL ROR TIM CLR AIM EIM OIM Addrm llus 1 lrp Code Addr...+ 1 3 2 FFFF 3 JumpAddr... 1 Op Code Addr...+ 1 2 FFFF 4 3 IX+Offsat 4 Op Code Addr...+2 1 Op Code Addrm+1 4 2 FFFF 3 IX+Offset 4 Op Code Addr...+2 1 OP C:odaAddr...+1 2 FFFF 5 3 IX+Offsat 4 IX+Offsat+ 1 5 Op Code Address+ 2 1 Op Code Addr...+ 1 2 FFFF 5 3 IX+Otfsat 4 IX +Offset+ 1 5 Op Coda Addr...+2 1 Op Code Addr...+1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer- 1 5 IX+Offsat 1 Op Code Addr...+ 1 2 FFFF 8 3 IX+Offsat 4 FFFF 5 IX+Offset 8 OP Code Address+ 2 1 Op Code Addr...+1 2 Op Code Addr...+2 5 3 FFFF 4 IX+Otfsat 5 Op Code Address+ 3 1 Op Code Addr...+1 2 FFFF 5 3 IX+Offsat 4 IX+Offsat 5 Op Coda Addr...+2 1 Op Coda Addr...+ 1 2 Op Coda Addr...+2 3 FFFF 7 4 IX+Offsat 5 FFFF 8 IX+Offsat 7 Op Code Addr...+3 Data Bus 1 0 1 1 Offsat 1 1 1 1 Restar1 Addr... (LSB) 1 0 1 0 First Op Code of Jump Aautine 1 0 1 1 Offsat 1 1 1 1 Restar1 Addrns (LSB) 1 0 1 1 Operand Data 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restar1 Addrm (LSB) 0 1 0 1 Accumulator Data 1 0 1 0 Next Op Coda 1 0 1 1 Offset 1 1 1 1 RHtar1 Addr... (LSB) 1 0 1 1 Operand Data (MSBI 1 0 1 1 Operand Data (LSB) 1 0 1 0 Next Op Coda 1 0 1 1 Offset 1 1 1 1 Rastar1 Addr... (LSBI 0 1 0 1 Register Data (MSBI 0 1 0 1 Register Data (LSB) 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restart Addr... (LSBI 0 1 0 1 Return Addr... (LSB) 0 1 0 1 Return Addr... (MSB) 1 0 1 0 First Subroutine Op Code 1 0 1 1 Offset 1 1 1 1 RHtar1 Addr... (LSBI 1 0 1 1 Operand Data 1 1 1 1 RHtar1 Addr... (LSB) 0 1 0 1 New Operand Data 1 0 1 0 Next Op Coda 1 0 1 1 Immediate Data 1 0 1 1 .. Offset 1 1 1 1 RHtart Addr... ILSBI 1 0 1 1 Operand Data 1 0 1 0 Next Op Code 1 0 1 1 Offset 1 1 1 1 Restart Addrns 'ILSBI 1 0 1 1 Operand Data 0 1 0 1 00 1 0 1 0 Next Op Coda 1 0 1 1 Immediate Data 1 0 1 1 Offset 1 1 1 1 RHtart Addr... (LSBI 1 0 1 1 Operand Data 1 1 1 1 Rntart Addr... (LSBI 0 1 0 1 N- Operand Data 1 0 1 0 Next Op Coda (Continued) .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 265 Address Modill · Instructions IMPLIED WAI RTI SWI SLP Cycles Cycle # Address Bus 1 Op Code Address+ 1 2 FFFF 3 Stack Pointer 4 Stack Pointer - 1 9 5 Stack Pointer - 2 6 Stack Pointer - 3 7 Stack Pointer-4 6 Stack Pointer -5 9 Stack Pointer - 6 1 Op Code Address+ 1 2 FFFF 3 Stack Pointer+ 1 4 Stack Pointer+ 2 10 5 Stack Pointer+ 3 6 Stack Pointer +4 7 Stack Pointer+ 5 8 Stack Pointer+ 6 9 Stack Pointer+ 7 10 Return Address 1 Op Code Addr~s+ 1 2 FFFF 3 Stack Pointer 4 Stack Pointer - 1 5 Stack Pointer - 2 12 6 Stack Pointer - 3 7 Stack. Pointer -4 6 Stack Pointer -5 9 Stack Poi111ar - 6 10 Vector Address FFFA 11 Vector Address FFFB 12 Address of SWI Routine t Op Code Address+ 1 2 FFFF 1 4 Sleep j 3 FFFF 4 Op Code Address+ 1 R/W Dete Bus 1 0 l 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 .o 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 I I I 1 1 1 1 0 1 1 Next Op Code 1 Restart Address (LSI) 1 Return Address (LSI) 1 Return Address (MSll 1 Index Register (LSI) 1 Index Register (MSll 1 Accu.mulator A 1 Accumulator B 1 Conditional Code Register 1 Next Op ~ode 1 Restart Address (LSI) 1 Conditional Code Register 1 Accumulator B 1 Accumulator A 1 Index Register (MSB) 1 Index Register (LSB) 1 Return Address (MSI) 1 Return Address (LSBI 0 First Op Code of Return Routine 1 Next Op Code 1 Restart Address (LSll 1 Return Address (LSI) 1 Return Address (MSI) 1 Index Register (LSI) 1 Index Register (MSB) 1 Accumulator A 1 Accumulator B 1 Conditional Code Register 1 Address of SWI Routine (MSB) 1 Address of SW1 Routine (LSB) 0 First Op Code of SWl Routine 1 Next Op Code 1 Restart Address (LSll I 1 1 Restart Address (LSll 0 Next Op Code RELATIVE ICC BCS BEQ BGE BGT BHI BLE BLS BLT BMT BNE BPL BRA BRN ave BVS BSR 1 Op Code Address+ 1 1 0 1 1 Branch Offset 3 2 3 jFFFF Branch Address· .... ·Test="1" 1 Op Code Address+ 1.. ·Test="O" 1 1 0 1 1 1 Restart Address ILSB) First Op Code of Branch RoU!ine 0 Next Op Code 1 Op Code Address+ 1 2 FFFF 5 3 Stack Pointer 4 Stack Pointer - 1 5 Branch Address 1 0 1 1 Offset 1 1 1 1 Restart Address (LSll 0 1' 0 1 Return Address (LSB) 0 1 0 1 Return Address IMSBI 1 0 1 0 First Op Code of Subroutine 266 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · PRECAUTION TO THE BOARD DESIGN OF OSCILLA· TION CIRCUIT A1 1hown In Fig. 31, there Is a case thRI the cross talk dis· turbs the nurmui u1clllatiun If signal lines ure put near the usclllutlon circuit. When deslgninll u board, pay attention to this. Crystal und CL must be put as near the HD6303Y H possible. J J J J CL f ,j;i---XTAL r-l1-<1.....,--'-l1EXTAL mi::L H08303Y __,,.... Avoid 1lgn1I lln11 ,,,.- In thl11r11. e HD8303Y Do not use this kind of print board design. Figure 31 Precaution to the boad design of oscillation circuit (Top View) Figure 32 Example of Oscillation Circuits in Board Design · RECEIVE MARGIN OF THE SCI Receive margin of the SCI contained in the HD6303Y is shown in Table 18. Note: SCI= Serial Communication Interface H06303Y Table 18 Bit distortion tolerance (t-to) /to ±43.7% Character distortion tolerance (T-To) /To ±4.37% Ideal Waveform Real Waveform START 2 3 4 5 6 8 STOP I Sit length r--to-1 .4 . >----------Character length T0 - - - - - - - - - - e o l @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 267 HD6305X2,HD63A05X2,HD63B05X2- HD6305Y2,HD63A05Y2,HD63B05Y2 CMOS MPU (Micro Processing Unit} The HD6305X2 and the HD6305Y2 are CMOS 8-bit micro processing units which contains a CPU, a clock generator, RAM, 1/0 terminals, two timers, and a Serial Communication Interface (SCI). The memory space is expandable up to 16k bytes externally. The HD6305X2 and the HD6305Y2 provides the equivalent functions as the HD6305XO and the HD6305YO except for the number of I/O terminals. ·HARDWARE FEATURES · 8-bit based MPU · 128-bytes of RAM (HD6305X2), 256-bytes of RAM (HD6305Y2) ·A total of 31 terminals, including 24 I/O's, 7 inputs ·Two timers 8-bit timer with a 7-bit prescaler (programmable prescaler; event counter) 15-bit timer (multiplexed with the SCI clock divider) ·On-chip serial interface circuit (synchronized with clock) ·Six interrupts (two external, two timer, one serial and one software) ·Low power dissipation modes - Wait .... In this mode, the clock oscillator is on and the CPU halts but the timer/serial/interrupt function is operatable. - Stop .... In this mode, the clock stops but the RAM data, 1/0 status and registers are held. - Standby. . In this mode, the clock stops, the RAM data is held, and the other internal condition is reset. ·Minimum instruction cycle time HD6305X2/Y2 .... 1 µs (f = 1 MHz) - HD63A05X2/Y2 ... 0.67µs (f = 1.5 MHz) - HD63805X2/Y2 ... 0.5 µs (f = 2 MHz) ·Wide operating range Vee= 3 to 6V (f = 0.1 to 0.5 MHz) HD6305X2/Y2 ..... f=0.1to1 MHz (Vee=5V±10%) HD63A05X2/Y2 .... f = 0.1 to 1.5 MHz (Vee = 5V ± 10%) HD63B05X2/Y2 .... f = 0.1 to 2 MHz (Vee=5V± 10%) ·System development fully supported by an evaluation kit ·Compatibility with the HD6305XO and the HD6305YO except for external memory expansion and the number of 1/0 terminals. HD6305X2P, HD63A05X2P, HD63B05X2P, HD6305Y2P, HD63A05Y2P, HD63B05Y2P HD6305X2F, HD63A05X2F, HD63B05X2F, HD6305Y2F, HD63A05Y2F, HD63B05Y2F (FP-64) ·SOFTWARE FEATURES ·Similar to HD6800 ·Byte efficient instruction set ·Powerful bit manipulation instructions (Bit Set, Bit Clear, and Bit Test and Branch usable for all RAM bits and all 1/0 terminals) ·A variety of interrupt operations · lnde>< addressing mode useful for table processing ·A variety of conditional branch instructions ·Ten powerful addressing modes ·All addressing modes adaptable to RAM, and 1/0 instructions ·Three new instructions, STOP, WAIT and DAA, added to the HD6805 family instruction set 268 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · PIN ARRANGEMENT (Top Vl1wl · HDl301X2P, HDl3AOIX2P, HDl3BOIX2P HDl30IV2P, HDl3AOIV2P, HDl3BOIV2P ~ 0 At MTAL UTAL NUM TIMlll DATA1 DATA, DATA1 DATA1 DATAo DATAI DATAI DATA, A, I Ao II/GI/ A, ADll11 Ao ADff:11 A, ADll11 A, A, ···a····A·······,o C1/Ta C1/A1 c,1fl!: c, c, c, c, ADii" ADlh ADll1 ADii, ADll1 ADll1 ADllo ADll1 ADR 1 ADRt ADRo D, D1/IWT; D, Do D, D, D. Co Vee ~~~~~~~~ ·BLOCK DIAGRAM XTAL EXTAL · HDl301X21', HDl3AOIX21', HD83BOIX21' HD830IV21', HDl3AOIV21', HD83BOIV21' .~~ ,{ II C1/Tx AtW ADll11 ADll 11 ADll 11 4 ADll1 ADR1 ADAo ADA1 ADA2 ADRt ADRo o, TIMER Timer/ a Counter Timer Control Ao A, Port A A, .... 1/0 A, Terminals A..., A, .u<ii ~ii o·-·i·i. a: l!a:: s~ Part B 1/0 Terminals -~-.. ii rmtf:a·i:li: 0 Sl!a.g:: Accumulator A Index Register x Condition Code RegisterCCR CPU Stack Pointer SP Program Counter 6 "High" PCH Program Counter "Low" PCL CPU Control ALU Hus o-·~I·.ii a: Sl!a.g:: Serio! °"'"Regioto< Sario! Control Regi111< RAM· 0 HD6305X2; 128XB RAM HD6305V2; 256X8 RAM o, OJINT2 Ds o, Port D D, o, o, Input Terminals ADRn ADRu AOR11 ADR10 ADAs ADRa ADA1 ADAs ADA. ADA. ADA:. ADRa AOR 1 ADAo DATA, l>ATAo DATA, DATAo OATAa DATAa DATA, DATAo @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 269 ·ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee -0.3-+7.0 v Input Voltage Vin -0.3-Vee + 0.3 v Operating Temperature Topr 0-+10 ·c Storage Temperature Tng -55-+150 ·c (NOTE) These produc:ts have· prol8Ction circuit in their input terminals against high electrostatic voltege or high electric fields. Notwithstanding, be careful not to -ly any voltage higher than the abloluta maximum rating to th- high input impedance circuits. To assure normal operation, - recommended Vin· Vout; Vss ~(Vin or V0 utl ~Vee· · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee= 5.0V±10%, Vss = OV, Ta" 0- +70°C, unless otherwise noted.) Item Symbol Test Condition min typ max Unit Input "High" Voltage Input "Low" Voltage RES,ST8Y EXT AL Other Inputs All Inputs Output '1High" Voltage All Outputs Output "Low" Voltage All Outputs ViH V1L loH = -200jlA VoH loH = -10µA VoL loL= 1.6mA Vcc-0.5 - v~+o.3 Vccx0.7 - Vcc+o.3 v 2.0 - v~+o.3 -0.3 - 0.8 v ~ - - Vcc-0.7 - - v - - 0.55 v Input Leakage Current TIMER, INT, D1 -D7 ,ST8Y ll1d - - 1.0 µA Ao-A,,80-81, Vin = 0.5 - Vcc-0.5 Three-state Current C0 - C,, ADRo - ADR 13", llTS1I - DATA0-DATA7 ,E",R/W" Operating - Current Dissipation*" Wait Stop Ice f = 1MHz··· - Standby - Input Capacitance All Terminals Cin f = 1MHz, Vin= OV - - 1.0 µA 5 10 mA 2 5 mA 2 10 µA 2 10 µA - 12 pF · Only at standby ·· V1H min= Vcc-1.0V, V1 L max= O.BV, all output and RES terminal are open and penetrate current of input are not included. ···The value at f = xMHz is given by using. Ice (f =xMHzl =Ice (f = 1MHz) xx · AC CHARACTERISTICS (Vee= 5.0V±10%, Vss = OV, Ta· 0 - +70°C, unless oth-isa noted.I Item Symbol Test HD6305X2. HD6305Y2 HD63A05X2. HD63A05Y2 HD63805X2 HD63805Y2 Condition Unit min typ max min typ max min typ max Cycle Time lcvc - - - 1 10 0.666 10 0.5 10 /JS Enable Rise Time tEr - - 20 - - 20 - - 20 ns Enable Fall Time tEt - - 20 - - 20 - - 20 ns Enable Pulse Width("High" Level) PWEH 450 - - 300 - - 220 - - ns Enable Pulse Width("Low" Level) PWEL Address Delay Time tAo Fig. 1 450 - - - - 300 250 - - - 220 ·190 - - - ns 180 ns Address Hold Time tAH 40 - - 30 - - 20 - - n, Data Delay Time tow - - 200 - - 160 - - 120 ns Data Hold Time (Write) tHw - 40 - 30 - - 20 - - ns Data Set-up Time (Read) tosR 80 - - 60 - - 5o - - ns Data Hold Time (Read) tHR 0 - - 0 - - 0 - - ns 270 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · PORT TIMING (Vee= 5:0V±10%, Vss = ov. Ta= 0 - +70°C, unless oth-ise noted.) Item Port Data Set-up Time (Port A, B, C, DI Port Data Hold Time (Port A, B, C, DI Port Data Delay Time (Port A, B, C) Symbol tpos tpoH tpow Test HD6306X2, HD6305Y2 Condition min typ max 200 - - Fig. 2 200 - - Fig. 3, - - 300 HD63A05X2, H063A05Y2 min typ max 200 - - 200 - - - - 300 HD63B06X2, HD63805Y2 min typ max 200 - - 200 - - - - 300 Unit ns ns ns · CONTROL SIGNAL TIMING (Vee= 5.0V±10%, Vss = OV, Ta= 0 - +70°C, unless oth-ise noted.) Item illiTPulse Width INT2 Pulse Width RES Pulse Width Control Set-up Time Timer Pulse Width Oscillation Start Time (Crystall Reset Delay Time Symbol Test H06305X2, HD6306Y2 Condition min typ max HD63A06X2, HD63A05Y2 min typ max HD63B05X2, HD63B05Y2 min typ max Unit t1wL t1wL2 tRWL tcs tcyc +250 - tcyc +250 - 5 - Fig. 5 250 - - - tcyc +200 - - tcyc +200 - 5- - 250 - - tcvc +200 - - tcyc +200 -5- - 250 - - ns - ns - !eve - ns tTWL tosc tRHL tcyc +250 - - Fig.5, Fig.20* - - Fig. 19 80 - - tcyc +200 20 - - - 80 - - - tcvc +200 20 - - - 80 - - ns 20 ms - ms * CL = 22pF ±20%, R5 = 60f2 max. · SCI TIMING (Vee = 5.0V±10%, Vss= OV, Ta= o- +70°C, unless otherwise noted.) Item Clock Cycle , Data Output Delay Time Data Set-up Time Data Hold Time Symbol tscvc tTXD tsRX tHRX Test Condition Fig.6, Fig. 7 HD6305X2, H06305Y2 H063A05X2, H063A05V2. min typ max min typ max - - 1 32768 0.67 21845 - - 250 - - 250 - 200 - 200 - - 100 - - 100 - - HD83B06X2. H063B05Y2 min typ max Unit - 0.5 16384 µs - - 250 ns 200 - - ns 100 - - ns @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 271 ~---------tcyc----------.i E ' " " - - - P W e L _ ___.., 0.6V Ao-A13 R/W MPU Write DATAo - DATA7 2.4V 0.6V Address Valid tow MPU Read DATAo - DATA7 Figure 1 Bus Timing E Port A,B,C,D 2.0V Data O.SV Valid E \o.sv I i:=tpow Port A,B,C 2.4V Data 0.6V Valid Figure 2 Port Data Set-up and Hold Times (MPU Read) Figure 3 Port Data Delay Time (MPU Write) Interrupt Test E Address Bus Data Bus R/W PC0PC1 Op Operand lrr9'evant Code Op Code Data PCa- IX ACC CC -:~~or ~s~or First Inst. of . PC13 AddressAddress Interrupt Routtne Figure 4 Interrupt Sequence 272 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Vee Address Bus R/W Data Bus ~.-. ~ f--o~~~~---11-----fllllllllllll Figures Reset Timing Clock Output Cs/CK 0.6V tscvc _ _ _ _ __.., 0.6V 2.4V 0.6V Data Output C1/Tx Data Input Cs/Rx 2.4V 0.6V 0.8V tHRX ----~ 2.0V 0.8V Figure6 SCI Timing (Internal Clock) Cloe!-. input Cs/CK 0.8V tscyc 0.8V 2.0V 0.8V Data Output C1/TX Data Input Cs/Rx tHRX - - - - - i 2.0V 0.8V Figure7 SCI Timing(External Clock) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 273 TTL Lo9d (Port) 2.4kQ ~~r.:~I 0-~~-.~~--<.-~--tll-....... C· 90pF for DATA0 -DATA,, ADAo-ADA11 , E, A/'11 c · 40pF for Port A, Band C. 12kQ ·DatlBua(DATAo -DATA,) This TTL compatible three-state buffer can drive one 1TL load and 90pF. · Addreu Bua (ADR0 -ADR13) Each terminal is TTL compatible and can drive one TTL load and 90pF. ·PortsA,B,C IA0 -A7,Bo -87,Co -C,) These 24 terminals consist of three 8-bit I/0 ports (A, B, C). Each of them can be used as an input or output terminal on a bit through program control of the data direction register. For details, refer to "1/0 PORTS." [NOTES] 1. The load capacitance includes stary capacitance ceulld by the probe, ate. 2. All diodes are 152074@. Figure 8 Test Load ·Port D ID1 - D,) These seven input-only terminals are TTL or CMOS com- patible. Of the port D's, D6 is also used as INT2. If n. is used as a port, the iN'f2 interrupt mask bit of the miscellane- ous register must be set to "1" to prevent an 002 interrupt from being accidentally accepted. · DESCRIPTION OF TERMINAL FUNCTIONS The input and output signals of the MPU are described here. ·Vcc.Vss Voltage is applied to the MPU through these two terminals. Vee is 5.0V ± 10%, while Vss is grounded. ·INT, INT2 External interrupt request inputs to the MPU. For details, refer to "INTERRUPT". The INT2 terminal is also used as the port n. terminal. · XTAL, EXTAL These terminals provide input to the on-chip clock circuit. A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic filter is connected to the terminal. Refer to "INTERNAL OSCILLATOR" for using these input terminals. ·STBY This terminal is used to place the MPU into the standby mode. With STBY at "Low" level, the oscillation stops and the internal condition is reset. For details, refer to "Standby Mode." The terminals described in the following are I/O pins for serial communication interface (SCI). They are also used as ports Cs, C6 and C7 · For details, refer to "SERIAL COMMUNICATION INTERFACE." ·CK (Cs) Used to input or output clocks for serial operation. ·Rx (C6) Used to receive serial data. ·TX (07) Used to transmit serial data. ·TIMER This is an input terminal for event counter. Refer to "TIMER" for details. ·RES Used to reset the MPU. Refer to "RESET'' for details. ·NUM This tenninal is not for user application. This tenninal should be connected to VSS· ·Enable (E) This output terminal supplies E clock. Output is a single- phase, TTL compatible and 1/4 crystal oscillation frequency or l /4 external clock frequency. It can drive one TTL load and a 90 pF condenser. ·MEMORY MAP The memory map of the MPU is shown in Fig, 9. During interrupt processing, the contents of the CPU registers are saved into the stack in the sequence shown in Fig. 10. This saving begins with the lower byte (PCL) of the program counter. Then the value of the stack pointer is decremented and the higher byte (PCH) of the program counter, index register (X), accumulator (A) and condition code register (CCR) are stacked in that order. In a subroutine call, only the contents of the program counter (PCH and PCL) are stacked. ·Read/Write (R/Wl This TTL compatible output signal indicates to peripheral and memory devices whether MPU is in Read ("High"), or in Write ("Low"). The normal standby state is Read ("High"). Its output can drive one TTL load and a 90pF condenser. 274 · HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 0 1/0 Ports 1:00000 Timer SCI 12 7 12B RAM ~88~~ l~r~ (128Bytes) 255 Stack 25 EKtefnal Memory Space 1 :A PORT B soo sot 2 ~TC $02 3 PORT D so3·· 4 PORT A ODA $04" 5 PORT B DOR S05" 6 PORT C DOR $06" _!'!!>! 8 Timer D.n11 Rig SOB 9 Timer CTAL Reg $09 10 _l\,1iSC__!l!li $0A Not Used -Y··W·-- 8182 -~n~;,:;.~;t-- 1$1FF6 8t9 1 S1FFF 16 SCICTALRBg $t0 1 SCI STSRtig Stt 1 SCI Da.UI Rag $t2 External Memory Space Not Used 31 $tF 3( External $20 127 Memory Space $7F t638 $3FFF · Wri1t1only ·· Reedonlyregl (a) HD6305X2 0 1/0 Ports I'""""" Timer SCI 3 $003F 4 RAM $0040 01 t :.A PQ!!I:!: $00 sot 2 ::e_ORTC $02 3 PORT D 503·· 4 PORT A DOR $04" ~~ (t92Bytes) 255 Stack 25 RAM i64Bytes) 3t 9 $0t3F 5 PORT BODA $05" 6 PORT C DOR $06" Not 8 TinwfO.W....!!!!!.. $08 9 to nmer CTRl Reg J!!!:scJ!:eg $09 SOA 320 $0t40 \External Memory Space ~B 2 Bt9 1 -_~-a-ro-r-Wu-p-tt·- · St FF St FF Not Used SCI CTIIL Reg $10 t set sTS Reg ~t tB SCI D.U. Rag $12 Exttlrnal M.......,Spoce t63B3 $3FFF j( Not Used 3t $tF External $20 63 Memory Space $3F .... · Wri· only reg~ 0 Reed only - (b) HD6305Y2 Figure 9 Memory Maps of MPU 1 7 6 5 4 3 2 1 0 n-4 1 1 1 Conditi~n Code Register n+1 Pull n-3 Accumulator n+2 n-2 Index Register n+3 ol n-1 0 PCH' n+4 n Push PCL* n+5 · In a subroutine call, only PCL and PCH are stacked. Figure 10 Sequence of Interrupt Stacking ·REGISTERS There are five registers which the programmer can operate. 7 0 I.__ _ _ _A_ _ _ __.I Accumulator 7 0 I x Index ----------"'Reg' ister 13 0 I...__ _ _ _ _ _ _PC_ _ _ _ _ ___,cPoruognrtaemr ' 13 Io lololololol 1 I 6 1 I 5 SP 0 .-......--..--,...-..---. Condition ...H,._._I.,.....,......,.....,_C.Roedgeister ~gg~~ Zero ~---Negative ~----Interrupt Mask '-------Half Carry Figure 11 Programming Model ·Accumulator CAI This accumulator is a general purpose 8-bit register which holds operands or the result of arithmetic operation or data processing. · Index Register (XI The index register is an 8-bit register, and is used for index addressing mode. Each of the addresses contained in the register consists of 8 bits which, combined with an offset value, provides an effective address. In the case of a read/modify/write instruction, the index register can be used like an accumulator to hold operation data or the result of operation. If not used in the index addressing mode. the register can be used to store data temporarily. ·Program Counter (PC) The program counter is a 14-bit register that contains the address of the next instruction to be executed. · Stack Pointer (SP) The stack pointer is a 14-bit register that indicates the ad- dress of the next stacking space. Just after reset, the stack pointer is set at address SOOFF. It is decremented when data is pushed, and incremented when pulled. The upper 8 bits. of the stack pointer are fJXed to 00000011. During the MPU being reset or during a reset stsck. pointer (RSP) instruction, the pointer is set to addresli $00FF. Since a subroutine or interrupt can use space up to address SOOCl for stacking, the subroutine can be used up to 31 levels and the interrupt up to 12 levels. · ·Condition Code Register (CCR I The condition code register is a 5-bit register, each bit indicating the result of the instruction just executed. The bits can be individually tested by conditional branch instruc· @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 275 HD6305X2/HD6305Y2-------------------------- tions. The CCR bits are as follows: Half Carry (H): Used to indicate that a carry occurred be- tween bits 3 and 4 during an arithmetic oper- ation (ADD, ADC). Interrupt (I): Setting this bit causes all interrupts, except a software interrupt, to be masked. If an interrupt occurs with the bit I set, it is latched. It will be processed the instant the interrupt mask bit is reset. (More specifi- cally, it will enter the interrupt processing routine after the instruction following the CLI has been executed.) Negative (N): Used to indicate that the result of the most recent arithmetic operation, logical operation or data processing is negative (bit 7 is logic "l"). Zero (Z): Used to indicate that the result of the most recent arithmetic operation, logical operation or data processing is zero. Carry/ Represents a carry or borrow that occurred Borrow (C): in the most recent arithmetic operation. This bit is also affected by the Bit Test and Branch instruction and a Rotate instruction. ·INTERRUPT There_!!_e six different types of interrupt: external interrupts (INT, . IN_T2 ), internal timer interrupts (TIMER, TIMER2 ), senal mterrupt (SCI) and interrupt by an instruction (SWI). Of these six interrupts, the INT2 and TIMER or the SCI and TIMER2 generate the same vector address, respectively. When an interrupt occurs, the program in progress stops and the then CPU status is saved onto the stack. And then, the interrupt mask bit (I) of the condition code register is set and the start address of the interrupt processing routine is obtained from a particular interrupt vector address. Then the interrupt routine starts from the start address. System can exit from the interrupt routine by an RTI instruction. When this instruction is executed, the CPU status before the interrupt (saved onto the stack) is pulled and the CPU restarts the sequence with the instruction next to the one at which the interrupt occurred. Table 1 lists the priority of interrupts and their vector addresses. Table 1 Priority of Interrupts Interrupt· RES SWI INT TIMER/INT2 SCl/TIMER2 Priority 1 2 3 4 5 Vector Address $1FFE, $1FFF $1FFC, $1FFD $1FFA, $1FFB $1FF8, $1FF9 $1FF6, $1FF7 A flowchart of the interrupt· sequence is shown in Fig. 12. A block diagram of the interrupt request source is shown in Fig. 13. Reset 1-1 $FF-SP 0-DDR's CLR INT Logic $FF-TOR $7F-Timer Prescaler $50-TCR $3F-SSR $00-SCR $7F-MR Load PC From Reset: $1 FFE. $1 FFF y Fetch Instruction y Execute Instruction 276 Figure 12 Interrupt Flow Chart ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Jn the block diagram, both the external interrupts INT and INTi are edge trigger inputs. At the falling edge of each input, an interrupt request is generated,and latched. The INT interrupt request is automatically cleared if jumping is made to the 00 processing routine. Meanwhile, the INT2 request is cleared if "O" is written in bit 7 of the miscellaneous register. For the external interrupts (INT, INT2 ), internal timer interrupts (TIMER, TIMER2) and serial interrupt (SCI), each interrupt request is held, but not processed, if the I bit of the condition code register is set. Immediately after the I bit is cleared, the corresponding interrupt processing starts accord- ing to th!..e!!ority. The INT2 interrupt can be masked by setting bit 6 of the miscellaneous register; the TIMER interrupt by setting bit 6 of the timer control register; the SCI interrupt by setting bit 5 of the serial status register; and the TIMER2 interrupt by setting bit 4 of the serial status register. The status of the 00 terminal can be tested by a BIL or BIH instruction. The 00 falling edge detector circuit and its latching circuit are independent of testing by these instruc- tions. This is also true with the status of the INT2 terminal. ·Miscellaneous Register (MR; $000AI The interrupt vector address for the external interrupt 002 is the same as that for the TIMER interrupt, as shown in Table 1. For this reason, a special register called the miscellaneous register (MR; $000A} is available to control the INT2 interrupts. Bit 7 of this register is the INTi interrupt request flag. When the falling edge is detected at the INTi terminal, "1" is set in bit 7. Then the software in the interrupt routine (vector addresses: $1FF8, SIFF9) checks bit 7 to see if it is INT2 interrupt. Bit 7 can be reset by software. Miscellaneous Register (MR;$000AI 76543210 l '--------- IMR~MR61ZIZIZIZIZIZI ~ iN'fi Interrupt Mask ~-- - - - - - - - - - - iiiiTi Interrupt Request Flag Miscellaneous Register (MR;$000AI Bit 6 is the INT2 interrupt mask bit. If this bit is set to "l ", then the INT2 interrupt is disabled. Both read and write are possible with bit 7 but "I" cannot be written in this bit by software. This means that an interrupt request by software is impossible. When reset, bit 7 is cleared to "O" and bit 6 is set to "1". ·TIMER Figure 14 shows a MPU timer block diagram. The timer data register is loaded by software and, upon receipt of a clock input, begins to count down. When the timer data BIH/BIL Test illli' Inter- rupt Latch I Falling Edge Detector I Vectoring generated $1 FFA, $1 FFB Condition Code Register (CCR) INT TIMER SCl/TIMER2 ">--<._f---- Vectoring generated $1FFB, $1FF9 Serial Status Register (SSR) >---+---- Vectoring generated $1 FF6, $1 FF7 Figure 13 Interrupt Request Generation Circuitry .HITACHI Hitachi America Ltd- · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 277 register (TDR) becomes "0", the timer interrupt request bit (bit 7) in the timer control register is set. In response to the interrupt request, the CPU saves its status into the stack and fetches timer interrupt routine address from addresses $1 FF8 and $1 FF9 and execute the interrupt routine. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the timer control register. The mask bit (I) in the condition code register can also mask the timer interrupt. The source clock to the timer can be either an external signal from the timer input terminal or the internal E signal (the oscillator clock divided by 4). If the E signal is used as the source, the clock input can be gated by the input to the timer input terminal. Once .the timer count has reached "O", it starts counting down with "$FF". The count can be monitored whenever desired by reading the timer data register. This permits the program to know the length of time having passed after !he occurrence of a timer interrupt, without disturbing the contents of the counter. When the MPU is reset, both the prescaler and counter are initialized to logic "l ". The timer interrupt request bit (bit 7) then is cleared and the timer interrupt mask bit (bit 6) is set. To clear the timer interrupt request bit (bit 7), it is ileeessary to write "O" in that bit. TCR7 0 Timer interrupt request Absent Present TCR6 0 Timer interrupt mask Enabled Disabled ·Timer Control Register.ITCR; $0009) Selection of a clock source, selection of a prescaler fre- quency division ratio, and a timer interrupt can be controlled by the timer control register (TCR; $0009). For the selection of a clock source, any one of the four modes (see Table 2) can be selected by bits 5 and 4 of the timer control register (TCR). Timer Control Register (TCR; $0009) 76 54 0 TCR7 CR6 L Prescaler division ratio selection Prescaler initlalize ' - - - - - - - - - - C l o c k input source ' - - - - - - - - - - - - T i m e r interrupt mask ' - - - - - - - - - - - - - - T i m e r interrupt request After reset, the TCR is initialized to "E under timer termi- nal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is "I", the counter starts counting down with "$FF" immediately after reset. When "I" is written in bit 3, the prescaler is initialized. This bit always shows "O" when read. Table 2 Clock Source Selection TCR Bit 5 Bit4 0 0 0 1 1 0 1 1 Clock input source Internal clock E E under timer terminal control No clock input (counting stopped) Event input from timer terminal Initialize (Internal Clock) E --r--1 7128 Timer Data Register (TDR;$0008) S·Bit Counter Clock Input '----~----.----'Timer Interrupt Write Read Figure 14 Timer Block Diagram 278 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 A prescaler division ratio is selected by the combination of three bits (bits 0, 1 and 2) of the timer control register (see Table 3). There are eight different division ratios:+!, +2, +4, +8, + 16, +32, +64 and + 128. After reset, the TCR is set to the +I mode. Table 3 Prescaler Division Ratio Selection Bit 2 0 0 0 TCR Bit 1 0 0 1 Bit 0 0 1 0 Prescaler division ratio +11 +2 +4 0 1 1 +8 1 0 0 +16 1 0 1 +32 1 1 0 1 1 1 +64 +128 A timer interrupt is enabled when the timer interrupt mask bit is "O", and disabled when the bit is "I". When a timer interrupt occurs, "I" is set in the timer interrupt request bit. This bit can be cleared by writing "O" in that bit. ·SERIAL COMMUNICATION INTERFACE (SCI) This interface is used for serial transmission or reception of 8-bit data. Sixteen transfer rates are available in the range from I µs to approx. 32 ms (for oscillation at 4 MHz). The SCI consists of three registers, one eighth counter and one prescaler. (See Fig. 15.) SCI communicates with the CPU via the data bus, and with the outside world through bits 5, 6 and 7 of port C. Described below are the operations of each register and data transfer. ·SCI Control Register (SCR; $00101 6 54 2 0 SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR 1 SCRO SCI Control Registers (SCA; 00101 SCRO E Prescaler Transfer Clock Generator Initialize SCI Status Registers (SSR :$00111 SCl/TIMER2 Figure 15 SC I Block Diagram .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 279 SCR7 0 C1 terminal Used as 1/0 terminal (by DOR). Serial data output (DOR output} SCR6 0 C6 terminal Used as 1/0 terminal (by DOR). Serial data input (DOR input) SCR5 SCR4 0 0 0 1 1 0 1 1 Clock source - Internal External Cs terminal Used as 1/0 terminal (by DOR}. Clock output (DOR output) Clock input (DOR input) Bit 7 (SCR7) When this bit is set, the DDR corresponding to the C7 becomes "1" and this terminal serves for output of SCI data. After reset, the bit is cleared to "O". Bit 6 (SCR6) When this bit is set, the DDR corresponding to the C6 becomes "O" and this terminal serves for input of SCI data. After reset, the bit is cleared to "O". Bits 5 and 4 (SCRS, SCR4) These bits are used to select a clock source. After reset, the bits are cleared to "O". Bits 3 - 0 (SCR3 - SCRO) These bits are used to select a transfer clock rate. After reset, the bits are cleared to "0". Bit? (SSR7) Bit 7 is the SCI interrupt request bit which is set upon completion of transmitting or receiving 8-bit data. It is cleared when reset or data is written to or read from the SCI data register with the SCRS="I ". The bit can also be cleared by writing "O" in it. Bit 6 (SSR6) Bit 6 is the TIMER2 interrupt request bit. TIMER2 is multi- plexed with the serial clock generator, and SSR6 is set each time the internal transfer clock falls. When reset, the bit is cleared. It also be cleared by writing "O" in it. (For details, see TIMER2 .) Bit 5 (SSRS) Bit 5 is the SCI interrupt mask bit which can be set or cleared by software. When it is "l ",the SCI interrupt (SSR7) is masked. When reset, it is set to "l". Bit 4 (SSR4) Bit 4 is the TIMER2 interrupt mask bit which can be set or cleared by software. When the bit is "1 ", the TIMER2 interrupt (SSR6) is masked. When reset, it is set to "1 ". Bit 3 (SSR3) When "1" is written in this bit, the prescaler of the transfer clock generator is initialized. When read, the bit always is "O". Bits 2 -: 0 Not used. SSR7 0 SCI interrupt request Absent Present SSR6 0 TIMER 2 interrupt request Absent Present SCR3 SCR2 SCR1 SCRO 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 I I I I 1 1 1 1 Transfer clock rate 4.00MHz 4.194MHz 1 j.!S 2µs 4µs Bµs I 32768µs 0.95 j.!S 1.91 j.IS 3.82 j.!S 7.64µs I 1/32 s ·SCI Data Register (SOR; $0012) A serial-parallel conversion register that is used for transfer of data. ·SCI Status Register (SSR; $0011 I SSR5 0 SCI interrupt mask Enabled Disabled SSR4 0 TIMER2 interrupt mask Enabled Disabled · Data Transmission By writing the desired control bits into the SCI control registers, a transfer rate and a source of transfer clock are determined and bits 7 and 5 of port C are set at the serial data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data written in the SCI data register is output from the C7 /Tx terminal, starting with the LSB, synchronously with the falling edge of the serial clock. (See Fig. 16.) When 8 bit of 280 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 data have been transmitted, the interrupt request bit is set in bit 7 of the SCI status register with the rising edge of the last serial clock. This request can be masked by setting bit 5 of the SCI status register. Once the data has been sent, the 8th bit data (MSB) stays at the C1 /Tx terminal. If an external clock source has bec:n selected, the transfer rate determined by bits 0 - 3 of the SCI control register is ignored, and the Cs/CK terminal is set as input. If the internal clock has been selected, the Cs/ CK terminal is set as output and clocks are output at the transfer rate selected by bits 0 - 3 of the SCI control register. Figure 1-6 SCI Timing Chart · Data Reception By writing the desired control bits into the SCI control register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data input terminal and the serial clock terminal, respectively. Then dummy-writing or -reading the SCI data register, the system is ready for receiving data. (This procedure is not needed after reading the subsequent received data. It must be taken after reset and after not reading the subsequent received data.) The data from the C6 /Rx terminal is input to the SCI data register synchronously with the rising edge of the serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI status register. This request can be masked by setting bit 5 of the SCI status register. If an external clock source have been selected, the transfer rate determined by bits 0- 3 of the SCI control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal clock has been selected, the Cs/CK terminal is set as output and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register. ·TIMER2 The SCI transfer clock generator can be used as a timer. The clock selected by bits 3 - 0 of the SCI control register (4µs - approx. 32 ms (for oscillation at 4 MHz)) is input to bit 6 of the SCI status register and the TIMER2 interrupt request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a reload counter or clock. CD ®@ ©@ ----. . ,~!_ ___.~--~t~--~ L CD :Transfer ctock generator is reset and mask bit {bit 4 of SCI status register) is cleared. @, © :TIMER2 interrupt request @,@ : TIMER2 interrupt request bit cleared TIMER2 is multiplexed with the SCI transfer clock generator. If wanting to use TIMER2 independently of the SCI, specify "External" (SCRS =I, SCR4 =I) as the SCI clock source. If "Internal" is selected as the clock source, reading or writing the SDR causes the· prescaler of the transfer clock generator to be initialized. ·1/0 PORTS There are 24 input/output terminals (ports A, B, C). Each I/O terminal can be selected for either input or output by the data direction register. More specifically, an I/O port will be input if "O" is written in the data direction register, and output if "I" is written in the data direction register. Port A, B or C reads latched data if it has been programmed as output, even with the output level being fluctuated by the output load. (See Fig. I7.) When reset, the data direction register and data register go to "O" and all the input/output terminals are used as input. Bit of data direction register 1 1 0 Bit of output data 0 1 x Status of output 0 1 3-state Input to CPU 0 1 Pin Figure 17 Input/Output Port Diagram Seven input-only terminals are available (port D). Writing to an input terminal is invalid. All input/output terminals and input terminals are TTL compatible and CMOS compatible in respect of both input and output. If 1/0 ports or input ports are not used, they should be connected to Vss via resistors. With none connected to these terminals, there is the possibility of power being consumed despite that they are not used. ·RESET The MPU can be reset either by external reset input (RES) or power-on reset. (See Fig. 18.) On power up, the reset input must be held "Low" for at least tosc to assure that the internal oscillator is stabilized. A sufficient time of delay can be obtained by connecting a capacitance to the RES input as shown in Fig. 19. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 281 RE5 Terminal Figure 18 Power On and Reset Timing 100kU typ Vee MPU requirement for minimull} external configurations. It can be driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or ceramic oscillator between pins 5 and 6 depending on the re· quired oscillation frequency stability. Three different terminal connections are shown in Fig. 20. Figs. 21, and 22 illustrate the specifications and typical arrange· ment of the crystal, respectively. C1 AT Cut ~~ Parallel Resonance XTALL___f~ EXTAL Co=7pF max. f=2.0-8.0MHz Rs=60Q max. Figure 21 Parameters of Crystal (a) (b) Figure 19 Input Reset Delay Circuit CL ~~~CjXTAL 16,4.l~~DEXTAL MPU ·INTERNAL OSCILLATOR The internal oscillator circuit is designed to meet the 1----t>---t EXTAL .OMHzCJ XTAL 10-22pF±20% MPU Crystal Oscillator XTAL MPU External Clock Input EXTAL NC XTAL MPU External Clock Drive Figure 20 Internal Oscillator Circuit [NOTE} Use as short wirings as possible for connection of the crystal with the EXT AL and XTAL terminals. Do not allow these wirings to cross others. Figure 22 Typical Crystal Arrangement ·LOW POWER DISSIPATION MODE The HD6305X2 and the HD630SY2 provides three low power dissipation modes: wait, stop and standby. eWaitMode When WAIT instruction being executed, the MPU enters into the wait mode. In this mode, the oscillator stays active but the internal clock stops. The CPU stops but the peripheral functions - the timer and the serial communication inter· face - stay active. (NOTE: Once the system has entered the wait mode, the serial communication interface can no longer be retriggered.) In the wait mode, the registers, RAM and 1/0 tenninals hold their condition just before entering into the wait mode. The escape from this mode can be done by interrupt (INT, TIMER/INTI or SCI/TIMER2), RES or STBY. The RES resets the MPU and the STBY brings it into the standby mode. (This will be mentioned later.) When interrupt is requested to the CPU and accepted, the wait mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register, after releasing from the wait mode the MPU executes the instruction next to the WAIT. If an interrupt other than the INT (i.e., TIMER/INT2 or SCI/TIMER2) is masked by the timer control @HITACHI 282 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 register, miscellaneous register or serial status register, there is no interrupt request to the CPU, so the wait mode cannot be released. Fig. 23 shows a flowchart for the wait function. ·StopMode When STOP instruction being executed, MPV enters into the stop mode. In this mode, the oscillator stops and the CPU and peripheral functions become inactive but the RAM, registers and I/O terminals hold their condition just before entering into the stop mode. The escape from this mode can be done by an external interrupt (INT or INT2 ), RES or STBY. The RES resets the MPV and the STBY brings into the standby mode. When interrupt is requested to the CPU and accepted, the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register, after releasing from the stop mode, the MPV executes the instruction next to the STOP. If the INT2 interrupt is masked by the miscellaneous register, there is no interrupt request to the MPV, so the stop mode cannot be released. Fig. 24 shows a flowchart for the stop function. Fig. 25 shows a timing chart of return to the operation mode from the stop mode. For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal delay time for stabilized oscillation, the CPU becomes active. For restarting by RES, oscillation starts when the RES goes "O" and the CPU restarts when the RES goes "l". The duration of RES="O" must exceed lose to assure stabilized oscillation. ·Standby Mode The MPV enters into the standby mode when the STBY terminal goes "Low". In this mode, all operations stop and the internal condition is reset but the contents of the RAM are hold. The I/O terminals turn to high-impedance state. The standby mode should escape by bringing STBY "High". The CPU must be restarted by reset. The timing of input signals at the RES and STBY terminals is shown in Fig. 26. Table 4 lists the status of each parts of the MPV in each low power dissipation modes. Transitions between each mode are shown in Fig. 27. (Note) When 1 bit of condition code register is "l" and interrupt (INT, TIMER/INT,, SCI/TIMER,) is held, MPV does not enter WAIT mode by the execution of WAIT instruction. In that case, after the 4 dummy cycles MCU executes the next iil6truction. In the same way, when external interrupts (INT, INT2 ) are held at the bit I set, MPV does not enter STOP mode by the execution of STOP instruction. In that case, also, MPV executes the next instruction after the 4 dummy cycles. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 283 Wait Oscillator Active Timer and Serial Clock Active All Other Clocks Stop No to Standby Mode Restart Processor Clocks Yes Initialize CPU, TIMER, SCI, 1/0 and All Other Functions No No Load PC from $1FFE, $1FFF Restart Processor Clocks 1=0 1=1 Load PC from Interrupt Vector Addresses Fetch Instruction Figure 23 Wait Mode Flow Chart 284 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Stop Stop Oscillator and All Clocks No to Standby Mode No Turn on Oscillator Wait for Time Delay to Stabilize Load PC from $1FFE, $1FFF Turn on Oscillator Wait for Time Delay to Stabilize 1=0 1=1 Load PC from Interrupt Vector Addresses Fetch Instruction Figure 24 Stop Mode Flow Chart @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 285 o~·:u.~1---+~-,A--'~ ! STOP instruction executed Time required for oscillation to become Interrupt stabilized (built-in delay time) (a) Restart by Interrupt Instructions restart Oscillator 11111111111111111111111111111 E STOP instruction executed Time required for oscillation to become stabilized (t05cl Reset start (b) Restart by Reset Figure 25 Timing Chart of Releasing from Stop Mode I tosc Restart Figure 26 Timing Chart of Releasing from Standby Mode Table 4 Status of Each Part of MPU in Low Power Dissipation Modes Mode _ _ , WAIT Soft· ware STOP Stand- Hard- by ware Start WAIT in· struction STOP in· struction STBY="Low" Osei I· lator Active Stop Stop CPU Stop Stop Stop Condition Timer. Serial Register Active Keep Stop Keep Stop Reset RAM Keep Keep 1/0 terminal Keep Escape STBY, RES, INT, INT2. each interrupt request of TIMER, TIMER,, SCI Keep STBY, RES, INT, INT2 Keep High im· pedance STBY="High" 286 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Figure 27 Transitions among Active Mode, Wait Mode, Stop Mode, Standby Mode and Reset ·BIT MANIPULATION The MPU can use a single instruction (BSET or BCLR) to set or clear one bit of the RAM within page 0 or an 1/0 port (except the write-only registers such as the data direction register). Every bit of memory or I/O within page 0 ($00 $FF) can be tested by the BRSET or BRCLR instruction; depending on the result of the test, the program can branch to required destinations. Since bits in the RAM, or I/O can be manipulated, the user may use a bit within the RAM as a flag or handle a single I/O bit as an independent I/O terminal. Fig. 28 shows an example of bit manipulation and the validity of test instructions. In the example, the program is configured assuming that bit 0 of port A is connected to a zero cross detector circuit and bit 1 of the same port to the trigger of a triac. ·The program shown can activate the triac within a time of lOµs from zero-crossing through the use of only 7 bytes on the memory. The on-chip timer provides a required time of delay and pulse width modulation of power is also posSlble. SELF 1. BRCLR 0, PORTA, SELF 1 BSET 1, PORT A BCLR 1, PORT A Figure 28 Exainple of Bit Manipulation ·ADDRESSING MODES Ten different addressing modes are available to the MPU. ·Immediate See Fig. 29. The immediate addressing mode provides access to a constant which does not vary during execution of the program. This access requires an instruction length of 2 bytes. The effective address (EA) is PC and the operand is fetched from the byte that follows the operation code. ·Direct See Fig. 30. In the direct addressing mode, the address of the operand is contained in the 2rid byte of the instruction. The user can gain direct access to memory up to the lower 2SSth address. All RAM (HD630SX2) or 192 bytes of RAM (HD630SY2), and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized. ·Extended See Fig. 31. The extended addressing is used for referenc- ing to all addresses of memory. The EA is the contents of the 2 bytes that follow the operation code. An extended addressing instruction requires 3 bytes. ·Relative See Fig. 32. The relative addressing mode is used with branch instructions only. When a branCh occurs, the program counter is loaded with the contents of the byte following the operation code. EA = (PC) + 2 + Rel., where Rel. indicates a signed 8-bit data following the operation code. If no branch occurs, Rel. = 0. When a branch occurs, the program jumps to any byte in the range +129 to -127. A branch instruction requires 2 bytes. ·Indexed (No Offsetl See Fig. 33. The indexed addressing mode allows access up to the lower 2SSth address of memory. In this mode, an instruction requires a length of one byte. The EA is the contents of the index register. ~HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 287 · Indexed (8-bit Offset) See Fig. 34. The EA is the contents of the byte follow- ing the operation code, plus the contents of the index register. This mode allows access up to the lower S11th address of memory. Each instruction when used in the index addressing mode (8-bit offset) requires 2 bytes. ·Indexed (16-bit Offset) See Fig. 35. The contents of the 2 bytes following the operation code are added to content of the index register to compute the value of EA. In this mode, the complete memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction requires 3 bytes. · Bit Set/Clear See Fig. 36. This addressing mode is applied to the BSET and BCLR instructions that can set or clear any bit on page 0. The lower 3 bits of the operation code specify the bit to be set or cleared. The byte that follows the operation code indicates an address within page 0. ·Bit Test and Branch See Fig. 37. This addressing mode is applied to the BRSET and BRCLR' instructions that can test any bit within page 0 and can be branched in the relative addressing mode. The byte to be tested is addressed depending on the contents of the byte following the operation code. Individual bits within the byte to be tested are specified by the lower 3 bits of the operation code. The 3rd byte represents a relative value which will be added to the program counter when a branch condition is established. Each of these instructions requires 3 bytes. The value of the test bit is written in the carry bit of the condition code register. ·Implied See Fig. 38. This mode involves no EA. All information needed for execution of an instruction is contained in the operation code. Direct manipulation on the accumulator and index register is included in the implied addressing mode. Other instructions such as SWI and RTI are also used in this mode. All instructions used in the implied addressing mode re quires one byte. ~ ili--~--{A~c:::J j Memory ' I FS Index Reg I : : Stack Point PROG LOA #$F8 05BEt::JA~6=l-------_j OSBF FS Prog Count 0750 CCR ~ ' ' Figure 29 Example of Immediate Addressing Memory CAT FCB 32 0048 20 PROG LOA CAT 0520 86 052E 48 8 : : ' A 20 lndex eg I Stack Point Prog ~ount 052F CCR I Figure 30 Example of Direct Addressing 288 @HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Memory PAOG LDA CAT 0409 C6 040A 06 0408 ES CAT FCB 64 06E5l::::J4@0=::l-------_J A 40 Index Reg I Stack Point Prag Count 040C CCR Figure 31 Example of Extended Addressing Memory PAOG BEO PAOG2 ::~1--?i~~:-~ A Index Reg I Stack Point Prag Count 04C1 CCR Figure 32 Example of Relative Addressing CCR Figure 33 Example of Indexed (No Offset) Addressing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 289 Memory TABL FCB BF 0089 BF FCB 86 008A 86 FC8 08 0088 DB FCB CF 008C CF PROG LOA TABL.X 0758 E6 075C 89 ~ A CF lndeit Reg 03 Stack Point I Prop Count 0750 CCR I Figure 34 Example of Index (8-bit Offset) Addressing Memory ~. . PROG LOA TABLX 0692 0693 07 0694 7E TABL FCB :BF 077E BF FCB ·86 077F B6 FCB :i:DB 0780 DB FCB #CF 0781 CF A Stack I Prog count 0695 CCR I Figure 35 Example of Index (16-bit Offset) Addressing 290 . . Memory : ' PORTBEQU 1 0001~ lear . . Bdt PROG BCLR 6. PORT B 05BF t=:J:lD t : j - - - - _ j 0590 01 ~ I : 0000 A lndH Reg I Stack Point Prog Count 0591 CCR Figure 36 Example of Bit Set/Clear Addressing $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Figure 37 Example of Bit Test and Branch Addressing 'Memory Figure 38 Example of Implied Addressing ·INSTRUCTION SET There are 62 basic instructions available to the HD6305X2 and the HD6305Y2. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, and control. The details of each instruction are described in Tables 5 through 11. ·Register/Memory Instructions Most of these instructions use two operands. One operand is either an accumulator or index register. The other is derived from memory using one of the addressing modes used on the HD6305X2 and the HD6305Y2. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump instruction (JSR). See Table 5. ·Read/Modify/Write Instructions These instructions read a memory or register, then modify or test its contents, and write the modified value into the memory or register. Zero test instruction (TST) does not write data, and is handled as an exception in the read/modify/ write group. See Table 6. ·Branch Instructions A branch instruction branches from the program seqµence in progress if a particular condition is established. See Table 7. ·Bit Manipulation Instructions These instructions can be used with any bit located up to the lower 255th address of memory. Two groups are available; one for setting or clearing and the other for bit testing and branching. See Table 8. ·Control Instructions The control instructions control the operation of the MPU which is executing a program. See Table 9. · List of Instructions in Alphabetical Order Table 10 lists all the instructions used on the HD6305X2 and the HD6305Y2 MPU in the alphabetical order. ·Operation Code Map Table 11 shows the operation code map for the instructions used on the MPU. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 291 Table 5 Register/Memory Instructions ()poratlon1 Load A from Memory Add,..lngModll Mn.-nonic lrnmedi. . . Direct OP # - OP # - 1-.ec1 Indexed lndeud Extended (No Otlset) 18-BitOlllll) llMIOllllll - OP # - OP # - OP # - OP # Boolean/ Artthmetic Operation LOA AB 2 2 B8 2 3 CB 3 4 FB 1 3 EB 2 4 D6 3 5 M-->A Load X from Memory Store A in Memory Store X in Memory LOX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 M-X STA STX x- - - - B7 2 3 C7 3 4 F7 1 4 E7 2 4 D7 3 5 A-M - - - BF 2 3 CF 3 4 FF 1 4 EF 2 4 OF 3 5 Add Memory to A ADD AB 2 2 B.B 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 A+M-->A Add Memory and Carry to A Subtract Memory ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5 A+M+C-A SUB AO 2 2 BO 2 3 co 3 4 FO 1 3 EO 2 4 DO 3 5 A-M-A Subtract Memory from A with Borrow SBC A2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 D2 3 5 A-M-C-A AND Memory to A OR Memory with A AND ORA A4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 D4 3 5 A·M-A AA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5 A+M-A Exclusive OR Memory with A EOR AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 08 3 5 A$M-A Arithmetic Compare A with Memory CMP A1 2 2 B1 2 3 C1 3 4 F1 1 3 E1 2 4 D1 3 5 A-M Ar!thmetiC Compare X with Memory CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5 X-M Bit Test Memory with A (logical Compare) Jump Unconditional Jump to Subroutine BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 05 3 5 A·M - - JMP - BC 2 2 cc 3 3 FC 1 2 EC 2 3 DC 3 4 JSR - - - BD 2 5 CD 3 B fl! 1 5 ED 2 5 DD 3 B Symbols:·Op· Operation # · Number of bytes - = Number of cycles Condition Code H I Nzc · · · /\ /\ · · · /\ /\ · · · /\ /\ · · · /\ /\ · " /\ " /\ A /\ r. /\ · ·· ,, /\ /\ · · /\ /\ /\ · · · /\ /\ · · " " · · · " " · · · " " ·' · · " r. " · · · · · " · " · · · · · · · Table 6 Read/Modify/Write Instructions C)poratloM Increment O.Crement Clear Complement ~ 12·s Complement) Rohte Left Thru Carry Rotete Right Thru Carry LogiCll SNft I.oft LogiCll Shilt Right Addrening- Mnemonic lmplied(A) lmpliedlXl Indexed Indexed Boolean/Arithmetic Operation Direct INoOllut) 18-Bit Olllll) Condition Code - OP # - OP # - OP # - OP # - OP # H I Nzc INC DEC CLR COM 4C 1 4A 1 4F 1 43 1 2 5C 1 2 5A 1 2 5F 1 2 53 1 2 3C 2 2 3A 2 2 3F 2 2 33 2 5 7C 1 5 7A 1 5 7F 1 5 73 1 5 BC 2 5 BA 2 5 BF 2 5 B3 2 B A+1-A or x+1-x or M+1-M B A-1--A or x-1-x or M-1-M 8 oo-A or oo-x or 00-M B A-->A or "lt'-x or M-M · · · A /\ · · · /\ /\ · · o· 1 · · · /\ /\ 1 00-A-A or 00-X-X NEG 40 1 2 50 1 2 30 2 5 70 1 5 60 2 B orOO-M-M · · /\ /\ /\ ROL ROR Lfu"' '·j·· 5J 49 1 2 59 1 2 39 2 5 79 1 5 B9 2 B I 11 11 I ..µ 4B 1 2 5B 1 2 3B 2 5 7B 1 5 66 2 B L§1!!11 l·E3·:MI I · · /\ /\ /\ · · /\ A /\ LSL LSR c .. .. 48 1 2 58 1 2 38 2 5 78 1 5 BB 2 B D-..C:IHEIi"I°JH-Jo · I l·E~..:MI o-j 44 1 2 54 1 2 34 2 5 74 1 5 64 2 B · · A /\ /\ ·0 A A Arithmetic SNft Right ASR Arithmetic Shilt I.oft ASL T"' for Negative or Zoro TST Symbols: Op· Operation # ·Nu-ofbytes - · N u - of cycles ~ M 47 1 2 57 1 2 37 2 5 77 1 5 B7 2 B 48 1 2 58 1 2 3B 2 5 78 1 5 88 2 B Equol to LSL · · /\ A A ··A A A 4D 1 2 5D 1 2 30 2 4 7D 1 4 BD 2 5 A-00 or X-00 or M-00 ··A A · 292 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Operations Branch Always Branch Never Branch IF Higher Branch IF Lower or Same Branch IF Carry Clear (Branch IF Higher or Same) Branch IF Carry Set (Branch IF Lower) Branch IF Not Equal Branch IF Equal Branch IF Half Carry Clear Branch IF Half Carry Set Branch IF Plus Branch IF Minus Branch IF Interrupt Mask Bit is Clear Branch IF Interrupt Mask Bit is Set Branch IF Interrupt Line is Low Branch IF Interrupt Line is High Branch to Subroutine Symbols: Op =Operation # = Number of bytes .... =Number of cycles Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Table 7 Branch Instructions Addressing Modes Relative OP # - 20 2 3 None 21 2 3 None 22 2 3 C+Z=O 23 2 3 C+Z=l 24 2 3 C=O 24 2 3 C=O 25 2 3 C=1 25 2 3 C=l 26 2 3 Z=O 27 2 3 Z=1 28 2 3 H=O 29 2 3 H=l 2A 2 3 N=O 2B 2 3 N=l Branch Test 2C 2 3 1=0 2D 2 3 1=1 2E 2 3 INT=O 2F 2 AD 2 3 INT=l 5 -- Condition Code H I Nzc · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · I · · · ·l· l · · · · · · · · · · Table 8 Bit Manipulation Instructions Operations Branch IF Bit n is set Branch IF Bit n is clear Set Bit n Clear Bit n Mnemonic BRSET n(n =0· ··7) BRCLR n(n=O··· 7) BSET n(n=0···7) BCLR n(n=0···7) Addressing Modes Bit Set/Clear Bit Test and Branch OP # - OP # - - - - 2-n 3 5 - - - 01+2·n 3 5 10+2·n 2 5 - 11+2·n 2 5 - ... -- Boolean/ Arithmetic Operation - 1~Mn o~Mn Branch Test Mn=1 Mn=O - - Symbols: Op= Operation # = Number of bytes - = Number of cycles Condition Code H I Nzc · · · · /\ · · · · /\ · · · · · · · · · · @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 293 Table 9 Control Instructions Operations Transfer A to X Transfer X to A Set Carry Bit Clear Carry Bit Set Interrupt Mask Bit Clear Interrupt Mask Bit Software Interrupt Return from Subroutine Return from Interrupt Reset Stack Pointer No-Operation Decimal Adjust A Stop Wait Symbols: ~P: ~=:~~f bytes Mnemonic TAX TXA SEC CLC SEI cu SWI RTS RTI RSP NOP OAA STOP WAIT Addressing Modes Implied OP II - Boolean Operation 97 1 2 A-X 9F 1 2 X-A 99 1 1 1-c 9B 1 1 o-c 9B 1 2 1-1 9A 1 2 0-1 B3 1 10 B1 1 5 BO 1 B 9C 1 2 $FF-SP 90 1 BO 1 BE 1 1 Advance Prog. Cntr. Qnly 2 Converts binary add of BCD charcters into BCD format 4 BF 1 4 Condition Code H I Nzc · · · · · · · · · · · · · · 1 · · · · · · 1 0 1 · · · · · · · · · · · 0 · · · · ? ? ? ? ? · · · · · · · · /\ · · /\ · · /\ * · · · · · · · · · · ·Are BC_D characters of upper byte 10 or more? (They are not cleared if set in advance.) - .., Number of cycles Table 10 Instruction Set (in Alphabetical Order) Addressing MQdes Condition Code Bit Bit Mnemonic ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI (BHS) BIH BIL BIT (BLO) BL'S BMC BMI BMS BNE BPL BRA Indexed Indexed Indexed Set/ Test& z c Implied Immediate Direct Extended Relative (No Offset) (B-Bit) (16-Bit) Clear Branch H I N x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x · /\ /\ /\ /\ · /\ /\ /\ /\ · · · /\ /\ · · /\ /\ /\ · · · · · · /\ · · " · · /\ · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · /\ /\ · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Condition Code Symbols: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) Z Zero c Carry/Borrow /\ Test and Set if True, Cleared Otherwise · Not Affected ? Load CC Register From Stack (to be continued) 294 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 10 Instruction Set (in Alphabetical Order) Addressing Modes Condition Code Bit Bit Mnemonic BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP COM CPX DAA DEC EOR INC JMP JSR LOA LOX LSL LSR NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT Indexed Indexed Indexed Set/ Test ll z c Implied Immediate Direct Extended Relative (No Offset) (B-Bit) (16-Bit) Clear Branch H I N x · · · · · x · · · · /\ x · · · · /\ x · · · · · x · · · · · x · · · · 0 x ·0 ··· x x x x ··0 1 · x x x x x x · · /\ /\ /\ x x x x · · /\ /\ 1 x x x x x x · · /\ /\ /\ x · · /\ /\ /\ x x x x · · · /\ I\ x x x x x x · · · /\ /\ x x x x · · · ,\ /\ x x x x x · · · · · x x x x x · · · · · x x x x x x · · · /\ /\ x x x x x x · · · /\ /\ x x x x · · /\ /\ /\ x x x ·X x x x x x x x x x x x · · 0 I\ /\ · · /\ /\ /\ · · · · · · · · /\ /\ x x x x x x x x x · · /\ /\ /\ · · /\ /\ /\ · · · · · x ? ? ? ? ? x x x x x x x x x x x x x x x x x x x x x x x x x x x · · · · · · · /\ /\ /\ ···· 1 · 1 · · · · · · /\ /\ · · · · · · · · /\ /\ · · /\ /\ /\ · 1 · · · x x x x x x x · · · · · · · · /\ /\ · · · · · · · · · · Condition Code Symbols: H Half Carry (From Bit 3) I Interrupt Mask N Negative (Sign Bit) Z Zero c Carry/Borrow /\ Test and Set if True, Cleared Otherwise · Not Affected ? Load CC flegis~r From Stack ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 295 Bit Manipulation Test & Set/ Branch Clear 0 1 0 BRSETO BSETO 1 BRCLRO BCLRO 2 BRSET1 BSET1 3 BRCLR1 BCLR1 4 BRSET2 BSET2 5 BRCLR2 BCLR2 6 BRSET3 BSET3 7 BRCLR3 BCLR3 B BRSET4 BSET4 9 BRCLR4 BCLR4 A BRSET5 BSET5 B BRCLR5 BCLR5 c BRSET6 BSET6 D BRCLR6 BCLR6 E BRSET7 BSET7 F BRCLR7 BCLR7 3/5 2/5 Branch Table 11 Operation Code Map Read/Modify/Write Control Register /Memory Rel 2 BRA BRN BHI BLS BCC BCS BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH 2/3 DIR A x ,X1 ,XO IMP IMP IMM DIR EXT ,X2 ,X1 ,XO 3 4 5 6 7 B 9 A B c D E F +- HIGH NEG RTI' - SUB 0 - RTS' CMP 1 - - - SBC 2 COM LSR - SWI' - - - - - CPX AND BIT 3 L 4 w0 5 ROR - - LOA 6 ASR - TAX' - STA STA1+1) 7 LSL/ASL - CLC EOR B ROL SEC ADC 9 DEC - cu· ORA A - - SEI* ADD B INC - RSP' - JMP(-1) c TSTHI TST - TST(-1) DAA' NOP BSR' JSR(+2) JSR(+1) JSR(+21 D - STOP' LOX E CLR WAIT' TXA' - STX STX(+1) F 2/5 1/2 1/2 2/6 1/5 1/' 1/1 2/2 2/3 3/4 3/5 2/4 1/3 INOTESI 1. "-"is an undefined operation code. 2. The lo-rmost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles). The number of cycles for the mnemonics asterisked l·I is as follows: RTI 8 TAX 2 RTS 5 RSP 2 SWI 10 TXA 2 DAA 2 BSR 5 STOP 4 CLI 2 WAIT 4 SEI 2 3. The parenthesized numbers must be added to the cycle count of the particular instruction. · Additional Instructions The following new instructions are used on the HD630SX2 and the HD630SY2: DAA Converts the contents of the accumulator into BCD code. WAIT Causes the MPU to enter the wait mode. For this mode, see 1he topic, Wait Mode. STOP Causes the MPU to enter the stop mode. For this mode, · OPERATION AT EACH INSTRUCTION CYCLE The HD630SX2 and 1he HD6305Y2 employs a mechanism of the pipeline control for the instruction fetch and the subsequent instruction fetch is performed during the current instruction being executed. Table 12 provides the information about the relationship among each data on the Address Bus, Data Bus and R/W status in cycle-by-cycle basis during the execution of each instruction. see the topic, Stop Mode. Table 12 Cycle-by-Cycle Operation I I I Address Mode & Instructions Cycles cycle# Address Bus IMMEDIATE ADC, ADD, AND, BIT, CMP, CPX, EOR, LOA, LOX, ORA, SBC, SUB 2 1 Op Code Address +1 2 Op Code Address +2 DIRECT ADC, ADD, AND, BIT, CMP, CPX, EOR, LOA, LOX, ORA, SBC, SUB 3 1 Op Code Address +1 2 Address of Operand 3 Op Code Address +2 Data Bus 1 Operand Data 1 Next Op Code 1 Address of Operand 1 Operand Data 1 Next Op Code (to be continued) ~HITACHI 296 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I Address Mode & Instructions j Cycles jCycle # Address Bus STA, STX JMP JSR ASR, CLR, COM, DEC, INC, LSL, LSR, NEG, ROL, ROR TST EXTENDED ADC, ADD, AND, BIT, CMP, CPX, EOR, L[)A, LOX, ORA, SBC, SUB STA, STX JMP JSR INDEXED (No offset) ADC, ADD, AND, BIT, CMP, CPX, EOR, LOA, LOX, ORA, SBC, SUB STA, STX JMP 3 1 Op Code Address+1 2 Address of Operand 3 Op Code Address+ 1 2 1 Op Code Address +1 2 Jump Address 5 1 Op Code Address+ 1 2 1FFF 3 Stack Pointer 4 Stack Pointer -1 5 Jump Address 5 1 Op Code Address +1 2 Address of Operand 3 1FFF 4 Address of Operand 5 Op Code Address +2 4 1 Op Code Address+ 1 2 Address of Operand 3 1FFF 4 Op Code Address +2 4 1 Op Code Address +1 2 Op Code Address +2 3 Address of Operand 4 Op Code Address +3 4 1 Op Code Address +1 2 Op Code Address +2 3 Address of Operand 4 Op Code Address +3 3 1 Op Code Address +1 2 Op Code Address +2 3 Jump Address 6 1 Op Code Address +1 2 Op Code Address +2 3 1FFF 4 Stack Pointer 5 Stack Pointer -1 6 Jump Address 3 1 Op Code Address +1 2 Ix 3 Op Code Address +1 4 1 Op Code Address +1 2 1FFF 3 Ix 4 Op Code Address +1 2 1 Op Code Address +1 2 Ix Data Bus 1 Address of Operand 0 ( Data from Acc. Data from Ix. 1 Next Op Code 1 Jump Address 1 Next Op Code 1 Jump Address (LSB) 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Address of Operand 1 Operand Data 1 Irrelevant Data 0 New Operand Data 1 Next Op Code 1 Address of Operand 1 Operand Data ·1 Irrelevant Data 1 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 1 Operand Data 1 Next Op Code 1 Address of Operand (MSB) 1 Address of Operand (LSB) 0 { Data from Acc. Data from Ix. 1 Next Op Code 1 Jump Address. (MSB) 1 Jump Address (LSB) 1 Next Op Code 1 Jump Address (MSB) 1 Jump Address (LSB) 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Next Op Code 1 Operand Data 1 Next Op Code 1 Next Op Code 1 Irrelevant Data 0 ( Data from Acc. Data from Ix. 1 Next Op Code 1 Next Op Code 1 First.Op Code of Jump Routine (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 297 Address Mode & Instructions Cycles Cycle# Address Bus JSR ASR, CLR, COM, DEC, INC, LSL, LSR, NEG, ROL, ROR TST INDEXED (8-bit offset) ADC, ADD, AND, BIT, CMP, CPX, EOR, LOA, LOX, ORA, SBC, SUB STA, STX JMP JSR ASR, CLR, COM, DEC, INC, LSL, LSR, NEG, ROL, ROR TST INDl:XED (16-bit offset) ADC, ADD, AND, BIT, CMP, CPX, EOR, LOA, LOX, ORA, SBC, SUB 5 1 Op Code Address +1 2 1FFF 3 Stack Pointer 4 Stack Pointer -1 5 Ix 5 1 Op Code Address +1 2 Ix 3 11'FF 4 Ix 5 Op Code Address +1 4 1 Op Code Address+ 1 2 Ix 3 1FFF 4 Op Code Address +1 4 1 Op Code Address +1 2 1FFF 3 Ix+ Offset 4 Op Code Address +2 4 1 Op Code Address +1 2 1FFF 3 Ix+ Offset 4 Op Code Address +2 3 1 Op Code Address +1 2 1FFF 3 Ix+ Offset 5 1 Op Code Address +1 2 1FFF 3 Stack Pointer 4 Stack Pointer -1 5 Ix+ Offset 6 1 Op Code Address +1 2 1FFF 3 Ix+ Offset 4 1FFF 5 Ix+ Offset 6 Op Code Address +1 5 1 Op Code Address +1 2 1FFF 3 Ix+ Offset 4 1FFF 5 Op Code Address +2 5 1 Op Code Address +1 2 Op Code Address +2 3 1FFF 4 Ix+ Offset 5 Op Code Address +1 R/W Data Bus 1 Next Op Code 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 1 First'Subroutine Op Code 1 Next Op Code 1 Operand Data 1 Irrelevant Data 0 New Operand Data 1 Next Op Code 1 Next Op Code 1 Ope rand Data 1 Irrelevant Data 1 Next Op Code 1 Offset 1 Irrelevant Data 1 Operand Data 1 Next Op Code 1 Offset 1 Irrelevant Data 0 ( Data from Ace; Data from Ix. 1 Next Op Code 1 Offset 1 Irrelevant Data 1 First Op Code of Jump Routine 1 Offset 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Offset 1 Irrelevant Data 1 Operand Data 1 Irrelevant Data 0 New Operand Data 1 Next Op Code 1 Offset 1 Irrelevant Data 1 Operand Data 1 Irrelevant Data 1 Next Op Code 1 Offset (MSB) 1 Offset (LSB) 1 Irrelevant Data 1 Operand Data 1 Next Op Code (to be continued) ~HITACHI 298 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I I j Address Mode & Instructions Cycles Cycle # Address Bus STA, STX JMP JSR IMPLIED ASR, CLR, COM, DEC, INC, LSL, LSR, NEG, ROL, ROR, TST CLC, NOP, SEC RSP, TAX, TXA CLI, SEI DAA STOP, WAIT RTI RTS SWI 5 1 Op Code Address +1 2 Op Code Address +2 3 1FFF 4 Ix+ Offset 5 Op Code Address +3 4 1 Op Code Address +1 2 Op Code Address +2 3 lFFF 4 Ix +Offset 6 1 Op Code Address +1 2 Op Code Address +2 3 lFFF 4 Stack Pointer 5 Stack Pointer -1 6 Ix+ Offset 2 1 Op Code Address +1 2 Op Code Address +1 1 1 2 1 2 2 1 2 2 1 2 4 1 2 3 4 8 1 2 3 4 5 6 7 8 5 1 2 3 4 5 10 1 2 3 4 5 6 7 8 9 10 Op Code Address +1 Op Code Address +1 Op Code Address +1 Op Code Address+1 1FFF Op Code Address+1 Op Code Address +1 Op Code Address +1 lFFF 1FFF Op Code Address +1 Op Code Address +1 lFFF Stack Pointer Stack Pointer +1 Stack Pointer +2 Stack Pointer +3 Stack Pointer +4 Return Address Op Code Address +1 1FFF Stack Pointer Stack Pointer +1 Return Address Op Code Address +1 lFFF Stack Pointer Stack Pointer-1 Stack Pointer-2 · Stack Pointer-3 Stack Pointer-4 Vector Address 1FFC Vector Address 1FFD Address of SWI Routine Data Bus 1 Offset (MSB) 1 Offset (LSB) 1 Irrelevant Data 0 ( Data from Acc. Data from Ix. 1 Next Op Code 1 Offset (MSB) 1 Offset (LSB) 1 Irrelevant Data 1 First Op Code of Jump Routine 1 Offset (MSB) 1 Offset (LSB) 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 1 First Subroutine Op Code 1 Next Op Code 1 Next Op Code 1 Next Op Code 1 NextOpCqde 1 Next Op Code 1 Next Op Code 1 Irrelevant Data 1 Next Op Code 1 Next Op Code 1 Next Op Code 1 Irrelevant Data 1 Irrelevant Data 1 Next Op Code 1 Next Op Code 1 Irrelevant Data 1 cc 1 Acc. 1 Ix. 1 Return Address (MSB) 1 Return Address (LSB) 1 First Op Code of Return Routine 1 Next Op Code 1 Irrelevant Data 1 Return Address (MSB) 1 Return Address (LSB) 1 First Op Code of Return Routine 1 Next Op Code 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 0 Ix. 0 Acc. 0 cc 1 Address of SWI Routine (MSB) 1 Address of SWI Routine (LSB) 1 First Op Code of SWI Routine @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 299 Address Mode & Instructions Cycles Cycle # Address Bus R/W Data Bus RELATIVE BCC, BCS, BEQ, BHCC, BHCS, BHI, BIH, BIL, BLS, BMC, BMI, BMS, BNE, BPL, BRA, BRN BSR BIT TEST AND BRANCH BRCLR, BRSET BIT SET/CLEAR BCLR, BSET 3 1 Op Code Address +1 1 Next Op Code 2 1FFF 1 Irrelevant Data 3 ( ( Branch Address .............Test= "1" Op Code Address +1 .... Test= "O" 1 First Op Code of Branch Routine Next Op Code 5 1 Op Code Address +1 2 1FFF 3 Stack Pointer 4 Stack Pointer-1 5 Branch Address 1 Offset 1 Irrelevant Data 0 Return Address (LSB) 0 Return Address (MSB) 1 First Op Code of Subroutine 5 1 Op Code ~ddress +1 1 Address of Operand 2 Address of Operand 1 Operand Data 3 Op Code Address +2 1 Offset 4 1FFF 1 Irrelevant Data 5 ( ( Branch Address ..............Test ="1" Op Code Address +3 ......Test= "O" 1 First Op Code of Branch Address Next Op Code 5 1 Op Code Address +1 2 Address of Operand 3 1FFF 4 Address of Operand 5 Op Code Address +1 1 Address of Operand 1 Operand Data 1 Irrelevant Data 0 New Operand Data 1 Next Op Code · PRECAUTIONS · Precaution; Board Design of Oscillation .Circuit Impossible "l! "l! r--~ ~ Signal CL .--I l-4o---t-Yl(XTAL) 7hicL c::i ~ (EXT AL) HD6305X2 HD6305Y2 Figure 39 Example of Circuit Causing Trouble in Oscillation Wire the signal lines to the neighboring XTAL and EXTAL pins as far apart as possible. And locate crystal and capacity as close to XTAL and EXTAL as possible. 300 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · Precaution; Program of Writa Only Register Read/Modify/Write instructions are applied to Write Only Register (e.g. DDR; Data Direction Register of 1/0 port) of the HD6305X2 and the HD6305Y2 and its contents cannot be changed. (!) Data cannot be read from Write Only Register. (e.g. DDR of I/0 port) Read/Modify/Write instructions are executed in the following sequence. (i) Reads the contents from appointed address. (ii) Changes the data which has been read. (iii) Turn the data back to the original address. Evidently, Read/Modify/Write instructions cannot be applied to Write Only Register such as DDR. (2) For the same reason, do not set DOR of 1/0 port using BSET and BCLR instructions of the HD6305X2 and the HD6305Y2. (3) In the correct writing method into Write Only Register, stored instruction as STA and STX, etc. are used. · Precaution; Sending/Receiving Program of Serial Data Reading from or Writing into the SCI data register (SOR: $0012) during sending/receiving of serial data may make sending/receiving operation of SCI out of order. · Precaution; WAIT/STOP Instructions Program When I bit of condition code register is "I" and interrupt (INT, TIMER(iiii'r,, SCI/TIMER2 ) is held, MCU does not enter WAIT mode by the execution of WAIT instruction. In that case, after the 4 dummy cycles MCU executes the next instruction. In the same way, when external interrupts (INT, INT2 ) are held at the bit I set, MCU does not enter STOP mode by the execution of STOP instruction. In that case, also, MCU executes the next instruction after the 4 dummy cycles. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 301 HD63B09, HD63C09 CMOS MPU (Micro Processing Unit) Description The HD6309 is the .highest 8-bit microprocessor of HMCS6800 family, which is compatible with the conventional HD6809. The HD6309 has hardware and software features which make it an ideal processor for higher level language execution or standard controller applications. The HD6309 is complete CMOS device and its power dissipation is extremely low. Moreover, the SYNC and CWAI instruction makes low power application possible. Features · Hardware - Interfaces with all HMCS6800 peripherals - DMA transfer with no auto-refresh cycle · Software: object code compatible with the HD6809 · Low power consumption mode (Sleep mode) -SYNC state of SYNC Instruction - WAIT state of CWAI Instruction · On chip oscillator · Wide operation range: f = 0.5 to 3 MBz (Vcc = 5 V±l0%) Pin Arrangement ..,Yu NMI IRQ FIRQ ~ BA VAeo e 40 HALT 39 XTAL 38 EXTAL 37 RES ~ MR~ 35 Q 3334i=::~D~EM~A~/~BR~E~Q A, 32 R/W A2 31 Do Aa 30 0 1 A4 29 02 As 28 Da Ae 27 04 A1 26 Ds Ae 25 De As 24 D1 A10 23 A1s A11 22 A14 A12 21 A1a -~L-~~~~~--'~ (Top view) · PLCC package available Type of Products Type No. Bua Timing HD63809 2.0 MHz HD63C09 3.0 MHz (lbpViow) 302 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 r- Block Diagram PC u s y x A D{ B DP cc ALU +--Vee +--Vss POST RES NMI FIRQ IRQ DMA/BREQ R/W HALT BA BS XTAL EXT AL MADY E a .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 303 HD6309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~- Prograrnrning Model As shown in figure 1, the HD6309 adds three registers to the set available in the HD6800. The added registers are a direct page register, the user stack pointer and a second index register. Accumulators (A, B, D) The A and B registers are general purpose accumulators which are used for arithmetic calcu· lations and manipulation of data. part in the calculation of effective addresses. This address may be used to point to data directly or may be modified by an optional constant or register offset. In some indexed modes, the contents of the index register are incremented or decremented to point to the next item of tabular data. All four pointer registers (X, Y, U, S) may be used as index , registers. · Stack Pointer (U, S) Certain instructions concatenate the A and B registers to form a single 16-bit accumulator. This is referred to as the D register. It is formed with the A register as the most significant byte. Direct Page Register (DP) The direct page register of the HD6309 serves to enhance the direct addressing mode. The contents of this register appears at the higher address outputs (A8 - A15) during direct addressing instruction execution. This allows the direct mode to be used at any place in memory, under program control. To ensure HD6800 compatibility, all bits of this register are cleared during processor reset. The hardware stack pointer (S) is used automatically by the processor during subroutine calls and interrupts. The stack pointers of the HD6309 point to the top of the stack, in contrast to the HD6800 stack pointer, which pointed to the next free location on the stack. The user stack pointer (U) is controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. Both stack pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support push and pull instructions. This allows the HD6309 to be used efficiently as a stack processor, greatly enhancing its ability to support higher level languages and modular programming. Index Registers (X, Y) The index registers are used in indexed mode addressing. The 16-bit address in this register takes Note: The stack pointers of the HD6309 point to the top of the stack, in contrast to the HD6800 stack pointer, which pointed to the next free location on stack. 15 X - Index Register Y - Index Register U - User Stack Po inter S - Hardware Stack Pointer PC A l B D " 0 } '·'-""'m" Program Counter Accumulators 7 0 ._I_____o_P_ _ _ ___,l Direct Page Register 7 0 I l l l l l I I I E F H 1 N Z V C CC - Condition Code Register Figure 1. Programming Model of The Microprocessing Unit 304 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Program Counter (PC) The program counter is used by the processor to point to the address of the next instruction to be executed by the processor. Relative addressing is provided allowing the program counter to be used like an index register in some situations. Condition Code Register (CC) The condition code register defines the state of the processor at any given time. See figure 2. Condition Code Register Description Bit 0 (C) Bit 0 is the carry flag. It is usually the carry from the binary ALU. C is also used to represent a 'borrow' from subtract-like instructions (CMP, NEG, SUB, SBC). Then, it is the complement of the carry from the binary ALU. Bit 1 (V)' Bit 1 is the overflow flag. It is set to a one by an operation which causes a signed two's complement arithmetic overflow. This overflow is detected in an operation in which the carry from the MSB in the ALU does not match the carry from the MSB minus 1. Bit 2 (Z) Bit 2 is the zero flag. It is set to one if the result of the previous operation was identically zero. Bit 3 (N) Bit 3 is the negative flag. It contains exactly the value of the MSB of the result of the preceding operation. Thus, a negative two's-complement result will leave N set to one. Bit 4 (I) Bit 4 is the IRQ mask bit. The processor will not recognize interrupts from the IRQ line if this bit is set to one. NMI, FIRQ, IRQ, RES, and SWI all set I to one; SWI2 and SWI3 do not affect I. Bit 5 (H) Bit 5 is the half-carry bit. It is used to indicate a carry from bit 3 in the ALU as a result of an 8-bit addition only (ADC or ADD). This bit is used by the DAA instruction to perform a BCD decimal add adjust operation. The state of this flag is undefined in all subtract-like instructions. Bit 6 (F) Bit 6 is the FIRQ mask bit. The processor will not recognize interrupts from the FIRQ line if this bit is a one. NMI, FIRQ, SWI, and RES all set F to one. IRQ, SWI2 and SWI3 do not affect F. Bit 7 (E) Bit 7 is the entire flag. Set to one, it indicates that the complete machine state (all the registers) was stacked, as opposed to the subset state (PC and CC). The E bit of the stacked CC is used on a return from interrupt (RTI) to determine the extent of the unstacking. Therefore, the current E left in the condition code register represents past action. E F H Carry Overflow ~---Zero .___ _ _ _ Negative ~------ IRQ Mask ~-------Half Carry ~-------- FIRQ Mask ~----------Entire Flag Figure 2. Condition Code Register Format .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 305 HD6309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signal Description Power (V88, Vcc) Two pins supply power to the part: Vss is ground or 0 volts, while Vee is +5.0 V ±10%. Address Bus (Ao - Ais) Sixteen pins output address information from the MPU onto the address bus. When the processor does not require the bus for a data transfer, it will output address FFFF16, R/W=high, and BS=low. This is a "dummy access" or VMA cycle (see figures 25 and 26). All address bus drivers are made high impedance when the bus available output (BA) is high. Each pin will drive one Schottky TTL load or four LS TTL loads, and typically 90 pF. Data Bus (Do - D1 ) Read/Write (R/W) This signal indicates the direction of data transfer on the data bus. A low indicates that the MPU is writing data onto the data bus. R/W is made high impedance when BA is high. Refer to figures 25 and 26. Reset (RES) A low level on this Schmitt-trigger input for greater than one bus cycle will reset the MPU, as shown in figure 3. The reset vectors are fetched from locations FFFEi6 and FFFF16 (table 2) when interrupt acknowledge is true, ( BA · BS= 1). During initial power-on, the reset line should be held low until the clock oscillator is fully operational. See figure 4. These eight pins provide communication with the system bi-directional data bus. Each pin will drive one Schottky TTL load or four LS TTL loads, and typically 130 pF. Because the HD6309 reset pin has a Schmitttrigger input with a threshold voltage higher than that of standard peripherals, a simple R/C network may be used to reset the entire system. This'higher Table 1. Pin Description Symbol Pin No. 1/0 Vss NMI 2 IRQ 3 FIRQ 4 BS, BA 5, 6 0 Vee 7 Ao -A1s 8-23 0 D1 -Do 24-31 1/0 R/W 32 0 DMA/BREQ 33 E, Q 34, 35 0 MRDY 36 RES 37 EXTAL, XTAL 38, 39 HALT 40 Function Ground Non maskable interrupt Interrupt request Fast interrupt request Bus status, Bus available + 5 V power supply Address bus, bits 0-15 Data bus, bits 0- 7 Read I Write output DMA Bus request Clock signal Memory ready Reset input Oscillator connection Halt input .HITACHI 306 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 threshold voltage ensures that all peripherals are out of the reset state before the processor. Halt (HALT) A low level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. When halted, the BA output is driven high indicating the buses are high impedance. BS is also high which indicates the processor is in the halt or bus grant state. While halted, the MPU will not respond to external realtime requests (FIRQ, IRQ) although DMA/BREQ will always be accepted, and NMI or RES will be latched for later response. During the halt state, Q and E continue to run normally. If the MPU is not running (RES), a halted state (BA · BS = 1) can be achieved by pulling HALT low while RES is still low. See figure 5. Bus Available, Bus Status (BA, BS) The BA output is an indication of an internal control signal which makes the MOS buses of the MPU high impedance. This signal does not imply that the bus will be available for more than one cycle. When BA goes low, an additional dead cycle will elapse before the MPU acquires the bus. The BS output signal, when· decoded with BA, represents the MPU state. Interrupt Acknowledge is indicated during both cycles of a hardware vector fetch (RES, NMI, FIRQ, IRQ, SWI, SWI2, SWl3). This signal, plus decoding of the lower four address lines, can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device. See Table 2. Sync Acknowledge is indicated while the MPU is waiting for external synchronization on an interrupt line. Halt/Bus Grant is true when the HD6309 is in a halt or bus grant condition. Non Maskable Interrupt (NMI) A negative edge on NMI requests that a nonmaskable interrupt sequence be generated. A nonmaskable interrupt cannot be inhibited by the program, and also has a higher priority than FIRQ, IRQ or software interrupts. During recognition of an NMI, the entire machine state is saved on the hardware stack. After reset, an NMI will not be recognized until the first program load of the hardware stack pointer (S). The pulse width of NMI low must be at least one E cycle. If the NMI input does not meet the minimum set up with respect to Q, the interrupt will not be recognized until the next cycle See figure 6. Table 2. Memory Map for Interrupt Vectors Memory Map for Vector Locations MS LS Interrupt Vector Description FFFE FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFFO FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF3 FFF1 RES NMI SWI IRQ FIRQ SWl2 SWl3 Reserved Table 3. MPU State Definition BA BS MPU State 0 0 0 1 1 0 1 Normal (Running) Interrupt or RESET Acknowledge SYNC Acknowledge HALT or Bus Grant .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 307 ::r: (Al 0 00 0 gO> :r: ~· :!. )> 3 ~r;· !":' ' ?- 0""'' 0 0~@· iii -:g- :I "~' ~ (fJ C') ~ :I c... 0 ~ () )> ~ ~ ~ .EB ~ a, ~ 0 . Vee 4.5V Q- + - - - f . I RES ~ ~4.·0~V· I 0.8 v ~ Add~:\\\\\\\~~ S 0.8 v I o.~ HtpcsR ~ v Data,....,...,,....~,.{l.,.....,..,...,"",............ -............,............v-......"""'r-"""'V-......"""'\r-"""'"V""""'"""'\~"""'"V"f~--..r-......-v......--..r-......-v............v-......-v.....,.....,v-......-v.....,......v-......"""'r-"""''\r"""'"""'\~"""'-..r Bus BA,,\\\\~ BS ,ss\\sssss:msm New PC New PC VMA First Hi Byte Lo Byte Instruction S , \ - - - - - - - - J f l_ _ _ _ _ _ _ _ _ _ _ _ _ _..., Instruction Figure 3. RES Timing ___ Vee _, E y 12 MHz 8 MHz 10~20 pF :!: 20% 10~20 pF :!: 20% 10~20 pF :!: 20% 10~20 pF :!: 20% AT Cut Parallel Resonance Crystal c0 =7 pF max Rs=60 n max HD6309 38 39 y D Cout Figure 4. Crystal Connections and Oscillator Start Up 2nd To Last last Cycle I· Cycle of Current j!nst. of Current Dead Inst., ,Cycle Dead lns::~~~0?nstruction Dead ..ff-----=Ha=lt=ed~-----r---C_yc_le--i·jr-----tj-Ex_e_c_ut_e"'l-c_v_c1_e~·ji-·~H=a=lt=ed~ Q HALT Address Bus BS Data Bus . . . - - - - ~---fr-------------------~~ lnstruction Opcode Figure 5. HALT and Single Instruction Execution for System Debug @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 309 lastCyde of Cummt Instruction Figure 6. IRQ and NMI Interrupt Timing Last Cycle of Current Instruction Instruction Fetch 14----+...--------lntorrupt Stocking and Vector Fetch Soquenco--------ii-----+i a Address_,.,..........,.....,,...~-..,....~~,,..~~.,..~~,,..~~,r~-,r~~,r~~,r~~,,~~~,~~-,~~....,.,....~-..,-- Bus VMA PCL PCH cc New PCH New PCL VMA R/W~ \.___ _ _ _..JI BA~~~~~~~~~~~~~~~~~~~~~~~~~~~- BS~.__~~~~~~~~~~~~--' E Figure 7. FIRQ Interrupt Timing 310 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Fast Interrupt Request (FIRQ) A low level on FIRQ input will initiate a fast interrupt sequence provided its mask bit (F) in the CC is clear. This sequence has priority over the standard interrupt request (IRQ). It is fast in the sense that it stacks only the contents of the condition code register and the program counter. The interrupt service routine should clear the source of the interrupt before doing an RTI. See figure 7. Interrupt Request (IRQ) A low level input on IRQ will initiate an interrupt request sequence provided the mask bit (I) in the CC is clear. Since IRQ stacks the entire machine state it provides a slower response to interrupts than FIRQ. IRQ also has a lower priority than FIRQ. Again, the interrupt service routine should clear the source of the interrupt before doing an RTL See figure 6. Note: NMI, FIRQ, and IRQ requests are sampled on the falling edge of Q. One cycle is required for synchronization before these interrupts are recognized. The pending interrupt(s) will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. lfIRQ and FIRQ do not remain low until completion of the current instruction they may not be recognized. However, NMI is latched and need only remain low for one cycle. XTAL,EXTAL These two pins are connected with parallel resonant fundamental crystal, AT cut. Alternately, the pin EXTAL may be used as a TTL level input for external timing with XTAL floating. The crystal or external frequency is four times the bus frequency. See figure 4. Proper RF layout techniques should be observed in the layout of printed circuit boards. Note for Board Design of the Oscillation Circuit: In designing the board, the following notes should be taken when the crystal oscillator is used. See figure 8. 1. Crystal oscillator and load capacity Cin, Cout must be placed near the LSI as much as possible. (Normal oscillation may be disturbed when external noise is induced to pin 38 and 39.) 2. Pin 38 and 39 signal line should be wired apart from other signal line as much as possible. Don't wire them in parallel with other Jines. (Normal oscillation may be disturbed when E or Q signal feeds back to pin 38 and 39.) 0 r--,.::.:....:::...:.::.,._~-4ICo7ir ch HD6309 Figure 8. Board Design of the Oscillation Circuit .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 311 HD6309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~- Designs to be Avoided: A signal line or a power source line must not cross or go near the oscillation circuit line as shown in figure 9 to prevent induction from these lines. The resistance between XTAL, EXTAL and other pins should be over 10 Mn. bus accesses. MRDY may also be used to stretch clocks (for slow memory) when bus control has been transferred to an external device (through the use of HALT and DMA/BREQ). MRDY also stretches E and Q during dead cycles. E,Q DMA Bus Request (DMA/BREQ) E is similar to the HD6800 bus timing signal <f>z: Q is a quadrature clock signal which leads E. Q has no parallel on the HD6800. Data is latched on the falling edge of E. Timing for E and Q is shown in figure 10. Memory Ready (MRDY) This input control signal allows stretching of E and Q to extend data-access time. E and Q operate normally while MRDY is high. When MRDY is low, E and Q may be stretched in integral multiples of half (1/2) bus cycles, thus allowing interface to slow memories, as shown in figure 11. The maximum stretch is 5 microseconds. During nonvalid memory access (VMA cycles) MRDY has no effect on stretching E and Q: this inhibits slowing the processor during "don't care" The DMA/BREQ input provides a method of suspending execution and acquiring the MPU bus for another use, as shown in figure 12. Typical uses include DMA and dynamic memory refresh. Transition of DMA/BREQ should occur during Q. A low level on this pin will stop instruction execution at the end of the current cycle. The MPU will acknowledge DMA/BREQ by setting BA and BS to high level. The HD6309 does not perform the auto-refresh executed in the HD6809. See figure 13. Typically, the DMA controller will request to use the bus by asserting DMA/BREQ pin low on the leading edge of E. When the MPU replies by setting BA and BS to one, that cycle will be a dead cycle used to transfer bus mastership to the DMA controller. Must be avoided. I \ <{ a:i '6 cg c: c: c";; '"Vi' I I 0 ------ I I ' Signal C I I h._XTAL : a 39 I--' : 38h ~E.X'TA~ L :I 'I' Cout C~i~~ HD6309 I I'' ' I'' ' ' Figure 9. Example of Normal Oscillation may be Disturbed 312 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-HD6309 False memory accesses may be prevented during dead cycles by developing a system DMAVMA signal which is low in any cycle when BA has changed. When BA goes low (a result of DMA/BREQ = high), another dead cycle will elapse before the MPU accesses memory, to allow transfer of bus mastership without contention. The DMA/BREQ input should be tied high during reset state. Q MRDY Start of Cycle I I End of Cycle ~Latch Data) I 1 E \o.av Ir--tAvs / \-o.av I I 0 : ""'v,....c-c--2-.0-_v ______\ ____,_:- - - - 1 I Figure 10. E/Q Relationship \ ________,/ \ \ \ o.av Vee - 2.0V Figure 11. MRDY Clock Stretching @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 313 MPU Operation During normal operation, the MPU fetches an instruction from memory and then executes the requested function. This sequence begins at RES and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Soft- ware instructions that alter normal MPU operation are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An interrupt, HALT or DMA/BREQ can also alter the normal execution of instructions. Figure 14 illustrates the flow chart for the HD6309. MPU 0 DEAD OMA DEAD MPU BA, BS ADDA (MPU) ADDA (DMAC) ------------< * DMAVMA is developed externally, but it is a system requirement for DMA. Figure 12. Typical DMA Timing IDEAD 1 I1 2 3 4 5 DMACvcles-------------------6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 E I I 0 I I BA, BS *DMAVMA is developed externally, but it is a system requirement for DMA. The HD6309 does not perform the auto-refresh executed in the HD6809. Figure 13. DMA Timing 314 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ::c ~ =. §' (1) ~· Ill ~ ~ 0 0 c~ ~ l.:.ca ~ ~ (1) - (/) gi 0:c ~'- ~ ~ ~ 1 i w ~ C11 RES Sea. 0--DP 1-+F, I 1-R,W ClrNMT Logic ~ CWA! HD6309 Interrupt Structure Bus State BA BS Running 0 0 Interrupt or Reset Acknowledge 0 Note: Asserting RES will result in entering the reset sequence from any point in the flow chart. Sync Halt/Bus Grant Figure 14. Flowchart for HD6309 Instruction 0 J: 0 ~ co Addressing Modes The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The HD6309 has the most complete set of addressing modes available on any microcomputer today. For example, the HD6309 has 59 basic instructions, however, it recognizes 1464 different variations of instructions and addressing modes. The addressing modes support modem programming techniques. The following addressing modes are available on the HD6309: · Implied (includes accumulator) · Immediate · Extended · Extended indirect · Direct · Register · Indexed - Zero-offset -Constant offset - Accumulator offset -Auto increment/decrement · Indexed indirect · Relative · Program counter relative Implied (Includes Accumulator) In this addressing mode, the opcode of the instruction contains all the address information necessary. Examples of implied addressing are: ABX, DAA, SWI, ASRA, and CLRB. Immediate Addressing In immediate addressing, the effective address of the data is the location immediately following the opcode (i.e., the data to be used in the instruction immediately follows the opcode of the instruction). The HD6309 uses both 8-and 16-bit immediate values depending on the size of the argument specified by the opcode. Examples of instructions with immediate addressing are: LDA #$20 LDX #$FOOO LDY #CAT Note: # signifies immediate addressing, $ signifies hexadecimal value. Extended Addressing In extended addressing, the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of extended addressing include: LDA CAT STX MOUSE LDD $2000 Extended Indirect As a special case of indexed addressing (discussed below), one level of indirection may be added to extended addressing. In extended indirect, the two bytes following the postbyte of an indexed instruction contain the address of the data. LDA (CAT] LDX ($FFFE] STU [DOG) Direct Addressing Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. This byte specifies the lower 8 bits of the address to be used. The upper 8 bits of the address are supplied by the direct page register. Since only one byte of address is required in direct addressing, this mode requires less memory and executes faster than extended addressing. Of course, only 256 locations (one page) can be accessed without redefining the contents of the DP register. Since the DP register is set to $00 on reset, direct addressing on the HD6309 is compatible with direct addressing on the HD6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are: LDA SETDP LDB LDD $30 $10 (Assembler directive) $1030 <CAT Note: < is 'an assembler directive which forces direct addressing. Register Addressing Some opcodes are followed by a byte that defines a register or set of registers to be used by the instruction. This is called a postbyte. Some examples of register addressing are: TFR EXG PSHS PULU X,Y Transfers X into Y A,B Exchanges A with B A,B,X, Y Push Y, X, B, and A onto S X,Y,D Pull D, X, and Y from U 316 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~HD6309 Indexed Addressing In all indexed addressing, one of the pointer registers (X, Y, U, S, and sometimes PC) is used in a calculation of the effective address of the operand to be used by the instruction. Five basic types of indexing are available and are discussed below. The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode as well as the pointer register to be used. Figure 15 lists the legal formats for the postbyte. Table 4 gives the assembler form and the number of cycles and bytes added to the basic values for indexed addressing for each variation. Zero-Offset Indexed: In this mode, the selected pointer register contains the effective address of the data to be used by the instruction. This is the fastest indexing mode. Examples are: LDD O,X LDA S Post-byte Register Bit Indexed Addressing 7 6 5 4 3 2 1 0 Mode 0 R R d d d d d EA = ,R +5 Bit Offset R R 0 0 0 0 0 ,R+ R R 0/1 0 0 0 ,R++ R R 0 0 0 0 ,-R R R p/1 0 0 ,--R R R I0/1 0 0 0 EA = ,R + 0 Offset R R p/1 0 0 EA = ,R + B Offset R R 0/1 0 0 EA = ,R + A Offset R R 0/1 0 0 0 EA = ,R + 8 Bit Offset R R 0/1 0 0 EA = ,R + 16 Bit Offset R R 0/1 x x 0/1 0 EA = ,R + D Offset 0 0 EA = ,PC + 8 Bit Offset x x 0/1 0 EA = ,PC + 16 Bit Offset 00 1 ...._,._..,._,.., L I d =Offset Bit X =Don't Care EA = L Address) Addressing Mode Field Indirect Field (Sign bit when b7 = 0) O·· ....... Non Indirect 1......... Indirect Register Field : RR 00 = x 01 = v 10 = u 11 = s Figure 15. Indexed Addressing Postbyte Register Bit Assignments $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 317 HD6309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~- Constant Offset Indexed: In this mode, a two's -complement offset and the contents of one of the pointer registers are added to form the effective address of the operand. The pointer register's initial content is unchanged by the addition. Three sizes of offsets are available: 5-bit (-16 to + 15) 8-bit (-128to+127) 16-bit (-32768 to+32767) the two bytes following the postbyte. In most cases the· programmer need not be concerned with the size of this offset since the assembler will select the optimal size automatically. Examples of constant-offset indexing are: LDA 23, x LDX -2, s LDY 300, x LDU CAT,Y The two's complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and cycles. The two's complement 8-bit offset is contained in a single byte following the postbyte. The two's complement 16-bit offset is in Accumulator Offset Indexed: This mode is similar to constant offset indexed except that the two's-complement value in one of the accumulators (A, B or D) and the contents of one of the pointer registers are added to form Table 4. Indexed Addressing Mode Non Indirect Indirect Type Forms Constant Offset From R (2's Complement Offsets) No Offset 5 Bit Offset 8 Bit Offset 16 Bit Offset Assembler Poatbyte + + Assembler Postbyte ++ Form OP Code - #Form OP Code -# ,R 1RR001000 0 [.R] 1RR10100 30 n,R · ORRnnnnn 1 0 defaults to 8-bit n,R 1RR01000 1 1 [n, R] 1RR11000 41 n,R 1RR01001 4 2 [n, R] 1RR11001 72 Accumulator Offset From R A Register Offset A,R (2's Complement Offsets) B Register Offset B,R 1RR001101 0 [A, R] 1RR00101 1 0 [B, R] 1RR10110 40 1RR10101 40 D Register Offset D,R 1RR01011 4 0 [D, R] 1RR11011 70 Auto Increment/Decrement R Increment By 1 ,R+ 1RROOOOO 2 0 not allowed Increment By 2 Decrement By 1 ,R++ ,-R 1RR00001 3 0 [.R++] 1RR10001 60 1RR0001020 not allowed Decrement By 2 ,--R 1RR00011 3 0 [.- -R] 1RR10011 60 Constant Offset From PC (2's Complement Offsets) 8 Bit Offset 16 Bit Offset n, PCR n, PCR 1xx01100 1 1 [n, PCR] 1xx01101 52 [n, PCR] 1xx11100 41 1xx11101 82 Extended Indirect 16 Bit Address R = x. v. u ors x = Don't Care RR: OO=X 01=Y 10=U 11 =S [n] 10011111 52 ;tandjindicate the number of additional cycles and bytes for the particular variation. 318 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · ·San Jose, CA 95131 · (408) 435-8300 the effective address of the operand. The contents of both the accumulator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time. auto increment/decrement by one, or a ±4-bit offset may have an additional level of indirection specified. In indirect addressing, the effective address is contained at the location specified by the contents of the index register plus any offset. In the example below, the A accumulator is loaded indirectly using an effective address calculated from the index register and an offset. Some examples are: Before Execution: LDA LDX LEAX B, y D, y B,X Auto Increment/Decrement Indexed: In the auto increment addressing mode, the pointer regis· ter contains the address of the operand. Then, after the pointer register is used it is incremented by one or two. This addressing mode is useful in stepping through tables, moving data, or for the creation of software stacks. In auto decrement,. the pointer register is decremented prior to use as the address of the data. The use of auto decrement is similar to that of auto increment; but the tables, etc, are scanned from high to low addresses. The size of the increment/decrement can be either one or two to allow for tables of either 8-or 16-bit data to be accessed, selectable by the programmer. The predecrement, post-increment nature of these modes allow them to be used to create additional software stacks that behave identically to the U and S stacks. Some examples of the auto increment/decrement addressing modes are: LDA STD LDB LDX ,X+ ,Y++ ,-Y ,--S Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the effective address. Consider the following instruction: STX 0, X + + (X initialized to 0) A= x x (don't care) X=$FOOO $0100 LDA [$10, X] EA is now $F010 $F010 $Fl $F01l $50 $Fl50 is now the new EA $Fl50 $AA After Execution: A=$AA (Actual Data Loaded) X=$FOOO All modes of indexed indirect are included except those which are meaningless (e.g., auto increment/ decrement by 1indirect). Some examples of indexed indirect are: LDA LDD LDA LDD [,X] [10,S] [B,Y] (,X++] Relative Addressing The byte(s) following the branch opcode is (are) treated as a signed offset which may be added to the program counter. If the branch condition is true then the calculated address (PC + signed offset) is loaded into the program counter. Program execution continues at the new location as indicated by the PC. Short (1 byte offset) and long (2 bytes offset) relative addressing modes are available. All of memory can be reached in long relative addressing as an effective address is interpreted modulo 216· Some examples of relative addressing are: The desired result is to store a 0 in locations $0000 and $0001 then increment X to point to $0002. In reality, the following occurs: 0-+temp X+2->X X->(temp) calculate the EA; temp is a holding register perform autoincrement do store operation Indexed Indirect CAT DOG BEQ BGT LBEQ LBGT CAT DOG RAT RABBIT (short) (short) (long) (long) RAT NOP RABBIT NOP All of the i.ndexing modes with the exception of @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 319 Program Counter Relative The PC can be used as the pointer register with 8 -or 16-bit signed offsets. As in relative addressing, the offset is added to the current PC to create the effective address. The effective address is then used as the address of the operand or data. Program counter relative addressing is used for writing position independent programs. Tables related to a particular routine will maintain the same relationship after the routine is moved, if referenced rela- tive to the program counter. Examples are: LDA LEAX CAT,PCR TABLE, PCR Since program counter relative is a type of indexing, an additional level of indirection is available. LDA [CAT, PCRJ LDU [DOG, PCRJ HD6309 Instruction Set The instruction set of the HD6309 is similar to that of the HD6800 and is upward compatible at the source code level. The number of opcodes has been reduced from 72 to 59, but because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) has risen from 197 to 1464. Some of the instructions and addressing modes are described in detail below: PSHU/PSHS The push instructions can push onto either the hardware -stack (S) or user stack (U) any single register, or set of registers with a single instruction. PULU/PULS The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following the push or pull opcode determines which register or registers are to be pushed or pulled. The actual PUSH/PULL sequence is fixed: each bit defines a unique register to push or pull, as shown in figure 16. Push/Pull Postbyte -CC A B ~----DP '------- x '-------~ y ·~------- SIU PC +-Pull Order Push Order-+ PC U Y X DP B A CC FFFF.. ·+-increasing memory address.. ·0000 PC S Y X DP B A CC Figure 16. Push and Pull Order 320 ¢i>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 TFR/EXG Within the HD6309, any register may be transferred to or exchanged with another of like-size: i. e., 8-bit to 8-bit or 16-bit to 16-bit. Bits 4-7 of the postbyte define the source register, while bits 0-3 represent the destination register (figure 17). They are denoted as follows: 0000-D 0001-X 0010-Y 0011-U 0100-S 0101-PC 1000-A 1001-B 1010-CC 1011-DP Note: All other combinations are undefined and invalid. LEAX/LEA Y/LEAU /LEAS The LEA (load effective address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction are illustrated in table 5. The LEA instruction also allows the user to access data in a position independent manner. For example: LEAX MSG!, PCR LBSR PDAT A(Print message routine) MSG! FCC 'MESSAGE' This sample program prints: 'MESSAGE'. By writing MSGl, PCR, the assembler computes the distance between the present address and MSGL This result is placed as a constant into the LEAX instruction which will be indexed from the PC value at the time of execution. No matter where the code is located, when it is executed, the computed offset from the PC will put the absolute address of MSGl into the X pointer register. This code is totally position independent. The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the aut6increment and autodecrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows: LEAa ,b+ 1. b--+temp 2. b + 1--+b 3. temp -+a (any of the 16-bit pointer registers X, Y, U, or S may be substituted for a and b) (calculate the EA) (modify b, postincrement) (load a) LEAa,-b 1. b - 1 -+temp 2. b -1 --+b 3. temp -+a (calculate EA with predecrement) (modify b, predecrement) (load a) Autoincrement-by-two and autodecrement-bytwo instructions work similarly. Note that LEAX, X + does not change X, however LEAX, - X does decrement X. LEAX 1, X should be used to increment X by one. MUL Multiplies the unsigned binary numbers in the A Transfer/Exchange Postbyte ;soyrce; j D~sti~atiqn j Figure 17. TFR/EXG Format Table 5. LEA Examples Instruction Operation Comment LEAX 10, X X+10-+X Adds 5-bit constant 10 to X LEAX 500, X X+500-+X Adds 16-bit constant 500 to X LEAY A, Y Y+A-+Y Adds 8-bit A accumulator to Y LEAY D, Y Y+D-+Y Adds 16-bit D accumulator to Y LEAU-10, U U-10-+U Subtracts 1O from U LEAS-10, S S-10-+S Used to reserve area on stack LEAS 10, S S+ 10-+S Used to 'clean up' stack LEAX 5, S S+5-+X Transfers as well as adds $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 321 and B accumulator and places the unsigned result into the 16-bit D accumulator. This unsigned multiply also allows multiple-precision multiplications. Long And Short Relative Branches The HD6309 has the capability of program counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8-or 16-bit signed offset is added to the value of the program counter to be used as the effective address. This allows the program to branch anywhere in the 64k memory map. Position independent code can be easily generated through the use of relative branching. Both short (8-bit) and long (16-bit) branches are available. SYNC After encountering a sync instruction, the MPU enters a sync state, stops processing instructions, and waits for an interrupt. If the pending interrupt is non-maskable ( NMI) or maskable (FIRQ, IRQ) with its mask bit (F or I) clear, the processor will clear the sync state and perform the normal interrupt stacking and service routine. Since FIRQ and IRQ are not edge-triggered, a low level with a minimum duration of three bus cycles is required to assure that the interrupt will be taken. If the pending interrupt is maskable (FIRQ, IRQ) with its mask bit (F or I) set, the processor will clear the sync state and continue processing by executing the next inline instruction. Figure 18 depicts sync timing. Software Interrupt A software interrupt instruction will cause an interrupt, and its associated vector fetch. These software interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SWI arf! available on this HD6309, and are prioritized in the following order: SWI, SWI2, SWI3. Last Cycle Sync of Previous Opcode Instruction Fetch Execute Sync Acknowledge (Sleep mode) Last Cycle of Sync Instruction Notes: 1. If the associated mask bit is set when the interrupt is requested, this cycle will be an instruction fetch from address location PC + 1.However if the interrupt is accepted (NMI or an unmasked FIRQ or IRQ) interrupt processing continues with this cycle as (m) on figures 6 and 7 (interrupt timing). 2. If mask bits are clear, IRQ and FIRQ must be held low for three cycles to guarantee that interrupt will be taken, although only one cycle is necessary to bring the processor out of SYNC. Figure 18. Sync Timing 322 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 16-Bit Operation The HD6309 has the capability of processing 16bit data. These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes and pulls. Cycle-by-Cycle Operation The address bus cycle-by-cycle performance chart illustrates the memory-access sequence corresponding to each possible instruction and address ing mode in the HD6309. Each instruction begins with an opcode fetch. While that opcode is being internally decoded, the next program byte is always fetched. (Most instructions will use the next byte, so this technique considerably speeds throughput.) Next, the operation of each opcode will follow the flow chart.VMA is an indication of FFFF16 on the address bus, R/W = high and BS = low. The following examples illustrate the use of the chart : see figure 19. Example 1: LBSR (Branch Taken) Before Execution SP = FOOO $8000 LBSR CAT $AOOO CAT Cycle-by-Cycle Flow Cycle# Address Data R/W Description 1 8000 17 1 Opcode Fetch 2 8001 lF 1 Offset High Byte 3 8002 FD 1 Offset Low Byte 4 5 6 7 8 FFFF FFFF FFFF FFFF EFFF 0****3 1 1 1 1 0 VMA Cycle VMA Cycle VMA Cycle VMA Cycle Stack Low Order Byte of Return Address 9 EFFE 80 0 Stack High Order Byte of Return Address Example 2: DEC (Extended) $8000 DEC $AOOO FCB $AOOO $80 Cycle-by-Cycle Flow Cycle# Address Data R/W Description 1 8000 7A 1 Opcode Fetch 2 8001 AO 1 Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 5 * FFFF 1 AOOO 80 1 VMA Cycle Read the Data 6 7 * FFFF 1 AOOO 7F 0 VMA Cycle Store the Decremented Data * The data bus has the data at that particular address. ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 323 I · Yes No 2nd Opcode NNNN+1 Direct BCC.BCS BEO.BGE BGT.BHI aHS,aLE aLO,aLS BLT,BMI BNE,BPL 1BRA,BRN 'aaSvRs,aVC -Low NNNN+1(21 Don't Care FFFF NNNN+1 Extended Immediate All Instructions Except ANDCC ORCC CWAI ANDCC DRCC Dau NNNN+1 Don't Care NNNN+2 c Y· No Yes No I Notes: 1. Each state sh?ows~~_.,...,.,,....,,......., Date Bus Offset High Address Bus NNNN + H2) 2. Address NNNN is location of opcode. 3. If opcode is two byte opcode subsequent addresses are in parenthesis ( ) . 4. Two-byte opcodes are highlighted. Figure 19. Cycle-by-Cycle Performance 324 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Implied A A ABX Don't Care NNNN+1 Don't Care FFFF ATS Don't Care FFFF ASLA/B ASRA/B CLRA/B COMA/B DAA DECA/B INCA/B LSLA/B LSRA/B NEGA/B NOP ROLA/B RORA/B SEX TSTA/B Don't Care NNNN+1 MUL Figure 19. Cycle-by-Cycle Performance (Cont.) ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 325 Register Al-~~~~~~~~~~~~~~~~--<,._~~~~~~~~~~~~~~~~~~~~~~~~--IA Don't Care FFFF Don't Care FFFF B B Figure 19. Cycle-by-Cycle Performance (Cont.) 326 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 J: ~ :!'. > 3 !5!?· ll> !:: ?- ~ 0 0 0~.· 10" ! J: ~ ::J - ffi ~~ gjt... - > 0 ~ ~ ~ .!!! ~ (A) I\) " " NoOffset I R+SBitl R+BBit R+168it Don't Care FFFF Don't Care FF"fF Indexed Post Byte NNNN+1(2) ---r- PC+S Bitl PC+16Bit Extended Indirect =t=: Don't Care mF' oo;;:-t Care FF!!__ I =r Don't Care --mF ~ Don't Care FF"fF Yes No Constant Offset No Offset 8-Bit Offset 16-Bit Offset Accumulator Offset A Register Offset B Register Offset 0 Register Offset Auto lncrementJDecremant Increment by 2 KDe:ZcrOemfffeenttobuynt2er Relative 16-Bit Offset Extended Indirect 16-Bit Address xxxx Pointer Register Pointer Register+ Offset Byte Pointer Register+Offset High Byte: Offset Low Byte Pointer Register+ A Register Pointer Register:+ B Register Pointer Register+ D Register Pointer Regm&r · Pointer Register-2 Program Counter+Offaet Byte Program Counter+Offset High Byte: Offset Low Byte Address High Byte: Address Low Byte c *Pointer Register is incremented following the indexed access. :c:x:: O> Figure 19. Cycle-by-Cycle Performance (Cont.) ~ co w cN o I ~· :!: )> 3 ~ 15· "'!p::. ~ a 0 mo0 i@· ~ :c ;! ~<t> :c (/) C') ~ c... @ ·("') )> ~"' ~ ~ a ~... ~ CD "g ' J: ~ c.> ~ c JMP ADCA/B ADDA/B ANDA/B BITA/B CMPA/B EORA/B STA/8 -LOO LOU LOX ml -STD 11111 STU STX ASL,ASR CLR,COM DEC, INC LSL,LSR NEG.ROL ROR TST LDA/B ORA/B SBCA/B SUBA/B JSR LEAS LEAU LEAX LEAY Don't Care FFFF Data EA _ Re_ gisE_teA_r(W_) _D_atEa _HAig_h Data Low EA+1 Don't Care FFFF Don't Care FFFF e r - - . . __ _ _ _ _..__ _ _ _ _~----~~----~~----~-----~~-----"-------'--------' Constant Offset No Offset 5-Bit Offset 8-Bit Offset 16-Bit Offset Accumulewr Offset A Register Offset B Register Offset O Register Offset Auto Increment/Decrement Increment by 1 Increment by 2 Decrement by 1 Decrement by 2 ;~;;(JffZtt"·er Relative 16.-Bit Offset ~ !2i!!£!. ~ Effective Address (EA) Pointer Register Pointer Register+ Post Byte Pointer Register+ Offset Byte Pointer Register+Offset High Byte: Offset Low Byte Pointer Register+ A Register Pointer Register+ B Register Pointer Register+ D Register Pointer Register"' Pointer Register· Pointer Register-1 Pointer Register-2 Program Counter+ Offset Byte Program Counter+Offset High Byte: Offset Low Byte Indirect High Byte: Indirect Low Byte Direct Page Register: Address Low Byte Address High Byte: Address Low Byte Immediate NNNN+1(2) * Pointer Register is incremented following the indexed access. Figure 19. Cycle-by-Cycle Performance (Cont.) Sleep Mode During the interrupt wait period in the SYNC instruction (the sync state) and in the CWAI instruction (the wait state), MPU operation is halted and goes to the sleep mode. However, the state of I/O pins is the same as that of the HD6809 in this mode. HD6309 Instruction set Tables The instructions of the HD6309 have been broken down into five different categories. They are as follows: - 8-Bit operation (table 6) · 16-Bit operation (table 7) · Index register/stack pointer instructions (table 8) · Relative branches (long or short) (table 9) · Miscellaneous instructions (table 10) HD6309 instruction set tables and Hexadecimal Values of instructions are shown in table 11 and table 12. Table 6. 8-Bit ·Accumulator and Memory Instructions Mnemonic(s) ADCA,ADCB ADDA,ADDB ANDA,ANDB ASL, ASLA, ASLB ASR, ASRA, ASRB BITA, BITB CLR, CLRA, CLRB CMPA, CMPB COM, COMA, COMB DAA DEC, DECA, DECB EORA. EORB EXG R1, R2 INC, INCA, INCB LDA, LDB LSL, LSLA, LSLB LSR, LSRA, LSRB MUL NEG, NEGA, NEGB ORA, ORB ROL, ROLA, ROLB ROR, RORA, RORB SBCA, SBCB STA, STB SUBA, SUBB TST, TSTA, TSTB TFR R1, R2 Operation Add memory to accumulator with carry Add memory to accumulator AND memory with accumulator Arithmetic shift of accumulator or memory left Arithmetic shift of accumulator or memory right Bit test memory with accumulator Clear accumulator or memory location Compare memory from accumulator Complement accumulator or memory location Decimal adjust A accumulator Decrement accumulator or memory location Exclusive OR memory with accumulator Exchange R1 with R2 (R1, R2=A, B, CC, DP) Increment accumulator or memory location Load accumulator from memory Logical shift left accumulator or memory location Logical shift right accumulator or memory location Unsigned multiply (Ax B-+D) Negate accumulator or memory OR memory with accumulator Rotate accumulator or memory left Rotate accumulator or memory right Subtract memory from accumulator with borrow Store accumulator to memory Subtract memory from accumulator Test accumulator or memory location Transfer R1 or R2 (R1, R2=A, B, CC, DP) Note: A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS, PULU) instructions . · HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 329 Table 7. 16-Bit Accumulator and Memory Instructions Mnemonic(s) ADDO CMPD EXG D, R LDD SEX STD SUBD TFR D, R TFR R, D Operation Add memory to D accumulator Compare memory from D accumulator Exchange D with X, Y, S, U or PC Load D accumulator from memory Sign Extend B accumulator into A accumulator Store D accumulator to memory Subtract memory from D accumulator Transfer D to X, Y, S, U or PC Transfer X, Y, S, U or PC to D Note: D may be pushed (pulled) to either stack with PSHS, PSHU (PULS, PULU) instructions. Table 8. Index Register/Stack Pointer Instructions Mnemonic(s) CMPS, CMPU CMPX, CMPY EXG R1, R2 LEAS, LEAU LEAX, LEAY LOS, LDU LDX, LDY PSHS PSHU PULS PULU STS, STU STX, STY TFR R1, R2 ABX Operation Compare memory from stack pointer Compare memory from index register Exchange D, X, Y, S, U or PC with D, X. Y, S, U or PC Load effective address into stack pointer Load effective address into index register Load stack pointer from memory Load index register from memory Push A, B, CC, DP, D, X, Y, U or PC onto hardware stack Push A, B, CC, DP, D, X, Y, Sor PC onto user stack Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack Pull A, B, CC, DP, D, X, Y, Sor PC from user stack Store stack pointer to memory Store index register to memory Transfer D, X, Y, S, U or PC to D, X, Y, S, U or PC Add B accumulator to X (unsigned) 330 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 9. Branch Instructions Mnemonic(s) BEQ, LBEQ BNE, LBNE BMI, LBMI BPL, LBPL BCS, LBCS BCC, LBCC BVS, LBVS BVC, LBVC BGT, LBGT BGE, LBGE BEQ, LBEQ BLE, LBLE BLT, LBLT BHI, LBHI BHS, LBHS BEQ, LBEQ BLS, LBLS BLO, LBLO BSR, LBSR BRA, LBRA BRN, LBRN Operation Simple Branches Branch if equal Branch if not equal Branch if minus Branch if plus Branch if carry set Branch if carry clear Branch if overflow set Branch if overflow clear Signed Branches Branch if greater (signed) Branch if greater than or equal (signed) Branch if equal Branch if less than or equal (signed) Branch if less than (signed) Unsigned Branches Branch if higher (unsigned) Branch if higher or same (unsigned) Branch if equal Branch if lower or same (unsigned) Branch if lower (unsigned) Other Branches Branch to subroutine Branch always Branch never Table 10. Miscellaneous Instructions Mnemonic(s) AND CC CWAI NOP ORCC JMP JSR RTI RTS SWI, SWl2, SWl3 SYNC Operation AND condition code register AND condition code register, then wait for interrupt No operation OR condition code register Jump Jump to subroutine Return from interrupt Return from subroutine Software interrupt (absolute indirect) Synchronize with interrupt line ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 331 Table 11. HD6309 Instruction Set Instruction/ Forms ABX HD6309 Addressing Modes Implied Direct Extended Immediate Indexed© Relative - OP # OP ~ # OP - # OP - # OP - # OP-@# 3A 3 1 Description B+x~x (Unsigned) 53 210 HN zvc · · · · · ADC ADCA ADCB 99 4 2 B9 5 3 89 2 2 A9 4+ 2+ 09 4 2 F9 5 3 C9 2 2 E9 4+ 2+ A+M+C~A B+M+C~B l I I JJ JJJ! I ADD ADDA ADDB ADDO AND ANDA ANDB AN DCC 9B 4 DB 4 03 6 94 4 04 4 2 BB 5 2 FB 5 2 F3 7 2 84 5 2 F4 5 3 BB 2 3 CB 2 3 C3 4 3 84 2 3 C4 2 1C 3 2 AB 4+ 2+ 2 EB 4+ 2+ 3 E3 6+ 2+ 2 A4 4+ 2+ 2 E4 4+ 2+ 2 A+M~A B+M~B D+M:M+1~D AAM~A BAM~B CCAIMM~cc I I I I I ·I l I I I I I JJ ·· ·· J I 0 I J0 1---0>----I ASL ASLA ASLB ASL ASR ASRA ASRB ASR BCC BCC LBCC 8CS BCS LBCS BEQ BEQ LBEQ BGE BGE LBGE BGT BGT LBGT BHI BHI LBHI BHS BHS LBHS BIT SITA BITS BLE BLE LBLE BLO BLO LBLO BLS BLS LBLS BLT BLT LBLT BMI BMI LBMI 48 2 58 2 47 2 57 2 1 1 08 6 1 1 07 6 95 4 05 4 2 78 7 2 77 7 2 B5 5 2 F5 5 3 3 3 85 2 3 C5 2 68 6+ 2+ A B !HI} IIII- IJ}-o M c b7 bO ®I I J J ®J l I J ®J J I J 67 6+ 2+ A~ } CffiITlTIJ.o b7 bO C 24 3 2 Branch C=O 10 5161 4 Long Branch 24 C=O ··· ® I I I @J J I ®J J J ·· ·· ·· ·· ·· 25 3 2 Branch C=1 10 5161 4 Long Branch 25 C=1 ·· ·· ·· ·· ·· 27 3 2 Branch Z=1 10 5161 4 Long Branch 27 Z=1 ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· 2C 3 2 Branch NEilV=O 10 5161 4 Long Branch 2C NEilV=O ·· ·· ·· ·· ·· 2E 3 2 Branch ZV(NEilVl=O 10 5161 4 Long Branch 2E ZV(NEJ)V)=O ·· ·· ·· ·· ·· 22 3 2 Branch CVZ= 0 10 5161 4 Long Branch 22 CVZ=O 24 3 2 10 5161 4 24 Branch C=O Long Branch C=O · · · · · · · · · · 2 A5 4+ 2+ 2 E5 4+ 2+ Bit Test A(MAA) Bit Test B(MAB) ·· ·· I I 0 I I0 ·· ·· ·· ·· ·· 2F 3 2 Branch ZV(NEIJV) = 1 10 5161 4 Long Branch 2F ZV(NEilV)=1 25 3 2 Branch C=1 10 5161 4 Long Branch 25 C=1 ·· ·· ·· ·· ·· 23 3 2 10 5161 4 23 Branch CVZ=1 Long Branch CVZ=1 · · · · · · · · · · ·· ·· ·· ·· ·· 2D 3 2 Branch NEBV= 1 10 5161 4 Long Branch 20 NEilV=1 28 3 2 Branch N=1 10 5161 4 Long Branch 2B N=1 ·· ·· ·· ·· ·· 332 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 11. HD6309 Instruction Set (Cont.) Instruction/ Forms BNE BNE LBNE BPL BPL LBPL BRA BRA LBRA BAN BAN LBRN BSA BSA LSSR BVC BVC LBVC BVS BVS LBVS CLR CLRA CLRB CLR CMP CMPA CMPB CMPD CMPS CMPU CMPX CMPY COM COMA COMB COM CWAI DAA DEC DECA DECB DEC EOR EORA EORS EXG INC Rl, R2 INCA INCB INC JMP JSR Implied OP - I 4F 2 1 SF 2 1 43 2 1 S3 2 1 19 2 1 4A 2 1 SA 2 1 1E 7 2 4C 2 1 SC 2 1 HD6309 Addreuing Modes Direct Extended lmmediete Indexed© Reletlve OP - # OP - I OP - I OP - I OP-@ I 26 3 2 10 5161 4 26 2A 3 2 10 5161 4 2A 20 3 2 16 s 3 21 3 2 10 5 4 21 SD 7 2 17 9 3 28 3 2 10 Sl61 4 28 29 3 2 10 Sl61 4 29 OF 6 91 4 01 4 10 7 93 11 7 9C 11 7 93 9C 6 10 7 9C 2 7F 7 2 2 B1 Fl s s 3 10 8 B3 3 11 8 BC 3 11 8 B3 2 BC 7 3 10 8 BC 3 3 81 2 3 C1 2 4 10 s 83 4 11 s 4 BC 11 s 83 3 SC 4 4 10 5 SC 6F 6+ 2+ 2 A1 4+ 2+ 2 E1 4+ 2+ 4 10 7+ 3+ A3 4 11 7+ 3+ AC 4 11 7+ 3+ A3 3 AC 6+ 2+ 4 10 7+ 3+ AC 03 6 2 73 7 3 63 6+ 2+ 3C ~20 2 OA 6 98 4 DB 4 2 7A 7 2 88 s 2 FS 5 3 3 3 c88s 2 2 6A 6+ 2+ 2 AS 4+ 2+ 2 ES 4+ 2+ oc 6 2 7C 7 3 OE 3 2 7E 4 3 9D 7 2 BD 8 3 6C 6+ 2+ 6E 3+ 2+ AD 7+ 2+ , 5 3 2 0 Description Branch Z=O Long Branch Z=O HNzv c ·· ·· ·· ·· ·· Branch N=O Long Branch N=O ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· Branch Always Long Branch Always ·· ·· ·· ·· ·· Branch Never Long Branch Never Branch to Subroutine Long Branch to Subroutine · · · · · · · · · · Branch V=O Long Branch V=O ·· ·· ·· ·· ·· Branch V= 1 Long Branch V=l ·· ·· ·· ·· ·· O-A o-B O-M 0 10 0 ·0 1 0 0 ·· 0 1 0 0 Compare M from A @ I I I I Compare M from B @ I Compare M:M+1 I · from D Compare M:M+1 I · from S Compare M:M+l I · from U Compare M:M+l I · from X Compare M:M+l I · fromY I I I I I I I I I I I I I I I I I I sA--sA M-M ··· I I 0 1 I I01 I I01 CC/\IMM-CC (except 1-EI (--0>-----1 · Wait for Interrupt Decimal Adjust A I I@I A-1-A B-1-B M-1-M A Ell M-A B Ell M-B I I I · · I I I ·· ·· I I I ·· ·· I I 0 I I0 R1-R2® (----@--) A+l-A B+l-B M+l-M I I I · · I I ·I ·· ·· I I I EA®-pc · ·· ·· ·· ·· Jump to Subroutine · $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 333 Table 11. HD6309 Instruction Set (Cont.) HD6309 Addressing Modes Instruction/ Forms LD LOA LDB LDD LDS LOU LOX LOY LEA LEAS LEAU LEAX LEAY LSL LSLA LSLB LSL LSR LSRA LSRB LSR MUL Implied OP~ # 4B 2 1 5B 2 1 44 2 1 54 2 1 30 11 1 Direct - OP # 96 4 2 06 4 2 DC 5 2 10 6 3 DE DE 5 2 9E 5 2 10 6 3 9E 08 6 2 04 6 2 Extended - OP # 86 5 3 F6 5 3 FC 6 3 10 7 4 FE FE 6 3 BE 6 3 10 7 4 BE 7B 7 3 74 7 3 Immediate Indexed© Relative OP ~ # OP - # OP-@ # 86 2 C6 2 cc 3 10 4 CE CE 3 BE 3 10 4 BE 2 A6 4+ 2+ 2 E6 4+ 2+ 3 EC 5+ 2+ 4 10 6+ 3+ EE 3 EE 5+ 2+ 3 AE 5+ 2+ 4 10 6+ 3+ AE 32 4+ 2+ 33 4+ 2+ 30 4+ 2+ 31 4+ 2+ 68 6+ 2+ 64 6+ 2+ Description M~A M~B M:M+1~D M:M+1-·S M:M+1~U M:M+1~X M:M+1~Y EA®~s EA®~u EA®~x EAlJJ~y A B D-!} IIIJ- IIl}-o M c b7 bO A B } o-I-TIJIIIlHJ M b7 bO c Axs~o (Unsigned) 532 10 H N z vc I I0 · · I I 0 · · I I 0 ·· ·· I I 0 I I0 · · I I 0 ·· ·· I I 0 · · · · · · · · ··I I · · · · · · · · ··· I I I I I I I I I I I I 0 I I · · 0 J J ·· ·· 0 J J ·· J ·® NEG NEGA NEGB NEG NOP OR ORA ORB ORCC PSH PSHS PSHU 40 2 1 50 2 1 00 6 2 70 7 3 60 6+ 2+ 12 2 1 9A 4 DA 4 34 5+1 2 36 5+ ~ 2 2 BA 5 2 FA 5 3 BA 2 3 CA 2 lA 3 2 AA 4+ 2+ 2 EA 4+ 2+ 2 A+1~A B+l~B M+1~M No Operation AVM~A BVM~B CCVIMM~cc Push Registers on S Stack Push Registers on U Stack ®I I J I ®I I J I ®I J I J · · · · · ·· ·· I I 0 J J0 (-----(j)------) · · · · · · · · · · PUL PULS PULU ROL ROLA ROLB ROL ROR RORA RORB ROR RTI RTS 35 5+'.1-: 2 37 5+:~ 2 49 2 1 59 2 1 09 6 2 79 7 3 46 2 1 56 2 1 06 6 2 76 7 3 38 6/15 1 39 5 1 69 6+ 2+ 66 6+ 2+ Pull Registers from S Stack Pull Registers from U Stack (------(@--) (------(@--) · ~ } l(@fill]J ·· M c~o ) I JI I ) I J I I ) I · · A } LO=OJI[j]}J ·· ·· MB c - b7 - bO I ) I I I I I I J Return from Interrupt (-----(j)------) Return from Subroutine · · · · · SBC SBCA SBCB SEX ST STA STB STD STS STU STX STY 1D 2 92 4 02 4 1 2 82 5 2 F2 5 3 82 2 3 C2 2 2 A2 4+ 2+ 2 E2 4+ 2+ 97 4 2 87 5 3 D7 4 2 F7 5 3 DD 5 2 FD 6 3 10 6 3 10 7 4 DF FF DF 5 2 FF 6 3 9F 5 2 BF 6 3 10 6 3 10 7 4 9F BF A7 4+ 2+ E7 4+ 2+ ED 5+ 2+ 10 6+ 3+ EF EF 5+ 2+ AF 5+ 2+ 10 6+ 3+ AF A-M-C~A B-M-C~B Sign Extend B into A A~M B~M D~M:M+1 S~M:M+l U~M:M+1 x~M:M+1 Y~M:M+l ®I I I I ®) I I I · I J ·· J ) 0 · · I I 0 · · ) I 0 ·· ·· I ) 0 I J0 · · ) I 0 ·· ·· I ) 0 334 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 11. HD6309 Instruction Set (Cont.) Instruction/ Forms SUB SUBA SUBB SUBD SWI sw1® sw12® sw13® SYNC Implied - OP # 3F 19 1 10 20 2 3F 11 20 2 3F 13 ~4 1 HD6309 Addreasing Modes Direct Extended Immediate Indexed® Relative - - - - OP # OP # OP # OP # OP-@ # 90 4 DO 4 93 6 2 BO 5 2 FO 5 2 B3 7 3 3 cBoO 2 2 3 83 4 2 AO 4+ 2+ 2 EO 4+ 2+ 3 A3 6+ 2+ Description 5 3 2 10 H N zvc A-M-A @I I I I B-M-B D-M:M+l-D ·@ I I I I I I I I ·· ·· ·· ·· Software Interrupt 1 · Software Interrupt 2 · · · · · Software Interrupt 3 · · · · · · Synchronize to Interrupt TFR R1, R2 TST TSTA TSTB TST 1F 6 2 4D 2 1 5D 2 1 OD 6 2 7D 7 3 6D 6+ 2+ R1-R2® Test A Test B Test M 1----®--I I I0 · · I I 0 ·· ·· I I 0 Legend: OP + x M H N Operation Code (Hexadecimal) Number of MPU Cycles Number of Program Bytes Arithmetic Plus Arithmetic Minus Multiply Complement of M Transfer Into Half-carry (from bit 3) Negative (sign bit) z Zero (byte) v Overflow, 2's complement c Carry from bit 7 Test and set if true, cleared otherwise · Not Affected cc Condition Code Register Concatenation v Logical or /\ L.Ogical and E!l Logical Exclusive or Notes: CD This column gives a base cycle and byte count. To obtain total count, and the values obtained from the Indexed Addressing Modes table. @ R1 and R2 may be any pair of 8-bit or any pair of 16-bit registers. The 8-bit registers are: A, B, CC, DP The 16-bit registers are: X, Y, U, S, D, PC @ EA is the effective address. @The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled. ® 5161 means: 5 cycles if branch not taken, 6 cycles if taken. @ SWI sets I and F bits. SWl2 and SWl3 do not affect I and F. (])Conditions Codes set as a direct result of the instruction ® Value of half-carry flag is undefined. ® Special Case-Carry set if b7 is SET. @> Condition Codes set as a direct result of the instruction if CC is specified, and not affected otherwise. ~HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 335 Table 12. Hexadecimal Values of Machine Codes OP Mnem 00 NEG 01 * 02 * 03 COM 04 LSR 05 * 06 ROR 07 ASR OS ASL, LSL 09 ROL OA DEC OB oc * INC OD TST OE JMP OF CLR Mode Direct Direct -# 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 3 2 6 2 OP Mnem 30 LEAX 31 LEAY 32 LEAS 33 LEAU 34 PSHS 35 PULS 36 PSHU 37 PULU 38 * 39 RTS 3A ABX 3B RTI 3C CWAI 30 MUL 3E * 3F SWI Mode -# OP Mnem Indexed t Indexed 4+ 2+ 60 NEG * 4+ 2+ 61 * 4+ 2+ 62 4+ 2+ 63 COM Implied 5+ 2 64 LSR I 5+ 5+ 5+ 5 2 2 2 1 3 1 65 * 66 ROR 67 ASR 68 ASL, LSL 69 ROL 6A DEC Implied lmmed 6, 15 1 «20 2 6B * 6C INC Implied 11 1 60 TST 6E JMP Implied 19 1 6F CLR 10 See 11 Next Page 12 NOP 13 SYNC - - Implied Implied -- -- 2 1 ;,;4 1 40 NEGA 41 * 42 * 43 COMA Implied 2 1 2 1 14 * 15 * 16 LBRA 44 LSRA 45 * Relative 5 3 46 RORA 2 1 2 1 17 LBSR Relative 9 3 47 ASRA 2 1 18 * 19 DAA 4B ASLA, LSLA Implied 2 1 49 ROLA 2 1 2 1 1A ORCC lmmed 3 2 4A DECA 2 1 18 * 1C AN DCC 4B * lmmed 3 2 4C INCA 2 1 10 SEX Implied 2 1 40 TSTA 2 1 1E EXG 1F TFR t * B 2 4E Implied 6 2 4F CLRA Implied 2 1 20 BRA Relative 3 2 50 NEGB Implied 2 1 21 BRN 22 BHI 23 BLS * 3 2 51 * 3 2 52 3 2 53 COMB 2 1 24 BHS, BCC 3 2 54 LSRB 2 1 25 BLO, BCS 26 BNE * 3 2 55 3 2 56 RORB 2 1 27 BEO 3 2 57 ASRB 2 1 2B BVC 3 2 5S ASLB, LSLB 2 1 29 BVS 3 2 59 ROLB 2 1 2A BPL 3 2 5A DECB 2 1 28 BMI 2C BGE * 3 2 58 3 2 5C INCB 2 1 20 BLT 2E BGT 2F BLE 3 2 50 TSTB ' 3 Relative 3 2 2 5E * 5F CLRB 2 1 Implied 2 1 Legend: Number of MPU cycles (less possible push pull or indexed-mode cycles) Number of program bytes * Denotes unused opcode 70 NEG 71 * 72 * 73 COM 74 LSR 75 * 76 ROR 77 ASR 7B ASL, LSL 79 ROL 7A DEC * 7B 7C INC 70 TST 7E JMP 7F CLR so SUBA B1 CMPA S2 SBCA S3 SUBD B4 ANDA S5 BITA S6 LOA S7 * BS EORA B9 ADCA BA ORA BB ADDA BC CMPX SD BSR SE LOX SF * Mode Indexed -# 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ Indexed 6+ 2+ 6+ 2+ 3+ 2+ 6+ 2+ Extended 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 4 3 Extended 7 3 lmmed 2 2 2 2 2 2 4 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Im med 4 3 Relative 7 2 Im med 3 3 336 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 12. Hexadecimal Values of Machine Codes (Cont.) OP Mnem Mode ~ # OP Mnem 90 SUBA 91 CMPA 92 SBCA 93 SUBD 94 ANDA 95 BITA 96 LOA 197 STA 9B EORA 99 ADCA 9A ORA 98 ADDA 9C CMPX 90 JSR 9E LOX 9F STX AO SUBA A1 CMPA A2 SBCA A3 SUBD A4 ANDA A5 BITA A6 LOA A7 STA AB EORA A9 ADCA AA ORA AB ADDA AC CMPX AD JSR AE LOX AF STX BO SUBA B1 CMPA B2 SBCA 83 SUBD 84 ANDA B5 BITA B6 LOA B7 STA 88 EORA B9 ADCA BA ORA BB ADDA BC CMPX BO JSR BE LOX BF STX co SUBB C1 CMPB C2 S8CB C3 ADDO C4 ANDB C5 BITB Direct 4 2 C6 LOB * 4 2 C7 4 2 CB EORB 6 2 C9 ADCB 4 2 CA ORB 4 2 CB ADDB 4 2 cc LOO * 4 2 CD 4 2 CE LOU * 4 2 CF 4 2 4 2 DO SUBB 6 2 01 CMPB 7 2 02 S8CB 5 2 03 ADDO Direct 5 2 04 ANDB 05 81TB Indexed 4+ 2+ 06 LOB 4+ 2+ 07 STB 4+ 2+ DB EORB 1 6+ 2+ 09 ADCB 4+ 2+ DA ORB 4+ 2+ DB ADDB 4+ 2+ DC LDD 4+ 2+ DD STD 4+ 2+ DE LOU 4+ 2+ OF STU 4"- 2+ 4+ 2+ EO SUBB 6+ 2+ E1 CMPB 7+ 2+ E2 SBCB j 5+ 2+ E3 ADDO Indexed 5+ 2+ E4 ANDB E5 BIT8 Extended 5 3 E6 LOB 5 3 E7 STB 5 3 EB EORB 7 3 E9 ADCB 5 3 EA ORB ' 5 3 EB ADDB 5 3 EC LOO 5 3 ED STD 5 3 EE LOU 5 3 EF STU 5 3 5 3 FD SUBB 7 3 F1 CMPB 8 3 F2 SBCB 6 3 F3 ADDO Extended 6 3 F4 ANDB F5 BITB Im med 2 2 F6 LOB I 2 2 4 2 2 2 3 2 F7 STB FB EORB F9 ADCB FA ORB Im med 2 2 F8 ADDB Note: All unused opcodes are both undefined and illegal. Mode ~ # OP Mnem Mode ~ # Immed 2 2 FC LOO Extended 6 3 FD STD 2 2 FE LOU t 6 3 6 3 2 2 FF STU Extended 6 3 2 2 2 2 3 3 2 Bytes Opcode lmmed 3 3 Direct ~ Direct 4 2 4 2 4 2 6 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 5 2 5 2 5 2 5 2 Indexed Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ Extended 5 3 5 3 5 3 7 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 Extended 5 3 1021 L8RN 1022 L8HI 1023 L8LS 1024 LBHS, LBCC 1025 L8CS, L8LO 1026 L8NE 1027 LBEQ 1028 LBVC 1029 LBVS 102A L8PL 1028 LBMI 102C LBGE 102D LBLT 102E LBGT 102F LBLE 103F SWl2 1083 CMPD 108C CMPY 108E LOY 1093 CMPD 109C CMPY 109E LDY 109F STY 10A3 CMPD 10AC CMPY 10AE LDY lOAF STY 1083 CMPD lOBC CMPY 108E LOY 108F STY 10CE LOS 10DE LDS lOOF STS 10EE LDS lOEF STS 10FE LDS lOFF STS 113F SWl3 1183 CMPU 118C CMPS 1193 CMPU 119C CMPS 11A3 CMPU 1lAC CMPS 1183 CMPU 11BC CMPS Relative Relative Implied lmmed *lmmed Direct t Direct Indexed t Indexed Extended t Extended lmmed Direct Direct Indexed Indexed Extended Extended Implied lmmed lmmed Direct Direct Indexed Indexed Extended Extended 5 4 5161 4 5161 4 5161 4 5161 4 5161 4 5161 4 5161 4 5161 4 5161 4 5(61 4 5161 4 5161 4 5161 4 5161 4 20 2 5 4 5 4 4 4 7 3 7 3 6 3 6 3 7+ 3+ 7+ 3+ 6+ 3+ 6+ 3+ 8 4 8 4 7 4 7 4 4 4 6 3 6 3 6+ 3+ 6+ 3+ 7 4 7 4 20 2 5 4 5 4 7 3 7 3 7+ 3+ 7+ 3+ 8 4 8 4 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 337 Note for Use Compatibility with NMOS MPU (HD6809) The difference between HD6309 (CMOS) and HD6809 (NMOS) is shown in table 13. Execution Sequence of CLR Instruction Cycle-by-cycle flow of CLR instruction (direct, extended, indexed addressing mode) is shown below. In this sequence the contents of the memory location specified by the operand is read before writing 00 into it. Note that status flags, such as IRQ Flag, will be cleared by this extra data read operation when accessing the control/status register (sharing the same address between read and write) of peripheral devices. Example: CLR (Extended) $8000 CLR $AOOO FCB $AOOO $80 Cycle# Address Data R/W Description 1 8000 7F Opcode Fetch 2 8001 AO Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 5 FFFF AOOO * 1 80 1 VMA Cycle Read the Data 6 7 FFFF AOOO * 1 00 0 VMA Cycle Store Fixed 00 into Specified Location * The data bus has the data at that particular address. Table 13. Difference between HD6309 and HD6809 Item MADY Stretch Unit HD6309 (CMOS) integral multiples of half (1/2) bus cycles HD6809 (NMOS) integral multiples of quarter (1 /4) bus cycles 1/2 cycle E~ 1/4 cycle :~ tpcsM MRDY Stretch Time DMA/BREQ Auto-refresh External Clock Input 5µs max None XTAL floating 10µs max Executed XTAL grounded XTAL floating EXTAL 4x CLK 338 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Application Note for System Design At the trailing edge of the address bus, the noise pulses may appeare on the output signals in HD6309. Note the noise pulses and the following measures against them. Noise Occurrence Condition: As shown in figure 20, the noise pulses which are 0.8 V or over may appear on E and Q clocks when the address bus changes from high to low. If the address buses (Ao -A15, and R/W) change from high to low, the transient current flows through the GND. The noise pulses are generated on the LSI's Vss pins according to the current and to the impedance state of the GND wirings. Figure 21 shows the noise voltage dependency on the each parameter. Figure 23 shows the noise voltage dependency on the load capacitance of the address bus. Note: The noise level should be carefully checked because it depends on the each parameter of actual application system. Noise Reduction: 1. Control each parameter such as Cd, V cc. Zg in figure 21, and the noise level is reduced to be allowable. 2. Insert a bypass capacitor between the Vee and the GND of the HD6309. 3. Connect the CMOS buffer with noise margin to E and Q clocks. 4. Insert the damping registors to the address bus. That is effective for the noise level to reduce less than 0.8 V. The damping resistor is about 40-50 0 on the higher byte of the address bus (A 15 A8 )and about 130-140 0 on the lower byte of the address bus (A7 - A0 ), and R/W as shown in figure 22. Electrical characteristics do not change by inserting the damping resistors. E Q Ao-A1s R/W Test condition T, = -20'C Vcc=5.5V Noise~ A I \__ Noise peek (worst case) : about 1.0V Number of address bus lines switching from High to Low = 17 (Address bus $FFFF->$0000) R/W High->Low Figure 20. Noise at Address Bus Output Changing V, Noise Voltage Z0 GND Impedance C0 Address bus load capacitance N Number of address bus lines switching from H to L Figure 21. Dependency of the Noise Voltage on Each Parameter @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 339 Damping Resistors \ -""'~-Ao 130-140Q -'""'---'A1 Ae -,'""--.As -v" "--.A10 A11 A12 (Top view) }40-50Q Figure 22. Connecting Damping Resistors to Address Bus (V) 1.0 >., Cl ~ > ".!!l z 0 0.5 0 Conditions Ta = 25°C Zg = 0 N = 17 Maximum Capaci- ) tCd = 90 pF (tance of HD6309 Specification Vcc=5.0V ___ Vcc=4.5V i -·-Connecting --·/' - - rI ..-----· I I Damping Resistors (Vcc=5 V) ./ I / I I I I I I I I I I 50 100 (pF) Address Bus Load Capacitance Cd Figure 23. Dependency of the Noise Voltage on the Load Capacitance of the Address Bus 340 @HITACHI Hitachi America Ltd. · 2210 O"Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Absolute Maximum Ratings Item Supply Voltage Input Voltage Maximum Output Current Maximum Total Output Current Operating Temperature Storage Temperature Symbol Vee 1 V;n1 l1ol 2 l~1ol 3 Topr Tst9 Value -0.3 to +7.0 -0.3 to + 7.0 5 100 -20to+75 -55 to + 150 HD6309 Unit v v mA mA "C °C Notes: 1 .·With respect to Vss (system GND) 2. Maximum output current is the maximum currents which can flow out from one output terminal and 1/0 common terminal (Ao -A, 5· R;W, Do -D7' BA, BS, Q, El. 3. Maximum total output current is the total sum of output currents which can flow out simultaneously from output terminals and 1/0 common terminals (Ao -A 15, R;W, Do -D 7 , BA, BS, Q, El. 4. Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. Recommended Operating Conditions Item Symbol Min Typ Supply Voltage 4.5 5.0 Input Voltage EXT AL -0.3 Other Inputs -0.3 EXT AL Other In puts Operating Temperature Note: 1. With respect to Vss (system GNDI Vee XO. 7 2.0 -20 25 Max 5.5 0.6 0.8 Vee Vee Vee 75 Unit v v v v v v "C @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 341 HD6309 Electrical Characteristics DC Characteristics (Vee=5.0 V ± 10%, V88=0 V, Ta= -20 to +75'C, unless otherwise noted.) HD63B09 HD63C09 Item Symbol Min Typ Max Min Typ Max Unit Test Condition Input High Voltage RES V1H Vcc-0.5 Vee Vec-0.5 Vee v EXT AL Vccx0.7 Vee Vccx0.7 Vee Other Inputs Input Low Voltage EXT AL VIL Other Inputs Input Leakage Current Except EXTAL, l;n XTAL 2.0 -0.3 -0.3 -2.5 Vee 2.0 0.6 -0.3 0.8 -0.3 2.5 -2.5 Vee 0.6 v 0.8 2.5 µA V;n =Oto Vee. Vcc=max Three State (Off State) D0 -D 7 lrs1 Input Current A0 -A15, RfiJ Output High Voltage Do-D1 VoH -10 -10 4.1 10 -10 10 -10 4.1 10 µA 10 v V;n =0.4 to Vee. Vcc=max ILoAo= -400µA Vcc-0.1 Vcc-0.1 tOAD;:>-10µA A0 -A15 , RfiJ, 4.1 4.1 ILoAo= -400µA Q, E Vcc-0.1 Vcc-0.1 ILOAD;:; -10µA BA, BS 4.1 4.1 ILOAD = -400µA Output Low Voltage Vcc-0.1 Vcc-0.1 ILOAD;:>-10µA VoL 0.5 0.5 v ILOAo=2mA Input Capacitance Do-D1 ~n Except D0 -D1 15 15 pF V;n =OV, Ta =25'C, 10 10 f=1MHz Output Capacitance Ao-A15, R/W, Cout BA, BS 12 12 pF Current Dissipation Ice 24 36 mA Operating 15 18 Sleeping @HITACHI 342 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6309 AC Characteristics (Vcc=5.0 V ± 10%, V8s=O V, Ta= -20 to +75"C, unless otherwise noted.) Clock Timing HD63B09 HD63C09 Item Frequency of Operation (Crystal External Input) Cycle Time Total Up Time Processor Clock High Processor Clock Low E Rise and Fall Time ~ow to Otiigh Time Q Clock High Q Clock Low Q Rise and Fall Time ~ow to ELow Time Symbol fxTAL 1;,yc 1:ur ti>vltEH ti>vltEL fe,, fet 1Avs ti>vltOH ti>vltoL to,, tot toe Min Typ Max Min Typ Max Unit Test Condition 2 8 2 12 MHz Figs. 25, 26 500 2000 333 2000 ns 480 310 ns 220 5000 140 5000 ns 210 1000 140 1000 ns 20 20 ns 100 140 70 100 ns 220 1000 140 1000 ns 220 5000 140 5000 ns 20 20 ns 100 70 ns Bus Timing HD63B09 HD63C09 Item Symbol Address Delay Peripheral Read Access Time (tur-!Ao-tosR = 1Accl Data Set Up Time (Read) Input Data Hold Time Address Hold Time Ta=O to +75"C Ta=-20 to O"C Data Delay Time (Write) Output Hold Time Ta=O to +75'C Ta=-20to0'C !Ao tAcc foSR foHR 1AH to ow foHW Min Typ Max Min Typ Max Unit Test Condition 110 110 ns Figs. 25, 26 330 160 ns 40 40 ns 10 10 ns 20 20 ns 10 10 110 70 ns 30 30 ns 20 20 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 343 HD6309 Processor Control Timing Item Symbol MRDY Set Up Time MRDY Set Up Time 2 1PcsM 1PCSM2 Interrupts Set Up Time 1Pcs HALT Set Up Time 1PcsH RES Set Up Time 1PcsR DMA/BREO Set Up Time 1Pcso Processor Control Rise and Fall Timetpc,. 1Pct Crystal Oscillator Start Time ~c HD63B09 HD63C09 Min Typ Max Min Typ Max Unit Test Condition 110 70 ns Figs. 3 - 7 240 160 ns Figs. 11, 12 110 70 ns 110 70 ns 110 110 ns 110 70 ns 100 100 ns 20 20 ms 5.0V · C= 30 pF (BA, BS) 130 pF (00 -0 7 , E, Q) 90 pF (Ao -A15, R;W) · R= 10k0 (Do-D7) 10 kO (Ao -A15 , E, Q, R;W) 10 kO (BA, BS) All diodes are 1S2074<8l or equivalent. C includes stray capacitance. Figure 24. Bus Timing Test Load 344 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 E Vee - 2.0V Q A/W ADDA Vee - 2.0V BA, BS O.BV o.sv Vee - 2.0V Vee - 2.0V -----tPWEH _ _ ___. O.BV Vee - 2.0V ~ NotValid Figure 25. Read Data from Memory or Peripherals ------------tcyc------------,... E te. ADDA Vee - 2.0V BA.BS ~O~.B~V!.;:;;""f=-~-..:::o,_;;;:::.-1--~~~~~---,~~~~~~~-==-!4~ ~ NotValid Figure 26. Write Data to Memory or Peripherals ~HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 345 Package Dimensions DP-40 52.8(2.079) 40 54.0max. (2. I 26max.) 21 2.54±0.25 (OTo(i±o.010) .E ·~ . ~ ~-~ ~~ ci 8 ~~ 0.48±0. l .~ .E (0.019±0.004)~ ~ o·~ 15· e Unit : mm (inch) CP-44 17 53±0 12(0690±0 005) "g' 7 0 +I $ ~ I 4~M' 40 0 39 >WW 18 28 "g ' 16.58(0 653) 6 +1 0 0 '__, b~±OS~0±0,~20) 346 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 347 HD63B09E,HD63C09E--CMOS MPU (Micro Processing Unit} Tue HD6309E is the highest 8-bit microprocessor of HMCS6800 family, which is just compatible with the conventional HD6809E. Tue HD6309E has hardware and software features which make it an ideal processor for higher level language execution or standard controller applications. External clock inputs are provided to allow synchronization with peripherals, systems or other MPl.Js. Tue HD6309E is complete CMOS device and the power dissipation is extremely low. Moreover, the SYNC and CWAI instruction makes low power application possible. · FEATURES · Hardware - Interface with All HMCS6800 Peripherals · Software - Object Code Compatible with the HD6809E · low Power Consumption Mode (Sleep mode) SYNC state of SYNC Instruction WAIT state of CWAI Instruction · External Clock Inputs, E and 0, Allow Synchronization · Wide Operation Range f = 0.5 to 3MHz (Vcc=5V±10%) Type No. HD63809E HD63C09E Bus Timing 2.0MHz 3.0MHz HD63809EP, HD63C09EP (DP-40) · PIN ARRANGEMENT BA Vee Ao A, A, HD6309E A, A, A, A, A, A, HAIT" TSC LIC RES AVMA a E BUSY R/W Do o, o, D, D, D, D, o, Au A" Au (Top View) 348 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Maximum Output Current Maximum Total Output Current Operating Temperature Storage Temperature Symbol .Vee* Vin llol** l~lol*** Topr Ts1g Value -0.3- +7.0 -0.3-+7.0 5 100 -20-+75 -55-+150 Unit v v mA mA oc oc *With respect to Vss (SYSTEM GND) ··Maximum output current is the maximum currents which can flow out from one output terminal and J/0 common terminal. (Ao - A,., R/W, Do - D,, BA, BS, LIC, AVMA, BUSY) *** Maximum total output current is the total sum of output currents which can flow out simultaneously from output terminals and 1/0 common terminals. IA0 - Au, R/W, D0 - D,, BA, BS, LIC, AVMA, BUSY) (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · RECOMMENDED OPERATING CONDITIONS Item Supply Voltage Logic, RES Input Voltage E,O Logic E,O RES Operating Temperature Symbol .Vee ..V1L min 4.5 -0.3 V1Le -0.3 typ 5.0 - max 5.5 O.B 0.4 Unit v v v . 2.0 V1H 3.0 - Vee Vee v v Vee-0.5 - Vee v Topr -20 25 75 oc *With respect to Vss (SYSTEM GNDI · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vec=5.0V±10%, Vss=OV, Ta=- 20- +75°C, unless otherwise noted.) Item ~ymbol Test Condition HD63B09E min typ* max HD63C09E Unit min typ* max Logic V1H 2.0 - Vee 2.0 - Vee v Input "High" Voltage E,Q RES' VJ!i V1HR 3.0 - Vec-0.5 - ~ 3.0 - Vee Vee-0.5 - Vee v Vee v Input "Low" Voltage Logic, RES E,Q V1L V1Le -0.3 - -b.3 - O.B -0.3 - 0.4 -0.3 - O.B v 0.4 v Input Leakage Current Logic, 0. RES E Vin""O ~Vex:, .. lin Vec=max -2.5 - -10 - 2.5 -2.5 - 10 -10 - 2.5 µA 10 µA Do - 07 ILOAD=-400µA 4.1 - - 4.1 - - ILOAD~-10µA Vcc-0.1 - - Vee--0.1 - - v Output "High" Voltage I 1,,Q_Ao=-400µA Ao - Au, R/W VoH ILoAo:S:-10µA 4.1 - vee-0.1 - - 4.1 - - Vee-0.1 - - v BA, BS, Lie, AVMA,BUSY ILOAo=-400µA 4.1 - ILoAo~-10µA Vce-0.1 - - 4.1 - - Vee-0.1 - - - v Output "Low" Voltage VoL ILOAD=2mA - - 0.5 - - 0.5 v Input Capacitance Do""" 07 , Logic lnputO, RES E Vin=OV, Cin Tac25°C, f=1MHz - 10 15 - 10 15 pF - 30 50 - 30 50 pF Output Capacitance Frequency of Operation Three-State (Off Stata) Input Current Current Dissipation A,-Au,R/W, BA, BS, LIC, AVMA,BUSY E,Q Do - O., Ao"""Au,R/W Cout f ITSI Ice V;n=OV, Ta=25'C, f=1MHz V;n=0.4-Vce. Vcc=max Operating Sleeping - 10 15 - 10 15 pF 0.5 - 2.0 0.5 - 3.0 MHz -10 - 10 -10 - 10 µA -10 - 10 -10 - 10 µA - - 20 - - 10 - - 30 - mA 15 *Ta·25'e, Vec=5V @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 349 · AC CHARACTERISTICS (Vcc=5.0V±10%, Vss·O, Ta=-20- +75°C, unless otherwise noted.) 1. CLOCK TIMING Item Symbol Test Condition Cycle Time E Clock '"Low" E Clock "High"" (Measured at V1Hl E Rise and Fall Time Q Clock "High"" Q Rise and Fall Time E "Low" to Q Rising E ""Lqw""->O""High" Q "High" to E Rising Q "High""4E ""High"" E "High"" to Q Falling E "High""->O""Low"" Q ""Low"" to E Falling Q ""Low"4E '"Low"" tcvc tf>WEL tPWEH te,. tef tPWQH to.. tQf teo1 teo2 teoo te04 Fig.1,2 HD63B09E min typ mex 500 - 2000 210 - 1000 220 - 1000 -- 20 220 - 1000 - - 20 100 - - 100 - - 100 - - 100 - - HD63C09E min typ max Unit 333 - 2000 ns 140 - 1000 ns 140 - 1000 ns -- 15 ns 140 - 1000 ns -- 15 ns 65 - 65 - 65 - - ns - ns - ns 65 - - ns 2. BUS TIMING Item Address Delay l Address Hold Time Ta= 0- 75°C l (Address. R/W, BA, BS) Ta = _ 20-cf C Peripheral Read Accass Times ~-tet-tAo-tosR=tAcc> Data Setup Time (Read) Input Data Hold Time Deta Delay Time (Write) . 1J Ta= 0-75°C Output Data Hold Time Ta= -20-o·c -,.,-- 3. PROCESSOR CONTROL TIMING Symbol Test Condition tAO tAH tACC tosR tOHR toow toHw Fig.1, 2 Item Symbol Test Condition Control Delay (BUSY. LIC. AVMA) tco Interrupts Set Up Time tpcs ifAl:TSet Up Time ~SetUpTlme tpcs tpcs TSC Setup. Time tpcs TSC Drive to Valid Logic Levels !TSA TSC Releese MOS Buffers to High Impedance !TSR Fig.1, 2, 7 -10. 14 and 17 TSC Three-State Deley !Tso Processor Control Rise/Fall tpcr. tpcf TSC Input Delay tpCT HD63B09E min typ max - - 110 20 - - 10 - - 330 - - 40 - - 20 - - - - 110 30 - - 20 - - HD63B09E min typ max - - 200 110 - - 110 - - 110 - - 110 - - - - 120 - - 110 - - 80 - - 100 30 - - HD63C09E min typ max Unit - - 110 ns 20 - 10 - - ns - 185 - - ns 20 - 20 - -- 30 - 20 - - ns - ns 70 ns - - ns HD63C09E min typ mex Unit - - 130 ns 70 - - ns 70 - - ns 70 - - ns 70 - - ns - - 120 ns - - 110 ns - - 80 ns - - 100 ns 30 - - ns 350 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 --------------------------------HD6309E V1H 'PWEL E V1LC IEQI Q vcc-2.av R/W Addr. Vcc-2.av BA, BS a.av 'AD Data BUSY, UC, AVMA ~NotValid tcyc tpwe~----' t c D - - -..... Vcc-2.av a.av (NOTE) Waveform measurements for all inputs and outputs are specified at logic ''High''= V IHmin and logic "Low""' V ILmax unless otherwise specified. Figure 1 Read Data from Memory or Peripherals 1o------------ tcyc -----------+< E 'Er IEf tar R/W Addr. · Vcc-2.0V BA, BS a.av Data BUSY, UC, AVMA-----------+;:,,.~:...;,..;>...-- ~NotValid Data Valid vcc-2.av a.BV (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High"= V IHmin and logic "Low"= V llmax unless otherwise specified. Figure 2 Write Data to Memory or Peripherals @HITACHI Hitachi America Ltd. · 2210 O'Toale Avenue · San Jose, CA 95131 · (408) 435-8300 351 +--Vee +--Vss PC u s y x o{ A B OP cc m NMi FlFiC1 iFfO LIC AVMA R/W TSC HATI' BA BS BUSY ALU ' -'--------aE Figure 3 HD6309E Expanded Block Diagram 5.0V RL=1.Bkl"! C =30 pF for BA, BS, LIC, AVMA, BUSY 130 pF for Do -D, 90 pF for Ao -A,., RIW R =IC kS'!for Do -D, 10 kS'!for Ao -A,., R/W 10 kS'!for BA, BS, LIC, AVMA, BUSY All diodes are 1S2074@ or equivalent, C includes stray capacitance, Figure 4 Bus Timing Test Load · PROGRAMMING MODEL As shown in Figure 5, the lID6309E adds three registers to the set available in the HD6800. The added registers include a Direct Page Register, the User Stack pointer and a second Index Register. · Accumulators (A, B, Dl The A and B registers are general purpose accumulators which are used for arithmetic calculations and manipulation of data. Certain instructions concatenate the A and B registers to form a single 16-bit accumulator. This is referred to as the D Register, and is formed with the A Register as the most significant byte. · Direct Page Register (DP) The Direct Page Register of the lID6309E serves to enhance the Direct Addressing Mode. The content of this register appears at the higher address outputs (A8 - A15) during direct addressing instruction execution. This allows the direct mode to be used at any place in memory, under program control. To ensure HD6800 compatibility, all bits of this register are cleared during Processor Reset. 352 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 15 X - Index Register Y - Index Register U - User Stack Pointer S - Hardware Stack Pointer PC A l B D 0 Pointer Registers Program Counter Accumulators 7 0 _____ l~ ~j D_P_ _ _ _ Direct Page Register I I I I I I I I 7 0 j E F H 1 N Z V C CC - Condition Code Register Figure 5 Programming Model of The Microprocessing Unit · Index Registers (X, Yl The Index Registers are used in indexed mode of addressing. The 16-bil address in this register takes part in the calculation of effective addresses. This address may be used to point to data directly or may be modified by an optional constant or register offset. During some indexed modes, the contents of the index register are incremented or decremented to point to the next item of tabular type data. All four pointer registers (X, Y, U, S) may be used as index registers. · Stack Pointer (U, S) The Hardware Stack Pointer (S) is used automatically by the processor during subroutine calls and interrupts. The User Stack Pointer (U) is controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. The U-register is frequently used as a stack marker. Both Stack Pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push and Pull instructions. This allows the HD6309E to be used efficiently as a· stack processor, greatly enhancing its ability to support higher level languages and modular programming. (NOTE) The stack pointers of the HD6309E point to the top of the stack, in contrast to the HD6800 stack pointer, which pointed to the next free location on stack. · Program Counter (PC) The Program Counter is used by the processor to point to the address of the next instruction to be executed by the processor. Relative Addressing is provided allowing the Program Counter to be used like an index register in some situations. · Condition Code Register (CC) The Condition Code Register defines the state of the processor at any given time. See Figure 6. E F H Carry Overflow ~---Zero ~---- Negative ~----- IRQ Mask ~-------Half Carry ~-------- FIRO Mask ~---------Entire Flag Figure 6 Condition Code Register Format · CONDITION CODE REGISTER DESCRIPTION · Bit 0 (C) Bit 0 is the carry flag, and is usually the carry from the binary ALU. C is also used to represent a 'borrow' from subtract like instructions (CMP, NEG, SUB, SBC) and is the complement of the carry from the binary ALU. · Bit 1 IV) Bit I is the overflow flag, and is set to a one by an operation which causes a signed two's complement arithmetic overflow. This overflow is detected in an operation in which the carry from the MSB in the ALU does not match the carry from the MSB-1. · Bit 2 (Z) Bit 2 is the zero flag, and is set to a one if the result of the previous operation was identically zero. e Bit3 IN) Bit 3 is the negative flag, which contains exactly the value of the MSB of the result of the preceding operation. Thus, a negative two's-complement result will leave N set to a one. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 353 · Bit 4 (I) Bit 4 is the mQ mask bit. The processor will not recognize interrupts from the tim" line if this bit is set to a one. RMI, FIRQ, IRQ, RES and SWI all set I to a one; SWI2 and SWl3 do not affect I. · Bit5 (HI Bit 5 is the half-carry bit, and is used to indicate a carry from bit 3 in the ALU as a result of an B·bit addition only (ADC or ADD). This bit is used by the DAA irtstruction to perform a BCD decimal add adjust operation. The state of this flag is undefined in all subtract-like instructions. · Bit 6 (Fl Bit 6 is the FIRQ mask bit. The processor will not recognize interrupts from the FIRQ line if this bit is a one. NMI, FIRQ, SWI, and m' all set F to a one. IRQ, SWl2 and SWI3 do not affect F. · Bit 7 (El Bit 7 is the entire flag, and when set to a one indicates that the complete machine state (all the registers) was stacked, as opposed to the. subset state (PC and CC). The E bit of the stacked CC is used on a return from interrupt (RT!) to deter· mine the extent of the unstacking. Therefore, the current E left in the Condition Code Register represents past action. · HD6309E MPU SIGNAL DESCRIPTION · Power (Vss, Vee) Two pins are used to supply power to the part: Vss is ground or 0 volts, while Vee is +5.0 V ±10%. · Address Bus (A0 - A 15 I Sixteen pins are used to output address information from the MPU onto the Address Bus. When the processor does not require the bus for a data transfer, it will output address FFFF 16 , R/W = "High'', and BS = "Low"; this is a "dummy access" or VMA cycle. All address bus drivers are made high· impedance when output Bus Available (BA) is "High" or when TSC is asserted. Each pin will drive one Schottky TTL load or four LS TTL loads, and 90 pF. Refer to Figures I and 2. · Data Bus (D0 - D 7 I These eight pins provide communication with the system bi-directional data bus. Each pin will drive one Schottky TTL load or four LS TTL loads, and 130 pF. · Read/Write (R/WI This signal indicates the direction of data transfer on the data bus. A "Low" indicates that the MPU is writing data-0nto the data bus. R/W is made high impedance when BA is "High" or when TSC is asserted. Refer to Figures I and 2. · RES A "Low" level on this Schmitt-trigger input for greater tl)lln one bus cycle will reset the MPU, as shown in Figure 7. The Reset vectors are fetched from locations FFFE 16 and FFFF 16 (Table I) when Interrupt Acknowledge is true, (BA · BS= !). During initial power-on, the Reset line should be held "Low" until the clock input signals are fully operational. Because the lID6309E Reset pin has a Schmitt-trigger input with a threshold voltage higher than that of standard peripherals, a simple R/C network may be used to reset the entire system. This higher threshold voltage ensures that all peripherals are out of the reset state before the Processor. Table 1 Memory Map for Interrupt Vectors Memory Map for Vector Locations MS LS FFFE FFFC FFFA FFFS FFF6 FFF4 FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF2 FFFO FFF3 FFF1 Interrupt Vector Description RES m;;rr SWI nm FTRQ SWl2 SWl3 Reserved · HALT A "Low" level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefmitely without loss of data. When halted, the BA output is driven "High" indicating the buses are high .impedance. BS is also "High" which indicates the processor is in the Halt state. While halted, the MPU will not ~nd to external real-time requests (FIRQ, IRQ) although NMI or RES will be latched for later response. During the Halt state Q and E should continue to run normally. A halted state (BA · BS = I) can be achieved by pulling HALT "Low" while iIBS is still "Low". See Figure 8. · Bus Available, Bus Status (BA, BSI The Bus Available output is an indication of an internal control signal which makes the MOS buses of the MPU high impedance. When BA goes "Low", a dead cycle will elapse before the MPU acquires the bus. BA will not be asserted when TSC is active, thus allowing dead cycle consistency. The Bus Status output signal, when decoded with BA, represents the MPU state (valid with leading edge of Q). MPU State BA BS 0 0 0 0 MPU State Definition Normal (Running) Interrupt or RESET Acknowledge SYNC Acknowledge HALT Acknowledge Interrupt Acknowled~ indicated durin~th cycles of a hardware-vector-fetch (RES, NMI, FIRQ, IRQ, SWI, SWl2, SWl3). This signal, plus decoding of the lower four address lines, can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device. See Table I. Sync Acknowledge is indicated while the MPU is waiting for external synchronization on an interrupt line. Halt Acknowledge is indicated when the lID6309E is in a Halt condition. 354 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 :c ~"" 2: > 3 <1> n:::!. "!': fl. sRl q i@ ->ai :c " is ~ -:c rn () ~ _'0e.n-, n > . ~ ~ '.j;: ~.,. "'UI Co "00 ' E a RES Address Data r n R/W New PCH Naw PCL VMA 1st Opcode ~ BA mm\\\ · BS ..................__ _ _ __,/ \ ~ AVMA BUSY ..... LIC ,....----, New PCH New PCL Vli1lll: I \....__ _ (NOTE} Waveform measurements for all inputs and outputs are specified at logic "High"= V IHmin and logic "Low"= V 1Lmax unless otherwise specified. Figure 7 RES Timing w :c::c CJ) U1 w U1 0cmo w (J'I O> I ~- :nr. )> 3 c~;· .!":': !"- N N 0 0 cQ.l@· <t> :c ~ <t> ~ c::::J <t> "' :c (J) (') :::J ~ 0 (/) ~ () )> .""~'' ~ 0 .$ ~ "aw ' , 0 0 2nd to Last Last Cycle Cycle of of Current Current Inst. I Inst. I Dead Cycle Halted :I: 0 Ow > 0 mCD Dead Instruction Instruction Dead Cycle I Fetch I Execute I Cycle Halted Q E HALT Address Bus R/W BA BS Data Bus AVMA ~~____.~ \ LIC Fetch Execute Instruction Opcode I '~~~ (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High""" ViHmin and logic "Low"== ViLmax unless otherwise specified. Figure 8 HALT and Single Instruction Execution for System Debug · Non Maskable Interrupt (NMll* A negative transition on this input requests that a non- maskable interrupt sequence be generated. A non-maskable interrupt cannot be inhibited by the program, and also has a higher priority than FIRQ, IRQ or software interrupts. During recognition of an NM!, the entire machine state is saved on the hardware stack. After reset, an lilMI will not be recognized until the first program load of the Hardware Stack Pointer (S). The pulse width of NMI low must be at least one E cycle. If the NMI input does not meet the minimum set up with respect to Q, the interrupt will not be recognized until the next cycle. See Figure 9. · Fast-Interrupt Request (FIRQ)* A "Low" level on this input pin will initiate a fast interrupt sequence, provided its mask bit (F) in the CC is clear. This sequence has priority over the standard Interrupt Request (fRQ), and is fast in the sense that it stacks only the contents of the condition code register and the program counter. The interrupt service routine should clear the source of the interrupt before doing an RTL See Figure I0. · Interrupt Request (IRQ)* A "Low" level input on this pin will initiate an Interrupt Request sequence provided the mask bit (I) in the CC is clear. Since IRQ stacks the entire machine state it provides a slower response to interrupts than FIRQ. IRQ also has a lower priority than FIRQ. Again, the interrupt service routine should clear the source of the interrupt before doing an RTL See Figure·9. * NMI. FIRQ, and IRQ requests are sampled on the falling edge of Q. One cyde is required for synchronization before these interrupts are rc1.:ognized. The pending intcrrupt(s) will not be servked until compl~tion of the current instruction unless a SYNC' or C'WAI condition is present. If IRQ and FIRQ do not remain "Low.. until completion of the l'Urrcnt instruction they may not be recognized. However, NMI is h1td1cd and need only remain "Low" for one cycle. · Clock Inputs E, Q E and Q are the clock signals required by the HD6309E. Q must lead E; that is, a transition on Q must be followed by a similar transition on E after a minimum delay. Addresses will be valid from the MPU, tAo after the falling edge of E, and data will be latched from the bus by the falling edge of E. While the Q input is fully TTL compatible, the E input directly drives internal MOS circuitry and, thus, requires levels above normal TTL levels. This approach minimizes clock skew inherent with an internal buffer. Timing and waveforms for E and Q are shown in Figures I and 1 while Figure 11 shows a simple clock generator for the HD6309E. · BUSY Busy will be "High" for the read and modify cycles of a read- modify-write instruction and during the access of the first byte of a double-byte operation (e.g., LDX, STD, ADDD). Busy is also "High" during the first byte of any indirect or other vector fetch (e.g., jump extended, SW! indirect etc.). In a multi-processor system, busy indicates the need to defer the rearbitration of the next bus cycle to insure the integrity of the above operations. This difference provides the indivisible memory access required for a "test-and-set" primitive, using any one of several read-modify-write instructions. Busy does not become active during PSH or PUL operations. A typical read-modify-write instruction (ASL) is shown in Figure 12. Timing information is given in Figure 13. Busy is valid !co after the rising edge of Q. · AVMA AVMA is the Advanced VMA signal and indicates that the MPU will use the bus in the following bus cycle. The predictive nature of the AVMA signal allows efficient shared-bus multiprocessor systems. AVMA is "Low" when the MPU is in either a HALT or SYNC state. AVMA is valid tco after the rising edge ofQ. · LIC LIC (Last Instruction Cycle) is "High" during the last cycle of every instruction, and its transition from "High" to "Low" will indicate that the first byte of an opcode will be latched at the end of the present bus cycle. LIC will be "High" when the MPU is Halted at the end of an instruction, (i.e., not in CWAI or RESET) in SYNC state or while stacki11g during interrupts. UC is valid !co after the rising edge of Q. · TSC TSC (Three-State Control) will cause MOS address, data, and R/W buffers to assume a high-impedance state. The control signals (BA, BS, BUSY, AVMA and LIC) will not go to the high-impedance state. TSC is intended to allow a single bus to be shared with other bus masters (processors or DMA controllers). While E is "Low", TSC controls the address buffers and R/W directly. The data bus buffers during a write operation are in a high-impedance state until Q rises at which time, if TSC is true, they will remain in a high-impedance state. If TSC is held beyond the rising edge of E, then it will be internally latched, keeping the bus drivers in a high-impedance state for the remainder of the bus cycle. See Figure 14. · MPU Operation During normal operation, the MPU fetches an instruction from memory and then executes the requested function. This sequence begins after RES and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SW!, SWl2, SWl3, CWAI, RT! and SYNC. An interrupt or HALT input can also alter the normal execution of instructions. Figure 15 illustrates the flow chart for the HD6309E. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 357 :::c w 0 C11 CXl 0) w 0cmo I ~ ;<: )> 3 CD £· ~ "~ ' 0 0 -Qc. }@· CD ~ :I ~ ~ (/) (') gi :I <- 0 5 (') )> ""g"' .~s ~ ~ Last Cycle of Current Instruction i-----i.~---------------- Interrupt Stacking and Vector Fetch Sequence Instruction Fetch +---l + m-2 m-1 m I· I ·I· I m+1 m+2 I m+3 I ·· m+4 m+5 m+6 m+7 m+S ·I· ·I· ·I· ·I· I m+9 m+10 ·I· · ·1m+11jm+12 m+13 I m+14 m+15 m+16m+17 lm+18 I· I ·I· 1· · ·i· n n+1 I ·I E Q Data VMA PCL PCH UL UH YL YH XL XH DP B \..A--J'c\c...-.J\=="N'e-w---N'e"w--.J\==J'--~'---'' PCH PCL R/W~ \ I BA:x::::x::::>.~------------------------------~ BS :x::::x::::>. I \.__ _ _ __ AVMA--J~ BUSY ::J. LIC ---E {\ c=. (NOTE) W~veform measurements for all inputs and outputs are specified at logic "High"= V1Hmin and logic "Low"= V1Lmax unless otherwise specified. E clock shown for reference only. Figure 9 TAO and NMI Interrupt Timing :i: ~ ;:?'. )> 3 <D ~· "!': !"- ~ 0 0 -Q(. }@· <D ~ :I ~ ~ <D - (/) C') gi :I '0 ~ ~ <O ~ ~ ~ -!B ~ ~ w (11 CD Last Cycle of Current Instruction Instruction Fetch i - - - - - 1 - - - - - - - - - - - - - l n t e r r u p t Stacking and Vector Fetch Sequence------------i-~-~..i I I m-2 I m-1 m I I I m+l m+2 m+3 m+4 I m+5 m+6 I I m+7 m+8 m+9 n n+l · · · · · ·I · · · ·I E Q ·~ct~r ~~-=-===~ Address Bus FIRQ V1H 1Pcs PC PC FFFF SP-1 SP-2 SP-3 $FFFF $FFF6 $FFF7 $FFFF New PC New PC+ 1 V1L Data \7MA PCL PCH cc VMA New PCH New PCL VMA BA BS AVMA BUSY~ UC r E I\ ~ (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High"= V1Hmin and logic "Low"= ViLmax unless otherwise specified. E clock shown for reference only. ::c Figure 10 FIRQ Interrupt Timing ew0n 0 Cm D ~-------------------, I +SV I I I I I I IMRD I I I IL ___ _ +5V NOTE: If optional circuit is not included the CLR and PRE inputs of U2 and U3 must be tied high. 360 Figure 11 HD6309E Clock Generator Memory Location Memory Contents -.., Contents Description PC-+ $0200 $68 $0201 $9F $0202 $63 $0203 $00 $0204 L-- ASL Indexed Opcode Extended Indirect Postbyte Indirect Address Hi-Byte Indirect Address Lo-Byte - Next Main Instruction $6300~ Effective Address Hi-Byte $6301~ Effective Address Lo-Byte """~ ·-·~ Figure 12 Read Modify Write Instruction Example (ASL Extended Indirect) .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 :c ~ :;;, > 3 CD n::!. ID .!: !"- Rl 0 0t@ ~ J: ~ ~ :J en 0 ~ J: g<- 50 () > .!!i ~ ~ .!'!! ~ Co ~ 0 Last Cycle of Current Instr. E a Address Data R/W BUSY LIC AVMA E ~ ~ ~ ~ m - - - - - ~ ~ ~ ~ ~ (NOTE) Waveform measurements for all inputs and outputs are specified at logic "High"= ViHmin and logic "Low"= V ILmax unless otherwise specified. Figure 13 BUSY Timing (ASL Extended Indirect Instruction) w O> {NDTESI Data will be asserted by the MPU only during the interval while R/Wis "Low" and E or Q is "High". Waveform measurements for all inputs and outputs are specified at logic ''High'':= V1Hmin and logic ''Low''""' ViLmax unless otherwise specified. Figure 14 TSC Timing :i: 0 gwO> m w Ol N :r ~ :!: )> 3 CD :n:!. Ill ~ ~ 0 0 -Qc. }@· CD ~ :I ~ ~ CD - en 0 ~ :I <... ~ () )> ~ ~ 1 ~ a REs Seq. C>+DPR ::~$ Clrlllm Logic -O-is-ar-mr'R-m- (NOTES) 1. Asserting RES will result in entering the reset sequence from any point in the flow chart. 2. BUSY is "High" during first vector fetch cycle. :c 0 Ol c.> 0co m CWAI HD6309E Interrupt Structure Bus State Running BA BS 0 0 Interrupt or Reset Acknowledge 0 t Sync Acknowledge 1 0 Halt Acknowledge 1 1 Figure 15 Flowchart for HD6309E Instruction · ADDRESSING MODES The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The lID6309E has the most complete set of addressing mo(jes available on any microcomputer today. For example, the lID6309E has 59 basic instructions; however, it recognizes 1464 different variations of instructions and addressing modes. The addressing modes support modern programming techniques. The following addressing modes are available on the IID6309E: (1) Implied (Includes Accumulator) (2) Immediate (3) Extended (4) Extended Indirect (5) Direct (6) Register (7) Indexed Zero-Offset Constant Offset Accumulator Offset Auto Increment/Decrement (8) Indexed Indirect (9) Relative (10) Program Counter Relative · Implied (Includes Accumulator) In this addressing mode, the opcode of the instruction contains all the address information necessary. Examples of Implied Addressing are: ABX, DAA, SWI, ASRA, and CLRB. · lmmediata Addressing In Immediate Addressing, the effective address of the data is the location immediately following the opcode (i.e., the data to be used in the instruction immediately follows the opcode of the instruction). The lID6309E uses both 8 and 16-bit immediate values depending on the size of argument specified by the opcode. Examples of instructions with Immediate Addressing are: LDA #$20 LOX #$FOOO LOY #CAT (NOTE) # signifies immediate addressing, $ signifies hexadecimal value. · Extanded Addressing In Extended Addressing, the contents of the two bytes im- mediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of Extended Addressing include: LOA CAT STX MOUSE LDD $2000 · Extanded Indirect As a special case of indexed addressing (discussed below), one level of indirection may be added to Extended Addressing. In Extended Indirect, the two bytes following the postbyte of an Indexed instruction contain the address of the data. IDA [CAT] IDX ($FFFE) STU [DOG) · Direct Addressing Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. This byte specifies the lower 8 bits of the address to be used. The upper 8 bits of the addres· are supplied by the direct page register. Since only one byte of address is required ,in direct addressing, this mode requires less memory and executes faster than extended addressing. Of course, only 256 locations (one page) can be accessed without redefining the contents of the DP register. Since the DP register is set to $00 on Reset, direct addressing on the lID6309E is compatible with direct addressing on the HD6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are: LOA $30 SETDP $10 (Assembler directive) IDB $1030 LDD <CAT (NOTE) < is an assembler directive which forces direct addressing. · Registar Addr111ing Some opcodes are followed by a byte that defines a register or set of registers to be used by the instruction. This is called a postbyte. Some examples of register addressing are: TFR X, Y Transfer X into Y EXG A, B Exchanges A with B PSHS A, B, X, Y Push Y, X, Band A onto S PULU X, Y, D Pull D, X, and Y from U · Indexed Addr111ing In all indexed addressing, one of the pointer registers (X, Y, U, S, and sometimes PC) is used in a calculation of the effective address of the operand to be used by the instruction. Five basic types of indeXing are available and are discussed below. The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode as well as the pointer register to be used. Figure 16 lists the legal formats for the postbyte. Table 2 gives the assembler form and the number of cycles and bytes added to the basic values for indexed addressing for each variation. Po1t-By1e Register Bit · · 7 5 3 21 0 RRd d d d d RR 0 0 0 0 0 RR ; 0 0 0 1 RR 0 0 0 1 RR ; 0 0 1 RR ; 0 1 0 RR i 0 1 0 RR ; 0 1 RR ; 1 0 0 RR ; 1 0 0 RR ; 1 0 1 ; 1 10 0 ,. ; 1 1 0 1 RR i 1 1 Indexed Addrening Mode EA "' ,R + 5 Bit Offset ,R + ,R + + ,·R .--R EA·,R+OOfftet EA · ,R + ACCB Offset EA · ,R + ACCA Offset EA· R+8Bie0fftet EA· ,R + 16 Bit Offset EA·,R+DOfftat EA· ,PC+ 8 Bit Offut EA · ,PC + 18 Bit Offset EA·l.-1 L _ _ Addr·sing Mode Fiekl '--------- lS:~1':':nb7·0) ~-------Register Ftekt: RR oo· x "·Don't Care 01-v d ·Off1et:Blt 10·U 11 ·S ; · IO·Nonlndlrwct 1 · lndlf9Ct Figure 16 Index Addressing Postbyte Register Bit Assignments ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 363 Table 2 Indexed Addressing Mode Type Constant Offset From R (2's Complement Offsets) Accumulator Offset From R (2's Complement Offsets) Auto Increment/Decrement R Constant Offset From PC (2's Complement Offsets) Extended Indirect Non Indirect Forms Assembler Form Post byte OP Code -+ + # No Offset ,R 1RR00100 0 0 5 Bit Offset n,R ORRnnnnn 1 0 8 Bit Offset n, R 1RR01000 1 1 16 Bit Offset n,R 1 RR01001 4 2 A Register Offset A,R 1RR00110 1 0 B Register Offset B,R 1RR00101 1 0 D Register Offset D,R 1RR01011 4 0 Increment By 1 ,R + lRROOOOO 2 0 Increment By 2 ,R + + 1RR00001 3 0 Decrement By 1 Decrement Sy 2 '-R ·- - R 1RR00010 2 0 1RROOOl1 3 0 8 Bit Offset n,PCR 1xx01100 1 1 16 Bit Offset 16 Bit Address n,PCR - 1xx01101 5 2 - -- R=X,Y,UorS x = Don't Care RR: 00= x 01 = y 10 = u 11 = s ~and# indicate the number of additional cycles and bytes for the particular variation. Indirect Assembler Form Postbyte OP Code [.RI 1RR10100 defaults to 8-bit [n, RI 1RR11000 [n, RI 1RR11001 [A, RI 1 RR10110 [B, RI 1RR10101 [D, RI 1RR11011 not allowed [.R ++I 1 RR10001 not allowed [. - - RI 1 RR10011 [n,PCRI 1xx11100 [n, PCRI 1xx11101 [nl 10011111 -+ + # 3 0 4 1 7 2 4 0 4 0 7 0 6 0 6 0 4 1 8 2 5 2 Zero-Offset Indexed In this mode, the selected pointer register contains the effective address of the data to be used by the instruction. This is the fastest indexing mode. Examples are: LDD O,X LDA S Constant Offset Indexed In this mode, a two's-complement offset and the contents of one of the pointer registers are added to form the effective address of the operand. The pointer register's initial content is unchanged by the addition. Three sizes of offsets are available: 5-bit (-16 to +IS) 8-bit (-128 to +127) 16-bit (-32768 to +32767) The two's complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and cycles. The two's complement 8-bit offset is contained in a single byte following the postbyte. The two's complement 16-bit offset is in the two bytes following the postbyte. In most cases the programmer need not be concerned with the size of this offset since the assembler will select the optimal size automatically. Examples of constant-offset indexing are: LDA 23,X LDX -2,S LDY 300, X LDU CAT,Y Accumulator-Offset Indexed This mode is similar to constant offset indexed except that the two's-complement value in one of the accumulators (A, B or D) and the contents of one of the pointer registers are added to form the effective address of the operand. The contents of both the accumulator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator ·to use as an offset and no additional bytes are required. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time. Some examples are: LDA B, Y LDX D,Y LEAX B,X Auto lncrement/Decrement Indexed In the auto increment addressing mode, the pointer register contains the address of the operand. Then, after the pointer register is used it is incremented by one or two. This addressing mode is useful in stepping through tables, moving data, or for ti.e creation of software stacks. In auto decrement, the pointer register is decremented prior to use as the address ·of the data. The use of auto decrement is similar to that of auto increment; but the tables, etc., are scanned from the high to low addresses. The size of the increment/decrement can be either one or two to allow for tables of either 8- or 16-bit data to be accessed and is selectable by the programmer. The pre- 364 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 decrement, post-increment nature of these modes allow them to be used to create additional software stacks that behave identically to the U and S stacks. Some examples of the auto increment/decrement addressing modes are: LOA ,Xi' STD ,Yi'i' LOB ,-Y LOX ,--S Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the effective address. Consider the following instruction: STX 0, X i' i' (X initialized to 0) The desired result is to store a 0 in locations $0000 and $0001 then increment X to point to $0002. In reality, the following occurs: 0 ->temp calculate the EA; temp is a holding register Xi' 2 ->'X perform autoincrement X ... (temp) do store operation · Indexed Indirect All of the indexing modes with the exception of auto increment/decrement by one, or a ±4-bit offset may have an additional level of indirection specified. In indirect addressing, the effective address is contained at the location specified by the contents of the Index Register plus any offset. In the example below, the A accumulator is loaded indirectly using an effective address calculated from the Index Register and an offset. Before Execution A= XX (don't care) X = $FOOO $0100 LOA [$10, X) EA is now $FOi 0 $FOIO $Fl $F011 $50 $F 150 is now the new EA $Fl50 $AA After Execution A= $AA (Actual Data Loaded) X = $FOOO All modes of indexed indirect are included except those which are meaningless (e.g., auto increment/decrement by I indirect). Some examples of indexed indirect are: LOA [, X] LDD [10,S) LOA [B,Y) LOD [,XH) · Relative Addressing The byte(s) following the branch opcode is (are) treated as a signed offset which may be added to the program counter. If the branch condition is true then the calculated address (PC i' signed offset) is loaded into the program counter. Program execution continues at the new location as indicated by the PC; short (I byte offset) and long (2 bytes offset) relative addressing modes are available. All of memory can be reached in long relative addressing as an effective address is interpreted modulo 216 · Some examples of relative addressing are: BEQ CAT (short) BGT DOG (short) CAT DOG LBEQ LBGT RAT (long) RABBIT (long) RAT NOP RABBIT NOP · Program Counter Relative The PC can be used as the pointer register with 8 or 16-bit signed offsets. As in relative addressing, the offset is added to the current PC to create the effective address. The effective address is then used as the address of the operand or data. Program Counter Relative Addressing is used for writing position independent programs. Tables related to a particular routine will maintain the same relationship after the routine is moved, if referenced relative to the Program Counter. Examples are: LOA CAT,PCR LEAX TABLE, PCR Since program counter relative is a type of indexing, an additional level of indirection is available. LOA [CAT, PCR) LDU [DOG,PCR) · HD6309E INSTRUCTION SET The instruction set of the HD6309E is similar to that of the HD6800 and is upward compatible at the source code level. The number of opcodes has been rec\uced from 72 to 59, but because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) has risen from 197 to 1464. Some of the instructions are described in detail below: · PSHU/PSHS The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register, or set of registers with a single instruction. · PULU/PULS The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following the push or pull opcode determines which register or registers are to be pushed or pulled. The actual PUSH/PULL sequence is fixed; each bit defines a unique register to push or pull, as shown in below. PUSH/PULL POST BYTE -cc A ~---8 ~----DP ~-----x ~------Y ' - - - - - - - - S/U PC ~--------- <- Pull Order Push Order -> PC UYXDPBACC FFFF ....... <- increasing memory address ....... 0000 PCS YXDPBACC @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 365 · TFR/EXG Within the HD6309E, any. register may be transferred to or exchanged with another of like-size; i.e., 8-bit to 8-bit or 16-bit to 16-bit. Bits 4-7 ofpostbyte define the source register, while bits 0-3 represent the destination register. These are denoted as follows: oooo~D 0001-X 0010-Y 0011-U 0100 -S 0101-PC 1000-A 1001 - B 1010-CC 1011 -DP (NOTE) All other combinations are undefined and INVALID. TRANSFER/EXCHANGE POST BYTE ~o+c~ Io++T1:0NI · LEAX/LEAY/LEAU/LEAS The LEA (Load Effective Address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction are illustrated in Table 3. The LEA instruction also allows the user to access data in a position independent manner. For example: LEAX MSG 1, PCR LBSR PDATA (Print message routine). MSG! FCC 'MESSAGE' This sample program prints: 'MESSAGE'. By writing MSG l, PCR, the assembler computes the distance between the present address and MSG I. This result is placed as a constant into the LEAX instruction which will be indexed from the PC value at the time of execution. No matter where the code is located, when it is executed, the computed offset from the PC will put the absolute address of MSG1 into the X pointer register. This code is totally position independent. The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the autoincrement and autodecrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows: LEAa, b+ (any of the 16-bit pointer registers X, Y, U or Smay be substituted for a and b.) I. b .... temp (calculate the EA) 2. b + I -+ b (modify b, postincrement) 3. temp-+ a (load a) LEAa,-b I. b - 1 -+temp (calculate EA with predecrement) 2. b - I -+ b (modify b, predecrement) 3. temp -+a (load a) Autoincrement-by-two and autodecrement-by-two instructions work similarly. Note that LEAX, X+ does not change X, however LEAX, -X does decrement X. LEAX I, X should be used to increment X by one. Instruction LEAX 10, X LEAX 500, X LEAY A, Y LEAY D, Y LEAU -10, U LEAS -10, S LEAS 10, S LEAX 5, S Table 3 LEA Examples Operation X+ 10 -+ X X+500-+X Y +A -+Y Y+D -+Y u -10 ... u S -10 -+S s + 10 -+S S+5 -+ X Comment Adds 5-bit constant 1ci to X Adds 16·bit constant 500 to X Adds B-bit A accumulator to Y · Adds 16-bit D accumulator to Y Subtracts 10 from U Used to reserve area on stack Used to 'clean up' stack Transfers as well as adds · MUL Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D accumulator. This unsigned multiply also allows multipleprecision multiplications. long and ShOrt Relative Branches The HD6309E has the capability of program counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8 or 16-bit signed offset is added to the. value of the program counter to be used as the effective address. This allows the program to branch anywhere in the 64k memory map. Position independent code can be easily generated through the use of relative branching. Both short (8-bit) and long (16-bit) branches are available. ·SYNC After encountering a Sync instruction, the MPU enters a Sync state, stops processing instructions and waits for an interrupt. If the ~ing interrupt .is non-maskable (NM!) or maskable (FIRQ, IRQ) with its mask bit (F or I) clear, the processor will clear the Sync state and perform the normal interrupt stacking and service routine. Since FIRQ and IRQ are not edge-triggered, a low level with a minimum duration of three bus cycles is required to assure that the interrupt will be taken. If the pending interrupt is maskable (FIRQ, IRQ) with its mask bit (F or I) set, the processor will clear the Sync state and continue processing by executing the next inline instruction. Figure 17 depicts Sync timing. Software Interrupts A Software Interrupt is an instruction which will cause an interrupt, and its associated vector fetch. These Software Interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SW! are available on this HD6309E, and are prioritized in the following order: SWI, SWl2,SWI3. 16-Bit Operation The HD6309E has the capability of processing 16-bit data. These instructions include loads, stores, compares, adds, subtracts, transfers, ·exchanges, pushes and pulls. · .CYCLE-BY-CYCLE OPERATION The address bus cycle-by-cycle performanee chart illustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the HD6309E. Each instruction begins with an opcode fetch. While that opcode is being internally decoded, the next program byte is always fetched. (Most instructions will use the next byte, so this 366 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 technique considerably speeds throughput.~!, the operation of each opcode will follow the flow chart. VMA is an indication of FFFF 16 on the address bus, R/W ="High" and BS= "Low". The following examples illustrate the use of the chart; see Figure 18. Example 1: LBSR (Branch Taken) Before Execution SP = FOOO $8000 -LBSR CAT $AOOO Cycle# 1 2 3 4 5 6 7 8 9 CAT Address 8000 8001 8002 FFFF FFFF FFFF FFFF EFFF EFFE CYCLE-BY -CYCLE FLOW Data R/W Description 17 I Opcode Fetch IF Offset High Byte FD Offset Low Byte * VMA Cycle I VMA Cycle * 1 VMACycle I VMA Cycle 03 0 Stack Low Order Byte of Return Address 80 0 Stack High Order Byte of Return Address Example 2: DEC (Extended) $8000 DEC $AOOO FCB $AOOO $80 CYCLE-BY-CYCLE FLOW Cycle# Address Data R/W Description 1 8000 7A I Opcode Fetch 2 8001 AO 1 Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 FFFF I VMA Cycle 5 AOOO 80 1 Read the Data 6 7 FFFF * AOOO 7F I WA Cycle 0 Store the Deere- mented Data * The data bus has the data at that particular address. HD6309E · SLEEPMODE During the interrupt wait period in the SYNC instruction (the SYNC state) and that period in the CWAI instruction (the WAIT state), MPU operation is halted and goes to the sleep mode. However, the state of 1/0 pins is the same as that of the HD6809E in this mode. · HD6309E INSTRUCTION SET TABLES The instructions of the HD6309E have been broken down into five different categories. They are as follows: 8-Bit operation (Table 4) 16-Bit operation (Table 5) Index register/stack pointer instructions (Table 6) Relative branches (long or short) (Table 7) Miscellaneous instructions (Table 8) HD6309E instruction set tables and Hexadecimal Values of instructions are shown in Table 9 and Table I 0. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 367 c.v O'l OJ ;I : "=- )> 3 9l 15" !"': !"- I\) ~ 0 0 -0m<}@· -~ :I '~" ~ (/) 0 !l.l :I '0en5" ~ CD ~ ~ ~ ~ ~ ga, ::i: 0 Oc.>v 0 <mD Last Cycle Sync of Previous Opcode Instruction Fetch Execute Sync Acknowledge (Sleep mode) Last Cycle InosftrSuycnticon E Q Address Data ~ AVMA~ \ LIC r\__J 1Ra ~ NMI : ~ l I \ ~i~tpcf X See Note 1 \ v1HV~~ V1L~~~s~ ee~No~te:2 ;.:_:_~~~~~~~~~~~~~~~- (NOTES) 1. :~c~~~o~55~~i!t~~ ~~:!'e~~:. ifts:~e~~~;rr~~t ii~t=~~~~~e~ {~s~~d~nL~~:a~~i~ ;·1~0~~ra~h~1t~~lv;~~~~n8~~7~~.~~~~~~::~r~~~0;o~~~:~ 2. ~il~~~a~tb7t~t~r~h~1~:r~lrnh(~~do~:~s:~~ ~~1~1 ~t'~~.'?~:,.i';~~e~~ycles to guarantee that interrupt will be taken, although only one cycle is necessary to bring the processor out of SYNC. 3. Waveform measurements for all _inputs and outputs are specified at logic "High"= V1Hmin and logic "Low"= V1Lmax unless otherwise specified. Figure 17 SYNC Timing s I ":!: )> 3 ~ O' ~"' ~ 0 0 -0r}@· iD l :I ~ ~ Ul (') ~ :I <0 (/) CD ~ ~ ~ j t; "~ ' w Ol (s:J (F;;;;-) I Opcode (Fetch) Long Branch Short Branch Immediate and Implied Opcr+ VMA VMA Opcode+ I VMA N VMA -In-d-e.xed Offset ACCA ACCB R + 5 Bit R + 8 Bit PC+ 8 Bit VMA I Auto Auto Inc/Dec Inc/Dec Opcode+ by 1 by 2 R + 16 Bits R + D PC + Extended No 16 Bits Indirect Offset VMA I r· Opcode+ Opcode+ Opcode+ II I V~A V'fA VMA VMA I VMA VMA I VMA VMA I VMA V'fA VMA VMA I V¥A VMA VMA N VMA I VMA I Stack Write I Stack Write Operation (Following Pages) N VMA Fetch VMA (NOTE) 1. Busy = "High" during access of first byte of double byte immediate load. :I: 2. Write operation during store instruction. Busy= "High" during first two cycles of a double-byte access and the first cycle of read-modify-write access. 0 3. AVMA is asserted on the cycle before a VMA cycle. Ol ~ Figure 18 Address Bus Cycle-by-Cycle Performance (s:J m w -..J 0 sI · (") ;!: )> 3 f"i'· P> ~ N N 0 0 c2.;1@· "~' :c ~ c::i "' en ~ 0:c <0 CJ) !" 0 )> ID .01 ~ ~ 0 ~.,,. "ecln>' "00 ' :c 0 Implied Page , (J) w 0 <m D ASLA ASLB ASAA ASAB CLAA CLAB COMA COMB OAA OECA DECB INCA INCB LSLA LSLB LSAA LSAB NEGA NEGB NOP ROLA AOLB RORA AOAB SEX TSTA TSTB PSHU PULU SWI ABX ATS TFA EXG MUL PSHS PULS SWl2 CWAI ATI SWl3 VMA VMA VMA l7MA VMA STACK IA) STACK (A) VMA ~ _j VMA VMA VMA VMA VMA VMA _j ADDA STACK IA) I -VMA VMA VMA VMA VMA VMA IV~IA VM~ ADDA SP +- IVMA VMA I STACK IW) STACK IW) STACK (W) STACK IW) STACK IW) STACK (W) E= VMA STACKIW) STACK (W) ? - VM-A /stack 1w1) 1'2 VMA O STACK (w) STACK (W) STACK (W) STACK (W) 0 I 1. VMA 1Note3) STACK IW) STACK IW) VMA /stack IA)) 2 STACK IW) STACK (W) I(Note 3) O STACK IW) STACK IW) STACK IW) STACK IW) STACK IW) STACK (W) STACK (W) STACK IW) STACK IA) STACK (A) I I 00 ADDA+- SP VMA I IVMA; (Note 4) VECTOR IH), VECTOR (H), BUSY +-1 BUSY +-1. VECTOR (L), VECTOR (L), BUSY +-0 I BUSY +-0 I ADDA +-SP VMA VMA _j l l .. STACK IA) STACK IA) STACK IA) STACK (A) STACK (A) STACK IA) STACK (A) STACK (A) STACK (A) STACK IA) STACK (A) (NOTES) 1. Stack (W} refers to the following sequence: SP +-SP - 1, then ADDA+- SP with R/W"" "Low" Stack (A) refers to the following sequence: ADDA +-SP with R/W = "High", then SP ...-sp + 1. PSHU, PULU instructions use the user stack pointer (i.e., SP= U} and PSHS, PULS use the hardware stack pointer (i.e., SP"" SL 2. Vector refers to the address of an interrupt or reset vector (see Table 11. 3. The number of stack accesses will vary according to the number of bytes saved. 4. VMA cycles will occur until an interrupt occurs. Figure 18 Address Sus Cycle-by-Cycle Performance (Continued) ::r:: ~ :!'. )> 3 ~ ff Ill ~ 0-~c}. 2. · -CD ~ :I "~' ~ (/) C') ~ ::c c.... ~ 0 )> ~ ~ ~... a (,) -.J Non~ Implied t ADCA ADCB ADDA AOOB ANDA ANOB BITA BITB CMPA CMPB EORA EORB LOA LOB ORA ORB SBCA SBCB STA STB SUBA SUBB LDD LOS LOU LOX LOY AN DCC ORCC ASL ASR CLR COM DEC INC LSL LSR NEG ROL ROR TST ADDO JSR STD CMPD STS CMPS STU CMPU STX CMPX STY CMPY SUBD VMA STACK (W) STACK (W) VMA, BUSY +-1 ADDR+ BUSY +-0 AOOR+ WA VMA ADOR+ I VMA ADDRI +(W) , l l (NOTES) 1. Stack (W) refers to the following sequence: SP <-SP - 1, then ADDR +-SP with RiW = "Low" Stack (R) refers to the following sequence: AODR +-SP with R/W = "High", then SP<- SP+ 1. PSHU, PULU instructions use the user stack pointer (i.e., SP= U) and PSHS, PULS use the hardware stack pointer (i.e., SP= S). 2. Vector refers to the address of an interrupt or reset vector (see Table 1). 3. The number of stack accesses will vary according to the number of bytes saved. 4. VMA cycles will occur until an interrupt occurs. · ::r 0 O> Figure 18 Address Bus Cycle-by-Cycle Performance (Continued) (,) 0cmo Mnemonic(s) ADCA,AOCB ADDA,ADDB ANDA,ANDB ASL,ASLA,ASLB ASR, ASRA, ASRB BITA,BITB CLR, CLRA, CLRB CMPA,CMPB COM, COMA, COMB DAA DEC,DECA,DECB EORA,EORB EXG Rl, R2 INC, INCA, INCB LOA, LOB LSL, LSLA, LSLB LSR, LSRA, LSRB MUL NEG, NEGA, NEGB ORA, ORB ROL, ROLA, ROLB ROR, RORA, RORB SBCA, SBCB STA,STB SUBA, SUBB TST, TSTA, TSTB TFR Rl, R2 Table 4 8-Bit Accumulator and Memory Instructions Operation Add memory to accumulator with carry Add memory to accumulator And memory with accumulator Arithmetic shift of accumulator or memory left Arithmetic shift of accumulator or memory right Bit test memory with accumulator Clear accumulator or memory location Compare memory from accumulator Complement accumultor or memory location Decima I adjust A accumulator Deaement accumulator or memory location Exclusive or memory with aceumulator Exchange Rl with R2(R1, R2 =A, B, CC, DP) Increment accumulator or memory location Load accumulator from memory Logical shift left accumulator or memory location Logical shift ~ight accumulator or memory location Unsigned multiply (A x B-+ DI Negate accumulator or memory Or memory with accumulator Rotate accumulator or memory left Rotate accumulator or memory right Subtract memory from accumulator with borrow Store accumulator to memory Subtract memory from accumulator Test accumulator or memory location Transfer Rl to R2 ( Rl, R2 =A, B, CC, DP} (NOTE) A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS, PULU) instructions. Mnemonic(s) ADDO CMPD EXG D, R LOO SEX STD SUBD - - - TFR D, R TFR R,D Table 5 16-Bit Accumulator and Memory Instructions Operation Add memory to D accumulator Compare memory from D accumulator Exchange D with X, Y, S, U or PC Load D accumulator from memory Sign Extend B accumulator into A accumulator Store D accumulator to memory Subtract memory from D accumulator Transfer D to X, Y, S, U or PC Transfer X, Y, S, U or PC to D (NOTE) D may be pushed (pUlled) to either stack with PSHS, PSHU (PULS, PULU) instructions. ~HITACHI 372 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Mnemonic(s) CMPS,CMPU CMPX,CMPY EXG Rl, R2 LEAS, LEAU LEAX, LEAY LOS, LOU LOX, LOY PSHS PSHU PULS PULU STS, STU STX, STY TFRR1,R2 ABX Table 6 Index Register Stack Pointer Instructions Operation Compare memory from stack pointer Compare memory from index register Exchange D, X, Y, S, U or PC with D, X, Y, S, U or PC Load effective address into stack pointer Load effective address into index register Load stack pointer from memory Load index register from memory Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack Push A, B, CC, DP, D, X, Y, S, or PC onto user stack Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack Pull A, B. CC, DP, D, X, Y, Sor PC from user stack Store stack pointer to memory Store index register to memory Transfer D, X, Y, S, U or PC to D, X, Y, S, U or PC Add B accumulator to X (unsigned) Table 7 Branch Instructions Mnemonic(s) Operation --BEQ,LBEQ SIMPLE BRANCHES Branch if equal BNE,LBNE Branch if not equal BMI, LBMI Branch if minus BPL, LBPL Branch ii plus BCS,LBCS Branch if carry set BCC,LBCC Branch if carry clear BYS. LBVS Branch if overflow set BVC, LBVC Branch if overflow clear SIGNED BRANCHES BGT, LBGT Branch if greater (signed) BGE, LBGE Branch if gceater than or equal (signed) BEQ,LBEO Branch if equal . -~~-----------------------·-------- ------- BLE, LBLE Branch if ------~~=-----+---- -les-s -th-an-o-r e-q-ua-l (-sig·n-ed-) - - - - - - - - - - - - - - - - - - - - - - - - - BLT, LBLT Branch if less than (signed) UNSIGNED BRANCHES BHI, LBHI Branch if higher (unsigned) BHS,LBHS Branch if higher or same (unsigned) BEO, LBEO Branch if equal BLS, LBLS Branch if lower or same (unsigned) BLO,LBLO Branch if lower (unsigned) OTHER BRANCHES BSR,LBSR Branch to subroutine BRA, LBRA Branch always BAN, LBRN Branch never @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 373 Mnernonic(s) AN DCC CWAI NOP ORCC JMP JSR RTI RTS SWI, SWl2, SWIJ SYNC Table 8 Miscellaneous Instructions Operation AND condition code register AND condition code register, then wait for interrupt No operation OR condition code register Jump Jump to subroutine Return from interrupt Return from subroutine Software interrupt (absolute indirect) Synchronize with interrupt line 374 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 9 HD6309E Instruction Set Table INSTRUCTION/ FORMS -IMPLIED OP # ABX 3A 3 1 ADC ADCA ADCB ADD ADDA ADDB ADDO AND ANDA ANDB AN DCC ASL ASLA 48 2 1 ASLB 58 2 1 ASL ASA ASRA 47 2 1 ASRB S7 2 1 ASA BCC BCC LBCC BCS BCS LBCS BEO BGE BEQ LBEO BGE LBGE BGT BGT LBGT BHI BHI LBHI BHS BHS HD6309E ADDRESSING MODES -DIRECT OP # - - - EXTENDED IMMEDIATE INDEXED(j; RELATIVE OP # OP # DP # OP _,., # 99 4 09 4 9B 4 DB 4 03 6 94 4 04 4 2 B9 s 2 F9 s 2 BB s 2 FB s 2 F3 7 2 2 114 F4 s s 3 B9 2 3 C9 2 3 BB 2 3 CB 2 3 CJ 4 3 84 2 3 C4 2 1C 3 2 A9 4+ 2+ 2 E9 4+ 2+ 2 AB 4+ 2+ 2 EB 4+ 2+ 3 E3 6+ 2+ 2 A4 4+ 2+ 2 E4 4+ 2+ 2 OB 6 2 7B 7 3 68 6+ 2+ 07 6 2 77 7 3 67 6+ 2+ 24 3 2 10 S(61 4 24 25 3 2 10 S(61 4 2S 27 3 2 10 Sl61 4 27 2C 3 2 10 S(61 4 2C 2E 3 2 10 S(61 4 2E 22 3 2 10 S(61 4 22 24 3 2 LBHS BIT BLE BLO BITA BITB BLE LBLE BLO LBLO BLS BLS 9S 4 OS 4 2 BS ·S 2 FS s 3 BS 2 3 cs 2 10 S(61 4 24 2 AS 4+ 2+ 2 ES 4+ 2+ 2F 3 2 10 St61 4 2F 2S 3 2 10 St6) 4 2S 23 3 2 LBLS BLT BLT LBLT BMI BMI LBMI BNE BNE LBNE BPL BPL LBPL BRA BRA LBRA 10 5(61 4 23 20 3 2 10 S(61 4 20 2B 3 2 10 S(61 4 2B 26 3 2 10 S(6) 4 26 2A 3 2 10 S(6) 4 2A 20 16 s 3 2 3 BRN BAN LBRN 21 3 2 10 5 4 21 DESCRIPTION ArUi+N+~Gx1+-1x;E-DA l B+M+C-B 5 3 2 1 0 H N z v c · · · · · II III I I I I I A+M-A I I I I I · B+M- B I I I I I D+M:M+1-D I III AllM-A B llM-B · ·· I I I I 0 · 0 CCII IMM-CC (-f-1 r·H) OiJJililJ} I I I I BA} 0 ,8e I I I I M c b1 iB" I I I I lCUfiillIHJ AB M b7 ·· .,aa· I I I I I I · "° c ,a. I I I Branch C=O Long Branch C=O ·· ·· ·· ·· ·· Branch C=1 Long Branch ·· ·· ·· ·· ·· C=1 Branch z =1 Long Branch Z=1 ·· .· .· .· ·. Branch N EllV=O · · · · · Long Branch · · · · · NEllV=O · · · . Branch ZVINEIJV)=O · · · · ·· Long Branch ZV(N EllVl=O · · · · · Branch CVZ=O · · · · · Long Branch CVZ=O Branch C=O Long Branch C=O · · · · · · · · · · Bit Test A (M II. A) ·· ·· Bit Test B (M 11.B) I I0 I I0 Braru:h ZV(NEIJVl=l · · · · · Long Branch · · · · · ZVIN EllVl=l Branch C=1 Long Branch C=l ·· ·· ·· ·· ·· Branch CVZ=l Long Branch CVZ=1 · · · · · · · · · · Branch N Ell V=l Long Branch NEllV=l Branch N=1 Long Branch N=1 ·. . ·· ·· ·· ·· ·· ·· ·· ·· · · Branch Z sO Long Branch Z=O ·· ·· ·· ·· ·· Branch N = O Long Branch N=O ·· ·· ·· ·· ·· Branch Always Long Branch/ Always ·· ·· ·· ·· ·· · · ·· ·· ·· · Branch Never Long Branch Never · (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 375 INSTRUCTION/ FORMS BSR BSR IMPLIED OP - # LBSR BVC BVC LBVC BVS BVS LBVS CLR CLRA 4F 2 1 CLRB 5F 2 1 CLR CMP CMPA CMPB CMPD CMPS CMPU CMPX CMPY COM COMA 43 2 1 COMB 53 2 1 COM CWAI DAA 19 2 1 DEC DECA 4A 2 1 DECB SA 2 1 DEC EOR EORA EORB EXG Rl, R2 lE 7 2 INC INCA 4C 2 1 INCB SC 2 1 INC JMP JSR LO LDA LDB LDD LDS LDU LDX LDY LEA LEAS LEAU LEAX LEAY LSL LSLA 48 2 1 LSLB 58 2 1 LSL LSR LSRA 44 2 1 LSRB 54 2 1 LSR MUL 3D 11 1 NEG NEGA 40 2 1 NEGB 50 2 1 NEG NOP 12 2 1 HD6309E ADDRESSING MODES -DIRECT OP # - - EXTENDED IMMEDIATE OP # OP # INDEXEDCC - OP # RELATIVE OP -~ # SD 7 2 17 9 3 28 3 2 10 5(6) 4 28 29 3 2 10 5(6) 4 29 OF 6 2 7F 7 91 4 2 Bl 5 D1 4 2 Fl 5 10 7 3 10 8 93 B3 11 7 3 11 8 9C BC 11 7 3 11 s 93 B3 9C 6 2 BC 7 10 7 3 10 8 9C BC 3 6F 6+ 2+ 3 81 2 2 Al 4+ 2+ 3 Cl 2 2 E1 4+ 2+ 4 10 5 4 10 7+ 3+ S3 A3 4 11 5 4 11 7+ 3+ SC AC 4 11 5 4 11 7+ 3+ S3 A3 3 BC 4 3 AC 6+ 2+ 4 10 5 SC 4 10 7+ 3+ AC 03 6 2 73 7 3 63 6+ 2+ 3C ~20 2 OA 6 9S 4 DB 4 2 7A 7 2 BS 5 2 FS 5 3 I 6A 6+ 2+ 3 SS 2 2 AB 4+ 2+ 3 cs 2 2 ES 4+ 2+ QC 6 2 7C 7 OE 3 2 7E 4 9D 7 2 BO 8 96 4 2 86 5 06 4 2 F6 5 DC 5 2 FC 6 10 6 3 10 7 DE FE DE 5 2 FE 6 9E 5 2 BE 6 10 6 3 10 7 9E BE 3 6C 6+ 2+ 3 6E 3+ 2+ 3 AD 7+ 2+ 3 S6 2 2 A6 4+ 2+ 3 C6 2 2 E6 4+ 2+ 3 cc 3 3 EC 5+ 2+ 4 10 4 4 10 6+ 3+ CE EE 3 CE 3 3 EE 5+ 2+ 3 SE 3 3 AE 5+ 2+ 4 10 4 4 10 6+ 3+ SE AE 32 4+ 2+ 33 4+ 2+ 30 4+ 2+ 31 4+ 2+ 08 6 2 78 7 3 64 6 2 74 7 3 68 6+ 2+ 64 6+ 2+ 00 6 2 70 7 3 60 6+ 2+ DESCRIPTION 5 3 2 10 H N z v c Branch to Subroutine Long Branch to Subroutine Branch V=O Long Branch V=O Branch v = 1 Long Branch v = 1 O-A 0- B O-M · · · · · . ·1· · · · ·· ·· · ·· ·· .·· ·· · ·· ·· .0 1 0 0 0 10 0 ·· 0 1 0 0 Compare M from A 8 I I l I · Compare M from B s ! ! ! I Compare M: M + 1 I I I I fromD · Compare M: M + 1 I I I I from S Compare M: M + 1 I · from U . Compare M: M+1 I from X . Compare M: M + 1 I I I I I I I I I I fromY A-A B-· B M-M ..· I I 0 1 I I01 I I01 CC/\IMM-CC (except 1---+E) Wait for Interrupt Decimal Adjust A A-1 -A B - 1 -· B M-1-'M r - \ --t--; 7 l .I I 8 I I I I . · · I I I . ·· I ! I A<!l M-·A B <ll M-· B R1 ·-· R2' . A+ 1-· A B+1- B I· M + 1-M . EA' -·PC · · I I I I 0 0 · · ,-r--, toir-- I I I · I I I · ·· I I I · '· . . . . Jump to Subroutine · . ·1· M-·A . M-- B . . Mi M + 1 -· D . Mi M+ 1-S I I I · I I 0 · I 0· I 0 I 0 M: M+ 1- U M: M+1- X M: M+ 1-Y EA1 - S EA·;,_ U EAa_. X EA'--Y . · ··· ! I ! I I I 0 0 0 · · .. . . ·· · ·· · ... .. · t t · · lHJillllJ}' ~Al - · · t t I I I I I I ·! I I I GiJilllID1J . ~Al - · · 0 0 0 t I I · · · I I I AxB-D · · t · ~) (Unsigned) A+1-A B+ 1- B f;I+ 1-M rg, I I I I (I!) I t I : @I I I I No Operation · · · · · (to be continued) 376 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 INSTRUCTION/ FORMS IMPLIED - OP # OR ORA ORB ORCC PSH PSHS 34 5+(j, 2 PSHU 36 5-+l"j 2 HD6309E ADDRESSING MODES DIRECT EXTENDED - - OP # OP # 9A 4 2 BA 5 3 DA 4 2 FA 5 3 IMMEDIATE - OP # BA 2 2 CA 2 2 IA 3 2 INDEXED© - OP # AA 4+ 2+ EA 4+ 2+ RELATIVE -" OP # PUL PULS PULU 35 5+'4; 2 37 5+~' 2 ROL ROLA 49 2 I ROLB 59 2 I ROL 09 6 2 79 7 3 ROR RORA 46 2 I RORB 56 2 I ROR 06 6 2 76 7 3 RT! 3B 6/15 I 69 6+ 2+ 66 6+ 2+ RTS 39 5 I SBC SEX SBCA S8CB 10 2 92 4 2 B2 5 02 4 2 F2 5 I 3 82 2 2 A2 4+ 2+ 3 C2 2 2 E2 4+ 2+ ST STA STB STD STS STU STX STY 97 4 07 4 DD 5 10 6 OF OF 5 9F 5 10 6 9F SUB SUBA SUBB SUBD 90 4 DO 4 93 6 SWI SWI''= 3F 19 I SWl2"' 10 20 2 3F SWl3' II 20 2 3F SYNC 13 ~4 I 2 B7 5 2 F7 5 2 FD 6 3 10 7 FF 2 FF 6 2 BF 6 3 10 7 BF 2 80 5 2 FO 5 2 B3 7 3 3 3 4 3 3 4 3 80 2 3 co 2 3 83 4 A7 4+ 2+ E7 4+ 2+ ED 5+ 2+ 10 6+ 3+ EF EF 5+ 2+ AF 5+ 2+ 10 6+ 3+ AF 2 AO 4+ 2+ 2 EO 4+ 2+ 3 A3 6+ 2+ TFR RI, R2 IF 6 2 TST TSTA 40 2 I TSTB 50 2 I TST OD 6 2 70 7 3 60 6+ 2+ DESCRIPTION AVM-A BvM-B CCV IMM-CC Push Registers on S Stack Push Registers on U Stack 532I 0 HNz vc · · ( l +-l - l l ·7, 0 0 1-- · · ) . . . · · .. . · · ( + - Pull Registers from (!OJ~ ) ( +-- S Stack Pull Registers from ~OJI- ) U Stack .l l I I I I I I ~)~ ·· I I I I . .I I I .I I I ~l~ ·· · I I I Return From Interrupt Return From . . . . . (+-- 7 1-- ) Subroutine A-M-C-A 8-M-C-8 Sign Extend B into A A-M B-M D-M: M+I S - M: M +I U- M: M+ I x- M: M+ I Y- M: M+ I · · . 10/ l I I I I (8.1 I l I I l . ·· I I l I 0 0 · . .. · I I 0 I I0 . I I 0 . · I I 0 . ·· I I 0 A-M-A 8I III B-M-B 8I I I I 0-M: M + 1- D I I I I ·· . · . . Software Interrupt1 · . . Software Interrupt2 . · · .· ·· Software Interrupt3 Synchronize to Interrupt Al_,. R2 2 Test A Test B Test M '· · · · · (+-i ~oJH l . · I l 0 .. .· l I 0 I I0 (NOTES) (t) This column gives a base cycle and byte count. To obtain total count, and the values obtained from the INDEXED ADDRESSING MODES table. (2) R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers. The 8 bit registers are: A, B. CC, DP The 16 bit registers are: X, Y. u. s. D. PC @ EA is the effective address. ~) The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled. @ 5C6) means: 5 cycles if branch not taken, 6 cycles if taken. (8) SWI sets 1 and F bits. SWl2 and SWl3 do not affect I and F. (?) Conditions Codes set as a direct result of the. instruction. (_§) Value of half-carry flag is undefined. @ Special Case - Carry set if b7 is SET. @> Condition Codes set as a direct result of the instruction if CC is specified,. and not affected otherwise. LEGEND: OP Operation Code (Hexadecimal) Number of MPU Cycles # Number of Program Bytes + Arithmetic Plus Arithmetic Minus X Multiply D Complement of M Transfer Into H Half-carry (from bit 3) N Negative (sign bid Z Zero (byte) V Overflow, 2's complement C Carry from bit 1 t Test and set if true, cleared otherwise · Not Affected CC Condition Code Register Concatenation V Logical or A Logical and <±> Logical Exclusive or @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 377 Table 10 Hexadecimal Values of Machine Codes OP Mnem Mode 00 NEG Direct 01 02 03 COM 04 LSR 06 06 ROR 07 ASR 08 ASL,LSL 09 ROL OA DEC OB oc INC OD TST OE JMP OF CLR Direct # 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 3 2 6 2 ~~ l:'xt Page 12 NOP Implied 2 13 SYNC Implied ~4 14 15 16 LBRA Relative 5 3 17 LBSR Relative 9 3 18 19 DAA Implied 2 1 1A ORCC lmmed 3 2 1B 1C ANDCC lmmed 3 2 1D SEX 1E EXG 1F TFR Implied i Implied 2 1 B 2 6 2 20 BRA Relative 21 8RN 22 BHI 23 BLS 24 BHS, BCC 25 BLO, BCS 26 8NE 27 BEQ 28 eve 29 BVS 2A BPL 2B BMI 2C BGE 2D BLT 2E BGT 2F BLE Relative 3 2 3 ·2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 OP Mnem 30 LEAX 31 LEAY 32 LEAS 33 LEAU 34 PSHS 35 PULS 36 PSHU 37 PULU 3B 39 RTS 3A ABX 3B RTI 3C CWAI 3D MUL 3E 3F SWI Mode # Indexed 4+ 2+ l 4+ 2+ 4+ 2+ Indexed 4+ 2+ Implied 5+ 2' I 5+ 2 5+ 2 5+ 2 5 ·1 3 1 Implied 6, 15 1 lmmed ~20 2 Implied 11 1 Implied 19 40 lllEGA Implied 2 41 42 43 COMA 2 44 LSRA 2 45 46 RORA 2 47 ASRA 2 4B ASLA, LSLA 2 49 ROLA 2 4A DECA 2 4B 4C INCA 2 40 TSTA 2 4E 4F CLRA Implied 2 50 NEGB Implied 2 51 52 53 COMB 2 54 LSRB 2 55 56 RORB 2 57 ASRB 2 5B ASLB, LSLB 2 59 ROLB 2 5A DECB 2 5B 5C INCB 2 5D TSTB 2 5E 5F CLRB Implied 2 OP Mnem Mode 60 NEG Indexed 61 62 63 COM 64 LSR 65 66 ROR 67 ASR 68 AsL, LSL 69 ROL 6A DEC 6B 6C INC 6D TST 6E JMP 6F CLR Indexed # 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 6+ 2+ 3+ 2+ 6+ 2+ 70 NEG Extended 7 3 71 72 73 COM 7 3 74 LSR 7 3 75 76 ROR 7 3 77 ASR 7 3 78 ASL,LSL 7 3 79 ROL 7 3 7A DEC 7 3 7B 7C INC 70 TST 7E JMP 7F CLR l . 7 7 4 Extended 7 3 3 3 3 BO SUBA lmmed 2 2 Bl CMPA 2 2 B2 SBCA 2 2 B3 SUBD 4 3 84 ANDA 2 2 BS BITA 2 2 86 LOA 2 2 87 88 EORA 2 2 89 ADCA 2 2 BA ORA 2 2 BB ADDA 2 2 BC CMPX lmmed 4 3 BO BSR Relative 7 2 BE LOX lmmed 3 3 BF LEGEND: - Number of MPU cycles (less possible push pull or indexed-mode cycles) # Number of program bytes · Denotes unused opcode (to be continued) 378 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 OP Mnem 90 SUBA 91 CMPA 92 SBCA 93 SUBO 94 ANDA 9S BITA 96 LOA 97 STA 9B EORA 99 ADCA 9A ORA 9B ADDA 9C CMPX 90 JSR 9E LOX 9F STX AO SUBA A1 CMPA A2 SBCA A3 SUBD A4 ANDA A5 BITA AG LOA A7 STA AB EORA A9 ADCA AA ORA AB ADDA AC CMPX AO JSR AE LOX AF STX BO SUBA B1 CMPA B2 SBCA B3 SUBD 84 ANDA BS BITA B6 LOA B7 STA BS EORA B9 AOCA BA ORA BB ADDA BC CMPX BO JSR BE LOX BF STX CO SUBB C1 CMPB C2 SBCB C3 ADDO C4 ANDB CS BITB Mode Direct Direct # 4 2 4 2 4 2 6 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 6 2 7 2 s 2 s 2 Indexed Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 7+ 2+ 5+ 2+ S+ 2+ Extended s 3 s 3 s 3 7 3 s 3 5 3 5 3 5 3 5 3 5 3 5 3 s 3 7 3 B 3 6 3 rExtended 6 2 2 2 4 3 2 2 2 3 2 2 lmmed 2 2 OP Mnem CS. LOB C7 CB EORB C9 AOCB CA ORB CB ADDB CC LOO co CE LOU CF DO SUBB 01 CMPB 02 SBCB 03 ADDO 04 ANDB 05 BITB 06 LOB 07 STB DB EORB 09 ADCB DA ORB DB ADDB DC LOO DD STD DE LOU OF STU EO SUBB E1 CMPB E2 SBCB E3 ADDO E4 ANDB E5 BITB ES LOB E7 STB EB EORB E9 ADCB EA ORB EB ADOB EC LOO ED STD EE LOU EF STU FO SUBB F1 CMPB F2 SBCB F3 ADDO F4 ANDB F5 BITB F6 LOB F7 STB FB EORB F9 AOCB FA ORB FB ADDB INOTEl: All unused opcodes are both undefined and illegal Mode # lmmed 2 I 2 2 2 2 3 2 2 2 2 3 lmmed 3 Direct r l Direct 4 2 4 2 4 2 6 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 5 2 5 2 5 2 5 2 Indexed Indexed 4+ 2+ 4+ 2+ 4+ 2+ 6+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 4+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ 5+ 2+ Extended 5 3 5 3 5 3 3 I 5 5 5 s 5 5 3 3 3 3 3 3 5 3 Extended 5 3 OP Mnem Mode # FC LOO Extended 6 3 FD STD FE LOU l.6 3 6 3 FF STU Extended 6 3 2 Bytes Opcode 1021 LBRN 1022 LBHI 1023 LBLS iRelative 1024 LBHS, LBCC I· 1025 LBCS,LBLO 1026 LBNE 1027 LBEQ 102B LBVC 1029 LBVS 102A LBPL 102B LBMI 102C LBGE 1020 LBLT 102E LBGT 102F LBLE Relative 103F SWl2 Implied 1083 CMPD 108C CMPY 10BE LOY 1093 CMPD 109C CMPY 109E LOY lmmed i lmmed :Direct 109F STY Direct 10A3 CMPD lndted 10AC CMPY 10AE LOY 10AF STY Indexed 10B3 CMPD Extinded 10BC CMPY 10BE LOY 10BF STY Extended 10CE LOS lmmed !ODE LOS Direct 10DF STS Direct 10EE LOS Indexed 10EF STS Indexed 10FE LOS Extended !OFF STS Extended 113F SWl3 Implied 11B3 CMPU lmmed 11BC CMPS lmmed 1193 CMPU Direct 119C CMPS Direct 11A3 CMPU Indexed 11AC CMPS Indexed 11B3 CMPU Extended 11BC CMPS Extended 5 4 5161 4 5161 4 5161 4 5161 4 5161 4 5161 4 5(61 4 5(6) 4 5161 4 5161 4 5(61 4 5(61 4 5(61 4 5(61 4 20 2 5 4 5 4 4 4 7 3 7 3 6 3 6 3 7+ 3+ 7+ 3+ 6+ 3+ 6+ 3+ B 4 8 4 7 4 7 4 4 4 6 3 6 3 6+ 3+ 6+ 3+ 7 4 7 4 20 2 s 4 s 4 7 3 7 3 7+ 3+ 7+ 3+ B 4 B 4 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 379 · NOTE FOR USE · Execution Sequence of CLR Instruction Example: CLR (Extended) $8000 CLR $AOOO PCB $AOOO $80 Cycle# Address Data R/W Description 1 8000 7F 1 Opcode Fetch 2 8001 AO 1 Operand Address, High Byte 3 8002 00 Operand Address, Low Byte 4 FFFF * 1 VMACycle 5 AOOO 80 1 Read the Data 6 FFFF · 1 VMACycle 7 AOOO 00 0 Store Fixed "00" into Specified Location · The data bus has the data at that particular address. Cycle-by-cycle flow of CLR instruction (Direct, Extended, Indexed Addressing Mode) is shown below. In this sequence the content of the memory location specified by the operand is read before writing "00" into it. Note that status Flags, such as IRQ Flag, will be cleared by this extra data read operation when accessing the control/status register (sharing the same address between read ~d write) of peripheral devices. · The Noise of HD6309E at Bus Outputs Changing We shall notify you of the noise of the HD6309E. The noise over 0.8V may appear on the output signals when data bus or address bus outputs change from "High" to "Low". Problems and countermeasure are shown as follows. (1) The Noise at Data Bus Outputs Changing ("High-+"Low") Problem: The noise over 0.8V may appear on A15 -A13 , R/W outputs change (worst case; $FF-+$00) as shown in Figure 19. E a Au-Au R/W tAo=110ns Noise peak (worst case); about 1.5V Test condition Ta= -20°c Vee =5.5V Number of data bus lines switching from "High.. to "Low"· 8 ($FF-+$00) data bus load capacitance= 130pF Period of the noise occurrence (reference data) t = 6-34ns (Ta= -20°C) t = 8-43ns (Ta = 25° C) t = 12-54ns (Ta= 75°C) Figure 19 Noise at data bus output changing Countermeasure: If the noise level can not be reduced by controlling data bus load capacitance or reducing Vee in your application system, connect damping resistors (about 100-150!!) to data bus to reduce the noise level as shown in Figure 20. Table 11 shows the relationship between damping resistors and electrical characteristics. Connecting damping resistors to data bus is effective to reduce the noise level as shown in Figure 21. 380 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD6309E / damping resistors (about 100'1) o, Do Figure 20 Connecting damping resistors to data bus Table 11 The relationship between damping resistors and electrical characteristics HD63B09E (2MHz} HD63C09E (3M Hz} toHW t o ow toHW Ta= -20-o·c Ta= 0-75°C Ta= -20-0°c Ta= 0-75°C R=OO 20 ns 30 ns 70 ns 20 ns 30 ns R = 100-1500 , 10 ns 15 ns 80 ns 10 ns 15 ns .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 381 Test condition Vee =5.5V Ta= -2o"C data bus load capacitance = 130pF (V) V peak The waveform of the noise --Vpeak -----Vn ---- 0.50----------+-----------1 recommendable 0 50 100 150 200 R(l1) Figure 21 An example of the dependency of the noise voltage on damping resistors 382 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 -------------------------------HD63-09E 2. The Noise at Address Bus Outputs Changing ("High" -+ "Low") Problem: The noise over 0.8V may appear on BUSY, LIC, AVMA outputs when address bus outputs change (worst case; $FFFF-+$0000) as shown in Figure 22. E a BUSY LIC AVMA tco = 130ns~ noise c Noise peak (worst easel; about 1.5V Test condition Ta= -20°c Vcc=5.5V Number of address bus lines switching from "High" to "Low" =- 16 ($FFFF-+$00001 address bus load capacitance· 90pF Period of the noise occurrence lreferenco data) t · 25-65ns (Ta · -20° Cl t · 30-74ns (Ta· 26°C) t · 34-83ns (Ta· 75°C) Figure 22 Noise at address bus output changing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 383 Countermeasure: To prevent the noise on BUSY, LIC, AVMA outputs from appearing, this signals must be latched at the negative edge of E or Qclock as shown in Figure 23. An example of counter· measure circuit is shown in Figure 24. E a BUSY LIC AVMA . t ,I noise Figure 23 An example of countermeasure of the noise 74LS74 :BUSY LIC AVMA E ~: aor a · I Figure 24 An example of countermeasure circuit 384 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD64180R 8-BIT CMOS {Micro Processing Unit) The HD64180R is an 8-bit MPU developed with a microcoded execution unit and advanced CMOS manufacturing technology. It incorporates high performance CPU, a memory management unit (MMU), two channel direct memory access controller (DMAC), two channel 16-bit programmable reload timer, two channel asynchronous serial communication interface (ASCI), clock synchronous serial I/O port. The HD64180R featuring MMU is suitable for high end application requiring lM byte memory physical address space. This device including the numerous peripheral functions is also suitable for system applications which require compactness as well as high performance. · Software Features · Enhanced standard 8-bit software architecture: Upward compatible with CP/M-80® · Hardware Features · On-chip MMU supporting 1M byte memory (Provided 512K byte for DP-648) · Two channel DMAC with memory-memory, memory-1/0 and memory-memory mapped 1/0 transfer capabilities · two channel, full duplex asynchronous serial communication interface (ASCI) with programmable baud rate generator and modem control handshake signals · One channel clocked serial 1/0 port with serial/parallel shift register · Two channel 16-bit programmable reload timer for output waveform generation · Four external and eight internal interrupts · Dual bus interface compatible with Motorola 68 family and with Intel 80 family · On-chip clock generator · Operating Frequency up to 8 MHz · Low power dissipation: 50 mW at 4 MHz Operation (typ.) · TYPE OF PRODUCTS Type No. HD64180RP-6 HD64180RP-8 HD64180RF-6 HD64180RF-8 HD64180RCP·6X HD64180RCP-BX Clock Frequency 6 MHz 8 MHz 6 MHz 8 MHz 6MHz BMHz Address Space 512 Kb Package DP-648 1 Mb FP-80 FP-68 HD64180RP HD64180RCP HD64180RF (DP-645) (CP-68) (FP-80) ®HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 385 HD64180RP 0 · Im BUSREQ B RESET NMI INT1 1 Ae A10 E ~ lOE REF RlITT TENDi DJm}; CKS RXS/C'fSi 1 TXS CKA1/TEND0 RXA1 TXA1 7 CKAo/DREOo RXAo 4 TXAo DC Do CTSo R'fSO 1 01 De o, A1s 02 A11 A1e/TOUT 31 Vee Vss (DP-645) ltu 1~ 1~ II- <I .... HD64180RCP ~~~~~~S~~.~-~w~~~ 0 HD64180RF ss CKA1/TEND0 .i.ii~~~S~~~OCCddC ~ <( (FP-80) 386 NC: Not connected. Please leave open the NC pins. (CP-68) $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · BLOCK DIAGRAM Ii I~ Timing Generator Bus State Control CPU I~ I~ I~ I~ Interrupt Arn/TOUT 16-bit Programmable Reload Timers (2) TXS RXSICTS1 CKS Clocked Serial 1/0 Port ~ =J:, ~ ~ m":J' m:"J' I""!!'' "O .l!! ~ "O <( MMU OMACs (2) DREQ1 TEND1 Asynchronous SCI (channel 0) TXAo CKAo/DREQo RXAo RTSo CTSo DC Do Asynchronous SCI (channel 1) TXA1 CKA1/TEND0 RXA1 Do-D1 -vcc -vss @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 387 HD64180R~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4.Electrical characteristics · ABSOLUTE MAXIMUM RATINGS Item Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol Vee Vin Topr Tstg Value -0.3-+7.0 -0.3-Vcc+0.3 -20-+75 -55-+ 150 Unit v v ·c ·c (NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. · DC CHARACTERISTICS (Vcc=5V±10%, Vss=OV, Ta=-20-+75'C, unless otherwise noted.) Item Input "H" Voltage RESET, EXTAL,NMI Input "H" Voltage Except RESET, EXTAL,NMI Input "L" Voltage RESET, EXTAL,NMI Input "L" Voltage Except RESET, EXTAL,NMI Symbol V1H1 Condition V1H2 V1L1 V1L2 min typ Vcc-0.6 max Unit Vcc+0.3 v 2.0 Vcc+0.3 v -0.3 0.6 v -0.3 0.8 v Output "H" Voltage All Outputs Output "L'' Voltage All Outputs loH=-200µA VoH loH= -20µA Vol loL=2.2mA 2.4 Vcc-1.2 v 0.45 v Input Leakage Current All Inputs Except XTAL, EXTAL Vin=0.5 - Vcc-0.5 1.0 µA Three State Leakage Current Vin=0.5 - Vcc-0.5 1.0 µA Power Dissipation (Normal Operation) Ice f=4MHz f=6MHz 10 20 15 30 f=SMHz 20 40 Power Dissipation (SYSTEM STOP mode) f=4MHz f=6MHz 2.5 5.0 3.3 7.5 f=SMHz 5.0 10.0 Pin Capacitance Cp Vin=OV, f=1MHz Ta=25'C 12 pF 388 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA g5131 · (408) 435-8300 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-HD64180R· · AC CHARACTERISTICS (Vcc=5V±10%, Vss=OV, Ta=-20-+75'C, unless otherwise noted.) HD64180R -4 HD64180R -6 HD64180R -8 Item Symbol min max min max min max unit Clock Cycle Time tcyc 250 2000 162 2000 125 2000 ns Clock "H" Pulse Width tcHW 110 65 50 ns Clock "L" Pulse Width Clock Fall Time tcLW 110 65 15 50 15 ns 15 ns Clock Rise Time 15 15 15 ns Address Delay Time 110 90 80 ns Address Set-up Time (ME or IOE i ) ME Delay Time 1 50 30 20 ns 85 60 50 ns RD Delay Time 1 LI R Delay Time 1 85 60 100 80 50 ns 70* ns Address Hold Time 1 (ME, IOE, RD or WR r ) ME Delay Time 2 80 35 20 ns 85 60 50 ns RD Delay Time 2 85 60 50 ns UR Delay Time 2 100 80 70* ns Data Read Set-up Time Data Read Hold Time ST Delay Time 1 ST Delay Time 2 WAIT Set-up Time WAIT Hold Time to RS 50 to RH 0 tsro1 tsTD2 tws 80 70 40 0 110 110 40 40 30 0 90 90 40 40 ns ns 70 ns 70 ns ns ns Write Data Floating Delay Time twoz 100 95 70 ns WR Delay Time 1 twRDl 90 65 60 ns Write Data Delay Time twoo 110 90 80 ns Write Data Set-up Time twos 60 40 20 ns (WR i ) WR Delay Time 2 twRD2 90 80 60 ns WR Pulse Width twRP 280 170 130 ns "'For a loading capacitance of less than or equal to 40 picofarads and operating temperature from 0 to 50 degrees, substract 10 nanoseconds from the value given in the maximun columns. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 389 HD64180R Item Write Data Hold Time (WR i ) IOE Delay Time 1 IOE Delay Time 2 IOE Delay Time 3 (UR l ) INT Set-up Time (r/> l ) INT Hold Time (r/> l ) NMI Pulse Width BUSREQ Set-up Time (r/> l ) BUSREQ Hold Time (r/> l ) BUSACK Delay Time 1 BUSACK Delay Time 2 Bus Floating Delay Time ME Pulse Width (HIGH) ME Pulse Width (LOW) REF Delay Time 1 REF Delay Time 2 HALT Delay Time 1 HALT Delay Time 2 OREO i Set-up Time OREO i Hold Time TEND i Delay Time 1 TEND i Delay Time 2 Enable Delay Time 1 Enable Delay Time 2 E Pulse Width (HIGH) E Pulse Width (LOW) Symbol twoH HD64180R -4 HD64180R -6 HD64180R -8 min max min max min max unit 60 40 15 ns t1001 t1002 t1003 85 60 50 ns 85 60 50 ns 540 340 250 ns t1NTS 80 40 40 ns t1NTH 70 40 40 ns tNMIW 120 120 100 ns t s Rs 80 40 40 ns tBRH 70 40 40 ns tBAD1 tBAD2 tszo tMEWH tMEWL tRFD1 tRFD2 tHAD1 tHAD2 toRQS toRQH tTED1 trm2 teo1 tm2 PweH PweL 200 210 80 70 150 300 100 100 130 110 125 110 110 110 110 40 40 85 85 100 100 75 180 95 95 125 90 100 90 90 90 90 40 40 70 70 95 95 65 130 70 ns 70 ns 90 ns ns ns 80 ns 80 ns 80 ns 80 ns ns ns 60 ns 60 ns 70 ns 70 ns ns ns ~HITACHI 390 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Item Enable Rise Time Enable Fall Time Timer Output Delay Time CSl/0 Transmit Data Delay Time (Internal Clock Operation) CSl/O Transmit Data Delay Time (External Clock Operation) CSl/0 Receive Data Set-up Time (Internal Clock Operation) CSl/0 Receive Data Hold Time (Internal Clock Operation) CSl/0 Receive Data Set-up Time (External Clock Operation) CSl/0 Receive Data Hold Time (External Clock Operation) RESET Set-up Time RESET Hold Time Oscillator Stabilization Time External Clock Rise Time (EXTAL) External Clock fall Time (EXT AL) RESET Rise Time RESET Fall Time Input Rise Time (except EXTAL, RESET) Input fall Time (except EXTAL, RESET) HD64180R Symbol te, te1 troo tsro1 HD64180R -4 HD64180R -6 HD64180R -8 min max min max min max unit 25 20 20 ns 25 20 20 ns 300 200 200 ns 200 200 200 ns tsroe tsRSI 7 .5tcyc +300 7.5tcyc +300 7.5tcyc ns +200 tcyc tsRHI tcyc tsRSE tcyc tsRHE tcyc tRES 120 120 100 ns tREH 80 80 70 ns tosc 20 20 20 ms texr 25 25 25 ns tex1 25 25 25 ns tRr 50 50 50 ms tRI 50 50 50 ms t1, 100 100 100 ns t11 100 100 100 ns $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 391 tMED1 IOE RD tRDD1 WR LIR ST tMED2tAH t1002tAH twRD1 twRP tsTD2 DOaUtTa ---++---------------..t'I RESET~ t-EH______ --:re*1t * 1 Output buffer is off at this point. Figure 1 CPU Timing (1) 392 ®HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 UR "1 1003 m·1 Data IN "1 ME *2 REF *2 ~EWH MEW BUSREQ BUSACK ADDADTRAESS _ _ _ _ _ _ ___,__, te D ME, RD 1>---------...(1 WR. 10E ----- ·3 tttADl Figure 1 CPU Timing (2) · 1 during INTo acknowledge cycle *2 during refresh cycle ·3 Output buffer is off at this point. ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 393 omr. (at lev~ sense) IDlKif (at edge sense) ST E (Memory Read/Write) E 11/0 Read) E 0/0Write) trED1 ·4 tsro2 · 1 toRQS and toAOH are specjfied for the rising edge of clock followed by T3. *2 toRQS and tonaH are specified for the rising edge of clock. ·3 OMA cycle starts. ·4 CPU cycle starts. Figure 2 OMA Control Signals T2 T, to Rs Figure 3 E Clock Timing (1) 394 Figure 3 E Clock Timing (2) ®HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Timer Data Reg.=OOOOH troo Figure 4 Timer Output Timing Ao-A1a IHAD1 Figure 5 SLP Execution Cycle ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 395 CSVO Clock Transm~ data Ontemal Clock) Transm~ data (External Clock) Receive data (Internal Clock) Receive data (External Clock) isTDI tsroE 11tcyc tsro1 tsroE 111cyc Figure 6 CSl/O Receive/Transmit Timing Test Point Vee RL=2.2k!l ID\ 152074 \IJ/ or Equiv. C= 90pF R= 12k!l 2.0V 2.0V o.sv o.sv Reference Level (Input) 2.4V 2.4V o.sv o.sv Reference Level (Output) EXTAL ViLl EXTAL Rise time and Fall time Inputs, other than EXTAL, Rise time and Fall time Figure 7 Bus Timing Test Load (TTL Load) 396 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 INDEX 1. PIN DESCRIPTION···························...................................................................................399 2. CPU REGISTERS .............,...................................................................................................400 3. ADRESSING MODES ..........................................................................................................401 4. CPU BUS TIMING...............................................................................................................403 5. HALT AND LOW POWER OPERATION MODES ............................................................,408 6. INTERRUPTS .......................................................................................................................410 7. MEMORY MANAGEMENT UNIT (MMU) ..........................................................................420 8. DYNAMIC RAM REFRESH CONTROL..............................................................................424 9. WAIT STATE GENERATOR ................................................................................................425 10. OMA CONTROLLER (DMAC) .............................................................................................427 11. ASYNCHRONOUS SERIAL COMMUNICATION INTERFACE (ASCI) .............................434 12. CLOCKET SERIAL 1/0 PORT (CSl/O) ................................................................................439 13. PROGRAMMABLE RELOAD TIMER (PRT) .......................................................................443 14. INTERNAL 1/0 REGISTERS ................................................................................................445 15. E CLOCK OUTPUT TIMING -6800 TYPE BUS INTERFACE_ ......................................449 16. ON-CHIP CLOCK GENERATOR .........................................................................................451 17. MISCELLANEOUS····...........................................................................................................,453 18. OPERATION NOTES............................................................................................................453 19. INSTRUCTION SET .............................................................................................................459 20. INSTRUCTION SUMMARY IN ALPHABETICAL ORDER.................................................474 21. OP-CODE MAP ...................................................................................................................494 22. BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE CYCLE...................... 497 23. REQUEST ACCEPTANCES IN EACH OPERATING MODE .............................................. 505 24. REQUEST PRIORITY ...........................................................................................................507 25. OPERATION MODE TRANSITION .....................................................................................507 26. STATUS SIGNALS ...............................................................................................................509 27. PIN STATUS DURING RESET AND LOW POWER OPERATION MODES .................... 509 28. INTERNAL 1/0 REGISTERS ................................................................................................510 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 397 1 PIN DESCRIPTION XTAL UNI Crystal oscillator connection. Should be left open if an external TIL clock is used. It is noted this input is not a TIL level input. See Table D.C. characteristics. EXTAL (IN) Crystal oscillator connection. An external TTL clock can be input on this line. This input is schmitt triggered. </>(OUT) System Clock. The frequency is equal to one-half of crystal oscil- lator. RESET - CPU Reset (IN) When LOW, initializes the HD64180 CPU. All output signals are held inactive during RESET. Ao-A17 - Address Bus (OUT, 3-STATE) A,9/TOUT 19-bit address bus provides physical memory addresses of up to 512k bytes. The address bus enters the high impedance state during RESET and when another device acquires the bus as indicated by BUSREQ and BUSACK LOW. A18 is multiplexed with the TOUT output from PRT channel I. During RESET, the address bus function is selected. TOUT function can be selected under software control. D0 -D7 - Data Bus (IN/OUT, 3-STATE) Bidirectional 8-bit data bus. The data bus enters the high impe- dance state during RESET and when another device acquires the bus as indicated by BUSREQ and BUSACK LOW. RD - Read (OUT, 3-STATE) Used during a CPU read cycle to enable transfer from the exter- nal memory or 1/0 device to the CPU data bus. WR - Write (OUT, 3-STATE) Used during a CPU write cycle to enable transfer from the CPU data bus to the external memory or 1/0 device. ME - Memory Enable (OUT, 3-STATE) _Jndicates memory read or write operation. The HD64180 asserts ME LOW in the following cases. (a) When fetching instructions and operands. (b) When reading or writing memory data. (c) During memory access cycles of OMA. (d) During dynamic RAM refresh cycles. IOE - 1/0 Enable (OUT, 3-STATE) Indicates 1/0 read or write operation. The HD64180 asserts JOE LOW in the following cases. (a) When reading or writing 1/0 data. (b) During 1/0 access cycles of OMA. (c) During INT0 acknowledge cycle WAIT - Bus Cycle Wait (IN) Introduces wait states to extend memory and 1/0 cycles. If LOW at the falling edge ofT,, a wait state (Tw) is inserted. Wait states will continue to be inserted until the WAIT input is sampled HIGH at the falling edge of Tw, at which time the bus cycle will proceed to completion. E - Enable IOUTI Synchronous clock for connection to HD63 x x series and other 6800/6500 series compatible peripheral LS!s. BUSREQ - Bus Request (IN) Another device may request use of the bus by asserting BUSREQ LOW. The CPU will stop executing instructions and places the address bus, data bus, RD, WR, ME and JOE in the high impedance state. BUSACK - Bus Acknowledge (OUT) When the CPU completes bus release (in response to BUSREQ LOW), it will assert BUSACK LOW. This acknowledges that the bus is free for use by the requesting device. HALT - Halt/Sleep Status (OUT) Asserted LOW after execution of the HALT or SLP instruc- tions. Used with LIR and ST output pins to encode CPU status. LIR - Load Instruction Register (OUT) Asserted LOW when the current cycle is an op-code fetch cycle. Used with HAI,,T and ST output pins to encode CPU status. ST - Status (OUT) Used with the HALT and LIR output pins to encode CPU status. Table 1 Status Summary ST HALT LIR Operation 0 1 0 CPU operation I1st op-code fetch) 1 1 0 CPU operation (2nd op-code and 3rd op-code fetch) 1 1 1 CPU operation IMC except for op-code fetch) 0 x 1 DMA operation 0 0 0 HALT mode 1 0 1 SLEEP mode (including SYSTEM STOP mode) NOTE} X: Don't care MC: Machine cycle REF - Refreah (OUT) When LOW, indicates the CPU is in the dynamic RAM refresh cycle and the low-order 8 bits (A0-A7) of the address bus contain the refresh address. iiiiiii - Non-Maskable Interrupt (IN) When edge transition from HIGH to LOW is detected, forces the CPU to save certain state information and vector to an interrupt service routine at address 0066H. The saved state information is restored by executing the RETN (Return from Non-Maskable Interrupt) instruction. INT0 - Maskable Interrupt Level 0 (IN) When LOW, requests a CPU interrupt (unless masked) and saves certain state information unless masked by software. INT0 requests service using one of three software programmable interrupt modes. Mode 0 1 2 Operation Instruction fetched and executed from data bus. Instruction fetched and executed from address 0038H. Vector System - Low-order 8 bits vector table address fetched from data bus. In all modes, the saved state information is restored by executing RETI (Return from Interrupt) instruction. I @HITACHI 398 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 INT1 · INT2 - Maskable Interrupt Level 1, 2 (IN) When LOW, requests a CPU interrupt (unless masked) and saves certain state information unless masked by software. INT1 and INT2 (and internally generated interrupts) re~t interrupt service using a vector system similar to Mode 2 of INT0· DRE00 - OMA Request - Channel 0 (IN) When LOW (programmable edge or level sensitive), requests OMA transfer service from channel 0 of the HD64180 DMAC. DREQ0 is used for Channel 0 memory ~ 110 and memory ~ memory mapped I/0 transfers. DREQ0 is not used for memory ~ memory transfers. This pin is multiplexed with CKA0 · TEND0 - Transfer End - Channel O (OUT) Asserted LOW synchronous with the last write cycle of channel 0 OMA transfer to indicate OMA completion to an external device. This pin is multiplexed with CKA1. DRE01 - OMA Request - Channel 1 (IN) When LOW (programmable edge or level sense), requests OMA transfer service from channel l of the HD64180 DMAC. Channel I supports Memory ~ 110 transfers. TEND1 - Transfer End - Channel 1 (OUT) Asserted LOW synchronous with the last write cycle of channel I OMA transfer to indicate OMA completion to an external device. TXA0 - Asynchronous Transmit Data - Channel 0 (OUT) Asynchronous transmit data from channel 0 of the Asynchro- nous Serial Communication Interface (ASCI). RXAo - Asynchronous Receive Data - Channel 0 (IN) Asynchronous receive data to channel 0 of the ASCI. CKA0 - Asynchronous Clock - Channel 0 (IN/OUT) Clock input/output for channel 0 of the ASCI. This pin is multiplexed (software selectable) with DREQ0· RTS0 - Request to Send - Channel 0 (OUT) Programmable modem control output signal for channel 0 of the ASCI. CTS0 - Clear to Send - Channel 0 (IN) Modem control input signal for channel 0 of the ASCI. DCD0 - Data Carrier Detect - Channel 0 (IN) Modem control input signal for channel 0 of the ASCI. TXA1 - Asynchronous Transmit Data - Channel 1 (OUT) Asynchronous transmit data from channel I of the ASCI. RXA1 - Asynchronous Receive Data - Channel 1 (IN) Asynchronous receive data to channel I of the ASCI. CKA1 - Asynchronous Clock - Channel 1 (IN/OUT) Clock input/output for channel I of the ASCI. This pin is multiplexed (software selectable) with TEND,. CTS1 - Clear to Send - Channel 1 (IN) Modem control input signal for channel I of the ASCI. This pin is multiplexed (software selectable) with RXS. TXS - Clocked Serial Transmit Data (OUT) Clocked serial transmit data from the Clocked Serial 1/0 Port (CSI/0). RXS - Clocked Serial Receive Data (IN) Clocked serial receive data to the CSI/O. This pin is multiplexed (software selectable) with ASCI channel I CTS1 modem control input. CKS - Serial Clock (IN/OUT) Input or output clock for the CSl/O. TOUT - Timer Output (OUT) Pulse output from Programmable Reload Timer channel I. This pin is multiplexed (software selectable) with A18 (Address 18). Vee - Power Supply V88 - Ground Multiplexed pin descriptions A1a/TOUT During RESET, this pin is initialized as A18 pin. If either TOCI or TOCO bit in Timer Control Register (TCR) is set to I, TOUT function is selected. IfTOCI and TOCO bits are cleared to 0, A18 function is selected. CKAo/DREOo During RESET, this pin is initialized as CKA0 pin. Ifeither DMl or SM! in OMA Mode Register (DMODE) is set to l, DREQ0 function is always selected. CKA1/TEND0 _ __ During RESET, this pin is initialized as CKA1pin. IfCKA ID bit in ASCI control register ch I (CNTLA!) is set to I, TEND0 func- tion is selected. IfCKAID bit is set to 0, CKA1function is selected. RXS/CTS1 During RESET, this pin is initialized as RXS pin. If CTSIE bit in ASCI status register ch I (STATl) is set to I, CTS1 function is selected. If CTSIE bit is set to 0, RXS function is selected. ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 399 2 CPU REGISTERS The HD64180 CPU registers consist of Register Set GR, Register Set GR' and Special Registers. The Register Set GR consists of 8-bit Accumulator (A), 8-bit Flag Register (F), and three General Purpose Registers (BC, DE, and HL) which may be treated as 16-bit registers (BC, DE, and HL) or as individual 8-bit registers (B, C, D, E, H, and L) depending on the instruction to be executed. The Register Set GR' is alternate register set of Register Set GR and also contains Accumulator (A'), Flag Register (F') and three General Purpose Registers (BC', DE', and HL'). While the alternate Register Set GR' contents are not directly accessible, the contents can be programmably exchanged at high speed with those of Register Set GR. The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit R Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack Pointer (SP), and 16-bit Program Counter (PC). Fig. 8 shows CPU registers configuration. Register Set GR Accumulator A Flag Register F B Register D Register H Register C Register E Register L Register I\ General ('- Purpose Registers Special Registers Interrupt Vector Register I R Counter R Index Register IX Index Register IV Stack Pointer SP Register Set GR' Accumulator A' Flag Register F' Program Counter PC B' Register D' Register H' Register C' Register E' Register L' Register General >'" Purpose Registers Figure 8 CPU Register Configuration 2.1 Register Description 111 Accumulator IA. A'I . The Accumulator (A) serves as the primary register used for many arithmetic, logical and 1/0 instructions. 121 Flag Registers (F. F'I The flag register stores various status bits (described in the next section) which reflect the results of instruction execution. (3) General Purpose Registers (BC, BC', DE, DE', HL, HL'I The General Purp<ise Registers are used for both address and data operation. Depending on instruction, each half (8 bits) of these registers (B, C, D, E, H, and L) may also be used. (41 Interrupt Vector Register Ill For interrupts which require a vector table address to be calcu- lated dNf0 Mode 2, INT,, INT, and internal interrupts), the Inter- rupt Vector Register (I) provides the most significant byte of the vector table address. (6) R Counter (RI The least significant seven bits of the R Counter (R) serve to count the number of instructions executed by the HD64180. R is incremented for each CPU op-code fetch cycles (each LIR cycles). (6) Index Registers OX. and IV) The Index Registers are used for both address .and data opera- tions. For addressing, the contents of a displacement specified in the instruction are added to or subtracted from the Index Register to determine an effective operand address. (7) Stack Pointer ISP) The Stack Pointer (SP) contains the memory address based LIFO stack. 181 Program Counter (PC) The Program Counter (PC) contains the address of the instruc- tion to be executed and is automatically updated after each instruction fetch. (91 Flag Register (Fl The Flag Register stores the logical state reflecting the results of instruction execution. The contents of the Flag Register are used to control program flow and instruction operation. 400 ~HITACHI / Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 bit 4 2 0 LI_s___._l_z---"l~-_.__H___._l_-___,l~P_N~l_N___,~c~ Flag Register IFI S: Sig!' (bit 7) S stores the state of the most significant bit (bit 7) of the result. This is useful for operations with signed numbers in which values with bit 7 = I are interpreted as negative. Z: Zero (bit 6) Z is set to I when instruction execution results containing 0. Otherwise, Z is reset to 0. H: Half Carry (bit 4) His used by the DAA (Decimal Adjust Accumulator) instruction to reflect borrow or carry from the least significant 4 bits and thereby adjust the results of BCD addition and subtraction. PN: Parity/OverfJow (bit 21 P/V serves a dual purpose. For logical operations P/V is set to I ifthe number of I bit in the result is even and P/V is reset to 0 if the number of I bit in the result is odd. For two complement arithmetic, P/V is set to I ifthe operation produces a result which is outside the allowable range (+ 127 to - 128 for 8-bit operations, + 32767 to -32768 for 16-bit operations). N: Negative (bit 11 N is set to I if the last arithmetic instruction was a subtract oper- ation (SUB, DEC, CP, etc.) and N is reset to 0 if the last arithmetic 8-bit Register g or g' field 0 0 0 00 1 0 10 0 11 10 0 10 1 1 10 1 1 1 Register B c D E H L - A 16-bit Register zz field 0 0 0 1 1 0 1 1 Register BC DE HL AF instruction was an addition operation (ADD, INC, etc.). C: Carry (bit 0) C is set to I when a carry (addition) or borrow (subtraction) from the most significant bit of the result occurs. C is also affected by Accumulator logic operations such as shifts and rotates. 3 ADDRESSING MODES The HD64!80 instruction set includes eight addressing modes. Implied Register Register Direct Register Indirect Indexed Extended Immediate Relative IO (1) Implied Register UMP) Certain op-codes automatically imply register usage, such as the arithmetic operations which inherently reference the Accumulator, Index Registers, Stack Pointer and General Purpose Registers. 121 Register Direct (REG) Many op-codes contain bit fields specifying registers to be used for the operation. The exact bit field definition vary depending on instruction as follows. WW field 0 0 0 1 1 0 1 1 xx field 0 0 0 1 1 0 1 1 yy field 0 0 0 1 1 0 1 1 Register BC DE H L SP Register BC DE IX SP Register BC DE IV SP Suffixed H and L to ww,xx,yy,zz (ex. wwH,IXU indicate upper and lower 8-bit of the 16-bit register respectively. .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 401 (3) Register Indirect (REG) The memory operand address is contained in one of the 16-bit General Purpose Registers (B~, DE and HL). (6) Immediate (IMMED) The memory operands are contained within one or two bytes of the instruction. BC DE ft L Operand Memory (4) Indexed (INDXl The memory operand address is calculated using the contents of an lndex Register (IX or IY) and an 8-bit signed displacement specified in the instruction. op-code 1 op-code 2 displacement (d) IX or IY Operand Memory I ~ 11 a-btt operand 171 Relative IREU Relative addressing modi: is only used by the conditional and unconditional branch instructions. The branch displacement (relative to the ci>ntents of the program counter) is contained in the instruction. op-code displacement (j) ~nexadd [ Program Counter IPC) J t (5) Extended (EXT) The memory operand address is specified by two bytes contained in the instruction. op-code n m m n Operand Memory 181 10 (IOI IO addressing mode is used only by I/O instructions. This mode specifies I/O address <IDE = 0) and outputs them as follows. (I) An operand is output to A,,-A,. The Contents of Accumulator is output to A8-Aw (2) The Contents of Register Bis output to A0-A7· The Contents of Register C is output to A8-A16· (3) An operand is output to A0-A7· OOH is output to A8-A16· (useful for internal I/O register access) (4) The Contents of Register C is output to A0-A7· OOH is output to A8-A,·. (useful for internal 1/0 register access) 402 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 4 CPU BUS TIMING This section explains the HD64 l 80 CPU timing for the following operations. (I) Instruction {op-code) fetch timing. (2) Operand and data read/write timing. (3) 1/0 read/write timing. (4) Basic instruction (fetch and execute) timing. (5) RESET ti~ (6) BUSREQ/BUSACK bus exchange timing. The basic CPU operation consists of one or more "machine cycles" (MC). A machine cycle consists of three system clocks, T" T, and T3 while accessing memory or 1/0, or it consists of one system clock, Ti while the CPU internal operation. The system clock (if>) is half frequency of crystal oscillation (Ex. 8 MHz crystal~ if> of 4 MHz, 250 nsec). For interfacing to slow memory or peripherals, optional wait states (Tw) may be inserted between T, and T3· 4. 1 Instruction (op-code) Fetch Timing Fig. 9 shows the instruction (op-code) fetch timing with no wait states. _ An op-code fetch cycle is externally indicated when the LIR (Load Instruction Register) output pin is LOW. In the first half ofT,, the address bus (A0-A18) is driven with the contents of the Program Counter (PC). Note that this is the trans- lated address output of the HD64180 on-chip MMU. _ In the second half of T" the ME (Memory Enable) and RD (Read) signals are asserted LOW, enabling the memory. The op-code on the data bus is latched at the rising edge of T3 and the bus cycle terminates at the end of T3· I· Op-code Fetch Timing ·I T1 T2 Ta T1 T2 ==::x Ao-A1a Do-D1 I I I I I I i Pei X PC+ 1 i (~p-code)>------- WAIT LIR ME ::::::::::~' ::I :::::::::::::: ~ \ I I I I : :/ I I : I r-----\...__ _ __ Figure 9 Op-Code Fetch Timing Fig. 10 illustrates the insertion of wait states (Tw) into the op- code fetch cycle. Wait states (Tw) are controlled by the external WAIT input combined with an on-chip programmable wait state generator. __ At the falling edge ofT, the combined WAIT input is sampled. If WAIT input is asserted LO~a wait state (Tw) is inserted. The address bus, ME, RD and LIR are held stable during wait states. When the WAIT is sampled inactive HIGH at the falling edge of Tw, the bus cycle enters T, and completes at the end of T,. Op-code fetch cycle Figure 1O Op-Code Fetch Timing (with wait state) .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 403 4.2 Operand and Data Read/Write Timing The instruction operand and data read/write timing differs from op-code fetch timing in two ways. First, the LIR output is held inactive. Second, the read cycle timing is relaxed by one-half clock cycle since data is latched at the falling edge of T,. Instruction operands include immediate data, displacement and extended addresses and have the same timing as memory data reads. During memory write cycles the ME signal goes active in the Read cycle second half of T1· At the end ofT1, the data bus is driven with the write data. At the start of I..,_the WR signal is asserted LOW enabling the memory. ME and WR go inactive in the second halfofT3 followed by deactivation of the write data on the data bus. Wait states (Tw) are inserted as previously described for op-code fetch cycles. Fig. 11 illustrates the read/write timing without wait states (Tw), while Fig. 12 illustrates read/write timing with wait states (Tw). + Write cycle + I I Ao-A1a :==>---- 1 I I I ==~~~=====~~~~~l~~~~..:-r::::..7t'c=============== I I I I I \ I I I II I \ I I I ~~~~TI1~~~~-· \_ : \ I I I I I I I I I I I I. I j I I I I I I I I .__~,~~~~~ \__ Figure 11 Memory Read/Write Timing (without wait state) Read cycle + Write cycle T2 Tw Ao-A1a ==:x------r-----t-----t----'X~__._______,,__---~:---~ I Do-D1 - - - - - - - r 1 I - - - r - 1I -~~ · l ( I Write datB I; - - ---------\ ----- -- --'" I I ; "--r ---J '---- ; \I: i : - - - - - 1I -----r -- -- -- -- -- -- -1I --- -r- -- --\ --.l. I I ;- r--T 1--- " TI ' \ _- -- ------ -- --- 1 I I I I \ ~.----,r-----~1I ----t-'· I I II \'---41I -----;-------'I I I I '~---l-----+1-I -'--+-'f I I I I : I I I I Figure 12 Memory Read/Write Timing (with wait state) 404 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 4.3 1/0 Read/Write Timing 1/0 instructions cause data read/write transfer which differs from memory data transfer in the following three ways. The !OE (I/ 0 Enable) signal is asserted LOW instead of the ME signal. The 16bit 1/0 address is not translated by· the MMU and A16-A18 are held 1/0 read cycle LOW. At least one wait state (Tw) is always inserted for 1/0 read and write cycles (except internal 1/0 cycles). Fig. 13 shows 1/0 read/write timing with the automatically inserted wait state (Tw). 1/0 write cycle Ao-A1s _:=)(..___ __;;1/~0'-"'ad~d~re~s~s_ _.__ _ _~:_ __,X~-.-----+-'1~/0'-'-a_dd~r_e_ss_ _ _ __ Do-Dr I ------+-----i--<I ~ I l ( Write data ) I I I I '----.,.,- - - - - - - - - - - - ' J: _-_-_-_-_-_-__-_-.4J _-_-_-_--rL\.--,-----1----~-------:-----+-----:------ ~--~-------------- ~ ' I I I I 1/ ~-~~~J....-~~~~1i--~~~T""""' I 1I \ I I I I I ~~--........- - - - i i I -- - _ . . _ _ , / I I I I : I I I I = I NOTE: A1e-A18 0 for lfO cycles Figure 13 1/0 Read/Write Timing 4.4 Basic Instruction Timing An instruction may consist of a number of machine cycles including op-code fetch, operand fetch and data read/write cycles. An instruction may also include cycles for internal processing in which case the bus is idle. The example in Fig. 14 illustrates the bus timing for the data transfer instruction LD (IX+d),g. This instruction moves the contents of a CPU register (g) to the memory location with address computed by adding an signed 8-bit displacement (d) to the contents of an index register (IX). The instruction cycle starts with the two machine cycles to read the two bytes instruction op-code as indicated by LIR LOW. Next, the instruction operand (d) is fetched. The external bus is idle while the CPU computes the effective address. Finally, the computed memory location is written with the contents of the CPU register (g). @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA g5131 · (408) 435-8300 405 HD64180R------------------------------ CPU internal I I· 1. - +j T .I·- 1st op-code 2nd op-code Displacement operation ·fetch cycle fetch cycle cycle Memory Next instruction cycle+ fetch cycle .,. Ao-A1a. ]( Do-01 lJR x x PC PC+1 (DOH) (70H-77Hl PC+2 d x D<+d ~ 9 ME RD WR Machine Cycle MCI MC2 NOTE:d=d~ g = nigistar contents MC3 MC7 Figure 14 LD (IX+dl, g Instruction Timing 4.5 RESET Timing Fig. 15 shows the HD64180 hardware RESET timing. Ifthe RE- SET pin is LOW for at least six clock cycles, processing is termi- nated and the HD64180 restarts execution from (logical and physical) address OOOOOH. RESET I RESET Start .: OP-code fetch cycle T1 T2 I : : I I REW __,, 6 or more than 6 clocks I 1 11-J! : : ~--------+1---tllt---f I I I I I :)-----;1-1 - - - - - - - - - . . . . . ; . · Ao-A,. -~H-ig-h=i-m-p-e-da-n-c-e..:(KR:estart address(OOOOOH) I I Figure 15 RESET Timing 4.6 BUSREQ/BUSACK Bus Exchange Timing The HD64180 can coordinate the exchange of control, address and da1a bus ownership with another bus master. The alternate bus master can request the bus release by asserting the BUSREQ (Bus Request) input LOW. After the HD64180 releases the bus, it relinquishes control to the alternate bus master by asserting the BUSArK. (Bus Acknowledge) output LOW. The bus may be released by the HD64180at the end ofeach machine cycle. In this context a machine cycle consists of a minimum of 3 clock cycles (more if wait states are inserted) for op-code fetch, memory read/write and 1/0 read/write cycles. Except for these cases, a machine cycle corresponds to one clock cycle. When the bus is released, the address (A0-A18), da1a (D0-D7) ·and control (ME, IOE, RD, and WR) signals are placed in the high impedance state. Note that dynamic RAM refresh is not performed when the HD64180 has released the bus. The alternate bus master must pro- vide dynamic memory refreshing if the bus is released for long peri- ods of time. . _ _ _ _ __ Fig. 16 illustrates BUSREQ/BUSACK bus exchange during a memory read cycle. Fig. 17 illustrates bus exchanse when the bus release is requested during an HD64l 80 CPU internal operation. BUSREQ is sampled at the falling edge of the system clock prior to T., Ti and Tx (BUS RELEASE state). If BUSREQ is asserted LOW at the falling edge of the clock state prior to Tx, another Tx is ex- ecuted . 406 · HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 I· CPU memory read cycle + Bus release cycle ·I·CPU cycle Ao-A 1a =:){ :)>------+-------i(:c= -------'-----------'11 I I Do-D1 I I I I I I -=============::=================~),~I -------...-------II-'(:~ I I BUSREQ BUSACK Figure 16 Bus Exchange Timing (1) CPU internal operation + Bus release cycle +CPU cycle I Ao-A18 ~~~~~~~~'--~~~-r':>~~~~.......-~~r--~~ Do-D1 I I I ! )>--------1--~:c= ------------;-------~!~ I BUSREQ BUSACK Figure 17 Bus Exchange Timing (2) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 407 5 HALT AND LOW POWER OPERATION MODES The HD64180 can operate in 4 different modes. HALT mode, IOSTOP mode and two low power operation modes - SLEEP and SYSTEM STOP. Note that in all operating modes, the basic CPU clock (XTAL, EXTAL) must remain active. 5.1 HALT Mode HALT mode is entered by execution of the HALT instruction (op-code = 76H) and has the following characteristics. (1) The internal CPU clock remains active. (2) All internal and external interrupts can be received. (3) Bus exchange (BUSREQ and BUSACK) can occur. (4) Dynamic RAM refresh cycle (REF) insertion continues at the programmed interval. · (5) 1/0 operations (ASCI, CSI/O and PRT) continue. (6) The DMAC can operate. (7) The HALT output pin is asserted LOW. (8) The external bus activity consists of repeated 'dummy' fetches of the op-code following the HALT instruction. Essentially, the HD64180 operates normally in HALT mode, except that instruction execution is stopped. HALT mode can be exited in the following two ways. RESET Exit from HALT Mode Ifthe RESET input is asserted LOW for at least six clock cycles, HALT mode is exited and the normal RESET sequence (restart at address OOOOOH) is initiated. Interrupt Exit from HALT Mode When an internal or external interrupt is generated, HALT mode is exited and the normal interrupt response sequence is initiated. If the interrupt source is masked (individually by enable bit, or globally by IEF1 state), the HD64180 remainsJ!!..!IALT mode. However, NMI interrupt will initiate the normal NMI interrupt response sequence independent of the state of IEF,. HALT timing is shown in Fig. 18. I· HALT op-code fetch cycle 1 HALT mode ,I· Interrupt acknowledge cycle Ao-A1a I I I I I I I HALT op-code address~'-----H_A_L_T_1_0'-p-__cod_e_ad_d_res_s~t------- ' I I r - - - - - - - - 1 Figure 18 HALT Timing 5.2 SLEEP Mode SLEEP mode is entered by execution of the 2 byte SLP instruc- tion. SLEEP mode has the following characteristics. (1) The internal CPU clock stops, reducing power consumption. (2) The internal crystal oscillator does not stop. (3) Internal and external interrupt inputs can be received. (4) DRAM refresh cycles stop. (5) 1/0 operations using on-chip peripherals continue. (6) The internal DMAC stop. (7) BUSREQ can be received and acknowledged. (8) Address outputs go HIGH and all other control signal output become inactive HIGH. (9) Data Bus, 3-state. SLEEP mode is exited in one of two ways as shown below. RESET Exit from SLEEP Mode If the RESET input is held LOW for at least six clock cycles, the HD64180 will exit SLEEP mode and begin the normal RESET sequence with execution starting at address (logical and physical) OOOOOH. Interrupt Exit from SLEEP Mode The SLEEP mode is exited by detection of an external (NMI, INT0, INT" INT,l.J!!.internal (ASCI, CSI/O, PRT) interrupt. In the case of NMI, SLEEP Mode is exited and the CPU begins the normal NMI interrupt response sequence. In the case of all other interrupts, the interrupt response depends on the state of the global interrupt enable flag QEF,) and the individual interrupt source enable bit. If the individual interrupt condition is disabled by the corresponding enable bit, occurrence of that interrupt is ignored and the CPU remains in the SLEEP state. Assuming the individual interrupt condition is enabled, the response to that interrupt depends on the global interrupt enable flag (IEF1). If interrupts are globally enabled (IEF1= 1) and an individually enabled interrupt occurs, SLEEP mode is exited and the appropriate normal interrupt response sequence is executed. If interrupts are globally disabled (IEF,=0) and an individually enabled interrupt occurs, SLEEP mode is exited and instruction execution begins with the instruction following the SLP instruction. Note that this provides a technique for synchronization with high speed external events without incurring the latency imposed by an interrupt response sequence. Fig. 19 shows SLEEP timing. 408 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 5.3 IOSTOP Mode JOSTOP mode is entered by setting the IOSTP bit of the 110 Control Register (!CR) to I. In this case, on-chip 1/0 (ASCI, CSll 0, PRT) stops operating. However, the CPU continues to operate. Recovery from JOSTOP mode is by clearing the IOSTP bit in !CR to 0. 5.4 SYSTEM STOP Mode SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes. SYSTEM STOP mode is entered by setting the JOSTP bit in !CR to 1 followed by execution of the SLP instruction. In this mode, on-chip 1/0 and CPU stop operating, reducing power consumption. Recoveryfrom SYSTEM STOP mode is the same as recovery from SLEEP mode, noting that internal 110 sources (disabled by IOSTOP) cannot generate a recovery interrupt. SLP 2nd op-code fetch cycle SLEEP mode Op-code fetch or interrupt acknowledge cycle INTj, NMI -------+------~ Ao-A10 X SLP 2nd op-code address I I I I I 7FFFFH :x..___ __ Figure 19 SLEEP Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 409 6 INTERRUPTS The HD64 ! 80 CPU has twelve interrupt sources, four external and eight internal, with fixed priority. This section explains the CPU registers associated with interrupt processing, the TRAP interrupt, interrupt response modes and the extern~ interrupts. The detailed discussion of internal interrupt generatmn (except TRAP) is presented in the appropriate hardware section (i.e. PRT, DMAC, ASCI and CSI/0). Priority Higher 1 Priority 2 3 4 5 6 7 8 9 10 Lower 11 Priority' 12 Interrupt TRAP (Undefined Op-code Trap) I NMT (Non Maskable Interrupt) INTo (Maskable Interrupt Level 0) m1 (Maskable Interrupt Level 1) lfili2 (Maskable Interrupt Level 2) Timer 0 Timer 1 OMA channel 0 OMA channel 1 Clocked Serial VO Port Asynchronous SCI channel 0 Asynchronous SCI channel 1 Internal Interrupt External Interrupt Internal Interrupt Figure 20 Interrupt Sources 6.1 Interrupt Control Registers and Flags The HD64I 80 contains three registers and two flags which are associated with interrupt processing. Register and Flag Name I IL ITC IEF 1,IEF 2 Function Contains upper 8-bit of interrupt vector Contains lower 8-bit of interrupt vector Interrupt/Trap control Enable/ disable interrupt Access Method LO A, land LO I. A instructions 1/0 instruction (addr= 33H) 110 instruction (addr= 34H) El.DI, LOA, I, and LO A, R instructions (1) Interrupt Vector Register (I) Mode 2 for INT, external interrupt, INT, and INT2 external in- terrupts and all internal interrupts (except TRAP) use a programmable vectored technique to determine the address at which interrupt processing starts. In response to the interrupt a 16-bit address is generated. This address accesses a vector table in memory to obtain the address at which execution restarts. While the method for generation of the least significant byte of the table address differs, all vectored interrupts use the contents of I as the most significant byte of the table address. By programming the contents of I, vector tables can be relocated on 256 bytes boundaries throughout the 64k bytes logical address space. Note that I is read/written with the LD A, I and LD I, A instructions rather than 1/0 (IN, OUT) instructions. I is initialized to OOH during RESET. 121 Interrupt Vactor Low Register (IL) lntenupt Vactor Low Register Ill : VO Address = 33H) bit 7 6 5 4 Iu Iu I~ I R/W R/W R/W ~ Programmable Interrupt Soi.rce Dependent Code 0 -I This register determines the most significant three bits of the low-orde~te of the interrupt vector table address for external interrupts INT, and INT2 and all internal interrupts (except TRAP). The five least significant bits are fixed for each specific interrupt source. By programming IL the vector table can be relocated on 32 bytes boundaries. IL is initialized to OOH during RESET. (3) INT/TRAP Control Re_gister (ITC) INT!TRAP Control Register (ITC : VO Address = 34H) I I I I I ~·~-'-~--''--~_o._~~4-'-~-=-~~-=-~--'~~~0:__ TRAP UFO ITE2 ITT1 ITEO R/W R R/W R/W R/W ITC is used to handle TRAP interrupts and to enable or disable the external maskable interrupt inputs f!ilT,, INT,, and INT2 · TRAP lbit 71 This bit is set to 1 when an undefined op-code is fetched. TRAP can be reset under program control by writing it with 0, however it cannot be written with 1 under program control. TRAP is cleared to 0 during RESET. UFO: Undefined Fetch Object (bit 6) When a TRAP interrupt occurs (TRAP bit is·set to 1), the con- tents of UFO allow determination of the starting address of the undefined instruction. This is necessary since the TRAP may occur on either the second or third byte of the op-code. UFO allows the stacked PC value (stacked in response to TRAP) to be correctly ad- justed. 1f UFO = 0, the first op-code should be interpreted as the .stacked PC-1. If UFO = 1, the first op-code address is stacked PC- 2. UFO is read-only. ITE2, 1.0: Interrupt Enable 2,1,0 (bits 2-0) ITE.h.!!El and !TEO enable and disable the external interrupt inputs INT2, INT" and INT, respectively. If cleared to 0, the interrupt is masked·. During RESET, !TEO is initialized to I while ITEi and ITE2 are initialized to 0. · Interrupt Enable Flag 1,2 (IEF1, IEFzl a I nd EexFt1ercnoanltrmoalssktahbeleoivnetrearlrluepntsab(lii.en.galalnidntedrirsuabpltisnegxocefpatlNl iMntierannadl 410 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 TRAP). IfIEF, = 0, all maskable interrupts are disabled. IEF1 can be re- set to 0 by the DI (Disable Interrupts) instruction and set to 1 by the EI (Enable Interrupts) instruction. ___])te purpose of IEF2 is to correctly manage the occurrence of NM!. During NM!, the prior interrupt reception state is saved and all maskable interrupts are automatically disabled (IEF, copied to IEF, and then IEF, cleared to 0). At the end of the NM! interrupt service routine, execution of the RETN (Return from Non-maskable Interrupt) will automatically restore the interrupt receiving state (by copying IEF, to IEF1) prior to the occurrence of NM!. IEF2 state can be reflected in the P/V bit of the CPU Status register by executing LD A, I or LD A, R instructions. Table 2 shows the state of IEF1 and IEF2· CPU Operation RESET NMI RETN Interrupt except NMlandTRAP RETI TRAP El DI LDA,I LDA. R Table 2 State of IEF 1 and IEF 2 IEF, IE~ REMARKS 0 0 Inhibits the interrupt except NMI and TRAP. 0 IEF 1 Copies the contents of IEF 1 to IEF 2· IEF 2 not affected Returns from the NMI service routine. 0 0 Inhibits the interrupt except NMI and TRAP. not affected not affected 1 0 not affected not affected not affected not affected 1 0 not affected not affected Transfers the contents of IEF2 to P/V flag. Transfers the contents of IEF2 to P/V flag. 6.2 TRAP Interrupt The HD64180 generates a non-maskable (not affected by the state of IEF1) TRAP interrupt when an undefined op-code fetch occurs. This feature can be used to increase software reliability, implement an 'extended' instruction set, or both. TRAP may occur during op-code fetch cycles and also if an undefined op-code is fetched during the interrupt acknowledge cycle for INT0 when Mode 0 is used. When a TRAP interrupt occurs the HD64180 operates as follows. (1) The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1. (2) The current PC (Program Counter) value, reflecting the loca- tion of the undefined op-code, is saved on the stack. (3) The HD64180 vectors to logical address 0. Note that if logical address OOOOH is mapped to physical address OOOOOH, the vector is the same as for RESET. In this case, testing the TRAP bit in ITC will reveal whether the restart at physical address OOOOOH was caused by RESET or TRAP. The state of the UFO (Undefined Fetch Object) bit in ITC allows TRAP manipulation software to correctly 'adjust' the stacked = PC depending on whether the second or third byte of the op-code generated the TRAP. If UFO 0, the starting address of the invalid instruction is equal to the· stacked PC-1. If UFO = I, the starting address of the invalid instruction is equal to the stacked PC- 2. Fig. 21 shows TRAP Timing. Note that Bus Release cycle, Refresh cycle, DMA cycle and WAIT cycle can't be inserted just after Ttp state which is inserted for TRAP interrupt sequence. $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435·8300 411 2nd op-code ·1 1 ·-qoO TTP Do-D1 PC stacking Restart from OOOOH Op-code fetch cycle Figure 21 (a) TRAP Timing - 2nd Op-code Undefined 3rd. op-code fetch cycle · . Memory read cycle · 1 1 PC stacking Restart from OOOOH Op-code fetch cycle Figure 21 (b) TRAP Timing - 2nd Op-code Undefined 412 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 6.3 External Interrupts The HD64180 has four external hardware interrupt inputs. (I) NM! - Non-maskable Interrupt (2) ~ - Maskable Interrupt Level 0 (3) INT, - Maskable Interrupt Level I (4) INT2-=..Maskable Interrupt Level 2 __ NM!, INT, and JNT2 have fixed interrupt response modes. INT0 has three different software programmable interrupt response mod- es - Mode 0, Mode I and Mode 2. 6.4 iiiMl - Non-Maskable Interrupt The NM! interru.i!!J!!put is edge sensitive and cannot be masked by software. When NM! is detected, the HD64180 operates as follows. (I) DMAC operation is suspended by clearing the DME (DMA Main Enable) bit in DCNTL. (2) The PC is pushed onto the stack. (3) The contents of IEF1 are copied to IEF2· This saves the interrupt reception state that existed prior to NM!. (4) IEF1 is cleared to 0. This disables all external and internal maskable interrupts (i.e. all interrupts except NM! and TRAP). (5) Execution commences at logical address 0066H. The last instruction of an NM! service routine should be RETN (Return from Non-maskable Interrupt). This restores the stacked PC, allowing the interrupted program to continue. Furthermore, RETN causes IEF, to be copied to IE~storing the interrupt reception state that existed prior to the NMI. Note that NMI, since it can be accepted during HD64180 onchip DMAC o~on, can be used to externally interrupt DMA transfer. The NM! service routine can reactivate or abort the DMAC operation as required by the application. For NMI, special care must be taken to insure that interrupt inputs do not 'overrun' the NMI service routine. Unlimited NM! inputs without a corresponding number of RETN instructions will eventually cause stack overflow. Fig. 22 shows the use of~ and RETN while Fig. 23 details NM! r~se timing. NM! is edge sensitive and the internally latched NMI falling edge is held until it is sampled. If the falling edge of NM! is latched before the falling edge of clock state ~to T3 or Ti in the last machine cycle, the internally latched NM! is sampled at the falling edge of the clock state prior to T, or Ti in the last machine cycle and NM! acknowledge cycle begins at the end of the current machine cycle. IEF1 -IEF2 main O -IEF1 program~ PCH -(SP-1) PCL -(SP-2) NMl- Tf ~~~:\~Pi 11. PCH -(SP+ 1) NMI Interrupt service program RETN Last MC Figure 22 NMI Sequence NMI acknowledge cycle PC is pushed onto stack Restart from 0066H Op-code fetch Ao-A1a Do-D1 x x x x== SP-1 SP-2 0066H Instruction ( PCH >-< PCL >--0 \_/ Figure 23 iiiMl Timing $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 413 6.5 INT0 - Maskable Interrupt Level 0 __ __ __Ihe next highest priority external interrupt after NMI is INT,. INT0 is sampled at the fallin~ge of the clock state prior to T3 or Ti in the last machine cycle. lfINT0 is asserted LOW at the falli~ge of the clock state prior to T3 or Ti in the last machine cycle, INT0 is accepted. The interrupt is masked if either the IEF, flag or the !TEO (interrupt Enable 0) bit in ITC are cleared to 0. Note that after RE- SET the state is as follows. (1) IEF, is 0, so I~ is masked. (2) !TEO is I, so INT0 is enabled by execution of the EI (Enable Interrupts) instruction. The INT0 interrupt is unique in that three programmable inter- rupt response modes are available - Mode 0, Mode I, and Mode 2. The specific mode is selected with the IM 0, IM I and IM 2 (Set In- terrupt Mode) instructions. During RESET, the HD64180 is initialized to use Mode 0 for INT,. The three interrupt response modes for INT0 are... (I) Mode 0 - Instruction fetch from data bus. (2) Mode I - Restart at logical address 0038H. (3) Mode 2 - Low byte vector table address fetch from data bus. INT0 Mode0 During the interrupt acknowledge cycle, an instruction is fetched from the data bus (D0-D7) at the rising edge of T3· Often, this instruction is one of the eight single byte RST (RESTART) instructions which stack the PC and restart execution at a fixed logical address. However, multibyte instructions can be processed if the interrupt acknowledging device can provide a multibyte response. Unlike all other interrupts, the PC is not automatically stacked. Note that TRAP interrupt will occur if an invalid instruction is fetched during INT, Mode 0 interrupt acknowledge. Fig. 24 shows INT;; Mode 0 Timing. ..... .... Last MC llNTo acknowledge cycle! AST instruction execution ,.. PC is pushed onto stack T, T2 Tw" Tw" T3 Ti Ti T, T· T3 T, T2 T3 liiilo ~~~/~------ Ao-A1a Do-Dr AST instruction ------~o>----<( PCH MC: Machine Cycle · Two wait states are automatically inserted. Figure 24 INT 0 Mode 0 Timing (RST Instruction on the Data Bus) 414 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 INT0 Modtl When INT0 is received, the PC is stacked and instruction execu- tion restarts at logical address 0038H. Both IEF1 and IEF2 flags are reset to 0, disabling all maskable interrupts. The interrupt service routine should normally terminate with the El (Enable Interrupts) instruction followed by the RETI (Return from Interrupt) instruction, so that the interrupts are reenabled. Fig. 25 shows the use of INT0 (Mode I) and RETI. Fig. 26 shows INT0 Mode I timing. -··llmain 11 0 -IEF1, IEF2 PCH -(SP-1) PCL -(SP-2) INTo (Mode1)- INT o (Mode 1) Interrupt service program El (1 - IEf,, IEF2) RETI Figure 25 IN"f';;"Mode 1 Interrupt Sequence Last MC iJiITO acknowledge cycle Op-code fetch cycle PC is pushed onto stack '-----~/ X X SP-1 SP-2 0038H 'C_ Do-D1 ST PCH PCL \'-_ _____,/ · Two wait states are automatically inserted. Figure 26 INT 0 Mode 1 Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA gs131 · (408) 435-8300 415 iiiIT0 Mode 2 This method determines the restart address by reading the contents of a table residing in memory. The vector table consists of up to 128 two-byte restart addresses stored in low byte, high byte order. The vector table address is located on 256 bytes boundaries in the 64k bytes logical address space as programmed in the 8-bit In- terrupt Vector Register (I). Fig. 27 shows the INT0 Mode 2 Vector acquisition. During INT0 Mode 2 acknowledge cycle, first, the low-order 8 bits of vector is fetched from the data bus at the rising edge of T8 and CPU acquires the 16-bit vector. Next, the PC is stacked. Finally, the 16-bit restart address is fetched from the vector table and execution commences at that address. Note that external vector acquisition is indicated by LIR and !OE both LOW. Two wait states (Tw) are automatically inserted for external vector fetch cycles. During RESET the Interrupt Vector Register (I) is initialized to OOH and, if necessary, should be set to a different value prior to the occurrence of a TliIT;; Mode 2 interrupt. Fig. 28 shows INT0 Mode 2 interrupt Timing. Memory 16-bit Vector Interrupt Vector 8-bit on Register I Data Bus .... ., Vector+ 1 High-order 8 bits of starting address Off.set Vector Low-order 8 bits of starting address 256 Bytes Vector Table Figure 27 INT0 Mode 2 Vector Acquisition 416 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Last MC mo acknowledge cycle OP-code fetch cycle J Vector lower Interrupt manipulation address read PC is pushed onto stac~ cycle I I I T1 T2 Tw"Tw*T3 Ti T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 ==x...___ X: Ao-A1a Starting addres-; X X X PC_ _ _ SP-1 SP-2 Vector y.yr--ec-to_r...,..+"""'iX Do-Dr ST Lower vector ~ Starting address Starting address ----(lower address) (upper address) PCH PCL........ \-------I ·Two wait states are automatically inserted. Figure 28 INT0 Mode 2 Timing 6.6 iNT,, INT2 _ _ The operation o( external interrupts INT, and IN!._ is av~ mode similar to INT0 Mode 2. The difference is that INT1 and INT2 generate the low-order byte of vector table address using the I~ (In- terrupt Vector Low) register rather than fetching it from the data bus. This is also the interrupt response sequence used for all inter- nal interrupts (except TRAP). As shown in Fig. 29 the low-order byte of vector table address is comprised of the most significant three bits of the software pro- grammable IL register and the least significant five bits which are a unique fixed value for each interrupt ONT;", i'iiiT, and internal) source. INT1 and INT, are globally masked by IEF, = 0. Each is also in- dividually maskable by respectively clearing the ITEi and ITE2 (bits I, 2) of the INT/TRAP control register to 0. During RESET, IEF,, ITEi and ITE2 bits are initialized to 0. 6.7 Internal Interrupts Internal interrupts (except TRAP) use the same vectored re- sponse mode as INT1 and fNT, (Fig. 29). Internal interrupts are globally masked by IEF, = 0. Individual internal interrupts are enabled/disabled by programming each individual 1/0 (PRT, DMAC, CSI/O, ASCI) control register. The lower vector of INT,, INT,, and internal interrupt are summarized in Table 3. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 417 16-bit Vector I I IL Fixed Code . (5 bits) . Memory H + 1 High-order 8 bits of starting address r Low-order 8 bits of starting address 32 Bytes Vector table H Figure 29 INT 1, INT2and Internal Interrupts Vector Acquisition Table 3 Interrupt Source and Lower Vector Interrupt Source INT, IN"G_ PRT channel 0 PRT channel 1 OMA channel 0 OMA channel 1 CSl/O ASCI channel 0 ASCI channel 1 · Programmable IL Priority Highest Lowest b.........7 b.........e b......5 . . . Fixed Code b, b3 b2 b, bo 0 0 0 0 0 0 0 0 10 00 100 00 110 0 1000 010 10 0 1 10 0 0 1 1 10 10 0 0 0 418 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Interrupt Acknowledge Cycle Timing Fig. 30 shows interrupt acknowle~ycle timing for internal in- terrupts, INT1, and INT,. INT1 and INT, are sampled at the falling ed~ clock state prior to T3 or Ti in the last machine cycle. If INT1 or INT2 is asserted LOW at the falling edge of clock state prior to T, or Ti in the last machine cycle, the interrupt request is accepted. Op-code LastMC~·--l~~~__:lN'f..._._T~1,~IN~T~2~,~in~t~em""'.:al~i~nt~e~rru~p~t~a~c~k~no~w~l~ed~g~e~c~y~c~le:._~~~~~~~~~~~~~--t~f_et_c_h_c_y_c_~--j PC Stacking Vector Table Read -1. Tt Tw" Tw" Ta Ta Starting address MC: Machine Cycle. · Two wait states are automatically inserted. Figure 30 INT1, INT2and Internal Interrupts Timing 6.8 Interrupt Sources and Reset (1) Interrupt Vector Register (I) All bits are reset to 0. Since I = O locates the vector tables starting at logical address OOOOH, vectored interrupts (INT0 Mode 2, INT1, INT, and internal interrupts) will overlap with fixed restart interrupts like RESET (0), NMI (0066H), INT0 Mode 1 (0038H) and RST (OOOOH - 0038H). The vector table (s) can be built elsewhere in memory and located on 256 bytes boundaries by reprogramming I with the LD I, A instruction. (2) IL Register Bits 7 - 5 are reset to 0. The IL Register can be programmed to locate the vector table for INT1, INT2 and internal interrupts on 32 bytes sub-boundaries within the 256 bytes area specified by I. (3) IEF1 · IEF2 Flags Reset to 0. Interrupts other than NM! and TRAP are disabled. (4) ITC Register !TEO are set to 1. ITEi and ITE2 are reset to 0. = INT0 can be enabled by the EI instruction, which sets IEF1 1. To enable INT1 and INT2 also requires that the ITEi and ITE2 bits be respectively set = I by writing to ITC. 151 1/0 Control Registers Interrupt enable bits reset to 0. All HD64180 on-chip 1/0 (PRT, DMAC, CSI/O, ASCI) inter- rupts are disabled and can be individually enabled by writing to each 1/0 control register interrupt enable bit. 6.9 Difference between INT0 interrupt and the other interrupts liNT,. INT2 and internal interrupts) in the interrupt acknowledge cycles As shown in Fig. £i,__Fig. 26, Fig. 28 and Fig. 30, the interrupt acknowledge c~ofl~ is different from those of the other interrupts, that is, INT1t INT, and internal interrupts concerning the state of control signals. The state of the control signals in each interrupt acknowledge cycle are shown below. INT0 interrupt acknowledge cycle: LIR = 0, JOE= O~T = 0 INT1t INT2, and internal interrupt acknowledge cycle: LIR = !, JOE= I, ST= 0 @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 419 7 MEMORY MANAGEMENT UNIT (MMU) The HD64180 contains an on-chip MMU which performs the translation of the CPU 64k bytes (16-bit addresses- OOOOH to FFFFH) logical memory address space into a 512k bytes 09-bit addresses- OOOOOH to 7FFFFH) physical memory address space. Address translation occurs internally in parallel with other CPU operation. 7 .1 Logical Address Spaces The 64k bytes CPU logical address space is interpreted by the MMU as consisting of up to three separate logical address areas, Common Area 0, Bank Area and Common Area I. As shown in Fig. 31 a variety of logical memory configurations are possible. The boundaries between the Common and Bank Areas can be programmed with 4k bytes resolution. Common Area 1 Bank Area Common Area 0 Common Area 1 Bank Area Common Area 1 Common Area 0 Common Area 1 Figure 31 Logical Address Mapping Examples 7.2 Logical to Physical Address Translation Fig. 32 shows an example in which the three logical address space portions are mapped into a 5l 2k bytes physical address space. The important points to note are that Common and Bank Areas can overlap and that Common Area I and Bank Area can be freely relocated (on 4k bytes physical address boundaries). Common Area 0 (if it exists) is always based at physical address OOOOOH. . - - - - - - - - . 7FFFFH FFFFH ~------. Common Area 1 ommon Bas·e;...-1-.1------1 Bank Area Bank Base y Common Area C COOCH.....__ _ _ _..........., 0 xyz Logical Address Space .__ _...,......_._x _ _ ____,OOOOOH Physical Address Space Figure 32 Logical - Physical Memory Mapping Example 420 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 7.3 MMU Block Diagram The MMU block diagram is shown in Fig. 33. The MMU trans- lates internal 16-bit logical addresses to external 19-bit physical ad- dresses. Internal Address/Data Bus 4 LA12-LA1s MMU Common/Bank Area Register; CBAR (8) Memory anagement Unit MMU Common Base Register; CBR (7) MMU Bank Base Register; BBR (7) 7 PA12-PA10 LA: Logical Address PA: Physical Address Figure 33 MMU Block Diagram Whether address translation takes place depends on the type of 'CPU cycle as follows. (I) Memory Cycles Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes, hardware interrupt vector fetch and software interrupt restarts. (2) 1/0 Cycles The MMU is logically bypassed for 1/0 cycles. The 16-bit logical 1/0 address space corresponds directly with the 16-bit physical 110 address space. The upper three bits (A16-A18) of the physical address are always 0 during 1/0 cycles. "000" PA1a LA1s ~A,. PA1s LAo P~o Logical Address Physical Address Figure 34 1/0 Address Translation (3) DMA Cycles When the HD64180 on-chip DMAC is using the external bus, the MMU is physically bypassed. The 19-bit source and destination registers in the DMAC are directly output on the physical address bus (A0-A18). @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 421 7.4 MMU Registers Three MMU registers are used to program a specific configuration of logical and physical memory. (1) MMU Common/Bank Area Register (CBAR) (2) MMU Common Base Register (CBR) (3) MMU Bank Base Register (BBR) CBAR is used to define the logical memory organization, while CBR and BBR are used to relocate logical areas within the 512k bytes physical address space. The resolution for both setting boundaries within the logical space and relocation within the physical space is 4k bytes. The CAR field of CBAR determines the start address of Com- mon Area I (Upper Common) and by default, the end address of the Bank Area. The BAR field determines the start address of the Bank Area and by default, the end address of Common Area 0 (Lower Common). The CA and BA fields of CBAR may be freely programmed subject only to the restriction that CA may never be less than BA. Fig. 35 and Fig. 36 shows example of logical memory organizations associated with different values of CA and BA. 2 3 4 Common Area 1 BankArea Common Area 1 Bank Area Common Area 1 Common Area 0 Common Area 1 Common Area 0 1 Common Area lower limit address > Bank Area lower limit address > OOOOH 1 Common Area lower limit address > Bank Area lower limit address = OOOOH (RESET condition) 1 Common Area lower limit address Bank Area lower limit address > OOOOH Common Area 1 lower limit address = Bank Area lower limit address = OOOOH Figure 35 Logical Memory Organization MMU Common/Bank Area Register FFFFH Common Area 1 l1'1lol1I o DOOOH 1-------1 ----+CFFFH D1 De Os 04 Bank Area MMU Common/Bank Area Register Io 11' oIo I 4 ---~.~-~.~~ 1---------1 Os D2D1Do Common Area 0 OOOOH ~----- Figure 36 Logical Space Configuration (Example) 422 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 7.5 MMU Register Description (1) MMU Common/Bank Area Register (CBAR) CBAR specifies boundaries within the HD64180 64k bytes logi- cal address space for up to three areas, Common Area 0, Bank Area, and Common Area 1. MMU Common/Bank Area Register ICBAR : 1/0 Address = 3AH) CA3 R/W CA2 R/W CA1 R/W CAO R/W BA3 R/W BA2 R/W BA1 R/W BAO R/W CA3-CAO: CA (bits 7-4) CA specifies the start (low) address (on 4k bytes boundaries) for the Common Area 1. This also determines the last address of the Bank Area. All bits of CA are initialized to 1 during RESET. BA3-BAO: BA (bits 3-0) BA specifies the start (low) address (on 4k bytes boundaries) for the Bank Area. This also determines the last address of the Common Area 0. All bits of BA are initialized to 0 during RESET. (2) MMU Common Base Register (CBRI CBR specifies the base address (on 4k bytes boundaries) used to generate a 19-bit physical address for Common Area 1 accesses. All bits of CBR are initialized to 0 during RESET. MMU Common Base Register ICBR : 1/0 Address= 38H) bit.,_..:..__,_-"--,-..:_-,--'--,-3'-,--,--,-, CB6 R/W CBS R/W CB4 R/W CB3 R/W CB2 R/W CB1 R/W CBO R/W (3) MMU Bank Base Register IBBR) BBR specifies the base address (on 4k bytes boundaries) used to generate a 19-bit physical address for Bank Area accesses. All bits of BBR are initialized to 0 during RESET. MMU Benk Bese Register IBBR : 1/0 Address = 39H) bn;--=-,......,,-~a'-,__::_s_,--·-,--~,---,---,---, I 886 I 885 I 884 I 883 882 BB1 BBQ R/W R/W R/W R/W R/W R/W R/W 7.6 Physical Address Translation Fig. 37 shows the way in which physical addresses are generated based on the contents of CBAR, CBR and BBR. MMU comparators classify an access by logical area as defined by CBAR. Depending on which of the three potential logical areas (Common Area 1, Bank Area or Common Area 0) is being accessed, the appropriate 7-bit base address is added to the upper 4 bits of the logical address, yielding a 19-bit physical address. CBR is associated with Common Area 1 accesses. Common Area 0 accesses use a (non-accessible, internal) base register which contains 0. Thus, Common Area 0, if defined, is always based at physical address OOOOOH. MMU Common/ Bank Area Register MMU Common/ Bank Area Register Da-Oo 4 Comparator 4 4 15 12 11 0 . - - - - - - - . . - - - - - - - - - - - - - - - - , Logical Address (64k) MMU Common Base Reg. MMU Benk Bese Reg. 4 o o o o o o o..____,. Adder 18 12 11 Figure 3 7 Physical Address Generation 0 Physical Address (512k) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 423 7.7 MMU and RESET During RESET, all bits of the CA field of CBAR are set to 1 while all bits of the BA field of CBAR, CBR, and BBR are cleared to 0. The logical 64k bytes address space corresponds directly with the first 64k bytes (OOOOH to FFFFH) of the 512k bytes (OOOOOH to 7FFFFH) physical address space. Thus, after RESET, the HD64180 will begin execution at logical and physical address 0. 7.8 MMU Register Access Timing When data is written into CBAR, CBR, or BBR, the value will be effective from the cycle immediately following the 110 write cycle which updates these registers. Care must be taken during MMU programming to insure that CPU program execution is not disrupted. Observe that the next cycle following MMU register programming will normally be an opcode fetch from the newly translated address. One simple technique is to localize all MMU programming routines in a Common Area that is always enabled. 8 DYNAMIC RAM REFRESH CONTROL The HD64 I 80 incorporates a dynamic RAM refresh control cir- cuit including 8-bit refresh address generation and programmable refresh timing. This circuit generates asynchronous refresh cycles inserted at the programmable interval independent of CPU program execution. For systems which don't use dynamic RAM, the refresh function can be disabled. When the internal refresh controller determines that a refresh cycle should occur, the current instruction is interrupted at the first breakpoint between machine cycles. The refresh cycle is inserted by placing the refresh address on A0-A7 and the REF output is driven LOW. Refresh cycles may be programmed to be either two or three clock cycles in duration by programming the REFW (Refresh Wait) bit in Refresh Control Register (RCR). Note that the external WAIT input and the internal wait state generator are not effective during refresh. Fig. 38 shows the timing of a refresh cycle with a refresh wait (TRw) cycle. MCi Refresh cycle MCi+1 TRw* TR2 Refresh signal !Internal signal) Refresh address X Ao-A1 X'------- z____ ME ___________ ~ I \ ______ __ NOTE: * If three refresh cycles are specified, TRW. is inserted. Otherwise, TRW is not inserted. MC: Machine Cycle Figure 38 Refresh Timing 8.1 Refresh Control Register (RCRJ RCR specifies the interval and length of refresh cycles, as well as enabling or disabling the refresh function. Refresh Control Register IRCR: 1/0 Address= 36H) I I I bit.~_:__~-=-"-.--=-__,.--'-4-,---=--.-"--,--'-,----, REFE REFW CYC1 CYCO RIW R/W R/W R/W REFE: Refresh Enable (bit 7) = = REFE 0 disables the refresh controller while REFE 1 ena- bles refresh cycle insertion. REFE is set to I during RESET. REFW: Refresh Wait (bit 6) REFW = 0 causes the refresh cycle to be two clocks in duration. REFW = I causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle (TRw). REFW is set to 1 during RE- SET. CYC1, 0: Cycle Interval (bits 1-0) CYCl and CYCO specify the interval (in clock cycles) between refresh cycles. Jn the case of dynamic RAMs requiring 128 refresh cycles every 2 ms (or 256 cycles every 4 ms), the required refresh interval is less than or equal to 15.625 µs. Thus, the underlined values indicate the best refresh interval depending on CPU clock frequency. CYCO and CYCl are cleared to 0 during RESET. · 424 ®HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 CYC1 CYCO Insertion interval 0 0 10 states 0 1 20 states 1 0 40 states 1 1 BO states · calculated interval Table 4 Refresh Interval cJ>: lOMHz (1.0µs)· (2.0µs)· (4.0µs)" (8.0µs)· Time interval B MHz 6MHz (1.25 µs)" (2.5 µs)" (5.0µs)" (10.0µs)" 1.66 µs 3.3 µs 6.6 µs 13.3 µS 4MHz 2.5 µs 5.0µs 10.0µs 20.0 µs 2.5 MHz 4.0µs ~ 16.0 µs 32.0 µs 8.2 Refresh control and reset After RESET, based on the initialized value ofRCR, refresh cy- cles will occur with an interval of 10 clock cycles and be 3 clock cycles in duration. 8.3 Dynamic RAM refresh operation notes (1) Refresh cycle insertion is stopped when the CPU is in the fol- lowing states. (a) During RESET _ __ (b) When the bus is released in response to BUSREQ (c) During SLEEP mode (d) During WAIT states (2) Refresh cycles are suppressed when the bus is released in re- sponse to BUSREQ. However, the refresh timer continues to operate. Thus, the time at which the first refresh cycle occurs after the HD64 l 80 re-acquires the bus depends on the refresh timer, and has no timing relationship with the bus exchange. (3) Refresh cycles are suppressed during SLEEP mode. Ifa refresh cycle is requested during SLEEP mode, the refresh cycle re- quest is internally 'latched' (until replaced with the next re- fresh request). The 'latched' refresh cycle is inserted at the end of the first machine cycle after SLEEP mode is exited. After this initial cycle, the time at which the next refresh cycle will occur depending on the refresh time, and has no timing rela- tionship with the exit from SLEEP mode. (4) Regarding (2) and (3), the refresh address is incremented by 1 for each successful refresh cycle, not for each refresh request. Thus, independent of the number of 'missed' refresh requests, each refresh bus cycle will use a refresh address incremented by 1 from that of the previous refresh bus cycles. 9 WAIT STATE GENERATOR 9.1 Wait State Timing To ease interfacing with slow memory and 1/0 devices, the HD64180 uses wait states (Tw) to extend bus cycle timing. A wait state(s) is inserted based on the combined (logical OR) state of the external WAIT input and an internal programmable wait state (Tw) generator. Wait states (Tw) can be inserted in both CPU execution and DMA transfer cycles. 9.2 WAIT Input When the external WAIT input is asserted LOW, wait state (Tw) are inserted between T2 and T3 to extend the bus cycle duration. The WAIT input is sampled at the falling edge of the system clock in T2 or Tw. If the WAIT input is asserted LOW at the falling edge of the system clock in Tw, another Tw is inserted into the bus cycle. Note that WAIT input transitions must meet specified set-up and hold times. This can easily be accomplished by externally synchronizing WAIT input transitions with the rising edge of the system clock. Dynamic RAM refresh is not performed during wait states (Tw) and thus systems designs which uses the automatic refresh function must consider the affects of the occurrence and duration of wait states (Tw). Fig. 39 shows WAIT timing. \ C\!''' I 7! ~~~~~~~~--'-+...._~~~~,~~~- I \ ~~~~~~~~~~~~~~~ Figure 39 WAIT Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 425 9.3 Programmable Wait State Insertion In addition to the WAIT input, wait states (Tw) can also b.e programmably inserted using the H064 I 80 on-chip wait state generator. Wait state (Tw) timing applies for both CPU execution and on-chip OMAC cycles. By programming the 4 significant bits of the OMA/WAIT Control Register (OCNTL), the number of wait states (Tw) automatically inserted in memory and 1/0 cycles can be separately specified. Bits 4-5 specify the number of wait states (Tw) inserted for 1/0 access and bits 6-7 specify the number of wait states (Tw) inserted for memory access. OMA/WAIT Control Register (DCNTL : l/D Address = 32H) b;tl~1 1M:~1 ~"I:~ I: R/W R/W R/W R/W The number of wait states (Tw) inserted in a specific cycle is the maximum of the number requested by the WAIT input, and the number automatically generated by the on-chip wait state generator. MWl1, MWIO: Memory Wait Insertion (bits 7-6) For CPU and OMAC cycles which access memory (including memory mapped 1/0), 0 to 3 wait states may be automatically inserted depending on the programmed value in MWII and MWIO. MW11 0 0 1 1 MWIO 0 1 0 1 The number of wait states 0 1 2 3 IWl1, IWIO: 1/0 Wait Insertion (bits 5-4) For CPU and OMA cycles which access external 1/0 (and inter- rupt acknowledge cycles), I to 6 wait states (Tw) may be automat- ically inserted depending on the programmed value in IWII and IWIO. IWl1 0 0 1 1 For external 1/0 registers accesses IWIO 0 1 1 2 0 3 1 4 For internal 1/0 registers accesses The number of wait states For INT0 interrupt acknowledge cycles when LIR is LOW For INT 1, INT 2 and internal interrupts acknowledge cy- cles (Note (2)) 2 0 4 (Note (1)) 5 2 6 For NMI interrupt acknowledge cycles when LIR is LOW (Note (2)) 0 NOTE: (1) For HD64180 internal 1/0 register access 11/0 addresses OOOOH-003FH). IWl1 and IWIO do not determine wait state (Tw) timing. For ASCI, CSI/ 0 and PRT Data Register accesses. 0 to 4 wait states {Tw) will be generated. Wait states inserted during access to these registers is a function of internal synchronization requirements and CPU state. All other on-chip 1/0 register accesses (i.e. MMU, DMAC, ASCI Control Registers, etc.) have 0 wait states inserted and thus require only three clock cycles. (2) For interrupt acknowledge cycles in which UR is HIGH, such as interrupt vector table read and PC stacking cycle, memory access timing applies. 9.4 WAIT Input and RESET During RESET, MW!l, MWIO, !Wll and IW!O are all set to I, selecting the maximum number of wait states (Tw) (3 for memory accesses, 4 for external 1/0 accesses). Also, note that the WAIT input is ignored during RESET. For example, if RESET is detected while the H064180 is in a wait state (Tw), the wait stated cycle in progress will be aborted, and the RESET sequence initiated. Thus, RESET has higher priority than WAIT. 426 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 10 DMA CONTROLLER IDMAC) The HD64180 contains a two channel DMA (Direct Memory Access) controller which supports high speed data transfer. Both channels (channel 0 and channel I) have the following capabilities. Memory Address Space Memory source and destination addresses can be directly speci- fied anywhere within the 512k bytes physical address space using 19-bit source and destination memory addresses. In addition, memory transfers can arbitrarily cross 64k bytes physical address boundaries without CPU intervention. 1/0 Address Space 1/0 source and destination addresses can be directly specified anywhere within the 64k bytes 1/0 address space (16-bit source and destination l/O addresses). Transfer Length Up to 64k bytes can be transferred based on a 16-bit byte count register. DREQ Input Level and edge sense DREQ input detection are selectable. TEND Output Used to indicate DMA completion to external devices. Transfer Rate Each byte transfer can occur every six clock cycles. Wait states can be inserted in DMA cycles for slow memory or 1/0 devices. At the system clock (./,) = 6 MHz, the DMA transfer rate is as high as 1.0 megabytes/second (no wait states). Additional feature disk for DMA interrupt request by DMA END. Each channel has the following additional specific capabilities. Channel 0 · Memory ~ memory, memory ~ 1/0, memory ~ memory mapped 1/0 transfers · Memory address increment, decrement, no-change · Burst or cycle steal memory ·~ memory transfers · DMA to and from both ASCI channels · Higher priority than DMAC channel I Channel I · Memory ~ 1/0 transfer · Memory address increment, decrement DMAC Registers Each channel of the DMAC (channel 0, I) has three registers specifically associated with that channel. Channel 0 SARO DARO BCRO Source Address Register Destination Address Register Byte Count Register Channel I MARI IARI BCRI Memory Address Register 1/0 Address Register Byte Count Register The two channels share the following three additional registers in common. DSTAT DMA Status Register DMODE - DMA Mode Register DCNTL - DMA Control Register 10.1 DMAC Block Diagram Fig. 40 shows the HD64180 DMAC Block Diagram. Internal Address/Data Bus OMA Source Address Register chO: SARO (19) OMA Destination Address Register chO : DARO (19) OMA Byte Count Register chO : BCRO (16) OMA Memory Address Registerch1: MAR1 119) OMA VO Address Register ch 1 : IAR1 (16) OMA Byte Count Register ch 1 : BCR 1 (16) OMA Status Register : OSTAT (8) OMA Mode Register : OMOOE (8) OMA/WAIT Control Register : OCNTL (8) OMA Control Priority & Request Control - DREOo -DREQ1 Bus & CPU Control lncrementer/Decrementer (19) ~ TEND1 Interrupt Request Figure 40 OMAC Block Diagram .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 427 10.2 DMAC Register Description (1) OMA Source Address Register Channel 0 (SARO: 1/0 Address = 20H to 22H} Specifies the physical source address for channel 0 transfers. The register contains 19 bits and may specify up to 5I 2k bytes memory addresses or up to 64k bytes 1/0 addresses. Channel 0 source can be memory, 110 or memory mapped 1/0. (2) OMA Destination Address Register Channel O (DARO: 1/0 Address = 23H to 25H) Specifies the physical destination address for channel 0 transfers. The register contains 19 bits and may specify up to 512k bytes memory addresses or up to 64k bytes 1/0 addresses. Channel 0 destination can be memory, 110 or memory mapped 1/0. (3) OMA Byte Count Register Channel 0 (BCRO: 1/0 Address = 26H to 27H} Specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64k bytes transfers. When one byte is transferred, the register is decremented by one. If "n" bytes should be transferred, "n" must be stored before the DMA operation. (4) OMA Memory Address Register Channel 1 (MAR1: 1/0 Address = 28H to 2AH) Specifies the physical memory address for channel I transfers. This may be destination or source memory address. This register contains 19 bits and may specify up to 512k bytes memory addresses. (5) OMA 1/0 Address Register Channel 1 (IAR1: 1/0 Address = 2BH to 2CH} Specifies the 110 address for channel I transfers. This may be destination or source 1/0 address. This register contains 16 bits and may specify up to 64k bytes 110 addresses. (6) OMA Byte Count Register Channel 1 (BCR1: 1/0 Address = 2EH to 2FH} Specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64k bytes transfers. When one byte is transferred, the register is decremented by one. (7) OMA Status Register (DSTAT} DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DST AT also allows determining the status of a DMA transfer i.e. completed or in progress. OMA Status Register (DSTAT : 1/0 Address = 30H) I bit~-'-___,.-:_,-_::_..-_4.:_.,....-"-..--'--,--,--0--, DE1 DEO DWE1 DWEO DIE1 DIEO DME R/W R/W w w R/W R/W DE1: OMA Enable Channel 1 (bit 7) When DEi = I and DME = I, channel I DMA is enabled. When a DMA transfer terminates (BCRI = 0), DEi is reset to 0 by the DMAC. When DEl = 0 and the DMA interrupt is enabled (DIEi = !), a DMA interrupt request is made to the CPU. To perform a software write to DEi, DWEI should be written with 0 during the same register write access. Writing DEi to 0 disa- bles channel 1 DMA, but DMA is restartable. Writing DEl to I enables channel 1 DMA and automatically sets DME (DMA Main Enable) to I. DEl is cleared to 0 during RESET. DEO: OMA Enable Channel 0 (bit 6} When DEO = I and DME = I, channel 0 OMA is enabled. When a OMA transfer terminates (BCRO = 0), DEO is cleared to 0 by the DMAC. When DEO = 0 and the DMA interrupt is enabled (DIEO = 1), a DMA interrupt request is made to the CPU. To perform a software write to DEO, DWEO should be written with 0 during the same register write access. Writing DEO to 0 disables channel 0 DMA. Writing DEO to I enables channel 0 DMA and automatically sets DME (DMA Main Enable) to 1. DEO is cleared to 0 during RESET. DWE1: DE1 Bit Write Enable (bit 5) ____,_ When performing any software write to DEi, DWEI should be written with 0 during the same access. DWEl write value of 0 is not held and DWEI is always read as I. DWEO: DEO Bit Write Enable (bit 4) When performing any software write to DEO, DwEo should be written with 0 during the same access. DWEO write value of 0 is not held and DWEO is always read as 1. DIE1: OMA Interrupt Enable Channel 1 (bit 3) When DIEi is set to I, the termination of channel I DMA trans- fer (indicated when DEi = 0) causes a CPU interrupt request to be generated. When DIEi = 0, the channel I DMA termination inter- rupt is disabled. DIE! is cleared to 0 during RESET. DIEO: OMA Interrupt Enable Channel 0 (bit 21 When DIEO is set to I, the termination channel 0 ofDMA transfer (indicated when DEO = 0) causes a CPU interrupt request to be generated. When DIEO = 0, the channel 0 DMA termination inter- rupt is disabled. DIEO is cleared to 0 during RESET. DME: OMA Main Enable (bit 0) A DMA operation is only enabled when its DE bit (DEO for channel O,J;IBI for channel I) and the DME bit are set to 1. When NM! occurs, DME is reset to 0, thus disabling DMA ac- tivity during the NM! interrupt service routine. To restart DMA, DEO and/or DEi should be written with 1 (even ifthe contents are already I). This automatically sets DME to I, allowing OMA operations to continue. Note that DME cannot be directly written. It is cleared to 0 by NM! or indirectly set to 1 by setting DEO and/or DE! to I. DME is cleared to 0 during RESET. (8) OMA Mode Register (DMODE} DMODE is used to set the addressing and transfer mode for channel 0. OMA Mode Register (DMOOE : 1/0 Address = 31 H) ""r---.~-.,---,--4~-.---"-.-_.::;_---,r-~,-.--=--, DM1 OMO SM1 I I SMO MMOD R/W R/W R/W R/W R/W DM1, OMO: Destination Mode Channel 0 (bits&, 4} Specifies whether the destination for channel 0 transfers is memory, 1/0 or memory mapped 1/0 and the corresponding address modifier. DMI and DMO are cleared to 0 during RESET. DM1 OMO 0 0 0 1 1 0 1 1 Table 5 Dest.ination Memory/1/0 Memory Memory Memory 1/0 Address Increment/Decrement +1 -1 fixed fixed 428 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 SM1, SMO: Source Mode Channel 0 (bits 3, 21 Specifies whether the source for channel 0 transfers is memory, 1/0 or memory mapped 1/0 and the corresponding address modifier. SM! and SMO are cleared to 0 during RESET. Table 7 shows all DMA transfer mode combinations of DMO, DMI, SMO, SM!. Since 1/0 ~ 110 transfers are not implemented, twelve combinations are available. SM1 SMO 0 0 0 1 1 0 1 1 Table 6 Source Memory/110 Memory Memory Memory 110 Address Increment/Decrement +1 -1 fixed fixed Table 7 Combination of Transfer Mode DM1 DMO SM1 SMO 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Transfer Mode Memory-Memory Memory-Memory Memory·-Memory 110-Memory Memory-Memory Memory-Memory Memory·-Memory 110-Memory Memory-Memory· Memory-Memory· reserved reserved Memory-110 Memory-110 reserved reserved Address Increment/Decrement SARO+ 1. DARO+ 1 SARO- 1, DARO+ 1 SARO fixed, DARO+ 1 SARO fixed, DARO+ 1 SARO+ 1, DARO- 1 SAR0-1, DARO- 1 SARO fixed, DARO- 1 SARO fixed, DAR0-1 SARO+ 1, DARO fixed SARO- 1, DARO fixed SARO+ 1, DARO fixed SARO- 1, DARO fixed · : includes memory mapped 1/0 MMOD: Memory Mode Channel 0 (bit 11 When channel 0 is configured for memory ~ memory transfers, the external DREQ0 input is not used to control the trans- fer timing. Instead, two automatic transfer timing modes are selec- table - burst (MMOD = I) and cycle steal (MMOD = 0). For burst memory ~ memory transfers, the DMAC will sieze con- trol of the bus continuously until the DMA transfer completes (as shown by the byte count register = 0). In cycle steal mode, the CPU is given a cycle for each DMA byte transfer cycle mitil the transfer is completed. _ __ For channel 0 DMA with 1/0 source or destination, the DREQ, input times the transfer and thus MMOD is ignored. MMOD is cleared to 0 during RESET. DMA/WAIT Control Register (DCNTL) DCNTL controls the insertion of wait states into DMAC (and CPU) accesses of memory or 1/0. Also; the DMA request mode for each DREQ (DREQ0 and DREQ,) input is defined as level or edge sense. DCNTL also sets the DMA transfer mode for channel I, which is limited to memory ~ 1/0 transfers. OMA/WAIT Control Register (DCNTL: 1/0 Address= 32H) 4 0 MWl1 MWIO IWl1 R1W R1W R/W IWIO OMS 1 DMSO DIM1 R/W R/W R1W R/W DIMO RIW MWl1, MWIO: Memory Wait Insertion (bits 7-61 Specifies the number of wait states introduced into CPU or DMAC memory access cycles. MWII and MW!Oareset to I during RESET. See section of Wait State Control for details. IWl1, IWIO: 1/0 Wait Insertion (bits 5-4) Specifies the number of wait states introduced into CPU or DMAC 1/0 access cycles. !WI! and IWIO are set to I during RESET. See section of Wait State Control for details. DMS1, DMSO: DMA Request Sense (bits 3-2) DMSI and DMSO specify the DMA request sense for channel 0 (DREQ0) and channel I (DREQ,) respectively. When reset to 0, the input is level sense. When set to I, the input is edge sense. DMSI and DMSO are cleared to 0 during RESET. DIM 1, DIMO: DMA Channel 1 1/0 and Memory Mode (bits 1-0) Specifies the source/destination and address modifier for chan- nel I memory ~ 1/0 transfer modes. IM I and IMO are cleared to 0 during RESET. Table 8 Channel 1 Transfer Mode DIM1 DIMO 0 0 0 1 1 0 1 1 Transfer Mode Memory-110 Memory-110 110-Memory 110-Memory Address Increment/Decrement MAR1+1,IAR1 fixed MAR1-1,IAR1 fixed IAR1 fixed, MARI+ 1 IAR1 fixed, MAR1-1 10.3 DMA Operation This section discusses the three DMA operation modes for channel 0, memory ~ memory, memory ~ 1/0 and memory ~ memory mapped I/0.1n addition, the operation of channel O DMA with the on-chip ASCI (Asynchronous Serial Communication Interface) as well as Channel I DMA are de- scribed. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 429 (1) Memory~ Memory - Channel 0 __ For memory ~ memory transfers, the external OREQ0 input is not used for OMA transfer timing. Rathe(, the OMA oper- ation is timed in one of two programmable modes - burst or cycle steal. In both modes, the OMA operation will automatically pro- ceed until termination as shown by byte count (BCRO) = 0. In burst mode, the OMA operation will proceed until termina- tion. In this case, the CPU cannot perform any program execution until the OMA operation is completed. In cycle steal mode, the OMA and CPU operation are alternated after each OMA byte transfer until the OMA is completed. Thesequence ... ( 1 CPU Machine Cycle°' OMA Byte Transfer J ... is repeated until DMA is completed. Fig. 41 shows cycle steal mode OMA timing. + + ·I"'. + 6~~o~;cle CPU cycle DMA cycle (transfer 1 byte) CPU cycle OMA cycle LD g,m Source Destination LO g,m op-code address memory address memory address operand address _ Address:=:J<~ ___,X,_____,X~____,X,_____,X~--- _) DATA LO g,m "Read data Write data m Figure 41 Cycle Steal Mode OMA Timing To initiate memory ~ memory OMA transfer for channel 0, perform the following operations. CD Load the memory source and destination addresses into SARO and DARO. CD Specify memory ~ memory mode and address incre- ment/decrement in the SMO, SM!, OMO and DMI bits of OMOOE. G) Load the number of bytes to transfer in BCRO. © Specify burst or cycle steal mode in the MMOO bit ofOCNTL. ® Program OEO = I = (with OWEO 0 in the same access) in OSTAT and the OMA operation will start 1 machine cycle later. If interrupt occurs at the same time, the OIEO bit should be set to 1. (2) Memory ~ 1/0 (Memory Mapped 1/0) - Channel 0 For memory ~ 110 (and memory ~ memory mapped 1/0) the OREQ0 input is used to time the OMA transfers. In addi- = tion, the TEND0 (Transfer End) output is used to indicate the last (byte count register BCRO OOH) transfer. The DREQ0 input can be programmed as level or edge sensitive. When level sense is programmed, the OMA operation begins when DREQ0 is sampled LOW. If OREQ0 is sampled HIGH, after the next OMA byte transfer, control is relinquished to the H064180 CPU. As shown in Fig. 42. DREQ0 is sampled at the rising edge of the clock cycle prior to T3 i.e. either T2 or Tw. OMA Write Cycle CPU Machine Cycle OMA Read Cycle OMA Write Cycle (1/0) Tw Tw Ta Tw Tw Ta !.. \.__ _ _--JI l .. \ ' .. --- DREOo is s-am-pled-at-f" Figure 42 CPU Operation and OMA Operation (OREQ 0 is programmed for level sense) 430 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 When edge sense is programmed, DMA operation begins at the falling edge of DREQ,. If another falling edge is detected before the rising edge of the clock prior to T, during OMA write cycle (i.e. T2 or Tw), the DMAC continues operating. Ifan edge is not detected, the CPU is given control after the current byte OMA transfer com- OMA write cycle CPU machine OMA read cycle cycle pletes. The CPU will continue operating until a DREQ0 falling edge is detected before the rising edge of the clock prior to T3 at which time the OMA operation will (re)start. Fig. 43 shows the edge sense OMA timing. OMA write cycle CPU machine cycle ·· DREOo is sampled at j. Figure 43 CPU Operation and OMA Operation (DREQ0 is programmed for edge sense) During the transfers for channel 0, the TEND, output will go LOW synchronous with the write cycle of the last (BCRO = OOH) OMA transfer as shown in Fig. 44. Last OMA cycle (BCRO = OOH) OMA read cycle .l T OMA write cycle Figure 44 TEND 0 Output Timing The DREQ, and TEND0 pins are programmably multiplexed with the CKAO and CKAl ASCI clock input/outputs. However, when OMA channel 0 is programmed for memory~ I/O (and memory ~ memory mapped I/0) transfers, the CKAO/DRE- Q.; pin automatically functions as input pin even if it has been pro- grammed as output pin for CKAO. And the CKAI/TEND, pin functions as output pin for TEND, by setting CKAID to 1 in CNTLAl. To initiate memory ~~ I/O (and memory ~ memory . mapped I/0) OMA transfer for channel 0, perform the following operations. CD Load the memory and I/O or memory mapped I/O source and destination addresses inio SARO and DARO. Note that I/O addresses (not memory mapped 1/0) are limited to 16 bits (A0- A15). Make sure that bits A16 and A17 are 0 (A18 is a don't care) to correctly enable the external DREQ0 input. @ Specify memory ~ I/O or memory ~ memory map- ped I/O mode and address increment/decrement in the SMO, SMl, OMO, and DMl bits of DMODE. ® Load the number of bytes to transfer in BCRO. © Specify whether DREQ, is edge or level sense by programming the DMSO bit of DCNTL. ® Enable or disable OMA termination interrupt with the DIEO bit in DSTAT. = = ® Program DEO 1 (with DWEO 0 in the same access) in DSTAT and the OMA operation will begin under the control of the DREQ0 input. (3) Memory ~ ASCI - Channel 0 Channel 0 has extra capability to support DMA transfer to and from the on-chip two channel ASCI. In this case the external DRE- Q.; input is not used for OMA timing. Rather, the ASCI status bits are used to generate an internal DREQ0· The TORE (Transmit Data Register Empty) bit and the RDRF (Receive Data Register Full) bit are used to generate an internal DREQ, for ASCI transmission and reception respectively. To initiate memory~ ASCI OMA transfer, perform the following operations. CD Load the source and destination addresses into SARO and DARO. Specify the I/O (ASCI) address as follows. Bits A0-A7 should be contain the address of the ASCI channel transmitter or receiver (l/O addresses 06H-09H). Bits A8-A15 should equal 0. Bits A17-A16 should be set according to the following table to enable use of the appropriate ASCI status bit as an internal OMA reQuest. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 431 Table 9 DMA Request SAR18 x x x x SAR17 0 0 1 1 X: Don't care SAR16 0 1 0 1 DMA Transfer Request DREQ 0 RDRF (ASCI channel 0) RDRF (ASCI channel 1) reserved DAR18 x x x x DAR17 0 0 1 1 DAR16 0 1 0 1 DMA Transfer Request DREQ 0 TDRE (ASCI channel 0) TDRE (ASCI channel 1) reserved X: Don't care @ Specify memory ~ 1/0 transfer mode and address increment/decrement in the SMO, SMl, DMO and DMI bits of DMODE. @ Load the number of bytes to transfer in BCRO. © The DMA request sense mode (DMSO bit in DCNTL) MUST be specified as 'edge sense'. ® Enable or disable DMA termination interrupt with the DIEO bit in DST AT. ® Program DEO = I (with DWEO = 0 in the same access) in DSTAT and the DMA operation with the ASCI will begin under control of the ASCI generated internal DMA request. The ASCI receiver or transmitter being used for DMA must be initialized to allow the first DMA transfer to begin. The ASCI receiver must be 'empty' as shown by RDRF = 0. The ASCI transmitter must be 'full' as shown by TDRE = 0. Thus the first byte should be written to the ASCI Transmit Data Regi;ter under program control. The remaining bytes will be trans- ferred using DMA. (4) Channel 1 OMA DMAC Channel I can perform memory ~ 110 transfers. Except for different registers and status/control bits, operation is exactly the same as described for channel 0 memory ~ 110 DMA. To initiate DMA channel I memory ~ l/O transfer per- form the following operations. CD Load the memory address (19 bits) into MARI. ffi Load the 1/0 address (16 bits) into !ARI. @ Program the source/destination and addre_ss i_ncrement/decrement mode using the DIM! and DIMO bits m DCNTL. . © Specify whether DREQ1 is level or edge sense m the DMSI bit in DCNTL. ® Enable or disable DMA termination interrupt with the DIEi bit in DSTAT. ® Program DEi = I (with DWEI = 0 in the same access) in DSTAT and the DMA operation with the external 1/0 device will begin using the external DREQ1 input and TEND, output. 10.4 OMA Bus Timing When memory (and memory mapped 1/0) is specified as a source or destination, ME goes LOW during the memory access. When I/O is specified as a source or destination, IOE goes LOW during the I/O access. When 1/0 (and memory mapped I/0) is specified as a so~ destination, the DMA timing is controlled by the external DREQ input and the TEND output indicates DMA termination. Note that external J/O devices may not overlap addresses with internal 1/0 and control registers, even using DMA. For 110 accesses, I wait state is automatically inserted. Additional wait states can be inserted by programming the on-chip wait state generator or using the external WAIT input. Note that for memory mapped 1/0 accesses, this automatic l/O wait state is not inserted. For memory to memory transfers (channel 0 only), the external DREQ0 input is ignored. Automatic DMA timing is programmed as either burst or cycle steal. When a DMA memory address carry/borrow between bits A15 and A16 of the address bus occurs (when crossing 64k bytes boundaries), the minimum bus cycle is extended to four clocks by automatic insertion of one internal Ti state. 10.5 DMAC Channel Priority For simultaneous DREQ0 and DREQ, requests, channel 0 has priority over channel I. When channel 0 is performing a memory ~ memory transfer, channel I cannot operate until the channel Ooperation has terminated. If channel I is operating, channel 0 cannot operate until channel I releases control of the bus. 10.6 DMAC and BUSREQ, BUSACK The BUSREQ and BUSACK inputs allow another bus master to take control of the HD64180 bus. BUSREQ and BUSACK have priority over the on-chip DMAC and will suspend DMAC operation. The DMAC releases the bus to the external bus master at the breakpoint of the DMAC memory or I/O access. Since a single byte DMl\.C transfer requires a read and a write cycle, it is possible for the DMAC to be suspended after the DMAC read, but before the DMAC write. Even in this case, when the external master releases the HD64180 bus (BUSREQ HIGH), the on-chip DMAC will correctly continue the suspended DMA operation. 10.7 OMAC Internal Interrupts Fig. 45 illustrates the internal DMA interrupt request generation circuit. 432 DE1 DIE1 OEO OIEO OMA ch 1 Interrupt Request OMA chO Interrupt Request Figure 45 DMAC Interrupt Request Circuit Diagram @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 DEO and DEl are automatically cleared to 0 by the HD64180 at the completion (byte count= 0) of a DMA operation for channel 0 and channel 1 respectively. They remain 0 until a 1 is written. Since DEO and DEi use level sense, an interrupt will occur if the CPU IEF1 flag is set to I. Therefore, the DMA termination interrupt service routine should disable further DMA interrupts (by programming the channel DIE bit = 0) before enabling CPU interrupts (i.e. IEF1 is set to I). After reloading the DMAC address and count registers, the DIE bit can be set to I to reenable the channel interrupt, and at the same time DMA can resume by programming the channel DE bit = I. I OMA read cycle 10.8 DMAC and iii1iii1 NM!, unlike all other interrupts, automatically disables DMAC operation by clearing the DME bit of DSTAT. Thus, the NMI interrupt service routine may respond to time critical events without delay due to DMAC bus usage. Also, NMI can be effectively used as an external DMA abort input, recognizing that both channels are suspended by the cleari'.!L.2.!: DME. If the falling edge of NMI occurs before the falling clock of the state prior to T3 (T2 or Tw) of the DMA write cycle, the DMAC will be suspended and the CPU will start the NMI response at the end of the current cycle. By setting a channels DE bit to 1, that channels operation can be restarted, and DMA will correctly resume from the point at which it was suspended by NMI. See Fig. 46 for details. ·I· OMA write cycle CPU machine cycle Figure 46 NM! and OMA Opera ion OME= "O" (OMA Stop) 10.9 DMAC and RESET During RESET the bits in DSTAT, DMODE, and DCNTL are initialized as stated in their individual register descriptions. Any DMA operation in progress is stopped allowing the CPU to use the bus to perform the RESET sequence. However, the address register (SARO, DARO, MARI, !ARI) and byte count register (BCRO, BCRI) contents are not changed during RESET. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 433 11 ASYNCHRONOUS SERIAL COMMUNICATION INTERFACE (ASCI) The HD64180 on-chip ASCI has two independent full duplex channels. Based on full programmability of the following functions, the ASCJ can directly communicate with a wide variety of standard UARTs (Universal Asynchronous Receiver/Transmitter) including the HD6350 CMOS ACIA and the Serial Communication Interface (SCI) contained on the HD6301 series CMOS single chip controllers. The key functions for ASCI are shown below. Each channel is independently programmable. · Full duplex communication · 7- or 8-bit data length · Program controlled 9th data bit for multiprocessor communica- tion · I or 2 stop bits · Odd, even, no parity · Parity, overrun, framing error detection · Programmable baud rate generator, /16 and /64 modes Speed to 38.4k bits per second (CPU fc = 6.144 MHz) __ ·Modem control signals - Channel 0 has DCD0, CTS0 and RTS0 Channel I has CTS1 · Programmable interrupt condition enable and disable · Operation with on-chip DMAC 11.1 ASCI Block Diagram Fig. 47 shows the ASCI Block Diagram. ....._ J... Internal Address/Data Bus ~ l Interrupt Request l v ASCI Transmit Data Register ASCI Transmit Data Register ch 0 : TORO (8) ch 1 : TDR1 (8) TXAo -1ASCI Transmit Shift Register· ch 0 : TSAO (8) ASCI Transmit Shift Register*f- TX ch 1 : TSR1 (8) ASCI Receive Data Register ch 0 : RDRO (8) l+-1 ASCI Receive Data Register r---1 ch 1 : RDR1 (8) RXAo-1 ASCI .Receive Shift Register· ch 0 : RSRO (8) ASCI Control ASCI Receive Shift Register* 1-- RX ch 1 : RSR1 (8) ASCI Control Register A -R TS-o-] ch 0 : CNTLAO (8) 1--t- l-+--1 ASCI ch Control Register 1 : CNTLA 1 (8) A -C TSo- -I ASCI Control Register B ch 0 : CNTL80 (8) -D CD-o-1 ASCI Status Register ch 0 : STATO (8) '---r-' L-, r ASCI Control Register B ch 1 : CNTLB 1 (8) ASCI Status Register ch 1 : STAT1 (8) f-- CTS CKAo.--.. CKA1....-- Baud Rate Generator 0 Baud Rate Generator 1 -¢ ·Not program Accessible Figure 47 ASCI Block Diagram 11.2 ASCl Register Description (1) ASCI Transmit Shift Register 0, 1 (TSAO, 1) When the ASCJ Transmit Shift Register receives data from the ASCJ Transmit Data Register (TDR), the data is shifted out to the TXA pin. When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts. If no data is available for transmission, TSR idles by outputting a continuous HIGH level. This register is not program accessible. (2) ASCI Transmit Data Register 0, 1 (TORO, 1: 1/0 Address= 06H, 07H) Data written to the ASCI Transmit Data Register is transferred to the TSR as soon as TSR is empty. Data can be written to while TSR is shifting out the previous byte of data. Thus, the ASCJ transmitter is double bufferred. Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation won't be affected by this read operation. (3) ASCI Receive Shift Register 0, 1 (RSRO,. 1) This register receives ctSta shifted in on the RXA pin. When full, data is automatically transferred to the ASCJ Receive Data Register (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs. This register is not program accessible. (4) ASCI Receive Data Register 0, 1 (RDRO, 1: 1/0 Address = 08H, 09H) When a complete incoming data byte is assembled in RSR, it is automatically transferred to the RDR ifRDR is empty. The next incoming data byte can be shifted into RSR while RDR contains the previous received data byte. Thus, the ASCJ receiver is double buffered. = The ASCI Receive Data Register is read-only-register. However, if RDRF 0, data can be written into the ASCI Receive Data Register, and the data can be read. 434 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 (51 ASCI Status Register 0, 1 (STATO, 11 Each channel status register allows interrogation of ASCI com- munication, error and modem control signal status as well as enabling and disabling of ASCI interrupts. ASCI Status Register 0 (STATO : 1/0 Address = 04H) I I ··.----'-_,.---'=-----.-......:~,---"-~.----=----.----==---.---'-~.--~o:......, RORF OVRN PE FE RIE OCOo TORE TIE R/W R R/W .. ASCI Stetus Register 1 (STAT1 : 1/0 Address = 05H) 4 2 0 I RDRF OVRN PE FE I I RIE CTS1E TORE TIE R/W R/W R/W RDRF: Receive Data Register Full (bit 7) RDRF is set to 1 when an incoming data byte is loaded into RDR. Note that if a framing or parity error occurs, RDRF is still set and the receive data (which generated the error) is still loaded into RDR. RDRF is cleared to 0 by reading RDR, when the DCD0 input is HIGH, in IOSTOP mode and during RESET. OVRN: Overrun Error (bit 61 OVRN is set to 1 when RDR is full and RSR becomes full. OVRN is cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when DCD0 is HIGH, in IOSTOP mode and during RESET. PE: Parity Error (bit 5) PE is set to 1 when a parity error is detected on an incoming data byte and ASCI parity detection is enabled (the MODl bit of CNTLA is set to 1). PE is cleared to 0 when the EFR bit (Error Flag Reset) of CN1:LA is written to 0, when DCD0 is HIGH, in IOSTOP mode and durmg RESET. FE: Framing Error (bit 41 Ifa receive data byte frame is delimited by an invalid stop bit (i.e. 0, should be 1), FE is set to 1. FE is cleared to 0 when ihe EFR bit .<Error Flag Reset) ofCNTLA is written to 0, when DCD0 is HIGH, m IOSTOP mode and during RESET. RIE: Receive Interrupt Enable (bit 3) RIE should be set to 1 to enable ASCI receive interrupt requests. When RIE to 1, if any of the flags RDRF, OVRN, PE, FE become set to 1 an interrupt request is generated. For channel 0, an inter~pt will also be generated by the transition of the external DCD0 mput from LOW to HIGH. RIE is cleared to 0 during RESET. DCD0 : Data Carrier Detect (bit 2 STATOI Channel 0 has an external DCD0 input pin. The DCD0 bit is set to 1 when the DCD0 input is HIGH. It is cleared to 0 on the first ~ead of STATO following the HIGH to LOW transition of DCD0 mput and during RESET. When DCD0 = 1, receiver unit is reset and receiver operation is inhibited. CTS1E: Channel 1 CTS Enable (bit 2 STAT1) Channel 1 has an external CTS1 input which is multiplexed with the receive data pin (RXS) for the CSI/O (Clocked Serial 1/0 Port). Setting CTSlE to 1 selects the CTS, function and clearing CTSlE to 0 selects the RXS function. TDRE: Transmit Data Register Empty (bit 1) TORE = 1 indicates that the TOR is empty and the next trans- mit data byte can be written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until the ASCI transfers the byte from the TDR to the TSR, at which time TORE is again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. When the external CTS input is HIGH, TDRE is reset to 0. TIE: Transmit Interrupt Enable (bit 0) TIE should be set to 1 to enable ASCI transmit interrupt re- quests. IfTIE = 1, an interrupt will be requested when TORE= 1. TIE is cleared to 0 during RESET. · ASCI Control Register AO, 1 (CNTLAO, 1I Each ASCI channel Control Register A configures the major op- erating modes such as receiver/transmitter enable and disable, data format, and multiprocessor communication mode. ASCI Control Register A 0 (CNTLAO : 1/0 Address = OOH) I I I I~ I I I I "".----'--,.~=-----.-......:s~~-4~--.---"3~.---~2=----~--'-'~.---~o'----. MPE RE TE RTSo M002 M001 MOOD R/W R/W R/W R/W RIW R/W R/W R/W ASCI Control Register A 1 (CNTLA1 : 1/0 Address = 01 H) bit 4 0 .---M-P-E-,.~R-E~.---~TE--.-l-C~KA1-0~,rMP-E_:'_/~,-M-00-2-,.-M0~0-1-~l-MO~OO~, R/W R/W R/W R/W R/W R/W R/W R/W MPE: Multi Processor Mode Enable (bit 7) The ASCI has a multiprocessor communication mode which utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no effect. If multiprocessor mode is selected, MPE enables or disaM~ the 'wake-up' feature as follows. If MPE is set to 1, only received bytes in which the MPB (multiprocessor bit) = 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB = 0) are 'ignored' by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the RDRF and error flags. MPE is cleared to 0 during RESET. RE: Receiver Enable (bit 6) When RE is set to 1, the ASCI receiver is enabled. When RE is cleared to 0, the receiver is disabled and any receive operation in progress is interrupted. However, the RDRF and error flags are not reset and the previous contents of RDRF and error flags are held. RE is cleared to 0 in IOSTOP mode and during RESET. TE: Transmitter Enable (bit &I When TE is set to 1, the ASCI transmitter is enabled. When TE is cleared to 0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to Oin IOSTOP mode and during RESET. RTSo - Request to Send Channel 0 (bit 4 in CNTLAOI When RTS0 is cleared to 0, the RTS0 output pin will go LOW. When RTS0 is set to 1, the RTS0 output immediately goes HIGH. RTS0 is set to I during RESET. CKA1D: CKA1 Clock Disable (bit 4 in CNTLA1) When CKAlD is set to 1, the multiplexed CKA1/TEND0 pin is used for the TEND0 function. When CKAID = 0, the pin is used as CKAl, an external data clock input/output for channel 1. CKAID is cleared to 0 during RESET. MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 31 When multiprocessor mode is enabled (MP in CNTLB = 1), MPBR, when read, contains the value of the MPB bit for the last re- @HITACHI Hitachi America Lid. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 435 ceive operation. When written to 0, the EFR function is selected to reset all error flag..< (OVRN, FE and PE) to 0. MPBR/EFR is undefined during RESET. MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2-0) These bits program the ASCI data format as follows. MOD2 = O- 7 bit data = I - 8 bit data MODI = 0 - No parity = I - Parity enabled MODO = 0 - I stop bit = I - 2 stop bits The data formats available based on all combinations of MOD2, MODI and MODO are shown in Table 10. Table 10 Combination of Data Format MOD2 MOD1 MODO Data Format 0 0 0 Start+ 7 bit data+ 1 stop 0 0 1 Start+ 7 bit data+ 2 stop 0 1 0 Start+ 7 bit data+ parity+ 1 stop 0 1 1 Start+ 7 bit data+ parity+ 2 stop 1 0 0 Start+ 8 bit data+ 1 stop 1 0 1 Start+ 8 bit data+ 2 stop 1 1 0 Start+B bit data+ parity+ 1 stop 1 1 1 Start+B bit data+parity+ 2 stop (6) ASCI Control Register BO, 1 (CNTLBO, 11 Each ASCI channel control register B configures multiprocessor mode, parity and baud rate selection. ASCI Control Register B 0 (CNTLBO : 1/0 Address = 02H) ASCI Control Register B 1 ICNTLB1 : 1/0 Address = 03Hl bit 5 4 0 r,~~-.-~~,.--,C~T-S/_,.~~-,-~~-r-~---,~~~~~~ MPBT MP PS PEO DR $$2 SS 1 SSO R/W R/W R/W R!W R/W R/W R/W R/W MPBT: Multiprocessor Bit Transmit (bit 7) When multiprocessor communication format is selected (MP bit = I), MPBT is used to specify the MPB data bit for transmission. If MPBT = I, then MPB = I is transmitted. If MPBT = 0, then MPB = 0 is transmitted. MPBT state is undefined during and after RESET. MP: Multiprocessor Mode (bit 6) When MP is set to I, the data format is configured for multi- processor mode based on the MOD2 (number of data bits) and MODO (number of stop bits) bits in CNTLA. The format is as follows. Start bit+ 7 or 8 data bits + MPB bit+ 1 or 2 stop bits Note that multiprocessor (MP = I) format has no provision for parity. If MP= 0, the data format is based on MODO, MODI and MOD2 and may include parity. The MP bit is cleared to 0 during RESET. CTS/PS: Clear to Send/Prescale (bit 51 When read, CTS/PS reflects the state of the external CTS input. If the CTS input pin is HIGH, CTS/PS will be read as I. Note that when the CTS input pin is HIQ!!, the TORE bit is inhibited (i.e. held at 0). For channel I, the CTS1 input is multiplexed with RXS pin (Clocked Serial Receive Data). Thus, CTS/PS is only valid when read if the channel I CTSIE bit = I and the CTS1 input pin function is selected. The read data of CTS/PS is not affected by RESET. When written, CTS/PS specifies the baud rate generator prescale factor. If CTS/PS is set to I, the system clock(</>) is prescaled by 30 while if CTS/PS is cleared to 0, the system clock is prescaled by 10. CTS/PS is cleared to 0 during RESET. PEO: Parity Even Odd (bit 41 PEO selects even or odd parity. PEO does not affect the enab- ling/disabling of parity (MODI bit ofCNTLA). If PEO is cleared to 0, even parity is selected. If PEO is set to I, odd parity is selected. PEO is cleared to 0 during RESET. DR: Divide Ratio (bit 3) DR specifies the divider used to obtain baud rate from the data sampling clock. If DR is cleared to 0, divide by 16 is used while if DR is set to I, divide by 64 is used. DR is cleared to 0 during RE- SET. SS2, 1, 0: Source/Speed Select 2, 1, 0 (bits 2-0) Specify the data clock source (internal or external) and baud rate prescale factor. SS2, SS!, and SSO are all set to I during RESET. Table 11 shows the divide ratio corresponding to SS2, SS!, and SSO. Table 11 Divide Ratio SS2 SS1 sso 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Divide Ratio +1 +2 +4 +8 +16 +32 +64 external clock The external ASCI channel 0 data clock pins are multiplexed with OMA control lines (CKAofDREQ0 and CKA/TEND0). During RESET, these pins are initialized as ASCI data clock inputs. If SS2, SS I, and SSO are reprogrammed (any other value than SS2, SS!, SSO = I) these pins become ASCI data clock outputs. However, if DMAC channel 0 is configured to perform memory ~ 1/0 (and memory mapped 1/0) transfers the CKA0/DREQ0 pin revert to OMA control signals regardless of SS2, SS!, and SSO pro- gramming. Also, ifthe CKAID bit in the CNTLA register is set to I, then the CKA/TEND0 reverts to the OMA Control output function regardless of SS2, SS!, and SSO programming. Final data clock rates are based on CTS/PS (prescale), DR, SS2, SS!, SSO, and the HD64180 system clock (<f>) frequency as shown in Table 12. 436 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Prescaler PS Divide Ratio Sampling Rate DR Rate 0 16 0 cf>+10 1 64 0 16 1 </>+30 1 64 Table 12 Baud Rate List Baud Rate SS2 SS1 sso Divide Ratio General Divide Ratio Baud Rate (Example) (BPS) cf>-6.144 cf>=4.608 cf>=3.072 MHz MHz MHz CKA 1/0 Clock Frequency 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 : 1 cf>+160 38400 19200 cf>+10 2 320 19200 9600 20 4 640 9600 4800 40 8 1280 4800 2400 0 80 16 2560 2400 1200 160 32 5120 1200 600 320 64 10240 600 300 640 - fc+ 16 - - I fc 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 +1 cf>+640 9600 2 1280 4800 4 2560 2400 8 5120 1200 16 10240 600 32 20480 300 64 40960 150 - fc+64 - - 4800 2400 1200 600 0 300 150 75 - I cf>+10 20 40 80 160 320 640 fc 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 +1 cf>+480 2 960 4 1920 8 3840 16 7680 32 15360 64 30720 - fc+16 - 9600 cf>+30 4800 60 2400 120 1200 0 240 600 4BO 300 960 150 1920 - - I fc 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 +1 cf>+1920 2 3840 4 7680 8 15360 16 30720 32 61440 64 122880 - fc+64 - 2400 1200 600 300 150 75 37.5 - cf>+30 60 120 0 240 480 960 1920 I fc 11.3 MODEM Control ~al_s__ __ ASCI channel 0 has CTS,, DCD,, and RTS0 external modem control signals. ASCI channel 1 has a CTS, modem control signal which is multiplexed with RXS pin (Clocked Serial Receive Data). 111 CTS0 : Clear to Send 0 (input) The CTS0 input allows external control (start/stop) of ASCI channel 0 transmit operations. When CTS0 is HIGH, channel 0 TORE bit is held at 0 regardless of whether the TDRO (Transmit Data Register) is full or empty. When CTS0 is LOW, TDRE will reflect the state of TORO. Note that the actual transmit operation is not disabled by CTS0 HIGH, only TDRE is inhibited. (2) DCD0 : Data Carrier Detect 0 (input) The DCD0 input allows external control (start/stop) of ASCI channel 0 receive operations. When DCD0 is HIGH, channel 0 RDRF bit is held at 0 regardless of whether the RDRO (Receive Data Register) is full or empty. The error flags (PE, FE and OVRN bits) are.also held at 0. Even after the DCD0 input goes LOW, these bits will not resume normal operation until the status register (STATO) is read. Note that this first read ofSTATO, while enabling normal operation, will still indicate the DCD, input is HIGH (DCDO bit= I) even though it has gone LOW. Thus, the STATO register should be read twice to insure the DCDO bit is cleared to 0. (3) RTS0 : Request to Send 0 (output) RTS0 allows the ASCI to control (start/stop) another communi- cation devices transmission (for example, by connection to that devices CTS input). RTS0 is essentially a I bit output port, having no side effects on other ASCI registers or flags. (4) CTS1 : Clear to Send 1 (input) Channel I CTS1 input is mJ!!!iplexed with the RXS pin (Clocked Serial .Receive Data). The CTS, function is selected when the CTSIE bit in ST!!:Tl is set to 1. When enabled, the CTS, operation is equivalent to CTS0· Modem control signal timing is shown in Fig. 48(a) and Fig.48(b) . · HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 437 DCDo Pin Status Register - - - - - - - - - - - - - - ' ' - - - - - - - - - - - - - - Read Figure 48 (a) DCD 0 Timing VO instruction ·I· 1/0 write cycle ·I RTSO Flag RTSo Pin Figure 48 (b) RTS 0 Timing 11.4 ASCI Interrupts Fig. 49 shows the ASCI interrupt request generation circuit. DCDO IEF1 RDRFO ---"[--... OVRNO PEO FEO ASCIO Interrupt Request RDRF1 PE1 FE1 ASCI 1 Interrupt Request Figure 49 ASCI Interrupt Request Circuit Diagram 438 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 11.5 ASCI ~ DMAC operation Operation of the ASCI with the on-chip DMAC channel 0 re- quires the DMAC be correctly configured to utilize the ASCI flags as OMA request signals. 11.6 ASCI and RESET During RESET, the ASCI status and control registers are initialized as defined in the individual register descriptions. Receive and Transmit operations are stopped during RESET. However, the contents of the transmit and receive data registers (TOR and RDR) are not changed by RESET. 11.7 ASCI Clock In external clock input mode, the external clock is directly input to the sampling rate (+ 16/+ 64) as shown in Fig. 50. <t>-4 H .,.- Internal Clock Baud Rate Selection 1 to+ 64 Prescaler Sampling Rate 101+ 30 ~ ..,.- 16/+ 641 External Clock I s fc <f> + 40--------------~ Figure 50 ASCI Clock Block Diagram 12 CLOCKED SERIAL 1/0 PORT (CSl/0) The HD64180 includes a simple, high speed clock synchronous serial 1/0 port. The CSl/O includes transmit/receive (half duplex), fixed 8-bit data and internal or external data clock selection. High speed operation (baud rate as high as 200k bits/second at fc = 4 MHz) is provided. The CSl/O is ideal for implementing a multiprocessor communication link between the HD64180 and the HMCS400 series (4-bit) and the HD6301 series (8-bit) single chip controllers as well as additional HD64180s. These secondary devices may typically perform a portion of the system 1/0 processing such as keyboard scan/decode, LDC interface etc. 12.1 CSl/0 Block Diagram The CSI/O block diagram is shown in Fig. 51. The CSI/O con- sists of two registers - the Transmit/Receive Data Register (TRDR) and Control Register (CNTR). Internal Address/Data Bus TXS ..,_ CSl/O Transmit/Receive Data Register: RXS TRDR (8) Baud Rate Generator CSl/O Control Register: CNTR (8) ------~ CKS Interrupt Request Figure 51 CSl/O Block Diagram 12.2 CSl/0 Register Description (1) CSl/0 Transmit/Receive Data Register (TRDR: 1/0 Address= OBH) TRDR is used for both CSl/O transmission and reception. Thus, the system design must insure that the constraints of half-duplex operation are met (Transmit and receive operation can't occur simultaneously). For example, if a CSl/O transmission is attempted at the same time that the CSl/O is receiving data, a CSI/O will not work. Also note that TRDR is not buffered. Therefore, attempting to perform a CSl/O transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, thereby corrupting the transmit operation in progress. Similarly, reading TRDR while a transmit or receive is in progress should be avoided. (2) CSl/0 Control/Status Register (CNTR: 1/0 Address = OAH) CNTR is used to monitor CSI/0 status, enable and disable the CSI/O, enable and disable interrupt generation and select the data clock speed and source. CSl/O Control Register (CNTR : 1/0 Address = OAH) bit 4 0 I I EF EIE RE TE R/W R/W R/W SS2 SS1 $$0 R/W R/W R/W EF: End Flag (bit 7) EF is set to I by the CSI/O to indicate, completion of an 8-bit data transmit or receive operation. If EIE (End Interrupt Enable) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 439 bit = 1 during the time EF = 1, a CPU interrupt request will be generated. Program access of TRDR should only occur if EF = 1. The CSI/O clears EF to 0 when TRDR is read or written. EF is cleared to 0 during RESET and IOSTOP mode. EIE: End Interrupt Enable (bit 6) EIE should be set to 1 to enable EF = 1 to generate a CPU inter- rupt request. The interrupt request is inhibited ifEIE is cleared to 0. EIE is cleared to 0 during RESET. RE: Receive Enable (bit 6) A CSI/O receive operation is started by setting RE to 1. When RE is set to 1, the data clock is enabled. In internal clock mode, the data clock is output from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either case, data is shifted in on the RXS pin in synchronization with the (internal or external) data clock. After receiving 8 bits of data, the CSl/O automatically clears RE to 0, EF is set to I and an interrupt (if enabled by EIE = 1) will be generated. Note that RE and TE should never both be set to 1 at the same time. RE is cleared to 0 during RESET and IOSTOP mode. Note that the RXS pin (pin 52) is multiplexed with CTS~ modem control input of ASCI channel 1. In order to enable the RXS function, the CTS1E bit in CNTAI should be reset to 0. TE: Transmit Enable (bit 4) A CSI/O transmit operation is started by setting TE to 1. When TE is set to 1, the data clock is enabled. In internal clock mode, the data clock is output from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either case, data is shifted out on the TXS pin synchronous with the (internal or external) data clock. After transmitting 8 bits of data, the CSI/O automatically clears TE to 0, EF is set to 1 and an interrupt (if enabled by EIE = 1) will be generated. Note that TE and RE should never both be set to 1 at the same time. TE is cleared to 0 during RESET and IOSTOP mode. SS2, 1, 0: Speed Select 2, 1, O (bits 2-0) SS2, SS1 and SSO select the CSI/O transmit/receive clock source and speed. SS2, SS! and SSO are all set to I during RESET. Table 13 shows CSI/O Baud Rate Selection. Table 13 CSl/O Baud Rate Selection SS2 SS1 sso Divide Ratio Baud Rate 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 +20 +40 +80 +160 +320 +640 +1280 (200000) (100000) (50000) (25000) (12500) (6250) (3125) 1 1 1 external Clock input (less than + 20) ( I shows the baud rate (BPS) at q, = 4 MHz. After RESET, the CKS pin is configured as an external clock input (SS2, SSl, SSO = 1). Changing these values causes CKS to become an output pin and the selected clock will be output when transmit or receive operations are enabled. 12.3 CSl/0 Interrupts The CSI/O interrupt request circuit is shown in Fig. 52. EF CSl/O Interrupt Request EIE Figure 52 CSl/O Interrupt Circuit Diagram 12.4 CSl/0 Operation The CSI/O Can be operated using status polling or interrupt driven algorithms. (1) Transmit - Polling CD Poll the TE bit in CNTR until TE = 0. (]) Write the transmit data into TRDR. @ Set the TE bit in CNTR to 1. © Repeat 1 to 3 for each transmit data byte. (2) Transmit - Interrupts CD Poll the TE bit in CNTR until TE = 0. (]) Write the first transmit data byte into TRDR. @ Set the TE and EIE bits in CNTR to 1. © When the transmit interrupt occurs, write the next transmit data byte into TRDR. @ Set the TE bit in CNTR lo 1. ® Repeat 4 to 5 for each transmit data byte. (3) Receive - Polling CD Poll the RE bit in CNTR until RE = 0. (]) Set the RE bit in CNTR to 1. @ Poll the RE bit in CNTR until RE = 0. © Read the receive data from TRDR. ® Repeat 2 to 4 for each receive data byte. (4) Receive - Interrupts CD Poll the RE bit in CNTR until RE = 0. (]) Set the RE and EIE bits in CNTR to 1. @ When the receive interrupt occurs read the receive data from TRDR. © Set the RE bit in CNTR to 1. ® Repeat 3 to 4 for each receive data byte. 12.5 CSl/O Operation Timing Notes (1) Note that transmitter clocking and receiver sampling timings are different from internal and external clocking modes. Fig. 53 to Fig. 54 shows CSI/O Transmit/Receive Timing. (2) The transmitter and receiver should be disabled (TE and RE = 0) when initializing or changing the baud rate. 12.6 CSl/0 Operation Notes (1) Disable the transmitter and receiver (TE and RE= 0) before initializing or changing the baud rate. When changing the baud rate after completion of transmission or reception, a delay of at least one bit time is required before baud rate modification. ~HITACHI 440 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 (2) When RE or TE is cleared to 0 by software, a corresponding re- ceive or transmit operation is immediately terminated. Normally, TE or RE should only be cleared to 0 when EF = 1. (3) Simultaneous transmission and reception is not possible. Thus, TE and RE should not both be l at the same time. CKS TXS --~ ..___L_S_B_ __, '-------1~._______,X....___M_S__ B ___ TE EF CKS TXS TE EF Figure 53 Transmit Timing - Internal Clock l Read or write of CSl/O Transmit/Receive Data Register MSB 7.5c/J 7.5c/J 7.5c/J 7.5c/J Figure 54 Transmit Timing - External Clock t Read or write of CSl/O Transmit/Receive Data Register @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 441 CKS RXS RE EF LSB MSB 11 q, 11 q, 11 q, 11 q, Sampling 171/> Figure 55 Receive Timing - Internal Clock Read or write of CSl/O Transmit/Receive Data Register CKS 16.51/> 16.51/> 16.5 16.51/> Sampling RE EF l Read or write of CSl/O Transmit/Receive Data Register Figure 56 Receive Timing - External Clock 12.7 CSl/0 and RESET During RESET each bit in the CNTR is initialized as defined in the CNTR register description. CSUO transmit and receive operations in progress are aborted during RESET. However, the contents ofTRDR are not changed. 442 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 13 PROGRAMMABLE RELOAD TIMER (PRT) The HD64180 contains a two channel 16-bit Programmable Reload Timer. Each PRT channel contains a 16-bit down counter and a 16-bit reload register. The down counter can be directly read and written and a down counter overflow interrupt can be programmably enabled or disabled. In addition, PRT channel I has a TOUT output pin (multiplexed with A1,) which can be set HIGH, LOW, or toggled. Thus PRTl can perform programmable output waveform generation. 13.1 PRT Block Diagram The PRT block diagram is shown in Fig. 57. The two channels have separate timer data and reload registers and a common status/ control register. The PRT input clock for both channels is equal to the system clock (¢) divided by 20. Internal Address/Data Bus cf>+ 20 Timer Data Timer Data Register OL Register OH : TMDROL (8) : TMDROH (8) Timer Reload Timer Reload Register OL Register OH : RLDROL (8) : RLDROH (8) Timer Control Register : TCR (8) </> + 20 ~ Timer Data Timer Data Register 1L Register 1H TOUT : TMDR1 L (8): TMDR1 H (8) Timer Reload Timer Reload Register 1L Register 1H : TLDR1 L (8) : TLDR1 H (8) Interrupt Request Figure 5 7 PRT Block Diagram 13.2 PRT Register Description (1) Timer Data Register (TMDR: 1/0 Address = CHO: OOH, OCH CH1: 15H, 14H) PRTO and PRTI each have 16-bit Timer Data Registers (TMDR). TMDRO and TMDRl are each accessed as low and high byte registers (TMDROH, TMDROL and TMDRIH, TMDRlL). During RESET, TMDRO and TMDRl are set to FFFFH. TMDR is decremented once every twenty q, clocks. When TMDR counts down to 0, it is automatically reloaded with the value contained in the Reload Register (RLDR). TMDR can be read and written by software using the following procedures. The read procedure uses a PRT internal temporary storage register to return accurate data without requiring the timer to be stopped. The write procedure requires the PRT to be stopped. For reading (without stopping the timer), TMDR must be read in the order of lower byte - higher byte (TMDRnL, TMDRnH). The lower byte read (TMDRnL) will store the higher byte value in an internal register. The following higher byte read (TMDRnH) will access this internal register. This procedure insures timer data validity by eliminating the problem of potential 16-bit timer updating between each 8-bit read. Specifically, reading TMDR in higher byte - lower byte order may result in invalid data. Note the implications of TMDR higher byte internal storage for applications which may read only the lower and/or higher bytes. In normal operation all TMDR read routines should access both the lower and higher bytes, in that order. For writing, the TMDR down counting must be inhibited using the TDE (Timer Down Count Enable) bits in the TCR (Timer Control Register), following which any or both higher and lower bytes ofTMDR can be freely written (and read) in any order. = (2) Timer Reload Register (RLDR: 1/0 Address CHO: OEH, OFH CH1: 16H, 17H) PRTO and PRTI each have 16-bit Timer Reload Registers (RLDR). RLDRO and RLDRl are each accessed as low and high byte registers (RLDROH, RLDROL and RLDRlH, RLDRIL). During RESET RLDRO and RLDRI are set to FFFFH. When the TMDR counts down to 0, it is automatically reloaded with the contents of RLDR. (3) Timer Control Register (TCR) TCR monitors both channels (PRTO, PRTI) TMDR status and controls enabling and disabling of down counting and interrupts as well as controlling the output pin (A 1,JTOUT) for PRT I. = Timer Control Register (TCR : 1/0 Address 1OH) bit.~-'-~--6-,----,---,----,---,--....,--o-.., TIF1 TIFO TIE1 TIEO TOC1 TOCO TDE.1 TOEO RIW RIW RIW RIW RIW RIW TIF1: Timer Interrupt Flag 1 (bit 7) When TMDRI decrements to 0, TIFl is set to I. This can gener- ate an interrupt request if enabled by TIE! = I. TIFI is reset to O when TCR is read and the higher or lower byte ofTMDRI are read. During RESET, TIFl is cleared to 0. TIFO: Timer Interrupt Flag O (bit 6) When TMDRO decrements to 0, TIFO is set to I. This can gener- ate an interrupt request if enabled by TIEO = I. TIFO is reset to 0 when TCR is read and the higher or lower byte ofTMDRO are read. During RESET, TIFO is cleared to 0. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 443 TIE1: Timer Interrupt Enable 1 (bit 5) When TIE! is set to I, TIFI = I will generate a CPU interrupt request. When TIE! is reset to 0, the interrupt request is inhibited. During RESET, TIE! is cleared to 0. TIEO: Timer Interrupt Enable 0 !bit 41 When TIEO is set to I, TIFO = I will generate a CPU interrupt request. When TIEO is reset to 0, the interrupt request is inhibited. During RESET, TIEO is cleared to 0. TOC1, 0: Timer Output Control (bits 3, 21 TOCI and TOCO control the output of PRTI using the multip- lexed A1,ITOUT pin as shown below. During RESET, TOCI and TOCO are cleared to 0. This selects the address function for A1,f TOUT. By programming TOCI and TOCO, the A1,ITOUT pin can be forced HIGH, LOW or toggled when TMDRI decrements to 0. TOC1 TOCO OUTPUT 0 0 Inhibited (A, ,.!TOUT pin is selected as an address output function.) 0 1 1 1 0 1 toggled·} 0 (A,,.ITOUT pin is selected 1 as a PRT1 output function.) · When TMDR1 decrements to 0, TOUT level is reversed. This can provide square wave with 50% duty to external devices without any software support. TDE1, 0: Timer Down Count Enable (bits 1, 0) TDEI and TDEO enable and disable down counting for TMDRI and TMDRO respectively. When TDEn (n = 0, I) is set to I, down counting is executed for TMDRn. When TDEn is reset to 0, down counting is stopped and TMDRn can be freely read or written. TDEI and TDEO are cleared to 0 during RESET and TMDRn will not decrement until TDEn is set to I. Fig. 58 shows timer initialization, count down and reload timing. Fig. 59 shows timer output (A1,ITOUT) timing. Timer Data Register Timer Data Register write (0004H) 0 < t <20<fJ Reset tl FFFFH J_ 20<fJ 20<fJ 2Q<fJ 20<fJ 2Q<fJ 20<fJ 20<fJ 2Q<fJ 2Q<fJ I 0004H I 0003H 0002H 0001H OOOOH 0003H 0002H 0001H OOOOH 0003H I I I Timer Reload Register Write (0003H) Reload Reload ' iI Timer Reload Register FFFFH 0003H : ________.FI Write ''1'' to TOE TOE Flag TIF Flag Figure 58 PRT Operation Timing I IT____ L Timer Control Register read Timer Data Reg.=OOOOH 444 TOUT Figure 59 PAT Output Timing ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 TIF1 PRT1 Interrupt TIE1 Request TIFO TIEO PRTO Interrupt Request Figure 60 PRT Interrupt Request Circuit Diagram 13.3 PRT Interrupts The PRT interrupt request circuit is shown in Fig. 60. 13.4 PRT and RESET During RESET the bits in TCR are initialized as defined in the TCR register description. Down counting is stopped and the TMDR and RLDR registers are initialized to FFFFH. The A,/TOUT pin reverts to the address output function. 13.5 PR"( Operation Notes (1) TMDR data can be accurately read without stopping down counting by reading the lower (TMDRnL·) and higher (TMDRnH*) bytes in that order. Or, TMDR can be freely read or written by stopping the down counting. (2) Care should be taken to insure that a timer reload does not occur during or between lower (RLDRnL*) and higher (RLDRnH·) byte writes. This may be guaranteed by system design/timing or by stopping down counting (with TMDR containing a non-zero value) during the RLDR updating. Similarly, in applications in which TMDR is written at each TMDR overflow, the system/software design should guarantee that RLDR can be updated before the next overflow occurs. Otherwise, time base inaccuracy will occur. NOTE: · n = 0, I (3) During RESET, the multiplexed A1g/TOUT pin reverts to the address output. By reprogramming the TOCI and TOCO bits, the timer output function for PRT channel I can be selected. The following shows the initial state of the TOUT pin after TOCl and TOCO are programmed to select the PRT channel I timer output function. (i) PRT (channel 1) has not counted down to 0. If the PRT has not counted down to 0 (timed out), the initial state of TOUT depends on the programmed value in TOCI and TOCO; TOC1 0 1 1 TOCO 1 0 1 TOUT State After Programming TOC1/TOCO HIGH (1) HIGH (1) HIGH (1) TOUT State After Next Timeout LOW(O) LOW(O) HIGH (1) (ii)PRT (channel 1) has counted down to 0 at least once. If the PRT has counted down to 0 (timed out) at least once, the initial state of TOUT depends on the number of time outs (even or odd) that have occurred. Numbers of Timeouts (even or odd) Even (2. 4. 6 ...) Odd (1, 3, 5 ...I TOUT State After Programming TOC 1/TOCO HIGH (1) LOW(O) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 445 HD64180R------------------------------ 14 INTERNAL 1/0 REGISTERS The HD64l 80 internal I/O Registers occupy 64 1/0 addresses (including reserved addresses). These registers access the internal I/O modules {ASCI, CSI/O, PRT) and control functions {DMAC, DRAM refresh, interrupts, wait state generator, MMU and 1/0 relocation). To avoid address conflicts with external I/0, the HD64180 internal 1/0 addresses can be relocated on 64 bytes boundaries within the bottom 256 bytes of the 64k bytes 1/0 address space. 14.1 1/0 Control Register (ICRI ICR allows relocating of the internal 1/0 addresses. ICR also controls enabling/disabling of the IOSTOP mode. VO Control Register (ICR : VO Address = 3FHI R/W R/W R/W IOA7,6: 1/0 Address Relocation (bits 7-61 IOA7 and IOA6 relocate internal I/Oas shown in Fig. 61. Note that the high-order 8 bits of 16-bit internal 1/0 addresses are always 0. IOA7 and IOA6 are cleared to 0 during RESET. IOA7·IOA6=1 1 IOA7·IOA6=1 0 IOA7 · IOA6=0 1 IOA7 · IOA6=0 0 Figure 61 Internal 1/0 Address Relocation IOSTP: IOSTOP Mode {bit &I IOSTOP mode is enabled when IOSTP is set to l. Normal I/O operation resumes when IOSTP is reset to 0. IOSTP is cleared to 0 during RESET. 14.2 Internal 1/0 Registers Address Map The internal I/O register addresses are shown in Table 14. These addresses are relative to the 64 bytes boundary base address specified in ICR. 446 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ASCI CSl/O Timer Others Table 14 Internal 1/0 Register Address Map (1) Register ASCI Control Register A Ch 0 ASCI Control Register A Ch 1 ASCI Control Register B Ch 0 ASCI Control Register B Ch 1 ASCI Status Register Ch 0 ASCI Status Register Ch 1 ASCI Transmit Data Register Ch 0 ASCI Transmit Data Register Ch 1 ASCI Receive Data Register Ch 0 ASCI Receive Data Register Ch 1 CSl/O Control Register CSl/0 Transmit/Receive Data Register Timer Data Register Ch OL Timer Data Register Ch OH Reload Register Ch OL Reload Register Ch OH Timer Control Register Reserved Mnemonic CNTLAO CNTLA1 CNTLBO CNTLB1 STATO STAT1 TORO TDR1 RDRO RDR1 CNTR TRDR TMDROL TMDROH RLDROL RLDROH TCR Timer Data Register Ch 1L Timer Data Register Ch 1H Reload Register Ch 1L Reload Register Ch 1H Free Running Counter Reserved TMDR1L TMDR1H RLDR1L RLDR1H FRC Address Binary xxoooooo Hexadecimal OOH XX000001 01H XX000010 02H XX000011 03H XX000100 04H XX000101 05H XX000110 06H XX000111 07H XX001000 OSH XX001001 09H XX001010 XX001011 OAH OBH XX001100 XX001101 XX001110 XX001111 XX010000 XX010001 s XX010011 XX010100 XX010101 XX010110 XX010111 OCH ODH OEH OFH 10H s11H 13H 14H 15H 16H 17H XX011000 18H s XX011001 s19H XX011111 1FH @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 447 OMA INT Refresh MMU 1/0 Table 14 Internal 1/0 Register Address Map (2) Register Mnemonic OMA Source Address Register Ch OL OMA Source Address Register Ch OH OMA Source Address Register Ch OB DMA Destination Address Register Ch OL DMA Destination Address Register Ch OH DMA Destination Address Register Ch OB DMA Byte Count Register Ch OL OMA Byte Count Register Ch OH OMA Memory Address Register Ch 1L OMA Memory Address Register Ch 1H OMA Memory Address Register Ch 1B DMA 1/0 Address Register Ch 1L OMA 1/0 Address Register Ch 1H Reserved OMA Byte Count Register Ch 1L OMA Byte Count Register Ch 1H OMA Status Register OMA Mode Register OMA/WAIT Control Register IL Register (Interrupt Vector Low Register) INT/TRAP Control Register Reserved Refresh Control Register Reserved MMU Common Base Register MMU Sank Base Register MMU Common/Bank Area Register Reserved 1/0 Control Register SAROL SAROH SAROB DAROL DAROH DAROB BCROL BCROH MAR1L MAR1H MAR1B IAR1L IAR1H BCR1L BCR1H DSTAT DMODE DC NTL IL ITC RCR CBR BBR CBAR ICR Address Binary Hexadecimal XX100000 XX100001 XX100010 XX100011 XX100100 XX100101 XX100110 XX100111 XX101000 XX101001 XX101010 XX101011 XX101100 XX101101 XX101110 XX101111 XX110000 XX110001 XX110010 XX110011 XX110100 XX110101 XX110110 XX110111 XX111000 XX111001 XX111010 XX111011 ~ XX111110 XX111111 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH ) 3EH 3FH 14.3 1/0 Addressing Notes The internal 1/0 register addresses are located in the 1/0 address space from OOOOH to OOFFH 06-bit 1/0 addresses). Thus, to access the internal 1/0 registers (using 1/0 instructions), the high-order 8 bits of the 16-bit 1/0 address must be 0. The conventional I/O instructions (OUT (rn),A/ IN A,(rn) I OUT! I !NI/ etc.) place the contents of a CPU register on the highorder 8 bits of the address bus, and thus may be difficult to use for accessing internal 1/0 registers. For efficient internal I/O register access, a number of new instructions have been added, which force the high-order 8 bits of the 16-bit I/O address to 0. These instructions are !NO, OUTO, OTIM, OTIMR, OTDM, OTDMR and TSTIO (See section 19 Instruction Set). Note that when writing to an internal 1/0 register, the same 1/0 write occurs on the external bus. However, the duplicate external II 0 write cycle will exhibit internal I/O write cycle timing. For example, the WAIT input and programmable wait state generator are ignored. Similarly, internal 1/0 read cycles also cause a duplicate external 1/0 read cycle - however, the external read data is ignored by the HD64180. Normally, external 1/0 addresses should be chosen to avoid overlap with internal 1/0 addresses to avoid duplicate I/O accesses. 448 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 15 E CLOCK OUTPUT TIMING - 6800 TYPE BUS INTERFACE A large selection of 6800 type peripheral devices can be con- nected to the HD64180, including the Hitachi 6300 CMOS series (6321 PIA, 6350 ACIA, etc.) as well as 6500 family devices. These devices require connection with the HD64180 synchronous E clock output. The speed (access time) required for the peripheral device are determined by the HD64180 clock rate. Table 15, Fig. 62 and Fig. 63 define E clock output timing. Table 15 E Clock Timing in Each Condition Condition Op-code Fetch Cycle Memory Read/Write Cycle 1/0 read Cycle 1/0 Write Cycle m;;TI Acknowledge 1st MC rnT0 Acknowledge 1st MC BUS RELEASE mode SLEEP mode SYSTEM STOP mode Duration of E Clock Output "High" T2! - T3j (1.5</> + nw ·</>) 1stTw! - T3j 1stTw! - T3! T2! - T3j 1stTw) - T3j (0.5</> + nw · </>) (nw·</>) (1.5</>) (0.5</> + nw · </>) <Pl - </>I (2</> or 1</>) NOTE) '1w the number of wait states MC Machine Cycle OP-code Memory read/ I . fetch cycle ~write cycle 1/0 read cycle 1 1/0 write cycle NM! acknowledge INTo acknowledge Ta·~, . I 1st MC ..T1 T2 1st MC E NOTE) MC: Machine Cycle " Two wait states are automatically inserted. Figure 62 E Clock Timing (During Read/Write Cycle and Interrupt Acknowledge Cycle) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 449 ILast state Tx BUS RELEASE mode BUSACK E E~ (a) E Clock Timing in BUS RELEASE Mode SLP instruction 2nd op-code j ·fetch cycle · . 1 SLEEP mode or SYSTEM STOP mode Do-Dr iNT, NMI _,f--_ _7;6;H...;;.;;.;__-+-----------"'----- E (b) E Clock Timing in SLEEP Mode and SYSTEM STOP Mode Figure 63 E Clock Timing (in BUS RELEASE mode, SLEEP mode, SYSTEM STOP mode) Wait states inserted in op-code fetch, memory read/write and I/ 0 read/write cycles extend the duration of E clock output HIGH. Note that during I/O read/write cycles with no wait states (only occurs during on-chip I/O register accesses), E will not go HIGH. The correspondence between the duration of E clock output HIGH and standard peripheral device speed selections is as follows. Device Speed Selection 1.0 MHz (ex: HD6321 Pl 1.5 MHz (ex: HD63A21 P) 2.0 MHz (ex: HD63B21 P) Required duration of E clock output HIGH 500nsmin. 333 nsmin. 230nsmin. 16.1 6800 Type Bus Interfacing Note When the HD64180 is connected to 6800 type peripheral LSls with E clock, the 6800 type peripheral LSis should be located in UO address space. If the 6800 type peripheral LSis are located in memory address space, WR set-up time and WR hold time for E clock won't be guaranteed during memory read/write cycles and 6800 type peripheral LSIs can't be connected correctly. 450 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 16 ON-CHIP CLOCK GENERATOR The HD64180 contains a crystal oscillator and system clock (q,) generator. A crystal can be directly connected or an external clock input can be provided. In either case, the system clock (q,) is equal to one-half the input clock. For example, a crystal or external clock = input of 8 MHz corresponds with a system clock rate of q, 4 MHz. The following table shows the AT cut crystal characteristics (Co, Rs) and the load capacitance (CL!, CL2) required for various frequencies of HD64180 operation. ~ m Co Rs CL,. CL, Table 16 Crystal Characteristics 4MHz < 7 pF <son 10 to 22 pF ± 10% 4MHz < f ~ 12MHz <7pF <60!l 10 to 22 pF ± 10% 12MHz < f~ 16MHz <7 pF <60!l 10to22pF±10% If an external clock input is used instead of a crystal, the waveform (twice the q, clock rate) should exhibit a 50% ± 5% duty cycle. Note that the minimum clock input HIGH voltage level is Vcc-0.6V. The external clock input is connected to the EXTAL pin, while the XTAL pin is left open. Fig. 64 shows external clock interface. JUlJL EXTA'-!------ External Clock Input XTAL Open Figure 64 External Clock Interface Fig. 65 shows the HD64180 clock generator circuit while Fig. 66 and Fig. 67 specify circuit board design rules. CL1 EXTAL,_______,~ CJ XTAu-----,1------, ---~ CL277'r HD64180 must be avoided I~ B A, B: Signal Signal C-----~-~--1-- XTAL EXTAL HD64180 Figure 65 Crystal Interface Figure 66 Note for Board Design of the Oscillation Circuit @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA g5131 · (408) 435-8300 451 Signal line layout should ---avoid areas marked with /////. )( IV E E E 0 N l HD64180 (DP-645) (Top View) Figure 67 Example of Board Design Circuit Board design should observe the followings. (1) To prevent induced noise, the crystal and load capacitors should be physically located as close to the LSI as possible. (2) Signal lines should not run parallel to the clock oscillator inputs. In particular, the clock input circuitry and the system clock if> output should be separated as much as possible. (3) Similar to (2), Vee power lines should be separated from the clock oscillator input circuitry. (4) Resistivity between XTAL or EXTAL and the other pins should be greater than IOM ohms. Signal line layout should avoid areas marked with 11111. 452 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 17 MISCELLANEOUS Free Running Counter (1/0 Address = 18H) Read only 8-bit free running counter without control registers and status registers. The contents of the 8-bit free running counter is counted down by I with an interval of 10 ¢clock cycles. The free running counter continues counting down without being affected by the read operation. If data is written into the free running counter, we can't guarantee the interval of DRAM refresh cycle and baud rates of ASCI and CSI/O. In IOSTOP mode, the free running counter continues counting down. It is initialized to FFH during RESET. 18 OPERATION NOTES 18.1 Precaution on Interfacing the Z80* Family Peripheral LSls to the HD64180 (I) Problem In daisy chain, the Z80* family peripheral LSI (PIO, OMA, CTC, SIO, or DART) resets interrupt circuit (i.e. IEO changes from LOW to HIGH) by fetching the RETI op-code on the data bus concurrently during the CPU fetches the RETI. Therefore, the followings should be noted for the RETI opcode (EDH, 4DH) fetch timing in the Z80* peripheral LSI. When the peripheral LSI fetches the first op-code of RETI (EDH), LIR should be negated HIGH at the rising edge of system clock ¢ as shown in Fig. 71, A. (This is~ referred in the manuals for the Z80* peripheral LSI.) So, LIR hold time (LIR = HIGH) should be required as shown in Fig. 71. Because LIR changes synchronously with the rising edge of system clock¢, LIR delay time is equal to LIR hold time of the Z80* peripheral LSI. However, this LIR hold time may not be sufficient for the Z80* peripheral LSI in some case and IEO line may not be reset. (2) An example of countermeasure Fig. 72 shows an example of circuit, while Fig. 73 shows the LIR and LIR' timing in the circuit. IJli· to Peripheral LSI Figure 72 Circuit Example ' Z80 is a registered trademark of Zilog, Inc. A Data Bus Figure 71 OR Hold Time Figure 73 LIR and UR' Timing in the Circuit LIR', which is synchronized with the falling edge of system clock¢, is provided to the peripheral LSI. In this case, one-half clock cycle duration is confirmed as the hold time. Please carefully examine the circuit before you use it on your application. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 453 18.5 Precaution on Interfacing HD64180 with zso· CTC (1) Problem The following problem may happen when interfacing HD64180 with Z80* CTC (Z8430). Therefore, countermeasure shown in sec- tion 2 should be taken. Fig. 81 illustrates Z80* CTC write timing specified in Z80* CTC Data Sheet. Fig. 82 and Fig. 83 show Z80' I/ 0 write timing and HD64180 1/0 write timing respectively. As shown above, JOE in HD64180 goes LOW by a half q, clock cycle faster than IORQ in Z80. When interfacing Z80 with Z80' CTC, data is written into Z80* CTC at the rising edge of Tw. By contrast, when interfacing HD64180 with Z80* CTC, data is written into Z80* CTC at the rising edg~_Qf_T2· In the latter case, data may not be written into Z80* CTC if JOE set-up time for the rising edge of T, is less than the set-up time specified in Z80* CTC. - - - - - - - . . . . -S1et-uptime Set-uptime -------,...._..! Data Set-up time Hold time Figure 81 Z80" CTC Write Timing.. T1 T2 Tw Ta q, J1__Jl_J1__J1_ IORQ \1 - < Data I ~ t Write data Figure 82 Z80" 110 Write Timing (2) Countermeasure To Avoid the problem, IOE in HD64180 should be asserted LOW at the rising edge of T, to assure the set-up time specified in Z80* CTC. Fig. 84 (a) shows a circuit for delaying JOE by a half q, clock cycle. If this circuit is externally connected between HD64180 and Z80' CTC, JOE' will be pulled LOW at the rising edge ofT2 o~ 1/0 read/write cycl£.__!s shown in Fig. 84 (b). While in INT0 acknowledge cycle, JOE and JOE' are asserted LOW at the timing shown in Fig. 84 (c). In ~NT0 acknowledge cycle, JOE' delays because of propagation time of TTL gates of the countermeasure circuit and the vector access time is shortened. If vector access time for HD64 l 80 is not assured during INT0 acknowledge cycle, wait states should be inserted by programming IWIO and IWII bits of DMA/WAIT Control Register. However, note that wait states insertion by software should be inhibited during Z80* CTC read/write cycles, because more than one wait state can not be allowed in the case of Z80* CTC. (Please see Z80* CTC Data Sheet. One wait state is automatically inserted during the cycles.) Refer to "Fig. 85 Z80* CTC Access Flow" for details. iOE _ _ __._....., OR -1-".r--r""" <f> LS75 (a) Countermeasure Circuit (b) 1/0 Read/Write Timing Tw Tw Fixed to HIGH :jl t Write data Figure 83 HD64180 1/0 Write Timing Propagation time of TTL gates (c) INT o Acknowledge Cycle Timing Figure 84 Countermeasure Circuit and Timings in the Circuit · Z80 is a registered tr.ademark of Zilog, Inc. ··Copied from Z80' CTC Data Sheet (April, 1985) 454 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Program OMA/WAIT Control Register to insert wait states Disable INT o Disable programmable wait states insertion for 1/0 access (One wait state ·1 zso· is automatically inserted during CTC read/write cycles.) Access ZBO* CTC Enable programmable wait states insertion for 1/0 access EnablelNTo * 1 More than one wait state can not be allowed during ZBO* CTC read/write cycles. Figure 85 Z80· CTC Access Flow ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 455 18.6 Notes on HD64180 INT0 Mode 0 (1) Problem In TN'T; Mode 0, the CPU executes an instruction which is placed on the data bus during the interrupt acknowledge cycle. UsJally, RST 0-byte instruction) or CALL (3-byte instruction) is placed on the data bus. Then, the CPU pushes the Program Counter (PC) onto the stack and jumps to the interrupt service routine. In the case of RST instruction, the correct return address is pushed onto the stack. However, in the case of CALL instruction, the pushed return address is equal to the correct return address + 2. (2) Explanation of operation During the !st op-code fetch cycle in the interrupt acknowledge cycle, the CPU stops incrementing the PC. At this time, the PC contains the return address. After the !st op-code is fetched, the CPU restarts incrementing the PC. Therefore, is RST (I-byte instruction) is executed in the interrupt acknowledge cycle, the correct return address is pushed onto the stack and the CPU can return from the interrupt service routine correctly. While, if CALL (3-byte instruction) is executed in the interrupt acknowledge cycle, the PC is incremented twice during the operand read cycle of the 2 bytes after the !st op-code is fetched. Therefore, the return address + 2 in the PC is pushed onto the stack. So, when RETI is executed at the end of the interrupt service routine, the CPU can not return from the interrupt correctly. Fig. 86 shows the CALL execution timing in INT0 Mode 0. Last Machine Cycle INT0 Mode0 acknowledge cycle CALL instruction execution Interrupt service routine Ao-A1a Do 17 CALL ,~(High) I I I I I I I I I I I I I I r--------------------.1 I ' I I 1 .L----' I L/ ------------, I The return address+ 2 in the PC is pushed onto the stack. I : 1____ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _____ _J Figure 86 The CALL Execution Timing in INT 0 Mode O 456 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 (3) Countermeasure The following explains the countermeasure of the problem in INT;; Mode 0. CD RST When RST is executed, the correct return address in the PC is pushed onto the stack. (2) CALL When CALL is executed, the stack contents must be decremented by two in the interrupt service routine to return from the interrupt correctly. Table 18 summarizes how to adjust the stack contents depending on the instruction to be executed. Main Routine Table 18 Stack Contents Adjustment Instruction RST CALL Other instructions Stack Contents Adjustment No Decrement the stack contents by two No (The PC is not stacked.) The INT0 Mode 0 sequences when executing RST and CALL are shown in Fig. 87. Interrupt service routine Address PC-1 ~-;c~~ RST PC (High) - (SP-1)) ( PC (Low) - (SP- 2) SP-2-SP El RETI ( PC (Low) +- (SP) ) PC (High) +-(SP+ 1) SP-SP+2 (a) INT oMode 0 Sequence when executing RST Main Routine Interrupt service routine RST (PC+ 2 (High) - (SP-1 )) PC+2 (Low) - (SP-2) SP-2-SP Address PC-1 INToPC PDOECP BBCC } Decrements the stack DEC BC contents by two PUSH BC El RETI ( PC (Low) +- (SP) ) PC (High) +-(SP+ 1) SP +-SP+2 (bl INT oMode 0 Sequence when executing CALL NOTE) PC: PC indicates the return address Figure 87 INT 0 Mode 0 Sequence ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 457 19 INSTRUCTION SET 19.1 Instruction set overview The HD64180 is object code compatible with standard 8-bit operating system and application software. The instruction set also contains a number of new instructions to improve system and software performance, reliability and efficiency. New Instructions SLP MLT !NO g, (m) OUTO (m), g OTIM OTIMR OTDM OTDMR TSTIO m TSTg TSTm TST (HL) Operation Enter SLE mode 8-bit multiply with 16-bit result Input contents of immediate 1/0 address into register Output register contents to immediate I/O address Block output - increment Block output - increment and repeat Block output - decrement Block output - decrement and repeat Non-destructive AND, 1/0 port and accumulator Non-destructive AND, register and accumulator Non-destructive AND, immediate data and ac- cumulator Non-destructive AND, memory data and accumulator (1) SLP - Sleep The SLP instruction causes the HD64 l 80 to enter SLEEP low power consumption mode. See section 5 for a complete description of the SLEEP state. (2) MLT - Multiply The MLT performs unsigned multiplication on two 8 bit num- bers yielding a 16 bit result. MLT may specify BC, DE, HL or SP registers. In all cases, the 8-bit operands are loaded imo each half of the 16-bit register and the 16-bit result is returned in that register. (3) INO 9, (m) - Input, Immediate 1/0 address The contents of immediately specified 8-bit 1/0 address are input into the specified register. When 1/0 is accessed, OOH is output in high-order bits of address automatically. (4) OUTO (m), g - Output. immediate 1/0 address The contents of the specified register are output to the immedia- tely specified 8-bit 1/0 address. When 1/0 is accessed, OOH is output in high-order bits of address automatically. (5) OTIM. OTIMR, OTDM, OTDMR - Block 1/0 The contents of memory pointed to by HL is output to the 1/0 address in (C). The memory address (HL) and 1/0 address (C) are incremented in OTIM and OTIMR and decremented in OTDM and OTDMR respectively. B register is decremented. The OTIMR and OTDMR variants repeat the above sequence until register B is decremented to 0. Since the 1/0 address (C) is automatically incremented or decremented, these instructions are useful for block 1/0 (such as HD64180 on-chip 1/0) initialization. When 1/0 is accessed, OOH is output in high-order bits of address automatically. (6) TSTIO m - Test 1/0 Port The contents of the 1/0 port addressed by Care ANDed with 8- bit immediate data and the status flags are updated. The 1/0 port contents are not written (non-destructive AND). When 1/0 is accessed, OOH is output in higher bits of address automatically. (7) TST g - Test Register The contents of the specified register are ANDed with the ac- cumulator (A) and the status flags are updated. The accumulator and specified register are not changed (non-destructive AND). 458 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 (8) TST m - Test Immediate The 8-bit immediate data is ANDed with the accumulator (A) and the status flags are updated. The accumulator is not changed (non-destructive AND). (9) TST (HL) - Test Memory The contents of memory pointed to by HL are ANDed with the accumulator (A) and the status flags are updated. The memory contents and accumulator are not changed (non-destructive AND). 19.2 Instruction set summary The followings explain the symbols in instruction set, and the following tables summarize the operation of each instruction. (1) Register g, g', ww, xx, yy, and zz specify a register to be used. g and g' specify an 8-bit register. ww, xx, yy, and zz specify a pair of 16-bit registers. The following tables show the correspondence between symbols and registers. g,g' Reg. 000 B 001 c 010 D 011 E 100 H 101 L 111 A WW Reg. 00 BC 01 DE 10 HL 11 SP xx Reg. 00 BC 01 DE 10 IX 11 SP YY Reg. 00 BC 01 DE 10 IY 11 SP zz Reg. 00 BC 01 DE 10 HL 11 AF NOTE: Suffixed H and L to ww,xx,yy,zz (ex.wwH,IXL) indicate upper and lower 8-bit of the 16-bit register respectively. (2) Sit b specifies a bit to be manipulated in the bit manipulation in- struction. The following table shows the correspondern;e between b and bits. b Bit 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 (3) Condition f specifies the condition in program control instructions. The fol- lowing shows the correspondence between f and conditions. f Condition 000 NZ non zero 001 Z zero 010 NC non carry 011 C carry 100 PO parity odd IOI PE parity even 110 p sign plus 111 M sign minus (4) Restart Address v specifies a restart address. The following table shows the correspondence between v and restart addresses. v Address 000 OOH 001 08H 010 lOH 011 18H 100 20H 101 28H 110 30H 111 38H (5) Flag The following symbols show the flag conditions. not affected affected x undefined S settol R reset to 0 P parity V overflow (6) Miscellaneous ( )M ( >1 morn mn r R b-( )M b·gr d or j s D + ® data in the memory address data in the 1/0 address 8-bitdata 16-bit data 8-bit register 16-bit register a content of bit bin the memory address a content of bit b in the register gr 8-bit signed displacement source addressing mode destination addressing mode AND operation OR operation EXCLUSIVE OR operation ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 459 Data Manipulation Instructions Arithmetic and Logical Instructions (8-bit) o..- """" ADD MNEMONICS ADOA.g ADDA. (HU ADOA.m ADD A. (IX+d) ADDA. OY+dJ ADC ADCA.g ADC A, IHU ADC A,m ADC A. UX+d) ADC A. QY+d) ANO ANOg AND (HU ANDm ANO OX+d) AND UY+ di Com. . . . CPg CP (HU CPm CP flX+dl CP lfY+d) COMPLEMENT CPL OEC DEC g DEC IHU DEC ax+d) DEC OY+dJ INC INC g NClHU NC llX+dl OP·code Addressing MMEO EXT INO REG REGi MP 10 000 g 10 000 110 11 000 110 s <m > 11 011 101 10 ()()() 110 <d > 11111 101 10 ()()() 110 <d > s 0 s D D s D s D 10 001 g 10 001 110 11 001 110 s <m > 11 011 101 10 001 110 <d > 11111 101 10 0()1 110 <d > s D s 0 D s D s D 10 100 g 10 100 110 11 100 110 s <m > 11 011 101 10 100 110 <d > s D s D D s D 11111 101 10 100 110 <d > 10 111 g 10 111 110 11111 110 s <m > 11 011 101 10 111 110 <d > 11111 101 10 111 110 ,,, < d > 00 101 s D s D s D D s D s D SID 00 g 101 00 110 101 11 011 101 00 110 101 <d > 11111 101 00 110 101 <d > SID SID SID SID 00 g 100 00 110 100 11 011 101 00 110 100 SID SID SID - Stateo REL 1 4 1 6 2 6 3 14 3 14 1 4 1 6 2 · 3 14 3 14 1 4 1 6 2 6 3 14 3 14 1 4 1 6 2 6 3 14 3 14 1 3 1 4 1 10 3 18 3 18 1 4 1 10 3 18 Operation Ar+ gr-Ar Ar+(HUM"'"'""Ar Ar+m-Ar A1+ ax+ dlM-Ar ,.. 7 6 4 2 10 s z H PN N c I I I vRI I I I vRI I I I vRI I I IvRI + Ar+ OY d)M-Ar I I I vR I Ar+gr+c-Ar Ar+ (HUM+ c-Ar Ar+m+c-Ar I I I vRI I I IvRI I I IvRI Ar+ UX+dlM+c-Ar I I I v R I Ar+UY+d~+c-Ar I I I vRI Ar· gr-Ar .,Ar· !HUM-Ar m-IV .,. (IX+d)M-Ar I I sp RR I I s p RR I I sp RR I I sp RR /iv· OY+d.IM-Ar I l s p RR Ar-gr Ar-(HU,.. Ar-m Al- OX+dJ,.. I I I vs I I l l vsI I I IvsI I l l vs I Ar-(IY+d)M I l l vs I , ,.,._.A, gr-1-gr IHUM-1-(HU,.. UX+d1M-1- OX+dlM llY+d~-1-- 11Y+dl. s s I I l vs l I I vs l I I vs I I I vs gr+ 1--gr lHLIM+1-.. (HUM llX+d)M+1-llX+dlM I l I vR l I l vR l I IvR (to be continued) 460 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 -.... INC MUl.T NEGATE "" SUB SUBC TEST XOR --=s WCIV+d) Ml.Tww NEG ""· ORKJ ORm ORllX+cl OR IY+dl SUBg SUB IHU SUBm SUB tx+d) SUBOV+dl SBCA,g SBC A. IHLI SBCA.m sac A. OX+dl SBC A. IY+dl TSTg TST IHU TSTm XORg XOR HJ XORm XOR IX+c9 XOR IY+dl - ... - - .... OP..... ......, EXT INO REG REL <d > 11 111 101 SID 00110 100 <d > 3 18 11101 101 S<> 01 ww1 100 2 17 11101 101 01 000 100 10 110 g 10 110 110 11 110 110 s <m > 11 011 101 10110 110 <d > 11111 101 10110 110 <d > 10010 g 10010 110 11 010 110 s <m > 11 011 101 10010 110 <d > 11111 101 10010 110 <d > 10011 g 10011 110 11 011 110 s <m > 11 011 101 10 011 110 <d > 11 111 101 10011 110 <d > 11 101 101 00. 100 11101 101 00110 100 11101 101 s 01 100 100 <m > 10 101 9 10101 110 11101 110 s <m > 11011 101 10101 110 <d > 11111 101 10101 110 <d > S<> s D s D D s D s D s D s D D s D s D s D s D D s D s D s s s D s D D s D s D 2 6 1 4 1 · 2 6 3 14 3 14 1 4 1 2 · · 3 14 3 14 1 4 1 · 2 6 3 14 3 14 2 1 2 10 3 9 1 4 1 2 · · 3 14 3 14 - .... 164 2 10 5 z H PN N c OY+dlM+ 1OV+dl. " I I I v wwHrX wwlr-WWR O-Ar-Ar I I I vs I Ar+gr-Ar Ar+ftfllM-Ar Ar+m-Ar Ar+(l)(+dlu-Ar I I I I I I "" p p " p """ """ I I "p "" Ar+OV+ d!M-Ar I I "p "" Ar-,,-Ar Ar-OiUtrAr Ar-m-Ar Ar-OX+d)arAr I I I vs I I I I vs I I I I vs I I I Ivs I Ar-OV+dh.-Ar I I I vs I Ar-gr-c-Ar Ar-IHIJr.ii-c-Ar Al-m-c-AI I I I vs I I I IvsI I I I vsI Ar-(1)(+~-c-AI I I I vs I Ar- tv+ dlr.- c-Ar I I I v s I Ar· gr A<·ll<LIM A<·m ,.,,..,...,., ArE8 IHU~Ar Ar!ilm-Ar A<fl OX+dl.-A< A<flOV+diM-A< " " I I s p " " I I s p " " I I s p I I I I I I " " " p p p """ """ I I "p "" I I "p "" (to be continued) .HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 461 Rotate and Shift Instructions Oper:aliOn """" MNEMONICS OP-code IMMED EXT ......... .., REG REGI MP REL - s- Rotate ""' Shift Data AlA Rlg RL IHU RL (IX+d) RL OY+d) RLCA RLC g RLC IHU RLC OX+dl RLC UY+d) RLD ()() 010 111 11 001 011 00 010 g 11 001 011 00010 110 11 Oll IOI II 001 Oil <d > 00 010 110 11111 101 11 001 011 <d > 00 010 110 DD 000 111 11 001 011 00 DOD 9 11 001 011 ()() 000 110 11 011 101 11 001 011 <d > DD DOD 110 11111 101 11 001 011 <d > DD 000 110 11 101 101 SID SID SID SID 1 3 2 7 2 13 4 19 SID 4 19 SID SID SID SID 1 3 2 7 2 13 4 19 SID 4 19 SID 2 16 RRA RRg RR !HU RR llX+d) RR OY+d) RRCA RRC g RRC (HU ARC OX+d) RRC (IY+d) 01 101 111 00 011 111 11 001 011 · 00 011 11 001 011 00 011 110 11 011 101 11 001 011 <d > 00 011 110 11 111 101 11 001 011 <d > 00 011 110 DD DD1 111 11 001 011 DD DD1 g 11 001 011 DD DD1 110 11 011 101 11 001 011 <d > DD DD1 110 11111 101 11 001 011 <d > DD DD1 110 SID SID SID SID 1 3 2 7 2 13 4 19 SID 4 19 SID SID SID SID 1 3 2 7 2 13 4 19 SID 4 19 Operation 4Xim1 Flag 764 2 10 s z H PN N c R R l " I I R p I l I Rp Rl l I RpR I l I RpRl r1iJl!..!..!.!.tP R R l l I RpR I I I RpRI l l RpRl l I RpRl ~r " IHU.. I I R p R ~ ~ R R l I I RpRI I I RpRl I I RpRl I I Rp RI ~ R R I I I Rp RI I I Rp Rl I I Rp Rl l l Rp R l (to be continued) 462 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Operation "'~ Rotate ""' Shift Do!a MNEMONICS RRO SLA g SLA IHU SLA OX+d) SLA (IY+dl SRA g SRA (HU SRA OX+d) SRA UY+d) SILg SAL (HU SRL OX+d) SAL llY+d) OP-code Addressing ... """' IMMEO EXT NO REG REGI REL 11 101 101 "' 01 100 11 001 011 00 100 0 11 001 011 00 100 110 11 011 101 11 001 011 <d > 00 100 110 11111 101 ,, 001 011 <d > 00 100 110 11 001 011 · 00 101 11 001 011 ()() 101 110 11 011 101 ,, 001 011 <d > 00 101 110 11111 101 11 001 011 <d > 00 101 110 11 001 011 S/O 2 S/O 2 S/O 2 S/O 4 SID 4 SID 2 SID 2 SID 4 SID 4 SID 2 · 00 111 11 001 011 SID 2 00 111 110 11 011 101 SID 4 11 001 011 <d > 00 111 110 11111 101 SIO 4 11 001 011 <d > 00 111 110 s- 16 7 13 19 19 7 13 19 19 7 13 19 19 ,.. Operation 764 2 10 =Af s z H PN N c I I Rp R HU. - " I I ~· p R I I I Rp RI I I Rp R I I I Rp RI ~ I I RpRl l l RpRI I l RpR l I l Rp Rl -- o~ - - ~~ l I Rp R I l I RpRI l I Rp R I l l Rp R I ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 463 HD64180R------------------------------- Bit Manipulation Instructions -..... MNEMONICS OP. . . . . - .. - - "" IMMED EXT REG AEGI REL lltSel SETb,g 11 001 011 SID 2 7 · 11 b SET b. HI 11 001 011 SID 2 13 11 b 110 SETb. Ox+dl 11 011 101 SID 11 001 011 · 19 <d > 11 b 110 SET b. IV+d) 11111 101 SID 11 001 011 · 19 <d > ,.._ RESb,g RES b. liU 11 b 110 11 001 011 · 10 b 11 001 011 SID SID 2 7 2 13 10 b 110 RESb. ID<+dl 11 011 101 SID · 19 11 001 011 <d > 10 b 110 RES b. IY+dl 11111 101 SID 11 001 011 · 19 <d > Bit Test BIT b,g BIT b. HI 10 b 110 11 001 011 · 01 b 11 001 011 s s 2 · 2 9 01 b 110 BITb. OX+d) 11 011 101 s 11 001 011 · 15 <d > 01 b 110 llT b. tv+d) 11111 101 s 11 001 011 · 16 <d > 01 b 110 01-b·gr 1-b· Hlu 1-b· GX+dloo 1-b· IV+clu 0-b· gr 0--b: tulu 0--b· lx+<flM 0-b· llV+d>t, -~z b · ·u-r~z ~. ~. .... · · 7 2 10 s z H PN.N c · x 1 s x · x I s x · x I s x · x I s x 464 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Arithmetic Instructions (16-bit) Operation nome ADD ADC MNEMONICS AODHl,ww ADOIX,Kll ADO N,yy ADCHL,ww OP.code IMMED EXT 00 ww1 001 11 011 1D1 00 Klll 001 11111 101 oo vv1 001 11 101 101 01 wwl 010 Addressing ND REG REGI MP s D s D s D s D - REL 1 2 2 2 DEC DECww 00 wwl 011 DECIX 11 011 101 00 101 011 OECIY 11111 101 00 101 011 SID 1 SID 2 SID 2 INC NC- 00 wwO 011 . .C I X 11 011 101 00 100 011 INC IY 11111 101 00 100 011 SBC SBCHLww 11 101 101 01 wwO 010 SIO 1 SIO 2 SID 2 s D 2 s- 7 10 10 10 4 7 7 4 7 7 10 Operation H~+WWR__,Hl..fi IXJi+xlffl-IXi. IYR+VYR-IYR Flag 76 4 2 10 s z H PN N c x R I x A I x A I H~+ WWR+ c-H4q I I xvAI WWJl-1-WWR 1x.:i-1-1><ii IYR-1--+IYR WWR+ 1--+WWfl IXi.+1-l>C,i IYR+1-IYR H4t-WWR-c-H41 I I xvs I (to be continued) @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 465 Data Transfer Instructions 8-Bit Load Operation """' Lood 6-btt Dato MNEMONICS lD A.I lDA.R LO A. IBCI LD A. IDEI lD A. fmn) lD ~A LO A.A LD IBCl.A LO 00.A LO lml\l.A lD .... LDg, (Hl) lDg.m LO g. OX+d) LO g, (IV+d) LD ttU.m LO ox+dl,m LO OY+d),m LO IHL).g LO OX+d),g LO OY+dl.g O!'·oOOe ..MED EXT - IND REG REG ... REL """' 11 101 101 S/O 2 01 010 111 11 101 101 SID 2 01 011 111 DO D01 010 00 011 010 00 111 010 s <n > s 0 1 s 0 1 0 3 <m > 11 101 101 SID 2 01 000 111 11 101 101 5/0 2 01 001 111 DO 000 010 D s 1 00 010 010 D s 1 00 110 010 0 s 3 <n > .. < m > 01. S/O 1 01 g 110 D s 1 DO g 110 s 0 2 <m > 11 011 101 s D 3 01. 110 <d > 11111 101 s 0 3 01. 110 <d > 00 110 110 s 0 2 <m > 11 011 101 s 0 4 00 110 110 <d > <m > 11111 101 s 0 4 00 110 110 <d > <m > 01 110 g s 0 1 11 011 101 D s 3 01 110 g <d > 11111 101 0 s 3 01 110 g <d > s- Operation 6 ,,....., 6 R.-A< · IBCIM-Ar 6 IDEIM-14r 12 tm~-At 6 A.-· 6 A.---R< 7 Ar-IBClu 7 Ar-(DE)M 13 Ar--(mnlM 4 gr'-gr 6 IHWM-gr 6 m-gr 14 OX+d)lrr""gr 14 UY+d1ir-gr 9 m-IKJ,, 15 m-UX+dJu 15 m-(IY+diM 7 gr-IHUu 15 gr-OX+dlu 15 gr-(IV+d)y Flag 7 64 2 10 s z H PN N c I I R IEf, R I I R E" R 466 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD64180R 16-Bit Load 0- MNEMONCS -..... 1. . . . LDww. mn LDIX. mn LDIY, mn LD SP. HL LDSP, IX LO SP, IV LDww.lmnl LO HL. lmn) LO IX, lmnl LO IY, lmnl LO lmn>,ww LD lnri.HL LD..W.IX LO lmn), IY ......... ..... OP-oode ... ...ED EXT IND REG REGI REL 00 wwO 001 < > <m > 11 011 101 00 100 001 < > <m > 11111 101 00 100 001 < > <m > 11111 001 11 011 101 11111 001 11 111 101 11111 001 11 101 101 01 wwl 011 > <m > 00 101 010 SID SID SID 0 <m > 11 011 101 00 101 010 < > <m > 11111 101 D 00 101 010 < > <m > 11 101 101 01 wwO 011 < > <m > 00 100 010 < <m > 11 011 101 00 100 010 < > <m > 11111 101 00 100 010 < > <m > ·- 12 12 ·18 15 18 18 19 16 19 19 0- ... -.... mn-OX. ....--iv, HLtr-SPit 1>41-SPR IYA-SPR lmn+ l)u-wwHr lmnlu-wwlr lmn+ 1)u--Hr lmnlar-Lr lmn+ 1)u--IXHr lm~-IXLr Wm+ 1)u--IVHr '""""""IVU wwHr-lmn+ 1lu wwU--fmnlu Hl-lmn+ 11u Lr-Im.... IXHr-lmn+ l)u IXLr-fmnlo. IVHr-(mn+1JM IYLr-(rmlM Flog · · 7 2 10 s z H PN N c (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 467 Block Transfer --....... --'""""" Data MNEMONICS CPD CPDR CPI CPIR LOO LDDR LDl LOii OP-code -- - .., .... IMMED EXT REG REG! REL States -- 11 101 101 10 101 001 11 101 101 10 111 001 11 101 101 10 100 001 11 101 101 10 110 001 11 101 101 10 101 000 11 101 101 10 111 000 11 101 101 10 100 000 11 101 101 10 110 000 s s s s s s s s SID SID SID SID 2 12 Ar-(HUM oc.-1-oc. H'-ff-1-Ht.,i 2 14 BC,i:;t:OAr:l=IHUu 12 Bc..=OorAr=KJM [N-~ 0 BC..-1-Beti Hl,t-1-Hl.ft -Qunti Ar=IHWM or BCR=O 2 12 Ar-IHWM ec..-1-ec.i H41+t-H~ 2 14 ISCR'FQ Ar*(HUM 12 ~=O or Ar=fHLIM [k-liU.. Q oc.-1-oc. HL..i+l-Hl..,i RepeatO until Ar=iHIJM or8CA=O 2 12 IHLIM-OOu oc.-1-oc. 0£,,-1-0£,, 1i4-1-.... 2 1411Cti::jl:::O) [llu..-~ 1218Co=OI Q oc.-1-oc. 0£,,-1~0£,, H41-1-Hl.fl -Q- ec.i=o 2 12 liU..-iDBM oc.-1-oc. DE,i+t-Dfrt H~+1-Hl.,i 2 14(84:;t:O) [~-~~ 1218C..=Ol Q oc.-1-oc. 0£,,+1-Df,, H4i+ t-HLR "-'a""' BCR=O G) PN=OoOC.-1=0 PN=l :Beti-1¢0 @ Z=1 oN=~ Z=O : Ar=FIHIJu Flag · 7 42 10 s z H PN N c @ G) Il IIs @ G) Il IIs @ G) II I ls qi (j) I I Is G) RI R R R R G) RI R R R R 468 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ---------------------------------HD64180R Stack and Exchange Operation """" PUSH MNEMONICS PUSH zz OP-code IMMED EXT Addressing IND REG REC?! MP ·-REL 11 uO 101 s D 1 PUSH IX PUSH IV 11 011 101 11 100 101 11111 101 11 100 101 POP POP zz 11 zzO 001 SID 2 SID 2 D s 1 POP IX POP IV Exchange EX Af,AF' EX DE,Hl EXX 11 011 101 11 100 001 11 111 101 11 100 001 00 001 000 11 101 011 11 011 001 SID 2 SID 2 SID 1 SID 1 SID 1 EX ISPJ,HL EX (SP),IX EX ISP),IY 11 100 011 11 011 101 ,, 100 011 11 111 101 11 100 011 SID 1 SID 2 SID 2 S t o. . . Openition 11 zzlr-(SP- 2)M .z:zHr-(SP-1)M SPR-2-SPR 14 IXL.r--(SP-21M IXHr-(SP-1)M SPR- 2-SPrt 14 IYLr-!SP- 2)M IYHr-tSP- 1IM SPR-2-SPR 9 !SP+ 1""-zzHr ISPlu-zzlr SPR+2-5Prt 12 (SP+ 1)M----..IXHr (SPIM-IXlr SPR+2-SPR 12 (SP+ l)i,r""IYHr (SPIM-IYLr SP11+2--SPA 4 AFR-AFR' 3 oe,,-Ht,, 3 BCJi-BCR' DE,-oe,,· H~-H4l' 16 Hr-(SP+ l)M Lr-!SPIM 19 IXHr- !SP+ 1)M IXLr-ISPlu 19 IYHr-ISP+11"' lYLr-ISPIM Rog 7 6 4 2 10 s z H PN N c @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 469 _,Program Control Instructions MNEMONICS OP-code . .MEO EXT Cal CALL mn 11 001 101 <m > CALLf,mn 11f 100 < > <m > Addressing ... IND REG R£GI - ·- Operation AEL 16 ·ff ofolMl 161f. true) PCHr----ISP- l)M PCLr--ISP-21M mn-PC,, SPR-2-SPR continue:f is false CALL rm:f is true Rag · 7 4 210 s z H PN N c Jump OJNZ j 00 010 000 < j-2 > JP f, mn 111 010 > <m > $f8r:F0) 7 fBr=Ol e If :false) 9 It. true) Br-1-Br continua:Br=O PCR+ j-PC11:Br*O mn-PC,.:f is tNe continue:fisfalse ....... ..Pmo ..P IHU JP OXI ..P OYI JR j JRCj JR NC,j JR Zj JR NZJ RET AET I RETI """' ,, 000 011 > <m > 11 101 001 11 011 101 11 101 001 11111 101 11 101 001 00011 000 < j-2 00 111 000 < j-2 > ()() 110 ()()() < j-2 > 00 101 000 < j-2 ()() 100 000 < j-2 11 001 001 ,,, 000 11 101 101 01 001 101 ,, 101 101 01 000 101 mn-PGi Hl,t-PC,. l~-PC,. IYA-Pett Pet!+j-PC,. conti'lue: C=O FGi+ j-PC,.: C= 1 comn.: c= 1 Pt,i+j-PC,.: C=O continue: Z=O PC,.+ j-..PC,.: Z= 1 continue: Z=l P(«+j-PC,.: Z=O 5(f :falsel 10(f:true) ISPIM-PClr (SP+l~-PCHr 5PR+2-SPR continue:f is false RET: fistrue 12 (SP),,-PClr ISP+ 11M-PCHr SP,.+2-SPR 12 ISPlM-"PClr ISP+ 11.,rPCHr SP,.+2-SPi:i 1EF2-1Ef1 (to be continued) 470 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 - MNIMONICS RSTv MMED EXT N> REG REGI MP REL 11 v 111 Operation " PCHr--CSP- 1>M PCt.r-ISP- 2IM 0--PCHr 764210 SZHPNNC 1/0 Instructions INPUT MNEMONCS INA.(ml MMED EXT IND REG REGI MP IO 11 011 011 <m > Ng.IC) 11 101 101 01 g 000 N>g,(ml 11 101 101 0 00. 000 < m IND 11 101 101 10 101 010 11 101 101 10 111 010 N 11 101 101 10 100 010 .... 11 101 101 10 110 010 m-Ao-A1 _... Ar-As-A15 8Clrgr g= 110: Only the '""""" 12 IOOmlrll' g=110: Only the flagswlll change. m-Ao-A1 00--Aa-A·s 12 Flog 764 2 10 SZHPNNC I JRPR I JRPR © xI xx I x 1418r*O) 121Br=OI Bl-Aa-AH a[~:'. Br-1-Br a Repeat until 8'=0 © xsxx I x 12 14(8r:f::OI 121Bt=OI llCl,.-tU)w H~+l-Hl.fi Br-1-Br @ © xI xxI x Cr-Ao-A1 Br-Aa-A15 a[=~~~ © XSXXJX Br-1--Br Repeet Q l#ltil Br=O Cr-Ao-A1 Br-Ae-A15 (to be continued) @ Z=1 B<-1=0 Z=O Br-1¢0 @ N=1 MSBot0...=1 N=O MSBoto.ta=O @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 471 0 ....- . OUTPllT MNEMONCS OUT !ml.A OUT!Cl,g OUTO lml.g OlllM OTDMR OTOR oun OTll TSTIO m .......... OP-code .., IMMED EXT REG REGI IMP 11 010 011 s <m > 11101 101 s 01. 001 11 101 101 OD g 001 <m > 11101 101 10001 011 s s 11101 101 s 10011 011 11101 101 s 10 111 011 11 101 101 s 10 100 011 11101 101 s 10110 011 11 101 101 s 01 110 100 <m > -- Kl 0 2 10 D 2 10 D 3 13 D 2 14 D 2 16-0I 141Br=O) D 2 1411W'OI 1218r=Q) D 2 12 D 2 t4(8r:jl::OI 121Br=O) s 3 12 ---rrr-Ao-Ar Al-A.-Au ..-161:1 Cr-Ao-Ar Br-A1-A1G ..-llXlmh rn:-Ao-Ar O(1O1.-J-,,--A(O1O-AC1)s, fflR-1---HLR c:r-1-er Br-1-Br Cr-Ao-Ar 00-Aa-An [~~(OOC), Q Hl,fl-1-Hl« -Q-er-1-cr Br-1-Br -0 Cr-Ao-Ar 00-Aa-Au; Q[~161:1 Hlo-1-K, -Q-er-1-Br &=O Cr-Ao-Ar .....A1-A11 ~llCh HL,t+t-..... Br-1-Br Cr-Ao-Ar Br-A1-A1s [~16C\ Q Hl.fi+t-HL,: -Q-er-1-er -0 Cr-Ao-Ar Br-Aa-Au IOOCJ, ·m Cr-Ao-Ar ()()-oA1-A1s .... · · 1 2 10 s z H PN N c @ © II IpII © "s "s I " © xs xxI x @ x I x x © I x © xs xx I x " " I I s p (to be continued) @ Z=1 Br-1=0 Z=O Br-1'1'=0 @ N=1 MSBof-=1 N=O MS8 of Datl=O 472 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 -" - MNEMONICS OP-<Ode -.., .... IMMEO EXT REG REGI - s- Kl o......, OUll'UT OTM 11 101 101 10000 011 OTNA 11 101 101 10 010 011 OUTO 11 101 101 10 101 011 s 0 2 14 tt.J~(OOC~ H4t+1-H4' Cr+1-Cr Br-1-Br Cr-Ao-A1 00-A~-Aos s 0 2 161Br:i=OI 14tBr=OI [~- Q H4t+ 1-HL,i Cr+l-Cr &--1-Br Repeat a until Br=O Cr-Ao-A1 OO--Aa-A1s s 0 2 12 IHLI.-IBC~ HL41-1-"""' Br-1-Br Cr-Ao-A1 Br--Ae-A1s ,.. · · 1 2 10 s 2 H PN N c @ © I I IpI I © Rs Rs I R @ © x I xx I x @ 2=1 ....-1=0 Z=O:Br-1*0 @ N=t :MSBofData=t N=O MSB of Data=O Special Control Instructions ---·...."..""" MNEMONICS OAA OP-<Ode 00 100 111 IMMEO EXT -.., REG REGI IMP SID REL 1 s- · c.ov CCF "°"""' SCF CPU DI """""' a HALT NO N1 N2 NOP SLP 00 111 111 00 110 111 11 110 011 11 111 011 01 110 110 11 101 101 01 000 110 11 101 101 01 010 110 11101 101 01 011 110 00 000 000 11 101 101 01 110 110 1 3 1 3 1 3 1 3 1 3 2 · 2 6 2 6 1 3 2 6 o....- """""' Adjust Accwnulator c=c 1-0 @ 0--IEF 1, O--EF2 1-1EF1, l-EF2@ CPU halted ~-· modeO N-o-~· mode 1 mode2 s... ,.. · · 1 2 10 s 2 H PN N c I I Ip I R R I R R s @ Interrupts are not sampled at the end of DI or El. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 473 20 INSTRUCTION SUMMARY IN ALPHABETICAL ORDER MNEMONICS ADC A.m ADC A.g ADC A. (HU ADC A. OX+d) ADC A. OV+d) ADDA.m ADD A.g ADD A. IHU ADD A. OX+d) ADD A. OV+d) ADC HL.ww ADD HL.ww ADD IX.xx ADD rf,yy ANDm ANDg AND IHU AND OX+d) AND OV+d) BIT b, IHU BIT b, OX+d) err b, OV+d) BIT b,g CALlf,mn Bytes 2 1 1 3 3 2 1 1 3 3 2 1 2 2 2 1 1 3 3 2 4 4 2 3 3 Machine Cycles 2 2 2 6 6 2 2 2 6 6 6 5 6 6 2 2 2 6 6 3 5 5 2 2 6 States 6 4 6 14 14 6 4 6 14 14 10 7 10 10 6 4 6 14 14 9 15 15 6 6 (If condition is false) 16 (If condition is true) (to be continued) 474 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MNEMONICS CALL mn CCF CPD CPDR CP (HL) CPI CPIR CP (IX+d) CP (IY+d) CPL CPm CPg DAA DEC (HU DECIX DECIY DEC OX+dl DEC OY+dl DECg DECww DI Bytes 3 1 2 2 2 1 2 2 2 3 3 1 2 1 1 1 2 2 3 3 1 1 1 Machine Cycles 6 1 6 8 6 2 6 8 6 6 6 1 2 2 2 4 3 3 8 8 2 2 1 States 16 3 12 14 (If BCR*O and Ar*IHLlMI 12 (If BCR= 0 or Ar= (HL)M) 6 12 14 (If BCR*O and Ar*IHLIMI 12 (If BCR= 0 or Ar= (HL)M) 14 14 3 6 4 4 10 7 7 18 18 4 4 3 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 475 MNEMONICS DJNZj El EX AF.AF' EX DE.Hl EX (SP),Hl EX (SP).IX EX (SP),IY EXX HALT IMO IM 1 IM2 INCg INC (HU INC CIX+dl INC OY+d) INCww INC IX INC IY IN A.Im) IN g,(C) INI INIR IND INDR Bytes 2 2 1 1 1 1 2 2 1 1 2 2 2 1 1 3 3 1 2 2 2 2 2 2 2 2 2 Machine Cycles 5 3 1 2 1 6 1 1 1 1 2 2 2 2 4 8 8 2 3 3 3 3 4 6 4 4 6 States 9 (If Br:;t:O) 1 (If Br=O) 3 4 3 16 19 19 3 3 6 6 6 4 10 18 18 4 1 1 9 9 12 14 (If Br:;t:O) 12 (If Br=O) 12 14 (If Br*O) (to be continued) 476 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MNEMONICS INDR INO g,(m) JP f,mn JP (HU JP (IX) JP (IV) JP mn JR j JR C,j JR NC,j JR Z,j JR NZ,j Bytes 2 3 3 3 1 2 2 3 2 2 2 2 2 2 2 2 2 Machine Cycles 4 4 2 3 1 2 2 3 4 2 4 2 4 2 4 2 4 States 12 (If Br=O) 12 6 (If f is false) 9 (If f is true) 3 6 6 9 8 6 (If condition is false) 8 (If condition is true) 6 (If condition is false) 8 (If condition is true) 6 (If condition is false) 8 (If condition is true) 6 (If condition is false) 8 (If condition is true) (to be continued) ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 477 MNEMONICS LO A, (BC) LO A, (DE) LO A.I LO A, (mn) LDA.R LO (BC),A LOO LO (OE),A LD ww,mn LO ww,(mn) LDOR LD IHU,m LO HL.(mn) LO (HU,g LOI lD ~A LDIR lD IX,mn LO IX,(mn) LO (IX+d),m LO OX+d),g LO IY,mn LD IY,(mn) LD llY+d),m LD OY+d),g Bytes 1 1 2 3 2 1 2 1 3 4 2 2 2 3 1 2 2 2 2 4 4 4 3 4 4 4 3 Machine Cycles 2 2 2 4 2 3 4 3 3 6 6 4 3 5 3 4 2 6 4 4 6 5 7 4 6 5 7 States 6 6 6 12 6 7 12 7 9 18 14 (If BCR*=Ol 12 (If BCR=O) 9 15 7 12 6 14 (If BCR*=OI 12 (If BCR=O) 12 18 15 15 12 18 15 15 (to be continued) 478 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MNEMONICS LO (mnl.A LO (mn),ww LO (mn),HL LO (mn),IX LO (mn),IY LO R,A LO g,(HL) LO g,(IX+dl LO g,(IY+dl LO g,m LO g,g' LO SP,HL LO SP.IX LO SP.IV MLTww NEG NOP OR (HU OR (IX+dl OR llY+d) ORm OR g OTOM OTOMR OTOR Bytes 3 4 3 4 4 2 1 3 3 2 1 1 2 2 2 2 1 1 3 3 2 1 2 2 2 2 2 Machine Cycles 5 7 6 7 7 2 2 6 6 2 2 2 3 3 13 2 1 2 6 6 2 2 6 8 6 6 4 States 13 19 16 19 19 6 6 14 14 6 4 4 7 7 17 6 3 6 14 14 6 4 14 16 (If Br=*'O) 14 (If Br=O) 14 (If Br=*'O) 12 (If Br=O) (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 479 MNEMONICS OTIM OTIMR OTIR OUTD OUTI OUT (m),A OUT (C),g OUTO (m),g POPIX POPIY POPzz PUSH IX PUSH IV PUSH zz RES b,(HU RES b,OX+d) RES b,(IY+d) RES b,g RET RETf RETI RETN Bytes 2 2 2 2 2 2 2 2 2 3 2 2 1 2 2 1 2 4 4 2 1 1 1 2 2 Machine Cycles 6 8 6 6 4 4 4 4 4 5 4 4 3 6 6 5 5 7 7 3 3 3 4 4 4 States 14 16 (If Br::FO) 14 (If Br=Ol 14 (If Br::FO) 12 (If Br=O) 12 12 10 10 13 12 12 9 14 14 11 13 19 19 7 9 5 Of condition is false) 10 (If condition is true) 12 12 (to be continued) 480 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MNEMONICS RI.A RLCA RLC IHU RLC (IX+d) RLC (IY+d) RLC g RLD RL (HU RL (IX+d) RL OY+d) RL g RRA RRCA RRC(HU RRC (IX+d) RRC (IY+d) RRC g RRD RR (HU RR (IX+d) RR (IY+d) RR g RSTv SBC A,(HU SBC A,OX+dl SBC A,OY+d) SBC A,m Bytes 1 1 2 4 4 2 2 2 4 4 2 1 1 2 4 4 2 2 2 4 4 2 1 1 3 3 2 Machine Cycles 1 1 5 7 7 3 8 5 7 7 3 1 1 5 7 7 3 8 5 7 7 3 5 2 6 6 2 States 3 3 13 19 19 7 16 13 19 19 7 3 3 13 19 19 7 16 13 19 19 7 11 6 14 14 6 (to be continued) .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 481 MNEMONICS SBC A,g SBC HL,ww SCF SET b,(HU SET b.(IX+ d) SET b,(IY+d) SET b,g SLA (HU SLA (IX+d) SLA OY+d) SLAg SLP SRA (HL) SRA (IX+d) SRA (IY+d) SRAg SRL (HL) SRL (IX+d) SRL (IY+d) SRLg SUB (HL) SUB (IX+d) SUB (IY+d) SUBm SUBg TSTIO m TSTg Bytes 1 2 1 2 4 4 2 2 4 4 2 2 2 4 4 2 2 4 4 2 1 3 3 2 1 3 2 Machine Cycles 2 6 1 5 7 7 3 5 7 1 3 2 5 7 7 3 5 7 7 3 2 6 6 2 2 4 3 States 4 10 3 13 19 19 7 13 19 19 7 8 13 19 19 7 13 19 19 7 6 14 14 6 4 12 7 (to be continued) 482 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MNEMONICS TSTm TST (HU XOR (HU XOR (IX+dl XOR (IY+dl XORm XORg Bytes 3 2 1 3 3 2 1 Machine Cycles 3 4 2 6 6 2 2 States 9 10 6 14 14 6 4 ~HITACHI Hitachi. America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 483 ::c "O"""il 21 OP-CODE MAP -(LO=ALL) Table 18 1 In ode map ion format : XX BO DE HL SP [ (L0=0-7) 0 ."O.">. Oil L0=0-7 0 ~ BO DE HL AF zz NZ NO PO p f B D H (HL) B I D I H (HL) OOH 10H 20H 30H y :I: S' ~ l 0000 0001 0010 0011 01001010110110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 1 2 3 4 516 7 8 9 A B 0 D E F ~ B 0000 0 NOP D.Nj JR~ JR NC,j I RET f 0 f. !::: ?- 00~-c}. 2. · (I) ~ :c ;! ::J - 15 ~~ (:)c c... ~ 0 0001 D 0010 E 0011 H 0100 3 L 0101 <[ 1HLI 0110 II A 0111 ~ B 1000 0 1001 U) D 1010 E 1011 H 1100 L 1101 1HIJ 1110 A 1111 1 LO -.mn : NOTE1l POP zz 1 2 LO(-), A LD(lm) LD(lm) I I JP f, mn 2 ,HI.. ,A I I JP mn WTUiiJ] EX(lPJ ! DI 3 3 INC- LO g,s I I ADDA SUB s AND s OR s ,A ,HL 4 INO_j_ 1NOTE1) I I ,S CALL f,mn 4 5 6 DEC ..I. LO_&,_ m =====~~T~2~===~ I NOTE1) , NOTE11 I PUSH zz 5 NOTE2) NOTE21 NOTE21 NOTE2) AOO A.111 SUB m AN> m OR m 6 7 RLOA RLA DAA SOF 8 FJ.Af,lf' JR l JR Z,j_ JR OJJ RST v 7 RET f 8 9 ADD HL,- RET EXX JI (HL) LO SP, 9 A LO A, (-) LO HL. LO A, It. (rm) (rm) JP f,mn A B DEC- LO g,s ADC A SBC A XOR s OP s Table2 ,. A, (m) ElDE,tl El B 0 INC.&. ,s ,S CALL f,mn 0 D DE0...1. -------------------- :r E LO _s._ m --------------- F RROA RRA CPL OOF NOTE2l - - - - CALL Ill NOTE3l Table3 NOTE3l D NOTE2) NOTE2l NOTE2l NOTE2l ADCA,11 SBCA,11 XOR m OP m RST v F ~ !!i 0 0 1 E 2 L 3 A 4I 5I e 0 IE IL 7 A 8 9 A B 0 z DE F 0 PE M f ~ _g_(L0-8-F) OSH 18H 28H 38H y · LO=S-F j NOTE!) IHU replaces g. 2) (HL) replaces s. i 3) If DOH is supplemented as 1st op-code for the instructions which have HL or (HL) as an operand in Table 18, the instructions are executed replacing HL with IX and (HL) with OX+d). ex. 22H : LD (mn), HL DOH 22H : LD lmn), IX If FDH is supplemented as 1st op-code for the instruc1ions which have HL or IHU as an operand in Table 18. the instructions are executed replacing HL with IV and (HL) with llY+d). ex. 34H : INC (HL) FDH 34H: INC OY+d) However, JP (HL) and EX DE. HL are exception end note the foHowings. If DOH is supplemented as 1st op-code for JP (HL), (IX) replaces (HL) as operand and JP (IX) is executed. If FDH is supplemented as 1st op-coda for JP {HL), OXI replaces (HL) as operand and JP (IY) Is executed. Even if DOH or FDH is supplemented as 1st op-code for EX DE, HL, HL is not replaced~ the instruc1ion is regarded as Hlagal instruction. ::c ~ ::!: )> 3 .5",'· ~ "~ ' 0 q oQ. '@· -"~~r' s:~:c en 0 ~ ::c c:.... J8 () )> ~ ~ i ~ Tabla 19 2nd op-code map Instruction format : ~ B 0000 0 0001 D 0010 E 0011 H 0100 :J' L 0101 ..J .<!!{. (HL) A 0110 0111 ,¢ B 1000 0 1001 l>O D 1010 E 1011 H 1100 L 1101 (HL) 1110 A 1111 b (L0=0-7) oI2 I4 I6 oI2 I4 I6 OI 2 I 4 I 6 0000 0001 0010 0011 0100 0101 0110 0111 1000110011101011011 1100111011111011111 0 1 2 3 4 5 6 7 8 9 AB0 DEF 0 0 1 1 2 2 3 3 4 RLO g RL g SLA g BIT b,g RES b,g SET b,g 4 5 6 ----------- NOTE11 NOTE11 NOTE11 7 ----------- 8 5 ======~o=r!D=====I=====~~r}Ii= ====I=====~QiEJ[===== 67 8 9 9 A A B B 0 RRO gJRR gJSRA gJSRL gJ BIT b,g RES b,g SET b,g 0 D E F NOTE1) I I NOTE111 NOTE1) NOTE1) ,- - - - - -N-OTEl)- - - - - - - - - - - -NOTEl)- - - - - - - - - - -NOTE1)- - - - - ------------------------------------------------ D E F 0 2 3 4 I 5 I 6 I 7 I8 I9 IAIBICIDIE I F 11315171113151711131517 b (LO=S-F) NOTE1) If DOH is supplemented as 1st op-code for the instructions which have (HL) as operand in Table 19, the instructions are executed replacing (HL) with UX+d). If FDH is supplemented as 1st op-code for the instructions which have (HL} as operand in Table 19, the instructions are executed replacing (HL) with (IY+d). J: 0 Ol .j>. Cl) ..j.>... (11 Q) 0 ::0 "'"(Xl O'l ::c ~ 2: ~ CD ~- ~ ~ 0 q i ~ ·:c .~ ~ CD (') -~ :c '5-l 50 §;? !!l ~ · ; j ::c 0 2...!. ~ :u Table 20 2nd op-code map Instruction format : ~ WW (LO=ALL) BC DE HL SP j (L0=0-7) 8 DH 8 DH ~ l l J 0000 0001 0010 0011 0100 0101 0110 0111 100011001 1010 1011 1100111011111011111 0 0 1 2 3 4 5 6 7 8l 9 A B C D E F 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0.111 7 1000 8 1001 9 1010 A 1011 8 HOO 0 1101 . D 1110 E 11tt F INO _.I! (m) IN _sJ_C) LOI LDIR OUTO J_m),g OUT (C),g CPI CPIR SBC HL, ww INI INIR LO (im), ww OTIMlO~ OUTI OTIR TST _L TST (ll) NEG TST m lS110 nt RETN IMO IM1 ~ LO ~A LO A,I ARD INO _:I! {m) IN _.I!_ (C) LOO LODA OUT<i J_m),g OUT J_C)._g_ CPD CPDR ADC HL, ww IND INDR LO ww,J.iml Q_TDMlOIOMR OlJTD OTDR TST _L MLT ww RETI IM 2 LO R,A LO A.R RLD l 0 1 2 3 4 5 6 7 8 9 A 8 ~ r-J.--, ~ 3 ~ ~ t---e' i---r--1 ~ ~ ~ ~ ~ ir----ro-- 1----f" OJDJEJF 0 EL A0 ELA .i_J_LO=B-F 22 BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE CYCLE Instruction Machine Cycle States ADD HL,ww MC, T1T2T3 MC, -MCs TiTiTiTi ADD ix.xx ADO IY,yy MC, T1T2Ta MC, T1T2Ta MC, -MCe TiTiTiTi ADC HL.ww SBC HL,ww ADOA,g ADC A,g SUB g SBC A,g ANOg ORg XORg CP g ADD A,m AOCA,m SUBm SBC A,m ANDm ORm XORm CPm ADO A, {HU ADC A. {HU SUB {HU SBC A, {HU AND {HU OR {HU XOR {HU CP {HU ADO A. (IX+ d} ADD A, (IY+di ADC A. (IX+ di ADC A. OV+dl SUB (IX+d} SUB OV+dl SBC A, (IX+ d} MC, T1T2Ta MC2 T1T2Ta MC, -MCe TiTiTffi MC1 T1T2Ta MC2 Ti MC1 T1T2Ta MC2 T1T2Ta MC, T1T2Ta MC2 T1T:ff3 MC, T1T2Ta MC2 T1T2Ta ADDRESS 1st op-code Address 1st op-code Address 2nd op-code Address 1st op-code Address 2nd op-code Address 1st op-code Address . 1st op-code Address 1st operand Address 1st op-code Address HL 1st op-code Address 2nd op-code Address DATA 1st op-code z 1st op-code 2nd op-code z 1st op-code 2nd op-code z 1st op-code z 1st op-code m 1st op-code DATA 1st op-code 2nd op-code · !ADDRESS) : invaid Z (OATA) : high impedance. - RD WR ME IOE UR HALT ST 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 487 Instruction SBC A. llY+ d) AND llX+d) AND llY+dl OR OX+dl OR llY+dl XOR OX+d) XOR OY+d) CP OX+d) CP llY+dl Machine Cycle States MCs T,T2T3' MC· -MCo TiTi MCe T,T2To err b,g MC1 T1T2Ta MC2 T1T2T3 err b, IHL) MC1 T1T2T3 MC2 T1T2T3 MCo T1T2Ta MC1 T1T2Ta err b. ox+dl Brrb, OY+d) MC2 T1T2Ta MCo T1T2Ta MC· T1T2T3 MCs T1T2Ta MC1 T1T2T3 MC2 T1T2Ta CALL mn MCa T1T2l3 MC· Ti MCs T1T2Ts CALL f,mn IH condition is false) MCe T,T2Ta MC1 T1T2Ts MC2 T1T2Ts ADDRESS 1st operand Address IX+d IY+d 1st op-code Address 2nd op-code Address 1st op-code Address 2nd op-code Address HL 1st op-code Address 2nd op-code Address 1st operand Address 3rd op-code Address IX+d IY+d 1st op-code Address 1st operand Address 2nd operand Address SP-1 SP-2 1st op-code Address 1st operand Address DATA d z DATA 1st op-code 2nd op-code 1st op-code 2nd op-code DATA 1st op-code 2nd op-code d 3rd op-code DATA 1st op-code n m z PCH PCL 1st op-code n RD WR ME IOE LiR HAi.T ST 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 i 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 Ito be ccntinued) .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction CALL f,mn (K condttion is true) Machine Cycle States MC, T1T2Ta MC2 T1T2Ta MC, T1T2Ta ADDRESS 1st op-code Address 1st operand Address 2nd operand Address MC, Ti DATA 1st op-code n m z MC, T1T2Ta SP-1 PCH CCF CPI CPD CPIR CPDR IK ec.*o and Ar;"(HLIM) CPIR CPDR (If ec.=o or Ar=(HU.,) CPL DAA DI MCs T1T2Ta MC, T1T2Ta MC, T1T2Ta MC2 T1T2Ta MC, T1T2Ta MC· -Mes Tilili MC, T1T2Ta MC2 T1T2Ta SP-2 1st op-code Address 1st op-code Address 2nd op-code Address HL 1st op-code Address 2nd op-code Address MC, T1T2Ta MC, -MCo TiTiTiliTi MC, T1T2Ta MC2 T1T2Ta HL 1st op-code Address 2ndop-c~ Address MC, T1T2Ta MC, -MCs TiliTi MC1 T1T2Ta MC1 T1T2Ta HL 1st op-code Address 1st op-code Address MC2 Ti MC, T1T2Ta 1st op-code Address PCL 1st op-code 1st op-code 2nd op-code DATA z 1st op-code 2nd op-code DATA z 1st op-code 2nd op-code DATA z 1st op-code 1st op-code z 1st op-code - - - -- RD WR ME \OE UR HALT ST 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 Ito be continued\ @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 489 HD64180R·------------------------------- Instruction DJNZj (W Br*OI DJNZj (W Br=O) El EX DE, HL EXX EX AF. AF' Machine Cycle States MC1 T1T2Ta MC2 Ti'1 MC· T1T2T· MC· -MCs TiTi MC1 T1T2Ta ADDRESS 1st op-code Address . 1st operand Address . 1st op-<:ode Addrass MC2 Ti'1 MC· T1T2Ta MC1 T1T2Ta MC1 T1T2Ta MC1 T1T2Ta MC2 Ti MC1 T1T2Ta 1st operand Addrass 1st op-<:ode Addrass 1st op-code Addrass 1st op-<:ode Addrass . 1st op-code Addrass DATA 1st op-<:ode z j-2 z 1st op-code z j-2 1st op-code 1st op-code 1st op-code z 1st op-code RD iiiiR ME IOE Lfl HAL't ST 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 MC2 T1T2Ta SP DATA 0 1 0 1 1 1 1 EX (SP), HL MC· T1T2Ta MC· TI SP+1 DATA z 0 1 0 1 1 1 1 1; 1 1 1 1 1 1 EX (SP),IX EX (SP),IY MCo T1T2T· MCe T1T2Ta ·MC1 T1T2Ta MC2 T1T2Ta MC· T1T2Ta SP+1 SP 1st op-axle Addrass 2nd op-code Address SP H L 1st op-code 2nd op-axle DATA 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 MC· T1T2Ta MCs Ti SP+1 . DATA z 0 1 0 1 1 1 1 1 1 1 1 1 1 1 '1 OMA, REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored) Ito be continued) 490 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction EX (SP), IX EX (SP), IV HALT 11110 11111 11112 INCg DEC g INC IHU DEC(HU INC OX+dl INC OY+dl DEC OX+d) DEC OV+d) INC- oec- INC IX INC IV DEC IX DEC IV Machine Cycle States ADDRESS MCe T,T2Ta SP+1 MC1 T1T2T3 MC1 T1Tiff3 - --- MC1 T1T2T3 MC2 T1T2Ta MC1 T1T2Ta MC2 Ti MC1 T1T2Ta SP 1st op-code Addl88S Next op-code Address 1st op-code Addn!ss 2nd op-code Address 1st op-code Address . 1st op-code Address MC2 T·T2Ta MC a Ti HL . MC· T1T2Ta MC1 T1T2Ta MC2 T·T2Ta MCa T1T2Ta MC, -MCs TiTi MCe T1T2Ta MC1 Ti MCe T1T2Ta MC1 T1T2Ta MC2 Ti MC1 T1T2Ta MC2 T·T2Ta MCa Ti HL 1st op-code Address 2nd op-code Ad<lress 1st operand Address . IX+d IY+d . IX+d IV+d 1stop-code Addl88S . 1st op-code Address ~nd op-code Address . DATA IXH IVH IXL IVL 1st op-code Next op-code 1st op-code 2nd op-code 1st op-code z 1st op-code DATA z DATA 1st op-code 2nd op-code d z DATA z DATA 1st op-code z 1st op-dode 2nd op-code z RD WR" ME' iOE UR ilAt'I' ST 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 Ito be continuedl .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 491 Instruction INA,(m) IN g,(C) INO g,(m) INI IND INIR INDR (H Br*O) INIR INDR (H Br=O) Machine Cycle States MC, T1T2Ta MC2 T,T2T3 MC· T1T2T3 MC, T1T2T3 MC2 T1T2T3 ADDRESS 1st op-code Address 1st operand Addl8SS m to Ao-A1 AtoAa-A15 1st op-code Address 2nd op-code Addl8SS DATA 1st op-code m DATA 1st op-code 2nd op-code MC· T1T2Ta MC, T1T2Ts MC2 T1T2Ts MC· T1T2Ts MC· TiT2T· MC, T1T2Ts MC2 T1T2Ts BC DATA 1st op-code Addl8SS 1st op-code 2nd op-<:ode Addl8SS 2nd op-code 1st operand Address m m to Ao-A1 OOH to Aa-A" DATA 1st op-<:ode Addl8SS 1st op-code 2nd op-code Address 2nd op-code MC, T1T2Ts BC DATA MC, T1T2Ts MC, T1T2Ta MC2 T1T2T3 HL 1st op-code Address 2nd op-<:ode Address DATA 1st op-code 2nd op-code MC, T,T2T· BC DATA MC, T1T2Ts MCo -MCa TiTi MC, T1T2Ta MC2 T1T2T· HL . 1st op-code Address 2nd op-<:ode Address DATA z 1st op-code 2nd op-code MC, T1T2T· BC DATA MC, T1T2T· HL DATA - - - - - - - RD WR ME IOE LiR HALT ST 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 .o 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 1 1 1 Ito be continued) 492 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction Machine Cycle States JPmn MC1 T1T2T3 MC2 T,T2T3 MC· T,T2T3 JP f,mn (WI is !else) MC1 T,T2T3 MC2 T,T2T3 JP I.rm (WI is truel MC1 T,T2T3 MC2 T1T2T3 JP IHU MC· T,T2T3 MC1 T,T2T3 JP (IX) JP hYI MC1 T,T2T3 MC2 T,T2T3 JRj JR C,j JR NC,j JR Zj JR NZj (W condition is false) MC1 TtT2T3 MC2 T1T2T3 MC· -MC· TiTi MC1 TtT2T3 MC2 T1T2T3 JR Cj JR NCj JR Zj JR NZJ Of condition is true! MC1 T1T2T3 MC2 T1T2T3 MC· -MC· TiTi LO g.g' MC1 T1T2T· MC2 Ti LDg.m MC1 T1T2T3 MC2 T1T2T· ADDRESS 1st op-code AddnlSS 1st operand Addfass 2nd operand AddnlSS 1st op-code Address 1st operand AddnlSS 1st op-code AddnlSS 1st operand AddnlSS 2nd operand Addfass 1st op-code AddnlSS 1st op-code Addfass 2nd op-code Address 1st op-code Addl8SS 1st operand Address 1st op-code AddnlSS 1st operand Address 1st op-codii> Addfass 1st operand AddnlSS . 1st op-code AddnlSS . 1st op-code Address 1st operand Address DATA 1st op-code n m 1st op-code n 1st op-code n m 1st op-code 1st op-code 2nd op-code 1st op-code j-2 z 1st op-code j-2 1st op-code j-2 z 1st op-code z 1st op-code m -- -- - RD WR ME IOE UR HALT ST 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 Ito be continuadl $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 493 Instruction LO g, IHU LD g, OX+ di LO g, (IY+d) LD (HL),g LO (IX+d).g LD (IY+d),g LD (HU.m LD (IX+dl,m LD (IY+d),m LD A, (BC) LD A, (DE) Machine Cycle States MC, T1T2Ta ADDRESS 1st op-code Address DATA 1st op-code MC2 T1T2Ta MC, T1T2T3 MC2 T1T2T3 MC, T1T2T3 MC, -MC, TiTi MCe T1T2Ta MC, T1T2T3 MC2 Ti HL 1st op-code Address 2nd op-code Address 1st operand Address IX+d IY+d 1st op-code Address DATA 1st op-code 2nd op-code d z DATA 1st op-code z MC, T1T2Ta MC, T1T2Ta MC2 T1T2Ta MC, T1T2T3 MC, -MCe TiTiTi MC1 T1T2T3 MC, T1T2Ts MC2 T1T2T3 HL 1st op-code Address 2nd op-code Address 1st operand Address IX+d IY+d 1st op-code Address 1st operand Address g 1st op-code 2nd op-code d z g 1st op-code m MC, T1T2T3 MC, T1T2T3 MC2 T1T2T3 MC, T1T2T3 MC, T1T2T3 MCo T1T2T3 MC, T1T2T3 HL 1st op-code Address 2nd op-code Address 1st operand Address 2nd operand Address IX+d IY+d 1st op-code Address DATA 1st op-code 2nd op-code d m DATA 1st op-code Ri5 WR "ME IOE UR HALT ST 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 {to be continued) 494 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction LO A. (BC) LO A. (DE) LO A,(mnl LO (BC).A LO (DE),A LO (mnl.A LO A.I LOA,R LO iA LO A.A LOww, mn LO IX,mn LO IY,mn LO HL, (mn) Machine Cycle States MC2 T1T2T3 MC1 T,T2T3 MC2 T,T2T3 MC, T,T2T3 ADDRESS BC DE 1st op-code Address 1st operand Address 2nd operand Address DATA DATA 1st op-code n m MC, T1T2T3 MC1 T1T2Ts MC2 Ti MC, T1T2Ts MC1 T1T2Ts MC2 T,T2T3 MC, T,T2Ts MC, Ti mn 1st op-code Address BC DE 1st op-code Address 1st operand Address 2nd operand Address . DATA 1st op-code z A 1st op-code n m z MC· T,T2Ts MC1 T1T2T3 MC2 T1T2T3 MC1 T1T2T3 MC2 T,T2Ts MC, T1T2Ts MC1 T,T2T3 MC2 T1T2T3 MC, T1T2Ts MC, T1T2Ts MC1 T1T2T3 MC2 T1T2T3 mn 1st op-oode Address 2nd op-code Address 1st op-code Address 1st operand Address 2nd operand Address 1st op-code Address 2nd op-oode Address 1st operand Address 2nd operand Address 1st op-code Address 1st operand Address A 1st op-oode 2nd op-code 1st op-code n m 1st op-code 2nd op-code n m 1st op-code n Rii WR ME IOE iJlf HALT ST 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 O· 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 495 Instruction LO HL. lmnl LOww,lmnl LO IX,lmnl LO IY.lmnl \ LO lmnl,HL Machine Cycle States MC a T·T2Ta ADDRESS 2nd aperand Address MC· T,T2T3 mn MCo T1T2Ta MC1 T1T2T3 MC2 T1T2Ts MC a T1T2T3 MC, T1T2T3 mn+1 1st op-code Addrass 2nd op-code Address 1st operand Address 2nd operand Address MCo T1T2Ts mn MCo T1T2Ts MC1 T1T2Ta MC2 T1T2Ts MC a T·T2Ta MC· T1T2Ta mn+1 1st op-code Addres8 2nd op-code Addrass 1st operand Addrass 2nd operand Addrass MCo T1T2Ts mn MCo T·T2Ta MC1 T·T2Ta MC2 T·T2Ta MC a T1T2Ta MC· Ti mn+1 1st op-code Addrass 1st operand Addrass 2nd operand Addrass . MCo T1T2Ta mn MCo T1T2Ts mn+1 DATA m DATA DATA 1st op-code 2nd op-code n m DATA DATA 1st op-code 2nd op-code n m DATA DATA 1st op-code n m z L H 'Im WI! ll! lllE" 1Jf RA[T ST 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 . 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 Ctoba- 496 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 lnstructK>n LO lmn),ww LO lmnl.IX LO lmn),IY LO SP, HL LO SP.IX LO SP,IY LOI LOO Machine Cycle States MC, T1T2T3 MC2 T1T2T3 MC a T1T2l3 MC, T1T2T3 ADDRESS 1st op-code Address 2nd op-code Address 1st operand Address 2nd operand Address MCs Ti MC a T1T2T3 mn MC, T1T2l3 MC, T1T2T3 MC2 T1T2T3 MC a T1T2T3 MC, T1T2T3 mn+1 1st op-code Address 2nd op-code Address 1st operand Address 2nd operand Address MCs Ti MCs T1T2T3 mn MC, T1T2T3 MC, T1T2T3 mn+1 1st op-code Address MC2 Ti MC, T1T2T3 MC2 T1T2T3 1st op-code Address 2nd op-code Address MC a Ti MC, T1T2T3 MC2 T1T2T3 1st op-code Address 2nd op-code Address MC a T1T2T3 HL MC, T1T2T3 DE DATA 1st op-code 2nd op-code n m z wwL wwH 1st op-code 2nd op-code n m z IXL IYL IXH IYH 1st op-code z 1st op-code 2nd op-code z 1st op-code 2nd op-code DATA DATA Ri5 WR ME IOE DR HALT ST 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 497 Instruction LDlll LDDR (W BC,,*Ol LDIR LDDR 1w ec.=ol MLTww NEG NOP OUT (ml.A Machine Cycle States MC1 T1T2T3 MC2 T1T2T3 ADDRESS 1st op-code Address 2nd op-code Address DATA 1st op-code 2nd op-code MC, T1T2T3 HL DATA MC· T1T2T3 MCs -MCe TiTi MC1 T,T2T3 MC2 T1T2T3 DE 1st op-code Address 2nd op-code Address DATA z 1st op-code 2nd op-code MC, T1T2T3 HL DATA MC, T,T2T3 MC1 T 1T2T3 MC2 T 1T2l3 TiTiTiTi MC, TiTiTiTi -MC13 TiTiTi MC1 T1T2T3 MC2 T,T2T3 MC1 T 1T2T3 MC1 T1T2T3 MC2 T 1T2T3 MC, Ti MC· T1T2T3 DE 1st op-code Address 2nd op-code Address DATA 1st op-code 2nd op-code z 1st op-code Address 2nd op-code Addl8SS 1st op-code Addl8SS 1st op-code Addl8SS 1st operand Addrass . m to Ao-A1 A to Aa-A15 1st op-code 2nd op-code 1st op-code 1st op-code m z A REi WR ME N" Tili 'Rm ST 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 (to be continued) 498 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction OUT (C),g OUTO (m),g OTIM OTDM OTIMR OTDMR (lfBr'>"O) Machine Cycle States MC, T1T2T3 MC2 T1T2T3 ADDRESS 1st op-code Address 2nd op-code Address MC, Ti DATA 1st op-code 2nd op-code z MC< T1T2T3 MC, T1T2TJ MC2 T1T2T3 MC, T1T2TJ MC, Ti MCs T1T2TJ MC, T1T2T3 MC2 T1T2T3 MC, Ti BC 1st op-code Address 2nd op-code Address 1st operand Address g 1st op-code 2nd op-code m z mt0Ao-A1 OOH to A<1-A1s g 1st op-code Address 1st op-code 2nd op-code Address 2nd op-code z MC; T1T2T3 MCs T1T2T3 MCo Ti MC, T1T2T3 MC2 T1T2TJ MC, Ti HL DATA C to Ao-A1 OOH to Ad-A1s DATA 1st op-code Address 2nd op-code Address z 1st op-code 2nd op-code z MC· T1T2TJ MCs T1T2Ts MCo -MC" TiTiTi HL DATA Cto Ao-A1 OOH to Ad-A1s DATA z Ri5 WR ME IOE ITli HALT ST 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 499 Instruction OTIMR OTDMR (If Br=O) OUTI OUTD OTIR OTDR (lfBr*Ol OTIR OTDR (If Br=O) POP zz POPIX POP IV Machine Cycle States MC1 T1T2T3 MC2 T 1T2T3 MC, Ti MC· T1T2T3 MCs T1T2T3 MCa Ti MC1 T1T2T3 MC2 T1T2T3 Mc, T1T2T3 MC· T1T2Ta MC1 T 1T2T3 MC2 T1T2T3 MC, T1T2T3 MC· T1T2T3 MCs -Meo TiTi MC1 T1T2T3 MC2 T1T2T3 MC, T1T2T3 MC· T1T2T3 MC1 T1T2T3 MC2 T1T2l3 MC, T1T2T3 MC1 T1T2T3 ADDRESS 1st op-code Address 2nd op-code Address DATA 1st op-code 2nd op-code z HL DATA C 1o Ao-A1 OOH 1o A·-A15 . DATA z 1st op-code Address 2nd op-code Address 1st op-code 2nd op-code HL DATA BC 1st op-code Address 2nd op-code Address DATA 1st op-code 2nd op-code HL DATA BC 1st op-code Address 2nd op-code Address DATA z 1st op-code 2nd op-code HL DATA BC 1st op-code Address DATA 1st op-code SP DATA SP+1 1st op-code Address DATA 1st op-code iiD WR ME KiE Dif HACT ST 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 (to be continued! 500 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction POP IX POP IY PUSH zz PUSH IX PUSH IY RET RET I (tt condition is false) RET I (tt cond~ion is true) RETI RETN Machine Cycle States MC2 T,T2T3 ADDRESS 2nd op-code Address MC, T1T2T3 SP MC, T1T2T3 MC, T1T2T3 MC2 -MC, Tili SP+1 1st op-code Address MC, T1T2T3 SP-1 MC, T1T2T3 MC, T1T2T3 MC2 T1T2T3 MC, --MC4 TiTi SP-2 1st op-code Address 2nd op-code Address MC, T1T2T3 SP-1 MCs T1T2T3 MC, T1T2T3 SP-2 1st op-code Address MC2 T1T2T3 SP Mc, T1T2T3 MC, T1T2T3 MC2 -MC, TiTi MC, T1T2T3 SP+1 1st op-code Address 1st op-code Address MC2 Ti MC, T1T2T3 SP MC, T1T2T3 MC, T1T2T3 MC2 T1T2T3 SP+1 1st op-code Address 2nd op-code Address DATA 2nd op-code DATA DATA 1st op-code z zzH zzL 1st op-code 2nd op-code z IXH IYH IXL IYL 1st op-code DATA DATA 1st op-code z 1st op-code z DATA DATA 1st op-code 2nd op-code RB WR ME IOE UR HALT ST . 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 501 Instruction REll RETN RLCA RLA RRCA RRA RLC g Rlg RRC g RRg SLA g SRA g SRLg RLC (HU RL !HU RRC (HL) RR(HU SLA (HL) SRA (HU SAL (HU RLC (IX+d) RLC (IY+d) RL (IX+d) RL (IY+d) RRC (IX+d) RRC (IY+d) RR (IX+d) RR (IY+d) SLA (IX+d) SLA (IY+d) SRA (IX+d) SRA (IY+d) SRL (IX+d) SRL (IY+d) RLD RRD Machine Cycle States ADDRESS MC· T1T2T3 MC, T1T:ff3 SP SP+1 MC1 T1T2T3 1st op-code Address MC1 T1T2T3 MC, T1T2T3 1st op-code Address 2nd op-code Address MC· Ti MC1 T1T2T3 MC2 T1T2T3 MC, T1T2l3 1st op-code Address 2nd op-code Address HL MC, Ti MC, T1T2T3 MC1 T1T2T3 MC2 T1T2T3 MC· T1T2T3 MC, T1T2T3 MC, T1T2T3 MCe Ti MC1 T1T2T3 MC1 T1T2T3 MC2 T1T2T3 MC· T1T2T3 HL 1st op-code Address 2nd op-code Address 1st operand Address 3rd op-code Address IX+d IY+d . IX+d IY+d 1st op-code Address 2nd op-code Address HL DATA DATA DATA 1st op-code 1st op-code 2nd op-code z 1st op-code 2nd op-code DATA z DATA 1st op-code 2nd op-code d 3rd op-code DATA z DATA 1st op-code 2nd op-code DATA 'RD WR ME IOE Tiii HA[T ST 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 Ito be continued! 502 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 lnstructK>n RLD RRD RST v SCF SET b,g RES b,g SET b, (HU RES b, (HU SET b, (IX+ d) SET b, (IY+d) RES b. OX+d) RES b, (IY+d) Machine Cycle States MC· -MC1 TiTiTiTi ADDRESS MC a T,T2Ta MC, T1T2Ta MC2 -MCa TiTi HL 1st op-code Address MC, T1T2T3 SP-1 MCs T1T2T3 MC, T1T2T3 MC, T1T2Ta MC2 T,T2T3 SP-2 1st op-code Address 1st op-code Address 2nd op-code Address MCa Ti MC, T,T2Ta MC2 T1T2T3 1st op-code Address 2nd op-code Address MC a T1T2T3 HL MC· Ti MC, T1T2T3 MC, T,T2Ta MC2 T1T2Ta MC a T1T2Ta MC, T1T2Ta MC, T1T2Ta HL 1st op-code Address 2nd op-code Address 1st operand Address 3rd op-code Address tx+d IY+d MCe Ti MC1 T1T2T3 IX+d IY+d DATA z DATA 1st op--code z PCH PCL 1st op-code 1st op-code 2nd op-code z 1st op-code 2nd op-code DATA z DATA 1st op-code 2nd op-code d 3rd op-code DATA z DATA ms WR ME IOE LIR HALT ST 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 (to be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 503 Instruction SLP TSTIO m TSTg TSTm TST(HU Machine Cycle States MC, T1T2Ta MC2 T1T2Ta - -- MC, T1T2Ta MC2 T1T2Ta MC, T1T2Ta MC· T1T2Ta MC, T1T2Ta MC2 T1T2Ta MC, Ti MC, T1T~!Ta MC2 T1T2T3 MC, T1T2Ta MC, T1T2Ta MC2 T1T2Ta MC, Ti ADDRESS DATA 1st op-axle Address 2nd op-code Addl9SS 7FFFFH 1st op-axle 2nd op-code z 1st op-code Addl9SS 2nd Op-<:ode Addrass 1st op-code 2nd op-axle 1st operand Address m C toAo-A1 OOH to Aa-A15 DATA 1st op-<:ode Addl9SS 1st op-code 2nd op-code Addl9SS . 2nd op-code z 1st op-axle Addl9SS 2nd op-code Addl9SS 1st op-code 2nd op-code 1st operand Addl9SS m 1st op-code Addrass 1st op-<:ode 2nd op-axle Addl9SS . 2iid op-code z INTERRUPT MC, T1T2Ta MC, T1T2Ta MC2 -MC, TiTi NMI MC· T1T2Ta HL DATA Next op-code Addrass IPCl . z SP-1 PCH INTo MODE 0 (RST INSERTED) MCs T1T2Ta T1T2Tw MC, TwTa MC2 -MCa TiTi SP-2 Next op-code Addrass (PC) . PCL 1st op-code z ftD Wli ~ m Ill HAIT ST 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 ,o 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 (to be oontinued) 504 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Instruction Machine Cycle States ADDRESS DATA INTo MODE 0 IRST NSERTED) INTo MODE 0 (CALL INSERTED) INTo MODE 1 INTo MODE 2 MC, TiT2T3 MCs TiT2T3 T,T2Tw MC, TwT3 MC2 TiT2T3 MC, T1T2T3 MC, Ti MCs TiT2T3 MCs TiT2T3 T1T2Tw MC, Twls MC2 T1T2Ts MC, T1T2Ts T,T2Tw MC, TwTs MC2 Ti MC, TiT2Ts MC, T1T2T3 SP-1 PCH SP-2 Next op-code Address (PC) PCL 1st op-code PC n PC+1 . m z SP-1 PC+21H) SP-2 Next op-code Address (PC) PC+21U SP-1 PCH SP-2 Next op-code Address IPC) PCL Vector z SP-1 PCH SP-2 PCL INT, INT2 Internal Interrupts MCs Til2T3 MCs T1T2Ts TiT2Tw MC, TwTs MC2 Ti MC, T1T2Ts MC, T,T2Ts MCs T,T2Ts I. Vector DATA I. Vector+ 1 Next op-code Address (PC) DATA z SP-1 PCH SP-2 PCL I, Vector DATA MCs T1T2Ts I, Vector+ 1 DATA RB WR ME IDE TIR HALT ST 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 505 (11 0 Ol :c: ~ :e: )> 3 ~ ~r !::.: !1 ~ 0 Q c0mt@· ~ :I g ~ CD - (/) C') ~ :I c.... -~ §;; "S!' ~ ~ 0 ..$.. """~ " ' ' 0 ~ts t WAIT Refresh Request (Request of Refresh by the on-chip Refresh Controller) DREOo DRE01 Normal Operation (CPU mode) (IOSTOP mode) Acceptable Refresh cycle begins at the end of MC. OMA cycle begins at the end of MC. BUSREO Interrupt INTo, INT1, INT2 Bus is released at the end of MC. Accepted after executing the current instruction. Internal 1/0 1 Interrupt NMI 1 WAIT State Acceptable Not acceptable OMA cycle begins at the end of MC. Not acceptable Accepted after executing the current instruction 1 1 Refresh Cycle Interrupt Acknowledge Cycle Not acceptable Acceptable Not acceptable Refresh cycle begins at the end of MC. Acceptable · Refresh cycle precedes. OMA cycle begins at the end of one MC. Acceptable OMA cycle begins at the end of MC. Not acceptable Bus is released at the end of MC. Not acceptable Not acceptable OMA Cycle BUS RELEASE SLEEP mode mode Acceptable Not acceptable Not acceptable Refresh cycle begins at the end of MC. Not acceptable Not acceptable Acceptable Refer to "2.9.0MA Controller" for details. Ar.r.P.ntahle ·After BUS RELEASE cycle, OMA cycle begins at the end of one MC. Not acceptable Bus is released at the end of MC. Continue BUS RELEASE mode. Acceptable Not acceptable Not acceptable Acceptable Return from SLEEP mode to normal operation. 1 1 1 1 1 Not acceptable Acceptable Interrupt OMA cycle acknowledge stops. 1 cycle precedes. NMI is accepted I 1 after executing the next in- struction. SYSTEM STOP mode Not acceptable Not acceptable Not acceptable Acceptable Acceptable Return from SYSTEM STOP mode to normal operation. Not acceptable Acceptable Return from SYSTEM STOP mode to normal operation . ./ NOTE) · 1 not acceptable when OMA Request is in level sense. same as the above MC : Machine Cycle N w :m:a :I: c Ol p ...cm Ill 0"~ "0" 0 :;JJ )> (') (m') ~ z)> m 0 zIll m )> 0 :i: 0 :"m:IaI z ~ G) 3: 0cm 24 REQUEST PRIORITY The HD64180 has the following three types of requests. Type 1. To be accepted in specified state........... WAIT Type 2. To be accepted in each machine cycle ...... Refresh Req. DMA Req. Bus Req. Type 3. To be accepted in each instruction ......... Interrupt Req. 26 OPERATION MODE TRANSITION Type I, Type 2, and Type 3 requests priority is shown as follows. highest priority Type I > Type 2 > Type 3 lowest priority Each request priority in Type 2 is shown as follows. highest priority Bus Req. > Refresh Req. > DMA Req. lowest priority (NOTE) If Bus Req. and Refresh Req. occurs simultaneously, Bus Req. is accepted but Refresh Req. is cleared. Refer to "2. 7 Interrupts" for each request priority in Type 3. NOTE) *1 NORMAL: CPU executes instructions normaHv in NORMAL mode. ·2 OMA request: OMA is requested in the following cases. = (11 ~. ~ 0 (memory ~ (memory mapped) 1/0 OMA transfer) = 12) OEO 1 (memory ......._ memory OMA ...nsferl ·3 OMA end: OMA ends in the following cases. = 11) OREQo, OREQ, 1 (memory......._ (memory mapped) 1/0 OMA transferl = 12) BCRO, BCR1 OOOOH (all OMA transfers) {3) lilM1 = O lal OMA transfers) Other operation mode transitions The following operation mode transitions are also possible. 1. HALT ~ f:MA } REFRESH BUS RELEASE IOSTOP ~~ESH l;~S } RELEASE 2. SLEEP ~ BUS RELEASE SYSTEM STOP ~ BUS RELEASE @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 507 26 STATUS SIGNALS The following table shows pin outputs in each operating mode. Mode CPU operation Op-code Fetch (1 st op-code) O~ode Fetch (except 1st op-code) Memory Read Memory Write VO Read VO Write Internal Operation Refresh nterrupt NMI jAcknowledg INTo lcvcle (1st machine INT 1, lllT2 & lcvclel Internal Interrupts BUS RELEASE HALT SLEEP Internal OMA RESET Memory Read Memory Write VO Read VO Write NOTE! 1 HIGH 0 LOW A Programmable Z High Impedance IN Input OUT: Output Invalid Address Data LIR ME IOE RD Wft ~ HALT BUSACK ST BUS BUS 0 0 1 0 1 1 1 1 0 A IN 0 0 1 0 1 1 1 1 1 A IN 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 A IN A OUT A IN A OUT 1 1 1 1 1 1 1 1 1 A IN 1 0 1 1 1 0 1 . 1 A IN 0 0 1 0 1 1 1 1 0 A IN 0 1 0 1 1 1 1 1 0 A IN 1 1 1 1 1 1 1 1 0 A IN 1zzzz1 1 0 . z IN 0 0 1 0 1 1 0 1 0 A IN 1 1 1 1 1 1 0 1 1 1 1111 1 0 1 0 1 1 1 1 0 A IN 1 0 1 1 0 1 1 1 0 A OUT 1 1 0 0 1 1 1 1 0 A IN 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 A OUT z IN 508 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 27 PIN STATUS DURING RESET AND LOW POWER OPERATION MODES Pin No. Symbol 4 WAIT 5 BUSACK 6 BUSREQ 7 RESET 8 NMI 9 INTo 10 INT1 11 INT2 12 ST 13-30 Ao--A11 31 A1.JTOUT 34-41 42 43 44 45 46 47 Do-01 RTSo CTSo DCDo TXAo RXAo CKAo/DREQo Pin function - - - - - - - - A1· TOUT - - - CKAo Gntemal clock model CKAo (external clock mode) DREQo RESET IN (NI 1 IN (NI 0 IN (NI IN (NI IN INI IN (NI 1 z z z z 1 IN (NI IN INI 1 IN INI z z z 48 TXA1 49 RXA1 50 CKA1/TEND0 51 TXS 52 RXS/CTS1 - - CKA1 Gntemal clock mode) CKA1 (external clock model TEN Do - RXS 1 IN (N) z z z 1 IN (N) 53 CKS 54 DREQ1 55 TEND1 56 HALT 57 REF 58 IOE 59 ME 60 E 61 UR 62 Wli 63 RD 64 "' CTS1 CKS (internal clock mode) CKS (external clock mode) - - - - - - - -- - IN (NI z z IN (NI 1 1 1 1 1 0 1 1 1 </> clock output 1: HIGH 0: LOW A: Programmable Z: High Impedance IN (A): Input (Active) IN (N): Input (Not active) OUT: Output H: Holds the pravious state -: same as the left Pin status in each operatioo mode SLEEP IOSTOP IN (NI IN (A) OUT IN (A) OUT IN (A) IN (A) IN (A) IN (A) IN (A) IN (A) IN (A) IN (Al IN (A) IN (Al IN (A) 1 OUT 1 A 1 A OUT H z A H OUT IN (Al IN (N) IN (A) IN (N) OUT H IN (Al OUT IN (NI z IN (Al IN INI IN IN) OUT IN (A) OUT IN (A) H IN INI z IN (Al IN INI 1 OUT IN (A) IN (A) OUT IN (A) OUT H IN(NI IN IN) 1 z IN (N) 1 0 1 1 1 E clock output 1 1 -1 IN (A) OUT OUT OUT OUT -OUT OUT OUT -OUT SYSTEM STOP IN (N) OUT IN (A) IN (A) IN (Al IN (A) IN (Al IN (Al 1 1 1 H z H IN (NI IN (NI H IN INI z IN INI IN (NI H IN (NI z IN INI 1 H IN (N) IN (N) 1 z IN (NI 1 0 1 1 -1 1 1 -1 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 509 28 INTERNAL 1/0 REGISTERS By programming IOA7 and IOA6 in the 1/0 control register, in- temal UO register addresses are relocatable within ranges from OOOOH to OOFFH in the UO address space. REGISTER ] MNEMONICS ADDRESS REMARKS ASCI CQntml Regis111r A Channel 0 : CNTLAO ASCI Control Ragis111r A Channel 1 : CNTLA1 0 0 0 1 bit during RESET R/W MPE RE TE ~ MPBR/ EFR MOD2 MOD1 MODO 0 0 0 1 invalid 0 0 0 R/W R/W R/W R/W 1 L R/W R/W R/W R/W MODE Selection Multi Processor Bit Receive/ Error Flag Reset Request To Sand L- Transmit Enable L- Recalve Enable '--Multi Processor Enable bit during RESET R/W MPE RE TE icKA1D MPBR/ EFR MOD2 MOD1 MODO 0 0 0 1 invalid 0 0 0 R/W R/W R/W R/W 1R/W R/W R/W R/W LMODE Selection Multi Processor Btt Receive/ Error Flag Reset L- CKA1 Disable ' -Transrntt Enable '-Receive Enable ' - Multi Processor Enable MOD2, 1,0 000 0 0 1 0 10 0 1 1 10 0 10 1 1 1 0 1 1 1 + + Start 7 bit Data 1 Stop + + Start 7 btt Data 2 Stop + + + Start 7 bit Data Parity 1 Stop + + + Start 7 bit Data Parity 2 Stop + + Start B bit Data 1 Stop + + Start 8 bit Data 2 Stop + + + Start 8 bit Data Parity 1 Stop + + + Start 8 btt Data Parity 2 Stop ~Cl Control Ragistar II Chamel 0 0 2 : CNTLBO bit MPBT MP during RESET invalid 0 .f'TS/ PS PEO 0 DR 0 SS2 1 SS1 1 sso 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W [ Tclock Soun:e and Speed Select Divide Ratio '-Parity Even or Odd '-- Clear To Sand/Prascala '-Multi Processor L.Multi Processor Bil Transmit · CTS : D!IPending on the condttion of CTS Pin. PS : Cleared to 0. 510 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 REGISTER l MNEMONICS ADDRESS REMARKS ASCI Control Register B Channel 1 : CNTLB1 0 3 bit MPBT MP CTS/ PS PEO DR SS2 SS1 sso during RESET R/W invalid 0 0 0 0 1 1 1 R/W R/W R/W R/W lR/W I R/W R/W R/W L Clock Source and Speed Select Divide Ratio '-Parity Even or Odd '- Clear To Send/Prescale '- Multi Processor '-Multi Processor Bit Transmit General divide ra1io SS2,1,0 000 001 010 011 100 101 110 111 PS=O (divide ratio= 10) PS=1 (divide ratio= 30) DR=O {X16) DR=1 (X64) DR=O (X16) DR=1 (X64) <f>+ 160 + 320 + 640 <f>+ 640 + 1280 + 2560 + 1280 + 5120 + 2560 +10240 + 5120 +20480 +10240 +40960 External clock (frequency < <f>+ 480 + 960 + 1920 + 3840 + 7680 +15360 +30720 "' +40) <f>+ 1920 + 3840 + 7680 + 15360 + 30720 + 61440 + 122880 jAsc1 Status Register Channel o 0 4 : STATO jA.sc1 Status Register Channel 1 0 5 : STAT1 bit RDRF OVRN PE during RESET 0 0 0 FE 0 . .. RIE DCfiO TORE TE 0 0 R/W R R R R R/W R R R/W Tra~smit Interrupt Enable Transmit Data Register Empty Data Carrier Datect '-- Receive Interrupt En- ' - Framing Enor '--ParityEnor '- Over Run Error '-Receive Data Register Ful · DCDii : "-1ding on the condition of DCDo Pin. ·· CTSo Pinl TORE l L 1 H 0 bit RDRF OVRN PE FE RIE CTS1E TORE TIE during RESET 0 0 0 0 0 0 1 0 R/W R R R R R/W R/W R R/W lsmit Interrupt Enable :rransmit Data ___l!!gister Empty ' - CTS 1 Enable '-Receive Interrupt Enable '-Framing Error '-Parity Enor '- Over Run Error '- Receive Data Register Full Ito be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 511 REGISTER I MNEMONICS ADDRESS ASCI Transmit Data Register Channel 0 6 0 : TORO ASCI Transmit Data Register Channel 1 : TDR1 0 7 ASCI Receive Data Register Channel 0 : TSAO 0 8 ASCI Receive Data Register Channel 1 : TSR1 0 9 CSVO Control Register : CNTR 0 A CSVO Transmit/Receive Data Ragistar : TRDR Timer Data Register Channel Ol :TMDROL Timer Data Register Channel OH : TMDROH Timer Reload Register Channel Ol : RLDROL Timer Reload Register Channel OH : RLDROH Timer Control Register : TCR 0 8 0 C 0 D 0 E 0 F 1 O REMARKS bit during RESET R/W EF EE RE TE - SS2 SS1 SSO 0 0 0 0 1 1 1 1 R R/W lR/W I R/W R/W R/W R/W T 1speec1 Select Transmit Enable Receive Enable L. End Interrupt Enable End Flag SS2,1,0 000 001 010 011 Baud Rata t/J+ 20 + 40 + 80 +160 SS2,1,0 100 101 110 111 Baud Rata t/J+ 320 + 640 +1280 External (frequency < + 201 bit TIF1 during RESET 0 R/W R TFO TE1 TIEO TOC1 TOCO TDE1 TDEO 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W [ l Tiner 0own Count Enable 1,0 Tmer Output Control 1,0 Tiner Interrupt Enable 1,0 I Tmer Interrupt Flag 1,0 TOC1,0 00 01 10 11 lnhilited Toggle 0 1 Ito be c:ontiruedl 512 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 REGISTER jMNEMONICS ADDRESS Timer Data Register Channel 1L : TMDRIL Timer Data Register Channel I H :TMDRIH Timer Raload Register Channel IL : RLDR1L Timer Reload Register Channel 1H : RLDR1H Free Running Counter : FRC OMA Source Address Register Channel OL : SAROL OMA Source Addl888 Register Channel OH : SAROH OMA Source Addraes Register Channel OB : SAROB 1 4 I 5 I 6 I 7 I 8 2 0 2 1 2 2 OMA Dastination Addraes Register 2 3 Channel OL : DAROL OMA Das!Ntion Addl888 Register 2 4 Channel OH : DAROH OMA Destination Address Register 2 5 Channel OB : DAROB OMA Byte Count Register Channel OL : BCROL OMA Byte Count Register Channel OH : BCROH OMA Memooy Address Register Channel 1L :MARIL OMA Memooy Address Register Channel 1H : MAR1H OMA Memory Address Register Channel IB : MAR1B OMA VO Addl888 Register Channel 1L : IAR1L OMA VO Address Register Channel 1H : IARIH 2 6 2 7 2 8 2 9 2 A 2 B 2 c REMARKS reed only Bits 0-2 are used for SAROB. A1s, A11, A10 x0 0 x0 1 xI 0 xI I OMA Transfer Request DREQo laxtermilf RDRO IASCIO) RORI IASCl1) Not Used Bits 0-2 are used for OAROB. A1s, A11, A10 x0 0 x0 I x 1 0 xI I OMA Transfer Request [}ffEllO <axtemal) TORO IASCIO) TORI IASCl1) Not Used Bits 0-2 are used for MAR1B. Ito be continued) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 513 REGISTER 1 MNEMONICS ADDRESS OMA Byte Count Register Channel 1L : BCR1L 2 E OMA Byte Count Register Channel 1H : BCR1H 2 F REMARKS OMA Status Register 3 0 : DSTAT bit - DE1 DEO DWE1 DWEO DIE1 DIEO DME during RESET 0 0 1 1 0 0 1 0 R/W R/W R/W w w R/W R/W R OMA Mode Register : DMODE 3 1 bit during RESET R/W loMA Master Enable loMA lnlelTupt Enable 1.0 '-OMA Enable Bit Write Enable 1,0 '--OMA Enabl!I ch 1.0 - - - DM1 OMO SM1 SMO MMOD 1 1 0 0 0 0 0 1 R/W R/W R/W R/W R/W DM1, 0 Destination Address 00 M 0 1 M 1 0 M DAR0+1 DAR0-1 DARO fixed 1 1 VO DARO fixed l MMOD Mode 0 I Cycle Steal Mode 1 Burst Mode LMemory MODE Select ' - Ch 0 Source Mode 1,0 '-Ch 0 Destination Mode 1, 0 SM1,0 Source 00 M 01 M 10 M 1 1 VO Address SAR0+1 SAR0-1 SARO fixed SARO fixed (to be continued) 514 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 REGISTER l MNEMONICS ADDRESS REMARKS DMA/WAJT Control Register : DCNTL 3 2 bit during RESET R/W MWl1 1 R/W MWIO 1 R/W IWl1 1 R/W IWIO 1 R/W DMS1 0 R/W DMSO 0 R/W DM1 0 R/W DIMO 0 R/W LDMA Ch 1 1/0 Merner( Mode Select '- l5Rffii Select i = 1,0 '- 1/0 Wait Insertion ~ Merner( Wait Insertion MWl1,D The number of wait states OD D 01 1 10 2 11 3 J OMSi Sense I 1 Edge sense 0 Level sense IWl1,0 00 01 10 11 The number of wait states 0 2 3 4 DM1,0 OD D1 10 1 1 Transfer Mode M-1/0 M-1/0 1/0-M 1/0-M Address Increment/Decrement MAR1+1 MAR1-1 IAR1 fixed IAR1 fixed IAR1 fixed IAR1 fixed MAR1+1 MAR1-1 Interrupt Vector Low Register : IL 3 3 INT/TRAP Control Register 3 4 : ITC Refresh Control Register : RCR 3 6 bit IL7 IL6 IL5 - - - - - during RESET 0 0 0 0 0 0 0 0 R/W R/W R/W R/W [lntenupt Vector Low bit - TRAP UFO - - during RESET 0 0 1 1 1 R/W lR/W R lUndefined Fetch Object TRAP bit - REFE REFW - - during RESET 1 1 1 1 1 R/W lR/W R/W Lefresh Wait State Refresh Enable CYC1,0 00 01 10 11 Interval of Refresh Cycle 10 States 20 40 80 ITE2 0 R/W ITE1 0 R/W ITEO 1 R/W LINT Enable 2, 1,0 - CYC1 CYCO 1 0 0 R/W R/W lcvcle Select (to be continued) @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 515 REGISTER I MNEMONICS AODRESS MMU Common Base Register : CBR 3 B MMU Bank Base Register : BBR 3 9 MMU Common/Bank Area Register : CBAR 3 A REMARKS bn during RESET R/W - 0 R/W CBS 0 R/W CB5 0 R/W CB4 0 R/W CB3 0 R/W CB2 0 R/W CB1 0 R/W CBO 0 R/W 1 MMU Common Base Register btt - 886 BB5 884 BB3 882 BB1 BBO during RESET 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W L _ MMU Bank Base Register bn CA3 during RESET 1 R/W R/W CA2 1 R/W CA1 1 R/W CAO 1 R/W BA3 0 R/W BA2 0 R/W BA1 0 R/W BAO 0 R/W VO Control Register : ICR 3 F [MMUCommon Area Register bit - IOA7 IOA6 IOSTP - during RESET 0 0 0 1 1 R/W R/W R/W R/W L Lvo Stop 11 /0 Address LMMUBank Area Register --- 1 1 1 516 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 16-BIT MICROPROCESSOR $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 517 518 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD68000/HD68HC000--MPU (Micro Processing Unit) -HD68000The HD68000 is the first in a family of advanced micropro- cessors from Hitachi. Utilizing VLSI technology, the HD68000 is a fully-implemented 16-bit microprocessor with 32-bit registers, a rich basic instruction set, and versatile addressing modes. The HD68000 possesses an asynchronous bus structure with a 24-bit address bus and a 16-bit data bus. FEATURES · 32-Bit Data and Address Registers · 16 Megabyte Direct Addressing Range · 56 Powerful Instruction Types · Operations of Five Main Data Types · Memory Mapped, 1/0 · 14 Addressing Modes H068000-8, HD68000·10, HD68000-12 HD68HC000·8, HD68HC000-10, HD68HC000·12 IDC-64) HD68000Y-8, H068000Y-10, HD68000Y·12 HD68HCOOOY·8, H068HCOOOY·10, HD68HCOOOY-12 - HD68HCOOO - The HD68HCOOO is a 16-bit microprocessor of HD68000 family, which is exactly compatible with the conventional HD68000. The HD68HCOOO is a complete CMOS device and the power dissipation is extremely low. FEATURES · Instruction Compatible with NMOS HD68000 · Pin Compatible with NMOS HD68000 · AC Timing Compatible with NMOS HD68000 · Low Power Dis5ipation !Ice typ = 20 mA, Ice max =3!; mA at f = 12.5 MHz) HD68000P-8 HD68HCOOOP-8, H068HCOOOP·10, HD68HCOOOP·12 HD68000PS-8 HD68HCOOOPS·8, HD68HCOOOPS-10, HD68HCOOOPS-12 (DP-648) HOSSOOOCP-8 H068HCOOOCP-8, HD68HCOOOCP-10, HD68HCOOOCP-12 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 519 HD68000/HD68HCOOO-------------------------- · TYPE OF PRODUCTS Type No. HD68000-8 HD68000·10 HD68000·12 HD68000Y-8 HD68000Y·10 HD68000Y-12 HD680001la HD6BOOOPS8 HD68000Cf!B HD68HC000-8 HD68HC000·10 HD68HC000-12 HD68HC000¥8 HD68HCOOOV-10 HD68HCOOOV-12 HD68HCOOOP8 HD68HCOOOP-10 HD68HCOOOP-12 HD68HCOOOPS8 HD68HCOOOPS'I 0 H D68HCOOOP912 HD68HCOOOCP8 H D68HCOOOCP-10 H D68HCOOOCP-12 Process NMOS CMOS Clock Frequency (MHz) 8.0 10.0 12.5 8.0 10.0 12.5 8.0 8.0 8.0 8.0 10.0 12.5 8.0 10.0 12.5 8.0 10.0 12.5 8.0 10.0 12.5 8.0 10.0 12.5 Pack,ge DC-64 PGA-68 DP-64 DP-645 CP-68 DC-64 PGA-68 DP-64 DP-645 CP-68 (Note) HD68000 refers to the NMOS version 68000. and HD68HCOOO refers to the CMOS version 68000. 68000 stands for NMOS and CMOS version. 520 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · PIN ARRANGEMENT · DC-64, DP-64, DP·64S Os De D1 1 De Og 010 BR 1 Vee 1 CLK 1 Vss 1 HALT 1 RES 1 VMA1 E IPL2 2 IPL1 IPLo 5 FC2 FC1 FCo Al A2 A,1 Vee A20 Ale A11 Ale A1s A14 1 A13 A12 (Top View) · PGA-68 1 PIN @ D (Top View) · (Bottom View) Pin No. 1 2 3 · 6 8 7 · 8 10 11 12 13 1· 16 18 17 Function N/C l)TACK illAei( ill eLK HALT iiiDi E SERR N/C Fe, FC. A, A, ""A'', Pin No. 18 19 20 21 22 23 20 25 28 27 28 21 30 31 32 33 3" ,..Function N/C A,. A,. An A., A,. Au An D., D., Doo D, D, D, D, D, Pin No. 35 36 37 38 38 00 ·1 .02 ·3 06 ..·016 50 61 Function D, AS LDS BG Vee v.. RES VPA IPL2 IPLo Fe, N/C A, A, A, Aoo Au Pin No. 62 53 54 55 66 67 66 68 80 61 .62 63 66 86 67 86 Function A., A., A,. Vee v,. A,, D.. Du D, D, D, Do UDS R/W IPL1 A., D., · CP-68 I~ ll!l /1S .,g.;: !VJ 0 - f'l "1 .,. .,, ...... ., OI j::l a:..J~lc(OCOCCOOCCOuuu (Top View) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 521 ·ABSOLUTE MAXIMUM RATINGS Item !Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Symbol Vee * Vin * Topr T11g HD68000 Value -0.3-+7.0 -0.3-+7.0 0-+10 -55-+150 HD68HCOOO Value -0.3-+6.5 -0.3-+6.5 0-+10 -55 -+150 Unit v v "c "c *With respect to Vss (SYSTEM GND) (NOTE) Pt!rman&nt LSI damage may occur if maxim~m ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI. Since the HD68HeOOO is a e-MOS device, users are expected to be cautious on "latch-up" problem caused by voltage frecturetions. · RECOMMENDED OPERATING CONDITIONS Item Supply Voltage CLK Input Voltage Other Inputs All Inputs Operating Temperature * With respect to Vss (SYSTEM GN 0) Symbol Vee * VIH * V1L * Topr min 4.75 2.0 -0.3 0 HD68000 typ 5.0 - 25 max 5.25 Vee 0.8 70 HD68HCOOO min typ max 4.75 5.0 5.25 2.8 2.0 -0.3 - Vee - Vee - 0.8 0 25 70 Unit v v v oc 522 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ELECTRICAL CHARACTERISTICS · DC CHARACTERISTICS (Vee= 5V ± 5%, Vss = OV, Ta= O- +70°C, Fig. 1, unless otherwise noted.) Item Symbol Test Condition HD68000 HD68HCOOO min max min max CLK Input "High" Voltage Other Inputs Input "Low" Voltage Input Leakage Current ~~R, !!§_ACK, BR, DTACK, IPL0 - IPL2, VPA, CLK HALT, RES Three-State (Off State) Input Current AS, A 1- A 23, Do - Dis. FC0 - FC2, LOS, R/W, UDS, VMA AS, A 1 - A2L..!!.G, ~~, Output "High" Voltage FCo - FC2, LOS, R W, UDS, VMA,E E* HALT A1-A23, BG, FCo - FC2 Output "Low" Voltage RES AS, Do - 0 15 · LOS, R/W, E, UDS, VMA V1H V1L lin ITSI VoH VoL CERAMIC PACKAGE Power Dissipation Po PLASTIC PACKAGE Current Dissipation Capacitance (Package Type Dependent) *With external pull up resistor of 1.1 kn. **Without load. lo** C;n @5.25V 2.0 Vss-0.3 - 2.8 Vee 2.0 0.8 Vss-0.3 2.5 - 20 - Vee ~ 0.8 2.5 20 @l 2.4V/0.4V - 20 - 20 loH = -400µ.'°1 2.4 - Vee-015 - Vee-OJ5 - loL-1.6mA - 0.5 - 0.5 loL =3.2 mA - 0.5 - 0.5 loL=5.0 mA - 0.5 - 0.5 loL=5.3 mA - 0.5 - 0.5 f= 6MHz f = 8 MHz - 1.5 f = 10 MHz - f = 12.5 MHz 1.75 - - f = 8 MHz, Vee= 5V, - 0.9 Ta= ;!5°C f = 8 MHz - - - 25 f= 10 MHz - - - 30 - f = 12.5 MHz - - 35 Vin =OV, Ta= 25°C, f = 1 MHz - - 20.0 20.0 Unit v v µA µA v v w mA pF 1 . 00 RL-j_ ~130pF ~+SV 2.9kn HATT l70pF Test Point +5 v 1S2074(£f. or Equivalent R · = 740n RL 152074@ ()r EqfJivalent CL = 130 pf Uncludes all Parasitics) RL = 6.0 kn for AS, A, -A,,, irn,£0,.. E, Fe, -Fe,, LOS, R/W, ~. VMA *R = 1.22 kn for A, -A,,. iiG, Fe, -Fe, Figure 1 Test Loads @>HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 523 ov. o- · AC CHARACTERISTICS (Vee - 5V ± 5%, Vss = Ta= +70°C, unless otherwise noted.) CLOCK TIMING Item Symbol Test Condition 8 MHz 10 MHz 12.5 MHz min max min max min max Frequency of Operation f Cycle Time tcyc tcL Clock Pulse Width tcH ter Rise and Fall Times tc1 Fig. 2 4.0 8.0 4.0 10.0 4.0 12.5 125 250 100 250 80 250 55 125 45 125 35 125 55 125 - 10 - 10 45 125 - 10 - 10 35 125 - 5 - 5 Unit MHz ns ns ns ns ns i.--------tcyc-------<~ (NOTE) Timing measurements ere referenced to and from a low voltage of 0.8 volt and high a voltage of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts. Figure 2 Clock Input Timing 524 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 READ AND WRITE CYCLES Num. 1 2 3 4 5 6 6A 7 8 91 112 11A2 12 1 132 142 14A2 152 16 172 1e1 201 20A6 212 21A2 222 23 252 262 275 282 29 30 312,5 32 33 34 35 Item Clock Period Clock Width Low Clock Width High Clock Fall Time Clock Rise Time Clock Low to Address Valid Clock High to FC Valid Clock High to Address, Data Bus High Impedance (Maximum) Clock High to Address, FC Invalid (Minimum) Clock H.!B_h to AS, OS Low Address Valid to AS, OS Low (Read)/ AS Low (Write) FC Valid to AS, OS Low (Read)/ AS Low (Write) Clock Low to AS, OS High AS, OS High to Address/FC Invalid AS, OS Width Low (Read)/AS Low (Write) i5S" Width Low (Write) AS, OS Width High Clock High to Control Bus High Impedance AS, OS High to R/W High (Read) Clock High to R/W High Clock High to R/W Low (Write) AS Low to R/W Valid (Write) Address Valid to R/W Low (Write) FC Valid to R/W Low (Write) R/W Low to OS Low (Write) Clock Low to Data Out Valid (Write) AS, OS High to Data Out Invalid (Write) Data Out Valid to OS Low (Write) Data In to Clock Low (Setup Time on Read) AS, OS High to DTACK High AS, OS High to Data In Invalid (Hold Time on Read) AS, OS High to BERR High DTACK Low to Data In (Setup Time) HALT and RESET Input Transition Time Clock High to BG Low Clock High to BG High BR Low to BG Low Test BMHz 10 MHz 12.5 MHz Symbol Condition min max min max min max Unit tcyc 125 250 100 250 BO 250 ns tcL 55 125 45 125 35 125 ns tcH tct tcr tCLAV tcHFCV 55 125 45 125 35 125 ns - 10 - 10 - 5 ns - - 10 - 10 5 ns - - - 70 60 55· ns - 70 - 60 - 55 ns tcHADZ tcHAFI tcHSL - - - BO 70 60 ns 0 - 0 - 0 - ns 0 60 0 55 0 55 ns tAVSL - - 30 - 20 0 ns tFCVSL - 60 50 - 40 - ns - - tcLSH Fig. 3, 70 - 55 50 ns tsHAFI Fig.4 - - 30 - 20 10 ns tsL - 240 - 195 160 - ns tosL - 115 - 95 BO - ns tsH - - 150 - 105 65 ns tcHcz - - BO 70 - 60 ns tsHRH - - 40 20 10 - ns tcHRH tcHRL tASRV tAVRL tFCVRL 'tRLSL tcLDO tsHDOI toosL toJC_L 0 70 0 60 0 60 ns - - 70 60 - 60 ns - - 20 20 - 20 ns - - 20 - 0 0 ns - 60 - 50 - 30 ns - BO - 50 - 30 ns - - 70 - 55 55 ns - - 30 - 20 15 ns - - 30 20 15 - ns - - 15 10 10 - ns tsHDAH 0 245 0 190 0 150 ns tsHOll tsHBEH toALDI tRHr, f tcHGL tcHGH taRLGL - 0 - 0 - 0 ns - 0 - 0 - 0 ns - - - 90 65 50 ns 0 200 0 200 0 200 ns - - - 70 60 50 ns - - 70 - 60 50 ns 90 BO 70 1.5 ns +3.5 1.5 ns +3.5 1.5 ns +3.5 Clk. Per. · 57 for HD68HCOOO @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 525 READ AND WRITE CYCLES (CONTINUED) Num. 367 37 37A8 38 39 40 41 42 43 44 45 46 47 5 483 499 50 51 53 54 55 564 57 5B7 Item BR High to BG High Test Symbol Condition teRHGH 8 MHz min max 1.5 90ns +3.5 10MHz min max 1.5 80ns +3.5 12.5 MHz Unit min max 1.5 70ns +3.5 Clk.Per. BGACK Low to BG High taALGH 9Jns 80ns 70ns 1.5 +3.5 1.5 +3.5 1.5 +3.5 Clk.Per. BGACK Low to BR High foALBRH. 1.5 1.5 1.5 20 Clocks 20 Clocks 20 Clocks ns BG Low to Control, Address, Data Bus High Impedance (AS High) taLz BG Width High Clock Low to VMA Low taH tcLVML Clock Low to E Transition tcLET E Output Rise and Fall Time ter. t VMA Low to E High tvMLEH AS, DS High to VPA High tsHVPH E Low to Control, Address Bus Invalid (Address Hold Time) BGACK Width Low Asynchronous Input Setup Time teLCAI ta AL tASI BERR Low to DTACK Low AS, DS High to E Low teELDAL tsHEL E Width High teH E Width Low teL Clock High to Data Out Invalid tcHDOI E Low to Data Out Invalid tELDOI Fig. 3, Fig. 4 - 80 - 1.5 - 1.5 - 70 - - 70 - - 25 200 - 150 0 120 0 30 - 10 1.5 - 1.5 20 - 20 20 - 20 -70 70 -55 450 - 350 700 - 550 0-0 30 - 20 70 - 1.5 70 55 25 - 90 90 0 - 10 - 1.5 - 20 - 20 55 -45 - 280 - 440 -0 - 15 60 ns - Clk.Per. 70 ns 45 ns 25 ns - ns 70 ns - ns - Clk.Per. - ns - ns 45 ns - ns - ns - ns - ns R/W to Data Bus Driven HALT/RESET Pulse Width BGACK High to Control Bus Driven BG High to Control Bus Driven tRLDBD tHRPW taABD ta HBO 30 - 10 - 1.5 - 1.5 - 20 10 1.5 1.5 - 10 - ns 10 - Clk.Per. 1.5 - Clk.Per. 1.5 - Clk.Per. NOTES: 1. For a loading capacitimce of less than or equal to 50 picoferads, substr8ct 5 nanoseconds {rom the value given in the maximum columns. 2. Actmll value depends on clock period. 3. If #47 is satisfied for both DTACK and B'ERR, #48 may be 0 nonoseconds. 4. For power up, the MPU must be held in RES state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the system. 5. If the asynchronous setup time {fl47) requirements are satisfied, the DTACK low-to-data setup time (#31) requirement can be ignored. The data must only satisfy the date-in clock-low setup time (# 27) for the following cycle. 6. When AS and R/W are equally loaded (120%), subtract 10 nanoseconds from the values given in these columns. 7. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR' before asserting~- 8. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. 9. The falling edge of S6 triggers both the negation of the strobes (As and xDS) and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolut~ maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock. 526 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation. so 51 52 53 54 55 56 Data In BEAR/BR (Note 2) ---~ Asynchronous - - - - - - - - - - - - · _ Input (Note 1) ---------- NOTES: 1. Setup time for the synchronous inputs BGACK, IPLo_2 and VPA guarantees their recognition at the next falling edge of the clock. 2. BR need fall at this time only in order to insure being recognized at the end of this bus cycle. 3. Timing measurements are referenced to and from l!I low voltage of 0.8 volt and a high voltage 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise·or fall will be linear between 0.8 volt and 2.0 volts. Figure 3. Read Cycle Timing @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 527 These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation. CLK FC0-FC2 A1-~ @ A5 LDS/UDS R/W Data Out BERR/BR (Note 2) ------------'? AsynchrIonnpouutss _A (Note 1) "---------- NOTES: I 1. Timing measurements are referenced to and from a ICM voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. ) The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between O.B volt and 2.0 volts. 2. Because of loading variations, R/W may be valid after AR even though both are initiated by the rising edge of 82 (Specification 20A). Figure 4. Write Cycle Timing 528 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · HMCS6800 TIMING Num. 12 18 20 23 27 29 40 41 42 43 44 45 47 491 50 51 54 Item Clock Low to AS, DS High Clock High to R/W High Clock High to R/W Low (Write) Clock Low to Data Out Valid (Write) Data In to Clock Low (Setup Time on Read) AS, DS High to Data In Invalid (Hold Time on Read) Clock Low to VMA Low Clock Low to E Transition E Output Rise and Fall Time VJilA Low to E High AS, DS High to VPA High E Low to Control, Address Bus Invalid (Address Hold Time) Asynchronous Input Setup Time AS, DS High to E Low E Width High E Width Low E Low to Data Out Invalid Test 6 MHz 8MHz 10 MHz 12.5 MHz Symbol Unit Condition min max min max min max min max tcLSH tcHAH tcHAL tcLDO tocL - 80 - 70 - 55 - 50 ns 0 80 0 70 0 60 0 60 ns - 80 - 70 - 60 ·- 60 ns - 80 - 70 - 55 -- 55 ns 25 - 15 - 10 - 10 - ns tsHDll Fig. 5, 0 - 0 - 0 - 0 - ns tcLVML Fig. 6 - 80 - 70 - 70 - 70 ns tcLET - 35 - 70 - 55 - 45 ns !Er f - 25 - 25 - 25 - 25 ns tvMLEH 240 - 200 - 150 - 90 - ns fsHVPH tELCAI 0 160 0 120 0 90 0 70 ns 35 - 30 - 10 - 10 - ns tASI fsHEL !EH !EL tELDDI 25 - 20 - 20 - 20 - ns -80 - -70 70 -55 55 -45 45 ns 600 - 450 - 350 - 280 - ns 900 - 700 - 550 - 440 - ns 40 - 30 - 20 - 15 - ns NOTE: 1. The falling edge of $6 triggers both the negation of the strobes (AS and x5S} and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute meximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock. CLK A1 -A,,3 A5 SO S1 52 53 54 w w w w w w w w w w w w SS S6 57 SO @ R/W E @ VPA VMA Data Out @ Data In NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the best case possibly attainable. Figure 5. HD6800 Timing-Best Case @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 529 ~~~~~wwwwwwwwwwwwwwwwwwwwwwwwwwww~~m~ NOTE: This timing diagram is included for those who wish to design their own circuit to generate\IMA. It shows the worst case possibly attainable. Figure 6. HD6800 Timing-Worst Case BUS ARBITRATION Nurn. 1 16 33 34 35 361 37 37A2 3B 39 46 47 57 581 Item Clock High to Address, Data Bus High Impedance Clock High to Control Bus High Impedance Clock High to BG Low Clock High to BG High BR Low to BG Low BR High to BG High BGACK Low to BG High BGACK Low to BR High BG Low to Control, Address, Data Bus High Impedance (AS High) BG Width High BGACK Width Low Asynchronous Input Setup Time BGACK High to Control Bus Driven BG High to Control Bus Driven Test 8MHz 10 MHz 12.5 MHz Symbol Unit Condition min max min max min max tcHADZ tcHCZ tcHGL tcHGH tsRLGL teRHGH lGALGH Fig. 7 Fig. 9 lGALBRH tGLZ tGH lGAL ~SI lGABD lGHBD - 80 - 70 - 60 ns - 80 - 70 - 60 ns - 70 - 60 - 50 ns - 70 - 60 - 50 ns 1.5 90ns +3.5 1.5 80ns +3.5 1.5 70ns +3.5 Clk.Per. 1.5 90ns +3.5 1.5 80ns +3.5 1.5 70ns +3.6 Clk.Per. 1.5 90ns +3.5 1.5 80ns +3.5 1.5 70ns +3.5 Clk.Per. 20 1.5 Clocks 20 1.5 jclock· 20 1.5 Clock· ns - BO - 70 - 60 ns 1.5 - 1.5 20 - 1.5 - 1.5 - 1.5 - 1.5 - 20 - 1.5 1.5 - 1.5 - Ok.Per. 1.5 - Clk.Per. 20 - ns 1.5 - Clk.Per. 1.5 - Clk.Per. NOTES: BGACK. 1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting 2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded. BG may be reasserted. 530 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Figures 7, 8, and 9 depict the three bus arbitration cases that can arise. Figure 7 shows the timing where AS is negated when the processor asserts B"G (Idle Bus Case). Figure 8 shows the timing where AS is asserted when the processor asserts BG (Active Bus Case). Figure 9 shows the timing where more than one bus master are requesting the bus. Refer to Bus Arbitration for a complete discussion of bus arbitration. The waveforms shown in Figures 7, 8, and 9 should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation. CLK BR EiG BGACK @ @ A5 LDS/UDS VMA R/W FC0 -FC2 A1-A23 Do-015 Figure 7. Bus Arbitration Timing Diagram - Idle Bus Case @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 531 Figure B. Bus Arbitration Timing Diagram_ - Active Bus Case @ I-- Rfii FCo-FC2 @ 1-- Jr-- I,-- Ir-- -+ I,-- I,-- 532 Figure 9. Bus Arbitration Timing Diagram - Multiple Bus Requests .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · INTRODUCTION As shown in the programming model, the 68000 offers seven- teen 32-bit registers in addition to the 32-bit program counter and a 16-bit status register. The first eight registers (DO - 07) are used as data registers for byte (8-bit), word (16-bit), and long word (32-bit) data operations. The second set of seven registers (AO - A6) and the system stack pointer may be used as software stack pointers and base address registers. In addition, these registers may be used for word and long word address operations. All 17 registers may be used as index registers. The status register contains the interrupt mask (eight levels available) as well as the condition codes; extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional status bits indicate that the processor is in a trace (T) mode and/or in a supervisor (S) state. Status Register System Byte ~~~~/\~~~----- User Byte (Condition Code Register) ~~~~~/\.~~~~~ 3 o\ v c Interrupt Mask Unused, read as zero. Zero Overflow Carry · DATA TYPES AND ADDRESSING MODES Five basic data types are supported. These data types are: (1) Bits (2) BCD Digits (4 bits) (3) Bytes (8 bits) (4) Word (16 bits) (5) Long Words (32 bits) In addition, operations on other data types such as memory address, status word data, etc., are provided for in the instruction set. The 14 addressing modes, shown in Table 1, includes six basic types: ( 1) Register Direct (2) Register Indirect (3) Absolute (4) Immediate (5) Program Counter Relative (6) Implied Included in the register indirect addressing modes is the capability to do postincrementing, predecrementing, offsetting and indexing. Program counter relative mode can also be modified via indexing and offsetting. Programming Model 31 1615 8 7 0 DO 01 02 03 Eight Data 04 Registers 05 06 07 1615 0 AO A1 A2 Seven A3 Address Registers A4 AS AG r------u~Sta-;k'Poin;';r-- -----~A 7T~o Stack Li!.---- -- --1-1 S-2u3p-er-vis-or-S-tac-k -Po-int-er------~0 I I L · - - - - - · - - - - - - 15- - - -8-7- - - - "0 System Byte : User Byte Pointers Program Counter Status Register Table 1 Addressing Modes Mode Register Direct Addressing Data Regilter Diredt Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with Offset Relative with Index and Offset Register Indirect Addressing Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Indexed Register Indirect with Offset Immediate Data Addressing Immediate Quick Immediate Implied Addressing Implied Register (NOTES) EA = Effective Address An = Address Register Dn = Data Register Xn = Address or Data Register used 11s Index Register SR =Status Register PC = Program Counter I I = Contents of d 8 = Eight-bit Offset (displacement) Generation EA= Dn EA= An EA= (Next Word) EA = (Next Two Words) EA= (PC)+ d" EA = (PC) + (Xnl + d, EA= (An) EA= IANI, An +-An+ N An +-An - N, EA= (An) EA= (An)+ d" EA= (An)+ (Xnl + d, DATA= Next Word(s) Inherent Data EA= SR, USP, SP, PC d 16 = Sixteen-bit Offset (displacement) N = 1 for Byte, 2 for Words and 4 for Long Words. If An is the stack pointer and the operand size is byte, N=2 to keep the stack pointer on a word boundary. ,.._ =Replaces @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 533 · INSTRUCTION SET OVERVIEW The 68000 instruction set is shown in Table 2. Some addi- tional instructions are variations, or subsets, of these and they appear in Table 3. Special emphasis has been given to the instruction set's support of structured high-level languages to facilitate ease of programming. Each instruction, with few exceptions, operates 'on bytes, words, and long words and most instructions can use any of the 14 addressing modes. Combining instruction types, data types, and addressing modes, over 1000 useful instructions are provided. These instructions include signed and unsigned multiply and divide, "quick" arithmetic operations, BCD arithmetic and expanded operations (through traps). Table 2 Instruction Set Mnemonic ABCD ADD AND ASL ASR Bee BCHG BCLR BRA BSET BSR BTST CHK CLR CMP DBcc DIVS DIVU Description Add Decimal with Extend Add Logical And Arithmetic Shift Left Arithmetic Shift Right Branch Conditionally Bit Test and Chango Bit Test and Clear Branch Always Bit Test and.Sot Branch to Subroutine BitTest Check Register Agoinat Bounds Clear Operand Compare Test Condition. Decrement and Branch Signed Divide Unsigned Divide Mnemonic EOR EXG EXT JMP JSR LEA LINK LSL LSR MOVE MOVEM MOVEP MULS MULU NBCD NEG NOP NOT OR Description Exclusive Or Exchange Registers Sign Extend Jump Jurrip to Subrou~ine Load Effective Address Link Stack Logical Shift Left Logical Shift Right Move Move Multiple Registers Move Peripheral Data Signed Multiply Unsigned Multiply Negete Decimal with Extend Negate No Operation One's Complement Logical Or Mnemonic PEA RESET .ROL ROR ROXL ROXR RTE RTR RTS SBCD Sec STOP SUB SWAP TAS TRAP TRAPV TST UNLK Description Push Effective Address Resat External Devices Rotate Left without Extend Rotate Right without Extend Rotate Left with Extend Rotate Right with Extend Return from Exception Return and Restore Return f.rom Subroutine Subtract Decimal with Extend Set Conditional StoP Subtract Swap Data Register Halves Test and Sot Operand Trap Trap on Overflow Test Unlink Instruction Type ADD AND CMP EOR Variation ADD ADDA ADDO ADDI ADDX AND ANDI ANDI to CCR ANDI to SR CMP CMPA CMPM CMPI EOR EORI EORI to CCR EORI to SR Table 3 Variations of Instruction Types Description Add Add Address Add Quick Add Immediate Add with Extend Logical And And Immediate And Immediate to Condition Codes And Immediate to Status Register Compare Compare Address Compare Memory Compare Immediate Exclusive Or Exclusive Or Immediate Exclusive Or Immediate to Condition Codes Exclusive Or Immediate to Status Register I n~truction Type MOVE NEG OR SUB Variation Description MOVE MOVE A MOVEQ MOVE from SR MOVE to SR MOVE to CCR MOVE USP NEG NEGX OR ORI ORI to CCR ORI to SR Move Move Address Move Quick Move from Status Register Move to Status Register Move to Condition Codes Move User Steck Pointer Negate Negate with Extend Logical Or Or Immediate Or Immediate to Condition Codes Or Immediate to Status Register SUB SUBA SUBI SUBQ SUBX Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend 534 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · REGISTER DESCRIPTION AND DATA ORGANIZATION The following paragraphs describe the registers and data organization of the 68000. · OPERAND SIZE Operand sizes are defined as follows: a byte equals 8 bits, a word equals 16 bits, and a long word equals 32 bits. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. hnplict instructions support some subset of all three sizes. · DATA ORGANIZATION IN REGISTERS The eight data registers support data operands of I, 8, 16, or 32 bits. The seven address· registers together with the active stack pointer support address operands of 32 bits. DATA REGISTERS Each data register is 32 bits wide. Byte operands occupy the low order 8 bits. word operands the low order 16 bits, and long word operands the entire 32 bits. The least significant bit is addressed as bit zero: the most significant bit is addressed as bit 31. When a data register is used as either a source or destination operand, only the appropriate low-order portion is changed: the remaining high-order portion is neither used nor changed. ADDRESS REGISTERS Each address register and the stack pointer is 32 bits wide and holds a full 32 bit address. Address registers do not support byte sized operands. Therefore. when an address register is used as a source operand. either the low order word or the entire lung word operand is used depending upon the operation size. When an address register is used as the destination operand, the entire register is affected regardless of the operation size. If the operation size is word, any other operands are sign extended to 32 bits before the operation is performed. · DATA ORGANIZATION IN MEMORY Bytes are individually addressable with the high order byte having an even address the same as the word. as shown in Figure 10. The low order byte has an odd address that is one count higher than the word address. Instructions and multibyte data are accessed only on word (even byte) boundaries. If a long word datum is located at address n (n even), then the second word of that datum is located at address n + 2. The data types supported by the 68000 are: bit data, integer data of 8, 16, or 32 bits, 32-bit addresses and binary coded decimal data. Each of these data types is put in memory, as shown in Figure 11. The numbers indicate the order in which the data would be accessed from the processor. Byte FFFFFE Byte FFFFFF Figure 10 Word Organization in Memory @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 535 HD68000/HD68HCOOO Bit Data 1 Byte= B Bits 6 54 32 0 Integer Data 1 Byte = B Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 n IMSB n+2 ByteO Byte 2 LSBI Byte 1 Byte3 0 In+1 n+3 1 Word= 16 Bits 15 14 13 12 11 10 9 B 6 5432 ~l' WordO Word 1 n+4 Word:Z 0 ~1 n+l n+3 n+5 1 Long Word = 32 Bits 15 14 13 12 11 10 9 B 7 6 5 4 3 2 0 MSB ~ -- Long Word o---- - - - - - - ---- High Order - - - - - - - - - - - - - ---1 n+1 n+2 Low Order LSB n+3 n+4 n+5 ---LongWord 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1 n+6 n+7 n+B n+9 - - ·Long Word 2-- - - - - - - - - - - - - - - - - - - - - - - - - - - - -1 n+10 n+ll Addresses 1 Address = 32 Bits 15 14 13 12 11 10 9 B 7 6 5 4 3 2 0 MSB High Order n+1 t---AddressO-------- --------- --- - -------- n+2 Low Order LSB n+3 n+4 n+5 t-- - Address 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - n+6 n+7 n+B n+10 --·Address2. - - "'- - - - - - - - - - - - - - - - - - - - - - - - - - - MSB =Most Significant Bit LSB = Least Significant Bit Decimal Data 2 Binary Coded Oecimal Oigits =1 Byte 15 14 13 12 11 10 9 B 7 6 5 4 n MSO BCDO BCOl LSD BC02 n+2 BCD4 BCD5 BCD6 3 2 BCD3 BCD7 MSD = Most Significant Digit LSD = Least Significant Digit Figure 11 Data Organization in Memory n+9 n+11 n+1 n+3 536 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · ADDRESSING Instructions for the 68000 contain two kinds of information: the type of function to be performed, and the location of the operand(s) on which to perform that function. The methods used to locate (address) the operand(s) are explained in the following paragraphs. Instructions specify an operand location in one of three ways: Register Specification - the number of the register is given in the register field of the instruction. Effective Address - use of the different effective address modes. Implicit Reference - the definition of certain instructions implies the use of specific registers. · INSTRUCTION FORMAT Instructions are from one to five words in length, as shown in Figure 12. The length of the instruction and the operation to be performed is specified by the first word of the instruction which is called the operation word. The remaining words further specify the operands. These words are either immediate operands or extensions to the effective address mode specified in the operation word. · PROGRAM/DATA REFERENCES The 68000 separates memory references into two classes: program references, and data references. Program references, as .the name implies, are references to that section of memory that contains the program being executed. Data references refer to that section of memory that contains data. Operand reads are from the data space except in the case of the program counter relative addressing mode. All operand writes are to the data space. · REGISTER SPECIFICATION The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used. · EFFECTIVE ADDRESS Most instructions specify the location of an operand by using the effective address field in the operation word. For example, Figure 13 shows the general format ofthe single effective address instruction· operation word. The effective address is composed of two 3-bit fields: the mode field, and the register field. The value in the mode field selects the different address modes. The register field contains the number of a register. The effective· address field may require additional information to fully specify the operand. This additional information, called the effective address extension, is contained in the following word or words and is considered part of the instruction, as shown in Figure 12. The effective address modes are grouped into three categories: register direct, memory addressing, and special . 15_ .1.4 13 12 11 10 ...JI.. _j_ 7 ..2. 5 4 3 2 1 0 Operation Word (First Word Specifies Operation and Modes) Immediate Operand (If Any, One or Two Words) Source Effective Address Extension (If Any, One or Two Words) Destination Effective Address Extension !!! A~One or Two Words) Figure 12 Instruction Format 15 14 13 12 11 10 9 8 7 6 x xxx x xx x x x 54 32 0 Effective Address Mode Register Figure 13 Single-Effective-Address Instruction Operation Word General Format @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 537 REGISTER DIRECT MODES These effective addressing modes sj>ecify that the operand is in one of the 16 multifunction registers. Data Register Direct The operand is in the data register specified by the effective address register field. MPU ~ MEMORY jOOOOABCDI DO $001FOO MOVE DO, $1 FOO OWL OWL+2 31CO 1FOO COMMENTS .·EA= On ·Machine Level Coding MOVE DO, $1 FOO 0011 ~ Word 0001 1100 0000 I l k a Absolute Short Data Register Direct Address Register Direct The operand is in the address register specified by the effec- tive address register field. MPU MEMORY COMMENTS ·EA= An l00001234I A4 MOVE A4, $201000 OWL 33CC 1--------1 OWL +2 0020 1--------1 OWL+4 1000 1--------1 · Machine Level Coding MOVE A4, $201000 ~ I T I 1 0 0 Word Absolute Long Address Register Direct ~HITACHI 538 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MPU ~ MEMORY 1000012341 A4 MOVE $201000, A4 OWL OWL+2 OWL+4 3879 0020 1000 HD68000/HD68HCOOO COMMENTS ·EA= An · Address Register Sign Extended · Machine Level Coding I l l - MOVE $201000, A4 0011 Move Word 1000 0111 1001 _L Absolute Long Reg#4 Address Register Direct MEMORY ADDRESS MODES These effective addressing modes specify that the operand is in memory and provide the specific address of the operand. Address Register Indirect The address of the operand is in the address register specified by the register field. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions. MPU MEMORY COMMENTS ·EA= IAnl 1000010001 AO MOVE IAOI. DO · Machine Level Coding MOVE IAOJ, 00 ~ Word Jioooo.\oaT--Q.~ .1:1 Register Direct Reg #0 ARI (Addre55 Register Indirect) @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 539 Address Register Indirect With Postincrement The address of the operand is in the address register specified by the register field. After the operand address is used, it is incremented by one, two, or four depending upon whether the size of the operand is byte, word, or long word. If the address register is the stack pointer and the operand size is byte, the address is incremented by two rather than one to keep the stack pointer on a word boundary. The reference is classified as a data reference. MPU EXAMPLE MEMORY L00000100J A4 l [0000010:1] $100 $2000 MOVE IA4) +,$2000 OWL OWL+2 31DC 2000 COMMENTS ·EA= (An); An+ M-An Where An~ Address Register M _..1,2,or4 (Depending Whether Byte, wo·rd, or Long Word) · Machine level Coding MOVE IA4) +, $2000 0011 0001 1101 1100 IMoveII::~ Word Absolute Short AA I with Increment Address Register Indirect With Predecrement The address of the operand is in the address register specified by the register field. Before the operand address is used, it is decremented by one, two, or four depending upon whether the operand size is byte, word, or long word. If the address register is the stack pointer and the operand size is byte, the address is decremented by two rather than one to keep the stack pointer on a word boundary. The reference is classified as a data reference. MPU EXAMPLE MEMORY 00000100 A3 ooooQQE]j $00FE $0100 $4000 MOVE - IA3),$4000 OWL OWL+2 31E3 4000 COMMENTS ·An - M-An; EA= (An) Where An .....,Address Register M -1.2,or4 (Depending Whether Byte, Word, or Long Word) · Machine Level Coding MOVE - (A3), $4000 0011 0001 1110 0011 II~l Move with Word Pred ic· Absolute rement Short Reg #3 540 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Address Register Indirect With Displacement This address mode requires one word of extension. The ad· dress of the operand is the sum of the address in the address register and the sign-extended 16-bit displacement integer in the extension word. The reference is classified as ·a data refer· ence with the exception of the jump to subroutine instructions. MPU I00001000 IAO MEMORY COMMENTS ·EA= An+ d1 6 Where An ---Pointer Register d 16 ---l6-8it Displacement · d1 6 Displacement is Sign Extended · Machine Level Coding :r =r=--r_:r_ MOVE $100(A0),$3000 0001 1110 1000 Absolute Short Reg #0 Move ARI Word with Displacement MOVE $100(A0),$3000 ADDRESS CALCULATION: AO = 00001000 d,. = 00000100 00001100 OWL 31E8 ~-------i OWL + 2 0100 OWL + 4 ~-------i 3000 >--------< Address Register Indirect With Index This address mode requires one word of extension. The address of the operand is the sum of the address in the address register, the sign-extended displacement integer in the low order eight bits of the extension word, and the contents of the index register. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions. MPU loooo2eDcl DO I00002000 IAO MEMORY MOVE $04(AO, DO), $1000 ADDRESS CALCULATION: AO = 00002000 DO= 00002BDC d = 00000004 00004BEO OWL 31FO OWL + 2 ~-------i 0004 ~-------i OWL +4 1000 ~-------i COMMENTS ·EA= An+ Ax+ d~ Where An --- Pointer Register Rx --- Designated Index Register, (Either Address Register or Data Register) d~ - - - 8-Bit Displacement · Ax & d 1 are Sign Extended · Rx may be Word or Long Word Long Word may be Designated with Rx.L · Machine Level Coding MOVE $04(A0, DO), $1000 Il: __r- 0011 0001 1111 0000 Move Absolute #0 Word Short ARI with Index ct.[wlral 0000 0000 0000 0100 ~ Reg #0 Constant Zeros @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 541 SPECIAL ADDRESS MODE The special address modes use the effective address register field to specify the special addressing mode instead of a register number. Absolute Short Addren This address mode requires one word of extension. The ad· dress of the operand is the extension word. The 16-bit address is sign extended before it is used. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions. MPU MEMORY COMMENTS · EA= (Next Word) · 16-Bit Word is Sign Extended $2000 FFFF -+0000 $20021-=;..;__;_;,_;-l · Machine Level Coding NOT.L $2000 0100 0110 1011 1000 t . ti. Jolute Not Instruction Short NOT.L $2000 OWL 4688 OWL+2 2000 ~------1 MPU EXAMPLE MEMORY $1000 $2000 MOVE $1000, $2000 OWL OWL+2 OWL+4 31F8 1000 2000 COMMENTS · EA = (Next Word) · 16-Bit Word is Sign Extended · Machine Level Coing MOVE $1000, $2000 0011 0001 1111 1000 r~ ~ Word Short Absolute Short 542 $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Absolute Long Address This address mode requires two words of extension. The address of the operand is developed by the concatenation of the extension words. The high-order part of the address is the first extension word; the low-order part of the address is the second extension word. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions. MPU MEMORY COMMENTS · EA= (Next Two Words) · Machine Level Coding NEG $014000 0100 0100 0111 1001 i=__f;..-=c_ N EG Absolute Instruction Long NEG $014000 OWL+2 0001 t--------t OWL +4 4000 Program Counter With Displacement This address mode requires one word of extension. The address of the operand is the sum of the address in the program counter and the sign-extended 16-bit displacement integer in the extension word. The value in the program counter is the address of the extension word. The reference is classified as a program reference. MPU IXXXXABCDI DO MEMORY COMMENTS · EA= IPCl + d,. · d1~ is Sign Extended · Machine Level Coding MOVE !LABEL), DO 0011 0000 0011 1010 IT--:J.:.h ~~;~ ~=~~ster Displacement Direct MOVE ILABELI. DO ADDRESS CALCULATION: PC ~ 00008002 d = OOOOlOOO <LABEL>$9002 00009002 1-------1 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 543 Program Counter With Index This address mode requires one word of extension. This address is the sum of the address in the program counter, the sign-extended displacement integer in the lower eight bits of the extension word, and the contents of the index register. The value in the program counter is the address of the extension word. This reference is classified as a program reference. EA= IPC) + (Rx) + d, Beginning ) Address of PC + di. Data Table ~~~~~~~~~;.able } PC+ d~ + Rx____..,. Data Table (NOTE) Extension Word 15 14 13 12 ·11 10 9 8 7 6 5 4 3 2 0 /A Register W/L 0 0 0 Displacement Integer D/A : Data Register= 0, Address Register= 1 Register : Index Register Number W/L : Sign-extented, low order Word integer in Index Register = 0 Long Word in Index Register = 1 MPU IXXXX3456IDO 100001010 IAO MEMORY! $8000~ $8002~ ~ <LABEL> L..sso12~ MOVE ILABEL) IAO). DO ADDRESS CALCULATIONS: PC = 00008002 AO= 00001010 d =00000010 00009022 COMMENTS · EA= IPCI + IRxl + d, Where PC-..Current Program Counter Ax ....... oesignated Index Register (Either Data or Address Registed da --s~Bit Displacement · Rx and da are Sign Extended · Rx may be Word or Long Word Long Word is Designated with Rx.L · Machine Level Coding MOVE ILABELI IAO). DO 0011 0000 0011 1011 _ l _ _ ~- ~ Move PCwith Word Index Data Register Direct -i:r [T 1000 0000 00010000 ilrnP,_ .. Register Register Constant Zeros Number Index Length 544 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Immediate Data This address mode requires either one or two words of ex· tension depending on the size of the operation. Byte operation - operand is low order byte of extension word Word operation - operand is extension word Long word operation - operand is in the two extension words, high-order 16 bits are in the first extension word, low-order 16 bits are in the second extension word. Extension Word lo o o: 15 0 0 0 0 0 0 Byte 15 or 0 Word t---- -I 15 or a Long Word - - - - - - - - '=!i~h_O_r~e!. ___ Low Order MPU [00001000[ AO MOVE #$1000. AO MEMORY COMMENTS · Data= Next Word(s) · Data is Sign Extended for Address Register but not Data Register · Machine Level Coding MOVE #$1000. AO I Move Word 0000 0111 1100 Ji t#0 Immediate Data Address Register Direct MPU MOVEQ #$5A, 03 MEMORY COMMENTS · Inherent Data · Data is Sign Extended to Long Word · Destination must be a Data Register · Machine Level Coding MOVEQ #$5A, 03 0111 011 0 0101 1010 I~~~ Move Zero Data Quick ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 545 Condition Codes or Status Register A selected set of instructions may reference the status regis- ter by means of the effective address field. These are: ANDI to CCR ANDI to SR EORltoCCR EORI tq SR ORI to CCR MPU ORI to SR MEMORY MOVE to CCR MOVE to SR TSR MOVE from SR ~ COMMENTS · EA = (Next Word I ·Note: This Example is a Privileged Instruction · Machine Level Coding MOVE $1020, SR 0100 0110 1111 1000 Move to SR lbsolute Short MOVE $1020, SR OWL+2 1020 t--------1 · EFFECTIVE ADDRESS ENCODING SUMMARY Table 4 is a summary of the effective addressing modes dis- cussed in the previous paragraphs. Table 4 Effective Address Encoding Summary Addressing Mode Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register Indirect with Index Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index Immediate Mode 000 001 010 011 Register register number register number register number register number 100 register number 101 register number 110 register number 111 000 111 001 111 010 111 011 111 100 · IMPLICIT REFERENCE Some instructions make implicit reference to the program counter (PC), the system stack pointer (SP), the supervisor stack pointer (SSP), the user stack pointer (USP), or the status register (SR). SYSTEM STACK The system stack is used implicitly by many instructions; user stacks and queues may be created and maintained through the addressing modes. Address register seven (A7) is the system stack pointer (SP). The system stack pointer is either the supervisor stack pointer (SSP) or the user stack pointer (USP), depending on the state of the S-bit in the status register. If the S-bit indicates supervisor state, SSP is the active system stack pointer, and the USP cannot be referenced as an address register. If the S-bit indicates user state, the USP is the active system stack pointer, and the SSP cannot be referenced. Each system stack fills from high memory to low memory. SYSTEM STACK POINTERS User Stack - --Supervisor Stack A7' USP · Accessed when S =0 · PC is Stacked on Subroutine Calls in User State · Increasing Addresses ·-SSP __./ · Accessed when S = 1 · PC is Stacked on Subroutine Calls in Supervisor State · Used for Exception Processing ~HITACHI 546 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 The address mode SP @- creates a new item on the active system stack, and the address mode SP@+ deletes an item from the active system stack. The program counter is saved on the active system stack on subroutine calls, and restored from the active system stack on returns. On the other hand, both the program counter and the status register are saved on the supervisor stack during the processing of traps and interrupts. Thus, the correct execution of the supervisor state code is not dependent on the behavior of user code and user programs may use the user stack pointer arbitrarily. In order to keep data on the system stack aligned properly, data entry on the stack is restricted so that data is always put in the stack on a word boundary. Thus byte data is pushed on or pulled from the system stack in the high order half of the word; the lower half is unchanged. USER STACKS User stacks can be implemented and manipulated by employ- ing the address register indirect with postincrement and predecrement addressing modes. Using an address register (on of AO through A6), the user may implement stacks which are filled either from high memory to low memory, or vice versa. The important things to remember are: using predecrement, the register is decremented before its contents are used as the pointer into the stack, using postincrement, the register is incremented after its contents are used as the pointer into the stack, byte data must be put on the stack in pairs when mixed with word or long data so that the stack will not get misaligned when the data is retrieved. Word and long accesses must be on word boundary (even) addresses. Stack growth from high to low memory is implemented with An@- to push data on the stack, An@+ to pull data from the stack. After eigher a push or a pull operation, register An points to the last (top) item on the stack. This is illustrated as: An- low memory (free) ... top of stack 7 bottom of stack high memory Stack growth from low to high memory is implemented with An@+ to push data on the stack, An@- to pull data from the stack. After either a push or a pull operation, register An points to the next available space on the stack. This is illustrated as: An- low memory ... bottom of stack top of stack (free) high memory QUEUES User queues can be implemented and manipulated with the address register indirect with postincrement or predecrement addressing modes. Using a pair of address registers (two of AO through A6), the user may implement queues which are filled either from high memory to low memory, or vice versa. Because queues are pushed from one end and pulled from the other. two registers are used: the put and get pointers. Queue growth from low to high memory is implemented with AputCa'+ to put data into the queue, Aget@+ to get data from the queue. After a put operation, the put address register points to the next available space in the queue and the unchanged get address register points to the next item to remove from the queue. After a get operation, the get address register points to the next item to remove from the queue and the unchanged put add1t·" register points to the next available space in the qurne I Im " illustrated as: Aput___. low memory last get (free) ...next get last put (free) high memory If the queue is to be implemented as a circular buffer, the address register should be checked and, if necessary, adjusted before the put or get operation is performed. The address register is adjusted by subtracting the buffer length (in bytes). Queue growth from high to low memory is implemented with Aput@- to put data into the queue. Aget@ - to get data from the queue. After a put operation, the put address register points to the last item put in the queue, and the unchanged get address register points to the last item removed from the queue. After a get operation, the get address register points to the last item removed from the queue and the unchanged put address register points to the last item put in the queue. This is illustrated as: @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 547 Aput--.. .t. Aget- low memory (free I ...last put next get last get (freeI high memory If the queue is to be implemented as a circular buffer. the get or put operation should be performed first, and then the address register should be checked and, if necessary, adjusted. The address register is adjusted by adding the buffer length (in bytes). ·INSTRUCTION SET SUMMARY The following paragraphs contain an overview of the form and structure of the 68000 instruction set. The instructions form a set of tools that include all the machine functions to perform the following operations: Data Movement Integer Arithmetic Logical Shift and Rotate Bit Manipulation Binary Coded Decimal Program Control System Control The complete range of instruction capabilities combined. with the flexible addressing modes described previously provide a very flexible base for program development. · DATA MOVEMENT OPERATIONS The basic method of data acquisition (transfer and storage) is provided by the move (MOVE) instruction. The move instruction and the effective addressing modes allow both address and data manipulation. Data move instructions allow byte, word, and long word operands to be transferred from memory to memory, memory to register, register to memory, and register to memory, and register to register. Address move instructions allow word and long word operand transfers and ensure that only legal address manipulations are executed. In addition to the general move instruction there are several special data movement instructions: move multiple registers (MOVEM), move peripheral data (MOVEP), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), unlink stack (UNLK), and move quick (MOVEQ). Table 5 is a summary of the data movement operations. Table 5 Data Movement Operations Instruction EXG LEA LINK MOVE MOVEM MOVEP MOVEO PEA SWAP UNLK Operand Size 32 32 - 8, 16,32 16,32 16,32 8 32 32 - Operation Rx .. Ry EA ... An (n ... -(SP) SP ... An; SP+d ... SP (EA)s ... EAd (EA) ... An,Dn An, On ... EA (EA) ... Dn On ... EA #xxx ... On EA ... -(SP) On[31:16) .. Dn[15:0) (An ... Sp; (SP)+ ... An (NOTES I s ·source d · destination I J · bit numbers -( }-=indirect with predecrement ( ) +=indirect with postincrement # = immediate data · INTEGER ARITHMETIC OPERATIONS The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP), clear (CLR), and negate (NEG). The add and subtract instructions are available for both address and data operations, with data operations accepting all operand sizes. Address operations are limited to legal address size operands (16 or 32 bits). Data, address, and memory compare operations are also available. The clear and negate instructions may be used on all sizes of data oper· ands. The multiply and divide operations are available for signed and unsigned operands using word multiply to produce a long word product, and a long word dividend with word divisor to produce a word quotien with a word remainder. Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These instructions are: add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). A test operand (TST) instruction that will set the condition codes as a result of a compare of the operand with zero is also available. Test and set (TAS) is a synchronization instruction useful in multiprocessor systems. Table 6 is a summary of the integer arithmetic operations. @HITACHI 548 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 6 Integer Arithmetic Operations Instruction ADD ADDX CLR CMP DIVS DIVU EXT MULS MULU NEG NEGX SUB SUBX TAS TST Operand Size 8, 16,32 16, 32 8, 16,32 16, 32 8, 16,32 8, 16,32 16, 32 32+ 16 32+ 16 8-+ 16 16-+32 16X16 - 32 15x16- 32 8, 16,32 8, 16,32 8, 16,32 16, 32 8, 16,32 8 8, 16,32 Operation On+ (EA)-+ On (EA)+ On-+ EA (EA)+ #xxx-+ EA AN+ (EA)-+ An Ox+ Dy+ X-+ Ox -(Ax) + - (Ay) + X-+ (Ax) (EA)-+MPU 0-+EA On - (EA) (EA) -#xxx (Ax) + - (Ay) + An - (EA) Dn+(EA)-+ On Dn+(EA)~ On (Dn)s-+ On16 (Onh6-+ On32 Dnx(EA)- On Onx(EA) - On 0 - (EAi- EA 0 - (EA) - X - EA On - (EA) - On (EAi - On- EA (EAi - #xxx - EA An - (EAi-An Ox - Dy - X -+ Ox -(Ax) - - (Ay) - X-+ (Ax) (EA) - 0, 1 -+ EA[7) (EA) -0 (NOTE) [ I =bit number - ( l = indirect with predecrement ( ) + = indirect with postincrement # = immediate data · LOGICAL OPERATIONS Logical operation instructions AND, OR. EOR. and NOT are available for all sizes of integer data operands. A similar set of immediate instructions (ANDI. ORI. and EORI) provide these logical operations with all sizes of immediate data. Table 7 is a summary of the logical operations. Table 7 Logical Operations Instruction AND Operand Size 8. 16, 32 OR 8, 16, 32 EOR 8, 16, 32 NOT 8, 16, 32 [NOTE] - == invert v = logical OR # = immediate data A = logical AND E9 = exclusive OR Operation Dn,(EAI- Dn {EA)/\ On ...... EA (EA)/\=XXX ...... EA Dn v (EA) - On IEAI v On - EA (EA) v .::-xxx __,.EA IEA)Ef)Dy - EA (EA)Ef) #xxx - EA - IEAJ- EA · SHIFT AND ROTATE OPERATIONS Shift operations in both directions are provided by the arithmetic instructions ASR and ASL and logical shift instructions LSR and LSL. The rotate instructions (with and without extend) available are ROXR. ROXL. ROR. and ROL. All shift and rotate operations can be performed in either registers or memory. Register shifts and rotates support all operand sizes and allow a shift count specified in the instruction of one to eight bits. or 0 to 63 specified in a data register. Memory shifts and rotates are for word operands only and allow only single-bit shifts or rotates. Table 8 is a summary of the shift and rotate operations. Table 8 Shift and Rotate Operations Instruction ASL ASA LSL LSR AOL ROA ROXL AOXA Operand Size Operation 8, 16, 32 ~o 8, 16,32 8, 16, 32 ~ ~o 8, 16, 32 8, 16, 32 8, 16,32 8, 16, 32 8, 16,32 o~ ~ ~ ~ f.CTJ.I ~ kD · BIT MANIPULATION OPERATIONS Bit manipulation operations are accomplished using thr following instructions: bit test (BTST). bit test and set ( BSl-l), bit test and clear (BCLR). and bit test and change (BCl!C). Table 9 is a summary of the bit manipulation operations. (Bit 2 of the status register is Z.) Table 9 Bit Manipulation Operations Instruction BTST BSET Operand Size 8, 32 8, 32 BCLR 8, 32 BCHG (Note) ,..., = invert 8, 32 Operation c- bit of IEAl-Z bit of IEA) - Z; 1 - bit of EA (-bit of (EAi- Z; o- bit of EA (- bit of (EAi - Z; - bit of (EA) - bit of EA · BINARY CODED DECIMAL OPERATIONS Multiprecision arithmetic operations on binary coded deci- mal numbers are accomplished using the following instructions: add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). Table 10· is a summary of the binary coded decimal operations. Table 10 Binary Coded Decimal Operations Instruction Operand Size Operation ABCD 8 Dx 10 + Dy 10 + X - Ox - (Ax),. + - IAy),. + X-+ (Ax) SBCD 8 Ox 10 -Dv 10 -X - Ox - (Ax),. - - (Ay),. - X-+ (Ax) N8CD 8 0 - (EAi,. - X - EA - ( )=indirect with predecrernent @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 549 · PROGRAM CONTROL OPERATIONS Program control operations are accomplished using a series of conditional and unconditional branch instructions and return instructions. These instructions are summarized in Table 11. The conditional instructions provide setting and branching for the following conditions: CC carry clear LS low or same CS carry set LT less than EQ equal MI minus F never true NE not equal GE greater or equal PL plus GT greater than HI high LE less or equal T always true vsvc no overflow overflow Table 11 Program Control Operations Instruction Conditional Bee DB cc Sec Unconditional BRA BSA JMP JSR R1turn1 RTR ATS Operation Branch conditionally (14 conditions) 8- and 16-bit displacement Test condition, decrement, and branch 16-bit displacement Set byte conditionally (16 conditions) Branch always 8-and 16-bit displacement Branch to subroutine 8- and 16-bit displacement Jump Jump to subroutine Return and restore condition codes Return from subroutine · SYSTEM CONTROL OPERATIONS System control operations are accomplished by using privi- leged instructions, trap generating instructions, and instructions that use or modify the status register. These instructions are summarized in Table 12. Table 12 System Control Operations Instruction Privileged RESET RTE STOP ORI to SR MOVE USP ANDI to SR EORI to SR MOVE EA to SR Trap Generating TRAP TRAPV CHK Status Register ANDI to CCR EORI to CCR MOVE EA to CCR ORI to CCR MOVE SR to EA Operation Reset external devices Return from exception Stop program execution Logical OR to status register Move user stack pointer Logical AND to status register Logical EOR to status register Load new status register Trap Trap on oveiflow Check register against bounds Logical AND to condition codes Logical EOR to condition codes Load new condition codes Logical OR to condition codes Store status register · BRANCH INSTRUCTION ADDRESSING BRANCH INSTRUCTION FORMAT Operation Word Extension Word 15 8 7 0 Operation Code 8 bit Displacement 16 bit Displacement if 8 bit Displacement= 0 RELATIVE, FORWARD REFERENCE, 8-81T OFFSET MPU MEMORY COMMENTS · Offset Contained in 8 LSBs of Op Word · Offset is 2"s Complement Number · If Offset = 0 then Word Offset is Used · Machine Level Coding BEQ NEXT cl:hl 0110 0111 0001 1110 ffik Branch If Equal BEQ NEXT PC+2=5002 d =001E 5020 $5020 Next OP Code @HITACHI 550 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 RELATIVE, BACKWARD REFERENCE 8-BIT OFFSET MPU EXAMPLE MEMORY COMMENTS · Offset Contained in 8 LSBs of Op Word · Offset is 2's Complement Number · If Offset == 0 then Word Offset is Used · Machine Level Coding BNE NEXT 0110 0110 1101 1110 ~i= i= Offset Branch If Not Equal BNE NEXT PC+ 2 ·4022 d · FFDE 4000 $4020 f---s_s_o_E_--1 RELATIVE, FORWARD REFERENCE. 16-BIT OFFSET MPU MEMORY COMMENTS Bee NEXT PC+2·4002 d·+1000 5002 $5002 Next OP Code @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 551 · SIGNAL AND BUS OPERATION DESCRIPTION The following paragraphs contain a brief description of the input and output signals. A discussion of bus operation during the various machine cycles and operations is also given. (NOTE) The terms assertion and negation will be used extensivel). This is done to avoid confusion when dealing with a mixture of "active-low" and "active-high" signals. The term assert or assertion is used to indicate that a signal is active or true independent of whether that voltage is low or high. The term negate or negation is used to indicate that a signal is inactive or false. · SIGNAL ·DESCRIPTION The input and output signals can be functionally organized into the groups shown in Figure 14. The following paragraphs provide a brief description of the signals and also a reference (if applicable) to other paragraphs that contain more detail about the function being performed. HD6800 { Peripheral Control Bus } Arbitration Control Read/Write (R/W) This signal defines the data bus transfer as a read or write cycle. The R/W signal also works in conjunction with the upper and lower data strobes as explained in the following paragraph. Upper and Lower Data Strobes (UDS, LOS) These signals control the data on the data bus, as shown in Table 13. When the R/W line is high, the processor will read from the data bus as indicated. When the R/W line is low, the processor will write to the data bus as shown. Table 13 Data Strobe Control of Data Bus UDS LDS R/W Ds - D" High High - No val id data Do- D1 No valid data Low Low High Valid data bits 8 - 15 Val id data bits 0-1 High Low High No valid data Val id data bits 0-7 Low High High Valid data bits 8 -15 No valid data Low Low Low Valid data bits 8-15 Val id data bits 0-7 High Low Low Valid data bits o-7* Valid data bits 0-7 Low High Low Valid data bits 8 - 15 Valid data bits 8 - 15* * These conditions are a result of current implementation and may not appear on future devices. Figure 14 Input and Output Signals ADDRESS BUS (A1 through A13) This 23-bit, unidirectional, three-state bus is capable of addressing 8 megawords of data. It provides the address for bus operation during all cycles except interrupt cycles. During interrupt cycles, address lines At, A1, and A3. Provide information about what level interrupt is being serviced while address lines A· through A1J are all set to a logic high. DATA BUS (Do through 015) This 16-bit, bidirectional, three-state bus is the general purpose data path. It can transfer and accept data in either word or byte length. During an interrupt acknowledge cycle, an external device supplies the vector number on data lines Do through D1. ASYNCHRONOUS BUS CONTROL Asynchronous data transfer are handled using the following control signals: address strobe, read/write, upper and lower data strobes, and data transfer acknowledge. These signals are explained in the following paragraphs. Address Strobe (AS) This signal indicates that there is a valid address on the address bus. Data Transfer Acknowledge (DTACKI This input indicates that the data transfer is completed. When the processor recognizes DTACK during a read cycle, data is latched and the bus cycle terminated. When DTACK is recognized during a write cycle, the bus cycle is. terminated. (Refer to ASYNCHRONOUS VERSUS SYNCHRONOUS OPERATION) BUS ARBITRATION CONTROL These three signals form a bus arbitration circuit to deter- mine which device will be the bus master device. Bus Request (BR I This input is wire ORed with all other devices that could be bus masters. This input indicates to the processor that some other device desires to become the bus master. Bus Grant (BG) This output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle. Bus Grand Acknowledge (BGACK) This input indicates that some other device has become the bus master. This signal cannot be asserted until the following four conditions are met: (I ) A Bus Grant has been received (2) Address Strobe is inactive which indicates that the microprocessor is not using the bus (3) Data Transfer Acknowledge is inactive which indicates @HITACHI 552 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 that neither memory nor peripherals are using the bus (4) Bus Grant Acknowledge is inactive which indicates that no other device is still claiming bus mastership. INTERRUPT CONTROL (IPL0 , IPL 1 , IPL2) These input pins indicate the encoded priority level of the device requesting an interrupt. Level seven is the highest priority while level zero indicates that no interrupts are requested. Level seven can not be masked. The least significant bit is given m 1PI:O and the most significant bit is contained in wr:;:. These lines must remain stable until the processor signals interrupt acknowledge (FCo - FC2 are all high) to insure that the interrupt is recognized. SYSTEM CONTROL The system control inputs are used to either reset or halt the processor and to indicate to the processor that bus errors have occurred. The three system control inputs are explained in the following paragraphs. Bus Error (BERRI This input informs the processor that there is a problem with the cycle currently being executed. Problems may be a result of: (I) Nonresponding devices (2) Interrupt vector number acquisition failure (3) Illegal access request as determined by a memory man- agement unit (4) Other application dependent errors. The bus error signal interacts with the halt signal to determine if exception processing should be performed or if the current bus cycle should be retried. Refer to BUS ERROR ANO HALT OPERATION paragraph for additional information about the interaction of the bus error and halt signals. Reset (RES) This bidirectional signal line acts to reset (initiate a system initialization sequence) the processor in response to an external reset signal. An internally generated reset (result of a RESET instruction) causes all external device.s to be reset and the internal state of the processor is not affected. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied at the same time. Refer to RESET OPERATION paragraph for additional information about reset operation. Halt (HALT) When this bidirectional line is driven by an external device, it will cause the processor to stop at the completion of the current bus cycle. When the processor has been halted using this input, all control signals are inactive and all three-state lines are put in their high-impedance state. Refer to BUS ERROR AND HALT OPERATION paragraph for additional information about the interaction between the halt and bus error signals. When the processor has stopped executing instructions, such as in a double bus fault condition, the halt line is driven by the processor to indicate to external devices that the processor has stopped. HMCS6800 PERIPHERAL CONTROL These control signals are used to allow the interfacing of synchronous HD6800 peripheral devices with the asynchronous 68000. These signals are explained in the following paragraphs. Enable (E) This signal is the standard enable signal common to all HD6800 type peripheral devices. The period for this output is ten 68000 clock periods (six clocks low; four clocks high). Enable is generated by an internal ring counter which may come up in any state (i.e., at power on, it is impossible to guarantee phase relationship of E to CLK), E is a free-running clock and runs regardless of the state of the bus on the MPU. Valid Peripheral Address (VPA) This input indicates that the device or region addressed is a HD6800 family device and that data transfer should be synchronized with the enable (E) signal. This input also indicates that the processor should use automatic vectoring for an interrupt. Refer to INTERFACE WITH HD6800 PERIPHERALS. ALS. Valid Memory Address (VMA) This output is used to indicate to HD6800 peripheral devices that there is a valid address on the address bus and the processor is synchronized to enable. This signal only responds to a valid peripheral address (VPA) input which indicates that the peripheral is a HD6800 family device. PROCESSOR STATUS (FC0 , FC 1 , FC21 These function code outputs indicate the state (user or supervisor) and the cycle type currently being executed, as shown in Table 14. The information indicated by the function code outputs is valid whenever address strobe (AS) is active. Table 14 Function Code Outputs FC2 FC 1 FCo Low Low Low Low Low High Low High Low Low High High High Low Low High Low High High High Low High High High Cycle Type (Undefined, Reserved) --~-·- User Data ~-- User Program (Undefined, Reserved) (Undefined, Reserved) Superviser Data Supervisor Program Interrupt Acknowledge CLOCK (CLK) The clock input is a TTL-<:ompatible signal that is internally buffered for development of the internal clocks needed by the processor. The clock input should not be gated off at any time, and the clock signal must conform to minimum and maximum pulse width time. SIGNAL SUMMARY Table IS is a summary of all the signals discussed in the previous paragraphs. · BUS OPERATION The following paragraphs explain control signal and bus operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 553 Signal Name Address Bus Data Bus Address Strobe Read/Write Upper and Lower Data Strobes Data Transfer Acknowledge Bus Request Bus Grant Bus Grant Acknowledge Interrupt Priority Level Bus Error Reset Halt Enable Valid Memory Address Valid Peripheral Address Function Code Output Clock Power Input Ground ·Open drain Table 15 Signal Summary Mnemonic A, -A" Do - Du AS R/W UDS, LOS DTACK BR BG BGACK IPLo. IPL,, iPC, BEAR RES HALT E VMA WA FCo,FC,,FC, CLK Vee Vss Input/Output output input/output output output output input input output input input input input/output input/output output output input output input input input Active State high high low read-high write-low low low low low low low low low low high low low high high - Three State On BGACK On HALT yes yes yes yes yes no yes no yes no no no no no no no no no no no no no no* no· no* no· no no yes no no no yes no no no - - - - DATA TRANSFER OPERATIONS Transfer of data between devices involve the following leads: (I) Address Bus A1 through A,3 (2) Data Bus D0 through D15 (3) Control Signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. In addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave device. The following paragraphs explain the read, write, and readmodify-write cycles. The indivisible read-modify-write cycle is the method used by the 68000 for interlocked multiprocessor communications. Read Cycle During a read cycle, the processor receives data from memory or a peripheral device. The processor reads bytes of data in all cases. If the instruction specifies a word (or double word) operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes. When the instruction specifies byte operation, the processor uses an internal Ao bit to determine which byte to read and then issues the data strobe required for that byte. For bytes operations, when the Ao bit equals zero, the upper data strobe is issued. When the Ao bit equals one, the lower data strobe is issued. When the data is received, the processor correctly positions it internally. A word read cycle flow chart is given in Figure 15. A byte read cycle flow chart is given in Figure 16. Read cycle timing is given in Figure 17. Figure 18 details word and byte read cycle operations. Refer to these illustrations during the following detailed. At state zero (SO) in the read cycle, the address bus (A 1 through A23) is in the high impedance state. A function code is asserted on the function code output line (FC0 through FC2). The read/write (R/W) signal is switched high to indicate a. read cycle. One half clock cycle later, at state 1, the address bus is released from the high impedance state. The function code outputs indicate which address space that this cycle will operate on. In state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus and the upper and lower data strobe (UDS, LDS) is asserted as required. The memory or peripheral device uses the address bus and the address strobe to determine if it has been selected. The selected device uses the read/write signal and the data strobe to place its information on the data bus. Concurrent with placing data on the data bus, the selected device asserts data transfer acknowledge (DTACK). Data transfer acknowledge must be present at the processor at the start of state 5 or the processor will substitute wait states for states 5 and 6. State 5 starts the synchronization of the returning data transfer acknowledge. At the end of state 6 (beginning of state 7) incoming data is latched into an internal data bus holding register. During state 7, address strobe and the upper and/or lower data strobes are negated. The address bus is held valid through state 7 to allow for static memory operation and signal skew. @HITACHI 554 Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 BUS MASTER SLAVE Address Device 1) Set R/W to Read 2) Place Function Code on FCo - FC2 3) Place Address on A1 -Au 4) Assert Address Strobe (AS) 5) Assert Upper Data Strobe (UDS) and Lower Data Strobe (Li'iS) I Input Data 1) Decode Address 2) Place Data on 0 0 - 0 15 3) Assert Data Transfer Acknowledge (OTACK) i Acquire Data 1) Latch Data 21 Negate Ul5S" and LOS" 3) Negate~ i Terminate Cycle 1) Remove Data from 0 0 -Dis 2) Negate DTACK ! Start Next Cycle BUS MASTER SLAVE Address Device 1) Set R/Wto Read 2) Place Function Code on FC0 - FC1 3) Place Address on A 1 - A 23 4) Assert Address Strobe IAS) 5) Assert Upper Data Strobe (LIDS) or Low- er Data Strobe (LI5S) (based on A, I I i Input Data 1) Decode Address 2) Place Data on 0 0 - 0 1 or 0 11 - 0 15 (based on UDS or LDSl 3) Assert Data Transfer Acknowledge (DTACK) Acquire Data 1) Latch Data 21 Negate UBS or LOS" 31 Negate AS l Terminate Cycle 1) Remove Data from Do ~ D1 or D~ - D1~ 2) Negate DTACK Start Next Cycle Figure 15 Word Read Cycle Flow Chart Figure 16 Byte Read Cycle Flow Chart CLK SO SI S2 SJ S4 SS S6 S7 SO S1 S2 S3 S4 SS S6 S7 SO Sl S2 S3 S4 w w w w SS S6 S7 UDS LOS :..._____.!:=====------.. R/W DTACK~ r o,-o., :J { >- o,-o, :J1--_;c===~-~._____J-----'----___J>- +- -- --.r---. - - - Fc, - FC, :::::X - - - 1~ Read - - Write - - >C --l Slow Read- - - Figure 17 Read and Write Cycle Timing Diagram @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 555 CLK A1 -Au Ao* AS uos r - \ LOS R/W :::> OTACK 011 -Du ~~;==<====\..>.~__::======~~ic=======\r- Do -D, ::x FCo -FC2 x *Internal Signal Only f- ---- ---j --j---- Word Read - - ·Odd Byte R e a d - - + - - Even Byte Read Figure 18 Word and Byte Read Cycle Timing Diagram The read/write signal and the function code outputs also remain valid through state 7 to ensure a correct transfer operation. The slave device keeps its data asserted until it detects the negation of either the address strobe or the upper and/or lower data strobe. The slave device must remove its data and data transfer acknowledge within one clock period of recognizing the nega· tion of the address or data strobes. Note that the data bus might not become free and data transfer acknowledge might· not be removed until state 0 or 1. When address strobe is negated, the slave device is released. Note that a slave device must remain selected as long as address strobe is asserted to ensure the correct functioning of the readmodify-write cycle. Write Cycle During a write cycle, the processor sends data to memory or a peripheral device. The processor writes bytes of data in all cases. If the instruction specifies a word operation, the processor writes both bytes. When the instruction specifies a byte opera tion. the processor uses an internal A0 bit to determine which byte to write and then issues the data strobe required for that byte. For byte operations, when the Ao bit equals zero, the upper data strobe is issued. When the Ao bit equals one, the lower data strobe is issued. A word write cycle flow chart is given in Figure 19. A byte write cycle flow chart is given in Figure 20. Write cycle timing is given in Figure 17. Figure 21 details word and byte write cycle operation. Refer to these illustrations during the following detailed discussion. At state zero (SO) in the write cycle, the address bus (A, through A23) is in the high impedance state. A function code is asserted on the function code output line (FC0 through FC,). (NOTE) The read/write (RJW) signal remains high until state 2 to prevent bus conflicts with preceding read cycles. The data bus is not driven until state 3. One half clock later, at state 1, the address bus is released from the high impedance state. The function code outputs indicate which address space that this cycle will operate on. In state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus. The memory or peripheral device uses the address bus and the address strobe to determine if it has been selected. During state 2, the read/ write signal is switched low to indicate a write cycle. When external processor data bus buffers are required, the read/write line provides sufficient directional control. Data is not asserted during this state to allow sufficient tum around time for external data buffers (if used). Data is asserted onto the data bus during state 3. In state 4, the data strobes are asserted as required to indicate that the data bus is stable. The selected device uses the read/write signal and the data strobes to take its information from the data bus. The selected device asserts data transfer acknowledge (DTACK) when it has successfully stored the data. Data transfer acknowledge must be present at the processor at the start of state 5 or the processor will substitute wait states for states 5 and 6. State 5 starts the synchronization of the returning data transfer acknowledge. During state 7, address strobe and the upper and/or lower data strobes are negated. The address and data buses are held valid through state 7 to allow for static memory operation and signal skew. The read/write signal and the function code outputs also remain valid through state 7 to ensure a correct transfer operation. The slave device keeps its data transfer acknowledge asserted until it detects the negation of either the address strobe or the upper and/or lower data strobe. The slave device must remove its data transfer acknowledge within one clock period after recognizing the negation of the address or data strobes. Note that the processor releases the data bus at the end of state 7 but that data transfer acknowledge might not be removed until state 0 or 1. When address strobe is negated, the slave device is released. @HITACHI 556 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 BUS MASTER Address Device 1) Place Function Code on FC0 ..... FC2 2) Place Address on A1 ~All J) Assert Address strobe (AS) 4) Set R/W to Write 5) Place Data on Do - Dis 6) Assert Upper Data Strobe !UOS) and Lower Data Strobe (CiSSJ SLAVE BUS MASTER SLAVE Address Device 1) Place Function Code on FC0 - FC1 2) Place Address on. A 1 ..... Au 3) Assert Address Strobe ('ASJ 4) Set R/W to Write 5) Place Data on 0 0 - 0 7 or OH - 0 15 (according to A0 ) 6) Assert Upper Data Strobe (DOSI or Lower Data Strobe (t'C:IBI (based on Ao) Input Data 1 ) Decode Address 2) Store Data on 0 0 - Dis 3) Assert Data Transfer Acknowledge IDTACKI Terminate Output Transfer 1I Negate UDS and LOS 21 Negate AS 3) Remove Data from Do ~ 0 15 4) Set R/W to Read l Terminate Cycle 11 Negate DTACK Input Data 1) Decode Address 2) Store Data on 0 0 0 ..... 7 if [l')S is asserted Store Data on D~ - Du if 015S is asserted 3) Assert Data Transfer Acknowledge IDTACKI ~ Terminate Output Transfer 11 Negate UD5 and LI5S 21 Negate AS 3) Remove Data from 0 0 - 0 7 or D/j ~ 0 15 41 Set R/W to Read Termin~~ycle 11 Negate DTACK I Start Next Cycle Figure 19 Word Write Cycle Flow Chart Start Next Cycle Figure 20 Byte Write Cycle Flow Chart SO S1 S2 SJ S4 S5 S6 S7 SO S1 S2 SJ S4 S5 S6 57 SO S1 52 SJ S4 55 S6 57 CLK A,· A5 UD5 LOS R/W DTACK ~~~-====~~~~--'',...~~==~~~~~-',~~-====~~~~___,, I- - - - + - + - --.1 *Internal Signal Only Word Write - -- -Odd Byte Write - - - ·Even Byte Write - - - Figure 21 Word and Byte Write Cycle Timing Diagram ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 557 Read-Modify-Write Cycle The read-modify-write cycle performs a read, modifies the data in the arithmetic-logic unit, and writes the data back to the same address. In the 68000 this cycle is indivisible in that the address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a multiple processor environment. This instruction is the only instruction that uses the read-modify-write cycle and since the test and set instruction only operates on bytes, all read-modify-write cycles are byte operations. A read-modify-write cycle flow chart is given in Figure 22 and a timing diagram is given in Figure 23. Refer to these illustrations during the following detailed discussions. At state zero (SO) in the read-modify-write cycle, the address bus (A 1 through A23) is in the high impedance state. A function code is asserted on the function code output line (FCo through FC,). The read/write (R/W) signal is switched high to indicate a read cycle. One half clock cycle later, at state 1, the address bus is released from the high impedance state. The function code outputs indicate which address space that this cycle will operate on. In state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus and the upper or lower data strobe (UDS, LOS) is asserted as required. The memory or peripheral device uses the address bus and the address strobe to determine if it has been selected. The selected device uses the read/write signal and the data strobe to place its information on the data bus. Concurrent with placing data on the data bus, the selected device asserts data transfer acknowledge (DTACK). Data transfer acknowledge must be present at the~ processor at the start of state 5 or the processor will substitute wait states for states S and 6. State 5 starts the synchronization of the returning data transfer acknowledge. At the end of state 6 (beginning of state 7) incoming data is latched into an internal data bus holding register. During state 7, the upper or lower data strobe is negated. The address bus, address strobe, read/write signal, and function code outputs remain as they were in preparation for the write portion of the cycle. The slave device keeps its data asserted until it detects the negation of the upper or lower data strobe. The slave device must remove its data and data transfer acknowledge within one clock period of recognizing the negation of the data strobes. Internal modification of data may occur from state 8 to state 11. (NOTE) The read/write signal remains high until state 14 to prevent bus conflicts with the preceding read portion of the cycle and the data bus is not asserted by the processor until state 15. In state 14, the read/write signal is switched low to indicate a write cycle. When external processor data bus buffers are required, the read/write line provides sufficient directional control. Data is not asserted during this state to allow sufficient turn around time for external data buffers (if used). Data is asserted onto the data bus during state 15. In state 16, the data strobe is asserted as required to indicate that the data bus is stable. The selected device uses the read/ write signal and the data strobe to take its information from the data bus. The selected device asserts data transfer acknowledge (DTACK) when it has successfully stored its data. Data transfer acknowledge must be present at the processor at the start of state 17 or the processor will substitute wait states for states 17 and 18. State 17 starts the synchronization of the returning data transfer acknowledge for the write portion of the cycle. The bus interface circuitry issues requests for subsequent internal cycles during state 18. During state 19, address strobe and the upper or lower data strobe is negated. The address and data buses are held valid through state 19 to allow for static memory operation and signal skew. The read/write signal and the function code outputs also remain valid through state 19 to ensure a correct transfer operation. The slave device keeps its data transfer acknowledge asserted until it detects the negation of either the address strobe or the upper or lower data strobe. The slave device must remove its data transfer acknowledge within once clock period after recognizing the negation of the address or data strobes. Note that the processor releases the data bus at the end of state 19 but that data transfer acknowledge might not be removed until state 0 or 1. When address strobe is negated the slave device is released. BUS ARBITRATION Bus arbitration is a technique used by master-type devices to request, be granted, and acknowledge bus mastership. In its simplest form, it consists of: (1) Asserting a bus mastership request. (2) Receiving a grant that the bus is available at the end of the current cycle. (3) Acknowledging that mastership has been assumed. Figure 24 is a flow chart showing the detail involved in a request from a single device. Figure 25 is a timing diagram for the same operations. This technique allows processing of bus requests during data transfer cycles. The timing diagram shows that the bus request is negated at the time that an acknowledge is asserted. This type of operation would be true for a system consisting of the processor and one device capable of bus mastership. In systems having a number of devices capable of bus mastership, the bus request line from each device is wire ORed to the processor. In this system, it is easy to see that there could be more than one bus request being made. The timing diagram shows that the bus grant signal is negated a few clock cycles after the transition of the acknowledge (BGACK) signal. However, if the bus requests are still pending, the processor will assert another bus grant within a few clock cycles after it was negated. This additional assertion of bus grant allows external arbitration circuitry to select the next bus master before the current bus master has completed its requirements. The following paragraphs provide additional information about the three steps in the arbitration process. @HITACHI 558 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 BUS MASTER Address Device 1I Set R/W to Read 2) Place Function Code on FC0 - FC 2 3) Place Address on A1 -AH 41 Assert Address Strobe IASI 5) Assert Upper Data Strobe (UDSI or Lower Data Strobe (LOS) SLAVE Input Data 1) Decode Address 2) Place Data on Do ... D1 or Os ... 0 15 3) Assert Data Transfer Acknowledge IDTACKI Acquire Data 1I Latch Data 21 Negate~ or ITlS 3) Start Data Modification ~~inate Cycle 1) Remove Data from Do -0, or 0 11 -0 15 21 Negate DiACK Start Output Transfer 1I Set R/W to Write 21 Place Data on 0 0 -D, or 0 8 -015 3) Assert Upper Data Strobe (UDS) or Lower Data Strobe ICTiSI Input Data 1) StrobeDataon0 0 -D1or0 11 -0 15 2) Assert Data Transfer Acknowledge (DTACKI Terminate Output Transfer ms 11 Negate ODS or 21 Negate AS 31 Remove Data from 0 0 -D, or 0 8 -0 15 41 Set R/W to Read Terminate Cycle 11 Negate DTACK Start Next Cycle Figure 22 Read-Modify-Write Cycle Flow Chart CLK R/W~~~-==========-~~~~~----.. DTACK Do - 07 or Os -015 FC, -FC2 ------/ ::x::::::::::::::::::::=~~~~~~~~=====::::::::::::::::::::::::::::===~~~~~~~= f'--- - - - - - - - - - - -+j Indivisible Cycle - - - - - - - - - - Figure 23 Read-Modify-Write Cycle Timing Diagram @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 559 PROCESSOR REQUESTING DEVICE Request the Bus 1) Assert Bus Request (BR) I Grant Bus Arbitration 1) Assert Bus Grant (BG) Acknowledge Bus Mastership 1) External arbitration determines next bus master 2) Next bus master waits for current cycle to complete 31 Next bus master asserts Bus Grant Acknowledge (BGACK) to become new master 4) Bus master negates BR I Terminate Arbitration 1) Negate BG (and wait for BG ACK to be negated) Operate as Bus Master 1) Perform Data Transfers (Read and Write cycles) according to the same rules the processor uses. Release Bus Mastership 1) Negate BG ACK Re-Arbitrate or Resume Processor Operation Figure 24 Bus Arbitration Cycle Flow Chart Requesting the Bus External devices capable of becoming bus masters request the bus by asserting the bus request (BR) signal. This is a wire ORed signal (although it need not be constructed from open collector devices) ·that indicates to the processor that some external device requires control of the external bus. The processor is effectively at a lower bus priority level that the external device and will relinquish the bus after it has completed the last bus cycle it has started. When no acknowledge is received before the bus request signal goes inactive, the processor will continue processing when it detects that the bus request is inactive. This allows ordinary processing to continue if the arbitration circuitry responded to noise inadvertently. Receiving the Bus Grant The processor asserts bus grant (BG) as soon as possible. Normally this is immediately after internal synchronization. The only exception to this occurs when the processor has made an internal decision to execute the next bus cycle but has not progressed far enough into the cycle to have asserted the address strobe (AS) signal. In this case, bus grant will not be asserted until one clock after address strobe is asserted to indicate to external devices that a bus cycle is being executed. The bus grant signal may be routed through a daisy-<:hained network or through a specific priority-encoded network. The processor is not affected by the external method of arbitration as long as the protocol is obeyed. Acknowledgement of Mastership Upon receiving a bus grant, the requesting device waits until address strobe, data transfer acknowledge, and bus grant acknowledge are negated before issuing its own BGACK. The negation of the address strobe indicates that the previous master has completed its cycle, the negation of bus grant acknowledge indicates that the previous master has released the bus. (While address strobe is asserted no device is allowed to "break into" a cycle.) The negation of data transfer acknowledge indicates the previous slave has terminated its connection to the previous master. Note that in some applications data CLK A5 LDS/UDS R/W DTACK Do -Du FCo -FC1 +- - -+- - - - - --+-- -- Processor - - OMA Device Processor - - - OMA Device - - - - Figure 25 Bus Arbitration Cycle Timing Diagram @HITACHI 560 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 transfer acknowledge might not enter into this function. General purpose devices would then be connected such that they were only dependent on address strobe. When bus grant acknowledge is issued the device is bus master until it negates bus grant acknowledge. Bus grant acknowledge should not be negated until after the bus cycle(s) is (are) completed. Bus mastership is terminated at the negation of bus grant acknowledge. The bus request from the granted device should be dropped after bus grant acknowledge is asserted. If a bus request is still pending, another bus grant will be asserted within a few clocks of the negation of bus grant. Refer to Bus Arbitration Control section. Note that the processor does not perform any external bus cycles before it re-asserts bus grant. BUS ARBITRATION CONTROL The bus arbitration control unit in the 68000 is implemented with a finite state machine. A state diagram of this machine is shown in Figure 26. All asynchronous signals to the 68000 are synchronized before being used internally. This synchronization is accomplished in a maximum of one cycle of the system clock, assuming that the asynchronous input setup time ("#'47) has been met (see Figure 27). The input signal is sampled on the falling edge of the clock and is valid internally after the next falling edge. As shown in Figure 26, input signals labeled R and A are internally synchronized on the bus request and bus grant acknowledge pins respectively. The bus grant output is lebeled G and the internal three-state control signal T. If Tis true, the address, data, function code line, and control buses are placed in a high-impedance state when AS is negated. All signals are shown in positive logic (active high) regardless of their true active voltage level. State changes (valid outputs) occur on the next rising edge after the internal signal is valid. A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 28. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 29. If a bus request is made at a time when the MPU has already begun a bus cycle but AS has not been asserted (bus state SO), BG will not be asserted on the next rising edge. Instead, BG will be delayed until. the second rising edge following it"s internal assertion. This sequence is shown in Figure 30. Internal Signal Valid------~l External Signal Sampled~ · BR O n t e r n a l ) - - - - - - - - - - - - - . A = Bus Request Internal A ::: Bus Grant Acknowledge Internal G =Bus Grant T =Three-State Control to Bus Control Logic·· X = Don't Care · State machine will not change state if bus is in SO. Refer to BUS ARBITRATION CONTROL for additional information. ** The address bus will be placed in the high impedance state if T is asserted and AS is negated. Figure 26 State Diagram of 68000 Bus Arbitration Unit Figure 27 Timing Relationship of External Asynchronous Inputs to Internal Signals @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 561 Bus three stated -------~ BG asserted~ 11 :~ ::~~1i:ernal BR asserted* CLK BR------, SO Sl S2 S3 S4 SS S6 S7 BG~~~~~======~~~~-' SO Sl S2 S3 S4 SS S6 S7 SO S1 BGACK \ !' ~ r-- \ !' \ !' ~ r-- ~ r-- ==:><: x::: FCo ._ RFC/2 W====~=============>=~~~~~~~~~~~~~=====(=========::::.=== DTACK . Processor Alternate Bus Master Processor · Figure 28 Bus Arbitration During Processor Bus Cycle Bus released from three state and processor starts next bus c y c l e - - - - - - - - - - - - - - - , BGACK negated------------------------~ BG asserted and bus three s t a t e d - - - - - - - - - , CLK BR SO Sl S2 S3 S4 SS 56 S7 BG~~~~~~~~~~~-=======~~~~~ BGACK SO Sl S2 S3 S4 R/W DTACK ~~~~~~~~~~~~~= .. Processor Bus Inactive Alternate Bus Master Processor Figure 29 Bus Arbitration with Bus Inactive 562 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 951.31 · (408) 435-8300 SO S1 S2 S3 S4 S5 S6 S7 BR BG -==========:-~~~~__J SO S1 S2 S3 S4 S5 S6 S7 SO S1 BGACK \ I' \ \ rI ' ) ~ r--'\ ~ rrr------ ( c R/W~~~~~~~~~~~~----"-~~~~~~~~~~~..Jr-~~~~~~~~~~~- DTACK .. Processor Alternate Bus Master Processor Figure 30 Bus Arbitration During Processor Bus Cycle Special Case BUS ERROR AND HALT OPERATION In a bus architecture that requires a handshake from an ex- ternal device, the possibility exists that the handshake might not occur. Since different systems will require a different maximum response time, a bus error input is provided. External circuitry must be used to determine the duration between address strobe and data transfer acknowledge before issuing a bus error signal. When a bus error signal is received, the processor has two options initiate a bus error exception sequence or try running the bus cycle again. Exception Sequence When the bus error signal is asserted, the current bus cycle is terminated. If BERR is asserted before the falling edge of S2, AS will be negated in S7 in either a read or write cycle. As long as BERR remains asserted, the data and address buses will be in the high-impedance state. When BERR is negated, the processor will begin stacking for exception processing. Figure 31 is a timing diagram for the exception sequence. The sequence is composed of the following elements. (I) Stacking the program counter and status register (2) Stacking the error information (3) Reading the bus error vector table entry (4) Executing the bus error handler routine The stacking of the program counter and the status register is the same as if an interrupt had occurred. Several additional items are stacked when a bus error occurs. These items are used to determine the nature of the error and correct it, if possible. The bus error vector is vector number two located at address $000008. The processor loads the new program counter from this location. A software bus error handler routine is then executed by the processor. Refer to EXCEPTION PROCESSING for additional information. Re-Running the Bus Cycle When, during a bus cycle, the processor receives a bus error signal and the halt pin is being driven by an external device, the processor enters the re-run sequence. Figure 32 is a timing diagram for re-running the bus cycle. The processor terminates the bus cycle, then puts the address and data output lines in the high-impedance state. The processor remains "halted," and will not run another bus cycle until the halt signal is removed by external logic. Then the processor will re-run the previous bus cycle using the same address, the same function codes, the same data (for a write operation), and the same controls. The bus error signal should be removed at least one clock cycle before the halt signal is removed. (NOTE) The processor will not re-run a read-modify-write cycle. This restriction is made to guarantee that the entire cycle runs correctly and that the write operation of a Test-and-Set operation is performed without ever releasing AS. If BERR and HALT are asserted during a read-modify-write bus cycle, a bus error operation results. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 563 CLK LDS/UDASS ------. R/W---~==============================~---1'~--~ DTACK-------------------------1'-..----:::::==~-- ~lf!i!.iat~ - - Response Failure- - ~ - - - Bus Error Detection- - - _...J..- - 1 ~it,!!t!_B~s- -- Read Error Stacking Figure 31 Bus Error Timing Diagram CLK AS::::_--==\"""-------;.~--------_:.__:._~=\'"-----;:::!.~~ LDS/UDS R/w----------------------------------=----- DTACK--------------------------------~ FCo BEFRCR,::::::::.2:::::x::-::-:'-\-;:=--=-=--=--=--=-=i;=.!=f:=====:=Z:=:=1::C::l'o.:c.:k.:-P:-er-:i-o-:d-==-==-=-==-==-=-==-==~=======================f==x==:==:=:~=:==:= HALf------":~~~~~~~~~~~~~~~~--'r-::==::===::=~=:~=-=-.-i~~------------------- t-- -+- - - - - - - - Read - - - Halt - - - - - - ~.._ - - - - Rerun- - ~ Figure 32 Re-Run Bus Cycle Timing Information Halt Operation with No Bus Error The halt input signal to the 68000 perform a Halt/Run/ Single-Step function in a similar fashion to the HD6800 halt function. The halt and run modes are somewhat self explanatory in that when the halt signal is constantly active the processor "halts" (does nothing) and when the halt signal is constantly inactive the processor "runs" (does something). The single-step mode is derived from correctly timed transitions on the halt signal input. It forces the processor to execute a single bus cycle by entering the "run" mode until the processor starts a bus cycle then changing to the "halt" mode. Thus, the single-step mode allows the user to proceed through (and therefore debug) processor operations one bus cycle at a time. Figure 33 details the timing required for correct single-step operations and Figure 34 shows a simple circuit for providing the single-step function. Some care must be exercised to avoid harmful interactions between the bus error signal and the halt pin when using the single cycle mode as a debugging tool. This is also true of interactions between the halt and reset lines since these can reset the machine. When the processor completes a bus cycle after recognizing that the halt signal is active, most three-state signals are put in the high-impedance state. These include: ( 1) Address lines (2) Data lines This is required for correct performance of the re-run bus cycle operation. While the processor is honoring the halt request, bus arbitration performs as usual. That is, halting has no effect on bus arbitration. It is the bus arbitration function that removes the control signals from the bus. The halt function and the hardware trace capability allow the hardware debugger to trace single bus cycles or single instructions at a time. These processor capabilities, along with a software debugging package, give total debugging flexibility. ~HITACHI 564 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 CLK A1 -AAlls :~~~~-------;::~::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::~:::;:--------;:?:..~:== LDS/UDS R/W _ _ _...=::=::=::=::=~------------~===:=:::=-=:!.__ __ DTACK Do -Du x::= :::JC FC, H- AFCL, T~'.=::====~-----'X'---------;:=:=:=:=:=:==::=:=:=::==:~=== -+- - - - -+-- - j.- ---Read- - -Halt- - - -Read- - ---j Figure 33 Halt Signal Timing Characteristics RUN MODE SINGLE STEP MODE SINGLE STEP RUN/SINGLE STEP [ (To Processor) ·OPEN COLLECTOR DEVICE > STEP K a a,__...._S_TE_P ~ Figure 34 Simplified Single-Step Circuit AS (From Processor) RESET Double Bus Faults When a bus error exception occurs, the processor will at- tempt to stack several words containing information about the state of the machine. If a bus error exception occurs during the stacking operation, there have been two bus errors in a row. This is commonly referred to as a double bus fault. When a double bus fault occurs, the processor will halt. Once a bus error exception has occurred, any bus error exception occurring before the execution of the next instruction constitutes a double bus fault. Note that a bus cycle which is re-run does not constitute a bus error exception, and does not contribute to a double bus fault. Note also that this means that as long as the external hardware requests it, the processor will continue to re-run the same bus cycle. The bus error pin also has an effect on processor operation after the processor receives an external reset input. The processor reads the vector table after a reset to determine the address to start program execution. If a bus error occurs while reading the vector table (or at any time before the first instruction is executed), the processor reacts as if a double bus fault has occurred and it halts. Only an external reset will start a halted processor. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 565 RESET OPERATION The reset signal is a bidirectional signal that allows either the processor or an external signal to reset the system. Figure 35 is a timing diagram for the reset operations. Both the halt and reset lines must be asserted to ensure total reset of the processor. When the reset and halt lines are driven by an external device, it is recognized as an entire system reset, including the processor. The processor responds by reading the reset vector table entry (vector unumber zero, address $000000) and loads it into the supervisor stack pointer (SSP). Vector table entry number one at address $000004 is read next and loaded into the program counter. The processor initializes the status register to an interrupt level of seven. No other CLK registers are affected by the reset sequence. When a RESET instruction is executed, the processor drives the reset pin for 124 clock periods. In this case, the processor is trying to reset the rest of the system. Therefore, there is no effect on the internal state of the processor. All of the processor's internal registers and the status register are unaffected by the execution of a RESET instruction. All external devices connected to the reset line should be reset at the completion of the RESET instruction. Asserting the Reset and Halt pins for 10 clock cycles will cause a processor reset, except when Vcc is initially applied to the processor. In this case, an external reset must be applied for 100 milliseconds. t > 100 M1lliseconds--l,...._ _ _ _ _ _ _ _ _ _ _ _ __ Bus Cycles 1-----1 t <4 !NOTES) 1) Internal start-up time 2) SSP High read in here 3) SSP Low read in here 4) PC High read in here 5) PC Low read in here 6) First instruction fetched here. i.111.-.l 12) 13) 14) (5) BusStateUnknown: ~ Figure 35 Reset Operation Timing Diagram THE RELATIONSHIP OF DTACK, BERR, AND HALT In order to properly control termination of a bus cycle for a re-run or a bus error condition, DTACK, BERR, and HALT should be asserted and negated on the rising edge of the 68000 clock. This will assure that when two signals are asserted simultaneously, the required setup time f11'4 7) for both of them will be met during the same bus state. This, or some equivalent precaution, should be designed external to the 68000. Parameter jj=48 is intended to ensure this operation in a totally asynchronous system, and may be ignored if the above conditions are met. The preferred bus cycle terminations may be summarized as follows (case numbers refer to Table 16): Normal Termination: DTACK occurs first (case 1). Halt Termination: RACT is asserted at the same time or before MACK and BERR remains negated (cases 2 and 3). Bus Error Termination: BERR is asserted in lieu of, at the same time, or before DTACK (case 4); BERR is negated at the same time or after DTACK. Re-Run Termination: HALT and BERR are asserted in lieu of, at the same time, or before DTACK (cases 6 and 7); HALT must be held at least one cycle after BERR. Case 5 in- dicates BERR may precede HALT which allows fully asynchronous assertion. Table 16 details the resulting bus cycle termination under various combinations of control signal sequences. The negation of these same control signals under several conditions is shown in Table 17 (DTACK is assumed to be negated normally in all cases; for best results, both DTACK and BERR should be negated when address strobe is negated.) Example A: A system uses a watch-dog timer to terminate ~ to un-populated address space. The timer asserts DTACK and BERR simultaneously after time-out. (case 4) Example B: A system uses error detection on RAM contents. Designer may (a) delay DTACK until data verified, and return BERR and HALT simultaneously to re-run error cycle (case 6), or if valid, return DTACK; (b) delay DTACK until data verified. and return BERR at same time as DTACK if data in error (case 4); (c) return DTACK prior to data verification, as described in previous section. If data invalid, BERR is asserted (case 1) in next cycle. Error-handling software must know how to recover error cycle. @HITACHI 566 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 16 DTACK, BERR, HALT Assertion Results Case No. Asserted on Rising Control Signal r--- __Ecj_ge_of_Sta~-------1 N N +2 Result 1 ---~' 2 DTACK BERR HALT DTACK BERR HALT A l--N~A- -+- [ NAA A S X Normal cycle terminate and continue. x - --+-------------------------------------- ~ Normal cycle terminate and halt. Continue when HALT removed. S DTACK NA A 3 BERR HALT NA NA Normal cycle ter-minate and halt. Continue when HALT removed. A s DTACK x 4 BERR A x S Terminate and take bus error trap. HALT NA NA --- -- -l-------+---~-----+---~---+----~----------------------- DTACK NA X 5 BERR A S Terminate and re·run. HALT NA A DTACK x x 6 BERR A S Terminate and re-run when HALT removed. HALT A S DTACK NA 7 BERR NA HALT A X A Terminate and re-run when HALT removed. S gend: N - The number of the current even bus state (e.g., S4, 56, etc.) A - Signal is asserted in this bus state NA - Signal is not asserted in this state X - Don't care S - Signal was asserted in previous state and remains asserted in this state Table 17 BERR and HALT Negation Results Conditions of Termination in Table A Bus Error Re-run Re-run Normal Normal Control Signal BERR HALT BERR HALT BERR HALT BERA HALT BERR HALT Negated on Rising Edge of State N N +2 · · or or · · ·· or · · · ·· or · · · or none Results - Next Cycle Takes bus error trap. Illegal sequence; usually traps to vector number 0. Re-runs the bus cycle. May lengthen next cycle. If next cycle is started it will be terminated as a bus error. ASYNCHRONOUS VERSUS SYNCHRONOUS OPERATION Asynchronous Operation To achieve clock frequency independence at a system level, the 68000 can be used in an asynchronous manner. This entails using only the bus handshake lines (AS, UOS, LOS, OTACK, BERR, HALT, and VPA) to control the data transfer. Using this method, AS signals the start of a bus cycle and the data strobes are used as a condition for valid data on a write cycle. The slave device (memory or peripheral) then responds by placing the requested data on the data bus for a read cycle or latching data on a write cycle and asserting the data transfer acknowledge signal (IYTACK) to terminate the bus cycle. If no slave responds or the access is invalid, external control logic asserts the BERR, or BERR and HALT, signal to abort or re-run the bus cycle. The OTACK signal is allowed to be asserted before the data from a slave device is valid on a read cycle. The length of time that OTACK may precede data is given as parameter #31 and it must be met in any asynchronous system to insure that valid data is latched into the processor. Notice that there is no maximum time specified from the assertion of AS" to the asser- tion of OTACK. This is because the MPU will insert wait cycles of one clock period each until OTACK is recognized. The BERR signal is allowed to be asserted after the OTACK signal is asserted. SERR must be asserted within the time given as parameter #48 after [)TACK is asserted in any asynchronous @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 567 system to insure proper operation. If this maximum delay time is violated, the processor may exhibit erratic behavior. Synchronous Operation To allow for those systems which use the system clock as a signal to generate lTI'ACR: and other asynchronous inputs, the asynchronous input setup time is given as parameter #4 7. If this setup is met on an input, such as i'YfACK, the processor is guaranteed to recognize that signal on the next falling edge of the system clock. However, the converse is not true - if the input signal does not meet the setup time it is not guaranteed not to be recognized. In addition, if DTACK is recognized on a falling edge, valid data will be latched into the processor (on a read cycle) on the next falling edge provided that the data meets the setup time given as parameter #27. Given this, parameter #31 may be ignored. Note that if DTACK is asserted, with the required setup time, before the falling edge of S4, no wait status will be incurred and the bus cycle will run at its maximum speed of four clock periods. In order to assure proper operation in a synchronous system when BERR is asserted after DT ACK. BERR must meet the setup time parameter #27A prior to the falling edge of the clock one clock cycle after DTACK was recogniLed. This setup time is critical to proper operation, and the HD68000 may exhibit erratic behavior if it is violated. (NOTE) During an active bus cycle. VPA and BERR arc sampled on every falling edge of the ciDck starting with SO. DT ACK is sampled Dn every falling edge of the clock starting with S4 and data is latched on the falling edge Df S6 during a read. The bus cycle will then be terminated m S7 except when BERR is asserted in the absence of OT ACK, in which case it will terminate one clock cycle later in S9. · PROCESSING STATES This section describes the actions the 68000 which are out- side the normal processing associated with the execution of instructions. The functions of the bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace enable bit, and the processor interrupt priority mask. Finally, the sequence of memory references and actions taken by the processor on exception conditions is detailed. The 68000 is always in one of three processing states: normal. exception, or halted. The normal processing state is that associated with instruction execution: the memory references are to fetch instructions and operands, and to store results. A special case of the normal state is the stopped state which the processor enters when a STOP instruction is executed. In this state, no further memory references are made. The exception processing state is associated with interrupts, trap instructions, tracing and other exceptional conditions. The exception may be internally generated by an instruction or by an unusual condition arising during the execution of an instruction. Externally. exception processing can be forced by an interrupt, by a bus error, or by a reset. Exception processing is designed to provide an efficient context switch so that the processor may handle unusual conditions. The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a processor in the stopped state is not in the halted state, nor vice versa. PROCESSING STATES NORMAL EXCEPTION HALTED INSTRUCTION EXECUTION (INCLUDING STOP) INTERRUPTS TRAPS TRACING ETC. HARDWARE HALT DOUBLE BUS FAULT · PRIVILEGE STATES The processor operates in one of two states of privilege: the "user" state or the "supervisor" state. The privilege state determines which operations are legal, are used to choose between the supervisor stack pointer and the user stack pointer in instruction references, and may be used by an external memory management device to control and translate accesses. The privileges state is a mechanism for providing security in a computer system. Programs should access only their own code and data areas, and ought to be restricted from accessing information which they do not need and must not modify. The privilege mechanism provides security by allowing most programs to execute in user state. In this state, the accesses are controlled, and the effects on other parts of the system are limited. The operating system executes in the supervisor state, has access to all resources, and performs the overhead tasks for the user state programs. SUPERVISOR STATE The supervisor state is the higher state of privilege. For instruction execution, the supervisor state is determined by the S-bit of the status register; if the S-bit is asserted (high), the processor is in the supervisor state. All instructions can be executed in the supervisor state. The bus cycles generated by instructions executed in the supervisor state are classified as supervisor references. While the processor is in the supervisor privilege state, those instructions which use either the system stack pointer implicitly or address register 'seven explicitly access the supervisor stack pointer. All exception processing is done in the supervisor state, regardless of the setting of the S-bit. The bus cycles generated during exception processing are classified as supervisor references. All stacking operations during exception processing use the supervisor stack pointer. USER STATE The user state is the lower state of privilege. For instruction execution, the user state is determined by the S-bit of the status register; if the S-bit is negated (low), the processor is executing instructions in the user state. Most instructions execute the same in user state as in the supervisor state. However, some instructions which have important system effects are made privileged. User programs are not permitted to execute the STOP instruction, or the 568 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 RESET instruction. To ensure that a user program cannot enter the supervisor state except in a controlled manner, the instructions which modify the whole status register are privileged. To aid in debugging programs which are to be used as operating systems, the move to user stack pointer (MOVE to USP) and move from user stack pointer (MOVE from USP) instructions are also privileged. The bus cycles generated by an instruction executed in user state are classified as user state references. This allows an external memory management device to translate the address and to control access to protected portions of the address space. While the processor is in the user privilege state, those instructions which use either the system stack pointer im· plicitly, or address register seven explicitly, access the use stack pointer. PRIVILEGE STATE CHANGES Once the processor is in the user state and executing instruc- tions, only exception processing can change the privilege state. During exception processing, the current setting of the S-bit of the status register is saved and the S-bit is asserted, putting the processing in the supervisor state. Therefore, when instruction execution resumes at the address specified to process the exception, the processor is in the supervisor privilege state. USER/SUPERVISOR MODES TRANSITION ONLY MAY OCCUR DURING EXCEPTION PROCESSING SUPER· VISOR STATE TRANSITION MAY BE MADE BY: RTE; MOVE, ANDI, EORI TO STATUS WORD REFERENCE CLASSIFICATION When the processor makes a reference, it classifies the kind of reference being made, using the encoding on the three function code output lines. This allows external translation of addresses, control of access, and differentiation of special processor states, such as interrupt acknowledge. Table 18 lists the classification of references. Table 18 Reference Classification Function Code Output FC2 FC 1 FCo 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Reference Class (Unassigned) User Data User Program (Unassigned) (Unassigned) Supervisor Data Supervisor Program Interrupt Acknowledge · EXCEPTION PROCESSING Before discussing the details of interrupts, traps, and tracing, a general description of exception processing is in order. The processing of an exception occurs in four steps, with variations for different exception causes. During the first step, a temporary copy of the status register is made, and the status register is set for exception processing. In the second step the exception vector is determined, and the third step is the saving of the current processor context. In the fourth step a new context is obtained, and the processor switches to instruction processing. EXCEPTION VECTORS Exception vectors are memory locations from which the processor fetches the address of a routine which will handle that exception. All exception vectors are two words in length (Figure 36), except for the reset vector, which is four words. All exception vectors lie in the supervisor data space, except for the reset vector which is in the supervisor program space. A vector number is an eight-bit number which, when multiplied by four, gives the address of an exception vector. Vector numbers are generated internally or externally depending on the cause of the exception. In the case of interrupts, during the interrupt acknowledge bus cycle, a peripheral provides an 8-bit vector number (Figure 37) to the processor on data bus lines D0 through D7 . The processor translates the vector number into a full 24-bit address, as shown in Figure 38. The memory layout for exception vectors is given in Table 19. As shown in Table 19, the memory layout is 512 words Jong (1024 bytes). It starts at address 0 and proceeds through address 1023. This provides 255 unique vectors; some of these are reserved for TRAPS and other system functions. Of the 255, there are 192 reserved for user interrupt vectors. llowevn. there is no protection on the first 64 entries, so user interrupt vectors may overlap at the discretion of the systems designer. KINDS OF EXCEPTIONS Exceptions can be generated by either internal or external causes. The externally generated exceptions are the interrupts and the bus error and reset requests. The interrupts are requests from peripheral devices for processor action while the bus error and reset inputs are used for access control and processor restart. The internally generated exceptions come from instructions, or from address error or tracing. The trap (TRAP), trap on overflow (TRAPV), check register against bounds (CHK) and divide (DIV) instructions all can generate exceptions as part of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege violations cause exceptions. Tracing behaves like a very high priority, internally generated interrupt after each instruction execution. EXCEPTION PROCESSING SEQUENCE Exception processing occurs in four identifiable steps. In the first step, an internal copy is made of the status register. After the copy is made, the S-bit is asserted, putting the processor into the supervisor privilege state. Also, the T-bit is negated which will allow the exception handler to execute unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is also updated. In the second step, the vector number of the exception is determined. For interrupts, the vector number is obtained by a processor fetch, classified as an interrupt acknowledge. For all other exceptions, internal logic provides the vector number. This vector number is then used to generate the address of the exception vector. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 569 570 WordO New Program Counter {High) A0=0,A1=0 Word 1 New Program Counter (Low) AO=O, A1 =1 Figure 36 Exception Vector Format D15 DB D7 DO Ignored Where: v7 is the MSB of the Vector Number vO is the LSB of the Vector Number Figure 37 Peripheral Vector Number Format A23 A10 A9 AB A7 A6 A5 A4 A3 A2 A1 AO AH Zeroes Figure 38 Address Translated From 8-Bit Vector Number Table 19 Exception Vector Assignment Vector Number(s) 0 2 3 4 5 6 7 8 9 10 11 12* 13* 14* 15 16 - 23* 24 25 26 27 28 29 30 31 32 -47 48 -63* 64 - 255 Dec 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 95 96 100 104 108 112 116 120 124 128 191 192 255 256 1023 Address Hex 000 004 008 ooc 010 014 018 01C 020 024 028 02C 030 034 038 03C 040 05F 060 064 068 06C 070 074 078 07C 080 OBF oco OFF 100 3FF Space SP SP SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD Assignment Reset: Initial SSP Reset: Initial PC Bus Error Address Error Illegal Instruction Zero Divide CHK Instruction TRAPV Instruction Privilege Violation Trace line 1010 Emulator line 1111 Emulator (Unassigned, reserved) (Unassigned, reserved) (Unassigned, reserved) Uninitialized Interrupt Vector (Unassigned, reserved) Spurious Interrupt Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level .S Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector TRAP Instruction Vectors (Unassigned, reserved) User Interrupt Vectors SP: Supervisor program, SD: Supervisor data ·Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are reserved for future enhancements by Hitachi. No user peripheral devices should be assigned these numbers. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 The third step is to save the current processor status, except for the reset exception. The current program counter value and the saved copy of the status register are stacked using the supervisor stack pointer as shown in Figure 39. The program counter value stacked usually points to the next unexecuted instruction, however for bus error and address error, the value stacked for the program counter is unpredictable, and may be incremented from the address of the instruction which caused the error. Additional information defining the current context is stacked for the bus error and address error exceptions. The last step is the same for all exceptions. The new program counter value is fetched from the exception vector. The processor then resumes instruction execution. Then instruction at the address given in the exception vector is fetched, and normal instruction decoding and execution is started. 15 14 13 12 11 10 9 8 6 5 4 2 0 Lower Address Status Register Higher Address High - - - - Program Counter - - -- - - -- - - ---- ---- -- --- - - - - - - - - - - - - - - - - - - - - Low Figure 39 Exception Stack Order (Group 1, 2) Forct!SPurtou· !n1erru,:HVKIOr ln1ernally Figure 40 Exception Processing Sequence (Not Reset) .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 571 MULTIPLE EXCEPTIONS These paragraphs describe the processing which occurs when multiple exceptions arise simultaneously. Exceptions can be grouped according to their occurrence and priority. The Group 0 exceptions are reset, bus error, and address error. These exceptions cause the instruction currently being executed to be aborted, and the exeception processing to commence within two clock cycles. The Group I exceptions are trace and interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to execute to completion, but preempt the execution of the next instruction by forcing exception processing to occur (privilege violations and illegal instructions are detected when they are the next instruction to be executed). The Group 2 exceptions occur as part of the normal processing of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions are in thls group. For these exceptions, the normal execution of an instruction may lead to exception processing. Group 0 exceptions have highest priority, while Group 2 exceptions have lowest priority. Within Group 0, reset has highest priority, followed by address error and then bus error. Within Group l, trace has priority over external interrupts, which in turn takes priority over illegal instruction and privilege violation. Since only one instruction can be executed at a time, there is no priority relation within Group 2. The priority relation between two exceptions determines which is taken, or taken first, if the conditions for both arise simultaneously. Therefore, if a bus error occurs during a TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is aborted. In another example, if an interrupt request occurs during the execution of an instruction while the T-bit is asserted, the trace exception has priority, and is processed first. Before instruction processing resumes, however, the interrupt exception is also processed, and instruction processing commences finally in the interrupt handler routine. A summary of exception grouping and priority is given in Table 20. Table 20 Exception Grouping and Priority Group 0 1 2 Exception Reset Address Error Bus Error Trace Interrupt Illegal Privilege TRAP, TRAPV CHK, Zero Divide Processing Exception processing begins within two clock cycles. Exception processing begins before the next instruction Exception processing is started by normal instruction execution RECOGNITION TIMES OF EXCEPTIONS, HALT, AND BUS ARBITRATION END OF A CLOCK CYCLE RESET END OF A BUS CYCLE ADDRESSER ROA BUS ERROR HALT BUS ARBIJ"RATION END OF AN INSTRUCTION CYCLE TRACE EXCEPTION INTERRUPT EXCEPTIONS ILLEGAL INSTRUCTION UNIMPLEMENTED INSTRUCTION PRIVILEGE VIOLATION WITHIN AN INSTRUCTION CYCLE TRAP, TRAPV CHK ZERO DIVIDE · EXCEPTION PROCESSING DETAILED DISCUSSION Exceptions have a number of sources, and each exception has processing which is peculiar to it. The following paragraphs detail the sources of exceptions, how each arises, and how each is processed. RESET The reset input provides the highest exception level. The processing of the reset signal is designed for system initiation, and recovery from catastrophic failure. Any processing in progress at the time of the reset is aborted and cannot be recovered. The processor is forced into the supervisor state, and the trace state is forced off. The processor interrupt priority mask is set at level seven. The vector number is internally generated to reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions can be made about the validity of register contents, in particular the supervisor stack pointer, neither the program counter nor the status register is saved. The address contained in the first two words of the reset exception vector is fetched as the initial supervisor stack pointer, and the address in the last two words of the reset exception vector is fetched as the initial program counter. Finally, instruction execution is started at the address in the program counter. The power-up/restart code should be pointed to by the initial program counter. The RESET instruction does not cause loading of the reset vector, but does assert the reset line to reset external devices. Thls allows the software to reset the system to a known state and then continue processing with the next instruction. @HITACHI 572 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Start Double Bus Fault END Fetch Yes Vector No.1 Contents of VectOr No. 1 -+PC Yes Yes > - - - - - - - B u s Error Exception Processing ENO Figure 41 Reset Exception Processing INTERRUPTS Seven levels of interrupt priorities are provided. Devices may be chained externally within interrupt priority levels, allowing an unlimited number of peripheral devices to interrupt the processor. Interrupt priority levels are numbered from one to seven, with level seven being the highest priority. The status register contains a three-bit mask which indicates the current processor priority, and interrupts are inhibited for all priority levels less than or equal to the current processor priority. An interrupt request is made to the processor by encoding the interrupt request level on the interrupt request lines; a zero indicates no interrupt request. Interrupt requests arriving at the processor do not force immediate exception processing, but are made pending. Pending interrupts are detected between instruction executions. If the priority of the pending interrupt is lower than or equal to the current processor priority, execution continues with the next instruction and the interrupt exception processing is postponed. (The recognition of level seven is slightly different, as explained in a following paragraph.) If the priority of the pending interrupt is greater than the current processor priority, the exception processing sequence is started. First a copy of the status register is saved, and the privilege state is set to supervisor, tracing is suppressed, and the processor priority level is set to the level of the interrupt being acknowledged. The processor fetches the vector number from the interrupting device, classifying the reference as an interrupt acknowledge and displaying the level number of .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 573 the interrupt being acknowledged on the address bus. If external logic requests an automatic vectoring, the processor internally generates a vector number which is determined by the interrupt level number. If external logic indicates a bus error, the "interrupt is taken to be spurious, and the generated vector number references the spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the program counter and status register on the supervisor stack. The saved value of the program counter is the address of the instruction which would have been executed had the interrupt not been present. The content of the interrupt vector whose vector number was previously obtained is fetched and loaded into the program counter, and normal instruction execution commences in the interrupt handling routine. A flow chart for the interrupt acknowledge sequence is given in Figure 42, a timing diagram is given in Figure 43, and the interrupt exception timing sequence is shown in Figure 44. Table 21 Internal Interrupt Level Level 12 7 1 6 1 5 1 4 1 3 0 11 1 1 0 0 1 10 1 0 1 0 1 l Interrupt Non-Maskable Interrupt M·""''' ' ore""' 2 0 1 0 1 0 0 1 0 0 0 0 No Interrupt (NOTE) The internal interrupt mask level 02, 11, 10) are inverted to the logic level applied to the pins ffJ1[ 2 · TPT1 , fi5I'0 ). CLK PROCESSOR INTERRUPTING DEVICE Request Interrupt Grant Interrupt 1) Compare interrupt level in status register and wait for current instruction to complete 2) Place interrupt level on A 1 , A 2 , A 3 3) Set R/W to read 4) Set function code to interrupt acknowledge 5) Assert address strobe (A'S) 6) Assert lower data strobe (O'OS* and I:OSI I Provide Vector Number 1) Place vector number of 0 0 - D1 2) Assert data transfer acknowledge (DTACKI I i Acquire Vector Number 1 ) Latch vector number 21 Negate ODS· and roS" 3) Negate AS ~1-------,i Release 1) Negate DTACK ! Start Interrupt Processing *Although a vector number is one byte, both data strobes ere asse!ted due to the microcode used for exception processm_g. The processor does not recognize anything on data Imes Da through Du at this time. Figure 42 Interrupt Acknowledge Sequence Flow Chart As~'-----' UDS* LOS R/W DTACK '""--'\.....___ _, \ \ - - -'-,-'--_--_-_-_-,; ')r---------c\.~._-_--_-_-_,r --, 1---------~ \ I __ \,,_ _,/ \____F \___ Do - D, ------< D '-------- FC, IPL, -- IFPC,L::,:::~:x------------~~,~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~:;7...------------ Last Bus Cycle of Instruction I· ·I· ·l~SSP~ I· ·I· (Read or Write) Idle Stack IACK Cycle PCL (Vector Number Acquisition) 4 Clocks Idle Stack and Vector Fetch · Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not recognize anything on data lines Da through D 15 at this time. Figure 43 Interrupt Acknowledge Sequence Timing Diagram 574 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Last Bus Cycle of Instruction (During Which Interrupt Was Recognized) I-- Stack PCL (SSP-21 IACK 1--1 I - - Cycle (Vector Number Acquisition) Stack Status (SSP-61 t-----1 Stack PCH ISSP-41 t--i .__ Read Vector High (A,, - An) t-----1 Read Vector Low (Ao -Au) Fetch First Word t---- of Instruction of Interrupt Routine Note: SSP refers to the value of the supervisor stack pointer before the interrupt occurs. Figure 44 Interrupt Exception Timing Sequence Priority level seven is a special case. Level seven interrupts cannot be inlubited by the interrupt priority mask, thus providing a "non-maskable interrupt" capability. An interrupt is generated each time the interrupt request level changes from some lower level to level seven. Note that a level seven interrupt may still be caused by the level comparison if the request level is a seven and the processor priority is set to a lower level by an instruction. UNINITIALIZED INTERRUPT An interrupting device asserts VPA or provides an interrupt vector during an interrupt acknowledge cycle to the 68000. If the vector register has not been initialized, the responding HD68000 Family peripheral will provide vector 15, the unitialized interrupt vector. This provides a uniform way to recover from a programming error. SPURIOUS INTERRUPT If during the interrupt acknowledge cycle no device responds by asserting DTACK or VPA, the bus error line should be asserted to terminate the vector acquisition. The processor separates the processing of this error from bus error by fetching the spurious interrupt vector instead of the bus error vector. The processor then proceeds with the usual exception processing. INSTRUCTION TRAPS Traps are exceptions caused by instructions. They arise either from processor recognition of abnormal conditions during instruction execution, or from use of inst\Uctions whose normal behavior is trapping. Some instructions are used specifically to generate traps. The TRAP instruction always forces an exception, and is useful for implementing system calls for user programs. The TRAPV and CHK instructions force an exception if the user program detects a runtime error, which may be an arithmetic overflow or a subscript out of bounds. The signed divide (DNS) and unsigned divide (DNU) instructions will force an exception if a division operation is attempted with a divisor of zero. ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS Illegal instruction is the term used to refer to any of the word bit patterns which are not the bit pattern of the first word of a legal instruction. During instruction execution, if such an instruction is fetched, an illegal instruction exception occurs. Word patterns with bits 15 through 12 equaling 1010 or 1111 are distinguished as unimplemented instructions and separate exception vectors are given to these patterns to permit efficient emulation. This facility allows the operating system to detect program errors, or to emulate unimplemented instructions in software. ILLEGAL INSTRUCTION EXAMPLE MOVE DO, #$1000 + MOVE OP WORD 0011 T MOVE WORD 100111 t * 000 t IMMEDIATE DATA REGISTER DIRECT - +000 - REGISTER NUMBER "O" PRIVILEGE VIOLATIONS In order to provide system security, various instructions are privileged. An attempt to execute one of the privileged instructions while in the user state will cause an exception. The privileged instruction are: STOP AND (word) Immediate to SR RESET EOR (word) Immediate to SR RTE OR (word) Immediate to SR MOVE to SR MOVE USP TRACING To aid in program development, the 68000 includes a facility to allow instruction by instruction tracing. In the trace state, after each instruction is executed an exceptions is forced, allowing a debugging program to monitor the execution of the program under test. The trace facility uses the T-bit in the supervisor portion of the status register. If the T-bit is negated (off), tracing is disabled, and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at the beginning of the execution of an instruction, a trace exception will be generated after the execution of that instruction is completed. If the instruction is not executed. either because an interrupt is taken, or the instruction is illegal or privileged, the trace exception does not occur. The trace exception also does not occur if the instruction is aborted by a reset, bus @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 575 error, or address error exception. If the instruction is indeed executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If, during the execution of the instruction, an exception is forced DY that instruction, the forced exception is processed before the trace exception. As an extreme illustration of the above rules, consider the arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First the trap exception is processed, then the trace exception, and finally the interrupt exception. Instruction execution resumes in the interrupt handler routine. IF T = 1 TRACE MODE STATUS REGISTER AODRESS OBTAINED FROM VECTOR TABLE RETURN TO EXECUTE NEXT INSTRUCTION 1. If, upon completion of an instruction, T = 1, go to trace exception processing. 2. Execute trace exception sequence. 3. Execute trace service routine. 4. At the end of the service routine, execute return from exception (RTE). BUS ERROR Bus error exceptions occur when the external logic requests that a bus error be processed by an exception. The current bus cycle which the processor is making is then aborted. Whether the processor was doing instruction or exception processing, that processing is terminated, and the processor immediately begins exception processing. Exception processing for bus error follows the usual sequence of steps. The status register is copied, the supervisor state is entered, and the trace state is turned off. The vector number is generated to refer to the bus error vector. Since the processor was not between instructions when the bus error exception request was made, the context of the processor is more detailed. To save more of this context, additional information is saved on the supervisor stack. The program counter and the copy of the status register are of course saved. The value saved for the program counter is advanced by some amount, one to five words beyond the address of the first word of the instruction which made the reference causing the bus error. If the bus error occurred during the fetch of the next instruction, the saved program counter has a value in the vicinity of the current instruction, even if the current instruction is a branch, a jump, or a return instruction. Besides the usual information, the processor saves its internal copy of the first word of the instruction being processed, and the address which was being accessed by the aborted bus cycle. Specific information about the access is also saved: whether it was a read or a write, whether the processor was processing an instruction or not, and the classification displayed on the function code outputs when the bus error occurred. The processor is processing an instruction if it is in the normal state or processing a Group 2 exception; the processor is not processing an instruction if it is processing a Group 0 or a Group I exception. Figure 45 illustrates how this information is organized on the supervisOr stack. Although this information is not sufficient in general to effect full recovery from the bus error, it does allow software diagnosis. Finally, the processor commences ir:istruction processing at the acldress contained in the vector. It is the responsibility of the error handler routine to clean up the stack and determine where to continue execution. If a bus error occurs during the exception processing for a bus error, address error, or reset, the processor is halted, and all processing cases. This simplifies the detection of catastrophic system failure, since the processor removes itself from the system rather than destroy all memory contents. Only the RES pin can restart a halted processor. ADDRESS ERROR Address error exceptions occur when the processor attempts to access a word or a long word operand or an instruction at an odd address. The effect is much like an internally generated bus error, so that the bus cycle is aborted, and the processor ceases whatever processing it is currently doing and begins exception processing. After exception processing commences, the sequence is the same as that for bus error including the information that is stacked, except that the vector number refers to the address error vector instead. Likewise, if an address error occurs during the exception processing for a bus error, address error, or reset, the processor is halted. As shown in Figure 46, an address error will execute a short bus cycle followed by exception processing. @HITACHI 576 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 15 14 13 12 11 10 9 8 6 4 3 2 0 Lower Address Function Code High 1-- - ·Access Address-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Low Instruction Register Status Register High r- -Program Counter·-- - - --- ---- --- ------- --- --- ----- -- Low R/W (read/write): write== 0, read= 1. l/N (instruction/not): instruction':= 0, not= 1 Figure 45 Exception Stack Order (Group 0) CLK ~---~~------;:=~~~------::~--._:....----~;-----~ iJD!l -----~ iN-----~ 5TR/WACi(----------- Do - Du ----------- Write Stack - - - - + Figure 46 Address Error Timing · INTERFACE WITH HD6800 PERIPHERALS Hitachi's extensive line of HD6800 peripherals are directly compatible with the 68000. Some of these devices that are particularly useful are: HD682 l Peripheral Interface Adapter HD6840 Programmable Timer Module HD6843 Floppy Disk Controller HD6845S CRT Controller HD46508 Analog Data Acquisition Unit HD6850 Asynchronous Communication Interface Adapter HD6852 Synchronous Serial Data Adapter To interface the synchronous HD6800 peripherals with the asynchronous 68000, the processor modifies its bus cycle to meet the HD6800 cycle requirements whenever an HD6800 device address is detected. This is possible since both processors use memory mapped I/O. Figure 48 is a flow chart of the interference operation between the processor and HD6800 devices. · DATA TRANSFER OPERATION Three signals on the processor provide the HD6800 interface. They are enable (E), valid memory address (VMA), and valid peripheral address (VPA). Enable corresponds to the E or ¢ 2 signal in existing HD6800 systems. The bus frequency is one tenth of the incoming 68000 clock frequency. The timing of E allows 1 MHz peripherals to be used with an 8 MHz 68000. Enable has a 60/40 duty cycle; that is, it is low for six input clocks and high for four in~locks. This duty cycle allows the processor to do successive VPA accesses on successive E pulses. HD6800 cycle timing is given in Figures 49 and 50. At state zero (SO) in the cycle, the address bus is in the high-impedance state. A function code is asserted on the function code output lines. One-half clock later, in state 1 the address bus is released from the high-impedance state. During state 2, the address strobe (AS) is asserted to indicate tnat there is a valid address on the address bus. If the bus cycle is a read cycle, the upper and/or lower data strobes are also asserted in state 2. If the bus cycle is a write cycle, @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 577 Address Bus AS 68000 \/PA VMA E Address & CS's cs Block of HD6800 Devices cs E Figure 47 Connection of HD6800 Peripherals the read/write (R/W) signal is switched to low (write) during state 2. One half clock later, in state 3, the write data is placed on the data bus, and in state 4 the data strobes are issued to indicate valid data on the data bus. The processor now inserts wait states until it recognizes the assertion of VPA. The VPA input signals the processor that the address on the bus is the address of an HD6800 device (or an area reserved for HD6800 devices) and that the bus should conform to the ¢ 2 transfer characteristics of the HD6800 bus. Valid peripheral address is derived by decoding the address bus, conditioned by address strobe. Chip select for the HD6800 peripherals should be derived by decoding the address bus conditioned by VMA. After the recognition of VPA, the processor assures that the Enable~s low, by waiting if necessary, and subsequently asserts VMA. Valid memory address is then used as part of the chip select equation of the peripheral. This ensures that the HD6800 peripherals are selected and deselected at the correct time. The peripheral now runs in cycle during the high portion of the E signal. Figures 49 and 50 depict the best and worst case HD6800 cycle timing. This cycle length is dependent strictly upon when VPA is asserted in relationship to the E clock. dependent strictly upon when VPA is asserted in relationship to the E clock. If we assume that external circuitry asserts WA as soon as possible after the assertion of AS. then VPA will be recognized as being asserted on the falling edge of S4. In this case. no ..extra'' wait cycles will be inserted prior to the recognition of VPA asserted and only the wait cycles inserted to synchronize with the E clock will determine the total length of the cycle. In any case. the synchronization delay will be some integral number of clock cycles withi.n the following two extremes: I. Best Case - VPA is recognized as being asserted on the falling edge three clock cycles before E rises (or three clock cycles after E falls). 2. Worst Case -- VPA is recog11ized as being asserted on the falling edge two clock cycles before E rises(or four clock cycles after E falls). During a read cycle, the processor latches the peripheral data in state 6. For all cycles, the processor negates the address and data strobes one half clock cycle later in state 7, and the Enable signal goes low at this time. Another half clock later, the address bus is put in the high-impedance state. During a write cycle, the data bus is put in the high-impedance state PROCESSOR SLAVE Initiate Cycle 1) The processor starts a normal Read or Write cycle Define HDSBOO Cycle 1) External hardware asserts Valid Peripheral Address (VPAI ! Synchronize With Enable 1) The processor monitors Enable (El until it is low (Phase 11 2) The processor asserts Valid Memory Address (VMA) Transfer Data 1) The peripheral waits until E is active and then transfers the data ! Terminate Cycle 1) The processor waits until E goes low. (On a Read cycle the data is latched as E goes low internally) 2) The processor negates VMA 3) The processor negates AS. UDS. and LOS ! Start Next Cycle Figure 48 HD6800 Interface Flow Chart @HITACHI 578 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 so S2 S4 w w w w w w SS SO S2 CLK AS DTACK Data Ou Data In t - - - - - c : " ' - - - - - - - - - - - - - - - - ; : : = : = : = : = : : : ; _ >e:: FC0-FC2::::><_______________________________________ VVMPAEA==~~~~~~:,~::;\.'=~=-=-=--=-=-----------------------~-,-r----~-·r--'\-.-_ Figure 49 68000 to HD6800 Peripheral Timing-Best Case ~~~wwwwwwwwwwwwwww~~ Data Out----c FC0-Fe_ C2~..._ ...--_ ---__-,/------\-_ --_ ---_--_ --!----'f:L._ Figure 50 68000 to HD6800 Peripheral Timing-Worst Case .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 579 HD68000/HD68HCOOO---------------------------- 68000 CLK HMCS6800 VMA, R/W HM1C5S6080n0o' ~TypeB 180 n1 Type A . - - - - - 270 n1 Std t=Ptri7p0hensr1~·1 Type B 140 nt Type A 140n1 Std HMCS6800 E Clock Froq. 2.0 MHz 1.6 MHz 1.0 MHz Type B A Std ~"""""""""""''--------------- HMCS6800 Addrtu .-.j ~ 10 ns HMCS68001 --i I.- 1O ns Peripheral" Ptriphtr11 · Type B ~ 180 n1~ Type A 220 nt HMCS6800Read om -------------@/j//;:~~0~0,;~/'/;~/Sftd;CL:;/f;~32~0Z":' ;y/;~ML__ I--- ~ 10 no HMCS6800' _µI r-)-1"------ .......j 10 n1 Ptr1pli1r11 Type a E:=P·r·:·~:'3' I Type A 80 ns Std 195 n1 HMCS6800WriteDat· ----------------ez~ ) eaoooAdd«" ~..W......l._/ ________________________J)~------- \ 68000 (8 MHz) f.o--200 "'~ ·Times are expressed for different device dock frequencies Figure 51 68000 to HD6800 Peripheral Timing Diagram 3.Jk ·5V 0 0 - D,, A, , A,, 68000 c 0 ' HD6821 PIA ~ ~ ~ E R/W 580 R/W Figure 52 HD6800 Interface-Example 1 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ::c: =~ . )> ~ :::!. "Ic»: ?- · N N 0 0 t@ ~ :c ~ ~ <D - :c0 Ul ~ '- §l !" {) )> <D ."~' ~ 0 ~ .I> f c.:l 8 (J1 CXl AS r'VMA Oo-01~ Ai-An 68000 [ilj I · I i> . 1 I~ < ~. 74LS A 138 B c 3.3k +5 1~1~1; w 1~ -- 6800Addrno s " I 81., :<Ii <O > 0 ~ '<!.7 CS, CS, CS, RS HD6850 ACIA 1!!1 I~ w a: RES R/W '·--'·r 74LS 348 "Ll '·r--1 I· l,~NMI 1, . +5 33k [ ~ Figure 53 HD6800 Interface-Example 2 :cI: CJ) co -- ~ :cI: CJ) co :I: (") § and the read/write signal is switched high. The peripheral logic must remove VPA within one clock after address strobe is negated. Figure 51 shows the timing required by HD6800 peripherals, th.e timing specified for HD6800, and the corresponding timing for the 68000. Two example systems with HD6800 peripherals are shown in Figures 52 and 53. The system in Figure 52 reserves the upper eiglit megabytes of memory for HD6800 peripherals. The system in Figure 53 is more efficient with memory and easily expandable, but more complex. DTACK should not be asserted while VPA is asserted. Notice that the 68000 WA is active low, contrasted with the active high HD6800 VMA. This allows the processor to put its buses in the high-impedance state on OMA requests without inadvertently selecting peripherals. · INTERRUPT OPERATION During an interrupt acknowledge cycle while the processor is fetching the vector, if VPA is asserted, the 68000 will assert VMA and complete a normal HD6800 read cycle as shown in Figure 54. The processor will then use an internally generated SO S2 54 56 58 SO S2 S4 Sw --------cc::::::J~-----------------~ -~~~~~-ic::::::J~~~~~~~~~~~~~~~~~~- Low ~~~~~::ng--+--Pc Stacking-oof+------Autovector Operation---------i.-~~:e"~:ng * Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not recognize anything on data lines De through 0 15 at this time. Figure 54 Autovector Operation Timing Diagram vector that is a function of the interrupt being serviced. This process is known as autovectoring. The seven autovectors are vector numbers 25 through 31 (decimal). This operates in the same fashion (but is not restricted to) HD6800 interrupt sequence. The basic difference is that there are six normal interrupt vectors and one NMI type vector. As with both the HD6800 and the 68000's normal vectored interrupt, the interrupt service routine can be located anywhere in the address space. This is due to the fact that while the vector numbers are fixed, the contents of the vector table entries are assigned by the user. Since VMA is asserted autovectoring, the HD6800 peripheral address decoding should prevent unintended accesses. · CONDITION CODES COMPUTATION This provides a discussion of how the condition codes were developed, the meanings of each bit, how they are computed, and how they are represented in the instruction set details. · CONDITION CODE REGISTER The condition code register portion of the status register con- tains five bits: N - Negative Z - Zero V - Overflow C - Carry X - Extend The first four bits are true condition code bits in that they reflect the condition of the result of a processor operation. The X·bit is an operand for multiprecision computations. The carry bit (C) and the multiprecision operand extend bit (X) are separate in the 68000 to simplify the programming model. ~HITACHI 582 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · CONDITION CODE REGISTER NOTATION In the instruction set details, the description of the effect on the condition codes is given in the following form: Condition Codes: x N z v c Where N (negative) set if the most significant bit of the result is set. Cleared otherwise. Z (zero) set if the result equals zero. Cleared otherwise. V (overflow) set if there was an arithmetic overflow. This implies that the result is not representable in the operand size. Cleared otherwise. C (carry) set if a carry ls generated out of the most significant bit of the operands for an addition. Also set if a borrow is generated in a subtrac- tion. Cleared otherwise. X (extend) transparent to data movement. When affected, it is set the same as the C-bit. The notational convention that appears in the representation of the condition code registers is: · set according to the result of the operation not affected by the operation 0 cleared I set U undefined after the operation · CONDITION CODE COMPUTATION Most operations take a source operand and a destination operand, compute, and store the result in the destination location. Unary operations take a destination operand, compute, and store the result in the destination location. Table 22 details how each instruction sets the condition codes. Table 22 Condition Code Computations Operations ABCD ADD.ADDI. ADDO ADDX xN z v c u u AND, ANDI. EOR. EORI, MOVEO. MOVE. OR.ORI, CLR. EXT. NOT. TAS. TST CHK sue. SUBI SUBQ SUBX 0 0 u u u CMP,CMPI. CMPM DIVS.DIVU MULS.MULU SBCD.NBCD NEG NEGX BTST,BCHG. BSET,BCLR ASL 0 0 0 u u ASL Ir= 01 LSL, ROXL LSR lr·OI ROXL (r= OI ROL ROL (r·OI ASR, LSR, ROXR ASR. LSR Ir= OI ROXR (r-01 ROR ROR (r ·0) - Not 8ff9CtMI U Undllfintd 1 Other- . . Specie! Definition 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 ? 0 0 · General Case: X·C N·Rm Z·Rin· ... ·fln Special Definition C = Decimal Carry Z = Z ·Rm· ... · RO V=Sm·Dm·Rm+Sm·Om·Rm C = Sm · Om + Rm · Om + Sm · Rm V = Sm · Om · lfrii + Sm · Om · Rm C = Sm · Om + Rm · Om + Sm · Rm Z = Z ·Rm· ... · RO V = Sm · Om · lfrii + Sm · Om · Rm C = Sm · Din+ Rm · Dm +Sm · Rm V =Sm · Om · Rm + Sm · Om · Rm C ·= Sm · Om+ Rm · Om + Sm · Rm Z =Z· Rm· ... · RO V = Sm· Om · lfrii + Sm · Om · Rm C = Sm · Om+ Rm · Om +Sm · Rm V = Division Overflow C = Decimal Borrow Z = Z ·Rm· ... · RO V = Om · Rm. C = Om+ Rm V = Dm.:.J!m, C =.Q.m +Rm Z = Z ·Rm· ... · RO z =!Jn V =Om· (Dm-1 + ... + ~) +Om · (Dm-t + ... + Dm-r) C = Dm-r+t C = Dm-r+t C=X C = Dm-r+t C=D,.1 C=X C =D,.1 Sm - Source operand most significant bit Om - Destination operand mon significant bit Rm - Result bit most significent bit n - bit number ' - shift ·mount @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 583 · CONDITIONAL TESTS Table 23 lists the condition names, encodings, and tests for the conditional branch and set instructions. The test associated with each condition is a logical formula based on the current state of the condition codes. If this formula evaluates to l, the condition succeeds, or is true. If the formula evaluates to 0, the condition is unsuccessful, or false. For example, the T condition always succeeds, while the EQ condition succeeds only if the Z bit is currently set in the condition codes. Mnemonic T F HI LS cc cs NE EQ vc vs PL Ml GE LT GT LE Table 23 Conditional Tests Condition true false high low or same carry clear carry set not equal equal overflow clear overflow set plus minus greater or equal less than greater than less or eq ua I Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Test 1 0 C·Z C+Z c· c z z v v N N N·V+N·V N·V+llf·V N·V·Z+N·V·Z Z+N·V+N·V · INSTRUCTION SET The following paragraphs provide information about the addressing categories and instruction set of the 68000. · ADDRESSING CATEGORIES Effective address modes may be categorized by the ways in which they may used. The following classifications will be used in the instruction definitions. Data If an effective address mode may be used to refer to data operands, it is considered a data address- ing effective address mode. Memory If an effective address mode may be used to refer to memory operands, it is considered a memory addressing effective address mode. Alterable If an effective address mode may be used to refer to alterable (writeable) operands, it is considered an alterable addressing effective address mode. Control If an effective address mode may be used to refer to memory operands without an associated size, it is considered a control addressing effective address mode. Table 24 shows the various categories to which each of the effective address modes belong. Table 25 is the instruction set summary. The status register addressing mode is not permitted unless it is explicitly mentioned as a legal addressing mode. These categories may be combined so that additional, more restrictive, classifications may be defined. For example, the instruction descriptions use such classifications as alterable memory or data alterable. The former refers to those addressing modes which are both alterable and memory addresses, and the latter refers to addressing modes which are both data and alterable. · INSTRUCTION PRE-FETCH The 68000 uses a 2-word tightly-coupled instruction prefetch mechanism to enhance performance. This mechanism is described in terms of the microcode operations involved. If the execution of an instruction is defined to begin when the microroutine for that instruction is entered, some features of the prefetch mechanism can be described. I) When execution of an instruction begins, the operation word and the word following have already been fetched. The operation word is in the instruction decoder. 2) In the case of multi-word instructions, as each addi· tional word of the instruction is used internally, a fetch is made to the instruction stream to replace it. 3) The last fetch from the instruction stream is made when the operation word is discarded and decoding is started on the next instruction. 4) If the instruction is a single-word instruction causing a branch, the second word is not used. But because this word is fetched by the preceding instruction, it is im· possible to avoid this superfluous fetch. In the case of an interrupt or trace exception, both words are not used. 5) The program counter usually points to the last word fetched from the instruction stream. 584 @HITACHI Hitachi America ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Effective Address Modes Dn An An@ An@+ An@An@(d) An@(d, ix) xxx.W xxx.L PC@(d) PC@(d, ix) #xxx Table 24 Effective Addressing Mode Categories Mode 000 001 010 011 100 101 110 111 111 111 111 111 Register Addressing Categories Data Memory Control Alterable register number x - register number - - register number x x - - --~--- register number x x register number x x register number x x register number x x 000 x x 001 x x - - x --- - I I - x ' ' x x x x x x x x I x x x x 010 x x x - 011 x x x - 100 x x - - The following example illustrates many of the features of instruction prefetch. The contents of memory are assumed to be as illustrated in Figure 55. ORG DC.L DC.L ORG DC.L ORG RESTART: NOP BRA.S ADD.W LABEL: SUB.W CMP.W SGE.B 0 INISSP RESTART INTVECTOR INTHANDLER LABEL DO, D1 OISP(AOI, A1 D2,D3 D7 DEFINE RESTART VECTOR INITIAL SYSTEM STACK POINTER RESTART SYSTEM ENTRY POINT DEFINE AN INTERRUPT VECTOR HANDLER ADDRESS FOR THIS VECTOR SYSTEM RESTART CODE NO OPERATION EXAMPLE SHORT BRANCH ADD REGISTER TO REGISTER SUBTRACT REGISTER INDIRECT WITH OFFSET COMPARE REGISTER TO REGISTER Sec TO REGISTER INTHANDLER: MOVE.W NOP SWAP.W LONGADR1, LONGADR2 MOVE WORD FROM AND TO LONG ADDRESS NO OPERATION REGISTER SWAP Figure 55 Instrvction Prefetch Example, Memory Contents The sequence we shall illustrate consists of the power-up reset, the execution of NOP, BRA, SUB, the taking of an interrupt, and the execution of the MOVE.W xxx. L to yyy.L. The order of operations described within each microroutine is not exact, but is intended for illustrative purpose only. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 585 HD68000/HD68HCOOO Microroutine Operation Reset NOP BRA SUB INTERRUPT MOVE Read Read Read Read Read Read <begin NOP> Read <begin BRA> PC=PC+d Read Read <begin SUB> Read Read Read <begin CMP> Write Read Write Write Read Read Read Read <begin MOVE> Read Read Read Read Write Read Read <begin NOP> Location 0 2 4 6 (PCI +(PC) +(PC) (PC) +(PCI +(PCI DISP(AO) +(PC) <take INT> -(SSP) <INT ACK> -(SSPI -(SSPI (VR) +(VRI (PC) +(PCI +(PC) +!PC) xxx +(PC) yyy1 +!PCI +(PC) Operand SSP High SSP Low PC High PC Low NOP BRA ADO SUB DISP CMP <src> SGE PC Low Vector# SR PC High PC High PC Low MOVE xxx High xxx Low VVV High <src> VVV Low <dest> NOP SWAP Figure 56 Instruction Prefetch Example · DATA PREFETCH Normally the 68000 prefetches only instructions and not data. However, when the MOVEM instruction is used to move data from memory to registers, the data stream is prefetched in order to optimize performance. As a result, the processor reads one extra word beyond the higher end of the source area. For example, the instruction sequence in Figure 57 will operate as shown in Figure 58. MOVEM.L A, 00/Dl MOVE TWO LONGWORDS INTO REGISTERS A DC.W 1 B DC.W 2 c DC.W 3 D DC.W 4 E DC.W 5 F DC.W 6 WORD 1 WORD2 WORD3 WORD4 WORD5 WORDS Figure 57 MOVEM Example, Memory Contents Assume Effective Address Evaluation is Already Done Microroutine Operation Location Other Operations MOVEM Read Raad Read Read Read A Prepare to Fill DO B A-+DOH c B -+DOL Prepare to Fill 01 D C-+DlH E D -+DlL Detect Register List Complete Figure 58 MOVEM Example, Operation Sequence 586 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 25 Instruction Set Mnemonic An (An) (An) + - (An) d(An) d(An, XI) Abs. W Abs. L d(PC) d(PC, Xi) ....OperatiOn Add Digits ADO Add ....Binary ="m""m~e"d". 'Ii!illiillllilililllllll~llliilllllillllll~liillilllllllilllilillllilliliillllil ADDO Add Quick ADDX ...AddMultl- preclsion Logic And Memory ICHG Tce.s.t.a,n.d ICLR aTe.s.t ,and .U.E.T... Sel mr ...BitTest Check Register Against Sounds CUI Clear Operand ........,CllP Compare Compare -Address CMomPpIare Imm'1.I111111111111111111111111111111111111111111111.i11111-.11111111111111..1111111111111111111111111..111111111111111111111111111..111111 Co""'~ ....:M!eelllQsiIYgnedm· m1111111111111111111.-1111111111111111111111-...............ll......illllllllllllllllllllllllllllllllllllll ...Divide Unsigned ....'L"og"ic"a"l "°" -...Exclusive OR Immediate Exchange EXT -Sign.Extend LEA Load Effect· Ive Address Link and Mocate Nott :Aet" to"Condtt1on Codi! Comou1at1ons u lor condihon Code · Word~y <:M·tftllll!lvllut l;NUll!Mrofl'nlll'.,.lytn -:NumbtrofCloc:l Per.- AAddrn1Ae111ter II C.TnlCOftdit1on D.0111 Afllller # t.SourceElltct111tAddrn1 E.D11hnat1011 Ellect1w1 Address Opcode Bit P·ttern Key 1.0ir..:11on.O-R11111. t-Lelt M. Oest1~11on EA Modi R.Oest<nat1an Aes1ste< S. Sou. 00 e,1e P.D11place-ment 01 Word Q. Qui<:~ lmmecllate 01t1 10-Long Word r.Souru Re11<$lfr IL· Another Ope·111on V.Veetorll [ . '""'"""") ""' '" ,01 Byre 10 Lo~ Word \l Word (to be i::olitinued) ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 587 Moomonlc Size Operation Addr. MOOe Ul, LSR logical Shift -Memo~ -Data On An # - ·# - (An) # - (An) + -(An) d(An) #- #-#- d(An, X1} Abs. W Abs. L d(PC) II - # - # - # - d(PC, X~ ~:1::· 1111 O~ode Bit Pattern II - # - 5432 1098 7654 3210 Boolean Coodillon Codes XNZVC --MMP -EQ MIMI Quick MULS --·MUW Muldpl>J ..._.. .... Unsigned H:EGiX eei8n'IIary·~~;;,'.;:f~if$$1J·················"~~·~~~~~J;·$i~it!!~~,~~,~~~~,,~~- ....,..,,NegatlveMulti L precisiOn Complement OR Inclusive OR loQlcal Note. Rele· to"Condtl·"" Code Computahons aslorcondlflonCDOe · Word onlr < Mot··ml>"' value #.Numbe< ol Procram Bytn ·.Number ol Clock Pertods e· Tt.MPUg-lh·oughanexira n.MrMClcyd91her 1mul11plolf'ucl 11done(ThelHI EA+2) A.Adclress A911st~ · C,TestCondih"" O,D1t1Ae11ster # eSourceEflec11veAddress E.Oes11...t1onEl!ec:11weAdclreu Opcode 8tt P·tt·m Key 1,Direct1on.D-A11ht. l .. Lelt M.Oest1nahon EA Mode A Oeshnahon Aec1sle· S S1z1,0D-Byte P.Oosplacement Q. Q111ck Immediate 0111 01·-Word LO-Lq Word r.Source A111ster \I-Another ()per1!>0n V,Vec:tor # (to be continued) 588 .HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Mnemonic Size Operation ROXR, ROXL Rotate throughX Memory SBCD Subtract digits 'S"· Add~ Mode On # - An # - (An) # - (An) + - (An) d(An) d(An, Xi) Abs. W Abs. L d(PC) #- #- #-#- #- #-#- d(PC, Xi) sd:I~;~~- 1111 Oi~ode Bit Pattern # - # - 5 4 3 2 1098 7 6 5 4 3 21 0 Subtract Binary SUBA Subtract Address SUBI Subtract Immediate suao Subtract Quick SUBX Subtract Boolean Condition Codes XN ZVC Decrement Counter & Branch Until Condition True or Count= 1 JMP Jump to JSR Jump to Subroutine NOP Note: Refer to"Cond1t1011 Code ComPl'l·l<ons 15forcondit1onCodt · Word only <.M..imumnlue #: Nwnbttt Of Procram 8ytn -:Number of Clock Periods A;A<ldrns A11·S1er II: C:TestCondttoon D.Data Ae1·ster II: e:Source E!l..:tin Address E.De-s!1nat1on Eltectove Address Opcode Bit P1ttern Key I: Oorect·on, O-Rr1tM. l -Left M. Oeslon;mon EA Mode R. Destmatoon Regoster S Size 00 B~te P.Orsp!a"menl Ol Word Q.Qu·tk lmmed·ate Dara r. Source Register 10-·Lons Word ll Anot~er Qperat·on V Vector II: In t~e MOVE [ 01 Byte 10-LonG Word ll Word @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 589 · INSTRUCTION FORMAT SUMMARY This provides a summary of the first word in each instruction of the instruction set. Table 26 is an operation code (op-code) map which illustrates how bits 15 through 12 are used to specify the operations. The remaining paragraph groups the instructions according to the op-code map. where, Size; Byte = 00 Sz; Word= 0 Word= 01 Long Word= I Long Word= 10 Table 26 Oper~ion Code Map Bits 15 thru i2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1r>10 1011 1100 1101 1110 1111 Operation Bit Manipulation/MOVEP/lmmediate Move Syte Mo9e Long Move Word Miscellaneous ADDQ/SUBQ/See/DBc:c Bee Move a OR/DIV/SBCD SUB/SU BX (Unassi~ned) CMP/EOR AND/MULiABCD/EXG ADD/ADDX Shift/Rotate (U nassighed) ~ (1) BIT MANIPULATION, MOVE l>ERIPHERAL, IMMEDIATE INSTRUCTIONS Dynamic Bit 15 14 13 12 11 10 9 8 6 54 32 0 I Jo L_._ 0 I 0 I 0 RegiSter I 1 Type Effective Address Static Bit 15 14 13 12 it tci 9 8 6 54 3 2 0 I I I I I I I 0 0 0 0 1 0 0 0 Type Effective Address Bit Type Codes: TST = 00, CHG =di, CLR =i 0, SET =11 MOVEP 15 14 13 12 11 iO 9 8 654 32 0 I I I 0 0 0 0 Register Op-Mode I I 0 0 1 Register Op-Mode; Word to Reg= 100, Long to Ai!!i = 101, Word to Mem = 110, Long to Mem = 111 OR Immediate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I I I I I I I 0 0 0 0 0 I 0 0 0 Size Effective Address AND Immediate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I I I I I I I 0 0 0 0 0 0 1 0 Size Effective Address @HITACHI 590 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 HD68000/HD68HCOOO SUB Immediate 15 14 1~ 12 11 10 9 8 6 5 4 3 2 0 I I I I 0 0 0 0 0 1 0 0 Size Effective Address ADD Immediate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I I I I I I 0 0 0 0 0 1 1 0 Size Effective Address EOR Immediate 15 14 13 i2 11 10 9 8 6 5 4 3 2 0 I I I I I I I o 0 0 ci 1 0 1 0 Size Effective Address CMP Immediate 15 14 13 12 11 10 9 8 6 5 4 3 2 0 I I I I I I I 0 0 0 d 1 1 0 0 Size Effective Address (2) MOVE BYTE INSTRUCTION MOVE Byte 15 14 13 12 11 10 g 8 7 6 5 4 3 2 0 0 0 0 Destination Register Mode Source Mode (3) MOVE LONG INSTRUCTION MOVE Long 15 14 13 1ii 11 10 9 8 j 6 0 0 0 bestinatiori Aigiiter Mode 5 4 3 2 0 Source Mode Register (4) MOVE WORD INSTRUCflON MOVE Word 15 14 13 i2 11 10 9 8 6 0 0 Dettiriation Register Mode 5 4 3 2 0 Source Mode Register (5) MISCELLANEOUS INSTRUCTIONS NEGX 15 14 13 12 11 10 9 8 6 5 4 3 2 0 I I I I 0 1 0 0 0 0 0 0 Site Effectiw Address MOVE from SR 15 14 13 12 11 10 9 8 6 5 4 3 2 0 I I I I 0 1 0 ci 0 0 0 0 1 1 Effectiw Address CLR :i j 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I~ I I I 0 1 0 0 0 0 1 0 Size Effectiw Address i~ 1I't ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 ' 591 11 : ~I NEG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 Size Effective Address MOVE to CCR 15 14 13 12 11 10 9 8 LiJ:i]oJ0JoJ1 6 5 4 3 2 0 ~ffective Address NOT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 Size Effective Address MOVE to SR 15 14 13 12 11 10 9 8 6 54 32 0 IO [Qi_]_~ _.J_o__._J_1----''----~--'--o-'-J_1___LJ_1~---E_ffe_c_tive_A_dd_re_ss_ ___, NBCD 15 14 13 12 11 10 9 8 6 5 4 3 2 0 [ii__ _J J O J 1 _(_o [ 1 _[ o_ o ~J_o~J'----o~!_o~_ _ _E_ffe_c_tiv_e_A_dd_re_s·_ _~ PEA I I I 15 14 13 12 11 10 9 8 654 3 2 0 O 1 OJ~J:TE~l-0-~l-o~i-o~l-1~---E-f-fe-ct-ive_A_d_d_re-ss--~ SWAP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 J o 11 I o L~J _ci::i:_ I o I o I o I 1 I o I o I o Register MOVEM Registers to EA 15 14 13 12 11 10 9 8 6 5 4 3 2 0 Effective Address EXTW EXTL TST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 JoJ1 JoJoJ1 JoJ0Joi1 Joioio 0 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 o Io Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 o 11 Size Effective Address TAS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Effective Address 592 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 MOVEM EA to Registers 15 14 13 12 11 10 9 B 7 6 5 4 3 2 0 j 0 I 1 I 0 j 0 j 1 j 1 I 0 I 0 I 1 I Sz Effective Address TRAP 15 14 13 12 11 10 9 B 6 5 4 3 2 0 I0 I1 I0 I0 I1 j 1 I 1 I0 I0 I1 I0 I0 Vector LINK 15 14 13 12 11 10 9 B 7 6 5 4 3 2 0 I0 I1 I0 I0 I 1 I1 I 1 I0 I0 I 1 I0 I1 I0 Register UNLK 15 14 13 12 11 10 9 B 7 6 5 4 3 2 o I 0 I 1 I 0 I 0 I 1 I 1 I 1 I 0 I O~_I 0 I 1 I 1 Register MOVE to USP 15 14 13 12 11 10 9 B 6 543 2 0 lo 11 lo lo 11 11 11 lo lo l1T1ro=G=r Register MOVE from USP 15 14 13 12 11 10 9 B I0 I1 I0 I0 I 1 I1 I1 I0 7 6 5432 0 0:JLJ_1 Jj~:JTI Register RESET 15 14 13 12 11 10 9 B 6 5 4 3 2 0 NOP STOP RTE 15 14 13 12 11 10 9 B 7 6 5 4 3 2 0 lol1 !olol1 !1 l1 lolol1 l1 l1 lo olol1 15 14 13 12 11 10 9 B 7 6 5 4 3 2 0 Io I 1IoIoI1I1I1IoIoi1I1i1IoioI1 Io 15 14 13 12 11 10 9 B 6 5 4 3 2 0 RTS 15 14 13 12 11 10 9 B 7 6 5 4 3 2 o Jol1 olol1 !1 J1 loiol1 l1 i1 lol1 lol1 TRAPV 15 14 13 t2 11 10 9 B 7 6 5 4 3 2 O Jol1 lolol1 l1 !1 lolo!1 l1 i1 lol1 l1 lo @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 593 RTR 15 14 13 12 11 10 9 8 6 54 3 2 0 JSR JMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Effectiv,e Address 15 14 13 12 11 10 9 8 654 3 2 0 Effective Address CHK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Register Effective Address LEA 15 14 13 12 11 10 9 8 Register 654 3 2 0 Effective Address~ (6) ADD QUICK, SUBTRACT QUICK, SET CONDITIONALLY, DECREMENT INSTRUCTIONS ADDO 15 14 13 12 11 10 9 8 654 3 0 Data I o Size Effective Address SUBO 15 14 13 12 11 10 9 8 654 3 0 Data I 1 Size Effective Address Sec 15 14 13 12 11 10 9 8 654 3 0 Condition I1 I1 Effective Address DBcc 15 14 13 12 11 10 9 8 ["Q" I Io I 1 Condition 654 32 0 Register (7) BRANCH CONDITIONALLY, BRANCH TO SUBROUTINE INSTRUCTION Bee 15 14 13 12 11 10 9 8 6 5 4 3 2 0 Condition 8 bit Displacement BSA 15 14 13 12 11 10 9 8 6 5 4 3 2 0 8 bit Displacement (B) MOVE QUICK INSTRUCTION MOVEQ 15 14 13 12 11 10 9 8 6 5 4 3 2 0 Data 594 ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 H068000/H D68HCOOO (9) OR, DIVIDE, SUBTRACT DECIMAL INSTRUCTIONS OR 15 14 13 12 11 10 9 8 6 543 2 0 I 0 0 0 Register Op-Mode Effective Address Op-Mode B wL 000 001 010 On V EA-+On 100 101 110 EAvOn-+EA DIVU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 Register I I 0 1 1 Effective Address DIVS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 Register I 1 I 1 Effective Address SBCD 15 14 13 12 11 10 9 8 6 543 0 0 0 Destination Register 0 0 0 0 R/M RIM (register/memory): register - register= 0, memory - memory= 1 2 0 Source Register (10) SUBTRACT, SUBTRACT EXTENDED INSTRUCTIONS SUB SUBX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I 0 0 1 Register Op-Mode I --Eff~tive Address Op-Mode B wL 000 001 010 On-EA-+On 100 101 110 EA-On-+EA - 011 111 An-EA-+An 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 Destination Register Size 0 0 R/M RIM (register/memory): register - register = 0, memory - memory = 1 2 0 Source Register (11) COMPARE, EXCLUSIVE OR INSTRUCTIONS CMP CMPM 15 14 13 12 11 10 9 0 Register Op-Mode B w L 000 001 010 On-EA - 011 111 An-EA 15 14 13 12 11 10 9 0 Register 8 765 Op-Model 8 765 Size 0 4 3 2 0 Effective Address 4 3. I 0 1 2 0 Register EOR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I I 0 1 1 Register Size Effective Address (12) AND, MULTIPLY, ADD DECIMAL, EXCHANGE INSTRUCTIONS AND 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 10 0 Register Op-Mode Effective Address Op-Mode Bw L 000 001 010 On AEA-+On 100 101 110 EA A On-+EA $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 595 HD68000/HD68HCOOO MULU MULS 15 14 13 12 11 10 9 8 0 0 Register 0 15 14 13 12 11 10 9 8 0 0 Register 6 54 3 2 0 Effective Address 6 54 3 2 0 Effective Address ABCD 15 14 13 12 11 10 9 8 6 5 4 3 0 0 Destination Register 0 0 0 0 R/M R/M (register/memory): register - register= 0, memory - memory= 1 2 0 Source Register EXGD 15 14 13 12 11 10 9 8 6 5 4 3 2 0 0 0 Data Register 0 0 0 0 Data Register EXGA 15 14 13 12 11 10 9 8 6 5 4 0 0 Address Register 0 0 0 2 0 Address Register EXGM 15 14 13 12 11 10 9 8 0 0 Data Register 6 5 4 3 2 0 0 0 0 Address Register (13) ADD, ADD EXTENDED INSTRUCTIONS ADD 15 14 13 12 11 10 9 8 6 5 4 3 0 0 Register Op-Mode Effective Address Op-Mode B wL 000 001 010 On+ EA-+Dn 100 101 110 EA+ On-> EA 011 111 An+ EA-+An ADDX 15 14 13 12 11 10 9 8 6 5 4 0 Destination Register Size 0 0 R/M R/M (register/memory): register - register= 0, memory - memory= 1 2 0 Source Register (14) SHIFT/ROTATE INSTRUCTIONS Data Register Shifts 15 14 13 12 11 10 9 8 0 Count/Register d 6 Size 5 4 3 i/r Type 2 0 Register Memory Shifts 15 14 13 12 11 10 9 8 [!.!1 0 0 Type d 6 5 4 3 2 0 Effective Address Shift Type Codes: AS= 00, LS= 01, ROX= 10, RO= 11 d (direction): Right= 0, Left= 1 i/r (count source): Immediate Count= 0, Register Count= 1 596 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 · INSTRUCTION EXECUTION TIMES The following paragraphs i:ontain listings of the instruction execution times in terms of external clock (CLK) periods. In this timing data, it is assumed that both memory read and write cycle times are four clock periods. Any wait states caused by a longer memory cycle must be added to the total instruction time. The number of bus read and write cycles for each instruction is also included with the timing data. This data is enclosed in parenthesis following the execution periods and is shown as: (r/w) where r is the number of read cycles and w is the number of write cycles. (NOTE) The number of periods includes instruction fetch and all applicable operand fetches and stores. · EFFECTIVE ADDRESS OPERAND CALCULATION TIMING Table 27 lists the number of clock periods required to com- pute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand. The number of bus read and write cycles is shown in parenthesis as (r/w). Note there are no write cycles involved in processing the effective address. · MOVE INSTRUCTION CLOCK PERIODS Table 28 and 29 indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes. The number of bus read and Write cycles is shown in parenthesis as: (r/w). · STANDARD INSTRUCTION CLOCK PERIODS The number of clock periods shown in Table 30 indicates the time required to perform the operations, store the results, and read the next instruction. The number of 'bus read and write cycles is shown in parenthesis as: (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. In Table 30 the headings have the following meanings: An = address register operand, Dn = data register operand, ea = an operand specified by an effective address, and M = memory effective address operand. · IMMEDIATE INSTRUCTION CLOCK PERIODS The number of clock periods shown in Table 31 includes the time to fetch immediate operands, perform the operations, store the results, and read the next operation. The number of bus read and write cycles is shown in parenthesis as: (r/w). The number of ~lock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. In Table 31, the headings have the following meanings: # = immediate. operand, Dn = data register operand, An = address register operand, M =memory operand, CCR =condition code register, and SR = status register. · SINGLE OPERAND INSTRUCTION CLOCK PERIODS Table 32 indicates the number of clock periods for the single operand instructions. The number of bus read and write cycles is shown in parenthesis as: (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. Table 27 Effective Address Calculation Timing Dn An An@ An@+ An@An@(dl An@(d,ixl* xxx.W xxx.l PC@(di PC@(d,ixl* #xxx Addressing Mode Register Data Register Direct Address Register Direct Memory Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register Indirect with Index Absolute Short Absolute long Program· Counter with Displacement Program Counter with Index Immediate · The size of the index register (ix, does not affect execution time. Byte, Word 0(0/0) 0(0/0) 4(1/0) 4(1/01 6(1/0) 8(2/01 10(2/01 8(2/01 1213/0I 8(2/01 10(2/01 4(1/01 long 0(0/0) 0(0/0) 8(2/0) 8(2/01 10(2/0) 12(3/01 14(3/01 12(3/01 16(4/0I 12(3/01 14(3/01 8(2/0I ~HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 597 Table 28 Move Byte and Word Instruction Clock Periods Source On An An@ An@+ An@An@(d) An@(d, ix)* xxx.W xxx. L PC@(d) PC@(d,ix)* #xxx On 4(1/0) 4(1/0) B(2/0) B(2/0) 10(2/0) 12(3/0) 14(3/0) 12(3/0) 16(4/0) 121::/0) 14(3/0) B(2/0) An 4(1/0) 4(1/0) B(2/0) B(2/0) 10(2/0) 12(3/0) 14(3/0) 12(3/0) 16(4/0) 12(3/0) 14(3/0) B(2/0) An@ B(1/1) B(1/1) 12(2/1) 12(2/1) 14(2/1) 16(3/1) 1B(3/1) 16(3/1) 20(4/1) 16(3/1) 1B(3/1) 12(2/1) An@+ B(1/1) Bl1/1) 12(2/1) 12(2/1) 14(2/1) 16(3/1) 1B(3/1) 16(3/1) 20(4/1) 16(3/1) 1B(3/1) 12(2/1) Destination An@- Bl1/1) Bl1/1) 12(2/1) 12(2/1) 14(2/1) 16(3/1) 1B(3/1) 16(3/1) 20(4/1) 16(3/1) 1B(3/1) 12(2/1) An@(d) 12(2/1) 12(2/1) 16(3/1) 16(3/1) 1B(3/1) 20(4/1) 22(4/1) 20(4/1) 24(5/1) 20(4/1) 22(4/1) 16(3/1) An@(d,ix)* 14(2/1) 14(2/1) 1B(3/1) 18(3/1) 20(3/1) 22(4/1) 24(4/1) 22(4/1) 26(5/1) 22(4/1) 24(4/1) 1B(3/1) xxx.W xxx.L 12(2/1) 12(2/1) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 16(3/1) 20(4/1) 1B(3/1) 22(4/1) 20(4/1) I 24(5/1) 22(4/1) 20(4/1) 24(5/1) 26(5/1) 24(5/1) 2B(6/1) 20(4/1) 22(4/1) 16(3/1) 24(5/1) 26(5/1) 20(4/1) * l;he size of the index register (ix) does not affect execution time. Table 29 Move Long Instruction Clock Periods Source On An An@ An@+ An@An@(d) An@(d, ix)* xxx.W xxx. L PC@(dl PC@(d, ixl* #xxx On 4(1/0) 4(1/0) 12(3/0) 12(3/0) 14(3/0) 16(4/0) 1B(4/0) 16(4/0) 20(5/0) 16(4/0) 1B(4/0) 12(3/0) An 4(1/0) 4(1/0) 12(3/0) 12(3/0) 14(3/0) 16(4/0) 1B(4/01 16(4/0) 20(5/0) 16(4/01 1B(4/0) 12(3/0) An@ 12(1/2) 12(1/2) 20(3/2) 20(3/2) 22(3/2) 24(4/2) 26(4/2) 24(4/2) 2B(5/2) 24(4/21 26(4/2) 20(3/2) An@+ 12(1/2) 12(1/2) 20(3/2) 20(3/2) 22(3/2) 24(4/2) 26(4/21 24(4/2) 2B(5/2) 24(4/2) 26(4/2) 20(3/2) Destination An@ - 12(1/2) 12(1/2) 20(3/2) 20(3/2) 22(3/2) 24(4/2) 26(4/21 24(4/2) 2B(5/2) 24(4/2) 26(4/2) 20(3/2) An@(d) 16(2/2) 16(212) 24(4/2) 24(4/2) 26(4/2) 2B(5/2) 30(5/21 2B(5/2) 32(6/2) 2B(5/2) 30(5/2) 24(4/2) An@(d, ix)* 1B(2/2) 1B(2/2) 26(4/2) 26(4/2) 2B(4/2) 30(5/2) 32(5/21 30(5/2) 34(6/2) 30(5/2) 32(5/21 26(4/2) xxx.W 16(2/2) 16(2/2) 24(4/2) 24(4/2) 26(4/2) 2B(5/2) 30(5/2) 2B(5/2) 32(6/2) 2B(5/2) 30(5/2) 24(4/2) * The size of the index register (ix) does not affect execution time. xxx.L 20(3/2) 20(3/2) 2B(5/2) 2B(5/2) 30(5/2) 32(6/2) 34(6/2) 32(6/2) 36(7/2) 32(6/2) 34(6/2) 2B(5/2) Instruction ADD AND CMP DIVS DIVU EOR MULS MULU OR SUB Table 30 Standard Instruction Clock Periods Size Byte, Word Long Byte, Word Long Byte, Word Long - - Byte, Word Long - - Byte, Word Long Byte, Word Long op<ea>,An B(1/0) + 6(1/01 + ·· - 6(1/01 + 6(1/01 + - - - - B(1/0) + 6(1/01 + ·· op<ea>, On 4(1/0) + 6(1/0) + ·· 4(1/0) + 6(1/0) + ·· 4(1/0) + 6(1/0) + 158(1/0) +. 140(1/0) +. 4(1/0) ··· B(1/0) ··· 70(1/0) +. 70(1/0) +. 4(1/0) + 6(1/0) + ·· 4(1/0) + 6(1/0) + ·· opDn,<M> B(1/1)+ 12(1/2) + B(1/1)+ 12(1/2) + - B(1/1) + 12(1/21 + - B(1/1) + 12(1/2) + B(1/1) + 12(1/2) + + add effective address calculation time · indicates maximum value · · total of 8 clock periods for instruction if the effecti.te address is register direct · ·· only available effective address mode is data register direct DIVS, DIVU - The divide algorithm used by the 68000 provides less than 10% difference between the best and worst case timings. MULS, MULU - The multiply algorithm requires 38+2n clocks when n is defined as MU LU; n = the number of ones in the < ea > MULS; n = concatenate the < ea > with a zero as the LSB; n is the resultant number of 10 or 01 patterns in the 17-bit source; i.e. worst case happens when the source is $5555. $HITACHI 598 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 31 lmmediation Instruction Clock Periods Instruction ADDI ADDO ANDI CMPI EORI MOVEO ORI SUBI SUBO Size Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Long Byte, Word Long Byte, Word Long Byte, Word Long +add effective address calculation time ·word only op#, Dn 8(2/0) 16(3/0) 4(1/0) 8(1/0) 8(2/0) 16(3/0) 8(2/0) 14(3/0) 8(2/0) 16(3/0) 4(1/0) 8(2/0) 16(3/0) 8(2/0) 16(3/0) 4(1/0) 8(1/0) op#, An op#,M - 12(2/1) + - 20(3/2) + 8(1/0)* 8(1/1) + 8(1/0) 12(1/2) + -- - 12(2/1) + - 20(3/1) + 8(2/0) 8(2/0) + -t-1413101- ~-2(3/0) + - 12(2/1) + - 20(3/2) + - - - 12(2/1) + - 20(3/2) + - 12(2/1) + - 20(3/2) + 8(1/0)* 8(1/1) + 8(1/0) 12(1/2) + op#, CCR/SR - - - 20(3/0) - 20(3/0) - 20(3/0) - - - - - Table 32 Single Operand Instruction Clock Periods Instruction CLR NBCD NEG NEGX NOT Sec TAS TST Size Byte, Word Long Byte Byte, Word Long Byte, Word Long Byte, Word Long Byte, False Byte, True Byte Byte, Word Long +add effective address calculation time Register 4(1/0) 6(1/0) 6(1/0) 4(1/0) 6(1/0) 4(1/0) 6(1/0) 4(1/0) 6(1/0) 4(1/0) 6(1/0) 4(1/0) 4(1/0) 4(1/0) Memory 8(1/11 + 12(1/2) + ------ 8(1/1) + 8(1/1) + 12(1/2) + 8(1/1) + 12(1/2) + 8(1/1) + 12(1/2) + 8(1/1) + 8(1/1) + 10(1/1) + 4(1/0) + 4(1/0) + · SHIFT/ROTATE INSTRUCTION CLOCK PERIODS Table 33 indicates the number of clock periods for the shift and rotate instructions. The number of bus read and write cycles is shown in parenthesis as: (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. · BIT MANIPULATION INSTRUCTION CLOCK PERIODS Table 34 indicates the number of clock periods required for the bit manipulation instructions. The number of bus read and write cycles is shown in parenthesis as: (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 599 · CONDITIONAL INSTRUCTION CLOCK PERIODS Table 35 indicates the number of clock periods required for the conditional instructions. The number of bus read and write cycles is indicated in parenthesis as: (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated. · JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS Table 36 indicates the number of clock periods required fOI" the jump, jump to subroutine, load effective address, push effective address, and move multiple registers instructions. The number of bus read and write cycles is shown in parenthesis as: (r/w). Table 33 Shift/Rotate Instruction Clock Periods Instruction ASR,ASL LSR, LSL ROA, AOL ROXR,ROXL Size Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Register 6 + 2n(1/0) 8 + 2n(1/0) 6 + 2n(1/0) 8 + 2n(1/0) 6 + 2n(1/0) 8 + 2n(1/0) 6 + 2n(1/0) 8 + 2n(1/0) Memory 8(1/1) + - 8(1/1)+ - 8(1/1) + - 8(1/1) + - Table 34 Bit Manipulation Instruction Clock Periods Instruction BCHG BCLR BSET --~-·--- BTST Size Byte Long Byte Long Byte Long Byte Long Dynamic Register Memory - 8(1/1) + 8(1/0)* - - 8(1/1) + 10(1/0)* - - 8(1/1) + 8(1/0)* - - 4(1/0) + 6(1/0) - + add effective address calculation time * indicates maximum value Static Register Memory - 12(2/1)+ 12(2/0)* - - 12(2/1)+ 14(2/0)* - - 12(2/1)+ 12(2/0)* - - 10(2/0) 8(2/0) + - T~ble 35 Conditional Instruction Clock Periods Instruction Displacement Bee BRA BSA DBee CHK TRAP TRAPV Byte Word Byte Word Byte Word k:.. CC true CC false - - +add effective address calculation time * indicates maximum value Trap or Branch Taken 10(2/0) 10(2/0) 10(2/0) 10(2/0) 18(2/2) 18(2/2) - 10(2/0) 40(5/3) +. 34(4/3) 34(5/3) Trap of Branch Not Taken 8(1/0) 12(2/0) - - - 12(2/0) 14(3/0) 10(1/0) + - 4(1/0) @HITACHI 600 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 Table 36 JMP, JSR, LEA, PEA, MOMEM Instruction Clock Periods Instr JMP JSR LEA PEA MOVEM Size - - - Word M-+R Long MOVEM Word R-+M Long An@ 8(2/0) 16(2/2) 4(1/0) 12(1/2) 12+4n (3+n/0) 12+8n (3+2n/0) 8+4n (2/n) 8+8n (2/2n) An@+ - - 12+4n (3+n/O) 12+8n (3+2n/0) - An@- - 8+4n (2/n) 8+8n (2/2n) An@(d) 10(2/0) 18(2/2) 8(2/0) 16(2/2) 16+4n (4+n/0) 16+8n (4+2n/0) 12+4n (3/n) 12+8n (3/2n) An@(d,ix)* 14(3/0) 22(2/2) 12(2/0) 20(2/2) 18+4n (4+n/0) 18+8n (4+2n/0) 14+4n (3/n) 14+8n (3/2n) xxx.W xxx.L PC@(d) 10(2/0) 12(3/0) 10(2/0) 18(2/2) 20(3/2) 18(2/2) 8(2/0) 12(3/0) 8(2/0) 16(2/2) 20(3/2) 16(2/2) j 16+4n I 20+4n 16+4n (4+n/0) (5+n/0) (4+n/0) 16+8n ' 20+8n I 16+8n 1 - (4+2n/0) (5+2n/0) : (4+2n/0) 12+4n 16+4n (3/n) 12+8n 1(64/+n8) ~~1-- (3/2n) (4/2n) - PC@(d,ix)* 14(3/0) 22(2/2) 12(2/0) 20(2/2) 18+4n (4+n/0) 18+8n (4+2n/0) - - n is the number of registers to move * is the size of the index register (ix) does not affect the instruction's execution time · MULTl-PRECISION INSTRUCTION CLOCK PERIODS Table 37 indicates the number of clock periods for the multi- precision instructions. The number of clock periods includes the time to fetch both operands, perform the operations, store the results, and read the next instructions. The number of read and write cycles is shown in parenthesis as: (r/w). In Table 37, the headings have the following meanings: On= data register operand and M = memory operand. Table 37 Multi-Precision Instruction Clock Periods Instruction AODX CMPM SUBX ABCO SBCO Size Byte, Word Long Byte, Word Long Byte, Word Long Byte Byte op On, On 4(1/0) 8(1/0) - 4(1/0) 8(1/0) 6(1/0) 6(1/0) opM, M 18(3/1) 30(5/2) 12(3/0) 20(5/0) 18(3/1) 30(5/2) 18(3/1) 18(3/1) · MISCELLANEOUS INSTRUCTION CLOCK PERIODS Table 38 indicates the number of clock periods for the fol- lowing miscellaneous instructions. The number of bus read and write cycles is shown in parenthesis as: (r/w). The number of clock periods plus the number of read and write cycles must be added to those of the effective address calculation where indicated. · EXCEPTION PROCESSING CLOCK PERIODS Table 39 indicates the number of clock periods for exception processing. The number of clock periods includes the time for all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. The number of bus read and write cycles is shown in parenthesis as: (r/w). @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 601 Table 38 Miscellaneous Instruction Clock Periods Instruction MOVE from SR MOVE to CCR MOVE to SR MOVEP EXG EXT LINK MOVE from USP MOVE to USP NOP RESET RTE RTR RTS STOP SWAP UNLK Size - Word Long - Word Long - - - - +add effective address calculation time Register 6(1/0) 12(2/0) 12(2/0) - 6(1/0) 4(1/0) 4(1/0) 16(2/2) 4(1/0) 4(1/0) 4(1/0) 132(1/0) 20(5/0) 20(5/0 16(4/0) 4(0/0) 4(1/0) 12(3/0) Memory 8(1/1) + 12(2/0) + 12(2/0) + - - - Register -+ Memory - - 16(2/2) 24(2/4) - - - - - - - Memory -+ Register - - - 16(4/0) 24(6/0) - - - - - - Table 39 Exception Processing Clock Periods Exception Reset** Address Error Sus Error Interrupt Illegal Instruction Privileged Violation Trace Periods 38.5 (6/0) 50(417) 50(4/7) 44(5/3)* 34(4/3) 34(4/3) 34(4/3) · The interrupt acknowledge bus cycle is assumed to take four external clock periods. * * Indicates the time from when RtS and HALT are first sampled as negated to when instruction execution starts. · MASI( VERSION Type No. HD68000-8 HD68000-10 HD6800Q-12 HD68000'1!8 HD68000¥-10 HD68000Y-12 Mask version 68000S1 HD68000P-8 HD68000P98 HD68000CP-8 68000U The difference of function between mask version 6800081 and 680000 is only as following (Figure 59). The function of HD68HCOOO is as same as mask version 680000. @HITACHI 602 Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 so Sl S2 S3 54 S5 S6 S7 so Sl S2 S3 S4 S5 S6 S7 CLK so Sl S2 S3 54 S5 R/W \ \ DTACK - - - - - - - - - . o,-o.. -~~~~~~~~<~~~~~)>~~--<i<-~~~~__,}----1'rt---------1(_~~~ ,. .·----Read-----<-+o1-----.;~~:----··+1·~A"'pp""r"'"o~d~C""l"'"oc.;;..k-"'s--t·"'il··- Write Stack -----<· Figure 59 Address Error Timing Broken line: mask version 68000U and HD68HCOOO. · NOTE FOR USE · Power Supply Circuit When designing Vee and Vss pattern of the circuit board, the capacitors need to be located nearest to Vee and Vss as shown in the Figure 60. (Top View) (a) DIP (Bottom View) (b) PGA 1µF/35V Tantalum Capacitor (2 pairs) Figure 60 Power Supply Circuit (Top View) (c) PLCC $HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 603 604 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 @HITACHI Hitachi America Ltd. · 2210 O'Toole Avenue · San Jose, CA 95131 · (408) 435-8300 605 Hitachi America, Ltd. SEMICONDUCTOR and IC DIVISION Hitachi America, Ltd. Semiconductor & IC Division Hitachi Plaza 2000 Sierra Point Parkway Brisbane, CA 94005-1819 Telephone: 415-589-8300 Telex: 17-1581 Twx: 910-338-2103 FAX: 415-583-4207 REGIONAL OFFICES MID-ATLANTIC REGION Hitachi America, Ltd. 1700 Galloping Hill Rd. Kenilworth, NJ 07033 201 /245-6400 NORTHEAST REGION Hitachi America, Ltd. 5 Burlington Woods Drive Burlington, MA 01803 617 /229-2150 NORTH CENTRAL REGION Hitachi America, Ltd. 500 Park Blvd., Suite 415 Itasca, IL 60143 312/773-4864 NORTHWEST REGION Hitachi America, Ltd. 2000 Sierra Point Parkway Brisbane, CA 94005-1819 415/589-8300 SOUTH CENTRAL REGION Hitachi America, Ltd. Two Lincoln Centre, Suite 865 5420 LBJ Freeway Dallas, TX 75240 214/991-4510 SOUTHWEST REGION Hitachi America, Ltd. 18300 Von Karman Avenue, Suite 730 Irvine, CA 92715 714/553-8500 SOUTHEAST REGION Hitachi America, Ltd. 4901 N.W. 17th Way, Suite 302 Fort Lauderdale, FL 33309 305/491-6154 AUTOMOTIVE Hitachi America, Ltd. 6 Parklane Blvd., #558 Dearborn, Ml 48126 313/271-4410 DISTRICT OFFICES Hitachi America, Ltd. 3800 W. 80th Street Suite 1050 Bloomington, MN 55431 61 2/896-3444 Hitachi America, Ltd. 21 Old Main Street, Suite 104 Fishkill, NY 12524 914/897-3000 Hitachi America, Ltd. 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