4Gb: x4, x8, x16 DDR4 SDRAM

DDR4 SDRAM, DDR4 DRAM

micron technology, inc, micron, ddr4, double data rate, manufacturer, semiconductor$Id: micron-ds-fo.xsl, v 1.75 2010/09/04 18:03:15 bobs Exp $

AE-sschaefer; tw-ckholman

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DDR4 SDRAM
MT40A1G4
MT40A512M8
MT40A256M16
Features
· VDD = VDDQ = 1.2V ±60mV · VPP = 2.5V, ­125mV/+250mV · On-die, internal, adjustable VREFDQ generation · 1.2V pseudo open-drain I/O · TC maximum up to 95°C
­ 64ms, 8192-cycle refresh up to 85°C ­ 32ms, 8192-cycle refresh at >85°C to 95°C · 16 internal banks (x4, x8): 4 groups of 4 banks each · 8 internal banks (x16): 2 groups of 4 banks each · 8n-bit prefetch architecture · Programmable data strobe preambles · Data strobe preamble training · Command/Address latency (CAL) · Multipurpose register READ and WRITE capability · Write leveling · Self refresh mode · Low-power auto self refresh (LPASR) · Temperature controlled refresh (TCR) · Fine granularity refresh · Self refresh abort · Maximum power saving · Output driver calibration · Nominal, park, and dynamic on-die termination (ODT) · Data bus inversion (DBI) for data bus · Command/Address (CA) parity · Databus write cyclic redundancy check (CRC) · Per-DRAM addressability · Connectivity test · sPPR and hPPR capability · JEDEC JESD-79-4 compliant

4Gb: x4, x8, x16 DDR4 SDRAM Features

Options1

Marking

· Configuration

­ 1 Gig x 4

1G4

­ 512 Meg x 8 ­ 256 Meg x 16

512M8 256M162

· FBGA package (Pb-free) ­ x4, x8

­ 78-ball (9mm x 11.5mm) ­ Rev. A

HX

­ 78-ball (9mm x 10.5mm) ­ Rev. B

RH

­ 78-ball (8mm x 12mm) ­ Rev. E

WE

­ 78-ball (7.5mm x 11mm) ­ Rev. F,G

SA

· FBGA package (Pb-free) ­ x16

­ 96-ball (9mm x 14mm) ­ Rev. A

HA

­ 96-ball (9mm x 14mm) ­ Rev. B

GE

­ 96-ball (7.5mm x 13.5mm) ­ Rev. E, F

LY

­ 96-ball (7.5mm x 13mm) ­ Rev. G

TB

· Timing ­ cycle time

­ 0.625ns @ CL = 22 (DDR4-3200)

-062E

­ 0.682ns @ CL = 20 (DDR4-2933)

-068E

­ 0.682ns @ CL = 21 (DDR4-2933)

-068

­ 0.750ns @ CL = 18 (DDR4-2666)

-075E

­ 0.750ns @ CL = 19 (DDR4-2666)

-075

­ 0.833ns @ CL = 16 (DDR4-2400)

-083E

­ 0.833ns @ CL = 17 (DDR4-2400)

-083

­ 0.937ns @ CL = 15 (DDR4-2133)

-093E

­ 0.937ns @ CL = 16 (DDR4-2133)

-093

­ 1.071ns @ CL = 13 (DDR4-1866)

-107E

· Operating temperature

­ Commercial (0°  TC  95°C) ­ Industrial (­40°  TC  95°C)
­ Revision

None IT :A

:B

:E

:F

:G

Notes:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings.
2. Not available on Rev. A.
3. Restricted and limited availability.

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x4, x8, x16 DDR4 SDRAM Features

Table 1: Key Timing Parameters

Speed Grade1 -062Y -062E -068 -075E -075 -083E -083 -093E -093 -107E

Data Rate (MT/s) 3200 3200 2933 2666 2666 2400 2400 2133 2133 1866

Target CL-nRCD-nRP 22-22-22 22-22-22 21-21-21 18-18-18 19-19-19 16-16-16 17-17-17 15-15-15 16-16-16 13-13-13

Note: 1. Refer to the Speed Bin Tables for additional details.

tAA (ns) 13.75 (13.32)
13.75 14.32 (13.75)
13.50 14.25 (13.75)
13.32 14.16 (13.75) 14.06 (13.50)
15.00 13.92 (13.50)

tRCD (ns) 13.75 (13.32)
13.75 14.32 (13.75)
13.50 14.25 (13.75)
13.32 14.16 (13.75) 14.06 (13.50)
15.00 13.92 (13.50)

tRP (ns) 13.75 (13.32)
13.75 14.32 (13.75)
13.50 14.25 (13.75)
13.32 14.16 (13.75) 14.06 (13.50)
15.00 13.92 (13.50)

Table 2: Addressing

Parameter Number of bank groups Bank group address Bank count per group Bank address in bank group Row addressing Column addressing Page size1

1024 Meg x 4 4
BG[1:0] 4
BA[1:0] 64K (A[15:0])
1K (A[9:0]) 512B

512 Meg x 8 4
BG[1:0] 4
BA[1:0] 32K (A[14:0])
1K (A[9:0]) 1KB

256 Meg x 16 2
BG0 4
BA[1:0] 32K (A[14:0])
1K (A[9:0]) 2KB

Note: 1. Page size is per bank, calculated as follows: Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.

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4Gb: x4, x8, x16 DDR4 SDRAM Features

Figure 1: Order Part Number Example Example Part Number: MT40A1G4-083:B

MT40A

Configuration

Package

Speed

: Revision

{

Configuration

1 Gig x 4

1G4

512 Meg x 8 512M8

256Meg x 16 256M16

Package 78-ball 9.0mm x 11.5mm FBGA 78-ball 9.0mm x 10.5mm FBGA 78-ball 8.0mm x 12.0mm FBGA 78-ball 7.5mm x 11.0mm FBGA 96-ball 9.0mm x 14.0mm FBGA 96-ball 9.0mm x 14.0mm FBGA 96-ball 7.5mm x 13.5mm FBGA 96-ball 7.5mm x 13.0mm FBGA

Mark HX RH WE SA HA GE LY TB

Revision :A, :B, :E, :F, :G

Case Temperature

Commercial

None

Industrial

IT

Speed Grade ­107E tCK = 1.071ns, CL = 13 ­093 tCK = 0.937ns, CL = 16 ­093E tCK = 0.937ns, CL = 15 ­083 tCK = 0.833ns, CL = 17 ­083E tCK = 0.833ns, CL = 16 ­075 tCK = 0.750ns, CL = 19 ­075E tCK = 0.750ns, CL = 18 ­068 tCK = 0.682ns, CL = 21 ­068E tCK = 0.682ns, CL = 20 ­062E tCK = 0.625ns, CL = 22

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Contents
Important Notes and Warnings ....................................................................................................................... 19 General Notes and Description ....................................................................................................................... 19
Description ................................................................................................................................................ 19 Industrial Temperature ............................................................................................................................... 20 Automotive Temperature ............................................................................................................................ 20 General Notes ............................................................................................................................................ 20 Definitions of the Device-Pin Signal Level ................................................................................................... 21 Definitions of the Bus Signal Level ............................................................................................................... 21 Functional Block Diagrams ............................................................................................................................. 22 Ball Assignments ............................................................................................................................................ 24 Ball Descriptions ............................................................................................................................................ 26 Package Dimensions ....................................................................................................................................... 29 State Diagram ................................................................................................................................................ 37 Functional Description ................................................................................................................................... 39 RESET and Initialization Procedure ................................................................................................................. 40 Power-Up and Initialization Sequence ......................................................................................................... 40 RESET Initialization with Stable Power Sequence ......................................................................................... 43 Uncontrolled Power-Down Sequence .......................................................................................................... 44 Programming Mode Registers ......................................................................................................................... 45 Mode Register 0 .............................................................................................................................................. 48 Burst Length, Type, and Order ..................................................................................................................... 49 CAS Latency ............................................................................................................................................... 50 Test Mode .................................................................................................................................................. 51 Write Recovery (WR)/READ-to-PRECHARGE ............................................................................................... 51 DLL RESET ................................................................................................................................................. 51 Mode Register 1 .............................................................................................................................................. 52 DLL Enable/DLL Disable ............................................................................................................................ 53 Output Driver Impedance Control ............................................................................................................... 54 ODT RTT(NOM) Values .................................................................................................................................. 54 Additive Latency ......................................................................................................................................... 54 Rx CTLE Control ......................................................................................................................................... 54 Write Leveling ............................................................................................................................................ 55 Output Disable ........................................................................................................................................... 55 Termination Data Strobe ............................................................................................................................. 55 Mode Register 2 .............................................................................................................................................. 56 CAS WRITE Latency .................................................................................................................................... 58 Low-Power Auto Self Refresh ....................................................................................................................... 58 Dynamic ODT ............................................................................................................................................ 58 Write Cyclic Redundancy Check Data Bus .................................................................................................... 58 Mode Register 3 .............................................................................................................................................. 59 Multipurpose Register ................................................................................................................................ 60 WRITE Command Latency When CRC/DM is Enabled ................................................................................. 61 Fine Granularity Refresh Mode .................................................................................................................... 61 Temperature Sensor Status ......................................................................................................................... 61 Per-DRAM Addressability ........................................................................................................................... 61 Gear-Down Mode ....................................................................................................................................... 61 Mode Register 4 .............................................................................................................................................. 62 Hard Post Package Repair Mode .................................................................................................................. 63 Soft Post Package Repair Mode .................................................................................................................... 63 WRITE Preamble ........................................................................................................................................ 64

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4Gb: x4, x8, x16 DDR4 SDRAM Features
READ Preamble .......................................................................................................................................... 64 READ Preamble Training ............................................................................................................................ 64 Temperature-Controlled Refresh ................................................................................................................. 64 Command Address Latency ........................................................................................................................ 64 Internal VREF Monitor ................................................................................................................................. 64 Maximum Power Savings Mode ................................................................................................................... 65 Mode Register 5 .............................................................................................................................................. 66 Data Bus Inversion ..................................................................................................................................... 67 Data Mask .................................................................................................................................................. 68 CA Parity Persistent Error Mode .................................................................................................................. 68 ODT Input Buffer for Power-Down .............................................................................................................. 68 CA Parity Error Status ................................................................................................................................. 68 CRC Error Status ......................................................................................................................................... 68 CA Parity Latency Mode .............................................................................................................................. 68 Mode Register 6 .............................................................................................................................................. 69 tCCD_L Programming ................................................................................................................................. 70 VREFDQ Calibration Enable .......................................................................................................................... 70 VREFDQ Calibration Range ........................................................................................................................... 70 VREFDQ Calibration Value ............................................................................................................................ 71 Truth Tables ................................................................................................................................................... 72 NOP Command .............................................................................................................................................. 75 DESELECT Command .................................................................................................................................... 75 DLL-Off Mode ................................................................................................................................................ 75 DLL-On/Off Switching Procedures .................................................................................................................. 77 DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 77 DLL-Off to DLL-On Procedure .................................................................................................................... 79 Input Clock Frequency Change ....................................................................................................................... 80 Write Leveling ................................................................................................................................................ 81 DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 82 Procedure Description ................................................................................................................................ 83 Write Leveling Mode Exit ............................................................................................................................ 84 Command Address Latency ............................................................................................................................ 86 Low-Power Auto Self Refresh Mode ................................................................................................................. 91 Manual Self Refresh Mode .......................................................................................................................... 91 Multipurpose Register .................................................................................................................................... 93 MPR Reads ................................................................................................................................................. 94 MPR Readout Format ................................................................................................................................. 96 MPR Readout Serial Format ........................................................................................................................ 96 MPR Readout Parallel Format ..................................................................................................................... 97 MPR Readout Staggered Format .................................................................................................................. 98 MPR READ Waveforms ............................................................................................................................... 99 MPR Writes ............................................................................................................................................... 101 MPR WRITE Waveforms ............................................................................................................................. 102 MPR REFRESH Waveforms ........................................................................................................................ 103 Gear-Down Mode .......................................................................................................................................... 106 Maximum Power-Saving Mode ....................................................................................................................... 109 Maximum Power-Saving Mode Entry .......................................................................................................... 109 Maximum Power-Saving Mode Entry in PDA .............................................................................................. 110 CKE Transition During Maximum Power-Saving Mode ................................................................................ 110 Maximum Power-Saving Mode Exit ............................................................................................................ 110 Command/Address Parity .............................................................................................................................. 112 Per-DRAM Addressability .............................................................................................................................. 120

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4Gb: x4, x8, x16 DDR4 SDRAM Features
VREFDQ Calibration ........................................................................................................................................ 123 VREFDQ Range and Levels ........................................................................................................................... 124 VREFDQ Step Size ........................................................................................................................................ 124 VREFDQ Increment and Decrement Timing .................................................................................................. 125 VREFDQ Target Settings ............................................................................................................................... 129
Connectivity Test Mode ................................................................................................................................. 131 Pin Mapping ............................................................................................................................................. 131 Minimum Terms Definition for Logic Equations ......................................................................................... 132 Logic Equations for a ×4 Device .................................................................................................................. 132 Logic Equations for a ×8 Device .................................................................................................................. 133 Logic Equations for a ×16 Device ................................................................................................................ 133 CT Input Timing Requirements .................................................................................................................. 133
Post Package Repair ....................................................................................................................................... 135 Post Package Repair ................................................................................................................................... 135 Hard Post Package Repair .......................................................................................................................... 136 hPPR Row Repair - Entry ........................................................................................................................ 136 hPPR Row Repair ­ WRA Initiated (REF Commands Allowed) .................................................................. 136 hPPR Row Repair ­ WR Initiated (REF Commands NOT Allowed) ............................................................. 138 sPPR Row Repair ....................................................................................................................................... 139 hPPR/sPPR Support Identifier .................................................................................................................... 142
Excessive Row Activation ............................................................................................................................... 144 ACTIVATE Command .................................................................................................................................... 144 PRECHARGE Command ................................................................................................................................ 145 REFRESH Command ..................................................................................................................................... 146 Temperature-Controlled Refresh Mode .......................................................................................................... 148
Normal Temperature Mode ........................................................................................................................ 148 Extended Temperature Mode ..................................................................................................................... 148 Fine Granularity Refresh Mode ....................................................................................................................... 151 Mode Register and Command Truth Table .................................................................................................. 151 tREFI and tRFC Parameters ........................................................................................................................ 151 Changing Refresh Rate ............................................................................................................................... 154 Usage with TCR Mode ................................................................................................................................ 154 Self Refresh Entry and Exit ......................................................................................................................... 154 SELF REFRESH Operation .............................................................................................................................. 156 Self Refresh Abort ...................................................................................................................................... 158 Self Refresh Exit with NOP Command ......................................................................................................... 159 Power-Down Mode ........................................................................................................................................ 161 Power-Down Clarifications ­ Case 1 ........................................................................................................... 166 Power-Down Entry, Exit Timing with CAL ................................................................................................... 167 ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 169 CRC Write Data Feature ................................................................................................................................. 171 CRC Write Data ......................................................................................................................................... 171 WRITE CRC DATA Operation ...................................................................................................................... 171 DBI_n and CRC Both Enabled .................................................................................................................... 172 DM_n and CRC Both Enabled .................................................................................................................... 172 DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 172 CRC and Write Preamble Restrictions ......................................................................................................... 172 CRC Simultaneous Operation Restrictions .................................................................................................. 172 CRC Polynomial ........................................................................................................................................ 172 CRC Combinatorial Logic Equations .......................................................................................................... 173 Burst Ordering for BL8 ............................................................................................................................... 174 CRC Data Bit Mapping ............................................................................................................................... 174

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4Gb: x4, x8, x16 DDR4 SDRAM Features
CRC Enabled With BC4 .............................................................................................................................. 175 CRC with BC4 Data Bit Mapping ................................................................................................................ 175 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 178 CRC Error Handling ................................................................................................................................... 179 CRC Write Data Flow Diagram ................................................................................................................... 181 Data Bus Inversion ........................................................................................................................................ 182 DBI During a WRITE Operation .................................................................................................................. 182 DBI During a READ Operation ................................................................................................................... 183 Data Mask ..................................................................................................................................................... 184 Programmable Preamble Modes and DQS Postambles .................................................................................... 186 WRITE Preamble Mode .............................................................................................................................. 186 READ Preamble Mode ............................................................................................................................... 189 READ Preamble Training ........................................................................................................................... 189 WRITE Postamble ...................................................................................................................................... 190 READ Postamble ....................................................................................................................................... 190 Bank Access Operation .................................................................................................................................. 192 READ Operation ............................................................................................................................................ 196 Read Timing Definitions ............................................................................................................................ 196 Read Timing ­ Clock-to-Data Strobe Relationship ....................................................................................... 197 Read Timing ­ Data Strobe-to-Data Relationship ........................................................................................ 199 tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations ............................................................................ 200 tRPRE Calculation ..................................................................................................................................... 201 tRPST Calculation ...................................................................................................................................... 202 READ Burst Operation ............................................................................................................................... 203 READ Operation Followed by Another READ Operation .............................................................................. 205 READ Operation Followed by WRITE Operation .......................................................................................... 210 READ Operation Followed by PRECHARGE Operation ................................................................................ 216 READ Operation with Read Data Bus Inversion (DBI) .................................................................................. 219 READ Operation with Command/Address Parity (CA Parity) ........................................................................ 220 READ Followed by WRITE with CRC Enabled .............................................................................................. 222 READ Operation with Command/Address Latency (CAL) Enabled ............................................................... 223 WRITE Operation .......................................................................................................................................... 225 Write Timing Definitions ........................................................................................................................... 225 Write Timing ­ Clock-to-Data Strobe Relationship ...................................................................................... 225 tWPRE Calculation .................................................................................................................................... 227 tWPST Calculation ..................................................................................................................................... 228 Write Timing ­ Data Strobe-to-Data Relationship ........................................................................................ 228 WRITE Burst Operation ............................................................................................................................. 232 WRITE Operation Followed by Another WRITE Operation ........................................................................... 234 WRITE Operation Followed by READ Operation .......................................................................................... 240 WRITE Operation Followed by PRECHARGE Operation ............................................................................... 244 WRITE Operation with WRITE DBI Enabled ................................................................................................ 247 WRITE Operation with CA Parity Enabled ................................................................................................... 249 WRITE Operation with Write CRC Enabled ................................................................................................. 250 Write Timing Violations ................................................................................................................................. 255 Motivation ................................................................................................................................................ 255 Data Setup and Hold Violations ................................................................................................................. 255 Strobe-to-Strobe and Strobe-to-Clock Violations ........................................................................................ 255 ZQ CALIBRATION Commands ....................................................................................................................... 256 On-Die Termination ...................................................................................................................................... 258 ODT Mode Register and ODT State Table ........................................................................................................ 258 ODT Read Disable State Table .................................................................................................................... 259

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4Gb: x4, x8, x16 DDR4 SDRAM Features

Synchronous ODT Mode ................................................................................................................................ 260 ODT Latency and Posted ODT .................................................................................................................... 260 Timing Parameters .................................................................................................................................... 260 ODT During Reads .................................................................................................................................... 262
Dynamic ODT ............................................................................................................................................... 263 Functional Description .............................................................................................................................. 263
Asynchronous ODT Mode .............................................................................................................................. 266 Electrical Specifications ................................................................................................................................. 267
Absolute Ratings ........................................................................................................................................ 267 DRAM Component Operating Temperature Range ...................................................................................... 267 Electrical Characteristics ­ AC and DC Operating Conditions .......................................................................... 268 Supply Operating Conditions ..................................................................................................................... 268 Leakages ................................................................................................................................................... 269 VREFCA Supply ............................................................................................................................................ 269 VREFDQ Supply and Calibration Ranges ....................................................................................................... 270 VREFDQ Ranges ........................................................................................................................................... 271 Electrical Characteristics ­ AC and DC Single-Ended Input Measurement Levels .............................................. 272 RESET_n Input Levels ................................................................................................................................ 272 Command/Address Input Levels ................................................................................................................ 272 Command, Control, and Address Setup, Hold, and Derating ........................................................................ 274 Data Receiver Input Requirements ............................................................................................................. 276 Connectivity Test (CT) Mode Input Levels .................................................................................................. 280 Electrical Characteristics ­ AC and DC Differential Input Measurement Levels ................................................. 284 Differential Inputs ..................................................................................................................................... 284 Single-Ended Requirements for CK Differential Signals ............................................................................... 285 Slew Rate Definitions for CK Differential Input Signals ................................................................................ 286 CK Differential Input Cross Point Voltage .................................................................................................... 287 DQS Differential Input Signal Definition and Swing Requirements .............................................................. 288 DQS Differential Input Cross Point Voltage ................................................................................................. 290 Slew Rate Definitions for DQS Differential Input Signals .............................................................................. 291 Electrical Characteristics ­ Overshoot and Undershoot Specifications ............................................................. 293 Address, Command, and Control Overshoot and Undershoot Specifications ................................................ 293 Clock Overshoot and Undershoot Specifications ......................................................................................... 294 Data, Strobe, and Mask Overshoot and Undershoot Specifications .............................................................. 295 Electrical Characteristics ­ AC and DC Output Measurement Levels ................................................................ 295 Single-Ended Outputs ............................................................................................................................... 295 Differential Outputs .................................................................................................................................. 297 Reference Load for AC Timing and Output Slew Rate ................................................................................... 298 Connectivity Test Mode Output Levels ........................................................................................................ 299 Electrical Characteristics ­ AC and DC Output Driver Characteristics ............................................................... 300 Connectivity Test Mode Output Driver Electrical Characteristics ................................................................. 300 Output Driver Electrical Characteristics ..................................................................................................... 302 Output Driver Temperature and Voltage Sensitivity ..................................................................................... 305 Alert Driver ............................................................................................................................................... 305 Electrical Characteristics ­ On-Die Termination Characteristics ...................................................................... 306 ODT Levels and I-V Characteristics ............................................................................................................ 306 ODT Temperature and Voltage Sensitivity ................................................................................................... 308 ODT Timing DefinitionsODT Timing Definitions and Waveforms ................................................................ 308 DRAM Package Electrical Specifications ......................................................................................................... 312 Thermal Characteristics ................................................................................................................................. 316 Current Specifications ­ Measurement Conditions .......................................................................................... 317 IDD, IPP, and IDDQ Measurement Conditions ................................................................................................ 317

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4Gb: x4, x8, x16 DDR4 SDRAM Features
IDD Definitions .......................................................................................................................................... 319 Current Specifications ­ Patterns and Test Conditions ..................................................................................... 323
Current Test Definitions and Patterns ......................................................................................................... 323 IDD Specifications ...................................................................................................................................... 332 Current Specifications ­ Limits ....................................................................................................................... 333 Speed Bin Tables ........................................................................................................................................... 344
Refresh Parameters By Device Density ............................................................................................................ 363 Electrical Characteristics and AC Timing Parameters ...................................................................................... 364 Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 ........................................................ 376 Converting Time-Based Specifications to Clock-Based Requirements .............................................................. 388 Options Tables .............................................................................................................................................. 389

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4Gb: x4, x8, x16 DDR4 SDRAM Features
List of Figures
Figure 1: Order Part Number Example .............................................................................................................. 3 Figure 2: 1 Gig x 4 Functional Block Diagram .................................................................................................. 22 Figure 3: 512 Meg x 8 Functional Block Diagram ............................................................................................. 22 Figure 4: 256 Meg x 16 Functional Block Diagram ........................................................................................... 23 Figure 5: 78-Ball x4, x8 Ball Assignments ........................................................................................................ 24 Figure 6: 96-Ball x16 Ball Assignments ............................................................................................................ 25 Figure 7: 78-Ball FBGA ­ x4, x8 "HX" .............................................................................................................. 29 Figure 8: 78-Ball FBGA ­ x4, x8 "RH" .............................................................................................................. 30 Figure 9: 78-Ball FBGA ­ x4, x8 "WE" .............................................................................................................. 31 Figure 10: 78-Ball FBGA ­ x4, x8 "SA" .............................................................................................................. 32 Figure 11: 96-Ball FBGA ­ x16 "HA" ................................................................................................................ 33 Figure 12: 96-Ball FBGA ­ x16 "GE" ................................................................................................................ 34 Figure 13: 96-Ball FBGA ­ x16 "LY" ................................................................................................................. 35 Figure 14: 96-Ball FBGA ­ x16 (TB) ................................................................................................................. 35 Figure 15: Simplified State Diagram ............................................................................................................... 37 Figure 16: RESET and Initialization Sequence at Power-On Ramping ............................................................... 43 Figure 17: RESET Procedure at Power Stable Condition ................................................................................... 44 Figure 18: tMRD Timing ................................................................................................................................ 46 Figure 19: tMOD Timing ................................................................................................................................ 46 Figure 20: DLL-Off Mode Read Timing Operation ........................................................................................... 76 Figure 21: DLL Switch Sequence from DLL-On to DLL-Off .............................................................................. 78 Figure 22: DLL Switch Sequence from DLL-Off to DLL-On .............................................................................. 79 Figure 23: Write Leveling Concept, Example 1 ................................................................................................ 81 Figure 24: Write Leveling Concept, Example 2 ................................................................................................ 82 Figure 25: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 84 Figure 26: Write Leveling Exit ......................................................................................................................... 85 Figure 27: CAL Timing Definition ................................................................................................................... 86 Figure 28: CAL Timing Example (Consecutive CS_n = LOW) ............................................................................ 86 Figure 29: CAL Enable Timing ­ tMOD_CAL ................................................................................................... 87 Figure 30: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled ....................................................... 87 Figure 31: CAL Enabling MRS to Next MRS Command, tMRD_CAL .................................................................. 88 Figure 32: tMRD_CAL, Mode Register Cycle Time With CAL Enabled ............................................................... 88 Figure 33: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group ............................................... 89 Figure 34: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group ............................................... 89 Figure 35: Auto Self Refresh Ranges ................................................................................................................ 92 Figure 36: MPR Block Diagram ....................................................................................................................... 93 Figure 37: MPR READ Timing ........................................................................................................................ 99 Figure 38: MPR Back-to-Back READ Timing .................................................................................................. 100 Figure 39: MPR READ-to-WRITE Timing ....................................................................................................... 101 Figure 40: MPR WRITE and WRITE-to-READ Timing ..................................................................................... 102 Figure 41: MPR Back-to-Back WRITE Timing ................................................................................................. 103 Figure 42: REFRESH Timing .......................................................................................................................... 103 Figure 43: READ-to-REFRESH Timing ........................................................................................................... 104 Figure 44: WRITE-to-REFRESH Timing ......................................................................................................... 104 Figure 45: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) ......................................................... 107 Figure 46: Clock Mode Change After Exiting Self Refresh ................................................................................ 107 Figure 47: Comparison Between Gear-Down Disable and Gear-Down Enable ................................................. 108 Figure 48: Maximum Power-Saving Mode Entry ............................................................................................. 109 Figure 49: Maximum Power-Saving Mode Entry with PDA .............................................................................. 110 Figure 50: Maintaining Maximum Power-Saving Mode with CKE Transition ................................................... 110

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Figure 51: Maximum Power-Saving Mode Exit ............................................................................................... 111 Figure 52: Command/Address Parity Operation ............................................................................................. 112 Figure 53: Command/Address Parity During Normal Operation ..................................................................... 114 Figure 54: Persistent CA Parity Error Checking Operation ............................................................................... 115 Figure 55: CA Parity Error Checking ­ SRE Attempt ........................................................................................ 115 Figure 56: CA Parity Error Checking ­ SRX Attempt ........................................................................................ 116 Figure 57: CA Parity Error Checking ­ PDE/PDX ............................................................................................ 116 Figure 58: Parity Entry Timing Example ­ tMRD_PAR ..................................................................................... 117 Figure 59: Parity Entry Timing Example ­ tMOD_PAR ..................................................................................... 117 Figure 60: Parity Exit Timing Example ­ tMRD_PAR ....................................................................................... 117 Figure 61: Parity Exit Timing Example ­ tMOD_PAR ....................................................................................... 118 Figure 62: CA Parity Flow Diagram ................................................................................................................ 119 Figure 63: PDA Operation Enabled, BL8 ........................................................................................................ 121 Figure 64: PDA Operation Enabled, BC4 ........................................................................................................ 121 Figure 65: MRS PDA Exit ............................................................................................................................... 122 Figure 66: VREFDQ Voltage Range ................................................................................................................... 123 Figure 67: Example of VREF Set Tolerance and Step Size .................................................................................. 125 Figure 68: VREFDQ Timing Diagram for VREF,time Parameter .............................................................................. 126 Figure 69: VREFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 127 Figure 70: VREF Step: Single Step Size Increment Case .................................................................................... 128 Figure 71: VREF Step: Single Step Size Decrement Case ................................................................................... 128 Figure 72: VREF Full Step: From VREF,min to VREF,maxCase .................................................................................. 129 Figure 73: VREF Full Step: From VREF,max to VREF,minCase .................................................................................. 129 Figure 74: VREFDQ Equivalent Circuit ............................................................................................................. 130 Figure 75: Connectivity Test Mode Entry ....................................................................................................... 134 Figure 76: hPPR WRA ­ Entry ........................................................................................................................ 137 Figure 77: hPPR WRA ­ Repair and Exit ......................................................................................................... 138 Figure 78: hPPR WR ­ Entry .......................................................................................................................... 139 Figure 79: hPPR WR ­ Repair and Exit ............................................................................................................ 139 Figure 80: sPPR ­ Entry ................................................................................................................................. 142 Figure 81: sPPR ­ Repair, and Exit ................................................................................................................. 142 Figure 82: tRRD Timing ................................................................................................................................ 145 Figure 83: tFAW Timing ................................................................................................................................. 145 Figure 84: REFRESH Command Timing ......................................................................................................... 147 Figure 85: Postponing REFRESH Commands (Example) ................................................................................. 147 Figure 86: Pulling In REFRESH Commands (Example) ................................................................................... 147 Figure 87: TCR Mode Example1 ..................................................................................................................... 150 Figure 88: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 153 Figure 89: OTF REFRESH Command Timing ................................................................................................. 154 Figure 90: Self Refresh Entry/Exit Timing ...................................................................................................... 157 Figure 91: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 158 Figure 92: Self Refresh Abort ......................................................................................................................... 159 Figure 93: Self Refresh Exit with NOP Command ............................................................................................ 160 Figure 94: Active Power-Down Entry and Exit ................................................................................................ 162 Figure 95: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 163 Figure 96: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 163 Figure 97: Power-Down Entry After Write ...................................................................................................... 164 Figure 98: Precharge Power-Down Entry and Exit .......................................................................................... 164 Figure 99: REFRESH Command to Power-Down Entry ................................................................................... 165 Figure 100: Active Command to Power-Down Entry ....................................................................................... 165 Figure 101: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry ................................................ 166 Figure 102: MRS Command to Power-Down Entry ......................................................................................... 166

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Figure 103: Power-Down Entry/Exit Clarifications ­ Case 1 ............................................................................ 167
Figure 104: Active Power-Down Entry and Exit Timing with CAL .................................................................... 167
Figure 105: REFRESH Command to Power-Down Entry with CAL ................................................................... 168
Figure 106: ODT Power-Down Entry with ODT Buffer Disable Mode .............................................................. 169
Figure 107: ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................. 170
Figure 108: CRC Write Data Operation .......................................................................................................... 171
Figure 109: CRC Error Reporting ................................................................................................................... 180
Figure 110: CA Parity Flow Diagram .............................................................................................................. 181 Figure 111: 1tCK vs. 2tCK WRITE Preamble Mode ........................................................................................... 186 Figure 112: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 ............................................................................ 187 Figure 113: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 ............................................................................ 188 Figure 114: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 ........................................................................... 188 Figure 115: 1tCK vs. 2tCK READ Preamble Mode ............................................................................................ 189
Figure 116: READ Preamble Training ............................................................................................................. 190
Figure 117: WRITE Postamble ....................................................................................................................... 190
Figure 118: READ Postamble ........................................................................................................................ 191
Figure 119: Bank Group x4/x8 Block Diagram ................................................................................................ 192 Figure 120: READ Burst tCCD_S and tCCD_L Examples .................................................................................. 193 Figure 121: Write Burst tCCD_S and tCCD_L Examples ................................................................................... 193 Figure 122: tRRD Timing ............................................................................................................................... 194 Figure 123: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) ......................... 194 Figure 124: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) .............................. 195
Figure 125: Read Timing Definition ............................................................................................................... 197
Figure 126: Clock-to-Data Strobe Relationship .............................................................................................. 198
Figure 127: Data Strobe-to-Data Relationship ................................................................................................ 199 Figure 128: tLZ and tHZ Method for Calculating Transitions and Endpoints .................................................... 200 Figure 129: tRPRE Method for Calculating Transitions and Endpoints ............................................................. 201 Figure 130: tRPST Method for Calculating Transitions and Endpoints ............................................................. 202
Figure 131: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) ................................................................... 203
Figure 132: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) ................................................................. 204 Figure 133: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group .......................................... 205 Figure 134: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group .......................................... 205 Figure 135: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group ....................... 206 Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group ....................... 206 Figure 137: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group ...................................... 207 Figure 138: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group ...................................... 207 Figure 139: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ............................... 208 Figure 140: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group ............................... 208 Figure 141: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group ............................... 209 Figure 142: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group ............................... 209 Figure 143: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group ........................ 210 Figure 144: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group ........................ 210 Figure 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group ......... 211 Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group ......... 212 Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group ..... 212 Figure 148: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group ..... 213 Figure 149: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group ................ 214 Figure 150: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group ................ 214 Figure 151: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group ................ 215 Figure 152: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group ................ 215 Figure 153: READ to PRECHARGE with 1tCK Preamble .................................................................................. 216 Figure 154: READ to PRECHARGE with 2tCK Preamble .................................................................................. 217

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Figure 155: READ to PRECHARGE with Additive Latency and 1tCK Preamble .................................................. 217 Figure 156: READ with Auto Precharge and 1tCK Preamble ............................................................................ 218 Figure 157: READ with Auto Precharge, Additive Latency, and 1tCK Preamble ................................................. 219 Figure 158: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group ............................ 219 Figure 159: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group .................... 220 Figure 160: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group ... 221 Figure 161: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 222 Figure 162: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 223 Figure 163: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group .................. 223 Figure 164: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group .................. 224
Figure 165: Write Timing Definition .............................................................................................................. 226 Figure 166: tWPRE Method for Calculating Transitions and Endpoints ............................................................ 227 Figure 167: tWPST Method for Calculating Transitions and Endpoints ............................................................ 228
Figure 168: Rx Compliance Mask .................................................................................................................. 229
Figure 169: VCENT_DQ VREFDQ Voltage Variation .............................................................................................. 229 Figure 170: Rx Mask DQ-to-DQS Timings ...................................................................................................... 230
Figure 171: Rx Mask DQ-to-DQS DRAM-Based Timings ................................................................................. 231
Figure 172: Example of Data Input Requirements Without Training ................................................................ 232
Figure 173: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) ................................................................. 233
Figure 174: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) ............................................................. 234 Figure 175: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group ........................................ 234 Figure 176: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group ........................................ 235 Figure 177: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group ..................... 236 Figure 178: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group ..................... 236 Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group .................... 237 Figure 180: WRITE (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Different Bank Group .................... 238 Figure 181: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 238 Figure 182: WRITE (BL8) to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group ............................ 239 Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1 tCK Preamble in Different Bank Group ............................ 240 Figure 184: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group ..................................... 240 Figure 185: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group .......................................... 241 Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ...................... 242 Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group ........................... 242 Figure 188: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 243 Figure 189: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group ....................... 243 Figure 190: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble ........................................................ 244 Figure 191: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble .............................................................. 245 Figure 192: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble ................................................ 245 Figure 193: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble ...................................................... 246 Figure 194: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI ................................................................... 247 Figure 195: WRITE (BC4-Fixed) with 1tCK Preamble and DBI ......................................................................... 248 Figure 196: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group ..................... 249 Figure 197: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank
Group ....................................................................................................................................................... 250 Figure 198: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank
Group ....................................................................................................................................................... 251 Figure 199: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 252 Figure 200: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 253

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Figure 201: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group .2..54 Figure 202: ZQ Calibration Timing ................................................................................................................ 257 Figure 203: Functional Representation of ODT .............................................................................................. 258 Figure 204: Synchronous ODT Timing with BL8 ............................................................................................. 261 Figure 205: Synchronous ODT with BC4 ........................................................................................................ 261 Figure 206: ODT During Reads ...................................................................................................................... 262 Figure 207: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......................... 264 Figure 208: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......... 265 Figure 209: Asynchronous ODT Timings with DLL Off ................................................................................... 266 Figure 210: VREFDQ Voltage Range .................................................................................................................. 269 Figure 211: RESET_n Input Slew Rate Definition ............................................................................................ 272 Figure 212: Single-Ended Input Slew Rate Definition ..................................................................................... 274 Figure 213: DQ Slew Rate Definitions ............................................................................................................ 277 Figure 214: Rx Mask Relative to tDS/tDH ....................................................................................................... 279 Figure 215: Rx Mask Without Write Training .................................................................................................. 280 Figure 216: TEN Input Slew Rate Definition ................................................................................................... 281 Figure 217: CT Type-A Input Slew Rate Definition .......................................................................................... 281 Figure 218: CT Type-B Input Slew Rate Definition .......................................................................................... 282 Figure 219: CT Type-C Input Slew Rate Definition .......................................................................................... 283 Figure 220: CT Type-D Input Slew Rate Definition ......................................................................................... 283 Figure 221: Differential AC Swing and "Time Exceeding AC-Level" tDVAC ....................................................... 284 Figure 222: Single-Ended Requirements for CK .............................................................................................. 286 Figure 223: Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 287 Figure 224: VIX(CK) Definition ........................................................................................................................ 287 Figure 225: Differential Input Signal Definition for DQS_t, DQS_c .................................................................. 288 Figure 226: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling ..... 289 Figure 227: VIXDQS Definition ........................................................................................................................ 290 Figure 228: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c ..................................... 291 Figure 229: ADDR, CMD, CNTL Overshoot and Undershoot Definition ........................................................... 293 Figure 230: CK Overshoot and Undershoot Definition .................................................................................... 294 Figure 231: Data, Strobe, and Mask Overshoot and Undershoot Definition ..................................................... 295 Figure 232: Single-ended Output Slew Rate Definition ................................................................................... 296 Figure 233: Differential Output Slew Rate Definition ...................................................................................... 298 Figure 234: Reference Load For AC Timing and Output Slew Rate ................................................................... 299 Figure 235: Connectivity Test Mode Reference Test Load ................................................................................ 299 Figure 236: Connectivity Test Mode Output Slew Rate Definition .................................................................... 300 Figure 237: Output Driver During Connectivity Test Mode ............................................................................. 301 Figure 238: Output Driver: Definition of Voltages and Currents ...................................................................... 302 Figure 239: Alert Driver ................................................................................................................................ 306 Figure 240: ODT Definition of Voltages and Currents ..................................................................................... 307 Figure 241: ODT Timing Reference Load ....................................................................................................... 308 Figure 242: tADC Definition with Direct ODT Control .................................................................................... 310 Figure 243: tADC Definition with Dynamic ODT Control ................................................................................ 310 Figure 244: tAOFAS and tAONAS Definitions .................................................................................................. 311 Figure 245: Thermal Measurement Point ....................................................................................................... 317 Figure 246: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx ........................................................... 318 Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power ....................................... 319

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4Gb: x4, x8, x16 DDR4 SDRAM Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 2 Table 2: Addressing ......................................................................................................................................... 2 Table 3: Ball Descriptions .............................................................................................................................. 26 Table 4: State Diagram Command Definitions ................................................................................................ 38 Table 5: Supply Power-up Slew Rate ............................................................................................................... 40 Table 6: Address Pin Mapping ........................................................................................................................ 48 Table 7: MR0 Register Definition .................................................................................................................... 48 Table 8: Burst Type and Burst Order ............................................................................................................... 50 Table 9: Address Pin Mapping ........................................................................................................................ 52 Table 10: MR1 Register Definition .................................................................................................................. 52 Table 11: Additive Latency (AL) Settings ......................................................................................................... 54 Table 12: TDQS Function Matrix .................................................................................................................... 55 Table 13: Address Pin Mapping ...................................................................................................................... 56 Table 14: MR2 Register Definition .................................................................................................................. 56 Table 15: Address Pin Mapping ...................................................................................................................... 59 Table 16: MR3 Register Definition .................................................................................................................. 59 Table 17: Address Pin Mapping ...................................................................................................................... 62 Table 18: MR4 Register Definition .................................................................................................................. 62 Table 19: Address Pin Mapping ...................................................................................................................... 66 Table 20: MR5 Register Definition .................................................................................................................. 66 Table 21: Address Pin Mapping ...................................................................................................................... 69 Table 22: MR6 Register Definition .................................................................................................................. 69 Table 23: Truth Table ­ Command .................................................................................................................. 72 Table 24: Truth Table ­ CKE ........................................................................................................................... 74 Table 25: MR Settings for Leveling Procedures ................................................................................................ 82 Table 26: DRAM TERMINATION Function in Leveling Mode ........................................................................... 82 Table 27: Auto Self Refresh Mode ................................................................................................................... 91 Table 28: MR3 Setting for the MPR Access Mode ............................................................................................. 93 Table 29: DRAM Address to MPR UI Translation ............................................................................................. 93 Table 30: MPR Page and MPRx Definitions ..................................................................................................... 94 Table 31: MPR Readout Serial Format ............................................................................................................. 96 Table 32: MPR Readout ­ Parallel Format ....................................................................................................... 97 Table 33: MPR Readout Staggered Format, x4 ................................................................................................. 98 Table 34: MPR Readout Staggered Format, x4 ­ Consecutive READs ................................................................ 98 Table 35: MPR Readout Staggered Format, x8 and x16 ..................................................................................... 99 Table 36: Mode Register Setting for CA Parity ................................................................................................. 114 Table 37: VREFDQ Range and Levels ................................................................................................................ 124 Table 38: VREFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 130 Table 39: Connectivity Mode Pin Description and Switching Levels ................................................................ 132 Table 40: PPR MR0 Guard Key Settings .......................................................................................................... 136 Table 41: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 139 Table 42: sPPR Associated Rows .................................................................................................................... 140 Table 43: PPR MR0 Guard Key Settings .......................................................................................................... 141 Table 44: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 142 Table 45: DDR4 Repair Mode Support Identifier ............................................................................................ 142 Table 46: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 144 Table 47: Normal tREFI Refresh (TCR Enabled) .............................................................................................. 148 Table 48: MRS Definition .............................................................................................................................. 151 Table 49: REFRESH Command Truth Table .................................................................................................... 151 Table 50: tREFI and tRFC Parameters ............................................................................................................. 152

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Table 51: Power-Down Entry Definitions ....................................................................................................... 161 Table 52: CRC Error Detection Coverage ........................................................................................................ 172 Table 53: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 174 Table 54: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 174 Table 55: CRC Data Mapping for x16 Devices, BL8 ......................................................................................... 175 Table 56: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 175 Table 57: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 176 Table 58: CRC Data Mapping for x16 Devices, BC4 ......................................................................................... 177 Table 59: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 182 Table 60: DBI Write, DQ Frame Format (x8) ................................................................................................... 182 Table 61: DBI Write, DQ Frame Format (x16) ................................................................................................. 182 Table 62: DBI Read, DQ Frame Format (x8) .................................................................................................... 183 Table 63: DBI Read, DQ Frame Format (x16) .................................................................................................. 183 Table 64: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 184 Table 65: Data Mask, DQ Frame Format (x8) .................................................................................................. 184 Table 66: Data Mask, DQ Frame Format (x16) ................................................................................................ 184 Table 67: CWL Selection ............................................................................................................................... 187 Table 68: DDR4 Bank Group Timing Examples .............................................................................................. 192 Table 69: Read-to-Write and Write-to-Read Command Intervals .................................................................... 197 Table 70: Termination State Table ................................................................................................................. 259 Table 71: Read Termination Disable Window ................................................................................................. 259 Table 72: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 260 Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) ................................ 263 Table 74: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix ............................ 264 Table 75: Absolute Maximum Ratings ............................................................................................................ 267 Table 76: Temperature Range ........................................................................................................................ 267 Table 77: Recommended Supply Operating Conditions .................................................................................. 268 Table 78: VDD Slew Rate ................................................................................................................................ 268 Table 79: Leakages ....................................................................................................................................... 269 Table 80: VREFDQ Specification ...................................................................................................................... 270 Table 81: VREFDQ Range and Levels ................................................................................................................ 271 Table 82: RESET_n Input Levels (CMOS) ....................................................................................................... 272 Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 ........................................... 272 Table 84: Command and Address Input Levels: DDR4-2666 ............................................................................ 273 Table 85: Command and Address Input Levels: DDR4-2933 and DDR4-3200 ................................................... 273 Table 86: Single-Ended Input Slew Rates ....................................................................................................... 274 Table 87: Command and Address Setup and Hold Values Referenced ­ AC/DC-Based ..................................... 275 Table 88: Derating Values for tIS/tIH ­ AC100DC75-Based .............................................................................. 275 Table 89: Derating Values for tIS/tIH ­ AC90/DC65-Based .............................................................................. 276 Table 90: DQ Input Receiver Specifications .................................................................................................... 277 Table 91: Rx Mask and tDS/tDH without Write Training .................................................................................. 280 Table 92: TEN Input Levels (CMOS) .............................................................................................................. 280 Table 93: CT Type-A Input Levels .................................................................................................................. 281 Table 94: CT Type-B Input Levels .................................................................................................................. 282 Table 95: CT Type-C Input Levels (CMOS) ..................................................................................................... 282 Table 96: CT Type-D Input Levels .................................................................................................................. 283 Table 97: Differential Input Swing Requirements for CK_t, CK_c ..................................................................... 284 Table 98: Minimum Time AC Time tDVAC for CK ........................................................................................... 285 Table 99: Single-Ended Requirements for CK ................................................................................................. 286 Table 100: CK Differential Input Slew Rate Definition ..................................................................................... 286 Table 101: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 ................ 288 Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 ................ 288

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c ............. 288 Table 104: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c ............. 289 Table 105: Cross Point Voltage For Differential Input Signals DQS ................................................................... 290 Table 106: DQS Differential Input Slew Rate Definition .................................................................................. 291 Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 291 Table 108: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 292 Table 109: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 293 Table 110: CK Overshoot and Undershoot/ Specifications .............................................................................. 294 Table 111: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 295 Table 112: Single-Ended Output Levels ......................................................................................................... 295 Table 113: Single-Ended Output Slew Rate Definition .................................................................................... 296 Table 114: Single-Ended Output Slew Rate .................................................................................................... 297 Table 115: Differential Output Levels ............................................................................................................. 297 Table 116: Differential Output Slew Rate Definition ....................................................................................... 297 Table 117: Differential Output Slew Rate ....................................................................................................... 298 Table 118: Connectivity Test Mode Output Levels .......................................................................................... 299 Table 119: Connectivity Test Mode Output Slew Rate ..................................................................................... 300 Table 120: Output Driver Electrical Characteristics During Connectivity Test Mode ......................................... 302 Table 121: Strong Mode (34) Output Driver Electrical Characteristics ........................................................... 303 Table 122: Weak Mode (48) Output Driver Electrical Characteristics ............................................................. 304 Table 123: Output Driver Sensitivity Definitions ............................................................................................ 305 Table 124: Output Driver Voltage and Temperature Sensitivity ....................................................................... 305 Table 125: Alert Driver Voltage ...................................................................................................................... 306 Table 126: ODT DC Characteristics ............................................................................................................... 307 Table 127: ODT Sensitivity Definitions .......................................................................................................... 308 Table 128: ODT Voltage and Temperature Sensitivity ..................................................................................... 308 Table 129: ODT Timing Definitions ............................................................................................................... 309 Table 130: Reference Settings for ODT Timing Measurements ........................................................................ 309 Table 131: DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 312 Table 132: DRAM Package Electrical Specifications for x16 Devices ................................................................ 313 Table 133: Pad Input/Output Capacitance ..................................................................................................... 315 Table 134: Thermal Characteristics ............................................................................................................... 316 Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions .......................................................................... 319 Table 136: IDD0 and IPP0 Measurement-Loop Pattern1 .................................................................................... 323 Table 137: IDD1 Measurement ­ Loop Pattern1 ............................................................................................... 324 Table 138: IDD2N, IDD3N, and IPP3P Measurement ­ Loop Pattern1 .................................................................... 325 Table 139: IDD2NT Measurement ­ Loop Pattern1 ............................................................................................ 326 Table 140: IDD4R Measurement ­ Loop Pattern1 .............................................................................................. 327 Table 141: IDD4W Measurement ­ Loop Pattern1 ............................................................................................. 328 Table 142: IDD4Wc Measurement ­ Loop Pattern1 ............................................................................................ 329 Table 143: IDD5R Measurement ­ Loop Pattern1 .............................................................................................. 330 Table 144: IDD7 Measurement ­ Loop Pattern1 ............................................................................................... 331 Table 145: Timings used for IDD, IPP, and IDDQ Measurement ­ Loop Patterns .................................................. 332 Table 146: IDD, IPP, and IDDQ Current Limits ­ Rev. A (0°  TC  85°C) ............................................................... 333 Table 147: IDD, IPP, and IDDQ Current Limits ­ Rev. B (0°  TC  85°C) ............................................................... 334 Table 148: IDD, IPP, and IDDQ Current Limits ­ Rev. E (0°  TC  85°C) ............................................................... 336 Table 149: IDD, IPP, and IDDQ Current Limits ­ Rev. F (-40°  TC  85°C) ............................................................ 339 Table 150: IDD, IPP, and IDDQ Current Limits ­ Rev. G (-40°  TC  85°C) ............................................................ 341 Table 151: Backward Compatibility ............................................................................................................... 345 Table 152: DDR4-1600 Speed Bins and Operating Conditions ......................................................................... 347 Table 153: DDR4-1866 Speed Bins and Operating Conditions ......................................................................... 349 Table 154: DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 351

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4Gb: x4, x8, x16 DDR4 SDRAM Features
Table 155: DDR4-2400 Speed Bins and Operating Conditions ......................................................................... 353 Table 156: DDR4-2666 Speed Bins and Operating Conditions ......................................................................... 355 Table 157: DDR4-2933 Speed Bins and Operating Conditions ......................................................................... 358 Table 158: DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 361 Table 159: Refresh Parameters by Device Density ........................................................................................... 363 Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 ................... 364 Table 161: Electrical Characteristics and AC Timing Parameters ..................................................................... 376 Table 162: Options ­ Speed Based ................................................................................................................. 389 Table 163: Options ­ Width Based ................................................................................................................. 390

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4Gb: x4, x8, x16 DDR4 SDRAM Important Notes and Warnings

Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative.

General Notes and Description

Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the

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4Gb: x4, x8, x16 DDR4 SDRAM General Notes and Description

x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Industrial Temperature
An industrial temperature (IT) device option requires that the case temperature not exceed below ­40°C or above 95°C. JEDEC specifications require the refresh rate to double when TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when operating outside of the commercial temperature range, when TC is between ­40°C and 0°C.

Automotive Temperature
The automotive temperature (AT) device option requires that the case temperature not exceed below ­40°C or above 105°C. The specifications require the refresh rate to 2X when TC exceeds 85°C; 4X when TC exceeds 95°C. Additionally, ODT resistance and the input/output impedance must be derated when operating temperature Tc <0°C.

General Notes

· The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation), unless specifically stated otherwise.
· Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.
· The terms "_t" and "_c" are used to represent the true and complement of a differential signal pair. These terms replace the previously used notation of "#" and/or overbar characters. For example, differential data strobe pair DQS, DQS# is now referred to as DQS_t, DQS_c.
· The term "_n" is used to represent a signal that is active LOW and replaces the previously used "#" and/or overbar characters. For example: CS# is now referred to as CS_n.
· The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.
· Complete functionality may be described throughout the entire document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
· Any specific requirement takes precedence over a general statement.
· Any functionality not specifically stated here within is considered undefined, illegal, and not supported, and can result in unknown operation.
· Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for row/col address.
· The NOP command is not allowed, except when exiting maximum power savings mode or when entering gear-down mode, and only a DES command should be used.

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4Gb: x4, x8, x16 DDR4 SDRAM General Notes and Description
· Not all features described within this document may be available on the Rev. A (first) version.
· Not all specifications listed are finalized industry standards; best conservative estimates have been provided when an industry standard has not been finalized.
· Although it is implied throughout the specification, the DRAM must be used after VDD has reached the stable power-on level, which is achieved by toggling CKE at least once every 8192 × tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least once every 8192 × tREFI is an acceptable alternative. Placing the DRAM into self refresh mode also alleviates the need to toggle CKE.
· Not all features designated in the data sheet may be supported by earlier die revisions due to late definition by JEDEC.
· A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted:
­ Connect UDQS_t to VDDQ or VSS/ VSSQ via a resistor in the 200  range. ­ Connect UDQS_c to the opposite rail via a resistor in the same 200 range. ­ Connect UDM to VDDQ via a large (10,000) pull-up resistor. ­ Connect UDBI to VDDQ via a large (10,000) pull-up resistor. ­ Connect DQ [15:8] individually to VDDQ via a large (10,000) resistors, or float DQ
[15:8] .
Definitions of the Device-Pin Signal Level
· HIGH: A device pin is driving the logic 1 state. · LOW: A device pin is driving the logic 0 state. · High-Z: A device pin is tri-state. · ODT: A device pin terminates with the ODT setting, which could be terminating or tri-
state depending on the mode register setting.
Definitions of the Bus Signal Level
· HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT or High-Z. The voltage level on the bus is nominally V DDQ.
· LOW: One device on the bus is LOW, and all other devices on the bus are either ODT or High-Z. The voltage level on the bus is nominally V OL(DC) if ODT was enabled, or VSSQ if High-Z.
· High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as the bus is floating.
· ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage level on the bus is nominally VDDQ.
· The specification requires 8,192 refresh commands within 64ms between 0 oC and 85 oC. This allows for a tREFI of 7.8125s (the use of "7.8s" is truncated from 7.8125s). The specification also requires 8,192 refresh commands within 32ms between 85 oC and 95 oC. This allows for a tREFI of 3.90625s (the use of "3.9s" is truncated from 3.90625s).

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4Gb: x4, x8, x16 DDR4 SDRAM Functional Block Diagrams
Functional Block Diagrams
DDR4 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 16-bank (4-banks per Bank Group) DRAM.

Figure 2: 1 Gig x 4 Functional Block Diagram

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. M 03/2020 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Functional Block Diagrams

Figure 4: 256 Meg x 16 Functional Block Diagram

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

Ball Assignments

4Gb: x4, x8, x16 DDR4 SDRAM Ball Assignments

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dressing).

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Ball Assignments

Figure 6: 96-Ball x16 Ball Assignments



















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4Gb: x4, x8, x16 DDR4 SDRAM Ball Descriptions

Ball Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4 devices. All pins listed may not be supported on the device defined in this data sheet. See the Ball Assignments section to review all pins used on this device.

Table 3: Ball Descriptions

Symbol A[17:0]

Type Input

A10/AP

Input

A12/BC_n ACT_n

Input Input

BA[1:0] BG[1:0]

Input Input

C0/CKE1, C1/CS1_n, C2/ODT1

Input

CK_t, CK_c

Input

Description
Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional functions, see individual entries in this table.) The address inputs also provide the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and 16Gb parts. A17 connection is part-number specific; Contact vendor for more information.
Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses.
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chopped). See the Command Truth Table.
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command Truth Table.
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command.
Bank group address inputs: Define the bank group to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. BG1 is not used in the x16 configuration.
Stack address inputs: These inputs are used only when devices are stacked; that is, they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not used in the x16 configuration). DDR4 will support a traditional DDP package, which uses these three signals for control of the second die (CS1_n, CKE1, ODT1). DDR4 is not expected to support a traditional QDP package. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of configuration where C0, C1, and C2 are used as chip ID selects in conjunction with a single CS_n, CKE, and ODT signal.
Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.

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4Gb: x4, x8, x16 DDR4 SDRAM Ball Descriptions

Table 3: Ball Descriptions (Continued)

Symbol CKE
CS_n DM_n, UDM_n LDM_n
ODT
PAR
RAS_n/A16, CAS_n/A15, WE_n/A14
RESET_n TEN

Type Input
Input Input Input Input
Input Input Input

Description
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit, however, timing parameters such as tXS are still calculated from the first rising clock edge where CKE HIGH satisfies tIS. After VREFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET_n) are disabled during self refresh.
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides for external rank selection on systems with multiple ranks. CS_n is considered part of the command code.
Input data mask: DM_n is an input mask signal for write data. Input data is masked when DM is sampled LOW coincident with that input data during a write access. DM is sampled on both edges of DQS. DM is not supported on x4 configurations. The UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Mask section.
On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations (when the TDQS function is enabled via mode register). For the x16 configuration, RTT is applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable RTT.
Parity for command and address: This function can be enabled or disabled via the mode register. When enabled, the parity signal covers all command and address inputs, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT covered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are density- and configuration-specific should be treated internally as 0s by the DRAM parity logic. Command and address inputs will have parity check performed when commands are latched via the rising edge of CK_t and when CS_n is LOW.
Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and ACT_n) define the command and/or address being entered. See the ACT_n description in this table.
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mV for DC HIGH and 240 mV for DC LOW).
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC LOW). On Micron 3DS devices, connectivity test mode is not supported and the TEN pin should be considered NF maintained LOW at all times.

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4Gb: x4, x8, x16 DDR4 SDRAM Ball Descriptions

Table 3: Ball Descriptions (Continued)

Symbol DQ
DBI_n, UDBI_n, LDBI_n
DQS_t, DQS_c, UDQS_t, UDQS_c, LDQS_t, LDQS_c ALERT_n
TDQS_t, TDQS_c
VDD VDDQ VPP VREFCA VSS VSSQ ZQ RFU
NC NF

Type I/O
I/O
I/O
Output
Output
Supply Supply Supply Supply Supply Supply Reference
­ ­ ­

Description
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled via mode register, the write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal VREF level during test via mode register setting MR[4] A[4] = HIGH, training times change when enabled. During this mode, the RTT value should be set to High-Z. This measurement is for verification purposes and is NOT an external voltage supply pin.
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The DBI feature is not supported on the x4 configuration. DBI is not supported for 3DS devices and should be disabled in MR5. DBI can be configured for both READ (output) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Bus Inversion section.
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with READ data, centered-aligned with WRITE data. For the x16, LDQS corresponds to the data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe.
Alert output: This signal allows the DRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include the command/ address parity error and the CRC data error when either of these functions is enabled in the mode register.
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When enabled via the mode register, the DRAM will enable the same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in the mode register for both the x4 and x16 configurations. The DM function is supported only in x8 and x16 configurations.
Power supply: 1.2V ±0.060V.
DQ power supply: 1.2V ±0.060V.
DRAM activating power supply: 2.5V ­0.125V/+0.250V.
Reference voltage for control, command, and address pins.
Ground.
DQ ground.
Reference ball for ZQ calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. Reserved for future use.
No connect: No internal electrical connection is present.
No function: Internal connection is present but has no function.

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Package Dimensions
Figure 7: 78-Ball FBGA ­ x4, x8 "HX" 0.155

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions
Seating plane

1.8 CTR

A

Nonconductive

overmold

0.12 A

78X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads.

987

11.5 ±0.1 9.6 CTR

321
A B C D E F G H
J
K L M N

Ball A1 ID

Ball A1 ID

0.8 TYP

0.8 TYP 6.4 CTR 9 ±0.1

1.1 ±0.1 0.25 MIN

Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (Pb-free 96.8% Sn, 3% Ag, 0.2% Cu).

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Figure 8: 78-Ball FBGA ­ x4, x8 "RH"
0.155
1.8 CTR nonconductive
overmold

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Seating plane

A

0.12 A

78X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads.

987

10.5 ±0.1 9.6 CTR
0.8 TYP

321
A B C D E F G H J K L M N

Ball A1 ID (covered by SR)

Ball A1 ID

0.8 TYP

1.1 ±0.1

6.4 CTR

0.34 ±0.05

9 ±0.1
Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (Pb-free 96.8% Sn, 3% Ag, 0.2% Cu).

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Figure 9: 78-Ball FBGA ­ x4, x8 "WE"
0.155
1.8 CTR nonconductive
overmold

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Seating plane

A

0.12 A

78X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads.

987

12 ±0.1 9.6 CTR
0.8 TYP

321
A B C D E F G H J K L M N

Ball A1 ID (covered by SR)

0.8 TYP

1.1 ±0.1

6.4 CTR

0.34 ±0.05

8 ±0.1

Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

Ball A1 ID

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

Figure 10: 78-Ball FBGA ­ x4, x8 "SA"
0.155
1.8 CTR nonconductive
overmold

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Seating plane

A

0.12 A

78X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads.

987

11 ±0.1 9.6 CTR
0.8 TYP

321
A B C D E F G H J K L M N

Ball A1 ID (covered by SR)

0.8 TYP

1.1 ±0.1

6.4 CTR

0.34 ±0.05

7.5 ±0.1

Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

Ball A1 ID

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Figure 11: 96-Ball FBGA ­ x16 "HA"

0.155

96X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads.

1.8 CTR Nonconductive
overmold

9 8 7

3 2 1

12 CTR 0.8 TYP

Seating plane

A

0.12 A

Ball A1 Index (covered by SR)
A B C D E F G H
14 ±0.1 J K L M N P R T

Ball A1 Index

0.8 TYP 6.4 CTR 9 ±0.1

1.1 ±0.1 0.25 MIN

Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (Pb-free 96.8% Sn, 3% Ag, 0.2% Cu).

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Figure 12: 96-Ball FBGA ­ x16 "GE"

0.155
1.8 CTR Nonconductive
overmold

Seating plane

A

0.12 A

96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads.

987

14 ±0.1 12 CTR
0.8 TYP

321
A B C D E F G H J K L M N P R T

Ball A1 ID (covered by SR)

Ball A1 ID

0.8 TYP

1.1 ±0.1

6.4 CTR

0.29 MIN

9 ±0.1

Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (Pb-free 96.8% Sn, 3% Ag, 0.3% Cu).

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Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Figure 13: 96-Ball FBGA ­ x16 "LY"

0.155
A 1.8 CTR Nonconductive overmold

Seating plane 0.12 A

96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads.

987

13.5 ±0.1 12 CTR
0.8 TYP

321
A B C D E F G H J K L M N P R T

Ball A1 ID (covered by SR)

0.8 TYP

1.1 ±0.1

6.4 CTR

0.34 ±0.05

7.5 ±0.1
Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

Ball A1 ID

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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions

Figure 14: 96-Ball FBGA ­ x16 (TB) 0.155

Seating plane

A
1.8 CTR Nonconductive
overmold

0.1 A

96X Ø0.47 Dimensions apply to solder balls post-reflow on Ø0.42 SMD ball pads.

987

13 ±0.1 12 CTR
0.8 TYP

321
A B C D E F G H J K L M N P R T

Ball A1 ID (covered by SR)

0.8 TYP

1.1 ±0.1

6.4 CTR

0.34 ±0.05

7.5 ±0.1
Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).

Ball A1 ID

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4Gb: x4, x8, x16 DDR4 SDRAM State Diagram

State Diagram

This simplified state diagram provides an overview of the possible state transitions and the commands to control them. Situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail.

Figure 15: Simplified State Diagram

MPSM

IVREFDQ, RTT, and so on

From any state RESET SRX* = SRX with NOP

SRX*

MRS

Power
applied Power-On

RESET

TEN = 1

Reset procedure

Initialization

MRS SRX*
PDA mode

MRS, MPR, write leveling, VREFDQ training

TEN = 1

ZQCL

MRS

MRS MRS

MRS

SRE

Connectivity test

ZQ

calibration ZQCL,ZQCS

Idle

REF

TEN = 0

RESET

CKE_L

ACT

PDE

PDX

CKE_L
Self refresh
SRX
Refreshing
CKE_L

Active powerdown
PDX

Activating

Precharge powerdown

PDE

WRITE
Writing

WRITE

Bank active

READ

WRITE A WRITE

READ A READ

READ
Reading

WRITE A
Writing

WRITE A

READ A

PRE, PREA

PRE, PREA

PRE, PREA

READ A
Reading

Precharging

Automatic sequence
Command sequence

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4Gb: x4, x8, x16 DDR4 SDRAM State Diagram

Table 4: State Diagram Command Definitions

Command ACT MPR MRS PDE PDX PRE PREA READ READ A REF RESET SRE SRX TEN WRITE WRITE A ZQCL ZQCS

Description Active Multipurpose register Mode register set Enter power-down Exit power-down Precharge Precharge all RD, RDS4, RDS8 RDA, RDAS4, RDAS8 Refresh, fine granularity refresh Start reset procedure Self refresh entry Self refresh exit Boundary scan mode enable WR, WRS4, WRS8 with/without CRC WRA, WRAS4, WRAS8 with/without CRC ZQ calibration long ZQ calibration short
Note: 1. See the Command Truth Table for more details.

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4Gb: x4, x8, x16 DDR4 SDRAM Functional Description
Functional Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devices, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16 devices. The device uses double data rate (DDR) architecture to achieve high-speed operation. DDR4 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for a device module effectively consists of a single 8n-bit-wide, four-clockcycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected location and continue for a burst length of eight or a chopped burst of four in a programmed sequence. Operation begins with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0] select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select the bank, and A[17:0] select the row. See the Addressing section for more details). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst operation, determine if the auto PRECHARGE command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via A12) if enabled in the mode register.
Prior to normal operation, the device must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.
NOTE: The use of the NOP command is allowed only when exiting maximum power saving mode or when entering gear-down mode.

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4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure

RESET and Initialization Procedure
To ensure proper device function, the power-up and reset initialization default values for the following mode register (MR) settings are defined as:
· Gear-down mode (MR3 A[3]): 0 = 1/2 rate · Per-DRAM addressability (MR3 A[4]): 0 = disable · Maximum power-saving mode (MR4 A[1]): 0 = disable · CS to command/address latency (MR4 A[8:6]): 000 = disable · CA parity latency mode (MR5 A[2:0]): 000 = disable · Hard post package repair mode (MR4 A[13]): 0 = disable · Soft post package repair mode (MR4 A[5]): 0 = disable
Power-Up and Initialization Sequence
The following sequence is required for power-up and initialization: 1. Apply power (RESET_n and TEN should be maintained below 0.2 × VDD while supplies ramp up; all other inputs may be undefined). When supplies have ramped to a valid stable level, RESET_n must be maintained below 0.2 × VDD for a minimum of tPW_RESET_L and TEN must be maintained below 0.2 × VDD for a minimum of 700s. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time of 10ns). The power voltage ramp time between 300mV to V DD,min must be no greater than 200ms, and during the ramp, VDD must be greater than or equal to VDDQ and (VDD - VDDQ) < 0.3V. VPP must ramp at the same time or up to 10 minutes prior to VDD, and VPP must be equal to or higher than VDD at all times. The total time for which VPP is powered and VDD is unpowered should not exceed 360 cumulative hours. After VDD has ramped and reached a stable level, RESET_n must go high within 10 minutes. After RESET_n goes high, the initialization sequence must be started within 3 seconds. For debug purposes, the 10 minute and 3 second delay limits may be extended to 60 minutes each provided the DRAM is operated in this debug mode for no more than 360 cumulative hours.
During power-up, the supply slew rate is governed by the limits stated in the table below and either condition A or condition B listed below must be met.

Table 5: Supply Power-up Slew Rate

Symbol VDD_SL, VDDQ_SL, VPP_SL VDD_ona
VDDQ_ona

Min 0.004
N/A
N/A

Max 600
200
200

Unit Comment
V/ms Measured between 300mV and 80% of supply minimum
ms VDD maximum ramp time from 300mV to VDD minimum
ms VDDQ maximum ramp time from 300mV to VDDQ minimum

Note: 1. 20 MHz band-limited measurement.

· Condition A:
­ Apply VPP without any slope reversal before or at the same time as VDD and VDDQ.

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4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure
­ VDD and VDDQ are driven from a single-power converter output and apply VDD/VDDQ without any slope reversal before or at the same time as VTT and VREFCA.
­ The voltage levels on all balls other than VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and must be greater than or equal to VSSQ and VSS on the other side.
­ VTT is limited to 0.76V MAX when the power ramp is complete.
­ VREFCA tracks VDD/2.
· Condition B:
­ Apply VPP without any slope reversal before or at the same time as VDD.
­ Apply VDD without any slope reversal before or at the same time as VDDQ.
­ Apply VDDQ without any slope reversal before or at the same time as VTT and VREFCA.
­ The voltage levels on all pins other than VPP, VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET_n is de-asserted, wait for another 500s but no longer then 3 seconds until CKE becomes active. During this time, the device will start internal state initialization; this will be done independently of external clocks. A reasonable attempt was made in the design to power up with the following default MR settings: geardown mode (MR3 A[3]): 0 = 1/2 rate; per-DRAM addressability (MR3 A[4]): 0 = disable; maximum power-down (MR4 A[1]): 0 = disable; CS to command/address latency (MR4 A[8:6]): 000 = disable; CA parity latency mode (MR5 A[2:0]): 000 = disable. However, it should be assumed that at power up the MR settings are undefined and should be programmed as shown below.
3. Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 tCK (whichever is larger) before CKE goes active. Because CKE is a synchronous signal, the corresponding setup time to clock (tIS) must be met. Also, a DESELECT command must be registered (with tIS setup time to clock) at clock edge Td. After the CKE is registered HIGH after RESET, CKE needs to be continuously registered HIGH until the initialization sequence is finished, including expiration of tDLLK and tZQinit.
4. The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further, the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is registered HIGH. The ODT input signal may be in an undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held either LOW or HIGH. If RTT(NOM) is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power-up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, tXPR, before issuing the first MRS command to load mode register (tXPR = MAX (tXS, 5 × tCK).
6. Issue MRS command to load MR3 with all application settings, wait tMRD. 7. Issue MRS command to load MR6 with all application settings, wait tMRD. 8. Issue MRS command to load MR5 with all application settings, wait tMRD. 9. Issue MRS command to load MR4 with all application settings, wait tMRD. 10. Issue MRS command to load MR2 with all application settings, wait tMRD. 11. Issue MRS command to load MR1 with all application settings, wait tMRD. 12. Issue MRS command to load MR0 with all application settings, wait tMOD.

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4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure
13. Issue a ZQCL command to start ZQ calibration. 14. Wait for tDLLK and tZQinit to complete. 15. The device will be ready for normal operation. Once the DRAM has been initial-
ized, if the DRAM is in an idle state longer than 960ms, then either (a) REF commands must be issued within tREFI constraints (specification for posting allowed) or (b) CKE or CS_n must toggle once within every 960ms interval of idle time. For debug purposes, the 960ms delay limit maybe extended to 60 minutes provided the DRAM is operated in this debug mode for no more than 360 cumulative hours.
A stable valid VDD level is a set DC level (0Hz to 250 KHz) and must be no less than VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the noise doesn't alter VDD to less than VDD,min or greater than VDD,max.
A stable valid VDDQ level is a set DC level (0Hz to 250 KHz) and must be no less than VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.
A stable valid VPP level is a set DC level (0Hz to 250 KHz) and must be no less than VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±120mV (greater than 250KHz) is allowed on VPP provided the noise doesn't alter VPP to less than VPP,min or greater than VPP,max.

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4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure

Figure 16: RESET and Initialization Sequence at Power-On Ramping

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

CK_t, CK_c

tCKSRX VPP

VDD, VDDQ RESET_n CKE
Command

tPW_RESET_L

T = 500s

tIS T (MIN) = 10ns

tDLLK

tIS

tXPR

tMRD

tMRD

tMRD

tMOD

Note 1

MRS

MRS

MRS

MRS

ZQCL

Tj
tZQinit Note 1

Tk
Valid Valid

BG, BA ODT

MRx

MRx

MRx

MRx

tIS

Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW

Valid tIS
Valid

RTT

Time Break

Don't Care

Notes:

1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL commands.
2. MRS commands must be issued to all mode registers that have defined settings. 3. In general, there is no specific sequence for setting the MRS locations (except for de-
pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0, for example). 4. TEN is not shown; however, it is assumed to be held LOW.

RESET Initialization with Stable Power Sequence
The following sequence is required for RESET at no power interruption initialization: 1. Assert RESET_n below 0.2 × VDD any time when reset is needed (all other inputs may be undefined). RESET_n needs to be maintained for minimum tPW_RESET. CKE is pulled LOW before RESET_n being de-asserted (minimum time 10ns). 2. Follow Steps 2 through 10 in the Reset and Initialization Sequence at Power-On Ramping procedure.
When the reset sequence is complete, all counters except the refresh counters have been reset and the device is ready for normal operation.

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4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure

Figure 17: RESET Procedure at Power Stable Condition

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

CK_t, CK_c

tCKSRX VPP

VDD, VDDQ RESET_n CKE
Command

tPW_RESET_S

T = 500s

tIS T (MIN) = 10ns

tIS

tXPR

tMRD

tMRD

tMRD

tDLLK tMOD

Note 1

MRS

MRS

MRS

MRS

ZQCL

Tj
tZQinit Note 1

Tk
Valid Valid

BG, BA ODT

MRx

MRx

MRx

MRx

tIS

Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW

Valid tIS
Valid

RTT

Time Break

Don't Care

Notes:

1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL commands.
2. MRS commands must be issued to all mode registers that have defined settings. 3. In general, there is no specific sequence for setting the MRS locations (except for de-
pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0, for example). 4. TEN is not shown; however, it is assumed to be held LOW.

Uncontrolled Power-Down Sequence
In the event of an uncontrolled ramping down of VPP supply, VPP is allowed to be less than VDD provided the following conditions are met:
· Condition A: VPP and VDD/VDDQ are ramping down (as part of turning off ) from normal operating levels.
· Condition B: The amount that VPP may be less than VDD/VDDQ is less than or equal to 500mV.
· Condition C: The time VPP may be less than VDD is 10ms per occurrence with a total accumulated time in this state 100ms.

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4Gb: x4, x8, x16 DDR4 SDRAM Programming Mode Registers
· Condition D: The time VPP may be less than 2.0V and above VSS while turning off is 15ms per occurrence with a total accumulated time in this state 150ms.
Programming Mode Registers
For application flexibility, various functions, features, and modes are programmable in seven mode registers (MRn) provided by the device as user defined variables that must be programmed via a MODE REGISTER SET (MRS) command. Because the default values of the mode registers are not defined, contents of mode registers must be fully initialized and/or re-initialized; that is, they must be written after power-up and/or reset for proper operation. The contents of the mode registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS and DLL RESET commands do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents.
The MRS command cycle time, tMRD, is required to complete the WRITE operation to the mode register and is the minimum time required between the two MRS commands shown in the tMRD Timing figure.
Some of the mode register settings affect address/command/control input functionality. In these cases, the next MRS command can be allowed when the function being updated by the current MRS command is completed. These MRS commands don't apply tMRD timing to the next MRS command; however, the input cases have unique MR setting procedures, so refer to individual function descriptions:
· Gear-down mode · Per-DRAM addressability · CMD address latency · CA parity latency mode · VREFDQ training value · VREFDQ training mode · VREFDQ training range
Some mode register settings may not be supported because they are not required by certain speed bins.

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Figure 18: tMRD Timing

CK_c CK_t
Command

T0 Valid

T1 Valid

T2 Valid

Address

Valid

Valid

Valid

CKE

Settings

Old settings

Ta0 MRS2 Valid

Ta1 DES Valid

4Gb: x4, x8, x16 DDR4 SDRAM Programming Mode Registers

Tb0 DES Valid

Tb1 DES Valid

Tb2 DES Valid

tMRD Updating settings

Tc0 DES Valid

Tc1 MRS2 Valid

Tc2 Valid Valid

Time Break

Don't Care

Notes:

1. This timing diagram depicts CA parity mode "disabled" case. 2. tMRD applies to all MRS commands with the following exceptions:
Gear-down mode CA parity latency mode CMD address latency Per-DRAM addressability mode VREFDQ training value, VREFDQ training mode, and VREFDQ training range

The MRS command to nonMRS command delay, tMOD, is required for the DRAM to
update features, except for those noted in note 2 in figure below where the individual function descriptions may specify a different requirement. tMOD is the minimum time
required from an MRS command to a nonMRS command, excluding DES, as shown in the tMOD Timing figure.

Figure 19: tMOD Timing

CK_c CK_t
Command

T0 Valid

T1 Valid

T2 Valid

Address

Valid

Valid

Valid

CKE

Settings

Old settings

Ta0 MRS2 Valid

Ta1 DES Valid

Ta2 DES Valid

Ta3 DES Valid

Ta4 DES Valid

tMOD Updating settings

Tb0 DES Valid

Tb1 Valid Valid

Tb2 Valid Valid

New settings

Time Break

Don't Care

Notes:

1. This timing diagram depicts CA parity mode "disabled" case. 2. tMOD applies to all MRS commands with the following exceptions:
DLL enable, DLL RESET, Gear-down mode VREFDQ training value, internal VREF training monitor, VREFDQ training mode, and VREFDQ training range

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4Gb: x4, x8, x16 DDR4 SDRAM Programming Mode Registers
Maximum power savings mode , Per-DRAM addressability mode, and CA parity latency mode
The mode register contents can be changed using the same command and timing requirements during normal operation as long as the device is in idle state; that is, all banks are in the precharged state with tRP satisfied, all data bursts are completed, and CKE is HIGH prior to writing into the mode register. If the RTT(NOM) feature is enabled in the mode register prior to and/or after an MRS command, the ODT signal must continuously be registered LOW, ensuring RTT is in an off state prior to the MRS command. The ODT signal may be registered HIGH after tMOD has expired. If the RTT(NOM) feature is disabled in the mode register prior to and after an MRS command, the ODT signal can be registered either LOW or HIGH before, during, and after the MRS command. The mode registers are divided into various fields depending on functionality and modes.
In some mode register setting cases, function updating takes longer than tMOD. This type of MRS does not apply tMOD timing to the next valid command, excluding DES. These MRS command input cases have unique MR setting procedures, so refer to individual function descriptions.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0

Mode Register 0
Mode register 0 (MR0) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR0 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR0 Register Definition table.

Table 6: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 7: MR0 Register Definition

Mode Register
21 20:18
17 13,11:9

Description
RFU 0 = Must be programmed to 0 1 = Reserved
MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU
N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved
WR (WRITE recovery)/RTP (READ-to-PRECHARGE) 0000 = 10 / 5 clocks1 0001 = 12 / 6 clocks 0010 = 14 / 7 clocks1 0011 = 16 / 8 / clocks 0100 = 18 / 9 clocks1 0101 = 20 /10 clocks 0110 = 24 / 12 clocks 0111 = 22 / 11 clocks1 1000 = 26 / 13 clocks1 1001 = 28 / 14 clocks2 1010 through 1111 = Reserved

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0

Table 7: MR0 Register Definition (Continued)

Mode Register
8 7 12, 6:4, 2
3 1:0

Description
DLL reset 0 = No 1 = Yes
Test mode (TM) ­ Manufacturer use only 0 = Normal operating mode, must be programmed to 0
CAS latency (CL) ­ Delay in clock cycles from the internal READ command to first data-out 00000 = 9 clocks1 00001 = 10 clocks 00010 = 11 clocks1 00011 = 12 clocks 00100 = 13 clocks1 00101 = 14 clocks 00110 = 15 clocks1 00111 = 16 clocks 01000 = 18 clocks 01001 = 20 clocks 01010 = 22 clocks 01011 = 24 clocks 01100 = 23 clocks1 01101 = 17 clocks1 01110 = 19 clocks1 01111 = 21 clocks 1 10000 = 25 clocks 10001 = 26 clocks 10011 = 28 clocks 10100 = 29 clocks1 10101 = 30 clocks 10110 = 31 clocks1 10111 = 32 clocks
Burst type (BT) ­ Data burst ordering within a READ or WRITE burst access 0 = Nibble sequential 1 = Interleave
Burst length (BL) ­ Data burst size associated with each read or write access 00 = BL8 (fixed) 01 = BC4 or BL8 (on-the-fly) 10 = BC4 (fixed) 11 = Reserved

Notes: 1. Not allowed when 1/4 rate gear-down mode is enabled. 2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28 clocks and RTP should be set to 14 clocks.

Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type,

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0

and the starting column address as shown in the following table. Burst length options include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n.

Table 8: Burst Type and Burst Order

Note 1 applies to the entire table

Starting

Burst

READ/ Column Address

Length

WRITE

(A[2, 1, 0])

BC4

READ

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

WRITE

0, V, V

1, V, V

BL8

READ

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

WRITE

V, V, V

Burst Type = Sequential (Decimal)
0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7

Burst Type = Interleaved (Decimal)
0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7

Notes 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3
3

Notes:

1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a burst.
2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 (fixed) case.
3. T = Output driver for data and strobes are in High-Z. V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins. X = "Don't Care."

CAS Latency

The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0

overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or functionality is specified if MR0[7] = 1.

Write Recovery (WR)/READ-to-PRECHARGE
The programmed write recovery (WR) value is used for the auto precharge feature along with tRP to determine tDAL. WR for auto precharge (MIN) in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding to the next integer using the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section. The WR value must be programmed to be equal to or larger than tWR (MIN). When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array; tWR values will change when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data.
Internal READ-to-PRECHARGE (RTP) command delay for auto precharge (MIN) in clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding to the next integer using the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section. The RTP value in the mode register must be programmed to be equal to or larger than RTP (MIN). The programmed RTP value is used with tRP to determine the ACT timing to the same bank.

DLL RESET

The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET should be applied. Any time the DLL RESET function is used, tDLLK must be met before functions requiring the DLL can be used. Such as READ commands or synchronous ODT operations, for example.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1

Mode Register 1
Mode register 1 (MR1) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR1 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR1 Register Definition table.

Table 9: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 10: MR1 Register Definition

Mode Register
21 20:18
17 12 11

Description
RFU 0 = Must be programmed to 0 1 = Reserved
MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU
N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved
Data output disable (Qoff) ­ Output buffer disable 0 = Enabled (normal operation) 1 = Disabled (both ODI and RTT) Termination data strobe (TDQS) ­ Additional termination pins (x8 configuration only) 0 = TDQS disabled 1 = TDQS enabled

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1

Table 10: MR1 Register Definition (Continued)

Mode Register 10, 9, 8
7 13, 6, 5
4, 3 2, 1
0

Description
Nominal ODT (RTT(NOM) ­ Data bus termination setting 000 = RTT(NOM) disabled 001 = RZQ/4 (60 ohm) 010 = RZQ/2 (120 ohm) 011 = RZQ/6 (40 ohm) 100 = RZQ/1 (240 ohm) 101 = RZQ/5 (48 ohm) 110 = RZQ/3 (80 ohm) 111 = RZQ/7 (34 ohm)
Write leveling (WL) ­ Write leveling mode 0 = Disabled (normal operation) 1 = Enabled (enter WL mode)
Rx CTLE Control 000 = Vendor Default 001 = Vendor Defined 010 = Vendor Defined 011 = Vendor Defined 100 = Vendor Defined 101 = Vendor Defined 110 = Vendor Defined 111 = Vendor Defined
Additive latency (AL) ­ Command additive latency setting 00 = 0 (AL disabled) 01 = CL - 11 10 = CL - 2 11 = Reserved
Output driver impedance (ODI) ­ Output driver impedance setting 00 = RZQ/7 (34 ohm) 01 = RZQ/5 (48 ohm) 10 = Reserved (Although not JEDEC-defined and not tested, this setting will provide RZQ/6 or 40 ohm) 11 = Reserved
DLL enable ­ DLL enable feature 0 = DLL disabled 1 = DLL enabled (normal operation)

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

DLL Enable/DLL Disable
The DLL must be enabled for normal operation and is required during power-up initialization and upon returning to normal operation after having the DLL disabled. During normal operation (DLL enabled with MR1[0]) the DLL is automatically disabled when entering the SELF REFRESH operation and is automatically re-enabled upon exit of the SELF REFRESH operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a READ or SYNCHRONOUS ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Fail-

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1

ing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters.
During tDLLK, CKE must continuously be registered HIGH. The device does not require DLL for any WRITE operation, except when RTT(WR) is enabled and the DLL is required for proper ODT operation.
The direct ODT feature is not supported during DLL off mode. The ODT resistors must be disabled by continuously registering the ODT pin LOW and/or by programming the RTT(NOM) bits MR1[9,6,2] = 000 via an MRS command during DLL off mode.
The dynamic ODT feature is not supported in DLL off mode; to disable dynamic ODT externally, use the MRS command to set RTT(WR), MR2[10:9] = 00.
Output Driver Impedance Control
The output driver impedance of the device is selected by MR1[2,1], as shown in the MR1 Register Definition table.

ODT RTT(NOM) Values
The device is capable of providing three different termination values: RTT(Park), RTT(NOM), and RTT(WR). The nominal termination value, RTT(NOM), is programmed in MR1. A separate value, RTT(WR), may be programmed in MR2 to enable a unique RTT value when ODT is enabled during WRITE operations. The R TT(WR) value can be applied during WRITE commands even when RTT(NOM) is disabled. A third RTT value, RTT(Park), is programed in MR5. RTT(Park) provides a termination value when the ODT signal is LOW.

Additive Latency

The ADDITIVE LATENCY (AL) operation is supported to make command and data buses efficient for sustainable bandwidths in the device. In this operation, the device allows a READ or WRITE command (either with or without auto precharge) to be issued immediately after the ACTIVATE command. The command is held for the time of AL before it is issued inside the device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL) register settings. WRITE latency (WL) is controlled by the sum of the AL and CAS WRITE latency (CWL) register settings.

Table 11: Additive Latency (AL) Settings

A4

A3

AL

0

0

0 (AL disabled)

0

1

CL - 1

1

0

CL - 2

1

1

Reserved

Note: 1. AL has a value of CL - 1 or CL - 2 based on the CL values programmed in the MR0 register.

Rx CTLE Control

The Mode Register for Rx CTLE Control MR1[A13,A6,A5] is vendor specific. Since CTLE circuits can not be typically bypassed a disable option is not provided. Instead, a vendor optimized setting is given. It should be noted that the settings are not specifically linear

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1

in relationship to the vendor optimized setting, so the host may opt to instead walk through all the provided options and use the setting that works best in their environment.

Write Leveling

For better signal integrity, the device uses fly-by topology for the commands, addresses,
control signals, and clocks. Fly-by topology benefits from a reduced number of stubs
and their lengths, but it causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a write leveling feature that al-
lows the controller to compensate for skew.

Output Disable

The device outputs may be enabled/disabled by MR1[12] as shown in the MR1 Register Definition table. When MR1[12] is enabled (MR1[12] = 1) all output pins (such as DQ and DQS) are disconnected from the device, which removes any loading of the output drivers. For example, this feature may be useful when measuring module power. For normal operation, set MR1[12] to 0.

Termination Data Strobe
Termination data strobe (TDQS) is a feature of the x8 device and provides additional termination resistance outputs that may be useful in some system configurations. Because this function is available only in a x8 configuration, it must be disabled for x4 and x16 configurations.
While TDQS is not supported in x4 or x16 configurations, the same termination resistance function that is applied to the TDQS pins is applied to the DQS pins when enabled via the mode register.
The TDQS, DBI, and DATA MASK (DM) functions share the same pin. When the TDQS function is enabled via the mode register, the DM and DBI functions are not supported. When the TDQS function is disabled, the DM and DBI functions can be enabled separately.

Table 12: TDQS Function Matrix

TDQS Disabled
Enabled

Data Mask (DM) Enabled Disabled Disabled Disabled

WRITE DBI Disabled Enabled Disabled Disabled

READ DBI Enabled or disabled Enabled or disabled Enabled or disabled Disabled

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2

Mode Register 2
Mode register 2 (MR2) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR2 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR2 Register Definition table.

Table 13: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 14: MR2 Register Definition

Mode Register Description

21 RFU 0 = Must be programmed to 0 1 = Reserved

20:18

MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU

17 N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved

13 RFU 0 = Must be programmed to 0 1 = Reserved

12 WRITE data bus CRC 0 = Disabled 1 = Enabled

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2

Table 14: MR2 Register Definition (Continued)

Mode Register Description

11:9

Dynamic ODT (RTT(WR)) ­ Data bus termination setting during WRITEs 000 = RTT(WR) disabled (WRITE does not affect RTT value) 001 = RZQ/2 (120 ohm)

010 = RZQ/1 (240 ohm)

011 = High-Z

100 = RZQ/3 (80 ohm)

101 = Reserved

110 = Reserved

111 = Reserved

7:6 Low-power auto self refresh (LPASR) ­ Mode summary
00 = Manual mode - Normal operating temperature range (TC: -40°C­85°C) 01 = Manual mode - Reduced operating temperature range (TC: -40°C­45°C) 10 = Manual mode - Extended operating temperature range (TC: -40°C­105°C) 11 = ASR mode - Automatically switching among all modes

5:3 CAS WRITE latency (CWL) ­ Delay in clock cycles from the internal WRITE command to first data-in 1tCK WRITE preamble 000 = 9 (DDR4-1600)1 001 = 10 (DDR4-1866) 010 = 11 (DDR4-2133/1600)1 011 = 12 (DDR4-2400/1866) 100 = 14 (DDR4-2666/2133) 101 = 16 (DDR4-2933,3200/2400) 110 = 18 (DDR4-2666) 111 = 20 (DDR4-2933, 3200)

CAS WRITE latency (CWL) ­ Delay in clock cycles from the internal WRITE command to first data-in 2tCK WRITE preamble 000 = N/A 001 = N/A 010 = N/A 011 = N/A 100 = 14 (DDR4-2400) 101 = 16 (DDR4-2666/2400) 110 = 18 (DDR4-2933, 3200/2666) 111 = 20 (DDR4-2933, 3200)

8, 2 RFU 0 = Must be programmed to 0 1 = Reserved

1:0 RFU 0 = Must be programmed to 0 1 = Reserved

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2

CAS WRITE Latency
CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Definition table. CWL is the delay, in clock cycles, between the internal WRITE command and the availability of the first bit of input data. The device does not support any half-clock latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity latency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.

Low-Power Auto Self Refresh
Low-power auto self refresh (LPASR) is supported in the device. Applications requiring SELF REFRESH operation over different temperature ranges can use this feature to optimize the IDD6 current for a given temperature range as specified in the MR2 Register Definition table.

Dynamic ODT

In certain applications and to further enhance signal integrity on the data bus, it is desirable to change the termination strength of the device without issuing an MRS command. This may be done by configuring the dynamic ODT (RTT(WR)) settings in MR2[11:9]. In write leveling mode, only RTT(NOM) is available.

Write Cyclic Redundancy Check Data Bus
The write cyclic redundancy check (CRC) data bus feature during writes has been added to the device. When enabled via the mode register, the data transfer size goes from the normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for the CRC information.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 3

Mode Register 3
Mode register 3 (MR3) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR3 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR3 Register Definition table.

Table 15: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 16: MR3 Register Definition

Mode Register
21 20:18
17 13 12:11
10:9

Description
RFU 0 = Must be programmed to 0 1 = Reserved
MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU
N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved
RFU 0 = Must be programmed to 0 1 = Reserved
Multipurpose register (MPR) ­ Read format 00 = Serial 01 = Parallel 10 = Staggered 11 = Reserved
WRITE CMD latency when CRC/DM enabled 00 = 4CK (DDR4-1600) 01 = 5CK (DDR4-1866/2133/2400/2666) 10 = 6CK (DDR4-2933/3200) 11 = Reserved

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 3

Table 16: MR3 Register Definition (Continued)

Mode Register
8:6
5 4 3 2 1:0

Description
Fine granularity refresh mode 000 = Normal mode (fixed 1x) 001 = Fixed 2x 010 = Fixed 4x 011 = Reserved 100 = Reserved 101 = On-the-fly 1x/2x 110 = On-the-fly 1x/4x 111 = Reserved
Temperature sensor status 0 = Disabled 1 = Enabled
Per-DRAM addressability 0 = Normal operation (disabled) 1 = Enable
Gear-down mode ­ Ratio of internal clock to external data rate 0 = [1:1]; (1/2 rate data) 1 = [2:1]; (1/4 rate data)
Multipurpose register (MPR) access 0 = Normal operation 1 = Data flow from MPR
MPR page select 00 = Page 0 01 = Page 1 10 = Page 2 11 = Page 3 (restricted for DRAM manufacturer use only)

Multipurpose Register
The multipurpose register (MPR) is used for several features:
· Readout of the contents of the MRn registers · WRITE and READ system patterns used for data bus calibration · Readout of the error frame when the command address parity feature is enabled
To enable MPR, issue an MRS command to MR3[2] = 1. MR3[12:11] define the format of read data from the MPR. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). After MPR is enabled, any subsequent RD or RDA commands will be redirected to a specific mode register.
The mode register location is specified with the READ command using address bits. The MR is split into upper and lower halves to align with a burst length limitation of 8. Power-down mode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA commands are not allowed during MPR mode. The RESET function is supported during MPR mode, which requires device re-initialization.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 3
WRITE Command Latency When CRC/DM is Enabled
The WRITE command latency (WCL) must be set when both write CRC and DM are enabled for write CRC persistent mode. This provides the extra time required when completing a WRITE burst when write CRC and DM are enabled. This means at data rates less than or equal to 1600 MT/s then 4nCK is used, 5nCK or 6nCK are not allowed; at data rates greater than 1600 MT/s and less than or equal to 2666 MT/s then 5nCK is used, 4nCK or 6nCK are not allowed; and at data rates greater than 2666 MT/s and less than or equal to 3200 MT/s then 6nCK is used; 4nCK or 5nCK are not allowed.
Fine Granularity Refresh Mode
This mode had been added to DDR4 to help combat the performance penalty due to refresh lockout at high densities. Shortening tRFC and decreasing cycle time allows more accesses to the chip and allows for increased scheduling flexibility.
Temperature Sensor Status
This mode directs the DRAM to update the temperature sensor status at MPR Page 2, MPR0 [4,3]. The temperature sensor setting should be updated within 32ms; when an MPR read of the temperature sensor status bits occurs, the temperature sensor status should be no older than 32ms.
Per-DRAM Addressability
This mode allows commands to be masked on a per device basis providing any device in a rank (devices sharing the same command and address signals) to be programmed individually. As an example, this feature can be used to program different ODT or VREF values on DRAM devices within a given rank.
Gear-Down Mode
The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS command followed by a sync pulse to align the proper clock edge for operating the control lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. For operation in 1/2 rate mode, no MRS command or sync pulse is required.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4

Mode Register 4
Mode register 4 (MR4) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR4 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR4 Register Definition table.

Table 17: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command.

Table 18: MR4 Register Definition

Mode Register
21 20:18
17 13 12 11 10

Description
RFU 0 = Must be programmed to 0 1 = Reserved
MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU
N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved
Hard Post Package Repair (hPPR mode) 0 = Disabled 1 = Enabled
WRITE preamble setting 0 = 1tCK toggle1 1 = 2tCK toggle (When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.)
READ preamble setting 0 = 1tCK toggle1 1 = 2tCK toggle
READ preamble training 0 = Disabled 1 = Enabled

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4

Table 18: MR4 Register Definition (Continued)

Mode Register
9 8:6
5 4 3 2 1 0

Description
Self refresh abort mode 0 = Disabled 1 = Enabled
CMD (CAL) address latency 000 = 0 clocks (disabled) 001 =3 clocks1 010 = 4 clocks 011 = 5 clocks1 100 = 6 clocks 101 = 8 clocks 110 = Reserved 111 = Reserved
soft Post Package Repair (sPPR mode) 0 = Disabled 1 = Enabled
Internal VREF monitor 0 = Disabled 1 = Enabled
Temperature controlled refresh mode 0 = Disabled 1 = Enabled
Temperature controlled refresh range 0 = Normal temperature mode 1 = Extended temperature mode
Maximum power savings mode 0 = Normal operation 1 = Enabled
RFU 0 = Must be programmed to 0 1 = Reserved

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

Hard Post Package Repair Mode
The hard post package repair (hPPR) mode feature is JEDEC optional for 4Gb DDR4 memories. Performing an MPR read to page 2 MPR0 [7] indicates whether hPPR mode is available (A7 = 1) or not available (A7 = 0). hPPR mode provides a simple and easy repair method of the device after placed in the system. One row per bank can be repaired. The repair process is irrevocable so great care should be exercised when using.

Soft Post Package Repair Mode
The soft post package repair (sPPR) mode feature is JEDEC optional for 4Gb and 8Gb DDR4 memories. Performing an MPR read to page 2 MPR0 [6] indicates whether sPPR mode is available (A6 = 1) or not available (A6 = 0). sPPR mode provides a simple and

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4

easy repair method of the device after placed in the system. One row per bank can be repaired. The repair process is revocable by either doing a reset or power-down or by rewriting a new address in the same bank.

WRITE Preamble

Programmable WRITE preamble, tWPRE, can be set to 1tCK or 2tCK via the MR4 register. The 1tCK setting is similar to DDR3. However, when operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
Some even settings will require addition of 2 clocks. If the alternate longer CWL was used, the additional clocks will not be required.

READ Preamble

Programmable READ preamble tRPRE can be set to 1tCK or 2tCK via the MR4 register. Both the 1tCK and 2tCK DDR4 preamble settings are different from that defined for the
DDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controller
to train (or read level) its data strobe receivers using the READ preamble training.

READ Preamble Training
Programmable READ preamble training can be set to 1tCK or 2tCK. This mode can be used by the memory controller to train or READ level its data strobe receivers.

Temperature-Controlled Refresh
When temperature-controlled refresh mode is enabled, the device may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ratio. For example, the DRAM temperature sensor detected less than 45°C. Normal temperature mode covers the range of -40°C to 85°C, while the extended temperature range covers -40°C to 105°C.

Command Address Latency
COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled or disabled via the MRS setting. CAL is defined as the delay in clock cycles (tCAL) between a CS_n registered LOW and its corresponding registered command and address. The value of CAL (in clocks) must be programmed into the mode register according to the tCAL(ns)/tCK(ns) rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section.

Internal VREF Monitor
This mode enables output of internally generated VREFDQ for monitoring on DQ0, DQ1, DQ2, and DQ3. May be used during VREFDQ training and test. While in this mode, RTT should be set to High-Z. VREF_time must be increased by 10ns if DQ load is 0pF, plus an additional 15ns per pF of loading. This measurement is for verification purposes and is NOT an external voltage supply pin.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4
Maximum Power Savings Mode
This mode provides the lowest power mode where data retention is not required. When the device is in the maximum power saving mode, it does not need to guarantee data retention or respond to any external command (except the MAXIMUM POWER SAVING MODE EXIT command and during the assertion of RESET_n signal LOW).

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5

Mode Register 5
Mode register 5 (MR5) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR5 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR5 Register Definition table.

Table 19: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 20: MR5 Register Definition

Mode Register
21 20:18
17 13 12 11 10

Description
RFU 0 = Must be programmed to 0 1 = Reserved
MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU
N/A on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved
RFU 0 = Must be programmed to 0 1 = Reserved
Data bus inversion (DBI) ­ READ DBI enable 0 = Disabled 1 = Enabled
Data bus inversion (DBI) ­ WRITE DBI enable 0 = Disabled 1 = Enabled
Data mask (DM) 0 = Disabled 1 = Enabled

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5

Table 20: MR5 Register Definition (Continued)

Mode Register
9 8:6
5 4 3 2:0

Description
CA parity persistent error mode 0 = Disabled 1 = Enabled
Parked ODT value (RTT(Park)) 000 = RTT(Park) disabled 001 = RZQ/4 (60 ohm) 010 = RZQ/2 (120 ohm) 011 = RZQ/6 (40 ohm) 100 = RZQ/1 (240 ohm) 101 = RZQ/5 (48 ohm) 110 = RZQ/3 (80 ohm) 111 = RZQ/7 (34 ohm)
ODT input buffer for power-down 0 = Buffer enabled 1 = Buffer disabled
CA parity error status 0 = Clear 1 = Error
CRC error status 0 = Clear 1 = Error
CA parity latency mode 000 = Disable 001 = 4 clocks (DDR4-1600/1866/2133) 010 = 5 clocks (DDR4-2400/2666)1 011 = 6 clocks (DDR4-2933/3200) 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved

Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.

Data Bus Inversion
The DATA BUS INVERSION (DBI) function has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). The DBI function shares a common pin with the DM and TDQS functions. The DBI function applies to both READ and WRITE operations; Write DBI cannot be enabled at the same time the DM function is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12.
DBI is not supported for 3DS devices and should be disabled in MR5.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5

Data Mask

The DATA MASK (DM) function, also described as a partial write, has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). The DM function shares a common pin with the DBI and TDQS functions. The DM function applies only to WRITE operations and cannot be enabled at the same time the write DBI function is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three functions (TDQS/DM/DBI).

CA Parity Persistent Error Mode
Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA parity checking while the parity error status bit remains set at 1. However, with CA parity persistent mode enabled, CA parity checking continues to be performed when the parity error status bit is set to a 1.

ODT Input Buffer for Power-Down
This feature determines whether the ODT input buffer is on or off during power-down. If the input buffer is configured to be on (enabled during power-down), the ODT input signal must be at a valid logic level. If the input buffer is configured to be off (disabled during power-down), the ODT input signal may be floating and the device does not provide RTT(NOM) termination. However, the device may provide RTT(Park) termination depending on the MR settings. This is primarily for additional power savings.

CA Parity Error Status
The device will set the error status bit to 1 upon detecting a parity error. The parity error status bit remains set at 1 until the device controller clears it explicitly using an MRS command.

CRC Error Status

The device will set the error status bit to 1 upon detecting a CRC error. The CRC error status bit remains set at 1 until the device controller clears it explicitly using an MRS command.

CA Parity Latency Mode
CA parity is enabled when a latency value, dependent on tCK, is programmed; this accounts for parity calculation delay internal to the device. The normal state of CA parity is to be disabled. If CA parity is enabled, the device must ensure there are no parity errors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16 , CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 6

Mode Register 6
Mode register 6 (MR6) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR6 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR6 Register Definition table.

Table 21: Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

bus

_n _n _n

Mode 21 20 19 18 17 ­ ­ ­ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register

Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.

Table 22: MR6 Register Definition

Mode Register
21 20:18
17 12:10

Description
RFU 0 = Must be programmed to 0 1 = Reserved
MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU
NA on 4Gb and 8Gb, RFU 0 = Must be programmed to 0 1 = Reserved
tCCD_L 000 = 4 clocks (Data rate 1333 Mb/s) 001 = 5 clocks (1333 Mb/s <Data rate 1866 Mb/s) 010 = 6 clocks (1866 Mb/s <Data rate 2400 Mb/s) 011 = 7 clocks (2400 Mb/s <Data rate 2666 Mb/s) 100 = 8 clocks (2666 Mb/s <Data rate 3200 Mb/s) 101 = Reserved 110 = Reserved 111 = Reserved

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 6

Table 22: MR6 Register Definition (Continued)

Mode Register 13, 9, 8
7 6 5:0

Description
RFU Default = 000; Must be programmed to 000 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved
VREF Calibration Enable 0 = Disable 1 = Enable
VREF Calibration Range 0 = Range 1 1 = Range 2
VREF Calibration Value See the VREFDQ Range and Levels table in the VREFDQ Calibration section

tCCD_L Programming
The device controller must program the correct tCCD_L value. tCCD_L will be programmed according to the value defined per operating frequency in the AC parameter table. Although JEDEC specifies the larger of 5nCK or Xns, Micron's DRAM supports the larger of 4nCK or Xns.

VREFDQ Calibration Enable
VREFDQ calibration is where the device internally generates its own VREFDQ to be used by the DQ input receivers. The V REFDQ value will be output on any DQ of DQ[3:0] for evaluation only. The device controller is responsible for setting and calibrating the internal VREFDQ level using an MRS protocol (adjust up, adjust down, and so on). It is assumed that the controller will use a series of writes and reads in conjunction with VREFDQ adjustments to optimize and verify the data eye. Enabling VREFDQ calibration must be used whenever values are being written to the MR6[6:0] register.

VREFDQ Calibration Range
The device defines two VREFDQ calibration ranges: Range 1 and Range 2. Range 1 supports VREFDQ between 60% and 92% of VDDQ while Range 2 supports VREFDQ between 45% and 77% of VDDQ, as seen in VREFDQ Specification table. Although not a restriction, Range 1 was targeted for module-based designs and Range 2 was added to target pointto-point designs.

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4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 6
VREFDQ Calibration Value
Fifty settings provide approximately 0.65% of granularity steps sizes for both Range 1 and Range 2 of VREFDQ, as seen in VREFDQ Range and Levels table in the VREFDQ Calibration section.

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Truth Tables
Table 23: Truth Table ­ Command Notes 1­5 apply to the entire table; Note 6 applies to all READ/WRITE commands

Symbol CS_n ACT_n
RAS_n/A16 CAS_n/A15 WE_n/A14
BG[1:0] BA [1:0]
C[2:0] A12/BC_n A[13,11]
A10/AP A[9:0]

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Function

Prev. Pres. CKE CKE

MODE REGISTER SET

MRS H H L

REFRESH

REF H H L

Self refresh entry

SRE H

L

L

Self refresh exit

SRX L H H

L

Single-bank PRECHARGE

PRE H H L

PRECHARGE all banks

PREA H H L

Reserved for future use

RFU H H L

Bank ACTIVATE

ACT H H L

WRITE

BL8 fixed, BC4 fixed WR

H

H

L

BC4OTF

WRS4 H H L

BL8OTF

WRS8 H H L

WRITE

BL8 fixed, BC4 fixed WRA H

H

L

with auto BC4OTF precharge BL8OTF

WRAS4 H H L WRAS8 H H L

READ

BL8 fixed, BC4 fixed RD

H

H

L

BC4OTF

RDS4 H H L

BL8OTF

RDS8 H H L

READ

BL8 fixed, BC4 fixed RDA H H L

with auto BC4OTF precharge BL8OTF

RDAS4 H H L RDAS8 H H L

NO OPERATION

NOP H H L

Device DESELECTED

DES H H H

Power-down entry

PDE H

L

H

Power-down exit

PDX L H H

ZQ CALIBRATION LONG

ZQCL H H L

ZQ CALIBRATION SHORT

ZQCS H H L

H

L

L

L BG BA

H

L

L

HVV

H

L

L

HVV

XXXXXX

HHHHVV

H

L

H

L BG BA

H

L

H

L

V

V

H

L

H

H

L Row address (RA) BG BA

H

H

L

L BG BA

H

H

L

L BG BA

H

H

L

L BG BA

H

H

L

L BG BA

H

H

L

L BG BA

H

H

L

L BG BA

H

H

L

H BG BA

H

H

L

H BG BA

H

H

L

H BG BA

H

H

L

H BG BA

H

H

L

H BG BA

H

H

L

H BG BA

HHHHVV

XXXXXX

XXXXXX

XXXXXX

H

H

H

L

X

X

H

H

H

L

X

X

Notes

V

OP code

7

VVVVV

V V V V V 8, 9, 10

X X X X X 8, 9, 10,

VVVVV

11

V

V

V

L

V

VVVHV

RFU

V

Row address (RA)

V

V

V

L CA

V

L

V

L CA

V

H

V

L CA

V V V H CA

V

L

V

H CA

V H V H CA

V

V

V

L CA

V

L

V

L CA

V

H

V

L CA

V V V H CA

V

L

V

H CA

V H V H CA

VVVVV

12

XXXXX

13

X X X X X 10, 14

X X X X X 10, 14

XXXHX

X

X

X

L

X

4Gb: x4, x8, x16 DDR4 SDRAM Truth Tables
Notes: 1. · BG = Bank group address · BA = Bank address · RA = Row address · CA = Column address · BC_n = Burst chop · X = "Don't Care" · V = Valid
2. All DDR4 SDRAM commands are defined by states of CS_n, ACT_n, RAS_n/A16, CAS_n/ A15, WE_n/A14, and CKE at the rising edge of the clock. The MSB of BG, BA, RA, and CA are device density- and configuration-dependent. When ACT_n = H, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as command pins RAS_n, CAS_n, and WE_n, respectively. When ACT_n = L, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as address pins A16, A15, and A14, respectively.
3. RESET_n is enabled LOW and is used only for asynchronous reset and must be maintained HIGH during any function.
4. Bank group addresses (BG) and bank addresses (BA) determine which bank within a bank group is being operated upon. For MRS commands, the BG and BA selects the specific mode register location.
5. V means HIGH or LOW (but a defined logic level), and X means either defined or undefined (such as floating) logic level.
6. READ or WRITE bursts cannot be terminated or interrupted, and fixed/on-the-fly (OTF) BL will be defined by MRS.
7. During an MRS command, A17 is RFU and is device density- and configuration-dependent.
8. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.
9. VPP and VREF (VREFCA) must be maintained during SELF REFRESH operation. 10. Refer to the Truth Table ­ CKE table for more details about CKE transition. 11. Controller guarantees self refresh exit to be synchronous. DRAM implementation has
the choice of either synchronous or asynchronous. 12. The NO OPERATION (NOP) command may be used only when exiting maximum power
saving mode or when entering gear-down mode. 13. The NOP command may not be used in place of the DESELECT command. 14. The power-down mode does not perform any REFRESH operation.

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4Gb: x4, x8, x16 DDR4 SDRAM Truth Tables

Table 24: Truth Table ­ CKE

Notes 1­7, 9, and 20 apply to the entire table CKE

Previous Cycle Present Cycle

Current State

(n - 1)

(n)

Power-down

L

L

L

H

Self refresh

L

L

L

H

Bank(s) active

H

L

Reading

H

L

Writing

H

L

Precharging

H

L

Refreshing

H

L

All banks idle

H

L

H

L

Command (n) X
DES X
DES DES DES DES DES DES DES REFRESH

Action (n) Maintain power-down
Power-down exit Maintain self refresh
Self refresh exit Active power-down entry
Power-down entry Power-down entry Power-down entry Precharge power-down entry Precharge power-down entry
Self refresh

Notes 8, 10, 11 8, 10, 12
11, 13 8, 13, 14, 15 8, 10, 12, 16 8, 10, 12, 16, 17 8, 10, 12, 16, 17 8, 10, 12, 16, 17
8, 12 8, 10, 12, 16, 18
16, 18, 19

Notes: 1. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock edge n.
2. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge.
3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of COMMAND (n); ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.
6. During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must be maintained until 1 nCK prior to tCKE (MIN) being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Truth Table ­ Command table.
8. For power-down entry and exit parameters, see the Power-Down Modes section. 9. CKE LOW is allowed only if tMRD and tMOD are satisfied.
10. The power-down mode does not perform any REFRESH operations.
11. X = "Don't Care" (including floating around VREF) in self refresh and power-down. X also applies to address pins.
12. The DESELECT command is the only valid command for power-down entry and exit.
13. VPP and VREFCA must be maintained during SELF REFRESH operation. 14. On self refresh exit, the DESELECT command must be issued on every clock edge occur-
ring during the tXS period. READ or ODT commands may be issued only after tXSDLL is satisfied.
15. The DESELECT command is the only valid command for self refresh exit.
16. Self refresh cannot be entered during READ or WRITE operations. For a detailed list of restrictions see the SELF REFRESH Operation and Power-Down Modes sections.
17. If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command, then precharge power-down is entered; otherwise, active power-down is entered.

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4Gb: x4, x8, x16 DDR4 SDRAM NOP Command
18. Idle state is defined as all banks are closed (tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on), as well as all self refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXSDLL, and so on).
19. Self refresh mode can be entered only from the all banks idle state. 20. For more details about all signals, see the Truth Table ­ Command table; must be a legal
command as defined in the table.

NOP Command
The NO OPERATION (NOP) command was originally used to instruct the selected DDR4 SDRAM to perform a NOP (CS_n = LOW and ACT_n, RAS_n/A16, CAS_n/A15, and WE_n/A14 = HIGH). This prevented unwanted commands from being registered during idle or wait states. NOP command general support has been removed and the command should not be used unless specifically allowed, which is when exiting maximum power-saving mode or when entering gear-down mode.

DESELECT Command
The deselect function (CS_n HIGH) prevents new commands from being executed; therefore, with this command, the device is effectively deselected. Operations already in progress are not affected.

DLL-Off Mode

DLL-off mode is entered by setting MR1 bit A0 to 0, which will disable the DLL for subsequent operations until the A0 bit is set back to 1. The MR1 A0 bit for DLL control can be switched either during initialization or during self refresh mode. Refer to the Input Clock Frequency Change section for more details.
The maximum clock frequency for DLL-off mode is specified by the parameter tCKDLL_OFF.
Due to latency counter and timing restrictions, only one CL value and CWL value (in MR0 and MR2 respectively) are supported. The DLL-off mode is only required to support setting both CL = 10 and CWL = 9.
DLL-off mode will affect the read data clock-to-data strobe relationship (tDQSCK), but not the data strobe-to-data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain.
Compared with DLL-on mode, where tDQSCK starts from the rising clock edge (AL + CL) cycles after the READ command, the DLL-off mode tDQSCK starts (AL + CL - 1) cycles after the READ command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK), and the difference between tDQSCK (MIN) and tDQSCK (MAX) is significantly larger than in DLL-on mode. The tDQSCK (DLL-off) values are undefined and the user is responsible for training to the data-eye.
The timing relations on DLL-off mode READ operation are shown in the following diagram, where CL = 10, AL = 0, and BL = 8.

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4Gb: x4, x8, x16 DDR4 SDRAM DLL-Off Mode

Figure 20: DLL-Off Mode Read Timing Operation

CK_c CK_t
Command
Address
DQS_t, DQS_c (DLL-on)
DQS_c (DLL-on)

T0 ( ( T1

T6

T7

T8

T9

T10

T11

T12

T13

T14

))

((

))

((

))

((

))

RD

(( ))

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

((

))

((

))

ARD

(( ))

((

))

(( ))

RL (DLL-on) = AL + CL = 10 CL = 10, AL = 0

tDQSCK (MIN)

tDQSCK (MAX)

((

))

DIN DIN DIN DIN DIN DIN DIN DIN

b b+1 b+2 b+3 b+4 b+5 b+6 b+7

DQS_t, DQS_c (DLL-off)

RL (DLL-off) = AL + (CL - 1) = 9
CL = 10, AL = 0 (( ))

tDQSCK (DLL-off) MIN

DQS_c (DLL-off)

(( ))

DQS_t, DQS_c

((

(DLL-off)

))

DIN DIN DIN DIN DIN DIN DIN DIN b b+1 b+2 b+3 b+4 b+5 b+6 b+7
tDQSCK (DLL-off) MAX

DQS_c

((

(DLL-off)

))

DIN DIN DIN DIN DIN DIN DIN DIN b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Transitioning data

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures
DLL-On/Off Switching Procedures
The DLL-off mode is entered by setting MR1 bit A0 to 0; this will disable the DLL for subsequent operations until the A0 bit is set back to 1.
DLL Switch Sequence from DLL-On to DLL-Off
To switch from DLL-on to DLL-off requires the frequency to be changed during self refresh, as outlined in the following procedure:
1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and, to disable the DLL, the DRAM on-die termination resistors, RTT(NOM), must be in High-Z before MRS to MR1.)
2. Set MR1 bit A0 to 1 to disable the DLL. 3. Wait tMOD. 4. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR is satisfied. 5. Change frequency, following the guidelines in the Input Clock Frequency Change
section. 6. Wait until a stable clock is available for at least tCKSRX at device inputs. 7. Starting with the SELF REFRESH EXIT command, CKE must continuously be regis-
tered HIGH until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If RTT(NOM) was disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care." 8. Wait tXS_FAST, tXS_ABORT, or tXS, and then set mode registers with appropriate values (an update of CL, CWL, and WR may be necessary; a ZQCL command can also be issued after tXS_FAST).
· tXS_FAST: ZQCL, ZQCS, and MRS commands. For MRS commands, only CL and WR/RTP registers in MR0, the CWL register in MR2, and gear-down mode in MR3 may be accessed provided the device is not in per-DRAM addressability mode. Access to other device mode registers must satisfy tXS timing.
· tXS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command after a delay of tXS_ABORT. Upon exiting from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same regardless of the MRS bit setting for self refresh abort.
· tXS: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8, RD, RDS4, RDS8, RDA, RDAS4, and RDAS8.
9. Wait tMOD to complete.
The device is ready for the next command.

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4Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures

Figure 21: DLL Switch Sequence from DLL-On to DLL-Off

CK_c CK_t
CKE Command

Ta

Tb0

Tb1

Tc

tCKSRE/tCKSRE_PAR tIS tCPDED

MRS2

SRE3

DES

Note 4

Td

Te0

Te1

Tf

Tg

Th

tCKSRX5

Valid tXS_FAST

SRX6

Valid7

Valid Valid8

Valid Valid9

Address ODT

tRP tIS

tCKESR/tCKESR_PAR

Valid tXS_ABORT
tXS

Valid

Valid Valid

Enter self refresh

Exit self refresh Time Break

Notes:

1. Starting in the idle state. RTT in stable state. 2. Disable DLL by setting MR1 bit A0 to 0. 3. Enter SR. 4. Change frequency. 5. Clock must be stable tCKSRX. 6. Exit SR. 7. Update mode registers allowed with DLL-off settings met.

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures
DLL-Off to DLL-On Procedure
To switch from DLL-off to DLL-on (with required frequency change) during self refresh: 1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and DRAM ODT resistors (RTT(NOM)) must be in High-Z before self refresh mode is entered.) 2. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR are satisfied. 3. Change frequency (following the guidelines in the Input Clock Frequency Change section). 4. Wait until a stable clock is available for at least tCKSRX at device inputs. 5. Starting with the SELF REFRESH EXIT command, CKE must continuously be registered HIGH until tDLLK timing from the subsequent DLL RESET command is satisfied. In addition, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must continuously be registered LOW or HIGH until tDLLK timing from the subsequent DLL RESET command is satisfied. If RTT(NOM) disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care." 6. Wait tXS or tXS_ABORT, depending on bit 9 in MR4, then set MR1 bit A0 to 0 to enable the DLL. 7. Wait tMRD, then set MR0 bit A8 to 1 to start DLL reset. 8. Wait tMRD, then set mode registers with appropriate values; an update of CL, CWL, and WR may be necessary. After tMOD is satisfied from any proceeding MRS command, a ZQCL command can also be issued during or after tDLLK. 9. Wait for tMOD to complete. Remember to wait tDLLK after DLL RESET before applying any command requiring a locked DLL. In addition, wait for tZQoper in case a ZQCL command was issued.
The device is ready for the next command.

Figure 22: DLL Switch Sequence from DLL-Off to DLL-On

Ta
CK_c CK_t
Note 1
CKE

Tb0

Tb1

Tc

tCKSRE/tCKSRE_PAR tIS tCPDED

Command

MRS2

SRE3

DES

Td

Te0

Te1

Tf

Tg

Th

Note 4

tCKSRX5

Valid tXS_ABORT

SRX6

Valid7

Valid Valid7

Valid Valid7

Address ODT

tRP tIS

tCKESR/tCKESR_PAR

Valid tXS

Valid

Valid

tMRD

Valid

Enter self refresh

Notes: 1. Starting in the idle state.

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Exit self refresh Time Break

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Input Clock Frequency Change
2. Enter SR. 3. Change frequency. 4. Clock must be stable tCKSRX. 5. Exit SR. 6. Set DLL to on by setting MR1 to A0 = 0. 7. Update mode registers. 8. Issue any valid command.
Input Clock Frequency Change
After the device is initialized, it requires the clock to be stable during almost all states of normal operation. This means that after the clock frequency has been set and is in the stable state, the clock period is not allowed to deviate except for what is allowed by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another stable clock rate only when in self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequency.
After the device has been successfully placed in self refresh mode and tCKSRE/ tCKSRE_PAR have been satisfied, the state of the clock becomes a "Don't Care." Following a "Don't Care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met as outlined in SELF REFRESH Operation.
For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5, and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode, READ and WRITE preamble, Command Address Latency, and tCCD_L/tDLLK values.
When the clock rate is being increased (faster), the MR settings that require additional clocks should be updated prior to the clock rate being increased. In particular, the PL latency must be disabled when the clock rate changes, ie. while in self refresh mode. For example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA parity mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 6. The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit self refresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0].
If the MR settings that require additional clocks are updated after the clock rate has been increased, for example. after exiting self refresh mode, the required MR settings must be updated prior to removing the DRAM from the IDLE state, unless the DRAM is RESET. If the DRAM leaves the IDLE state to enter self refresh mode or ZQ Calibration, the updating of the required MR settings may be deferred to the next time the DRAM enters the IDLE state.
If MR6 is issued prior to self refresh entry for new the tDLLK value, DLL will relock automatically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0 must be issued to reset the DLL.
The device input clock frequency can change only within the minimum and maximum operating frequency specified for the particular speed grade. Any frequency change below the minimum operating frequency would require the use of DLL-on mode to DLLoff mode transition sequence (see DLL-On/Off Switching Procedures).

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4Gb: x4, x8, x16 DDR4 SDRAM Write Leveling

Write Leveling

For better signal integrity, DDR4 memory modules use fly-by topology for the commands, addresses, control signals, and clocks. Fly-by topology has benefits from the reduced number of stubs and their length, but it also causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a write leveling feature to allow the controller to compensate for skew. This feature may not be required under some system conditions, provided the host can maintain the tDQSS, tDSS, and tDSH specifications.
The memory controller can use the write leveling feature and feedback from the device to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory controller involved in the leveling must have an adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay established though this exercise would ensure the tDQSS specification. Besides tDQSS, tDSS and tDSH specifications also need to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in the AC Timing Parameters section in order to satisfy tDSS and tDSH specifications. A conceptual timing of this scheme is shown below.

Figure 23: Write Leveling Concept, Example 1

T0

T1

T2

T3

T4

T5

T6

T7

Source

CK_c CK_t

diff_DQS

Tn

T0

T1

T2

T3

T4

T5

T6

Destination CK_c
CK_t

diff_DQS

DQ

0 or 1

0

0

0

diff_DQS

Push DQS to capture the 0-1 transition

DQ

0 or 1

1

1

1

DQS driven by the controller during leveling mode must be terminated by the DRAM based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
All data bits carry the leveling feedback to the controller across the DRAM configurations: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-toclock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)to-clock relationship.

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4Gb: x4, x8, x16 DDR4 SDRAM Write Leveling

The figure below is another representative way to view the write leveling procedure. Although it shows the clock varying to a static strobe, this is for illustrative purpose only; the clock does not actually change phase, the strobe is what actually varies. By issuing multiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the time at which the clock edge arrives at the DRAM clock input buffer.

Figure 24: Write Leveling Concept, Example 2

CK_c CK_t CK_c CK_t
CK_c CK_t DQS_t/ DQS_c

tWLS 111 11111 11 111 1111 1 tWLH
0 000 000 000 000 tWLS tWLH
0 0 0 0 0 0 0 X XX XXX 11 111 1111 1
tWLO

DQ (CK 0 to 1)

DQ (CK 1 to 0)

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode
The DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is finished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR Leveling Procedures table). Note that in write leveling mode, only DQS terminations are activated and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TERMINATION Function in Leveling Mode table).

Table 25: MR Settings for Leveling Procedures
Function Write leveling enable Output buffer mode (Q off)

MR1 A7 A12

Enable 1 0

Disable 0 1

Table 26: DRAM TERMINATION Function in Leveling Mode

ODT Pin at DRAM RTT(NOM) with ODT HIGH

DQS_t/DQS_c Termination On

DQ Termination Off

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4Gb: x4, x8, x16 DDR4 SDRAM Write Leveling

Table 26: DRAM TERMINATION Function in Leveling Mode (Continued)

ODT Pin at DRAM RTT(Park) with ODT LOW

DQS_t/DQS_c Termination On

DQ Termination Off

Notes:

1. In write leveling mode, with the mode's output buffer either disabled (MR1[bit7] = 1 and MR1[bit12] = 1) or with its output buffer enabled (MR1[bit7] = 1 and MR1[bit12] = 0), all RTT(NOM) and RTT(Park) settings are supported.
2. RTT(WR) is not allowed in write leveling mode and must be set to disable prior to entering write leveling mode.

Procedure Description
The memory controller initiates the leveling mode of all DRAM by setting bit 7 of MR1 to 1. When entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only the DESELECT command is supported, other than MRS commands to change the Qoff bit (MR1[A12]) and to exit write leveling (MR1[A7]). Upon exiting write leveling mode, the MRS command performing the exit (MR1[A7] = 0) may also change the other MR1 bits. Because the controller levels one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. The controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal, unless DODTLon or DODTLoff have been altered (the ODT internal pipe delay is increased when increasing WRITE latency [WL] or READ latency [RL] by the previous MR command), then ODT assertion should be delayed by DODTLon after tMOD is satisfied, which means the delay is now tMOD + DODTLon.
The controller may drive DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN, at which time the DRAM has applied ODT to these signals. After tDQSL and tWLMRD, the controller provides a single DQS_t, DQS_c edge, which is used by the DRAM to sample CK driven from the controller. tWLMRD (MAX) timing is controller dependent.
The DRAM samples CK status with the rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit. There are no read strobes (DQS_t, DQS_c) needed for these DQs. The controller samples incoming DQ and either increments or decrements DQS delay setting and launches the next DQS pulse after some time, which is controller dependent. After a 0-to-1 transition is detected, the controller locks the DQS delay setting, and write leveling is achieved for the device. The following figure shows the timing diagram and parameters for the overall write leveling procedure.

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4Gb: x4, x8, x16 DDR4 SDRAM Write Leveling

Figure 25: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)

CK_c5 CK_t Command MRS2 ODT diff_DQS4
Late Prime DQ1

DES3

DES

DES

tMOD

tWLDQSEN tWLMRD

T1 tWLH
tWLS

T2 tWLH
tWLS

DES

DES

DES NOP DES

DES

DES

tDQSL6

tDQSH6

tDQSL6

tWLO

tDQSH6 tWLO

Early Prime DQ1

tWLO

tWLOE

tWLO

DES

DES

tWLOE

Undefined Driving Mode Time Break

Don't Care

Notes:

1. The device drives leveling feedback on all DQs. 2. MRS: Load MR1 to enter write leveling mode. 3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings.
DQS_t is shown with a solid line; DQS_c is shown with a dotted line. 4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line. 5. DQS needs to fulfill minimum pulse width requirements, tDQSH (MIN) and tDQSL (MIN),
as defined for regular WRITEs; the maximum pulse width is system dependent. 6. tWLDQSEN must be satisfied following equation when using ODT:

· DLL = Enable, then tWLDQSEN > tMOD (MIN) + DODTLon + tADC · DLL = Disable, then tWLDQSEN > tMOD (MIN) + tAONAS

Write Leveling Mode Exit
Write leveling mode should be exited as follows: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note that from this point on, DQ pins are in undefined driving mode and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin LOW (tIS must be satisfied) and continue registering LOW (see Tb0). 3. After RTT is switched off, disable write leveling mode via the MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command can be registered. (MR commands can be issued after tMRD [Td1]).

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4Gb: x4, x8, x16 DDR4 SDRAM Write Leveling

Figure 26: Write Leveling Exit

T0

T1

T2

Ta0

Tb0

Tc0

Tc1

CK_c

CK_t

Command DES

DES

DES

DES

DES

DES

DES

Address
ODT
RTT(DQS_t) RTT(DQS_c)
DQS_t, DQS_c
RTT(DQ)
DQ1

RTT(NON) tWLO

tIS ODTL (OFF)

tADC (MIN) tADC (MAX)

result = 1

Tc2
DES MR1

Td0

Td1

DES tMRD

Valid
Valid tMOD

RTT(Park)

Te0 DES

Te1 Valid Valid

Undefined Driving Mode

Transitioning

Time Break

Don't Care

Notes: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t HIGH just after the T0 state.
2. See previous figure for specific tWLO timing.

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4Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency
Command Address Latency
DDR4 supports the command address latency (CAL) function as a power savings feature. This feature can be enabled or disabled via the MRS setting. CAL timing is defined as the delay in clock cycles (tCAL) between a CS_n registered LOW and its corresponding registered command and address. The value of CAL in clocks must be programmed into the mode register (see MR1 Register Definition table) and is based on the tCAL(ns)/ tCK(ns) rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section.
Figure 27: CAL Timing Definition

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

CLK

CS_n

CMD/ADDR

tCAL
CAL gives the DRAM time to enable the command and address receivers before a command is issued. After the command and the address are latched, the receivers can be disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the command and address input receivers enabled for the duration of the command sequence.

Figure 28: CAL Timing Example (Consecutive CS_n = LOW)

1

2

3

4

5

6

7

8

9 10 11 12

CLK

CS_n CMD/ADDR

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4Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency
When the CAL mode is enabled, additional time is required for the MRS command to complete. The earliest the next valid command can be issued is tMOD_CAL, which should be equal to tMOD + tCAL. The two following figures are examples.

Figure 29: CAL Enable Timing ­ tMOD_CAL

T0 CK_c
CK_t

T1

Ta0

Ta1

Ta2

Ta3

Command

Valid

MRS

DES

DES

DES

DES

Address

Valid

Valid

Valid

Valid

Valid

Valid

CS_n Settings Old settings

tMOD_CAL Updating settings

Note: 1. CAL mode is enabled at T1.

Ta4
DES Valid

Tb0

Tb1

Tb2

Tb3

DES Valid

DES Valid

Valid Valid

Valid Valid

tCAL

New settings

Time Break

Don't Care

Figure 30: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled

T0 CK_c
CK_t

T1

Ta0

Ta1

Ta2

Tb0

Tb1

Tb2

Tc0

Tc1

Tc2

Command

Valid

Address

Valid

DES

DES

tCAL

Valid

Valid

MRS Valid

DES Valid

DES Valid

DES Valid

DES

DES

tCAL

Valid

Valid

Valid Valid

Valid Valid

CS_n Settings

Old settings

tMOD_CAL

Updating settings

New settings

Time Break

Don't Care

Note: 1. MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL setting if modified.

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4Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency
When the CAL mode is enabled or being enabled, the earliest the next MRS command can be issued is tMRD_CAL is equal to tMOD + tCAL. The two following figures are examples.

Figure 31: CAL Enabling MRS to Next MRS Command, tMRD_CAL

T0 CK_c
CK_t

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Tb0

Tb1

Tb2

Tb3

Command

Valid

Address

Valid

MRS Valid

DES Valid

DES Valid

DES Valid

DES Valid

DES Valid

DES tCAL
Valid

DES Valid

MRS Valid

DES Valid

CS_n Settings Old settings

tMRD_CAL

Updating settings

Note: 1. Command address latency mode is enabled at T1.

Updating settings

Time Break

Don't Care

Figure 32: tMRD_CAL, Mode Register Cycle Time With CAL Enabled

7 CK_c
CK_t

7

7D

7D

7D

7E

7E

7E

7F

7F

7F

Command Address

9DOLG W &$/

'(6

9DOLG

9DOLG

'(6 9DOLG

056 9DOLG

'(6 9DOLG

'(6 9DOLG

'(6 W &$/

'(6

9DOLG

9DOLG

'(6 9DOLG

056 9DOLG

'(6 9DOLG

CS_n Settings

2OGVHWWLQJV

W 05'B&$/

8SGDWLQJVHWWLQJV

1HZVHWWLQJV

7LPH%UHDN

'RQ¶W&DUH

Note: 1. MRS at Ta1 may or may not modify CAL, tMRD_CAL is computed based on new tCAL setting if modified.
CAL Examples: Consecutive READ BL8 with two different CALs and 1tCK preamble in different bank group shown in the following figures.

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Figure 33: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group

CK_c CK_t CS_n
Command
Bank Group Address Address
DQS_t, DQS_c DQ

T0

T1

T2

T3

T4

T5

T6

T7

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

tCAL = 3

DES

DES

READ
BG a Bank, Col n

tCAL = 3

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BG b

Bank, Col b

tRPRE (1nCK)

tRPST

RL = 11

RL = 11

DOUT n

DOUT n + 1

DOUT n + 2

DOUT n + 3

DOUT n + 4

DOUT n + 5

DOUT n + 6

DOUT n + 7

DOUT b

DOUT b + 7

DOUT b + 2

DOUT b + 3

DOUT b + 4

DOUT b + 5

DOUT b + 6

DOUT b + 7

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1tCK. 2. DOUT n = data-out from column n; DOUT b = data-out from column b. 3. DES commands are shown for ease of illustration, other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T3 and
T7. 5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable. 6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.

89

4Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency

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Figure 34: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group

7 &.BF &.BW &6BQ
&RPPDQG
%DQN*URXS $GGUHVV $GGUHVV
'46BW'46BF '4

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

W&$/ 

'(6

'(6

'(6

5($'
%*D %DQN &ROQ

W&$/ 

'(6

'(6

W&&'B6 

'(6

5($'
%*E %DQN &ROE

'(6

'(6

W 535(Q&.

'(6

'(6

'(6

'(6

'(6

'(6

'(6

'(6

W 5367

5/ 

5/ 

'2Q87

'Q287

'Q287

'Q287

'Q287

'Q287

'Q287

'Q287

'2E87

'E287

'E287

'E287

'E287

'E287

'E287

'E287

7UDQVLWLRQLQJ'DWD

'RQ¶W&DUH

Notes:

1. BL = 8, AL = 0, CL = 11, CAL = 4, Preamble = 1tCK. 2. DOUT n = data-out from column n; DOUT b = data-out from column b. 3. DES commands are shown for ease of illustration, other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T4 and
T8.

4Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency

5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable. 6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Low-Power Auto Self Refresh Mode

Low-Power Auto Self Refresh Mode
An auto self refresh mode is provided for application ease. Auto self refresh mode is enabled by setting MR2[6] = 1 and MR2[7] = 1. The device will manage self refresh entry over the supported temperature range of the DRAM. In this mode, the device will change its self refresh rate as the DRAM operating temperature changes, going lower at low temperatures and higher at high temperatures.
Manual Self Refresh Mode
If auto self refresh mode is not enabled, the low-power auto self refresh mode register must be manually programmed to one of the three self refresh operating modes. This mode provides the flexibility to select a fixed self refresh operating mode at the entry of the self refresh, according to the system memory temperature conditions. The user is responsible for maintaining the required memory temperature condition for the mode selected during the SELF REFRESH operation. The user may change the selected mode after exiting self refresh and before entering the next self refresh. If the temperature condition is exceeded for the mode selected, there is a risk to data retention resulting in loss of data.

Table 27: Auto Self Refresh Mode

MR2[7] MR2[6]

0

0

1

0

0

1

1

1

Low-Power Auto Self Refresh
Mode Normal
Extended temperature
Reduced temperature
Auto self refresh

Operating Temperature

Range for Self Refresh Mode

SELF REFRESH Operation

(DRAM TCASE)

Variable or fixed normal self refresh rate

-40°C to 85°C

maintains data retention at the normal oper-

ating temperature. User is required to ensure

that 85°C DRAM TCASE (MAX) is not exceeded to avoid any risk of data loss.

Variable or fixed high self refresh rate optimizes data retention to support the extended temperature range.

-40°C to 105°C

Variable or fixed self refresh rate or any other DRAM power consumption reduction control for the reduced temperature range. User is required to ensure 45°C DRAM TCASE (MAX) is not exceeded to avoid any risk of data loss.

-40°C to 45°C

Auto self refresh mode enabled. Self refresh power consumption and data retention are optimized for any given operating temperature condition.

All of the above

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Figure 35: Auto Self Refresh Ranges
IDD6

4Gb: x4, x8, x16 DDR4 SDRAM Low-Power Auto Self Refresh Mode

2x refresh rate 1x refresh rate

1/2x refresh rate

Reduced temperature
range

-40°C

45°C

Normal temperature
range

Extended temperature
range

85°C

105°C Tc

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
Multipurpose Register
The MULTIPURPOSE REGISTER (MPR) function, MPR access mode, is used to write/ read specialized data to/from the DRAM. The MPR consists of four logical pages, MPR Page 0 through MPR Page 3, with each page having four 8-bit registers, MPR0 through MPR3. Page 0 can be read by any of three readout modes (serial, parallel, or staggered) while Pages 1, 2, and 3 can be read by only the serial readout mode. Page 3 is for DRAM vendor use only. MPR mode enable and page selection is done with MRS commands. Data bus inversion (DBI) is not allowed during MPR READ operation.
Once the MPR access mode is enabled (MR3[2] = 1), only the following commands are allowed: MRS, RD, RDA WR, WRA, DES, REF, and RESET; RDA/WRA have the same functionality as RD/WR which means the auto precharge part of RDA/WRA is ignored. Power-down mode and SELF REFRESH command are not allowed during MPR enable mode. No other command can be issued within tRFC after a REF command has been issued; 1x refresh (only) is to be used during MPR access mode. While in MPR access mode, MPR read or write sequences must be completed prior to a REFRESH command.
Figure 36: MPR Block Diagram
Memory core (all banks precharged)

MR3 [2] = 1
MPR data flow DQ,s DM_n/DBI_n, DQS_t, DQS_c

Four multipurpose registers (pages), each with four 8-bit registers:
Data patterns (RD/WR) Error log (RD)
Mode registers (RD) DRAM manufacture only (RD)

Table 28: MR3 Setting for the MPR Access Mode

Address A[12:11]
A2
A[1:0]

Operation Mode MPR data read format
MPR access
MPR page selection

Description
00 = Serial ........... 01 = Parallel 10 = Staggered .... 11 = Reserved
0 = Standard operation (MPR not enabled) 1 = MPR data flow enabled
00 = Page 0 .... 01 = Page 1 10 = Page 2 .... 11 = Page 3

Table 29: DRAM Address to MPR UI Translation

MPR Location

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

DRAM address ­ Ax

A7

A6

A5

A4

A3

A2

A1

A0

MPR UI ­ UIx

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Table 30: MPR Page and MPRx Definitions

Address MPR Location [7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Note

MPR Page 0 ­ Read or Write (Data Patterns)

BA[1:0]

00 = MPR0

0

1

0

1

0

1

0

1

Read/

01 = MPR1

0

0

1

1

0

0

1

1

Write

(default

10 = MPR2

0

0

0

0

1

1

1

1

value lis-

11 = MPR3

0

0

0

0

0

0

0

0

ted)

MPR Page 1 ­ Read-only (Error Log)

BA[1:0]

00 = MPR0

A7

A6

A5

A4

A3

A2

A1

A0 Read-on-

01 = MPR1 CAS_n/A WE_n/A1 A13

A12

A11

A10

A9

A8

ly

15

4

10 = MPR2

PAR ACT_n BG1

BG0

BA1

BA0

A17 RAS_n/A

16

11 = MPR3 CRC er- CA pari- CA parity latency: [5] =

C2

ror sta- ty error MR5[2], [4] = MR5[1], [3] =

tus

status

MR5[0]

C1

C0

MPR Page 2 ­ Read-only (MRS Readout)

BA[1:0]

00 = MPR0

hPPR support

sPPR support

RTT(WR) MR2[11]

Temperature sensor status2

CRC write enable MR2[12]

RTT(WR) MR2[10:9]

Read-only

01 = MPR1

VREFDQ traing-
ing range MR6[6]

VREFDQ training value: [6:1] = MR6[5:0]

Geardown enable MR3[3]

10 = MPR2

CAS latency: [7:3] = MR0[6:4,2,12]

CAS write latency [2:0] = MR2[5:3]

11 = MPR3

RTT(NOM): [7:5] = MR1[10:8]

RTT(Park): [4:2] = MR5[8:6]

RON: [1:0] = MR2[2:1]

MPR Page 3 ­ Read-only (Restricted, except for MPR3 [3:0])

BA[1:0]

00 = MPR0

DC

DC

DC

DC

DC

DC

DC

DC Read-on-

01 = MPR1

DC

DC

DC

DC

DC

DC

DC

DC

ly

10 = MPR2

DC

DC

DC

DC

DC

DC

DC

DC

11 = MPR3

DC

DC

DC

DC

MAC

MAC

MAC MAC

Notes: 1. DC = "Don't Care" 2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh; MPR[4:3] 11 = Reserved

MPR Reads

MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not supported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ operation; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR mode. READ commands for BC4 are supported with a starting column address of A[2:0] = 000

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
or 100. After power-up, the content of MPR Page 0 has the default values, which are defined in Table 30. MPR page 0 can be rewritten via an MPR WRITE command. The device maintains the default values unless it is rewritten by the DRAM controller. If the DRAM controller does overwrite the default values (Page 0 only), the device will maintain the new values unless re-initialized or there is power loss.
Timing in MPR mode:
· Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between READ commands
· Reads (back-to-back) from Pages 1, 2, or 3 may not use tCCD_S timing between READ commands; tCCD_L must be used for timing between READ commands
The following steps are required to use the MPR to read out the contents of a mode register (MPR Page x, MPRy).
1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read for-
mat, and MR3[1:0] MPR page. a. MR3[12:11] MPR read format: 1. 00 = Serial read format 2. 01 = Parallel read format 3. 10 = staggered read format 4. 11 = RFU b. MR3[1:0] MPR page: 1. 00 = MPR Page 0 2. 01 = MPR Page 1 3. 10 = MPR Page 2 4. 11 = MPR Page 3
4. tMRD and tMOD must be satisfied. 5. Redirect all subsequent READ commands to specific MPRx location. 6. Issue RD or RDA command.
a. BA1 and BA0 indicate MPRx location: 1. 00 = MPR0 2. 01 = MPR1 3. 10 = MPR2 4. 11 = MPR3
b. A12/BC = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported. 1. If BL = 8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR READ commands.
c. A2 = burst-type dependant: 1. BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7 2. BL8: A2 = 1 not allowed 3. BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T, T, T, T 4. BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T, T, T, T
d. A[1:0] = 00, data burst is fixed nibble start at 00. e. Remaining address inputs, including A10, and BG1 and BG0 are "Don't
Care." 7. After RL = AL + CL, DRAM bursts data from MPRx location; MPR readout format
determined by MR3[A12,11,1,0]. 8. Steps 5 through 7 may be repeated to read additional MPRx locations. 9. After the last MPRx READ burst, tMPRR must be satisfied prior to exiting. 10. Issue MRS command to exit MPR mode; MR3[2] = 0.

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
11. After the tMOD sequence is completed, the DRAM is ready for normal operation from the core (such as ACT).
MPR Readout Format
The MPR read data format can be set to three different settings: serial, parallel, and staggered.
MPR Readout Serial Format
The serial format is required when enabling the MPR function to read out the contents of an MRx, temperature sensor status, and the command address parity error frame. However, data bus calibration locations (four 8-bit registers) can be programmed to read out any of the three formats. The DRAM is required to drive associated strobes with the read data similar to normal operation (such as using MRS preamble settings).
Serial format implies that the same pattern is returned on all DQ lanes, as shown the table below, which uses values programmed into the MPR via [7:0] as 0111 1111.

Table 31: MPR Readout Serial Format

Serial

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

x4 Device

DQ0

0

1

1

1

1

1

1

1

DQ1

0

1

1

1

1

1

1

1

DQ2

0

1

1

1

1

1

1

1

DQ3

0

1

1

1

1

1

1

1

x8 Device

DQ0

0

1

1

1

1

1

1

1

DQ1

0

1

1

1

1

1

1

1

DQ2

0

1

1

1

1

1

1

1

DQ3

0

1

1

1

1

1

1

1

DQ4

0

1

1

1

1

1

1

1

DQ5

0

1

1

1

1

1

1

1

DQ6

0

1

1

1

1

1

1

1

DQ7

0

1

1

1

1

1

1

1

x16 Device

DQ0

0

1

1

1

1

1

1

1

DQ1

0

1

1

1

1

1

1

1

DQ2

0

1

1

1

1

1

1

1

DQ3

0

1

1

1

1

1

1

1

DQ4

0

1

1

1

1

1

1

1

DQ5

0

1

1

1

1

1

1

1

DQ6

0

1

1

1

1

1

1

1

DQ7

0

1

1

1

1

1

1

1

DQ8

0

1

1

1

1

1

1

1

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Table 31: MPR Readout Serial Format (Continued)

Serial DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

MPR Readout Parallel Format
Parallel format implies that the MPR data is returned in the first data UI and then repeated in the remaining UIs of the burst, as shown in the table below. Data pattern location 0 is the only location used for the parallel format. RD/RDA from data pattern locations 1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern programmed in the data pattern location 0 is 0111 1111. The x4 configuration only outputs the first four bits (0111 in this example). For the x16 configuration, the same pattern is repeated on both the upper and lower bytes.

Table 32: MPR Readout ­ Parallel Format

Parallel

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

x4 Device

DQ0

0

0

0

0

0

0

0

0

DQ1

1

1

1

1

1

1

1

1

DQ2

1

1

1

1

1

1

1

1

DQ3

1

1

1

1

1

1

1

1

x8 Device

DQ0

0

0

0

0

0

0

0

0

DQ1

1

1

1

1

1

1

1

1

DQ2

1

1

1

1

1

1

1

1

DQ3

1

1

1

1

1

1

1

1

DQ4

1

1

1

1

1

1

1

1

DQ5

1

1

1

1

1

1

1

1

DQ6

1

1

1

1

1

1

1

1

DQ7

1

1

1

1

1

1

1

1

x16 Device

DQ0

0

0

0

0

0

0

0

0

DQ1

1

1

1

1

1

1

1

1

DQ2

1

1

1

1

1

1

1

1

DQ3

1

1

1

1

1

1

1

1

DQ4

1

1

1

1

1

1

1

1

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Table 32: MPR Readout ­ Parallel Format (Continued)

Parallel

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

DQ5

1

1

1

1

1

1

1

1

DQ6

1

1

1

1

1

1

1

1

DQ7

1

1

1

1

1

1

1

1

DQ8

0

0

0

0

0

0

0

0

DQ9

1

1

1

1

1

1

1

1

DQ10

1

1

1

1

1

1

1

1

DQ11

1

1

1

1

1

1

1

1

DQ12

1

1

1

1

1

1

1

1

DQ13

1

1

1

1

1

1

1

1

DQ14

1

1

1

1

1

1

1

1

DQ15

1

1

1

1

1

1

1

1

MPR Readout Staggered Format
Staggered format of data return is defined as the staggering of the MPR data across the lanes. In this mode, an RD/RDA command is issued to a specific data pattern location and then the data is returned on the DQ from each of the different data pattern locations. For the x4 configuration, an RD/RDA to data pattern location 0 will result in data from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data from location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA command to data pattern location 1 will result in data from location 1 being driven on DQ0, data from location 2 being driven on DQ1, data from location 3 being driven on DQ2, and so on. Examples of different starting locations are also shown.

Table 33: MPR Readout Staggered Format, x4

x4 READ MPR0 Command

Stagger

UI[7:0]

DQ0

MPR0

DQ1

MPR1

DQ2

MPR2

DQ3

MPR3

x4 READ MPR1 Command x4 READ MPR2 Command x4 READ MPR3 Command

Stagger

UI[7:0]

Stagger

UI[7:0]

Stagger

UI[7:0]

DQ0

MPR1

DQ0

MPR2

DQ0

MPR3

DQ1

MPR2

DQ1

MPR3

DQ1

MPR0

DQ2

MPR3

DQ2

MPR0

DQ2

MPR1

DQ3

MPR0

DQ3

MPR1

DQ3

MPR2

It is expected that the DRAM can respond to back-to-back RD/RDA commands to the MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be created on the data bus with no bubbles or clocks between read data. In this case, the system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2), RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3).

Table 34: MPR Readout Staggered Format, x4 ­ Consecutive READs

Stagger DQ0 DQ1

UI[7:0] MPR0 MPR1

UI[15:8] MPR1 MPR2

UI[23:16] MPR2 MPR3

UI[31:24] MPR3 MPR0

UI[39:32] MPR0 MPR1

UI[47:40] MPR1 MPR2

UI[55:48] MPR2 MPR3

UI[63:56] MPR3 MPR0

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Table 34: MPR Readout Staggered Format, x4 ­ Consecutive READs (Continued)

Stagger DQ2 DQ3

UI[7:0] MPR2 MPR3

UI[15:8] MPR3 MPR0

UI[23:16] MPR0 MPR1

UI[31:24] MPR1 MPR2

UI[39:32] MPR2 MPR3

UI[47:40] MPR3 MPR0

UI[55:48] MPR0 MPR1

UI[63:56] MPR1 MPR2

For the x8 configuration, the same pattern is repeated on the lower nibble as on the upper nibble. READs to other MPR data pattern locations follow the same format as the x4 case. A read example to MPR0 for x8 and x16 configurations is shown below.

Table 35: MPR Readout Staggered Format, x8 and x16

x8 READ MPR0 Command

Stagger

UI[7:0]

DQ0

MPR0

DQ1

MPR1

DQ2

MPR2

DQ3

MPR3

DQ4

MPR0

DQ5

MPR1

DQ6

MPR2

DQ7

MPR3

x16 READ MPR0 Command

Stagger

UI[7:0]

DQ0

MPR0

DQ1

MPR1

DQ2

MPR2

DQ3

MPR3

DQ4

MPR0

DQ5

MPR1

DQ6

MPR2

DQ7

MPR3

x16 READ MPR0 Command

Stagger

UI[7:0]

DQ8

MPR0

DQ9

MPR1

DQ10

MPR2

DQ11

MPR3

DQ12

MPR0

DQ13

MPR1

DQ14

MPR2

DQ15

MPR3

MPR READ Waveforms
The following waveforms show MPR read accesses.

Figure 37: MPR READ Timing

CK_c CK_t Command
Address

T0

Ta0

Ta1

MPE Enable

PREA

MRS1

DES

tRP

tMOD

Valid

Valid

Valid

Tb0 READ Add2

Tc0 DES Valid

Tc1 DES Valid

Tc2 DES Valid

Tc3 DES Valid

Td0 DES Valid

Td1

Te0

Tf0

Tf1

MPE Disable

DES

MRS3

Valid4

tMPRR

tMOD

Valid

Valid

Valid

DES Valid

CKE
DQS_t, DQS_c
DQ

PL5 + AL + CL

UI0 UI1 UI2 UI5 UI6 UI7
Time Break
Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK. 2. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don't Care," including BG1 and BG0. A12 is "Don't Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01 3. Multipurpose registers read/write disable (MR3 A2 = 0). 4. Continue with regular DRAM command. 5. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.

Figure 38: MPR Back-to-Back READ Timing

T0

T1

T2

T3

T4

T5

T6

Ta0

CK_c

CK_t

Command DES Address Valid

READ Add2

DES

DES

tCCD_S1

Valid

Add2

DES Valid

READ

DES

Valid

Valid

DES Valid

CKE
DQS_t, DQS_c
DQ
DQS_t, DQS_c
DQ

PL3 + AL + CL

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Ta9

DES

DES

DES

DES

DES

DES

DES

DES

DES

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

UI0 UI1 UI2 UI3

UI0 UI1 UI2 UI3

Ta10 DES Valid

Time Break

Don't Care

Notes:

1. tCCD_S = 4tCK, Read Preamble = 1tCK.
2. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is fixed at 0, 1, 2, 3, T, T, T, T) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don't Care," including BG1 and BG0. A12 is "Don't Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Figure 39: MPR READ-to-WRITE Timing

T0

T1

T2

Ta0

Ta1

CK_c

CK_t

Command READ

DES

DES

DES

DES

Address Add1

Valid

Valid

Valid

Valid

Ta2 DES Valid

Ta3 DES Valid

Ta4 DES Valid

Ta5 DES Valid

Ta6

Tb0

Tb1

DES

WRITE

tMPRR

Valid

Add2

DES Valid

Tb2 DES Valid

CKE DQS_t, DQS_c
DQ
MPR Writes

PL3 + AL + CL

UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

Time Break

Don't Care

Notes:

1. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don't Care," including BG1 and BG0. A12 is "Don't Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01
2. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR BA1 and BA0 indicate the MPR location A10 and other address pins are "Don't Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.

MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0]. Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will maintain the new written values unless re-initialized or there is power loss.
The following steps are required to use the MPR to write to mode register MPR Page 0. 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR Page 0); writes to 01, 10, and 11 are not allowed. 4. tMRD and tMOD must be satisfied. 5. Redirect all subsequent WRITE commands to specific MPRx location. 6. Issue WR or WRA command: a. BA1 and BA0 indicate MPRx location 1. 00 = MPR0 2. 01 = MPR1 3. 10 = MPR2 4. 11 = MPR3 b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0].

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
c. Remaining address inputs, including A10, and BG1 and BG0 are "Don't Care."
7. tWR_MPR must be satisfied to complete MPR WRITE. 8. Steps 5 through 7 may be repeated to write additional MPRx locations. 9. After the last MPRx WRITE, tMPRR must be satisfied prior to exiting. 10. Issue MRS command to exit MPR mode; MR3[2] = 0. 11. When the tMOD sequence is completed, the DRAM is ready for normal operation
from the core (such as ACT).
MPR WRITE Waveforms
The following waveforms show MPR write accesses.

Figure 40: MPR WRITE and WRITE-to-READ Timing

CK_c CK_t Command
Address

T0

Ta0

Ta1

MPR Enable

PREA

MRS1

DES

tRP

tMOD

Valid

Valid

Valid

Tb0

Tc0

Tc1

WRITE Add2

DES

DES

tWR_MPR

Valid

Valid

Tc2 READ Add

Td0 DES Valid

Td1 DES Valid

Td2 DES Valid

Td3 DES Add2

Td4 DES Valid

Td5 DES Valid

CKE
DQS_t, DQS_c
DQ

PL3 + AL + CL

UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7

Time Break

Don't Care

Notes:

1. Multipurpose registers read/write enable (MR3 A2 = 1).
2. Address setting: BA1 and BA0 indicate the MPR location A10 and other address pins are "Don't Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Figure 41: MPR Back-to-Back WRITE Timing

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Ta9

Ta10

Command WRITE

DES

Address Add1

Valid

DES

DES

tWR_MPR

Valid

Add1

WRITE Valid

DES Valid

DES Add

DES Valid

DES

DES

Valid

Valid

DES Valid

DES

DES

Valid

Valid

CKE

DQS_t, DQS_c

DQ

Note:

1. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR A10 and other address pins are "Don't Care"

Time Break

MPR REFRESH Waveforms
The following waveforms show MPR accesses interaction with refreshes.

Don't Care

Figure 42: REFRESH Timing

CK_c CK_t Command
Address

T0

Ta0

Ta1

MPR Enable

PREA

MRS1

DES

tRP

tMOD

Valid

Valid

Valid

Tb0 REF2 Valid

Tb1 DES Valid

Tb2 DES Valid

Tb3

Tb4

DES

DES

tRFC

Valid

Valid

Tc0 DES Valid

Tc1 DES Valid

Tc2 Valid Valid

Tc3 Valid Valid

Tc4 Valid Valid

Time Break

Don't Care

Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1). Redirect all subsequent read and writes to MPR locations.
2. 1x refresh is only allowed when MPR mode is enabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register

Figure 43: READ-to-REFRESH Timing

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Ta9

CK_c

CK_t

Command READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

REF2

DES

DES

Address Add1

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

CKE
BL = 8 DQS_t, DQS_c
DQ
BC = 4 DQS_t, DQS_c
DQ

PL + AL + CL

(4 + 1) Clocks UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3

tRFC

Time Break

Don't Care

Notes:

1. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don't Care," including BG1 and BG0. A12 is "Don't Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01
2. 1x refresh is only allowed when MPR mode is enabled.

Figure 44: WRITE-to-REFRESH Timing

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Command WRITE Address Add1

DES Valid

DES tWR_MPR
Valid

DES Valid

REF2 Valid

Ta3 DES Valid

Ta4 DES Valid

Ta5

Ta6

DES

DES

tRFC

Valid

Valid

Ta7 DES Valid

Ta8 DES Valid

Ta9 DES Valid

Ta10 DES Valid

CKE
DQS_t, DQS_c
DQ

Notes: 1. Address setting: BA1 and BA0 indicate the MPR location

Time Break

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register
A[7:0] = data for MPR A10 and other address pins are "Don't Care" 2. 1x refresh is only allowed when MPR mode is enabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode
Gear-Down Mode
The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and uses a low-frequency MRS command (the MRS command has relaxed setup and hold) followed by a sync pulse (first CS pulse after MRS setting) to align the proper clock edge for operating the control lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. Gear-down mode is only supported at DDR4-2666 and faster. For operation in 1/2 rate mode, neither an MRS command or a sync pulse is required. Gear-down mode may only be entered during initialization or self refresh exit and may only be exited during self refresh exit. CAL mode and CA parity mode must be disabled prior to gear-down mode entry. The two modes may be enabled after tSYNC_GEAR and tCMD_GEAR periods have been satisfied. The general sequence for operation in 1/4 rate during initialization is as follows:
1. The device defaults to a 1N mode internal clock at power-up/reset. 2. Assertion of reset. 3. Assertion of CKE enables the DRAM. 4. MRS is accessed with a low-frequency N × tCK gear-down MRS command. (NtCK
static MRS command is qualified by 1N CS_n. ) 5. The memory controller will send a 1N sync pulse with a low-frequency N × tCK
NOP command. tSYNC_GEAR is an even number of clocks. The sync pulse is on an even edge clock boundary from the MRS command. 6. Initialization sequence, including the expiration of tDLLK and tZQinit, starts in 2N mode after tCMD_GEAR from 1N sync pulse.
The device resets to 1N gear-down mode after entering self refresh. The general sequence for operation in gear-down after self refresh exit is as follows:
1. MRS is set to 1, via MR3[3], with a low-frequency N × tCK gear-down MRS command. a. The NtCK static MRS command is qualified by 1N CS_n, which meets tXS or tXS_ABORT. b. Only a REFRESH command may be issued to the DRAM before the NtCK static MRS command.
2. The DRAM controller sends a 1N sync pulse with a low-frequency N × tCK NOP command. a. tSYNC_GEAR is an even number of clocks. b. The sync pulse is on even edge clock boundary from the MRS command.
3. A valid command not requiring locked DLL is available in 2N mode after tCMD_GEAR from the 1N sync pulse. a. A valid command requiring locked DLL is available in 2N mode after tXSDLL or tDLLK from the 1N sync pulse.
4. If operation is in 1N mode after self refresh exit, N × tCK MRS command or sync pulse is not required during self refresh exit. The minimum exit delay to the first valid command is tXS, or tXS_ABORT.
The DRAM may be changed from 2N to 1N by entering self refresh mode, which will reset to 1N mode. Changing from 2N to by any other means can result in loss of data and make operation of the DRAM uncertain.
When operating in 2N gear-down mode, the following MR settings apply:
· CAS latency (MR0[6:4,2]): Even number of clocks
· Write recovery and read to precharge (MR0[11:9]): Even number of clocks
· Additive latency (MR1[4:3]): CL - 2
· CAS WRITE latency (MR2 A[5:3]): Even number of clocks

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4Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode

· CS to command/address latency mode (MR4[8:6]): Even number of clocks · CA parity latency mode (MR5[2:0]): Even number of clocks

Figure 45: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization)

CK_c CK_t
DRAM internal CLK

tCKSRX

TdkN1

TdkN + Neven2

RESET_n

CKE
CS_n Command
Time Break

tXPR_GEAR

tSYNC_GEAR 1N sync pulse

tCMD_GEAR

2N mode

tGEAR_setup tGEAR_hold

tGEAR_setup tGEAR_hold

MRS

NOP

Valid

Configure DRAM
to 1/4 rate Don't Care

1) After tSYNC_GEAR from gear down command, internal clock rate is changed at TdkN 2) After tSYNC_GEAR + tCMD_GEAR from gear down command, both internal clock rate and
command cycle are changed at TdkN+Neven

Figure 46: Clock Mode Change After Exiting Self Refresh

CK_c CK_t
DRAM internal CLK

TdkN1

TdkN + Neven2

CKE CS_n Command

tXPR_GEAR

tSYNC_GEAR 1N sync pulse

tCMD_GEAR

2N mode

Time Break

tGEAR_setup tGEAR_hold
MRS
Configure DRAM to 1/4 rate
Don't Care

tGEAR_setup tGEAR_hold

NOP

Valid

1) After tSYNC_GEAR from gear down command, internal clock rate is changed at TdkN 2) After tSYNC_GEAR + tCMD_GEAR from gear down command, both internal clock rate and
command cycle are changed at TdkN+Neven

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Figure 47: Comparison Between Gear-Down Disable and Gear-Down Enable

T0 CK_c CK_t

T1

T2

T3

T15

T16

T17

T18

T19

T30

T31

T32

T33

T34

T35

T36

T37

T38

AL = 0 (geardown = disable)

Command ACT

DES

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DQ tRCD = 16

RL =CL= 16 (AL = 0)

DO DO DO DO DO DO DO DO n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7

AL = CL - 1 (geardown = disable)

READ

Command ACT

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DQ

DO DO DO DO DO DO DO DO n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7

RL = AL + CL = 31 (AL = CL - 1 = 15)

Command ACT

READ

READ

DES

DES

DES

DES

DES

DES

DES

DQ

DO DO DO DO DO DO DO DO n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7

AL + CL = RL = 30 (AL = CL - 2 = 14)

Time Break

Transitioning Data

Don't Care

108

4Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode

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4Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode
Maximum Power-Saving Mode
Maximum power-saving mode provides the lowest power mode where data retention is not required. When the device is in the maximum power-saving mode, it does not maintain data retention or respond to any external command, except the MAXIMUM POWER SAVING MODE EXIT command and during the assertion of RESET_n signal LOW. This mode is more like a "hibernate mode" than a typical power-saving mode. The intent is to be able to park the DRAM at a very low-power state; the device can be switched to an active state via the per-DRAM addressability (PDA) mode.
Maximum Power-Saving Mode Entry
Maximum power-saving mode is entered through an MRS command. For devices with shared control/address signals, a single DRAM device can be entered into the maximum power-saving mode using the per-DRAM addressability MRS command. Large CS_n hold time to CKE upon the mode exit could cause DRAM malfunction; as a result, CA parity, CAL, and gear-down modes must be disabled prior to the maximum powersaving mode entry MRS command.
The MRS command may use both address and DQ information, as defined in the PerDRAM Addressability section. As illustrated in the figure below, after tMPED from the mode entry MRS command, the DRAM is not responsive to any input signals except CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals may become High-Z). The system will provide a valid clock until tCKMPE expires, at which time clock inputs (CK) should be disabled (external clock signals may become High-Z).

Figure 48: Maximum Power-Saving Mode Entry

Ta0

Ta1

Ta2

Tb0

Tb1

Tb3

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Tc11

CK_c

CK_t

tCKMPE

MR4[A1=1] MPSM Enable)

Command DES

MRS

DES

DES

DES

tMPED

Address

Valid

CS_n

CKE

CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode

RESET_n

Time Break

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode
Maximum Power-Saving Mode Entry in PDA
The sequence and timing required for the maximum power-saving mode with the perDRAM addressability enabled is illustrated in the figure below.

Figure 49: Maximum Power-Saving Mode Entry with PDA

Ta0

Ta1

Ta2

Tb0

Tb1

Tb3

Tb4

Tb5

Tb6

Tb7

Tb8

Tb9

Tc0

Tc1

Tc2

Td0

Td1

Td2

CK_c

CK_t

MR4[A1 = 1] MPSM Enable)

Command DES

MRS

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCKMPE

CS_n

CKE
DQS_t DQS_c
DQ0

AL + CWL

tPDA_S

tMPED tPDA_H

RESET_n

Time Break

Don't Care

CKE Transition During Maximum Power-Saving Mode
The following figure shows how to maintain maximum power-saving mode even though the CKE input may toggle. To prevent the device from exiting the mode, CS_n should be HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (tMPX_S) and hold (tMPX_H) timings.

Figure 50: Maintaining Maximum Power-Saving Mode with CKE Transition

CLK

CMD

CS_n CKE

tMPX_S tMPX_HH

RESET_n

Don't Care

Maximum Power-Saving Mode Exit
To exit the maximum power-saving mode, CS_n should be LOW at the CKE LOW-toHIGH transition, with appropriate setup (tMPX_S) and hold (tMPX_LH) timings, as

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4Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode
shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during this mode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n signal level is detected LOW, the DRAM clears the maximum power-saving mode MRS bit and begins the exit procedure from this mode. The external clock must be restarted and be stable by tCKMPX before the device can exit the maximum power-saving mode. During the exit time (tXMP), only NOP and DES commands are allowed: NOP during tMPX_LH and DES the remainder of tXMP. After tXMP expires, valid commands not requiring a locked DLL are allowed; after tXMP_DLL expires, valid commands requiring a locked DLL are allowed.

Figure 51: Maximum Power-Saving Mode Exit

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tb2

Tb3

Tc0

Tc1

Tc2

Tc4

Td0

Td1

Td2

Td3

Te0

Te1

CK_c

CK_t

tCKMPX

Command CS_n CKE

NOP

NOP

NOP

NOP

NOP

DES

DES

DES

DES

Valid

DES

DES

tMPX_LH

tMPX_S

tXMP tXMP_DLL

RESET_n

Time Break

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity
Command/Address Parity
Command/address (CA) parity takes the CA parity signal (PAR) input carrying the parity bit for the generated address and commands signals and matches it to the internally generated parity from the captured address and commands signals. CA parity is supported in the DLL enabled state only; if the DLL is disabled, CA parity is not supported.
Figure 52: Command/Address Parity Operation

DRAM Controller CMD/ADDR
Even parity GEN
Even parity bit

CMD/ADDR Even parity bit

DRAM
CMD/ADDR
Even parity GEN
Compare parity bit

CA parity is disabled or enabled via an MRS command. If CA parity is enabled by programming a non-zero value to CA parity latency in the MR, the DRAM will ensure that there is no parity error before executing commands. There is an additional delay required for executing the commands versus when parity is disabled. The delay is programmed in the MR when CA parity is enabled (parity latency) and applied to all commands which are registered by CS_n (rising edge of CK_t and falling CS_n). The command is held for the time of the parity latency (PL) before it is executed inside the device. The command captured by the input clock has an internal delay before executing and is determined with PL. ALERT_n will go active when the DRAM detects a CA parity error.
CA parity covers ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, the address bus including bank address and bank group bits, and C[2:0] on 3DS devices; the control signals CKE, ODT, and CS_n are not covered. For example, for a 4Gb x4 monolithic device, parity is computed across BG[1:0], BA[1:0], A16/RAS_n, A15/CAS_n, A14/ WE_n, A[13:0], and ACT_n. The DRAM treats any unused address pins internally as zeros; for example, if a common die has stacked pins but the device is used in a monolithic application, then the address pins used for stacking and not connected are treated internally as zeros.
The convention for parity is even parity; for example, valid parity is defined as an even number of ones across the inputs used for parity computation combined with the parity signal. In other words, the parity bit is chosen so that the total number of ones in the transmitted signal, including the parity bit, is even.
If a DRAM device detects a CA parity error in any command qualified by CS_n, it will perform the following steps:
1. Ignore the erroneous command. Commands in the MAX NnCK window (tPAR_UNKNOWN) prior to the erroneous command are not guaranteed to be executed. When a READ command in this NnCK window is not executed, the device

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4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity
does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set. When CA Parity and WRITE CRC are both enabled and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset. 2. Log the error by storing the erroneous command and address bits in the MPR error log. 3. Set the parity error status bit in the mode register to 1. The parity error status bit must be set before the ALERT_n signal is released by the DRAM (that is, tPAR_ALERT_ON + tPAR_ALERT_PW (MIN)). 4. Assert the ALERT_n signal to the host (ALERT_n is active LOW) within tPAR_ALERT_ON time. 5. Wait for all in-progress commands to complete. These commands were received tPAR_UNKOWN before the erroneous command. 6. Wait for tRAS (MIN) before closing all the open pages. The DRAM is not executing any commands during the window defined by (tPAR_ALERT_ON + tPAR_ALERT_PW ). 7. After tPAR_ALERT_PW (MIN) has been satisfied, the device may de-assert ALERT_n.
a. When the device is returned to a known precharged state, ALERT_n is allowed to be de-asserted.
8. After (tPAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for normal operation. Parity latency will be in effect; however, parity checking will not resume until the memory controller has cleared the parity error status bit by writing a zero. The DRAM will execute any erroneous commands until the bit is cleared; unless persistent mode is enabled.
· It is possible that the device might have ignored a REFRESH command during tPAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is recommended that extra REFRESH cycles be issued, as needed.
· The parity error status bit may be read anytime after tPAR_ALERT_ON + tPAR_ALERT_PW to determine which DRAM had the error. The device maintains the error log for the first erroneous command until the parity error status bit is reset to a zero or a second CA parity occurs prior to resetting.
The mode register for the CA parity error is defined as follows: CA parity latency bits are write only, the parity error status bit is read/write, and error logs are read-only bits. The DRAM controller can only program the parity error status bit to zero. If the DRAM controller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be certain that parity will be checked; the DRAM may opt to block the DRAM controller from writing a 1 to the parity error status bit.
The device supports persistent parity error mode. This mode is enabled by setting MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asserted, even if the parity error status bit remains a 1. If multiple errors occur before the error status bit is cleared the error log in MPR Page 1 should be treated as "Don't Care." In persistent parity error mode the ALERT_n pulse will be asserted and de-asserted by the DRAM as defined with the MIN and MAX value tPAR_ALERT_PW. The DRAM controller must issue DESELECT commands once it detects the ALERT_n signal, this response time is defined as tPAR_ALERT_RSP. The following figures capture the flow of events on the CA bus and the ALERT_n signal.

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4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity

Table 36: Mode Register Setting for CA Parity

CA Parity Latency MR5[2:0]1
000 = Disabled 001 = 4 clocks 010 = 5 clocks 011 = 6 clocks 100 = 8 clocks 101 = Reserved 110 = Reserved 111 = Reserved

Applicable Speed Bin N/A
1600, 1866, 2133 2400, 2666 2933, 3200 RFU RFU RFU RFU

Parity Error Status Parity Persistent Mode

Erroneous CA Frame

MR5 [4] 0 = Clear MR5 [4] 1 = Error

C[2:0], ACT_n, BG1,

BG0, BA[1:0], PAR,

MR5 [9] 0 = DisabledMR5 [9] 1 = Enabled

A17, A16/RAS_n, A15/

CAS_n, A14/WE_n,

A[13:0]

Notes:

1. Parity latency is applied to all commands.
2. Parity latency can be changed only from a CA parity disabled state; for example, a direct change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to PL = 4.
3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL. READ latency = AL + CL + PL.

Figure 53: Command/Address Parity During Normal Operation

CK_c CK_t
Command/ Address

T0 Valid2

T1 Valid2

Ta0 Valid2

tPAR_UNKNOWN2

Ta1

Ta2

Tb0

Tc0

Tc1

Td0

Error

Valid

Valid

tPAR_ALERT_ON

Valid

DES2

t > 2nCK

tPAR_ALERT_PW1

DES2 tRP

ALERT_n

Te0 Valid3

Te1 Valid3

Valid2

DES2 Command execution unknown

Error

Valid Command not executed

Valid3 Command executed

Don't Care

Time Break

Notes:

1. DRAM is emptying queues. Precharge all and parity checking are off until parity error status bit is cleared.
2. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking is off until parity error status bit is cleared.

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4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity

Figure 54: Persistent CA Parity Error Checking Operation

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Tb0

Tc0

Tc1

Command/ Address

Valid2

Valid2

Valid2

tPAR_UNKNOWN2

Error

Valid

tPAR_ALERT_ON

Valid

Valid

DES

tPAR_ALERT_RSP

tPAR_ALERT_PW1

ALERT_n

Td0
DES t > 2nCK

Te0

Te1

DES tRP

Valid3

Valid2 Error Valid3

DES Command execution unknown Valid Command not executed Command executed

Don't Care

Time Break

Notes:

1. DRAM is emptying queues. Precharge all and parity check re-enable finished by tPAR_ALERT_PW.
2. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set
3. Normal operation with parity latency and parity checking (CA parity persistent error mode enabled).

Figure 55: CA Parity Error Checking ­ SRE Attempt

T0 CK_c
CK_t

T1

Ta0

Ta1

Tb0

Tb1

Tc0

Tc1

Td0

Td1

Td2

Td3

Te0

Te1

tCPDED + PL

tXP + PL

Command/ Address
CKE

DES1, 5 tIH

Error2 tIS

DES1 tPAR_ALERT_ON

Note 4

DES6 tIS

DES6

tPAR_ALERT_PW1

t > 2nCK

DES5

Valid3

tRP

ALERT_n

DES1, 5 Error2 Valid3

DES6

DES5 Command execution unknown

DES1 Command not executed

Command executed

Don't Care

Time Break

Notes:

1. Only DESELECT command is allowed. 2. SELF REFRESH command error. The DRAM masks the intended SRE command and enters
precharge power-down. 3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until the parity error status bit cleared. 4. The controller cannot disable the clock until it has been capable of detecting a possible
CA parity error. 5. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. 6. Only a DESELECT command is allowed; CKE may go HIGH prior to Tc2 as long as DES commands are issued.

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4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity

Figure 56: CA Parity Error Checking ­ SRX Attempt

T0 CK_c CK_t

Command/ Address

SRX1

tIS

CKE

Ta0

Ta1

Tb0

Tb1

Tc0

DES

DES

Error2

Valid2

Valid2

tPAR_UNKNOWN

tPAR_ALERT_ON

ALERT_n

tXS_FAST8 tXS tXSDLL

Tc1

Tc2

Td0

Td1

Te0

Tf0

Valid2

DES2, 3

DES2, 3

Valid2, 4, 5

t > 2nCK

tRP

Valid2, 4, 6

Valid2, 4, 7

tPAR_ALERT_PW

SRX1

DES Valid3, 5 Command execution unknown

Error

Valid Command not executed

Valid4,5,6,7 Command executed

Time Break

Don't Care

Notes:

1. Self refresh abort = disable: MR4 [9] = 0. 2. Input commands are bounded by tXSDLL, tXS, tXS_ABORT, and tXS_FAST timing.
3. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications.
4. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking off until parity error status bit cleared.
5. Only an MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL command is allowed.
6. Valid commands not requiring a locked DLL.
7. Valid commands requiring a locked DLL. 8. This figure shows the case from which the error occurred after tXS_FAST. An error may
also occur after tXS_ABORT and tXS.

Figure 57: CA Parity Error Checking ­ PDE/PDX

T0 CK_c CK_t

T1

Ta0

Ta1

Tb0

Tb1

Tc0

Tc1

Td0

Td1

Td2

Td3

Te0

Te1

tCPDED + PL

tXP + PL

Command/ Address
CKE

Error2 tIH

DES1 tIS

DES1 tPAR_ALERT_ON

DES5 tIS

DES5

tPAR_ALERT_PW1

t > 2nCK

DES4

Valid3

tRP

ALERT_n

DES4 Error2 Valid3

DES5 Command execution unknown DES1 Command not executed Command executed

Don't Care

Time Break

Notes:

1. Only DESELECT command is allowed. 2. Error could be precharge or activate. 3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit cleared.

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4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity

4. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications.
5. Only a DESELECT command is allowed; CKE may go HIGH prior to Td2 as long as DES commands are issued.

Figure 58: Parity Entry Timing Example ­ tMRD_PAR

Ta0

Ta1

Ta2

Tb0

Tb1

Tb2

CK_c

CK_t

Command

DES

MRS

DES

DES

MRS

DES

Parity latency

PL = 0

Updating setting tMRD_PAR

PL = N

Enable parity

Time Break

Don't Care

Note: 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.

Figure 59: Parity Entry Timing Example ­ tMOD_PAR

Ta0

Ta1

Ta2

Tb0

Tb1

Tb2

CK_c

CK_t

Command

DES

MRS

DES

DES

Valid

DES

Parity latency

PL = 0

Updating setting tMOD_PAR

PL = N

Enable parity

Time Break

Don't Care

Note: 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.

Figure 60: Parity Exit Timing Example ­ tMRD_PAR

Ta0 CK_c CK_t

Ta1

Ta2

Tb0

Tb1

Tb2

Command

DES

MRS

DES

DES

MRS

DES

Parity latency

PL = N

Updating setting tMRD_PAR

Disable parity

Time Break

Don't Care

Note: 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.

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Figure 61: Parity Exit Timing Example ­ tMOD_PAR

Ta0

Ta1

Ta2

CK_c

CK_t

Command

DES

MRS

DES

4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity

Tb0

Tb1

Tb2

DES

Valid

DES

Parity latency

PL = N

Updating setting tMOD_PAR

Disable parity

Time Break

Don't Care

Note: 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Figure 62: CA Parity Flow Diagram

CA process start

MR5[2:0] set parity latency (PL) MR5[4] set parity error status to 0 MR5[9] enable/disable persistent mode

CA latched in

119

CA parity Yes enabled
No

Persistent Yes mode enabled
No

MR5[4] = 0 Yes @ ADDR/CMD
latched

No

Yes CA error
No

CA parity Yes error
No

Good CA processed

Ignore bad CMD

ALERT_n LOW 44 to 144 CKs

Command execution unknown
Log error/ set parity status

Good CA processed

Bad CA processed

Internal precharge all

Normal operation ready

Operation ready?

ALERT_n HIGH

CA parity Yes error
No

Good CA processed

Ignore bad CMD

Command execution unknown

ALERT_n LOW 44 to 144 CKs

MR5[4] = 0 Yes @ ADDR/CMD
latched
No
Internal precharge all

Log error/ set parity status

ALERT_n HIGH
Command execution unknown

Command execution unknown

Normal operation ready MR5[4] reset to 0 if desired

Normal operation ready MR5[4] reset to 0 if desired

4Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity

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4Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability

Per-DRAM Addressability

DDR4 allows programmability of a single, specific DRAM on a rank. As an example, this feature can be used to program different ODT or VREF values on each DRAM on a given rank. Because per-DRAM addressability (PDA) mode may be used to program optimal VREF for the DRAM, the data set up for first DQ0 transfer or the hold time for the last DQ0 transfer cannot be guaranteed. The DRAM may sample DQ0 on either the first falling or second rising DQS transfer edge. This supports a common implementation between BC4 and BL8 modes on the DRAM. The DRAM controller is required to drive DQ0 to a stable LOW or HIGH state during the length of the data transfer for BC4 and BL8 cases. Note, both fixed and on-the-fly (OTF) modes are supported for BC4 and BL8 during PDA mode.
1. Before entering PDA mode, write leveling is required.

· BL8 or BC4 may be used. 2. Before entering PDA mode, the following MR settings are possible:

· RTT(Park) MR5 A[8:6] = Enable
· RTT(NOM) MR1 A[10:8] = Enable 3. Enable PDA mode using MR3 [4] = 1. (The default programed value of MR3[4] = 0.) 4. In PDA mode, all MRS commands are qualified with DQ0. The device captures
DQ0 by using DQS signals. If the value on DQ0 is LOW, the DRAM executes the MRS command. If the value on DQ0 is HIGH, the DRAM ignores the MRS command. The controller can choose to drive all the DQ bits. 5. Program the desired DRAM and mode registers using the MRS command and DQ0. 6. In PDA mode, only MRS commands are allowed. 7. The MODE REGISTER SET command cycle time in PDA mode, AL + CWL + BL/2 0.5tCK + tMRD_PDA + PL, is required to complete the WRITE operation to the mode register and is the minimum time required between two MRS commands. 8. Remove the device from PDA mode by setting MR3[4] = 0. (This command requires DQ0 = 0.)

Note: Removing the device from PDA mode will require programming the entire MR3 when the MRS command is issued. This may impact some PDA values programmed within a rank as the EXIT command is sent to the rank. To avoid such a case, the PDA enable/disable control bit is located in a mode register that does not have any PDA mode controls.
In PDA mode, the device captures DQ0 using DQS signals the same as in a normal WRITE operation; however, dynamic ODT is not supported. Extra care is required for the ODT setting. If RTT(NOM) MR1 [10:8] = enable, device data termination needs to be controlled by the ODT pin, and applies the same timing parameters (defined below).

Symbol DODTLon DODTLoff
tADC tAONAS tAOFAS

Parameter Direct ODT turnon latency Direct ODT turn off latency
RTT change timing skew Asynchronous RTT(NOM) turn-on delay Asynchronous RTT(NOM) turn-off delay

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4Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability

Figure 63: PDA Operation Enabled, BL8

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Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.

Figure 64: PDA Operation Enabled, BC4

CK_c CK_t MR3 A4 = 1 (PDA enable) MRS DQS_t DQS_c DQ0
ODT
RTT

tMOD

MRS

CWL+AL+PL

tMRD_PDA

MRS

tPDA_S DODTLoff = WL-3

tPDA_H

DODTLon = WL-3

RTT(Park)

RTT(NOM)

RTT(Park)

Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.

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4Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability

Figure 65: MRS PDA Exit

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Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.

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4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration
VREFDQ Calibration
The VREFDQ level, which is used by the DRAM DQ input receivers, is internally generated. The DRAM V REFDQ does not have a default value upon power-up and must be set to the desired value, usually via VREFDQ calibration mode. If PDA or PPR modes (hPPR or sPPR) are used prior to VREFDQ calibration, VREFDQ should initially be set at the midpoint between the VDD,max, and the LOW as determined by the driver and ODT termination selected with wide voltage swing on the input levels and setup and hold times of approximately 0.75UI. The memory controller is responsible for V REFDQ calibration to determine the best internal VREFDQ level. The V REFDQ calibration is enabled/disabled via MR6[7], MR6[6] selects Range 1 (60% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of VDDQ), and an MRS protocol using MR6[5:0] to adjust the VREFDQ level up and down. MR6[6:0] bits can be altered using the MRS command if MR6[7] is enabled. The DRAM controller will likely use a series of writes and reads in conjunction with VREFDQ adjustments to obtain the best VREFDQ, which in turn optimizes the data eye.
The internal VREFDQ specification parameters are voltage range, step size, VREF step time, VREF full step time, and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for DDR4 SDRAM devices. The minimum range is defined by VREFDQ,min and VREFDQ,max. As noted, a calibration sequence, determined by the DRAM controller, should be performed to adjust VREFDQ and optimize the timing and voltage margin of the DRAM data input receivers. The internal VREFDQ voltage value may not be exactly within the voltage range setting coupled with the VREF set tolerance; the device must be calibrated to the correct internal VREFDQ voltage.
Figure 66: VREFDQ Voltage Range
VDDQ

VREF range

VREF,max VREF,min

VSWING small VSWING large

System variance Total range

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VREFDQ Range and Levels

4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration

Table 37: VREFDQ Range and Levels

MR6[5:0] 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001

Range 1 MR6[6] 0 60.00% 60.65% 61.30% 61.95% 62.60% 63.25% 63.90% 64.55% 65.20% 65.85% 66.50% 67.15% 67.80% 68.45% 69.10% 69.75% 70.40% 71.05% 71.70% 72.35% 73.00% 73.65% 74.30% 74.95% 75.60% 76.25%

Range 2 MR6[6] 1 45.00% 45.65% 46.30% 46.95% 47.60% 48.25% 48.90% 49.55% 50.20% 50.85% 51.50% 52.15% 52.80% 53.45% 54.10% 54.75% 55.40% 56.05% 56.70% 57.35% 58.00% 58.65% 59.30% 59.95% 60.60% 61.25%

MR6[5:0] Range 1 MR6[6] 0

01 1010

76.90%

01 1011

77.55%

01 1100

78.20%

01 1101

78.85%

01 1110

79.50%

01 1111

80.15%

10 0000

80.80%

10 0001

81.45%

10 0010

82.10%

10 0011

82.75%

10 0100

83.40%

10 0101

84.05%

10 0110

84.70%

10 0111

85.35%

10 1000

86.00%

10 1001

86.65%

10 1010

87.30%

10 1011

87.95%

10 1100

88.60%

10 1101

89.25%

10 1110

89.90%

10 1111

90.55%

11 0000

91.20%

11 0001

91.85%

11 0010

92.50%

11 0011 to 11 1111 = Reserved

Range 2 MR6[6] 1 61.90% 62.55% 63.20% 63.85% 64.50% 65.15% 65.80% 66.45% 67.10% 67.75% 68.40% 69.05% 69.70% 70.35% 71.00% 71.65% 72.30% 72.95% 73.60% 74.25% 74.90% 75.55% 76.20% 76.85% 77.50%

VREFDQ Step Size

The VREF step size is defined as the step size between adjacent steps. VREF step size ranges from 0.5% VDDQ to 0.8% VDDQ. However, for a given design, the device has one value for VREF step size that falls within the range.
The VREF set tolerance is the variation in the VREF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a function of number of steps n.
The VREF set tolerance is measured with respect to the ideal line, which is based on the MIN and MAX VREF value endpoints for a specified range. The internal V REFDQ voltage

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4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration
value may not be exactly within the voltage range setting coupled with the VREF set tolerance; the device must be calibrated to the correct internal VREFDQ voltage.
Figure 67: Example of VREF Set Tolerance and Step Size

VREF

Actual VREF output

VREF set tolerance

VREF set tolerance
VREF step size

Straight line (endpoint fit)

Note: 1. Maximum case shown.

Digital Code

VREFDQ Increment and Decrement Timing
The VREF increment/decrement step times are defined by VREF,time. VREF,time is defined from t0 to t1, where t1 is referenced to the VREF voltage at the final DC level within the VREF valid tolerance (VREF,val_tol). The V REF valid level is defined by VREF,val tolerance to qualify the step time t1. This parameter is used to insure an adequate RC time constant behavior of the voltage level change after any VREF increment/decrement adjustment.

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Figure 68: VREFDQ Timing Diagram for VREF,time Parameter
CK_c CK_t

4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration

Command DQ VREF

MRS VREF setting adjustment Old VREF setting
t0

Updating VREF setting VREF_time

New VREF setting t1

Don't Care
Note: 1. t0 is referenced to the MRS command clock t1 is referenced to VREF,tol
VREFDQ calibration mode is entered via an MRS command, setting MR6[7] to 1 (0 disables VREFDQ calibration mode) and setting MR6[6] to either 0 or 1 to select the desired range (MR6[5:0] are "Don't Care"). After VREFDQ calibration mode has been entered, VREFDQ calibration mode legal commands may be issued once tVREFDQE has been satisfied. Legal commands for VREFDQ calibration mode are ACT, WR, WRA, RD, RDA, PRE, DES, and MRS to set VREFDQ values, and MRS to exit VREFDQ calibration mode. Also, after VREFDQ calibration mode has been entered, "dummy" WRITE commands are allowed prior to adjusting the VREFDQ value the first time VREFDQ calibration is performed after initialization.
Setting VREFDQ values requires MR6[7] be set to 1 and MR6[6] be unchanged from the initial range selection; MR6[5:0] may be set to the desired VREFDQ values. If MR6[7] is set to 0, MR6[6:0] are not written. VREF,time-short or VREF,time-long must be satisfied after each MR6 command to set VREFDQ value before the internal VREFDQ value is valid.
If PDA mode is used in conjunction with VREFDQ calibration, the PDA mode requirement that only MRS commands are allowed while PDA mode is enabled is not waived. That is, the only VREFDQ calibration mode legal commands noted above that may be used are the MRS commands: MRS to set VREFDQ values and MRS to exit VREFDQ calibration mode.
The last MR6[6:0] setting written to MR6 prior to exiting VREFDQ calibration mode is the range and value used for the internal VREFDQ setting. VREFDQ calibration mode may be exited when the DRAM is in idle state. After the MRS command to exit VREFDQ calibration mode has been issued, DES must be issued until tVREFDQX has been satisfied where any legal command may then be issued. VREFDQ setting should be updated if the die temperature changes too much from the calibration temperature.
The following are typical script when applying the above rules for VREFDQ calibration routine when performing VREFDQ calibration in Range 1:
· MR6[7:6]10 [5:0]XXXXXXX.

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4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration
­ Subsequent legal commands while in VREFDQ calibration mode: ACT, WR, WRA, RD, RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode).
· All subsequent VREFDQ calibration MR setting commands are MR6[7:6]10 [5:0]VVVVVV.
­ "VVVVVV" are desired settings for VREFDQ. · Issue ACT/WR/RD looking for pass/fail to determine VCENT (midpoint) as needed. · To exit VREFDQ calibration, the last two VREFDQ calibration MR commands are:
­ MR6[7:6]10 [5:0]VVVVVV* where VVVVVV* = desired value for V REFDQ. ­ MR6[7]0 [6:0]XXXXXXX to exit VREFDQ calibration mode.
The following are typical script when applying the above rules for VREFDQ calibration routine when performing VREFDQ calibration in Range 2:
· MR6[7:6]11 [5:0]XXXXXXX.
­ Subsequent legal commands while in VREFDQ calibration mode: ACT, WR, WRA, RD, RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode).
· All subsequent VREFDQ calibration MR setting commands are MR6[7:6]11 [5:0]VVVVVV.
­ "VVVVVV" are desired settings for VREFDQ. · Issue ACT/WR/RD looking for pass/fail to determine VCENT (midpoint) as needed. · To exit VREFDQ calibration, the last two VREFDQ calibration MR commands are:
­ MR6[7:6]11 [5:0]VVVVVV* where VVVVVV* = desired value for V REFDQ. ­ MR6[7]0 [6:0]XXXXXXX to exit VREFDQ calibration mode. Note:
Range may only be set or changed when entering VREFDQ calibration mode; changing range while in or exiting VREFDQ calibration mode is illegal.

Figure 69: VREFDQ Training Mode Entry and Exit Timing Diagram

CK_c CK_t
Command

T0

T1

Ta0

Ta1

Tb0

Tb1

Tc0

Tc1

Td0

Td1

Td2

DES

MRS

DES

CMD

DES

CMD

DES

MRS1,2

DES

tVREFDQE

tVREFDQX

VREFDQ training on

New VREFDQ value or write

New VREFDQ value or write

VREFDQ training off

WR

DES

Don't Care

Notes:

1. New VREFDQ values are not allowed with an MRS command during calibration mode entry.
2. Depending on the step size of the latest programmed VREF value, VREF must be satisfied before disabling VREFDQ training mode.

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Figure 70: VREF Step: Single Step Size Increment Case
V REF
Voltage
Step size

4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration

VREF,val_tol

V REF
(VDDQ(DC))

t1

Figure 71: VREF Step: Single Step Size Decrement Case
VREF Voltage
Step size

Time

t1 VREF,val_tol

V REF
(VDDQ(DC))

Time

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Figure 72: VREF Full Step: From VREF,min to VREF,maxCase

V REF
Voltage

VREF,max

Full range step

4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration

V REF,val_tol t1

VREF (V )
DDQ(DC)

VREF,min

Time

Figure 73: VREF Full Step: From VREF,max to VREF,minCase

VREF Voltage

VREF,max

Full range

step

t1

V REF,min

VREF,val_tol
Time

VREF (V )
DDQ(DC)

VREFDQ Target Settings
The VREFDQ initial settings are largely dependant on the ODT termination settings. The table below shows all of the possible initial settings available for VREFDQ training; it is unlikely the lower ODT settings would be used in most cases.

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Table 38: VREFDQ Settings (VDDQ = 1.2V)

RON 34 ohm
48 ohm

ODT 34 ohm 40 ohm 48 ohm 60 ohm 80 ohm 120 ohm 240 ohm 34 ohm 40 ohm 48 ohm 60 ohm 80 ohm 120 ohm 240 ohm

Vx ­ VIN LOW (mV) 600 550 500 435 360 265 150 700 655 600 535 450 345 200

Figure 74: VREFDQ Equivalent Circuit
VDDQ

RON

4Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration

VREFDQ (mv) 900 875 850 815 780 732 675 950 925 900 865 825 770 700
VDDQ
ODT
RXer Vx
VREFDQ (internal)

VREFDQ (%VDDQ) 75% 73% 71% 68% 65% 61% 56% 79% 77% 75% 72% 69% 64% 58%

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4Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode

Connectivity Test Mode
Connectivity test (CT) mode is similar to boundary scan testing but is designed to significantly speed up the testing of electrical continuity of pin interconnections between the device and the memory controller on the PC boards. Designed to work seamlessly with any boundary scan device, CT mode is supported in all ×4, ×8, and ×16 non-3DS devices (JEDEC states CT mode for ×4 and ×8 is not required on 4Gb and is an optional feature on 8Gb and above). 3DS devices do not support CT mode and the TEN pin should be considered RFU maintained LOW at all times.
Contrary to other conventional shift-register-based test modes, where test patterns are shifted in and out of the memory devices serially during each clock, the CT mode allows test patterns to be entered on the test input pins in parallel and the test results to be extracted from the test output pins of the device in parallel. These two functions are also performed at the same time, significantly increasing the speed of the connectivity check. When placed in CT mode, the device appears as an asynchronous device to the external controlling agent. After the input test pattern is applied, the connectivity test results are available for extraction in parallel at the test output pins after a fixed propagation delay time.
Note: A reset of the device is required after exiting CT mode (see RESET and Initialization Procedure).

Pin Mapping

Only digital pins can be tested using the CT mode. For the purposes of a connectivity check, all the pins used for digital logic in the device are classified as one of the following types:
· Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT mode. In CT mode, the normal memory function inside the device is bypassed and the I/O pins appear as a set of test input and output pins to the external controlling agent. Additionally, the device will set the internal VREFDQ to VDDQ × 0.5 during CT mode (this is the only time the DRAM takes direct control over setting the internal VREFDQ). The TEN pin is dedicated to the connectivity check function and will not be used during normal device operation.
· Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the device. When de-asserted, these output pins will be High-Z. The CS_n pin in the device serves as the CS_n pin in CT mode.
· Test input: A group of pins used during normal device operation designated as test input pins. These pins are used to enter the test pattern in CT mode.
· Test output: A group of pins used during normal device operation designated as test output pins. These pins are used for extraction of the connectivity test results in CT mode.
· RESET_n: This pin must be fixed high level during CT mode, as in normal function.

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4Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode

Table 39: Connectivity Mode Pin Description and Switching Levels

CT Mode Pins

Pin Name During Normal Memory Operation

Test enable TEN

Chip select CS_n

Test input

BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14, A CAS_n/A15, RAS_n/A16, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n C ALERT_n

D RESET_n

Test output

DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c

Switching Level CMOS (20%/80% VDD) VREFCA ±200mV VREFCA ±200mV
VREFDQ ±200mV CMOS (20%/80% VDD) CMOS (20%/80% VDD) VTT ±100mV

Notes 1, 2 3 3
4 2, 5
2 6

Notes:

1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW. TEN must be LOW during normal operation.
2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of VDD (960mV for DC HIGH and 240mV for DC LOW.)
3. VREFCA should be VDD/2. 4. VREFDQ should be VDDQ/2. 5. ALERT_n switching level is not a final setting.
6. VTT should be set to VDD/2.

Minimum Terms Definition for Logic Equations
The test input and output pins are related by the following equations, where INV denotes a logical inversion operation and XOR a logical exclusive OR operation:

MT0 = XOR (A1, A6, PAR) MT1 = XOR (A8, ALERT_n, A9) MT2 = XOR (A2, A5, A13) or XOR (A2, A5, A13, A17) MT3 = XOR (A0, A7, A11) MT4 = XOR (CK_c, ODT, CAS_n/A15) MT5 = XOR (CKE, RAS_n/A16, A10/AP) MT6 = XOR (ACT_n, A4, BA1) MT7 = ×16: XOR (DMU_n/DBIU_n , DML_n/DBIL_n, CK_t)
= ×8: XOR (BG1, DML_n/DBIL_n, CK_t) = ×4: XOR (BG1, CK_t) MT8 = XOR (WE_n/A14, A12 / BC, BA0) MT9 = XOR (BG0, A3, RESET_n and TEN)

Logic Equations for a ×4 Device

DQ0 = XOR (MT0, MT1) DQ1 = XOR (MT2, MT3) DQ2 = XOR (MT4, MT5) DQ3 = XOR (MT6, MT7) DQS_t = MT8 DQS_c = MT9

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4Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode

Logic Equations for a ×8 Device

DQ0 = MT0 DQ1 = MT1 DQ2 = MT2 DQ3 = MT3 DQ4 = MT4

DQ5 = MT5 DQ6 = MT6 DQ7 = MT7 DQS_t = MT8 DQS_c = MT9

Logic Equations for a ×16 Device

DQ0 = MT0

DQ10 = INV DQ2

DQ1 = MT1

DQ11 = INV DQ3

DQ2 = MT2

DQ12 = INV DQ4

DQ3 = MT3

DQ13 = INV DQ5

DQ4 = MT4

DQ14 = INV DQ6

DQ5 = MT5

DQ15 = INV DQ7

DQ6 = MT6

LDQS_t = MT8

DQ7 = MT7

LDQS_c = MT9

DQ8 = INV DQ0 UDQS_t = INV LDQS_t

DQ9 = INV DQ1 UDQS_c = INV LDQS_c

CT Input Timing Requirements
Prior to the assertion of the TEN pin, all voltage supplies, including VREFCA, must be valid and stable and RESET_n registered high prior to entering CT mode. Upon the assertion of the TEN pin HIGH with RESET_n, CKE, and CS_n held HIGH; CLK_t, CLK_c, and CKE signals become test inputs within tCTECT_Valid. The remaining CT inputs become valid tCT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, provided inputs were valid for at least tCT_Valid. While in CT mode, refresh activities in the memory arrays are not allowed; they are initiated either externally (auto refresh) or internally (self refresh).
The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM is initialized and VREFDQ is calibrated, CT mode may no longer be used. The TEN pin may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the integrity of the original content of the memory array are unknown. A full reset of the memory device is required.
After CT mode has been entered, the output signals will be stable within tCT_Valid after the test inputs have been applied as long as TEN is maintained HIGH and CS_n is maintained LOW.

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4Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode

Figure 75: Connectivity Test Mode Entry

CK_t CK_c

Ta

Tb

Tc

Td

Valid input

CKE RESET_n
TEN
CS_n CT Inputs

T = 10ns T = 200s

tCKSRX tIS

tCT_IS tCT_IS

T = 500s

tCTCKE_Valid tCT_IS

Valid input

tCT_Enable

tCTCKE_Valid>10ns tCT_IS >0ns

tCT_IS
Valid input tCT_Valid

tCT_Valid

CT Outputs

Valid

Valid input Valid input
Valid input tCT_Valid
Valid Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair
Post Package Repair
Post Package Repair
JEDEC defines two modes of Post Package Repair (PPR): soft Post Package Repair (sPPR) and hard Post Package Repair (hPPR). sPPR is non-persistent so the repair row maybe altered; that is, sPPR is NOT a permanent repair and even though it will repair a row, the repair can be reversed, reassigned via another sPPR, or made permanent via hPPR. Hard Post Package Repair is persistent so once the repair row is assigned for a hPPR address, further PPR commands to a previous hPPR section should not be performed, that is, hPPR is a permanent repair; once repaired, it cannot be reversed. The controller provides the failing row address in the hPPR/sPPR sequence to the device to perform the row repair. hPPR Mode and sPPR Mode may not be enabled at the same time.
JEDEC states hPPR is optional for 4Gb and sPPR is optional for 4Gb and 8Gb parts however Micron 4Gb and 8Gb DDR4 DRAMs should have both sPPR and hPPR support. The hPPR support is identified via an MPR read from MPR Page 2, MPR0[7] and sPPR support is identified via an MPR read from MPR Page 2, MPR0[6].
The JEDEC minimum support requirement for DDR4 PPR (hPPR or sPPR) is to provide one row of repair per bank group (BG), x4/x8 have 4 BG and x16 has 2 BG; this is a total of 4 repair rows available on x4/x8 and 2 repair rows available on x16. Micron PPR support exceeds the JEDEC minimum requirements; Micron DDR4 DRAMs have at least one row of repair for each bank which is essentially 4 row repairs per BG for a total of 16 repair rows for x4 and x8 and 8 repair rows for x16; a 4x increase in repair rows.
JEDEC requires the user to have all sPPR row repair addresses reset and cleared prior to enabling hPPR Mode. Micron DDR4 PPR does not have this restriction, the existing sPPR row repair addresses are not required to be cleared prior to entering hPPR mode. Each bank in a BG is PPR independent: sPPR or hPPR issued to a bank will not alter a sPPR row repair existing in a different bank.
sPPR followed by sPPR to same bank
When PPR is issued to a bank for the first time and is a sPPR command, the repair row will be a sPPR. When a subsequent sPPR is issued to the same bank, the previous sPPR repair row will be cleared and used for the subsequent sPPR address as the sPPR operation is non-persistent.
sPPR followed by hPPR to same bank
When a PPR is issued to a bank for the first time and is a sPPR command, the repair row will be a sPPR. When a subsequent hPPR is issued to the same bank, the initial sPPR repair row will be cleared and used for the hPPR address. If a further subsequent PPR (hPPR or sPPR) is issued to the same bank, the further subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the previous hPPR address as the hPPR operation is persistent.
hPPR followed by hPPR or sPPR to same bank
When a PPR is issued to a bank for the first time and is a hPPR command, the repair row will be a hPPR. When a subsequent PPR (hPPR or sPPR) is issued to the same bank, the subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the initial hPPR address as the initial hPPR is persistent.

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

Hard Post Package Repair
All banks must be precharged and idle. DBI and CRC modes must be disabled. Both sPPR and hPPR must be disabled. sPPR is disabled with MR4[5] = 0. hPPR is disabled with MR4[13] = 0, which is the normal state, and hPPR is enabled with MR4 [13]= 1, which is the hPPR enabled state. There are two forms of hPPR mode. Both forms of hPPR have the same entry requirement as defined in the sections below. The first command sequence uses a WRA command and supports data retention with a REFRESH operation except for the bank containing the row that is being repaired; JEDEC has relaxed this requirement and allows BA[0] to be a don't care regarding the banks which are not required to maintain data a REFRESH operation during hPPR. The second command sequence uses a WR command (a REFRESH operation can't be performed in this command sequence). The second command sequence doesn't support data retention for the target DRAM.
hPPR Row Repair - Entry
As stated above, all banks must be precharged and idle. DBI and CRC modes must be disabled, and all timings must be followed as shown in the timing diagram that follows.
All other commands except those listed in the following sequences are illegal. 1. Issue MR4[13] 1 to enter hPPR mode enable. a. All DQ are driven HIGH. 2. Issue four consecutive guard key commands (shown in the table below) to MR0 with each command separated by tMOD. The PPR guard key settings are the same whether performing sPPR or hPPR mode. a. Any interruption of the key sequence by other commands, such as ACT, WR, RD, PRE, REF, ZQ, and NOP, are not allowed. b. If the guard key bits are not entered in the required order or interrupted with other MR commands, hPPR will not be enabled, and the programming cycle will result in a NOP. c. When the hPPR entry sequence is interrupted and followed by ACT and WR commands, these commands will be conducted as normal DRAM commands. d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a supplier perspective and the user should rely on vendor datasheet.

Table 40: PPR MR0 Guard Key Settings

MR0

BG1:0 BA1:0 A17:12 A11

A10

A9

A8

A7

A6:0

First guard key

0

0

xxxxxx

1

1

0

0

1

1111111

Second guard key

0

0

xxxxxx

0

1

1

1

1

1111111

Third Guard key

0

0

xxxxxx

1

0

1

1

1

1111111

Fourth guard key

0

0

xxxxxx

0

0

1

1

1

1111111

hPPR Row Repair ­ WRA Initiated (REF Commands Allowed) 1. Issue an ACT command with failing BG and BA with the row address to be repaired. 2. Issue a WRA command with BG and BA of failing row address. a. The address must be at valid levels, but the address is "Don't Care." 3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair
a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW. The bank under repair does not get the REFRESH command applied to it.
b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. 1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than 2tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than 2tCK, then hPPR mode execution is unknown.
c. DQS should function normally. 4. REF command may be issued anytime after the WRA command followed by WL +
4nCK + tWR + tRP. a. Multiple REF commands are issued at a rate of tREFI or tREFI/2, however back-to-back REF commands must be separated by at least tREFI/4 when the DRAM is in hPPR mode. b. All banks except the bank under repair will perform refresh.
5. Issue PRE after tPGM time so that the device can repair the target row during tPGM time. a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target row address.
6. Issue MR4[13] 0 command to hPPR mode disable. a. Wait tPGMPST for hPPR mode exit to complete. b. After tPGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be repeated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back.

Figure 76: hPPR WRA ­ Entry

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

Figure 77: hPPR WRA ­ Repair and Exit

CK_c CK_t CMD
BG BA
ADDR CKE
DQS_t DQS_c
DQs1
All Banks Precharged and idle state

Te0
ACT BGf BAf Valid

Tf0

Tg0

Tg1

WRA

DES

DES

BGf

N/A

N/A

BAf

N/A

N/A

Valid

N/A

N/A

WL = CWL+AL+PL

Th0

Th1

DES

DES

N/A

N/A

N/A

N/A

N/A

N/A

4nCK

tRCD hPPR Repair

bit 0 bit 1

bit 6 bit 7 tPGM

hPPR Repair

Tj0

Tj1

DES

REF/DES

N/A

N/A

N/A

N/A

N/A

N/A

tWR +tRP + 1nCK

Tj2
REF/DES N/A N/A N/A

hPPR Repair

Tk0
PRE Valid Valid Valid

Tk1
REF/DES N/A N/A N/A

Tm0
MRSx Valid Valid Valid (A13 = 0)

Tm1
DES N/A N/A N/A

Tn0
Valid Valid Valid Valid

tPGM_Exit hPPR Recognition

tPGMPST hPPR Exit

Normal mode Don't Care

hPPR Row Repair ­ WR Initiated (REF Commands NOT Allowed) 1. Issue an ACT command with failing BG and BA with the row address to be repaired. 2. Issue a WR command with BG and BA of failing row address. a. The address must be at valid levels, but the address is "Don't Care." 3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair. a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW. b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. 1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than 2tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than 2tCK, then hPPR mode execution is unknown. c. DQS should function normally. 4. REF commands may NOT be issued at anytime while in PPT mode. 5. Issue PRE after tPGM time so that the device can repair the target row during tPGM time. a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target row address. 6. Issue MR4[13] 0 command to hPPR mode disable. a. Wait tPGMPST for hPPR mode exit to complete. b. After tPGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be repeated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back.

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

Figure 78: hPPR WR ­ Entry

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7

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1$

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7E

7F

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1$

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7F

7G

7G

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1$

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1$

7H
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Figure 79: hPPR WR ­ Repair and Exit

CK_c CK_t CMD

Te0

Tf0

ACT

WR

Tg0

Tg1

Th0

Th1

DES

DES

DES

DES

Tj0

Tj1

Tj2

Tk0

Tk1

Tm0

Tm1

Tn0

DES

DES

DES

PRE

DES

MRSx

DES

Valid

BG

BGf

BGf

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Valid

N/A

Valid

N/A

Valid

BA

BAf

BAf

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Valid

N/A

Valid

N/A

Valid

ADDR

Valid

Valid

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Valid

N/A

Valid (A13 = 0)

N/A

Valid

CKE

DQS_t DQS_c
DQs1
All Banks Precharged and idle state

WL = CWL + AL + PL

4nCK

tRCD hPPR Repair

bit 0 bit 1

bit 6 bit 7 tPGM

hPPR Repair

hPPR Repair

tPGM_Exit hPPR Recognition

tPGMPST hPPR Exit

Normal mode Don't Care

Table 41: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200

Parameter hPPR programming time
hPPR precharge exit time hPPR exit time

Symbol

tPGM

×4, ×8

×16

tPGM_Exit

tPGMPST

Min 1000 2000
15 50

Max ­ ­ ­ ­

Unit ms ms ns s

sPPR Row Repair

Soft post package repair (sPPR) is a way to quickly, but temporarily, repair a row element in a bank on a DRAM device, where hPPR takes longer but permanently repairs a row element. sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4[5] while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 0, which is the normal state, and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state.

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

sPPR requires the same guard key sequence as hPPR to qualify the MR4 PPR entry. After sPPR entry, an ACT command will capture the target bank and target row, herein seed row, where the row repair will be made. After tRCD time, a WR command is used to select the individual DRAM, through the DQ bits, to transfer the repair address into an internal register in the DRAM. After a write recovery time and PRE command, the sPPR mode can be exited and normal operation can resume.
The DRAM will retain the soft repair information as long as VDD remains within the operating region unless rewritten by a subsequent sPPR entry to the same bank. If DRAM power is removed or the DRAM is reset, the soft repair will revert to the unrepaired state. hPPR and sPPR should not be enabled at the same time; Micron sPPR does not have to be disabled and cleared prior to entering hPPR mode.
With sPPR, Micron DDR4 can repair one row per bank. When a subsequent sPPR request is made to the same bank, the subsequently issued sPPR address will replace the previous sPPR address. When the hPPR resource for a bank is used up, the bank should be assumed to not have available resources for sPPR. If a repair sequence is issued to a bank with no repair resource available, the DRAM will ignore the programming sequence.
The bank receiving sPPR change is expected to retain memory array data in all rows except for the seed row and its associated row addresses. If the data in the memory array in the bank under sPPR repair is not required to be retained, then the handling of the seed row's associated row addresses is not of interest and can be ignored. If the data in the memory array is required to be retained in the bank under sPPR mode, then prior to executing the sPPR mode, the seed row and its associated row addresses should be backed up and subsequently restored after sPPR has been completed. sPPR associated seed row addresses are specified in the Table below; BA0 is not required by Micron DRAMs however it is JEDEC reserved.

Table 42: sPPR Associated Rows

sPPR Associated Row Address

BA0*

A17

A16

A15

A14

A13

A1

A0

All banks must be precharged and idle. DBI and CRC modes must be disabled, and all sPPR timings must be followed as shown in the timing diagram that follows.

All other commands except those listed in the following sequences are illegal. 1. Issue MR4[5] 1 to enter sPPR mode enable. a. All DQ are driven HIGH. 2. Issue four consecutive guard key commands (shown in the table below) to MR0 with each command separated by tMOD. Please note that JEDEC recently added the four guard key entry used for hPPR to sPPR entry; early DRAMs may not require four guard key entry code. A prudent controller design should accommodate either option in case an earlier DRAM is used. a. Any interruption of the key sequence by other commands, such as ACT, WR, RD, PRE, REF, ZQ, and NOP, are not allowed. b. If the guard key bits are not entered in the required order or interrupted with other MR commands, sPPR will not be enabled, and the programming cycle will result in a NOP. c. When the sPPR entry sequence is interrupted and followed by ACT and WR commands, these commands will be conducted as normal DRAM commands.

140

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a supplier perspective and the user should rely on vendor datasheet.

Table 43: PPR MR0 Guard Key Settings

MR0 First guard key Second guard key Third guard key Fourth guard key

BG1:0 BA1:0 A17:12 A11

A10

A9

A8

A7

A6:0

0

0

xxxxxx

1

1

0

0

1

1111111

0

0

xxxxxx

0

1

1

1

1

1111111

0

0

xxxxxx

1

0

1

1

1

1111111

0

0

xxxxxx

0

0

1

1

1

1111111

3. After tMOD, issue an ACT command with failing BG and BA with the row address

to be repaired.

4. After tRCD, issue a WR command with BG and BA of failing row address.

a. The address must be at valid levels, but the address is a "Don't Care."

5. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)

after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair.

a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through

bit 7 are LOW.

b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through

bit 7 is HIGH.

1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH

is driven to all DQs of a DRAM consecutively for equal to or longer than

the first 2tCK, then DRAM does not conduct hPPR and retains data if

REF command is properly issued; if all DQs are neither LOW for 4tCK

nor HIGH for equal to or longer than the first 2tCK, then hPPR mode ex-

ecution is unknown.

c. DQS should function normally.

6. REF command may NOT be issued at anytime while in sPPR mode.

7. Issue PRE after tWR time so that the device can repair the target row during tWR

time.

a. Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired tar-

get row address.

8. Issue MR4[5] 0 command to sPPR mode disable.

a. Wait tPGMPST_s for sPPR mode exit to complete.

b. After tPGMPST_s has expired, any valid command may be issued.

The entire sequence from sPPR mode enable through sPPR mode disable may be repeated if more than one repair is to be done.

After sPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back.

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

Figure 80: sPPR ­ Entry

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7F

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1$

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7F

7G

7G

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1$

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WK .H\

1$

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Figure 81: sPPR ­ Repair, and Exit

Te0

Tf0

CK_c

Tg0

Tg1

CK_t

CMD

ACT

WR

DES

DES

BG

BGf

BA

BAf

BGf

N/A

N/A

BAf

N/A

N/A

ADDR Valid

Valid

N/A

N/A

CKE

DQS_t DQS_c DQs1
All Banks Precharged and idle state

WL = CWL + AL + PL

tRCD sPPR Repair

bit 0 bit 1 sPPR Repair

Th0

Th1

DES

DES

N/A

N/A

N/A

N/A

N/A

N/A

4nCK

bit 6 bit 7 tPGM_s
sPPR Repair

Tj0

Tj1

DES

DES

N/A

N/A

N/A

N/A

N/A

N/A

tWR

Tj2

Tk0

DES

PRE

N/A

Valid

N/A

Valid

N/A

Valid

Tk1
DES N/A N/A N/A

Tm0
MRS4 Valid Valid Valid (A5=0)

Tm1
DES N/A N/A N/A

Tn0
Valid Valid Valid Valid

sPPR Repair

tPGM_Exit_s sPPR Recognition

tPGMPST_s sPPR Exit

Normal Mode Don't Care

Table 44: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200

Parameter sPPR programming time
sPPR precharge exit time sPPR exit time

Symbol tPGM_s
tPGM_Exit_s tPGMPST_s

Min t RCD(MIN)+ WL + 4nCK
+ tWR(MIN)
20 tMOD

hPPR/sPPR Support Identifier

Max ­
­ ­

Table 45: DDR4 Repair Mode Support Identifier

MPR Page 2

A7

A6

A5

A4

A3

A2

A1

UI0

UI1

UI2

UI3

UI4

UI5

UI6

Unit ns ns ns
A0 UI7

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4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair

Table 45: DDR4 Repair Mode Support Identifier (Continued)

MPR0

hPPR1

sPPR2

RTT_WR

Temp sensor

CRC

Notes: 1. 0 = hPPR mode is not available, 1 = hPPR mode is available. 2. 0 = sPPR mode is not available, 1 = sPPR mode is available. 3. Gray shaded areas are for reference only.

RTT_WR

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4Gb: x4, x8, x16 DDR4 SDRAM Excessive Row Activation

Excessive Row Activation
Rows can be accessed a limited number of times within a certain time period before adjacent rows require refresh. The maximum activate count (MAC) is the maximum number of activates that a single row can sustain within a time interval of equal to or less than the maximum activate window (tMAW) before the adjacent rows need to be refreshed, regardless of how the activates are distributed over tMAW.
Micron's DDR4 devices automatically perform a type of TRR mode in the background and provide an MPR Page 3 MPR3[3:0] of 1000, indicating there is no restriction to the number of ACTIVATE commands to a given row in a refresh period provided DRAM tim-ing specifications are not violated. However, specific attempts to by-pass TRR may result in data disturb.

Table 46: MAC Encoding of MPR Page 3 MPR3

[7] [6] [5] [4] [3] [2] [1] [0]

MAC

Comments

x x x x 0 0 0 0 Untested The device has not been tested for MAC.

x x x x 0 0 0 1 tMAC = 700K

x x x x 0 0 1 0 tMAC = 600K

x x x x 0 0 1 1 tMAC = 500K

x x x x 0 1 0 0 tMAC = 400K

x x x x 0 1 0 1 tMAC = 300K

x x x x 0 1 1 0 Reserved

x x x x 0 1 1 1 tMAC = 200K

xxxx1000

Unlimited

There is no restriction to the number of ACTIVATE commands to a given row in a refresh period provided DRAM timing specifications are not violated.

x x x x 1 0 0 1 Reserved

x x x x : : : : Reserved

x x x x 1 1 1 1 Reserved

Note: 1. MAC encoding in MPR Page 3 MPR3.

ACTIVATE Command
The ACTIVATE command is used to open (activate) a row in a particular bank for subsequent access. The values on the BG[1:0] inputs select the bank group, the BA[1:0] inputs select the bank within the bank group, and the address provided on inputs A[17:0] selects the row within the bank. This row remains active (open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Bank-to-bank command timing for ACTIVATE commands uses two different timing parameters, depending on whether the banks are in the same or different bank group. tRRD_S (short) is used for timing between banks located in different bank groups. tRRD_L (long) is used for timing between banks located in the same bank group. Another timing restriction for consecutive ACTIVATE commands [issued at tRRD (MIN)] is tFAW (fifth activate window). Because there is a maximum of four banks in a bank group, the tFAW parameter applies across differ-

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4Gb: x4, x8, x16 DDR4 SDRAM PRECHARGE Command
ent bank groups (five ACTIVATE commands issued at tRRD_L (MIN) to the same bank group would be limited by tRC).

Figure 82: tRRD Timing

CK_c

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK_t

Command

ACT

DES

DES

DES

ACT

DES

DES

DES

DES

DES

ACT

DES

tRRD_S

tRRD_L

Bank

Group BG a

BG b

(BG)

BG b

Bank Bank c

Bank c

Bank d

Address Row n

Row n

Row n

Don't Care

Notes:

1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTIVATE commands to different bank groups (that is, T0 and T4).
2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group (that is, T4 and T10).

Figure 83: tFAW Timing

CK_c

T0

CK_t

Ta0

Tb0

Tc0

Tc1

Tc2

Td0

Td1

Command

ACT

Valid

ACT

Valid

ACT

Valid

ACT

Valid

Valid

Valid

ACT

NOP

Bank Group
(BG)

Valid

tRRD

Valid

tRRD

Valid

tRRD

Valid

tFAW

Valid

Bank

Valid

Valid

Valid

Valid

Valid

Address

Valid

Valid

Valid

Valid

Valid

Note: 1. tFAW; four activate windows.

Don't Care

Time Break

PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation for a specified time (tRP) after the PRECHARGE command is issued. An exception to this is the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters.
After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank.

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4Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command
The auto precharge feature is engaged when a READ or WRITE command is issued with A10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay the PRECHARGE operation until the ARRAY RESTORE operation has completed. The RAS lockout circuit feature allows the PRECHARGE operation to be partially or completely hidden during burst READ cycles when the auto precharge feature is engaged. The PRECHARGE operation will not begin until after the last data of the burst write sequence is properly stored in the memory array.
REFRESH Command
The REFRESH command (REF) is used during normal operation of the device. This command is nonpersistent, so it must be issued each time a refresh is required. The device requires REFRESH cycles at an average periodic interval of tREFI. When CS_n, RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH command can be applied. The refresh addressing is generated by the internal DRAM refresh controller. This makes the address bits "Don't Care" during a REFRESH command. An internal address counter supplies the addresses during the REFRESH cycle. No control of the external address bus is required once this cycle has started. When the REFRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle time tRFC (MIN), as shown in Figure 84 (page 147).
Note: The tRFC timing parameter depends on memory density.
In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing and pullingin the REFRESH command. A limited number REFRESH commands can be postponed depending on refresh mode: a maximum of 8 REFRESH commands can be postponed when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH commands can be postponed when the device is in 4X refresh mode.
When 8 consecutive REFRESH commands are postponed, the resulting maximum interval between the surrounding REFRESH commands is limited to 9 × tREFI (see Figure 85 (page 147)). For both the 2X and 4X refresh modes, the maximum interval between surrounding REFRESH commands allowed is limited to 17 × tREFI2 and 33 × tREFI4, respectively.
A limited number REFRESH commands can be pulled-in as well. A maximum of 8 additional REFRESH commands can be issued in advance or "pulled-in" in 1X refresh mode, a maximum of 16 additional REFRESH commands can be issued when in advance in 2X refresh mode, and a maximum of 32 additional REFRESH commands can be issued in advance when in 4X refresh mode. Each of these REFRESH commands reduces the number of regular REFRESH commands required later by one. Note that pulling in more than the maximum allowed REFRESH commands in advance does not further reduce the number of regular REFRESH commands required later, so that the resulting maximum interval between two surrounding REFRESH commands is limited to 9 × tREFI (Figure 86 (page 147)), 17 × tRFEI2, or 33 × tREFI4. At any given time, a maximum of 16 additional REF commands can be issued within 2 × tREFI, 32 additional REF2 com-

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4Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command
mands can be issued within 4 × tREFI2, and 64 additional REF4 commands can be issued within 8 × tREFI4 (larger densities are limited by tRFC1, tRFC2, and tRFC4, respectively, which must still be met).

Figure 84: REFRESH Command Timing

T0 CK_c CK_t

Command

REF

T1

DES

DES

tRFC

DRAM must be idle

Ta0 REF

Ta1

DES

DES

tRFC (MIN)

Tb0

Tb1

Tb2

Valid

Valid

Valid

tREFI (MAX 9 × tREFI)

Tb3 Valid

Tc0

Tc1

Tc2

Tc3

Valid

REF

Valid

Valid

Valid

DRAM must be idle

Time Break

Don't Care

Notes:

1. Only DES commands are allowed after a REFRESH command is registered until tRFC (MIN) expires.
2. Time interval between two REFRESH commands may be extended to a maximum of 9 × tREFI.

Figure 85: Postponing REFRESH Commands (Example)

9 × tREFI

tREFI

W
tRFC

Figure 86: Pulling In REFRESH Commands (Example)
tREFI
tRFC

8 REF-Commands postponed
9 × tREFI
W

8 REF-Commands pulled-in

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4Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode

Temperature-Controlled Refresh Mode
During normal operation, temperature-controlled refresh (TCR) mode disabled, the device must have a REFRESH command issued once every tREFI, except for what is allowed by posting (see REFRESH Command section). This means a REFRESH command must be issued once every 3.9s if TC is greater than 85°C, and once every 7.8s if TC is less than or equal to 85°C, regardless of which Temperature Mode is selected (MR4[2]). TCR mode is disabled by setting MR4[3] = 0 while TCR mode is enabled by setting MR4[3] = 1. When TCR mode is enabled (MR4[3] = 1), the Temperature Mode must be selected where MR4[2] = 0 enables the Normal Temperature Mode while MR4[2] = 1 enables the Extended Temperature Mode.
When TCR mode is enabled, the device will register the externally supplied REFRESH command and adjust the internal refresh period to be longer than tREFI of the normal temperature range, when allowed, by skipping REFRESH commands with the proper gear ratio. TCR mode has two Temperature Modes to select between the normal temperature range and the extended temperature range; the correct Temperature Mode must be selected so the internal control operates correctly. The DRAM must have the correct refresh rate applied externally; the internal refresh rate is determined by the DRAM based upon the temperature.
Normal Temperature Mode
REFRESH commands should be issued to the device with the refresh period equal to tREFI of normal temperature range (-40°C to 85°C). The system must guarantee that the TC does not exceed 85°C. The device may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ratio when TC is below 85°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control.
Extended Temperature Mode
REFRESH commands should be issued to the device with the refresh period equal to tREFI of extended temperature range (85°C to 105°C) . The system must guarantee that the TC does not exceed 105°C. Even though the external refresh supports the extended temperature range, the device may adjust its internal refresh period to be equal to or longer than tREFI of the normal temperature range (-40°C to 85°C) by skipping external REFRESH commands with the proper gear ratio when TC is equal to or below 85°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control.

Table 47: Normal tREFI Refresh (TCR Enabled)

Temperature TC  85°C
85°C < TC  95°C

Normal Temperature Mode

External Refresh Period

Internal Refresh Period

7.8s

7.8s

N/A

Extended Temperature Mode

External Refresh Period

Internal Refresh Period

3.9s1

7.8s 3.9s

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4Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode

Table 47: Normal tREFI Refresh (TCR Enabled) (Continued)

Temperature 95°C < TC  105°C

Normal Temperature Mode

External Refresh Period

Internal Refresh Period

N/A

Extended Temperature Mode

External Refresh Period

Internal Refresh Period

1.95s

1.95s

Note: 1. If the external refresh period is slower than 3.9s, the device will refresh internally at too slow of a refresh rate and will violate refresh specifications.

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4Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode

Figure 87: TCR Mode Example1

Controller

External tREFI
3.9s

REFRESH REFRESH

85°C  TC  95°C

Internal tREFI
3.9s

REFRESH REFRESH

Internal tREFI 7.8s

TC  85°C REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

REFRESH

Controller issues REFRESH commands at extended
temperature rate

External REFRESH commands are not
ignored

At least every other external REFRESH ignored

Note: 1. TCR enabled with Extended Temperature Mode selected.

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4Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode

Fine Granularity Refresh Mode
Mode Register and Command Truth Table
The REFRESH cycle time (tRFC) and the average refresh interval (tREFI) can be programmed by the MRS command. The appropriate setting in the mode register will set a single set of REFRESH cycle times and average refresh interval for the device (fixed mode), or allow the dynamic selection of one of two sets of REFRESH cycle times and average refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be enabled by MRS before any OTF REFRESH command can be issued.

Table 48: MRS Definition

MR3[8] 0 0 0 0 1 1 1 1

MR3[7] 0 0 1 1 0 0 1 1

MR3[6] 0 1 0 1 0 1 0 1

Refresh Rate Mode Normal mode (fixed 1x) Fixed 2x Fixed 4x Reserved Reserved On-the-fly 1x/2x On-the-fly 1x/4x Reserved

There are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by programming the appropriate values into the mode register MR3 [8:6]. When either of the two OTF modes is selected, the device evaluates the BG0 bit when a REFRESH command is issued, and depending on the status of BG0, it dynamically switches its internal refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the corresponding REFRESH operation.

Table 49: REFRESH Command Truth Table

Refresh Fixed rate OTF: 1x OTF: 2x OTF: 4x

CS_n L L L L

ACT_n H H H H

RAS_n/A CAS_n/A

15

14

L

L

L

L

L

L

L

L

WE_n/ A13 H H H H

BG1 V V V V

BG0 V L H H

A10/ AP V V V V

A[9:0], A[12:11], A[20:16]
V V V V

MR3[8:6 ]
0vv 1vv 101 110

tREFI and tRFC Parameters
The default refresh rate mode is fixed 1x mode where REFRESH commands should be issued with the normal rate; that is, tREFI1 = tREFI(base) (for TC  85°C), and the duration of each REFRESH command is the normal REFRESH cycle time (tRFC1). In 2x mode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to the device at the double frequency (tREFI2 = tREFI(base)/2) of the normal refresh rate. In 4x mode, the REFRESH command rate should be quadrupled (tREFI4 = tREFI(base)/4). Per

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4Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode

each mode and command type, the tRFC parameter has different values as defined in the following table.
For discussion purposes, the REFRESH command that should be issued at the normal refresh rate and has the normal REFRESH cycle duration may be referred to as an REF1x command. The REFRESH command that should be issued at the double frequency (tREFI2 = tREFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESH command that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) may be referred to as a REF4x command.
In the fixed 1x refresh rate mode, only REF1x commands are permitted. In the fixed 2x refresh rate mode, only REF2x commands are permitted. In the fixed 4x refresh rate mode, only REF4x commands are permitted. When the on-the-fly 1x/2x refresh rate mode is enabled, both REF1x and REF2x commands are permitted. When the OTF 1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permitted.

Table 50: tREFI and tRFC Parameters

Refresh Mode 1x mode
2x mode
4x mode

Parameter tREFI (base) tREFI1
tRFC1 tREFI2
tRFC2 tREFI4
tRFC4

-40°C  TC  85°C 85°C  TC  95°C 95°C  TC  105°C
-40°C  TC  85°C 85°C  TC  95°C 95°C  TC  105°C
-40°C  TC  85°C 85°C  TC  95°C 95°C  TC  105°C

2Gb

4Gb

8Gb

16Gb

7.8

7.8

7.8

7.8

tREFI(base) tREFI(base) tREFI(base) tREFI(base)

tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 tREFI(base)/2

tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4

160

260

350

350

tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 tREFI(base)/2

tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4

tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8

110

160

260

260

tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4

tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8

tREFI(base)/16 tREFI(base)/16 tREFI(base)/16 tREFI(base)/16

90

110

160

160

Units s s s s ns s s s ns s s s ns

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Figure 88: 4Gb with Fine Granularity Refresh Mode Example

Normal Temperature Operation ­ -40°C to 85°C

1x Mode (-40°C to 85°C)
REF@260ns

2x Mode (-40°C to 85°C)
REF@160ns

4x Mode (-40°C to 85°C)
REF@110ns

t REFI = 3.9s

REF@110ns

t REFI = 7.8s

REF@160ns

t REFI = 3.9s

REF@110ns REF@110ns

REF@260ns

REF@160ns

t REFI = 7.8s

REF@160ns

t REFI = 3.9s

REF@110ns REF@110ns

t REFI = 3.9s

REF@110ns REF@110ns

REF@260ns

REF@160ns

REF@110ns

t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s

1x Mode (-40°C to 105°C)
REF@260ns
REF@260ns
REF@260ns
REF@260ns
REF@260ns

Extended Temperature Operation ­ -40°C to 105°C

2x Mode (-40°C to 105°C)
REF@160ns

t REFI = 3.9s

REF@160ns

t REFI = 3.9s

REF@160ns REF@160ns

REF@160ns

t REFI = 3.9s

REF@160ns

REF@160ns

t REFI = 3.9s

REF@160ns

REF@160ns

t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s t REFI = 1.95s

4x Mode (-40°C to 105°C)
REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns

t t t t t t t t t t t t t t t t

REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI REFI

= = = = = = = = = = = = = = = =

0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s 0.975s

4Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode

4Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode
Changing Refresh Rate
If the refresh rate is changed by either MRS or OTF. New tREFI and tRFC parameters will be applied from the moment of the rate change. When the REF1x command is issued to the DRAM, tREF1 and tRFC1 are applied from the time that the command was issued; when the REF2x command is issued, tREF2 and tRFC2 should be satisfied.

Figure 89: OTF REFRESH Command Timing

CK_c

CK_t

Command

DES

REF1

DES

DES

DES

Valid

Valid

REF2

DES

DES

Valid

DES

REF2

DES

tRFC1 (MIN)

tRFC2 (MIN)

tREFI1

tREFI2

Don't Care

The following conditions must be satisfied before the refresh rate can be changed. Otherwise, data retention cannot be guaranteed.
· In the fixed 2x refresh rate mode or the OTF 1x/2x refresh mode, an even number of REF2x commands must be issued because the last change of the refresh rate mode with an MRS command before the refresh rate can be changed by another MRS command.
· In the OTF1x/2x refresh rate mode, an even number of REF2x commands must be issued between any two REF1x commands.
· In the fixed 4x refresh rate mode or the OTF 1x/4x refresh mode, a multiple-of-four number of REF4x commands must be issued because the last change of the refresh rate with an MRS command before the refresh rate can be changed by another MRS command.
· In the OTF1x/4x refresh rate mode, a multiple-of-four number of REF4x commands must be issued between any two REF1x commands.
There are no special restrictions for the fixed 1x refresh rate mode. Switching between fixed and OTF modes keeping the same rate is not regarded as a refresh rate change.

Usage with TCR Mode
If the temperature controlled refresh mode is enabled, only the normal mode (fixed 1x mode, MR3[8:6] = 000) is allowed. If any other refresh mode than the normal mode is selected, the temperature controlled refresh mode must be disabled.

Self Refresh Entry and Exit
The device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any restriction on the number of REFRESH commands that have been issued during the mode before the self refresh entry. However, upon self refresh exit, extra REFRESH command(s) may be required, depending on the condition of the self refresh entry.
The conditions and requirements for the extra REFRESH command(s) are defined as follows:
· In the fixed 2x refresh rate mode or the enable-OTF 1x/2x refresh rate mode, it is recommended there be an even number of REF2x commands before entry into self refresh after the last self refresh exit, REF1x command, or MRS command that set the

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4Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode
refresh mode. If this condition is met, no additional REFRESH commands are required upon self refresh exit. In the case that this condition is not met, either one extra REF1x command or two extra REF2x commands must be issued upon self refresh exit. These extra REFRESH commands are not counted toward the computation of the average refresh interval (tREFI). · In the fixed 4x refresh rate mode or the enable-OTF 1x/4x refresh rate mode, it is recommended there be a multiple-of-four number of REF4x commands before entry into self refresh after the last self refresh exit, REF1x command, or MRS command that set the refresh mode. If this condition is met, no additional refresh commands are required upon self refresh exit. When this condition is not met, either one extra REF1x command or four extra REF4x commands must be issued upon self refresh exit. These extra REFRESH commands are not counted toward the computation of the average refresh interval (tREFI).
There are no special restrictions on the fixed 1x refresh rate mode.
This section does not change the requirement regarding postponed REFRESH commands. The requirement for the additional REFRESH command(s) described above is independent of the requirement for the postponed REFRESH commands.

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4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the device, even if the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is defined by having CS_n, RAS_n, CAS_n, and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock.
Before issuing the SELF REFRESH ENTRY command, the device must be idle with all banks in the precharge state and tRP satisfied. Idle state is defined as: All banks are closed (tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on). After the SELF REFRESH ENTRY command is registered, CKE must be held LOW to keep the device in self refresh mode. The DRAM automatically disables ODT termination, regardless of the ODT pin, when it enters self refresh mode and automatically enables ODT upon exiting self refresh. During normal operation (DLL_on), the DLL is automatically disabled upon entering self refresh and is automatically enabled (including a DLL reset) upon exiting self refresh.
When the device has entered self refresh mode, all of the external control signals, except CKE and RESET_n, are "Don't Care." For proper SELF REFRESH operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VPP, and VREFCA) must be at valid levels. The DRAM internal VREFDQ generator circuitry may remain on or be turned off depending on the MR6 bit 7 setting. If the internal VREFDQ circuit is on in self refresh, the first WRITE operation or first write-leveling activity may occur after tXS time after self refresh exit. If the DRAM internal VREFDQ circuitry is turned off in self refresh, it ensures that the VREFDQ generator circuitry is powered up and stable within the tXSDLL period when the DRAM exits the self refresh state. The first WRITE operation or first write-leveling activity may not occur earlier than tXSDLL after exiting self refresh. The device initiates a minimum of one REFRESH command internally within the tCKE period once it enters self refresh mode.
The clock is internally disabled during a SELF REFRESH operation to save power. The minimum time that the device must remain in self refresh mode is tCKESR/ tCKESR_PAR. The user may change the external clock frequency or halt the external clock tCKSRE/tCKSRE_PAR after self refresh entry is registered; however, the clock must be restarted and tCKSRX must be stable before the device can exit SELF REFRESH operation.
The procedure for exiting self refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT command (SRX, combination of CKE going HIGH and DESELECT on the command bus) is registered, the following timing delay must be satisfied:
Commands that do not require locked DLL:
· tXS = ACT, PRE, PREA, REF, SRE, and PDE. · tXS_FAST = ZQCL, ZQCS, and MRS commands. For an MRS command, only DRAM
CL, WR/RTP register, and DLL reset in MR0; RTT(NOM) register in MR1; the CWL and RTT(WR) registers in MR2; and gear-down mode register in MR3; WRITE and READ preamble registers in MR4; RTT(PARK) register in MR5; tCCD_L/tDLLK and VREFDQ calibration value registers in MR6 may be accessed provided the DRAM is not in per-DRAM mode. Access to other DRAM mode registers must satisfy tXS timing. WRITE commands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT and dynamic ODT controlled by the WRITE command require a locked DLL.

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4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation
Commands that require locked DLL in the normal operating range:
· tXSDLL ­ RD, RDS4, RDS8, RDA, RDAS4, and RDAS8 (unlike DDR3, WR, WRS4, WRS8, WRA, WRAS4, and WRAS8 because synchronous ODT is required).
Depending on the system environment and the amount of time spent in self refresh, ZQ CALIBRATION commands may be required to compensate for the voltage and temperature drift described in the ZQ CALIBRATION Commands section. To issue ZQ CALIBRATION commands, applicable timing requirements must be satisfied (see the ZQ Calibration Timing figure).
CKE must remain HIGH for the entire self refresh exit period tXSDLL for proper operation except for self refresh re-entry. Upon exit from self refresh, the device can be put back into self refresh mode or power-down mode after waiting at least tXS period and issuing one REFRESH command (refresh period of tRFC). The DESELECT command must be registered on each positive clock edge during the self refresh exit interval tXS. ODT must be turned off during tXSDLL.
The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from self refresh mode. Upon exit from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode.

Figure 90: Self Refresh Entry/Exit Timing

T0

T1

Ta0

Tb0

Tc0

CK_c

CK_t

tCKSRE/tCKSRE_PAR

tIS

tCPDED

CKE

tCKESR/tCKESR_PAR

ODT

Command

DES

SRE

DES

Td0

Td1

tCKSRX

Te0

Tf0

Tg0

Valid

Valid

Valid

tXS_FAST

SRX

Valid1

Valid2

Valid Valid3

ADDR tRP

Valid tXS tXSDLL

Valid

Valid

Enter Self Refresh

Exit Self Refresh

Don't Care

Time Break

Notes:

1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL commands are allowed.
2. Valid commands not requiring a locked DLL. 3. Valid commands requiring a locked DLL.

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4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation

Figure 91: Self Refresh Entry/Exit Timing with CAL Mode
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W&.65(
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'(6

65(

'(6

'(6

7D 7D 7D 7D 7D 7E 7E 7E
W&.65;

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1RWH

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9DOLG

W &$/

W&3'('

W;6B)$67

9DOLG
W &$/

'RQ¶W&DUH

Notes:

1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE/tCKSRE_PAR = 8nCK, tCKSRX = 8nCK, tXS_FAST = tREFC4 (MIN) + 10ns.
2. CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't Care," WE_n/A14 = "Don't Care."
3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or ZQCL commands are allowed.
4. The figure only displays tXS_FAST timing, but tCAL must also be added to any tXS and tXSDLL associated commands during CAL mode.

Self Refresh Abort
The exit timing from self refresh exit to the first valid command not requiring a locked DLL is tXS. The value of tXS is (tRFC+ 10ns). This delay allows any refreshes started by the device time to complete. tRFC continues to grow with higher density devices, so tXS will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled, the controller uses tXS timings (location MR4, bit 9). If the bit is enabled, the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command not requiring a locked DLL after a delay of tXS_ABORT. Upon exit from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same irrespective of the setting of the MRS bit for self refresh abort.

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4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation

Figure 92: Self Refresh Abort

T0

T1

Ta0

Tb0

Tc0

CK_c

CK_t

tCKSRE/tCKSRE_PAR

tIS

tCPDED

CKE

tCKESR/tCKESR_PAR

Td0

Td1

tCKSRX

Te0

Tf0

Tg0

Valid

Valid

Valid

ODT

Command

DES

SRE

DES

tXS_FAST

SRX

Valid1

Valid2

Valid Valid3

ADDR tRP

Valid

Valid

tXS_ABORT tXSDLL

Valid

Enter Self Refresh

Exit Self Refresh

Don't Care

Time Break

Notes:

1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL commands are allowed.
2. Valid commands not requiring a locked DLL with self refresh abort mode enabled in the mode register.
3. Valid commands requiring a locked DLL.

Self Refresh Exit with NOP Command
Exiting self refresh mode using the NO OPERATION command (NOP) is allowed under a specific system application. This special use of NOP allows for a common command/ address bus between active DRAM devices and DRAM(s) in maximum power saving mode. Self refresh mode may exit with NOP commands provided:
· The device entered self refresh mode with CA parity, CAL, and gear-down disabled. · tMPX_S and tMPX_LH are satisfied. · NOP commands are only issued during tMPX_LH window.
No other command is allowed during the tMPX_LH window after an SELF REFRESH EXIT (SRX) command is issued.

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4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation

Figure 93: Self Refresh Exit with NOP Command

7D 7D 7D 7D 7E 7E 7E 7E 7F 7F 7F 7F 7F 7G 7G 7G 7G 7H 7H &.BF

&.BW

W &.65;

&.(

2'7
&6BQ &RPPDQG
$''5

9DOLG

W03;B6

W03;B/+

1RWH

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65; 123 123 123 123 '(6 '(6 '(6 '(6 '(6 9DOLG '(6 9DOLG

9DOLG 9DOLG 9DOLG 9DOLG 9DOLG
W ;6 W;6 W;6'//

9DOLG

9DOLG

'RQ¶W&DUH

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW (along with a DESELECT command). CKE is not allowed to go LOW when the following operations are in progress: MRS command, MPR operations, ZQCAL operations, DLL locking, or READ/ WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the power-down IDD specification will not be applied until those operations are complete. The timing diagrams that follow illustrate power-down entry and exit.
For the fastest power-down exit timing, the DLL should be in a locked state when power-down is entered. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper READ operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well as proper DLL operation with any CKE intensive operations as long as the controller complies with DRAM specifications.
During power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after inprogress commands are completed, the device will be in active power-down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CKE, and RESET_n. In power-down mode, DRAM ODT input buffer deactivation is based on Mode Register 5, bit 5 (MR5[5]). If it is configured to 0b, the ODT input buffer remains on and the ODT input signal must be at valid logic level. If it is configured to 1b, the ODT input buffer is deactivated and the DRAM ODT input signal may be floating and the device does not provide RTT(NOM) termination. Note that the device continues to provide RTT(Park) termination if it is enabled in MR5[8:6]. To protect internal delay on the CKE line to block the input signals, multiple DES commands are needed during the CKE switch off and on cycle(s); this timing period is defined as tCPDED. CKE LOW will result in deactivation of command and address receivers after tCPDED has expired.

Table 51: Power-Down Entry Definitions

DRAM Status

DLL

Active

On

(a bank or more open)

Precharged

On

(all banks precharged)

Power-

Down Exit Relevant Parameters

Fast

tXP to any valid command.

Fast

tXP to any valid command.

The DLL is kept enabled during precharge power-down or active power-down. In pow-
er-down mode, CKE is LOW, RESET_n is HIGH, and a stable clock signal must be main-
tained at the inputs of the device. ODT should be in a valid state, but all other input sig-
nals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out of power-down mode and in the reset state.) CKE LOW must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 × tREFI.

The power-down state is synchronously exited when CKE is registered HIGH (along with DES command). CKE HIGH must be maintained until tCKE has been satisfied. The
ODT input signal must be at a valid level when the device exits from power-down mode,
independent of MR1 bit [10:8] if RTT(NOM) is enabled in the mode register. If RTT(NOM) is disabled, the ODT input signal may remain floating. A valid, executable command can

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode
be applied with power-down exit latency, tXP, after CKE goes HIGH. Power-down exit latency is defined in the AC Specifications table.

Figure 94: Active Power-Down Entry and Exit

T0

T1

T2

Ta0

Ta1

CK_c

CK_t

Command

Valid

CKE tIH

DES tIS

DES tPD tIH

DES tIS

ODT (ODT buffer enabled - MR5[5] = 0)2

Tb0 DES tCKE

Tb1 DES Valid

Tc0 Valid Valid

ODT (ODT buffer disabled - MR5[5] = 1)3

Refer to ODT Power-Down Entry/Exit with ODT Buffer Disable Mode figures

Address

Valid

tCPDED

Valid tXP

Enter power-down
mode

Exit power-down
mode

Time Break

Don't Care

Notes:

1. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after completion of the PRECHARGE command.
2. ODT pin driven to a valid state; MR5[5] = 0 (normal setting).
3. ODT pin drive/float timing requirements for the ODT input buffer disable option (for additional power savings during active power-down) is described in the section for ODT Input Buffer Disable Mode for Power-Down (page 169); MR5[5] = 1.

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Figure 95: Power-Down Entry After Read and Read with Auto Precharge

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

CK_c

CK_t

Command

RD or RDA

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tIS tCPDED

CKE

Tb0

Tb1

DES

Valid

Valid

Address Valid
DQS_t, DQS_c DQ BL8 DQ BC4

RL = AL + CL

Valid tPD

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7 DI DI DI DI n n+1 n+2 n+3 tRDPDEN

Power-Down entry

Transitioning Data

Time Break

Don't Care

Note: 1. DI n (or b) = data-in from column n (or b).

Figure 96: Power-Down Entry After Write and Write with Auto Precharge

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

CKE

Address

Bank, Col n

A10

DQS_t, DQS_c DQ BL8 DQ BC4

WL = AL + CWL

WR

DI

DI

DI

DI

DI

DI

DI

DI

b

b+1 b+2 b+3 b+4 b+5 b+6 b+7

Start internal

precharge

DI

DI

DI

DI

n

n+1 n+2 n+3

tWRAPDEN

Tb1

Tb2

Tc0

DES

DES

DES

tIS

tCPDED

tPD

Power-Down entry
Transitioning Data 7LPH%UHDN

Tc1 Valid Valid Valid
'RQ¶W&DUH

Notes: 1. DI n (or b) = data-in from column n (or b). 2. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after completion of the PRECHARGE command.

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Figure 97: Power-Down Entry After Write

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Command

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

CKE

Address

Bank, Col n

A10

DQS_t, DQS_c DQ BL8 DQ BC4

WL = AL + CWL

DI

DI

DI

DI

DI

DI

DI

DI

b

b+1 b+2 b+3 b+4 b+5 b+6 b+7

DI

DI

DI

DI

n

n+1 n+2 n+3

tWRPDEN

Note: 1. DI n (or b) = data-in from column n (or b).

Tb0

Tb1

Tb2

Tc0

Tc1

DES

DES

DES

DES

Valid

tIS

tCPDED

Valid

Valid

tWR

tPD

Power-Down entry
Transitioning Data Time Break

Don't Care

Figure 98: Precharge Power-Down Entry and Exit

T0 CK_c CK_t Command
CKE

T1

T2

Ta0

Ta1

Tb0

Tb1

Tc0

DES

DES

tCPDED tIS

tPD

DES tIH

DES tIS

DES tCKE
tXP

DES Valid

Valid Valid

Enter power-down
mode

Exit power-down
mode

Time Break

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Figure 99: REFRESH Command to Power-Down Entry

T0

T1

T2

Ta0

CK_c

CK_t

Command

REF

DES

DES

Address CKE

Valid tIS

tCPDED tPD

tREFPDEN

Tb0

Tb1

DES

DES

tCKE Valid

Time Break

Don't Care

Figure 100: Active Command to Power-Down Entry

T0

T1

T2

Ta0

CK_c

CK_t

Command

ACT

DES

DES

Address CKE

Valid

tCPDED

tIS

tPD

tACTPDEN

Tb0

Tb1

DES

DES

tCKE Valid

Time Break

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Figure 101: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry

T0 CK_c CK_t Command Address
CKE

T1

T2

Ta0

Tb0

Tb1

PRE or PREA

DES

DES

DES

Valid tIS

tCPDED tPD

Valid tCKE

tPREPDEN

Time Break

Don't Care

Figure 102: MRS Command to Power-Down Entry

T0

T1

Ta0

Ta1

Tb0

Tb1

CK_c

CK_t

Command

MRS

DES

DES

DES

DES

Address

Valid

CKE

tCPDED

tIS

tPD

tCKE

tMRSPDEN

Valid

Time Break

Don't Care

Power-Down Clarifications ­ Case 1
When CKE is registered LOW for power-down entry, tPD (MIN) must be satisfied before CKE can be registered HIGH for power-down exit. The minimum value of parameter tPD (MIN) is equal to the minimum value of parameter tCKE (MIN) as shown in the Timing Parameters by Speed Bin table. A detailed example of Case 1 follows.

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Figure 103: Power-Down Entry/Exit Clarifications ­ Case 1

T0

T1

T2

Ta0

Ta1

Tb0

Tb1

Tb2

CK_c

CK_t

Command

Valid

CKE tIH
Address

DES tIS

DES

DES

tPD

tIH

tIS
Valid tCPDED

DES tCKE

DES tIS

DES tPD

tCPDED

Enter power-down
mode

Exit power-down
mode

Enter power-down
mode
Time Break

Don't Care

Power-Down Entry, Exit Timing with CAL
Command/Address latency is used and additional timing restrictions are required when entering power-down, as noted in the following figures.

Figure 104: Active Power-Down Entry and Exit Timing with CAL

7

7

7D

7D

7D

7E

7E

7F

7F

&.BF

&.BW

&6BQ

7G

7G

7H

&RPPDQG

'(6

'(6

9DOLG

'(6

'(6

'(6

'(6

'(6

'(6

'(6

9DOLG

$GGUHVV &.(

W&$/

9DOLG
W,+ W,6

W&3'(' W3'

W;3

W,+

W,6

W&$/

9DOLG

7LPH%UHDN

'RQ¶W&DUH

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4Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode

Figure 105: REFRESH Command to Power-Down Entry with CAL

7

7

7D

7E

7E

7F

7F

7G

7G

&.BF

&.BW

&6BQ

&RPPDQG

'(6

'(6

5()

'(6

'(6

'(6

'(6

'(6

$GGUHVV

9DOLG

&.(

W&$/

W5()3'(1
W,6 W,+

W &3'(' W3'

W;3

W,+

W,6

7H

7H

7I

'(6

'(6

W&$/

9DOLG 9DOLG

7LPH%UHDN

'RQ¶W&DUH

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4Gb: x4, x8, x16 DDR4 SDRAM ODT Input Buffer Disable Mode for Power-Down
ODT Input Buffer Disable Mode for Power-Down
DRAM does not provide RTT_NOM termination during power-down when ODT input buffer deactivation mode is enabled in MR5 bit A5.
To account for DRAM internal delay on CKE line to disable the ODT buffer and block the sampled output, the host controller must continuously drive ODT to either low or high when entering power down (from tDODTLoff+1 prior to CKE low till tCPDED after CKE low). The ODT signal is allowed to float after tCPDEDmin has expired. In this mode, RTT_NOM termination corresponding to sampled ODT at the input when CKE is registered low (and tANPD before that) may be either RTT_NOM or RTT_PARK. tANPD is equal to (WL-1) and is counted backwards from PDE.
Figure 106: ODT Power-Down Entry with ODT Buffer Disable Mode
diff_CK

CKE
ODT
DRAM_RTT_sync (DLL enabled)
CA parity disabled
DRAM_RTT_async (DLL disabled)

tDODTLoff +1

tCPDED (MIN)

RTT(NOM) DODTLoff

Floating
tADC (MIN) RTT(Park)
tCPDED (MIN) + tADC (MAX)

RTT(NOM)

tAONAS (MIN) tCPDED (MIN) + tAOFAS (MAX)

RTT(Park)

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4Gb: x4, x8, x16 DDR4 SDRAM ODT Input Buffer Disable Mode for Power-Down

Figure 107: ODT Power-Down Exit with ODT Buffer Disable Mode
diff_CK

CKE

ODT_A (DLL enabled)

Floating

DRAM_RTT_A

ODT_B (DLL disabled)

Floating

DRAM_RTT_B

tXP RTT(Park)

DODTLon

tXP RTT(Park)
tAONAS (MIN)

tAOFAS (MAX)

tADC (MAX) tADC (MIN)

RTT(NOM)

RTT(NOM)

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

CRC Write Data Feature

CRC Write Data

The CRC write data feature takes the CRC generated data from the DRAM controller and compares it to the internally CRC generated data and determines whether the two match (no CRC error) or do not match (CRC error).

Figure 108: CRC Write Data Operation

DRAM Controller Data

DRAM Data

CRC engine

Data

CRC Code

CRC engine

CRC Code

CRC Code

Compare CRC

WRITE CRC DATA Operation
A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms the write data frames, as shown in the following CRC data mapping tables for the x4, x8, and x16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the remaining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input data bits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n is used (1s are sent when not used). A x16 device has two identical CRC trees each, one for the lower byte and one for the upper byte, with 64 input data bits used by each, and the remaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s are sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller must send 1s in transfer 9 location whether or not DM_n/DBI_n is used.
The DRAM checks for an error in a received code word D[71:0] by comparing the received checksum against the computed checksum and reports errors using the ALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM core without waiting for the CRC check for full writes when DM is disabled. If bad data is written to the DRAM core, the DRAM memory controller will try to overwrite the bad data with good data; this means the DRAM controller is responsible for data coherency when DM is disabled. However, in the case where both CRC and DM are enabled via

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

MRS (that is, persistent mode), the DRAM will not write bad data to the core when a CRC error is detected.

DBI_n and CRC Both Enabled
The DRAM computes the CRC for received written data D[71:0]. Data is not inverted back based on DBI before it is used for computing CRC. The data is inverted back based on DBI before it is written to the DRAM core.

DM_n and CRC Both Enabled
When both DM and write CRC are enabled in the DRAM mode register, the DRAM calculates CRC before sending the write data into the array. If there is a CRC error, the DRAM blocks the WRITE operation and discards the data. The Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group and the WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different BankGroup figures in the WRITE Operation section show timing differences when DM is enabled.

DM_n and DBI_n Conflict During Writes with CRC Enabled
Both write DBI_n and DM_n can not be enabled at the same time; read DBI_n and DM_n can be enabled at the same time.

CRC and Write Preamble Restrictions
When write CRC is enabled:
· And 1tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 4 clocks is not allowed.
· And 2tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 6 clocks is not allowed.

CRC Simultaneous Operation Restrictions
When write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed.

CRC Polynomial

The CRC polynomial used by DDR4 is the ATM-8 HEC, X8 + X2 + X1 + 1.
A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data includes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees.
The CRC polynomial and combinatorial logic used by DDR4 is the same as used on GDDR5.
The error coverage from the DDR4 polynomial used is shown in the following table.

Table 52: CRC Error Detection Coverage
Error Type Random single-bit errors Random double-bit errors

Detection Capability 100% 100%

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

Table 52: CRC Error Detection Coverage (Continued)

Error Type Random odd count errors Random multibit UI vertical column error detection excluding DBI bits

Detection Capability 100% 100%

CRC Combinatorial Logic Equations

module CRC8_D72; // polynomial: (0 1 2 8) // data width: 72 // convention: the first serial data bit is D[71] //initial condition all 0 implied // "^" = XOR function [7:0] nextCRC8_D72; input [71:0] Data; input [71:0] D; reg [7:0] CRC; begin D = Data;
CRC[0] = D[69]^D[68]^D[67]^D[66]^D[64]^D[63]^D[60]^D[56]^D[54]^D[53]^D[52]^D[50]^D[49 ]^D[48]^D[45]^D[43]^D[40]^D[39]^D[35]^D[34]^D[31]^D[30]^D[28]^D[23]^D[21]^D[1 9]^D[18]^D[16]^D[14]^D[12]^D[8]^D[7]^D[6]^D[0];
CRC[1] = D[70]^D[66]^D[65]^D[63]^D[61]^D[60]^D[57]^D[56]^D[55]^D[52]^D[51]^D[48]^D[46 ]^D[45]^D[44]^D[43]^D[41]^D[39]^D[36]^D[34]^D[32]^D[30]^D[29]^D[28]^D[24]^D[2 3]^D[22]^D[21]^D[20]^D[18]^D[17]^D[16]^D[15]^D[14]^D[13]^D[12]^D[9]^D[6]^D[1 ]^D[0];
CRC[2] = D[71]^D[69]^D[68]^D[63]^D[62]^D[61]^D[60]^D[58]^D[57]^D[54]^D[50]^D[48]^D[47 ]^D[46]^D[44]^D[43]^D[42]^D[39]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[2 2]^D[17]^D[15]^D[13]^D[12]^D[10]^D[8]^D[6]^D[2]^D[1]^D[0];
CRC[3] = D[70]^D[69]^D[64]^D[63]^D[62]^D[61]^D[59]^D[58]^D[55]^D[51]^D[49]^D[48]^D[47 ]^D[45]^D[44]^D[43]^D[40]^D[38]^D[35]^D[34]^D[30]^D[29]^D[26]^D[25]^D[23]^D[1 8]^D[16]^D[14]^D[13]^D[11]^D[9]^D[7]^D[3]^D[2]^D[1];
CRC[4] = D[71]^D[70]^D[65]^D[64]^D[63]^D[62]^D[60]^D[59]^D[56]^D[52]^D[50]^D[49]^D[48 ]^D[46]^D[45]^D[44]^D[41]^D[39]^D[36]^D[35]^D[31]^D[30]^D[27]^D[26]^D[24]^D[1 9]^D[17]^D[15]^D[14]^D[12]^D[10]^D[8]^D[4]^D[3]^D[2];
CRC[5] = D[71]^D[66]^D[65]^D[64]^D[63]^D[61]^D[60]^D[57]^D[53]^D[51]^D[50]^D[49]^D[47 ]^D[46]^D[45]^D[42]^D[40]^D[37]^D[36]^D[32]^D[31]^D[28]^D[27]^D[25]^D[20]^D[1 8]^D[16]^D[15]^D[13]^D[11]^D[9]^D[5]^D[4]^D[3];

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature
CRC[6] = D[67]^D[66]^D[65]^D[64]^D[62]^D[61]^D[58]^D[54]^D[52]^D[51]^D[50]^D[48]^D[47 ]^D[46]^D[43]^D[41]^D[38]^D[37]^D[33]^D[32]^D[29]^D[28]^D[26]^D[21]^D[19]^D[1 7]^D[16]^D[14]^D[12]^D[10]^D[6]^D[5]^D[4];
CRC[7] = D[68]^D[67]^D[66]^D[65]^D[63]^D[62]^D[59]^D[55]^D[53]^D[52]^D[51]^D[49]^D[48 ]^D[47]^D[44]^D[42]^D[39]^D[38]^D[34]^D[33]^D[30]^D[29]^D[27]^D[22]^D[20]^D[1 8]^D[17]^D[15]^D[13]^D[11]^D[7]^D[6]^D[5];
nextCRC8_D72 = CRC;
Burst Ordering for BL8
DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 (fixed).
CRC Data Bit Mapping

Table 53: CRC Data Mapping for x4 Devices, BL8

Func-

Transfer

tion

0

1

2

3

4

5

6

DQ0 D0

D1

D2

D3

D4

D5

D6

DQ1 D8

D9 D10 D11 D12 D13 D14

DQ2 D16 D17 D18 D19 D20 D21 D22

DQ3 D24 D25 D26 D27 D28 D29 D30

7

8

9

D7 CRC0 CRC4

D15 CRC1 CRC5

D23 CRC2 CRC6

D31 CRC3 CRC7

Table 54: CRC Data Mapping for x8 Devices, BL8

Func-

Transfer

tion

0

1

2

3

4

5

6

7

8

9

DQ0 D0

D1

D2

D3

D4

D5

D6

D7 CRC0 1

DQ1 D8

D9 D10 D11 D12 D13 D14 D15 CRC1 1

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1

DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1

DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1

DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1

DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1

DM_n/ D64 D65 D66 D67 D68 D69 D70 D71

1

1

DBI_n

A x16 device is treated as two x8 devices; a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72].

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

Table 55: CRC Data Mapping for x16 Devices, BL8

Func-

Transfer

tion

0

1

2

3

4

5

6

7

8

9

DQ0 D0

D1

D2

D3

D4

D5

D6

D7 CRC0 1

DQ1 D8

D9 D10 D11 D12 D13 D14 D15 CRC1 1

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1

DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1

DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1

DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1

DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1

LDM_n/ D64 D65 D66 D67 D68 D69 D70 D71

1

1

LDBI_n

DQ8 D72 D73 D74 D75 D76 D77 D78 D79 CRC8 1

DQ9 D80 D81 D82 D83 D84 D85 D86 D87 CRC9 1

DQ10 D88 D89 D90 D91 D92 D93 D94 D95 CRC10 1

DQ11 D96 D97 D98 D99 D100 D101 D102 D103 CRC11 1

DQ12 D104 D105 D106 D107 D108 D109 D110 D111 CRC12 1

DQ13 D112 D113 D114 D115 D116 D117 D118 D119 CRC13 1

DQ14 D120 D121 D122 D123 D124 D125 D126 D127 CRC14 1

DQ15 D128 D129 D130 D131 D132 D133 D134 D135 CRC15 1

UDM_n/ D136 D137 D138 D139 D140 D141 D142 D143 1

1

UDBI_n

CRC Enabled With BC4
If CRC and BC4 are both enabled, then address bit A2 is used to transfer critical data first for BC4 writes.

CRC with BC4 Data Bit Mapping
For a x4 device, the CRC tree inputs are 16 data bits, and the inputs for the remaining bits are 1.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to D[11:8], and so forth, for the CRC tree.

Table 56: CRC Data Mapping for x4 Devices, BC4

Transfer

Function

0

1

2

3

4

5

6

7

8

9

A2 = 0

DQ0

D0

D1

D2

D3

1

1

1

1

CRC0 CRC4

DQ1

D8

D9

D10

D11

1

1

1

1

CRC1 CRC5

DQ2

D16

D17

D18

D19

1

1

1

1

CRC2 CRC6

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

Table 56: CRC Data Mapping for x4 Devices, BC4 (Continued)

Function DQ3
DQ0 DQ1 DQ2 DQ3

Transfer

0

1

2

3

4

5

6

7

8

9

D24

D25

D26

D27

1

1

1

1

CRC3 CRC7

A2 = 1

D4

D5

D6

D7

1

1

1

1

CRC0 CRC4

D12

D13

D14

D15

1

1

1

1

CRC1 CRC5

D20

D21

D22

D23

1

1

1

1

CRC2 CRC6

D28

D29

D30

D31

1

1

1

1

CRC3 CRC7

For a x8 device, the CRC tree inputs are 36 data bits.

When A2 = 0, the input bits D[67:64]) are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[67:64]) are 1.

When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to D[11:8], and so forth, for the CRC tree. The input bits D[71:68]) are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68]) are 1.

Table 57: CRC Data Mapping for x8 Devices, BC4

Function
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM_n/DBI_n
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM_n/DBI_n

Transfer

0

1

2

3

4

5

6

7

8

9

A2 = 0

D0

D1

D2

D3

1

1

1

1

CRC0

1

D8

D9

D10

D11

1

1

1

1

CRC1

1

D16

D17

D18

D19

1

1

1

1

CRC2

1

D24

D25

D26

D27

1

1

1

1

CRC3

1

D32

D33

D34

D35

1

1

1

1

CRC4

1

D40

D41

D42

D43

1

1

1

1

CRC5

1

D48

D49

D50

D51

1

1

1

1

CRC6

1

D56

D57

D58

D59

1

1

1

1

CRC7

1

D64

D65

D66

D67

1

1

1

1

1

1

A2 = 1

D4

D5

D6

D7

1

1

1

1

CRC0

1

D12

D13

D14

D15

1

1

1

1

CRC1

1

D20

D21

D22

D23

1

1

1

1

CRC2

1

D28

D29

D30

D31

1

1

1

1

CRC3

1

D36

D37

D38

D39

1

1

1

1

CRC4

1

D44

D45

D46

D47

1

1

1

1

CRC5

1

D52

D53

D54

D55

1

1

1

1

CRC6

1

D60

D61

D62

D63

1

1

1

1

CRC7

1

D68

D69

D70

D71

1

1

1

1

1

1

There are two identical CRC trees for x16 devices, each have CRC tree inputs of 36 bits.

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

When A2 = 0, input bits D[67:64] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[67:64] are 1s. The input bits D[139:136] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[139:136] are 1s.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs for D[11:8], and so forth, for the CRC tree. Input bits D[71:68] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68] are 1s. The input bits D[143:140] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[143:140] are 1s.

Table 58: CRC Data Mapping for x16 Devices, BC4

Transfer

Function

0

1

2

3

4

5

6

7

8

9

A2 = 0

DQ0

D0

D1

D2

D3

1

1

1

1

CRC0

1

DQ1

D8

D9

D10

D11

1

1

1

1

CRC1

1

DQ2

D16

D17

D18

D19

1

1

1

1

CRC2

1

DQ3

D24

D25

D26

D27

1

1

1

1

CRC3

1

DQ4

D32

D33

D34

D35

1

1

1

1

CRC4

1

DQ5

D40

D41

D42

D43

1

1

1

1

CRC5

1

DQ6

D48

D49

D50

D51

1

1

1

1

CRC6

1

DQ7

D56

D57

D58

D59

1

1

1

1

CRC7

1

LDM_n/LDBI_n D64

D65

D66

D67

1

1

1

1

1

1

DQ8

D72

D73

D74

D75

1

1

1

1

CRC8

1

DQ9

D80

D81

D82

D83

1

1

1

1

CRC9

1

DQ10

D88

D89

D90

D91

1

1

1

1

CRC10

1

DQ11

D96

D97

D98

D99

1

1

1

1

CRC11

1

DQ12

D104 D105 D106 D107

1

1

1

1

CRC12

1

DQ13

D112 D113 D114 D115

1

1

1

1

CRC13

1

DQ14

D120 D121 D122 D123

1

1

1

1

CRC14

1

DQ15

D128 D129 D130 D131

1

1

1

1

CRC15

1

UDM_n/UDBI_n D136 D137 D138 D139

1

1

1

1

1

1

A2 = 1

DQ0

D4

D5

D6

D7

1

1

1

1

CRC0

1

DQ1

D12

D13

D14

D15

1

1

1

1

CRC1

1

DQ2

D20

D21

D22

D23

1

1

1

1

CRC2

1

DQ3

D28

D29

D30

D31

1

1

1

1

CRC3

1

DQ4

D36

D37

D38

D39

1

1

1

1

CRC4

1

DQ5

D44

D45

D46

D47

1

1

1

1

CRC5

1

DQ6

D52

D53

D54

D55

1

1

1

1

CRC6

1

DQ7

D60

D61

D62

D63

1

1

1

1

CRC7

1

LDM_n/LDBI_n D68

D69

D70

D71

1

1

1

1

1

1

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

Table 58: CRC Data Mapping for x16 Devices, BC4 (Continued)

Transfer

Function

0

1

2

3

4

5

6

7

8

9

DQ8

D76

D77

D78

D79

1

1

1

1

CRC8

1

DQ9

D84

D85

D86

D87

1

1

1

1

CRC9

1

DQ10

D92

D93

D94

D95

1

1

1

1

CRC10

1

DQ11

D100 D101 D102 D103

1

1

1

1

CRC11

1

DQ12

D108 D109 D110 D111

1

1

1

1

CRC12

1

DQ13

D116 D117 D118 D119

1

1

1

1

CRC13

1

DQ14

D124 D125 D126 D127

1

1

1

1

CRC14

1

DQ15

D132 D133 D134 D135

1

1

1

1

CRC15

1

UDM_n/UDBI_n D140 D141 D142 D143

1

1

1

1

1

1

CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1
The following example is of a CRC tree when x8 is used in BC4 mode (x4 and x16 CRC trees have similar differences).

CRC[0], A2=0 = 1^1^D[67]^D[66]^D[64]^1^1^D[56]^1^1^1^D[50]^D[49]^D[48]^1^D[43]^D[40]^1^D[3 5]^D[34]^1^1^1^1^1^D[19]^D[18]^D[16]^1^1^D[8] ^1^1^ D[0] ; CRC[0], A2=1 = 1^1^D[71]^D[70]^D[68]^1^1^D[60]^1^1^1^D[54]^D[53]^D[52]^1^D[47]^D[44]^1^D[3 9]^D[38]^1^1^1^1^1^D[23]^D[22]^D[20]^1^1^D[12]^1^1^D[4] ;

CRC[1], A2=0 = 1^D[66]^D[65]^1^1^1^D[57]^D[56]^1^1^D[51]^D[48]^1^1^1^D[43]^D[41]^1^1^D[34 ]^D[32]^1^1^1^D[24]^1^1^1^1^D[18]^D[17]^D[16]^1^1^1^1^D[9] ^1^ D[1]^D[0]; CRC[1], A2=1 = 1^D[70]^D[69]^1^1^1^D[61]^D[60]^1^1^D[55]^D[52]^1^1^1^D[47]^D[45]^1^1^D[38 ]^D[36]^1^1^1^D[28]^1^1^1^1^D[22]^D[21]^D[20]^1^1^1^1^D[13]^1^D[5]^D[4];

CRC[2], A2=0 = 1^1^1^1^1^1^1^D[58]^D[57]^1^D[50]^D[48]^1^1^1^D[43]^D[42]^1^1^D[34]^D[33]^1 ^1^D[25]^D[24]^1^D[17]^1^1^1^D[10]^D[8] ^1^D[2]^D[1]^D[0]; CRC[2], A2=1 = 1^1^1^1^1^1^1^D[62]^D[61]^1^D[54]^D[52]^1^1^1^D[47]^D[46]^1^1^D[38]^D[37]^1 ^1^D[29]^D[28]^1^D[21]^1^1^1^D[14]^D12]^1^D[6]^D[5]^D[4];

CRC[3], A2=0 = 1^1^D[64]^1^1^1^D[59]^D[58]^1^D[51]^D[49]^D[48]^1^1^1^D[43]^D[40]^1^D[35]^ D[34]^1^1^D[26]^D[25]^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^D[3]^D[2]^D[1]; CRC[3], A2=1 = 1^1^D[68]^1^1^1^D[63]^D[62]^1^D[55]^D[53]^D[52]^1^1^1^D[47]^D[44]^1^D[39]^ D[38]^1^1^D[30]^D[29]^1^D[22]^D[20]^1^1^D[15]^D[13]^1^D[7]^D[6]^D[5];

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature
CRC[4], A2=0 = 1^1^D[65]^D[64]^1^1^1^D[59]^D[56]^1^D[50]^D[49]^D[48]^1^1^1^D[41]^1^1^D[35 ]^1^1^D[27]^D[26]^D[24]^D[19]^D[17]^1^1^1^D[10]^D[8] ^1^D[3]^D[2]; CRC[4], A2=1 = 1^1^D[69]^D[68]^1^1^1^D[63]^D[60]^1^D[54]^D[53]^D[52]^1^1^1^D[45]^1^1^D[39 ]^1^1^D[31]^D[30]^D[28]^D[23]^D[21]^1^1^1^D[14]^D[12]^1^D[7]^D[6];
CRC[5], A2=0 = 1^D[66]^D[65]^D[64]^1^1^1^D[57]^1^D[51]^D[50]^D[49]^1^1^1^D[42]^D[40]^1^1^ D[32]^1^1^D[27]^D[25]^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^1^D[3]; CRC[5], A2=1 = 1^D[70]^D[69]^D[68]^1^1^1^D[61]^1^D[55]^D[54]^D[53]^1^1^1^D[46]^D[44]^1^1^ D[36]^1^1^D[31]^D[29]^1^D[22]^D[20]^1^1^D[15]^D[13]^1^1^D[7];
CRC[6], A2=0 = D[67]^D[66]^D[65]^D[64]^1^1^D[58]^1^1^D[51]^D[50]^D[48]^1^1^D[43]^D[41]^1^1 ^D[33]^D[32]^1^1^D[26]^1^D[19]^D[17]^D[16]^1^1^D[10]^1^1^1; CRC[6], A2=1 = D[71]^D[70]^D[69]^D[68]^1^1^D[62]^1^1^D[55]^D[54]^D[52]^1^1^D[47]^D[45]^1^1 ^D[37]^D[36]^1^1^D[30]^1^D[23]^D[21]^D[20]^1^1^D[14]^1^1^1;
CRC[7], A2=0 = 1^D[67]^D[66]^D[65]^1^1^D[59]^1^1^1^D[51]^D[49]^D[48]^1^1^D[42]^1^1^D[34]^ D[33]^1^1^D[27]^1^1^D[18]^D[17]^1^1^D[11]^1^1^1; CRC[7], A2=1 = 1^D[71]^D[70]^D[69]^1^1^D[63]^1^1^1^D[55]^D[53]^D[52]^1^1^D[46]^1^1^D[38]^ D[37]^1^1^D[31]^1^1^D[22]^D[21]^1^1^D[15]^1^1^1;
CRC Error Handling
The CRC error mechanism shares the same ALERT_n signal as CA parity for reporting write errors to the DRAM. The controller has two ways to distinguish between CRC errors and CA parity errors: 1) Read DRAM mode/MPR registers, and 2) Measure time ALERT_n is LOW. To speed up recovery for CRC errors, CRC errors are only sent back as a "short" pulse; the maximum pulse width is roughly ten clocks (unlike CA parity where ALERT_n is LOW longer than 45 clocks). The ALERT_n LOW could be longer than the maximum limit at the controller if there are multiple CRC errors as the ALERT_n signals are connected by a daisy chain bus. The latency to ALERT_n signal is defined as tCRC_ALERT in the following figure.
The DRAM will set the error status bit located at MR5[3] to a 1 upon detecting a CRC error, which will subsequently set the CRC error status flag in the MPR error log HIGH (MPR Page1, MPR3[7]). The CRC error status bit (and CRC error status flag) remains set at 1 until the DRAM controller clears the CRC error status bit using an MRS command to set MR5[3] to a 0. The DRAM controller, upon seeing an error as a pulse width, will retry the write transactions. The controller should consider the worst-case delay for ALERT_n (during initialization) and backup the transactions accordingly. The DRAM controller may also be made more intelligent and correlate the write CRC error to a specific rank or a transaction.

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4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

Figure 109: CRC Error Reporting

CK_c

T0

T1

T2

T3

T4

T5

T6

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

CK_t

DQIN ALERT_n

Dx Dx+1 Dx+2 Dx+3 Dx+4 Dx+5 Dx+6 Dx+7 CRCy 1

tCRC_ALERT

CRC ALERT_PW (MAX) CRC ALERT_PW (MIN)

Transition Data

Don't Care

Notes:

1. D[71:1] CRC computed by DRAM did not match CRC[7:0] at T5 and started error generating process at T6.
2. CRC ALERT_PW is specified from the point where the DRAM starts to drive the signal LOW to the point where the DRAM driver releases and the controller starts to pull the signal up.
3. Timing diagram applies to x4, x8, and x16 devices.

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CRC Write Data Flow Diagram
Figure 110: CA Parity Flow Diagram

DRAM write process start
Capture data

MR2 12 enable CRC MR5 3 set CRC error clear to 0 MR5 10 enable/disable DM MR3[10:9] WCL if DM enabled

CRC

Yes

enabled

No
Transfer Data Internally

Yes CA error
No

Persistent Yes mode
enabled
No
Transfer data internally

DRAM CRC same as No
controller CRC Yes
Transfer data internally

DRAM CRC same as
controller CRC
Yes

No
ALERT_n LOW 6 to 10 CKs

ALERT_n HIGH

MR5[3] = 0 Yes at WRITE

No
MR5[A3] and PAGE1 MPR3[7] remain set to 1

Set error flag MR5[A3] 1
Set error status PAGE1 MPR3[7] 1

ALERT_n LOW 6 to 10 CKs
ALERT_n HIGH

MR5[3] = 0 Yes at WRITE

No
MR5[A3] and PAGE1 MPR3[7] remain set to 1

Set error flag MR5[A3] 1
Set error status PAGE1 MPR3[7] 1

181

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WRITE burst completed

WRITE burst completed

WRITE burst completed

WRITE burst completed
Bad data written MR5 3 reset to 0 if desired

WRITE burst completed

WRITE burst rejected
Bad data not written MR5 3 reset to 0 if desired

4Gb: x4, x8, x16 DDR4 SDRAM Data Bus Inversion

Data Bus Inversion
The DATA BUS INVERSION (DBI) function is supported only for x8 and x16 configurations (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given DQS strobe edge. The DBI function shares a common pin with the DATA MASK (DM) and TDQS functions. The DBI function applies to either or both READ and WRITE operations: Write DBI cannot be enabled at the same time the DM function is enabled, and DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM, and DBI functions are shown below.

Table 59: DBI vs. DM vs. TDQS Function Matrix

Read DBI Enabled (or Disabled)
MR5[12]=1 (or MR5[12] = 0)
Disabled MR5[12] = 0

Write DBI
Disabled MR5[11] = 0
Enabled MR5[11] = 1
Disabled MR5[11] = 0
Disabled MR5[11] = 0

Data Mask (DM)
Disabled MR5[10] = 0
Disabled MR5[10] = 0
Enabled MR5[10] = 1
Disabled MR5[10] = 0

TDQS (x8 only)
Disabled MR1[11] = 0
Disabled MR1[11] = 0
Disabled MR1[11] = 0
Enabled MR1[11] = 1

DBI During a WRITE Operation
If DBI_n is sampled LOW on a given byte lane during a WRITE operation, the DRAM inverts write data received on the DQ inputs prior to writing the internal memory array. If DBI_n is sampled HIGH on a given byte lane, the DRAM leaves the data received on the DQ inputs noninverted. The write DQ frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the DBI function).

Table 60: DBI Write, DQ Frame Format (x8)

Function DQ[7:0] DM_n or DBI_n

0 Byte 0 DM0 or DBI0

1 Byte 1 DM1 or DBI1

2 Byte 2 DM2 or DBI2

Transfer

3

4

Byte 3

Byte 4

DM3 or DBI3

DM4 or DBI4

5 Byte 5 DM5 or DBI5

6 Byte 6 DM6 or DBI6

7 Byte 7 DM7 or DBI7

Table 61: DBI Write, DQ Frame Format (x16)

Function DQ[7:0] LDM_n or LDBI_n DQ[15:8]

0 LByte 0 LDM0 or LDBI0 UByte 0

1 LByte 1 LDM1 or LDBI1 UByte 1

Transfer, Lower (L) and Upper(U)

2

3

4

5

LByte 2

LByte 3

LByte 4

LByte 5

LDM2 or LDBI2

LDM3 or LDBI3

LDM4 or LDBI4

LDM5 or LDBI5

UByte 2

UByte 3

UByte 4

UByte 5

6 LByte 6 LDM6 or LDBI6 UByte 6

7 LByte 7 LDM7 or LDBI7 UByte 7

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4Gb: x4, x8, x16 DDR4 SDRAM Data Bus Inversion

Table 61: DBI Write, DQ Frame Format (x16) (Continued)

Function
UDM_n or UDBI_n

0
UDM0 or UDBI0

1
UDM1 or UDBI1

Transfer, Lower (L) and Upper(U)

2

3

4

5

UDM2 or UDBI2

UDM3 or UDBI3

UDM4 or UDBI4

UDM5 or UDBI5

6
UDM6 or UDBI6

7
UDM7 or UDBI7

DBI During a READ Operation
If the number of 0 data bits within a given byte lane is greater than four during a READ operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin HIGH. The read DQ frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the DBI function).

Table 62: DBI Read, DQ Frame Format (x8)

Function DQ[7:0] DBI_n

0 Byte 0 DBI0

1 Byte 1 DBI1

2 Byte 2 DBI2

Transfer Byte

3

4

Byte 3

Byte 4

DBI3

DBI4

5 Byte 5 DBI5

6 Byte 6 DBI6

7 Byte 7 DBI7

Table 63: DBI Read, DQ Frame Format (x16)

Function DQ[7:0] LDBI_n DQ[15:8] UDBI_n

0 LByte 0 LDBI0 UByte 0 UDBI0

1 LByte 1 LDBI1 UByte 1 UDBI1

Transfer Byte, Lower (L) and Upper(U)

2

3

4

5

LByte 2

LByte 3

LByte 4

LByte 5

LDBI2

LDBI3

LDBI4

LDBI5

UByte 2

UByte 3

UByte 4

UByte 5

UDBI2

UDBI3

UDBI4

UDBI5

6 LByte 6 LDBI6 UByte 6 UDBI6

7 LByte 7 LDBI7 UByte 7 UDBI7

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4Gb: x4, x8, x16 DDR4 SDRAM Data Mask

Data Mask

The DATA MASK (DM) function, also described as PARTIAL WRITE, is supported only for x8 and x16 configurations (it is not supported on x4 devices). The DM function shares a common pin with the DBI_n and TDQS functions. The DM function applies only to WRITE operations and cannot be enabled at the same time the WRITE DBI function is enabled. The valid configurations for the TDQS, DM, and DBI functions are shown here.

Table 64: DM vs. TDQS vs. DBI Function Matrix

Data Mask (DM) Enabled
MR5[10] = 1
Disabled MR5[10] = 0

TDQS (x8 only) Disabled
MR1[11] = 0
Enabled MR1[11] = 1
Disabled MR1[11] = 0
Disabled MR1[11] = 0

Write DBI Disabled MR5[11] = 0
Disabled MR5[11] = 0
Enabled MR5[11] = 1
Disabled MR5[11] = 0

Read DBI
Enabled or Disabled MR5[12] = 1 or MR5[12] = 0
Disabled MR5[12] = 0
Enabled or Disabled MR5[12] = 1 or MR5[12] = 0
Enabled (or Disabled) MR5[12] = 1 (or MR5[12] = 0)

When enabled, the DM function applies during a WRITE operation. If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core. The DQ frame format for x8 and x16 configurations is shown below. If both CRC write and DM are enabled (via MRS), the CRC will be checked and valid prior to the DRAM writing data into the DRAM core. If a CRC error occurs while the DM feature is enabled, CRC write persistent mode will be enabled and data will not be written into the DRAM core. In the case of CRC write enabled and DM disabled (via MRS), that is, CRC write nonpersistent mode, data is written to the DRAM core even if a CRC error occurs.

Table 65: Data Mask, DQ Frame Format (x8)

Function DQ[7:0] DM_n or DBI_n

0 Byte 0 DM0 or DBI0

1 Byte 1 DM1 or DBI1

2 Byte 2 DM2 or DBI2

Transfer

3

4

Byte 3

Byte 4

DM3 or DBI3

DM4 or DBI4

5 Byte 5 DM5 or DBI5

6 Byte 6 DM6 or DBI6

7 Byte 7 DM7 or DBI7

Table 66: Data Mask, DQ Frame Format (x16)

Function DQ[7:0]

0 LByte 0

1 LByte 1

Transfer, Lower (L) and Upper (U)

2

3

4

5

LByte 2

LByte 3

LByte 4

LByte 5

6 LByte 6

7 LByte 7

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4Gb: x4, x8, x16 DDR4 SDRAM Data Mask

Table 66: Data Mask, DQ Frame Format (x16) (Continued)

Function LDM_n or
LDBI_n DQ[15:8] UDM_n or UDBI_n

0 LDM0 or
LDBI0 UByte 0 UDM0 or UDBI0

1 LDM1 or
LDBI1 UByte 1 UDM1 or UDBI1

Transfer, Lower (L) and Upper (U)

2

3

4

5

LDM2 or LDBI2

LDM3 or LDBI3

LDM4 or LDBI4

LDM5 or LDBI5

UByte 2

UByte 3

UByte 4

UByte 5

UDM2 or UDBI2

UDM3 or UDBI3

UDM4 or UDBI4

UDM5 or UDBI5

6 LDM6 or
LDBI6 UByte 6 UDM6 or UDBI6

7 LDM7 or
LDBI7 UByte 7 UDM7 or UDBI7

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4Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles
Programmable Preamble Modes and DQS Postambles
The device supports programmable WRITE and READ preamble modes, either the normal 1tCK preamble mode or special 2tCK preamble mode. The 2tCK preamble mode places special timing constraints on many operational features as well as being supported for data rates of DDR4-2400 and faster. The WRITE preamble 1tCK or 2tCK mode can be selected independently from READ preamble 1tCK or 2tCK mode.
READ preamble training is also supported; this mode can be used by the DRAM controller to train or "read level" the DQS receivers.
There are tCCD restrictions under some circumstances:
· When 2tCK READ preamble mode is enabled, a tCCD_S or tCCD_L of 5 clocks is not allowed.
· When 2tCK WRITE preamble mode is enabled and write CRC is not enabled, a tCCD_S or tCCD_L of 5 clocks is not allowed.
· When 2tCK WRITE preamble mode is enabled and write CRC is enabled, a tCCD_S or tCCD_L of 6 clocks is not allowed.
WRITE Preamble Mode
MR4[12] = 0 selects 1tCK WRITE preamble mode while MR4[12] = 1 selects 2tCK WRITE preamble mode. Examples are shown in the figures below.

Figure 111: 1tCK vs. 2tCK WRITE Preamble Mode

1tCK Mode

WR
CK_c CK_t
DQS_t, DQS_c

WL Preamble

DQ
2tCK Mode
WR
CK_c CK_t
DQS_t, DQS_c

D0 D1 D2 D3 D4 D5 D6 D7
WL Preamble

DQ

D0 D1 D2 D3 D4 D5 D6 D7

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4Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles
CWL has special considerations when in the 2tCK WRITE preamble mode. The CWL value selected in MR2[5:3], as seen in table below, requires at least one additional clock when the primary CWL value and 2tCK WRITE preamble mode are used; no additional clocks are required when the alternate CWL value and 2tCK WRITE preamble mode are used.

Table 67: CWL Selection

Speed Bin DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

CWL - Primary Choice

1tCK Preamble

2tCK Preamble

9

N/A

10

N/A

11

N/A

12

14

14

16

16

18

16

18

CWL - Alternate Choice

1tCK Preamble

2tCK Preamble

11

N/A

12

N/A

14

N/A

16

16

18

18

20

20

20

20

Note: 1. CWL programmable requirement for MR2[5:3].
When operating in 2tCK WRITE preamble mode, tWTR (command based) and tWR (MR0[11:9]) must be programmed to a value 1 clock greater than the tWTR and tWR setting normally required for the applicable speed bin to be JEDEC compliant; however, Micron's DDR4 DRAMs do not require these additional tWTR and tWR clocks. The CAS_n-to-CAS_n command delay to either a different bank group (tCCD_S) or the same bank group (tCCD_L) have minimum timing requirements that must be satisfied between WRITE commands and are stated in the Timing Parameters by Speed Bin tables.

Figure 112: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4

1tCK Mode

CMD WRITE

WRITE

CK_c

CK_t

tCCD = 4

WL

DQS_t, DQS_c

Preamble

DQ
2tCK Mode

CMD
CK_c CK_t

WRITE

DQS_t, DQS_c

tCCD = 4

WRITE Preamble

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 WL

DQ

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1

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4Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles

Figure 113: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5

1tCK Mode

CMD WRITE

WRITE

CK_c CK_t

tCCD = 5

WL

DQS_t, DQS_c

Preamble

DQ

D0 D1 D2 D3 D4 D5 D6 D7

Preamble D0 D1 D2 D3

2tCK Mode: tCCD = 5 is not allowed in 2tCK mode. Note: 1. tCCD_S and tCCD_L = 5 tCKs is not allowed when in 2tCK WRITE preamble mode.

Figure 114: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6

1tCK Mode

CMD WRITE

WRITE

CK_c

CK_t

tCCD = 6

WL

DQS_t, DQS_c

Preamble

DQ

D0 D1 D2 D3 D4 D5 D6 D7

2tCK Mode

CMD WRITE

WRITE

CK_c CK_t

tCCD = 6

WL

DQS_t, DQS_c

Preamble

DQ

D0 D1 D2 D3 D4 D5 D6 D7

Preamble D0 D1 D2 D3

Preamble

D0 D1 D2 D3

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4Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles
READ Preamble Mode
MR4[11] = 0 selects 1tCK READ preamble mode and MR4[11] = 1 selects 2tCK READ preamble mode. Examples are shown in the following figure.

Figure 115: 1tCK vs. 2tCK READ Preamble Mode

1tCK Mode

RD
CK_c CK_t
DQS_t, DQS_c

CL Preamble

DQ
2tCK Mode
RD
CK_c CK_t
DQS_t, DQS_c

D0 D1 D2 D3 D4 D5 D6 D7
CL Preamble

DQ

D0 D1 D2 D3 D4 D5 D6 D7

READ Preamble Training
DDR4 supports READ preamble training via MPR reads; that is, READ preamble training is allowed only when the DRAM is in the MPR access mode. The READ preamble training mode can be used by the DRAM controller to train or "read level" its DQS receivers. READ preamble training is entered via an MRS command (MR4[10] = 1 is enabled and MR4[10] = 0 is disabled). After the MRS command is issued to enable READ preamble training, the DRAM DQS signals are driven to a valid level by the time tSDO is satisfied. During this time, the data bus DQ signals are held quiet, that is, driven HIGH. The DQS_t signal remains driven LOW and the DQS_c signal remains driven HIGH until an MPR Page0 READ command is issued (MPR0 through MPR3 determine which pattern is used), and when CAS latency (CL) has expired, the DQS signals will toggle normally depending on the burst length setting. To exit READ preamble training mode, an MRS command must be issued, MR4[10] = 0.

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4Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles

Figure 116: READ Preamble Training

CMD
DQS_c DQS_t,

MRS
tSDO

MPR RD
CL

DQs (Quiet/Driven HIGH)

D0 D1 D2 D3 D4 D5 D6 D7

WRITE Postamble

Whether the 1tCK or 2tCK WRITE preamble mode is selected, the WRITE postamble remains the same at ½tCK.

Figure 117: WRITE Postamble
1tCK Mode
WR WL
CK_c CK_t
DQS_t, DQS_c

Postamble

DQ
2tCK Mode
WR WL
CK_c CK_t
DQS_t, DQS_c

D0 D1 D2 D3 D4 D5 D6 D7 Postamble

DQ

D0 D1 D2 D3 D4 D5 D6 D7

READ Postamble

Whether the 1tCK or 2tCK READ preamble mode is selected, the READ postamble remains the same at ½tCK.

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Figure 118: READ Postamble 1tCK Mode
RD CL
CK_c CK_t
DQS_t, DQS_c
DQ
2tCK Mode
RD CL
CK_c CK_t
DQS_t, DQS_c
DQ

4Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles
Postamble D0 D1 D2 D3 D4 D5 D6 D7
Postamble D0 D1 D2 D3 D4 D5 D6 D7

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4Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation
Bank Access Operation
DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:0]), and each bank group is comprised of four subbanks (BA[1:0]); x16 DRAMs have two bank groups (BG[0]), and each bank group is comprised of four subbanks. Bank accesses to different banks' groups require less time delay between accesses than bank accesses to within the same bank's group. Bank accesses to different bank groups require tCCD_S (or short) delay between commands while bank accesses within the same bank group require tCCD_L (or long) delay between commands.

Figure 119: Bank Group x4/x8 Block Diagram
Bank 3 Bank 2 Bank 1 Bank 0 Memory Array

Bank 3 Bank 2 Bank 1
Bank 0 Memory Array

CMD/ADDR

CMD/ADDR register

Bank Group 0
Sense amplifiers

Bank Group 1
Sense amplifiers

Bank 3 Bank 2 Bank 1 Bank 0 Memory Array
Bank Group 2
Sense amplifiers

Bank 3 Bank 2 Bank 1 Bank 0 Memory Array
Bank Group 3
Sense amplifiers

Local I/O gating

Local I/O gating

Local I/O gating

Local I/O gating

Global I/O gating

Data I/O
Notes: 1. Bank accesses to different bank groups require tCCD_S. 2. Bank accesses within the same bank group require tCCD_L.

Table 68: DDR4 Bank Group Timing Examples

Parameter tCCD_S tCCD_L

DDR4-1600 4nCK
4nCK or 6.25ns

DDR4-2133 4nCK
4nCK or 5.355ns

tRRD_S (½K) tRRD_L (½K)

4nCK or 5ns 4nCK or 6ns

4nCK or 3.7ns 4nCK or 5.3ns

tRRD_S (1K) tRRD_L (1K)

4nCK or 5ns 4nCK or 6ns

4nCK or 3.7ns 4nCK or 5.3ns

tRRD_S (2K) tRRD_L (2K)

4nCK or 6ns 4nCK or 7.5ns

4nCK or 5.3ns 4nCK or 6.4ns

DDR4-2400 4nCK
4nCK or 5ns
4nCK or 3.3ns 4nCK or 4.9ns
4nCK or 3.3ns 4nCK or 4.9ns
4nCK or 5.3ns 4nCK or 6.4ns

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4Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation

Table 68: DDR4 Bank Group Timing Examples (Continued)

Parameter tWTR_S tWTR_L

DDR4-1600 2nCK or 2.5ns 4nCK or 7.5ns

DDR4-2133 2nCK or 2.5ns 4nCK or 7.5ns

DDR4-2400 2nCK or 2.5ns 4nCK or 7.5ns

Notes:

1. Refer to Timing Tables for actual specification values, these values are shown for reference only and are not verified for accuracy.
2. Timings with both nCK and ns require both to be satisfied; that is, the larger time of the two cases must be satisfied.

Figure 120: READ Burst tCCD_S and tCCD_L Examples

CK_c

T0

T1

T2

T3

T4

T5

T6

CK_t

Command READ

DES

DES

DES

READ

DES

DES

tCCD_S

Bank Group (BG)

BG a

BG b

Bank Bank c

Bank c

T7

T8

DES

DES

tCCD_L

T9

T10

T11

DES

READ

DES

BG b Bank c

Address Col n

Col n

Col n

Don't Care

Notes:

1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank groups (T0 to T4).
2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank group (T4 to T10).

Figure 121: Write Burst tCCD_S and tCCD_L Examples

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

WRITE

DES

tCCD_S

tCCD_L

Bank Group (BG)

BG a

BG b

BG b

Bank Bank c

Bank c

Bank c

Address

Coln

Coln

Coln

Don't Care

Notes:

1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank groups (T0 to T4).
2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank group (T4 to T10).

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4Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation

Figure 122: tRRD Timing

CK_c

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK_t

Command

ACT

DES

DES

DES

ACT

DES

DES

DES

DES

DES

ACT

DES

tRRD_S

tRRD_L

Bank

Group BG a

BG b

(BG)

BG b

Bank Bank c

Bank c

Bank d

Address Row n

Row n

Row n

Don't Care

Notes:

1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTIVATE commands to different bank groups (T0 and T4).
2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group (T4 and T10).

Figure 123: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled)

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

CK_c

CK_t

Command WRITE

Valid

Valid

Bank Group

BGa

Bank Bank c

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

tWTR_S

READ BGb Bank c

Valid

Address Col n DQS, DQS_c

tWPRE

tWPST

Col n

DQ

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

WL

RL

Time Break

Transitioning Data

Don't Care

Note: 1. tWTR_S: delay from start of internal write transaction to internal READ command to a different bank group.

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4Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation

Figure 124: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled)

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

CK_c

CK_t

Command WRITE

Valid

Valid

Bank Group

BGa

Bank Bank c

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

tWTR_L

READ BGa Bank c

Valid

Address Col n DQS, DQS_c

tWPRE

tWPST

Col n

DQ

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

WL

RL

Time Break

Transitioning Data

Don't Care

Note: 1. tWTR_L: delay from start of internal write transaction to internal READ command to the same bank group.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
READ Operation
Read Timing Definitions
The read timings shown below are applicable in normal operation mode, that is, when the DLL is enabled and locked. Note: tDQSQ = both rising/falling edges of DQS; no tAC defined.
Rising data strobe edge parameters: · tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela-
tive to CK. · tDQSCK is the actual position of a rising strobe edge relative to CK. · tQSH describes the DQS differential output HIGH time. · tDQSQ describes the latest valid transition of the associated DQ pins. · tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters: · tQSL describes the DQS differential output LOW time. · tDQSQ describes the latest valid transition of the associated DQ pins. · tQH describes the earliest invalid transition of the associated DQ pins.

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Figure 125: Read Timing Definition
CK_c

4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

CK_t tDQSCK (MIN) tDQSCK (MAX) tDQSCK (MIN) tDQSCK (MAX)

tDQSCKi

tDQSCKi

tDQSCK MAX

Rising strobe region window
tDQSCKi

Rising strobe region window
tDQSCKi

tDQSCK center

Rising strobe region
window

tDQSCKi

Rising strobe region window
tDQSCKi

tDQSCK MIN

Rising strobe region

window

tDQSCK tQSH/DQS_c

DQS_c

Rising strobe region window
tDQSCK
tQSH/DQS_t

DQS_t

tQH tDQSQ

tQH tDQSQ

Associated DQ Pins

Table 69: Read-to-Write and Write-to-Read Command Intervals

Access Type
Read-to-Write, minimum
Write-to-Read, minimum

Bank Group Same
Different Same
Different

Timing Parameters CL - CWL + RBL/2 + 1tCK + tWPRE CL - CWL + RBL/2 + 1tCK + tWPRE
CWL + WBL/2 + tWTR_L CWL + WBL/2 + tWTR_S

Note 1, 2 1, 2 1, 3 1, 3

Notes:

1. These timings require extended calibrations times tZQinit and tZQCS. 2. RBL: READ burst length associated with READ command, RBL = 8 for fixed 8 and on-the-
fly mode 8 and RBL = 4 for fixed BC4 and on-the-fly mode BC4. 3. WBL: WRITE burst length associated with WRITE command, WBL = 8 for fixed 8 and on-
the-fly mode 8 or BC4 and WBL = 4 for fixed BC4 only.

Read Timing ­ Clock-to-Data Strobe Relationship
The clock-to-data strobe relationship shown below is applicable in normal operation mode, that is, when the DLL is enabled and locked.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
Rising data strobe edge parameters:
· tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge relative to CK.
· tDQSCK is the actual position of a rising strobe edge relative to CK. · tQSH describes the data strobe high pulse width. · tHZ(DQS) DQS strobe going to high, nondrive level (shown in the postamble section
of the figure below).
Falling data strobe edge parameters:
· tQSL describes the data strobe low pulse width. · tLZ(DQS) DQS strobe going to low, initial drive level (shown in the preamble section
of the figure below).

Figure 126: Clock-to-Data Strobe Relationship

RL measured to this point

CK_t CK_c

DQS_t, DQS_c Early Strobe

tLZ(DQS) MIN

DQS_t, DQS_c Late Strobe

tLZ(DQS) MAX

tDQSCK (MIN)

tDQSCK (MIN)

tDQSCK (MIN)

tDQSCK (MIN)

tRPRE

tQSH Bit 0

tQSL Bit 1

tQSH Bit 2

tQSL Bit 3

tDQSCK (MAX)

tDQSCK (MAX)

tQSH Bit 4

tQSL Bit 5

tDQSCK (MAX)

Bit 6

Bit 7 tRPST

tDQSCK (MAX)

tHZ(DQS) MIN

tRPST

tHZ(DQS) MAX

tRPRE

Bit 0 tQSH

Bit 1 tQSL

Bit 2 tQSH

Bit 3 tQSL

Bit 4

Bit 5

Bit 6

Bit 7

Notes:

1. Within a burst, the rising strobe edge will vary within tDQSCKi while at the same volt-
age and temperature. However, when the device, voltage, and temperature variations are incorporated, the rising strobe edge variance window can shift between tDQSCK (MIN) and tDQSCK (MAX).

A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a device's actual tDQSCK (MAX). A timing of this window's left inside edge (earliest) from rising CK_t, CK_c is limited by tDQSCK (MIN).
2. Notwithstanding Note 1, a rising strobe edge with tDQSCK (MAX) at T(n) can not be immediately followed by a rising strobe edge with tDQSCK (MIN) at T(n + 1) because other timing relationships (tQSH, tQSL) exist: if tDQSCK(n + 1) < 0: tDQSCK(n) < 1.0 tCK - (tQSH (MIN) + tQSL (MIN)) - | tDQSCK(n + 1) |.
3. The DQS_t, DQS_c differential output HIGH time is defined by tQSH, and the DQS_t, DQS_c differential output LOW time is defined by tQSL.
4. tLZ(DQS) MIN and tHZ(DQS) MIN are not tied to tDQSCK (MIN) (early strobe case), and tLZ(DQS) MAX and tHZ(DQS) MAX are not tied to tDQSCK (MAX) (late strobe case).
5. The minimum pulse width of READ preamble is defined by tRPRE (MIN).
6. The maximum READ postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left side and tHZDSQ (MAX) on the right side.
7. The minimum pulse width of READ postamble is defined by tRPST (MIN).

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
8. The maximum READ preamble is bound by tLZDQS (MIN) on the left side and tDQSCK (MAX) on the right side.
Read Timing ­ Data Strobe-to-Data Relationship
The data strobe-to-data relationship is shown below and is applied when the DLL is enabled and locked. Note: tDQSQ: both rising/falling edges of DQS; no tAC defined.
Rising data strobe edge parameters: · tDQSQ describes the latest valid transition of the associated DQ pins. · tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters: · tDQSQ describes the latest valid transition of the associated DQ pins. · tQH describes the earliest invalid transition of the associated DQ pins.
Data valid window parameters: · tDVWd is the Data Valid Window per device per UI and is derived from [ tQH - tDQSQ]
of each UI on a given DRAM · tDVWp is the Data Valid Window per pin per UI and is derived [ tQH - tDQSQ] of each
UI on a pin of a given DRAM

Figure 127: Data Strobe-to-Data Relationship

CK_c CK_t
Command3

T0 READ

Address4

Bank, Col n

T1

T2

DES

DES

RL = AL + CL

DQS_t, DQS_c
DQ2 (Last data )
DQ2 (First data no longer)
All DQ collectively

T9

T10

T11

T12

T13

T14

T15

DES

DES

DES

DES

DES

DES

DES

tDQSQ (MAX) tRPRE (1nCK)

tDQSQ (MAX)

tRPST

tQH

tQH

DOUT n
DOUT n DOUT n

DOUT n + 1

DOUT n + 2

DOUT n + 3

DOUT n + 4

DOUT n + 5

DOUT n + 6

DOUT n + 7

DOUT n + 1
DOUT n + 1

DOUT n + 2
DOUT n + 2

DOUT n + 3
DOUT n + 3

DOUT n + 4
DOUT n + 4

DOUT n + 5
DOUT n + 5

tDVWp

DOUT n + 6

DOUT n + 7

tDVWp

DOUT n + 6

DOUT n + 7

tDVWd

tDVWd

T16 DES
Don't Care

Notes:

1. BL = 8, RL = 11 (AL = 0, CL = 1) , Premable = 1tCK.
2. DOUTn = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0.
5. Output timings are referenced to VDDQ, and DLL on for locking. 6. tDQSQ defines the skew between DQS to data and does not define DQS to clock.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst.
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). The figure below shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as singled-ended parameters.
Figure 128: tLZ and tHZ Method for Calculating Transitions and Endpoints

tLZ(DQ): CK_t, CK_c rising crossing at RL CK_t

tHZ(DQ) with BL8: CK_t, CK_c rising crossing at RL + 4CK tHZ(DQ) with BC4: CK_t, CK_c rising crossing at RL + 2CK

CK_c Begin point: Extrapolated point at VDDQ DQ
0.7 × VDDQ
0.4 × VDDQ

tLZ
VDDQ VSW2
VSW1

tHZ

VDDQ

DQ

VSW2 VSW1

0.7 × VDDQ

0.4 × VDDQ Begin point: Extrapolated point (low level)

Notes:

1. Vsw1 = (0.70 - 0.04) × VDDQ for both tLZ and tHZ. 2. Vsw2 = (0.70 + 0.04) × VDDQ for both tLZ and tHZ.
3. Extrapolated point (low level) = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ Driver impedance = RZQ/7 = 34 VTT test load = 50 to VDDQ.

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tRPRE Calculation

4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 129: tRPRE Method for Calculating Transitions and Endpoints

CK_t
CK_c Single-ended signal provided as background information
DQS_t
DQS_c

DQS_t DQS_c

Resulting differential signal relevant fortRPRE specification

DQS_t, DQS_c

VSW2 VSW1
tRPRE begins (t1)

VDD /2

VDDQ

0.7 × VDDQ

0.4 × VDDQ VDDQ

0.7 × VDDQ

0.4 × VDDQ

DQS_t

VDDQ

0.7 × VDDQ

DQS_c

0.4 × VDDQ

tRPRE ends (t2)

0.6 × VDDQ 0.3 × VDDQ 0V

Notes:

1. Vsw1 = (0.3 - 0.04) × VDDQ.
2. Vsw2 = (0.30 + 0.04) × VDDQ.
3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ Driver impedance = RZQ/7 = 34 VTT test load = 50 to VDDQ.

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tRPST Calculation

4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 130: tRPST Method for Calculating Transitions and Endpoints

CK_t
CK_c Single-ended signal provided as background information
DQS_t DQS_c
DQS_c DQS_t Resulting differential signal relevant fortRPST specification

VDD /2
VDDQ 0.7 × VDDQ 0.4 × VDDQ VDDQ 0.7 × VDDQ 0.4 × VDDQ
VDDQ 0.7 × VDDQ

tRPST beginst(1)

DQS_t, DQS_c

VSW2 VSW1
tRPST ends t(2)

0V ­0.3 × VDDQ ­0.6 × VDDQ

Notes:

1. Vsw1 = (­0.3 - 0.04) × VDDQ.
2. Vsw2 = (­0.30 + 0.04) × VDDQ.
3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ Driver impedance = RZQ/7 = 34 VTT test load = 50 to VDDQ.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
READ Burst Operation
DDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 onthe-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
· A12 = 0, BC4 (BC4 = burst chop) · A12 = 1, BL8
READ commands can issue precharge automatically with a READ with auto precharge command (RDA), and is enabled by A10 HIGH:
· READ command with A10 = 0 (RD) performs standard read, bank remains active after READ burst.
· READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in to precharge after READ burst.

Figure 131: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)

T0 CK_c CK_t

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Ta9

Command READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

Bank Group Address
Address

BGa Bank col n

DQS_t DQS_c

tRPRE

tRPST

DQ CL = 11
RL = AL + CL

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, RL = 0, AL = 0, CL = 11, Preamble = 1tCK. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 132: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8)

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tb2

Tb3

Tb4

Tb5

Tb6

Command READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

Bank Group Address
Address

BGa Bank col n

DQS_t DQS_c

tRPRE

tRPST

DQ AL = 10

CL = 11 RL = AL + CL

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1tCK. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
READ Operation Followed by Another READ Operation

Figure 133: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group Address

BGa

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

RL = 11

DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
RL = 11

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CL = 11, Preamble = 1tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 134: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group Address

BGa

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

RL = 11

DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
RL = 11

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CL = 11, Preamble = 2tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 135: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T5

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group Address

BGa

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S/L = 5

BGb

Bank Col b

tRPRE

tRPST

RL = 11

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
RL = 11

DO DO DO DO DO DO DO DO b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CL = 11, Preamble = 1tCK, tCCD_S/L = 5. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T5. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group

T0 CK_c CK_t

T1

T2

T5

T6

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group Address

BGa

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S/L = 6

BGa or BGb

Bank Col b

tRPRE

tRPRE

tRPST

RL = 11

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
RL = 11

DO DO DO DO DO DO DO DO b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CL = 11, Preamble = 2tCK, tCCD_S/L = 6. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0 and T6. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. 6. 6 tCCD_S/L = 5 isn't allowed in 2tCK preamble mode.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 137: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command READ

Bank Group BGa Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

tRPRE

tRPST

RL = 11

DO DO DO DO n n+1 n+2 n+3
RL = 11

DO DO DO DO b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CL = 11, Preamble = 1tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 138: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command READ

Bank Group BGa Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPRE

tRPST

RL = 11

DO DO DO DO n n+1 n+2 n+3
RL = 11

DO DO DO DO b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CL = 11, Preamble = 2tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 139: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group BGa Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

RL = 11

DO DO DO DO DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3
RL = 11

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4
setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 140: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group BGa Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

RL = 11

DO DO DO DO DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3
RL = 11

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL =0, CL = 11, Preamble = 2tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4
setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 141: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command READ

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

tRPRE

tRPST

RL = 11

DO DO DO DO n n+1 n+2 n+3 RL = 11

DO DO DO DO DO DO DO DO b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL =0, CL = 11, Preamble = 1tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8
setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 142: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command READ

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGb

Bank Col b

tRPRE

tRPST

RL = 11

DO DO DO DO n n+1 n+2 n+3 RL = 11

DO DO DO DO DO DO DO DO b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL = 0, CL = 11, Preamble = 2tCK. 2. DO n (or b) = data-out from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8
setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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READ Operation Followed by WRITE Operation

4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 143: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

4 Clocks

tWTR

Bank Group Address

BGa

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

tWPRE

tWPST

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 9

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

Figure 144: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

READ to WRITE command delay = RL +BL/2 - WL + 3 tCK

4 Clocks

tWR tWTR

Bank Group Address

BGa

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 10

tWPRE

tWPST

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9+1 [see Note 5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

Figure 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

4 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

tWPRE

tWPST

DO DO DO DO n n+1 n+2 n+3 WL = 9

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and WRITE commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 3 tCK

4 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

DO DO DO DO n n+1 n+2 n+3 WL = 10

tWPRE

tWPST

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and WRITE commands at T6.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

2 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

tWPRE

tWPST

WL = 9

DO DO DO DO n n+1 n+2 n+3

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 01. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.

Figure 148: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 3 tCK

2 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

DO DO DO DO n n+1 n+2 n+3 WL = 10

tWPRE

tWPST

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 9 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10. 5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 149: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

4 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b
RL = 11

tRPRE

tRPST

tWPRE

tWPST

DO DO DO DO n n+1 n+2 n+3 WL = 9

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 n+4 n+5 n+6 n+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

Figure 150: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 3 tCK

4 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b
RL = 11

tRPRE

tRPST

DO DO DO DO n n+1 n+2 n+3 WL = 10

tWPRE

tWPST

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 n+4 n+5 n+6 n+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

Figure 151: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

4 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

tWPRE

tWPST

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 9

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

Figure 152: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

READ to WRITE command delay = RL +BL/2 - WL + 3 tCK

4 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 11

tRPRE

tRPST

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 10

tWPRE

tWPST

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.
READ Operation Followed by PRECHARGE Operation
The minimum external READ command to PRECHARGE command spacing to the same bank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGE command delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied as well. The minimum value for the internal READ command to PRECHARGE command delay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE command may be issued to the same bank if the following two conditions are satisfied simultaneously:
· The minimum RAS precharge time (tRP [MIN]) has been satisfied from the clock at which the precharge begins.
· The minimum RAS cycle time (tRC [MIN]) from the previous bank activation has been satisfied.

Figure 153: READ to PRECHARGE with 1tCK Preamble

T0

T1

T2

T3

T6

T7

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command DES

READ

DES

DES

DES

PRE

DES

DES

DES

DES

DES

DES

DES

DES

ACT

DES

DES

DES

Bank Group

Address

BGa

BGa or BGb

BGa

Address

Bank a Col n

BC4 Opertaion DQS_t, DQS_c
DQ
BL8 Opertaion DQS_t, DQS_c
DQ

tRTP

Bank a (or all) RL = AL + CL

tRP DO DO DO DO n n+1 n+2 n+3 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Bank a Row b

Time Break

Transitioning Data

Don't Care

Notes:

1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 154: READ to PRECHARGE with 2tCK Preamble

T0

T1

T2

T3

T6

T7

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command DES

READ

DES

DES

DES

PRE

DES

DES

DES

DES

DES

DES

DES

DES

ACT

DES

DES

DES

Bank Group Address
Address

BGa Bank a Col n

BC4 Opertaion DQS_t, DQS_c
DQ
BL8 Opertaion DQS_t, DQS_c
DQ

BGa or BGb

tRTP

Bank a (or all) RL = AL + CL

tRP DO DO DO DO n n+1 n+2 n+3 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

BGa Bank a Row b

Time Break

Transitioning Data

Don't Care

Notes:

1. RL = 11 (CL = 11, AL = 0 ), Preamble = 2tCK, tRTP = 6, tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 155: READ to PRECHARGE with Additive Latency and 1tCK Preamble

T0

T1

T2

T3

T10

T11

T12

T13

T16

T19

T20

T21

T22

T23

T24

T25

T26

T27

CK_c

CK_t

Command DES

READ

DES

DES

DES

DES

DES

DES

PRE

DES

DES

DES

DES

DES

DES

DES

DES

ACT

Bank Group Address
Address

BGa Bank a Col n

BC4 Opertaion DQS_t, DQS_c
DQ
BL8 Opertaion DQS_t, DQS_c
DQ

AL = CL - 2 = 9

BGa or BGb

tRTP

CL = 11

Bank a (or all)

tRP DO DO DO DO n n+1 n+2 n+3 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

BGa Bank a Row b

Time Break
Notes: 1. RL =20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11. 2. DO n = data-out from column n.

Transitioning Data

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

Figure 156: READ with Auto Precharge and 1tCK Preamble

T0

T1

T2

T3

T6

T7

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

CK_c

CK_t

Command DES

RDA

DES

DES

DES

PRE

DES

DES

DES

DES

DES

DES

DES

DES

ACT

DES

DES

DES

Bank Group

Address

BGa

BGa or BGb

BGa

Address

Bank a Col n

BC4 Opertaion DQS_t, DQS_c
DQ
BL8 Opertaion DQS_t, DQS_c
DQ

tRTP

Bank a Col n RL = AL + CL

tRP DO DO DO DO n n+1 n+2 n+3 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Bank a Row b

Time Break

Transitioning Data

Don't Care

Notes:

1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. tRTP = 6 setting activated by MR0[A11:9 = 001]. 5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time
(T18). 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 157: READ with Auto Precharge, Additive Latency, and 1tCK Preamble

T0

T1

T2

T3

T10

T11

T12

T13

T16

T19

T20

T21

T22

T23

T24

T25

T26

T27

CK_c

CK_t

Command DES

RDA

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

ACT

Bank Group Address
Address

BGa Bank a Col n

BC4 Opertaion DQS_t, DQS_c
DQ
BL8 Opertaion DQS_t, DQS_c
DQ

AL = CL - 2 = 9

tRTP

CL = 11

tRP DO DO DO DO n n+1 n+2 n+3 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

BGa Bank a Row b

Time Break

Transitioning Data

Don't Care

Notes:

1. RL = 20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. tRTP = 6 setting activated by MR0[11:9] = 001. 5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time
(T27). 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

READ Operation with Read Data Bus Inversion (DBI)

Figure 158: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

Command READ

Bank Group BGa Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DBI_n

DES

DES

DES

tCCD_S = 4

READ BGb Bank Col b

RL = 11 + 2 (Read DBI adder)

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tRPRE

tRPST

RL = 11 + 2 (Read DBI adder)

DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 b b + 1 b + 2 b + 3 b +4 _ b + 5 b + 6 b + 7 DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI DBI n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Notes: 1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK, RL = 11 + 2 (Read DBI adder).

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
2. DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable.
READ Operation with Command/Address Parity (CA Parity)

Figure 159: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group

T0 CK_c CK_t

T1

T2

T3

T4

T7

T8

T13

T14

T15

T16

T17

T18

T19

T20

T21

T20

T21

Command READ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

Bank Group BGa

BGb

Address

Address Parity

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 15

tRPRE

tRPST

RL = 15

DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 b b + 1 b + 2 b + 3 b +4 _ b + 5 b + 6 b + 7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1tCK. 2. DO n (or b) = data-out from column n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during
READ commands at T0 and T4. 5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 160: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group

T0

T1

T7

T8

T9

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

4 Clocks

tWR tWTR

Bank Group

BGa

Address

BGa or BGb

Address Parity

Bank Col n

DQS_t, DQS_c

DQ

Bank Col b RL = 15

tRPRE

tRPST

tWPRE

tWPST

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 13

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1tCK, CWL = 9, AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1tCK.
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE command at T8.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.

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READ Followed by WRITE with CRC Enabled

4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 161: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

4 Clocks

tWR tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ x4, BL = 8
DQ x8/X16, BL = 8
DQ x4, READ: BL = 8, WRITE: BC = 4 (OTF)
DQ x8/X16, READ: BL = 8, WRITE: BC = 4 (OTF)

Bank Col b RL = 11

tRPRE

tRPST

tWPRE

tWPST

WL = 9

DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7

DI b

DI DI DI DI DI DI DI b+1 b+2 b+3 b+4 b+5 b+6 b+7

CRC

CRC

DI b

DI DI DI DI DI DI DI b+1 b+2 b+3 b+4 b+5 b+6 b+7

CRC

DI DI DI DI b b+1 b+2 b+3

CRC CRC

DI DI DI DI b b+1 b+2 b+3

CRC

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8 (or BC = 4: OTF for Write), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n, DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation

Figure 162: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group

T0

T1

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command READ

DES

DES

WRITE

DES

Bank Group Address

READ to WRITE command delay = RL +BL/2 - WL + 2 tCK

BGa

BGa or BGb

Address

Bank Col n

Bank Col b

DES

DES

DQS_t, DQS_c
DQ x4, BC = 4 (Fixed)
DQ x8/X16, BC = 4 (Fixed)

RL = 11

WL = 9

DES

DES

DES

DES

DES

DES

DES

DES

2 Clocks

tRPRE

tRPST

tWPRE

DO DO DO DO n n+1 n+2 n+3 DO DO DO DO n n+1 n+2 n+3

DI DI DI DI b b+1 b+2 b+3 DI DI DI DI b b+1 b+2 b+3

DES

DES

DES

tWR

tWTR

tWPST CRC CRC CRC

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
2. DO n = data-out from column n, DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.

READ Operation with Command/Address Latency (CAL) Enabled

Figure 163: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group

T0 CK_c CK_t
Command w/o CS_n
CS_n
Bank Group Address

T1

T2

T3

T4

T5

T6

T7

T8

T13

T14

T15

T17

T18

T19

T21

T22

T23

tCAL = 3

tCAL = 3

DES

DES

READ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGa

BGb

Address
DQS_t, DQS_c
DQ

Bank Col n

Bank Col b RL = 11

tRPRE

tRPST

RL = 11

DI DI DI DI DI DI DI DI DI DI DI DI n n+1 n+2 n+5 n+6 n+7 b b+1 b+2 b+5 b+6 b+7

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.

Time Break

Transitioning Data

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM READ Operation
2. DI n (or b) = data-in from column n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T7. 5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable. 6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.

Figure 164: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group

T0 CK_c CK_t
Command w/o CS_n
CS_n
Bank Group Address

T1

T2

T3

T4

T5

T6

T7

T8

T14

T15

T16

T18

T19

T21

T22

T23

T24

tCAL = 4

tCAL = 4

DES

DES

READ

DES

DES

DES

READ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tCCD_S = 4

BGa

BGb

Address
DQS_t, DQS_c
DQ

Bank Col n

RL = 11

Bank Col b

tRPRE

tRPST

DI DI DI DI DI DI DI DI DI DI DI DI n n+1 n+2 n+5 n+6 n+7 b b+1 b+2 b+5 b+6 b+7
RL = 11

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK. 2. DI n (or b) = data-in from column n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T8. 5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable. 6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
WRITE Operation
Write Timing Definitions
The write timings shown in the following figures are applicable in normal operation mode, that is, when the DLL is enabled and locked.
Write Timing ­ Clock-to-Data Strobe Relationship
The clock-to-data strobe relationship is shown below and is applicable in normal operation mode, that is, when the DLL is enabled and locked.
Rising data strobe edge parameters: · tDQSS (MIN) to tDQSS (MAX) describes the allowed range for a rising data strobe edge
relative to CK. · tDQSS is the actual position of a rising strobe edge relative to CK. · tDQSH describes the data strobe high pulse width. · tWPST strobe going to HIGH, nondrive level (shown in the postamble section of the
graphic below).
Falling data strobe edge parameters: · tDQSL describes the data strobe low pulse width. · tWPRE strobe going to LOW, initial drive level (shown in the preamble section of the
graphic below).

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 165: Write Timing Definition

T0

T1

T2

T7

T8

T9

T10

T11

T12

T13

CK_c

CK_t

Command3 WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

WL = AL + CWL

Address4

Bank, Col n

tDQSS (MIN)
DQS_t, DQS_c
DQ2

tDQSS tDSH tWPRE(1nCK)

tDSH

tDSH

tDSH tWPSTaa

tDQSL tDQSH (MIN)
tDSS

tDQSH

DIN n

tDQSL tDQSH tDQSL tDQSH

tDSS DIN n+ 2

tDSS

DIN n+ 3

DIN n+ 4

tDQSL tDQSH

tDQSL (MIN)

tDSS

tDSS

DIN n+ 6

DIN n+ 7

T14
DES

tDQSS (nominal)
DQS_t, DQS_c
DQ2

tWPRE(1nCK)

tDSH

tDSH

tDSH

tDSH tWPST (MIN)

tDQSH (MIN)

tDQSL tDSS

tDQSH

tDQSL tDQSH tDSS

tDQSL tDQSH tDSS

tDQSL tDSS

tDQSH tDQSL (MIN)
tDSS

DIN

DIN

DIN

DIN

DIN

DIN

n

n+ 2 n+ 3 n+ 4

n+ 6

n+ 7

tDQSS (MAX)
DQS_t, DQS_c
DQ2

tDQSS

tWPRE(1nCK)

tDSH

tDSH

tDSH

tDSH

tWPST (MIN)

tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH

tDQSH (MIN)

tDQSL (MIN)

tDSS DIN n

tDSS

DIN n+ 2

tDSS DIN n+ 3

DIN n+ 4

tDSS

DIN n+ 6

tDSS DIN n+ 7

DM_n

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, WL = 9 (AL = 0, CWL = 9).
2. DINn = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.

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tWPRE Calculation

4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 166: tWPRE Method for Calculating Transitions and Endpoints

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'46BF

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95()'4  95()'4

'46BW '46BF

5HVXOWLQJGLIIHUHQWLDOVLJQDOUHOHYDQWIRUW :35(VSHFLILFDWLRQ

'46BW'46BF

96: 96:
W:35(EHJLQV W

'46BW 95()'4
'46BF
9,+',))3HDN 9,+',))'46
9 W :35(HQGV W 

Notes: 1. Vsw1 = (0.1) × VIH,diff,DQS. 2. Vsw2 = (0.9) × VIH,diff,DQS.

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tWPST Calculation

4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 167: tWPST Method for Calculating Transitions and Endpoints

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&.BF 6LQJOHHQGHGVLJQDOSURYLGHGDVEDFNJURXQGLQIRUPDWLRQ

9''

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95()'4 95()'4

'46BF
'46BW 5HVXOWLQJGLIIHUHQWLDOVLJQDOUHOHYDQWIRU W:367VSHFLILFDWLRQ

95()'4

W:367EHJLQV W

'46BW'46BF
Notes: 1. Vsw1 =(0.9) × VIL,diff,DQS. 2. Vsw2 = (0.1) × VIL,diff,DQS.

96: 96:
W:367HQGV W

9
9,/',))'46 9,/',))3HDN

Write Timing ­ Data Strobe-to-Data Relationship
The DQ input receiver uses a compliance mask (Rx) for voltage and timing as shown in the figure below. The receiver mask (Rx mask) defines the area where the input signal must not encroach in order for the DRAM input receiver to be able to successfully capture a valid input signal. The Rx mask is not the valid data-eye. TdiVW and V diVW define the absolute maximum Rx mask.

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Figure 168: Rx Compliance Mask

4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Rx Mask

VCENTDQ,midpoint

VDIVW

TdiVW

VCENTDQ,midpoint is defined as the midpoint between the largest VREFDQ voltage level and the smallest VREFDQ voltage level across all DQ pins for a given DRAM. Each DQ pin's VREFDQ is defined by the center (widest opening) of the cumulative data input eye as depicted in the following figure. This means a DRAM's level variation is accounted for
within the DRAM Rx mask. The DRAM VREFDQ level will be set by the system to account for RON and ODT settings.

Figure 169: VCENT_DQ VREFDQ Voltage Variation

DQx

DQy (smallest VREFDQ Level)

DQz (largest VREFDQ Level)

VCENTDQx

VCENTDQy

VCENTDQz

VCENTDQ,midpoint

VREF variation (component)

The following figure shows the Rx mask requirements both from a midpoint-to-midpoint reference (left side) and from an edge-to-edge reference. The intent is not to add any new requirement or specification between the two but rather how to convert the relationship between the two methodologies. The minimum data-eye shown in the composite view is not actually obtainable due to the minimum pulse width requirement.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 170: Rx Mask DQ-to-DQS Timings

VdiVW

VdiVW

VdiVW

DQS, DQs Data-In at DRAM Ball
Rx Mask DQS_c

DQS_t

0.5 × TdiVW 0.5 × TdiVW

DQS, DQs Data-In at DRAM Ball
Rx Mask ­ Alternative View DQS_c

DQS_t

0.5 × TdiVW 0.5 × TdiVW

DRAMa DQx­z

Rx Mask
TdiVW

VdiVW

DRAMa DQx­z

Rx Mask
TdiVW

DRAMb DQy
DRAMb DQz
DRAMc DQz

tDQS2DQ
Rx Mask
tDQ2DQ
Rx Mask
tDQS2DQ
Rx Mask
tDQ2DQ

VdiVW

VdiVW

VdiVW

tDQS2DQ +0.5 × TdiVW

DRAMb DQy
DRAMb DQz
tDQ2DQ

Rx Mask
TdiVW
Rx Mask
TdiVW

tDQ2DQ

tDQS2DQ +0.5 × TdiVW

DRAMc DQz

tDQ2DQ

Rx Mask
TdiVW

DRAMc DQy

Rx Mask

VdiVW

DRAMc DQy

Rx Mask
TdiVW

tDQ2DQ

Notes:

1. DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask.
2. DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with early skews (negative tDQS2DQ). DRAMc represents a DRAM with delayed skews (positive tDQS2DQ).
3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ for a DRAM. Signals assume data is center-aligned at DRAM latch. TdiPW is not shown; composite data-eyes shown would violate TdiPW. VCENTDQ,midpoint is not shown but is assumed to be midpoint of VdiVW.

The previous figure shows the basic Rx mask requirements. Converting the Rx mask requirements to a classical DQ-to-DQS relationship is shown in the following figure. It should become apparent that DRAM write training is required to take full advantage of the Rx mask.

VdiVW

VdiVW

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 171: Rx Mask DQ-to-DQS DRAM-Based Timings

DQS, DQs Data-In at DRAM Ball
Rx Mask vs. Composite Data-Eye

DQS_c

DQS_t

TdiPW

DQS, DQs Data-In at DRAM Ball
Rx Mask vs. UI Data-Eye DQS_c

DQS_t

tDSx

tDHx

VdiVW

DRAMa DQx , y, z

Rx Mask
TdiVW
TdiPW

VdiVW

DRAMa DQx­z
DRAMb DQy

Rx Mask
TdiVW

TdiPW tDSy *Skew

tDHy

Rx Mask
TdiVW

tDQ2DQ

VdiVW

VdiVW

DRAMb DQz
DRAMc DQy

tDQ2DQ

Rx Mask
TdiVW

TdiPW tDSz

tDHz *Skew

tDQ2DQ

Rx Mask
TdiVW

VdiVW

VdiVW

DRAMc DQz

Rx Mask
TdiVW

tDQ2DQ

TdiPW

Notes:

1. DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask.
2. *Skew = tDQS2DQ + 0.5 × TdiVW DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with the earliest skews (negative tDQS2DQ, tDQSy > *Skew). DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew).
3. tDS/tDH are traditional data-eye setup/hold edges at DC levels. tDS and tDH are not specified; tDH and tDS may be any value provided the pulse width and Rx mask limits are not violated. tDH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ.

The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx mask of TdiVW provided the minimum pulse width is satisfied. The DRAM controller will have to train the data input buffer to utilize the Rx mask specifications to this maxi-

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

mum benefit. If the DRAM controller does not train the data input buffers, then the worst case limits have to be used for the Rx mask (TdiVW + 2 × tDQS2DQ), which will generally be the classical minimum ( tDS and tDH) and is required as well.
Figure 172: Example of Data Input Requirements Without Training

VdiVW

TdiVW + 2 × tDQS2DQ Rx Mask

VIH(DC) 0.5 × VdiVW
VCENTDQ,midpoint 0.5 × VdiVW
VIL(DC)

tDS

tDH

0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ

DQS_c

DQS_t
WRITE Burst Operation
The following write timing diagrams are intended to help understand each write parameter's meaning and are only examples. Each parameter will be defined in detail separately. In these write timing diagrams, CK and DQS are shown aligned, and DQS and DQ are shown center-aligned for the purpose of illustration.
DDR4 WRITE command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 onthe-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
· A12 = 0, BC4 (BC4 = burst chop) · A12 = 1, BL8
WRITE commands can issue precharge automatically with a WRITE with auto precharge (WRA) command, which is enabled by A10 HIGH.
· WRITE command with A10 = 0 (WR) performs standard write, bank remains active after WRITE burst
· WRITE command with A10 = 1 (WRA) performs write with auto precharge, bank goes into precharge after WRITE burst
The DATA MASK (DM) function is supported for the x8 and x16 configurations only (the DM function is not supported on x4 devices). The DM function shares a common pin with the DBI_n and TDQS functions. The DM function only applies to WRITE operations and cannot be enabled at the same time the DBI function is enabled.
· If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
· If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core.
· If CRC write is enabled, then DM enabled (via MRS) will be selected between write CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM enabled).

Figure 173: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)

T0

T1

T2

CK_c

CK_t

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

Bank Group BGa Address

Address

Bank Col n

DQS_t, DQS_c

tWPRE

tWPST

DQ

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

WL = AL + CWL = 9

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1tCK. 2. DI n = Data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0. 5. CA parity = Disable, CS to CA Latency = Disable, Read DBI = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 174: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)

T0

T1

T2

T9

T10

T11

T17

T18

T19

T20

T21

T22

T23

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

tWPRE

tWPST

DQ AL = 10

CWL = 9

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

WL = AL + CWL = 19

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1tCK. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.

WRITE Operation Followed by Another WRITE Operation

Figure 175: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DES

DES

tCCD_S = 4

DES

WRITE

DES

BGb Bank Col b

DQS_t, DQS_c
DQ

WL = AL + CWL = 9

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

4 Clocks

tWTR

tWPRE

tWPST

DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7 WL = AL + CWL = 9

Notes: 1. BL8, AL = 0, CWL = 9, Preamble = 1tCK. 2. DI n (or b) = data-in from column n (or column b).

Time Break

Transitioning Data

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.

Figure 176: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

Bank Group

BGa

Address

Address

Bank Col n

tCCD_S = 4

BGb Bank Col b

DQS_t, DQS_c
DQ

WL = AL + CWL = 10

DES

DES

tWPRE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

4 Clocks

tWTR

tWPST
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7 WL = AL + CWL = 10

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17. 7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 177: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group

T0

T1

T2

T3

T4

T5

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

tCCD_S/L = 5

WL = AL + CWL = 9

DES

WRITE

DES

DES

DES

DES

DES

DES

BGa or BGb Bank Col b

tWPRE

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = AL + CWL = 9

DES

DES

DES

DES

DES

DES

tWR

4 Clocks

tWTR

tWPST DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.

Figure 178: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group

T0

T1

T2

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

WRITE

DES

tCCD_S/L = 6

BGa or BGb

Bank Col b

WL = AL + CWL = 10

DES

DES

DES

DES

DES

DES

DES

DES

tWPRE

tWPRE

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = AL + CWL = 10

DES

DES

DES

DES

DES

tWR

4 Clocks

tWTR

tWPST DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2tCK, tCCD_S/L = 6tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. tCCD_S/L = 5 isn't allowed in 2tCK preamble mode. 7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T20. 8. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.

Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

tCCD_S = 4

4 Clocks

tWTR

Bank Group

BGa

BGb

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

WL = AL + CWL = 9

Bank Col b

tWPRE

tWPST

tWPRE

tWPST

DI DI DI DI n n+1 n+2 n+3 WL = AL + CWL = 9

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC4, AL = 0, CWL = 9, Preamble = 1tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T4. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 180: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

Bank Group

BGa

Address

tCCD_S = 4 BGb

Address

Bank Col n

Bank Col b

DQS_t, DQS_c
DQ

WL = AL + CWL = 10

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

4 Clocks

tWPRE

tWPRE

tWPST

DI DI DI DI n n+1 n+2 n+3 WL = AL + CWL = 10

DI DI DI DI b b+1 b+2 b+3

DES

DES

tWR

tWTR

Time Break

Transitioning Data

Don't Care

Notes:

1. BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18. 7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.

Figure 181: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

tCCD_S = 4

2 Clocks

tWTR

Bank Group

BGa

BGb

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

WL = AL + CWL = 9

Bank Col b

tWPRE

tWPST

tWPRE

tWPST

DI DI DI DI n n+1 n+2 n+3 WL = AL + CWL = 9

DI DI DI DI b b+1 b+2 b+3

Notes: 1. BC4, AL = 0, CWL = 9, Preamble = 1tCK. 2. DI n (or b) = data-in from column n (or column b).

Time Break

Transitioning Data

Don't Care

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T15.

Figure 182: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

Bank Group

BGa

Address

tCCD_S = 4 BGb

4 Clocks

Address

Bank Col n

DQS_t, DQS_c

DQ

WL = AL + CWL = 9

Bank Col b

tWPRE

tWPST

DI DI DI DI DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 WL = AL + CWL = 9

T18

T19

DES

DES

tWR

tWTR

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.

BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

Bank Group

BGa

Address

Address

Bank Col n

tCCD_S = 4

BGb Bank Col b

DQS_t, DQS_c
DQ

WL = AL + CWL = 9

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

4 Clocks

tWTR

tWPRE

tWPST

tWPRE

tWPST

DI DI DI DI n n+1 n+2 n+3 WL = AL + CWL = 9

DI DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6 b+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.

BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.

WRITE Operation Followed by READ Operation

Figure 184: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group

T0

T1

T7

CK_c

CK_t

T8

T9

T10

T11

T12

T13

T14

T15

T16

T24

T25

T26

T27

T28

T29

Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

DES

tWPRE

DES

DES

DES

4 Clocks

DES

DES

READ

tWTR_S = 2 BGb

tWPST

Bank Col b

WL = AL + CWL = 9

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

DES

DES

DES

DES

DES

DES

DES

tRPRE

RL = AL + CL = 11

DI DI DI DI DI DI DI b b+1 b+2 b+3 b+4 b+5 b+6

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0 and READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after the last write data shown at T13.

Figure 185: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T26

T27

T28

T29

CK_c

CK_t

Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

4 Clocks

tWTR_L = 4

WL = AL + CWL = 9

tWPRE

tWPST

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

READ BGa Bank Col b

DES

DES

DES

DES

DES

tRPRE

RL = AL + CL = 11

DI DI DI b b+1 b+2

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0 and READ command at T17.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after the last write data shown at T13.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group

T0 CK_c CK_t
Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T24

T25

T26

T27

T28

T29

DES

DES

DES

DES

tWPRE

DES

DES

DES

4 Clocks

tWPST

DES

DES

READ

DES

DES

tWTR_S = 2

BGb

Bank Col b

DES

DES

DES

tRPRE

DES

DES

tRPST

WL = AL + CWL = 9

DI DI DI DI n n+1 n+2 n+3

RL = AL + CL = 11

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after the last write data shown at T13.

Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group

T0 CK_c CK_t
Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T26

T27

T28

T29

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

READ

DES

DES

DES

DES

DES

4 Clocks

tWTR_L = 4

BGa

tWPRE

tWPST

Bank Col b

tRPRE

WL = AL + CWL = 9

DI DI DI DI n n+1 n+2 n+3

RL = AL + CL = 11

DI DI DI b b+1 b+2

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and READ command at T17.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after the last write data shown at T13.

Figure 188: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T22

T23

T24

T25

T26

T27

T28

T29

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

READ

DES

DES

DES

DES

DES

Bank Group

BGa

Address

2 Clocks

tWTR_S = 2

BGb

Address

Bank Col n

DQS_t, DQS_c

DQ

WL = AL + CWL = 9

tWPRE

tWPST

DI DI DI DI n n+1 n+2 n+3

Bank Col b tRPRE

tRPST

RL = AL + CL = 11

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after the last write data shown at T11.

Figure 189: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T24

T25

T26

T27

T28

T29

CK_c

CK_t

Command WRITE

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ

DES

DES

DES

DES

DES

DES

DES

DES

DES

2 Clocks

tWTR_L = 4

WL = AL + CWL = 9

tWPRE

tWPST

DI DI DI DI n n+1 n+2 n+3

READ BGa Bank Col b

DES

DES

DES

DES

DES

DES

DES

tRPRE

tRPST

RL = AL + CL = 11

DI DI DI DI b b+1 b+2 b+3

Time Break

Transitioning Data

Don't Care

Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1tCK, WRITE preamble = 1tCK.
2. DI b = data-in from column b.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable. 6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T11.
WRITE Operation Followed by PRECHARGE Operation
The minimum external WRITE command to PRECHARGE command spacing is equal to WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The minimum ACT to PRE timing, tRAS, must be satisfied as well.

Figure 190: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T22

T23

T24

T25

T26

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

PRE

DES

WL = AL + CWL = 9

4 Clocks

tWR = 12

tRP

BGa, Bank b Col n
Address

BGa, Bank b (or all)

BC4 (OTF) Opertaion
DQS_t, DQS_c

DQ
BL8 Opertaion DQS_t, DQS_c

DI DI DI DI n n+1 n+2 n+3

DQ

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 191: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T22

T23

T24

T25

T26

CK_c

CK_t

Command WRITE

DES

BGa, Bank b Col n
Address
BC4 (Fixed) Opertaion DQS_t, DQS_c
DQ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

PRE

DES

DES

DES

WL = AL + CWL = 9

2 Clocks

tWR = 12

tRP

BGa, Bank b (or all)

DI DI DI DI n n+1 n+2 n+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.

Figure 192: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T22

T23

T24

T25

T26

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

WL = AL + CWL = 9

4 Clocks

tWR = 12

tRP

BGa, Bank b Col n
Address

BC4 (OTF) Opertaion
DQS_t, DQS_c

DQ
BL8 Opertaion DQS_t, DQS_c

DI DI DI DI n n+1 n+2 n+3

DQ

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.

Figure 193: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble

T0

T1

T2

T3

T4

T7

T8

T9

T10

T11

T12

T13

T14

T22

T23

T24

T25

T26

CK_c

CK_t

Command WRITE

DES

BGa, Bank b Col n
Address
BC4 (Fixed) Opertaion DQS_t, DQS_c
DQ

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

WL = AL + CWL = 9

2 Clocks

tWR = 12

tRP

DI DI DI DI n n+1 n+2 n+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.

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WRITE Operation with WRITE DBI Enabled

4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 194: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

WL = AL + CWL = 9

4 Clocks

tWR tWTR

Address BGa

Address

Bank, Col n

BC4 (OTF) Opertaion

DQS_t, DQS_c

DQ

DI DI DI DI n n+1 n+2 n+3

DBI_n
BL8 Opertaion DQS_t, DQS_c
DQ

DI DI DI DI n n+1 n+2 n+3 DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

DBI_n

DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7

Transitioning Data

Don't Care

Notes:

1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled.
6. The write recovery time (tWR_DBI) is referenced from the first rising clock edge after the last write data shown at T13.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 195: WRITE (BC4-Fixed) with 1tCK Preamble and DBI

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

WL = AL + CWL = 9

2 Clocks

tWR tWTR

Address BGa

Address

Bank, Col n

BC4 (Fixed) Opertaion

DQS_t, DQS_c

DQ

DI DI DI DI n n+1 n+2 n+3

DBI_n

DI DI DI DI n n+1 n+2 n+3

Transitioning Data

Don't Care

Notes:

1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
bled.

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WRITE Operation with CA Parity Enabled

4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 196: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group

T0

T1

T2

T3

T4

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

CK_c

CK_t

Command WRITE

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

tCCD_S = 4

4 Clocks

tWTR

Bank Group

BGa

BGb

Address

Address

Bank Col n

Bank Col b

Parity Valid
DQS_t, DQS_c
DQ

Valid WL = PL + AL + CWL = 13

tWPRE

tWPST

DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7 WL = PL + AL + CWL = 13

Time Break

Transitioning Data

Don't Care

Notes:

1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1tCK. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-
mands at T0 and T4. 5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
ble. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.

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WRITE Operation with Write CRC Enabled

4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 197: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group

T0

T1

T2

T3

T4

T5

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ x4, BL = 8
DQ x8/X16, BL = 8
DQ x4, BC = 4 (OTF)
DQ x8/X16, BC = 4 (OTF)

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

tCCD_S/L = 5

4 Clocks

tWTR

BGa or BGb

Bank Col b

tWPRE

tWPST

WL = AL + CWL = 9

DI n

DI DI DI DI DI DI DI n+1 n+2 n+3 n+4 n+5 n+6 n+7

CRC

CRC

DI b

DI DI DI DI DI DI DI b+1 b+2 b+3 b+4 b+5 b+6 b+7

CRC

CRC

WL = AL + CWL = 9

DI n

DI DI DI DI DI DI DI n+1 n+2 n+3 n+4 n+5 n+6 n+7

CRC

DI b

DI DI DI DI DI DI DI b+1 b+2 b+3 b+4 b+5 b+6 b+7

CRC

DI DI DI DI n n+1 n+2 n+3

CRC CRC

DI DI DI DI b b+1 b+2 b+3

CRC CRC

DI DI DI DI n n+1 n+2 n+3

CRC

DI DI DI DI b b+1 b+2 b+3

CRC

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T5. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable. 7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 198: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group

T0

T1

T2

T3

T4

T5

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR

tCCD_S/L = 5

2 Clocks

tWTR

Bank Group

BGa

Address

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c
DQ x4, BC = 4 (Fixed)

DQ x8/X16, BC = 4 (Fixed)

WL = AL + CWL = 9

Bank Col b

tWPRE

DI n WL = AL + CWL = 9

DI DI DI n+1 n+2 n+3

DI DI DI DI n n+1 n+2 n+3

CRC CRC

DI DI DI DI b b+1 b+2 b+3

CRC

DI DI DI DI b b+1 b+2 b+3

tWPST CRC CRC CRC

Time Break

Transitioning Data

Don't Care

Notes:

1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T16.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 199: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

&.BF

&.BW

&RPPDQG :5,7(

%DQN*URXS $GGUHVV

%*D

$GGUHVV

%DQN &ROQ

'(6

'(6

W&&'B6/ 

'46BW '46BF

'4[ %/ 
'4[; %/ 
'4[ %& 27)
'4[; %& 27)

:5,7(

'(6

'(6

'(6

'(6

'(6

'(6

'(6

'(6

%*DRU %*E %DQN &ROE

W:35(

:/ $/&:/  :/ $/&:/ 

'Q, Q', Q', Q', Q', Q', Q', Q', &5& &5& 'Q, Q', Q', Q', Q', Q', Q', Q', &5&

'Q, Q', Q', Q',

&5& &5&

'Q, Q', Q', Q',

&5&

'(6

'(6

'(6

'(6

&ORFNV

'(6

'(6 W:5 W:75

W:367

'E, E', E', E', E', E', E', E', &5& &5&

'E, E', E', E', E', E', E', E', &5&

'E, E', E', E',

&5& &5&

'E, E', E', E',

&5&

7LPH%UHDN

7UDQVLWLRQLQJ'DWD

'RQ¶W&DUH

Notes:

1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 6tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at
these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T6. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable. 7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T19.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 200: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group

T0

T1

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

CK_c

CK_t

Command WRITE

DES

WRITE

DES

DES

DES

DES

DES

DES

DES

DES

Bank Group Address

tCCD_S/L = 7

BGa

BGa or BGb

Address

Bank Col n

DQS_t, DQS_c

DQ x4, BL = 8
DQ x8/X16, BL = 8
DQ x4, BC = 4 (OTF)

Bank Col b

tWPRE

WL = AL + CWL = 10 WL = AL + CWL = 10

DI n

DI DI DI DI DI DI DI n+1 n+2 n+3 n+4 n+5 n+6 n+7

CRC

CRC

DI n

DI DI DI DI DI DI DI n+1 n+2 n+3 n+4 n+5 n+6 n+7

CRC

DI DI DI DI n n+1 n+2 n+3

CRC CRC

DQ x8/X16, BC = 4 (OTF)

DI DI DI DI n n+1 n+2 n+3

CRC

DES tWPRE

DES

DES

DES

DES

DES

DES

tWR

4 Clocks

tWTR

tWPST

DI b

DI DI DI DI DI DI DI b+1 b+2 b+3 b+4 b+5 b+6 b+7

CRC

CRC

DI b

DI DI DI DI DI DI DI b+1 b+2 b+3 b+4 b+5 b+6 b+7

CRC

DI DI DI DI b b+1 b+2 b+3

CRC CRC

DI DI DI DI b b+1 b+2 b+3

CRC

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2tCK, tCCD_S/L = 7tCK (see Note 7).
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T7.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T7.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable.
7. tCCD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCCD_S/L allowed in 1tCK preamble mode would have been 6 clocks.
8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T21.
9. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.

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4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation

Figure 201: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group

T0

T1

T2

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

CK_c

CK_t

Command WRITE

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

tWR_CRC_DM

4 Clocks

tWTR_S_CRC_DM/tWTR_L_CRC_DM

Bank Group

BGa

Address

Address

Bank Col n

DQS_t, DQS_c

DQ x4, BL = 8

tWPRE

tWPST

WL = AL + CWL = 9

DI n

DI DI DI DI DI DI DI n+1 n+2 n+3 n+4 n+5 n+6 n+7

CRC

CRC

DQ x8/X16, BL = 8
DMx4/x8/x16 BL = 8
DQ x4, BC = 4 (OTF/Fixed)

DI n

DI DI DI DI DI DI DI n+1 n+2 n+3 n+4 n+5 n+6 n+7

CRC

DM DM DM DM DM DM DM DM n n+1 n+2 n+3 n+4 n+5 n+6 n+7

DI DI DI DI n n+1 n+2 n+3

CRC CRC

DQ x8/X16, BC = 4 (OTF/Fixed)

DI DI DI DI n n+1 n+2 n+3

CRC

DM x4/x8/x16 BC = 4 (OTF / Fixed)

DM DM DM DM n n+1 n+2 n+3

Time Break

Transitioning Data

Don't Care

Notes:

1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Enable.
7. The write recovery time (tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/ tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write data shown at T13.

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4Gb: x4, x8, x16 DDR4 SDRAM Write Timing Violations

Write Timing Violations

Motivation

Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the device works properly. However, for certain minor violations, it is desirable that the device is guaranteed not to "hang up" and that errors are limited to that specific operation. A minor violation does not include a major timing violation (for example, when a DQS strobe misses in the tDQSCK window).
For the following, it will be assumed that there are no timing violations with regard to the WRITE command itself (including ODT, and so on) and that it does satisfy all timing requirements not mentioned below.

Data Setup and Hold Violations
If the data-to-strobe timing requirements (tDS, tDH) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location addressed with this WRITE command.
In the example, the relevant strobe edges for WRITE Burst A are associated with the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, and T8.5.
Subsequent reads from that location might result in unpredictable read data; however, the device will work properly otherwise.

Strobe-to-Strobe and Strobe-to-Clock Violations
If the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data; however, the device will work properly otherwise with the following constraints:
· Both write CRC and data burst OTF are disabled; timing specifications other than tDQSH, tDQSL, tWPRE, tWPST, tDSS, tDSH, tDQSS are not violated.
· The offending write strobe (and preamble) arrive no earlier or later than six DQS transition edges from the WRITE latency position.
· A READ command following an offending WRITE command from any open bank is allowed.
· One or more subsequent WR or a subsequent WRA (to same bank as offending WR) may be issued tCCD_L later, but incorrect data could be written. Subsequent WR and WRA can be either offending or non-offending writes. Reads from these writes may provide incorrect data.
· One or more subsequent WR or a subsequent WRA (to a different bank group) may be issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA can be either offending or non-offending writes. Reads from these writes may provide incorrect data.
· After one or more precharge commands (PRE or PREA) are issued to the device after an offending WRITE command and all banks are in precharged state (idle state), a subsequent, non-offending WR or WRA to any open bank will be able to write correct data.

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4Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands
ZQ CALIBRATION Commands
A ZQ CALIBRATION command is used to calibrate DRAM RON and ODT values. The device needs a longer time to calibrate the output driver and on-die termination circuits at initialization and a relatively smaller time to perform periodic calibrations.
The ZQCL command is used to perform the initial calibration during the power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM and, after calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM I/O, which is reflected as an updated output driver and ODT values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after reset are allowed a timing period of tZQoper.
The ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5% (ZQ correction) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver and ODT Voltage and Temperature Sensitivity tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdrift_rate) and voltage (Vdrift_rate) drift rates that the device is subjected to in the application, is illustrated. The interval could be defined by the following formula:

ZQcorrection (Tsense x Tdrift_rate) + (Vsense x Tdrift_rate)
Where Tsense = MAX(dRTTdT, dRONdTM) and Vsense = MAX(dRTTdV, dRONdVM) define the temperature and voltage sensitivities.
For example, if Tsens = 1.5%/°C, Vsens = 0.15%/mV, Tdriftrate = 1 °C/sec and Vdriftrate = 15 mV/sec, then the interval between ZQCS commands is calculated as:

0.5

= 0.133 §128ms

(1.5 × 1) + (0.15 × 15)

No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output driver and on-die termination values. After DRAM calibration is achieved, the device should disable the ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ CALIBRATION commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self refresh exit, the device will not perform an I/O cali-

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4Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands
bration without an explicit ZQ CALIBRATION command. The earliest possible time for a ZQ CALIBRATION command (short or long) after self refresh exit is tXS, tXS_Abort, or tXS_FAST depending on operation mode.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS between the devices.

Figure 202: ZQ Calibration Timing

T0 CK_c CK_t

T1

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tc0

Tc1

Tc2

Command ZQCL

DES

DES

DES

Valid

Valid

ZQCS

DES

DES

DES

Valid

Address

Valid

Valid

Valid

A10

Valid

Valid

Valid

CKE
Note 1
Note 2
ODT

Valid

Valid

Valid

Valid

Valid Valid

DQ Bus
Note 3

High-Z or RTT(Park) tZQinit_tZQoper

Activities

High-Z or RTT(Park) tZQCS

Activities

Time Break

Don't Care

Notes:

1. CKE must be continuously registered HIGH during the calibration procedure. 2. During ZQ calibration, the ODT signal must be held LOW and DRAM continues to pro-
vide RTT_PARK. 3. All devices connected to the DQ bus should be High-Z during the calibration procedure.

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4Gb: x4, x8, x16 DDR4 SDRAM On-Die Termination

On-Die Termination
The on-die termination (ODT) feature enables the device to change termination resistance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control pin, WRITE command, or default parking value with MR setting. For the x16 configuration, ODT is applied to each UDQ, LDQ, UDQS, LDQS, UDM_n/UDBI_n, and LDM_n/ LDBI_n signal. The ODT feature is designed to improve the signal integrity of the memory channel by allowing the DRAM controller to independently change termination resistance for any or all DRAM devices. If DBI read mode is enabled while the DRAM is in standby, either DM mode or DBI write mode must also be enabled if RTT(NOM) or RTT(Park) is desired. More details about ODT control modes and ODT timing modes can be found further along in this document.
The ODT feature is turned off and not supported in self refresh mode.
Figure 203: Functional Representation of ODT

To other circuitry such as RCV, . . .

ODT
RTT Switch

VDDQ

DQ, DQS, DM, TDQS

The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTT is determined by the settings of mode register bits (see Mode Register). The ODT pin will be ignored if the mode register MR1 is programmed to disable RTT(NOM) [MR1[10,9,8] = 0,0,0] and in self refresh mode.
ODT Mode Register and ODT State Table
The ODT mode of the DDR4 device has four states: data termination disable, RTT(NOM), RTT(WR), and RTT(Park). The ODT mode is enabled if any of MR1[10:8] (RTT(NOM)), MR2[11:9] (RTT(WR)), or MR5[8:6] (RTT(Park)) are non-zero. When enabled, the value of RTT is determined by the settings of these bits.
RTT control of each RTT condition is possible with a WR or RD command and ODT pin.
· RTT(WR): The DRAM (rank) that is being written to provide termination regardless of ODT pin status (either HIGH or LOW).
· RTT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT is disabled by MR1).
· RTT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned on.
· The Termination State Table that follows shows various interactions.
The RTT values have the following priority:
· Data termination disable · RTT(WR) · RTT(NOM) · RTT(Park)

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4Gb: x4, x8, x16 DDR4 SDRAM ODT Mode Register and ODT State Table

Table 70: Termination State Table

Case A4 B5 C6
D6

RTT(Park) Disabled

RTT(NOM)1 Disabled

RTT(WR)2 Disabled

ODT Pin Don't Care

ODT READS3 ODT Standby ODT WRITES Off (High-Z) Off (High-Z) Off (High-Z)

Enabled Disabled
Enabled

Disabled Enabled
Enabled

Enabled Disabled Enabled Disabled
Enabled
Disabled
Enabled

Don't Care Don't Care Don't Care
Low High Low High Low High Low High

Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z) Off (High-Z)

Off (High-Z) RTT(Park) RTT(Park)
Off (High-Z) RTT(NOM)
Off (High-Z) RTT(NOM) RTT(Park) RTT(NOM) RTT(Park) RTT(NOM)

RTT(WR) RTT(Park) RTT(WR) Off (High-Z) RTT(NOM) RTT(WR) RTT(WR) RTT(Park) RTT(NOM) RTT(WR) RTT(WR)

Notes:

1. If RTT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power. 2. If RTT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period
time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in the Dynamic ODT section.
3. When a READ command is executed, the DRAM termination state will be High-Z for a defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in the ODT During Read section.
4. Case A is generally best for single-rank memories.
5. Case B is generally best for dual-rank, single-slotted memories.
6. Case C and Case D are generally best for multi-slotted memories.

ODT Read Disable State Table
Upon receiving a READ command, the DRAM driving data disables ODT after RL - (2 or 3) clock cycles, where 2 = 1tCK preamble mode and 3 = 2tCK preamble mode. ODT stays off for a duration of BL/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1tCK preamble mode, 3 = 2tCK preamble mode, 0 = CRC disabled, and 1 = CRC enabled.

Table 71: Read Termination Disable Window

Preamble 1tCK
2tCK

CRC Disabled Enabled Disabled Enabled

Start ODT Disable After Read RL - 2 RL - 2 RL - 3 RL - 3

Duration of ODT Disable BL/2 + 2 BL/2 + 3 BL/2 + 3 BL/2 + 4

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4Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode

Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes include the following:
· Any bank active with CKE HIGH · Refresh with CKE HIGH · Idle mode with CKE HIGH · Active power-down mode (regardless of MR1 bit A10) · Precharge power-down mode
In synchronous ODT mode, RTT(NOM) will be turned on DODTLon clock cycles after ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after ODT is registered LOW by a rising clock edge. The ODT latency is determined by the programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity latency (PL), as well as the programmed state of the preamble.
ODT Latency and Posted ODT
The ODT latencies for synchronous ODT mode are summarized in the table below. For details, refer to the latency definitions.

Table 72: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200

Applicable when write CRC is disabled

Symbol

Parameter

DODTLon

Direct ODT turn-on latency

DODTLoff

Direct ODT turn-off latency

RODTLoff READ command to internal ODT turn-off latency

RODTLon4 READ command to RTT(Park) turn-on latency in BC4-fixed

RODTLon8 READ command to RTT(Park) turn-on latency in BL8/BC4-OTF

ODTH4

ODT Assertion time, BC4 mode

ODTH8

ODT Assertion time, BL8 mode

1tCK Preamble CWL + AL + PL - 2 CWL + AL + PL - 2 CL + AL + PL - 2
RODTLoff + 4
RODTLoff + 6
4 6

2tCK Preamble CWL + AL + PL - 3 CWL + AL + PL - 3 CL + AL + PL - 3
RODTLoff + 5
RODTLoff + 7
5 7

Unit tCK

Timing Parameters
In synchronous ODT mode, the following parameters apply:
· DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX). · tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew
between different termination values. These timing parameters apply to both the synchronous ODT mode and the data termination disable mode.
When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or ODTH8 (BL = 8) is satisfied. If write CRC mode or 2tCK preamble mode is enabled, ODTH should be adjusted to account for it. ODTHx is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of a WRITE command.

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4Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode

Figure 204: Synchronous ODT Timing with BL8

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7 

diff_CK

Command

ODT DRAM_RTT

DODTLon = WL - 2 RTT(Park)

tADC (MAX) tADC (MIN)

DODTLoff = WL - 2 RTT(NOM)

tADC (MAX) tADC (MIN) RTT(Park)

Transitioning
Notes: 1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL + PL + CWL - 2 = 7.
2. ODT must be held HIGH for at least ODTH8 after assertion (T1).

Figure 205: Synchronous ODT with BC4

T0

T1

T2

T3

T4

T5

T18

T19

T20 T21

T22

T23

T36

T37

T38

T39

T40

T41

42

diff_CK

Command

ODTH4

WRS4

ODT

DRAM_RTT

DODTLon = CWL - 2

RTT(Park)

tADC (MAX) tADC (MIN)

DODTLoff = WL - 2 ODTLcnw= WL - 2 ODTLcwn4 = ODTLcnw + 4

tADC (MAX) tADC (MIN) RTT(NOM)

RTT(Park)

tADC (MAX) tADC (MIN)
RTT(WR)

tADC (MAX) tADC (MIN)
RTT(Park)

Transitioning
Notes: 1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw = AL + PL+ CWL - 2 = 17.
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).

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4Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode
ODT During Reads
Because the DRAM cannot terminate with RTT and drive with RON at the same time, RTT may nominally not be enabled until the end of the postamble as shown in the example below. At cycle T26 the device turns on the termination when it stops driving, which is determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC (MIN) timing may apply. If the DRAM stops driving late (that is, tHZ is late), then the DRAM complies with tADC (MAX) timing.
Using CL = 11 as an example for the figure below: PL = 0, AL = CL - 1 = 10, RL = PL + AL + CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK preamble.

Figure 206: ODT During Reads

7

7

7

7

7

7

7

7 7

7

7

7

7

7

7

7

7

7

7

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4Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT

Dynamic ODT

In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the device can be changed without issuing an MRS command. This requirement is supported by the dynamic ODT feature.

Functional Description
Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.
· Three RTT values are available: RTT(NOM), RTT(WR), and RTT(Park). ­ The value for RTT(NOM) is preselected via bits MR1[10:8]. ­ The value for RTT(WR) is preselected via bits MR2[11:9]. ­ The value for RTT(Park) is preselected via bits MR5[8:6].
· During operation without WRITE commands, the termination is controlled as follows: ­ Nominal termination strength RTT(NOM) or RTT(Park) is selected. ­ RTT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and DODTLoff, and RTT(Park) is on when ODT is LOW.
· When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is registered, and if dynamic ODT is enabled, the termination is controlled as follows: ­ Latency ODTLcnw after the WRITE command, termination strength RTT(WR) is selected. ­ Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the WRITE command, termination strength RTT(WR) is de-selected.
One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4, depending on write CRC mode and/or 2tCK preamble enablement.
The following table shows latencies and timing parameters relevant to the on-die termination control in dynamic ODT mode. The dynamic ODT feature is not supported in DLL-off mode. An MRS command must be used to set RTT(WR) to disable dynamic ODT externally (MR2[11:9] = 000).

Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled)

Name and Description

Abbr. Defined from Defined to

ODT latency for change from RTT(Park)/ RTT(NOM) to RTT(WR)
ODT latency for change from RTT(WR) to RTT(Park)/RTT(NOM) (BC = 4)
ODT latency for change from RTT(WR) to RTT(Park)/RTT(NOM) (BL = 8)

ODTLc Registering exnw ternal WRITE command
ODTLc Registering exwn4 ternal WRITE
command
ODTLc Registering exwn8 ternal WRITE
command

Change RTT strength from
RTT(Park)/ RTT(NOM) to
RTT(WR)
Change RTT strength from
RTT(WR) to RTT(Park)/ RTT(NOM)
Change RTT strength from
RTT(NOM) to RTT(WR)

1600/1866/ 2133/2400

2666

ODTLcnw = WL - 2

2933/3200

Unit tCK

ODTLcwn4 = 4 + ODTLcnw

tCK

ODTLcwn8 = 6 + ODTLcnw

tCK (AVG)

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4Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT

Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) (Continued)

Name and Description
RTT change skew

Abbr. Defined from

tADC

ODTLcnw ODTLcwn

Defined to RTT valid

1600/1866/ 2133/2400
tADC (MIN) = 0.30
tADC (MAX) = 0.70

2666
tADC (MIN) = 0.28
tADC (MAX) = 0.72

2933/3200 Unit

tADC (MIN) = tCK

0.26

(AVG)

tADC (MAX) =

0.74

Table 74: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix

Symbol ODTLcnw1 ODTLcwn4 ODTLcwn8

1tCK Parameter

CRC Off

CRC On

WL - 2

WL - 2

ODTLcnw + 4

ODTLcnw + 7

ODTLcnw + 6

ODTLcnw + 7

2tCK Parameter

CRC Off

CRC On

WL - 3

WL - 3

ODTLcnw + 5

ODTLcnw + 8

ODTLcnw + 7

ODTLcnw + 8

Note: 1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).

Unit tCK

Figure 207: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)

T0

T1

T2

T5

T6

T7

T8

T9

T10

T11

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

diff_CK

WR Command
ODT

DODTLon = WL - 2

DODTLoff = WL - 2

tADC (MAX)

tADC (MAX)

tADC (MAX)

tADC (MAX)

RTT

RTT(Park)

RTT(WR)

RTT(Park)

RTT(NOM)

RTT(Park)

ODTLcnw

tADC (MIN) ODTLcwn

tADC (MIN)

tADC (MIN)

tADC (MIN)

Transitioning
Notes: 1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble). 2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled.

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4Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT

Figure 208: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)

T0

T1

T2

T5

T6

T7

T9

T10

T11

T12

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

diff_CK

WR Command
ODT

ODTLcnw

ODTLcwn8

tADC (MAX)

tADC (MAX)

tADC (MAX)

RTT

RTT_NOM

RTT_WR

RTT_NOM

RTT_PARK

tADC (MIN)

tADC (MIN) DODTLoff = CWL -2

tADC (MIN)

Note: 1. Behavior with WR command issued while ODT is registered HIGH.

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4Gb: x4, x8, x16 DDR4 SDRAM Asynchronous ODT Mode
Asynchronous ODT Mode
Asynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asynchronous ODT timing mode, the internal ODT command is not delayed by either additive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)). In asynchronous ODT mode, two timing parameters apply: tAONAS (MIN/MAX), and tAOFAS (MIN/MAX).
RTT(NOM) Turn-on Time
· Minimum RTT(NOM) turn-on time (tAONAS [MIN]) is when the device termination circuit leaves RTT(Park) and ODT resistance begins to turn on.
· Maximum RTT(NOM) turn-on time (tAONAS [MAX]) is when the ODT resistance has reached RTT(NOM).
· tAONAS (MIN) and tAONAS (MAX) are measured from ODT being sampled HIGH.
RTT(NOM) Turn-off Time
· Minimum RTT(NOM) turn-off time (tAOFAS [MIN]) is when the device's termination circuit starts to leave RTT(NOM).
· Maximum RTT(NOM) turn-off time (tAOFAS [MAX]) is when the on-die termination has reached RTT(Park).
· tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW.

Figure 209: Asynchronous ODT Timings with DLL Off

T0

T1

T2

T3

T4

T5

T6

Ti

Ti + 1 Ti + 2 Ti + 3 Ti + 4 Ti + 5 Ti + 6

Ta

Tb

diff_CK

CKE ODT

tIH

tIS

tIH

tIS

RTT

RTT(Park)

tAONAS (MAX) tAONAS (MIN)

RTT(NOM)

tAONAS (MIN)
tAONAS (MAX)
Transitioning

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Specifications

Electrical Specifications

Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Although "unlimited" row accesses to the same row is allowed within the refresh period; excessive row accesses to the same row over a long term can result in degraded operation.

Table 75: Absolute Maximum Ratings

Symbol VDD VDDQ VPP
VIN, VOUT TSTG

Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VPP pin relative to VSS Voltage on any pin relative to VSS Storage temperature

Min ­0.4 ­0.4 ­0.4 ­0.4 ­55

Max 1.5 1.5 3.0 1.5 150

Unit V V V V °C

Notes 1 1 3
2

Notes:

1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be 300mV.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to the JESD51-2 standard.
3. VPP must be equal to or greater than VDD/VDDQ at all times when powered.

DRAM Component Operating Temperature Range
Operating temperature, TOPER, is the case surface temperature on the center/top side of the DRAM. For measurement conditions, refer to the JEDEC document JESD51-2.

Table 76: Temperature Range

Symbol TOPER

Parameter Normal operating temperature range Extended temperature range (optional)

Min -40 >85

Max 85 105

Unit °C °C

Notes 1 2

Notes:

1. The normal temperature range specifies the temperatures at which all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to 85°C under all operating conditions for the commercial offering; The industrial and automotive temperature offerings allow the case temperature to go below 0°C to -40°C.
2. Some applications require operation of the commercial, industrial, and automotive temperature DRAMs in the extended temperature range (between 85°C and 105°C case temperature). Full specifications are supported in this range, but the following additional conditions apply:

· Refer to tREFI and tRFC parameters table for tREFI requirements when operating above 85°C
· If SELF REFRESH operation is required in the extended temperature range, it is mandatory to use either the manual self refresh mode with extended temperature range ca-

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Operating Conditions
pability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode (MR2 [6] = 1 and MR2 [7] = 1).

Electrical Characteristics ­ AC and DC Operating Conditions
Supply Operating Conditions

Table 77: Recommended Supply Operating Conditions

Symbol VDD VDDQ VPP

Parameter Supply voltage Supply voltage for output Wordline supply voltage

Min 1.14 1.14 2.375

Rating Typ 1.2 1.2 2.5

Max 1.26 1.26 2.750

Unit V V V

Notes 1, 2, 3, 4, 5
1, 2, 6 7

Notes:

1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600 V/ms, 20 MHz band-limited measurement.
4. VDD ramp time from 300mV to VDD,min shall be no longer than 200ms.
5. A stable valid VDD level is a set DC level (0 Hz to 250 KHz) and must be no less than VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the noise doesn't alter VDD to less than VDD,min or greater than VDD,max.
6. A stable valid VDDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC
level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.
7. A stable valid VPP level is a set DC level (0 Hz to 250 KHz) and must be no less than VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±120mV (greater than 250 KHz) is allowed on VPP provided the noise doesn't alter VPP to less than VPP,min or greater than VPP,max.

Table 78: VDD Slew Rate

Symbol VDD_sl VDD_on

Min 0.004
­

Max 600 200

Unit V/ms ms

Notes:

1. Measurement made between 300mV and 80% VDD (minimum level). 2. The DC bandwidth is limited to 20 MHz. 3. Maximum time to ramp VDD from 300 mV to VDD minimum.

Notes 1, 2 3

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Operating Conditions

Leakages

Table 79: Leakages

Condition

Symbol

Min

Max

Input leakage (excluding ZQ and TEN)

IIN

­2

2

ZQ leakage

IZQ

­50

10

TEN leakage

ITEN

­6

10

VREFCA leakage

IVREFCA

­2

2

Output leakage: VOUT = VDDQ

IOZpd

­

10

Output leakage: VOUT = VSSQ

IOZpu

­50

­

Notes:

1. Input under test 0V < VIN < 1.1V. 2. Additional leakage due to weak pull-down. 3. VREFCA = VDD/2, VDD at valid level after initialization. 4. DQs are disabled. 5. ODT is disabled with the ODT input HIGH.

Unit A A A A A A

Notes 1 1
1, 2 3 4
4, 5

VREFCA Supply

VREFCA is to be supplied to the DRAM and equal to VDD/2. The V REFCA is a reference supply input and therefore does not draw biasing current.
The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA are illustrated in the figure below. The figure shows a valid reference voltage V REF(t) as a function of time (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long period of time (1 second). This average has to meet the MIN/MAX requirements. Furthermore, VREF(t) may temporarily deviate from VREF(DC) by no more than ±1% VDD for the AC-noise limit.

Figure 210: VREFDQ Voltage Range

Voltage

VREF(DC)

VREF AC-noise

VREF(t)

VDD
VREF(DC) MAX VDD/2 VREF(DC) MIN
VSS

Time

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Operating Conditions

The voltage levels for setup and hold time measurements are dependent on VREF. VREF is understood as VREF(DC), as defined in the above figure. This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW level, and therefore, the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on V REF up to the specified limit (±1% of VDD) are included in DRAM timings and their associated deratings.
VREFDQ Supply and Calibration Ranges
The device internally generates its own VREFDQ. DRAM internal VREFDQ specification parameters: voltage range, step size, VREF step time, VREF full step time, and VREF valid level are used to help provide estimated values for the internal VREFDQ and are not pass/fail limits. The voltage operating range specifies the minimum required range for DDR4 SDRAM devices. The minimum range is defined by V REFDQ,min and VREFDQ,max. A calibration sequence should be performed by the DRAM controller to adjust VREFDQ and optimize the timing and voltage margin of the DRAM data input receivers.

Table 80: VREFDQ Specification

Parameter

Symbol

Min

Typ

Max

Unit Notes

Range 1 VREFDQ operating points Range 2 VREFDQ operating points VREF step size VREF set tolerance
VREF step time VREF valid tolerance

VREFDQ R1 VREFDQ R2 VREF,step VREF,set_tol
VREF,time VREF_val_tol

60% 45% 0.5% ­1.625% ­0.15%
­ ­0.15%

­ ­ 0.65% 0% 0% ­ 0%

92% 77% 0.8% 1.625% 0.15% 150 0.15%

VDDQ VDDQ VDDQ VDDQ VDDQ
ns VDDQ

1, 2 1, 2
3 4, 5, 6 4, 7, 8 9, 10, 11
12

Notes: 1. VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V. 2. DRAM range 1 or range 2 is set by the MRS6[6]6.
3. VREF step size increment/decrement range. VREF at DC level. 4. VREF,new = VREF,old ±n × VREF,step; n = number of steps. If increment, use "+," if decrement,
use "-."
5. For n >4, the minimum value of VREF setting tolerance = VREF,new - 1.625% × VDDQ. The maximum value of VREF setting tolerance = VREF,new + 1.625% × VDDQ.
6. Measured by recording the MIN and MAX values of the VREF output over the range, drawing a straight line between those points, and comparing all other VREF output settings to that line.
7. For n 4, the minimum value of VREF setting tolerance = VREF,new - 0.15% × VDDQ. The maximum value of VREF setting tolerance = VREF,new + 0.15% × VDDQ.
8. Measured by recording the MIN and MAX values of the VREF output across four consecutive steps (n = 4), drawing a straight line between those points, and comparing all VREF output settings to that line.
9. Time from MRS command to increment or decrement one step size for VREF. 10. Time from MRS command to increment or decrement more than one step size up to the
full range of VREF. 11. If the VREF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and
an additional +15 ns/pF of DQ bus loading.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Operating Conditions

VREFDQ Ranges

12. Only applicable for DRAM component-level test/characterization purposes. Not applicable for normal mode of operation. VREF valid qualifies the step times, which will be characterized at the component level.
MR6[6] selects range 1 (60% to 92.5% of VDDQ) or range 2 (45% to 77.5% of VDDQ), and MR6[5:0] sets the VREFDQ level, as listed in the following table. The values in MR6[6:0] will update the VDDQ range and level independent of MR6[7] setting. It is recommended MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommended MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a calibration routine.

Table 81: VREFDQ Range and Levels

MR6[5:0] 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001

MR6[6] 0 = Range 1 60.00% 60.65% 61.30% 61.95% 62.60% 63.25% 63.90% 64.55% 65.20% 65.85% 66.50% 67.15% 67.80% 68.45% 69.10% 69.75% 70.40% 71.05% 71.70% 72.35% 73.00% 73.65% 74.30% 74.95% 75.60% 76.25%

MR6[6] 1 = Range 2 45.00% 45.65% 46.30% 46.95% 47.60% 48.25% 48.90% 49.55% 50.20% 50.85% 51.50% 52.15% 52.80% 53.45% 54.10% 54.75% 55.40% 56.05% 56.70% 57.35% 58.00% 58.65% 59.30% 59.95% 60.60% 61.25%

MR6[5:0] 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 11 0000 11 0001 11 0010

MR6[6] 0 = Range 1

MR6[6] 1 = Range 2

76.90%

61.90%

77.55%

62.55%

78.20%

63.20%

78.85%

63.85%

79.50%

64.50%

80.15%

65.15%

80.80%

65.80%

81.45%

66.45%

82.10%

67.10%

82.75%

67.75%

83.40%

68.40%

84.05%

69.05%

84.70%

69.70%

85.35%

70.35%

86.00%

71.00%

86.65%

71.65%

87.30%

72.30%

87.95%

72.95%

88.60%

73.60%

89.25%

74.25%

89.90%

74.90%

90.55%

75.55%

91.20%

76.20%

91.85%

76.85%

92.50%

77.50%

11 0011 to 11 1111 are reserved

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Electrical Characteristics ­ AC and DC Single-Ended Input Measurement Levels
RESET_n Input Levels

Table 82: RESET_n Input Levels (CMOS)

Parameter AC input high voltage DC input high voltage DC input low voltage AC input low voltage Rising time RESET pulse width after power-up RESET pulse width during power-up

Symbol
VIH(AC)_RESET VIH(DC)_RESET VIL(DC)_RESET VIL(AC)_RESET
tR_RESET tPW_RESET_S tPW_RESET_L

Min 0.8 × VDD 0.7 × VDD
VSS VSS ­ 1 200

Max VDD VDD 0.3 × VDD 0.2 × VDD
1 ­ ­

Unit V V V V s s s

Note 1 2 3 4 5
6, 7 6

Notes:

1. Overshoot should not exceed the VIN shown in the Absolute Maximum Ratings table. 2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n signal LOW.
3. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RESET during tPW_RESET, otherwise the DRAM may not be reset.
4. Undershoot should not exceed the VIN shown in the Absolute Maximum Ratings table. 5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-
gated as much as possible.
6. RESET is destructive to data contents.
7. See RESET Procedure at Power Stable Condition figure.

Figure 211: RESET_n Input Slew Rate Definition

VIH(AC)_RESET,min VIH(DC)_RESET,min

tPW_RESET

VIL(DC)_RESET,max VIL(AC)_RESET,max

Command/Address Input Levels

tR_RESET

Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400

Parameter AC input high voltage DC input high voltage

Symbol VIH(AC) VIH(DC)

Min VREF + 100 VREF + 75

Max VDD5 VDD

Unit mV mV

Note 1, 2, 3
1, 2

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Measurement Levels

Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)

Parameter DC input low voltage AC input low voltage Reference voltage for CMD/ADDR inputs

Symbol VIL(DC) VIL(AC)
VREFFCA(DC)

Min VSS VSS5 0.49 × VDD

Max VREF - 75 VREF - 100 0.51 × VDD

Unit mV mV V

Note 1, 2 1, 2, 3
4

Notes:

1. For input except RESET_n. VREF = VREFCA(DC). 2. VREF = VREFCA(DC). 3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV). 5. Refer to "Overshoot and Undershoot Specifications."

Table 84: Command and Address Input Levels: DDR4-2666

Parameter

Symbol

Min

Max

Unit

Note

AC input high voltage

VIH(AC)

VREF + 90

VDD5

mV

1, 2, 3

DC input high voltage

VIH(DC)

VREF + 65

VDD

mV

1, 2

DC input low voltage

VIL(DC)

VSS

VREF - 65

mV

1, 2

AC input low voltage

VIL(AC)

VSS5

VREF - 90

mV

1, 2, 3

Reference voltage for CMD/ADDR inputs

VREFFCA(DC)

0.49 × VDD

0.51 × VDD

V

4

Notes:

1. For input except RESET_n. VREF = VREFCA(DC). 2. VREF = VREFCA(DC). 3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV). 5. Refer to "Overshoot and Undershoot Specifications."

Table 85: Command and Address Input Levels: DDR4-2933 and DDR4-3200

Parameter AC input high voltage DC input high voltage DC input low voltage AC input low voltage Reference voltage for CMD/ADDR inputs

Symbol VIH(AC) VIH(DC) VIL(DC) VIL(AC) VREFFCA(DC)

Min VREF + 90 VREF + 65
VSS VSS5 0.49 × VDD

Max VDD5 VDD VREF - 65 VREF - 90 0.51 × VDD

Unit mV mV mV mV V

Note 1, 2, 3
1, 2 1, 2 1, 2, 3
4

Notes:

1. For input except RESET_n. VREF = VREFCA(DC). 2. VREF = VREFCA(DC). 3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV). 5. Refer to "Overshoot and Undershoot Specifications."

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Table 86: Single-Ended Input Slew Rates

Parameter Single-ended input slew rate ­ CA

Symbol SRCA

Min 1.0

Max 7.0

Unit V/ns

Note 1, 2, 3, 4

Notes:

1. For input except RESET_n.
2. VREF = VREFCA(DC). 3. tIS/tIH timings assume SRCA = 1V/ns. 4. Measured between VIH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC)
for rising edges

Figure 212: Single-Ended Input Slew Rate Definition

TFse

TRse

VIH(DC)

VIH(AC)

VREFCA

VIL(AC)

VIL(DC)

Command, Control, and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated to account for slew rate variation by adding the data sheet tIS (base) values, the VIL(AC)/VIH(AC) points, and tIH (base) values, the VIL(DC)/VIH(DC) points; to the tIS and tIH derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential clock at 2 V/ns. Example: tIS (total setup time) = tIS (base) + tIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for the time defined by tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the derating values may be obtained by linear interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back below VIH(DC)min . Setup (tIS) nominal slew rate for a falling signal is defined as the slew

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rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)max that does not ring back above VIL(DC)max.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back below VIH(DC)min. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)minthat does not ring back above VIL(DC)max.

Table 87: Command and Address Setup and Hold Values Referenced ­ AC/DC-Based

Symbol tIS(base, AC100) tIH(base, DC75) tIS(base, AC90) tIH(base, DC65)
tIS/tIH(Vref)

1600 115 140
­ ­ 215

1866 100 125
­ ­ 200

2133 80 105 ­ ­ 180

2400 62 87 ­ ­ 162

2666 ­ ­ 55 80
145

2933 ­ ­ 48 73
138

3200 ­ ­ 40 65
130

Unit ps ps ps ps ps

Reference VIH(AC)/VIL(AC) VIH(DC)/VIL(DC) VIH(AC)/VIL(AC) VIH(DC)/VIL(DC) VIH(DC)/VIL(DC)

Table 88: Derating Values for tIS/tIH ­ AC100DC75-Based

tIS with AC100 Threshold, tIH with DC75 Threshold Derating (ps) ­ AC/DC-Based

CMD/ ADDR Slew Rate V/ns

10.0 V/ns tIS tIH

8.0 V/ns tIS tIH

CK, CK# Differential Slew Rate 6.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns
tIS tIH tIS tIH tIS tIH tIH tIH

1.5 V/ns tIS tIH

1.0 V/ns tIS tIH

7.0

76 54 76 55 77 56 79 58 82 60 86 64 94 73 111 89

6.0

73 53 74 53 75 54 77 56 79 58 83 63 92 71 108 88

5.0

70 50 71 51 72 52 74 54 76 56 80 60 88 68 105 85

4.0

65 46 66 47 67 48 69 50 71 52 75 56 83 65 100 81

3.0

57 40 57 41 58 42 60 44 63 46 67 50 75 58 92 75

2.0

40 28 41 28 42 29 44 31 46 33 50 38 58 46 75 63

1.5

23 15 24 16 25 17 27 19 29 21 33 25 42 33 58 50

1.0

­10 ­10 ­9 ­9 ­8 ­8 ­6 ­6 ­4 ­4 0

0

8

8 25 25

0.9

­17 ­14 ­16 ­14 ­15 ­13 ­13 ­10 ­11 ­8 ­7 ­4 1

4 18 21

0.8

­26 ­19 ­25 ­19 ­24 ­18 ­22 ­16 ­20 ­14 ­16 ­9 ­7 ­1 9 16

0.7

­37 ­26 ­36 ­25 ­35 ­24 ­33 ­22 ­31 ­20 ­27 ­16 ­18 ­8 ­2 9

0.6

­52 ­35 ­51 ­34 ­50 ­33 ­48 ­31 ­46 ­29 ­42 ­25 ­33 ­17 ­17 0

0.5

­73 ­48 ­72 ­47 ­71 ­46 ­69 ­44 ­67 ­42 ­63 ­38 ­54 ­29 ­38 ­13

0.4

­104 ­66 ­103 ­66 ­102 ­65 ­100 ­63 ­98 ­60 ­94 ­56 ­85 ­48 ­69 ­31

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Table 89: Derating Values for tIS/tIH ­ AC90/DC65-Based

tIS with AC90 Threshold, tIH with DC65 Threshold Derating (ps) ­ AC/DC-Based

CMD/ ADDR Slew Rate V/ns

10.0 V/ns tIS tIH

8.0 V/ns tIS tIH

CK, CK# Differential Slew Rate 6.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns
tIS tIH tIS tIH tIS tIH tIH tIH

1.5 V/ns tIS tIH

1.0 V/ns tIS tIH

7.0

68 47 69 47 70 48 72 50 73 52 77 56 85 63 100 78

6.0

66 45 67 46 68 47 69 49 71 50 75 54 83 62 98 77

5.0

63 43 64 44 65 45 66 46 68 48 72 52 80 60 95 75

4.0

59 40 59 40 60 41 62 43 64 45 68 49 75 56 90 71

3.0

51 34 52 35 53 36 54 38 56 40 60 43 68 51 83 66

2.0

36 24 37 24 38 25 39 27 41 29 45 33 53 40 68 55

1.5

21 13 22 13 23 14 24 16 26 18 30 22 38 29 53 44

1.0

­9 ­9 ­8 ­8 ­8 ­8 ­6 ­6 ­4 ­4 0

0

8

8 23 23

0.9

­15 ­13 ­15 ­12 ­14 ­11 ­12 ­9 ­10 ­7 ­6 ­4 1

4 16 19

0.8

­23 ­17 ­23 ­17 ­22 ­16 ­20 ­14 ­18 ­12 ­14 ­8 ­7 ­1 8 14

0.7

­34 ­23 ­33 ­22 ­32 ­21 ­30 ­20 ­28 ­18 ­25 ­14 ­17 ­6 ­2 9

0.6

­47 ­31 ­47 ­30 ­46 ­29 ­44 ­27 ­42 ­25 ­38 ­22 ­31 ­14 ­16 1

0.5

­67 ­42 ­66 ­41 ­65 ­40 ­63 ­38 ­61 ­36 ­58 ­33 ­50 ­25 ­35 ­10

0.4

­95 ­58 ­95 ­57 ­94 ­56 ­92 ­54 ­90 ­53 ­86 ­49 ­79 ­41 ­64 ­26

Data Receiver Input Requirements
The following parameters apply to the data receiver Rx MASK operation detailed in the Write Timing section, Data Strobe-to-Data Relationship.
The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in the figure below. A LOW-to-HIGH transition time, tr1, is measured from 0.5 × VdiVW,max below VCENTDQ,midpoint to the last transition through 0.5 × VdiVW,max above VCENTDQ,midpoint; tr2 is measured from the last transition through 0.5 × VdiVW,max above VCENTDQ,midpoint to the first transition through the 0.5 × VIHL(AC)min above VCENTDQ,midpoint.
The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in the figure below. A HIGH-to-LOW transition time, tf1, is measured from 0.5 × VdiVW,max above VCENTDQ,midpoint to the last transition through 0.5 × VdiVW,max below VCENTDQ,midpoint; tf2 is measured from the last transition through 0.5 × VdiVW,max below VCENTDQ,midpoint to the first transition through the 0.5 × VIHL(AC)min below VCENTDQ,midpoint.

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Figure 213: DQ Slew Rate Definitions
tr2

0.5 × VIHL(AC)min

VdiVW,max

VIHL(AC)min

0.5 × VIHL(AC)min

Rx Mask
tr1 tf1
Rx Mask

0.5 × VdiVW,max VCENTDQ,midpoint
0.5 × VdiVW,max
0.5 × VdiVW,max VCENTDQ,midpoint
0.5 × VdiVW,max

0.5 × VIHL(AC)min

VdiVW,max

VIHL(AC)min

0.5 × VIHL(AC)min

tf2

Notes:

1. Rising edge slew rate equation srr1 = VdiVW,max/(tr1). 2. Rising edge slew rate equation srr2 = (VIHL(AC)min - VdiVW,max )/(2 × tr2). 3. Falling edge slew rate equation srf1 = VdiVW,max/(tf1). 4. Falling edge slew rate equation srf2 = (VIHL(AC)min - VdiVW,max )/(2 × tf2).

Table 90: DQ Input Receiver Specifications

Note 1 applies to the entire table DDR4-1600, 1866, 2133

Parameter

Symbol Min Max

VIN Rx mask input VdiVW

­

136

peak-to-peak

DQ Rx input tim- TdiVW ­

0.2

ing window

DQ AC input

VIHL(AC) 186

­

swing peak-to-

peak

DDR4-2400

Min Max

­

130

­

0.2

160

­

DDR4-2666

Min Max

­

120

­ 0.22

150

­

DDR4-2933

Min Max

­

115

­ 0.23

145

­

DDR4-3200

Min Max

­

110

Not Unit es
mV 2, 3

­ 0.23 UI 2, 3

140

­ mV 4, 5

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Single-Ended Input
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Table 90: DQ Input Receiver Specifications (Continued)

Note 1 applies to the entire table DDR4-1600, 1866, 2133

Parameter

Symbol Min Max

DDR4-2400 Min Max

DDR4-2666 Min Max

DDR4-2933 Min Max

DDR4-3200

Not

Min Max Unit es

DQ input pulse width

TdiPW 0.58

­

0.58

­

0.58

­

0.58

­

0.58

­

UI 6

DQS-to-DQ Rx mask offset

tDQS2D ­0.17 0.17 ­0.17 0.17 ­0.19 0.19 ­0.22 0.22 ­0.22 0.22 UI 7 Q

DQ-to-DQ Rx mask tDQ2DQ ­

0.1

­

0.1

­ 0.105 ­ 0.115 ­ 0.125 UI 8

offset

Input slew rate srr1, srf1 1 over VdiVW if tCK  0.937ns

Input slew rate
over VdiVW if 0.937ns > tCK  0.625ns

srr1, srf1 ­

9

1

9

1

9

1

9

1

9 V/ns 9

­ 1.25 9 1.25 9 1.25 9 1.25 9 V/ns 9

Rising input slew

srr2 0.2 × 9 0.2 × 9 0.2 × 9 0.2 × 9 0.2 × 9 V/ns 10

rate over 1/2

srr1

srr1

srr1

srr1

srr1

VIHL(AC)

Falling input slew srf2 0.2 × 9 0.2 × 9 0.2 × 9 0.2 × 9 0.2 × 9 V/ns 10

rate over 1/2

srf1

srf1

srf1

srf1

srf1

VIHL(AC)

Notes:

1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated.

2. Data Rx mask voltage and timing total input valid window where VdiVW is centered around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied per bit and should include voltage and temperature drift terms. The input buffer design specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated.

3. Defined over the DQ internal VREF range 1. 4. Overshoot and undershoot specifications apply.

5. DQ input pulse signal swing into the receiver must meet or exceed VIHL(AC)min. VIHL(AC)min is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a

valid TdiPW).

6. DQ minimum input pulse width defined at the VCENTDQ,midpoint. 7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word

(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM

balls over process, voltage, and temperature.

8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at the SDRAM balls for a given component over process, voltage, and temperature.

9. Input slew rate over VdiVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.

10. Input slew rate between VdiVW mask edge and VIHL(AC)min points.

The following figure shows the Rx mask relationship to the input timing specifications relative to system tDS and tDH. The classical definition for tDS/tDH required a DQ rising

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and falling edges to not violate tDS and tDH relative to the DQS strobe at any time; however, with the Rx mask tDS and tDH can shift relative to the DQS strobe provided the input pulse width specification is satisfied and the Rx mask is not violated.
Figure 214: Rx Mask Relative to tDS/tDH

VdiVW

TdiPW

Rx Mask

tf1

TdiVW

VIH(DC) 0.5 × VdiVW
VCENTDQ,pin mean 0.5 × VdiVW
VIL(DC)
tr1

DQS_c

tDS = Greater of 0.5 × TdiVW
or 0.5 × (TdiPW + VdiVW/tf1)

tDH = Greater of 0.5 × TdiVW
or 0.5 × (TdiPW + VdiVW/tr1)

DQS_t
The following figure and table show an example of the worst case Rx mask required if the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The figure and table show that without DRAM write DQ training, the Rx mask would increase from 0.2UI to essentially 0.54UI. This would also be the minimum tDS and tDH required as well.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Single-Ended Input
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Figure 215: Rx Mask Without Write Training

VdiVW

TdiVW + 2 × tDQS2DQ Rx Mask

VIH(DC) 0.5 × VdiVW
VCENTDQ,midpoint 0.5 × VdiVW
VIL(DC)

tDS

tDH

0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ

DQS_c

DQS_t

Table 91: Rx Mask and tDS/tDH without Write Training

DDR4
1600 1866 2133 2400 2666 2933 3200

VIHL(AC) (mV)

TdiPW (UI)

VdiVW (mV)

TdiVW (UI)

tDQS2DQ (UI)

tDQ2DQ (UI)

186

0.58

136

0.2

±0.17

0.1

186

0.58

136

0.2

±0.17

0.1

186

0.58

136

0.2

±0.17

0.1

160

0.58

130

0.2

±0.17

0.1

150

0.58

120

0.22

±0.19

0.105

145

0.58

115

0.23

±0.22

0.115

140

0.58

110

0.23

±0.22

0.125

Note: 1. VIHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint.

Rx Mask with Write
Train (ps) 125 107.1 94 83.3 82.5 78.4 71.8

tDS + tDH (ps)
338 289 253 225 225 228 209

Connectivity Test (CT) Mode Input Levels

Table 92: TEN Input Levels (CMOS)
Parameter TEN AC input high voltage TEN DC input high voltage TEN DC input low voltage TEN AC input low voltage TEN falling time

Symbol VIH(AC)_TEN VIH(DC)_TEN VIL(DC)_TEN VIL(AC)_TEN
tF_TEN

Min 0.8 × VDD 0.7 × VDD
VSS VSS ­

Max VDD VDD 0.3 × VDD 0.2 × VDD 1 0

Unit V V V V ns

Note 1
2

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Table 92: TEN Input Levels (CMOS) (Continued)

Parameter TEN rising time

Symbol tR_TEN

Min ­

Max 1 0

Unit ns

Note

Notes: 1. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table. 2. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.

Figure 216: TEN Input Slew Rate Definition

VIH(AC)_TENmin VIH(DC)_TENmin

VIL(DC)_TENmin VIL(AC)_TENmin

tF_TEN

tR_TEN

Table 93: CT Type-A Input Levels

Parameter CTipA AC input high voltage CTipA DC input high voltage CTipA DC input low voltage CTipA AC input low voltage CTipA falling time CTipA rising time

Symbol VIH(AC) VIH(DC) VIL(DC) VIL(AC) tF_CTipA tR_CTipA

Min VREF + 200 VREF + 150
VSS VSS11
­ ­

Max VDD11 VDD VREF - 150 VREF - 200
5 5

Unit V V V V ns ns

Note 2, 3 2, 3 2, 3 2, 3
2 2

Notes:

1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-A inputs: CS_n, BG[1:0], BA[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_C, PAR. 3. VREFCA = 0.5 × VDD.

Figure 217: CT Type-A Input Slew Rate Definition

VIH(AC)_CTipAmin VIH(DC)_CTipAmin
VREFCA
VIL(DC)_CTipAmax VIL(AC)_CTipAmax

tF_CTipA

tR_CTipA

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Table 94: CT Type-B Input Levels

Parameter CTipB AC input high voltage CTipB DC input high voltage CTipB DC input low voltage CTipB AC input low voltage CTipB falling time CTipB rising time

Symbol VIH(AC) VIH(DC) VIL(DC) VIL(AC) tF_CTipB tR_CTipB

Min VREF + 300 VREF + 200
VSS VSS11
­ ­

Max VDD11 VDD VREF - 200 VREF - 300
5 5

Unit V V V V ns ns

Notes:

1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n. 3. VREFDQ should be 0.5 × VDD

Figure 218: CT Type-B Input Slew Rate Definition

Note 2, 3 2, 3 2, 3 2, 3
2 2

VIH(AC)_CTipBmin VIH(DC)_CTipBmin
VREFDQ
VIL(DC)_CTipBmax VIL(AC)_CTipBmax

tF_CTipB

tR_CTipB

Table 95: CT Type-C Input Levels (CMOS)

Parameter CTipC AC input high voltage CTipC DC input high voltage CTipC DC input low voltage CTipC AC input low voltage CTipC falling time CTipC rising time

Symbol VIH(AC)_CTipC VIH(DC)_CTipC VIL(DC)_CTipC VIL(AC)_CTipC
tF_CTipC tR_CTipC

Min 0.8 × VDD 0.7 × VDD
VSS VSS1
­ ­

Max VDD1 VDD 0.3 × VDD 0.2 × VDD 1 0 1 0

Notes: 1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-C inputs: Alert_n.

Unit V V V V ns ns

Note 2 2 2 2 2 2

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Single-Ended Input
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Figure 219: CT Type-C Input Slew Rate Definition
VIH(AC)_TENmin VIH(DC)_TENmin

VIL(DC)_TENmin VIL(AC)_TENmin

tF_TEN

tR_TEN

Table 96: CT Type-D Input Levels

Parameter CTipD AC input high voltage CTipD DC input high voltage CTipD DC input low voltage CTipD AC input low voltage Rising time RESET pulse width - after power-up RESET pulse width - during power-up

Symbol
VIH(AC)_CTipD VIH(DC)_CTipD VIL(DC)_CTipD VIL(AC)_CTipD
tR_RESET tPW_RESET_S tPW_RESET_L

Min 0.8 × VDD 0.7 × VDD
VSS VSS ­ 1 200

Max VDD VDD 0.3 × VDD 0.2 × VDD
1 ­ ­

Unit V V V V s s s

Note 4 2 1 5 3

Notes:

1. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, the DRAM may not be reset.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_n signal LOW.
3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible.
4. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table. 5. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table. 6. CT Type-D inputs: RESET_n; same requirements as in normal mode.

Figure 220: CT Type-D Input Slew Rate Definition

VIH(AC)_RESETmin VIH(DC)_RESETmin

tPW_RESET

VIL(DC)_RESETmax VIL(AC)_RESETmax
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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Differential Input Meas-
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Electrical Characteristics ­ AC and DC Differential Input Measurement Levels
Differential Inputs
Figure 221: Differential AC Swing and "Time Exceeding AC-Level" tDVAC tDVAC
VIH,diff(AC)min

VIH,diff,min 0.0
VIL,diff,max

CK_t, CK_c

VIL,diff(AC)max

Half cycle

tDVAC

Notes: 1. Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope. 2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope.

Table 97: Differential Input Swing Requirements for CK_t, CK_c

Parameter Differential input high Differential input low Differential input high (AC)

Symbol VIHdiff VILdiff VIH-
diff(AC)

DDR4-1600 / 1866 / 2133

Min Max

150 Note 3

Note 3 ­150

2 × (VIH(AC) - VREF)

Note 3

DDR4-2400 / 2666

Min Max

135 Note 3

Note 3 -135

2 × (VIH(AC) - VREF)

Note 3

DDR4-2933

Min Max

125 Note 3

Note 3 -125

2 × (VIH(AC) - VREF)

Note 3

DDR4-3200

Min Max

110 Note 3

Note 3 -110

2 × (VIH(AC) - VREF)

Note 3

Note Unit s mV 1 mV 1
V2

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Table 97: Differential Input Swing Requirements for CK_t, CK_c (Continued)

Parameter
Differential input low (AC)

Symbol VIL-
diff(AC)

DDR4-1600 / 1866 / 2133
Min Max

DDR4-2400 / 2666
Min Max

DDR4-2933 Min Max

DDR4-3200

Note

Min Max Unit s

Note 3 2 × Note 3 2 × Note 3 2 × Note 3 2 ×

V

2

(VIL(AC) VREF)

(VIL(AC) VREF)

(VIL(AC) VREF)

(VIL(AC) VREF)

Notes:

1. Used to define a differential signal slew-rate.
2. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA. 3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as the limitations for overshoot and undershoot.

Table 98: Minimum Time AC Time tDVAC for CK

Slew Rate (V/ns) >4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0

tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|

200mV

TBDmV

120

TBD

115

TBD

110

TBD

105

TBD

100

TBD

95

TBD

90

TBD

85

TBD

80

TBD

80

TBD

Note: 1. Below VIL(AC).

Single-Ended Requirements for CK Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has to comply with certain requirements for single-ended signals. CK_t and CK_c have to reach approximately VSEHmin/VSEL,max, which are approximately equal to the AC levels VIH(AC) and VIL(AC) for ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD might differ per speed-bin, and so on. For example, if a value other than 100mV is used for ADD/CMD VIH(AC) and VIL(AC) signals, then these AC levels also apply for the singleended signals CK_t and CK_c.
While ADD/CMD signal requirements are with respect to VREFCA, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSEL,max/VSEH,min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Differential Input Meas-
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Figure 222: Single-Ended Requirements for CK VDD or VDDQ
VSEH,min

VDD/2 or VDDQ/2 VSEL,max
VSS or VSSQ

VSEH

CK VSEL

Table 99: Single-Ended Requirements for CK

Parameter
Single-ended high level for CK_t, CK_c
Single-ended low level for CK_t, CK_c

Symbol VSEH
VSEL

DDR4-1600 / 1866 / 2133

Min

Max

VDD/2 + Note 3 0.100

Note 3

VDD/2 0.100

DDR4-2400 / 2666 DDR4-2933 / 3200

Min

Max

VDD/2 + Note 3 VDD/2 + Note 3

0.095

0.085

Note 3

VDD/2 0.095

Note 3

VDD/2 0.085

Unit Notes

V

1, 2

V

1, 2

Notes:

1. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA. 2. ADDR/CMD VIH(AC) and VIL(AC) based on VREFCA. 3. These values are not defined; however, the differential signal (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as the limitations for overshoot and undershoot.

Slew Rate Definitions for CK Differential Input Signals

Table 100: CK Differential Input Slew Rate Definition

Measured

Description Differential input slew rate for rising edge Differential input slew rate for falling edge

From VIL,diff,max VIH,diff,min

To VIH,diff,min VIL,diff,max

Defined by |VIH,diff,min - VIL,diff,max_TRdiff |VIH,diff,min - VIL,diff,max_TFdiff

Note: 1. The differential signal CK_t, CK_c must be monotonic between these thresholds.

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urement Levels
Figure 223: Differential Input Slew Rate Definition for CK_t, CK_c
TRdiff
VIH,diff,min
0
VIL,diff,max

CK Differential Input Voltage

TFdiff
CK Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signal CK_t, CK_c must meet the requirements shown below. The differential input cross point voltage VIX(CK) is measured from the actual cross point of true and complement signals to the midlevel between VDD and VSS.
Figure 224: VIX(CK) Definition
VDD CK_c

VIX(CK) VSEH

VIX(CK) VSEL

VIX(CK)

VDD/2

CK_t VSS

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Table 101: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400

Parameter
Differential input cross point voltage relative to VDD/2 for CK_t, CK_c

Sym VIX(CK)

Input Level VSEH > VDD/2 + 145mV VDD/2 + 100mV  VSEH  VDD/2 + 145mV VDD/2 - 145mV  VSEL  VDD/2 - 100mV VSEL < VDD/2 - 145mV

DDR4-1600, 1866, 2133, 2400

Min

Max

N/A

120mV

N/A ­(VDD/2 - VSEL) + 25mV
­120mV

(VSEH - VDD/2) - 25mV N/A N/A

Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200

Parameter
Differential input cross point voltage relative to VDD/2 for CK_t, CK_c

Sym VIX(CK)

Input Level VSEH > VDD/2 + 145mV VDD/2 + 90mV  VSEH  VDD/2 + 145mV VDD/2 - 145mV  VSEL  VDD/2 - 90mV VSEL < VDD/2 - 145mV

DDR4-2666, 2933, 3200

Min

Max

N/A

110mV

N/A ­(VDD/2 - VSEL) + 30mV
­110mV

(VSEH - VDD/2) - 30mV N/A N/A

DQS Differential Input Signal Definition and Swing Requirements
Figure 225: Differential Input Signal Definition for DQS_t, DQS_c

V IH,diff,peak

DQS_t, DQS_c: Differential Input Voltage

Half cycle

Half cycle

0.0V

VIL,diff,peak

Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c

Parameter Peak differential input high voltage

Symbol VIH,diff,peak

DDR4-1600, 1866, 2133

Min

Max

186

VDDQ

DDR4-2400

Min

Max

160

VDDQ

Unit mV

Notes 1 , 2

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Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c (Continued)

DDR4-1600, 1866, 2133

DDR4-2400

Parameter

Symbol

Min

Max

Min

Max

Unit Notes

Peak differential input low voltage

VIL,diff,peak

VSSQ

­186

VSSQ

­160

mV

1 , 2

Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits.
2. Minimum value point is used to determine differential signal slew-rate.

Table 104: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c

Parameter
Peak differential input high voltage
Peak differential input low voltage

Symbol VIH,diff,peak
VIL,diff,peak

DDR4-2666 Min Max 150 VDDQ

DDR4-2933 Min Max 145 VDDQ

DDR4-3200 Min Max 140 VDDQ

Unit Notes mV 1 , 2

VSSQ ­150 VSSQ ­145 VSSQ ­140

mV

1 , 2

Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits.
2. Minimum value point is used to determine differential signal slew-rate.

The peak voltage of the DQS signals are calculated using the following equations: VIH,dif,Peak voltage = MAX(ft) VIL,dif,Peak voltage = MIN(ft) (ft) = DQS_t, DQS_c.
The MAX(f(t)) or MIN(f(t)) used to determine the midpoint from which to reference the ±35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all UIs.

Figure 226: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling

DQS_t DQS_c

MIN(ft)

+35% ­35%

+50% MAX(ft)
­50%

DQS_t, DQS_c: Single-Ended Input Voltages

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urement Levels

DQS Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet VIX_DQS,ratio in the table below. The differential input cross point voltage V IX_DQS (VIX_DQS_FR and VIX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c relative to the VDQS,mid of the DQS_t and DQS_c signals.
VDQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQS,mid of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning DQS signals. A non-monotonic transitioning signal's ledge is exempt or not used in determination of a horizontal tangent provided the said ledge occurs within ±35% of the midpoint of either VIH.DIFF.Peak voltage (DQS_t rising) or VIL.DIFF.Peak voltage (DQS_c rising), as shown in the figure below.
A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. That is, a falling transition's horizontal tangent is derived from its negative slope to zero slope transition (point A in the figure below), and a ring-back's horizontal tangent is derived from its positive slope to zero slope transition (point B in the figure below) and is not a valid horizontal tangent; a rising transition's horizontal tangent is derived from its positive slope to zero slope transition (point C in the figure below), and a ring-back's horizontal tangent derived from its negative slope to zero slope transition (point D in the figure below) and is not a valid horizontal tangent.

Figure 227: VIXDQS Definition
DQS_t

Lowest horizontal tanget above VDQS,mid of the transitioning signals
C

DQS_t, DQS_c: Single-Ended Input Voltages VDQS_trans/2 VDQS_trans

VDQS,mid

VIX_DQS,FR VIX_DQS,RF

VIX_DQS,FR B

D VIX_DQS,RF

DQS_c A

VSSQ

Highest horizontal tanget below VDQS,mid of the transitioning signals

Table 105: Cross Point Voltage For Differential Input Signals DQS

Parameter
DQS_t and DQS_c crossing relative to the midpoint of the DQS_t and DQS_c signal swings

Symbol VIX_DQS,ratio

DDR4-1600, 1866, 2133, 2400, 2666, 2933, 3200

Min

Max

­

25

Unit %

Notes 1, 2

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Table 105: Cross Point Voltage For Differential Input Signals DQS (Continued)

DDR4-1600, 1866, 2133, 2400, 2666, 2933, 3200

Parameter VDQS,mid to Vcent(midpoint) offset

Symbol VDQS,mid_to_Vcent

Min ­

Max Note 3

Unit mV

Notes 2

Notes:

1. VIX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQS,midd of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning DQS signals.
2. VDQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) obtained during VREF Training if the DQS and DQs drivers and paths are matched.
3. The maximum limit shall not exceed the smaller of VIH,diff,DQS minimum limit or 50mV.

Slew Rate Definitions for DQS Differential Input Signals

Table 106: DQS Differential Input Slew Rate Definition

Description Differential input slew rate for rising edge Differential input slew rate for falling edge

Measured

From

To

V IL,diff,DQS V IH,diff,DQS

V IH,diff,DQS V IL,diff,DQS

Defined by |VIH,diff,DQS - VIL,diff,DQS_TRdiff |VIHdiffDQS - VIL,diff,DQS_TFdiff

Note: 1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds.

Figure 228: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c

VIH,diff,peak VIH,diff,DQS

0.0V

DQS_t, DQS_c: Differential Input Voltage

TFdiff

TRdiff

VIL,diff,DQS VIL,diff,peak

Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c

Parameter Peak differential input high voltage Differential input high voltage Differential input low voltage

Symbol VIH,diff,peak VIH,diff,DQS VIL,diff,DQS

DDR4-1600, 1866, 2133

Min

Max

186

VDDQ

136

­

­

­136

DDR4-2400

Min

Max

160

VDDQ

130

­

­

­130

Unit mV mV mV

Notes 1
2, 3 2, 3

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Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c (Continued)

Parameter Peak differential input low voltage DQS differential input slew rate

Symbol VIL,diff,peak
SRIdiff

DDR4-1600, 1866, 2133

Min

Max

VSSQ 3.0

­186 18

DDR4-2400

Min

Max

VSSQ 3.0

­160 18

Unit mV V/ns

Notes 1
4, 5

Notes:

1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits.
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope. 3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope. 4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_TRdiff. 5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_TFdiff.

Table 108: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c

Parameter
Peak differential input high voltage
Differential input high voltage
Differential input low voltage
Peak differential input low voltage
DQS differential input slew rate

Symbol VIH,diff,peak VIH,diff,DQS VIL,diff,DQS VIL,diff,peak
SRIdiff

DDR4-2666

Min

Max

150

VDDQ

130

­

­

­130

VSSQ 2.5

­150 18

DDR4-2933

Min

Max

145

VDDQ

115

­

­

­115

VSSQ 2.5

­145 18

DDR4-3200

Min

Max

140

VDDQ

Unit Notes

mV

1

110

­

mV 2, 3

­

­110

mV 2, 3

VSSQ 2.5

­140

mV

1

18

V/ns 4, 5

Notes:

1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits.
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope. 3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope. 4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_TRdiff. 5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_TFdiff.

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cations
Electrical Characteristics ­ Overshoot and Undershoot Specifications
Address, Command, and Control Overshoot and Undershoot Specifications

Table 109: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications

Description

DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR41600 1866 2133 2400 2666 2933 3200

Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0)

Area A: Maximum peak amplitude above VDD absolute MAX

0.06 0.06

0.06

0.06 0.06 0.06 0.06

Area B: Amplitude allowed between VDD and VDD absolute MAX
Area C: Maximum peak amplitude allowed for undershoot below VSS Area A maximum overshoot area per 1tCK

0.24 0.24 0.30 0.30 0.0083 0.0071

0.24 0.30 0.0062

0.24 0.24 0.24 0.24 0.30 0.30 0.30 0.30 0.0055 0.0055 0.0055 0.0055

Area B maximum overshoot area per 1tCK

0.2550 0.2185 0.1914 0.1699 0.1699 0.1699 0.1699

Area C maximum undershoot area per 1tCK

0.2644 0.2265 0.1984 0.1762 0.1762 0.1762 0.1762

Unit
V V V V/ns V/ns V/ns

Figure 229: ADDR, CMD, CNTL Overshoot and Undershoot Definition

Absolute MAX overshoot VDD absolute MAX
VDD VSS

A B
1tCK

Volts (V)

C

Overshoot area above VDD absolute MAX Overshoot area below VDD absolute MAX and above VDD MAX
Undershoot area below VSS

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ Overshoot and Undershoot Specifi-
cations
Clock Overshoot and Undershoot Specifications

Table 110: CK Overshoot and Undershoot/ Specifications

Description
CLK_t, CLK_n
Area A: Maximum peak amplitude above VDD absolute MAX
Area B: Amplitude allowed between VDD and VDD absolute MAX Area C: Maximum peak amplitude allowed for undershoot below VSS Area A maximum overshoot area per 1UI
Area B maximum overshoot area per 1UI
Area C maximum undershoot area per 1UI

DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR41600 1866 2133 2400 2666 2933 3200 Unit

0.06 0.06 0.06 0.06 0.06 0.06 0.06

V

0.24 0.24 0.24 0.24 0.24 0.24 0.24

V

0.30 0.30 0.30 0.30 0.30 0.30 0.30

V

0.0038 0.0032 0.0028 0.0025 0.0025 0.0025 0.0025 V/ns 0.1125 0.0964 0.0844 0.0750 0.0750 0.0750 0.0750 V/ns 0.1144 0.0980 0.0858 0.0762 0.0762 0.0762 0.0762 V/ns

Volts (V)

Figure 230: CK Overshoot and Undershoot Definition
Absolute MAX overshoot
A
VDD absolute MAX
B
VDD 1UI
VSS
C

Overshoot area above VDD absolute MAX Overshoot area below VDD absolute MAX and above VDD MAX
Undershoot area below VSS

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Data, Strobe, and Mask Overshoot and Undershoot Specifications

Table 111: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications

Description

DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR41600 1866 2133 2400 2666 2933 3200

DQS_t, DQS_n, LDQS_t, LDQS_n, UDQS_t, UDQS_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI,

Area A: Maximum peak amplitude above VDDQ

0.16

0.16 0.16

0.16 0.16 0.16

0.16

absolute MAX

Area B: Amplitude allowed between VDDQ and VDDQ absolute MAX
Area C: Maximum peak amplitude allowed for undershoot below VSSQ
Area D: Maximum peak amplitude below VSSQ absolute MIN

0.24 0.24 0.24 0.24 0.24 0.24 0.24 0.30 0.30 0.30 0.30 0.30 0.30 0.30 0.10 0.10 0.10 0.10 0.10 0.10 0.10

Area A maximum overshoot area per 1UI

0.0150 0.0129 0.0113 0.0100 0.0100 0.0100 0.0100

Area B maximum overshoot area per 1UI

0.1050 0.0900 0.0788 0.0700 0.0700 0.0700 0.0700

Area C maximum undershoot area per 1UI

0.1050 0.0900 0.0788 0.0700 0.0700 0.0700 0.0700

Area D maximum undershoot area per 1UI

0.0150 0.0129 0.0113 0.0100 0.0100 0.0100 0.0100

Unit
V
V
V
V
V/ns V/ns V/ns V/ns

Figure 231: Data, Strobe, and Mask Overshoot and Undershoot Definition

Volts (V)

Absolute MAX overshoot
A
VDDQ absolute MAX
B
VDDQ 1UI
VSSQ

C

VSSQ absolute MIN

D

Absolute MAX undershoot

Overshoot area above VDDQ absolute MAX
Overshoot area below VDDQ absolute MAX and above VDDQ MAX
Undershoot area below VSSQ MIN and above VSSQ absolute MIN Undershoot area below VSSQ absolute MIN

Electrical Characteristics ­ AC and DC Output Measurement Levels
Single-Ended Outputs

Table 112: Single-Ended Output Levels
Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output slew rate)

Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC)

DDR4-1600 to DDR4-3200 1.1 × VDDQ 0.8 × VDDQ 0.5 × VDDQ
(0.7 + 0.15) × VDDQ

Unit V V V V

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Table 112: Single-Ended Output Levels (Continued)

Parameter AC output low measurement level (for output slew rate)

Symbol VOL(AC)

DDR4-1600 to DDR4-3200 Unit

(0.7 - 0.15) × VDDQ

V

Note: 1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50 to VTT = VDDQ.

Using the same reference load used for timing measurements, output slew rate for fall-
ing and rising edges is defined and measured between VOL(AC) and VOH(AC) for singleended signals.

Table 113: Single-Ended Output Slew Rate Definition

Description Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge

Measured

From

To

VOL(AC) VOH(AC)

VOH(AC) VOL(AC)

Figure 232: Single-ended Output Slew Rate Definition

TRse

Defined by [VOH(AC) - VOL(AC)@TRse [VOH(AC) - VOL(AC)@TFse

VOH(AC)

Single-Ended Output Voltage (DQ)

TFse

VOL(AC)

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Table 114: Single-Ended Output Slew Rate

For RON = RZQ/7
Parameter Single-ended output slew rate

Symbol SRQse

DDR4-1600/ 1866 / 2133 / 2400

Min

Max

4

9

DDR4-2666

Min

Max

4

9

DDR4-2933 / 3200

Min

Max

4

9

Unit V/ns

Notes: 1. SR = slew rate; Q = query output; se = single-ended signals. 2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte lane:
· Case 1 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are static (they stay at either HIGH or LOW).
· Case 2 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are switching into the opposite direction (from LOW-toHIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the opposite direction, the standard maximum limit of 9 V/ns applies.

Differential Outputs

Table 115: Differential Output Levels

Parameter
AC differential output high measurement level (for output slew rate)
AC differential output low measurement level (for output slew rate)

Symbol VOH,diff(AC)

DDR4-1600 to DDR4-3200 0.3 × VDDQ

Unit V

VOL,diff(AC)

­0.3 × VDDQ

V

Note: 1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50 to VTT = VDDQ at each differential output.
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential signals.

Table 116: Differential Output Slew Rate Definition

Description Differential output slew rate for rising edge Differential output slew rate for falling edge

Measured

From

To

VOL,diff(AC) VOH,diff(AC)

VOH,diff(AC) VOL,diff(AC)

Defined by [VOH,diff(AC) - VOL,diff(AC)@TRdiff [VOH,diff(AC) - VOL,diff(AC)@TFdiff

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Measurement
Levels
Figure 233: Differential Output Slew Rate Definition
TRdiff
VOH,diff(AC)

Differential Input Voltage (DQS_t, DQS_c)

VOL,diff(AC)

TFdiff

Table 117: Differential Output Slew Rate

For RON = RZQ/7

Parameter
Differential output slew rate

Symbol SRQdiff

DDR4-1600 / 1866 / 2133 / 2400

Min

Max

8

18

DDR4-2666

Min

Max

8

18

DDR4-2933 / 3200

Min

Max

8

18

Note: 1. SR = slew rate; Q = query output; diff = differential signals.

Unit V/ns

Reference Load for AC Timing and Output Slew Rate
The effective reference load of 50 to VTT = VDDQ and driver impedance of RZQ/7 for each output was used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.
RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC timing parameter values of the device. The maximum DC high level of output signal = 1.0 × VDDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × VDDQ = 0.4 × VDDQ.
The nominal reference level of an output signal can be approximated by the following: The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × VDDQ = 0.7 × VDDQ. The actual reference level of output signal might vary with driver RON and reference load tolerances. Thus, the actual reference level or midpoint of an output signal is at the widest part of the output signal's eye.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Measurement
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Figure 234: Reference Load For AC Timing and Output Slew Rate

CK_t, CK_c

VDDQ DUT

VTT = VDDQ DQ, DQS_t, DQS_c, DM, TDQS_t, TDQS_c
RTT = 50

VSSQ Timing reference point

Connectivity Test Mode Output Levels

Table 118: Connectivity Test Mode Output Levels

Parameter

Symbol DDR4-1600 to DDR4-3200

DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) DC output below measurement level (for IV curve linearity) AC output high measurement level (for output slew rate) AC output low measurement level (for output slew rate)

VOH(DC) VOM(DC) VOL(DC) VOB(DC) VOH(AC) VOL(AC)

1.1 × VDDQ 0.8 × VDDQ 0.5 × VDDQ 0.2 × VDDQ VTT + (0.1 × VDDQ) VTT - (0.1 × VDDQ)

Note: 1. Driver impedance of RZQ/7 and an effective test load of 50 to VTT = VDDQ.

Unit V V V V V V

Figure 235: Connectivity Test Mode Reference Test Load

CT_Inputs

VDDQ DUT

DQ, DQS_t, DQS_c, LDQS_t, LDQS_c, UDQS_t, UDQS_c,

DM, LDM, HDM, TDQS_t, TDQS_c

RTT = 50 

0.5 × VDDQ

VSSQ Timing reference point

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Driver Charac-
teristics
Figure 236: Connectivity Test Mode Output Slew Rate Definition

0.5 x VDD

VOH(AC) VTT VOL(AC)

TFoutput_CT

TRoutput_CT

Table 119: Connectivity Test Mode Output Slew Rate

Parameter Output signal falling time Output signal rising time

Symbol TF_output_CT TR_output_CT

DDR4-1600 / 1866 / 2133 / 2400

Min

Max

­

10

­

10

DDR4-2666

Min Max

­

10

­

10

DDR4-2933 / 3200

Min Max

­

10

­

10

Unit ns/V ns/V

Electrical Characteristics ­ AC and DC Output Driver Characteristics
Connectivity Test Mode Output Driver Electrical Characteristics
The DDR4 driver supports special values during connectivity test mode. These RON values are referenced in this section. A functional representation of the output buffer is shown in the figure below.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Driver Charac-
teristics

Figure 237: Output Driver During Connectivity Test Mode
Chip in drive mode Output driver

To other circuitry like RCV,
...

IPU_CT RONPU_CT
RONPD_CT IPD_CT

VDDQ
DQ IOUT
VOUT

VSSQ

The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON = RZQ/7. This targets 34 with nominal RZQ ; however, connectivity test mode uses uncalibrated drivers and only a maximum target is defined.
Mismatch between pull up and pull down is undefined.

The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows:

RONPu_CT when RONPd_CT is off:

52138B&7 

9''49287 ,287

RONPD_CT when RONPU_CT is off:

5213'B&7 

9287 ,287

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Driver Charac-
teristics

Table 120: Output Driver Electrical Characteristics During Connectivity Test Mode

Assumes RZQ ; ZQ calibration not required

RON,nom_CT

Resistor

VOUT

VOB(DC) = 0.2 × VDDQ

RONPD_CT

VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ



VOH(DC) = 1.1 × VDDQ VOB(DC) = 0.2 × VDDQ

RONPU_CT

VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ

VOH(DC) = 1.1 × VDDQ

Min N/A N/A N/A N/A N/A N/A N/A N/A

Nom N/A N/A N/A N/A N/A N/A N/A N/A

Max 1.9 2.0 2.2 2.5 1.9 2.0 2.2 2.5

Unit RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7

Output Driver Electrical Characteristics
The DDR4 driver supports two RON values. These RON values are referred to as strong mode (low RON) and weak mode (high RON). A functional representation of the output buffer is shown in the figure below.

Figure 238: Output Driver: Definition of Voltages and Currents

Chip in drive mode Output driver

VDDQ

To other circuitry like RCV,
...

IPU RONPU
RONPD IPD

DQ IOUT
VOUT

VSSQ

The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a nominal 34.3±10% or 48±10% with nominal RZQ 
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu when RONPd is off:

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Driver Charac-
teristics

VDDQ - VOUT

RONPU =

IOUT

RONPD when RONPU is off: VOUT
RONPD = IOUT

Table 121: Strong Mode (34) Output Driver Electrical Characteristics

Assumes RZQ ; Entire operating temperature range after proper ZQ calibration

RON,nom

Resistor

VOUT

Min

Nom

VOL(DC) = 0.5 × VDDQ

0.73

1.00

RON34PD

VOM(DC) = 0.8 × VDDQ

0.83

1.00



VOH(DC) = 1.1 × VDDQ

0.83

1.00

VOL(DC) = 0.5 × VDDQ

0.90

1.00

RON34PU

VOM(DC) = 0.8 × VDDQ

0.90

1.00

VOH(DC) = 1.1 × VDDQ

0.80

1.00

Mismatch between pull-up and pull- VOM(DC) = 0.8 × VDDQ

10

­

down, MMPUPD

Mismatch between DQ to DQ within VOM(DC) = 0.8 × VDDQ

­

­

byte variation pull-up, MMPUdd

Mismatch between DQ to DQ within VOM(DC) = 0.8 × VDDQ

-

­

byte variation pull-down, MMPDdd

Max 1.10 1.10 1.25 1.25 1.10 1.10 23
10
10

Unit RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7
%
%
%

Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4,
6, 7 1, 2, 3, 4,
5 1, 2, 3, 4,
6, 7

Notes:

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 × VDDQ. Other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON value:

MMPUPD =

RONPU - RONPD RON,nom

× 100

6. RON variance range ratio to RON nominal value in a given component, including DQS_t and DQS_c:

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Driver Charac-
teristics

MMPUDD =

RONPU,max - RONPU,min RON,nom

× 100

MMPDDD =

RONPD,max - RONPD,min RON,nom

× 100

7. The lower and upper bytes of a x16 are each treated on a per byte basis. 8. The minimum values are derated by 9% when the device operates between ­40°C and
0°C (TC).

Table 122: Weak Mode (48) Output Driver Electrical Characteristics

Assumes RZQ ; Entire operating temperature range after proper ZQ calibration

RON,nom

Resistor

VOUT

Min

Nom



RON48PD

VOL(DC) = 0.5 × VDDQ

0.73

1.00

VOM(DC) = 0.8 × VDDQ

0.83

1.00

VOH(DC) = 1.1 × VDDQ

0.83

1.00

RON48PU

VOL(DC) = 0.5 × VDDQ

0.90

1.00

VOM(DC) = 0.8 × VDDQ

0.90

1.00

VOH(DC) = 1.1 × VDDQ

0.80

1.00

Mismatch between pull-up and

VOM(DC) = 0.8 × VDDQ

10

­

pull-down, MMPUPD

Mismatch between DQ to DQ

VOM(DC) = 0.8 × VDDQ

­

­

within byte variation pull-up,

MMPUdd

Mismatch between DQ to DQ

VOM(DC) = 0.8 × VDDQ

­

­

within byte variation pull-down,

MMPDdd

Max 1.10 1.10 1.25 1.25 1.10 1.10 23
10
10

Unit RZQ/5 RZQ/5 RZQ/5 RZQ/5 RZQ/5 RZQ/5
%
%

Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4,
6, 7 1, 2, 3, 4, 5

%

1, 2, 3, 4,

6, 7

Notes:

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 × VDDQ. Other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON value:

MMPUPD =

RONPU - RONPD RON,nom

× 100

6. RON variance range ratio to RON nominal value in a given component, including DQS_t and DQS_c:

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ AC and DC Output Driver Charac-
teristics

MMPUDD =

RONPU,max - RONPU,min RON,nom

× 100

MMPDDD =

RONPD,max - RONPD,min RON,nom

× 100

7. The lower and upper bytes of a x16 are each treated on a per byte basis. 8. The minimum values are derated by 9% when the device operates between ­40°C and
0°C (TC).

Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the equations and tables below. T = T - T(@calibration); V = VDDQ - VDDQ(@ calibration); VDD = VDDQ

Table 123: Output Driver Sensitivity Definitions

Symbol RONPU@ VOH(DC) RON@ VOM(DC) RONPD@ VOL(DC)

Min 0.6 - dRONdTH × |T| - dRONdVH × |V| 0.9 - dRONdTM × |T| - dRONdVM × |V| 0.6 - dRONdTL × |T| - dRONdVL × |V|

Max 1.1 _ dRONdTH × |T| + dRONdVH × |V| 1.1 + dRONdTM × |T| + dRONdVM × |V| 1.1 + dRONdTL × |T| + dRONdVL × |V|

Unit RZQ/6 RZQ/6 RZQ/6

Table 124: Output Driver Voltage and Temperature Sensitivity

Symbol dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVM

Voltage and Temperature Range

Min

Max

0

1.5

0

0.15

0

1.5

0

0.15

0

1.5

0

0.15

Unit %/°C %/mV %/°C %/mV %/°C %/mV

Alert Driver

A functional representation of the alert output buffer is shown in the figure below. Output driver impedance, RON, is defined as follows.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ On-Die Termination Characteristics

Figure 239: Alert Driver

Alert driver

'5$0

RONPD IPD

IOUT

Alert VOUT

VSSQ

RONPD when RONPU is off: VOUT
RONPD = IOUT

Table 125: Alert Driver Voltage

RON,nom N/A

Register RONPD

VOUT VOL(DC) = 0.1 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ

Note: 1. VDDQ voltage is at VDDQ(DC).

Min 0.3 0.4 0.4

Nom N/A N/A N/A

Max 1.2 1.2 1.4

Unit RZQ/7 RZQ/7 RZQ/7

Electrical Characteristics ­ On-Die Termination Characteristics

ODT Levels and I-V Characteristics
On-die termination (ODT) effective resistance settings are defined and can be selected by any or all of the following options:
· MR1[10:8] (RTT(NOM)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms.
· MR2[11:9] (RTT(WR)): Disable, 240 ohms,120 ohms, and 80 ohms. · MR5[8:6] (RTT(Park)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40
ohms, and 34 ohms.
ODT is applied to the following inputs:
· x4: DQ, DM_n, DQS_t, and DQS_c inputs. · x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs. · x16: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs.
A functional representation of ODT is shown in the figure below.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ On-Die Termination Characteristics

Figure 240: ODT Definition of Voltages and Currents

Chip in termination mode ODT

VDDQ

To other

RTT

circuitry

like RCV,

...

IOUT

DQ VOUT

VSSQ

Table 126: ODT DC Characteristics

RTT 240 ohm 120 ohm 80 ohm 60 ohm 48 ohm 40 ohm 34 ohm DQ-to-DQ mismatch within byte

VOUT VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOL(DC) = 0.5 × VDDQ VOM(DC) = 0.8 × VDDQ VOH(DC) = 1.1 × VDDQ VOM(DC) = 0.8 × VDDQ

Min 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0

Nom 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ­

Max 1.25 1.1 1.1 1.25 1.1 1.1 1.25 1.1 1.1 1.25 1.1 1.1 1.25 1.1 1.1 1.25 1.1 1.1 1.25 1.1 1.1 10

Unit RZQ RZQ RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/3 RZQ/3 RZQ/3 RZQ/4 RZQ/4 RZQ/4 RZQ/5 RZQ/5 RZQ/5 RZQ/6 RZQ/6 RZQ/6 RZQ/7 RZQ/7 RZQ/7 %

Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4, 5, 6

Notes: 1. The tolerance limits are specified after calibration to 240 ohm ±1% resistor with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see ODT Temperature and Voltage Sensitivity.

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ On-Die Termination Characteristics

2. Micron recommends calibrating pull-up ODT resistors at 0.8 × VDDQ. Other calibration schemes may be used to achieve the linearity specification shown here.
3. The tolerance limits are specified under the condition that VDDQ = VDD and VSSQ = VSS. 4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t
and DQS_c. 5. RTT variance range ratio to RTT nominal value in a given component, including DQS_t
and DQS_c.
DQ-to-DQ mismatch = RTT(MAX) - RTT(MIN) × 100 RTT(NOM)
6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes. 7. For IT, AT, and UT devices, the minimum values are derated by 9% when the device op-
erates between ­40°C and 0°C (TC).
ODT Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the following equations and tables.
T = T - T(@ calibration); V = VDDQ - VDDQ(@ calibration); VDD = VDDQ

Table 127: ODT Sensitivity Definitions

Parameter RTT@

Min 0.9 - dRTTdT × |T| - dRTTdV × |V|

Max 1.6 + dRTTdTH × |T| + dRTTdVH × |V|

Unit RZQ/n

Table 128: ODT Voltage and Temperature Sensitivity

Parameter dRTTdT dRTTdV

Min 0 0

Max 1.5 0.15

Unit %/°C %/mV

ODT Timing Definitions
The reference load for ODT timings is different than the reference load used for timing measurements.

Figure 241: ODT Timing Reference Load

CK_t, CK_c

VDDQ DUT

DQ, DQS_t, DQS_c, DM, TDQS_t, TDQS_c
RTT = 50

VSSQ Timing reference point

VTT = VSSQ

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ On-Die Termination Characteristics

ODT Timing Definitions
Definitions for tADC, tAONAS, and tAOFAS are provided in the Table 129 (page 309) and shown in Figure 242 (page 310) and Figure 244 (page 311). Measurement reference settings are provided in the subsequent Table 130 (page 309).
The tADC for the dynamic ODT case and read disable ODT cases are represented by tADC of Direct ODT Control case.

Table 129: ODT Timing Definitions

Parameter

Begin Point Definition

tADC

Rising edge of CK_t, CK_c defined by the end point of DODTLoff

Rising edge of CK_t, CK_c defined by the end point of DODTLon

Rising edge of CK_t, CK_c defined by the end point of ODTLcnw

Rising edge of CK_t, CK_c defined by the end point of ODTLcwn4 or ODTLcwn8

tAONAS

Rising edge of CK_t, CK_c with ODT being first registered HIGH

tAOFAS

Rising edge of CK_t, CK_c with ODT being first registered LOW

End Point Definition Extrapolated point at VRTT,nom Extrapolated point at VSSQ Extrapolated point at VRTT,nom Extrapolated point at VSSQ Extrapolated point at VSSQ Extrapolated point at VRTT,nom

Figure
Figure 242 (page 310)
Figure 242 (page 310)
Figure 243 (page 310)
Figure 243 (page 310)
Figure 244 (page 311)
Figure 244 (page 311)

Table 130: Reference Settings for ODT Timing Measurements

Measure Parameter tADC
tAONAS tAOFAS

RTT(Park) Disable
­ Disable Disable

RTT(NOM) RZQ RZQ RZQ RZQ

RTT(WR) ­
High-Z ­ ­

VSW1 0.20V 0.20V 0.20V 0.20V

VSW2 0.40V 0.40V 0.40V 0.40V

Note 1, 2, 4 1, 3, 5 1, 2, 6 1, 2, 6

Notes:

1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for RTT(NOM) setting; MR5 has A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for RTT(WR) setting.
2. ODT state change is controlled by ODT pin.
3. ODT state change is controlled by a WRITE command.
4. Refer to Figure 242 (page 310).
5. Refer to Figure 243 (page 310).
6. Refer to Figure 244 (page 311).

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ On-Die Termination Characteristics

Figure 242: tADC Definition with Direct ODT Control

DODTLoff

Begin point: Rising edge of CK_t, CK_c defined by the end point of DODTLoff

CK_c

DODTLon

Begin point: Rising edge of CK_t, CK_c defined by the end point of DODTLon

CK_t

tADC

tADC

VRTT,nom
DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c

End point: Extrapolated point at VRTT,nom
Vsw2 Vsw1 VSSQ

VSSQ

VRTT,nom
End point: Extrapolated point at VSSQ

Figure 243: tADC Definition with Dynamic ODT Control

ODTLcnw

Begin point: Rising edge of CK_t, CK_c defined by the end point of ODTLcnw

CK_c

ODTLcnw4/8

Begin point: Rising edge of CK_t, CK_c defined by the end point of ODTLcnw4 or ODTLcnw8

CK_t

tADC

tADC

VRTT,nom
DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c

End point: Extrapolated point at VRTT,nom
Vsw2 Vsw1 VSSQ

VSSQ

VRTT,nom
End point: Extrapolated point at VSSQ

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics ­ On-Die Termination Characteristics

Figure 244: tAOFAS and tAONAS Definitions
Rising edge of CK_t, CK_c with ODT being first registered LOW

Rising edge of CK_t, CK_c with ODT being first registered HIGH

CK_c

CK_t

tAOFAS

tAONAS

VRTT,nom
DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c

End point: Extrapolated point at VRTT_NOM
Vsw2 Vsw1 VSSQ

VSSQ

VRTT,nom
End point: Extrapolated point at VSSQ

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4Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications
DRAM Package Electrical Specifications

Table 131: DRAM Package Electrical Specifications for x4 and x8 Devices

1600/1866/2133/ 2400/2666

2933

3200

Parameter

Input/ output

Zpkg Package delay

Lpkg

Cpkg

DQS_t, DQS_c

Zpkg Package delay

Delta Zpkg

Delta delay

Lpkg

Cpkg

Input CTRL Zpkg

pins

Package delay

Lpkg

Cpkg

Input CMD Zpkg ADD pins Package delay

Lpkg

Cpkg

CK_t, CK_c Zpkg

Package delay

Delta Zpkg

Delta delay

Lpkg

Cpkg

ZQ Zpkg

ZQ delay

ALERT Zpkg

ALERT delay

Symbol ZIO TdIO LIO CIO
ZIO DQS TdIO DQS DZIO DQS DTdIO DQS LIO DQS CIO DQS ZI CTRL TdI CTRL
LI CTRL CI CTRL ZI ADD CMD TdI ADD CMD LI ADD CMD CI ADD CMD
ZCK TdCK DZDCK DTdDCK LI CLK CI CLK ZO ZQ TdO ZQ ZO ALERT TdO ALERT

Min 45 14 ­ ­ 45 14 ­ ­ ­ ­ 50 14 ­ ­ 50 14 ­ ­ 50 14 ­ ­ ­ ­ ­ 20 40 20

Max 85 42 3.3 0.78 85 42 10 5 3.3 0.78 90 42 3.4 0.7 90 45 3.6 0.74 90 42 10 5 3.4 0.7 100 90 100 55

Min 48 14 ­ ­ 48 14 ­ ­ ­ ­ 50 14 ­ ­ 50 14 ­ ­ 50 14 ­ ­ ­ ­ ­ 20 40 20

Max 85 40 3.3 0.78 85 40 10 5 3.3 0.78 90 40 3.4 0.7 90 40 3.6 0.74 90 42 10 5 3.4 0.7 100 90 100 55

Min 48 14 ­ ­ 48 14 ­ ­ ­ ­ 50 14 ­ ­ 50 14 ­ ­ 50 14 ­ ­ ­ ­ ­ 20 40 20

Max 85 40 3.3 0.78 85 40 10 5 3.3 0.78 90 40 3.4 0.7 90 40 3.6 0.74 90 42 10 5 3.4 0.7 100 90 100 55

Unit Notes ohm 1, 2, 4
ps 1, 3, 4 nH 10 pF 11 ohm 1, 2 ps 1, 3 ohm 1, 2, 6 ps 1, 3, 6 nH 10 pF 11 ohm 1, 2, 8 ps 1, 3, 8 nH 10 pF 11 ohm 1, 2, 7 ps 1, 3, 7 nH 10 pF 11 ohm 1, 2 ps 1, 3 ohm 1, 2, 5 ps 1, 3, 5 nH 10 pF 11 ohm 1, 2 ps 1, 3 ohm 1, 2 ps 1, 3

Notes:

1. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c.

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4Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications

5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO (DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n. 8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE. 9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td. 11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.

Table 132: DRAM Package Electrical Specifications for x16 Devices

Parameter

Input/ output

Zpkg Package delay

Lpkg

Cpkg

LDQS_t/ LDQS_c/ UDQS_t/ UDQS_c

Zpkg Package delay Lpkg Cpkg

LDQS_t/ LDQS_c, UDQS_t/ UDQS_c,

Delta Zpkg Delta delay

Input CTRL Zpkg

pins

Package delay

Lpkg

Cpkg

Input CMD Zpkg ADD pins Package delay

Lpkg

Cpkg

CK_t, CK_c Zpkg

Package delay

Delta Zpkg

Delta delay

Input CLK Lpkg

Cpkg

ZQ Zpkg

ZQ delay

Symbol ZIO TdIO LIO CIO
ZIO DQS TdIO DQS LIO DQS CIO DQS DZIO DQS DTdIO DQS
ZI CTRL TdI CTRL LI CTRL CI CTRL ZI ADD CMD TdI ADD CMD LI ADD CMD CI ADD CMD
ZCK TdCK DZDCK DTdDCK LI CLK CI CLK ZO ZQ TdO ZQ

1600/1866/2133/ 2400/2666

Min

Max

45

85

14

45

­

3.4

­

0.82

45

85

14

45

­

3.4

­

0.82

­

10.5

­

5

50

90

14

42

­

3.4

­

0.7

50

90

14

52

­

3.9

­

0.86

50

90

14

42

­

10.5

­

5

­

3.4

­

0.7

­

100

20

90

2933

Min

Max

45

85

14

45

­

3.4

­

0.82

45

85

14

45

­

3.4

­

0.82

­

10.5

­

5

50

90

14

42

­

3.4

­

0.7

50

90

14

52

­

3.9

­

0.86

50

90

14

42

­

10.5

­

5

­

3.4

­

0.7

­

100

20

90

3200

Min

Max

45

85

14

45

­

3.4

­

0.82

45

85

14

45

­

3.4

­

0.82

­

10.5

­

5

Unit Notes ohm 1, 2, 4
ps 1, 3, 4 nH 11 pF 11 ohm 1, 2 ps 1, 3 nH 11 pF 11 ohm 1, 2, 6 ps 1, 3, 6

50

90

ohm 1, 2, 8

14

42

ps 1, 3, 8

­

3.4

nH 11

­

0.7

pF 11

50

90

ohm 1, 2, 7

14

52

ps 1, 3, 7

­

3.9

nH 11

­

0.86

pF 11

50

90

ohm 1, 2

14

42

ps 1, 3

­

10.5 ohm 1, 2, 5

­

5

ps 1, 3, 5

­

3.4

nH 11

­

0.7

pF 11

­

100 ohm 1, 2

20

90

ps 1, 3

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4Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications

Table 132: DRAM Package Electrical Specifications for x16 Devices (Continued)

Parameter ALERT Zpkg ALERT delay

1600/1866/2133/ 2400/2666

2933

3200

Symbol ZO ALERT TdO ALERT

Min 40 20

Max 100 55

Min 40 20

Max 100 55

Min 40 20

Max 100 55

Unit Notes ohm 1, 2
ps 1, 3

Notes:

1. The package parasitic (L and C) are validated using package only samples. The capaci-
tance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.

2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a

given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).

3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin

where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).

4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c. 5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c

for delay (Td).

6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO

(DQS_t), TdIO (DQS_c) for delay (Td).

7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n. 8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE. 9. Package implementations will meet specification if the Zpkg and package delay fall

within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi-

mum values shown.

10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td. 11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.

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4Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications

Table 133: Pad Input/Output Capacitance

DDR4-1600, 1866, 2133

Parameter

Symbol Min Max

Input/output capacitance: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c

CIO

0.55 1.4

Input capacitance: CK_t and

CCK

0.2 0.8

CK_c

Input capacitance delta: CK_t and CK_c

CDCK

0 0.05

Input/output capacitance del- CDDQS ta: DQS_t and DQS_c

0 0.05

Input capacitance: CTRL, ADD, CMD input-only pins

CI

0.2 0.8

Input capacitance delta: All CTRL input-only pins

CDI_CTRL ­0.1 0.1

Input capacitance delta: All CDI_ADD_CM ­0.1 0.1

ADD/CMD input-only pins

D

Input/output capacitance del- CDIO ta: DQ, DM, DQS_t, DQS_c,

­0.1 0.1

TDQS_t, TDQS_c

Input/output capacitance: ALERT pin

CALERT

0.5 1.5

Input/output capacitance: ZQ CZQ pin

­

2.3

Input/output capacitance: TEN pin

CTEN

0.2 2.3

DDR4-2400, 2666
Min Max 0.55 1.15

0.2 0.7 0 0.05 0 0.05 0.2 0.7 ­0.1 0.1 ­0.1 0.1 ­0.1 0.1

0.5 1.5

­

2.3

0.2 2.3

DDR4-2933 Min Max 0.55 1.00

0.2 0.7 0 0.05 0 0.05 0.2 0.6 ­0.1 0.1 ­0.1 0.1 ­0.1 0.1

0.5 1.5

­

2.3

0.2 2.3

DDR4-3200 Min Max 0.55 1.00

Unit pF

Notes 1, 2, 3

0.2 0.7 pF 2, 3

0 0.05 pF 2, 3, 6

0 0.05 pF 2, 3, 5

0.2 0.55 pF 2, 3, 4

­0.1 0.1 pF 2, 3, 8, 9
­0.1 0.1 pF 1, 2, 10, 11
­0.1 0.1 pF 1, 2, 3, 4

0.5 1.5 pF 2, 3

­

2.3 pF 2, 3, 12

0.2 2.3 pF 2, 3, 13

Notes:

1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to a production test; it is verified by design and characterization. The capacitance is measured according to the JEP147 specification, "Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA)," with VDD, VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). VDD = VDDQ = 1.2V, VBIAS = VDD/2 and on-die termination off. Measured data is rounded using industry standard half-rounded up methodology to the nearest hundredth of the MSB.
3. This parameter applies to monolithic die, obtained by de-embedding the package L and C parasitics.
4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)). 5. Absolute value of CIO (DQS_t), CIO (DQS_c) 6. Absolute value of CCK_t, CCK_c
7. CI applies to ODT, CS_n, CKE, A[17:0], BA[1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n.
8. CDI_CTRL applies to ODT, CS_n, and CKE. 9. CDI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)).

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4Gb: x4, x8, x16 DDR4 SDRAM Thermal Characteristics
10. CDI_ADD_CMD applies to A[17:0], BA1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n. 11. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)). 12. Maximum external load capacitance on ZQ pin: 5pF. 13. Only applicable if TEN pin does not have an internal pull-up.

Thermal Characteristics

Table 134: Thermal Characteristics

Parameter/Condition Operating case temperature: Commercial
Operating case temperature: Industrial
Operating case temperature: Automotive

REV A

78-ball "HX" 96-ball "HA"

REV B

78-ball "RH" 96-ball "GE"

REV E

78-ball "WE" 96-ball "LY"

REV F

78-ball "SA" 96-ball "LY"

REV G

78-ball "SA" 96-ball "TB"

Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board Junction-to-case (TOP) Junction-to-board

Value 0 to +85 0 to +95 ­40 to +85 ­40 to +95 ­40 to +85 ­40 to +105
4.4 12.7 3.6 12.0 7.7 20.9 5.0 19.0 3.2 20.2 TBD TBD 4.9 14.2 4.8 15.2 6.0 17.9 5.9 17.4

Units °C °C °C °C °C °C
°C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W

Symbol TC TC TC TC TC TC ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB ^JC ^JB

Notes 1, 2, 3 1, 2, 3, 4 1, 2, 3 1, 2, 3, 4 1, 2, 3 1, 2, 3, 4
5
5
5
5
5
5
5
5
5
5

Notes:

1. MAX operating case temperature. TC is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate.
5. The thermal resistance data is based off of a typical number.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Measurement Conditions
Figure 245: Thermal Measurement Point

(L/2)

TC test point

L

(W/2)
W
Current Specifications ­ Measurement Conditions
IDD, IPP, and IDDQ Measurement Conditions
IDD, IPP, and IDDQ measurement conditions, such as test load and patterns, are defined in this section.
· IDD currents (IDD0, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R, IDD6N, IDD6E, IDD6R, IDD6A, IDD7, and IDD8) are measured as time-averaged currents with all VDD balls of the device under test grouped together.
· IPP currents are IPP3N for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8), IPP0 for active cases (IDD0,IDD1, IDD4R, IDD4W), IPP5R for the distributed refresh case (IDD5R), IPP6x for self refresh cases (IDD6N, IDD6E, IDD6R, IDD6A) and IPP7 for the operating bank interleave read case (IDD7). These have the same definitions as the IDD currents referenced but are measured on the VPP supply.
· IDDQ currents are measured as time-averaged currents with VDDQ balls of the device under test grouped together. Micron does not specify IDDQ currents.
· IPP and IDDQ currents are not included in IDD currents, IDD and IDDQ currents are not included in IPP currents, and IDD and IPP currents are not included in IDDQ currents.
Note: IDDQ values cannot be directly used to calculate the I/O power of the device. They can be used to support correlation of simulated I/O power to actual I/O power. In DRAM module application, IDDQ cannot be measured separately because VDD and VDDQ are using a merged-power layer in the module PCB.
The following definitions apply for IDD, IPP and IDDQ measurements.
· "0" and "LOW" are defined as VIN VIL(AC)max · "1" and "HIGH" are defined as VIN VIH(AC)min · "Midlevel" is defined as inputs VREF = VDD/2 · Timings used for IDD, IPP and IDDQ measurement-loop patterns are provided in the
Current Test Definition and Patterns section.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Measurement Conditions

· Basic IDD, IPP, and IDDQ measurement conditions are described in the Current Test Definition and Patterns section.
· Detailed IDD, IPP, and IDDQ measurement-loop patterns are described in the Current Test Definition and Patterns section.
· Current measurements are done after properly initializing the device. This includes, but is not limited to, setting: RON = RZQ/7 (34 ohm in MR1); Qoff = 0B (output buffer enabled in MR1); RTT(NOM) = RZQ/6 (40 ohm in MR1); RTT(WR) = RZQ/2 (120 ohm in MR2); RTT(Park) = disabled; TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR3; Gear-down mode disabled in MR3; Read/Write DBI disabled in MR5; DM disabled in MR5
· Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA changes when directed.
· Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply invert of BG/BA changes when directed above.
Note: The measurement-loop patterns must be executed at least once before actual current measurements can be taken.
Figure 246: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx

IDD

IPP

IDDQ

VDD

VPP

RESET_n CK_t/CK_c

DDR4

CKE

SDRAM

CS_n C ACT_n, RAS_n, CAS_n, WE_n

VDDQ
DQS_t, DQS_c DQ
DM_n

A, BG, BA

ODT

ZQ

VSS

VSSQ

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Measurement Conditions

Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power

Applic ation-s pe c ific memory c ha nne l env ironmen t

IDD Q tes t loa d

C hanne l I/O pow er simulation

IDD Q s im u la tio n

IDD Q meas ure ment

C orre c tion

C or relation

C hanne l I/O power number
Note: 1. Supported by IDDQ measurement.
IDD Definitions

Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions

Symbol IDD0
IPP0 IDD1
IDD2N

Description
Operating One Bank Active-Precharge Current (AL = 0) CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the next table; Data I/O: VDDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table
Operating One Bank Active-Precharge IPP Current (AL = 0) Same conditions as IDD0 above
Operating One Bank Active-Read-Precharge Current (AL = 0) CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
Precharge Standby Current (AL = 0) CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Measurement Conditions

Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)

Symbol IDD2NT
IDD2P IDD2Q IDD3N
IPP3N IDD3P IDD4R
IDD4W

Description
Precharge Standby ODT Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern details: see the IDD2NT Measurement-Loop Pattern table
Precharge Power-Down Current CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Precharge Quiet Standby Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Active Standby Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
Active Standby IPP3N Current (AL = 0) Same conditions as IDD3N above
Active Power-Down Current (AL = 0) CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Operating Burst Read Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;15 AL: 0; CS_n: HIGH between RD; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measurement-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the next one according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table); Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Measurement-Loop Pattern table
Operating Burst Write Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measurement-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the next one according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see the IDD4W Measurement-Loop Pattern table

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Measurement Conditions

Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)

Symbol IDD5R
IPP5R IDD6N
IDD6E
IPP6x IDD6R
IDD7
IPP7 IDD8

Description
Distributed Refresh Current (1X REF) CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF; Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal: stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table
Distributed Refresh Current (1X REF) Same conditions as IDD5R above
Self Refresh Current: Normal Temperature Range TC: 0­85°C; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
Self Refresh Current: Extended Temperature Range 4 TC: 0­95°C; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
Self Refresh IPP Current Same conditions as IDD6E above
Self Refresh Current: Reduced Temperature Range TC: 0­45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
Operating Bank Interleave Read Current CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;15 AL: CL 1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1; Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7 Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD7 Measurement-Loop Pattern table
Operating Bank Interleave Read IPP Current Same conditions as IDD7 above
Maximum Power Down Current Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0

Notes:

1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.
2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON = RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001 (RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).
3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Measurement Conditions
4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended temperature range.
5. READ burst type: Nibble sequential, set MR0[3] 0. 6. In the dual-rank DDP case, note the following IDD measurement considerations:
· For all IDD measurements except IDD6, the unselected rank should be in an IDD2P condition.
· For all IPP measurements except IPP6, the unselected rank should be in an IDD3N condition.
· For all IDD6/IPP6 measurements, both ranks should be in the same IDD6 condition.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Current Specifications ­ Patterns and Test Conditions
Current Test Definitions and Patterns
Table 136: IDD0 and IPP0 Measurement-Loop Pattern1

CK_t, CK_c CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data3

0

0

ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0

­

1, 2

D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0

­

3, 4 D_n, 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

D_n

...

Repeat pattern 1...4 until nRAS - 1; truncate if necessary

nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0

­

...

Repeat pattern 1...4 until nRC - 1; truncate if necessary

1 1 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead

2 2 × nRC

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 3 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 4 × nRC

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 5 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 6 × nRC

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 7 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 8 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 9 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 10 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 11 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 12 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 13 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 14 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 15 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes:

1. DQS_t, DQS_c are VDDQ. 2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ. 4. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Table 137: IDD1 Measurement ­ Loop Pattern1

CK_c, CK_t, CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Data3

Toggling Static High

0

0

ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0

­

1, 2

D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0

­

3, 4

D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

...

Repeat pattern 1...4 until nRCD - AL - 1; truncate if necessary

nRCD - AL ...
nRAS ...

RD

0 1 1 0 1 0 0 0 0 0 0 0 0 0 D0 = 00, D1 =

Repeat pattern 1...4 until nRAS - 1; truncate if necessary PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0
Repeat pattern 1...4 until nRC - 1; truncate if necessary

FF, D2 = FF, D3 =
00, D4 = FF, D5 =

00,

D5 = 00, D7 = FF

1 1 × nRC + 0 ACT 0 0 0 1 1 0 1 1 0 0 0 0 0 0

­

1 × nRC + 1, D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0

­

2

1 × nRC + 3, D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

4

...

Repeat pattern nRC + 1...4 until 1 × nRC + nRAS - 1; truncate if necessary

1 × nRC +nRCD - AL
... 1 × nRC +
nRAS ...

RD

0110101100000

Repeat pattern 1...4 until nRAS - 1; truncate if necessary PRE 0 1 0 1 0 0 1 1 0 0 0 0 0

Repeat pattern nRC + 1...4 until 2 × nRC - 1; truncate if necessary

0 D0 = FF, D1 =

00,

D2 = 00, D3 =

0

FF,

D4 = 00, D5 =

FF,

D5 = FF, D7 = 00

2 2 × nRC

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 3 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 4 × nRC

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 5 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 6 × nRC

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 7 × nRC

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 9 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 10 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 11 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 12 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 13 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 14 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 15 × nRC

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 16 × nRC

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes: 1. DQS_t, DQS_c are VDDQ when not toggling.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ com-
mand. 4. For x4 and x8 only.
Table 138: IDD2N, IDD3N, and IPP3P Measurement ­ Loop Pattern1

CK_c, CK_t, CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data3

0

0

D 10000000000000

­

1

D 10000000000000

­

2

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

3

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

1

4­7

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead

2 8­11

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 12­15

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 16­19

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 20­23

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 24­27

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 28­31

Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 32­35

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 36­39

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 40­43

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 44­47

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 48­51

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 52­55

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 56­59

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 60­63

Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes:

1. DQS_t, DQS_c are VDDQ. 2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ. 4. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Table 139: IDD2NT Measurement ­ Loop Pattern1

CK_c, CK_t, CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data3

0

0

1

2

3

1

4­7

2 8­11

3 12­15

4 16­19

5 20­23

6 24­27

7 28­31

8 32­35

9 36­39

10 40­43

11 44­47

12 48­51

13 52­55

14 56­59

15 60­63

D 10000000000000

­

D 10000000000000

­

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4

Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes:

1. DQS_t, DQS_c are VSSQ. 2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VSSQ. 4. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Table 140: IDD4R Measurement ­ Loop Pattern1

CK_c, CK_t, CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data3

0

0

1

2, 3

1

4

5

6, 7

2

8­11

3

12­15

4

16­19

5

20­23

6

24­27

7

28­31

8

32­35

9

36­39

10 40­43

11 44­47

12 48­51

13 52­55

14 56­59

15 60­63

RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 D0 = 00, D1 =

D 10000000000000

FF,

D_n, 1 1 1 1 1 0 3 3 0 0 0 7 F 0 D2 = FF, D3 =

D_n

00, D4 = FF, D5 =

00,

D5 = 00, D7 =

FF

RD 0 1 1 0 1 0 1 1 0 0 0 7 F 0 D0 = FF, D1 = 00

D

1 0 0 0 0 0 0 0 0 0 0 0 0 0 D2 = 00, D3 =

D_n, 1 1 1 1 1 0 3 3 0 0 0 7 F 0

FF

D4 = 00, D5 =

D_n

FF

D5 = FF, D7 = 00

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes:

1. DQS_t, DQS_c are VDDQ when not toggling. 2. BG1 is a "Don't Care" for x16 devices.
3. Burst sequence driven on each DQ signal by a READ command. Outside burst operation, DQ signals are VDDQ.
4. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions

Table 141: IDD4W Measurement ­ Loop Pattern1

CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A1
6 CAS_n/A1
5 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,1
1]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data3

0

0

WR 0 1 1 0 0 1 0 0 0 0 0 0 0 0 D0 = 00, D1 = FF,

1

D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 D2 = FF, D3 = 00,

D4 = FF, D5 = 00,

2, 3

D_n, 1 1 1 1 0 1 3 3 0 0 0 7 F 0 D5 = 00, D7 = FF

D_n

1

4

WR 0 1 1 0 0 1 1 1 0 0 0 7 F 0 D0 = FF, D1 = 00

5

D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 D2 = 00, D3 = FF

D4 = 00, D5 = FF

6, 7 D_n, 1 1 1 1 0 1 3 3 0 0 0 7 F 0

D_n

D5 = FF, D7 = 00

2 8­11

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 12­15

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 16­19

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 20­23

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 24­27

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 28­31

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 32­35

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 36­39

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 40­43

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 44­47

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 48­51

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 52­55

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 56­59

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 60­63

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes:

1. DQS_t, DQS_c are VDDQ when not toggling. 2. BG1 is a "Don't Care" for x16 devices.
3. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation, DQ signals are VDDQ.
4. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Table 142: IDD4Wc Measurement ­ Loop Pattern1

CK_c, CK_t, CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]3 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data4

0

0

WR 0 1 1 0 0 1 0 0 0 0 0 0 0 0 D0 = 00, D1 = FF,

1, 2

D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 D2 = FF, D3 = 00,

3, 4

D_n, 1 1 1 1 0 1 3 3 0 0 0 7 F 0 D4 = FF, D5 = 00,

D_n

D8 = CRC

1

5

WR 0 1 1 0 0 1 1 1 0 0 0 7 F 0 D0 = FF, D1 = 00,

6, 7

D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 D2 = 00, D3 = FF,

8, 9

D_n, 1

1

1

1

0

1

3

3

0

0

0

7

F

0

D4 = 00, D5 = FF, D5 = FF, D7 = 00

D_n

D8 = CRC

2 10­14

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3 15­19

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

4 20­24

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

5 25­29

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

6 30­34

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

7 35­39

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

8 40­44

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4

9 45­49

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4

10 50­54

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4

11 55­59

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4

12 60­64

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4

13 65­69

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4

14 70­74

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4

15 75­79

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4

Notes:

1. Pattern provided for reference only. 2. DQS_t, DQS_c are VDDQ when not toggling. 3. BG1 is a "Don't Care" for x16 devices. 4. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ. 5. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Table 143: IDD5R Measurement ­ Loop Pattern1

CK_c, CK_t, CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Toggling Static High

Data3

0

0

REF 0 1 0 0 1 0 0 0 0 0 0 0 0 0

­

1

1

D 10000000000000

­

2

D 10000000000000

­

3

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

4

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

5­8

Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 1 instead

9­12

Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 2 instead

13­16

Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 3 instead

17­20

Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 1 instead

21­24

Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 2 instead

25­28

Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 3 instead

29­32

Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 0 instead

33­36

Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 0 instead4

37­40

Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 1 instead4

41­44

Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 2 instead4

45­48

Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 3 instead4

49­52

Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 1 instead4

53­56

Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 2 instead4

57­60

Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 3 instead4

61­64

Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 0 instead4

2 65...nREFI 1

Repeat sub-loop 1; truncate if necessary

Notes:

1. DQS_t, DQS_c are VDDQ. 2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ. 4. For x4 and x8 only.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions
Table 144: IDD7 Measurement ­ Loop Pattern1

CK_t, CK_c CKE
Sub-Loop Cycle
Number Command
CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14
ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP
A[9:7] A[6:3] A[2:0]

Data3

Toggling Static High

0

0

ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0

­

1

RDA 0 1 1 0 1 0 0 0 0 0 1 0 0 0

2

D 10000000000000

­

3

D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0

­

...

Repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary

1

nRRD

ACT 0 0 0 0 0 0 1 1 0 0 0 0 0 0

­

nRRD+1

RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0

...

Repeat pattern 2...3 until 2 × nRRD - 1, if nRRD > 4. Truncate if necessary

2

2 × nRRD

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead

3

3 × nRRD

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead

4

4 × nRRD

Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessary

5

nFAW

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead

6

nFAW + nRRD

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead

7 nFAW + 2 × nRRD

Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead

8 nFAW + 3 × nRRD

Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead

9 nFAW + 4 × nRRD

Repeat sub-loop 4

10

2 × nFAW

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead

11 2 × nFAW + nRRD

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead

12 2 × nFAW + 2 × nRRD

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead

13 2 × nFAW + 3 × nRRD

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead

14 2 × nFAW + 4 × nRRD

Repeat sub-loop 4

15

3 × nFAW

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead

16 3 × nFAW + nRRD

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead

17 3 × nFAW + 2 × nRRD

Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead

18 3 × nFAW + 3 × nRRD

Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead

19 3 × nFAW + 4 × nRRD

Repeat sub-loop 4

20

4 × nFAW

Repeat pattern 2...3 until nRC - 1, if nRC > 4 × nFAW. Truncate if necessary

Notes:

1. DQS_t, DQS_c are VDDQ. 2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Patterns and Test Conditions

IDD Specifications

4. For x4 and x8 only.

Table 145: Timings used for IDD, IPP, and IDDQ Measurement ­ Loop Patterns DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933

DDR4-3200

10-10-10 11-11-11 12-12-12 12-12-12 13-13-13 14-14-14 14-14-14 15-15-15 16-16-16 16-16-16 17-17-17 18-18-18 18-18-18 19-19-19 20-20-20 20-20-20 21-21-21 22-22-22 20-20-20 22-22-22 24-24-24

Symbol

tCK

1.25

CL

10 11 12

CWL 9 11 11

nRCD 10 11 12

nRC 38 39 40

nRP 10 11 12

nRAS

28

nFA x41

16

W x8

20

x1

28

6

nRRD x4

4

_S x8

4

x1

5

6

nRRD x4

5

_L x8

5

x1

6

6

nCCD_S

4

nCCD_L

5

nWTR_S

2

nWTR_L

6

nREFI

6,240

nRFC 2Gb

128

nRFC 4Gb

208

nRFC 8Gb

280

nRFC

280

16Gb

1.071 12 13 14 10 12 12 12 13 14 44 45 46 12 13 14
32 16 22 28
4 4 6
5 5 6
4 5 3 7 7,283 150 243 327 327

0.937 14 15 16 11 14 14 14 15 16 50 51 52 14 15 16
36 16 23 32
4 4 6
6 6 7
4 6 3 8 8,325 171 278 374 374

0.833 16 17 18 16 16 16 16 17 18 55 56 57 16 17 18
39 16 26 36
4 4 7
6 6 8
4 6 3 9 9,364 193 313 421 421

0.75 18 19 20 18 18 18 18 19 20 61 62 63 18 19 20
43 16 28 40
4 4 8
7 7 9
4 7 4 10 10,400 214 347 467 467

0.682 20 21 22 14 18 18 19 20 21 66 67 68 19 20 21
47 16 31 44
4 4 8
8 8 10
4 8 4 11 11,437 235 382 514 514

Uni t

0.625

ns

20 22 24 CK

16 20 20 CK

20 22 24 CK

72 74 76 CK

20 22 24 CK

52

CK

16

CK

34

CK

48

CK

4

CK

4

CK

9

CK

8

CK

8

CK

11

CK

4

CK

8

CK

4

CK

12

CK

12,480

CK

256

CK

416

CK

560

CK

560

CK

Note: 1. 1KB based x4 use same numbers of clocks for nFAW as the x8.

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Current Specifications ­ Limits

4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 146: IDD, IPP, and IDDQ Current Limits ­ Rev. A (0°  TC  85°C)

Symbol

Width

IDD0: One bank ACTIVATE-to-PRECHARGE current

x4, x8 x16

IPP0: One bank ACTIVATE-to-PRECHARGE x4, x8

IPP current

x16

IDD1: One bank ACTIVATE-to-READ-toPRECHARGE current

x4, x8 x16

DDR4-1600 58 66 4 4.6 63 78

DDR4-1866 58 66 4 4.6 63 78

DDR4-2133 60 68 4 4.6 65 80

DDR4-2400 64 70 4 4.6 68 83

Unit mA mA mA mA mA mA

IDD2N: Precharge standby current

ALL

44

44

46

50

mA

IDD2NT: Precharge standby ODT current x4, x8

50

50

54

58

mA

x16

60

60

64

68

mA

IDD2P: Precharge power-down current

ALL

30

30

30

32

mA

IDD2Q: Precharge quiet standby current

ALL

39

39

39

41

mA

IDD3N: Active standby current

ALL

61

61

63

67

mA

IPP3N: Active standby IPP current

ALL

3

3

3

3

mA

IDD3P: Active power-down current

ALL

44

44

44

44

mA

IDD4R: Burst read current

x4, x8

140

140

150

160

mA

x16

200

200

215

230

mA

IDD4W: Burst write current

x4, x8

156

156

176

196

mA

x16

246

246

276

314

mA

IDD5R: Distributed refresh current (1X

x4, x8

68

68

70

73

mA

REF)

x16

68

68

70

73

mA

IPP5R: Distributed refresh IPP current (1X x4, x8

4

4

4

4

mA

REF)

x16

4

4

4

4

mA

IDD6N: Self refresh current; 0­85°C1

ALL

20

20

20

20

mA

IDD6E: Self refresh current; 0­95°C2

ALL

27

27

27

27

mA

IDD6R: Self refresh current; 0­45C3, 4

ALL

10

10

10

10

mA

IDD6A: Auto self refresh current (25°C)4

ALL

9

9

9

9

mA

IDD6A: Auto self refresh current (45°C)4

ALL

10

10

10

10

mA

IDD6A: Auto self refresh current (75°C)4

ALL

16

16

16

16

mA

IPP6x: Auto self refresh current23

ALL

3

3

3

3

mA

IDD7: Bank interleave read current

x4, x8

160

160

185

210

mA

x16

230

230

240

250

mA

IPP7: Bank interleave read IPP current

x4, x8

10

10

12

14

mA

x16

12

12

14

16

mA

IDD8: Maximum power-down current

ALL

18

18

18

18

mA

Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0­85°C).

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0­95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0­45°C).
4. IDD6R, IDD6A, IDD6E and values are verified by design and characterization, and may not be subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately +0%. 6. When additive latency is enabled for IDD1 , current changes by approximately +5% (x4/
x8), +4% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately +1%. 8. When DLL is disabled for IDD2N, current changes by approximately 0%. 9. When CAL is enabled for IDD2N, current changes by approximately ­44%. 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +14%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +2%
(x4/8), +1% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +8%
(2133/2400), ­5% (1600/1866).
18. When CA parity is enabled for IDD4W, current changes by approximately +14% (x8), +8% (x16).
19. When 2X REF is enabled for IDD5R, current changes by approximately ­14%. 20. When 4X REF is enabled for IDD5R, current changes by approximately ­33%. 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests. 23. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.

Table 147: IDD, IPP, and IDDQ Current Limits ­ Rev. B (0°  TC  85°C)

Symbol

Width DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit

IDD0: One bank ACTIVATE- x4, x8

54

54

56

59

61

64

mA

to-PRECHARGE current

x16

68

68

69

72

76

80

mA

IPP0: One bank ACTIVATE- ALL

4

4

4

4

4

4

mA

to-PRECHARGE IPP current

IDD1: One bank ACTIVATE- x4, x8

71

71

73

76

81

86

mA

to-READ-to- PRECHARGE x16

93

93

97

100

105

110

mA

current

IDD2N: Precharge standby ALL

40

40

41

42

44

46

mA

current

IDD2NT: Precharge standby x4, x8

49

49

50

54

58

62

mA

ODT current

x16

54

54

56

58

62

66

mA

IDD2P: Precharge power-

ALL

22

22

22

22

22

23

mA

down current

IDD2Q: Precharge quiet

ALL

35

35

36

36

37

38

mA

standby current

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 147: IDD, IPP, and IDDQ Current Limits ­ Rev. B (0°  TC  85°C) (Continued)

Symbol

Width DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit

IDD3N: Active standby cur- ALL

56

56

57

58

60

63

mA

rent

IPP3N: Active standby IPP

ALL

3

3

3

3

3

3

mA

current

IDD3P: Active power-down ALL

33

33

33

33

34

35

mA

current

IDD4R: Burst read current

x4

135

135

135

145

160

170

mA

x8

153

153

157

169

169

206

mA

x16

230

230

236

255

287

315

mA

IDD4W: Burst write current x4

117

117

117

125

130

145

mA

x8

130

130

130

140

155

169

mA

x16

175

175

179

193

216

236

mA

IDD5R: Distributed refresh ALL

64

64

65

66

68

71

mA

current (1X REF)

IPP5R: Distributed refresh ALL

5

5

5

5

5

5

mA

IPP current (1X REF)

IDD6N: Self refresh current; ALL

24

24

24

24

24

24

mA

0­85°C1

IDD6E: Self refresh current; ALL

47

47

47

47

47

47

mA

0­95°C2

IDD6R: Self refresh current; ALL

25

25

25

25

25

25

mA

0­45C3, 4

IDD6A: Auto self refresh

ALL

9

9

9

9

9

9

mA

current (25°C)4

IDD6A: Auto self refresh

ALL

12

12

12

12

12

12

mA

current (45°C)4

IDD6A: Auto self refresh

ALL

47

47

47

47

47

47

mA

current (75°C)4

IPP6x: Auto self refresh

ALL

3

3

3

3

3

3

mA

current24

IDD7: Bank interleave read x4

191

191

196

210

225

240

mA

current

x8

206

206

211

225

240

255

x16

281

281

289

297

320

348

mA

IPP7: Bank interleave read x4, x8

14

14

14

14

14

15

mA

IPP current

x16

21

21

21

21

21

24

mA

IDD8: Maximum power-

ALL

19

19

19

19

19

19

mA

down current

Notes:

1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0­85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0­95°C).

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0­45°C).
4. IDD6R, IDD6A, IDD6E and values are verified by design and characterization, and may not be subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately +9%. 6. When additive latency is enabled for IDD1 , current changes by approximately +14% (x4/
x8), +14% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately 0%. 8. When DLL is disabled for IDD2N, current changes by approximately +1%. 9. When CAL is enabled for IDD2N, current changes by approximately ­34%. 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +15%. 12. When additive latency is enabled for IDD3N, current changes by approximately +9%. 13. When additive latency is enabled for IDD4R, current changes by approximately +6%. 14. When read DBI is enabled for IDD4R, current changes by approximately -8%. 15. When additive latency is enabled for IDD4W, current changes by approximately +6%
(x4/8), +4% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately +13%. 17. When write CRC is enabled for IDD4W, current changes by approximately +4%. 18. When CA parity is enabled for IDD4W, current changes by approximately +15% (x4/x8),
+10% (x16).
19. When 2X REF is enabled for IDD5R, current changes by approximately ­16%. 20. When 4X REF is enabled for IDD5R, current changes by approximately ­35%. 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 uses the same IDD limits as DDR4-1866. 24. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.

Table 148: IDD, IPP, and IDDQ Current Limits ­ Rev. E (0°  TC  85°C)

Symbol

Width

IDD0: One bank ACTIVATE-to- x4

PRECHARGE current

x8

x16

IPP0: One bank ACTIVATE-toPRECHARGE IPP current

x4, x8 x16

IDD1: One bank ACTIVATE-to- x4 READ-to- PRECHARGE current x8

x16

IDD2N: Precharge standby cur- ALL rent

IDD2NT: Precharge standby ODT current

x4, x8 x16

IDD2P: Precharge power-down ALL current

IDD2Q: Precharge quiet stand- ALL by current

DDR4-2133 40 45 75 3 4 52 57 95 33
45 67 25
30

DDR4-2400 43 48 80 3 4 55 60 100 34
50 75 25
30

DDR4-2666 46 51 85 3 4 58 63 105 35
50 75 25
30

DDR4-2933 49 54 90 3 4 61 66 110 36
55 78 25
30

DDR4-3200 52 57 95 3 4 64 69 115 37
60 81 25
30

Unit mA mA mA mA mA mA mA mA mA
mA mA mA
mA

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 148: IDD, IPP, and IDDQ Current Limits ­ Rev. E (0°  TC  85°C) (Continued)

Symbol

Width

IDD3N: Active standby current x4 x8

x16

IPP3N: Active standby IPP cur-

ALL

rent

IDD3P: Active power-down

x4

current

x8

x16

IDD4R: Burst read current

x4

x8

x16

IDD4W: Burst write current

x4

x8

x16

IDD5R: Distributed refresh cur- x4, x8

rent (1X REF)

x16

IPP5R: Distributed refresh IPP

ALL

current (1X REF)

IDD6N: Self refresh current; 0­ ALL 85°C1

IDD6E: Self refresh current; 0­ ALL 95°C2

IDD6R: Self refresh current; 0­ ALL 45C3, 4

IDD6A: Auto self refresh cur-

ALL

rent (25°C)4

IDD6A: Auto self refresh cur-

ALL

rent (45°C)4

IDD6A: Auto self refresh cur-

ALL

rent (75°C)4

IPP6x: Auto self refresh cur-

ALL

rent25

IDD7: Bank interleave read

x4

current

x8

x16

IPP7: Bank interleave read IPP

x4

current

x8

x16

DDR4-2133 40 45 49 3
30 35 39 100 125 225 105 125 225 48 61 4
24
27
18
8.6
18
24
4
175 170 239 16 15 20

DDR4-2400 43 48 52 3
32 37 41 110 135 243 113 132 240 50 64 4
24
27
18
8.6
18
24
4
185 175 249 17 15 20

DDR4-2666 46 51 55 3
34 39 43 121 146 263 122 142 255 52 67 4
24
27
18
8.6
18
24
4
200 180 259 18 15 20

DDR4-2933 49 54 58 3
36 41 45 132 157 283 130 150 270 55 69 4
24
27
18
8.6
18
24
4
215 185 269 19 15 20

DDR4-3200 52 56 61 3
38 43 47 143 168 302 140 160 290 57 72 4
24
27
18
8.6
18
24
4
230 190 279 20 15 20

Unit mA mA mA mA
mA mA mA mA mA mA mA mA mA mA mA mA
mA
mA
mA
mA
mA
mA
mA
mA mA mA mA mA mA

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 148: IDD, IPP, and IDDQ Current Limits ­ Rev. E (0°  TC  85°C) (Continued)

Symbol
IDD8: Maximum power-down current

Width ALL

DDR4-2133 25

DDR4-2400 25

DDR4-2666 25

DDR4-2933 25

DDR4-3200 25

Unit mA

Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0­85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0­95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0­45°C).
4. IDD6R, IDD6A, IDD6E and values are verified by design and characterization, and may not be subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately 0%. 6. When additive latency is enabled for IDD1 , current changes by approximately +5% (x4/
x8), +4% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately 0%. 8. When DLL is disabled for IDD2N, current changes by approximately -23%. 9. When CAL is enabled for IDD2N, current changes by approximately ­25%. 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +7%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%
(x4/8), +4% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +10%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12. 19. When 2X REF is enabled for IDD5R, current changes by approximately ­14%. 20. When 4X REF is enabled for IDD5R, current changes by approximately ­33%. 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 24. The IDD values must be derated (increased) when operated outside of the range 0°C  TC
 85°C:
When TC < 0°C: IDD2P, and IDD3P must be derated by +6%; IDD4R and IDD4W must be derated by +4%; IDD6, IDD6ET, and IDD7 must be derated by +11%.
When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, and IDD4W must be derated by +3%; IDD2P must be derated by +40%; and IDD5R and IPP5R must be derated by +30%. These values are verified by design and characterization, and may not be subject to production test.
25. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 149: IDD, IPP, and IDDQ Current Limits ­ Rev. F (-40°  TC  85°C)

Symbol

Width

IDD0: One bank ACTIVATE-to- x4

PRECHARGE current

x8

x16

IPP0: One bank ACTIVATE-toPRECHARGE IPP current

x4, x8 x16

IDD1: One bank ACTIVATE-to- x4 READ-to- PRECHARGE current x8

x16

IDD2N: Precharge standby cur- ALL rent

IDD2NT: Precharge standby ODT current

x4, x8 x16

IDD2P: Precharge power-down ALL current

IDD2Q: Precharge quiet stand- ALL by current

IDD3N: Active standby current x4 x8

x16

IPP3N: Active standby IPP cur-

ALL

rent

IDD3P: Active power-down

x4

current

x8

x16

IDD4R: Burst read current

x4

x8

x16

IDD4W: Burst write current

x4

x8

x16

IDD5R: Distributed refresh cur- ALL rent (1X REF)

IPP5R: Distributed refresh IPP

ALL

current (1X REF)

IDD6N: Self refresh current;

ALL

-40­85°C1

IDD6E: Self refresh current;

ALL

-40­95°C2,4

IDD6R: Self refresh current;

ALL

-40­45°C3, 4

DDR4-2133 37 39 46 3 4 50 55 72 29
36 43 22
26
34 35 36 3
28 29 30 110 135 235 96 114 182 39
5
24
44
16

DDR4-2400 39 41 48 3 4 52 57 74 30
38 46 22
26
36 37 38 3
29 30 31 120 145 253 105 123 199 40
5
24
44
16

DDR4-2666 41 43 50 3 4 54 59 76 31
40 49 22
26
38 39 40 3
30 31 32 131 156 273 114 132 216 41
5
24
44
16

DDR4-2933 43 45 52 3 4 56 61 78 32
42 52 22
26
40 41 42 3
31 32 33 142 167 293 123 141 233 42
5
24
44
16

DDR4-3200 45 47 54 3 4 58 63 80 33
44 55 22
26
42 43 44 3
32 33 34 153 178 312 132 150 250 43
5
24
44
16

Unit mA mA mA mA mA mA mA mA mA
mA mA mA
mA
mA mA mA mA
mA mA mA mA mA mA mA mA mA mA
mA
mA
mA
mA

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 149: IDD, IPP, and IDDQ Current Limits ­ Rev. F (-40°  TC  85°C) (Continued)

Symbol

Width

IDD6A: Auto self refresh cur-

ALL

rent (25°C)4

IDD6A: Auto self refresh cur-

ALL

rent (45°C)4

IDD6A: Auto self refresh cur-

ALL

rent (75°C)4

IDD6A: Auto self refresh cur-

ALL

rent (95°C)4

IPP6x: Auto self refresh IPP cur- ALL rent; -40­95°C27

IDD7: Bank interleave read

x4

current

x8

x16

IPP7: Bank interleave read IPP

x4

current

x8

x16

IDD8: Maximum power-down ALL current

DDR4-2133 8.6
16
23
44
5
175 170 234 14 13 18 18

DDR4-2400 8.6
16
23
44
5
185 175 243 14 13 18 18

DDR4-2666 8.6
16
23
44
5
200 180 252 14 13 18 18

DDR4-2933 8.6
16
23
44
5
215 185 261 14 13 18 18

DDR4-3200 8.6
16
23
44
5
230 190 270 14 13 18 18

Unit mA
mA
mA
mA
mA
mA mA mA mA mA mA mA

Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0­85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0­95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0­45°C).
4. IDD6R, IDD6A, IDD6E and values are verified by design and characterization, and may not be subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately +1%. 6. When additive latency is enabled for IDD1 , current changes by approximately +8% (x4/
x8), +7% (x16).
7. When additive latency is enabled for IDD2N , current changes by approximately +1%. 8. When DLL is disabled for IDD2N, current changes by approximately -6%. 9. When CAL is enabled for IDD2N, current changes by approximately ­30%. 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +10%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +4%. 14. When read DBI is enabled for IDD4R, current changes by approximately -14%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%
(x4/8), +4% (x16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately -5%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12%. 19. When 2X REF is enabled for IDD5R, current changes by approximately +0%. 20. When 4X REF is enabled for IDD5R, current changes by approximately +0%.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

21. When 2X REF is enabled for IPP5R, current changes by approximately +0%.
22. When 4X REF is enabled for IPP5R, current changes by approximately +0%.
23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests.
25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 26. The IDD and IPP values must be derated (increased) when operating between 85°C < TC 
95°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, and IDD4W must be derated by +3%; IDD2P must be derated by +10%; IDD5R and IPP5R must be derated by +33%; All IPP currents except IPP6x and IPP5R must be derated by +0%;. These values are verified by design and characterization, and may not be subject to production test.
27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.

Table 150: IDD, IPP, and IDDQ Current Limits ­ Rev. G (-40°  TC  85°C)

Symbol

Width

IDD0: One bank ACTIVATE-to- x4

PRECHARGE current

x8

x16

IPP0: One bank ACTIVATE-toPRECHARGE IPP current

x4, x8 x16

IDD1: One bank ACTIVATE-to- x4 READ-to- PRECHARGE current x8

x16

IDD2N: Precharge standby cur- ALL rent

IDD2NT: Precharge standby ODT current

x4, x8 x16

IDD2P: Precharge power-down ALL current

IDD2Q: Precharge quiet stand- ALL by current

IDD3N: Active standby current x4 x8

x16

IPP3N: Active standby IPP cur-

ALL

rent

IDD3P: Active power-down

x4

current

x8

x16

IDD4R: Burst read current

x4

x8

x16

DDR4-2133 35 37 44 3 4 48 52 68 28
34 41 22
26
34 35 36 3
28 29 30 105 128 223

DDR4-2400 37 39 46 3 4 50 54 70 29
36 44 22
26
36 37 38 3
29 30 31 114 138 240

DDR4-2666 39 41 48 3 4 51 56 72 30
38 47 22
26
38 39 40 3
30 31 32 125 148 260

DDR4-2933 41 43 50 3 4 53 58 74 30
40 50 22
26
40 41 42 3
31 32 33 135 158 278

DDR4-3200 43 44 52 3 4 55 60 76 31
42 53 22
26
42 43 44 3
32 33 34 145 169 296

Unit mA mA mA mA mA mA mA mA mA
mA mA mA
mA
mA mA mA mA
mA mA mA mA mA mA

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits

Table 150: IDD, IPP, and IDDQ Current Limits ­ Rev. G (-40°  TC  85°C) (Continued)

Symbol

Width

IDD4W: Burst write current

x4

x8

x16

IDD5R: Distributed refresh cur- ALL rent (1X REF)

IPP5R: Distributed refresh IPP

ALL

current (1X REF)

IDD6N: Self refresh current;

ALL

-40­85°C1

IDD6E: Self refresh current;

ALL

-40­95°C2,4

IDD6R: Self refresh current;

ALL

-40­45°C3, 4

IDD6A: Auto self refresh cur-

ALL

rent (25°C)4

IDD6A: Auto self refresh cur-

ALL

rent (45°C)4

IDD6A: Auto self refresh cur-

ALL

rent (75°C)4

IDD6A: Auto self refresh cur-

ALL

rent (95°C)4

IPP6x: Auto self refresh IPP cur- ALL rent; -40­95°C27

IDD7: Bank interleave read

x4

current

x8

x16

IPP7: Bank interleave read IPP

x4

current

x8

x16

IDD8: Maximum power-down ALL current

DDR4-2133 91 108 173 38
5
25
44
16
6.2
16
30
44
5
166 161 222 11 10 15 18

DDR4-2400 100 116 189 39
5
25
44
16
6.2
16
30
44
5
176 166 231 11 10 15 18

DDR4-2666 108 125 205 40
5
25
44
16
6.2
16
30
44
5
190 171 240 11 10 15 18

DDR4-2933 117 134 221 41
5
25
44
16
6.2
16
30
44
5
205 175 248 11 10 15 18

DDR4-3200 126 142 238 42
5
25
44
16
6.2
16
30
44
5
219 180 257 11 13 15 18

Unit mA mA mA mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA mA mA mA mA mA mA

Notes:

1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (0­85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (0­95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (0­45°C).
4. IDD6R, IDD6A, IDD6E and values are verified by design and characterization, and may not be subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately +1%. 6. When additive latency is enabled for IDD1 , current changes by approximately +8%(x4/
x8), +7%(x16).
7. When additive latency is enabled for IDD2N , current changes by approximately +1%.

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4Gb: x4, x8, x16 DDR4 SDRAM Current Specifications ­ Limits
8. When DLL is disabled for IDD2N, current changes by approximately -6%. 9. When CAL is enabled for IDD2N, current changes by approximately -20%. 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +13%. 12. When additive latency is enabled for IDD3N, current changes by approximately 2%. 13. When additive latency is enabled for IDD4R, current changes by approximately +4%(x4/
x8), +3%(x16).
14. When read DBI is enabled for IDD4R, current changes by approximately -14%(x4/x8), -20%(x16).
15. When additive latency is enabled for IDD4W, current changes by approximately +4%(x4/ x8), +3%(x16).
16. When write DBI is enabled for IDD4W, current changes by approximately +0%. 17. When write CRC is enabled for IDD4W, current changes by approximately -5%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12%. 19. When 2X REF is enabled for IDD5R, current changes by approximately +0%. 20. When 4X REF is enabled for IDD5R, current changes by approximately +0%. 21. When 2X REF is enabled for IPP5R, current changes by approximately +0%. 22. When 4X REF is enabled for IPP5R, current changes by approximately +0%. 23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 26. The IDD values must be derated (increased) when operating between 85°C < TC  95°C:
IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R,IDD4W,IDD7, and IDD8 must be derated by +3%; IDD2P must be derated by +13%; IDD5R and IPP5R must be derated by +43%; All IPP currents except IPP6x and IPP5R must be derated by +0%. These values are verified by design and characterization, and may not be subject to production test.
27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.

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4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables
Speed Bin Tables
DDR4 DRAM timing is primarily covered by two types of tables: the Speed Bin tables in this section and the tables found in the Electrical Characteristics and AC Timing Parameters section. The timing parameter tables define the applicable timing specifications based on the speed rating. The Speed Bin tables on the following pages list the tAA, tRCD, tRP, tRAS, and tRC limits of a given speed mark and are applicable to the CL settings in the lower half of the table provided they are applied in the correct clock range, which is noted.
Backward Compatibility
Although the speed bin tables list the slower data rates, tAA, CL, and CWL, it is difficult to determine whether a faster speed bin supports all of the tAA, CL, and CWL combinations across all the data rates of a slower speed bin. To assist in this process, please refer to the Backward Compatibility table.

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Component Speed Bin

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Table 151: Backward Compatibility Note 1 applies to the entire table

Speed Bin Supported

-125 -125E -107 -107E -093 -093E -083D -083 -083E -075D -075 -075E -068D -068 -068E -062 -062E -062Y

-125 yes yes2 yes yes2 yes yes2 yes yes yes2 yes yes yes yes yes yes yes yes2 yes

-125E yes yes yes yes yes
yes

-107
yes yes2 yes yes2 yes yes yes2 yes yes yes yes yes yes yes yes2 yes

-107E yes yes yes yes
yes

-093
yes yes2 yes yes yes2 yes yes yes yes yes yes yes yes2 yes

-093E -083D
yes yes yes
yes yes2 yes yes
yes yes yes yes yes yes yes2
yes yes

-083
yes yes2 yes yes yes yes yes2 yes

-083E -075D
yes yes yes yes yes yes yes yes yes2
yes yes

-075
yes yes yes yes yes2 yes

-075E -068D
yes yes yes yes yes yes2
yes yes

-068
yes yes yes2 yes

-068E yes

-062
yes yes2 yes

-062E -062Y
yes yes yes

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4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. The backward compatibility table is not meant to guarantee that any new device will be a drop in replacement for an existing part number. Customers should review the operating conditions for any device to determine its suitability for use in their design.
2. This condition exceeds the JEDEC requirement in order to allow additional flexibility for components. However, JEDEC SPD compliance may force modules to only support the JEDEC-defined value. Refer to the SPD documentation for further clarification.

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Table 152: DDR4-1600 Speed Bins and Operating Conditions

Notes 1­3 apply to the entire table DDR4-1600 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE-to-internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Max (MT/s)

Equivalent Speed Bin

tAAmin(ns): non-DB

1333

-

13.50

-

15.00

1600

-125E

13.75

-125

15.00

Supported CL settings

Supported CL settings with read DBI

Supported CWL settings

READ CL: nonDBI
9 10 11 12

READ CL: DBI
11 12 13 14

WRITE CWL
9
9, 11

Symbol tAA
tAA_DBI
tRCD tRP tRAS tRC5

-125E

11-11-11

Min

Max

13.75 (13.50)4

19.006

tAA (MIN) +
2nCK

tAA (MAX) +
2nCK

13.75

­

(13.50)4

13.75

­

(13.50)4

35

9 × tREFI

tRAS +

­

tRP

Symbol Min

Max

tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG)

1.500 1.5006 1.250

1.9006 1.9006 <1.500

9, 106, 11-12 11, 126, 13-14
9, 11

-125

12-12-12

Min

Max

15.00 19.006

tAA (MIN) +
2nCK
15.00

tAA (MAX) +
2nCK
­

15.00

­

35
tRAS + tRP

9 × tREFI ­

Min

Max

Reserved 1.500 1.9006
Reserved 1.250 <1.500
10, 12 12, 14 9, 11

Unit ns
ns
ns
ns
ns ns
Unit ns ns ns ns nCK nCK nCK

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

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Table 153: DDR4-1866 Speed Bins and Operating Conditions

Notes 1­3 apply to the entire table DDR4-1866 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Max (MT/s)

Equivalent tAAmin: non-

Speed Bin

DBI

1333

­

13.50

­

15.00

1600

-125E

13.75

-125

15.00

1866

-107E

13.92

-107

15.00

Supported CL settings

Supported CL settings with read DBI

Supported CWL settings

READ CL: nonDBI
9 10 11 12 13 14

READ CL: DBI 11 12 13 14 15 16

WRITE CWL
9
9, 11
10, 12

-107E

-107

13-13-13

14-14-14

Symbol Min

Max

Min

Max

tAA

13.92

19.006

15.00

19.006

(13.50)4

tAA_DBI tAA (MIN) tAA tAA (MIN) tAA

+ 2nCK (MAX) + + 2nCK (MAX) +

2nCK

2nCK

tRCD

13.92

­

15.00

­

(13.50)4

tRP

13.92

­

15.00

­

(13.50)4

tRAS

34

9 × tREFI

34

9 × tREFI

tRC5

tRAS +

­

tRAS +

­

tRP

tRP

Symbol Min

Max

Min

Max

tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG)

1.500 1.5006 1.250

1.9006 1.9006 <1.500

1.071 <1.250

9, 106 , 11­14 11, 126 , 13­16
9­12

Reserved

1.500

1.9006

Reserved

1.250 <1.500

Reserved

1.071 <1.250

10, 12, 14

12, 14, 16

9­12

Unit ns
ns
ns
ns
ns ns
Unit ns ns ns ns ns ns nCK nCK nCK

349

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4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

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Table 154: DDR4-2133 Speed Bins and Operating Conditions

Notes 1­3 apply to the entire table DDR4-2133 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Max (MT/s)

Equivalent tAAmin (ns):

Speed Bin

non-DBI

1333

­

13.50

­

15.00

1600

-125E

13.75

-125

15.00

1866

-107E

13.92

-107

15.00

2133

-093E

14.06

-093

15.00

Supported CL settings

Supported CL settings with read DBI

Supported CWL settings

READ CL: non-DBI
9 10 11 12 13 14 15 16

READ CL: DBI 11 12 13 14 15 16 18 19

WRITE CWL
9
9 , 11
10, 12
11, 14

-093E

-093

15-15-15

16-16-16

Symbol Min

Max

Min

Max

tAA

14.06

19.006

15.00

19.006

(13.50)4

tAA_DBI tAA (MIN) tAA tAA (MIN) tAA

+ 3nCK (MAX) + + 3nCK (MAX) +

3nCK

3nCK

tRCD

14.06

­

15.00

­

(13.50)4

tRP

14.06

­

15.00

­

(13.50)4

tRAS

33

9 × tREFI

33

9 × tREFI

tRC5

tRAS +

­

tRAS +

­

tRP

tRP

Symbol Min

Max

Min

Max

tCK (AVG) 1.500

1.9006

tCK (AVG) 1.5006 1.9006

tCK (AVG) 1.250 <1.500

tCK (AVG)

tCK (AVG) 1.071 <1.250

tCK (AVG)

tCK (AVG) 0.937 <1.071

tCK (AVG)

9, 106 , 11­16 11, 126 , 13­16, 18-19

9, 10, 11, 12, 14

Reserved

1.500

1.9006

Reserved

1.250 <1.500

Reserved

1.071 <1.250

Reserved

0.937 <1.071

10, 12, 14, 16

12, 14, 16, 19

9, 10, 11, 12, 14

Unit ns
ns
ns
ns
ns ns
Unit ns ns ns ns ns ns ns ns nCK nCK nCK

351

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

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4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

352

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 155: DDR4-2400 Speed Bins and Operating Conditions

353

Notes 1­3 apply to the entire table DDR4-2400 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Equivalent Max (MT/s) Speed Bin

tAAmin (ns):
non-DBI

1333

­

13.50

­

15.00

1600

-125E

13.75

-125

15.00

1866

-107E

13.92

-107

15.00

2133

-093E

14.06

-093

15.00

2400

-083E

13.32

-083

14.16

-083D

15.00

Supported CL settings

Supported CL settings with read DBI

READ CL:
non-DBI 9 10 11 12 13 14 15 16 16 17 18

READ CL: DBI 11 12 13 14 15 16 18 19 19 20 21

Supported CWL settings

-083E

-083

-083D

16-16-16

17-17-17

18-18-18

Symbol Min Max Min Max Min Max Unit

tAA

13.32 19.006 14.16 19.006 15.00 19.006 ns

(13.75)4

tAA_DBI tAA

tAA

tAA

tAA

tAA

tAA

ns

(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +

3nCK 3nCK 3nCK 3nCK 3nCK 3nCK

tRCD 13.32

­

14.16

­

(13.75)4

15.00 19.00 ns

tRP

13.32

­

14.16

­

(13.75)4

15.00 19.00 ns

tRAS

32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns

tRC5 tRAS +

­

tRAS +

­

tRAS +

­

ns

tRP

tRP

tRP

WRITE CWL Symbol Min

Max

Min

Max

Min

Max Unit

9 tCK (AVG) 1.500 1.9006 tCK (AVG) 1.5006 1.9006
9, 11 tCK (AVG) 1.250 <1.500 tCK (AVG)
10, 12 tCK (AVG) 1.071 <1.250 tCK (AVG)
11, 14 tCK (AVG) 0.937 <1.071 tCK (AVG)
12, 16 tCK (AVG) 0.833 <0.937 tCK (AVG) tCK (AVG) 9, 106 , 11­18 11, 126 , 13­16, 18­21
9­12, 14, 16

Reserved 1.500 1.9006 1.250 <1.500
1.071 <1.250
0.937 <1.071
Reserved 0.833 <0.937
10­18 12­16, 18­21

Reserved

ns

1.500 1.9006 ns

Reserved

ns

1.250 <1.500 ns

Reserved

ns

1.071 <1.250 ns

Reserved

ns

0.937 <1.071 ns

Reserved

ns

ns

0.833 <0.937 ns

10, 12, 14, 16, 18 nCK

12, 14, 16, 19, 21 nCK

9-12, 14, 16

9­12, 14, 16 nCK

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

354

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 156: DDR4-2666 Speed Bins and Operating Conditions

355

Notes 1­3 apply to the entire table DDR4-2666 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Equivalent Max (MT/s) Speed Bin

1333

-

-

1600

-125E

-125

1866

-107E

-107

2133

-093E

-093

2400

-083E

-083

-083D

2666

-075E

-075

-075D

Supported CL settings

tAAmin (ns):
non-DBI 13.50 15.00 13.75 15.00 13.92 15.00 14.06 15.00 13.32 14.16 15.00 13.50 14.25 15.00

READ CL:
non-DBI 9 10 11 12 13 14 15 16 16 17 18 18 19 20

READ CL: DBI 11 12 13 14 15 16 18 19 19 20 21 21 22 23

-075E

-075

-075D

18-18-18

19-19-19

20-20-20

Symbol Min Max Min Max Min Max Unit

tAA

13.50

19.006

14.25 (13.75)4

19.006

15.00

19.006

ns

tAA

tAA

tAA

tAA

tAA

tAA

tAA_DBI (MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) + ns

3nCK 3nCK 3nCK 3nCK 3nCK 3nCK

tRCD 13.50

14.25

­

(13.75)4

­

15.00

­

ns

tRP

13.50

14.25

­

(13.75)4

­

15.00

­

ns

tRAS

32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns

tRC5

tRAS + tRP

­

tRAS + tRP

­

tRAS + tRP

­

ns

WRITE CWL Symbol Min

Max

Min

Max

Min

Max Unit

9 9, 11 10, 12 11, 14 12, 16
14, 18

tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG)

1.500 1.9006 1.250 <1.500 1.071 <1.250 0.937 <1.071
Reserved 0.833 <0.937
0.750 <0.833 9­20

Reserved 1.500 1.9006 1.250 <1.500
1.071 <1.250
0.937 <1.071 Reserved
0.833 <0.937 Reserved
0.750 <0.833 10-20

Reserved

ns

1.500 1.9006 ns

Reserved

ns

1.250 <1.500 ns

Reserved

ns

1.071 <1.250 ns

Reserved

ns

0.937 <1.071 ns

ns Reserved
ns

0.833 <0.937 ns

ns Reserved
ns

0.750 <0.833 ns

10, 12, 14, 16, 18, nCK 20

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

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356

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 156: DDR4-2666 Speed Bins and Operating Conditions (Continued)

Notes 1­3 apply to the entire table DDR4-2666 Speed Bin CL-nRCD-nRP Parameter Supported CL settings with read DBI

Symbol

-075E 18-18-18 Min Max 11­16, 18­23

Supported CWL settings

9­12, 14, 16, 18

-075 19-19-19 Min Max 12­16, 18­23
9­12, 14, 16, 18

-075D 20-20-20 Min Max Unit 12, 14, 16, 19, 21, nCK
23 9­12, 14, 16, 18 nCK

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

357

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 157: DDR4-2933 Speed Bins and Operating Conditions

358

Notes 1­3 apply to the entire table DDR4-2933 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE-to-internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Max (MT/s)
1333 1600 1866 2133 2400
2666

Equivalent tAAmin(ns): READ CL:
Speed Bin non-DBI non-DBI

­

13.50

9

­

15.00

10

-125E

13.75

11

-125

15.00

12

-107E

13.92

13

-107

15.00

14

-093E

14.06

15

-093

15.00

16

-083E

13.32

16

-083

14.16

17

083D

15.00

18

-075E

13.50

18

-075

14.25

19

-075D

15.00

20

READ CL: DBI 11 12 13 14 15 16 18 19 19 20 21 21 22 23

-068E

-068

-068D

20-20-20

21-21-21

22-22-22

Symbol Min Max Min Max Min Max Unit

tAA

13.64 19.006 14.32 19.006 15.00 19.006 ns

(13.75)4

tAA_DBI tAA

tAA

tAA

tAA

tAA

tAA

ns

(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +

4nCK 4nCK 4nCK 4nCK 4nCK 4nCK

tRCD 13.64

­

14.32

­

15.00

­

ns

(13.75)4

tRP

13.64

­

14.32

­

15.00

­

ns

(13.75)4

tRAS

32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns

tRC5 tRAS +

­

tRAS +

­

tRAS +

­

ns

tRP

tRP

tRP

WRITE CWL Symbol Min

Max

Min

Max

Min

Max Unit

9 tCK (AVG)

Reserved

Reserved

Reserved

ns

tCK (AVG) 1.500 1.9006 1.500 1.9006 1.500 1.9006 ns

9, 11 tCK (AVG) 1.250 <1.500 1.250 <1.500

Reserved

ns

tCK (AVG)

1.250 <1.500 ns

10, 12 tCK (AVG) 1.071 <1.250 1.071 <1.250

Reserved

ns

tCK (AVG)

1.071 <1.250 ns

11, 14 tCK (AVG) 0.937 <1.071 0.937 <1.071

Reserved

ns

tCK (AVG)

0.937 <1.071 ns

12, 16 tCK (AVG)

Reserved

Reserved

Reserved

ns

tCK (AVG) 0.833 <0.937 0.833 <0.937

ns

tCK (AVG)

0.833 <0.937 ns

14, 18 tCK (AVG)

Reserved

Reserved

Reserved

ns

tCK (AVG) 0.750 <0.833 0.750 <0.833

ns

tCK (AVG)

0.750 <0.833 ns

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 157: DDR4-2933 Speed Bins and Operating Conditions (Continued)

Notes 1­3 apply to the entire table DDR4-2933 Speed Bin

CL-nRCD-nRP

Parameter

2933

-068E

13.64

-068

14.32

-068D

15.00

­

16.37

Supported CL settings

Supported CL settings with read DBI

Supported CWL settings

-068E

-068

-068D

20-20-20

21-21-21

22-22-22

Symbol Min Max Min Max Min Max Unit

20

24 16, 20 tCK (AVG) 0.682 <0.750

Reserved

Reserved

ns

21

25

tCK (AVG)

0.682 <0.750

ns

22

26

tCK (AVG)

0.682 <0.750 ns

24

28

tCK (AVG)

Reserved

Reserved

Reserved

ns

10­22

10­22

10, 12, 14, 16, 18, nCK 20, 22

12­16, 18­26

12­16,18­23, 12, 14, 16, 19, 21, nCK

25-26

23, 26

9­12, 14, 16, 18, 9­12, 14, 16, 18, 9­12, 14, 16, 18, nCK

20

20

20

359

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

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4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

360

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 158: DDR4-3200 Speed Bins and Operating Conditions

361

Notes 1­3 apply to the entire table DDR4-3200 Speed Bin CL-nRCD-nRP Parameter Internal READ command to first data
Internal READ command to first data with read DBI enabled

ACTIVATE-to-internal READ or WRITE delay time

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period

Data Rate Equivalent Max (MT/s) Speed Bin

1333 1600 1866 2133 2400
2666

-125E -125 -107E -107 -093E -093 -083E -083 -083D -075E -075 -075D

tAAmin (ns):
non-DBI 13.50 15.00 13.75 15.00 13.92 15.00 14.06 15.00 13.32 14.16 15.00 13.50 14.25 15.00

READ CL:
non-DBI 9 10 11 12 13 14 15 16 16 17 18 18 19 20

READ CL: DBI 11 12 13 14 15 16 18 19 19 20 21 21 22 23

Symbol tAA
tAA_DBI
tRCD tRP tRAS tRC5

-062Y6

-062E

-062

22-22-22

22-22-22

24-24-24

Min Max Min Max Min Max Unit

13.75 19.006 13.75 19.006 15.00 19.006 ns (13.32)4

tAA

tAA

tAA

tAA

tAA

tAA

ns

(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +

4nCK 4nCK 4nCK 4nCK 4nCK 4nCK

13.75

­

13.75

­

15.00

­

ns

(13.32)4

13.75

­

13.75

­

15.00

­

ns

(13.32)4

32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns

tRAS +

­

tRAS +

­

tRAS +

­

ns

tRP

tRP

tRP

WRITE CWL Symbol

Min

Max

Min

Max

Min

Max Unit

9 tCK (AVG) 1.500 1.9006

Reserved

Reserved

ns

tCK (AVG)

1.500 1.9006 1.500 1.9006 ns

9, 11 tCK (AVG) 1.250 <1.500 1.250 <1.500

Reserved

ns

tCK (AVG)

1.250 <1.500 ns

10, 12 tCK (AVG) 1.071 <1.250 1.071 <1.250

Reserved

ns

tCK (AVG)

1.071 <1.250 ns

11, 14 tCK (AVG) 0.937 <1.071 0.937 <1.071

Reserved

ns

tCK (AVG)

0.937 <1.071 ns

12, 16 tCK (AVG) 0.833 <0.937

Reserved

Reserved

ns

tCK (AVG)

0.833 <0.937

ns

tCK (AVG)

0.833 <0.937 ns

14, 18 tCK (AVG) 0.750 <0.833

Reserved

Reserved

ns

tCK (AVG)

0.750 <0.833

ns

tCK (AVG)

0.750 <0.833 ns

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 158: DDR4-3200 Speed Bins and Operating Conditions (Continued)

Notes 1­3 apply to the entire table DDR4-3200 Speed Bin

CL-nRCD-nRP

Parameter

2933

-068E

13.64

-068

14.32

-068D

15.00

­

16.37

3200

-062E

13.75

-062

15.00

Supported CL settings

Supported CL settings with read DBI

Supported CWL settings

-062Y6

-062E

-062

22-22-22

22-22-22

24-24-24

Symbol Min Max Min Max Min Max Unit

20

24 16, 20 tCK (AVG)

Reserved

Reserved

Reserved

ns

21

25

tCK (AVG) 0.682 <0.750 0.682 <0.750

ns

22

26

tCK (AVG)

0.682 <0.750 0.682 <0.750 ns

24

28

tCK (AVG)

0.682 <0.750 ns

22

26 16, 20 tCK (AVG) 0.625 <0.682 0.625 <0.682

Reserved

ns

24

28

tCK (AVG)

0.625 <0.682 ns

9­22, 24

10­22, 24

10, 12, 14, 16, 18, nCK 20, 22, 24

11­16, 18­23, 25-26, 28

12­16, 18­23, 12, 14, 16, 19, 21, nCK

25-26, 28

23, 26, 28

9­12, 14, 16, 18, 9­12, 14, 16, 18, 9­12, 14, 16, 18, nCK

20

20

20

362

4Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables

Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR4 SDRAM Refresh Parameters By Device Density

Notes:

1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.
3. The programmed value of CWL must be less than or equal to the programmed value of CL.
4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate
tRAS or tRP.
6. This value exceeds the JEDEC requirement in order to allow additional flexibility, especially for components. However, JEDEC SPD compliance may force modules to only support the JEDEC defined value, please refer to the SPD documentation.

Refresh Parameters By Device Density

Table 159: Refresh Parameters by Device Density

Parameter REF command to ACT or REF command time Average periodic refresh interval

Symbol tRFC (All bank groups)

tREFI

-40°C  TC  85°C 85°C < TC  95°C 95°C < TC  105°C

2Gb 160
7.8 3.9 1.95

4Gb 260
7.8 3.9 1.95

8Gb 350
7.8 3.9 1.95

16Gb 350

Unit Notes ns

7.8

s

3.9

s

1

1.95

s

1

Note: 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if the devices support these options or requirements.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

363

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Electrical Characteristics and AC Timing Parameters

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400

Parameter

Clock period average (DLL off mode) Clock period average

High pulse width average

Low pulse width average

Clock period jitter Clock absolute period

Total Deterministic DLL locking

Clock absolute high pulse width (includes duty cycle jitter)

Clock absolute low pulse width (includes duty cycle jitter)

Cycle-to-cycle jitter

Total

DLL locking

Symbol
tCK (DLL_OFF) tCK (AVG, DLL_ON) tCH (AVG)
tCL (AVG)
tJITper_tot tJITper_dj tJITper,lck tCK (ABS)
tCH (ABS)
tCL (ABS)
tJITcc _tot tJITcc,lck

DDR4-1600 DDR4-1866

Min Max Min Max

Clock Timing

8

20

8

20

1.25 1.9 1.071 1.9

DDR4-2133 Min Max

8

20

0.937 1.9

DDR4-2400 Min Max

8

20

0.833 1.9

0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52

0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52

­63

63

­54

54

­47

47

­42

42

­31

31

­27

27

­23

23

­21

21

­50

50

­43

43

­38

38

-33

33

MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX + tJITper_tot MAX

0.45

­

0.45

­

0.45

­

0.45

­

0.45

­

0.45

­

0.45

­

0.45

­

­

125

­

107

­

94

­

83

­

100

­

86

­

75

­

67

Unit Notes

ns ns 3 , 13

tCK (AVG)
tCK (AVG)
ps ps ps ps

17 , 18 17

tCK (AVG)
tCK (AVG)
ps
ps

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

364

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

Parameter Cumulative error across 2 cycles
3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles 11 cycles 12 cycles n = 13, 14 . . . 49, 50 cycles

Symbol tERR2per tERR3per tERR4per tERR5per tERR6per tERR7per tERR8per tERR9per tERR10per tERR11per tERR12per tERRnper

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

Min Max Min Max Min Max Min Max

­92

92

­79

79

­69

69

­61

61

­109 109 ­94

94

­82

82

­73

73

­121 121 ­104 104 ­91

91

­81

81

­131 131 ­112 112 ­98

98

­87

87

­139 139 ­119 119 ­104 104 ­92

92

­145 145 ­124 124 ­109 109 ­97

97

­151 151 ­129 129 ­113 113 ­101 101

­156 156 ­134 134 ­117 117 ­104 104

­160 160 ­137 137 ­120 120 ­107 107

­164 164 ­141 141 ­123 123 ­110 110

­168 168 ­144 144 ­126 126 ­112 112

tERRnper MIN = (1 + 0.68ln[n]) × tJITper_tot MIN

tERRnper MAX = (1 + 0.68ln[n]) × tJITper_tot MAX

Unit ps ps ps ps ps ps ps ps ps ps ps ps

Notes

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

365

Micron Technology, Inc. reserves the right to change products or specifications without notice.  2014 Micron Technology, Inc. All rights reserved.

DQ Input Timing

Data setup time to

Base (calibrated

tDS

Refer to DQ Input Receiver Specification section

­

DQS_t, DQS_c

VREF)

(approximately 0.15tCK to 0.28tCK )

Noncalibrated

tPDA_S

minimum of 0.5UI

UI

22

VREF

Data hold time from Base (calibrated

tDH

Refer to DQ Input Receiver Specification section

­

DQS_t, DQS_c

VREF)

(approximately 0.15tCK to 0.28tCK )

Noncalibrated

tPDA_H

minimum of 0.5UI

UI

22

VREF

DQ and DM minimum data pulse width

tDIPW

0.58

­

0.58

­

0.58

­

0.58

­

UI

for each input

DQ Output Timing (DLL enabled)

DQS_t, DQS_c to DQ skew, per group, per access

tDQSQ

­

0.16

­

0.16

­

0.16

­

0.17

UI

DQ output hold time from DQS_t, DQS_c

tQH

0.76

­

0.76

­

0.76

­

0.74

­

UI

Data Valid Window per device: tQH -

tDVWd

0.63

0.63

0.64

0.64

UI

tDQSQ each device's output per UI

Data Valid Window per device, per pin:

tDVWp

0.66

­

0.66

­

0.69

­

0.72

­

UI

tQH - tDQSQ each device's output per UI

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

366

Parameter DQ Low-Z time from CK_t, CK_c DQ High-Z time from CK_t, CK_c
DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 1tCKpreamble DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 2tCKpreamble DQS_t, DQS_c differential input low pulse width DQS_t, DQS_c differential input high pulse width DQS_t, DQS_c falling edge setup to CK_t, CK_c rising edge DQS_t, DQS_c falling edge hold from CK_t, CK_c rising edge DQS_t, DQS_c differential WRITE preamble for 1tCKpreamble DQS_t, DQS_c differential WRITE preamble for 2tCKpreamble DQS_t, DQS_c differential WRITE postamble
DQS_t, DQS_c rising edge output access time from rising CK_t, CK_c DQS_t, DQS_c rising edge output variance window per DRAM DQS_t, DQS_c differential output high time DQS_t, DQS_c differential output low time DQS_t, DQS_c Low-Z time (RL - 1) DQS_t, DQS_c High-Z time (RL + BL/2)

Symbol tLZDQ tHZDQ
tDQSS1ck
tDQSS2ck
tDQSL

DDR4-1600 DDR4-1866

Min Max Min Max

­450 225 ­390 195

­

225

­

195

DQ Strobe Input Timing

­0.27 0.27 ­0.27 0.27

DDR4-2133

Min Max

­360 180

­

180

­0.27 0.27

DDR4-2400

Min Max

­330 175

­

175

­0.27 0.27

Unit ps ps

Notes

CK

­0.50 0.50 ­0.50 0.50 ­0.50 0.50 ­0.50 0.50 CK

0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 CK

tDQSH

0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 CK

tDSS

0.18

­

0.18

­

0.18

­

0.18

­

CK

tDSH

0.18

­

0.18

­

0.18

­

0.18

­

CK

tWPRE1ck

0.9

­

0.9

­

0.9

­

0.9

­

CK

tWPRE2ck

1.8

­

1.8

­

1.8

­

1.8

­

CK

tWPST

0.33

­

0.33

­

0.33

­

0.33

­

CK

DQS Strobe Output Timing (DLL enabled)

tDQSCK

­225 225 ­195 195 ­180 180 ­175 175

ps

tDQSCKi

­

370

­

330

­

310

­

290

ps

tQSH

0.4

­

0.4

­

0.4

­

0.4

­

CK

tQSL

0.4

­

0.4

­

0.4

­

0.4

­

CK

tLZDQS tHZDQS

­450 225 ­390 195 ­360 180 ­330 175

ps

­

225

­

195

­

180

­

175

ps

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

367

Parameter DQS_t, DQS_c differential READ preamble for 1tCKpreamble DQS_t, DQS_c differential READ preamble for 2tCK preamble DQS_t, DQS_c differential READ postamble
DLL locking time CMD, ADDR setup time Base to CK_t, CK_c Base ref- VREFCA erenced to VIH(AC) and VIL(AC) levels CMD, ADDR hold time Base to CK_t, CK_c Base ref- VREFCA erenced to VIH(DC) and VIL(DC) levels CTRL, ADDR pulse width for each input ACTIVATE to internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE or REF command period ACTIVATE-to-ACTIVATE command period to different bank groups for 1/2KB page size ACTIVATE-to-ACTIVATE command period to different bank groups for 1KB page size ACTIVATE-to-ACTIVATE command period to different bank groups for 2KB page size

Symbol tRPRE1ck
tRPRE2ck
tRPST

DDR4-1600

Min Max

0.9

­

DDR4-1866

Min Max

0.9

­

DDR4-2133

Min Max

0.9

­

DDR4-2400

Min Max

0.9

­

Unit Notes

CK

20

1.8

­

1.8

­

1.8

­

1.8

­

CK

20

0.33

­

0.33

­

0.33

­

0.33

­

CK

21

Command and Address Timing

tDLLK

597

­

597

­

768

tIS

115

­

100

­

80

tISVREF

215

­

200

­

180

­

768

­

­

62

­

­

162

­

CK

2, 4

ps

ps

tIH tIHVREF

140

­

125

­

105

­

87

­

ps

215

­

200

­

180

­

162

­

ps

tIPW tRCD

600

­

525

­

460

­

410

­

ps

See Speed Bin Tables for tRCD

ns

tRP tRAS

See Speed Bin Tables for tRP See Speed Bin Tables for tRAS

ns

ns

12

tRC

See Speed Bin Tables for tRC

ns

12

tRRD_S

MIN = greater MIN = greater MIN = greater MIN = greater CK

1

(1/2KB)

of 4CK or 5ns of 4CK or 4.2ns of 4CK or 3.7ns of 4CK or 3.3ns

tRRD_S

MIN = greater MIN = greater MIN = greater MIN = greater CK

1

(1KB)

of 4CK or 5ns of 4CK or 4.2ns of 4CK or 3.7ns of 4CK or 3.3ns

tRRD_S

MIN = greater MIN = greater MIN = greater MIN = greater CK

1

(2KB)

of 4CK or 6ns of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 5.3ns

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

Parameter

Symbol

Min Max Min Max Min Max Min Max

ACTIVATE-to-ACTIVATE command period to same bank groups for 1/2KB page size

tRRD_L (1/2KB)

MIN = greater MIN = greater MIN = greater MIN = greater of 4CK or 6ns of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 4.9ns

ACTIVATE-to-ACTIVATE command period to same bank groups for 1KB page size

tRRD_L (1KB)

MIN = greater MIN = greater MIN = greater MIN = greater of 4CK or 6ns of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 4.9ns

ACTIVATE-to-ACTIVATE command period to same bank groups for 2KB page size

tRRD_L (2KB)

MIN = greater MIN = greater MIN = greater MIN = greater of 4CK or 7.5ns of 4CK or 6.4ns of 4CK or 6.4ns of 4CK or 6.4ns

Four ACTIVATE windows for 1/2KB page size

tFAW (1/2KB)

MIN = greater MIN = greater MIN = greater MIN = greater of 16CK or 20ns of 16CK or 17ns of 16CK or 15ns of 16CK or 13ns

Four ACTIVATE windows for 1KB page size

tFAW (1KB)

MIN = greater MIN = greater MIN = greater MIN = greater of 20CK or 25ns of 20CK or 23ns of 20CK or 21ns of 20CK or 21ns

Four ACTIVATE windows for 2KB page size

tFAW (2KB)

MIN = greater MIN = greater MIN = greater MIN = greater of 28CK or 35ns of 28CK or 30ns of 28CK or 30ns of 28CK or 30ns

WRITE recovery time

tWR

MIN = 15ns

WRITE recovery time when CRC and DM are both enabled

tWR2 tWR_CRC_DM

MIN = tWR + greater of (4CK
or 3.75ns)

MIN = 1CK + tWR MIN = tWR + greater of (5CK or 3.75ns)

Delay from start of internal WRITE transaction to internal READ command ­ Same bank group

tWR_CRC_DM2 tWTR_L tWTR_L2

MIN = 1CK + tWR_CRC_DM MIN = greater of 4CK or 7.5ns
MIN = 1CK + tWTR_L

Delay from start of internal WRITE trans- tWTR_L_CRC_D MIN = tWTR_L +

action to internal READ command ­ Same

M

greater of (4CK

bank group when CRC and DM are both

or 3.75ns)

enabled

tWTR_L_CRC_D

M2

Delay from start of internal WRITE trans-

tWTR_S

action to internal READ command ­ Dif-

ferent bank group

tWTR_S2

MIN = tWTR_L + greater of (5CK or 3.75ns)
MIN = 1CK + tWTR_L_CRC_DM MIN = greater of (2CK or 2.5ns)
MIN = 1CK + tWTR_S

Unit CK CK CK ns ns ns ns CK CK
CK CK CK CK
CK CK CK

Notes 1 1 1
5, 9, 1 5, 10, 1 6, 9, 1
6, 10, 1 5, 9, 1 5, 10, 1 6, 9, 1
6, 10, 1 5, 7, 8,
9, 1 5, 7, 8, 10, 1

368

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

369

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

Parameter

Symbol

Min Max Min Max Min Max Min Max

Delay from start of internal WRITE trans- tWTR_S_CRC_D MIN = tWTR_S +

action to internal READ command ­ Dif-

M

greater of (4CK

ferent bank group when CRC and DM are

or 3.75ns)

both enabled

tWTR_S_CRC_D

M2

READ-to-PRECHARGE time

tRTP

MIN = tWTR_S + greater of (5CK or 3.75ns) MIN = 1CK + tWTR_S_CRC_DM MIN = greater of 4CK or 7.5ns

CAS_n-to-CAS_n command delay to different bank group

tCCD_S

4

­

4

­

4

­

4

­

CAS_n-to-CAS_n command delay to same bank group

tCCD_L

MIN = ­ MIN = ­ MIN = ­ MIN = ­

greater

greater

greater

greater

of 4CK

of 4CK

of 4CK

of 4CK

or

or

or

or 5ns

6.25ns

5.355ns

5.355ns

Auto precharge write recovery + precharge time

tDAL (MIN)

MIN = WR + ROUNDtRP/tCK (AVG); MAX = N/A

MRS Command Timing

MRS command cycle time

tMRD

8

­

8

­

8

­

8

­

MRS command cycle time in PDA mode

tMRD_PDA

MIN = greater of (16nCK, 10ns)

MRS command cycle time in CAL mode

tMRD_CAL

MIN = tMOD + tCAL

MRS command update delay

tMOD

MIN = greater of (24nCK, 15ns)

MRS command update delay in PDA mode

tMOD_PDA

MIN = tMOD

MRS command update delay in CAL mode

tMOD_CAL

MIN = tMOD + tCAL

MRS command to DQS drive in preamble training

tSDO

MIN = tMOD + 9ns

MPR Command Timing

Multipurpose register recovery time

tMPRR

MIN = 1CK

Multipurpose register write recovery time tWR_MPR

MIN = tMOD + AL + PL

CRC Error Reporting Timing

CRC error to ALERT_n latency

tCRC_ALERT

3

13

3

13

3

13

3

13

CRC ALERT_n pulse width

tCRC_ALERT_P 6

10

6

10

6

10

6

10

W

Unit CK

Notes 6, 7, 8,
9, 1

CK 6, 7, 8, 10, 1

CK

1

CK

CK

14

CK

8

CK

CK

1

CK

CK

1

CK

CK

CK
ns CK

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

370

DDR4-1600

DDR4-1866

DDR4-2133

Parameter

Symbol

Min Max Min Max Min Max

CA Parity Timing

Parity latency

PL

4

­

4

­

4

­

Commands uncertain to be executed during this time

tPAR_UNKNOWN

­

PL

­

PL

­

PL

Delay from errant command to ALERT_n tPAR_ALERT_O ­

PL +

­

P L +

­

PL +

assertion

N

6ns

6ns

6ns

Pulse width of ALERT_n signal when as- tPAR_ALERT_P 48

96

56

112

64

128

serted

W

Time from alert asserted until DES com- tPAR_ALERT_RS ­

43

­

50

­

57

mands required in persistent CA parity

P

mode

CAL Timing

CS_n to command address latency

tCAL

3

­

4

­

4

­

CS_n to command address latency in gear-down mode

tCALg

N/A

­

N/A

­

N/A

­

MPSM Timing

Command path disable delay upopn MPSM entry

tMPED

MIN = tMOD (MIN) + tCPDED (MIN)

Valid clock requirement after MPSM entry

tCKMPE

MIN = tMOD (MIN) + tCPDED (MIN)

Valid clock requirement before MPSM exit

tCKMPX

MIN = tCKSRX (MIN)

Exit MPSM to commands not requiring a locked DLL

tXMP

tXS (MIN)

Exit MPSM to commands requiring a locked DLL

tXMPDLL

MIN = tXMP (MIN) + tXSDLL (MIN)

CS setup time to CKE

tMPX_S

MIN = tIS (MIN) + tIH (MIN)

CS_n HIGH hold time to CKE rising edge

tMPX_HH

MIN = tXP

CS_n LOW hold time to CKE rising edge

tMPX_LH

12 tXMP-1 12 tXMP-1 12 tXMP-1

0ns

0ns

0ns

Connectivity Test Timing

TEN pin HIGH to CS_n LOW ­ Enter CT mode

tCT_Enable

200

­

200

­

200

­

DDR4-2400 Min Max

5

­

­

PL

­

PL +

6ns

72

144

­

64

5

­

N/A

­

12 tXMP-1 0ns

200

­

Unit CK CK CK CK CK
CK CK
CK CK CK CK CK ns ns ns
ns

Notes
19 1 1 1 1

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

371

Parameter CS_n LOW and valid input to valid output CK_t, CK_c valid and CKE HIGH after TEN goes HIGH

ZQCL command: Long POWER-UP and

calibration time

RESET operation

Normal operation

ZQCS command: Short calibration time

The VREF increment/decrement step time
Enter VREFDQ training mode to the first write or VREFDQ MRS command delay
Exit VREFDQ training mode to the first WRITE command delay

Exit reset from CKE HIGH to a valid command RESET_L pulse low after power stable RESET_L pulse low at power-up Begin power supply ramp to power supplies stable RESET_n LOW to power supplies stable

REFRESH-to-ACTIVATE

or REFRESH command

4Gb

period (all bank

groups)

8Gb

16Gb

Symbol tCT_Valid tCTCKE_Valid

DDR4-1600

Min Max

­

200

10

­

DDR4-1866

Min Max

­

200

10

­

DDR4-2133

Min Max

­

200

10

­

DDR4-2400

Min Max

­

200

10

­

Calibration and VREFDQ Train Timing

tZQinit

1024

­

1024

­

1024

­

1024

­

tZQoper

512

­

512

­

512

­

512

­

tZQCS

128

­

128

­

128

­

128

­

VREF_time tVREFDQE

MIN = 150ns MIN = 150ns

tVREFDQX

MIN = 150ns

Initialization and Reset Timing

tXPR

MIN = greater of 5CK or tRFC (MIN) + 10ns

tPW_RESET_S 1.0

­

1.0

­

1.0

­

1.0

­

tPW_RESET_L 200

­

200

­

200

­

200

­

tVDDPR

MIN = N/A; MAX = 200

tRPS
tRFC1 tRFC2 tRFC4 tRFC1 tRFC2 tRFC4 tRFC1 tRFC2 tRFC4

Refresh Timing

MIN = 0; MAX = 0
MIN = 260 MIN = 160 MIN = 110 MIN = 350 MIN = 260 MIN = 160 MIN = 350 MIN = 260 MIN = 160

Unit ns ns
CK
CK
CK
ns
ns
CK
s s ms
ns
ns ns ns ns ns ns ns ns ns

Notes
1 1 1
1, 11 1, 11 1, 11 1, 11 1, 11 1, 11 1, 11 1, 11 1, 11

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

372

Parameter Average periodic refresh interval

-40°C  TC  85°C 85°C < TC  95°C 95°C < TC  105°C

Symbol tREFI tREFI tREFI

Exit self refresh to commands not requiring a locked DLL
Exit self refresh to commands not requiring a locked DLL in self refresh abort
Exit self refresh to ZQCL, ZQCS and MRS (CL, CWL, WR, RTP and gear-down)
Exit self refresh to commands requiring a locked DLL
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
Minimum CKE low pulse width for self refresh entry to self refresh exit timing when CA parity is enabled
Valid clocks after self refresh entry (SRE) or power-down entry (PDE)
Valid clock requirement after self refresh entry or power-down when CA parity is enabled
Valid clocks before self refresh exit (SRX) or power-down exit (PDX), or reset exit

tXS tXS_ABORT
tXS_FAST tXSDLL tCKESR
tCKESR_PAR
tCKSRE tCKSRE_PAR
tCKSRX

Exit power-down with DLL on to any valid command Exit power-down with DLL on to any valid command when CA Parity is enabled. CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing

tXP
tXP _PAR
tCKE (MIN) tCPDED tPD

DDR4-1600 Min Max

DDR4-1866

DDR4-2133

Min Max Min Max

MIN = N/A; MAX = 7.8

MIN = N/A; MAX = 3.9

MIN = N/A; MAX = 1.95

DDR4-2400 Min Max

Unit s s s

Notes 11 11 11

Self Refresh Timing

MIN = tRFC + 10ns MIN = tRFC4 + 10ns
MIN = tRFC4 + 10ns
MIN = tDLLK (MIN)

ns

1

ns

1

1 ns

CK

1

MIN = tCKE (MIN) + 1nCK

CK

1

MIN = tCKE (MIN) + 1nCK + PL

CK

1

MIN = greater of (5CK, 10ns) MIN = greater of (5CK, 10ns) + PL

CK

1

CK

1

MIN = greater of (5CK, 10ns)

CK

1

Power-Down Timing MIN = greater of 4CK or 6ns

CK

1

MIN = (greater of 4CK or 6ns) + PL

CK

1

MIN = greater of 3CK or 5ns

CK

1

4

­

4

­

4

­

4

­

CK

MIN = tCKE (MIN); MAX = 9 × tREFI

CK

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

373

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

Parameter

Symbol

Min Max Min Max Min Max Min Max

Begin power-down period prior to CKE registered HIGH

tANPD

WL - 1CK

Power-down entry period: ODT either synchronous or asynchronous

PDE

Greater of tANPD or tRFC - REFRESH command to CKE LOW time

Power-down exit period: ODT either syn-

PDX

chronous or asynchronous

tANPD + tXSDLL

Power-Down Entry Minimum Timing

ACTIVATE command to power-down en-

tACTPDEN

1

­

1

­

2

­

2

­

try

PRECHARGE/PRECHARGE ALL command

tPRPDEN

1

­

1

­

2

­

2

­

to power-down entry

REFRESH command to power-down entry tREFPDEN

1

­

1

­

2

­

2

­

MRS command to power-down entry

tMRSPDEN

MIN = tMOD (MIN)

READ/READ with auto precharge command to power-down entry

tRDPDEN

MIN = RL + 4 + 1

WRITE command to power-down entry (BL8OTF, BL8MRS, BC4OTF)

tWRPDEN

MIN = WL + 4 + tWR/tCK (AVG)

WRITE command to power-down entry (BC4MRS)

tWRPBC4DEN

MIN = WL + 2 + tWR/tCK (AVG)

WRITE with auto precharge command to power-down entry (BL8OTF, BL8MRS,BC4OTF)

tWRAPDEN

MIN = WL + 4 + WR + 1

WRITE with auto precharge command to tWRAPBC4DEN power-down entry (BC4MRS)

MIN = WL + 2 + WR + 1

ODT Timing

Direct ODT turn-on latency

DODTLon

WL - 2 = CWL + AL + PL - 2

Direct ODT turn-off latency

DODTLoff

WL - 2 = CWL + AL + PL - 2

RTT dynamic change skew
Asynchronous RTT(NOM) turn-on delay (DLL off)

tADC tAONAS

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

1

9

1

9

1

9

1

9

Asynchronous RTT(NOM) turn-off delay (DLL off)

tAOFAS

1

9

1

9

1

9

1

9

Unit CK CK CK
CK CK CK CK CK CK CK CK
CK
CK CK CK ns ns

Notes
1 1 1 1 1 1

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Table 160: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued)

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

Parameter ODT HIGH time with WRITE command and BL8
ODT HIGH time without WRITE command or with WRITE command and BC4
First DQS_t, DQS_c rising edge after write leveling mode is programmed DQS_t, DQS_c delay after write leveling mode is programmed Write leveling setup from rising CK_t, CK_c crossing to rising DQS_t, DQS_c crossing Write leveling hold from rising DQS_t, DQS_c crossing to rising CK_t, CK_c crossing Write leveling output delay Write leveling output error
Exit reset from CKE HIGH to a valid MRS gear-down CKE HIGH assert to gear-down enable time) MRS command to sync pulse time Sync pulse to first valid command Gear-down setup time Gear-down hold time

Symbol ODTH8 1tCK ODTH8 2tCK ODTH4 1tCK ODTH4 2tCK
tWLMRD

DDR4-1600 DDR4-1866

Min Max Min Max

6

­

6

­

7

­

7

­

4

­

4

­

5

­

5

­

Write Leveling Timing

40

­

40

­

DDR4-2133

Min Max

6

­

7

­

4

­

5

­

40

­

tWLDQSEN

25

­

25

­

25

­

tWLS

0.13

­

0.13

­

0.13

­

tWLH

0.13

­

0.13

­

0.13

­

tWLO

0

9.5

0

9.5

0

9.5

tWLOE

0

2

0

2

0

2

Gear-Down Timing (Not Supported Below DDR4-2666)

tXPR_GEAR

N/A

N/A

N/A

tXS_GEAR

N/A

N/A

N/A

tSYNC_GEAR tCMD_GEAR tGEAR_setup tGEAR_hold

N/A

N/A

N/A

­

N/A

­

N/A

N/A

N/A

­

N/A

­

N/A

N/A

N/A

­

N/A

­

DDR4-2400

Min Max

6

­

7

­

4

­

5

­

Unit Notes CK
CK

40 25 0.13
0.13
0 0

­

CK

­

CK

­

tCK

(AVG)

­

tCK

(AVG)

9.5

ns

2

ns

N/A

CK

N/A

CK

N/A

CK

N/A

CK

N/A

­

CK

N/A

­

CK

374

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4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters

Notes:

1. Maximum limit not applicable. 2. tCCD_L and tDLLK should be programmed according to the value defined per operating
frequency. Micron tDLLK values support the legacy JEDEC tDLLK specifications. 3. DDR4-1600 AC timing parameters apply if DRAM operates at lower than 1600 MT/s data
rate. 4. Data rate is greater than or equal to 1066 Mb/s. 5. WRITE-to-READ when CRC and DM are both not enabled. 6. WRITE-to-READ delay when CRC and DM are both enabled. 7. The start of internal write transactions is defined as follows:

· For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
· For BC4 (on-the-fly): rising clock edge four clock cycles after WL
· For BC4 (fixed by MRS): rising clock edge two clock cycles after WL 8. For these parameters, the device supports tnPARAM [nCK] = ROUND{tPARAM [ns]/tCK
(AVG) [ns]} according to the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section, in clock cycles, assuming all input clock jitter specifications are satisfied. 9. When operating in 1tCK WRITE preamble mode. 10. When operating in 2tCK WRITE preamble mode.
11. When CA parity mode is selected and the DLLoff mode is used, each REF command requires an additional "PL" added to tRFC refresh time.
12. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability.
13. Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables.
14. JEDEC specifies a minimum of five clocks. 15. The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left
side and tHZ(DQS) MAX on the right side.
16. The reference level of DQ output signal is specified with a midpoint as a widest part of output signal eye, which should be approximately 0.7 × VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ.
17. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should focus on meeting the total limit.
18. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20­60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN.
19. The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the applicable clocks required at targeted speed bin.
20. The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK (MAX) on the right side. See figure in the Clock to Data Strobe Relationship section. Boundary of DQS Low-Z occurs one cycle earlier in 2tCK toggle mode, as illustrated in the READ Preamble section.
21. DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of DQS differential signal cross-point.
22. The tPDA_S/tPDA_H parameters may use the tDS/tDH limits, respectively, if the signal is LOW the entire BL8.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

375

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CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

Electrical Characteristics and AC Timing Parameters: 2666 Through 3200

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

Table 161: Electrical Characteristics and AC Timing Parameters

Parameter

Clock period average (DLL off mode) Clock period average

High pulse width average

Low pulse width average

Clock period jitter Clock absolute period

Total Deterministic DLL locking

Clock absolute high pulse width (includes duty cycle jitter)

Clock absolute low pulse width (includes duty cycle jitter)

Cycle-to-cycle jitter

Total

DLL locking

Symbol
tCK (DLL_OFF) tCK (AVG, DLL_ON) tCH (AVG)
tCL (AVG)
tJITper_tot tJITper_dj tJITper,lck tCK (ABS)
tCH (ABS)
tCL (ABS)
tJITcc _tot tJITcc,lck

DDR4-2666 DDR4-2933

Min Max Min Max

Clock Timing

8

20

8

20

0.75 1.9 0.682 1.9

DDR4-3200 Min Max

8

20

0.625 1.9

Reserved Min Max

0.48 0.52 0.48 0.52 0.48 0.52

0.48 0.52 0.48 0.52 0.48 0.52

­38

38

-34

34

­32

32

­19

19

-17

17

­16

16

­30

30

-27

27

­25

25

MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX + tJITper_tot MAX

0.45

­

0.45

­

0.45

­

0.45

­

0.45

­

0.45

­

­

75

­

68

­

62

­

60

­

55

­

62

Unit Notes

ns

ns

3, 13

tCK (AVG)
tCK (AVG)
ps ps ps ps

17 , 18 17

tCK (AVG)
tCK (AVG)
ps
ps

376

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377

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter Cumulative error across 2 cycles
3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles 11 cycles 12 cycles n = 13, 14 . . . 49, 50 cycles

Symbol tERR2per tERR3per tERR4per tERR5per tERR6per tERR7per tERR8per tERR9per tERR10per tERR11per tERR12per tERRnper

DDR4-2666

DDR4-2933

DDR4-3200

Reserved

Min Max Min Max Min Max Min Max

­55

55

-50

50

­46

46

­66

66

-60

60

­55

55

­73

73

-66

66

­61

61

­78

78

-71

71

­65

65

­83

83

-75

75

­69

69

­87

87

-79

79

­73

73

­91

91

-83

83

­76

76

­94

94

-85

85

­78

78

­96

96

-88

88

­80

80

­99

99

-90

90

­83

83

­101 101 -92

92

­84

84

tERRnper MIN = (1 + 0.68ln[n]) × tJITper_tot MIN

tERRnper MAX = (1 + 0.68ln[n]) × tJITper_tot MAX

Data setup time to

Base (calibrated

DQS_t, DQS_c

VREF)

Non-calibrated

VREF

Data hold time from Base (calibrated

DQS_t, DQS_c

VREF)

Non-calibrated

VREF

DQ and DM minimum data pulse width

for each input

DQS_t, DQS_c to DQ skew, per group, per access
DQ output hold time from DQS_t, DQS_c Data Valid Window per device: tQH tDQSQ each device's output per UI
Data Valid Window per device, per pin: tQH - tDQSQ each device's output per UI

tDS tPDA_S

DQ Input Timing
Refer to DQ Input Receiver Specification section (approximately 0.15tCK to 0.28tCK )
minimum of 0.5ui

tDH tPDA_H

Refer to DQ Input Receiver Specification section (approximately 0.15tCK to 0.28tCK )
minimum of 0.5UI

tDIPW

0.58

­

0.58

­

0.58

­

DQ Output Timing (DLL enabled)

tDQSQ

­

0.18

­

0.19

­

0.20

tQH tDVWd
tDVWp

0.74

­

0.72

­

0.70

­

0.64

­

0.64

­

0.64

­

0.72

­

0.72

­

0.72

­

Unit ps ps ps ps ps ps ps ps ps ps ps ps
­
UI
­
UI
UI
UI
UI UI
UI

Notes
22 22

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter DQ Low-Z time from CK_t, CK_c DQ High-Z time from CK_t, CK_c
DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 1tCKpreamble DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 2tCKpreamble DQS_t, DQS_c differential input low pulse width DQS_t, DQS_c differential input high pulse width DQS_t, DQS_c falling edge setup to CK_t, CK_c rising edge DQS_t, DQS_c falling edge hold from CK_t, CK_c rising edge DQS_t, DQS_c differential WRITE preamble for 1tCKpreamble DQS_t, DQS_c differential WRITE preamble for 2tCKpreamble DQS_t, DQS_c differential WRITE postamble
DQS_t, DQS_c rising edge output access time from rising CK_t, CK_c DQS_t, DQS_c rising edge output variance window per DRAM DQS_t, DQS_c differential output high time DQS_t, DQS_c differential output low time DQS_t, DQS_c Low-Z time (RL - 1) DQS_t, DQS_c High-Z time (RL + BL/2)

Symbol tLZDQ tHZDQ
tDQSS1ck
tDQSS2ck
tDQSL

DDR4-2666 DDR4-2933

Min Max Min Max

­310 170 ­280 165

­

170

­

165

DQ Strobe Input Timing

­0.27 0.27 ­0.27 0.27

DDR4-3200

Min Max

­250 160

­

160

­0.27 0.27

­0.50 0.50 ­0.50 0.50 ­0.50 0.50

0.46 0.54 0.46 0.54 0.46 0.54

tDQSH

0.46 0.54 0.46 0.54 0.46 0.54

tDSS

0.18

­

0.18

­

0.18

­

tDSH

0.18

­

0.18

­

0.18

­

tWPRE1ck

0.9

­

0.9

­

0.9

­

tWPRE2ck

1.8

­

1.8

­

1.8

­

tWPST

0.33

­

0.33

­

0.33

­

DQS Strobe Output Timing (DLL enabled)

tDQSCK

­170 170 ­165 165 ­160 160

tDQSCKi

­

270

­

265

­

260

tQSH

0.40

­

0.40

­

0.40

­

tQSL

0.40

­

0.40

­

0.40

­

tLZDQS tHZDQS

­310 170 ­280 165 ­250 160

­

170

­

165

­

160

Reserved Min Max

Unit ps ps

Notes

CK CK CK CK CK CK CK CK CK

ps ps CK CK ps ps

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter
DQS_t, DQS_c differential READ preamble for 1tCKpreamble
DQS_t, DQS_c differential READ preamble for 2tCKpreamble
DQS_t, DQS_c differential READ postamble

DLL locking time

CMD, ADDR setup time Base

to CK_t, CK_c referenced to VIH(AC) and VIL(AC) levels

VREFCA

CMD, ADDR hold time Base

to CK_t, CK_c referenced to VIH(DC) and VIL(DC) levels

VREFCA

CTRL, ADDR pulse width for each input

ACTIVATE to internal READ or WRITE delay

PRECHARGE command period

ACTIVATE-to-PRECHARGE command period

ACTIVATE-to-ACTIVATE or REF command period

ACTIVATE-to-ACTIVATE command period to different bank groups for 1/2KB page size

ACTIVATE-to-ACTIVATE command period to different bank groups for 1KB page size

ACTIVATE-to-ACTIVATE command period to different bank groups for 2KB page size

Symbol tRPRE1ck
tRPRE2ck
tRPST

DDR4-2666

Min Max

0.9

­

DDR4-2933

Min Max

0.9

­

DDR4-3200

Min Max

0.9

­

Reserved Min Max

1.8

­

1.8

­

1.8

­

0.33

­

0.33

­

0.33

­

Command and Address Timing

tDLLK

854

­

940

­

1024

­

tIS

55

­

48

­

40

­

tISVREF

145

­

138

­

130

­

tIH tIHVREF

80

­

73

­

65

­

145

­

138

­

130

­

tIPW tRCD
tRP tRAS
tRC
tRRD_S (1/2KB)
tRRD_S (1KB)
tRRD_S (2KB)

385

­

365

­

340

­

See Speed Bin Tables for tRCD

See Speed Bin Tables for tRP See Speed Bin Tables for tRAS

See Speed Bin Tables for tRC

MIN = greater MIN = greater MIN = greater of 4CK or 3.0ns of 4CK or 2.7ns of 4CK or 2.5ns

MIN = greater MIN = greater MIN = greater of 4CK or 3.0ns of 4CK or 2.7ns of 4CK or 2.5ns

MIN = greater MIN = greater MIN = greater of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 5.3ns

Unit CK CK CK
CK ps ps
ps ps
ps ns ns ns ns CK
CK
CK

Notes 20 20 21 2, 4
12 12 1 1 1

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

DDR4-2666

DDR4-2933

DDR4-3200

Reserved

Parameter

Symbol

Min Max Min Max Min Max Min Max

ACTIVATE-to-ACTIVATE command period to same bank groups for 1/2KB page size

tRRD_L (1/2KB)

MIN = greater MIN = greater MIN = greater of 4CK or 4.9ns of 4CK or 4.9ns of 4CK or 4.9ns

ACTIVATE-to-ACTIVATE command period to same bank groups for 1KB page size

tRRD_L (1KB)

MIN = greater MIN = greater MIN = greater of 4CK or 4.9ns of 4CK or 4.9ns of 4CK or 4.9ns

ACTIVATE-to-ACTIVATE command period to same bank groups for 2KB page size

tRRD_L (2KB)

MIN = greater MIN = greater MIN = greater of 4CK or 6.4ns of 4CK or 6.4ns of 4CK or 6.4ns

Four ACTIVATE windows for 1/2KB page size

tFAW (1/2KB)

MIN = greater MIN = greater MIN = greater of 16CK or 12ns of 16CK or of 16CK or 10ns
10.875ns

Four ACTIVATE windows for 1KB page size

tFAW (1KB)

MIN = greater MIN = greater MIN = greater of 20CK or 21ns of 20CK or 21ns of 20CK or 21ns

Four ACTIVATE windows for 2KB page size

tFAW (2KB)

MIN = greater MIN = greater MIN = greater of 28CK or 30ns of 28CK or 30ns of 28CK or 30ns

WRITE recovery time

tWR

MIN = 15ns

WRITE recovery time when CRC and DM are both enabled

tWR2 tWR_CRC_DM

MIN = 1CK + tWR MIN = tWR + greater of (5CK or 3.75ns)

WRITE recovery time when CRC and DM tWR_CRC_DM2 are both enabled

MIN = 1CK + tWR_CRC_DM

Delay from start of internal WRITE transaction to internal READ command ­ Same bank group

tWTR_L tWTR_L2

MIN = greater of 4CK or 7.5ns MIN = 1CK + tWTR_L

Delay from start of internal WRITE trans- tWTR_L_CRC_D

action to internal READ command ­ Same

M

bank group when CRC and DM are both tWTR_L_CRC_D

enabled

M2

Delay from start of internal WRITE trans-

tWTR_S

action to internal READ command ­ Dif-

ferent bank group

tWTR_S2

MIN = tWTR_L + greater of (5CK or 3.75ns) MIN = 1CK + tWTR_L_CRC_DM MIN = greater of (2CK or 2.5ns) MIN = 1CK + tWTR_S

Delay from start of internal WRITE trans- tWTR_S_CRC_D

action to internal READ command ­ Dif-

M

ferent bank group when CRC and DM are tWTR_S_CRC_D

both enabled

M2

MIN = tWTR_S + greater of (5CK or 3.75ns) MIN = 1CK + tWTR_S_CRC_DM

Unit Notes

CK

1

CK

1

CK

1

ns

ns
ns
ns 5, 9, 1 CK 5, 10, 1 CK 6, 9, 1
CK 6, 10, 1
CK 5, 9, 1 CK 5, 10, 1
CK 6, 9, 1
CK 6, 10, 1
CK 5, 7, 8, 9, 1
CK 5, 7, 8, 10, 1
CK 6, 7, 8, 9, 1
CK 6, 7, 8, 10, 1

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

DDR4-2666

DDR4-2933

DDR4-3200

Reserved

Parameter

Symbol

Min Max Min Max Min Max Min Max

READ-to-PRECHARGE time

tRTP

MIN = greater of 4CK or 7.5ns

CAS_n-to-CAS_n command delay to different bank group

tCCD_S

4

­

4

­

4

­

CAS_n-to-CAS_n command delay to same bank group

tCCD_L

MIN = ­ MIN = ­ MIN = ­

greater

greater

greater

of 4CK

of 4CK

of 4CK

or 5ns

or 5ns

or 5ns

Auto precharge write recovery + precharge time

tDAL (MIN)

MIN = WR + ROUNDtRP/tCK (AVG); MAX = N/A

MRS Command Timing

MRS command cycle time

tMRD

8

­

8

­

8

­

MRS command cycle time in PDA mode

tMRD_PDA

MIN = greater of (16nCK, 10ns)

MRS command cycle time in CAL mode

tMRD_CAL

MIN = tMOD + tCAL

MRS command update delay

tMOD

MIN = greater of (24nCK, 15ns)

MRS command update delay in PDA mode

tMOD_PDA

MIN = tMOD

MRS command update delay in CAL mode

tMOD_CAL

MIN = tMOD + tCAL

MRS command to DQS drive in preamble training

tSDO

MIN = tMOD + 9ns

MPR Command Timing

Multipurpose register recovery time

tMPRR

MIN = 1nCK

Multipurpose register write recovery time tWR_MPR

MIN = tMOD + AL + PL

CRC Error Reporting Timing

CRC error to ALERT_n latency

tCRC_ALERT

3

13

3

13

3

13

CRC ALERT_n pulse width

tCRC_ALERT_P 6

10

6

10

6

10

W

CA Parity Timing

Parity latency

PL

5

­

6

­

6

­

Commands uncertain to be executed during this time

tPAR_UNKNOWN

­

PL

­

PL

­

PL

Delay from errant command to ALERT_n tPAR_ALERT_O ­

PL +

­

PL +

­

PL +

assertion

N

6ns

6ns

6ns

Unit CK CK CK
CK
CK CK CK CK CK
CK
ns CK
CK CK CK

Notes 1 14
8
1 1

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

DDR4-2666

DDR4-2933

DDR4-3200

Parameter

Symbol

Min Max Min Max Min Max

Pulse width of ALERT_n signal when as- tPAR_ALERT_P 80

160

88

176

96

192

serted

W

Time from alert asserted until DES com- tPAR_ALERT_RS ­

71

­

78

­

85

mands required in persistent CA parity

P

mode

CAL Timing

CS_n to command address latency

tCAL

5

­

6

­

6

­

CS_n to command address latency in gear-down mode

tCALg

6

­

8

­

8

­

MPSM Timing

Command path disable delay upopn MPSM entry

tMPED

MIN = tMOD (MIN) + tCPDED (MIN)

Valid clock requirement after MPSM entry

tCKMPE

MIN = tMOD (MIN) + tCPDED (MIN)

Valid clock requirement before MPSM exit

tCKMPX

MIN = tCKSRX (MIN)

Exit MPSM to commands not requiring a locked DLL

tXMP

tXS (MIN)

Exit MPSM to commands requiring a locked DLL

tXMPDLL

MIN = tXMP (MIN) + tXSDLL (MIN)

CS setup time to CKE

tMPX_S

MIN = tIS (MIN) + tIH (MIN)

CS_n HIGH hold time to CKE rising edge

tMPX_HH

MIN = tXP

CS_n LOW hold time to CKE rising edge

tMPX_LH

12 tXMP-1 12 tXMP-1 12 tXMP-1

0ns

0ns

0ns

Connectivity Test Timing

TEN pin HIGH to CS_n LOW ­ Enter CT mode

tCT_Enable

200

­

200

­

200

­

CS_n LOW and valid input to valid output tCT_Valid

­

200

­

200

­

200

CK_t, CK_c valid and CKE HIGH after TEN tCTCKE_Valid 10

­

10

­

10

­

goes HIGH

Calibration and VREFDQ Train Timing

Reserved Min Max

Unit CK CK
CK CK
CK CK CK CK CK ns ns ns
ns ns ns

Notes
19 1 1 1 1

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter

ZQCL command: Long POWER-UP and

calibration time

RESET operation

Normal operation

ZQCS command: Short calibration time

The VREF increment/decrement step time
Enter VREFDQ training mode to the first write or VREFDQ MRS command delay
Exit VREFDQ training mode to the first WRITE command delay

Exit reset from CKE HIGH to a valid command RESET_L pulse low after power stable RESET_L pulse low at power-up Begin power supply ramp to power supplies stable RESET_n LOW to power supplies stable

REFRESH-to-ACTIVATE

or REFRESH command

4Gb

period (all bank

groups)

8Gb

16Gb

Average periodic refresh interval

-40°C  TC  85°C 85°C < TC  95°C 95°C < TC  105°C

Symbol tZQinit

DDR4-2666

Min Max

1024

­

DDR4-2933

Min Max

1024

­

DDR4-3200

Min Max

1024

­

Reserved Min Max

tZQoper

512

­

512

­

512

­

tZQCS

128

­

128

­

128

­

VREF_time tVREFDQE

MIN = 150ns MIN = 150ns

tVREFDQX

MIN = 150ns

Initialization and Reset Timing

tXPR

MIN = greater of 5CK or tRFC (MIN) + 10ns

tPW_RESET_S 1.0

­

1.0

­

1.0

­

tPW_RESET_L 200

­

200

­

200

­

tVDDPR

MIN = N/A; MAX = 200

tRPS
tRFC1 tRFC2 tRFC4 tRFC1 tRFC2 tRFC4 tRFC1 tRFC2 tRFC4 tREFI tREFI tREFI

MIN = 0; MAX = 0 Refresh Timing
MIN = 260 MIN = 160 MIN = 110 MIN = 350 MIN = 260 MIN = 160 MIN = 350 MIN = 260 MIN = 160 MIN = N/A; MAX = 7.8 MIN = N/A; MAX = 3.9 MIN = N/A; MAX = 1.95

Unit CK
CK
CK
ns
ns
CK
s s ms
ns
ns ns ns ns ns ns ns ns ns s s s

Notes
1 1
1
1, 11 1, 11 1, 11 1, 11 1, 11 1, 11 1, 11 1, 11 1, 11
11 11 11

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter

Symbol

Exit self refresh to commands not requiring a locked DLL
Exit self refresh to commands not requiring a locked DLL in self refresh abort
Exit self refresh to ZQCL, ZQCS and MRS (CL, CWL, WR, RTP and gear-down)
Exit self refresh to commands requiring a locked DLL
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
Minimum CKE low pulse width for self refresh entry to self refresh exit timing when CA parity is enabled
Valid clocks after self refresh entry (SRE) or power-down entry (PDE)
Valid clock requirement after self refresh entry or power-down when CA parity is enabled
Valid clocks before self refresh exit (SRX) or power-down exit (PDX), or reset exit

tXS tXS_ABORT
tXS_FAST tXSDLL tCKESR
tCKESR_par
tCKSRE tCKSRE_par
tCKSRX

Exit power-down with DLL on to any valid command Exit precharge power-down with DLL frozen to commands not requiring a locked DLL when CA Parity is enabled. CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin power-down period prior to CKE registered HIGH

tXP tXP _PAR
tCKE (MIN) tCPDED tPD tANPD

DDR4-2666 DDR4-2933 Min Max Min Max
Self Refresh Timing

DDR4-3200 Min Max

Reserved Min Max

MIN = tRFC + 10ns MIN = tRFC4 + 10ns MIN = tRFC4 + 10ns

MIN = tDLLK (MIN)

MIN = tCKE (MIN) + 1nCK

MIN = tCKE (MIN) + 1nCK + PL

MIN = greater of (5CK, 10ns) MIN = greater of (5CK, 10ns) + PL

MIN = greater of (5CK, 10ns)
Power-Down Timing MIN = greater of 4CK or 6ns
MIN = (greater of 4CK or 6ns) + PL

MIN = greater of 3CK or 5ns

4

­

4

­

4

­

MIN = tCKE (MIN); MAX = 9 × tREFI

WL - 1CK

Unit
ns ns ns CK CK CK
CK CK
CK
CK CK
CK CK CK CK

Notes
1 1 1 1 1 1
1 1
1
1 1
1

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter Power-down entry period: ODT either synchronous or asynchronous Power-down exit period: ODT either synchronous or asynchronous
ACTIVATE command to power-down entry PRECHARGE/PRECHARGE ALL command to power-down entry REFRESH command to power-down entry MRS command to power-down entry READ/READ with auto precharge command to power-down entry WRITE command to power-down entry (BL8OTF, BL8MRS, BC4OTF) WRITE command to power-down entry (BC4MRS) WRITE with auto precharge command to power-down entry (BL8OTF, BL8MRS,BC4OTF) WRITE with auto precharge command to power-down entry (BC4MRS)
Direct ODT turn-on latency Direct ODT turn-off latency RTT dynamic change skew Asynchronous RTT(NOM) turn-on delay (DLL off) Asynchronous RTT(NOM) turn-off delay (DLL off) ODT HIGH time with WRITE command and BL8

Symbol PDE

DDR4-2666

DDR4-2933

DDR4-3200

Reserved

Min Max Min Max Min Max Min Max

Greater of tANPD or tRFC - REFRESH command to CKE LOW time

PDX

tANPD + tXSDLL

Power-Down Entry Minimum Timing

tACTPDEN

2

­

2

­

2

­

tPRPDEN

2

­

2

­

2

­

tREFPDEN

2

­

2

­

2

­

tMRSPDEN

MIN = tMOD (MIN)

tRDPDEN

MIN = RL + 4 + 1

tWRPDEN

MIN = WL + 4 + tWR/tCK (AVG)

tWRPBC4DEN

MIN = WL + 2 + tWR/tCK (AVG)

tWRAPDEN

MIN = WL + 4 + WR + 1

tWRAPBC4DEN

MIN = WL + 2 + WR + 1

DODTLon DODTLoff
tADC tAONAS

ODT Timing

WL - 2 = CWL + AL + PL - 2

WL - 2 = CWL + AL + PL - 2

0.28 0.72 0.26 0.74 0.26 0.74

1

9

1

9

1

9

tAOFAS

1

9

1

9

1

9

ODTH8 1tCK

6

­

6

­

6

­

ODTH8 2tCK

7

­

7

­

7

­

Unit CK CK
CK CK CK CK CK CK CK CK
CK
CK CK CK ns ns CK

Notes
1 1 1 1 1 1

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

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Table 161: Electrical Characteristics and AC Timing Parameters (Continued)

Parameter ODT HIGH time without WRITE command or with WRITE command and BC4

Symbol ODTH4 1tCK ODTH4 2tCK

First DQS_t, DQS_c rising edge after write leveling mode is programmed
DQS_t, DQS_c delay after write leveling mode is programmed
Write leveling setup from rising CK_t, CK_c crossing to rising DQS_t, DQS_c crossing
Write leveling hold from rising DQS_t, DQS_c crossing to rising CK_t, CK_c crossing
Write leveling output delay
Write leveling output error

tWLMRD tWLDQSEN
tWLS
tWLH
tWLO tWLOE

Exit reset from CKE HIGH to a valid MRS gear-down CKE HIGH assert to gear-down enable time) MRS command to sync pulse time Sync pulse to first valid command Gear-down setup time Gear-down hold time

tXPR_GEAR
tXS_GEAR
tSYNC_GEAR tCMD_GEAR tGEAR_setup tGEAR_hold

DDR4-2666 DDR4-2933

Min Max Min Max

4

­

4

­

5

­

5

­

Write Leveling Timing

40

­

40

­

25

­

25

­

0.13

­

0.13

­

0.13

­

0.13

­

0

9.5

0

9.5

0

2

0

2

Gear-Down Timing

tXPR

tXPR

tXS

tXS

tMOD + 4CK

tMOD

2CK

­

2CK

­

tMOD + 4CK

tMOD

2CK

­

2CK

­

DDR4-3200

Min Max

4

­

5

­

40

­

25

­

0.13

­

0.13

­

0

9.5

0

2

tXPR

tXS

tMOD + 4CK

tMOD

2CK

­

2CK

­

Reserved Min Max

Unit Notes CK
CK CK CK
CK
ns ns CK CK CK CK CK CK

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666
Through 3200

Notes:

1. Maximum limit not applicable. 2. tCCD_L and tDLLK should be programmed according to the value defined per operating
frequency. Micron tDLLK values support the legacy JEDEC tDLLK specifications. 3. DDR4-1600 AC timing parameters apply if DRAM operates at lower than 1600 MT/s data
rate. 4. Data rate is greater than or equal to 1066 Mb/s. 5. WRITE-to-READ when CRC and DM are both not enabled. 6. WRITE-to-READ delay when CRC and DM are both enabled. 7. The start of internal write transactions is defined as follows:

· For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
· For BC4 (on-the-fly): rising clock edge four clock cycles after WL
· For BC4 (fixed by MRS): rising clock edge two clock cycles after WL 8. For these parameters, the device supports tnPARAM [nCK] = ROUND{tPARAM [ns]/tCK
(AVG) [ns]} according to the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section, in clock cycles, assuming all input clock jitter specifications are satisfied. 9. When operating in 1tCK WRITE preamble mode. 10. When operating in 2tCK WRITE preamble mode.
11. When CA parity mode is selected and the DLLoff mode is used, each REF command requires an additional "PL" added to tRFC refresh time.
12. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability.
13. Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables.
14. JEDEC specifies a minimum of five clocks. 15. The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left
side and tHZ(DQS) MAX on the right side.
16. The reference level of DQ output signal is specified with a midpoint as a widest part of output signal eye, which should be approximately 0.7 × VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ.
17. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should focus on meeting the total limit.
18. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20­60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN.
19. The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the applicable clocks required at targeted speed bin.
20. The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK (MAX) on the right side. See figure in the Clock to Data Strobe Relationship section. Boundary of DQS Low-Z occurs one cycle earlier in 2tCK toggle mode, as illustrated in the READ Preamble section.
21. DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of DQS differential signal cross-point.
22. The tPDA_S/tPDA_H parameters may use the tDS/tDH limits, respectively, if the signal is LOW the entire BL8.

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

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4Gb: x4, x8, x16 DDR4 SDRAM Converting Time-Based Specifications to Clock-Based Require-
ments
Converting Time-Based Specifications to Clock-Based Requirements
Software algorithms for calculation of timing parameters are subject to potential rounding errors when converting DRAM timing requirements to system clocks; for example, a memory clock with a nominal frequency of 933.33...3MHz which yields a clock period of 1.071428571429...ns. It is unrealistic to represent all digits after the decimal point exactly and some sort of rounding needs to be done.
DDR4 SDRAM SPD-based specifications use a minimum granularity for SPD-associated timing parameters of 1ps. Clock periods such as tCK (AVG) MIN are defined to the nearest picosecond. For example, 1.071428571429...ns is stated as 1071ps. Parameters such as tAA MIN are specified in units of time (nanoseconds) and require mathematical computation to convert to system clocks (nCK). Rules for rounding allow optimization of device performance without violating device parameters. These SPD algorithms rely on results that are within nCK adjustment factors on device testing and specification to avoid losing performance due to rounding errors when using SPD-based parameters. Note that JEDEC also defines an nCK adjustment factor, but mandates the inverse nCK adjustment factor be used in case of conflicting results, so only the inverse nCK adjustment factor is discussed here.
Guidance converting SPD associated timing parameters to system clock requirements:
· Round the application clock period up to the nearest picosecond. · Express the timing specification and application clock period in picoseconds; scaling
a nanosecond-based parameter value by 1000 allows programmers to use integer math instead of real math by expressing timing in ps. · Divide the picosecond-based parameter by the picoseconds based application clock period. · Add an inverse nCK adjustment factor of 97.4%. · Truncate down to the next lower integer value. · nCK = Truncate[(parameter in ps)/(application tCK in ps) + (974/1000)].
Guidance converting nonSPD associated timing parameters to system clock requirements:
· Divide the time base specification (in ns) and divided by the clock period (in ns). · The resultant is set to the next higher integer number of clocks. · nCK = Ceiling[(parameter in ns/application tCK in ns)].

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

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Options Tables
Table 162: Options ­ Speed Based

Function Write leveling Temperature controlled refresh Low-power auto self refresh Fine granularity refresh Multipurpose register Data mask Data bus inversion TDQS ZQ calibration VREFDQ calibration Per-DRAM addressability Mode register readout Command/Address latency Write CRC CA parity Gear-down mode Programmable preamble Maximum power saving mode Additive latency Connectivity test mode Hard post package repair mode Soft post package repair mode

Acronym WL TCR
LPASR FGR MR DM DBI ­
ZQ CAL ­
Per DRAM ­
CAL CRC
­ ­ ­ MPSM AL CT hPPR sPPR

1600 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes

1866 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes

4Gb: x4, x8, x16 DDR4 SDRAM Options Tables

2133 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes

Data Rate 2400 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes

2666 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

2933 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

3200 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

CCMTD-1725822587-9046 4gb_ddr4_dram.pdf - Rev. L 08/19 EN

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4Gb: x4, x8, x16 DDR4 SDRAM Options Tables

Table 163: Options ­ Width Based

Function Write leveling Temperature controlled refresh Low-power auto self refresh Fine granularity refresh Multipurpose register Data mask Data bus inversion TDQS ZQ calibration VREFDQ calibration Per-DRAM addressability Mode regsiter readout Command/Address latency Write CRC CA parity Gear-down mode Programmable preamble Maximum power-down mode Additive latency Connectivity test mode
Hard post package repair mode
Soft post package repair mode

Width

Acronym

x4

x8

x16

WL

Yes

Yes

Yes

TCR

Yes

Yes

Yes

LPASR

Yes

Yes

Yes

FGR

Yes

Yes

Yes

MR

Yes

Yes

Yes

DM

No

Yes

Yes

DBI

No

Yes

Yes

­

No

Yes

No

ZQ CAL

Yes

Yes

Yes

­

Yes

Yes

Yes

Per DRAM

Yes

Yes

Yes

­

Yes

Yes

Yes

CAL

Yes

Yes

Yes

CRC

Yes

Yes

Yes

­

Yes

Yes

Yes

­

Yes

Yes

Yes

­

Yes

Yes

Yes

MPSM

Yes

Yes

Yes

AL

Yes

Yes

Yes

CT

JEDEC optional on 8Gb and larger densities

Yes

Micron supports on all densities

hPPR

JEDEC optional on 4Gb Micron supports on all densities

sPPR

JEDEC optional on 4Gb and 8Gb Micron supports on all densities

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Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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